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drm/i915: fix Haswell FDI link training code
[linux-block.git] / drivers / gpu / drm / i915 / intel_drv.h
CommitLineData
79e53945
JB		 1/*
2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 * IN THE SOFTWARE.
24 */
25#ifndef __INTEL_DRV_H__
26#define __INTEL_DRV_H__
27
28#include <linux/i2c.h>
760285e7 29#include <drm/i915_drm.h>
80824003 30#include "i915_drv.h"
760285e7
DH		 31#include <drm/drm_crtc.h>
32#include <drm/drm_crtc_helper.h>
33#include <drm/drm_fb_helper.h>
612a9aab 34#include <drm/drm_dp_helper.h>
913d8d11 35
481b6af3 36#define _wait_for(COND, MS, W) ({ \
913d8d11
CW		 37 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \
38 int ret__ = 0; \
0206e353 39 while (!(COND)) { \
913d8d11
CW		 40 if (time_after(jiffies, timeout__)) { \
41 ret__ = -ETIMEDOUT; \
42 break; \
43 } \
0cc2764c
BW		 44 if (W && drm_can_sleep()) { \
45 msleep(W); \
46 } else { \
47 cpu_relax(); \
48 } \
913d8d11
CW		 49 } \
50 ret__; \
51})
52
57f350b6 53#define wait_for_atomic_us(COND, US) ({ \
bcf9dcc1
CW		 54 unsigned long timeout__ = jiffies + usecs_to_jiffies(US); \
55 int ret__ = 0; \
56 while (!(COND)) { \
57 if (time_after(jiffies, timeout__)) { \
58 ret__ = -ETIMEDOUT; \
59 break; \
60 } \
61 cpu_relax(); \
62 } \
63 ret__; \
57f350b6
JB		 64})
65
481b6af3
CW		 66#define wait_for(COND, MS) _wait_for(COND, MS, 1)
67#define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
68
021357ac
CW		 69#define KHz(x) (1000*x)
70#define MHz(x) KHz(1000*x)
71
79e53945
JB		 72/*
73 * Display related stuff
74 */
75
76/* store information about an Ixxx DVO */
77/* The i830->i865 use multiple DVOs with multiple i2cs */
78/* the i915, i945 have a single sDVO i2c bus - which is different */
79#define MAX_OUTPUTS 6
80/* maximum connectors per crtcs in the mode set */
81#define INTELFB_CONN_LIMIT 4
82
83#define INTEL_I2C_BUS_DVO 1
84#define INTEL_I2C_BUS_SDVO 2
85
86/* these are outputs from the chip - integrated only
87 external chips are via DVO or SDVO output */
88#define INTEL_OUTPUT_UNUSED 0
89#define INTEL_OUTPUT_ANALOG 1
90#define INTEL_OUTPUT_DVO 2
91#define INTEL_OUTPUT_SDVO 3
92#define INTEL_OUTPUT_LVDS 4
93#define INTEL_OUTPUT_TVOUT 5
7d57382e 94#define INTEL_OUTPUT_HDMI 6
a4fc5ed6 95#define INTEL_OUTPUT_DISPLAYPORT 7
32f9d658 96#define INTEL_OUTPUT_EDP 8
00c09d70 97#define INTEL_OUTPUT_UNKNOWN 9
79e53945
JB		 98
99#define INTEL_DVO_CHIP_NONE 0
100#define INTEL_DVO_CHIP_LVDS 1
101#define INTEL_DVO_CHIP_TMDS 2
102#define INTEL_DVO_CHIP_TVOUT 4
103
6c9547ff
CW		 104/* drm_display_mode->private_flags */
105#define INTEL_MODE_PIXEL_MULTIPLIER_SHIFT (0x0)
106#define INTEL_MODE_PIXEL_MULTIPLIER_MASK (0xf << INTEL_MODE_PIXEL_MULTIPLIER_SHIFT)
3b5c78a3 107#define INTEL_MODE_DP_FORCE_6BPC (0x10)
f9bef081
DV		 108/* This flag must be set by the encoder's mode_fixup if it changes the crtc
109 * timings in the mode to prevent the crtc fixup from overwriting them.
110 * Currently only lvds needs that. */
111#define INTEL_MODE_CRTC_TIMINGS_SET (0x20)
6c9547ff
CW		 112
113static inline void
114intel_mode_set_pixel_multiplier(struct drm_display_mode *mode,
115 int multiplier)
116{
117 mode->clock *= multiplier;
118 mode->private_flags |= multiplier;
119}
120
121static inline int
122intel_mode_get_pixel_multiplier(const struct drm_display_mode *mode)
123{
124 return (mode->private_flags & INTEL_MODE_PIXEL_MULTIPLIER_MASK) >> INTEL_MODE_PIXEL_MULTIPLIER_SHIFT;
125}
126
79e53945
JB		 127struct intel_framebuffer {
128 struct drm_framebuffer base;
05394f39 129 struct drm_i915_gem_object *obj;
79e53945
JB		 130};
131
37811fcc
CW		 132struct intel_fbdev {
133 struct drm_fb_helper helper;
134 struct intel_framebuffer ifb;
135 struct list_head fbdev_list;
136 struct drm_display_mode *our_mode;
137};
79e53945 138
21d40d37 139struct intel_encoder {
4ef69c7a 140 struct drm_encoder base;
9a935856
DV		 141 /*
142 * The new crtc this encoder will be driven from. Only differs from
143 * base->crtc while a modeset is in progress.
144 */
145 struct intel_crtc *new_crtc;
146
79e53945 147 int type;
e2f0ba97 148 bool needs_tv_clock;
66a9278e
DV		 149 /*
150 * Intel hw has only one MUX where encoders could be clone, hence a
151 * simple flag is enough to compute the possible_clones mask.
152 */
153 bool cloneable;
5ab432ef 154 bool connectors_active;
21d40d37 155 void (*hot_plug)(struct intel_encoder *);
bf49ec8c 156 void (*pre_enable)(struct intel_encoder *);
ef9c3aee
DV		 157 void (*enable)(struct intel_encoder *);
158 void (*disable)(struct intel_encoder *);
bf49ec8c 159 void (*post_disable)(struct intel_encoder *);
f0947c37
DV		 160 /* Read out the current hw state of this connector, returning true if
161 * the encoder is active. If the encoder is enabled it also set the pipe
162 * it is connected to in the pipe parameter. */
163 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
f8aed700 164 int crtc_mask;
79e53945
JB		 165};
166
1d508706 167struct intel_panel {
dd06f90e 168 struct drm_display_mode *fixed_mode;
4d891523 169 int fitting_mode;
1d508706
JN		 170};
171
5daa55eb
ZW		 172struct intel_connector {
173 struct drm_connector base;
9a935856
DV		 174 /*
175 * The fixed encoder this connector is connected to.
176 */
df0e9248 177 struct intel_encoder *encoder;
9a935856
DV		 178
179 /*
180 * The new encoder this connector will be driven. Only differs from
181 * encoder while a modeset is in progress.
182 */
183 struct intel_encoder *new_encoder;
184
f0947c37
DV		 185 /* Reads out the current hw, returning true if the connector is enabled
186 * and active (i.e. dpms ON state). */
187 bool (*get_hw_state)(struct intel_connector *);
1d508706
JN		 188
189 /* Panel info for eDP and LVDS */
190 struct intel_panel panel;
9cd300e0
JN		 191
192 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
193 struct edid *edid;
5daa55eb
ZW		 194};
195
79e53945
JB		 196struct intel_crtc {
197 struct drm_crtc base;
80824003
JB		 198 enum pipe pipe;
199 enum plane plane;
a5c961d1 200 enum transcoder cpu_transcoder;
79e53945 201 u8 lut_r[256], lut_g[256], lut_b[256];
08a48469
DV		 202 /*
203 * Whether the crtc and the connected output pipeline is active. Implies
204 * that crtc->enabled is set, i.e. the current mode configuration has
205 * some outputs connected to this crtc.
08a48469
DV		 206 */
207 bool active;
93314b5b 208 bool primary_disabled; /* is the crtc obscured by a plane? */
652c393a 209 bool lowfreq_avail;
02e792fb 210 struct intel_overlay *overlay;
6b95a207 211 struct intel_unpin_work *unpin_work;
77ffb597 212 int fdi_lanes;
cda4b7d3 213
e506a0c6
DV		 214 /* Display surface base address adjustement for pageflips. Note that on
215 * gen4+ this only adjusts up to a tile, offsets within a tile are
216 * handled in the hw itself (with the TILEOFF register). */
217 unsigned long dspaddr_offset;
218
05394f39 219 struct drm_i915_gem_object *cursor_bo;
cda4b7d3
CW		 220 uint32_t cursor_addr;
221 int16_t cursor_x, cursor_y;
222 int16_t cursor_width, cursor_height;
6b383a7f 223 bool cursor_visible;
5a354204 224 unsigned int bpp;
4b645f14 225
ee7b9f93
JB		 226 /* We can share PLLs across outputs if the timings match */
227 struct intel_pch_pll *pch_pll;
6441ab5f 228 uint32_t ddi_pll_sel;
79e53945
JB		 229};
230
b840d907
JB		 231struct intel_plane {
232 struct drm_plane base;
233 enum pipe pipe;
234 struct drm_i915_gem_object *obj;
2d354c34 235 bool can_scale;
b840d907
JB		 236 int max_downscale;
237 u32 lut_r[1024], lut_g[1024], lut_b[1024];
238 void (*update_plane)(struct drm_plane *plane,
239 struct drm_framebuffer *fb,
240 struct drm_i915_gem_object *obj,
241 int crtc_x, int crtc_y,
242 unsigned int crtc_w, unsigned int crtc_h,
243 uint32_t x, uint32_t y,
244 uint32_t src_w, uint32_t src_h);
245 void (*disable_plane)(struct drm_plane *plane);
8ea30864
JB		 246 int (*update_colorkey)(struct drm_plane *plane,
247 struct drm_intel_sprite_colorkey *key);
248 void (*get_colorkey)(struct drm_plane *plane,
249 struct drm_intel_sprite_colorkey *key);
b840d907
JB		 250};
251
b445e3b0
ED		 252struct intel_watermark_params {
253 unsigned long fifo_size;
254 unsigned long max_wm;
255 unsigned long default_wm;
256 unsigned long guard_size;
257 unsigned long cacheline_size;
258};
259
260struct cxsr_latency {
261 int is_desktop;
262 int is_ddr3;
263 unsigned long fsb_freq;
264 unsigned long mem_freq;
265 unsigned long display_sr;
266 unsigned long display_hpll_disable;
267 unsigned long cursor_sr;
268 unsigned long cursor_hpll_disable;
269};
270
79e53945 271#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
5daa55eb 272#define to_intel_connector(x) container_of(x, struct intel_connector, base)
4ef69c7a 273#define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
79e53945 274#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
b840d907 275#define to_intel_plane(x) container_of(x, struct intel_plane, base)
79e53945 276
45187ace
JB		 277#define DIP_HEADER_SIZE 5
278
3c17fe4b
DH		 279#define DIP_TYPE_AVI 0x82
280#define DIP_VERSION_AVI 0x2
281#define DIP_LEN_AVI 13
c846b619
PZ		 282#define DIP_AVI_PR_1 0
283#define DIP_AVI_PR_2 1
3c17fe4b 284
26005210 285#define DIP_TYPE_SPD 0x83
c0864cb3
JB		 286#define DIP_VERSION_SPD 0x1
287#define DIP_LEN_SPD 25
288#define DIP_SPD_UNKNOWN 0
289#define DIP_SPD_DSTB 0x1
290#define DIP_SPD_DVDP 0x2
291#define DIP_SPD_DVHS 0x3
292#define DIP_SPD_HDDVR 0x4
293#define DIP_SPD_DVC 0x5
294#define DIP_SPD_DSC 0x6
295#define DIP_SPD_VCD 0x7
296#define DIP_SPD_GAME 0x8
297#define DIP_SPD_PC 0x9
298#define DIP_SPD_BD 0xa
299#define DIP_SPD_SCD 0xb
300
3c17fe4b
DH		 301struct dip_infoframe {
302 uint8_t type; /* HB0 */
303 uint8_t ver; /* HB1 */
304 uint8_t len; /* HB2 - body len, not including checksum */
305 uint8_t ecc; /* Header ECC */
306 uint8_t checksum; /* PB0 */
307 union {
308 struct {
309 /* PB1 - Y 6:5, A 4:4, B 3:2, S 1:0 */
310 uint8_t Y_A_B_S;
311 /* PB2 - C 7:6, M 5:4, R 3:0 */
312 uint8_t C_M_R;
313 /* PB3 - ITC 7:7, EC 6:4, Q 3:2, SC 1:0 */
314 uint8_t ITC_EC_Q_SC;
315 /* PB4 - VIC 6:0 */
316 uint8_t VIC;
0aa534df
PZ		 317 /* PB5 - YQ 7:6, CN 5:4, PR 3:0 */
318 uint8_t YQ_CN_PR;
3c17fe4b
DH		 319 /* PB6 to PB13 */
320 uint16_t top_bar_end;
321 uint16_t bottom_bar_start;
322 uint16_t left_bar_end;
323 uint16_t right_bar_start;
81014b9d 324 } __attribute__ ((packed)) avi;
c0864cb3
JB		 325 struct {
326 uint8_t vn[8];
327 uint8_t pd[16];
328 uint8_t sdi;
81014b9d 329 } __attribute__ ((packed)) spd;
3c17fe4b
DH		 330 uint8_t payload[27];
331 } __attribute__ ((packed)) body;
332} __attribute__((packed));
333
f5bbfca3 334struct intel_hdmi {
f5bbfca3
ED		 335 u32 sdvox_reg;
336 int ddc_bus;
f5bbfca3
ED		 337 uint32_t color_range;
338 bool has_hdmi_sink;
339 bool has_audio;
340 enum hdmi_force_audio force_audio;
341 void (*write_infoframe)(struct drm_encoder *encoder,
342 struct dip_infoframe *frame);
687f4d06
PZ		 343 void (*set_infoframes)(struct drm_encoder *encoder,
344 struct drm_display_mode *adjusted_mode);
f5bbfca3
ED		 345};
346
b091cd92 347#define DP_MAX_DOWNSTREAM_PORTS 0x10
54d63ca6
SK		 348#define DP_LINK_CONFIGURATION_SIZE 9
349
350struct intel_dp {
54d63ca6
SK		 351 uint32_t output_reg;
352 uint32_t DP;
353 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
354 bool has_audio;
355 enum hdmi_force_audio force_audio;
356 uint32_t color_range;
54d63ca6
SK		 357 uint8_t link_bw;
358 uint8_t lane_count;
359 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
b091cd92 360 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
54d63ca6
SK		 361 struct i2c_adapter adapter;
362 struct i2c_algo_dp_aux_data algo;
363 bool is_pch_edp;
364 uint8_t train_set[4];
365 int panel_power_up_delay;
366 int panel_power_down_delay;
367 int panel_power_cycle_delay;
368 int backlight_on_delay;
369 int backlight_off_delay;
54d63ca6
SK		 370 struct delayed_work panel_vdd_work;
371 bool want_panel_vdd;
dd06f90e 372 struct intel_connector *attached_connector;
54d63ca6
SK		 373};
374
da63a9f2
PZ		 375struct intel_digital_port {
376 struct intel_encoder base;
174edf1f 377 enum port port;
da63a9f2
PZ		 378 struct intel_dp dp;
379 struct intel_hdmi hdmi;
380};
381
f875c15a
CW		 382static inline struct drm_crtc *
383intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
384{
385 struct drm_i915_private *dev_priv = dev->dev_private;
386 return dev_priv->pipe_to_crtc_mapping[pipe];
387}
388
417ae147
CW		 389static inline struct drm_crtc *
390intel_get_crtc_for_plane(struct drm_device *dev, int plane)
391{
392 struct drm_i915_private *dev_priv = dev->dev_private;
393 return dev_priv->plane_to_crtc_mapping[plane];
394}
395
4e5359cd
SF		 396struct intel_unpin_work {
397 struct work_struct work;
398 struct drm_device *dev;
05394f39
CW		 399 struct drm_i915_gem_object *old_fb_obj;
400 struct drm_i915_gem_object *pending_flip_obj;
4e5359cd
SF		 401 struct drm_pending_vblank_event *event;
402 int pending;
403 bool enable_stall_check;
404};
405
1630fe75
CW		 406struct intel_fbc_work {
407 struct delayed_work work;
408 struct drm_crtc *crtc;
409 struct drm_framebuffer *fb;
410 int interval;
411};
412
d2acd215
DV		 413int intel_pch_rawclk(struct drm_device *dev);
414
4eab8136
JN		 415int intel_connector_update_modes(struct drm_connector *connector,
416 struct edid *edid);
335af9a2 417int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
f0217c42 418
3f43c48d 419extern void intel_attach_force_audio_property(struct drm_connector *connector);
e953fd7b
CW		 420extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
421
79e53945 422extern void intel_crt_init(struct drm_device *dev);
08d644ad
DV		 423extern void intel_hdmi_init(struct drm_device *dev,
424 int sdvox_reg, enum port port);
00c09d70
PZ		 425extern void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
426 struct intel_connector *intel_connector);
f5bbfca3 427extern struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
00c09d70
PZ		 428extern bool intel_hdmi_mode_fixup(struct drm_encoder *encoder,
429 const struct drm_display_mode *mode,
430 struct drm_display_mode *adjusted_mode);
f5bbfca3 431extern void intel_dip_infoframe_csum(struct dip_infoframe *avi_if);
eef4eacb
DV		 432extern bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg,
433 bool is_sdvob);
79e53945
JB		 434extern void intel_dvo_init(struct drm_device *dev);
435extern void intel_tv_init(struct drm_device *dev);
f047e395
CW		 436extern void intel_mark_busy(struct drm_device *dev);
437extern void intel_mark_idle(struct drm_device *dev);
438extern void intel_mark_fb_busy(struct drm_i915_gem_object *obj);
439extern void intel_mark_fb_idle(struct drm_i915_gem_object *obj);
c5d1b51d 440extern bool intel_lvds_init(struct drm_device *dev);
ab9d7c30
PZ		 441extern void intel_dp_init(struct drm_device *dev, int output_reg,
442 enum port port);
00c09d70
PZ		 443extern void intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
444 struct intel_connector *intel_connector);
a4fc5ed6
KP		 445void
446intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
447 struct drm_display_mode *adjusted_mode);
247d89f6 448extern void intel_dp_init_link_config(struct intel_dp *intel_dp);
c19b0669
PZ		 449extern void intel_dp_start_link_train(struct intel_dp *intel_dp);
450extern void intel_dp_complete_link_train(struct intel_dp *intel_dp);
451extern void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
00c09d70
PZ		 452extern void intel_dp_encoder_destroy(struct drm_encoder *encoder);
453extern void intel_dp_check_link_status(struct intel_dp *intel_dp);
454extern bool intel_dp_mode_fixup(struct drm_encoder *encoder,
455 const struct drm_display_mode *mode,
456 struct drm_display_mode *adjusted_mode);
cb0953d7 457extern bool intel_dpd_is_edp(struct drm_device *dev);
d6c50ff8
PZ		 458extern void ironlake_edp_backlight_on(struct intel_dp *intel_dp);
459extern void ironlake_edp_backlight_off(struct intel_dp *intel_dp);
82a4d9c0
PZ		 460extern void ironlake_edp_panel_on(struct intel_dp *intel_dp);
461extern void ironlake_edp_panel_off(struct intel_dp *intel_dp);
462extern void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
463extern void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
0206e353 464extern void intel_edp_link_config(struct intel_encoder *, int *, int *);
94bf2ced
DV		 465extern int intel_edp_target_clock(struct intel_encoder *,
466 struct drm_display_mode *mode);
814948ad 467extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder);
b840d907 468extern int intel_plane_init(struct drm_device *dev, enum pipe pipe);
6f1d69b0
ED		 469extern void intel_flush_display_plane(struct drm_i915_private *dev_priv,
470 enum plane plane);
32f9d658 471
a9573556 472/* intel_panel.c */
dd06f90e
JN		 473extern int intel_panel_init(struct intel_panel *panel,
474 struct drm_display_mode *fixed_mode);
1d508706
JN		 475extern void intel_panel_fini(struct intel_panel *panel);
476
1d8e1c75
CW		 477extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
478 struct drm_display_mode *adjusted_mode);
479extern void intel_pch_panel_fitting(struct drm_device *dev,
480 int fitting_mode,
cb1793ce 481 const struct drm_display_mode *mode,
1d8e1c75 482 struct drm_display_mode *adjusted_mode);
a9573556 483extern u32 intel_panel_get_max_backlight(struct drm_device *dev);
a9573556 484extern void intel_panel_set_backlight(struct drm_device *dev, u32 level);
0657b6b1 485extern int intel_panel_setup_backlight(struct drm_connector *connector);
24ded204
DV		 486extern void intel_panel_enable_backlight(struct drm_device *dev,
487 enum pipe pipe);
47356eb6 488extern void intel_panel_disable_backlight(struct drm_device *dev);
aaa6fd2a 489extern void intel_panel_destroy_backlight(struct drm_device *dev);
fe16d949 490extern enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1d8e1c75 491
d9e55608 492struct intel_set_config {
1aa4b628
DV		 493 struct drm_encoder **save_connector_encoders;
494 struct drm_crtc **save_encoder_crtcs;
5e2b584e
DV		 495
496 bool fb_changed;
497 bool mode_changed;
d9e55608
DV		 498};
499
a6778b3c
DV		 500extern bool intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
501 int x, int y, struct drm_framebuffer *old_fb);
a261b246 502extern void intel_modeset_disable(struct drm_device *dev);
79e53945 503extern void intel_crtc_load_lut(struct drm_crtc *crtc);
b2cabb0e 504extern void intel_crtc_update_dpms(struct drm_crtc *crtc);
1f703855 505extern void intel_encoder_noop(struct drm_encoder *encoder);
ea5b213a 506extern void intel_encoder_destroy(struct drm_encoder *encoder);
5ab432ef 507extern void intel_encoder_dpms(struct intel_encoder *encoder, int mode);
6ed0f796 508extern bool intel_encoder_check_is_cloned(struct intel_encoder *encoder);
5ab432ef 509extern void intel_connector_dpms(struct drm_connector *, int mode);
f0947c37 510extern bool intel_connector_get_hw_state(struct intel_connector *connector);
b980514c
DV		 511extern void intel_modeset_check_state(struct drm_device *dev);
512
79e53945 513
df0e9248
CW		 514static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector)
515{
516 return to_intel_connector(connector)->encoder;
517}
518
7739c33b
PZ		 519static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
520{
da63a9f2
PZ		 521 struct intel_digital_port *intel_dig_port =
522 container_of(encoder, struct intel_digital_port, base.base);
523 return &intel_dig_port->dp;
524}
525
526static inline struct intel_digital_port *
527enc_to_dig_port(struct drm_encoder *encoder)
528{
529 return container_of(encoder, struct intel_digital_port, base.base);
530}
531
532static inline struct intel_digital_port *
533dp_to_dig_port(struct intel_dp *intel_dp)
534{
535 return container_of(intel_dp, struct intel_digital_port, dp);
536}
537
538static inline struct intel_digital_port *
539hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
540{
541 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
7739c33b
PZ		 542}
543
df0e9248
CW		 544extern void intel_connector_attach_encoder(struct intel_connector *connector,
545 struct intel_encoder *encoder);
546extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
79e53945
JB		 547
548extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
549 struct drm_crtc *crtc);
08d7b3d1
CW		 550int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
551 struct drm_file *file_priv);
a5c961d1
PZ		 552extern enum transcoder
553intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
554 enum pipe pipe);
9d0498a2 555extern void intel_wait_for_vblank(struct drm_device *dev, int pipe);
58e10eb9 556extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
8261b191
CW		 557
558struct intel_load_detect_pipe {
d2dff872 559 struct drm_framebuffer *release_fb;
8261b191
CW		 560 bool load_detect_temp;
561 int dpms_mode;
562};
d2434ab7 563extern bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 564 struct drm_display_mode *mode,
8261b191 565 struct intel_load_detect_pipe *old);
d2434ab7 566extern void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 567 struct intel_load_detect_pipe *old);
79e53945 568
79e53945
JB		 569extern void intelfb_restore(void);
570extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
571 u16 blue, int regno);
b8c00ac5
DA		 572extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
573 u16 *blue, int regno);
0cdab21f 574extern void intel_enable_clock_gating(struct drm_device *dev);
79e53945 575
127bd2ac 576extern int intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 577 struct drm_i915_gem_object *obj,
919926ae 578 struct intel_ring_buffer *pipelined);
1690e1eb 579extern void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
127bd2ac 580
38651674
DA		 581extern int intel_framebuffer_init(struct drm_device *dev,
582 struct intel_framebuffer *ifb,
308e5bcb 583 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 584 struct drm_i915_gem_object *obj);
38651674
DA		 585extern int intel_fbdev_init(struct drm_device *dev);
586extern void intel_fbdev_fini(struct drm_device *dev);
3fa016a0 587extern void intel_fbdev_set_suspend(struct drm_device *dev, int state);
6b95a207
KH		 588extern void intel_prepare_page_flip(struct drm_device *dev, int plane);
589extern void intel_finish_page_flip(struct drm_device *dev, int pipe);
1afe3e9d 590extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
6b95a207 591
02e792fb
DV		 592extern void intel_setup_overlay(struct drm_device *dev);
593extern void intel_cleanup_overlay(struct drm_device *dev);
ce453d81 594extern int intel_overlay_switch_off(struct intel_overlay *overlay);
02e792fb
DV		 595extern int intel_overlay_put_image(struct drm_device *dev, void *data,
596 struct drm_file *file_priv);
597extern int intel_overlay_attrs(struct drm_device *dev, void *data,
598 struct drm_file *file_priv);
4abe3520 599
eb1f8e4f 600extern void intel_fb_output_poll_changed(struct drm_device *dev);
e8e7a2b8 601extern void intel_fb_restore_mode(struct drm_device *dev);
645c62a5 602
b840d907
JB		 603extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
604 bool state);
605#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
606#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
607
645c62a5 608extern void intel_init_clock_gating(struct drm_device *dev);
e0dac65e
WF		 609extern void intel_write_eld(struct drm_encoder *encoder,
610 struct drm_display_mode *mode);
d4270e57 611extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe);
45244b87 612extern void intel_prepare_ddi(struct drm_device *dev);
c82e4d26 613extern void hsw_fdi_link_train(struct drm_crtc *crtc);
0e72a5b5 614extern void intel_ddi_init(struct drm_device *dev, enum port port);
d4270e57 615
b840d907 616/* For use by IVB LP watermark workaround in intel_sprite.c */
f681fa23 617extern void intel_update_watermarks(struct drm_device *dev);
b840d907
JB		 618extern void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
619 uint32_t sprite_width,
620 int pixel_size);
1f8eeabf
ED		 621extern void intel_update_linetime_watermarks(struct drm_device *dev, int pipe,
622 struct drm_display_mode *mode);
8ea30864 623
5a35e99e
DL		 624extern unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
625 unsigned int bpp,
626 unsigned int pitch);
627
8ea30864
JB		 628extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
629 struct drm_file *file_priv);
630extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
631 struct drm_file *file_priv);
632
57f350b6
JB		 633extern u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg);
634
85208be0 635/* Power-related functions, located in intel_pm.c */
1fa61106 636extern void intel_init_pm(struct drm_device *dev);
85208be0 637/* FBC */
85208be0
ED		 638extern bool intel_fbc_enabled(struct drm_device *dev);
639extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
640extern void intel_update_fbc(struct drm_device *dev);
eb48eb00
DV		 641/* IPS */
642extern void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
643extern void intel_gpu_ips_teardown(void);
85208be0 644
0232e927 645extern void intel_init_power_wells(struct drm_device *dev);
8090c6b9
DV		 646extern void intel_enable_gt_powersave(struct drm_device *dev);
647extern void intel_disable_gt_powersave(struct drm_device *dev);
6590190d 648extern void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv);
930ebb46 649extern void ironlake_teardown_rc6(struct drm_device *dev);
b3daeaef 650
85234cdc
DV		 651extern bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
652 enum pipe *pipe);
b8fc2f6a 653extern int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
79f689aa 654extern void intel_ddi_pll_init(struct drm_device *dev);
8d9ddbcb 655extern void intel_ddi_enable_pipe_func(struct drm_crtc *crtc);
ad80a810
PZ		 656extern void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
657 enum transcoder cpu_transcoder);
fc914639
PZ		 658extern void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
659extern void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
6441ab5f
PZ		 660extern void intel_ddi_setup_hw_pll_state(struct drm_device *dev);
661extern bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock);
6441ab5f 662extern void intel_ddi_put_crtc_pll(struct drm_crtc *crtc);
dae84799 663extern void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
c19b0669 664extern void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
bcbc889b 665bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
72662e10 666
79e53945 667#endif /* __INTEL_DRV_H__ */
Linux 6.x block layer and io_uring tree(s)