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b7fa22d8 ACO |
1 | /* |
2 | * Copyright © 2014-2016 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | */ | |
23 | ||
24 | #include "intel_drv.h" | |
25 | ||
f38861b8 ACO |
26 | /** |
27 | * DOC: DPIO | |
28 | * | |
29 | * VLV, CHV and BXT have slightly peculiar display PHYs for driving DP/HDMI | |
30 | * ports. DPIO is the name given to such a display PHY. These PHYs | |
31 | * don't follow the standard programming model using direct MMIO | |
32 | * registers, and instead their registers must be accessed trough IOSF | |
33 | * sideband. VLV has one such PHY for driving ports B and C, and CHV | |
34 | * adds another PHY for driving port D. Each PHY responds to specific | |
35 | * IOSF-SB port. | |
36 | * | |
37 | * Each display PHY is made up of one or two channels. Each channel | |
38 | * houses a common lane part which contains the PLL and other common | |
39 | * logic. CH0 common lane also contains the IOSF-SB logic for the | |
40 | * Common Register Interface (CRI) ie. the DPIO registers. CRI clock | |
41 | * must be running when any DPIO registers are accessed. | |
42 | * | |
43 | * In addition to having their own registers, the PHYs are also | |
44 | * controlled through some dedicated signals from the display | |
45 | * controller. These include PLL reference clock enable, PLL enable, | |
46 | * and CRI clock selection, for example. | |
47 | * | |
48 | * Eeach channel also has two splines (also called data lanes), and | |
49 | * each spline is made up of one Physical Access Coding Sub-Layer | |
50 | * (PCS) block and two TX lanes. So each channel has two PCS blocks | |
51 | * and four TX lanes. The TX lanes are used as DP lanes or TMDS | |
52 | * data/clock pairs depending on the output type. | |
53 | * | |
54 | * Additionally the PHY also contains an AUX lane with AUX blocks | |
55 | * for each channel. This is used for DP AUX communication, but | |
56 | * this fact isn't really relevant for the driver since AUX is | |
57 | * controlled from the display controller side. No DPIO registers | |
58 | * need to be accessed during AUX communication, | |
59 | * | |
60 | * Generally on VLV/CHV the common lane corresponds to the pipe and | |
61 | * the spline (PCS/TX) corresponds to the port. | |
62 | * | |
63 | * For dual channel PHY (VLV/CHV): | |
64 | * | |
65 | * pipe A == CMN/PLL/REF CH0 | |
66 | * | |
67 | * pipe B == CMN/PLL/REF CH1 | |
68 | * | |
69 | * port B == PCS/TX CH0 | |
70 | * | |
71 | * port C == PCS/TX CH1 | |
72 | * | |
73 | * This is especially important when we cross the streams | |
74 | * ie. drive port B with pipe B, or port C with pipe A. | |
75 | * | |
76 | * For single channel PHY (CHV): | |
77 | * | |
78 | * pipe C == CMN/PLL/REF CH0 | |
79 | * | |
80 | * port D == PCS/TX CH0 | |
81 | * | |
82 | * On BXT the entire PHY channel corresponds to the port. That means | |
83 | * the PLL is also now associated with the port rather than the pipe, | |
84 | * and so the clock needs to be routed to the appropriate transcoder. | |
85 | * Port A PLL is directly connected to transcoder EDP and port B/C | |
86 | * PLLs can be routed to any transcoder A/B/C. | |
87 | * | |
88 | * Note: DDI0 is digital port B, DD1 is digital port C, and DDI2 is | |
89 | * digital port D (CHV) or port A (BXT). :: | |
90 | * | |
91 | * | |
92 | * Dual channel PHY (VLV/CHV/BXT) | |
93 | * --------------------------------- | |
94 | * | CH0 | CH1 | | |
95 | * | CMN/PLL/REF | CMN/PLL/REF | | |
96 | * |---------------|---------------| Display PHY | |
97 | * | PCS01 | PCS23 | PCS01 | PCS23 | | |
98 | * |-------|-------|-------|-------| | |
99 | * |TX0|TX1|TX2|TX3|TX0|TX1|TX2|TX3| | |
100 | * --------------------------------- | |
101 | * | DDI0 | DDI1 | DP/HDMI ports | |
102 | * --------------------------------- | |
103 | * | |
104 | * Single channel PHY (CHV/BXT) | |
105 | * ----------------- | |
106 | * | CH0 | | |
107 | * | CMN/PLL/REF | | |
108 | * |---------------| Display PHY | |
109 | * | PCS01 | PCS23 | | |
110 | * |-------|-------| | |
111 | * |TX0|TX1|TX2|TX3| | |
112 | * ----------------- | |
113 | * | DDI2 | DP/HDMI port | |
114 | * ----------------- | |
115 | */ | |
116 | ||
47a6bc61 ACO |
117 | bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv, |
118 | enum dpio_phy phy) | |
119 | { | |
120 | enum port port; | |
121 | ||
122 | if (!(I915_READ(BXT_P_CR_GT_DISP_PWRON) & GT_DISPLAY_POWER_ON(phy))) | |
123 | return false; | |
124 | ||
125 | if ((I915_READ(BXT_PORT_CL1CM_DW0(phy)) & | |
126 | (PHY_POWER_GOOD | PHY_RESERVED)) != PHY_POWER_GOOD) { | |
127 | DRM_DEBUG_DRIVER("DDI PHY %d powered, but power hasn't settled\n", | |
128 | phy); | |
129 | ||
130 | return false; | |
131 | } | |
132 | ||
133 | if (phy == DPIO_PHY1 && | |
134 | !(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE)) { | |
135 | DRM_DEBUG_DRIVER("DDI PHY 1 powered, but GRC isn't done\n"); | |
136 | ||
137 | return false; | |
138 | } | |
139 | ||
140 | if (!(I915_READ(BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) { | |
141 | DRM_DEBUG_DRIVER("DDI PHY %d powered, but still in reset\n", | |
142 | phy); | |
143 | ||
144 | return false; | |
145 | } | |
146 | ||
147 | for_each_port_masked(port, | |
148 | phy == DPIO_PHY0 ? BIT(PORT_B) | BIT(PORT_C) : | |
149 | BIT(PORT_A)) { | |
150 | u32 tmp = I915_READ(BXT_PHY_CTL(port)); | |
151 | ||
152 | if (tmp & BXT_PHY_CMNLANE_POWERDOWN_ACK) { | |
153 | DRM_DEBUG_DRIVER("DDI PHY %d powered, but common lane " | |
154 | "for port %c powered down " | |
155 | "(PHY_CTL %08x)\n", | |
156 | phy, port_name(port), tmp); | |
157 | ||
158 | return false; | |
159 | } | |
160 | } | |
161 | ||
162 | return true; | |
163 | } | |
164 | ||
165 | static u32 bxt_get_grc(struct drm_i915_private *dev_priv, enum dpio_phy phy) | |
166 | { | |
167 | u32 val = I915_READ(BXT_PORT_REF_DW6(phy)); | |
168 | ||
169 | return (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT; | |
170 | } | |
171 | ||
172 | static void bxt_phy_wait_grc_done(struct drm_i915_private *dev_priv, | |
173 | enum dpio_phy phy) | |
174 | { | |
175 | if (intel_wait_for_register(dev_priv, | |
176 | BXT_PORT_REF_DW3(phy), | |
177 | GRC_DONE, GRC_DONE, | |
178 | 10)) | |
179 | DRM_ERROR("timeout waiting for PHY%d GRC\n", phy); | |
180 | } | |
181 | ||
182 | void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy) | |
183 | { | |
184 | u32 val; | |
185 | ||
186 | if (bxt_ddi_phy_is_enabled(dev_priv, phy)) { | |
187 | /* Still read out the GRC value for state verification */ | |
188 | if (phy == DPIO_PHY0) | |
189 | dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, phy); | |
190 | ||
191 | if (bxt_ddi_phy_verify_state(dev_priv, phy)) { | |
192 | DRM_DEBUG_DRIVER("DDI PHY %d already enabled, " | |
193 | "won't reprogram it\n", phy); | |
194 | ||
195 | return; | |
196 | } | |
197 | ||
198 | DRM_DEBUG_DRIVER("DDI PHY %d enabled with invalid state, " | |
199 | "force reprogramming it\n", phy); | |
200 | } | |
201 | ||
202 | val = I915_READ(BXT_P_CR_GT_DISP_PWRON); | |
203 | val |= GT_DISPLAY_POWER_ON(phy); | |
204 | I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val); | |
205 | ||
206 | /* | |
207 | * The PHY registers start out inaccessible and respond to reads with | |
208 | * all 1s. Eventually they become accessible as they power up, then | |
209 | * the reserved bit will give the default 0. Poll on the reserved bit | |
210 | * becoming 0 to find when the PHY is accessible. | |
211 | * HW team confirmed that the time to reach phypowergood status is | |
212 | * anywhere between 50 us and 100us. | |
213 | */ | |
214 | if (wait_for_us(((I915_READ(BXT_PORT_CL1CM_DW0(phy)) & | |
215 | (PHY_RESERVED | PHY_POWER_GOOD)) == PHY_POWER_GOOD), 100)) { | |
216 | DRM_ERROR("timeout during PHY%d power on\n", phy); | |
217 | } | |
218 | ||
219 | /* Program PLL Rcomp code offset */ | |
220 | val = I915_READ(BXT_PORT_CL1CM_DW9(phy)); | |
221 | val &= ~IREF0RC_OFFSET_MASK; | |
222 | val |= 0xE4 << IREF0RC_OFFSET_SHIFT; | |
223 | I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val); | |
224 | ||
225 | val = I915_READ(BXT_PORT_CL1CM_DW10(phy)); | |
226 | val &= ~IREF1RC_OFFSET_MASK; | |
227 | val |= 0xE4 << IREF1RC_OFFSET_SHIFT; | |
228 | I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val); | |
229 | ||
230 | /* Program power gating */ | |
231 | val = I915_READ(BXT_PORT_CL1CM_DW28(phy)); | |
232 | val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | | |
233 | SUS_CLK_CONFIG; | |
234 | I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val); | |
235 | ||
236 | if (phy == DPIO_PHY0) { | |
237 | val = I915_READ(BXT_PORT_CL2CM_DW6_BC); | |
238 | val |= DW6_OLDO_DYN_PWR_DOWN_EN; | |
239 | I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val); | |
240 | } | |
241 | ||
242 | val = I915_READ(BXT_PORT_CL1CM_DW30(phy)); | |
243 | val &= ~OCL2_LDOFUSE_PWR_DIS; | |
244 | /* | |
245 | * On PHY1 disable power on the second channel, since no port is | |
246 | * connected there. On PHY0 both channels have a port, so leave it | |
247 | * enabled. | |
248 | * TODO: port C is only connected on BXT-P, so on BXT0/1 we should | |
249 | * power down the second channel on PHY0 as well. | |
250 | * | |
251 | * FIXME: Clarify programming of the following, the register is | |
252 | * read-only with bit 6 fixed at 0 at least in stepping A. | |
253 | */ | |
254 | if (phy == DPIO_PHY1) | |
255 | val |= OCL2_LDOFUSE_PWR_DIS; | |
256 | I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val); | |
257 | ||
258 | if (phy == DPIO_PHY0) { | |
259 | uint32_t grc_code; | |
260 | /* | |
261 | * PHY0 isn't connected to an RCOMP resistor so copy over | |
262 | * the corresponding calibrated value from PHY1, and disable | |
263 | * the automatic calibration on PHY0. | |
264 | */ | |
265 | val = dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, DPIO_PHY1); | |
266 | grc_code = val << GRC_CODE_FAST_SHIFT | | |
267 | val << GRC_CODE_SLOW_SHIFT | | |
268 | val; | |
269 | I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code); | |
270 | ||
271 | val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0)); | |
272 | val |= GRC_DIS | GRC_RDY_OVRD; | |
273 | I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val); | |
274 | } | |
275 | ||
276 | val = I915_READ(BXT_PHY_CTL_FAMILY(phy)); | |
277 | val |= COMMON_RESET_DIS; | |
278 | I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val); | |
279 | ||
280 | if (phy == DPIO_PHY1) | |
281 | bxt_phy_wait_grc_done(dev_priv, DPIO_PHY1); | |
282 | } | |
283 | ||
284 | void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy) | |
285 | { | |
286 | uint32_t val; | |
287 | ||
288 | val = I915_READ(BXT_PHY_CTL_FAMILY(phy)); | |
289 | val &= ~COMMON_RESET_DIS; | |
290 | I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val); | |
291 | ||
292 | val = I915_READ(BXT_P_CR_GT_DISP_PWRON); | |
293 | val &= ~GT_DISPLAY_POWER_ON(phy); | |
294 | I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val); | |
295 | } | |
296 | ||
297 | static bool __printf(6, 7) | |
298 | __phy_reg_verify_state(struct drm_i915_private *dev_priv, enum dpio_phy phy, | |
299 | i915_reg_t reg, u32 mask, u32 expected, | |
300 | const char *reg_fmt, ...) | |
301 | { | |
302 | struct va_format vaf; | |
303 | va_list args; | |
304 | u32 val; | |
305 | ||
306 | val = I915_READ(reg); | |
307 | if ((val & mask) == expected) | |
308 | return true; | |
309 | ||
310 | va_start(args, reg_fmt); | |
311 | vaf.fmt = reg_fmt; | |
312 | vaf.va = &args; | |
313 | ||
314 | DRM_DEBUG_DRIVER("DDI PHY %d reg %pV [%08x] state mismatch: " | |
315 | "current %08x, expected %08x (mask %08x)\n", | |
316 | phy, &vaf, reg.reg, val, (val & ~mask) | expected, | |
317 | mask); | |
318 | ||
319 | va_end(args); | |
320 | ||
321 | return false; | |
322 | } | |
323 | ||
324 | bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv, | |
325 | enum dpio_phy phy) | |
326 | { | |
327 | uint32_t mask; | |
328 | bool ok; | |
329 | ||
330 | #define _CHK(reg, mask, exp, fmt, ...) \ | |
331 | __phy_reg_verify_state(dev_priv, phy, reg, mask, exp, fmt, \ | |
332 | ## __VA_ARGS__) | |
333 | ||
334 | if (!bxt_ddi_phy_is_enabled(dev_priv, phy)) | |
335 | return false; | |
336 | ||
337 | ok = true; | |
338 | ||
339 | /* PLL Rcomp code offset */ | |
340 | ok &= _CHK(BXT_PORT_CL1CM_DW9(phy), | |
341 | IREF0RC_OFFSET_MASK, 0xe4 << IREF0RC_OFFSET_SHIFT, | |
342 | "BXT_PORT_CL1CM_DW9(%d)", phy); | |
343 | ok &= _CHK(BXT_PORT_CL1CM_DW10(phy), | |
344 | IREF1RC_OFFSET_MASK, 0xe4 << IREF1RC_OFFSET_SHIFT, | |
345 | "BXT_PORT_CL1CM_DW10(%d)", phy); | |
346 | ||
347 | /* Power gating */ | |
348 | mask = OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | SUS_CLK_CONFIG; | |
349 | ok &= _CHK(BXT_PORT_CL1CM_DW28(phy), mask, mask, | |
350 | "BXT_PORT_CL1CM_DW28(%d)", phy); | |
351 | ||
352 | if (phy == DPIO_PHY0) | |
353 | ok &= _CHK(BXT_PORT_CL2CM_DW6_BC, | |
354 | DW6_OLDO_DYN_PWR_DOWN_EN, DW6_OLDO_DYN_PWR_DOWN_EN, | |
355 | "BXT_PORT_CL2CM_DW6_BC"); | |
356 | ||
357 | /* | |
358 | * TODO: Verify BXT_PORT_CL1CM_DW30 bit OCL2_LDOFUSE_PWR_DIS, | |
359 | * at least on stepping A this bit is read-only and fixed at 0. | |
360 | */ | |
361 | ||
362 | if (phy == DPIO_PHY0) { | |
363 | u32 grc_code = dev_priv->bxt_phy_grc; | |
364 | ||
365 | grc_code = grc_code << GRC_CODE_FAST_SHIFT | | |
366 | grc_code << GRC_CODE_SLOW_SHIFT | | |
367 | grc_code; | |
368 | mask = GRC_CODE_FAST_MASK | GRC_CODE_SLOW_MASK | | |
369 | GRC_CODE_NOM_MASK; | |
370 | ok &= _CHK(BXT_PORT_REF_DW6(DPIO_PHY0), mask, grc_code, | |
371 | "BXT_PORT_REF_DW6(%d)", DPIO_PHY0); | |
372 | ||
373 | mask = GRC_DIS | GRC_RDY_OVRD; | |
374 | ok &= _CHK(BXT_PORT_REF_DW8(DPIO_PHY0), mask, mask, | |
375 | "BXT_PORT_REF_DW8(%d)", DPIO_PHY0); | |
376 | } | |
377 | ||
378 | return ok; | |
379 | #undef _CHK | |
380 | } | |
381 | ||
382 | uint8_t | |
383 | bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder *encoder, | |
384 | uint8_t lane_count) | |
385 | { | |
386 | switch (lane_count) { | |
387 | case 1: | |
388 | return 0; | |
389 | case 2: | |
390 | return BIT(2) | BIT(0); | |
391 | case 4: | |
392 | return BIT(3) | BIT(2) | BIT(0); | |
393 | default: | |
394 | MISSING_CASE(lane_count); | |
395 | ||
396 | return 0; | |
397 | } | |
398 | } | |
399 | ||
400 | void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder, | |
401 | uint8_t lane_lat_optim_mask) | |
402 | { | |
403 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
404 | struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev); | |
405 | enum port port = dport->port; | |
406 | int lane; | |
407 | ||
408 | for (lane = 0; lane < 4; lane++) { | |
409 | u32 val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane)); | |
410 | ||
411 | /* | |
412 | * Note that on CHV this flag is called UPAR, but has | |
413 | * the same function. | |
414 | */ | |
415 | val &= ~LATENCY_OPTIM; | |
416 | if (lane_lat_optim_mask & BIT(lane)) | |
417 | val |= LATENCY_OPTIM; | |
418 | ||
419 | I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val); | |
420 | } | |
421 | } | |
422 | ||
423 | uint8_t | |
424 | bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder) | |
425 | { | |
426 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
427 | struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev); | |
428 | enum port port = dport->port; | |
429 | int lane; | |
430 | uint8_t mask; | |
431 | ||
432 | mask = 0; | |
433 | for (lane = 0; lane < 4; lane++) { | |
434 | u32 val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane)); | |
435 | ||
436 | if (val & LATENCY_OPTIM) | |
437 | mask |= BIT(lane); | |
438 | } | |
439 | ||
440 | return mask; | |
441 | } | |
442 | ||
443 | ||
b7fa22d8 ACO |
444 | void chv_set_phy_signal_level(struct intel_encoder *encoder, |
445 | u32 deemph_reg_value, u32 margin_reg_value, | |
446 | bool uniq_trans_scale) | |
447 | { | |
448 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
449 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
450 | struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc); | |
451 | enum dpio_channel ch = vlv_dport_to_channel(dport); | |
452 | enum pipe pipe = intel_crtc->pipe; | |
453 | u32 val; | |
454 | int i; | |
455 | ||
456 | mutex_lock(&dev_priv->sb_lock); | |
457 | ||
458 | /* Clear calc init */ | |
459 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); | |
460 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); | |
461 | val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); | |
462 | val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; | |
463 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); | |
464 | ||
465 | if (intel_crtc->config->lane_count > 2) { | |
466 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); | |
467 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); | |
468 | val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); | |
469 | val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; | |
470 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); | |
471 | } | |
472 | ||
473 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch)); | |
474 | val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); | |
475 | val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; | |
476 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val); | |
477 | ||
478 | if (intel_crtc->config->lane_count > 2) { | |
479 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch)); | |
480 | val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); | |
481 | val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; | |
482 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val); | |
483 | } | |
484 | ||
485 | /* Program swing deemph */ | |
486 | for (i = 0; i < intel_crtc->config->lane_count; i++) { | |
487 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i)); | |
488 | val &= ~DPIO_SWING_DEEMPH9P5_MASK; | |
489 | val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT; | |
490 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val); | |
491 | } | |
492 | ||
493 | /* Program swing margin */ | |
494 | for (i = 0; i < intel_crtc->config->lane_count; i++) { | |
495 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); | |
496 | ||
497 | val &= ~DPIO_SWING_MARGIN000_MASK; | |
498 | val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT; | |
499 | ||
500 | /* | |
501 | * Supposedly this value shouldn't matter when unique transition | |
502 | * scale is disabled, but in fact it does matter. Let's just | |
503 | * always program the same value and hope it's OK. | |
504 | */ | |
505 | val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT); | |
506 | val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT; | |
507 | ||
508 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); | |
509 | } | |
510 | ||
511 | /* | |
512 | * The document said it needs to set bit 27 for ch0 and bit 26 | |
513 | * for ch1. Might be a typo in the doc. | |
514 | * For now, for this unique transition scale selection, set bit | |
515 | * 27 for ch0 and ch1. | |
516 | */ | |
517 | for (i = 0; i < intel_crtc->config->lane_count; i++) { | |
518 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); | |
519 | if (uniq_trans_scale) | |
520 | val |= DPIO_TX_UNIQ_TRANS_SCALE_EN; | |
521 | else | |
522 | val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN; | |
523 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); | |
524 | } | |
525 | ||
526 | /* Start swing calculation */ | |
527 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); | |
528 | val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; | |
529 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); | |
530 | ||
531 | if (intel_crtc->config->lane_count > 2) { | |
532 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); | |
533 | val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; | |
534 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); | |
535 | } | |
536 | ||
537 | mutex_unlock(&dev_priv->sb_lock); | |
538 | ||
539 | } | |
540 | ||
844b2f9a ACO |
541 | void chv_data_lane_soft_reset(struct intel_encoder *encoder, |
542 | bool reset) | |
543 | { | |
544 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
545 | enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base)); | |
546 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); | |
547 | enum pipe pipe = crtc->pipe; | |
548 | uint32_t val; | |
549 | ||
550 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); | |
551 | if (reset) | |
552 | val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); | |
553 | else | |
554 | val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET; | |
555 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); | |
556 | ||
557 | if (crtc->config->lane_count > 2) { | |
558 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); | |
559 | if (reset) | |
560 | val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); | |
561 | else | |
562 | val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET; | |
563 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); | |
564 | } | |
565 | ||
566 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); | |
567 | val |= CHV_PCS_REQ_SOFTRESET_EN; | |
568 | if (reset) | |
569 | val &= ~DPIO_PCS_CLK_SOFT_RESET; | |
570 | else | |
571 | val |= DPIO_PCS_CLK_SOFT_RESET; | |
572 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); | |
573 | ||
574 | if (crtc->config->lane_count > 2) { | |
575 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); | |
576 | val |= CHV_PCS_REQ_SOFTRESET_EN; | |
577 | if (reset) | |
578 | val &= ~DPIO_PCS_CLK_SOFT_RESET; | |
579 | else | |
580 | val |= DPIO_PCS_CLK_SOFT_RESET; | |
581 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); | |
582 | } | |
583 | } | |
419b1b7a ACO |
584 | |
585 | void chv_phy_pre_pll_enable(struct intel_encoder *encoder) | |
586 | { | |
587 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
588 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 589 | struct drm_i915_private *dev_priv = to_i915(dev); |
419b1b7a ACO |
590 | struct intel_crtc *intel_crtc = |
591 | to_intel_crtc(encoder->base.crtc); | |
592 | enum dpio_channel ch = vlv_dport_to_channel(dport); | |
593 | enum pipe pipe = intel_crtc->pipe; | |
594 | unsigned int lane_mask = | |
595 | intel_dp_unused_lane_mask(intel_crtc->config->lane_count); | |
596 | u32 val; | |
597 | ||
598 | /* | |
599 | * Must trick the second common lane into life. | |
600 | * Otherwise we can't even access the PLL. | |
601 | */ | |
602 | if (ch == DPIO_CH0 && pipe == PIPE_B) | |
603 | dport->release_cl2_override = | |
604 | !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true); | |
605 | ||
606 | chv_phy_powergate_lanes(encoder, true, lane_mask); | |
607 | ||
608 | mutex_lock(&dev_priv->sb_lock); | |
609 | ||
610 | /* Assert data lane reset */ | |
611 | chv_data_lane_soft_reset(encoder, true); | |
612 | ||
613 | /* program left/right clock distribution */ | |
614 | if (pipe != PIPE_B) { | |
615 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); | |
616 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); | |
617 | if (ch == DPIO_CH0) | |
618 | val |= CHV_BUFLEFTENA1_FORCE; | |
619 | if (ch == DPIO_CH1) | |
620 | val |= CHV_BUFRIGHTENA1_FORCE; | |
621 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); | |
622 | } else { | |
623 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); | |
624 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); | |
625 | if (ch == DPIO_CH0) | |
626 | val |= CHV_BUFLEFTENA2_FORCE; | |
627 | if (ch == DPIO_CH1) | |
628 | val |= CHV_BUFRIGHTENA2_FORCE; | |
629 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); | |
630 | } | |
631 | ||
632 | /* program clock channel usage */ | |
633 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch)); | |
634 | val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; | |
635 | if (pipe != PIPE_B) | |
636 | val &= ~CHV_PCS_USEDCLKCHANNEL; | |
637 | else | |
638 | val |= CHV_PCS_USEDCLKCHANNEL; | |
639 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val); | |
640 | ||
641 | if (intel_crtc->config->lane_count > 2) { | |
642 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch)); | |
643 | val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; | |
644 | if (pipe != PIPE_B) | |
645 | val &= ~CHV_PCS_USEDCLKCHANNEL; | |
646 | else | |
647 | val |= CHV_PCS_USEDCLKCHANNEL; | |
648 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val); | |
649 | } | |
650 | ||
651 | /* | |
652 | * This a a bit weird since generally CL | |
653 | * matches the pipe, but here we need to | |
654 | * pick the CL based on the port. | |
655 | */ | |
656 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch)); | |
657 | if (pipe != PIPE_B) | |
658 | val &= ~CHV_CMN_USEDCLKCHANNEL; | |
659 | else | |
660 | val |= CHV_CMN_USEDCLKCHANNEL; | |
661 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val); | |
662 | ||
663 | mutex_unlock(&dev_priv->sb_lock); | |
664 | } | |
e7d2a717 ACO |
665 | |
666 | void chv_phy_pre_encoder_enable(struct intel_encoder *encoder) | |
667 | { | |
668 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
669 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); | |
670 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 671 | struct drm_i915_private *dev_priv = to_i915(dev); |
e7d2a717 ACO |
672 | struct intel_crtc *intel_crtc = |
673 | to_intel_crtc(encoder->base.crtc); | |
674 | enum dpio_channel ch = vlv_dport_to_channel(dport); | |
675 | int pipe = intel_crtc->pipe; | |
676 | int data, i, stagger; | |
677 | u32 val; | |
678 | ||
679 | mutex_lock(&dev_priv->sb_lock); | |
680 | ||
681 | /* allow hardware to manage TX FIFO reset source */ | |
682 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); | |
683 | val &= ~DPIO_LANEDESKEW_STRAP_OVRD; | |
684 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); | |
685 | ||
686 | if (intel_crtc->config->lane_count > 2) { | |
687 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); | |
688 | val &= ~DPIO_LANEDESKEW_STRAP_OVRD; | |
689 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); | |
690 | } | |
691 | ||
692 | /* Program Tx lane latency optimal setting*/ | |
693 | for (i = 0; i < intel_crtc->config->lane_count; i++) { | |
694 | /* Set the upar bit */ | |
695 | if (intel_crtc->config->lane_count == 1) | |
696 | data = 0x0; | |
697 | else | |
698 | data = (i == 1) ? 0x0 : 0x1; | |
699 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i), | |
700 | data << DPIO_UPAR_SHIFT); | |
701 | } | |
702 | ||
703 | /* Data lane stagger programming */ | |
704 | if (intel_crtc->config->port_clock > 270000) | |
705 | stagger = 0x18; | |
706 | else if (intel_crtc->config->port_clock > 135000) | |
707 | stagger = 0xd; | |
708 | else if (intel_crtc->config->port_clock > 67500) | |
709 | stagger = 0x7; | |
710 | else if (intel_crtc->config->port_clock > 33750) | |
711 | stagger = 0x4; | |
712 | else | |
713 | stagger = 0x2; | |
714 | ||
715 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); | |
716 | val |= DPIO_TX2_STAGGER_MASK(0x1f); | |
717 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); | |
718 | ||
719 | if (intel_crtc->config->lane_count > 2) { | |
720 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); | |
721 | val |= DPIO_TX2_STAGGER_MASK(0x1f); | |
722 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); | |
723 | } | |
724 | ||
725 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch), | |
726 | DPIO_LANESTAGGER_STRAP(stagger) | | |
727 | DPIO_LANESTAGGER_STRAP_OVRD | | |
728 | DPIO_TX1_STAGGER_MASK(0x1f) | | |
729 | DPIO_TX1_STAGGER_MULT(6) | | |
730 | DPIO_TX2_STAGGER_MULT(0)); | |
731 | ||
732 | if (intel_crtc->config->lane_count > 2) { | |
733 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch), | |
734 | DPIO_LANESTAGGER_STRAP(stagger) | | |
735 | DPIO_LANESTAGGER_STRAP_OVRD | | |
736 | DPIO_TX1_STAGGER_MASK(0x1f) | | |
737 | DPIO_TX1_STAGGER_MULT(7) | | |
738 | DPIO_TX2_STAGGER_MULT(5)); | |
739 | } | |
740 | ||
741 | /* Deassert data lane reset */ | |
742 | chv_data_lane_soft_reset(encoder, false); | |
743 | ||
744 | mutex_unlock(&dev_priv->sb_lock); | |
745 | } | |
746 | ||
747 | void chv_phy_release_cl2_override(struct intel_encoder *encoder) | |
748 | { | |
749 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
750 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
751 | ||
752 | if (dport->release_cl2_override) { | |
753 | chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false); | |
754 | dport->release_cl2_override = false; | |
755 | } | |
756 | } | |
204970b5 ACO |
757 | |
758 | void chv_phy_post_pll_disable(struct intel_encoder *encoder) | |
759 | { | |
760 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
761 | enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe; | |
762 | u32 val; | |
763 | ||
764 | mutex_lock(&dev_priv->sb_lock); | |
765 | ||
766 | /* disable left/right clock distribution */ | |
767 | if (pipe != PIPE_B) { | |
768 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); | |
769 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); | |
770 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); | |
771 | } else { | |
772 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); | |
773 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); | |
774 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); | |
775 | } | |
776 | ||
777 | mutex_unlock(&dev_priv->sb_lock); | |
778 | ||
779 | /* | |
780 | * Leave the power down bit cleared for at least one | |
781 | * lane so that chv_powergate_phy_ch() will power | |
782 | * on something when the channel is otherwise unused. | |
783 | * When the port is off and the override is removed | |
784 | * the lanes power down anyway, so otherwise it doesn't | |
785 | * really matter what the state of power down bits is | |
786 | * after this. | |
787 | */ | |
788 | chv_phy_powergate_lanes(encoder, false, 0x0); | |
789 | } | |
53d98725 ACO |
790 | |
791 | void vlv_set_phy_signal_level(struct intel_encoder *encoder, | |
792 | u32 demph_reg_value, u32 preemph_reg_value, | |
793 | u32 uniqtranscale_reg_value, u32 tx3_demph) | |
794 | { | |
795 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
796 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); | |
797 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
798 | enum dpio_channel port = vlv_dport_to_channel(dport); | |
799 | int pipe = intel_crtc->pipe; | |
800 | ||
801 | mutex_lock(&dev_priv->sb_lock); | |
802 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000); | |
803 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value); | |
804 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), | |
805 | uniqtranscale_reg_value); | |
806 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040); | |
807 | ||
808 | if (tx3_demph) | |
809 | vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), tx3_demph); | |
810 | ||
811 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); | |
812 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value); | |
813 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); | |
814 | mutex_unlock(&dev_priv->sb_lock); | |
815 | } | |
6da2e616 ACO |
816 | |
817 | void vlv_phy_pre_pll_enable(struct intel_encoder *encoder) | |
818 | { | |
819 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
820 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 821 | struct drm_i915_private *dev_priv = to_i915(dev); |
6da2e616 ACO |
822 | struct intel_crtc *intel_crtc = |
823 | to_intel_crtc(encoder->base.crtc); | |
824 | enum dpio_channel port = vlv_dport_to_channel(dport); | |
825 | int pipe = intel_crtc->pipe; | |
826 | ||
827 | /* Program Tx lane resets to default */ | |
828 | mutex_lock(&dev_priv->sb_lock); | |
829 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), | |
830 | DPIO_PCS_TX_LANE2_RESET | | |
831 | DPIO_PCS_TX_LANE1_RESET); | |
832 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), | |
833 | DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | | |
834 | DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | | |
835 | (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) | | |
836 | DPIO_PCS_CLK_SOFT_RESET); | |
837 | ||
838 | /* Fix up inter-pair skew failure */ | |
839 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); | |
840 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); | |
841 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); | |
842 | mutex_unlock(&dev_priv->sb_lock); | |
843 | } | |
5f68c275 ACO |
844 | |
845 | void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder) | |
846 | { | |
847 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
848 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); | |
849 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 850 | struct drm_i915_private *dev_priv = to_i915(dev); |
5f68c275 ACO |
851 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
852 | enum dpio_channel port = vlv_dport_to_channel(dport); | |
853 | int pipe = intel_crtc->pipe; | |
854 | u32 val; | |
855 | ||
856 | mutex_lock(&dev_priv->sb_lock); | |
857 | ||
858 | /* Enable clock channels for this port */ | |
859 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); | |
860 | val = 0; | |
861 | if (pipe) | |
862 | val |= (1<<21); | |
863 | else | |
864 | val &= ~(1<<21); | |
865 | val |= 0x001000c4; | |
866 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); | |
867 | ||
868 | /* Program lane clock */ | |
869 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); | |
870 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); | |
871 | ||
872 | mutex_unlock(&dev_priv->sb_lock); | |
873 | } | |
0f572ebe ACO |
874 | |
875 | void vlv_phy_reset_lanes(struct intel_encoder *encoder) | |
876 | { | |
877 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
fac5e23e | 878 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
0f572ebe ACO |
879 | struct intel_crtc *intel_crtc = |
880 | to_intel_crtc(encoder->base.crtc); | |
881 | enum dpio_channel port = vlv_dport_to_channel(dport); | |
882 | int pipe = intel_crtc->pipe; | |
883 | ||
884 | mutex_lock(&dev_priv->sb_lock); | |
885 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000); | |
886 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060); | |
887 | mutex_unlock(&dev_priv->sb_lock); | |
888 | } |