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drm/i915: Move broxton phy code to intel_dpio_phy.c
[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_dpio_phy.c
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b7fa22d8
ACO		 1/*
2 * Copyright © 2014-2016 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24#include "intel_drv.h"
25
47a6bc61
ACO		 26bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
27 enum dpio_phy phy)
28{
29 enum port port;
30
31 if (!(I915_READ(BXT_P_CR_GT_DISP_PWRON) & GT_DISPLAY_POWER_ON(phy)))
32 return false;
33
34 if ((I915_READ(BXT_PORT_CL1CM_DW0(phy)) &
35 (PHY_POWER_GOOD | PHY_RESERVED)) != PHY_POWER_GOOD) {
36 DRM_DEBUG_DRIVER("DDI PHY %d powered, but power hasn't settled\n",
37 phy);
38
39 return false;
40 }
41
42 if (phy == DPIO_PHY1 &&
43 !(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE)) {
44 DRM_DEBUG_DRIVER("DDI PHY 1 powered, but GRC isn't done\n");
45
46 return false;
47 }
48
49 if (!(I915_READ(BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) {
50 DRM_DEBUG_DRIVER("DDI PHY %d powered, but still in reset\n",
51 phy);
52
53 return false;
54 }
55
56 for_each_port_masked(port,
57 phy == DPIO_PHY0 ? BIT(PORT_B) | BIT(PORT_C) :
58 BIT(PORT_A)) {
59 u32 tmp = I915_READ(BXT_PHY_CTL(port));
60
61 if (tmp & BXT_PHY_CMNLANE_POWERDOWN_ACK) {
62 DRM_DEBUG_DRIVER("DDI PHY %d powered, but common lane "
63 "for port %c powered down "
64 "(PHY_CTL %08x)\n",
65 phy, port_name(port), tmp);
66
67 return false;
68 }
69 }
70
71 return true;
72}
73
74static u32 bxt_get_grc(struct drm_i915_private *dev_priv, enum dpio_phy phy)
75{
76 u32 val = I915_READ(BXT_PORT_REF_DW6(phy));
77
78 return (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
79}
80
81static void bxt_phy_wait_grc_done(struct drm_i915_private *dev_priv,
82 enum dpio_phy phy)
83{
84 if (intel_wait_for_register(dev_priv,
85 BXT_PORT_REF_DW3(phy),
86 GRC_DONE, GRC_DONE,
87 10))
88 DRM_ERROR("timeout waiting for PHY%d GRC\n", phy);
89}
90
91void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)
92{
93 u32 val;
94
95 if (bxt_ddi_phy_is_enabled(dev_priv, phy)) {
96 /* Still read out the GRC value for state verification */
97 if (phy == DPIO_PHY0)
98 dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, phy);
99
100 if (bxt_ddi_phy_verify_state(dev_priv, phy)) {
101 DRM_DEBUG_DRIVER("DDI PHY %d already enabled, "
102 "won't reprogram it\n", phy);
103
104 return;
105 }
106
107 DRM_DEBUG_DRIVER("DDI PHY %d enabled with invalid state, "
108 "force reprogramming it\n", phy);
109 }
110
111 val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
112 val |= GT_DISPLAY_POWER_ON(phy);
113 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
114
115 /*
116 * The PHY registers start out inaccessible and respond to reads with
117 * all 1s. Eventually they become accessible as they power up, then
118 * the reserved bit will give the default 0. Poll on the reserved bit
119 * becoming 0 to find when the PHY is accessible.
120 * HW team confirmed that the time to reach phypowergood status is
121 * anywhere between 50 us and 100us.
122 */
123 if (wait_for_us(((I915_READ(BXT_PORT_CL1CM_DW0(phy)) &
124 (PHY_RESERVED | PHY_POWER_GOOD)) == PHY_POWER_GOOD), 100)) {
125 DRM_ERROR("timeout during PHY%d power on\n", phy);
126 }
127
128 /* Program PLL Rcomp code offset */
129 val = I915_READ(BXT_PORT_CL1CM_DW9(phy));
130 val &= ~IREF0RC_OFFSET_MASK;
131 val |= 0xE4 << IREF0RC_OFFSET_SHIFT;
132 I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val);
133
134 val = I915_READ(BXT_PORT_CL1CM_DW10(phy));
135 val &= ~IREF1RC_OFFSET_MASK;
136 val |= 0xE4 << IREF1RC_OFFSET_SHIFT;
137 I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val);
138
139 /* Program power gating */
140 val = I915_READ(BXT_PORT_CL1CM_DW28(phy));
141 val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN |
142 SUS_CLK_CONFIG;
143 I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
144
145 if (phy == DPIO_PHY0) {
146 val = I915_READ(BXT_PORT_CL2CM_DW6_BC);
147 val |= DW6_OLDO_DYN_PWR_DOWN_EN;
148 I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val);
149 }
150
151 val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
152 val &= ~OCL2_LDOFUSE_PWR_DIS;
153 /*
154 * On PHY1 disable power on the second channel, since no port is
155 * connected there. On PHY0 both channels have a port, so leave it
156 * enabled.
157 * TODO: port C is only connected on BXT-P, so on BXT0/1 we should
158 * power down the second channel on PHY0 as well.
159 *
160 * FIXME: Clarify programming of the following, the register is
161 * read-only with bit 6 fixed at 0 at least in stepping A.
162 */
163 if (phy == DPIO_PHY1)
164 val |= OCL2_LDOFUSE_PWR_DIS;
165 I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
166
167 if (phy == DPIO_PHY0) {
168 uint32_t grc_code;
169 /*
170 * PHY0 isn't connected to an RCOMP resistor so copy over
171 * the corresponding calibrated value from PHY1, and disable
172 * the automatic calibration on PHY0.
173 */
174 val = dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, DPIO_PHY1);
175 grc_code = val << GRC_CODE_FAST_SHIFT |
176 val << GRC_CODE_SLOW_SHIFT |
177 val;
178 I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code);
179
180 val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0));
181 val |= GRC_DIS | GRC_RDY_OVRD;
182 I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val);
183 }
184
185 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
186 val |= COMMON_RESET_DIS;
187 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
188
189 if (phy == DPIO_PHY1)
190 bxt_phy_wait_grc_done(dev_priv, DPIO_PHY1);
191}
192
193void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy)
194{
195 uint32_t val;
196
197 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
198 val &= ~COMMON_RESET_DIS;
199 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
200
201 val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
202 val &= ~GT_DISPLAY_POWER_ON(phy);
203 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
204}
205
206static bool __printf(6, 7)
207__phy_reg_verify_state(struct drm_i915_private *dev_priv, enum dpio_phy phy,
208 i915_reg_t reg, u32 mask, u32 expected,
209 const char *reg_fmt, ...)
210{
211 struct va_format vaf;
212 va_list args;
213 u32 val;
214
215 val = I915_READ(reg);
216 if ((val & mask) == expected)
217 return true;
218
219 va_start(args, reg_fmt);
220 vaf.fmt = reg_fmt;
221 vaf.va = &args;
222
223 DRM_DEBUG_DRIVER("DDI PHY %d reg %pV [%08x] state mismatch: "
224 "current %08x, expected %08x (mask %08x)\n",
225 phy, &vaf, reg.reg, val, (val & ~mask) | expected,
226 mask);
227
228 va_end(args);
229
230 return false;
231}
232
233bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
234 enum dpio_phy phy)
235{
236 uint32_t mask;
237 bool ok;
238
239#define _CHK(reg, mask, exp, fmt, ...) \
240 __phy_reg_verify_state(dev_priv, phy, reg, mask, exp, fmt, \
241 ## __VA_ARGS__)
242
243 if (!bxt_ddi_phy_is_enabled(dev_priv, phy))
244 return false;
245
246 ok = true;
247
248 /* PLL Rcomp code offset */
249 ok &= _CHK(BXT_PORT_CL1CM_DW9(phy),
250 IREF0RC_OFFSET_MASK, 0xe4 << IREF0RC_OFFSET_SHIFT,
251 "BXT_PORT_CL1CM_DW9(%d)", phy);
252 ok &= _CHK(BXT_PORT_CL1CM_DW10(phy),
253 IREF1RC_OFFSET_MASK, 0xe4 << IREF1RC_OFFSET_SHIFT,
254 "BXT_PORT_CL1CM_DW10(%d)", phy);
255
256 /* Power gating */
257 mask = OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | SUS_CLK_CONFIG;
258 ok &= _CHK(BXT_PORT_CL1CM_DW28(phy), mask, mask,
259 "BXT_PORT_CL1CM_DW28(%d)", phy);
260
261 if (phy == DPIO_PHY0)
262 ok &= _CHK(BXT_PORT_CL2CM_DW6_BC,
263 DW6_OLDO_DYN_PWR_DOWN_EN, DW6_OLDO_DYN_PWR_DOWN_EN,
264 "BXT_PORT_CL2CM_DW6_BC");
265
266 /*
267 * TODO: Verify BXT_PORT_CL1CM_DW30 bit OCL2_LDOFUSE_PWR_DIS,
268 * at least on stepping A this bit is read-only and fixed at 0.
269 */
270
271 if (phy == DPIO_PHY0) {
272 u32 grc_code = dev_priv->bxt_phy_grc;
273
274 grc_code = grc_code << GRC_CODE_FAST_SHIFT |
275 grc_code << GRC_CODE_SLOW_SHIFT |
276 grc_code;
277 mask = GRC_CODE_FAST_MASK | GRC_CODE_SLOW_MASK |
278 GRC_CODE_NOM_MASK;
279 ok &= _CHK(BXT_PORT_REF_DW6(DPIO_PHY0), mask, grc_code,
280 "BXT_PORT_REF_DW6(%d)", DPIO_PHY0);
281
282 mask = GRC_DIS | GRC_RDY_OVRD;
283 ok &= _CHK(BXT_PORT_REF_DW8(DPIO_PHY0), mask, mask,
284 "BXT_PORT_REF_DW8(%d)", DPIO_PHY0);
285 }
286
287 return ok;
288#undef _CHK
289}
290
291uint8_t
292bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder *encoder,
293 uint8_t lane_count)
294{
295 switch (lane_count) {
296 case 1:
297 return 0;
298 case 2:
299 return BIT(2) | BIT(0);
300 case 4:
301 return BIT(3) | BIT(2) | BIT(0);
302 default:
303 MISSING_CASE(lane_count);
304
305 return 0;
306 }
307}
308
309void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
310 uint8_t lane_lat_optim_mask)
311{
312 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
313 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
314 enum port port = dport->port;
315 int lane;
316
317 for (lane = 0; lane < 4; lane++) {
318 u32 val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
319
320 /*
321 * Note that on CHV this flag is called UPAR, but has
322 * the same function.
323 */
324 val &= ~LATENCY_OPTIM;
325 if (lane_lat_optim_mask & BIT(lane))
326 val |= LATENCY_OPTIM;
327
328 I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val);
329 }
330}
331
332uint8_t
333bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder)
334{
335 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
336 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
337 enum port port = dport->port;
338 int lane;
339 uint8_t mask;
340
341 mask = 0;
342 for (lane = 0; lane < 4; lane++) {
343 u32 val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
344
345 if (val & LATENCY_OPTIM)
346 mask |= BIT(lane);
347 }
348
349 return mask;
350}
351
352
b7fa22d8
ACO		 353void chv_set_phy_signal_level(struct intel_encoder *encoder,
354 u32 deemph_reg_value, u32 margin_reg_value,
355 bool uniq_trans_scale)
356{
357 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
358 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
359 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
360 enum dpio_channel ch = vlv_dport_to_channel(dport);
361 enum pipe pipe = intel_crtc->pipe;
362 u32 val;
363 int i;
364
365 mutex_lock(&dev_priv->sb_lock);
366
367 /* Clear calc init */
368 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
369 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
370 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
371 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
372 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
373
374 if (intel_crtc->config->lane_count > 2) {
375 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
376 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
377 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
378 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
379 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
380 }
381
382 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
383 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
384 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
385 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
386
387 if (intel_crtc->config->lane_count > 2) {
388 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
389 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
390 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
391 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
392 }
393
394 /* Program swing deemph */
395 for (i = 0; i < intel_crtc->config->lane_count; i++) {
396 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
397 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
398 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
399 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
400 }
401
402 /* Program swing margin */
403 for (i = 0; i < intel_crtc->config->lane_count; i++) {
404 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
405
406 val &= ~DPIO_SWING_MARGIN000_MASK;
407 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
408
409 /*
410 * Supposedly this value shouldn't matter when unique transition
411 * scale is disabled, but in fact it does matter. Let's just
412 * always program the same value and hope it's OK.
413 */
414 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
415 val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT;
416
417 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
418 }
419
420 /*
421 * The document said it needs to set bit 27 for ch0 and bit 26
422 * for ch1. Might be a typo in the doc.
423 * For now, for this unique transition scale selection, set bit
424 * 27 for ch0 and ch1.
425 */
426 for (i = 0; i < intel_crtc->config->lane_count; i++) {
427 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
428 if (uniq_trans_scale)
429 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
430 else
431 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
432 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
433 }
434
435 /* Start swing calculation */
436 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
437 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
438 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
439
440 if (intel_crtc->config->lane_count > 2) {
441 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
442 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
443 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
444 }
445
446 mutex_unlock(&dev_priv->sb_lock);
447
448}
449
844b2f9a
ACO		 450void chv_data_lane_soft_reset(struct intel_encoder *encoder,
451 bool reset)
452{
453 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
454 enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
455 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
456 enum pipe pipe = crtc->pipe;
457 uint32_t val;
458
459 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
460 if (reset)
461 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
462 else
463 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
464 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
465
466 if (crtc->config->lane_count > 2) {
467 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
468 if (reset)
469 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
470 else
471 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
472 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
473 }
474
475 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
476 val |= CHV_PCS_REQ_SOFTRESET_EN;
477 if (reset)
478 val &= ~DPIO_PCS_CLK_SOFT_RESET;
479 else
480 val |= DPIO_PCS_CLK_SOFT_RESET;
481 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
482
483 if (crtc->config->lane_count > 2) {
484 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
485 val |= CHV_PCS_REQ_SOFTRESET_EN;
486 if (reset)
487 val &= ~DPIO_PCS_CLK_SOFT_RESET;
488 else
489 val |= DPIO_PCS_CLK_SOFT_RESET;
490 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
491 }
492}
419b1b7a
ACO		 493
494void chv_phy_pre_pll_enable(struct intel_encoder *encoder)
495{
496 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
497 struct drm_device *dev = encoder->base.dev;
fac5e23e 498 struct drm_i915_private *dev_priv = to_i915(dev);
419b1b7a
ACO		 499 struct intel_crtc *intel_crtc =
500 to_intel_crtc(encoder->base.crtc);
501 enum dpio_channel ch = vlv_dport_to_channel(dport);
502 enum pipe pipe = intel_crtc->pipe;
503 unsigned int lane_mask =
504 intel_dp_unused_lane_mask(intel_crtc->config->lane_count);
505 u32 val;
506
507 /*
508 * Must trick the second common lane into life.
509 * Otherwise we can't even access the PLL.
510 */
511 if (ch == DPIO_CH0 && pipe == PIPE_B)
512 dport->release_cl2_override =
513 !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true);
514
515 chv_phy_powergate_lanes(encoder, true, lane_mask);
516
517 mutex_lock(&dev_priv->sb_lock);
518
519 /* Assert data lane reset */
520 chv_data_lane_soft_reset(encoder, true);
521
522 /* program left/right clock distribution */
523 if (pipe != PIPE_B) {
524 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
525 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
526 if (ch == DPIO_CH0)
527 val |= CHV_BUFLEFTENA1_FORCE;
528 if (ch == DPIO_CH1)
529 val |= CHV_BUFRIGHTENA1_FORCE;
530 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
531 } else {
532 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
533 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
534 if (ch == DPIO_CH0)
535 val |= CHV_BUFLEFTENA2_FORCE;
536 if (ch == DPIO_CH1)
537 val |= CHV_BUFRIGHTENA2_FORCE;
538 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
539 }
540
541 /* program clock channel usage */
542 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
543 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
544 if (pipe != PIPE_B)
545 val &= ~CHV_PCS_USEDCLKCHANNEL;
546 else
547 val |= CHV_PCS_USEDCLKCHANNEL;
548 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
549
550 if (intel_crtc->config->lane_count > 2) {
551 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
552 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
553 if (pipe != PIPE_B)
554 val &= ~CHV_PCS_USEDCLKCHANNEL;
555 else
556 val |= CHV_PCS_USEDCLKCHANNEL;
557 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
558 }
559
560 /*
561 * This a a bit weird since generally CL
562 * matches the pipe, but here we need to
563 * pick the CL based on the port.
564 */
565 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
566 if (pipe != PIPE_B)
567 val &= ~CHV_CMN_USEDCLKCHANNEL;
568 else
569 val |= CHV_CMN_USEDCLKCHANNEL;
570 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
571
572 mutex_unlock(&dev_priv->sb_lock);
573}
e7d2a717
ACO		 574
575void chv_phy_pre_encoder_enable(struct intel_encoder *encoder)
576{
577 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
578 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
579 struct drm_device *dev = encoder->base.dev;
fac5e23e 580 struct drm_i915_private *dev_priv = to_i915(dev);
e7d2a717
ACO		 581 struct intel_crtc *intel_crtc =
582 to_intel_crtc(encoder->base.crtc);
583 enum dpio_channel ch = vlv_dport_to_channel(dport);
584 int pipe = intel_crtc->pipe;
585 int data, i, stagger;
586 u32 val;
587
588 mutex_lock(&dev_priv->sb_lock);
589
590 /* allow hardware to manage TX FIFO reset source */
591 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
592 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
593 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
594
595 if (intel_crtc->config->lane_count > 2) {
596 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
597 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
598 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
599 }
600
601 /* Program Tx lane latency optimal setting*/
602 for (i = 0; i < intel_crtc->config->lane_count; i++) {
603 /* Set the upar bit */
604 if (intel_crtc->config->lane_count == 1)
605 data = 0x0;
606 else
607 data = (i == 1) ? 0x0 : 0x1;
608 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
609 data << DPIO_UPAR_SHIFT);
610 }
611
612 /* Data lane stagger programming */
613 if (intel_crtc->config->port_clock > 270000)
614 stagger = 0x18;
615 else if (intel_crtc->config->port_clock > 135000)
616 stagger = 0xd;
617 else if (intel_crtc->config->port_clock > 67500)
618 stagger = 0x7;
619 else if (intel_crtc->config->port_clock > 33750)
620 stagger = 0x4;
621 else
622 stagger = 0x2;
623
624 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
625 val |= DPIO_TX2_STAGGER_MASK(0x1f);
626 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
627
628 if (intel_crtc->config->lane_count > 2) {
629 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
630 val |= DPIO_TX2_STAGGER_MASK(0x1f);
631 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
632 }
633
634 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
635 DPIO_LANESTAGGER_STRAP(stagger) |
636 DPIO_LANESTAGGER_STRAP_OVRD |
637 DPIO_TX1_STAGGER_MASK(0x1f) |
638 DPIO_TX1_STAGGER_MULT(6) |
639 DPIO_TX2_STAGGER_MULT(0));
640
641 if (intel_crtc->config->lane_count > 2) {
642 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
643 DPIO_LANESTAGGER_STRAP(stagger) |
644 DPIO_LANESTAGGER_STRAP_OVRD |
645 DPIO_TX1_STAGGER_MASK(0x1f) |
646 DPIO_TX1_STAGGER_MULT(7) |
647 DPIO_TX2_STAGGER_MULT(5));
648 }
649
650 /* Deassert data lane reset */
651 chv_data_lane_soft_reset(encoder, false);
652
653 mutex_unlock(&dev_priv->sb_lock);
654}
655
656void chv_phy_release_cl2_override(struct intel_encoder *encoder)
657{
658 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
659 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
660
661 if (dport->release_cl2_override) {
662 chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false);
663 dport->release_cl2_override = false;
664 }
665}
204970b5
ACO		 666
667void chv_phy_post_pll_disable(struct intel_encoder *encoder)
668{
669 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
670 enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
671 u32 val;
672
673 mutex_lock(&dev_priv->sb_lock);
674
675 /* disable left/right clock distribution */
676 if (pipe != PIPE_B) {
677 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
678 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
679 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
680 } else {
681 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
682 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
683 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
684 }
685
686 mutex_unlock(&dev_priv->sb_lock);
687
688 /*
689 * Leave the power down bit cleared for at least one
690 * lane so that chv_powergate_phy_ch() will power
691 * on something when the channel is otherwise unused.
692 * When the port is off and the override is removed
693 * the lanes power down anyway, so otherwise it doesn't
694 * really matter what the state of power down bits is
695 * after this.
696 */
697 chv_phy_powergate_lanes(encoder, false, 0x0);
698}
53d98725
ACO		 699
700void vlv_set_phy_signal_level(struct intel_encoder *encoder,
701 u32 demph_reg_value, u32 preemph_reg_value,
702 u32 uniqtranscale_reg_value, u32 tx3_demph)
703{
704 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
705 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
706 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
707 enum dpio_channel port = vlv_dport_to_channel(dport);
708 int pipe = intel_crtc->pipe;
709
710 mutex_lock(&dev_priv->sb_lock);
711 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
712 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
713 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
714 uniqtranscale_reg_value);
715 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
716
717 if (tx3_demph)
718 vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), tx3_demph);
719
720 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
721 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
722 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
723 mutex_unlock(&dev_priv->sb_lock);
724}
6da2e616
ACO		 725
726void vlv_phy_pre_pll_enable(struct intel_encoder *encoder)
727{
728 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
729 struct drm_device *dev = encoder->base.dev;
fac5e23e 730 struct drm_i915_private *dev_priv = to_i915(dev);
6da2e616
ACO		 731 struct intel_crtc *intel_crtc =
732 to_intel_crtc(encoder->base.crtc);
733 enum dpio_channel port = vlv_dport_to_channel(dport);
734 int pipe = intel_crtc->pipe;
735
736 /* Program Tx lane resets to default */
737 mutex_lock(&dev_priv->sb_lock);
738 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
739 DPIO_PCS_TX_LANE2_RESET |
740 DPIO_PCS_TX_LANE1_RESET);
741 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
742 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
743 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
744 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
745 DPIO_PCS_CLK_SOFT_RESET);
746
747 /* Fix up inter-pair skew failure */
748 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
749 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
750 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
751 mutex_unlock(&dev_priv->sb_lock);
752}
5f68c275
ACO		 753
754void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder)
755{
756 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
757 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
758 struct drm_device *dev = encoder->base.dev;
fac5e23e 759 struct drm_i915_private *dev_priv = to_i915(dev);
5f68c275
ACO		 760 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
761 enum dpio_channel port = vlv_dport_to_channel(dport);
762 int pipe = intel_crtc->pipe;
763 u32 val;
764
765 mutex_lock(&dev_priv->sb_lock);
766
767 /* Enable clock channels for this port */
768 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
769 val = 0;
770 if (pipe)
771 val |= (1<<21);
772 else
773 val &= ~(1<<21);
774 val |= 0x001000c4;
775 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
776
777 /* Program lane clock */
778 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
779 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
780
781 mutex_unlock(&dev_priv->sb_lock);
782}
0f572ebe
ACO		 783
784void vlv_phy_reset_lanes(struct intel_encoder *encoder)
785{
786 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
fac5e23e 787 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0f572ebe
ACO		 788 struct intel_crtc *intel_crtc =
789 to_intel_crtc(encoder->base.crtc);
790 enum dpio_channel port = vlv_dport_to_channel(dport);
791 int pipe = intel_crtc->pipe;
792
793 mutex_lock(&dev_priv->sb_lock);
794 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000);
795 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060);
796 mutex_unlock(&dev_priv->sb_lock);
797}
Linux 6.x block layer and io_uring tree(s)