[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_dpio_phy.c

/*
 * Copyright © 2014-2016 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */

#include "intel_drv.h"

void chv_set_phy_signal_level(struct intel_encoder *encoder,
			      u32 deemph_reg_value, u32 margin_reg_value,
			      bool uniq_trans_scale)
{
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
	struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
	enum dpio_channel ch = vlv_dport_to_channel(dport);
	enum pipe pipe = intel_crtc->pipe;
	u32 val;
	int i;

	mutex_lock(&dev_priv->sb_lock);

	/* Clear calc init */
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
	val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
	val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
	val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);

	if (intel_crtc->config->lane_count > 2) {
		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
		val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
		val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
		val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
	}

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
	val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
	val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);

	if (intel_crtc->config->lane_count > 2) {
		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
		val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
		val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
	}

	/* Program swing deemph */
	for (i = 0; i < intel_crtc->config->lane_count; i++) {
		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
		val &= ~DPIO_SWING_DEEMPH9P5_MASK;
		val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
	}

	/* Program swing margin */
	for (i = 0; i < intel_crtc->config->lane_count; i++) {
		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));

		val &= ~DPIO_SWING_MARGIN000_MASK;
		val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;

		/*
		 * Supposedly this value shouldn't matter when unique transition
		 * scale is disabled, but in fact it does matter. Let's just
		 * always program the same value and hope it's OK.
		 */
		val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
		val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT;

		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
	}

	/*
	 * The document said it needs to set bit 27 for ch0 and bit 26
	 * for ch1. Might be a typo in the doc.
	 * For now, for this unique transition scale selection, set bit
	 * 27 for ch0 and ch1.
	 */
	for (i = 0; i < intel_crtc->config->lane_count; i++) {
		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
		if (uniq_trans_scale)
			val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
		else
			val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
	}

	/* Start swing calculation */
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
	val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);

	if (intel_crtc->config->lane_count > 2) {
		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
		val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
	}

	mutex_unlock(&dev_priv->sb_lock);

}

void chv_data_lane_soft_reset(struct intel_encoder *encoder,
			      bool reset)
{
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
	enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
	enum pipe pipe = crtc->pipe;
	uint32_t val;

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
	if (reset)
		val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
	else
		val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);

	if (crtc->config->lane_count > 2) {
		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
		if (reset)
			val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
		else
			val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
	}

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
	val |= CHV_PCS_REQ_SOFTRESET_EN;
	if (reset)
		val &= ~DPIO_PCS_CLK_SOFT_RESET;
	else
		val |= DPIO_PCS_CLK_SOFT_RESET;
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);

	if (crtc->config->lane_count > 2) {
		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
		val |= CHV_PCS_REQ_SOFTRESET_EN;
		if (reset)
			val &= ~DPIO_PCS_CLK_SOFT_RESET;
		else
			val |= DPIO_PCS_CLK_SOFT_RESET;
		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
	}
}

void chv_phy_pre_pll_enable(struct intel_encoder *encoder)
{
	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc =
		to_intel_crtc(encoder->base.crtc);
	enum dpio_channel ch = vlv_dport_to_channel(dport);
	enum pipe pipe = intel_crtc->pipe;
	unsigned int lane_mask =
		intel_dp_unused_lane_mask(intel_crtc->config->lane_count);
	u32 val;

	/*
	 * Must trick the second common lane into life.
	 * Otherwise we can't even access the PLL.
	 */
	if (ch == DPIO_CH0 && pipe == PIPE_B)
		dport->release_cl2_override =
			!chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true);

	chv_phy_powergate_lanes(encoder, true, lane_mask);

	mutex_lock(&dev_priv->sb_lock);

	/* Assert data lane reset */
	chv_data_lane_soft_reset(encoder, true);

	/* program left/right clock distribution */
	if (pipe != PIPE_B) {
		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
		if (ch == DPIO_CH0)
			val |= CHV_BUFLEFTENA1_FORCE;
		if (ch == DPIO_CH1)
			val |= CHV_BUFRIGHTENA1_FORCE;
		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
	} else {
		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
		if (ch == DPIO_CH0)
			val |= CHV_BUFLEFTENA2_FORCE;
		if (ch == DPIO_CH1)
			val |= CHV_BUFRIGHTENA2_FORCE;
		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
	}

	/* program clock channel usage */
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
	val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
	if (pipe != PIPE_B)
		val &= ~CHV_PCS_USEDCLKCHANNEL;
	else
		val |= CHV_PCS_USEDCLKCHANNEL;
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);

	if (intel_crtc->config->lane_count > 2) {
		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
		val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
		if (pipe != PIPE_B)
			val &= ~CHV_PCS_USEDCLKCHANNEL;
		else
			val |= CHV_PCS_USEDCLKCHANNEL;
		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
	}

	/*
	 * This a a bit weird since generally CL
	 * matches the pipe, but here we need to
	 * pick the CL based on the port.
	 */
	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
	if (pipe != PIPE_B)
		val &= ~CHV_CMN_USEDCLKCHANNEL;
	else
		val |= CHV_CMN_USEDCLKCHANNEL;
	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);

	mutex_unlock(&dev_priv->sb_lock);
}
Commit	Line	Data
b7fa22d8 ACO	1	/*
	2	* Copyright © 2014-2016 Intel Corporation
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	21	* DEALINGS IN THE SOFTWARE.
	22	*/
	23
	24	#include "intel_drv.h"
	25
	26	void chv_set_phy_signal_level(struct intel_encoder *encoder,
	27	u32 deemph_reg_value, u32 margin_reg_value,
	28	bool uniq_trans_scale)
	29	{
	30	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
	31	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
	32	struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
	33	enum dpio_channel ch = vlv_dport_to_channel(dport);
	34	enum pipe pipe = intel_crtc->pipe;
	35	u32 val;
	36	int i;
	37
	38	mutex_lock(&dev_priv->sb_lock);
	39
	40	/* Clear calc init */
	41	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
	42	val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 \| DPIO_PCS_SWING_CALC_TX1_TX3);
	43	val &= ~(DPIO_PCS_TX1DEEMP_MASK \| DPIO_PCS_TX2DEEMP_MASK);
	44	val \|= DPIO_PCS_TX1DEEMP_9P5 \| DPIO_PCS_TX2DEEMP_9P5;
	45	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
	46
	47	if (intel_crtc->config->lane_count > 2) {
	48	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
	49	val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 \| DPIO_PCS_SWING_CALC_TX1_TX3);
	50	val &= ~(DPIO_PCS_TX1DEEMP_MASK \| DPIO_PCS_TX2DEEMP_MASK);
	51	val \|= DPIO_PCS_TX1DEEMP_9P5 \| DPIO_PCS_TX2DEEMP_9P5;
	52	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
	53	}
	54
	55	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
	56	val &= ~(DPIO_PCS_TX1MARGIN_MASK \| DPIO_PCS_TX2MARGIN_MASK);
	57	val \|= DPIO_PCS_TX1MARGIN_000 \| DPIO_PCS_TX2MARGIN_000;
	58	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
	59
	60	if (intel_crtc->config->lane_count > 2) {
	61	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
	62	val &= ~(DPIO_PCS_TX1MARGIN_MASK \| DPIO_PCS_TX2MARGIN_MASK);
	63	val \|= DPIO_PCS_TX1MARGIN_000 \| DPIO_PCS_TX2MARGIN_000;
	64	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
65	}
66
67	/* Program swing deemph */
68	for (i = 0; i < intel_crtc->config->lane_count; i++) {
69	val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
70	val &= ~DPIO_SWING_DEEMPH9P5_MASK;
71	val \|= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
72	vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
73	}
74
75	/* Program swing margin */
76	for (i = 0; i < intel_crtc->config->lane_count; i++) {
77	val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
78
79	val &= ~DPIO_SWING_MARGIN000_MASK;
80	val \|= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
81
82	/*
83	* Supposedly this value shouldn't matter when unique transition
84	* scale is disabled, but in fact it does matter. Let's just
85	* always program the same value and hope it's OK.
86	*/
87	val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
88	val \|= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT;
89
90	vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
91	}
92
93	/*
94	* The document said it needs to set bit 27 for ch0 and bit 26
95	* for ch1. Might be a typo in the doc.
96	* For now, for this unique transition scale selection, set bit
97	* 27 for ch0 and ch1.
98	*/
99	for (i = 0; i < intel_crtc->config->lane_count; i++) {
100	val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
101	if (uniq_trans_scale)
102	val \|= DPIO_TX_UNIQ_TRANS_SCALE_EN;
103	else
104	val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
105	vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
106	}
107
108	/* Start swing calculation */
109	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
110	val \|= DPIO_PCS_SWING_CALC_TX0_TX2 \| DPIO_PCS_SWING_CALC_TX1_TX3;
111	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
112
113	if (intel_crtc->config->lane_count > 2) {
114	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
115	val \|= DPIO_PCS_SWING_CALC_TX0_TX2 \| DPIO_PCS_SWING_CALC_TX1_TX3;
116	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
117	}
118
119	mutex_unlock(&dev_priv->sb_lock);
120
121	}
122
844b2f9a ACO	123	void chv_data_lane_soft_reset(struct intel_encoder *encoder,
	124	bool reset)
	125	{
	126	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
	127	enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
	128	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
	129	enum pipe pipe = crtc->pipe;
	130	uint32_t val;
	131
	132	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
	133	if (reset)
	134	val &= ~(DPIO_PCS_TX_LANE2_RESET \| DPIO_PCS_TX_LANE1_RESET);
	135	else
	136	val \|= DPIO_PCS_TX_LANE2_RESET \| DPIO_PCS_TX_LANE1_RESET;
	137	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
	138
	139	if (crtc->config->lane_count > 2) {
	140	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
	141	if (reset)
	142	val &= ~(DPIO_PCS_TX_LANE2_RESET \| DPIO_PCS_TX_LANE1_RESET);
	143	else
	144	val \|= DPIO_PCS_TX_LANE2_RESET \| DPIO_PCS_TX_LANE1_RESET;
	145	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
	146	}
	147
	148	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
	149	val \|= CHV_PCS_REQ_SOFTRESET_EN;
	150	if (reset)
	151	val &= ~DPIO_PCS_CLK_SOFT_RESET;
	152	else
	153	val \|= DPIO_PCS_CLK_SOFT_RESET;
	154	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
	155
	156	if (crtc->config->lane_count > 2) {
	157	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
	158	val \|= CHV_PCS_REQ_SOFTRESET_EN;
	159	if (reset)
	160	val &= ~DPIO_PCS_CLK_SOFT_RESET;
	161	else
	162	val \|= DPIO_PCS_CLK_SOFT_RESET;
	163	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
	164	}
	165	}
419b1b7a ACO	166
	167	void chv_phy_pre_pll_enable(struct intel_encoder *encoder)
	168	{
	169	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
	170	struct drm_device *dev = encoder->base.dev;
	171	struct drm_i915_private *dev_priv = dev->dev_private;
	172	struct intel_crtc *intel_crtc =
	173	to_intel_crtc(encoder->base.crtc);
	174	enum dpio_channel ch = vlv_dport_to_channel(dport);
	175	enum pipe pipe = intel_crtc->pipe;
	176	unsigned int lane_mask =
	177	intel_dp_unused_lane_mask(intel_crtc->config->lane_count);
	178	u32 val;
	179
	180	/*
	181	* Must trick the second common lane into life.
	182	* Otherwise we can't even access the PLL.
	183	*/
	184	if (ch == DPIO_CH0 && pipe == PIPE_B)
	185	dport->release_cl2_override =
	186	!chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true);
	187
	188	chv_phy_powergate_lanes(encoder, true, lane_mask);
	189
	190	mutex_lock(&dev_priv->sb_lock);
	191
	192	/* Assert data lane reset */
	193	chv_data_lane_soft_reset(encoder, true);
	194
	195	/* program left/right clock distribution */
	196	if (pipe != PIPE_B) {
	197	val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
	198	val &= ~(CHV_BUFLEFTENA1_MASK \| CHV_BUFRIGHTENA1_MASK);
	199	if (ch == DPIO_CH0)
	200	val \|= CHV_BUFLEFTENA1_FORCE;
	201	if (ch == DPIO_CH1)
	202	val \|= CHV_BUFRIGHTENA1_FORCE;
	203	vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
	204	} else {
	205	val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
	206	val &= ~(CHV_BUFLEFTENA2_MASK \| CHV_BUFRIGHTENA2_MASK);
	207	if (ch == DPIO_CH0)
	208	val \|= CHV_BUFLEFTENA2_FORCE;
	209	if (ch == DPIO_CH1)
	210	val \|= CHV_BUFRIGHTENA2_FORCE;
	211	vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
	212	}
	213
	214	/* program clock channel usage */
	215	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
	216	val \|= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
	217	if (pipe != PIPE_B)
	218	val &= ~CHV_PCS_USEDCLKCHANNEL;
	219	else
	220	val \|= CHV_PCS_USEDCLKCHANNEL;
	221	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
	222
	223	if (intel_crtc->config->lane_count > 2) {
	224	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
	225	val \|= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
	226	if (pipe != PIPE_B)
	227	val &= ~CHV_PCS_USEDCLKCHANNEL;
	228	else
	229	val \|= CHV_PCS_USEDCLKCHANNEL;
230	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
231	}
232
233	/*
234	* This a a bit weird since generally CL
235	* matches the pipe, but here we need to
236	* pick the CL based on the port.
237	*/
238	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
239	if (pipe != PIPE_B)
240	val &= ~CHV_CMN_USEDCLKCHANNEL;
241	else
242	val \|= CHV_CMN_USEDCLKCHANNEL;
243	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
244
245	mutex_unlock(&dev_priv->sb_lock);
246	}