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b7fa22d8 ACO |
1 | /* |
2 | * Copyright © 2014-2016 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | */ | |
23 | ||
24 | #include "intel_drv.h" | |
25 | ||
f38861b8 ACO |
26 | /** |
27 | * DOC: DPIO | |
28 | * | |
29 | * VLV, CHV and BXT have slightly peculiar display PHYs for driving DP/HDMI | |
30 | * ports. DPIO is the name given to such a display PHY. These PHYs | |
31 | * don't follow the standard programming model using direct MMIO | |
32 | * registers, and instead their registers must be accessed trough IOSF | |
33 | * sideband. VLV has one such PHY for driving ports B and C, and CHV | |
34 | * adds another PHY for driving port D. Each PHY responds to specific | |
35 | * IOSF-SB port. | |
36 | * | |
37 | * Each display PHY is made up of one or two channels. Each channel | |
38 | * houses a common lane part which contains the PLL and other common | |
39 | * logic. CH0 common lane also contains the IOSF-SB logic for the | |
40 | * Common Register Interface (CRI) ie. the DPIO registers. CRI clock | |
41 | * must be running when any DPIO registers are accessed. | |
42 | * | |
43 | * In addition to having their own registers, the PHYs are also | |
44 | * controlled through some dedicated signals from the display | |
45 | * controller. These include PLL reference clock enable, PLL enable, | |
46 | * and CRI clock selection, for example. | |
47 | * | |
48 | * Eeach channel also has two splines (also called data lanes), and | |
49 | * each spline is made up of one Physical Access Coding Sub-Layer | |
50 | * (PCS) block and two TX lanes. So each channel has two PCS blocks | |
51 | * and four TX lanes. The TX lanes are used as DP lanes or TMDS | |
52 | * data/clock pairs depending on the output type. | |
53 | * | |
54 | * Additionally the PHY also contains an AUX lane with AUX blocks | |
55 | * for each channel. This is used for DP AUX communication, but | |
56 | * this fact isn't really relevant for the driver since AUX is | |
57 | * controlled from the display controller side. No DPIO registers | |
58 | * need to be accessed during AUX communication, | |
59 | * | |
60 | * Generally on VLV/CHV the common lane corresponds to the pipe and | |
61 | * the spline (PCS/TX) corresponds to the port. | |
62 | * | |
63 | * For dual channel PHY (VLV/CHV): | |
64 | * | |
65 | * pipe A == CMN/PLL/REF CH0 | |
66 | * | |
67 | * pipe B == CMN/PLL/REF CH1 | |
68 | * | |
69 | * port B == PCS/TX CH0 | |
70 | * | |
71 | * port C == PCS/TX CH1 | |
72 | * | |
73 | * This is especially important when we cross the streams | |
74 | * ie. drive port B with pipe B, or port C with pipe A. | |
75 | * | |
76 | * For single channel PHY (CHV): | |
77 | * | |
78 | * pipe C == CMN/PLL/REF CH0 | |
79 | * | |
80 | * port D == PCS/TX CH0 | |
81 | * | |
82 | * On BXT the entire PHY channel corresponds to the port. That means | |
83 | * the PLL is also now associated with the port rather than the pipe, | |
84 | * and so the clock needs to be routed to the appropriate transcoder. | |
85 | * Port A PLL is directly connected to transcoder EDP and port B/C | |
86 | * PLLs can be routed to any transcoder A/B/C. | |
87 | * | |
88 | * Note: DDI0 is digital port B, DD1 is digital port C, and DDI2 is | |
89 | * digital port D (CHV) or port A (BXT). :: | |
90 | * | |
91 | * | |
92 | * Dual channel PHY (VLV/CHV/BXT) | |
93 | * --------------------------------- | |
94 | * | CH0 | CH1 | | |
95 | * | CMN/PLL/REF | CMN/PLL/REF | | |
96 | * |---------------|---------------| Display PHY | |
97 | * | PCS01 | PCS23 | PCS01 | PCS23 | | |
98 | * |-------|-------|-------|-------| | |
99 | * |TX0|TX1|TX2|TX3|TX0|TX1|TX2|TX3| | |
100 | * --------------------------------- | |
101 | * | DDI0 | DDI1 | DP/HDMI ports | |
102 | * --------------------------------- | |
103 | * | |
104 | * Single channel PHY (CHV/BXT) | |
105 | * ----------------- | |
106 | * | CH0 | | |
107 | * | CMN/PLL/REF | | |
108 | * |---------------| Display PHY | |
109 | * | PCS01 | PCS23 | | |
110 | * |-------|-------| | |
111 | * |TX0|TX1|TX2|TX3| | |
112 | * ----------------- | |
113 | * | DDI2 | DP/HDMI port | |
114 | * ----------------- | |
115 | */ | |
116 | ||
842d4166 ACO |
117 | /** |
118 | * struct bxt_ddi_phy_info - Hold info for a broxton DDI phy | |
119 | */ | |
120 | struct bxt_ddi_phy_info { | |
121 | /** | |
122 | * @dual_channel: true if this phy has a second channel. | |
123 | */ | |
124 | bool dual_channel; | |
125 | ||
e7583f7b ACO |
126 | /** |
127 | * @rcomp_phy: If -1, indicates this phy has its own rcomp resistor. | |
128 | * Otherwise the GRC value will be copied from the phy indicated by | |
129 | * this field. | |
130 | */ | |
131 | enum dpio_phy rcomp_phy; | |
132 | ||
842d4166 ACO |
133 | /** |
134 | * @channel: struct containing per channel information. | |
135 | */ | |
136 | struct { | |
137 | /** | |
138 | * @port: which port maps to this channel. | |
139 | */ | |
140 | enum port port; | |
141 | } channel[2]; | |
142 | }; | |
143 | ||
144 | static const struct bxt_ddi_phy_info bxt_ddi_phy_info[] = { | |
145 | [DPIO_PHY0] = { | |
146 | .dual_channel = true, | |
e7583f7b | 147 | .rcomp_phy = DPIO_PHY1, |
842d4166 ACO |
148 | |
149 | .channel = { | |
150 | [DPIO_CH0] = { .port = PORT_B }, | |
151 | [DPIO_CH1] = { .port = PORT_C }, | |
152 | } | |
153 | }, | |
154 | [DPIO_PHY1] = { | |
155 | .dual_channel = false, | |
e7583f7b | 156 | .rcomp_phy = -1, |
842d4166 ACO |
157 | |
158 | .channel = { | |
159 | [DPIO_CH0] = { .port = PORT_A }, | |
160 | } | |
161 | }, | |
162 | }; | |
163 | ||
164 | static u32 bxt_phy_port_mask(const struct bxt_ddi_phy_info *phy_info) | |
165 | { | |
166 | return (phy_info->dual_channel * BIT(phy_info->channel[DPIO_CH1].port)) | | |
167 | BIT(phy_info->channel[DPIO_CH0].port); | |
168 | } | |
169 | ||
ed37892e ACO |
170 | void bxt_port_to_phy_channel(enum port port, |
171 | enum dpio_phy *phy, enum dpio_channel *ch) | |
172 | { | |
173 | const struct bxt_ddi_phy_info *phy_info; | |
174 | int i; | |
175 | ||
176 | for (i = 0; i < ARRAY_SIZE(bxt_ddi_phy_info); i++) { | |
177 | phy_info = &bxt_ddi_phy_info[i]; | |
178 | ||
179 | if (port == phy_info->channel[DPIO_CH0].port) { | |
180 | *phy = i; | |
181 | *ch = DPIO_CH0; | |
182 | return; | |
183 | } | |
184 | ||
185 | if (phy_info->dual_channel && | |
186 | port == phy_info->channel[DPIO_CH1].port) { | |
187 | *phy = i; | |
188 | *ch = DPIO_CH1; | |
189 | return; | |
190 | } | |
191 | } | |
192 | ||
193 | WARN(1, "PHY not found for PORT %c", port_name(port)); | |
194 | *phy = DPIO_PHY0; | |
195 | *ch = DPIO_CH0; | |
196 | } | |
197 | ||
b6e08203 ACO |
198 | void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv, |
199 | enum port port, u32 margin, u32 scale, | |
200 | u32 enable, u32 deemphasis) | |
201 | { | |
202 | u32 val; | |
ed37892e ACO |
203 | enum dpio_phy phy; |
204 | enum dpio_channel ch; | |
205 | ||
206 | bxt_port_to_phy_channel(port, &phy, &ch); | |
b6e08203 ACO |
207 | |
208 | /* | |
209 | * While we write to the group register to program all lanes at once we | |
210 | * can read only lane registers and we pick lanes 0/1 for that. | |
211 | */ | |
ed37892e | 212 | val = I915_READ(BXT_PORT_PCS_DW10_LN01(phy, ch)); |
b6e08203 | 213 | val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT); |
ed37892e | 214 | I915_WRITE(BXT_PORT_PCS_DW10_GRP(phy, ch), val); |
b6e08203 | 215 | |
ed37892e | 216 | val = I915_READ(BXT_PORT_TX_DW2_LN0(phy, ch)); |
b6e08203 ACO |
217 | val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE); |
218 | val |= margin << MARGIN_000_SHIFT | scale << UNIQ_TRANS_SCALE_SHIFT; | |
ed37892e | 219 | I915_WRITE(BXT_PORT_TX_DW2_GRP(phy, ch), val); |
b6e08203 | 220 | |
ed37892e | 221 | val = I915_READ(BXT_PORT_TX_DW3_LN0(phy, ch)); |
b6e08203 ACO |
222 | val &= ~SCALE_DCOMP_METHOD; |
223 | if (enable) | |
224 | val |= SCALE_DCOMP_METHOD; | |
225 | ||
226 | if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD)) | |
227 | DRM_ERROR("Disabled scaling while ouniqetrangenmethod was set"); | |
228 | ||
ed37892e | 229 | I915_WRITE(BXT_PORT_TX_DW3_GRP(phy, ch), val); |
b6e08203 | 230 | |
ed37892e | 231 | val = I915_READ(BXT_PORT_TX_DW4_LN0(phy, ch)); |
b6e08203 ACO |
232 | val &= ~DE_EMPHASIS; |
233 | val |= deemphasis << DEEMPH_SHIFT; | |
ed37892e | 234 | I915_WRITE(BXT_PORT_TX_DW4_GRP(phy, ch), val); |
b6e08203 | 235 | |
ed37892e | 236 | val = I915_READ(BXT_PORT_PCS_DW10_LN01(phy, ch)); |
b6e08203 | 237 | val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT; |
ed37892e | 238 | I915_WRITE(BXT_PORT_PCS_DW10_GRP(phy, ch), val); |
b6e08203 ACO |
239 | } |
240 | ||
47a6bc61 ACO |
241 | bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv, |
242 | enum dpio_phy phy) | |
243 | { | |
842d4166 | 244 | const struct bxt_ddi_phy_info *phy_info = &bxt_ddi_phy_info[phy]; |
47a6bc61 ACO |
245 | enum port port; |
246 | ||
247 | if (!(I915_READ(BXT_P_CR_GT_DISP_PWRON) & GT_DISPLAY_POWER_ON(phy))) | |
248 | return false; | |
249 | ||
250 | if ((I915_READ(BXT_PORT_CL1CM_DW0(phy)) & | |
251 | (PHY_POWER_GOOD | PHY_RESERVED)) != PHY_POWER_GOOD) { | |
252 | DRM_DEBUG_DRIVER("DDI PHY %d powered, but power hasn't settled\n", | |
253 | phy); | |
254 | ||
255 | return false; | |
256 | } | |
257 | ||
e7583f7b ACO |
258 | if (phy_info->rcomp_phy == -1 && |
259 | !(I915_READ(BXT_PORT_REF_DW3(phy)) & GRC_DONE)) { | |
260 | DRM_DEBUG_DRIVER("DDI PHY %d powered, but GRC isn't done\n", | |
261 | phy); | |
47a6bc61 ACO |
262 | |
263 | return false; | |
264 | } | |
265 | ||
266 | if (!(I915_READ(BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) { | |
267 | DRM_DEBUG_DRIVER("DDI PHY %d powered, but still in reset\n", | |
268 | phy); | |
269 | ||
270 | return false; | |
271 | } | |
272 | ||
842d4166 | 273 | for_each_port_masked(port, bxt_phy_port_mask(phy_info)) { |
47a6bc61 ACO |
274 | u32 tmp = I915_READ(BXT_PHY_CTL(port)); |
275 | ||
276 | if (tmp & BXT_PHY_CMNLANE_POWERDOWN_ACK) { | |
277 | DRM_DEBUG_DRIVER("DDI PHY %d powered, but common lane " | |
278 | "for port %c powered down " | |
279 | "(PHY_CTL %08x)\n", | |
280 | phy, port_name(port), tmp); | |
281 | ||
282 | return false; | |
283 | } | |
284 | } | |
285 | ||
286 | return true; | |
287 | } | |
288 | ||
289 | static u32 bxt_get_grc(struct drm_i915_private *dev_priv, enum dpio_phy phy) | |
290 | { | |
291 | u32 val = I915_READ(BXT_PORT_REF_DW6(phy)); | |
292 | ||
293 | return (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT; | |
294 | } | |
295 | ||
296 | static void bxt_phy_wait_grc_done(struct drm_i915_private *dev_priv, | |
297 | enum dpio_phy phy) | |
298 | { | |
299 | if (intel_wait_for_register(dev_priv, | |
300 | BXT_PORT_REF_DW3(phy), | |
301 | GRC_DONE, GRC_DONE, | |
302 | 10)) | |
303 | DRM_ERROR("timeout waiting for PHY%d GRC\n", phy); | |
304 | } | |
305 | ||
e7583f7b ACO |
306 | static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv, |
307 | enum dpio_phy phy) | |
47a6bc61 | 308 | { |
842d4166 | 309 | const struct bxt_ddi_phy_info *phy_info = &bxt_ddi_phy_info[phy]; |
47a6bc61 ACO |
310 | u32 val; |
311 | ||
312 | if (bxt_ddi_phy_is_enabled(dev_priv, phy)) { | |
313 | /* Still read out the GRC value for state verification */ | |
e7583f7b | 314 | if (phy_info->rcomp_phy != -1) |
47a6bc61 ACO |
315 | dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, phy); |
316 | ||
317 | if (bxt_ddi_phy_verify_state(dev_priv, phy)) { | |
318 | DRM_DEBUG_DRIVER("DDI PHY %d already enabled, " | |
319 | "won't reprogram it\n", phy); | |
47a6bc61 ACO |
320 | return; |
321 | } | |
322 | ||
323 | DRM_DEBUG_DRIVER("DDI PHY %d enabled with invalid state, " | |
324 | "force reprogramming it\n", phy); | |
325 | } | |
326 | ||
327 | val = I915_READ(BXT_P_CR_GT_DISP_PWRON); | |
328 | val |= GT_DISPLAY_POWER_ON(phy); | |
329 | I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val); | |
330 | ||
331 | /* | |
332 | * The PHY registers start out inaccessible and respond to reads with | |
333 | * all 1s. Eventually they become accessible as they power up, then | |
334 | * the reserved bit will give the default 0. Poll on the reserved bit | |
335 | * becoming 0 to find when the PHY is accessible. | |
336 | * HW team confirmed that the time to reach phypowergood status is | |
337 | * anywhere between 50 us and 100us. | |
338 | */ | |
339 | if (wait_for_us(((I915_READ(BXT_PORT_CL1CM_DW0(phy)) & | |
340 | (PHY_RESERVED | PHY_POWER_GOOD)) == PHY_POWER_GOOD), 100)) { | |
341 | DRM_ERROR("timeout during PHY%d power on\n", phy); | |
342 | } | |
343 | ||
344 | /* Program PLL Rcomp code offset */ | |
345 | val = I915_READ(BXT_PORT_CL1CM_DW9(phy)); | |
346 | val &= ~IREF0RC_OFFSET_MASK; | |
347 | val |= 0xE4 << IREF0RC_OFFSET_SHIFT; | |
348 | I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val); | |
349 | ||
350 | val = I915_READ(BXT_PORT_CL1CM_DW10(phy)); | |
351 | val &= ~IREF1RC_OFFSET_MASK; | |
352 | val |= 0xE4 << IREF1RC_OFFSET_SHIFT; | |
353 | I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val); | |
354 | ||
355 | /* Program power gating */ | |
356 | val = I915_READ(BXT_PORT_CL1CM_DW28(phy)); | |
357 | val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | | |
358 | SUS_CLK_CONFIG; | |
359 | I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val); | |
360 | ||
842d4166 ACO |
361 | if (phy_info->dual_channel) { |
362 | val = I915_READ(BXT_PORT_CL2CM_DW6(phy)); | |
47a6bc61 | 363 | val |= DW6_OLDO_DYN_PWR_DOWN_EN; |
842d4166 | 364 | I915_WRITE(BXT_PORT_CL2CM_DW6(phy), val); |
47a6bc61 ACO |
365 | } |
366 | ||
e7583f7b | 367 | if (phy_info->rcomp_phy != -1) { |
47a6bc61 ACO |
368 | uint32_t grc_code; |
369 | /* | |
370 | * PHY0 isn't connected to an RCOMP resistor so copy over | |
371 | * the corresponding calibrated value from PHY1, and disable | |
372 | * the automatic calibration on PHY0. | |
373 | */ | |
e7583f7b ACO |
374 | val = dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, |
375 | phy_info->rcomp_phy); | |
47a6bc61 ACO |
376 | grc_code = val << GRC_CODE_FAST_SHIFT | |
377 | val << GRC_CODE_SLOW_SHIFT | | |
378 | val; | |
e7583f7b | 379 | I915_WRITE(BXT_PORT_REF_DW6(phy), grc_code); |
47a6bc61 | 380 | |
e7583f7b | 381 | val = I915_READ(BXT_PORT_REF_DW8(phy)); |
47a6bc61 | 382 | val |= GRC_DIS | GRC_RDY_OVRD; |
e7583f7b | 383 | I915_WRITE(BXT_PORT_REF_DW8(phy), val); |
47a6bc61 ACO |
384 | } |
385 | ||
386 | val = I915_READ(BXT_PHY_CTL_FAMILY(phy)); | |
387 | val |= COMMON_RESET_DIS; | |
388 | I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val); | |
389 | ||
e7583f7b ACO |
390 | if (phy_info->rcomp_phy == -1) |
391 | bxt_phy_wait_grc_done(dev_priv, phy); | |
392 | ||
47a6bc61 ACO |
393 | } |
394 | ||
395 | void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy) | |
396 | { | |
397 | uint32_t val; | |
398 | ||
399 | val = I915_READ(BXT_PHY_CTL_FAMILY(phy)); | |
400 | val &= ~COMMON_RESET_DIS; | |
401 | I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val); | |
402 | ||
403 | val = I915_READ(BXT_P_CR_GT_DISP_PWRON); | |
404 | val &= ~GT_DISPLAY_POWER_ON(phy); | |
405 | I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val); | |
406 | } | |
407 | ||
e7583f7b ACO |
408 | void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy) |
409 | { | |
410 | const struct bxt_ddi_phy_info *phy_info = &bxt_ddi_phy_info[phy]; | |
411 | enum dpio_phy rcomp_phy = phy_info->rcomp_phy; | |
412 | bool was_enabled; | |
413 | ||
414 | lockdep_assert_held(&dev_priv->power_domains.lock); | |
415 | ||
416 | if (rcomp_phy != -1) { | |
417 | was_enabled = bxt_ddi_phy_is_enabled(dev_priv, rcomp_phy); | |
418 | ||
419 | /* | |
420 | * We need to copy the GRC calibration value from rcomp_phy, | |
421 | * so make sure it's powered up. | |
422 | */ | |
423 | if (!was_enabled) | |
424 | _bxt_ddi_phy_init(dev_priv, rcomp_phy); | |
425 | } | |
426 | ||
427 | _bxt_ddi_phy_init(dev_priv, phy); | |
428 | ||
429 | if (rcomp_phy != -1 && !was_enabled) | |
430 | bxt_ddi_phy_uninit(dev_priv, phy_info->rcomp_phy); | |
431 | } | |
432 | ||
47a6bc61 ACO |
433 | static bool __printf(6, 7) |
434 | __phy_reg_verify_state(struct drm_i915_private *dev_priv, enum dpio_phy phy, | |
435 | i915_reg_t reg, u32 mask, u32 expected, | |
436 | const char *reg_fmt, ...) | |
437 | { | |
438 | struct va_format vaf; | |
439 | va_list args; | |
440 | u32 val; | |
441 | ||
442 | val = I915_READ(reg); | |
443 | if ((val & mask) == expected) | |
444 | return true; | |
445 | ||
446 | va_start(args, reg_fmt); | |
447 | vaf.fmt = reg_fmt; | |
448 | vaf.va = &args; | |
449 | ||
450 | DRM_DEBUG_DRIVER("DDI PHY %d reg %pV [%08x] state mismatch: " | |
451 | "current %08x, expected %08x (mask %08x)\n", | |
452 | phy, &vaf, reg.reg, val, (val & ~mask) | expected, | |
453 | mask); | |
454 | ||
455 | va_end(args); | |
456 | ||
457 | return false; | |
458 | } | |
459 | ||
460 | bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv, | |
461 | enum dpio_phy phy) | |
462 | { | |
842d4166 | 463 | const struct bxt_ddi_phy_info *phy_info = &bxt_ddi_phy_info[phy]; |
47a6bc61 ACO |
464 | uint32_t mask; |
465 | bool ok; | |
466 | ||
467 | #define _CHK(reg, mask, exp, fmt, ...) \ | |
468 | __phy_reg_verify_state(dev_priv, phy, reg, mask, exp, fmt, \ | |
469 | ## __VA_ARGS__) | |
470 | ||
471 | if (!bxt_ddi_phy_is_enabled(dev_priv, phy)) | |
472 | return false; | |
473 | ||
474 | ok = true; | |
475 | ||
476 | /* PLL Rcomp code offset */ | |
477 | ok &= _CHK(BXT_PORT_CL1CM_DW9(phy), | |
478 | IREF0RC_OFFSET_MASK, 0xe4 << IREF0RC_OFFSET_SHIFT, | |
479 | "BXT_PORT_CL1CM_DW9(%d)", phy); | |
480 | ok &= _CHK(BXT_PORT_CL1CM_DW10(phy), | |
481 | IREF1RC_OFFSET_MASK, 0xe4 << IREF1RC_OFFSET_SHIFT, | |
482 | "BXT_PORT_CL1CM_DW10(%d)", phy); | |
483 | ||
484 | /* Power gating */ | |
485 | mask = OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | SUS_CLK_CONFIG; | |
486 | ok &= _CHK(BXT_PORT_CL1CM_DW28(phy), mask, mask, | |
487 | "BXT_PORT_CL1CM_DW28(%d)", phy); | |
488 | ||
842d4166 ACO |
489 | if (phy_info->dual_channel) |
490 | ok &= _CHK(BXT_PORT_CL2CM_DW6(phy), | |
47a6bc61 | 491 | DW6_OLDO_DYN_PWR_DOWN_EN, DW6_OLDO_DYN_PWR_DOWN_EN, |
842d4166 | 492 | "BXT_PORT_CL2CM_DW6(%d)", phy); |
47a6bc61 | 493 | |
e7583f7b | 494 | if (phy_info->rcomp_phy != -1) { |
47a6bc61 ACO |
495 | u32 grc_code = dev_priv->bxt_phy_grc; |
496 | ||
497 | grc_code = grc_code << GRC_CODE_FAST_SHIFT | | |
498 | grc_code << GRC_CODE_SLOW_SHIFT | | |
499 | grc_code; | |
500 | mask = GRC_CODE_FAST_MASK | GRC_CODE_SLOW_MASK | | |
501 | GRC_CODE_NOM_MASK; | |
e7583f7b | 502 | ok &= _CHK(BXT_PORT_REF_DW6(phy), mask, grc_code, |
ed37892e | 503 | "BXT_PORT_REF_DW6(%d)", phy); |
47a6bc61 ACO |
504 | |
505 | mask = GRC_DIS | GRC_RDY_OVRD; | |
e7583f7b ACO |
506 | ok &= _CHK(BXT_PORT_REF_DW8(phy), mask, mask, |
507 | "BXT_PORT_REF_DW8(%d)", phy); | |
47a6bc61 ACO |
508 | } |
509 | ||
510 | return ok; | |
511 | #undef _CHK | |
512 | } | |
513 | ||
514 | uint8_t | |
515 | bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder *encoder, | |
516 | uint8_t lane_count) | |
517 | { | |
518 | switch (lane_count) { | |
519 | case 1: | |
520 | return 0; | |
521 | case 2: | |
522 | return BIT(2) | BIT(0); | |
523 | case 4: | |
524 | return BIT(3) | BIT(2) | BIT(0); | |
525 | default: | |
526 | MISSING_CASE(lane_count); | |
527 | ||
528 | return 0; | |
529 | } | |
530 | } | |
531 | ||
532 | void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder, | |
533 | uint8_t lane_lat_optim_mask) | |
534 | { | |
535 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
536 | struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev); | |
537 | enum port port = dport->port; | |
ed37892e ACO |
538 | enum dpio_phy phy; |
539 | enum dpio_channel ch; | |
47a6bc61 ACO |
540 | int lane; |
541 | ||
ed37892e ACO |
542 | bxt_port_to_phy_channel(port, &phy, &ch); |
543 | ||
47a6bc61 | 544 | for (lane = 0; lane < 4; lane++) { |
ed37892e | 545 | u32 val = I915_READ(BXT_PORT_TX_DW14_LN(phy, ch, lane)); |
47a6bc61 ACO |
546 | |
547 | /* | |
548 | * Note that on CHV this flag is called UPAR, but has | |
549 | * the same function. | |
550 | */ | |
551 | val &= ~LATENCY_OPTIM; | |
552 | if (lane_lat_optim_mask & BIT(lane)) | |
553 | val |= LATENCY_OPTIM; | |
554 | ||
ed37892e | 555 | I915_WRITE(BXT_PORT_TX_DW14_LN(phy, ch, lane), val); |
47a6bc61 ACO |
556 | } |
557 | } | |
558 | ||
559 | uint8_t | |
560 | bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder) | |
561 | { | |
562 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
563 | struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev); | |
564 | enum port port = dport->port; | |
ed37892e ACO |
565 | enum dpio_phy phy; |
566 | enum dpio_channel ch; | |
47a6bc61 ACO |
567 | int lane; |
568 | uint8_t mask; | |
569 | ||
ed37892e ACO |
570 | bxt_port_to_phy_channel(port, &phy, &ch); |
571 | ||
47a6bc61 ACO |
572 | mask = 0; |
573 | for (lane = 0; lane < 4; lane++) { | |
ed37892e | 574 | u32 val = I915_READ(BXT_PORT_TX_DW14_LN(phy, ch, lane)); |
47a6bc61 ACO |
575 | |
576 | if (val & LATENCY_OPTIM) | |
577 | mask |= BIT(lane); | |
578 | } | |
579 | ||
580 | return mask; | |
581 | } | |
582 | ||
583 | ||
b7fa22d8 ACO |
584 | void chv_set_phy_signal_level(struct intel_encoder *encoder, |
585 | u32 deemph_reg_value, u32 margin_reg_value, | |
586 | bool uniq_trans_scale) | |
587 | { | |
588 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
589 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
590 | struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc); | |
591 | enum dpio_channel ch = vlv_dport_to_channel(dport); | |
592 | enum pipe pipe = intel_crtc->pipe; | |
593 | u32 val; | |
594 | int i; | |
595 | ||
596 | mutex_lock(&dev_priv->sb_lock); | |
597 | ||
598 | /* Clear calc init */ | |
599 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); | |
600 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); | |
601 | val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); | |
602 | val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; | |
603 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); | |
604 | ||
605 | if (intel_crtc->config->lane_count > 2) { | |
606 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); | |
607 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); | |
608 | val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); | |
609 | val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; | |
610 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); | |
611 | } | |
612 | ||
613 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch)); | |
614 | val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); | |
615 | val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; | |
616 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val); | |
617 | ||
618 | if (intel_crtc->config->lane_count > 2) { | |
619 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch)); | |
620 | val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); | |
621 | val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; | |
622 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val); | |
623 | } | |
624 | ||
625 | /* Program swing deemph */ | |
626 | for (i = 0; i < intel_crtc->config->lane_count; i++) { | |
627 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i)); | |
628 | val &= ~DPIO_SWING_DEEMPH9P5_MASK; | |
629 | val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT; | |
630 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val); | |
631 | } | |
632 | ||
633 | /* Program swing margin */ | |
634 | for (i = 0; i < intel_crtc->config->lane_count; i++) { | |
635 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); | |
636 | ||
637 | val &= ~DPIO_SWING_MARGIN000_MASK; | |
638 | val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT; | |
639 | ||
640 | /* | |
641 | * Supposedly this value shouldn't matter when unique transition | |
642 | * scale is disabled, but in fact it does matter. Let's just | |
643 | * always program the same value and hope it's OK. | |
644 | */ | |
645 | val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT); | |
646 | val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT; | |
647 | ||
648 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); | |
649 | } | |
650 | ||
651 | /* | |
652 | * The document said it needs to set bit 27 for ch0 and bit 26 | |
653 | * for ch1. Might be a typo in the doc. | |
654 | * For now, for this unique transition scale selection, set bit | |
655 | * 27 for ch0 and ch1. | |
656 | */ | |
657 | for (i = 0; i < intel_crtc->config->lane_count; i++) { | |
658 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); | |
659 | if (uniq_trans_scale) | |
660 | val |= DPIO_TX_UNIQ_TRANS_SCALE_EN; | |
661 | else | |
662 | val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN; | |
663 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); | |
664 | } | |
665 | ||
666 | /* Start swing calculation */ | |
667 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); | |
668 | val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; | |
669 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); | |
670 | ||
671 | if (intel_crtc->config->lane_count > 2) { | |
672 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); | |
673 | val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; | |
674 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); | |
675 | } | |
676 | ||
677 | mutex_unlock(&dev_priv->sb_lock); | |
678 | ||
679 | } | |
680 | ||
844b2f9a ACO |
681 | void chv_data_lane_soft_reset(struct intel_encoder *encoder, |
682 | bool reset) | |
683 | { | |
684 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
685 | enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base)); | |
686 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); | |
687 | enum pipe pipe = crtc->pipe; | |
688 | uint32_t val; | |
689 | ||
690 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); | |
691 | if (reset) | |
692 | val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); | |
693 | else | |
694 | val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET; | |
695 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); | |
696 | ||
697 | if (crtc->config->lane_count > 2) { | |
698 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); | |
699 | if (reset) | |
700 | val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); | |
701 | else | |
702 | val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET; | |
703 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); | |
704 | } | |
705 | ||
706 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); | |
707 | val |= CHV_PCS_REQ_SOFTRESET_EN; | |
708 | if (reset) | |
709 | val &= ~DPIO_PCS_CLK_SOFT_RESET; | |
710 | else | |
711 | val |= DPIO_PCS_CLK_SOFT_RESET; | |
712 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); | |
713 | ||
714 | if (crtc->config->lane_count > 2) { | |
715 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); | |
716 | val |= CHV_PCS_REQ_SOFTRESET_EN; | |
717 | if (reset) | |
718 | val &= ~DPIO_PCS_CLK_SOFT_RESET; | |
719 | else | |
720 | val |= DPIO_PCS_CLK_SOFT_RESET; | |
721 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); | |
722 | } | |
723 | } | |
419b1b7a ACO |
724 | |
725 | void chv_phy_pre_pll_enable(struct intel_encoder *encoder) | |
726 | { | |
727 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
728 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 729 | struct drm_i915_private *dev_priv = to_i915(dev); |
419b1b7a ACO |
730 | struct intel_crtc *intel_crtc = |
731 | to_intel_crtc(encoder->base.crtc); | |
732 | enum dpio_channel ch = vlv_dport_to_channel(dport); | |
733 | enum pipe pipe = intel_crtc->pipe; | |
734 | unsigned int lane_mask = | |
735 | intel_dp_unused_lane_mask(intel_crtc->config->lane_count); | |
736 | u32 val; | |
737 | ||
738 | /* | |
739 | * Must trick the second common lane into life. | |
740 | * Otherwise we can't even access the PLL. | |
741 | */ | |
742 | if (ch == DPIO_CH0 && pipe == PIPE_B) | |
743 | dport->release_cl2_override = | |
744 | !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true); | |
745 | ||
746 | chv_phy_powergate_lanes(encoder, true, lane_mask); | |
747 | ||
748 | mutex_lock(&dev_priv->sb_lock); | |
749 | ||
750 | /* Assert data lane reset */ | |
751 | chv_data_lane_soft_reset(encoder, true); | |
752 | ||
753 | /* program left/right clock distribution */ | |
754 | if (pipe != PIPE_B) { | |
755 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); | |
756 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); | |
757 | if (ch == DPIO_CH0) | |
758 | val |= CHV_BUFLEFTENA1_FORCE; | |
759 | if (ch == DPIO_CH1) | |
760 | val |= CHV_BUFRIGHTENA1_FORCE; | |
761 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); | |
762 | } else { | |
763 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); | |
764 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); | |
765 | if (ch == DPIO_CH0) | |
766 | val |= CHV_BUFLEFTENA2_FORCE; | |
767 | if (ch == DPIO_CH1) | |
768 | val |= CHV_BUFRIGHTENA2_FORCE; | |
769 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); | |
770 | } | |
771 | ||
772 | /* program clock channel usage */ | |
773 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch)); | |
774 | val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; | |
775 | if (pipe != PIPE_B) | |
776 | val &= ~CHV_PCS_USEDCLKCHANNEL; | |
777 | else | |
778 | val |= CHV_PCS_USEDCLKCHANNEL; | |
779 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val); | |
780 | ||
781 | if (intel_crtc->config->lane_count > 2) { | |
782 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch)); | |
783 | val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; | |
784 | if (pipe != PIPE_B) | |
785 | val &= ~CHV_PCS_USEDCLKCHANNEL; | |
786 | else | |
787 | val |= CHV_PCS_USEDCLKCHANNEL; | |
788 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val); | |
789 | } | |
790 | ||
791 | /* | |
792 | * This a a bit weird since generally CL | |
793 | * matches the pipe, but here we need to | |
794 | * pick the CL based on the port. | |
795 | */ | |
796 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch)); | |
797 | if (pipe != PIPE_B) | |
798 | val &= ~CHV_CMN_USEDCLKCHANNEL; | |
799 | else | |
800 | val |= CHV_CMN_USEDCLKCHANNEL; | |
801 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val); | |
802 | ||
803 | mutex_unlock(&dev_priv->sb_lock); | |
804 | } | |
e7d2a717 ACO |
805 | |
806 | void chv_phy_pre_encoder_enable(struct intel_encoder *encoder) | |
807 | { | |
808 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
809 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); | |
810 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 811 | struct drm_i915_private *dev_priv = to_i915(dev); |
e7d2a717 ACO |
812 | struct intel_crtc *intel_crtc = |
813 | to_intel_crtc(encoder->base.crtc); | |
814 | enum dpio_channel ch = vlv_dport_to_channel(dport); | |
815 | int pipe = intel_crtc->pipe; | |
816 | int data, i, stagger; | |
817 | u32 val; | |
818 | ||
819 | mutex_lock(&dev_priv->sb_lock); | |
820 | ||
821 | /* allow hardware to manage TX FIFO reset source */ | |
822 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); | |
823 | val &= ~DPIO_LANEDESKEW_STRAP_OVRD; | |
824 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); | |
825 | ||
826 | if (intel_crtc->config->lane_count > 2) { | |
827 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); | |
828 | val &= ~DPIO_LANEDESKEW_STRAP_OVRD; | |
829 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); | |
830 | } | |
831 | ||
832 | /* Program Tx lane latency optimal setting*/ | |
833 | for (i = 0; i < intel_crtc->config->lane_count; i++) { | |
834 | /* Set the upar bit */ | |
835 | if (intel_crtc->config->lane_count == 1) | |
836 | data = 0x0; | |
837 | else | |
838 | data = (i == 1) ? 0x0 : 0x1; | |
839 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i), | |
840 | data << DPIO_UPAR_SHIFT); | |
841 | } | |
842 | ||
843 | /* Data lane stagger programming */ | |
844 | if (intel_crtc->config->port_clock > 270000) | |
845 | stagger = 0x18; | |
846 | else if (intel_crtc->config->port_clock > 135000) | |
847 | stagger = 0xd; | |
848 | else if (intel_crtc->config->port_clock > 67500) | |
849 | stagger = 0x7; | |
850 | else if (intel_crtc->config->port_clock > 33750) | |
851 | stagger = 0x4; | |
852 | else | |
853 | stagger = 0x2; | |
854 | ||
855 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); | |
856 | val |= DPIO_TX2_STAGGER_MASK(0x1f); | |
857 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); | |
858 | ||
859 | if (intel_crtc->config->lane_count > 2) { | |
860 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); | |
861 | val |= DPIO_TX2_STAGGER_MASK(0x1f); | |
862 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); | |
863 | } | |
864 | ||
865 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch), | |
866 | DPIO_LANESTAGGER_STRAP(stagger) | | |
867 | DPIO_LANESTAGGER_STRAP_OVRD | | |
868 | DPIO_TX1_STAGGER_MASK(0x1f) | | |
869 | DPIO_TX1_STAGGER_MULT(6) | | |
870 | DPIO_TX2_STAGGER_MULT(0)); | |
871 | ||
872 | if (intel_crtc->config->lane_count > 2) { | |
873 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch), | |
874 | DPIO_LANESTAGGER_STRAP(stagger) | | |
875 | DPIO_LANESTAGGER_STRAP_OVRD | | |
876 | DPIO_TX1_STAGGER_MASK(0x1f) | | |
877 | DPIO_TX1_STAGGER_MULT(7) | | |
878 | DPIO_TX2_STAGGER_MULT(5)); | |
879 | } | |
880 | ||
881 | /* Deassert data lane reset */ | |
882 | chv_data_lane_soft_reset(encoder, false); | |
883 | ||
884 | mutex_unlock(&dev_priv->sb_lock); | |
885 | } | |
886 | ||
887 | void chv_phy_release_cl2_override(struct intel_encoder *encoder) | |
888 | { | |
889 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
890 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
891 | ||
892 | if (dport->release_cl2_override) { | |
893 | chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false); | |
894 | dport->release_cl2_override = false; | |
895 | } | |
896 | } | |
204970b5 ACO |
897 | |
898 | void chv_phy_post_pll_disable(struct intel_encoder *encoder) | |
899 | { | |
900 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
901 | enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe; | |
902 | u32 val; | |
903 | ||
904 | mutex_lock(&dev_priv->sb_lock); | |
905 | ||
906 | /* disable left/right clock distribution */ | |
907 | if (pipe != PIPE_B) { | |
908 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); | |
909 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); | |
910 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); | |
911 | } else { | |
912 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); | |
913 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); | |
914 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); | |
915 | } | |
916 | ||
917 | mutex_unlock(&dev_priv->sb_lock); | |
918 | ||
919 | /* | |
920 | * Leave the power down bit cleared for at least one | |
921 | * lane so that chv_powergate_phy_ch() will power | |
922 | * on something when the channel is otherwise unused. | |
923 | * When the port is off and the override is removed | |
924 | * the lanes power down anyway, so otherwise it doesn't | |
925 | * really matter what the state of power down bits is | |
926 | * after this. | |
927 | */ | |
928 | chv_phy_powergate_lanes(encoder, false, 0x0); | |
929 | } | |
53d98725 ACO |
930 | |
931 | void vlv_set_phy_signal_level(struct intel_encoder *encoder, | |
932 | u32 demph_reg_value, u32 preemph_reg_value, | |
933 | u32 uniqtranscale_reg_value, u32 tx3_demph) | |
934 | { | |
935 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
936 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); | |
937 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
938 | enum dpio_channel port = vlv_dport_to_channel(dport); | |
939 | int pipe = intel_crtc->pipe; | |
940 | ||
941 | mutex_lock(&dev_priv->sb_lock); | |
942 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000); | |
943 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value); | |
944 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), | |
945 | uniqtranscale_reg_value); | |
946 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040); | |
947 | ||
948 | if (tx3_demph) | |
949 | vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), tx3_demph); | |
950 | ||
951 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); | |
952 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value); | |
953 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); | |
954 | mutex_unlock(&dev_priv->sb_lock); | |
955 | } | |
6da2e616 ACO |
956 | |
957 | void vlv_phy_pre_pll_enable(struct intel_encoder *encoder) | |
958 | { | |
959 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
960 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 961 | struct drm_i915_private *dev_priv = to_i915(dev); |
6da2e616 ACO |
962 | struct intel_crtc *intel_crtc = |
963 | to_intel_crtc(encoder->base.crtc); | |
964 | enum dpio_channel port = vlv_dport_to_channel(dport); | |
965 | int pipe = intel_crtc->pipe; | |
966 | ||
967 | /* Program Tx lane resets to default */ | |
968 | mutex_lock(&dev_priv->sb_lock); | |
969 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), | |
970 | DPIO_PCS_TX_LANE2_RESET | | |
971 | DPIO_PCS_TX_LANE1_RESET); | |
972 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), | |
973 | DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | | |
974 | DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | | |
975 | (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) | | |
976 | DPIO_PCS_CLK_SOFT_RESET); | |
977 | ||
978 | /* Fix up inter-pair skew failure */ | |
979 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); | |
980 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); | |
981 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); | |
982 | mutex_unlock(&dev_priv->sb_lock); | |
983 | } | |
5f68c275 ACO |
984 | |
985 | void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder) | |
986 | { | |
987 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
988 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); | |
989 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 990 | struct drm_i915_private *dev_priv = to_i915(dev); |
5f68c275 ACO |
991 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
992 | enum dpio_channel port = vlv_dport_to_channel(dport); | |
993 | int pipe = intel_crtc->pipe; | |
994 | u32 val; | |
995 | ||
996 | mutex_lock(&dev_priv->sb_lock); | |
997 | ||
998 | /* Enable clock channels for this port */ | |
999 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); | |
1000 | val = 0; | |
1001 | if (pipe) | |
1002 | val |= (1<<21); | |
1003 | else | |
1004 | val &= ~(1<<21); | |
1005 | val |= 0x001000c4; | |
1006 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); | |
1007 | ||
1008 | /* Program lane clock */ | |
1009 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); | |
1010 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); | |
1011 | ||
1012 | mutex_unlock(&dev_priv->sb_lock); | |
1013 | } | |
0f572ebe ACO |
1014 | |
1015 | void vlv_phy_reset_lanes(struct intel_encoder *encoder) | |
1016 | { | |
1017 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
fac5e23e | 1018 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
0f572ebe ACO |
1019 | struct intel_crtc *intel_crtc = |
1020 | to_intel_crtc(encoder->base.crtc); | |
1021 | enum dpio_channel port = vlv_dport_to_channel(dport); | |
1022 | int pipe = intel_crtc->pipe; | |
1023 | ||
1024 | mutex_lock(&dev_priv->sb_lock); | |
1025 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000); | |
1026 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060); | |
1027 | mutex_unlock(&dev_priv->sb_lock); | |
1028 | } |