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b7fa22d8 ACO |
1 | /* |
2 | * Copyright © 2014-2016 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | */ | |
23 | ||
24 | #include "intel_drv.h" | |
25 | ||
f38861b8 ACO |
26 | /** |
27 | * DOC: DPIO | |
28 | * | |
29 | * VLV, CHV and BXT have slightly peculiar display PHYs for driving DP/HDMI | |
30 | * ports. DPIO is the name given to such a display PHY. These PHYs | |
31 | * don't follow the standard programming model using direct MMIO | |
32 | * registers, and instead their registers must be accessed trough IOSF | |
33 | * sideband. VLV has one such PHY for driving ports B and C, and CHV | |
34 | * adds another PHY for driving port D. Each PHY responds to specific | |
35 | * IOSF-SB port. | |
36 | * | |
37 | * Each display PHY is made up of one or two channels. Each channel | |
38 | * houses a common lane part which contains the PLL and other common | |
39 | * logic. CH0 common lane also contains the IOSF-SB logic for the | |
40 | * Common Register Interface (CRI) ie. the DPIO registers. CRI clock | |
41 | * must be running when any DPIO registers are accessed. | |
42 | * | |
43 | * In addition to having their own registers, the PHYs are also | |
44 | * controlled through some dedicated signals from the display | |
45 | * controller. These include PLL reference clock enable, PLL enable, | |
46 | * and CRI clock selection, for example. | |
47 | * | |
48 | * Eeach channel also has two splines (also called data lanes), and | |
49 | * each spline is made up of one Physical Access Coding Sub-Layer | |
50 | * (PCS) block and two TX lanes. So each channel has two PCS blocks | |
51 | * and four TX lanes. The TX lanes are used as DP lanes or TMDS | |
52 | * data/clock pairs depending on the output type. | |
53 | * | |
54 | * Additionally the PHY also contains an AUX lane with AUX blocks | |
55 | * for each channel. This is used for DP AUX communication, but | |
56 | * this fact isn't really relevant for the driver since AUX is | |
57 | * controlled from the display controller side. No DPIO registers | |
58 | * need to be accessed during AUX communication, | |
59 | * | |
60 | * Generally on VLV/CHV the common lane corresponds to the pipe and | |
61 | * the spline (PCS/TX) corresponds to the port. | |
62 | * | |
63 | * For dual channel PHY (VLV/CHV): | |
64 | * | |
65 | * pipe A == CMN/PLL/REF CH0 | |
66 | * | |
67 | * pipe B == CMN/PLL/REF CH1 | |
68 | * | |
69 | * port B == PCS/TX CH0 | |
70 | * | |
71 | * port C == PCS/TX CH1 | |
72 | * | |
73 | * This is especially important when we cross the streams | |
74 | * ie. drive port B with pipe B, or port C with pipe A. | |
75 | * | |
76 | * For single channel PHY (CHV): | |
77 | * | |
78 | * pipe C == CMN/PLL/REF CH0 | |
79 | * | |
80 | * port D == PCS/TX CH0 | |
81 | * | |
82 | * On BXT the entire PHY channel corresponds to the port. That means | |
83 | * the PLL is also now associated with the port rather than the pipe, | |
84 | * and so the clock needs to be routed to the appropriate transcoder. | |
85 | * Port A PLL is directly connected to transcoder EDP and port B/C | |
86 | * PLLs can be routed to any transcoder A/B/C. | |
87 | * | |
88 | * Note: DDI0 is digital port B, DD1 is digital port C, and DDI2 is | |
89 | * digital port D (CHV) or port A (BXT). :: | |
90 | * | |
91 | * | |
92 | * Dual channel PHY (VLV/CHV/BXT) | |
93 | * --------------------------------- | |
94 | * | CH0 | CH1 | | |
95 | * | CMN/PLL/REF | CMN/PLL/REF | | |
96 | * |---------------|---------------| Display PHY | |
97 | * | PCS01 | PCS23 | PCS01 | PCS23 | | |
98 | * |-------|-------|-------|-------| | |
99 | * |TX0|TX1|TX2|TX3|TX0|TX1|TX2|TX3| | |
100 | * --------------------------------- | |
101 | * | DDI0 | DDI1 | DP/HDMI ports | |
102 | * --------------------------------- | |
103 | * | |
104 | * Single channel PHY (CHV/BXT) | |
105 | * ----------------- | |
106 | * | CH0 | | |
107 | * | CMN/PLL/REF | | |
108 | * |---------------| Display PHY | |
109 | * | PCS01 | PCS23 | | |
110 | * |-------|-------| | |
111 | * |TX0|TX1|TX2|TX3| | |
112 | * ----------------- | |
113 | * | DDI2 | DP/HDMI port | |
114 | * ----------------- | |
115 | */ | |
116 | ||
842d4166 ACO |
117 | /** |
118 | * struct bxt_ddi_phy_info - Hold info for a broxton DDI phy | |
119 | */ | |
120 | struct bxt_ddi_phy_info { | |
121 | /** | |
122 | * @dual_channel: true if this phy has a second channel. | |
123 | */ | |
124 | bool dual_channel; | |
125 | ||
e7583f7b ACO |
126 | /** |
127 | * @rcomp_phy: If -1, indicates this phy has its own rcomp resistor. | |
128 | * Otherwise the GRC value will be copied from the phy indicated by | |
129 | * this field. | |
130 | */ | |
131 | enum dpio_phy rcomp_phy; | |
132 | ||
0a116ce8 ACO |
133 | /** |
134 | * @reset_delay: delay in us to wait before setting the common reset | |
135 | * bit in BXT_PHY_CTL_FAMILY, which effectively enables the phy. | |
136 | */ | |
137 | int reset_delay; | |
138 | ||
139 | /** | |
140 | * @pwron_mask: Mask with the appropriate bit set that would cause the | |
141 | * punit to power this phy if written to BXT_P_CR_GT_DISP_PWRON. | |
142 | */ | |
143 | u32 pwron_mask; | |
144 | ||
842d4166 ACO |
145 | /** |
146 | * @channel: struct containing per channel information. | |
147 | */ | |
148 | struct { | |
149 | /** | |
41e1bd56 | 150 | * @channel.port: which port maps to this channel. |
842d4166 ACO |
151 | */ |
152 | enum port port; | |
153 | } channel[2]; | |
154 | }; | |
155 | ||
156 | static const struct bxt_ddi_phy_info bxt_ddi_phy_info[] = { | |
157 | [DPIO_PHY0] = { | |
158 | .dual_channel = true, | |
e7583f7b | 159 | .rcomp_phy = DPIO_PHY1, |
0a116ce8 | 160 | .pwron_mask = BIT(0), |
842d4166 ACO |
161 | |
162 | .channel = { | |
163 | [DPIO_CH0] = { .port = PORT_B }, | |
164 | [DPIO_CH1] = { .port = PORT_C }, | |
165 | } | |
166 | }, | |
167 | [DPIO_PHY1] = { | |
168 | .dual_channel = false, | |
e7583f7b | 169 | .rcomp_phy = -1, |
0a116ce8 | 170 | .pwron_mask = BIT(1), |
842d4166 ACO |
171 | |
172 | .channel = { | |
173 | [DPIO_CH0] = { .port = PORT_A }, | |
174 | } | |
175 | }, | |
176 | }; | |
177 | ||
0a116ce8 ACO |
178 | static const struct bxt_ddi_phy_info glk_ddi_phy_info[] = { |
179 | [DPIO_PHY0] = { | |
180 | .dual_channel = false, | |
181 | .rcomp_phy = DPIO_PHY1, | |
182 | .pwron_mask = BIT(0), | |
183 | .reset_delay = 20, | |
184 | ||
185 | .channel = { | |
186 | [DPIO_CH0] = { .port = PORT_B }, | |
187 | } | |
188 | }, | |
189 | [DPIO_PHY1] = { | |
190 | .dual_channel = false, | |
191 | .rcomp_phy = -1, | |
192 | .pwron_mask = BIT(3), | |
193 | .reset_delay = 20, | |
194 | ||
195 | .channel = { | |
196 | [DPIO_CH0] = { .port = PORT_A }, | |
197 | } | |
198 | }, | |
199 | [DPIO_PHY2] = { | |
200 | .dual_channel = false, | |
201 | .rcomp_phy = DPIO_PHY1, | |
202 | .pwron_mask = BIT(1), | |
203 | .reset_delay = 20, | |
204 | ||
205 | .channel = { | |
206 | [DPIO_CH0] = { .port = PORT_C }, | |
207 | } | |
208 | }, | |
209 | }; | |
210 | ||
0a116ce8 ACO |
211 | static const struct bxt_ddi_phy_info * |
212 | bxt_get_phy_list(struct drm_i915_private *dev_priv, int *count) | |
213 | { | |
214 | if (IS_GEMINILAKE(dev_priv)) { | |
215 | *count = ARRAY_SIZE(glk_ddi_phy_info); | |
216 | return glk_ddi_phy_info; | |
217 | } else { | |
218 | *count = ARRAY_SIZE(bxt_ddi_phy_info); | |
219 | return bxt_ddi_phy_info; | |
220 | } | |
221 | } | |
222 | ||
223 | static const struct bxt_ddi_phy_info * | |
224 | bxt_get_phy_info(struct drm_i915_private *dev_priv, enum dpio_phy phy) | |
225 | { | |
226 | int count; | |
227 | const struct bxt_ddi_phy_info *phy_list = | |
228 | bxt_get_phy_list(dev_priv, &count); | |
229 | ||
230 | return &phy_list[phy]; | |
231 | } | |
232 | ||
233 | void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port, | |
ed37892e ACO |
234 | enum dpio_phy *phy, enum dpio_channel *ch) |
235 | { | |
0a116ce8 ACO |
236 | const struct bxt_ddi_phy_info *phy_info, *phys; |
237 | int i, count; | |
238 | ||
239 | phys = bxt_get_phy_list(dev_priv, &count); | |
ed37892e | 240 | |
0a116ce8 ACO |
241 | for (i = 0; i < count; i++) { |
242 | phy_info = &phys[i]; | |
ed37892e ACO |
243 | |
244 | if (port == phy_info->channel[DPIO_CH0].port) { | |
245 | *phy = i; | |
246 | *ch = DPIO_CH0; | |
247 | return; | |
248 | } | |
249 | ||
250 | if (phy_info->dual_channel && | |
251 | port == phy_info->channel[DPIO_CH1].port) { | |
252 | *phy = i; | |
253 | *ch = DPIO_CH1; | |
254 | return; | |
255 | } | |
256 | } | |
257 | ||
258 | WARN(1, "PHY not found for PORT %c", port_name(port)); | |
259 | *phy = DPIO_PHY0; | |
260 | *ch = DPIO_CH0; | |
261 | } | |
262 | ||
b6e08203 ACO |
263 | void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv, |
264 | enum port port, u32 margin, u32 scale, | |
265 | u32 enable, u32 deemphasis) | |
266 | { | |
267 | u32 val; | |
ed37892e ACO |
268 | enum dpio_phy phy; |
269 | enum dpio_channel ch; | |
270 | ||
0a116ce8 | 271 | bxt_port_to_phy_channel(dev_priv, port, &phy, &ch); |
b6e08203 ACO |
272 | |
273 | /* | |
274 | * While we write to the group register to program all lanes at once we | |
275 | * can read only lane registers and we pick lanes 0/1 for that. | |
276 | */ | |
ed37892e | 277 | val = I915_READ(BXT_PORT_PCS_DW10_LN01(phy, ch)); |
b6e08203 | 278 | val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT); |
ed37892e | 279 | I915_WRITE(BXT_PORT_PCS_DW10_GRP(phy, ch), val); |
b6e08203 | 280 | |
ed37892e | 281 | val = I915_READ(BXT_PORT_TX_DW2_LN0(phy, ch)); |
b6e08203 ACO |
282 | val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE); |
283 | val |= margin << MARGIN_000_SHIFT | scale << UNIQ_TRANS_SCALE_SHIFT; | |
ed37892e | 284 | I915_WRITE(BXT_PORT_TX_DW2_GRP(phy, ch), val); |
b6e08203 | 285 | |
ed37892e | 286 | val = I915_READ(BXT_PORT_TX_DW3_LN0(phy, ch)); |
b6e08203 ACO |
287 | val &= ~SCALE_DCOMP_METHOD; |
288 | if (enable) | |
289 | val |= SCALE_DCOMP_METHOD; | |
290 | ||
291 | if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD)) | |
292 | DRM_ERROR("Disabled scaling while ouniqetrangenmethod was set"); | |
293 | ||
ed37892e | 294 | I915_WRITE(BXT_PORT_TX_DW3_GRP(phy, ch), val); |
b6e08203 | 295 | |
ed37892e | 296 | val = I915_READ(BXT_PORT_TX_DW4_LN0(phy, ch)); |
b6e08203 ACO |
297 | val &= ~DE_EMPHASIS; |
298 | val |= deemphasis << DEEMPH_SHIFT; | |
ed37892e | 299 | I915_WRITE(BXT_PORT_TX_DW4_GRP(phy, ch), val); |
b6e08203 | 300 | |
ed37892e | 301 | val = I915_READ(BXT_PORT_PCS_DW10_LN01(phy, ch)); |
b6e08203 | 302 | val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT; |
ed37892e | 303 | I915_WRITE(BXT_PORT_PCS_DW10_GRP(phy, ch), val); |
b6e08203 ACO |
304 | } |
305 | ||
47a6bc61 ACO |
306 | bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv, |
307 | enum dpio_phy phy) | |
308 | { | |
0a116ce8 | 309 | const struct bxt_ddi_phy_info *phy_info; |
47a6bc61 | 310 | |
0a116ce8 ACO |
311 | phy_info = bxt_get_phy_info(dev_priv, phy); |
312 | ||
313 | if (!(I915_READ(BXT_P_CR_GT_DISP_PWRON) & phy_info->pwron_mask)) | |
47a6bc61 ACO |
314 | return false; |
315 | ||
316 | if ((I915_READ(BXT_PORT_CL1CM_DW0(phy)) & | |
317 | (PHY_POWER_GOOD | PHY_RESERVED)) != PHY_POWER_GOOD) { | |
318 | DRM_DEBUG_DRIVER("DDI PHY %d powered, but power hasn't settled\n", | |
319 | phy); | |
320 | ||
321 | return false; | |
322 | } | |
323 | ||
47a6bc61 ACO |
324 | if (!(I915_READ(BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) { |
325 | DRM_DEBUG_DRIVER("DDI PHY %d powered, but still in reset\n", | |
326 | phy); | |
327 | ||
328 | return false; | |
329 | } | |
330 | ||
47a6bc61 ACO |
331 | return true; |
332 | } | |
333 | ||
334 | static u32 bxt_get_grc(struct drm_i915_private *dev_priv, enum dpio_phy phy) | |
335 | { | |
336 | u32 val = I915_READ(BXT_PORT_REF_DW6(phy)); | |
337 | ||
338 | return (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT; | |
339 | } | |
340 | ||
341 | static void bxt_phy_wait_grc_done(struct drm_i915_private *dev_priv, | |
342 | enum dpio_phy phy) | |
343 | { | |
344 | if (intel_wait_for_register(dev_priv, | |
345 | BXT_PORT_REF_DW3(phy), | |
346 | GRC_DONE, GRC_DONE, | |
347 | 10)) | |
348 | DRM_ERROR("timeout waiting for PHY%d GRC\n", phy); | |
349 | } | |
350 | ||
e7583f7b ACO |
351 | static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv, |
352 | enum dpio_phy phy) | |
47a6bc61 | 353 | { |
0a116ce8 | 354 | const struct bxt_ddi_phy_info *phy_info; |
47a6bc61 ACO |
355 | u32 val; |
356 | ||
0a116ce8 ACO |
357 | phy_info = bxt_get_phy_info(dev_priv, phy); |
358 | ||
47a6bc61 ACO |
359 | if (bxt_ddi_phy_is_enabled(dev_priv, phy)) { |
360 | /* Still read out the GRC value for state verification */ | |
e7583f7b | 361 | if (phy_info->rcomp_phy != -1) |
47a6bc61 ACO |
362 | dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, phy); |
363 | ||
364 | if (bxt_ddi_phy_verify_state(dev_priv, phy)) { | |
365 | DRM_DEBUG_DRIVER("DDI PHY %d already enabled, " | |
366 | "won't reprogram it\n", phy); | |
47a6bc61 ACO |
367 | return; |
368 | } | |
369 | ||
370 | DRM_DEBUG_DRIVER("DDI PHY %d enabled with invalid state, " | |
371 | "force reprogramming it\n", phy); | |
372 | } | |
373 | ||
374 | val = I915_READ(BXT_P_CR_GT_DISP_PWRON); | |
0a116ce8 | 375 | val |= phy_info->pwron_mask; |
47a6bc61 ACO |
376 | I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val); |
377 | ||
378 | /* | |
379 | * The PHY registers start out inaccessible and respond to reads with | |
380 | * all 1s. Eventually they become accessible as they power up, then | |
381 | * the reserved bit will give the default 0. Poll on the reserved bit | |
382 | * becoming 0 to find when the PHY is accessible. | |
1b85147b ID |
383 | * The flag should get set in 100us according to the HW team, but |
384 | * use 1ms due to occasional timeouts observed with that. | |
47a6bc61 | 385 | */ |
1b85147b ID |
386 | if (intel_wait_for_register_fw(dev_priv, BXT_PORT_CL1CM_DW0(phy), |
387 | PHY_RESERVED | PHY_POWER_GOOD, | |
388 | PHY_POWER_GOOD, | |
389 | 1)) | |
47a6bc61 | 390 | DRM_ERROR("timeout during PHY%d power on\n", phy); |
47a6bc61 ACO |
391 | |
392 | /* Program PLL Rcomp code offset */ | |
393 | val = I915_READ(BXT_PORT_CL1CM_DW9(phy)); | |
394 | val &= ~IREF0RC_OFFSET_MASK; | |
395 | val |= 0xE4 << IREF0RC_OFFSET_SHIFT; | |
396 | I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val); | |
397 | ||
398 | val = I915_READ(BXT_PORT_CL1CM_DW10(phy)); | |
399 | val &= ~IREF1RC_OFFSET_MASK; | |
400 | val |= 0xE4 << IREF1RC_OFFSET_SHIFT; | |
401 | I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val); | |
402 | ||
403 | /* Program power gating */ | |
404 | val = I915_READ(BXT_PORT_CL1CM_DW28(phy)); | |
405 | val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | | |
406 | SUS_CLK_CONFIG; | |
407 | I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val); | |
408 | ||
842d4166 ACO |
409 | if (phy_info->dual_channel) { |
410 | val = I915_READ(BXT_PORT_CL2CM_DW6(phy)); | |
47a6bc61 | 411 | val |= DW6_OLDO_DYN_PWR_DOWN_EN; |
842d4166 | 412 | I915_WRITE(BXT_PORT_CL2CM_DW6(phy), val); |
47a6bc61 ACO |
413 | } |
414 | ||
e7583f7b | 415 | if (phy_info->rcomp_phy != -1) { |
47a6bc61 | 416 | uint32_t grc_code; |
01a55197 RV |
417 | |
418 | bxt_phy_wait_grc_done(dev_priv, phy_info->rcomp_phy); | |
419 | ||
47a6bc61 ACO |
420 | /* |
421 | * PHY0 isn't connected to an RCOMP resistor so copy over | |
422 | * the corresponding calibrated value from PHY1, and disable | |
423 | * the automatic calibration on PHY0. | |
424 | */ | |
e7583f7b ACO |
425 | val = dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, |
426 | phy_info->rcomp_phy); | |
47a6bc61 ACO |
427 | grc_code = val << GRC_CODE_FAST_SHIFT | |
428 | val << GRC_CODE_SLOW_SHIFT | | |
429 | val; | |
e7583f7b | 430 | I915_WRITE(BXT_PORT_REF_DW6(phy), grc_code); |
47a6bc61 | 431 | |
e7583f7b | 432 | val = I915_READ(BXT_PORT_REF_DW8(phy)); |
47a6bc61 | 433 | val |= GRC_DIS | GRC_RDY_OVRD; |
e7583f7b | 434 | I915_WRITE(BXT_PORT_REF_DW8(phy), val); |
47a6bc61 ACO |
435 | } |
436 | ||
0a116ce8 ACO |
437 | if (phy_info->reset_delay) |
438 | udelay(phy_info->reset_delay); | |
439 | ||
47a6bc61 ACO |
440 | val = I915_READ(BXT_PHY_CTL_FAMILY(phy)); |
441 | val |= COMMON_RESET_DIS; | |
442 | I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val); | |
47a6bc61 ACO |
443 | } |
444 | ||
445 | void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy) | |
446 | { | |
0a116ce8 | 447 | const struct bxt_ddi_phy_info *phy_info; |
47a6bc61 ACO |
448 | uint32_t val; |
449 | ||
0a116ce8 ACO |
450 | phy_info = bxt_get_phy_info(dev_priv, phy); |
451 | ||
47a6bc61 ACO |
452 | val = I915_READ(BXT_PHY_CTL_FAMILY(phy)); |
453 | val &= ~COMMON_RESET_DIS; | |
454 | I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val); | |
455 | ||
456 | val = I915_READ(BXT_P_CR_GT_DISP_PWRON); | |
0a116ce8 | 457 | val &= ~phy_info->pwron_mask; |
47a6bc61 ACO |
458 | I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val); |
459 | } | |
460 | ||
e7583f7b ACO |
461 | void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy) |
462 | { | |
0a116ce8 ACO |
463 | const struct bxt_ddi_phy_info *phy_info = |
464 | bxt_get_phy_info(dev_priv, phy); | |
e7583f7b ACO |
465 | enum dpio_phy rcomp_phy = phy_info->rcomp_phy; |
466 | bool was_enabled; | |
467 | ||
468 | lockdep_assert_held(&dev_priv->power_domains.lock); | |
469 | ||
0e870bf8 CW |
470 | was_enabled = true; |
471 | if (rcomp_phy != -1) | |
e7583f7b ACO |
472 | was_enabled = bxt_ddi_phy_is_enabled(dev_priv, rcomp_phy); |
473 | ||
0e870bf8 CW |
474 | /* |
475 | * We need to copy the GRC calibration value from rcomp_phy, | |
476 | * so make sure it's powered up. | |
477 | */ | |
478 | if (!was_enabled) | |
479 | _bxt_ddi_phy_init(dev_priv, rcomp_phy); | |
e7583f7b ACO |
480 | |
481 | _bxt_ddi_phy_init(dev_priv, phy); | |
482 | ||
0e870bf8 CW |
483 | if (!was_enabled) |
484 | bxt_ddi_phy_uninit(dev_priv, rcomp_phy); | |
e7583f7b ACO |
485 | } |
486 | ||
47a6bc61 ACO |
487 | static bool __printf(6, 7) |
488 | __phy_reg_verify_state(struct drm_i915_private *dev_priv, enum dpio_phy phy, | |
489 | i915_reg_t reg, u32 mask, u32 expected, | |
490 | const char *reg_fmt, ...) | |
491 | { | |
492 | struct va_format vaf; | |
493 | va_list args; | |
494 | u32 val; | |
495 | ||
496 | val = I915_READ(reg); | |
497 | if ((val & mask) == expected) | |
498 | return true; | |
499 | ||
500 | va_start(args, reg_fmt); | |
501 | vaf.fmt = reg_fmt; | |
502 | vaf.va = &args; | |
503 | ||
504 | DRM_DEBUG_DRIVER("DDI PHY %d reg %pV [%08x] state mismatch: " | |
505 | "current %08x, expected %08x (mask %08x)\n", | |
506 | phy, &vaf, reg.reg, val, (val & ~mask) | expected, | |
507 | mask); | |
508 | ||
509 | va_end(args); | |
510 | ||
511 | return false; | |
512 | } | |
513 | ||
514 | bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv, | |
515 | enum dpio_phy phy) | |
516 | { | |
0a116ce8 | 517 | const struct bxt_ddi_phy_info *phy_info; |
47a6bc61 ACO |
518 | uint32_t mask; |
519 | bool ok; | |
520 | ||
0a116ce8 ACO |
521 | phy_info = bxt_get_phy_info(dev_priv, phy); |
522 | ||
47a6bc61 ACO |
523 | #define _CHK(reg, mask, exp, fmt, ...) \ |
524 | __phy_reg_verify_state(dev_priv, phy, reg, mask, exp, fmt, \ | |
525 | ## __VA_ARGS__) | |
526 | ||
527 | if (!bxt_ddi_phy_is_enabled(dev_priv, phy)) | |
528 | return false; | |
529 | ||
530 | ok = true; | |
531 | ||
532 | /* PLL Rcomp code offset */ | |
533 | ok &= _CHK(BXT_PORT_CL1CM_DW9(phy), | |
534 | IREF0RC_OFFSET_MASK, 0xe4 << IREF0RC_OFFSET_SHIFT, | |
535 | "BXT_PORT_CL1CM_DW9(%d)", phy); | |
536 | ok &= _CHK(BXT_PORT_CL1CM_DW10(phy), | |
537 | IREF1RC_OFFSET_MASK, 0xe4 << IREF1RC_OFFSET_SHIFT, | |
538 | "BXT_PORT_CL1CM_DW10(%d)", phy); | |
539 | ||
540 | /* Power gating */ | |
541 | mask = OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | SUS_CLK_CONFIG; | |
542 | ok &= _CHK(BXT_PORT_CL1CM_DW28(phy), mask, mask, | |
543 | "BXT_PORT_CL1CM_DW28(%d)", phy); | |
544 | ||
842d4166 ACO |
545 | if (phy_info->dual_channel) |
546 | ok &= _CHK(BXT_PORT_CL2CM_DW6(phy), | |
47a6bc61 | 547 | DW6_OLDO_DYN_PWR_DOWN_EN, DW6_OLDO_DYN_PWR_DOWN_EN, |
842d4166 | 548 | "BXT_PORT_CL2CM_DW6(%d)", phy); |
47a6bc61 | 549 | |
e7583f7b | 550 | if (phy_info->rcomp_phy != -1) { |
47a6bc61 ACO |
551 | u32 grc_code = dev_priv->bxt_phy_grc; |
552 | ||
553 | grc_code = grc_code << GRC_CODE_FAST_SHIFT | | |
554 | grc_code << GRC_CODE_SLOW_SHIFT | | |
555 | grc_code; | |
556 | mask = GRC_CODE_FAST_MASK | GRC_CODE_SLOW_MASK | | |
557 | GRC_CODE_NOM_MASK; | |
e7583f7b | 558 | ok &= _CHK(BXT_PORT_REF_DW6(phy), mask, grc_code, |
ed37892e | 559 | "BXT_PORT_REF_DW6(%d)", phy); |
47a6bc61 ACO |
560 | |
561 | mask = GRC_DIS | GRC_RDY_OVRD; | |
e7583f7b ACO |
562 | ok &= _CHK(BXT_PORT_REF_DW8(phy), mask, mask, |
563 | "BXT_PORT_REF_DW8(%d)", phy); | |
47a6bc61 ACO |
564 | } |
565 | ||
566 | return ok; | |
567 | #undef _CHK | |
568 | } | |
569 | ||
570 | uint8_t | |
5161d058 | 571 | bxt_ddi_phy_calc_lane_lat_optim_mask(uint8_t lane_count) |
47a6bc61 ACO |
572 | { |
573 | switch (lane_count) { | |
574 | case 1: | |
575 | return 0; | |
576 | case 2: | |
577 | return BIT(2) | BIT(0); | |
578 | case 4: | |
579 | return BIT(3) | BIT(2) | BIT(0); | |
580 | default: | |
581 | MISSING_CASE(lane_count); | |
582 | ||
583 | return 0; | |
584 | } | |
585 | } | |
586 | ||
587 | void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder, | |
588 | uint8_t lane_lat_optim_mask) | |
589 | { | |
8f4f2797 VS |
590 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
591 | enum port port = encoder->port; | |
ed37892e ACO |
592 | enum dpio_phy phy; |
593 | enum dpio_channel ch; | |
47a6bc61 ACO |
594 | int lane; |
595 | ||
0a116ce8 | 596 | bxt_port_to_phy_channel(dev_priv, port, &phy, &ch); |
ed37892e | 597 | |
47a6bc61 | 598 | for (lane = 0; lane < 4; lane++) { |
ed37892e | 599 | u32 val = I915_READ(BXT_PORT_TX_DW14_LN(phy, ch, lane)); |
47a6bc61 ACO |
600 | |
601 | /* | |
602 | * Note that on CHV this flag is called UPAR, but has | |
603 | * the same function. | |
604 | */ | |
605 | val &= ~LATENCY_OPTIM; | |
606 | if (lane_lat_optim_mask & BIT(lane)) | |
607 | val |= LATENCY_OPTIM; | |
608 | ||
ed37892e | 609 | I915_WRITE(BXT_PORT_TX_DW14_LN(phy, ch, lane), val); |
47a6bc61 ACO |
610 | } |
611 | } | |
612 | ||
613 | uint8_t | |
614 | bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder) | |
615 | { | |
8f4f2797 VS |
616 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
617 | enum port port = encoder->port; | |
ed37892e ACO |
618 | enum dpio_phy phy; |
619 | enum dpio_channel ch; | |
47a6bc61 ACO |
620 | int lane; |
621 | uint8_t mask; | |
622 | ||
0a116ce8 | 623 | bxt_port_to_phy_channel(dev_priv, port, &phy, &ch); |
ed37892e | 624 | |
47a6bc61 ACO |
625 | mask = 0; |
626 | for (lane = 0; lane < 4; lane++) { | |
ed37892e | 627 | u32 val = I915_READ(BXT_PORT_TX_DW14_LN(phy, ch, lane)); |
47a6bc61 ACO |
628 | |
629 | if (val & LATENCY_OPTIM) | |
630 | mask |= BIT(lane); | |
631 | } | |
632 | ||
633 | return mask; | |
634 | } | |
635 | ||
636 | ||
b7fa22d8 ACO |
637 | void chv_set_phy_signal_level(struct intel_encoder *encoder, |
638 | u32 deemph_reg_value, u32 margin_reg_value, | |
639 | bool uniq_trans_scale) | |
640 | { | |
641 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
642 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
8f4f2797 | 643 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
b7fa22d8 ACO |
644 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
645 | enum pipe pipe = intel_crtc->pipe; | |
646 | u32 val; | |
647 | int i; | |
648 | ||
649 | mutex_lock(&dev_priv->sb_lock); | |
650 | ||
651 | /* Clear calc init */ | |
652 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); | |
653 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); | |
654 | val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); | |
655 | val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; | |
656 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); | |
657 | ||
658 | if (intel_crtc->config->lane_count > 2) { | |
659 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); | |
660 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); | |
661 | val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); | |
662 | val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; | |
663 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); | |
664 | } | |
665 | ||
666 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch)); | |
667 | val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); | |
668 | val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; | |
669 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val); | |
670 | ||
671 | if (intel_crtc->config->lane_count > 2) { | |
672 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch)); | |
673 | val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); | |
674 | val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; | |
675 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val); | |
676 | } | |
677 | ||
678 | /* Program swing deemph */ | |
679 | for (i = 0; i < intel_crtc->config->lane_count; i++) { | |
680 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i)); | |
681 | val &= ~DPIO_SWING_DEEMPH9P5_MASK; | |
682 | val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT; | |
683 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val); | |
684 | } | |
685 | ||
686 | /* Program swing margin */ | |
687 | for (i = 0; i < intel_crtc->config->lane_count; i++) { | |
688 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); | |
689 | ||
690 | val &= ~DPIO_SWING_MARGIN000_MASK; | |
691 | val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT; | |
692 | ||
693 | /* | |
694 | * Supposedly this value shouldn't matter when unique transition | |
695 | * scale is disabled, but in fact it does matter. Let's just | |
696 | * always program the same value and hope it's OK. | |
697 | */ | |
698 | val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT); | |
699 | val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT; | |
700 | ||
701 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); | |
702 | } | |
703 | ||
704 | /* | |
705 | * The document said it needs to set bit 27 for ch0 and bit 26 | |
706 | * for ch1. Might be a typo in the doc. | |
707 | * For now, for this unique transition scale selection, set bit | |
708 | * 27 for ch0 and ch1. | |
709 | */ | |
710 | for (i = 0; i < intel_crtc->config->lane_count; i++) { | |
711 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); | |
712 | if (uniq_trans_scale) | |
713 | val |= DPIO_TX_UNIQ_TRANS_SCALE_EN; | |
714 | else | |
715 | val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN; | |
716 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); | |
717 | } | |
718 | ||
719 | /* Start swing calculation */ | |
720 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); | |
721 | val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; | |
722 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); | |
723 | ||
724 | if (intel_crtc->config->lane_count > 2) { | |
725 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); | |
726 | val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; | |
727 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); | |
728 | } | |
729 | ||
730 | mutex_unlock(&dev_priv->sb_lock); | |
731 | ||
732 | } | |
733 | ||
844b2f9a | 734 | void chv_data_lane_soft_reset(struct intel_encoder *encoder, |
2e1029c6 | 735 | const struct intel_crtc_state *crtc_state, |
844b2f9a ACO |
736 | bool reset) |
737 | { | |
738 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
739 | enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base)); | |
2e1029c6 | 740 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
844b2f9a ACO |
741 | enum pipe pipe = crtc->pipe; |
742 | uint32_t val; | |
743 | ||
744 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); | |
745 | if (reset) | |
746 | val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); | |
747 | else | |
748 | val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET; | |
749 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); | |
750 | ||
751 | if (crtc->config->lane_count > 2) { | |
752 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); | |
753 | if (reset) | |
754 | val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); | |
755 | else | |
756 | val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET; | |
757 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); | |
758 | } | |
759 | ||
760 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); | |
761 | val |= CHV_PCS_REQ_SOFTRESET_EN; | |
762 | if (reset) | |
763 | val &= ~DPIO_PCS_CLK_SOFT_RESET; | |
764 | else | |
765 | val |= DPIO_PCS_CLK_SOFT_RESET; | |
766 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); | |
767 | ||
768 | if (crtc->config->lane_count > 2) { | |
769 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); | |
770 | val |= CHV_PCS_REQ_SOFTRESET_EN; | |
771 | if (reset) | |
772 | val &= ~DPIO_PCS_CLK_SOFT_RESET; | |
773 | else | |
774 | val |= DPIO_PCS_CLK_SOFT_RESET; | |
775 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); | |
776 | } | |
777 | } | |
419b1b7a | 778 | |
2e1029c6 VS |
779 | void chv_phy_pre_pll_enable(struct intel_encoder *encoder, |
780 | const struct intel_crtc_state *crtc_state) | |
419b1b7a ACO |
781 | { |
782 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
2e1029c6 VS |
783 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
784 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
419b1b7a | 785 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
2e1029c6 | 786 | enum pipe pipe = crtc->pipe; |
419b1b7a | 787 | unsigned int lane_mask = |
2e1029c6 | 788 | intel_dp_unused_lane_mask(crtc_state->lane_count); |
419b1b7a ACO |
789 | u32 val; |
790 | ||
791 | /* | |
792 | * Must trick the second common lane into life. | |
793 | * Otherwise we can't even access the PLL. | |
794 | */ | |
795 | if (ch == DPIO_CH0 && pipe == PIPE_B) | |
796 | dport->release_cl2_override = | |
797 | !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true); | |
798 | ||
799 | chv_phy_powergate_lanes(encoder, true, lane_mask); | |
800 | ||
801 | mutex_lock(&dev_priv->sb_lock); | |
802 | ||
803 | /* Assert data lane reset */ | |
2e1029c6 | 804 | chv_data_lane_soft_reset(encoder, crtc_state, true); |
419b1b7a ACO |
805 | |
806 | /* program left/right clock distribution */ | |
807 | if (pipe != PIPE_B) { | |
808 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); | |
809 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); | |
810 | if (ch == DPIO_CH0) | |
811 | val |= CHV_BUFLEFTENA1_FORCE; | |
812 | if (ch == DPIO_CH1) | |
813 | val |= CHV_BUFRIGHTENA1_FORCE; | |
814 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); | |
815 | } else { | |
816 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); | |
817 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); | |
818 | if (ch == DPIO_CH0) | |
819 | val |= CHV_BUFLEFTENA2_FORCE; | |
820 | if (ch == DPIO_CH1) | |
821 | val |= CHV_BUFRIGHTENA2_FORCE; | |
822 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); | |
823 | } | |
824 | ||
825 | /* program clock channel usage */ | |
826 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch)); | |
827 | val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; | |
828 | if (pipe != PIPE_B) | |
829 | val &= ~CHV_PCS_USEDCLKCHANNEL; | |
830 | else | |
831 | val |= CHV_PCS_USEDCLKCHANNEL; | |
832 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val); | |
833 | ||
2e1029c6 | 834 | if (crtc_state->lane_count > 2) { |
419b1b7a ACO |
835 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch)); |
836 | val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; | |
837 | if (pipe != PIPE_B) | |
838 | val &= ~CHV_PCS_USEDCLKCHANNEL; | |
839 | else | |
840 | val |= CHV_PCS_USEDCLKCHANNEL; | |
841 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val); | |
842 | } | |
843 | ||
844 | /* | |
845 | * This a a bit weird since generally CL | |
846 | * matches the pipe, but here we need to | |
847 | * pick the CL based on the port. | |
848 | */ | |
849 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch)); | |
850 | if (pipe != PIPE_B) | |
851 | val &= ~CHV_CMN_USEDCLKCHANNEL; | |
852 | else | |
853 | val |= CHV_CMN_USEDCLKCHANNEL; | |
854 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val); | |
855 | ||
856 | mutex_unlock(&dev_priv->sb_lock); | |
857 | } | |
e7d2a717 | 858 | |
2e1029c6 VS |
859 | void chv_phy_pre_encoder_enable(struct intel_encoder *encoder, |
860 | const struct intel_crtc_state *crtc_state) | |
e7d2a717 ACO |
861 | { |
862 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
863 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); | |
2e1029c6 VS |
864 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
865 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
e7d2a717 | 866 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
2e1029c6 | 867 | enum pipe pipe = crtc->pipe; |
e7d2a717 ACO |
868 | int data, i, stagger; |
869 | u32 val; | |
870 | ||
871 | mutex_lock(&dev_priv->sb_lock); | |
872 | ||
873 | /* allow hardware to manage TX FIFO reset source */ | |
874 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); | |
875 | val &= ~DPIO_LANEDESKEW_STRAP_OVRD; | |
876 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); | |
877 | ||
2e1029c6 | 878 | if (crtc_state->lane_count > 2) { |
e7d2a717 ACO |
879 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); |
880 | val &= ~DPIO_LANEDESKEW_STRAP_OVRD; | |
881 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); | |
882 | } | |
883 | ||
884 | /* Program Tx lane latency optimal setting*/ | |
2e1029c6 | 885 | for (i = 0; i < crtc_state->lane_count; i++) { |
e7d2a717 | 886 | /* Set the upar bit */ |
2e1029c6 | 887 | if (crtc_state->lane_count == 1) |
e7d2a717 ACO |
888 | data = 0x0; |
889 | else | |
890 | data = (i == 1) ? 0x0 : 0x1; | |
891 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i), | |
892 | data << DPIO_UPAR_SHIFT); | |
893 | } | |
894 | ||
895 | /* Data lane stagger programming */ | |
2e1029c6 | 896 | if (crtc_state->port_clock > 270000) |
e7d2a717 | 897 | stagger = 0x18; |
2e1029c6 | 898 | else if (crtc_state->port_clock > 135000) |
e7d2a717 | 899 | stagger = 0xd; |
2e1029c6 | 900 | else if (crtc_state->port_clock > 67500) |
e7d2a717 | 901 | stagger = 0x7; |
2e1029c6 | 902 | else if (crtc_state->port_clock > 33750) |
e7d2a717 ACO |
903 | stagger = 0x4; |
904 | else | |
905 | stagger = 0x2; | |
906 | ||
907 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); | |
908 | val |= DPIO_TX2_STAGGER_MASK(0x1f); | |
909 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); | |
910 | ||
2e1029c6 | 911 | if (crtc_state->lane_count > 2) { |
e7d2a717 ACO |
912 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); |
913 | val |= DPIO_TX2_STAGGER_MASK(0x1f); | |
914 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); | |
915 | } | |
916 | ||
917 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch), | |
918 | DPIO_LANESTAGGER_STRAP(stagger) | | |
919 | DPIO_LANESTAGGER_STRAP_OVRD | | |
920 | DPIO_TX1_STAGGER_MASK(0x1f) | | |
921 | DPIO_TX1_STAGGER_MULT(6) | | |
922 | DPIO_TX2_STAGGER_MULT(0)); | |
923 | ||
2e1029c6 | 924 | if (crtc_state->lane_count > 2) { |
e7d2a717 ACO |
925 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch), |
926 | DPIO_LANESTAGGER_STRAP(stagger) | | |
927 | DPIO_LANESTAGGER_STRAP_OVRD | | |
928 | DPIO_TX1_STAGGER_MASK(0x1f) | | |
929 | DPIO_TX1_STAGGER_MULT(7) | | |
930 | DPIO_TX2_STAGGER_MULT(5)); | |
931 | } | |
932 | ||
933 | /* Deassert data lane reset */ | |
2e1029c6 | 934 | chv_data_lane_soft_reset(encoder, crtc_state, false); |
e7d2a717 ACO |
935 | |
936 | mutex_unlock(&dev_priv->sb_lock); | |
937 | } | |
938 | ||
939 | void chv_phy_release_cl2_override(struct intel_encoder *encoder) | |
940 | { | |
941 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
942 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
943 | ||
944 | if (dport->release_cl2_override) { | |
945 | chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false); | |
946 | dport->release_cl2_override = false; | |
947 | } | |
948 | } | |
204970b5 | 949 | |
2e1029c6 VS |
950 | void chv_phy_post_pll_disable(struct intel_encoder *encoder, |
951 | const struct intel_crtc_state *old_crtc_state) | |
204970b5 ACO |
952 | { |
953 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
2e1029c6 | 954 | enum pipe pipe = to_intel_crtc(old_crtc_state->base.crtc)->pipe; |
204970b5 ACO |
955 | u32 val; |
956 | ||
957 | mutex_lock(&dev_priv->sb_lock); | |
958 | ||
959 | /* disable left/right clock distribution */ | |
960 | if (pipe != PIPE_B) { | |
961 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); | |
962 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); | |
963 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); | |
964 | } else { | |
965 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); | |
966 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); | |
967 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); | |
968 | } | |
969 | ||
970 | mutex_unlock(&dev_priv->sb_lock); | |
971 | ||
972 | /* | |
973 | * Leave the power down bit cleared for at least one | |
974 | * lane so that chv_powergate_phy_ch() will power | |
975 | * on something when the channel is otherwise unused. | |
976 | * When the port is off and the override is removed | |
977 | * the lanes power down anyway, so otherwise it doesn't | |
978 | * really matter what the state of power down bits is | |
979 | * after this. | |
980 | */ | |
981 | chv_phy_powergate_lanes(encoder, false, 0x0); | |
982 | } | |
53d98725 ACO |
983 | |
984 | void vlv_set_phy_signal_level(struct intel_encoder *encoder, | |
985 | u32 demph_reg_value, u32 preemph_reg_value, | |
986 | u32 uniqtranscale_reg_value, u32 tx3_demph) | |
987 | { | |
988 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
989 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); | |
990 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
991 | enum dpio_channel port = vlv_dport_to_channel(dport); | |
2e1029c6 | 992 | enum pipe pipe = intel_crtc->pipe; |
53d98725 ACO |
993 | |
994 | mutex_lock(&dev_priv->sb_lock); | |
995 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000); | |
996 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value); | |
997 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), | |
998 | uniqtranscale_reg_value); | |
999 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040); | |
1000 | ||
1001 | if (tx3_demph) | |
1002 | vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), tx3_demph); | |
1003 | ||
1004 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); | |
1005 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value); | |
1006 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); | |
1007 | mutex_unlock(&dev_priv->sb_lock); | |
1008 | } | |
6da2e616 | 1009 | |
2e1029c6 VS |
1010 | void vlv_phy_pre_pll_enable(struct intel_encoder *encoder, |
1011 | const struct intel_crtc_state *crtc_state) | |
6da2e616 ACO |
1012 | { |
1013 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
2e1029c6 VS |
1014 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
1015 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
6da2e616 | 1016 | enum dpio_channel port = vlv_dport_to_channel(dport); |
2e1029c6 | 1017 | enum pipe pipe = crtc->pipe; |
6da2e616 ACO |
1018 | |
1019 | /* Program Tx lane resets to default */ | |
1020 | mutex_lock(&dev_priv->sb_lock); | |
1021 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), | |
1022 | DPIO_PCS_TX_LANE2_RESET | | |
1023 | DPIO_PCS_TX_LANE1_RESET); | |
1024 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), | |
1025 | DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | | |
1026 | DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | | |
1027 | (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) | | |
1028 | DPIO_PCS_CLK_SOFT_RESET); | |
1029 | ||
1030 | /* Fix up inter-pair skew failure */ | |
1031 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); | |
1032 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); | |
1033 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); | |
1034 | mutex_unlock(&dev_priv->sb_lock); | |
1035 | } | |
5f68c275 | 1036 | |
2e1029c6 VS |
1037 | void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder, |
1038 | const struct intel_crtc_state *crtc_state) | |
5f68c275 ACO |
1039 | { |
1040 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
1041 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); | |
2e1029c6 VS |
1042 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
1043 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
5f68c275 | 1044 | enum dpio_channel port = vlv_dport_to_channel(dport); |
2e1029c6 | 1045 | enum pipe pipe = crtc->pipe; |
5f68c275 ACO |
1046 | u32 val; |
1047 | ||
1048 | mutex_lock(&dev_priv->sb_lock); | |
1049 | ||
1050 | /* Enable clock channels for this port */ | |
1051 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); | |
1052 | val = 0; | |
1053 | if (pipe) | |
1054 | val |= (1<<21); | |
1055 | else | |
1056 | val &= ~(1<<21); | |
1057 | val |= 0x001000c4; | |
1058 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); | |
1059 | ||
1060 | /* Program lane clock */ | |
1061 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); | |
1062 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); | |
1063 | ||
1064 | mutex_unlock(&dev_priv->sb_lock); | |
1065 | } | |
0f572ebe | 1066 | |
2e1029c6 VS |
1067 | void vlv_phy_reset_lanes(struct intel_encoder *encoder, |
1068 | const struct intel_crtc_state *old_crtc_state) | |
0f572ebe ACO |
1069 | { |
1070 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
fac5e23e | 1071 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
2e1029c6 | 1072 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); |
0f572ebe | 1073 | enum dpio_channel port = vlv_dport_to_channel(dport); |
2e1029c6 | 1074 | enum pipe pipe = crtc->pipe; |
0f572ebe ACO |
1075 | |
1076 | mutex_lock(&dev_priv->sb_lock); | |
1077 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000); | |
1078 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060); | |
1079 | mutex_unlock(&dev_priv->sb_lock); | |
1080 | } |