Commit | Line | Data |
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0e32b39c DA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * 2014 Red Hat Inc. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
22 | * IN THE SOFTWARE. | |
23 | * | |
24 | */ | |
25 | ||
26 | #include <drm/drmP.h> | |
27 | #include "i915_drv.h" | |
28 | #include "intel_drv.h" | |
c6f95f27 | 29 | #include <drm/drm_atomic_helper.h> |
0e32b39c DA |
30 | #include <drm/drm_crtc_helper.h> |
31 | #include <drm/drm_edid.h> | |
32 | ||
33 | static bool intel_dp_mst_compute_config(struct intel_encoder *encoder, | |
5cec258b | 34 | struct intel_crtc_state *pipe_config) |
0e32b39c | 35 | { |
6fa2d197 | 36 | struct drm_device *dev = encoder->base.dev; |
0e32b39c DA |
37 | struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); |
38 | struct intel_digital_port *intel_dig_port = intel_mst->primary; | |
39 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
e75f4771 ACO |
40 | struct drm_atomic_state *state; |
41 | int bpp, i; | |
04a60f9f | 42 | int lane_count, slots; |
7c5f93b0 | 43 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
da3ced29 ACO |
44 | struct drm_connector *drm_connector; |
45 | struct intel_connector *connector, *found = NULL; | |
46 | struct drm_connector_state *connector_state; | |
0e32b39c DA |
47 | int mst_pbn; |
48 | ||
49 | pipe_config->dp_encoder_is_mst = true; | |
50 | pipe_config->has_pch_encoder = false; | |
51 | pipe_config->has_dp_encoder = true; | |
52 | bpp = 24; | |
53 | /* | |
54 | * for MST we always configure max link bw - the spec doesn't | |
55 | * seem to suggest we should do otherwise. | |
56 | */ | |
57 | lane_count = drm_dp_max_lane_count(intel_dp->dpcd); | |
ed4e9c1d | 58 | |
ed4e9c1d | 59 | |
90a6b7b0 | 60 | pipe_config->lane_count = lane_count; |
0e32b39c DA |
61 | |
62 | pipe_config->pipe_bpp = 24; | |
04a60f9f | 63 | pipe_config->port_clock = intel_dp_max_link_rate(intel_dp); |
0e32b39c | 64 | |
e75f4771 ACO |
65 | state = pipe_config->base.state; |
66 | ||
da3ced29 ACO |
67 | for_each_connector_in_state(state, drm_connector, connector_state, i) { |
68 | connector = to_intel_connector(drm_connector); | |
e75f4771 | 69 | |
da3ced29 ACO |
70 | if (connector_state->best_encoder == &encoder->base) { |
71 | found = connector; | |
0e32b39c DA |
72 | break; |
73 | } | |
74 | } | |
75 | ||
76 | if (!found) { | |
77 | DRM_ERROR("can't find connector\n"); | |
78 | return false; | |
79 | } | |
80 | ||
3d52ccf5 LY |
81 | if (drm_dp_mst_port_has_audio(&intel_dp->mst_mgr, found->port)) |
82 | pipe_config->has_audio = true; | |
aad941d5 | 83 | mst_pbn = drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock, bpp); |
0e32b39c DA |
84 | |
85 | pipe_config->pbn = mst_pbn; | |
86 | slots = drm_dp_find_vcpi_slots(&intel_dp->mst_mgr, mst_pbn); | |
87 | ||
88 | intel_link_compute_m_n(bpp, lane_count, | |
89 | adjusted_mode->crtc_clock, | |
90 | pipe_config->port_clock, | |
91 | &pipe_config->dp_m_n); | |
92 | ||
93 | pipe_config->dp_m_n.tu = slots; | |
6fa2d197 ACO |
94 | |
95 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
96 | hsw_dp_set_ddi_pll_sel(pipe_config); | |
97 | ||
0e32b39c DA |
98 | return true; |
99 | ||
100 | } | |
101 | ||
102 | static void intel_mst_disable_dp(struct intel_encoder *encoder) | |
103 | { | |
104 | struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); | |
105 | struct intel_digital_port *intel_dig_port = intel_mst->primary; | |
106 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
3d52ccf5 LY |
107 | struct drm_device *dev = encoder->base.dev; |
108 | struct drm_i915_private *dev_priv = dev->dev_private; | |
109 | struct drm_crtc *crtc = encoder->base.crtc; | |
110 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
111 | ||
0e32b39c DA |
112 | int ret; |
113 | ||
114 | DRM_DEBUG_KMS("%d\n", intel_dp->active_mst_links); | |
115 | ||
116 | drm_dp_mst_reset_vcpi_slots(&intel_dp->mst_mgr, intel_mst->port); | |
117 | ||
118 | ret = drm_dp_update_payload_part1(&intel_dp->mst_mgr); | |
119 | if (ret) { | |
120 | DRM_ERROR("failed to update payload %d\n", ret); | |
121 | } | |
3d52ccf5 LY |
122 | if (intel_crtc->config->has_audio) { |
123 | intel_audio_codec_disable(encoder); | |
124 | intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO); | |
125 | } | |
0e32b39c DA |
126 | } |
127 | ||
128 | static void intel_mst_post_disable_dp(struct intel_encoder *encoder) | |
129 | { | |
130 | struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); | |
131 | struct intel_digital_port *intel_dig_port = intel_mst->primary; | |
132 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
133 | ||
134 | DRM_DEBUG_KMS("%d\n", intel_dp->active_mst_links); | |
135 | ||
136 | /* this can fail */ | |
137 | drm_dp_check_act_status(&intel_dp->mst_mgr); | |
138 | /* and this can also fail */ | |
139 | drm_dp_update_payload_part2(&intel_dp->mst_mgr); | |
140 | ||
141 | drm_dp_mst_deallocate_vcpi(&intel_dp->mst_mgr, intel_mst->port); | |
142 | ||
143 | intel_dp->active_mst_links--; | |
144 | intel_mst->port = NULL; | |
145 | if (intel_dp->active_mst_links == 0) { | |
146 | intel_dig_port->base.post_disable(&intel_dig_port->base); | |
147 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); | |
148 | } | |
149 | } | |
150 | ||
151 | static void intel_mst_pre_enable_dp(struct intel_encoder *encoder) | |
152 | { | |
153 | struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); | |
154 | struct intel_digital_port *intel_dig_port = intel_mst->primary; | |
155 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
156 | struct drm_device *dev = encoder->base.dev; | |
157 | struct drm_i915_private *dev_priv = dev->dev_private; | |
158 | enum port port = intel_dig_port->port; | |
159 | int ret; | |
160 | uint32_t temp; | |
9b4fd8f2 | 161 | struct intel_connector *found = NULL, *connector; |
0e32b39c DA |
162 | int slots; |
163 | struct drm_crtc *crtc = encoder->base.crtc; | |
164 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
165 | ||
9b4fd8f2 ACO |
166 | for_each_intel_connector(dev, connector) { |
167 | if (connector->base.state->best_encoder == &encoder->base) { | |
168 | found = connector; | |
0e32b39c DA |
169 | break; |
170 | } | |
171 | } | |
172 | ||
173 | if (!found) { | |
174 | DRM_ERROR("can't find connector\n"); | |
175 | return; | |
176 | } | |
177 | ||
e85376cb ML |
178 | /* MST encoders are bound to a crtc, not to a connector, |
179 | * force the mapping here for get_hw_state. | |
180 | */ | |
181 | found->encoder = encoder; | |
182 | ||
0e32b39c DA |
183 | DRM_DEBUG_KMS("%d\n", intel_dp->active_mst_links); |
184 | intel_mst->port = found->port; | |
185 | ||
186 | if (intel_dp->active_mst_links == 0) { | |
6a7e4f99 VS |
187 | intel_prepare_ddi_buffer(&intel_dig_port->base); |
188 | ||
d919161b | 189 | intel_ddi_clk_select(&intel_dig_port->base, intel_crtc->config); |
0e32b39c | 190 | |
901c2daf VS |
191 | intel_dp_set_link_params(intel_dp, intel_crtc->config); |
192 | ||
0e32b39c DA |
193 | intel_ddi_init_dp_buf_reg(&intel_dig_port->base); |
194 | ||
195 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); | |
196 | ||
0e32b39c | 197 | intel_dp_start_link_train(intel_dp); |
0e32b39c DA |
198 | intel_dp_stop_link_train(intel_dp); |
199 | } | |
200 | ||
201 | ret = drm_dp_mst_allocate_vcpi(&intel_dp->mst_mgr, | |
6e3c9717 ACO |
202 | intel_mst->port, |
203 | intel_crtc->config->pbn, &slots); | |
0e32b39c DA |
204 | if (ret == false) { |
205 | DRM_ERROR("failed to allocate vcpi\n"); | |
206 | return; | |
207 | } | |
208 | ||
209 | ||
210 | intel_dp->active_mst_links++; | |
211 | temp = I915_READ(DP_TP_STATUS(port)); | |
212 | I915_WRITE(DP_TP_STATUS(port), temp); | |
213 | ||
214 | ret = drm_dp_update_payload_part1(&intel_dp->mst_mgr); | |
215 | } | |
216 | ||
217 | static void intel_mst_enable_dp(struct intel_encoder *encoder) | |
218 | { | |
219 | struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); | |
220 | struct intel_digital_port *intel_dig_port = intel_mst->primary; | |
221 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
222 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
223 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3d52ccf5 | 224 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
0e32b39c DA |
225 | enum port port = intel_dig_port->port; |
226 | int ret; | |
227 | ||
228 | DRM_DEBUG_KMS("%d\n", intel_dp->active_mst_links); | |
229 | ||
230 | if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_ACT_SENT), | |
231 | 1)) | |
232 | DRM_ERROR("Timed out waiting for ACT sent\n"); | |
233 | ||
234 | ret = drm_dp_check_act_status(&intel_dp->mst_mgr); | |
235 | ||
236 | ret = drm_dp_update_payload_part2(&intel_dp->mst_mgr); | |
3d52ccf5 LY |
237 | |
238 | if (crtc->config->has_audio) { | |
239 | DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", | |
240 | pipe_name(crtc->pipe)); | |
241 | intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO); | |
242 | intel_audio_codec_enable(encoder); | |
243 | } | |
0e32b39c DA |
244 | } |
245 | ||
246 | static bool intel_dp_mst_enc_get_hw_state(struct intel_encoder *encoder, | |
247 | enum pipe *pipe) | |
248 | { | |
249 | struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); | |
250 | *pipe = intel_mst->pipe; | |
251 | if (intel_mst->port) | |
252 | return true; | |
253 | return false; | |
254 | } | |
255 | ||
256 | static void intel_dp_mst_enc_get_config(struct intel_encoder *encoder, | |
5cec258b | 257 | struct intel_crtc_state *pipe_config) |
0e32b39c DA |
258 | { |
259 | struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); | |
260 | struct intel_digital_port *intel_dig_port = intel_mst->primary; | |
261 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); | |
262 | struct drm_device *dev = encoder->base.dev; | |
263 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0cb09a97 | 264 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; |
0e32b39c DA |
265 | u32 temp, flags = 0; |
266 | ||
267 | pipe_config->has_dp_encoder = true; | |
268 | ||
3d52ccf5 LY |
269 | pipe_config->has_audio = |
270 | intel_ddi_is_audio_enabled(dev_priv, crtc); | |
271 | ||
0e32b39c DA |
272 | temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
273 | if (temp & TRANS_DDI_PHSYNC) | |
274 | flags |= DRM_MODE_FLAG_PHSYNC; | |
275 | else | |
276 | flags |= DRM_MODE_FLAG_NHSYNC; | |
277 | if (temp & TRANS_DDI_PVSYNC) | |
278 | flags |= DRM_MODE_FLAG_PVSYNC; | |
279 | else | |
280 | flags |= DRM_MODE_FLAG_NVSYNC; | |
281 | ||
282 | switch (temp & TRANS_DDI_BPC_MASK) { | |
283 | case TRANS_DDI_BPC_6: | |
284 | pipe_config->pipe_bpp = 18; | |
285 | break; | |
286 | case TRANS_DDI_BPC_8: | |
287 | pipe_config->pipe_bpp = 24; | |
288 | break; | |
289 | case TRANS_DDI_BPC_10: | |
290 | pipe_config->pipe_bpp = 30; | |
291 | break; | |
292 | case TRANS_DDI_BPC_12: | |
293 | pipe_config->pipe_bpp = 36; | |
294 | break; | |
295 | default: | |
296 | break; | |
297 | } | |
2d112de7 | 298 | pipe_config->base.adjusted_mode.flags |= flags; |
90a6b7b0 VS |
299 | |
300 | pipe_config->lane_count = | |
301 | ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; | |
302 | ||
0e32b39c DA |
303 | intel_dp_get_m_n(crtc, pipe_config); |
304 | ||
305 | intel_ddi_clock_get(&intel_dig_port->base, pipe_config); | |
306 | } | |
307 | ||
308 | static int intel_dp_mst_get_ddc_modes(struct drm_connector *connector) | |
309 | { | |
310 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
311 | struct intel_dp *intel_dp = intel_connector->mst_port; | |
312 | struct edid *edid; | |
313 | int ret; | |
314 | ||
315 | edid = drm_dp_mst_get_edid(connector, &intel_dp->mst_mgr, intel_connector->port); | |
316 | if (!edid) | |
317 | return 0; | |
318 | ||
319 | ret = intel_connector_update_modes(connector, edid); | |
320 | kfree(edid); | |
321 | ||
322 | return ret; | |
323 | } | |
324 | ||
325 | static enum drm_connector_status | |
f7f3d48a | 326 | intel_dp_mst_detect(struct drm_connector *connector, bool force) |
0e32b39c DA |
327 | { |
328 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
329 | struct intel_dp *intel_dp = intel_connector->mst_port; | |
330 | ||
c6a0aed4 | 331 | return drm_dp_mst_detect_port(connector, &intel_dp->mst_mgr, intel_connector->port); |
0e32b39c DA |
332 | } |
333 | ||
0e32b39c DA |
334 | static int |
335 | intel_dp_mst_set_property(struct drm_connector *connector, | |
336 | struct drm_property *property, | |
337 | uint64_t val) | |
338 | { | |
339 | return 0; | |
340 | } | |
341 | ||
342 | static void | |
343 | intel_dp_mst_connector_destroy(struct drm_connector *connector) | |
344 | { | |
345 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
346 | ||
347 | if (!IS_ERR_OR_NULL(intel_connector->edid)) | |
348 | kfree(intel_connector->edid); | |
349 | ||
350 | drm_connector_cleanup(connector); | |
351 | kfree(connector); | |
352 | } | |
353 | ||
354 | static const struct drm_connector_funcs intel_dp_mst_connector_funcs = { | |
4d688a2a | 355 | .dpms = drm_atomic_helper_connector_dpms, |
0e32b39c DA |
356 | .detect = intel_dp_mst_detect, |
357 | .fill_modes = drm_helper_probe_single_connector_modes, | |
358 | .set_property = intel_dp_mst_set_property, | |
2545e4a6 | 359 | .atomic_get_property = intel_connector_atomic_get_property, |
0e32b39c | 360 | .destroy = intel_dp_mst_connector_destroy, |
c6f95f27 | 361 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
98969725 | 362 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
0e32b39c DA |
363 | }; |
364 | ||
365 | static int intel_dp_mst_get_modes(struct drm_connector *connector) | |
366 | { | |
367 | return intel_dp_mst_get_ddc_modes(connector); | |
368 | } | |
369 | ||
370 | static enum drm_mode_status | |
371 | intel_dp_mst_mode_valid(struct drm_connector *connector, | |
372 | struct drm_display_mode *mode) | |
373 | { | |
832d5bfd MK |
374 | int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; |
375 | ||
0e32b39c DA |
376 | /* TODO - validate mode against available PBN for link */ |
377 | if (mode->clock < 10000) | |
378 | return MODE_CLOCK_LOW; | |
379 | ||
380 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) | |
381 | return MODE_H_ILLEGAL; | |
382 | ||
832d5bfd MK |
383 | if (mode->clock > max_dotclk) |
384 | return MODE_CLOCK_HIGH; | |
385 | ||
0e32b39c DA |
386 | return MODE_OK; |
387 | } | |
388 | ||
459485ad DV |
389 | static struct drm_encoder *intel_mst_atomic_best_encoder(struct drm_connector *connector, |
390 | struct drm_connector_state *state) | |
391 | { | |
392 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
393 | struct intel_dp *intel_dp = intel_connector->mst_port; | |
394 | struct intel_crtc *crtc = to_intel_crtc(state->crtc); | |
395 | ||
396 | return &intel_dp->mst_encoders[crtc->pipe]->base.base; | |
397 | } | |
398 | ||
0e32b39c DA |
399 | static struct drm_encoder *intel_mst_best_encoder(struct drm_connector *connector) |
400 | { | |
401 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
402 | struct intel_dp *intel_dp = intel_connector->mst_port; | |
403 | return &intel_dp->mst_encoders[0]->base.base; | |
404 | } | |
405 | ||
406 | static const struct drm_connector_helper_funcs intel_dp_mst_connector_helper_funcs = { | |
407 | .get_modes = intel_dp_mst_get_modes, | |
408 | .mode_valid = intel_dp_mst_mode_valid, | |
459485ad | 409 | .atomic_best_encoder = intel_mst_atomic_best_encoder, |
0e32b39c DA |
410 | .best_encoder = intel_mst_best_encoder, |
411 | }; | |
412 | ||
413 | static void intel_dp_mst_encoder_destroy(struct drm_encoder *encoder) | |
414 | { | |
415 | struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); | |
416 | ||
417 | drm_encoder_cleanup(encoder); | |
418 | kfree(intel_mst); | |
419 | } | |
420 | ||
421 | static const struct drm_encoder_funcs intel_dp_mst_enc_funcs = { | |
422 | .destroy = intel_dp_mst_encoder_destroy, | |
423 | }; | |
424 | ||
425 | static bool intel_dp_mst_get_hw_state(struct intel_connector *connector) | |
426 | { | |
e85376cb | 427 | if (connector->encoder && connector->base.state->crtc) { |
0e32b39c DA |
428 | enum pipe pipe; |
429 | if (!connector->encoder->get_hw_state(connector->encoder, &pipe)) | |
430 | return false; | |
431 | return true; | |
432 | } | |
433 | return false; | |
434 | } | |
435 | ||
7296c849 CW |
436 | static void intel_connector_add_to_fbdev(struct intel_connector *connector) |
437 | { | |
0695726e | 438 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
7296c849 | 439 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); |
54632abe LW |
440 | |
441 | if (dev_priv->fbdev) | |
442 | drm_fb_helper_add_one_connector(&dev_priv->fbdev->helper, | |
443 | &connector->base); | |
7296c849 CW |
444 | #endif |
445 | } | |
446 | ||
447 | static void intel_connector_remove_from_fbdev(struct intel_connector *connector) | |
448 | { | |
0695726e | 449 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
7296c849 | 450 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); |
54632abe LW |
451 | |
452 | if (dev_priv->fbdev) | |
453 | drm_fb_helper_remove_one_connector(&dev_priv->fbdev->helper, | |
454 | &connector->base); | |
7296c849 CW |
455 | #endif |
456 | } | |
457 | ||
12e6cecd | 458 | static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port, const char *pathprop) |
0e32b39c DA |
459 | { |
460 | struct intel_dp *intel_dp = container_of(mgr, struct intel_dp, mst_mgr); | |
461 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
462 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
0e32b39c DA |
463 | struct intel_connector *intel_connector; |
464 | struct drm_connector *connector; | |
465 | int i; | |
466 | ||
9bdbd0b9 | 467 | intel_connector = intel_connector_alloc(); |
0e32b39c DA |
468 | if (!intel_connector) |
469 | return NULL; | |
470 | ||
471 | connector = &intel_connector->base; | |
472 | drm_connector_init(dev, connector, &intel_dp_mst_connector_funcs, DRM_MODE_CONNECTOR_DisplayPort); | |
473 | drm_connector_helper_add(connector, &intel_dp_mst_connector_helper_funcs); | |
474 | ||
475 | intel_connector->unregister = intel_connector_unregister; | |
476 | intel_connector->get_hw_state = intel_dp_mst_get_hw_state; | |
477 | intel_connector->mst_port = intel_dp; | |
478 | intel_connector->port = port; | |
479 | ||
480 | for (i = PIPE_A; i <= PIPE_C; i++) { | |
481 | drm_mode_connector_attach_encoder(&intel_connector->base, | |
482 | &intel_dp->mst_encoders[i]->base.base); | |
483 | } | |
484 | intel_dp_add_properties(intel_dp, connector); | |
485 | ||
486 | drm_object_attach_property(&connector->base, dev->mode_config.path_property, 0); | |
6f134d7b DA |
487 | drm_object_attach_property(&connector->base, dev->mode_config.tile_property, 0); |
488 | ||
0e32b39c | 489 | drm_mode_connector_set_path_property(connector, pathprop); |
d9515c5e DA |
490 | return connector; |
491 | } | |
492 | ||
493 | static void intel_dp_register_mst_connector(struct drm_connector *connector) | |
494 | { | |
495 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
496 | struct drm_device *dev = connector->dev; | |
8bb4da1d | 497 | drm_modeset_lock_all(dev); |
7296c849 | 498 | intel_connector_add_to_fbdev(intel_connector); |
8bb4da1d | 499 | drm_modeset_unlock_all(dev); |
0e32b39c | 500 | drm_connector_register(&intel_connector->base); |
0e32b39c DA |
501 | } |
502 | ||
503 | static void intel_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr, | |
504 | struct drm_connector *connector) | |
505 | { | |
506 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
507 | struct drm_device *dev = connector->dev; | |
20fae983 | 508 | |
9e60290d L |
509 | intel_connector->unregister(intel_connector); |
510 | ||
0e32b39c | 511 | /* need to nuke the connector */ |
8bb4da1d | 512 | drm_modeset_lock_all(dev); |
20fae983 ML |
513 | if (connector->state->crtc) { |
514 | struct drm_mode_set set; | |
515 | int ret; | |
516 | ||
517 | memset(&set, 0, sizeof(set)); | |
518 | set.crtc = connector->state->crtc, | |
519 | ||
520 | ret = drm_atomic_helper_set_config(&set); | |
521 | ||
522 | WARN(ret, "Disabling mst crtc failed with %i\n", ret); | |
523 | } | |
0e32b39c | 524 | |
7296c849 | 525 | intel_connector_remove_from_fbdev(intel_connector); |
0e32b39c | 526 | drm_connector_cleanup(connector); |
8bb4da1d | 527 | drm_modeset_unlock_all(dev); |
0e32b39c | 528 | |
0e32b39c DA |
529 | kfree(intel_connector); |
530 | DRM_DEBUG_KMS("\n"); | |
531 | } | |
532 | ||
533 | static void intel_dp_mst_hotplug(struct drm_dp_mst_topology_mgr *mgr) | |
534 | { | |
535 | struct intel_dp *intel_dp = container_of(mgr, struct intel_dp, mst_mgr); | |
536 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
537 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
538 | ||
539 | drm_kms_helper_hotplug_event(dev); | |
540 | } | |
541 | ||
69a0f89c | 542 | static const struct drm_dp_mst_topology_cbs mst_cbs = { |
0e32b39c | 543 | .add_connector = intel_dp_add_mst_connector, |
d9515c5e | 544 | .register_connector = intel_dp_register_mst_connector, |
0e32b39c DA |
545 | .destroy_connector = intel_dp_destroy_mst_connector, |
546 | .hotplug = intel_dp_mst_hotplug, | |
547 | }; | |
548 | ||
549 | static struct intel_dp_mst_encoder * | |
550 | intel_dp_create_fake_mst_encoder(struct intel_digital_port *intel_dig_port, enum pipe pipe) | |
551 | { | |
552 | struct intel_dp_mst_encoder *intel_mst; | |
553 | struct intel_encoder *intel_encoder; | |
554 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
555 | ||
556 | intel_mst = kzalloc(sizeof(*intel_mst), GFP_KERNEL); | |
557 | ||
558 | if (!intel_mst) | |
559 | return NULL; | |
560 | ||
561 | intel_mst->pipe = pipe; | |
562 | intel_encoder = &intel_mst->base; | |
563 | intel_mst->primary = intel_dig_port; | |
564 | ||
565 | drm_encoder_init(dev, &intel_encoder->base, &intel_dp_mst_enc_funcs, | |
13a3d91f | 566 | DRM_MODE_ENCODER_DPMST, NULL); |
0e32b39c DA |
567 | |
568 | intel_encoder->type = INTEL_OUTPUT_DP_MST; | |
569 | intel_encoder->crtc_mask = 0x7; | |
570 | intel_encoder->cloneable = 0; | |
571 | ||
572 | intel_encoder->compute_config = intel_dp_mst_compute_config; | |
573 | intel_encoder->disable = intel_mst_disable_dp; | |
574 | intel_encoder->post_disable = intel_mst_post_disable_dp; | |
575 | intel_encoder->pre_enable = intel_mst_pre_enable_dp; | |
576 | intel_encoder->enable = intel_mst_enable_dp; | |
577 | intel_encoder->get_hw_state = intel_dp_mst_enc_get_hw_state; | |
578 | intel_encoder->get_config = intel_dp_mst_enc_get_config; | |
579 | ||
580 | return intel_mst; | |
581 | ||
582 | } | |
583 | ||
584 | static bool | |
585 | intel_dp_create_fake_mst_encoders(struct intel_digital_port *intel_dig_port) | |
586 | { | |
587 | int i; | |
588 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
589 | ||
590 | for (i = PIPE_A; i <= PIPE_C; i++) | |
591 | intel_dp->mst_encoders[i] = intel_dp_create_fake_mst_encoder(intel_dig_port, i); | |
592 | return true; | |
593 | } | |
594 | ||
595 | int | |
596 | intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_base_id) | |
597 | { | |
598 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
599 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
600 | int ret; | |
601 | ||
602 | intel_dp->can_mst = true; | |
603 | intel_dp->mst_mgr.cbs = &mst_cbs; | |
604 | ||
605 | /* create encoders */ | |
606 | intel_dp_create_fake_mst_encoders(intel_dig_port); | |
607 | ret = drm_dp_mst_topology_mgr_init(&intel_dp->mst_mgr, dev->dev, &intel_dp->aux, 16, 3, conn_base_id); | |
608 | if (ret) { | |
609 | intel_dp->can_mst = false; | |
610 | return ret; | |
611 | } | |
612 | return 0; | |
613 | } | |
614 | ||
615 | void | |
616 | intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port) | |
617 | { | |
618 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
619 | ||
620 | if (!intel_dp->can_mst) | |
621 | return; | |
622 | ||
623 | drm_dp_mst_topology_mgr_destroy(&intel_dp->mst_mgr); | |
624 | /* encoders will get killed by normal cleanup */ | |
625 | } |