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drm/i915: Fix intel_dp_mst_best_encoder()
[linux-block.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
611032bf 31#include <linux/types.h>
01527b31
CT		 32#include <linux/notifier.h>
33#include <linux/reboot.h>
611032bf 34#include <asm/byteorder.h>
760285e7 35#include <drm/drmP.h>
c6f95f27 36#include <drm/drm_atomic_helper.h>
760285e7
DH		 37#include <drm/drm_crtc.h>
38#include <drm/drm_crtc_helper.h>
20f24d77 39#include <drm/drm_dp_helper.h>
760285e7 40#include <drm/drm_edid.h>
20f24d77 41#include <drm/drm_hdcp.h>
a4fc5ed6 42#include "intel_drv.h"
760285e7 43#include <drm/i915_drm.h>
a4fc5ed6 44#include "i915_drv.h"
a4fc5ed6 45
e8b2577c 46#define DP_DPRX_ESI_LEN 14
a4fc5ed6 47
559be30c
TP		 48/* Compliance test status bits */
49#define INTEL_DP_RESOLUTION_SHIFT_MASK 0
50#define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
51#define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
52#define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
53
9dd4ffdf 54struct dp_link_dpll {
840b32b7 55 int clock;
9dd4ffdf
CML		 56 struct dpll dpll;
57};
58
45101e93 59static const struct dp_link_dpll g4x_dpll[] = {
840b32b7 60 { 162000,
9dd4ffdf 61 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
840b32b7 62 { 270000,
9dd4ffdf
CML		 63 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
64};
65
66static const struct dp_link_dpll pch_dpll[] = {
840b32b7 67 { 162000,
9dd4ffdf 68 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
840b32b7 69 { 270000,
9dd4ffdf
CML		 70 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
71};
72
65ce4bf5 73static const struct dp_link_dpll vlv_dpll[] = {
840b32b7 74 { 162000,
58f6e632 75 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
840b32b7 76 { 270000,
65ce4bf5
CML		 77 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
78};
79
ef9348c8
CML		 80/*
81 * CHV supports eDP 1.4 that have more link rates.
82 * Below only provides the fixed rate but exclude variable rate.
83 */
84static const struct dp_link_dpll chv_dpll[] = {
85 /*
86 * CHV requires to program fractional division for m2.
87 * m2 is stored in fixed point format using formula below
88 * (m2_int << 22) | m2_fraction
89 */
840b32b7 90 { 162000, /* m2_int = 32, m2_fraction = 1677722 */
ef9348c8 91 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
840b32b7 92 { 270000, /* m2_int = 27, m2_fraction = 0 */
ef9348c8 93 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
ef9348c8 94};
637a9c63 95
cfcb0fc9 96/**
1853a9da 97 * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
cfcb0fc9
JB		 98 * @intel_dp: DP struct
99 *
100 * If a CPU or PCH DP output is attached to an eDP panel, this function
101 * will return true, and false otherwise.
102 */
1853a9da 103bool intel_dp_is_edp(struct intel_dp *intel_dp)
cfcb0fc9 104{
da63a9f2
PZ		 105 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
106
107 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 108}
109
df0e9248
CW		 110static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
111{
fa90ecef 112 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 113}
114
adc10304
VS		 115static void intel_dp_link_down(struct intel_encoder *encoder,
116 const struct intel_crtc_state *old_crtc_state);
1e0560e0 117static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 118static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
adc10304
VS		 119static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
120 const struct intel_crtc_state *crtc_state);
46bd8383 121static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
a8c3344e 122 enum pipe pipe);
f21a2198 123static void intel_dp_unset_edid(struct intel_dp *intel_dp);
a4fc5ed6 124
68f357cb
JN		 125/* update sink rates from dpcd */
126static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
127{
229675d5 128 static const int dp_rates[] = {
c71b53cc 129 162000, 270000, 540000, 810000
229675d5 130 };
a8a08886 131 int i, max_rate;
68f357cb 132
a8a08886 133 max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
68f357cb 134
229675d5
JN		 135 for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
136 if (dp_rates[i] > max_rate)
a8a08886 137 break;
229675d5 138 intel_dp->sink_rates[i] = dp_rates[i];
a8a08886 139 }
68f357cb 140
a8a08886 141 intel_dp->num_sink_rates = i;
68f357cb
JN		 142}
143
10ebb736
JN		 144/* Get length of rates array potentially limited by max_rate. */
145static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
146{
147 int i;
148
149 /* Limit results by potentially reduced max rate */
150 for (i = 0; i < len; i++) {
151 if (rates[len - i - 1] <= max_rate)
152 return len - i;
153 }
154
155 return 0;
156}
157
158/* Get length of common rates array potentially limited by max_rate. */
159static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
160 int max_rate)
161{
162 return intel_dp_rate_limit_len(intel_dp->common_rates,
163 intel_dp->num_common_rates, max_rate);
164}
165
540b0b7f
JN		 166/* Theoretical max between source and sink */
167static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
a4fc5ed6 168{
540b0b7f 169 return intel_dp->common_rates[intel_dp->num_common_rates - 1];
a4fc5ed6
KP		 170}
171
db7295c2
AM		 172static int intel_dp_get_fia_supported_lane_count(struct intel_dp *intel_dp)
173{
174 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
175 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
176 enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
177 u32 lane_info;
178
179 if (tc_port == PORT_TC_NONE || dig_port->tc_type != TC_PORT_TYPEC)
180 return 4;
181
182 lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &
183 DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
184 DP_LANE_ASSIGNMENT_SHIFT(tc_port);
185
186 switch (lane_info) {
187 default:
188 MISSING_CASE(lane_info);
189 case 1:
190 case 2:
191 case 4:
192 case 8:
193 return 1;
194 case 3:
195 case 12:
196 return 2;
197 case 15:
198 return 4;
199 }
200}
201
540b0b7f
JN		 202/* Theoretical max between source and sink */
203static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
eeb6324d
PZ		 204{
205 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
540b0b7f
JN		 206 int source_max = intel_dig_port->max_lanes;
207 int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
db7295c2 208 int fia_max = intel_dp_get_fia_supported_lane_count(intel_dp);
eeb6324d 209
db7295c2 210 return min3(source_max, sink_max, fia_max);
eeb6324d
PZ		 211}
212
3d65a735 213int intel_dp_max_lane_count(struct intel_dp *intel_dp)
540b0b7f
JN		 214{
215 return intel_dp->max_link_lane_count;
216}
217
22a2c8e0 218int
c898261c 219intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 220{
fd81c44e
DP		 221 /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
222 return DIV_ROUND_UP(pixel_clock * bpp, 8);
a4fc5ed6
KP		 223}
224
340a44be
PZ		 225void icl_program_mg_dp_mode(struct intel_dp *intel_dp)
226{
227 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
de25eb7f 228 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
340a44be
PZ		 229 enum port port = intel_dig_port->base.port;
230 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
231 u32 ln0, ln1, lane_info;
232
233 if (tc_port == PORT_TC_NONE || intel_dig_port->tc_type == TC_PORT_TBT)
234 return;
235
236 ln0 = I915_READ(MG_DP_MODE(port, 0));
237 ln1 = I915_READ(MG_DP_MODE(port, 1));
238
239 switch (intel_dig_port->tc_type) {
240 case TC_PORT_TYPEC:
241 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
242 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
243
244 lane_info = (I915_READ(PORT_TX_DFLEXDPSP) &
245 DP_LANE_ASSIGNMENT_MASK(tc_port)) >>
246 DP_LANE_ASSIGNMENT_SHIFT(tc_port);
247
248 switch (lane_info) {
249 case 0x1:
250 case 0x4:
251 break;
252 case 0x2:
253 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
254 break;
255 case 0x3:
256 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
257 MG_DP_MODE_CFG_DP_X2_MODE;
258 break;
259 case 0x8:
260 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
261 break;
262 case 0xC:
263 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
264 MG_DP_MODE_CFG_DP_X2_MODE;
265 break;
266 case 0xF:
267 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE |
268 MG_DP_MODE_CFG_DP_X2_MODE;
269 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE |
270 MG_DP_MODE_CFG_DP_X2_MODE;
271 break;
272 default:
273 MISSING_CASE(lane_info);
274 }
275 break;
276
277 case TC_PORT_LEGACY:
278 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
279 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE;
280 break;
281
282 default:
283 MISSING_CASE(intel_dig_port->tc_type);
284 return;
285 }
286
287 I915_WRITE(MG_DP_MODE(port, 0), ln0);
288 I915_WRITE(MG_DP_MODE(port, 1), ln1);
289}
290
bc334d91
PZ		 291void icl_enable_phy_clock_gating(struct intel_digital_port *dig_port)
292{
293 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
294 enum port port = dig_port->base.port;
295 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
296 i915_reg_t mg_regs[2] = { MG_DP_MODE(port, 0), MG_DP_MODE(port, 1) };
297 u32 val;
298 int i;
299
300 if (tc_port == PORT_TC_NONE)
301 return;
302
303 for (i = 0; i < ARRAY_SIZE(mg_regs); i++) {
304 val = I915_READ(mg_regs[i]);
305 val |= MG_DP_MODE_CFG_TR2PWR_GATING |
306 MG_DP_MODE_CFG_TRPWR_GATING |
307 MG_DP_MODE_CFG_CLNPWR_GATING |
308 MG_DP_MODE_CFG_DIGPWR_GATING |
309 MG_DP_MODE_CFG_GAONPWR_GATING;
310 I915_WRITE(mg_regs[i], val);
311 }
312
313 val = I915_READ(MG_MISC_SUS0(tc_port));
314 val |= MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(3) |
315 MG_MISC_SUS0_CFG_TR2PWR_GATING |
316 MG_MISC_SUS0_CFG_CL2PWR_GATING |
317 MG_MISC_SUS0_CFG_GAONPWR_GATING |
318 MG_MISC_SUS0_CFG_TRPWR_GATING |
319 MG_MISC_SUS0_CFG_CL1PWR_GATING |
320 MG_MISC_SUS0_CFG_DGPWR_GATING;
321 I915_WRITE(MG_MISC_SUS0(tc_port), val);
322}
323
324void icl_disable_phy_clock_gating(struct intel_digital_port *dig_port)
325{
326 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
327 enum port port = dig_port->base.port;
328 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
329 i915_reg_t mg_regs[2] = { MG_DP_MODE(port, 0), MG_DP_MODE(port, 1) };
330 u32 val;
331 int i;
332
333 if (tc_port == PORT_TC_NONE)
334 return;
335
336 for (i = 0; i < ARRAY_SIZE(mg_regs); i++) {
337 val = I915_READ(mg_regs[i]);
338 val &= ~(MG_DP_MODE_CFG_TR2PWR_GATING |
339 MG_DP_MODE_CFG_TRPWR_GATING |
340 MG_DP_MODE_CFG_CLNPWR_GATING |
341 MG_DP_MODE_CFG_DIGPWR_GATING |
342 MG_DP_MODE_CFG_GAONPWR_GATING);
343 I915_WRITE(mg_regs[i], val);
344 }
345
346 val = I915_READ(MG_MISC_SUS0(tc_port));
347 val &= ~(MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE_MASK |
348 MG_MISC_SUS0_CFG_TR2PWR_GATING |
349 MG_MISC_SUS0_CFG_CL2PWR_GATING |
350 MG_MISC_SUS0_CFG_GAONPWR_GATING |
351 MG_MISC_SUS0_CFG_TRPWR_GATING |
352 MG_MISC_SUS0_CFG_CL1PWR_GATING |
353 MG_MISC_SUS0_CFG_DGPWR_GATING);
354 I915_WRITE(MG_MISC_SUS0(tc_port), val);
355}
356
22a2c8e0 357int
fe27d53e
DA		 358intel_dp_max_data_rate(int max_link_clock, int max_lanes)
359{
fd81c44e
DP		 360 /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
361 * link rate that is generally expressed in Gbps. Since, 8 bits of data
362 * is transmitted every LS_Clk per lane, there is no need to account for
363 * the channel encoding that is done in the PHY layer here.
364 */
365
366 return max_link_clock * max_lanes;
fe27d53e
DA		 367}
368
70ec0645
MK		 369static int
370intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
371{
372 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
373 struct intel_encoder *encoder = &intel_dig_port->base;
374 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
375 int max_dotclk = dev_priv->max_dotclk_freq;
376 int ds_max_dotclk;
377
378 int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
379
380 if (type != DP_DS_PORT_TYPE_VGA)
381 return max_dotclk;
382
383 ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
384 intel_dp->downstream_ports);
385
386 if (ds_max_dotclk != 0)
387 max_dotclk = min(max_dotclk, ds_max_dotclk);
388
389 return max_dotclk;
390}
391
4ba285d4 392static int cnl_max_source_rate(struct intel_dp *intel_dp)
53ddb3cd
RV		 393{
394 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
395 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
396 enum port port = dig_port->base.port;
397
398 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
399
400 /* Low voltage SKUs are limited to max of 5.4G */
401 if (voltage == VOLTAGE_INFO_0_85V)
4ba285d4 402 return 540000;
53ddb3cd
RV		 403
404 /* For this SKU 8.1G is supported in all ports */
405 if (IS_CNL_WITH_PORT_F(dev_priv))
4ba285d4 406 return 810000;
53ddb3cd 407
3758d968 408 /* For other SKUs, max rate on ports A and D is 5.4G */
53ddb3cd 409 if (port == PORT_A || port == PORT_D)
4ba285d4 410 return 540000;
53ddb3cd 411
4ba285d4 412 return 810000;
53ddb3cd
RV		 413}
414
46b527d1
MN		 415static int icl_max_source_rate(struct intel_dp *intel_dp)
416{
417 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
418 enum port port = dig_port->base.port;
419
420 if (port == PORT_B)
421 return 540000;
422
423 return 810000;
424}
425
55cfc580
JN		 426static void
427intel_dp_set_source_rates(struct intel_dp *intel_dp)
40dba341 428{
229675d5
JN		 429 /* The values must be in increasing order */
430 static const int cnl_rates[] = {
431 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
432 };
433 static const int bxt_rates[] = {
434 162000, 216000, 243000, 270000, 324000, 432000, 540000
435 };
436 static const int skl_rates[] = {
437 162000, 216000, 270000, 324000, 432000, 540000
438 };
439 static const int hsw_rates[] = {
440 162000, 270000, 540000
441 };
442 static const int g4x_rates[] = {
443 162000, 270000
444 };
40dba341
NM		 445 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
446 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
99b91bda
JN		 447 const struct ddi_vbt_port_info *info =
448 &dev_priv->vbt.ddi_port_info[dig_port->base.port];
55cfc580 449 const int *source_rates;
99b91bda 450 int size, max_rate = 0, vbt_max_rate = info->dp_max_link_rate;
40dba341 451
55cfc580
JN		 452 /* This should only be done once */
453 WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
454
46b527d1 455 if (INTEL_GEN(dev_priv) >= 10) {
d907b665 456 source_rates = cnl_rates;
4ba285d4 457 size = ARRAY_SIZE(cnl_rates);
46b527d1
MN		 458 if (INTEL_GEN(dev_priv) == 10)
459 max_rate = cnl_max_source_rate(intel_dp);
460 else
461 max_rate = icl_max_source_rate(intel_dp);
ba1c06a5
MN		 462 } else if (IS_GEN9_LP(dev_priv)) {
463 source_rates = bxt_rates;
464 size = ARRAY_SIZE(bxt_rates);
b976dc53 465 } else if (IS_GEN9_BC(dev_priv)) {
55cfc580 466 source_rates = skl_rates;
40dba341 467 size = ARRAY_SIZE(skl_rates);
fc603ca7
JN		 468 } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
469 IS_BROADWELL(dev_priv)) {
229675d5
JN		 470 source_rates = hsw_rates;
471 size = ARRAY_SIZE(hsw_rates);
fc603ca7 472 } else {
229675d5
JN		 473 source_rates = g4x_rates;
474 size = ARRAY_SIZE(g4x_rates);
40dba341
NM		 475 }
476
99b91bda
JN		 477 if (max_rate && vbt_max_rate)
478 max_rate = min(max_rate, vbt_max_rate);
479 else if (vbt_max_rate)
480 max_rate = vbt_max_rate;
481
4ba285d4
JN		 482 if (max_rate)
483 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
484
55cfc580
JN		 485 intel_dp->source_rates = source_rates;
486 intel_dp->num_source_rates = size;
40dba341
NM		 487}
488
489static int intersect_rates(const int *source_rates, int source_len,
490 const int *sink_rates, int sink_len,
491 int *common_rates)
492{
493 int i = 0, j = 0, k = 0;
494
495 while (i < source_len && j < sink_len) {
496 if (source_rates[i] == sink_rates[j]) {
497 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
498 return k;
499 common_rates[k] = source_rates[i];
500 ++k;
501 ++i;
502 ++j;
503 } else if (source_rates[i] < sink_rates[j]) {
504 ++i;
505 } else {
506 ++j;
507 }
508 }
509 return k;
510}
511
8001b754
JN		 512/* return index of rate in rates array, or -1 if not found */
513static int intel_dp_rate_index(const int *rates, int len, int rate)
514{
515 int i;
516
517 for (i = 0; i < len; i++)
518 if (rate == rates[i])
519 return i;
520
521 return -1;
522}
523
975ee5fc 524static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
40dba341 525{
975ee5fc 526 WARN_ON(!intel_dp->num_source_rates || !intel_dp->num_sink_rates);
40dba341 527
975ee5fc
JN		 528 intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
529 intel_dp->num_source_rates,
530 intel_dp->sink_rates,
531 intel_dp->num_sink_rates,
532 intel_dp->common_rates);
533
534 /* Paranoia, there should always be something in common. */
535 if (WARN_ON(intel_dp->num_common_rates == 0)) {
229675d5 536 intel_dp->common_rates[0] = 162000;
975ee5fc
JN		 537 intel_dp->num_common_rates = 1;
538 }
539}
540
1a92c70e
MN		 541static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
542 uint8_t lane_count)
14c562c0
MN		 543{
544 /*
545 * FIXME: we need to synchronize the current link parameters with
546 * hardware readout. Currently fast link training doesn't work on
547 * boot-up.
548 */
1a92c70e
MN		 549 if (link_rate == 0 ||
550 link_rate > intel_dp->max_link_rate)
14c562c0
MN		 551 return false;
552
1a92c70e
MN		 553 if (lane_count == 0 ||
554 lane_count > intel_dp_max_lane_count(intel_dp))
14c562c0
MN		 555 return false;
556
557 return true;
558}
559
fdb14d33
MN		 560int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
561 int link_rate, uint8_t lane_count)
562{
b1810a74 563 int index;
fdb14d33 564
b1810a74
JN		 565 index = intel_dp_rate_index(intel_dp->common_rates,
566 intel_dp->num_common_rates,
567 link_rate);
568 if (index > 0) {
e6c0c64a
JN		 569 intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
570 intel_dp->max_link_lane_count = lane_count;
fdb14d33 571 } else if (lane_count > 1) {
540b0b7f 572 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
e6c0c64a 573 intel_dp->max_link_lane_count = lane_count >> 1;
fdb14d33
MN		 574 } else {
575 DRM_ERROR("Link Training Unsuccessful\n");
576 return -1;
577 }
578
579 return 0;
580}
581
c19de8eb 582static enum drm_mode_status
a4fc5ed6
KP		 583intel_dp_mode_valid(struct drm_connector *connector,
584 struct drm_display_mode *mode)
585{
df0e9248 586 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 587 struct intel_connector *intel_connector = to_intel_connector(connector);
588 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 589 int target_clock = mode->clock;
590 int max_rate, mode_rate, max_lanes, max_link_clock;
70ec0645
MK		 591 int max_dotclk;
592
e4dd27aa
VS		 593 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
594 return MODE_NO_DBLESCAN;
595
70ec0645 596 max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
a4fc5ed6 597
1853a9da 598 if (intel_dp_is_edp(intel_dp) && fixed_mode) {
dd06f90e 599 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 600 return MODE_PANEL;
601
dd06f90e 602 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 603 return MODE_PANEL;
03afc4a2
DV		 604
605 target_clock = fixed_mode->clock;
7de56f43
ZY		 606 }
607
50fec21a 608 max_link_clock = intel_dp_max_link_rate(intel_dp);
eeb6324d 609 max_lanes = intel_dp_max_lane_count(intel_dp);
36008365
DV		 610
611 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
612 mode_rate = intel_dp_link_required(target_clock, 18);
613
799487f5 614 if (mode_rate > max_rate || target_clock > max_dotclk)
c4867936 615 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 616
617 if (mode->clock < 10000)
618 return MODE_CLOCK_LOW;
619
0af78a2b
DV		 620 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
621 return MODE_H_ILLEGAL;
622
a4fc5ed6
KP		 623 return MODE_OK;
624}
625
a4f1289e 626uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
a4fc5ed6
KP		 627{
628 int i;
629 uint32_t v = 0;
630
631 if (src_bytes > 4)
632 src_bytes = 4;
633 for (i = 0; i < src_bytes; i++)
634 v |= ((uint32_t) src[i]) << ((3-i) * 8);
635 return v;
636}
637
c2af70e2 638static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
a4fc5ed6
KP		 639{
640 int i;
641 if (dst_bytes > 4)
642 dst_bytes = 4;
643 for (i = 0; i < dst_bytes; i++)
644 dst[i] = src >> ((3-i) * 8);
645}
646
bf13e81b 647static void
46bd8383 648intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp);
bf13e81b 649static void
46bd8383 650intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
5d5ab2d2 651 bool force_disable_vdd);
335f752b 652static void
46bd8383 653intel_dp_pps_init(struct intel_dp *intel_dp);
bf13e81b 654
773538e8
VS		 655static void pps_lock(struct intel_dp *intel_dp)
656{
de25eb7f 657 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
773538e8
VS		 658
659 /*
40c7ae45 660 * See intel_power_sequencer_reset() why we need
773538e8
VS		 661 * a power domain reference here.
662 */
5432fcaf 663 intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
773538e8
VS		 664
665 mutex_lock(&dev_priv->pps_mutex);
666}
667
668static void pps_unlock(struct intel_dp *intel_dp)
669{
de25eb7f 670 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
773538e8
VS		 671
672 mutex_unlock(&dev_priv->pps_mutex);
673
5432fcaf 674 intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
773538e8
VS		 675}
676
961a0db0
VS		 677static void
678vlv_power_sequencer_kick(struct intel_dp *intel_dp)
679{
de25eb7f 680 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
961a0db0 681 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
961a0db0 682 enum pipe pipe = intel_dp->pps_pipe;
0047eedc
VS		 683 bool pll_enabled, release_cl_override = false;
684 enum dpio_phy phy = DPIO_PHY(pipe);
685 enum dpio_channel ch = vlv_pipe_to_channel(pipe);
961a0db0
VS		 686 uint32_t DP;
687
688 if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
e7f2af78 689 "skipping pipe %c power sequencer kick due to port %c being active\n",
8f4f2797 690 pipe_name(pipe), port_name(intel_dig_port->base.port)))
961a0db0
VS		 691 return;
692
693 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
8f4f2797 694 pipe_name(pipe), port_name(intel_dig_port->base.port));
961a0db0
VS		 695
696 /* Preserve the BIOS-computed detected bit. This is
697 * supposed to be read-only.
698 */
699 DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
700 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
701 DP |= DP_PORT_WIDTH(1);
702 DP |= DP_LINK_TRAIN_PAT_1;
703
920a14b2 704 if (IS_CHERRYVIEW(dev_priv))
59b74c49
VS		 705 DP |= DP_PIPE_SEL_CHV(pipe);
706 else
707 DP |= DP_PIPE_SEL(pipe);
961a0db0 708
d288f65f
VS		 709 pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
710
711 /*
712 * The DPLL for the pipe must be enabled for this to work.
713 * So enable temporarily it if it's not already enabled.
714 */
0047eedc 715 if (!pll_enabled) {
920a14b2 716 release_cl_override = IS_CHERRYVIEW(dev_priv) &&
0047eedc
VS		 717 !chv_phy_powergate_ch(dev_priv, phy, ch, true);
718
30ad9814 719 if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ?
3f36b937
TU		 720 &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
721 DRM_ERROR("Failed to force on pll for pipe %c!\n",
722 pipe_name(pipe));
723 return;
724 }
0047eedc 725 }
d288f65f 726
961a0db0
VS		 727 /*
728 * Similar magic as in intel_dp_enable_port().
729 * We _must_ do this port enable + disable trick
e7f2af78 730 * to make this power sequencer lock onto the port.
961a0db0
VS		 731 * Otherwise even VDD force bit won't work.
732 */
733 I915_WRITE(intel_dp->output_reg, DP);
734 POSTING_READ(intel_dp->output_reg);
735
736 I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
737 POSTING_READ(intel_dp->output_reg);
738
739 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
740 POSTING_READ(intel_dp->output_reg);
d288f65f 741
0047eedc 742 if (!pll_enabled) {
30ad9814 743 vlv_force_pll_off(dev_priv, pipe);
0047eedc
VS		 744
745 if (release_cl_override)
746 chv_phy_powergate_ch(dev_priv, phy, ch, false);
747 }
961a0db0
VS		 748}
749
9f2bdb00
VS		 750static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
751{
752 struct intel_encoder *encoder;
753 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
754
755 /*
756 * We don't have power sequencer currently.
757 * Pick one that's not used by other ports.
758 */
14aa521c
VS		 759 for_each_intel_dp(&dev_priv->drm, encoder) {
760 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
9f2bdb00
VS		 761
762 if (encoder->type == INTEL_OUTPUT_EDP) {
763 WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
764 intel_dp->active_pipe != intel_dp->pps_pipe);
765
766 if (intel_dp->pps_pipe != INVALID_PIPE)
767 pipes &= ~(1 << intel_dp->pps_pipe);
768 } else {
769 WARN_ON(intel_dp->pps_pipe != INVALID_PIPE);
770
771 if (intel_dp->active_pipe != INVALID_PIPE)
772 pipes &= ~(1 << intel_dp->active_pipe);
773 }
774 }
775
776 if (pipes == 0)
777 return INVALID_PIPE;
778
779 return ffs(pipes) - 1;
780}
781
bf13e81b
JN		 782static enum pipe
783vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
784{
de25eb7f 785 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
bf13e81b 786 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
a8c3344e 787 enum pipe pipe;
bf13e81b 788
e39b999a 789 lockdep_assert_held(&dev_priv->pps_mutex);
bf13e81b 790
a8c3344e 791 /* We should never land here with regular DP ports */
1853a9da 792 WARN_ON(!intel_dp_is_edp(intel_dp));
a8c3344e 793
9f2bdb00
VS		 794 WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
795 intel_dp->active_pipe != intel_dp->pps_pipe);
796
a4a5d2f8
VS		 797 if (intel_dp->pps_pipe != INVALID_PIPE)
798 return intel_dp->pps_pipe;
799
9f2bdb00 800 pipe = vlv_find_free_pps(dev_priv);
a4a5d2f8
VS		 801
802 /*
803 * Didn't find one. This should not happen since there
804 * are two power sequencers and up to two eDP ports.
805 */
9f2bdb00 806 if (WARN_ON(pipe == INVALID_PIPE))
a8c3344e 807 pipe = PIPE_A;
a4a5d2f8 808
46bd8383 809 vlv_steal_power_sequencer(dev_priv, pipe);
a8c3344e 810 intel_dp->pps_pipe = pipe;
a4a5d2f8
VS		 811
812 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
813 pipe_name(intel_dp->pps_pipe),
8f4f2797 814 port_name(intel_dig_port->base.port));
a4a5d2f8
VS		 815
816 /* init power sequencer on this pipe and port */
46bd8383
VS		 817 intel_dp_init_panel_power_sequencer(intel_dp);
818 intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
a4a5d2f8 819
961a0db0
VS		 820 /*
821 * Even vdd force doesn't work until we've made
822 * the power sequencer lock in on the port.
823 */
824 vlv_power_sequencer_kick(intel_dp);
a4a5d2f8
VS		 825
826 return intel_dp->pps_pipe;
827}
828
78597996
ID		 829static int
830bxt_power_sequencer_idx(struct intel_dp *intel_dp)
831{
de25eb7f 832 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
73c0fcac 833 int backlight_controller = dev_priv->vbt.backlight.controller;
78597996
ID		 834
835 lockdep_assert_held(&dev_priv->pps_mutex);
836
837 /* We should never land here with regular DP ports */
1853a9da 838 WARN_ON(!intel_dp_is_edp(intel_dp));
78597996 839
78597996 840 if (!intel_dp->pps_reset)
73c0fcac 841 return backlight_controller;
78597996
ID		 842
843 intel_dp->pps_reset = false;
844
845 /*
846 * Only the HW needs to be reprogrammed, the SW state is fixed and
847 * has been setup during connector init.
848 */
46bd8383 849 intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
78597996 850
73c0fcac 851 return backlight_controller;
78597996
ID		 852}
853
6491ab27
VS		 854typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
855 enum pipe pipe);
856
857static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
858 enum pipe pipe)
859{
44cb734c 860 return I915_READ(PP_STATUS(pipe)) & PP_ON;
6491ab27
VS		 861}
862
863static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
864 enum pipe pipe)
865{
44cb734c 866 return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD;
6491ab27
VS		 867}
868
869static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
870 enum pipe pipe)
871{
872 return true;
873}
bf13e81b 874
a4a5d2f8 875static enum pipe
6491ab27
VS		 876vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
877 enum port port,
878 vlv_pipe_check pipe_check)
a4a5d2f8
VS		 879{
880 enum pipe pipe;
bf13e81b 881
bf13e81b 882 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
44cb734c 883 u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) &
bf13e81b 884 PANEL_PORT_SELECT_MASK;
a4a5d2f8
VS		 885
886 if (port_sel != PANEL_PORT_SELECT_VLV(port))
887 continue;
888
6491ab27
VS		 889 if (!pipe_check(dev_priv, pipe))
890 continue;
891
a4a5d2f8 892 return pipe;
bf13e81b
JN		 893 }
894
a4a5d2f8
VS		 895 return INVALID_PIPE;
896}
897
898static void
899vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
900{
de25eb7f 901 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
a4a5d2f8 902 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
8f4f2797 903 enum port port = intel_dig_port->base.port;
a4a5d2f8
VS		 904
905 lockdep_assert_held(&dev_priv->pps_mutex);
906
907 /* try to find a pipe with this port selected */
6491ab27
VS		 908 /* first pick one where the panel is on */
909 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
910 vlv_pipe_has_pp_on);
911 /* didn't find one? pick one where vdd is on */
912 if (intel_dp->pps_pipe == INVALID_PIPE)
913 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
914 vlv_pipe_has_vdd_on);
915 /* didn't find one? pick one with just the correct port */
916 if (intel_dp->pps_pipe == INVALID_PIPE)
917 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
918 vlv_pipe_any);
a4a5d2f8
VS		 919
920 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
921 if (intel_dp->pps_pipe == INVALID_PIPE) {
922 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
923 port_name(port));
924 return;
bf13e81b
JN		 925 }
926
a4a5d2f8
VS		 927 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
928 port_name(port), pipe_name(intel_dp->pps_pipe));
929
46bd8383
VS		 930 intel_dp_init_panel_power_sequencer(intel_dp);
931 intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
bf13e81b
JN		 932}
933
78597996 934void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
773538e8 935{
773538e8
VS		 936 struct intel_encoder *encoder;
937
920a14b2 938 if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
cc3f90f0 939 !IS_GEN9_LP(dev_priv)))
773538e8
VS		 940 return;
941
942 /*
943 * We can't grab pps_mutex here due to deadlock with power_domain
944 * mutex when power_domain functions are called while holding pps_mutex.
945 * That also means that in order to use pps_pipe the code needs to
946 * hold both a power domain reference and pps_mutex, and the power domain
947 * reference get/put must be done while _not_ holding pps_mutex.
948 * pps_{lock,unlock}() do these steps in the correct order, so one
949 * should use them always.
950 */
951
14aa521c
VS		 952 for_each_intel_dp(&dev_priv->drm, encoder) {
953 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
7e732cac 954
9f2bdb00
VS		 955 WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
956
957 if (encoder->type != INTEL_OUTPUT_EDP)
958 continue;
959
cc3f90f0 960 if (IS_GEN9_LP(dev_priv))
78597996
ID		 961 intel_dp->pps_reset = true;
962 else
963 intel_dp->pps_pipe = INVALID_PIPE;
773538e8 964 }
bf13e81b
JN		 965}
966
8e8232d5
ID		 967struct pps_registers {
968 i915_reg_t pp_ctrl;
969 i915_reg_t pp_stat;
970 i915_reg_t pp_on;
971 i915_reg_t pp_off;
972 i915_reg_t pp_div;
973};
974
46bd8383 975static void intel_pps_get_registers(struct intel_dp *intel_dp,
8e8232d5
ID		 976 struct pps_registers *regs)
977{
de25eb7f 978 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
44cb734c
ID		 979 int pps_idx = 0;
980
8e8232d5
ID		 981 memset(regs, 0, sizeof(*regs));
982
cc3f90f0 983 if (IS_GEN9_LP(dev_priv))
44cb734c
ID		 984 pps_idx = bxt_power_sequencer_idx(intel_dp);
985 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
986 pps_idx = vlv_power_sequencer_pipe(intel_dp);
8e8232d5 987
44cb734c
ID		 988 regs->pp_ctrl = PP_CONTROL(pps_idx);
989 regs->pp_stat = PP_STATUS(pps_idx);
990 regs->pp_on = PP_ON_DELAYS(pps_idx);
991 regs->pp_off = PP_OFF_DELAYS(pps_idx);
b0d6a0f2
AS		 992 if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) &&
993 !HAS_PCH_ICP(dev_priv))
44cb734c 994 regs->pp_div = PP_DIVISOR(pps_idx);
8e8232d5
ID		 995}
996
f0f59a00
VS		 997static i915_reg_t
998_pp_ctrl_reg(struct intel_dp *intel_dp)
bf13e81b 999{
8e8232d5 1000 struct pps_registers regs;
bf13e81b 1001
46bd8383 1002 intel_pps_get_registers(intel_dp, &regs);
8e8232d5
ID		 1003
1004 return regs.pp_ctrl;
bf13e81b
JN		 1005}
1006
f0f59a00
VS		 1007static i915_reg_t
1008_pp_stat_reg(struct intel_dp *intel_dp)
bf13e81b 1009{
8e8232d5 1010 struct pps_registers regs;
bf13e81b 1011
46bd8383 1012 intel_pps_get_registers(intel_dp, &regs);
8e8232d5
ID		 1013
1014 return regs.pp_stat;
bf13e81b
JN		 1015}
1016
01527b31
CT		 1017/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
1018 This function only applicable when panel PM state is not to be tracked */
1019static int edp_notify_handler(struct notifier_block *this, unsigned long code,
1020 void *unused)
1021{
1022 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
1023 edp_notifier);
de25eb7f 1024 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
01527b31 1025
1853a9da 1026 if (!intel_dp_is_edp(intel_dp) || code != SYS_RESTART)
01527b31
CT		 1027 return 0;
1028
773538e8 1029 pps_lock(intel_dp);
e39b999a 1030
920a14b2 1031 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
e39b999a 1032 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
f0f59a00 1033 i915_reg_t pp_ctrl_reg, pp_div_reg;
649636ef 1034 u32 pp_div;
e39b999a 1035
44cb734c
ID		 1036 pp_ctrl_reg = PP_CONTROL(pipe);
1037 pp_div_reg = PP_DIVISOR(pipe);
01527b31
CT		 1038 pp_div = I915_READ(pp_div_reg);
1039 pp_div &= PP_REFERENCE_DIVIDER_MASK;
1040
1041 /* 0x1F write to PP_DIV_REG sets max cycle delay */
1042 I915_WRITE(pp_div_reg, pp_div | 0x1F);
1043 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
1044 msleep(intel_dp->panel_power_cycle_delay);
1045 }
1046
773538e8 1047 pps_unlock(intel_dp);
e39b999a 1048
01527b31
CT		 1049 return 0;
1050}
1051
4be73780 1052static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 1053{
de25eb7f 1054 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
ebf33b18 1055
e39b999a
VS		 1056 lockdep_assert_held(&dev_priv->pps_mutex);
1057
920a14b2 1058 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
9a42356b
VS		 1059 intel_dp->pps_pipe == INVALID_PIPE)
1060 return false;
1061
bf13e81b 1062 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 1063}
1064
4be73780 1065static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 1066{
de25eb7f 1067 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
ebf33b18 1068
e39b999a
VS		 1069 lockdep_assert_held(&dev_priv->pps_mutex);
1070
920a14b2 1071 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
9a42356b
VS		 1072 intel_dp->pps_pipe == INVALID_PIPE)
1073 return false;
1074
773538e8 1075 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
ebf33b18
KP		 1076}
1077
9b984dae
KP		 1078static void
1079intel_dp_check_edp(struct intel_dp *intel_dp)
1080{
de25eb7f 1081 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
ebf33b18 1082
1853a9da 1083 if (!intel_dp_is_edp(intel_dp))
9b984dae 1084 return;
453c5420 1085
4be73780 1086 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 1087 WARN(1, "eDP powered off while attempting aux channel communication.\n");
1088 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 1089 I915_READ(_pp_stat_reg(intel_dp)),
1090 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 1091 }
1092}
1093
9ee32fea 1094static uint32_t
8a29c778 1095intel_dp_aux_wait_done(struct intel_dp *intel_dp)
9ee32fea 1096{
de25eb7f 1097 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4904fa66 1098 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
9ee32fea
DV		 1099 uint32_t status;
1100 bool done;
1101
ef04f00d 1102#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
8a29c778
LDM		 1103 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
1104 msecs_to_jiffies_timeout(10));
9ee32fea 1105 if (!done)
8a29c778 1106 DRM_ERROR("dp aux hw did not signal timeout!\n");
9ee32fea
DV		 1107#undef C
1108
1109 return status;
1110}
1111
6ffb1be7 1112static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 1113{
de25eb7f 1114 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
9ee32fea 1115
a457f54b
VS		 1116 if (index)
1117 return 0;
1118
ec5b01dd
DL		 1119 /*
1120 * The clock divider is based off the hrawclk, and would like to run at
a457f54b 1121 * 2MHz. So, take the hrawclk value and divide by 2000 and use that
a4fc5ed6 1122 */
a457f54b 1123 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
ec5b01dd
DL		 1124}
1125
1126static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1127{
de25eb7f 1128 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
ec5b01dd
DL		 1129
1130 if (index)
1131 return 0;
1132
a457f54b
VS		 1133 /*
1134 * The clock divider is based off the cdclk or PCH rawclk, and would
1135 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and
1136 * divide by 2000 and use that
1137 */
449059a9 1138 if (intel_dp->aux_ch == AUX_CH_A)
49cd97a3 1139 return DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.cdclk, 2000);
e7dc33f3
VS		 1140 else
1141 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
ec5b01dd
DL		 1142}
1143
1144static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1145{
de25eb7f 1146 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
ec5b01dd 1147
449059a9 1148 if (intel_dp->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) {
2c55c336 1149 /* Workaround for non-ULT HSW */
bc86625a
CW		 1150 switch (index) {
1151 case 0: return 63;
1152 case 1: return 72;
1153 default: return 0;
1154 }
2c55c336 1155 }
a457f54b
VS		 1156
1157 return ilk_get_aux_clock_divider(intel_dp, index);
b84a1cf8
RV		 1158}
1159
b6b5e383
DL		 1160static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1161{
1162 /*
1163 * SKL doesn't need us to program the AUX clock divider (Hardware will
1164 * derive the clock from CDCLK automatically). We still implement the
1165 * get_aux_clock_divider vfunc to plug-in into the existing code.
1166 */
1167 return index ? 0 : 1;
1168}
1169
6ffb1be7 1170static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
6ffb1be7
VS		 1171 int send_bytes,
1172 uint32_t aux_clock_divider)
5ed12a19
DL		 1173{
1174 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
8652744b
TU		 1175 struct drm_i915_private *dev_priv =
1176 to_i915(intel_dig_port->base.base.dev);
5ed12a19
DL		 1177 uint32_t precharge, timeout;
1178
8652744b 1179 if (IS_GEN6(dev_priv))
5ed12a19
DL		 1180 precharge = 3;
1181 else
1182 precharge = 5;
1183
8f5f63d5 1184 if (IS_BROADWELL(dev_priv))
5ed12a19
DL		 1185 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
1186 else
1187 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
1188
1189 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 1190 DP_AUX_CH_CTL_DONE |
8a29c778 1191 DP_AUX_CH_CTL_INTERRUPT |
788d4433 1192 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 1193 timeout |
788d4433 1194 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 1195 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1196 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 1197 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 1198}
1199
b9ca5fad 1200static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
b9ca5fad
DL		 1201 int send_bytes,
1202 uint32_t unused)
1203{
6f211ed4
AS		 1204 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1205 uint32_t ret;
1206
1207 ret = DP_AUX_CH_CTL_SEND_BUSY |
1208 DP_AUX_CH_CTL_DONE |
1209 DP_AUX_CH_CTL_INTERRUPT |
1210 DP_AUX_CH_CTL_TIME_OUT_ERROR |
1211 DP_AUX_CH_CTL_TIME_OUT_MAX |
1212 DP_AUX_CH_CTL_RECEIVE_ERROR |
1213 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1214 DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
1215 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
1216
1217 if (intel_dig_port->tc_type == TC_PORT_TBT)
1218 ret |= DP_AUX_CH_CTL_TBT_IO;
1219
1220 return ret;
b9ca5fad
DL		 1221}
1222
b84a1cf8 1223static int
f7606265
VS		 1224intel_dp_aux_xfer(struct intel_dp *intel_dp,
1225 const uint8_t *send, int send_bytes,
8159c796
VS		 1226 uint8_t *recv, int recv_size,
1227 u32 aux_send_ctl_flags)
b84a1cf8
RV		 1228{
1229 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
0031fb96
TU		 1230 struct drm_i915_private *dev_priv =
1231 to_i915(intel_dig_port->base.base.dev);
4904fa66 1232 i915_reg_t ch_ctl, ch_data[5];
bc86625a 1233 uint32_t aux_clock_divider;
b84a1cf8
RV		 1234 int i, ret, recv_bytes;
1235 uint32_t status;
5ed12a19 1236 int try, clock = 0;
884f19e9
JN		 1237 bool vdd;
1238
4904fa66
VS		 1239 ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1240 for (i = 0; i < ARRAY_SIZE(ch_data); i++)
1241 ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i);
1242
773538e8 1243 pps_lock(intel_dp);
e39b999a 1244
72c3500a
VS		 1245 /*
1246 * We will be called with VDD already enabled for dpcd/edid/oui reads.
1247 * In such cases we want to leave VDD enabled and it's up to upper layers
1248 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
1249 * ourselves.
1250 */
1e0560e0 1251 vdd = edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 1252
1253 /* dp aux is extremely sensitive to irq latency, hence request the
1254 * lowest possible wakeup latency and so prevent the cpu from going into
1255 * deep sleep states.
1256 */
1257 pm_qos_update_request(&dev_priv->pm_qos, 0);
1258
1259 intel_dp_check_edp(intel_dp);
5eb08b69 1260
11bee43e
JB		 1261 /* Try to wait for any previous AUX channel activity */
1262 for (try = 0; try < 3; try++) {
ef04f00d 1263 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 1264 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1265 break;
1266 msleep(1);
1267 }
1268
1269 if (try == 3) {
02196c77
MK		 1270 static u32 last_status = -1;
1271 const u32 status = I915_READ(ch_ctl);
1272
1273 if (status != last_status) {
1274 WARN(1, "dp_aux_ch not started status 0x%08x\n",
1275 status);
1276 last_status = status;
1277 }
1278
9ee32fea
DV		 1279 ret = -EBUSY;
1280 goto out;
4f7f7b7e
CW		 1281 }
1282
46a5ae9f
PZ		 1283 /* Only 5 data registers! */
1284 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
1285 ret = -E2BIG;
1286 goto out;
1287 }
1288
ec5b01dd 1289 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
8159c796 1290 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
8159c796
VS		 1291 send_bytes,
1292 aux_clock_divider);
1293
1294 send_ctl |= aux_send_ctl_flags;
5ed12a19 1295
bc86625a
CW		 1296 /* Must try at least 3 times according to DP spec */
1297 for (try = 0; try < 5; try++) {
1298 /* Load the send data into the aux channel data registers */
1299 for (i = 0; i < send_bytes; i += 4)
4904fa66 1300 I915_WRITE(ch_data[i >> 2],
a4f1289e
RV		 1301 intel_dp_pack_aux(send + i,
1302 send_bytes - i));
bc86625a
CW		 1303
1304 /* Send the command and wait for it to complete */
5ed12a19 1305 I915_WRITE(ch_ctl, send_ctl);
bc86625a 1306
8a29c778 1307 status = intel_dp_aux_wait_done(intel_dp);
bc86625a
CW		 1308
1309 /* Clear done status and any errors */
1310 I915_WRITE(ch_ctl,
1311 status |
1312 DP_AUX_CH_CTL_DONE |
1313 DP_AUX_CH_CTL_TIME_OUT_ERROR |
1314 DP_AUX_CH_CTL_RECEIVE_ERROR);
1315
74ebf294
TP		 1316 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1317 * 400us delay required for errors and timeouts
1318 * Timeout errors from the HW already meet this
1319 * requirement so skip to next iteration
1320 */
3975f0aa
DP		 1321 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
1322 continue;
1323
74ebf294
TP		 1324 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1325 usleep_range(400, 500);
bc86625a 1326 continue;
74ebf294 1327 }
bc86625a 1328 if (status & DP_AUX_CH_CTL_DONE)
e058c945 1329 goto done;
bc86625a 1330 }
a4fc5ed6
KP		 1331 }
1332
a4fc5ed6 1333 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 1334 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 1335 ret = -EBUSY;
1336 goto out;
a4fc5ed6
KP		 1337 }
1338
e058c945 1339done:
a4fc5ed6
KP		 1340 /* Check for timeout or receive error.
1341 * Timeouts occur when the sink is not connected
1342 */
a5b3da54 1343 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 1344 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 1345 ret = -EIO;
1346 goto out;
a5b3da54 1347 }
1ae8c0a5
KP		 1348
1349 /* Timeouts occur when the device isn't connected, so they're
1350 * "normal" -- don't fill the kernel log with these */
a5b3da54 1351 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
a5570fe5 1352 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 1353 ret = -ETIMEDOUT;
1354 goto out;
a4fc5ed6
KP		 1355 }
1356
1357 /* Unload any bytes sent back from the other side */
1358 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
1359 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
14e01889
RV		 1360
1361 /*
1362 * By BSpec: "Message sizes of 0 or >20 are not allowed."
1363 * We have no idea of what happened so we return -EBUSY so
1364 * drm layer takes care for the necessary retries.
1365 */
1366 if (recv_bytes == 0 || recv_bytes > 20) {
1367 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
1368 recv_bytes);
14e01889
RV		 1369 ret = -EBUSY;
1370 goto out;
1371 }
1372
a4fc5ed6
KP		 1373 if (recv_bytes > recv_size)
1374 recv_bytes = recv_size;
0206e353 1375
4f7f7b7e 1376 for (i = 0; i < recv_bytes; i += 4)
4904fa66 1377 intel_dp_unpack_aux(I915_READ(ch_data[i >> 2]),
a4f1289e 1378 recv + i, recv_bytes - i);
a4fc5ed6 1379
9ee32fea
DV		 1380 ret = recv_bytes;
1381out:
1382 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
1383
884f19e9
JN		 1384 if (vdd)
1385 edp_panel_vdd_off(intel_dp, false);
1386
773538e8 1387 pps_unlock(intel_dp);
e39b999a 1388
9ee32fea 1389 return ret;
a4fc5ed6
KP		 1390}
1391
a6c8aff0
JN		 1392#define BARE_ADDRESS_SIZE 3
1393#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
32078b72
VS		 1394
1395static void
1396intel_dp_aux_header(u8 txbuf[HEADER_SIZE],
1397 const struct drm_dp_aux_msg *msg)
1398{
1399 txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf);
1400 txbuf[1] = (msg->address >> 8) & 0xff;
1401 txbuf[2] = msg->address & 0xff;
1402 txbuf[3] = msg->size - 1;
1403}
1404
9d1a1031
JN		 1405static ssize_t
1406intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 1407{
9d1a1031
JN		 1408 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1409 uint8_t txbuf[20], rxbuf[20];
1410 size_t txsize, rxsize;
a4fc5ed6 1411 int ret;
a4fc5ed6 1412
32078b72 1413 intel_dp_aux_header(txbuf, msg);
46a5ae9f 1414
9d1a1031
JN		 1415 switch (msg->request & ~DP_AUX_I2C_MOT) {
1416 case DP_AUX_NATIVE_WRITE:
1417 case DP_AUX_I2C_WRITE:
c1e74122 1418 case DP_AUX_I2C_WRITE_STATUS_UPDATE:
a6c8aff0 1419 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
a1ddefd8 1420 rxsize = 2; /* 0 or 1 data bytes */
f51a44b9 1421
9d1a1031
JN		 1422 if (WARN_ON(txsize > 20))
1423 return -E2BIG;
a4fc5ed6 1424
dd788090
VS		 1425 WARN_ON(!msg->buffer != !msg->size);
1426
d81a67cc
ID		 1427 if (msg->buffer)
1428 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 1429
f7606265 1430 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
8159c796 1431 rxbuf, rxsize, 0);
9d1a1031
JN		 1432 if (ret > 0) {
1433 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 1434
a1ddefd8
JN		 1435 if (ret > 1) {
1436 /* Number of bytes written in a short write. */
1437 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1438 } else {
1439 /* Return payload size. */
1440 ret = msg->size;
1441 }
9d1a1031
JN		 1442 }
1443 break;
46a5ae9f 1444
9d1a1031
JN		 1445 case DP_AUX_NATIVE_READ:
1446 case DP_AUX_I2C_READ:
a6c8aff0 1447 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 1448 rxsize = msg->size + 1;
a4fc5ed6 1449
9d1a1031
JN		 1450 if (WARN_ON(rxsize > 20))
1451 return -E2BIG;
a4fc5ed6 1452
f7606265 1453 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
8159c796 1454 rxbuf, rxsize, 0);
9d1a1031
JN		 1455 if (ret > 0) {
1456 msg->reply = rxbuf[0] >> 4;
1457 /*
1458 * Assume happy day, and copy the data. The caller is
1459 * expected to check msg->reply before touching it.
1460 *
1461 * Return payload size.
1462 */
1463 ret--;
1464 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 1465 }
9d1a1031
JN		 1466 break;
1467
1468 default:
1469 ret = -EINVAL;
1470 break;
a4fc5ed6 1471 }
f51a44b9 1472
9d1a1031 1473 return ret;
a4fc5ed6
KP		 1474}
1475
bdabdb63 1476static enum aux_ch intel_aux_ch(struct intel_dp *intel_dp)
8f7ce038 1477{
bdabdb63
VS		 1478 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1479 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1480 enum port port = encoder->port;
8f7ce038
VS		 1481 const struct ddi_vbt_port_info *info =
1482 &dev_priv->vbt.ddi_port_info[port];
bdabdb63 1483 enum aux_ch aux_ch;
8f7ce038
VS		 1484
1485 if (!info->alternate_aux_channel) {
bdabdb63
VS		 1486 aux_ch = (enum aux_ch) port;
1487
8f7ce038 1488 DRM_DEBUG_KMS("using AUX %c for port %c (platform default)\n",
bdabdb63
VS		 1489 aux_ch_name(aux_ch), port_name(port));
1490 return aux_ch;
8f7ce038
VS		 1491 }
1492
1493 switch (info->alternate_aux_channel) {
1494 case DP_AUX_A:
bdabdb63 1495 aux_ch = AUX_CH_A;
8f7ce038
VS		 1496 break;
1497 case DP_AUX_B:
bdabdb63 1498 aux_ch = AUX_CH_B;
8f7ce038
VS		 1499 break;
1500 case DP_AUX_C:
bdabdb63 1501 aux_ch = AUX_CH_C;
8f7ce038
VS		 1502 break;
1503 case DP_AUX_D:
bdabdb63 1504 aux_ch = AUX_CH_D;
8f7ce038 1505 break;
bb187e93
JA		 1506 case DP_AUX_E:
1507 aux_ch = AUX_CH_E;
1508 break;
a324fcac 1509 case DP_AUX_F:
bdabdb63 1510 aux_ch = AUX_CH_F;
a324fcac 1511 break;
8f7ce038
VS		 1512 default:
1513 MISSING_CASE(info->alternate_aux_channel);
bdabdb63 1514 aux_ch = AUX_CH_A;
8f7ce038
VS		 1515 break;
1516 }
1517
1518 DRM_DEBUG_KMS("using AUX %c for port %c (VBT)\n",
bdabdb63 1519 aux_ch_name(aux_ch), port_name(port));
8f7ce038 1520
bdabdb63
VS		 1521 return aux_ch;
1522}
1523
1524static enum intel_display_power_domain
1525intel_aux_power_domain(struct intel_dp *intel_dp)
1526{
1527 switch (intel_dp->aux_ch) {
1528 case AUX_CH_A:
1529 return POWER_DOMAIN_AUX_A;
1530 case AUX_CH_B:
1531 return POWER_DOMAIN_AUX_B;
1532 case AUX_CH_C:
1533 return POWER_DOMAIN_AUX_C;
1534 case AUX_CH_D:
1535 return POWER_DOMAIN_AUX_D;
bb187e93
JA		 1536 case AUX_CH_E:
1537 return POWER_DOMAIN_AUX_E;
bdabdb63
VS		 1538 case AUX_CH_F:
1539 return POWER_DOMAIN_AUX_F;
1540 default:
1541 MISSING_CASE(intel_dp->aux_ch);
1542 return POWER_DOMAIN_AUX_A;
1543 }
8f7ce038
VS		 1544}
1545
4904fa66 1546static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)
da00bdcf 1547{
de25eb7f 1548 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4904fa66
VS		 1549 enum aux_ch aux_ch = intel_dp->aux_ch;
1550
bdabdb63
VS		 1551 switch (aux_ch) {
1552 case AUX_CH_B:
1553 case AUX_CH_C:
1554 case AUX_CH_D:
1555 return DP_AUX_CH_CTL(aux_ch);
da00bdcf 1556 default:
bdabdb63
VS		 1557 MISSING_CASE(aux_ch);
1558 return DP_AUX_CH_CTL(AUX_CH_B);
da00bdcf
VS		 1559 }
1560}
1561
4904fa66 1562static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)
330e20ec 1563{
de25eb7f 1564 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4904fa66
VS		 1565 enum aux_ch aux_ch = intel_dp->aux_ch;
1566
bdabdb63
VS		 1567 switch (aux_ch) {
1568 case AUX_CH_B:
1569 case AUX_CH_C:
1570 case AUX_CH_D:
1571 return DP_AUX_CH_DATA(aux_ch, index);
330e20ec 1572 default:
bdabdb63
VS		 1573 MISSING_CASE(aux_ch);
1574 return DP_AUX_CH_DATA(AUX_CH_B, index);
330e20ec
VS		 1575 }
1576}
1577
4904fa66 1578static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)
bdabdb63 1579{
de25eb7f 1580 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4904fa66
VS		 1581 enum aux_ch aux_ch = intel_dp->aux_ch;
1582
bdabdb63
VS		 1583 switch (aux_ch) {
1584 case AUX_CH_A:
1585 return DP_AUX_CH_CTL(aux_ch);
1586 case AUX_CH_B:
1587 case AUX_CH_C:
1588 case AUX_CH_D:
1589 return PCH_DP_AUX_CH_CTL(aux_ch);
da00bdcf 1590 default:
bdabdb63
VS		 1591 MISSING_CASE(aux_ch);
1592 return DP_AUX_CH_CTL(AUX_CH_A);
da00bdcf
VS		 1593 }
1594}
1595
4904fa66 1596static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index)
bdabdb63 1597{
de25eb7f 1598 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4904fa66
VS		 1599 enum aux_ch aux_ch = intel_dp->aux_ch;
1600
bdabdb63
VS		 1601 switch (aux_ch) {
1602 case AUX_CH_A:
1603 return DP_AUX_CH_DATA(aux_ch, index);
1604 case AUX_CH_B:
1605 case AUX_CH_C:
1606 case AUX_CH_D:
1607 return PCH_DP_AUX_CH_DATA(aux_ch, index);
330e20ec 1608 default:
bdabdb63
VS		 1609 MISSING_CASE(aux_ch);
1610 return DP_AUX_CH_DATA(AUX_CH_A, index);
330e20ec
VS		 1611 }
1612}
1613
4904fa66 1614static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
bdabdb63 1615{
de25eb7f 1616 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4904fa66
VS		 1617 enum aux_ch aux_ch = intel_dp->aux_ch;
1618
bdabdb63
VS		 1619 switch (aux_ch) {
1620 case AUX_CH_A:
1621 case AUX_CH_B:
1622 case AUX_CH_C:
1623 case AUX_CH_D:
bb187e93 1624 case AUX_CH_E:
bdabdb63
VS		 1625 case AUX_CH_F:
1626 return DP_AUX_CH_CTL(aux_ch);
da00bdcf 1627 default:
bdabdb63
VS		 1628 MISSING_CASE(aux_ch);
1629 return DP_AUX_CH_CTL(AUX_CH_A);
da00bdcf
VS		 1630 }
1631}
1632
4904fa66 1633static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
bdabdb63 1634{
de25eb7f 1635 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4904fa66
VS		 1636 enum aux_ch aux_ch = intel_dp->aux_ch;
1637
bdabdb63
VS		 1638 switch (aux_ch) {
1639 case AUX_CH_A:
1640 case AUX_CH_B:
1641 case AUX_CH_C:
1642 case AUX_CH_D:
bb187e93 1643 case AUX_CH_E:
bdabdb63
VS		 1644 case AUX_CH_F:
1645 return DP_AUX_CH_DATA(aux_ch, index);
330e20ec 1646 default:
bdabdb63
VS		 1647 MISSING_CASE(aux_ch);
1648 return DP_AUX_CH_DATA(AUX_CH_A, index);
330e20ec
VS		 1649 }
1650}
1651
91e939ae
VS		 1652static void
1653intel_dp_aux_fini(struct intel_dp *intel_dp)
1654{
1655 kfree(intel_dp->aux.name);
1656}
1657
1658static void
1659intel_dp_aux_init(struct intel_dp *intel_dp)
330e20ec 1660{
de25eb7f 1661 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
91e939ae
VS		 1662 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1663
1664 intel_dp->aux_ch = intel_aux_ch(intel_dp);
1665 intel_dp->aux_power_domain = intel_aux_power_domain(intel_dp);
330e20ec 1666
4904fa66
VS		 1667 if (INTEL_GEN(dev_priv) >= 9) {
1668 intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg;
1669 intel_dp->aux_ch_data_reg = skl_aux_data_reg;
1670 } else if (HAS_PCH_SPLIT(dev_priv)) {
1671 intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg;
1672 intel_dp->aux_ch_data_reg = ilk_aux_data_reg;
1673 } else {
1674 intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg;
1675 intel_dp->aux_ch_data_reg = g4x_aux_data_reg;
1676 }
330e20ec 1677
91e939ae
VS		 1678 if (INTEL_GEN(dev_priv) >= 9)
1679 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
1680 else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
1681 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
1682 else if (HAS_PCH_SPLIT(dev_priv))
1683 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
1684 else
1685 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
bdabdb63 1686
91e939ae
VS		 1687 if (INTEL_GEN(dev_priv) >= 9)
1688 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
1689 else
1690 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
ab2c0672 1691
7a418e34 1692 drm_dp_aux_init(&intel_dp->aux);
8316f337 1693
7a418e34 1694 /* Failure to allocate our preferred name is not critical */
bdabdb63
VS		 1695 intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c",
1696 port_name(encoder->port));
9d1a1031 1697 intel_dp->aux.transfer = intel_dp_aux_transfer;
a4fc5ed6
KP		 1698}
1699
e588fa18 1700bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
ed63baaf 1701{
fc603ca7 1702 int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
e588fa18 1703
fc603ca7 1704 return max_rate >= 540000;
ed63baaf
TS		 1705}
1706
2edd5327
MN		 1707bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp)
1708{
1709 int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1710
1711 return max_rate >= 810000;
1712}
1713
c6bb3538
DV		 1714static void
1715intel_dp_set_clock(struct intel_encoder *encoder,
840b32b7 1716 struct intel_crtc_state *pipe_config)
c6bb3538 1717{
2f773477 1718 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
9dd4ffdf
CML		 1719 const struct dp_link_dpll *divisor = NULL;
1720 int i, count = 0;
c6bb3538 1721
9beb5fea 1722 if (IS_G4X(dev_priv)) {
45101e93
VS		 1723 divisor = g4x_dpll;
1724 count = ARRAY_SIZE(g4x_dpll);
6e266956 1725 } else if (HAS_PCH_SPLIT(dev_priv)) {
9dd4ffdf
CML		 1726 divisor = pch_dpll;
1727 count = ARRAY_SIZE(pch_dpll);
920a14b2 1728 } else if (IS_CHERRYVIEW(dev_priv)) {
ef9348c8
CML		 1729 divisor = chv_dpll;
1730 count = ARRAY_SIZE(chv_dpll);
11a914c2 1731 } else if (IS_VALLEYVIEW(dev_priv)) {
65ce4bf5
CML		 1732 divisor = vlv_dpll;
1733 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 1734 }
9dd4ffdf
CML		 1735
1736 if (divisor && count) {
1737 for (i = 0; i < count; i++) {
840b32b7 1738 if (pipe_config->port_clock == divisor[i].clock) {
9dd4ffdf
CML		 1739 pipe_config->dpll = divisor[i].dpll;
1740 pipe_config->clock_set = true;
1741 break;
1742 }
1743 }
c6bb3538
DV		 1744 }
1745}
1746
0336400e
VS		 1747static void snprintf_int_array(char *str, size_t len,
1748 const int *array, int nelem)
1749{
1750 int i;
1751
1752 str[0] = '\0';
1753
1754 for (i = 0; i < nelem; i++) {
b2f505be 1755 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
0336400e
VS		 1756 if (r >= len)
1757 return;
1758 str += r;
1759 len -= r;
1760 }
1761}
1762
1763static void intel_dp_print_rates(struct intel_dp *intel_dp)
1764{
0336400e
VS		 1765 char str[128]; /* FIXME: too big for stack? */
1766
1767 if ((drm_debug & DRM_UT_KMS) == 0)
1768 return;
1769
55cfc580
JN		 1770 snprintf_int_array(str, sizeof(str),
1771 intel_dp->source_rates, intel_dp->num_source_rates);
0336400e
VS		 1772 DRM_DEBUG_KMS("source rates: %s\n", str);
1773
68f357cb
JN		 1774 snprintf_int_array(str, sizeof(str),
1775 intel_dp->sink_rates, intel_dp->num_sink_rates);
0336400e
VS		 1776 DRM_DEBUG_KMS("sink rates: %s\n", str);
1777
975ee5fc
JN		 1778 snprintf_int_array(str, sizeof(str),
1779 intel_dp->common_rates, intel_dp->num_common_rates);
94ca719e 1780 DRM_DEBUG_KMS("common rates: %s\n", str);
0336400e
VS		 1781}
1782
50fec21a
VS		 1783int
1784intel_dp_max_link_rate(struct intel_dp *intel_dp)
1785{
50fec21a
VS		 1786 int len;
1787
e6c0c64a 1788 len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
50fec21a
VS		 1789 if (WARN_ON(len <= 0))
1790 return 162000;
1791
975ee5fc 1792 return intel_dp->common_rates[len - 1];
50fec21a
VS		 1793}
1794
ed4e9c1d
VS		 1795int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1796{
8001b754
JN		 1797 int i = intel_dp_rate_index(intel_dp->sink_rates,
1798 intel_dp->num_sink_rates, rate);
b5c72b20
JN		 1799
1800 if (WARN_ON(i < 0))
1801 i = 0;
1802
1803 return i;
ed4e9c1d
VS		 1804}
1805
94223d04
ACO		 1806void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1807 uint8_t *link_bw, uint8_t *rate_select)
04a60f9f 1808{
68f357cb
JN		 1809 /* eDP 1.4 rate select method. */
1810 if (intel_dp->use_rate_select) {
04a60f9f
VS		 1811 *link_bw = 0;
1812 *rate_select =
1813 intel_dp_rate_select(intel_dp, port_clock);
1814 } else {
1815 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1816 *rate_select = 0;
1817 }
1818}
1819
7c2781e4
JN		 1820struct link_config_limits {
1821 int min_clock, max_clock;
1822 int min_lane_count, max_lane_count;
1823 int min_bpp, max_bpp;
1824};
1825
f580bea9
JN		 1826static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
1827 struct intel_crtc_state *pipe_config)
f9bb705e 1828{
de25eb7f 1829 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
ef32659a 1830 struct intel_connector *intel_connector = intel_dp->attached_connector;
f9bb705e
MK		 1831 int bpp, bpc;
1832
1833 bpp = pipe_config->pipe_bpp;
1834 bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports);
1835
1836 if (bpc > 0)
1837 bpp = min(bpp, 3*bpc);
1838
ef32659a
JN		 1839 if (intel_dp_is_edp(intel_dp)) {
1840 /* Get bpp from vbt only for panels that dont have bpp in edid */
1841 if (intel_connector->base.display_info.bpc == 0 &&
1842 dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp) {
1843 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1844 dev_priv->vbt.edp.bpp);
1845 bpp = dev_priv->vbt.edp.bpp;
1846 }
1847 }
1848
f9bb705e
MK		 1849 return bpp;
1850}
1851
a4971453
JN		 1852/* Adjust link config limits based on compliance test requests. */
1853static void
1854intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
1855 struct intel_crtc_state *pipe_config,
1856 struct link_config_limits *limits)
1857{
1858 /* For DP Compliance we override the computed bpp for the pipe */
1859 if (intel_dp->compliance.test_data.bpc != 0) {
1860 int bpp = 3 * intel_dp->compliance.test_data.bpc;
1861
1862 limits->min_bpp = limits->max_bpp = bpp;
1863 pipe_config->dither_force_disable = bpp == 6 * 3;
1864
1865 DRM_DEBUG_KMS("Setting pipe_bpp to %d\n", bpp);
1866 }
1867
1868 /* Use values requested by Compliance Test Request */
1869 if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1870 int index;
1871
1872 /* Validate the compliance test data since max values
1873 * might have changed due to link train fallback.
1874 */
1875 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1876 intel_dp->compliance.test_lane_count)) {
1877 index = intel_dp_rate_index(intel_dp->common_rates,
1878 intel_dp->num_common_rates,
1879 intel_dp->compliance.test_link_rate);
1880 if (index >= 0)
1881 limits->min_clock = limits->max_clock = index;
1882 limits->min_lane_count = limits->max_lane_count =
1883 intel_dp->compliance.test_lane_count;
1884 }
1885 }
1886}
1887
3acd115d
JN		 1888/* Optimize link config in order: max bpp, min clock, min lanes */
1889static bool
1890intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
1891 struct intel_crtc_state *pipe_config,
1892 const struct link_config_limits *limits)
1893{
1894 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1895 int bpp, clock, lane_count;
1896 int mode_rate, link_clock, link_avail;
1897
1898 for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
1899 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1900 bpp);
1901
1902 for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
1903 for (lane_count = limits->min_lane_count;
1904 lane_count <= limits->max_lane_count;
1905 lane_count <<= 1) {
1906 link_clock = intel_dp->common_rates[clock];
1907 link_avail = intel_dp_max_data_rate(link_clock,
1908 lane_count);
1909
1910 if (mode_rate <= link_avail) {
1911 pipe_config->lane_count = lane_count;
1912 pipe_config->pipe_bpp = bpp;
1913 pipe_config->port_clock = link_clock;
1914
1915 return true;
1916 }
1917 }
1918 }
1919 }
1920
1921 return false;
1922}
1923
7769db58
JN		 1924/* Optimize link config in order: max bpp, min lanes, min clock */
1925static bool
1926intel_dp_compute_link_config_fast(struct intel_dp *intel_dp,
1927 struct intel_crtc_state *pipe_config,
1928 const struct link_config_limits *limits)
1929{
1930 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1931 int bpp, clock, lane_count;
1932 int mode_rate, link_clock, link_avail;
1933
1934 for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
1935 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1936 bpp);
1937
1938 for (lane_count = limits->min_lane_count;
1939 lane_count <= limits->max_lane_count;
1940 lane_count <<= 1) {
1941 for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
1942 link_clock = intel_dp->common_rates[clock];
1943 link_avail = intel_dp_max_data_rate(link_clock,
1944 lane_count);
1945
1946 if (mode_rate <= link_avail) {
1947 pipe_config->lane_count = lane_count;
1948 pipe_config->pipe_bpp = bpp;
1949 pipe_config->port_clock = link_clock;
1950
1951 return true;
1952 }
1953 }
1954 }
1955 }
1956
1957 return false;
1958}
1959
981a63eb
JN		 1960static bool
1961intel_dp_compute_link_config(struct intel_encoder *encoder,
1962 struct intel_crtc_state *pipe_config)
a4fc5ed6 1963{
2d112de7 1964 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5bfe2ac0 1965 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
7c2781e4 1966 struct link_config_limits limits;
94ca719e 1967 int common_len;
7c2781e4 1968
975ee5fc 1969 common_len = intel_dp_common_len_rate_limit(intel_dp,
e6c0c64a 1970 intel_dp->max_link_rate);
a8f3ef61
SJ		 1971
1972 /* No common link rates between source and sink */
94ca719e 1973 WARN_ON(common_len <= 0);
a8f3ef61 1974
7c2781e4
JN		 1975 limits.min_clock = 0;
1976 limits.max_clock = common_len - 1;
1977
1978 limits.min_lane_count = 1;
1979 limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
1980
1981 limits.min_bpp = 6 * 3;
1982 limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
a4fc5ed6 1983
7769db58 1984 if (intel_dp_is_edp(intel_dp) && intel_dp->edp_dpcd[0] < DP_EDP_14) {
344c5bbc
JN		 1985 /*
1986 * Use the maximum clock and number of lanes the eDP panel
7769db58
JN		 1987 * advertizes being capable of. The eDP 1.3 and earlier panels
1988 * are generally designed to support only a single clock and
1989 * lane configuration, and typically these values correspond to
1990 * the native resolution of the panel. With eDP 1.4 rate select
1991 * and DSC, this is decreasingly the case, and we need to be
1992 * able to select less than maximum link config.
344c5bbc 1993 */
7c2781e4
JN		 1994 limits.min_lane_count = limits.max_lane_count;
1995 limits.min_clock = limits.max_clock;
7984211e 1996 }
657445fe 1997
a4971453
JN		 1998 intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
1999
7c2781e4
JN		 2000 DRM_DEBUG_KMS("DP link computation with max lane count %i "
2001 "max rate %d max bpp %d pixel clock %iKHz\n",
2002 limits.max_lane_count,
2003 intel_dp->common_rates[limits.max_clock],
2004 limits.max_bpp, adjusted_mode->crtc_clock);
2005
7769db58
JN		 2006 if (intel_dp_is_edp(intel_dp)) {
2007 /*
2008 * Optimize for fast and narrow. eDP 1.3 section 3.3 and eDP 1.4
2009 * section A.1: "It is recommended that the minimum number of
2010 * lanes be used, using the minimum link rate allowed for that
2011 * lane configuration."
2012 *
2013 * Note that we use the max clock and lane count for eDP 1.3 and
2014 * earlier, and fast vs. wide is irrelevant.
2015 */
2016 if (!intel_dp_compute_link_config_fast(intel_dp, pipe_config,
2017 &limits))
2018 return false;
2019 } else {
2020 /* Optimize for slow and wide. */
2021 if (!intel_dp_compute_link_config_wide(intel_dp, pipe_config,
2022 &limits))
2023 return false;
2024 }
981a63eb
JN		 2025
2026 DRM_DEBUG_KMS("DP lane count %d clock %d bpp %d\n",
3acd115d
JN		 2027 pipe_config->lane_count, pipe_config->port_clock,
2028 pipe_config->pipe_bpp);
2029
2030 DRM_DEBUG_KMS("DP link rate required %i available %i\n",
2031 intel_dp_link_required(adjusted_mode->crtc_clock,
2032 pipe_config->pipe_bpp),
2033 intel_dp_max_data_rate(pipe_config->port_clock,
2034 pipe_config->lane_count));
981a63eb
JN		 2035
2036 return true;
2037}
2038
2039bool
2040intel_dp_compute_config(struct intel_encoder *encoder,
2041 struct intel_crtc_state *pipe_config,
2042 struct drm_connector_state *conn_state)
2043{
2044 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2045 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2046 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2047 enum port port = encoder->port;
2048 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
2049 struct intel_connector *intel_connector = intel_dp->attached_connector;
2050 struct intel_digital_connector_state *intel_conn_state =
2051 to_intel_digital_connector_state(conn_state);
53ca2edc
LS		 2052 bool constant_n = drm_dp_has_quirk(&intel_dp->desc,
2053 DP_DPCD_QUIRK_CONSTANT_N);
981a63eb
JN		 2054
2055 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
2056 pipe_config->has_pch_encoder = true;
2057
2058 pipe_config->has_drrs = false;
2059 if (IS_G4X(dev_priv) || port == PORT_A)
2060 pipe_config->has_audio = false;
2061 else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2062 pipe_config->has_audio = intel_dp->has_audio;
2063 else
2064 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;
2065
2066 if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
d93fa1b4
JN		 2067 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
2068 adjusted_mode);
981a63eb
JN		 2069
2070 if (INTEL_GEN(dev_priv) >= 9) {
2071 int ret;
2072
2073 ret = skl_update_scaler_crtc(pipe_config);
2074 if (ret)
2075 return ret;
2076 }
2077
2078 if (HAS_GMCH_DISPLAY(dev_priv))
2079 intel_gmch_panel_fitting(intel_crtc, pipe_config,
2080 conn_state->scaling_mode);
2081 else
2082 intel_pch_panel_fitting(intel_crtc, pipe_config,
2083 conn_state->scaling_mode);
2084 }
2085
e4dd27aa
VS		 2086 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2087 return false;
2088
929168c5 2089 if (HAS_GMCH_DISPLAY(dev_priv) &&
981a63eb
JN		 2090 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
2091 return false;
2092
2093 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2094 return false;
2095
2096 if (!intel_dp_compute_link_config(encoder, pipe_config))
2097 return false;
2098
8f647a01 2099 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
55bc60db
VS		 2100 /*
2101 * See:
2102 * CEA-861-E - 5.1 Default Encoding Parameters
2103 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
2104 */
0f2a2a75 2105 pipe_config->limited_color_range =
981a63eb 2106 pipe_config->pipe_bpp != 18 &&
c8127cf0
VS		 2107 drm_default_rgb_quant_range(adjusted_mode) ==
2108 HDMI_QUANTIZATION_RANGE_LIMITED;
0f2a2a75
VS		 2109 } else {
2110 pipe_config->limited_color_range =
8f647a01 2111 intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
55bc60db
VS		 2112 }
2113
981a63eb 2114 intel_link_compute_m_n(pipe_config->pipe_bpp, pipe_config->lane_count,
241bfc38
DL		 2115 adjusted_mode->crtc_clock,
2116 pipe_config->port_clock,
b31e85ed 2117 &pipe_config->dp_m_n,
53ca2edc 2118 constant_n);
9d1a455b 2119
439d7ac0 2120 if (intel_connector->panel.downclock_mode != NULL &&
96178eeb 2121 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
f769cd24 2122 pipe_config->has_drrs = true;
981a63eb
JN		 2123 intel_link_compute_m_n(pipe_config->pipe_bpp,
2124 pipe_config->lane_count,
2125 intel_connector->panel.downclock_mode->clock,
2126 pipe_config->port_clock,
2127 &pipe_config->dp_m2_n2,
53ca2edc 2128 constant_n);
439d7ac0
PB		 2129 }
2130
4f8036a2 2131 if (!HAS_DDI(dev_priv))
840b32b7 2132 intel_dp_set_clock(encoder, pipe_config);
c6bb3538 2133
4d90f2d5
VS		 2134 intel_psr_compute_config(intel_dp, pipe_config);
2135
03afc4a2 2136 return true;
a4fc5ed6
KP		 2137}
2138
901c2daf 2139void intel_dp_set_link_params(struct intel_dp *intel_dp,
dfa10480
ACO		 2140 int link_rate, uint8_t lane_count,
2141 bool link_mst)
901c2daf 2142{
edb2e530 2143 intel_dp->link_trained = false;
dfa10480
ACO		 2144 intel_dp->link_rate = link_rate;
2145 intel_dp->lane_count = lane_count;
2146 intel_dp->link_mst = link_mst;
901c2daf
VS		 2147}
2148
85cb48a1 2149static void intel_dp_prepare(struct intel_encoder *encoder,
5f88a9c6 2150 const struct intel_crtc_state *pipe_config)
a4fc5ed6 2151{
2f773477 2152 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
b934223d 2153 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
8f4f2797 2154 enum port port = encoder->port;
adc10304 2155 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
85cb48a1 2156 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
a4fc5ed6 2157
dfa10480
ACO		 2158 intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
2159 pipe_config->lane_count,
2160 intel_crtc_has_type(pipe_config,
2161 INTEL_OUTPUT_DP_MST));
901c2daf 2162
417e822d 2163 /*
1a2eb460 2164 * There are four kinds of DP registers:
417e822d
KP		 2165 *
2166 * IBX PCH
1a2eb460
KP		 2167 * SNB CPU
2168 * IVB CPU
417e822d
KP		 2169 * CPT PCH
2170 *
2171 * IBX PCH and CPU are the same for almost everything,
2172 * except that the CPU DP PLL is configured in this
2173 * register
2174 *
2175 * CPT PCH is quite different, having many bits moved
2176 * to the TRANS_DP_CTL register instead. That
2177 * configuration happens (oddly) in ironlake_pch_enable
2178 */
9c9e7927 2179
417e822d
KP		 2180 /* Preserve the BIOS-computed detected bit. This is
2181 * supposed to be read-only.
2182 */
2183 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 2184
417e822d 2185 /* Handle DP bits in common between all three register formats */
417e822d 2186 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
85cb48a1 2187 intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
a4fc5ed6 2188
417e822d 2189 /* Split out the IBX/CPU vs CPT settings */
32f9d658 2190
b752e995 2191 if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
1a2eb460
KP		 2192 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2193 intel_dp->DP |= DP_SYNC_HS_HIGH;
2194 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2195 intel_dp->DP |= DP_SYNC_VS_HIGH;
2196 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2197
6aba5b6c 2198 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 2199 intel_dp->DP |= DP_ENHANCED_FRAMING;
2200
59b74c49 2201 intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe);
6e266956 2202 } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
e3ef4479
VS		 2203 u32 trans_dp;
2204
39e5fa88 2205 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
e3ef4479
VS		 2206
2207 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2208 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2209 trans_dp |= TRANS_DP_ENH_FRAMING;
2210 else
2211 trans_dp &= ~TRANS_DP_ENH_FRAMING;
2212 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
39e5fa88 2213 } else {
c99f53f7 2214 if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
0f2a2a75 2215 intel_dp->DP |= DP_COLOR_RANGE_16_235;
417e822d
KP		 2216
2217 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2218 intel_dp->DP |= DP_SYNC_HS_HIGH;
2219 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2220 intel_dp->DP |= DP_SYNC_VS_HIGH;
2221 intel_dp->DP |= DP_LINK_TRAIN_OFF;
2222
6aba5b6c 2223 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 2224 intel_dp->DP |= DP_ENHANCED_FRAMING;
2225
920a14b2 2226 if (IS_CHERRYVIEW(dev_priv))
59b74c49
VS		 2227 intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);
2228 else
2229 intel_dp->DP |= DP_PIPE_SEL(crtc->pipe);
32f9d658 2230 }
a4fc5ed6
KP		 2231}
2232
ffd6749d
PZ		 2233#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
2234#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 2235
1a5ef5b7
PZ		 2236#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
2237#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 2238
ffd6749d
PZ		 2239#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
2240#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 2241
46bd8383 2242static void intel_pps_verify_state(struct intel_dp *intel_dp);
de9c1b6b 2243
4be73780 2244static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 2245 u32 mask,
2246 u32 value)
bd943159 2247{
de25eb7f 2248 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
f0f59a00 2249 i915_reg_t pp_stat_reg, pp_ctrl_reg;
453c5420 2250
e39b999a
VS		 2251 lockdep_assert_held(&dev_priv->pps_mutex);
2252
46bd8383 2253 intel_pps_verify_state(intel_dp);
de9c1b6b 2254
bf13e81b
JN		 2255 pp_stat_reg = _pp_stat_reg(intel_dp);
2256 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 2257
99ea7127 2258 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 2259 mask, value,
2260 I915_READ(pp_stat_reg),
2261 I915_READ(pp_ctrl_reg));
32ce697c 2262
9036ff06
CW		 2263 if (intel_wait_for_register(dev_priv,
2264 pp_stat_reg, mask, value,
2265 5000))
99ea7127 2266 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 2267 I915_READ(pp_stat_reg),
2268 I915_READ(pp_ctrl_reg));
54c136d4
CW		 2269
2270 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 2271}
32ce697c 2272
4be73780 2273static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 2274{
2275 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 2276 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 2277}
2278
4be73780 2279static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 2280{
2281 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 2282 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 2283}
2284
4be73780 2285static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127 2286{
d28d4731
AK		 2287 ktime_t panel_power_on_time;
2288 s64 panel_power_off_duration;
2289
99ea7127 2290 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c 2291
d28d4731
AK		 2292 /* take the difference of currrent time and panel power off time
2293 * and then make panel wait for t11_t12 if needed. */
2294 panel_power_on_time = ktime_get_boottime();
2295 panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
2296
dce56b3c
PZ		 2297 /* When we disable the VDD override bit last we have to do the manual
2298 * wait. */
d28d4731
AK		 2299 if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
2300 wait_remaining_ms_from_jiffies(jiffies,
2301 intel_dp->panel_power_cycle_delay - panel_power_off_duration);
dce56b3c 2302
4be73780 2303 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 2304}
2305
4be73780 2306static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 2307{
2308 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
2309 intel_dp->backlight_on_delay);
2310}
2311
4be73780 2312static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 2313{
2314 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
2315 intel_dp->backlight_off_delay);
2316}
99ea7127 2317
832dd3c1
KP		 2318/* Read the current pp_control value, unlocking the register if it
2319 * is locked
2320 */
2321
453c5420 2322static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 2323{
de25eb7f 2324 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
453c5420 2325 u32 control;
832dd3c1 2326
e39b999a
VS		 2327 lockdep_assert_held(&dev_priv->pps_mutex);
2328
bf13e81b 2329 control = I915_READ(_pp_ctrl_reg(intel_dp));
8090ba8c
ID		 2330 if (WARN_ON(!HAS_DDI(dev_priv) &&
2331 (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
b0a08bec
VK		 2332 control &= ~PANEL_UNLOCK_MASK;
2333 control |= PANEL_UNLOCK_REGS;
2334 }
832dd3c1 2335 return control;
bd943159
KP		 2336}
2337
951468f3
VS		 2338/*
2339 * Must be paired with edp_panel_vdd_off().
2340 * Must hold pps_mutex around the whole on/off sequence.
2341 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2342 */
1e0560e0 2343static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 2344{
de25eb7f 2345 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4e6e1a54 2346 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5d613501 2347 u32 pp;
f0f59a00 2348 i915_reg_t pp_stat_reg, pp_ctrl_reg;
adddaaf4 2349 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 2350
e39b999a
VS		 2351 lockdep_assert_held(&dev_priv->pps_mutex);
2352
1853a9da 2353 if (!intel_dp_is_edp(intel_dp))
adddaaf4 2354 return false;
bd943159 2355
2c623c11 2356 cancel_delayed_work(&intel_dp->panel_vdd_work);
bd943159 2357 intel_dp->want_panel_vdd = true;
99ea7127 2358
4be73780 2359 if (edp_have_panel_vdd(intel_dp))
adddaaf4 2360 return need_to_disable;
b0665d57 2361
5432fcaf 2362 intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
e9cb81a2 2363
3936fcf4 2364 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
8f4f2797 2365 port_name(intel_dig_port->base.port));
bd943159 2366
4be73780
DV		 2367 if (!edp_have_panel_power(intel_dp))
2368 wait_panel_power_cycle(intel_dp);
99ea7127 2369
453c5420 2370 pp = ironlake_get_pp_control(intel_dp);
5d613501 2371 pp |= EDP_FORCE_VDD;
ebf33b18 2372
bf13e81b
JN		 2373 pp_stat_reg = _pp_stat_reg(intel_dp);
2374 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 2375
2376 I915_WRITE(pp_ctrl_reg, pp);
2377 POSTING_READ(pp_ctrl_reg);
2378 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2379 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 2380 /*
2381 * If the panel wasn't on, delay before accessing aux channel
2382 */
4be73780 2383 if (!edp_have_panel_power(intel_dp)) {
3936fcf4 2384 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
8f4f2797 2385 port_name(intel_dig_port->base.port));
f01eca2e 2386 msleep(intel_dp->panel_power_up_delay);
f01eca2e 2387 }
adddaaf4
JN		 2388
2389 return need_to_disable;
2390}
2391
951468f3
VS		 2392/*
2393 * Must be paired with intel_edp_panel_vdd_off() or
2394 * intel_edp_panel_off().
2395 * Nested calls to these functions are not allowed since
2396 * we drop the lock. Caller must use some higher level
2397 * locking to prevent nested calls from other threads.
2398 */
b80d6c78 2399void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4 2400{
c695b6b6 2401 bool vdd;
adddaaf4 2402
1853a9da 2403 if (!intel_dp_is_edp(intel_dp))
c695b6b6
VS		 2404 return;
2405
773538e8 2406 pps_lock(intel_dp);
c695b6b6 2407 vdd = edp_panel_vdd_on(intel_dp);
773538e8 2408 pps_unlock(intel_dp);
c695b6b6 2409
e2c719b7 2410 I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
8f4f2797 2411 port_name(dp_to_dig_port(intel_dp)->base.port));
5d613501
JB		 2412}
2413
4be73780 2414static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 2415{
de25eb7f 2416 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
be2c9196
VS		 2417 struct intel_digital_port *intel_dig_port =
2418 dp_to_dig_port(intel_dp);
5d613501 2419 u32 pp;
f0f59a00 2420 i915_reg_t pp_stat_reg, pp_ctrl_reg;
5d613501 2421
e39b999a 2422 lockdep_assert_held(&dev_priv->pps_mutex);
a0e99e68 2423
15e899a0 2424 WARN_ON(intel_dp->want_panel_vdd);
4e6e1a54 2425
15e899a0 2426 if (!edp_have_panel_vdd(intel_dp))
be2c9196 2427 return;
b0665d57 2428
3936fcf4 2429 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
8f4f2797 2430 port_name(intel_dig_port->base.port));
bd943159 2431
be2c9196
VS		 2432 pp = ironlake_get_pp_control(intel_dp);
2433 pp &= ~EDP_FORCE_VDD;
453c5420 2434
be2c9196
VS		 2435 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2436 pp_stat_reg = _pp_stat_reg(intel_dp);
99ea7127 2437
be2c9196
VS		 2438 I915_WRITE(pp_ctrl_reg, pp);
2439 POSTING_READ(pp_ctrl_reg);
90791a5c 2440
be2c9196
VS		 2441 /* Make sure sequencer is idle before allowing subsequent activity */
2442 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2443 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
e9cb81a2 2444
5a162e22 2445 if ((pp & PANEL_POWER_ON) == 0)
d28d4731 2446 intel_dp->panel_power_off_time = ktime_get_boottime();
e9cb81a2 2447
5432fcaf 2448 intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
bd943159 2449}
5d613501 2450
4be73780 2451static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 2452{
2453 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
2454 struct intel_dp, panel_vdd_work);
bd943159 2455
773538e8 2456 pps_lock(intel_dp);
15e899a0
VS		 2457 if (!intel_dp->want_panel_vdd)
2458 edp_panel_vdd_off_sync(intel_dp);
773538e8 2459 pps_unlock(intel_dp);
bd943159
KP		 2460}
2461
aba86890
ID		 2462static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
2463{
2464 unsigned long delay;
2465
2466 /*
2467 * Queue the timer to fire a long time from now (relative to the power
2468 * down delay) to keep the panel power up across a sequence of
2469 * operations.
2470 */
2471 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
2472 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
2473}
2474
951468f3
VS		 2475/*
2476 * Must be paired with edp_panel_vdd_on().
2477 * Must hold pps_mutex around the whole on/off sequence.
2478 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2479 */
4be73780 2480static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 2481{
de25eb7f 2482 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
e39b999a
VS		 2483
2484 lockdep_assert_held(&dev_priv->pps_mutex);
2485
1853a9da 2486 if (!intel_dp_is_edp(intel_dp))
97af61f5 2487 return;
5d613501 2488
e2c719b7 2489 I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
8f4f2797 2490 port_name(dp_to_dig_port(intel_dp)->base.port));
f2e8b18a 2491
bd943159
KP		 2492 intel_dp->want_panel_vdd = false;
2493
aba86890 2494 if (sync)
4be73780 2495 edp_panel_vdd_off_sync(intel_dp);
aba86890
ID		 2496 else
2497 edp_panel_vdd_schedule_off(intel_dp);
5d613501
JB		 2498}
2499
9f0fb5be 2500static void edp_panel_on(struct intel_dp *intel_dp)
9934c132 2501{
de25eb7f 2502 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
99ea7127 2503 u32 pp;
f0f59a00 2504 i915_reg_t pp_ctrl_reg;
9934c132 2505
9f0fb5be
VS		 2506 lockdep_assert_held(&dev_priv->pps_mutex);
2507
1853a9da 2508 if (!intel_dp_is_edp(intel_dp))
bd943159 2509 return;
99ea7127 2510
3936fcf4 2511 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
8f4f2797 2512 port_name(dp_to_dig_port(intel_dp)->base.port));
e39b999a 2513
e7a89ace
VS		 2514 if (WARN(edp_have_panel_power(intel_dp),
2515 "eDP port %c panel power already on\n",
8f4f2797 2516 port_name(dp_to_dig_port(intel_dp)->base.port)))
9f0fb5be 2517 return;
9934c132 2518
4be73780 2519 wait_panel_power_cycle(intel_dp);
37c6c9b0 2520
bf13e81b 2521 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 2522 pp = ironlake_get_pp_control(intel_dp);
5db94019 2523 if (IS_GEN5(dev_priv)) {
05ce1a49
KP		 2524 /* ILK workaround: disable reset around power sequence */
2525 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 2526 I915_WRITE(pp_ctrl_reg, pp);
2527 POSTING_READ(pp_ctrl_reg);
05ce1a49 2528 }
37c6c9b0 2529
5a162e22 2530 pp |= PANEL_POWER_ON;
5db94019 2531 if (!IS_GEN5(dev_priv))
99ea7127
KP		 2532 pp |= PANEL_POWER_RESET;
2533
453c5420
JB		 2534 I915_WRITE(pp_ctrl_reg, pp);
2535 POSTING_READ(pp_ctrl_reg);
9934c132 2536
4be73780 2537 wait_panel_on(intel_dp);
dce56b3c 2538 intel_dp->last_power_on = jiffies;
9934c132 2539
5db94019 2540 if (IS_GEN5(dev_priv)) {
05ce1a49 2541 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 2542 I915_WRITE(pp_ctrl_reg, pp);
2543 POSTING_READ(pp_ctrl_reg);
05ce1a49 2544 }
9f0fb5be 2545}
e39b999a 2546
9f0fb5be
VS		 2547void intel_edp_panel_on(struct intel_dp *intel_dp)
2548{
1853a9da 2549 if (!intel_dp_is_edp(intel_dp))
9f0fb5be
VS		 2550 return;
2551
2552 pps_lock(intel_dp);
2553 edp_panel_on(intel_dp);
773538e8 2554 pps_unlock(intel_dp);
9934c132
JB		 2555}
2556
9f0fb5be
VS		 2557
2558static void edp_panel_off(struct intel_dp *intel_dp)
9934c132 2559{
de25eb7f 2560 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
99ea7127 2561 u32 pp;
f0f59a00 2562 i915_reg_t pp_ctrl_reg;
9934c132 2563
9f0fb5be
VS		 2564 lockdep_assert_held(&dev_priv->pps_mutex);
2565
1853a9da 2566 if (!intel_dp_is_edp(intel_dp))
97af61f5 2567 return;
37c6c9b0 2568
3936fcf4 2569 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
8f4f2797 2570 port_name(dp_to_dig_port(intel_dp)->base.port));
37c6c9b0 2571
3936fcf4 2572 WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
8f4f2797 2573 port_name(dp_to_dig_port(intel_dp)->base.port));
24f3e092 2574
453c5420 2575 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 2576 /* We need to switch off panel power _and_ force vdd, for otherwise some
2577 * panels get very unhappy and cease to work. */
5a162e22 2578 pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
b3064154 2579 EDP_BLC_ENABLE);
453c5420 2580
bf13e81b 2581 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 2582
849e39f5
PZ		 2583 intel_dp->want_panel_vdd = false;
2584
453c5420
JB		 2585 I915_WRITE(pp_ctrl_reg, pp);
2586 POSTING_READ(pp_ctrl_reg);
9934c132 2587
4be73780 2588 wait_panel_off(intel_dp);
d7ba25bd 2589 intel_dp->panel_power_off_time = ktime_get_boottime();
849e39f5
PZ		 2590
2591 /* We got a reference when we enabled the VDD. */
5432fcaf 2592 intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
9f0fb5be 2593}
e39b999a 2594
9f0fb5be
VS		 2595void intel_edp_panel_off(struct intel_dp *intel_dp)
2596{
1853a9da 2597 if (!intel_dp_is_edp(intel_dp))
9f0fb5be 2598 return;
e39b999a 2599
9f0fb5be
VS		 2600 pps_lock(intel_dp);
2601 edp_panel_off(intel_dp);
773538e8 2602 pps_unlock(intel_dp);
9934c132
JB		 2603}
2604
1250d107
JN		 2605/* Enable backlight in the panel power control. */
2606static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 2607{
de25eb7f 2608 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
32f9d658 2609 u32 pp;
f0f59a00 2610 i915_reg_t pp_ctrl_reg;
32f9d658 2611
01cb9ea6
JB		 2612 /*
2613 * If we enable the backlight right away following a panel power
2614 * on, we may see slight flicker as the panel syncs with the eDP
2615 * link. So delay a bit to make sure the image is solid before
2616 * allowing it to appear.
2617 */
4be73780 2618 wait_backlight_on(intel_dp);
e39b999a 2619
773538e8 2620 pps_lock(intel_dp);
e39b999a 2621
453c5420 2622 pp = ironlake_get_pp_control(intel_dp);
32f9d658 2623 pp |= EDP_BLC_ENABLE;
453c5420 2624
bf13e81b 2625 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 2626
2627 I915_WRITE(pp_ctrl_reg, pp);
2628 POSTING_READ(pp_ctrl_reg);
e39b999a 2629
773538e8 2630 pps_unlock(intel_dp);
32f9d658
ZW		 2631}
2632
1250d107 2633/* Enable backlight PWM and backlight PP control. */
b037d58f
ML		 2634void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
2635 const struct drm_connector_state *conn_state)
1250d107 2636{
b037d58f
ML		 2637 struct intel_dp *intel_dp = enc_to_intel_dp(conn_state->best_encoder);
2638
1853a9da 2639 if (!intel_dp_is_edp(intel_dp))
1250d107
JN		 2640 return;
2641
2642 DRM_DEBUG_KMS("\n");
2643
b037d58f 2644 intel_panel_enable_backlight(crtc_state, conn_state);
1250d107
JN		 2645 _intel_edp_backlight_on(intel_dp);
2646}
2647
2648/* Disable backlight in the panel power control. */
2649static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 2650{
de25eb7f 2651 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
32f9d658 2652 u32 pp;
f0f59a00 2653 i915_reg_t pp_ctrl_reg;
32f9d658 2654
1853a9da 2655 if (!intel_dp_is_edp(intel_dp))
f01eca2e
KP		 2656 return;
2657
773538e8 2658 pps_lock(intel_dp);
e39b999a 2659
453c5420 2660 pp = ironlake_get_pp_control(intel_dp);
32f9d658 2661 pp &= ~EDP_BLC_ENABLE;
453c5420 2662
bf13e81b 2663 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 2664
2665 I915_WRITE(pp_ctrl_reg, pp);
2666 POSTING_READ(pp_ctrl_reg);
f7d2323c 2667
773538e8 2668 pps_unlock(intel_dp);
e39b999a
VS		 2669
2670 intel_dp->last_backlight_off = jiffies;
f7d2323c 2671 edp_wait_backlight_off(intel_dp);
1250d107 2672}
f7d2323c 2673
1250d107 2674/* Disable backlight PP control and backlight PWM. */
b037d58f 2675void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
1250d107 2676{
b037d58f
ML		 2677 struct intel_dp *intel_dp = enc_to_intel_dp(old_conn_state->best_encoder);
2678
1853a9da 2679 if (!intel_dp_is_edp(intel_dp))
1250d107
JN		 2680 return;
2681
2682 DRM_DEBUG_KMS("\n");
f7d2323c 2683
1250d107 2684 _intel_edp_backlight_off(intel_dp);
b037d58f 2685 intel_panel_disable_backlight(old_conn_state);
32f9d658 2686}
a4fc5ed6 2687
73580fb7
JN		 2688/*
2689 * Hook for controlling the panel power control backlight through the bl_power
2690 * sysfs attribute. Take care to handle multiple calls.
2691 */
2692static void intel_edp_backlight_power(struct intel_connector *connector,
2693 bool enable)
2694{
2695 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
e39b999a
VS		 2696 bool is_enabled;
2697
773538e8 2698 pps_lock(intel_dp);
e39b999a 2699 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
773538e8 2700 pps_unlock(intel_dp);
73580fb7
JN		 2701
2702 if (is_enabled == enable)
2703 return;
2704
23ba9373
JN		 2705 DRM_DEBUG_KMS("panel power control backlight %s\n",
2706 enable ? "enable" : "disable");
73580fb7
JN		 2707
2708 if (enable)
2709 _intel_edp_backlight_on(intel_dp);
2710 else
2711 _intel_edp_backlight_off(intel_dp);
2712}
2713
64e1077a
VS		 2714static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2715{
2716 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2717 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2718 bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2719
2720 I915_STATE_WARN(cur_state != state,
2721 "DP port %c state assertion failure (expected %s, current %s)\n",
8f4f2797 2722 port_name(dig_port->base.port),
87ad3212 2723 onoff(state), onoff(cur_state));
64e1077a
VS		 2724}
2725#define assert_dp_port_disabled(d) assert_dp_port((d), false)
2726
2727static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2728{
2729 bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2730
2731 I915_STATE_WARN(cur_state != state,
2732 "eDP PLL state assertion failure (expected %s, current %s)\n",
87ad3212 2733 onoff(state), onoff(cur_state));
64e1077a
VS		 2734}
2735#define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2736#define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2737
85cb48a1 2738static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
5f88a9c6 2739 const struct intel_crtc_state *pipe_config)
d240f20f 2740{
85cb48a1 2741 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
64e1077a 2742 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
d240f20f 2743
64e1077a
VS		 2744 assert_pipe_disabled(dev_priv, crtc->pipe);
2745 assert_dp_port_disabled(intel_dp);
2746 assert_edp_pll_disabled(dev_priv);
2bd2ad64 2747
abfce949 2748 DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
85cb48a1 2749 pipe_config->port_clock);
abfce949
VS		 2750
2751 intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2752
85cb48a1 2753 if (pipe_config->port_clock == 162000)
abfce949
VS		 2754 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2755 else
2756 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2757
2758 I915_WRITE(DP_A, intel_dp->DP);
2759 POSTING_READ(DP_A);
2760 udelay(500);
2761
6b23f3e8
VS		 2762 /*
2763 * [DevILK] Work around required when enabling DP PLL
2764 * while a pipe is enabled going to FDI:
2765 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2766 * 2. Program DP PLL enable
2767 */
2768 if (IS_GEN5(dev_priv))
0f0f74bc 2769 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
6b23f3e8 2770
0767935e 2771 intel_dp->DP |= DP_PLL_ENABLE;
6fec7662 2772
0767935e 2773 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 2774 POSTING_READ(DP_A);
2775 udelay(200);
d240f20f
JB		 2776}
2777
adc10304
VS		 2778static void ironlake_edp_pll_off(struct intel_dp *intel_dp,
2779 const struct intel_crtc_state *old_crtc_state)
d240f20f 2780{
adc10304 2781 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
64e1077a 2782 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
d240f20f 2783
64e1077a
VS		 2784 assert_pipe_disabled(dev_priv, crtc->pipe);
2785 assert_dp_port_disabled(intel_dp);
2786 assert_edp_pll_enabled(dev_priv);
2bd2ad64 2787
abfce949
VS		 2788 DRM_DEBUG_KMS("disabling eDP PLL\n");
2789
6fec7662 2790 intel_dp->DP &= ~DP_PLL_ENABLE;
0767935e 2791
6fec7662 2792 I915_WRITE(DP_A, intel_dp->DP);
1af5fa1b 2793 POSTING_READ(DP_A);
d240f20f
JB		 2794 udelay(200);
2795}
2796
857c416e
VS		 2797static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
2798{
2799 /*
2800 * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
2801 * be capable of signalling downstream hpd with a long pulse.
2802 * Whether or not that means D3 is safe to use is not clear,
2803 * but let's assume so until proven otherwise.
2804 *
2805 * FIXME should really check all downstream ports...
2806 */
2807 return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
2808 intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT &&
2809 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
2810}
2811
c7ad3810 2812/* If the sink supports it, try to set the power state appropriately */
c19b0669 2813void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 2814{
2815 int ret, i;
2816
2817 /* Should have a valid DPCD by this point */
2818 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2819 return;
2820
2821 if (mode != DRM_MODE_DPMS_ON) {
857c416e
VS		 2822 if (downstream_hpd_needs_d0(intel_dp))
2823 return;
2824
9d1a1031
JN		 2825 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2826 DP_SET_POWER_D3);
c7ad3810 2827 } else {
357c0ae9
ID		 2828 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
2829
c7ad3810
JB		 2830 /*
2831 * When turning on, we need to retry for 1ms to give the sink
2832 * time to wake up.
2833 */
2834 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2835 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2836 DP_SET_POWER_D0);
c7ad3810
JB		 2837 if (ret == 1)
2838 break;
2839 msleep(1);
2840 }
357c0ae9
ID		 2841
2842 if (ret == 1 && lspcon->active)
2843 lspcon_wait_pcon_mode(lspcon);
c7ad3810 2844 }
f9cac721
JN		 2845
2846 if (ret != 1)
2847 DRM_DEBUG_KMS("failed to %s sink power state\n",
2848 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
c7ad3810
JB		 2849}
2850
59b74c49
VS		 2851static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv,
2852 enum port port, enum pipe *pipe)
2853{
2854 enum pipe p;
2855
2856 for_each_pipe(dev_priv, p) {
2857 u32 val = I915_READ(TRANS_DP_CTL(p));
2858
2859 if ((val & TRANS_DP_PORT_SEL_MASK) == TRANS_DP_PORT_SEL(port)) {
2860 *pipe = p;
2861 return true;
2862 }
2863 }
2864
2865 DRM_DEBUG_KMS("No pipe for DP port %c found\n", port_name(port));
2866
2867 /* must initialize pipe to something for the asserts */
2868 *pipe = PIPE_A;
2869
2870 return false;
2871}
2872
2873bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
2874 i915_reg_t dp_reg, enum port port,
2875 enum pipe *pipe)
2876{
2877 bool ret;
2878 u32 val;
2879
2880 val = I915_READ(dp_reg);
2881
2882 ret = val & DP_PORT_EN;
2883
2884 /* asserts want to know the pipe even if the port is disabled */
2885 if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
2886 *pipe = (val & DP_PIPE_SEL_MASK_IVB) >> DP_PIPE_SEL_SHIFT_IVB;
2887 else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
2888 ret &= cpt_dp_port_selected(dev_priv, port, pipe);
2889 else if (IS_CHERRYVIEW(dev_priv))
2890 *pipe = (val & DP_PIPE_SEL_MASK_CHV) >> DP_PIPE_SEL_SHIFT_CHV;
2891 else
2892 *pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT;
2893
2894 return ret;
2895}
2896
19d8fe15
DV		 2897static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2898 enum pipe *pipe)
d240f20f 2899{
2f773477 2900 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
19d8fe15 2901 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
6fa9a5ec 2902 bool ret;
6d129bea 2903
79f255a0
ACO		 2904 if (!intel_display_power_get_if_enabled(dev_priv,
2905 encoder->power_domain))
6d129bea
ID		 2906 return false;
2907
59b74c49
VS		 2908 ret = intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
2909 encoder->port, pipe);
6fa9a5ec 2910
79f255a0 2911 intel_display_power_put(dev_priv, encoder->power_domain);
6fa9a5ec
ID		 2912
2913 return ret;
19d8fe15 2914}
d240f20f 2915
045ac3b5 2916static void intel_dp_get_config(struct intel_encoder *encoder,
5cec258b 2917 struct intel_crtc_state *pipe_config)
045ac3b5 2918{
2f773477 2919 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
045ac3b5 2920 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 2921 u32 tmp, flags = 0;
8f4f2797 2922 enum port port = encoder->port;
adc10304 2923 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
045ac3b5 2924
e1214b95
VS		 2925 if (encoder->type == INTEL_OUTPUT_EDP)
2926 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
2927 else
2928 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
045ac3b5 2929
9ed109a7 2930 tmp = I915_READ(intel_dp->output_reg);
9fcb1704
JN		 2931
2932 pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
9ed109a7 2933
6e266956 2934 if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
b81e34c2
VS		 2935 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2936
2937 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
63000ef6
XZ		 2938 flags |= DRM_MODE_FLAG_PHSYNC;
2939 else
2940 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 2941
b81e34c2 2942 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
63000ef6
XZ		 2943 flags |= DRM_MODE_FLAG_PVSYNC;
2944 else
2945 flags |= DRM_MODE_FLAG_NVSYNC;
2946 } else {
39e5fa88 2947 if (tmp & DP_SYNC_HS_HIGH)
63000ef6
XZ		 2948 flags |= DRM_MODE_FLAG_PHSYNC;
2949 else
2950 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 2951
39e5fa88 2952 if (tmp & DP_SYNC_VS_HIGH)
63000ef6
XZ		 2953 flags |= DRM_MODE_FLAG_PVSYNC;
2954 else
2955 flags |= DRM_MODE_FLAG_NVSYNC;
2956 }
045ac3b5 2957
2d112de7 2958 pipe_config->base.adjusted_mode.flags |= flags;
f1f644dc 2959
c99f53f7 2960 if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
8c875fca
VS		 2961 pipe_config->limited_color_range = true;
2962
90a6b7b0
VS		 2963 pipe_config->lane_count =
2964 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
2965
eb14cb74
VS		 2966 intel_dp_get_m_n(crtc, pipe_config);
2967
18442d08 2968 if (port == PORT_A) {
b377e0df 2969 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
f1f644dc
JB		 2970 pipe_config->port_clock = 162000;
2971 else
2972 pipe_config->port_clock = 270000;
2973 }
18442d08 2974
e3b247da
VS		 2975 pipe_config->base.adjusted_mode.crtc_clock =
2976 intel_dotclock_calculate(pipe_config->port_clock,
2977 &pipe_config->dp_m_n);
7f16e5c1 2978
1853a9da 2979 if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
6aa23e65 2980 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
c6cd2ee2
JN		 2981 /*
2982 * This is a big fat ugly hack.
2983 *
2984 * Some machines in UEFI boot mode provide us a VBT that has 18
2985 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2986 * unknown we fail to light up. Yet the same BIOS boots up with
2987 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2988 * max, not what it tells us to use.
2989 *
2990 * Note: This will still be broken if the eDP panel is not lit
2991 * up by the BIOS, and thus we can't get the mode at module
2992 * load.
2993 */
2994 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
6aa23e65
JN		 2995 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2996 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
c6cd2ee2 2997 }
045ac3b5
JB		 2998}
2999
fd6bbda9 3000static void intel_disable_dp(struct intel_encoder *encoder,
5f88a9c6
VS		 3001 const struct intel_crtc_state *old_crtc_state,
3002 const struct drm_connector_state *old_conn_state)
d240f20f 3003{
e8cb4558 3004 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
495a5bb8 3005
edb2e530
VS		 3006 intel_dp->link_trained = false;
3007
85cb48a1 3008 if (old_crtc_state->has_audio)
8ec47de2
VS		 3009 intel_audio_codec_disable(encoder,
3010 old_crtc_state, old_conn_state);
6cb49835
DV		 3011
3012 /* Make sure the panel is off before trying to change the mode. But also
3013 * ensure that we have vdd while we switch off the panel. */
24f3e092 3014 intel_edp_panel_vdd_on(intel_dp);
b037d58f 3015 intel_edp_backlight_off(old_conn_state);
fdbc3b1f 3016 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 3017 intel_edp_panel_off(intel_dp);
1a8ff607
VS		 3018}
3019
3020static void g4x_disable_dp(struct intel_encoder *encoder,
3021 const struct intel_crtc_state *old_crtc_state,
3022 const struct drm_connector_state *old_conn_state)
1a8ff607
VS		 3023{
3024 intel_disable_dp(encoder, old_crtc_state, old_conn_state);
3025}
3026
3027static void vlv_disable_dp(struct intel_encoder *encoder,
3028 const struct intel_crtc_state *old_crtc_state,
3029 const struct drm_connector_state *old_conn_state)
3030{
1a8ff607 3031 intel_disable_dp(encoder, old_crtc_state, old_conn_state);
d240f20f
JB		 3032}
3033
51a9f6df 3034static void g4x_post_disable_dp(struct intel_encoder *encoder,
5f88a9c6
VS		 3035 const struct intel_crtc_state *old_crtc_state,
3036 const struct drm_connector_state *old_conn_state)
d240f20f 3037{
2bd2ad64 3038 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
adc10304 3039 enum port port = encoder->port;
2bd2ad64 3040
51a9f6df
VS		 3041 /*
3042 * Bspec does not list a specific disable sequence for g4x DP.
3043 * Follow the ilk+ sequence (disable pipe before the port) for
3044 * g4x DP as it does not suffer from underruns like the normal
3045 * g4x modeset sequence (disable pipe after the port).
3046 */
adc10304 3047 intel_dp_link_down(encoder, old_crtc_state);
abfce949
VS		 3048
3049 /* Only ilk+ has port A */
08aff3fe 3050 if (port == PORT_A)
adc10304 3051 ironlake_edp_pll_off(intel_dp, old_crtc_state);
49277c31
VS		 3052}
3053
fd6bbda9 3054static void vlv_post_disable_dp(struct intel_encoder *encoder,
5f88a9c6
VS		 3055 const struct intel_crtc_state *old_crtc_state,
3056 const struct drm_connector_state *old_conn_state)
49277c31 3057{
adc10304 3058 intel_dp_link_down(encoder, old_crtc_state);
2bd2ad64
DV		 3059}
3060
fd6bbda9 3061static void chv_post_disable_dp(struct intel_encoder *encoder,
5f88a9c6
VS		 3062 const struct intel_crtc_state *old_crtc_state,
3063 const struct drm_connector_state *old_conn_state)
a8f327fb 3064{
adc10304 3065 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
97fd4d5c 3066
adc10304 3067 intel_dp_link_down(encoder, old_crtc_state);
a8f327fb
VS		 3068
3069 mutex_lock(&dev_priv->sb_lock);
3070
3071 /* Assert data lane reset */
2e1029c6 3072 chv_data_lane_soft_reset(encoder, old_crtc_state, true);
580d3811 3073
a580516d 3074 mutex_unlock(&dev_priv->sb_lock);
580d3811
VS		 3075}
3076
7b13b58a
VS		 3077static void
3078_intel_dp_set_link_train(struct intel_dp *intel_dp,
3079 uint32_t *DP,
3080 uint8_t dp_train_pat)
3081{
de25eb7f 3082 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7b13b58a 3083 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
8f4f2797 3084 enum port port = intel_dig_port->base.port;
2edd5327 3085 uint8_t train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd);
7b13b58a 3086
2edd5327 3087 if (dp_train_pat & train_pat_mask)
8b0878a0 3088 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
2edd5327 3089 dp_train_pat & train_pat_mask);
8b0878a0 3090
4f8036a2 3091 if (HAS_DDI(dev_priv)) {
7b13b58a
VS		 3092 uint32_t temp = I915_READ(DP_TP_CTL(port));
3093
3094 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
3095 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
3096 else
3097 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
3098
3099 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2edd5327 3100 switch (dp_train_pat & train_pat_mask) {
7b13b58a
VS		 3101 case DP_TRAINING_PATTERN_DISABLE:
3102 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
3103
3104 break;
3105 case DP_TRAINING_PATTERN_1:
3106 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
3107 break;
3108 case DP_TRAINING_PATTERN_2:
3109 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
3110 break;
3111 case DP_TRAINING_PATTERN_3:
3112 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
3113 break;
2edd5327
MN		 3114 case DP_TRAINING_PATTERN_4:
3115 temp |= DP_TP_CTL_LINK_TRAIN_PAT4;
3116 break;
7b13b58a
VS		 3117 }
3118 I915_WRITE(DP_TP_CTL(port), temp);
3119
b752e995 3120 } else if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
6e266956 3121 (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
7b13b58a
VS		 3122 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
3123
3124 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3125 case DP_TRAINING_PATTERN_DISABLE:
3126 *DP |= DP_LINK_TRAIN_OFF_CPT;
3127 break;
3128 case DP_TRAINING_PATTERN_1:
3129 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
3130 break;
3131 case DP_TRAINING_PATTERN_2:
3132 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3133 break;
3134 case DP_TRAINING_PATTERN_3:
8b0878a0 3135 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
7b13b58a
VS		 3136 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3137 break;
3138 }
3139
3140 } else {
3b358cda 3141 *DP &= ~DP_LINK_TRAIN_MASK;
7b13b58a
VS		 3142
3143 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3144 case DP_TRAINING_PATTERN_DISABLE:
3145 *DP |= DP_LINK_TRAIN_OFF;
3146 break;
3147 case DP_TRAINING_PATTERN_1:
3148 *DP |= DP_LINK_TRAIN_PAT_1;
3149 break;
3150 case DP_TRAINING_PATTERN_2:
3151 *DP |= DP_LINK_TRAIN_PAT_2;
3152 break;
3153 case DP_TRAINING_PATTERN_3:
3b358cda
VS		 3154 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
3155 *DP |= DP_LINK_TRAIN_PAT_2;
7b13b58a
VS		 3156 break;
3157 }
3158 }
3159}
3160
85cb48a1 3161static void intel_dp_enable_port(struct intel_dp *intel_dp,
5f88a9c6 3162 const struct intel_crtc_state *old_crtc_state)
7b13b58a 3163{
de25eb7f 3164 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7b13b58a 3165
7b13b58a 3166 /* enable with pattern 1 (as per spec) */
7b13b58a 3167
8b0878a0 3168 intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1);
7b713f50
VS		 3169
3170 /*
3171 * Magic for VLV/CHV. We _must_ first set up the register
3172 * without actually enabling the port, and then do another
3173 * write to enable the port. Otherwise link training will
3174 * fail when the power sequencer is freshly used for this port.
3175 */
3176 intel_dp->DP |= DP_PORT_EN;
85cb48a1 3177 if (old_crtc_state->has_audio)
6fec7662 3178 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
7b713f50
VS		 3179
3180 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3181 POSTING_READ(intel_dp->output_reg);
580d3811
VS		 3182}
3183
85cb48a1 3184static void intel_enable_dp(struct intel_encoder *encoder,
5f88a9c6
VS		 3185 const struct intel_crtc_state *pipe_config,
3186 const struct drm_connector_state *conn_state)
d240f20f 3187{
2f773477 3188 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
e8cb4558 3189 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
adc10304 3190 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
e8cb4558 3191 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
d6fbdd15 3192 enum pipe pipe = crtc->pipe;
5d613501 3193
0c33d8d7
DV		 3194 if (WARN_ON(dp_reg & DP_PORT_EN))
3195 return;
5d613501 3196
093e3f13
VS		 3197 pps_lock(intel_dp);
3198
920a14b2 3199 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
adc10304 3200 vlv_init_panel_power_sequencer(encoder, pipe_config);
093e3f13 3201
85cb48a1 3202 intel_dp_enable_port(intel_dp, pipe_config);
093e3f13
VS		 3203
3204 edp_panel_vdd_on(intel_dp);
3205 edp_panel_on(intel_dp);
3206 edp_panel_vdd_off(intel_dp, true);
3207
3208 pps_unlock(intel_dp);
3209
920a14b2 3210 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
e0fce78f
VS		 3211 unsigned int lane_mask = 0x0;
3212
920a14b2 3213 if (IS_CHERRYVIEW(dev_priv))
85cb48a1 3214 lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
e0fce78f 3215
9b6de0a1
VS		 3216 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
3217 lane_mask);
e0fce78f 3218 }
61234fa5 3219
f01eca2e 3220 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 3221 intel_dp_start_link_train(intel_dp);
3ab9c637 3222 intel_dp_stop_link_train(intel_dp);
c1dec79a 3223
85cb48a1 3224 if (pipe_config->has_audio) {
c1dec79a 3225 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
d6fbdd15 3226 pipe_name(pipe));
bbf35e9d 3227 intel_audio_codec_enable(encoder, pipe_config, conn_state);
c1dec79a 3228 }
ab1f90f9 3229}
89b667f8 3230
fd6bbda9 3231static void g4x_enable_dp(struct intel_encoder *encoder,
5f88a9c6
VS		 3232 const struct intel_crtc_state *pipe_config,
3233 const struct drm_connector_state *conn_state)
ecff4f3b 3234{
bbf35e9d 3235 intel_enable_dp(encoder, pipe_config, conn_state);
b037d58f 3236 intel_edp_backlight_on(pipe_config, conn_state);
ab1f90f9 3237}
89b667f8 3238
fd6bbda9 3239static void vlv_enable_dp(struct intel_encoder *encoder,
5f88a9c6
VS		 3240 const struct intel_crtc_state *pipe_config,
3241 const struct drm_connector_state *conn_state)
ab1f90f9 3242{
b037d58f 3243 intel_edp_backlight_on(pipe_config, conn_state);
d240f20f
JB		 3244}
3245
fd6bbda9 3246static void g4x_pre_enable_dp(struct intel_encoder *encoder,
5f88a9c6
VS		 3247 const struct intel_crtc_state *pipe_config,
3248 const struct drm_connector_state *conn_state)
ab1f90f9
JN		 3249{
3250 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
8f4f2797 3251 enum port port = encoder->port;
ab1f90f9 3252
85cb48a1 3253 intel_dp_prepare(encoder, pipe_config);
8ac33ed3 3254
d41f1efb 3255 /* Only ilk+ has port A */
abfce949 3256 if (port == PORT_A)
85cb48a1 3257 ironlake_edp_pll_on(intel_dp, pipe_config);
ab1f90f9
JN		 3258}
3259
83b84597
VS		 3260static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
3261{
3262 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
fac5e23e 3263 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
83b84597 3264 enum pipe pipe = intel_dp->pps_pipe;
44cb734c 3265 i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
83b84597 3266
9f2bdb00
VS		 3267 WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
3268
d158694f
VS		 3269 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
3270 return;
3271
83b84597
VS		 3272 edp_panel_vdd_off_sync(intel_dp);
3273
3274 /*
e7f2af78 3275 * VLV seems to get confused when multiple power sequencers
83b84597
VS		 3276 * have the same port selected (even if only one has power/vdd
3277 * enabled). The failure manifests as vlv_wait_port_ready() failing
3278 * CHV on the other hand doesn't seem to mind having the same port
e7f2af78 3279 * selected in multiple power sequencers, but let's clear the
83b84597
VS		 3280 * port select always when logically disconnecting a power sequencer
3281 * from a port.
3282 */
3283 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
8f4f2797 3284 pipe_name(pipe), port_name(intel_dig_port->base.port));
83b84597
VS		 3285 I915_WRITE(pp_on_reg, 0);
3286 POSTING_READ(pp_on_reg);
3287
3288 intel_dp->pps_pipe = INVALID_PIPE;
3289}
3290
46bd8383 3291static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
a4a5d2f8
VS		 3292 enum pipe pipe)
3293{
a4a5d2f8
VS		 3294 struct intel_encoder *encoder;
3295
3296 lockdep_assert_held(&dev_priv->pps_mutex);
3297
14aa521c
VS		 3298 for_each_intel_dp(&dev_priv->drm, encoder) {
3299 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3300 enum port port = encoder->port;
a4a5d2f8 3301
9f2bdb00
VS		 3302 WARN(intel_dp->active_pipe == pipe,
3303 "stealing pipe %c power sequencer from active (e)DP port %c\n",
3304 pipe_name(pipe), port_name(port));
3305
a4a5d2f8
VS		 3306 if (intel_dp->pps_pipe != pipe)
3307 continue;
3308
3309 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
773538e8 3310 pipe_name(pipe), port_name(port));
a4a5d2f8
VS		 3311
3312 /* make sure vdd is off before we steal it */
83b84597 3313 vlv_detach_power_sequencer(intel_dp);
a4a5d2f8
VS		 3314 }
3315}
3316
adc10304
VS		 3317static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
3318 const struct intel_crtc_state *crtc_state)
a4a5d2f8 3319{
46bd8383 3320 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
adc10304 3321 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
adc10304 3322 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a4a5d2f8
VS		 3323
3324 lockdep_assert_held(&dev_priv->pps_mutex);
3325
9f2bdb00 3326 WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
093e3f13 3327
9f2bdb00
VS		 3328 if (intel_dp->pps_pipe != INVALID_PIPE &&
3329 intel_dp->pps_pipe != crtc->pipe) {
3330 /*
3331 * If another power sequencer was being used on this
3332 * port previously make sure to turn off vdd there while
3333 * we still have control of it.
3334 */
83b84597 3335 vlv_detach_power_sequencer(intel_dp);
9f2bdb00 3336 }
a4a5d2f8
VS		 3337
3338 /*
3339 * We may be stealing the power
3340 * sequencer from another port.
3341 */
46bd8383 3342 vlv_steal_power_sequencer(dev_priv, crtc->pipe);
a4a5d2f8 3343
9f2bdb00
VS		 3344 intel_dp->active_pipe = crtc->pipe;
3345
1853a9da 3346 if (!intel_dp_is_edp(intel_dp))
9f2bdb00
VS		 3347 return;
3348
a4a5d2f8
VS		 3349 /* now it's all ours */
3350 intel_dp->pps_pipe = crtc->pipe;
3351
3352 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
adc10304 3353 pipe_name(intel_dp->pps_pipe), port_name(encoder->port));
a4a5d2f8
VS		 3354
3355 /* init power sequencer on this pipe and port */
46bd8383
VS		 3356 intel_dp_init_panel_power_sequencer(intel_dp);
3357 intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
a4a5d2f8
VS		 3358}
3359
fd6bbda9 3360static void vlv_pre_enable_dp(struct intel_encoder *encoder,
5f88a9c6
VS		 3361 const struct intel_crtc_state *pipe_config,
3362 const struct drm_connector_state *conn_state)
a4fc5ed6 3363{
2e1029c6 3364 vlv_phy_pre_encoder_enable(encoder, pipe_config);
ab1f90f9 3365
bbf35e9d 3366 intel_enable_dp(encoder, pipe_config, conn_state);
89b667f8
JB		 3367}
3368
fd6bbda9 3369static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder,
5f88a9c6
VS		 3370 const struct intel_crtc_state *pipe_config,
3371 const struct drm_connector_state *conn_state)
89b667f8 3372{
85cb48a1 3373 intel_dp_prepare(encoder, pipe_config);
8ac33ed3 3374
2e1029c6 3375 vlv_phy_pre_pll_enable(encoder, pipe_config);
a4fc5ed6
KP		 3376}
3377
fd6bbda9 3378static void chv_pre_enable_dp(struct intel_encoder *encoder,
5f88a9c6
VS		 3379 const struct intel_crtc_state *pipe_config,
3380 const struct drm_connector_state *conn_state)
e4a1d846 3381{
2e1029c6 3382 chv_phy_pre_encoder_enable(encoder, pipe_config);
e4a1d846 3383
bbf35e9d 3384 intel_enable_dp(encoder, pipe_config, conn_state);
b0b33846
VS		 3385
3386 /* Second common lane will stay alive on its own now */
e7d2a717 3387 chv_phy_release_cl2_override(encoder);
e4a1d846
CML		 3388}
3389
fd6bbda9 3390static void chv_dp_pre_pll_enable(struct intel_encoder *encoder,
5f88a9c6
VS		 3391 const struct intel_crtc_state *pipe_config,
3392 const struct drm_connector_state *conn_state)
9197c88b 3393{
85cb48a1 3394 intel_dp_prepare(encoder, pipe_config);
625695f8 3395
2e1029c6 3396 chv_phy_pre_pll_enable(encoder, pipe_config);
9197c88b
VS		 3397}
3398
fd6bbda9 3399static void chv_dp_post_pll_disable(struct intel_encoder *encoder,
2e1029c6
VS		 3400 const struct intel_crtc_state *old_crtc_state,
3401 const struct drm_connector_state *old_conn_state)
d6db995f 3402{
2e1029c6 3403 chv_phy_post_pll_disable(encoder, old_crtc_state);
d6db995f
VS		 3404}
3405
a4fc5ed6
KP		 3406/*
3407 * Fetch AUX CH registers 0x202 - 0x207 which contain
3408 * link status information
3409 */
94223d04 3410bool
93f62dad 3411intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 3412{
9f085ebb
L		 3413 return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
3414 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 3415}
3416
1100244e 3417/* These are source-specific values. */
94223d04 3418uint8_t
1a2eb460 3419intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 3420{
de25eb7f 3421 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
a393e964
VS		 3422 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3423 enum port port = encoder->port;
1a2eb460 3424
a393e964 3425 if (HAS_DDI(dev_priv))
ffe5111e 3426 return intel_ddi_dp_voltage_max(encoder);
a393e964 3427 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
bd60018a 3428 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
b752e995 3429 else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
bd60018a 3430 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
6e266956 3431 else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
bd60018a 3432 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
1a2eb460 3433 else
bd60018a 3434 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
1a2eb460
KP		 3435}
3436
94223d04 3437uint8_t
1a2eb460
KP		 3438intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
3439{
de25eb7f 3440 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4718a365
VS		 3441 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3442 enum port port = encoder->port;
1a2eb460 3443
4718a365
VS		 3444 if (HAS_DDI(dev_priv)) {
3445 return intel_ddi_dp_pre_emphasis_max(encoder, voltage_swing);
8652744b 3446 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
e2fa6fba 3447 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 3448 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3449 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3450 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3451 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3452 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3453 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3454 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba 3455 default:
bd60018a 3456 return DP_TRAIN_PRE_EMPH_LEVEL_0;
e2fa6fba 3457 }
b752e995 3458 } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
1a2eb460 3459 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 3460 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3461 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3462 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3463 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3464 return DP_TRAIN_PRE_EMPH_LEVEL_1;
1a2eb460 3465 default:
bd60018a 3466 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460
KP		 3467 }
3468 } else {
3469 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 3470 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3471 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3472 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3473 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3474 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3475 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3476 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
1a2eb460 3477 default:
bd60018a 3478 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460 3479 }
a4fc5ed6
KP		 3480 }
3481}
3482
5829975c 3483static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
e2fa6fba 3484{
53d98725 3485 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
e2fa6fba
P		 3486 unsigned long demph_reg_value, preemph_reg_value,
3487 uniqtranscale_reg_value;
3488 uint8_t train_set = intel_dp->train_set[0];
e2fa6fba
P		 3489
3490 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3491 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e2fa6fba
P		 3492 preemph_reg_value = 0x0004000;
3493 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3494 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3495 demph_reg_value = 0x2B405555;
3496 uniqtranscale_reg_value = 0x552AB83A;
3497 break;
bd60018a 3498 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3499 demph_reg_value = 0x2B404040;
3500 uniqtranscale_reg_value = 0x5548B83A;
3501 break;
bd60018a 3502 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 3503 demph_reg_value = 0x2B245555;
3504 uniqtranscale_reg_value = 0x5560B83A;
3505 break;
bd60018a 3506 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba
P		 3507 demph_reg_value = 0x2B405555;
3508 uniqtranscale_reg_value = 0x5598DA3A;
3509 break;
3510 default:
3511 return 0;
3512 }
3513 break;
bd60018a 3514 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e2fa6fba
P		 3515 preemph_reg_value = 0x0002000;
3516 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3517 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3518 demph_reg_value = 0x2B404040;
3519 uniqtranscale_reg_value = 0x5552B83A;
3520 break;
bd60018a 3521 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3522 demph_reg_value = 0x2B404848;
3523 uniqtranscale_reg_value = 0x5580B83A;
3524 break;
bd60018a 3525 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 3526 demph_reg_value = 0x2B404040;
3527 uniqtranscale_reg_value = 0x55ADDA3A;
3528 break;
3529 default:
3530 return 0;
3531 }
3532 break;
bd60018a 3533 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e2fa6fba
P		 3534 preemph_reg_value = 0x0000000;
3535 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3536 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3537 demph_reg_value = 0x2B305555;
3538 uniqtranscale_reg_value = 0x5570B83A;
3539 break;
bd60018a 3540 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3541 demph_reg_value = 0x2B2B4040;
3542 uniqtranscale_reg_value = 0x55ADDA3A;
3543 break;
3544 default:
3545 return 0;
3546 }
3547 break;
bd60018a 3548 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e2fa6fba
P		 3549 preemph_reg_value = 0x0006000;
3550 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3551 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3552 demph_reg_value = 0x1B405555;
3553 uniqtranscale_reg_value = 0x55ADDA3A;
3554 break;
3555 default:
3556 return 0;
3557 }
3558 break;
3559 default:
3560 return 0;
3561 }
3562
53d98725
ACO		 3563 vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
3564 uniqtranscale_reg_value, 0);
e2fa6fba
P		 3565
3566 return 0;
3567}
3568
5829975c 3569static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
e4a1d846 3570{
b7fa22d8
ACO		 3571 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3572 u32 deemph_reg_value, margin_reg_value;
3573 bool uniq_trans_scale = false;
e4a1d846 3574 uint8_t train_set = intel_dp->train_set[0];
e4a1d846
CML		 3575
3576 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3577 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e4a1d846 3578 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3579 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3580 deemph_reg_value = 128;
3581 margin_reg_value = 52;
3582 break;
bd60018a 3583 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3584 deemph_reg_value = 128;
3585 margin_reg_value = 77;
3586 break;
bd60018a 3587 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3588 deemph_reg_value = 128;
3589 margin_reg_value = 102;
3590 break;
bd60018a 3591 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e4a1d846
CML		 3592 deemph_reg_value = 128;
3593 margin_reg_value = 154;
b7fa22d8 3594 uniq_trans_scale = true;
e4a1d846
CML		 3595 break;
3596 default:
3597 return 0;
3598 }
3599 break;
bd60018a 3600 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e4a1d846 3601 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3602 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3603 deemph_reg_value = 85;
3604 margin_reg_value = 78;
3605 break;
bd60018a 3606 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3607 deemph_reg_value = 85;
3608 margin_reg_value = 116;
3609 break;
bd60018a 3610 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3611 deemph_reg_value = 85;
3612 margin_reg_value = 154;
3613 break;
3614 default:
3615 return 0;
3616 }
3617 break;
bd60018a 3618 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e4a1d846 3619 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3620 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3621 deemph_reg_value = 64;
3622 margin_reg_value = 104;
3623 break;
bd60018a 3624 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3625 deemph_reg_value = 64;
3626 margin_reg_value = 154;
3627 break;
3628 default:
3629 return 0;
3630 }
3631 break;
bd60018a 3632 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e4a1d846 3633 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3634 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3635 deemph_reg_value = 43;
3636 margin_reg_value = 154;
3637 break;
3638 default:
3639 return 0;
3640 }
3641 break;
3642 default:
3643 return 0;
3644 }
3645
b7fa22d8
ACO		 3646 chv_set_phy_signal_level(encoder, deemph_reg_value,
3647 margin_reg_value, uniq_trans_scale);
e4a1d846
CML		 3648
3649 return 0;
3650}
3651
a4fc5ed6 3652static uint32_t
45101e93 3653g4x_signal_levels(uint8_t train_set)
a4fc5ed6 3654{
3cf2efb1 3655 uint32_t signal_levels = 0;
a4fc5ed6 3656
3cf2efb1 3657 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3658 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
a4fc5ed6
KP		 3659 default:
3660 signal_levels |= DP_VOLTAGE_0_4;
3661 break;
bd60018a 3662 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
a4fc5ed6
KP		 3663 signal_levels |= DP_VOLTAGE_0_6;
3664 break;
bd60018a 3665 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
a4fc5ed6
KP		 3666 signal_levels |= DP_VOLTAGE_0_8;
3667 break;
bd60018a 3668 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
a4fc5ed6
KP		 3669 signal_levels |= DP_VOLTAGE_1_2;
3670 break;
3671 }
3cf2efb1 3672 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3673 case DP_TRAIN_PRE_EMPH_LEVEL_0:
a4fc5ed6
KP		 3674 default:
3675 signal_levels |= DP_PRE_EMPHASIS_0;
3676 break;
bd60018a 3677 case DP_TRAIN_PRE_EMPH_LEVEL_1:
a4fc5ed6
KP		 3678 signal_levels |= DP_PRE_EMPHASIS_3_5;
3679 break;
bd60018a 3680 case DP_TRAIN_PRE_EMPH_LEVEL_2:
a4fc5ed6
KP		 3681 signal_levels |= DP_PRE_EMPHASIS_6;
3682 break;
bd60018a 3683 case DP_TRAIN_PRE_EMPH_LEVEL_3:
a4fc5ed6
KP		 3684 signal_levels |= DP_PRE_EMPHASIS_9_5;
3685 break;
3686 }
3687 return signal_levels;
3688}
3689
4d82c2b5 3690/* SNB CPU eDP voltage swing and pre-emphasis control */
e3421a18 3691static uint32_t
4d82c2b5 3692snb_cpu_edp_signal_levels(uint8_t train_set)
e3421a18 3693{
3c5a62b5
YL		 3694 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3695 DP_TRAIN_PRE_EMPHASIS_MASK);
3696 switch (signal_levels) {
bd60018a
SJ		 3697 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3698 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3699 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
bd60018a 3700 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3701 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
bd60018a
SJ		 3702 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3703 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3c5a62b5 3704 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
bd60018a
SJ		 3705 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3706 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3707 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
bd60018a
SJ		 3708 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3709 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3710 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 3711 default:
3c5a62b5
YL		 3712 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3713 "0x%x\n", signal_levels);
3714 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 3715 }
3716}
3717
4d82c2b5 3718/* IVB CPU eDP voltage swing and pre-emphasis control */
1a2eb460 3719static uint32_t
4d82c2b5 3720ivb_cpu_edp_signal_levels(uint8_t train_set)
1a2eb460
KP		 3721{
3722 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3723 DP_TRAIN_PRE_EMPHASIS_MASK);
3724 switch (signal_levels) {
bd60018a 3725 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3726 return EDP_LINK_TRAIN_400MV_0DB_IVB;
bd60018a 3727 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460 3728 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
bd60018a 3729 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1a2eb460
KP		 3730 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3731
bd60018a 3732 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3733 return EDP_LINK_TRAIN_600MV_0DB_IVB;
bd60018a 3734 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3735 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3736
bd60018a 3737 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3738 return EDP_LINK_TRAIN_800MV_0DB_IVB;
bd60018a 3739 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3740 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3741
3742 default:
3743 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3744 "0x%x\n", signal_levels);
3745 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3746 }
3747}
3748
94223d04 3749void
f4eb692e 3750intel_dp_set_signal_levels(struct intel_dp *intel_dp)
f0a3424e 3751{
de25eb7f 3752 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
f0a3424e 3753 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
8f4f2797 3754 enum port port = intel_dig_port->base.port;
f8896f5d 3755 uint32_t signal_levels, mask = 0;
f0a3424e
PZ		 3756 uint8_t train_set = intel_dp->train_set[0];
3757
d509af6c
RV		 3758 if (IS_GEN9_LP(dev_priv) || IS_CANNONLAKE(dev_priv)) {
3759 signal_levels = bxt_signal_levels(intel_dp);
3760 } else if (HAS_DDI(dev_priv)) {
f8896f5d 3761 signal_levels = ddi_signal_levels(intel_dp);
d509af6c 3762 mask = DDI_BUF_EMP_MASK;
920a14b2 3763 } else if (IS_CHERRYVIEW(dev_priv)) {
5829975c 3764 signal_levels = chv_signal_levels(intel_dp);
11a914c2 3765 } else if (IS_VALLEYVIEW(dev_priv)) {
5829975c 3766 signal_levels = vlv_signal_levels(intel_dp);
b752e995 3767 } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
4d82c2b5 3768 signal_levels = ivb_cpu_edp_signal_levels(train_set);
f0a3424e 3769 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
5db94019 3770 } else if (IS_GEN6(dev_priv) && port == PORT_A) {
4d82c2b5 3771 signal_levels = snb_cpu_edp_signal_levels(train_set);
f0a3424e
PZ		 3772 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3773 } else {
45101e93 3774 signal_levels = g4x_signal_levels(train_set);
f0a3424e
PZ		 3775 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3776 }
3777
96fb9f9b
VK		 3778 if (mask)
3779 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3780
3781 DRM_DEBUG_KMS("Using vswing level %d\n",
3782 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3783 DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3784 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3785 DP_TRAIN_PRE_EMPHASIS_SHIFT);
f0a3424e 3786
f4eb692e 3787 intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
b905a915
ACO		 3788
3789 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3790 POSTING_READ(intel_dp->output_reg);
f0a3424e
PZ		 3791}
3792
94223d04 3793void
e9c176d5
ACO		 3794intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3795 uint8_t dp_train_pat)
a4fc5ed6 3796{
174edf1f 3797 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
90a6b7b0
VS		 3798 struct drm_i915_private *dev_priv =
3799 to_i915(intel_dig_port->base.base.dev);
a4fc5ed6 3800
f4eb692e 3801 _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
47ea7542 3802
f4eb692e 3803 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
ea5b213a 3804 POSTING_READ(intel_dp->output_reg);
e9c176d5
ACO		 3805}
3806
94223d04 3807void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3ab9c637 3808{
de25eb7f 3809 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3ab9c637 3810 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
8f4f2797 3811 enum port port = intel_dig_port->base.port;
3ab9c637
ID		 3812 uint32_t val;
3813
4f8036a2 3814 if (!HAS_DDI(dev_priv))
3ab9c637
ID		 3815 return;
3816
3817 val = I915_READ(DP_TP_CTL(port));
3818 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3819 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3820 I915_WRITE(DP_TP_CTL(port), val);
3821
3822 /*
3823 * On PORT_A we can have only eDP in SST mode. There the only reason
3824 * we need to set idle transmission mode is to work around a HW issue
3825 * where we enable the pipe while not in idle link-training mode.
3826 * In this case there is requirement to wait for a minimum number of
3827 * idle patterns to be sent.
3828 */
3829 if (port == PORT_A)
3830 return;
3831
a767017f
CW		 3832 if (intel_wait_for_register(dev_priv,DP_TP_STATUS(port),
3833 DP_TP_STATUS_IDLE_DONE,
3834 DP_TP_STATUS_IDLE_DONE,
3835 1))
3ab9c637
ID		 3836 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3837}
3838
a4fc5ed6 3839static void
adc10304
VS		 3840intel_dp_link_down(struct intel_encoder *encoder,
3841 const struct intel_crtc_state *old_crtc_state)
a4fc5ed6 3842{
adc10304
VS		 3843 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3844 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3845 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
3846 enum port port = encoder->port;
ea5b213a 3847 uint32_t DP = intel_dp->DP;
a4fc5ed6 3848
4f8036a2 3849 if (WARN_ON(HAS_DDI(dev_priv)))
c19b0669
PZ		 3850 return;
3851
0c33d8d7 3852 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 3853 return;
3854
28c97730 3855 DRM_DEBUG_KMS("\n");
32f9d658 3856
b752e995 3857 if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
6e266956 3858 (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
e3421a18 3859 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1612c8bd 3860 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
e3421a18 3861 } else {
3b358cda 3862 DP &= ~DP_LINK_TRAIN_MASK;
1612c8bd 3863 DP |= DP_LINK_TRAIN_PAT_IDLE;
e3421a18 3864 }
1612c8bd 3865 I915_WRITE(intel_dp->output_reg, DP);
fe255d00 3866 POSTING_READ(intel_dp->output_reg);
5eb08b69 3867
1612c8bd
VS		 3868 DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3869 I915_WRITE(intel_dp->output_reg, DP);
3870 POSTING_READ(intel_dp->output_reg);
3871
3872 /*
3873 * HW workaround for IBX, we need to move the port
3874 * to transcoder A after disabling it to allow the
3875 * matching HDMI port to be enabled on transcoder A.
3876 */
6e266956 3877 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
0c241d5b
VS		 3878 /*
3879 * We get CPU/PCH FIFO underruns on the other pipe when
3880 * doing the workaround. Sweep them under the rug.
3881 */
3882 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3883 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3884
1612c8bd 3885 /* always enable with pattern 1 (as per spec) */
59b74c49
VS		 3886 DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK);
3887 DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) |
3888 DP_LINK_TRAIN_PAT_1;
1612c8bd
VS		 3889 I915_WRITE(intel_dp->output_reg, DP);
3890 POSTING_READ(intel_dp->output_reg);
3891
3892 DP &= ~DP_PORT_EN;
5bddd17f 3893 I915_WRITE(intel_dp->output_reg, DP);
0ca09685 3894 POSTING_READ(intel_dp->output_reg);
0c241d5b 3895
0f0f74bc 3896 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
0c241d5b
VS		 3897 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3898 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
5bddd17f
EA		 3899 }
3900
f01eca2e 3901 msleep(intel_dp->panel_power_down_delay);
6fec7662
VS		 3902
3903 intel_dp->DP = DP;
9f2bdb00
VS		 3904
3905 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3906 pps_lock(intel_dp);
3907 intel_dp->active_pipe = INVALID_PIPE;
3908 pps_unlock(intel_dp);
3909 }
a4fc5ed6
KP		 3910}
3911
24e807e7 3912bool
fe5a66f9 3913intel_dp_read_dpcd(struct intel_dp *intel_dp)
92fd8fd1 3914{
9f085ebb
L		 3915 if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
3916 sizeof(intel_dp->dpcd)) < 0)
edb39244 3917 return false; /* aux transfer failed */
92fd8fd1 3918
a8e98153 3919 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
577c7a50 3920
fe5a66f9
VS		 3921 return intel_dp->dpcd[DP_DPCD_REV] != 0;
3922}
edb39244 3923
fe5a66f9
VS		 3924static bool
3925intel_edp_init_dpcd(struct intel_dp *intel_dp)
3926{
3927 struct drm_i915_private *dev_priv =
3928 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
30d9aa42 3929
fe5a66f9
VS		 3930 /* this function is meant to be called only once */
3931 WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0);
30d9aa42 3932
fe5a66f9 3933 if (!intel_dp_read_dpcd(intel_dp))
30d9aa42
SS		 3934 return false;
3935
84c36753
JN		 3936 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
3937 drm_dp_is_branch(intel_dp->dpcd));
12a47a42 3938
fe5a66f9
VS		 3939 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3940 dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3941 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
474d1ec4 3942
7c838e2a
JN		 3943 /*
3944 * Read the eDP display control registers.
3945 *
3946 * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
3947 * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
3948 * set, but require eDP 1.4+ detection (e.g. for supported link rates
3949 * method). The display control registers should read zero if they're
3950 * not supported anyway.
3951 */
3952 if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
f7170e2e
DC		 3953 intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
3954 sizeof(intel_dp->edp_dpcd))
e6ed2a1b 3955 DRM_DEBUG_KMS("eDP DPCD: %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
fe5a66f9 3956 intel_dp->edp_dpcd);
06ea66b6 3957
84bb2916
DP		 3958 /*
3959 * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
3960 * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
3961 */
3962 intel_psr_init_dpcd(intel_dp);
3963
e6ed2a1b
JN		 3964 /* Read the eDP 1.4+ supported link rates. */
3965 if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
94ca719e 3966 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
ea2d8a42
VS		 3967 int i;
3968
9f085ebb
L		 3969 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
3970 sink_rates, sizeof(sink_rates));
ea2d8a42 3971
94ca719e
VS		 3972 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3973 int val = le16_to_cpu(sink_rates[i]);
ea2d8a42
VS		 3974
3975 if (val == 0)
3976 break;
3977
fd81c44e
DP		 3978 /* Value read multiplied by 200kHz gives the per-lane
3979 * link rate in kHz. The source rates are, however,
3980 * stored in terms of LS_Clk kHz. The full conversion
3981 * back to symbols is
3982 * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
3983 */
af77b974 3984 intel_dp->sink_rates[i] = (val * 200) / 10;
ea2d8a42 3985 }
94ca719e 3986 intel_dp->num_sink_rates = i;
fc0f8e25 3987 }
0336400e 3988
e6ed2a1b
JN		 3989 /*
3990 * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
3991 * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
3992 */
68f357cb
JN		 3993 if (intel_dp->num_sink_rates)
3994 intel_dp->use_rate_select = true;
3995 else
3996 intel_dp_set_sink_rates(intel_dp);
3997
975ee5fc
JN		 3998 intel_dp_set_common_rates(intel_dp);
3999
fe5a66f9
VS		 4000 return true;
4001}
4002
4003
4004static bool
4005intel_dp_get_dpcd(struct intel_dp *intel_dp)
4006{
27dbefb9
JN		 4007 u8 sink_count;
4008
fe5a66f9
VS		 4009 if (!intel_dp_read_dpcd(intel_dp))
4010 return false;
4011
68f357cb 4012 /* Don't clobber cached eDP rates. */
1853a9da 4013 if (!intel_dp_is_edp(intel_dp)) {
68f357cb 4014 intel_dp_set_sink_rates(intel_dp);
975ee5fc
JN		 4015 intel_dp_set_common_rates(intel_dp);
4016 }
68f357cb 4017
27dbefb9 4018 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_COUNT, &sink_count) <= 0)
fe5a66f9
VS		 4019 return false;
4020
4021 /*
4022 * Sink count can change between short pulse hpd hence
4023 * a member variable in intel_dp will track any changes
4024 * between short pulse interrupts.
4025 */
27dbefb9 4026 intel_dp->sink_count = DP_GET_SINK_COUNT(sink_count);
fe5a66f9
VS		 4027
4028 /*
4029 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
4030 * a dongle is present but no display. Unless we require to know
4031 * if a dongle is present or not, we don't need to update
4032 * downstream port information. So, an early return here saves
4033 * time from performing other operations which are not required.
4034 */
1853a9da 4035 if (!intel_dp_is_edp(intel_dp) && !intel_dp->sink_count)
fe5a66f9 4036 return false;
0336400e 4037
c726ad01 4038 if (!drm_dp_is_branch(intel_dp->dpcd))
edb39244
AJ		 4039 return true; /* native DP sink */
4040
4041 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
4042 return true; /* no per-port downstream info */
4043
9f085ebb
L		 4044 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
4045 intel_dp->downstream_ports,
4046 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 4047 return false; /* downstream port status fetch failed */
4048
4049 return true;
92fd8fd1
KP		 4050}
4051
0e32b39c 4052static bool
9dbf5a4e 4053intel_dp_sink_can_mst(struct intel_dp *intel_dp)
0e32b39c 4054{
010b9b39 4055 u8 mstm_cap;
0e32b39c 4056
0e32b39c
DA		 4057 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
4058 return false;
4059
010b9b39 4060 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_MSTM_CAP, &mstm_cap) != 1)
c4e3170a 4061 return false;
0e32b39c 4062
010b9b39 4063 return mstm_cap & DP_MST_CAP;
c4e3170a
VS		 4064}
4065
9dbf5a4e
VS		 4066static bool
4067intel_dp_can_mst(struct intel_dp *intel_dp)
4068{
4069 return i915_modparams.enable_dp_mst &&
4070 intel_dp->can_mst &&
4071 intel_dp_sink_can_mst(intel_dp);
4072}
4073
c4e3170a
VS		 4074static void
4075intel_dp_configure_mst(struct intel_dp *intel_dp)
4076{
9dbf5a4e
VS		 4077 struct intel_encoder *encoder =
4078 &dp_to_dig_port(intel_dp)->base;
4079 bool sink_can_mst = intel_dp_sink_can_mst(intel_dp);
4080
4081 DRM_DEBUG_KMS("MST support? port %c: %s, sink: %s, modparam: %s\n",
4082 port_name(encoder->port), yesno(intel_dp->can_mst),
4083 yesno(sink_can_mst), yesno(i915_modparams.enable_dp_mst));
c4e3170a
VS		 4084
4085 if (!intel_dp->can_mst)
4086 return;
4087
9dbf5a4e
VS		 4088 intel_dp->is_mst = sink_can_mst &&
4089 i915_modparams.enable_dp_mst;
c4e3170a
VS		 4090
4091 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4092 intel_dp->is_mst);
0e32b39c
DA		 4093}
4094
0e32b39c
DA		 4095static bool
4096intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4097{
e8b2577c
PD		 4098 return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI,
4099 sink_irq_vector, DP_DPRX_ESI_LEN) ==
4100 DP_DPRX_ESI_LEN;
0e32b39c
DA		 4101}
4102
c5d5ab7a
TP		 4103static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
4104{
da15f7cb 4105 int status = 0;
140ef138 4106 int test_link_rate;
da15f7cb
MN		 4107 uint8_t test_lane_count, test_link_bw;
4108 /* (DP CTS 1.2)
4109 * 4.3.1.11
4110 */
4111 /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
4112 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
4113 &test_lane_count);
4114
4115 if (status <= 0) {
4116 DRM_DEBUG_KMS("Lane count read failed\n");
4117 return DP_TEST_NAK;
4118 }
4119 test_lane_count &= DP_MAX_LANE_COUNT_MASK;
da15f7cb
MN		 4120
4121 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
4122 &test_link_bw);
4123 if (status <= 0) {
4124 DRM_DEBUG_KMS("Link Rate read failed\n");
4125 return DP_TEST_NAK;
4126 }
da15f7cb 4127 test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
140ef138
MN		 4128
4129 /* Validate the requested link rate and lane count */
4130 if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
4131 test_lane_count))
da15f7cb
MN		 4132 return DP_TEST_NAK;
4133
4134 intel_dp->compliance.test_lane_count = test_lane_count;
4135 intel_dp->compliance.test_link_rate = test_link_rate;
4136
4137 return DP_TEST_ACK;
c5d5ab7a
TP		 4138}
4139
4140static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
4141{
611032bf 4142 uint8_t test_pattern;
010b9b39 4143 uint8_t test_misc;
611032bf
MN		 4144 __be16 h_width, v_height;
4145 int status = 0;
4146
4147 /* Read the TEST_PATTERN (DP CTS 3.1.5) */
010b9b39
JN		 4148 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
4149 &test_pattern);
611032bf
MN		 4150 if (status <= 0) {
4151 DRM_DEBUG_KMS("Test pattern read failed\n");
4152 return DP_TEST_NAK;
4153 }
4154 if (test_pattern != DP_COLOR_RAMP)
4155 return DP_TEST_NAK;
4156
4157 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
4158 &h_width, 2);
4159 if (status <= 0) {
4160 DRM_DEBUG_KMS("H Width read failed\n");
4161 return DP_TEST_NAK;
4162 }
4163
4164 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
4165 &v_height, 2);
4166 if (status <= 0) {
4167 DRM_DEBUG_KMS("V Height read failed\n");
4168 return DP_TEST_NAK;
4169 }
4170
010b9b39
JN		 4171 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
4172 &test_misc);
611032bf
MN		 4173 if (status <= 0) {
4174 DRM_DEBUG_KMS("TEST MISC read failed\n");
4175 return DP_TEST_NAK;
4176 }
4177 if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
4178 return DP_TEST_NAK;
4179 if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
4180 return DP_TEST_NAK;
4181 switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
4182 case DP_TEST_BIT_DEPTH_6:
4183 intel_dp->compliance.test_data.bpc = 6;
4184 break;
4185 case DP_TEST_BIT_DEPTH_8:
4186 intel_dp->compliance.test_data.bpc = 8;
4187 break;
4188 default:
4189 return DP_TEST_NAK;
4190 }
4191
4192 intel_dp->compliance.test_data.video_pattern = test_pattern;
4193 intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
4194 intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
4195 /* Set test active flag here so userspace doesn't interrupt things */
4196 intel_dp->compliance.test_active = 1;
4197
4198 return DP_TEST_ACK;
c5d5ab7a
TP		 4199}
4200
4201static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
a60f0e38 4202{
b48a5ba9 4203 uint8_t test_result = DP_TEST_ACK;
559be30c
TP		 4204 struct intel_connector *intel_connector = intel_dp->attached_connector;
4205 struct drm_connector *connector = &intel_connector->base;
4206
4207 if (intel_connector->detect_edid == NULL ||
ac6f2e29 4208 connector->edid_corrupt ||
559be30c
TP		 4209 intel_dp->aux.i2c_defer_count > 6) {
4210 /* Check EDID read for NACKs, DEFERs and corruption
4211 * (DP CTS 1.2 Core r1.1)
4212 * 4.2.2.4 : Failed EDID read, I2C_NAK
4213 * 4.2.2.5 : Failed EDID read, I2C_DEFER
4214 * 4.2.2.6 : EDID corruption detected
4215 * Use failsafe mode for all cases
4216 */
4217 if (intel_dp->aux.i2c_nack_count > 0 ||
4218 intel_dp->aux.i2c_defer_count > 0)
4219 DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4220 intel_dp->aux.i2c_nack_count,
4221 intel_dp->aux.i2c_defer_count);
c1617abc 4222 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
559be30c 4223 } else {
f79b468e
TS		 4224 struct edid *block = intel_connector->detect_edid;
4225
4226 /* We have to write the checksum
4227 * of the last block read
4228 */
4229 block += intel_connector->detect_edid->extensions;
4230
010b9b39
JN		 4231 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
4232 block->checksum) <= 0)
559be30c
TP		 4233 DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4234
4235 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
b48a5ba9 4236 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
559be30c
TP		 4237 }
4238
4239 /* Set test active flag here so userspace doesn't interrupt things */
c1617abc 4240 intel_dp->compliance.test_active = 1;
559be30c 4241
c5d5ab7a
TP		 4242 return test_result;
4243}
4244
4245static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
a60f0e38 4246{
c5d5ab7a
TP		 4247 uint8_t test_result = DP_TEST_NAK;
4248 return test_result;
4249}
4250
4251static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4252{
4253 uint8_t response = DP_TEST_NAK;
5ec63bbd
JN		 4254 uint8_t request = 0;
4255 int status;
c5d5ab7a 4256
5ec63bbd 4257 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
c5d5ab7a
TP		 4258 if (status <= 0) {
4259 DRM_DEBUG_KMS("Could not read test request from sink\n");
4260 goto update_status;
4261 }
4262
5ec63bbd 4263 switch (request) {
c5d5ab7a
TP		 4264 case DP_TEST_LINK_TRAINING:
4265 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
c5d5ab7a
TP		 4266 response = intel_dp_autotest_link_training(intel_dp);
4267 break;
4268 case DP_TEST_LINK_VIDEO_PATTERN:
4269 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
c5d5ab7a
TP		 4270 response = intel_dp_autotest_video_pattern(intel_dp);
4271 break;
4272 case DP_TEST_LINK_EDID_READ:
4273 DRM_DEBUG_KMS("EDID test requested\n");
c5d5ab7a
TP		 4274 response = intel_dp_autotest_edid(intel_dp);
4275 break;
4276 case DP_TEST_LINK_PHY_TEST_PATTERN:
4277 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
c5d5ab7a
TP		 4278 response = intel_dp_autotest_phy_pattern(intel_dp);
4279 break;
4280 default:
5ec63bbd 4281 DRM_DEBUG_KMS("Invalid test request '%02x'\n", request);
c5d5ab7a
TP		 4282 break;
4283 }
4284
5ec63bbd
JN		 4285 if (response & DP_TEST_ACK)
4286 intel_dp->compliance.test_type = request;
4287
c5d5ab7a 4288update_status:
5ec63bbd 4289 status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
c5d5ab7a
TP		 4290 if (status <= 0)
4291 DRM_DEBUG_KMS("Could not write test response to sink\n");
a60f0e38
JB		 4292}
4293
0e32b39c
DA		 4294static int
4295intel_dp_check_mst_status(struct intel_dp *intel_dp)
4296{
4297 bool bret;
4298
4299 if (intel_dp->is_mst) {
e8b2577c 4300 u8 esi[DP_DPRX_ESI_LEN] = { 0 };
0e32b39c
DA		 4301 int ret = 0;
4302 int retry;
4303 bool handled;
45ef40aa
DP		 4304
4305 WARN_ON_ONCE(intel_dp->active_mst_links < 0);
0e32b39c
DA		 4306 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4307go_again:
4308 if (bret == true) {
4309
4310 /* check link status - esi[10] = 0x200c */
45ef40aa 4311 if (intel_dp->active_mst_links > 0 &&
901c2daf 4312 !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
0e32b39c
DA		 4313 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4314 intel_dp_start_link_train(intel_dp);
0e32b39c
DA		 4315 intel_dp_stop_link_train(intel_dp);
4316 }
4317
6f34cc39 4318 DRM_DEBUG_KMS("got esi %3ph\n", esi);
0e32b39c
DA		 4319 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4320
4321 if (handled) {
4322 for (retry = 0; retry < 3; retry++) {
4323 int wret;
4324 wret = drm_dp_dpcd_write(&intel_dp->aux,
4325 DP_SINK_COUNT_ESI+1,
4326 &esi[1], 3);
4327 if (wret == 3) {
4328 break;
4329 }
4330 }
4331
4332 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4333 if (bret == true) {
6f34cc39 4334 DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
0e32b39c
DA		 4335 goto go_again;
4336 }
4337 } else
4338 ret = 0;
4339
4340 return ret;
4341 } else {
4342 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4343 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4344 intel_dp->is_mst = false;
4345 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4346 /* send a hotplug event */
4347 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
4348 }
4349 }
4350 return -EINVAL;
4351}
4352
c85d200e
VS		 4353static bool
4354intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
4355{
4356 u8 link_status[DP_LINK_STATUS_SIZE];
4357
edb2e530
VS		 4358 if (!intel_dp->link_trained)
4359 return false;
4360
4361 if (!intel_dp_get_link_status(intel_dp, link_status))
c85d200e 4362 return false;
c85d200e
VS		 4363
4364 /*
4365 * Validate the cached values of intel_dp->link_rate and
4366 * intel_dp->lane_count before attempting to retrain.
4367 */
4368 if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
4369 intel_dp->lane_count))
4370 return false;
4371
4372 /* Retrain if Channel EQ or CR not ok */
4373 return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
4374}
4375
c85d200e
VS		 4376int intel_dp_retrain_link(struct intel_encoder *encoder,
4377 struct drm_modeset_acquire_ctx *ctx)
bfd02b3c 4378{
bfd02b3c 4379 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
c85d200e
VS		 4380 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
4381 struct intel_connector *connector = intel_dp->attached_connector;
4382 struct drm_connector_state *conn_state;
4383 struct intel_crtc_state *crtc_state;
4384 struct intel_crtc *crtc;
4385 int ret;
4386
4387 /* FIXME handle the MST connectors as well */
4388
4389 if (!connector || connector->base.status != connector_status_connected)
4390 return 0;
4391
4392 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4393 ctx);
4394 if (ret)
4395 return ret;
4396
4397 conn_state = connector->base.state;
4398
4399 crtc = to_intel_crtc(conn_state->crtc);
4400 if (!crtc)
4401 return 0;
4402
4403 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4404 if (ret)
4405 return ret;
4406
4407 crtc_state = to_intel_crtc_state(crtc->base.state);
4408
4409 WARN_ON(!intel_crtc_has_dp_encoder(crtc_state));
4410
4411 if (!crtc_state->base.active)
4412 return 0;
4413
4414 if (conn_state->commit &&
4415 !try_wait_for_completion(&conn_state->commit->hw_done))
4416 return 0;
4417
4418 if (!intel_dp_needs_link_retrain(intel_dp))
4419 return 0;
bfd02b3c
VS		 4420
4421 /* Suppress underruns caused by re-training */
4422 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
f56f6648 4423 if (crtc_state->has_pch_encoder)
bfd02b3c
VS		 4424 intel_set_pch_fifo_underrun_reporting(dev_priv,
4425 intel_crtc_pch_transcoder(crtc), false);
4426
4427 intel_dp_start_link_train(intel_dp);
4428 intel_dp_stop_link_train(intel_dp);
4429
4430 /* Keep underrun reporting disabled until things are stable */
0f0f74bc 4431 intel_wait_for_vblank(dev_priv, crtc->pipe);
bfd02b3c
VS		 4432
4433 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
f56f6648 4434 if (crtc_state->has_pch_encoder)
bfd02b3c
VS		 4435 intel_set_pch_fifo_underrun_reporting(dev_priv,
4436 intel_crtc_pch_transcoder(crtc), true);
c85d200e
VS		 4437
4438 return 0;
bfd02b3c
VS		 4439}
4440
c85d200e
VS		 4441/*
4442 * If display is now connected check links status,
4443 * there has been known issues of link loss triggering
4444 * long pulse.
4445 *
4446 * Some sinks (eg. ASUS PB287Q) seem to perform some
4447 * weird HPD ping pong during modesets. So we can apparently
4448 * end up with HPD going low during a modeset, and then
4449 * going back up soon after. And once that happens we must
4450 * retrain the link to get a picture. That's in case no
4451 * userspace component reacted to intermittent HPD dip.
4452 */
4453static bool intel_dp_hotplug(struct intel_encoder *encoder,
4454 struct intel_connector *connector)
5c9114d0 4455{
c85d200e
VS		 4456 struct drm_modeset_acquire_ctx ctx;
4457 bool changed;
4458 int ret;
5c9114d0 4459
c85d200e 4460 changed = intel_encoder_hotplug(encoder, connector);
5c9114d0 4461
c85d200e 4462 drm_modeset_acquire_init(&ctx, 0);
42e5e657 4463
c85d200e
VS		 4464 for (;;) {
4465 ret = intel_dp_retrain_link(encoder, &ctx);
5c9114d0 4466
c85d200e
VS		 4467 if (ret == -EDEADLK) {
4468 drm_modeset_backoff(&ctx);
4469 continue;
4470 }
5c9114d0 4471
c85d200e
VS		 4472 break;
4473 }
d4cb3fd9 4474
c85d200e
VS		 4475 drm_modeset_drop_locks(&ctx);
4476 drm_modeset_acquire_fini(&ctx);
4477 WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
bfd02b3c 4478
c85d200e 4479 return changed;
5c9114d0
SS		 4480}
4481
9844bc87
DP		 4482static void intel_dp_check_service_irq(struct intel_dp *intel_dp)
4483{
4484 u8 val;
4485
4486 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
4487 return;
4488
4489 if (drm_dp_dpcd_readb(&intel_dp->aux,
4490 DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val)
4491 return;
4492
4493 drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);
4494
4495 if (val & DP_AUTOMATED_TEST_REQUEST)
4496 intel_dp_handle_test_request(intel_dp);
4497
4498 if (val & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4499 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4500}
4501
a4fc5ed6
KP		 4502/*
4503 * According to DP spec
4504 * 5.1.2:
4505 * 1. Read DPCD
4506 * 2. Configure link according to Receiver Capabilities
4507 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4508 * 4. Check link status on receipt of hot-plug interrupt
39ff747b
SS		 4509 *
4510 * intel_dp_short_pulse - handles short pulse interrupts
4511 * when full detection is not required.
4512 * Returns %true if short pulse is handled and full detection
4513 * is NOT required and %false otherwise.
a4fc5ed6 4514 */
39ff747b 4515static bool
5c9114d0 4516intel_dp_short_pulse(struct intel_dp *intel_dp)
a4fc5ed6 4517{
de25eb7f 4518 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
39ff747b
SS		 4519 u8 old_sink_count = intel_dp->sink_count;
4520 bool ret;
5b215bcf 4521
4df6960e
SS		 4522 /*
4523 * Clearing compliance test variables to allow capturing
4524 * of values for next automated test request.
4525 */
c1617abc 4526 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4df6960e 4527
39ff747b
SS		 4528 /*
4529 * Now read the DPCD to see if it's actually running
4530 * If the current value of sink count doesn't match with
4531 * the value that was stored earlier or dpcd read failed
4532 * we need to do full detection
4533 */
4534 ret = intel_dp_get_dpcd(intel_dp);
4535
4536 if ((old_sink_count != intel_dp->sink_count) || !ret) {
4537 /* No need to proceed if we are going to do full detect */
4538 return false;
59cd09e1
JB		 4539 }
4540
9844bc87 4541 intel_dp_check_service_irq(intel_dp);
a60f0e38 4542
82e00d11
HV		 4543 /* Handle CEC interrupts, if any */
4544 drm_dp_cec_irq(&intel_dp->aux);
4545
c85d200e
VS		 4546 /* defer to the hotplug work for link retraining if needed */
4547 if (intel_dp_needs_link_retrain(intel_dp))
4548 return false;
42e5e657 4549
cc3054ff
JRS		 4550 intel_psr_short_pulse(intel_dp);
4551
da15f7cb
MN		 4552 if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
4553 DRM_DEBUG_KMS("Link Training Compliance Test requested\n");
4554 /* Send a Hotplug Uevent to userspace to start modeset */
2f773477 4555 drm_kms_helper_hotplug_event(&dev_priv->drm);
da15f7cb 4556 }
39ff747b
SS		 4557
4558 return true;
a4fc5ed6 4559}
a4fc5ed6 4560
caf9ab24 4561/* XXX this is probably wrong for multiple downstream ports */
71ba9000 4562static enum drm_connector_status
26d61aad 4563intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 4564{
e393d0d6 4565 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
caf9ab24 4566 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 4567 uint8_t type;
4568
e393d0d6
ID		 4569 if (lspcon->active)
4570 lspcon_resume(lspcon);
4571
caf9ab24
AJ		 4572 if (!intel_dp_get_dpcd(intel_dp))
4573 return connector_status_disconnected;
4574
1853a9da 4575 if (intel_dp_is_edp(intel_dp))
1034ce70
SS		 4576 return connector_status_connected;
4577
caf9ab24 4578 /* if there's no downstream port, we're done */
c726ad01 4579 if (!drm_dp_is_branch(dpcd))
26d61aad 4580 return connector_status_connected;
caf9ab24
AJ		 4581
4582 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 4583 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4584 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
9d1a1031 4585
30d9aa42
SS		 4586 return intel_dp->sink_count ?
4587 connector_status_connected : connector_status_disconnected;
caf9ab24
AJ		 4588 }
4589
c4e3170a
VS		 4590 if (intel_dp_can_mst(intel_dp))
4591 return connector_status_connected;
4592
caf9ab24 4593 /* If no HPD, poke DDC gently */
0b99836f 4594 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 4595 return connector_status_connected;
caf9ab24
AJ		 4596
4597 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 4598 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4599 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4600 if (type == DP_DS_PORT_TYPE_VGA ||
4601 type == DP_DS_PORT_TYPE_NON_EDID)
4602 return connector_status_unknown;
4603 } else {
4604 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4605 DP_DWN_STRM_PORT_TYPE_MASK;
4606 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4607 type == DP_DWN_STRM_PORT_TYPE_OTHER)
4608 return connector_status_unknown;
4609 }
caf9ab24
AJ		 4610
4611 /* Anything else is out of spec, warn and ignore */
4612 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 4613 return connector_status_disconnected;
71ba9000
AJ		 4614}
4615
d410b56d
CW		 4616static enum drm_connector_status
4617edp_detect(struct intel_dp *intel_dp)
4618{
b93b41af 4619 return connector_status_connected;
d410b56d
CW		 4620}
4621
7533eb4f 4622static bool ibx_digital_port_connected(struct intel_encoder *encoder)
5eb08b69 4623{
7533eb4f 4624 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
b93433cc 4625 u32 bit;
01cb9ea6 4626
7533eb4f
RV		 4627 switch (encoder->hpd_pin) {
4628 case HPD_PORT_B:
0df53b77
JN		 4629 bit = SDE_PORTB_HOTPLUG;
4630 break;
7533eb4f 4631 case HPD_PORT_C:
0df53b77
JN		 4632 bit = SDE_PORTC_HOTPLUG;
4633 break;
7533eb4f 4634 case HPD_PORT_D:
0df53b77
JN		 4635 bit = SDE_PORTD_HOTPLUG;
4636 break;
4637 default:
7533eb4f 4638 MISSING_CASE(encoder->hpd_pin);
0df53b77
JN		 4639 return false;
4640 }
4641
4642 return I915_READ(SDEISR) & bit;
4643}
4644
7533eb4f 4645static bool cpt_digital_port_connected(struct intel_encoder *encoder)
0df53b77 4646{
7533eb4f 4647 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
0df53b77
JN		 4648 u32 bit;
4649
7533eb4f
RV		 4650 switch (encoder->hpd_pin) {
4651 case HPD_PORT_B:
0df53b77
JN		 4652 bit = SDE_PORTB_HOTPLUG_CPT;
4653 break;
7533eb4f 4654 case HPD_PORT_C:
0df53b77
JN		 4655 bit = SDE_PORTC_HOTPLUG_CPT;
4656 break;
7533eb4f 4657 case HPD_PORT_D:
0df53b77
JN		 4658 bit = SDE_PORTD_HOTPLUG_CPT;
4659 break;
93e5f0b6 4660 default:
7533eb4f 4661 MISSING_CASE(encoder->hpd_pin);
93e5f0b6
VS		 4662 return false;
4663 }
4664
4665 return I915_READ(SDEISR) & bit;
4666}
4667
7533eb4f 4668static bool spt_digital_port_connected(struct intel_encoder *encoder)
93e5f0b6 4669{
7533eb4f 4670 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
93e5f0b6
VS		 4671 u32 bit;
4672
7533eb4f
RV		 4673 switch (encoder->hpd_pin) {
4674 case HPD_PORT_A:
93e5f0b6
VS		 4675 bit = SDE_PORTA_HOTPLUG_SPT;
4676 break;
7533eb4f 4677 case HPD_PORT_E:
a78695d3
JN		 4678 bit = SDE_PORTE_HOTPLUG_SPT;
4679 break;
0df53b77 4680 default:
7533eb4f 4681 return cpt_digital_port_connected(encoder);
b93433cc 4682 }
1b469639 4683
b93433cc 4684 return I915_READ(SDEISR) & bit;
5eb08b69
ZW		 4685}
4686
7533eb4f 4687static bool g4x_digital_port_connected(struct intel_encoder *encoder)
a4fc5ed6 4688{
7533eb4f 4689 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
9642c81c 4690 u32 bit;
5eb08b69 4691
7533eb4f
RV		 4692 switch (encoder->hpd_pin) {
4693 case HPD_PORT_B:
9642c81c
JN		 4694 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4695 break;
7533eb4f 4696 case HPD_PORT_C:
9642c81c
JN		 4697 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4698 break;
7533eb4f 4699 case HPD_PORT_D:
9642c81c
JN		 4700 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4701 break;
4702 default:
7533eb4f 4703 MISSING_CASE(encoder->hpd_pin);
9642c81c
JN		 4704 return false;
4705 }
4706
4707 return I915_READ(PORT_HOTPLUG_STAT) & bit;
4708}
4709
7533eb4f 4710static bool gm45_digital_port_connected(struct intel_encoder *encoder)
9642c81c 4711{
7533eb4f 4712 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
9642c81c
JN		 4713 u32 bit;
4714
7533eb4f
RV		 4715 switch (encoder->hpd_pin) {
4716 case HPD_PORT_B:
0780cd36 4717 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
9642c81c 4718 break;
7533eb4f 4719 case HPD_PORT_C:
0780cd36 4720 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
9642c81c 4721 break;
7533eb4f 4722 case HPD_PORT_D:
0780cd36 4723 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
9642c81c
JN		 4724 break;
4725 default:
7533eb4f 4726 MISSING_CASE(encoder->hpd_pin);
9642c81c 4727 return false;
a4fc5ed6
KP		 4728 }
4729
1d245987 4730 return I915_READ(PORT_HOTPLUG_STAT) & bit;
2a592bec
DA		 4731}
4732
7533eb4f 4733static bool ilk_digital_port_connected(struct intel_encoder *encoder)
93e5f0b6 4734{
7533eb4f
RV		 4735 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4736
4737 if (encoder->hpd_pin == HPD_PORT_A)
93e5f0b6
VS		 4738 return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
4739 else
7533eb4f 4740 return ibx_digital_port_connected(encoder);
93e5f0b6
VS		 4741}
4742
7533eb4f 4743static bool snb_digital_port_connected(struct intel_encoder *encoder)
93e5f0b6 4744{
7533eb4f
RV		 4745 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4746
4747 if (encoder->hpd_pin == HPD_PORT_A)
93e5f0b6
VS		 4748 return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
4749 else
7533eb4f 4750 return cpt_digital_port_connected(encoder);
93e5f0b6
VS		 4751}
4752
7533eb4f 4753static bool ivb_digital_port_connected(struct intel_encoder *encoder)
93e5f0b6 4754{
7533eb4f
RV		 4755 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4756
4757 if (encoder->hpd_pin == HPD_PORT_A)
93e5f0b6
VS		 4758 return I915_READ(DEISR) & DE_DP_A_HOTPLUG_IVB;
4759 else
7533eb4f 4760 return cpt_digital_port_connected(encoder);
93e5f0b6
VS		 4761}
4762
7533eb4f 4763static bool bdw_digital_port_connected(struct intel_encoder *encoder)
93e5f0b6 4764{
7533eb4f
RV		 4765 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4766
4767 if (encoder->hpd_pin == HPD_PORT_A)
93e5f0b6
VS		 4768 return I915_READ(GEN8_DE_PORT_ISR) & GEN8_PORT_DP_A_HOTPLUG;
4769 else
7533eb4f 4770 return cpt_digital_port_connected(encoder);
93e5f0b6
VS		 4771}
4772
7533eb4f 4773static bool bxt_digital_port_connected(struct intel_encoder *encoder)
e464bfde 4774{
7533eb4f 4775 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
e464bfde
JN		 4776 u32 bit;
4777
7533eb4f
RV		 4778 switch (encoder->hpd_pin) {
4779 case HPD_PORT_A:
e464bfde
JN		 4780 bit = BXT_DE_PORT_HP_DDIA;
4781 break;
7533eb4f 4782 case HPD_PORT_B:
e464bfde
JN		 4783 bit = BXT_DE_PORT_HP_DDIB;
4784 break;
7533eb4f 4785 case HPD_PORT_C:
e464bfde
JN		 4786 bit = BXT_DE_PORT_HP_DDIC;
4787 break;
4788 default:
7533eb4f 4789 MISSING_CASE(encoder->hpd_pin);
e464bfde
JN		 4790 return false;
4791 }
4792
4793 return I915_READ(GEN8_DE_PORT_ISR) & bit;
4794}
4795
b9fcddab
PZ		 4796static bool icl_combo_port_connected(struct drm_i915_private *dev_priv,
4797 struct intel_digital_port *intel_dig_port)
4798{
4799 enum port port = intel_dig_port->base.port;
4800
4801 return I915_READ(SDEISR) & SDE_DDI_HOTPLUG_ICP(port);
4802}
4803
6075546f
PZ		 4804static void icl_update_tc_port_type(struct drm_i915_private *dev_priv,
4805 struct intel_digital_port *intel_dig_port,
4806 bool is_legacy, bool is_typec, bool is_tbt)
4807{
4808 enum port port = intel_dig_port->base.port;
4809 enum tc_port_type old_type = intel_dig_port->tc_type;
4810 const char *type_str;
4811
4812 WARN_ON(is_legacy + is_typec + is_tbt != 1);
4813
4814 if (is_legacy) {
4815 intel_dig_port->tc_type = TC_PORT_LEGACY;
4816 type_str = "legacy";
4817 } else if (is_typec) {
4818 intel_dig_port->tc_type = TC_PORT_TYPEC;
4819 type_str = "typec";
4820 } else if (is_tbt) {
4821 intel_dig_port->tc_type = TC_PORT_TBT;
4822 type_str = "tbt";
4823 } else {
4824 return;
4825 }
4826
4827 /* Types are not supposed to be changed at runtime. */
4828 WARN_ON(old_type != TC_PORT_UNKNOWN &&
4829 old_type != intel_dig_port->tc_type);
4830
4831 if (old_type != intel_dig_port->tc_type)
4832 DRM_DEBUG_KMS("Port %c has TC type %s\n", port_name(port),
4833 type_str);
4834}
4835
39d1e234
PZ		 4836/*
4837 * This function implements the first part of the Connect Flow described by our
4838 * specification, Gen11 TypeC Programming chapter. The rest of the flow (reading
4839 * lanes, EDID, etc) is done as needed in the typical places.
4840 *
4841 * Unlike the other ports, type-C ports are not available to use as soon as we
4842 * get a hotplug. The type-C PHYs can be shared between multiple controllers:
4843 * display, USB, etc. As a result, handshaking through FIA is required around
4844 * connect and disconnect to cleanly transfer ownership with the controller and
4845 * set the type-C power state.
4846 *
4847 * We could opt to only do the connect flow when we actually try to use the AUX
4848 * channels or do a modeset, then immediately run the disconnect flow after
4849 * usage, but there are some implications on this for a dynamic environment:
4850 * things may go away or change behind our backs. So for now our driver is
4851 * always trying to acquire ownership of the controller as soon as it gets an
4852 * interrupt (or polls state and sees a port is connected) and only gives it
4853 * back when it sees a disconnect. Implementation of a more fine-grained model
4854 * will require a lot of coordination with user space and thorough testing for
4855 * the extra possible cases.
4856 */
4857static bool icl_tc_phy_connect(struct drm_i915_private *dev_priv,
4858 struct intel_digital_port *dig_port)
4859{
4860 enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
4861 u32 val;
4862
4863 if (dig_port->tc_type != TC_PORT_LEGACY &&
4864 dig_port->tc_type != TC_PORT_TYPEC)
4865 return true;
4866
4867 val = I915_READ(PORT_TX_DFLEXDPPMS);
4868 if (!(val & DP_PHY_MODE_STATUS_COMPLETED(tc_port))) {
4869 DRM_DEBUG_KMS("DP PHY for TC port %d not ready\n", tc_port);
4870 return false;
4871 }
4872
4873 /*
4874 * This function may be called many times in a row without an HPD event
4875 * in between, so try to avoid the write when we can.
4876 */
4877 val = I915_READ(PORT_TX_DFLEXDPCSSS);
4878 if (!(val & DP_PHY_MODE_STATUS_NOT_SAFE(tc_port))) {
4879 val |= DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
4880 I915_WRITE(PORT_TX_DFLEXDPCSSS, val);
4881 }
4882
4883 /*
4884 * Now we have to re-check the live state, in case the port recently
4885 * became disconnected. Not necessary for legacy mode.
4886 */
4887 if (dig_port->tc_type == TC_PORT_TYPEC &&
4888 !(I915_READ(PORT_TX_DFLEXDPSP) & TC_LIVE_STATE_TC(tc_port))) {
4889 DRM_DEBUG_KMS("TC PHY %d sudden disconnect.\n", tc_port);
4890 val = I915_READ(PORT_TX_DFLEXDPCSSS);
4891 val &= ~DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
4892 I915_WRITE(PORT_TX_DFLEXDPCSSS, val);
4893 return false;
4894 }
4895
4896 return true;
4897}
4898
4899/*
4900 * See the comment at the connect function. This implements the Disconnect
4901 * Flow.
4902 */
4903static void icl_tc_phy_disconnect(struct drm_i915_private *dev_priv,
4904 struct intel_digital_port *dig_port)
4905{
4906 enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
4907 u32 val;
4908
4909 if (dig_port->tc_type != TC_PORT_LEGACY &&
4910 dig_port->tc_type != TC_PORT_TYPEC)
4911 return;
4912
4913 /*
4914 * This function may be called many times in a row without an HPD event
4915 * in between, so try to avoid the write when we can.
4916 */
4917 val = I915_READ(PORT_TX_DFLEXDPCSSS);
4918 if (val & DP_PHY_MODE_STATUS_NOT_SAFE(tc_port)) {
4919 val &= ~DP_PHY_MODE_STATUS_NOT_SAFE(tc_port);
4920 I915_WRITE(PORT_TX_DFLEXDPCSSS, val);
4921 }
4922}
4923
4924/*
4925 * The type-C ports are different because even when they are connected, they may
4926 * not be available/usable by the graphics driver: see the comment on
4927 * icl_tc_phy_connect(). So in our driver instead of adding the additional
4928 * concept of "usable" and make everything check for "connected and usable" we
4929 * define a port as "connected" when it is not only connected, but also when it
4930 * is usable by the rest of the driver. That maintains the old assumption that
4931 * connected ports are usable, and avoids exposing to the users objects they
4932 * can't really use.
4933 */
b9fcddab
PZ		 4934static bool icl_tc_port_connected(struct drm_i915_private *dev_priv,
4935 struct intel_digital_port *intel_dig_port)
4936{
4937 enum port port = intel_dig_port->base.port;
4938 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
4939 bool is_legacy, is_typec, is_tbt;
4940 u32 dpsp;
4941
4942 is_legacy = I915_READ(SDEISR) & SDE_TC_HOTPLUG_ICP(tc_port);
4943
4944 /*
4945 * The spec says we shouldn't be using the ISR bits for detecting
4946 * between TC and TBT. We should use DFLEXDPSP.
4947 */
4948 dpsp = I915_READ(PORT_TX_DFLEXDPSP);
4949 is_typec = dpsp & TC_LIVE_STATE_TC(tc_port);
4950 is_tbt = dpsp & TC_LIVE_STATE_TBT(tc_port);
4951
39d1e234
PZ		 4952 if (!is_legacy && !is_typec && !is_tbt) {
4953 icl_tc_phy_disconnect(dev_priv, intel_dig_port);
6075546f 4954 return false;
39d1e234 4955 }
6075546f
PZ		 4956
4957 icl_update_tc_port_type(dev_priv, intel_dig_port, is_legacy, is_typec,
4958 is_tbt);
b9fcddab 4959
39d1e234
PZ		 4960 if (!icl_tc_phy_connect(dev_priv, intel_dig_port))
4961 return false;
4962
6075546f 4963 return true;
b9fcddab
PZ		 4964}
4965
4966static bool icl_digital_port_connected(struct intel_encoder *encoder)
4967{
4968 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4969 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
4970
4971 switch (encoder->hpd_pin) {
4972 case HPD_PORT_A:
4973 case HPD_PORT_B:
4974 return icl_combo_port_connected(dev_priv, dig_port);
4975 case HPD_PORT_C:
4976 case HPD_PORT_D:
4977 case HPD_PORT_E:
4978 case HPD_PORT_F:
4979 return icl_tc_port_connected(dev_priv, dig_port);
4980 default:
4981 MISSING_CASE(encoder->hpd_pin);
4982 return false;
4983 }
4984}
4985
7e66bcf2
JN		 4986/*
4987 * intel_digital_port_connected - is the specified port connected?
7533eb4f 4988 * @encoder: intel_encoder
7e66bcf2 4989 *
39d1e234
PZ		 4990 * In cases where there's a connector physically connected but it can't be used
4991 * by our hardware we also return false, since the rest of the driver should
4992 * pretty much treat the port as disconnected. This is relevant for type-C
4993 * (starting on ICL) where there's ownership involved.
4994 *
7533eb4f 4995 * Return %true if port is connected, %false otherwise.
7e66bcf2 4996 */
7533eb4f 4997bool intel_digital_port_connected(struct intel_encoder *encoder)
7e66bcf2 4998{
7533eb4f
RV		 4999 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5000
93e5f0b6
VS		 5001 if (HAS_GMCH_DISPLAY(dev_priv)) {
5002 if (IS_GM45(dev_priv))
7533eb4f 5003 return gm45_digital_port_connected(encoder);
93e5f0b6 5004 else
7533eb4f 5005 return g4x_digital_port_connected(encoder);
93e5f0b6
VS		 5006 }
5007
5008 if (IS_GEN5(dev_priv))
7533eb4f 5009 return ilk_digital_port_connected(encoder);
93e5f0b6 5010 else if (IS_GEN6(dev_priv))
7533eb4f 5011 return snb_digital_port_connected(encoder);
93e5f0b6 5012 else if (IS_GEN7(dev_priv))
7533eb4f 5013 return ivb_digital_port_connected(encoder);
93e5f0b6 5014 else if (IS_GEN8(dev_priv))
7533eb4f 5015 return bdw_digital_port_connected(encoder);
cc3f90f0 5016 else if (IS_GEN9_LP(dev_priv))
7533eb4f 5017 return bxt_digital_port_connected(encoder);
b9fcddab 5018 else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv))
7533eb4f 5019 return spt_digital_port_connected(encoder);
b9fcddab
PZ		 5020 else
5021 return icl_digital_port_connected(encoder);
7e66bcf2
JN		 5022}
5023
8c241fef 5024static struct edid *
beb60608 5025intel_dp_get_edid(struct intel_dp *intel_dp)
8c241fef 5026{
beb60608 5027 struct intel_connector *intel_connector = intel_dp->attached_connector;
d6f24d0f 5028
9cd300e0
JN		 5029 /* use cached edid if we have one */
5030 if (intel_connector->edid) {
9cd300e0
JN		 5031 /* invalid edid */
5032 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 5033 return NULL;
5034
55e9edeb 5035 return drm_edid_duplicate(intel_connector->edid);
beb60608
CW		 5036 } else
5037 return drm_get_edid(&intel_connector->base,
5038 &intel_dp->aux.ddc);
5039}
8c241fef 5040
beb60608
CW		 5041static void
5042intel_dp_set_edid(struct intel_dp *intel_dp)
5043{
5044 struct intel_connector *intel_connector = intel_dp->attached_connector;
5045 struct edid *edid;
8c241fef 5046
f21a2198 5047 intel_dp_unset_edid(intel_dp);
beb60608
CW		 5048 edid = intel_dp_get_edid(intel_dp);
5049 intel_connector->detect_edid = edid;
5050
e6b72c94 5051 intel_dp->has_audio = drm_detect_monitor_audio(edid);
82e00d11 5052 drm_dp_cec_set_edid(&intel_dp->aux, edid);
8c241fef
KP		 5053}
5054
beb60608
CW		 5055static void
5056intel_dp_unset_edid(struct intel_dp *intel_dp)
8c241fef 5057{
beb60608 5058 struct intel_connector *intel_connector = intel_dp->attached_connector;
8c241fef 5059
82e00d11 5060 drm_dp_cec_unset_edid(&intel_dp->aux);
beb60608
CW		 5061 kfree(intel_connector->detect_edid);
5062 intel_connector->detect_edid = NULL;
9cd300e0 5063
beb60608
CW		 5064 intel_dp->has_audio = false;
5065}
d6f24d0f 5066
6c5ed5ae 5067static int
cbfa8ac8
DP		 5068intel_dp_detect(struct drm_connector *connector,
5069 struct drm_modeset_acquire_ctx *ctx,
5070 bool force)
a9756bb5 5071{
cbfa8ac8
DP		 5072 struct drm_i915_private *dev_priv = to_i915(connector->dev);
5073 struct intel_dp *intel_dp = intel_attached_dp(connector);
d5acd97f 5074 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
a9756bb5 5075 enum drm_connector_status status;
a9756bb5 5076
cbfa8ac8
DP		 5077 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5078 connector->base.id, connector->name);
2f773477 5079 WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
6c5ed5ae 5080
2f773477 5081 intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
a9756bb5 5082
b93b41af 5083 /* Can't disconnect eDP */
1853a9da 5084 if (intel_dp_is_edp(intel_dp))
d410b56d 5085 status = edp_detect(intel_dp);
d5acd97f 5086 else if (intel_digital_port_connected(encoder))
c555a81d 5087 status = intel_dp_detect_dpcd(intel_dp);
a9756bb5 5088 else
c555a81d
ACO		 5089 status = connector_status_disconnected;
5090
5cb651a7 5091 if (status == connector_status_disconnected) {
c1617abc 5092 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4df6960e 5093
0e505a08 5094 if (intel_dp->is_mst) {
5095 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
5096 intel_dp->is_mst,
5097 intel_dp->mst_mgr.mst_state);
5098 intel_dp->is_mst = false;
5099 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5100 intel_dp->is_mst);
5101 }
5102
c8c8fb33 5103 goto out;
4df6960e 5104 }
a9756bb5 5105
d7e8ef02 5106 if (intel_dp->reset_link_params) {
540b0b7f
JN		 5107 /* Initial max link lane count */
5108 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
f482984a 5109
540b0b7f
JN		 5110 /* Initial max link rate */
5111 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
d7e8ef02
MN		 5112
5113 intel_dp->reset_link_params = false;
5114 }
f482984a 5115
fe5a66f9
VS		 5116 intel_dp_print_rates(intel_dp);
5117
84c36753
JN		 5118 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
5119 drm_dp_is_branch(intel_dp->dpcd));
0e390a33 5120
c4e3170a
VS		 5121 intel_dp_configure_mst(intel_dp);
5122
5123 if (intel_dp->is_mst) {
f21a2198
SS		 5124 /*
5125 * If we are in MST mode then this connector
5126 * won't appear connected or have anything
5127 * with EDID on it
5128 */
0e32b39c
DA		 5129 status = connector_status_disconnected;
5130 goto out;
f24f6eb9
DP		 5131 }
5132
5133 /*
5134 * Some external monitors do not signal loss of link synchronization
5135 * with an IRQ_HPD, so force a link status check.
5136 */
47658556
DP		 5137 if (!intel_dp_is_edp(intel_dp)) {
5138 int ret;
5139
5140 ret = intel_dp_retrain_link(encoder, ctx);
5141 if (ret) {
5142 intel_display_power_put(dev_priv,
5143 intel_dp->aux_power_domain);
5144 return ret;
5145 }
5146 }
0e32b39c 5147
4df6960e
SS		 5148 /*
5149 * Clearing NACK and defer counts to get their exact values
5150 * while reading EDID which are required by Compliance tests
5151 * 4.2.2.4 and 4.2.2.5
5152 */
5153 intel_dp->aux.i2c_nack_count = 0;
5154 intel_dp->aux.i2c_defer_count = 0;
5155
beb60608 5156 intel_dp_set_edid(intel_dp);
cbfa8ac8
DP		 5157 if (intel_dp_is_edp(intel_dp) ||
5158 to_intel_connector(connector)->detect_edid)
5cb651a7 5159 status = connector_status_connected;
c8c8fb33 5160
9844bc87 5161 intel_dp_check_service_irq(intel_dp);
09b1eb13 5162
c8c8fb33 5163out:
5cb651a7 5164 if (status != connector_status_connected && !intel_dp->is_mst)
f21a2198 5165 intel_dp_unset_edid(intel_dp);
7d23e3c3 5166
2f773477 5167 intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
5cb651a7 5168 return status;
f21a2198
SS		 5169}
5170
beb60608
CW		 5171static void
5172intel_dp_force(struct drm_connector *connector)
a4fc5ed6 5173{
df0e9248 5174 struct intel_dp *intel_dp = intel_attached_dp(connector);
beb60608 5175 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
25f78f58 5176 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
a4fc5ed6 5177
beb60608
CW		 5178 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5179 connector->base.id, connector->name);
5180 intel_dp_unset_edid(intel_dp);
a4fc5ed6 5181
beb60608
CW		 5182 if (connector->status != connector_status_connected)
5183 return;
671dedd2 5184
5432fcaf 5185 intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
beb60608
CW		 5186
5187 intel_dp_set_edid(intel_dp);
5188
5432fcaf 5189 intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
beb60608
CW		 5190}
5191
5192static int intel_dp_get_modes(struct drm_connector *connector)
5193{
5194 struct intel_connector *intel_connector = to_intel_connector(connector);
5195 struct edid *edid;
5196
5197 edid = intel_connector->detect_edid;
5198 if (edid) {
5199 int ret = intel_connector_update_modes(connector, edid);
5200 if (ret)
5201 return ret;
5202 }
32f9d658 5203
f8779fda 5204 /* if eDP has no EDID, fall back to fixed mode */
1853a9da 5205 if (intel_dp_is_edp(intel_attached_dp(connector)) &&
beb60608 5206 intel_connector->panel.fixed_mode) {
f8779fda 5207 struct drm_display_mode *mode;
beb60608
CW		 5208
5209 mode = drm_mode_duplicate(connector->dev,
dd06f90e 5210 intel_connector->panel.fixed_mode);
f8779fda 5211 if (mode) {
32f9d658
ZW		 5212 drm_mode_probed_add(connector, mode);
5213 return 1;
5214 }
5215 }
beb60608 5216
32f9d658 5217 return 0;
a4fc5ed6
KP		 5218}
5219
7a418e34
CW		 5220static int
5221intel_dp_connector_register(struct drm_connector *connector)
5222{
5223 struct intel_dp *intel_dp = intel_attached_dp(connector);
82e00d11 5224 struct drm_device *dev = connector->dev;
1ebaa0b9
CW		 5225 int ret;
5226
5227 ret = intel_connector_register(connector);
5228 if (ret)
5229 return ret;
7a418e34
CW		 5230
5231 i915_debugfs_connector_add(connector);
5232
5233 DRM_DEBUG_KMS("registering %s bus for %s\n",
5234 intel_dp->aux.name, connector->kdev->kobj.name);
5235
5236 intel_dp->aux.dev = connector->kdev;
82e00d11
HV		 5237 ret = drm_dp_aux_register(&intel_dp->aux);
5238 if (!ret)
5239 drm_dp_cec_register_connector(&intel_dp->aux,
5240 connector->name, dev->dev);
5241 return ret;
7a418e34
CW		 5242}
5243
c191eca1
CW		 5244static void
5245intel_dp_connector_unregister(struct drm_connector *connector)
5246{
82e00d11
HV		 5247 struct intel_dp *intel_dp = intel_attached_dp(connector);
5248
5249 drm_dp_cec_unregister_connector(&intel_dp->aux);
5250 drm_dp_aux_unregister(&intel_dp->aux);
c191eca1
CW		 5251 intel_connector_unregister(connector);
5252}
5253
a4fc5ed6 5254static void
73845adf 5255intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 5256{
1d508706 5257 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 5258
10e972d3 5259 kfree(intel_connector->detect_edid);
beb60608 5260
9cd300e0
JN		 5261 if (!IS_ERR_OR_NULL(intel_connector->edid))
5262 kfree(intel_connector->edid);
5263
bc3213c4 5264 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 5265
a4fc5ed6 5266 drm_connector_cleanup(connector);
55f78c43 5267 kfree(connector);
a4fc5ed6
KP		 5268}
5269
00c09d70 5270void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 5271{
da63a9f2
PZ		 5272 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
5273 struct intel_dp *intel_dp = &intel_dig_port->dp;
24d05927 5274
0e32b39c 5275 intel_dp_mst_encoder_cleanup(intel_dig_port);
1853a9da 5276 if (intel_dp_is_edp(intel_dp)) {
bd943159 5277 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 5278 /*
5279 * vdd might still be enabled do to the delayed vdd off.
5280 * Make sure vdd is actually turned off here.
5281 */
773538e8 5282 pps_lock(intel_dp);
4be73780 5283 edp_panel_vdd_off_sync(intel_dp);
773538e8
VS		 5284 pps_unlock(intel_dp);
5285
01527b31
CT		 5286 if (intel_dp->edp_notifier.notifier_call) {
5287 unregister_reboot_notifier(&intel_dp->edp_notifier);
5288 intel_dp->edp_notifier.notifier_call = NULL;
5289 }
bd943159 5290 }
99681886
CW		 5291
5292 intel_dp_aux_fini(intel_dp);
5293
c8bd0e49 5294 drm_encoder_cleanup(encoder);
da63a9f2 5295 kfree(intel_dig_port);
24d05927
DV		 5296}
5297
bf93ba67 5298void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
07f9cd0b
ID		 5299{
5300 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
5301
1853a9da 5302 if (!intel_dp_is_edp(intel_dp))
07f9cd0b
ID		 5303 return;
5304
951468f3
VS		 5305 /*
5306 * vdd might still be enabled do to the delayed vdd off.
5307 * Make sure vdd is actually turned off here.
5308 */
afa4e53a 5309 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
773538e8 5310 pps_lock(intel_dp);
07f9cd0b 5311 edp_panel_vdd_off_sync(intel_dp);
773538e8 5312 pps_unlock(intel_dp);
07f9cd0b
ID		 5313}
5314
20f24d77
SP		 5315static
5316int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
5317 u8 *an)
5318{
5319 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_dig_port->base.base);
32078b72
VS		 5320 static const struct drm_dp_aux_msg msg = {
5321 .request = DP_AUX_NATIVE_WRITE,
5322 .address = DP_AUX_HDCP_AKSV,
5323 .size = DRM_HDCP_KSV_LEN,
5324 };
5325 uint8_t txbuf[HEADER_SIZE + DRM_HDCP_KSV_LEN] = {}, rxbuf[2], reply = 0;
20f24d77
SP		 5326 ssize_t dpcd_ret;
5327 int ret;
5328
5329 /* Output An first, that's easy */
5330 dpcd_ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux, DP_AUX_HDCP_AN,
5331 an, DRM_HDCP_AN_LEN);
5332 if (dpcd_ret != DRM_HDCP_AN_LEN) {
5333 DRM_ERROR("Failed to write An over DP/AUX (%zd)\n", dpcd_ret);
5334 return dpcd_ret >= 0 ? -EIO : dpcd_ret;
5335 }
5336
5337 /*
5338 * Since Aksv is Oh-So-Secret, we can't access it in software. So in
5339 * order to get it on the wire, we need to create the AUX header as if
5340 * we were writing the data, and then tickle the hardware to output the
5341 * data once the header is sent out.
5342 */
32078b72 5343 intel_dp_aux_header(txbuf, &msg);
20f24d77 5344
32078b72 5345 ret = intel_dp_aux_xfer(intel_dp, txbuf, HEADER_SIZE + msg.size,
8159c796
VS		 5346 rxbuf, sizeof(rxbuf),
5347 DP_AUX_CH_CTL_AUX_AKSV_SELECT);
20f24d77
SP		 5348 if (ret < 0) {
5349 DRM_ERROR("Write Aksv over DP/AUX failed (%d)\n", ret);
5350 return ret;
5351 } else if (ret == 0) {
5352 DRM_ERROR("Aksv write over DP/AUX was empty\n");
5353 return -EIO;
5354 }
5355
5356 reply = (rxbuf[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK;
5357 return reply == DP_AUX_NATIVE_REPLY_ACK ? 0 : -EIO;
5358}
5359
5360static int intel_dp_hdcp_read_bksv(struct intel_digital_port *intel_dig_port,
5361 u8 *bksv)
5362{
5363 ssize_t ret;
5364 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv,
5365 DRM_HDCP_KSV_LEN);
5366 if (ret != DRM_HDCP_KSV_LEN) {
5367 DRM_ERROR("Read Bksv from DP/AUX failed (%zd)\n", ret);
5368 return ret >= 0 ? -EIO : ret;
5369 }
5370 return 0;
5371}
5372
5373static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port,
5374 u8 *bstatus)
5375{
5376 ssize_t ret;
5377 /*
5378 * For some reason the HDMI and DP HDCP specs call this register
5379 * definition by different names. In the HDMI spec, it's called BSTATUS,
5380 * but in DP it's called BINFO.
5381 */
5382 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BINFO,
5383 bstatus, DRM_HDCP_BSTATUS_LEN);
5384 if (ret != DRM_HDCP_BSTATUS_LEN) {
5385 DRM_ERROR("Read bstatus from DP/AUX failed (%zd)\n", ret);
5386 return ret >= 0 ? -EIO : ret;
5387 }
5388 return 0;
5389}
5390
5391static
791a98dd
R		 5392int intel_dp_hdcp_read_bcaps(struct intel_digital_port *intel_dig_port,
5393 u8 *bcaps)
20f24d77
SP		 5394{
5395 ssize_t ret;
791a98dd 5396
20f24d77 5397 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BCAPS,
791a98dd 5398 bcaps, 1);
20f24d77
SP		 5399 if (ret != 1) {
5400 DRM_ERROR("Read bcaps from DP/AUX failed (%zd)\n", ret);
5401 return ret >= 0 ? -EIO : ret;
5402 }
791a98dd
R		 5403
5404 return 0;
5405}
5406
5407static
5408int intel_dp_hdcp_repeater_present(struct intel_digital_port *intel_dig_port,
5409 bool *repeater_present)
5410{
5411 ssize_t ret;
5412 u8 bcaps;
5413
5414 ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
5415 if (ret)
5416 return ret;
5417
20f24d77
SP		 5418 *repeater_present = bcaps & DP_BCAPS_REPEATER_PRESENT;
5419 return 0;
5420}
5421
5422static
5423int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port,
5424 u8 *ri_prime)
5425{
5426 ssize_t ret;
5427 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME,
5428 ri_prime, DRM_HDCP_RI_LEN);
5429 if (ret != DRM_HDCP_RI_LEN) {
5430 DRM_ERROR("Read Ri' from DP/AUX failed (%zd)\n", ret);
5431 return ret >= 0 ? -EIO : ret;
5432 }
5433 return 0;
5434}
5435
5436static
5437int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port,
5438 bool *ksv_ready)
5439{
5440 ssize_t ret;
5441 u8 bstatus;
5442 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
5443 &bstatus, 1);
5444 if (ret != 1) {
5445 DRM_ERROR("Read bstatus from DP/AUX failed (%zd)\n", ret);
5446 return ret >= 0 ? -EIO : ret;
5447 }
5448 *ksv_ready = bstatus & DP_BSTATUS_READY;
5449 return 0;
5450}
5451
5452static
5453int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port,
5454 int num_downstream, u8 *ksv_fifo)
5455{
5456 ssize_t ret;
5457 int i;
5458
5459 /* KSV list is read via 15 byte window (3 entries @ 5 bytes each) */
5460 for (i = 0; i < num_downstream; i += 3) {
5461 size_t len = min(num_downstream - i, 3) * DRM_HDCP_KSV_LEN;
5462 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
5463 DP_AUX_HDCP_KSV_FIFO,
5464 ksv_fifo + i * DRM_HDCP_KSV_LEN,
5465 len);
5466 if (ret != len) {
5467 DRM_ERROR("Read ksv[%d] from DP/AUX failed (%zd)\n", i,
5468 ret);
5469 return ret >= 0 ? -EIO : ret;
5470 }
5471 }
5472 return 0;
5473}
5474
5475static
5476int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port,
5477 int i, u32 *part)
5478{
5479 ssize_t ret;
5480
5481 if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
5482 return -EINVAL;
5483
5484 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
5485 DP_AUX_HDCP_V_PRIME(i), part,
5486 DRM_HDCP_V_PRIME_PART_LEN);
5487 if (ret != DRM_HDCP_V_PRIME_PART_LEN) {
5488 DRM_ERROR("Read v'[%d] from DP/AUX failed (%zd)\n", i, ret);
5489 return ret >= 0 ? -EIO : ret;
5490 }
5491 return 0;
5492}
5493
5494static
5495int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port,
5496 bool enable)
5497{
5498 /* Not used for single stream DisplayPort setups */
5499 return 0;
5500}
5501
5502static
5503bool intel_dp_hdcp_check_link(struct intel_digital_port *intel_dig_port)
5504{
5505 ssize_t ret;
5506 u8 bstatus;
b7fc1a9b 5507
20f24d77
SP		 5508 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
5509 &bstatus, 1);
5510 if (ret != 1) {
5511 DRM_ERROR("Read bstatus from DP/AUX failed (%zd)\n", ret);
b7fc1a9b 5512 return false;
20f24d77 5513 }
b7fc1a9b 5514
20f24d77
SP		 5515 return !(bstatus & (DP_BSTATUS_LINK_FAILURE | DP_BSTATUS_REAUTH_REQ));
5516}
5517
791a98dd
R		 5518static
5519int intel_dp_hdcp_capable(struct intel_digital_port *intel_dig_port,
5520 bool *hdcp_capable)
5521{
5522 ssize_t ret;
5523 u8 bcaps;
5524
5525 ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
5526 if (ret)
5527 return ret;
5528
5529 *hdcp_capable = bcaps & DP_BCAPS_HDCP_CAPABLE;
5530 return 0;
5531}
5532
20f24d77
SP		 5533static const struct intel_hdcp_shim intel_dp_hdcp_shim = {
5534 .write_an_aksv = intel_dp_hdcp_write_an_aksv,
5535 .read_bksv = intel_dp_hdcp_read_bksv,
5536 .read_bstatus = intel_dp_hdcp_read_bstatus,
5537 .repeater_present = intel_dp_hdcp_repeater_present,
5538 .read_ri_prime = intel_dp_hdcp_read_ri_prime,
5539 .read_ksv_ready = intel_dp_hdcp_read_ksv_ready,
5540 .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo,
5541 .read_v_prime_part = intel_dp_hdcp_read_v_prime_part,
5542 .toggle_signalling = intel_dp_hdcp_toggle_signalling,
5543 .check_link = intel_dp_hdcp_check_link,
791a98dd 5544 .hdcp_capable = intel_dp_hdcp_capable,
20f24d77
SP		 5545};
5546
49e6bc51
VS		 5547static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
5548{
de25eb7f 5549 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
49e6bc51
VS		 5550
5551 lockdep_assert_held(&dev_priv->pps_mutex);
5552
5553 if (!edp_have_panel_vdd(intel_dp))
5554 return;
5555
5556 /*
5557 * The VDD bit needs a power domain reference, so if the bit is
5558 * already enabled when we boot or resume, grab this reference and
5559 * schedule a vdd off, so we don't hold on to the reference
5560 * indefinitely.
5561 */
5562 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
5432fcaf 5563 intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
49e6bc51
VS		 5564
5565 edp_panel_vdd_schedule_off(intel_dp);
5566}
5567
9f2bdb00
VS		 5568static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
5569{
de25eb7f 5570 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
59b74c49
VS		 5571 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
5572 enum pipe pipe;
9f2bdb00 5573
59b74c49
VS		 5574 if (intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
5575 encoder->port, &pipe))
5576 return pipe;
9f2bdb00 5577
59b74c49 5578 return INVALID_PIPE;
9f2bdb00
VS		 5579}
5580
bf93ba67 5581void intel_dp_encoder_reset(struct drm_encoder *encoder)
6d93c0c4 5582{
64989ca4 5583 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
dd75f6dd
ID		 5584 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5585 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
64989ca4
VS		 5586
5587 if (!HAS_DDI(dev_priv))
5588 intel_dp->DP = I915_READ(intel_dp->output_reg);
49e6bc51 5589
dd75f6dd 5590 if (lspcon->active)
910530c0
SS		 5591 lspcon_resume(lspcon);
5592
d7e8ef02
MN		 5593 intel_dp->reset_link_params = true;
5594
49e6bc51
VS		 5595 pps_lock(intel_dp);
5596
9f2bdb00
VS		 5597 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5598 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
5599
1853a9da 5600 if (intel_dp_is_edp(intel_dp)) {
9f2bdb00 5601 /* Reinit the power sequencer, in case BIOS did something with it. */
46bd8383 5602 intel_dp_pps_init(intel_dp);
9f2bdb00
VS		 5603 intel_edp_panel_vdd_sanitize(intel_dp);
5604 }
49e6bc51
VS		 5605
5606 pps_unlock(intel_dp);
6d93c0c4
ID		 5607}
5608
a4fc5ed6 5609static const struct drm_connector_funcs intel_dp_connector_funcs = {
beb60608 5610 .force = intel_dp_force,
a4fc5ed6 5611 .fill_modes = drm_helper_probe_single_connector_modes,
8f647a01
ML		 5612 .atomic_get_property = intel_digital_connector_atomic_get_property,
5613 .atomic_set_property = intel_digital_connector_atomic_set_property,
7a418e34 5614 .late_register = intel_dp_connector_register,
c191eca1 5615 .early_unregister = intel_dp_connector_unregister,
73845adf 5616 .destroy = intel_dp_connector_destroy,
c6f95f27 5617 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
8f647a01 5618 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
a4fc5ed6
KP		 5619};
5620
5621static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
6c5ed5ae 5622 .detect_ctx = intel_dp_detect,
a4fc5ed6
KP		 5623 .get_modes = intel_dp_get_modes,
5624 .mode_valid = intel_dp_mode_valid,
8f647a01 5625 .atomic_check = intel_digital_connector_atomic_check,
a4fc5ed6
KP		 5626};
5627
a4fc5ed6 5628static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6d93c0c4 5629 .reset = intel_dp_encoder_reset,
24d05927 5630 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 5631};
5632
b2c5c181 5633enum irqreturn
13cf5504
DA		 5634intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
5635{
5636 struct intel_dp *intel_dp = &intel_dig_port->dp;
de25eb7f 5637 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
b2c5c181 5638 enum irqreturn ret = IRQ_NONE;
1c767b33 5639
7a7f84cc
VS		 5640 if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
5641 /*
5642 * vdd off can generate a long pulse on eDP which
5643 * would require vdd on to handle it, and thus we
5644 * would end up in an endless cycle of
5645 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
5646 */
5647 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
8f4f2797 5648 port_name(intel_dig_port->base.port));
a8b3d52f 5649 return IRQ_HANDLED;
7a7f84cc
VS		 5650 }
5651
26fbb774 5652 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
8f4f2797 5653 port_name(intel_dig_port->base.port),
0e32b39c 5654 long_hpd ? "long" : "short");
13cf5504 5655
27d4efc5 5656 if (long_hpd) {
d7e8ef02 5657 intel_dp->reset_link_params = true;
27d4efc5
VS		 5658 return IRQ_NONE;
5659 }
5660
5432fcaf 5661 intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
1c767b33 5662
27d4efc5
VS		 5663 if (intel_dp->is_mst) {
5664 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
5665 /*
5666 * If we were in MST mode, and device is not
5667 * there, get out of MST mode
5668 */
5669 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
5670 intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
5671 intel_dp->is_mst = false;
5672 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5673 intel_dp->is_mst);
27d4efc5 5674 goto put_power;
0e32b39c 5675 }
27d4efc5 5676 }
0e32b39c 5677
27d4efc5 5678 if (!intel_dp->is_mst) {
c85d200e 5679 bool handled;
42e5e657
DV		 5680
5681 handled = intel_dp_short_pulse(intel_dp);
5682
20f24d77
SP		 5683 /* Short pulse can signify loss of hdcp authentication */
5684 intel_hdcp_check_link(intel_dp->attached_connector);
5685
cbfa8ac8 5686 if (!handled)
27d4efc5 5687 goto put_power;
0e32b39c 5688 }
b2c5c181
DV		 5689
5690 ret = IRQ_HANDLED;
5691
1c767b33 5692put_power:
5432fcaf 5693 intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
1c767b33
ID		 5694
5695 return ret;
13cf5504
DA		 5696}
5697
477ec328 5698/* check the VBT to see whether the eDP is on another port */
7b91bf7f 5699bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
36e83a18 5700{
53ce81a7
VS		 5701 /*
5702 * eDP not supported on g4x. so bail out early just
5703 * for a bit extra safety in case the VBT is bonkers.
5704 */
dd11bc10 5705 if (INTEL_GEN(dev_priv) < 5)
53ce81a7
VS		 5706 return false;
5707
a98d9c1d 5708 if (INTEL_GEN(dev_priv) < 9 && port == PORT_A)
3b32a35b
VS		 5709 return true;
5710
951d9efe 5711 return intel_bios_is_port_edp(dev_priv, port);
36e83a18
ZY		 5712}
5713
200819ab 5714static void
f684960e
CW		 5715intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
5716{
8b45330a 5717 struct drm_i915_private *dev_priv = to_i915(connector->dev);
68ec0736
VS		 5718 enum port port = dp_to_dig_port(intel_dp)->base.port;
5719
5720 if (!IS_G4X(dev_priv) && port != PORT_A)
5721 intel_attach_force_audio_property(connector);
8b45330a 5722
e953fd7b 5723 intel_attach_broadcast_rgb_property(connector);
53b41837 5724
1853a9da 5725 if (intel_dp_is_edp(intel_dp)) {
8b45330a
ML		 5726 u32 allowed_scalers;
5727
5728 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
5729 if (!HAS_GMCH_DISPLAY(dev_priv))
5730 allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
5731
5732 drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
5733
eead06df 5734 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
8b45330a 5735
53b41837 5736 }
f684960e
CW		 5737}
5738
dada1a9f
ID		 5739static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
5740{
d28d4731 5741 intel_dp->panel_power_off_time = ktime_get_boottime();
dada1a9f
ID		 5742 intel_dp->last_power_on = jiffies;
5743 intel_dp->last_backlight_off = jiffies;
5744}
5745
67a54566 5746static void
46bd8383 5747intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
67a54566 5748{
de25eb7f 5749 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
b0a08bec 5750 u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
8e8232d5 5751 struct pps_registers regs;
453c5420 5752
46bd8383 5753 intel_pps_get_registers(intel_dp, &regs);
67a54566
DV		 5754
5755 /* Workaround: Need to write PP_CONTROL with the unlock key as
5756 * the very first thing. */
b0a08bec 5757 pp_ctl = ironlake_get_pp_control(intel_dp);
67a54566 5758
8e8232d5
ID		 5759 pp_on = I915_READ(regs.pp_on);
5760 pp_off = I915_READ(regs.pp_off);
b0d6a0f2
AS		 5761 if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) &&
5762 !HAS_PCH_ICP(dev_priv)) {
8e8232d5
ID		 5763 I915_WRITE(regs.pp_ctrl, pp_ctl);
5764 pp_div = I915_READ(regs.pp_div);
b0a08bec 5765 }
67a54566
DV		 5766
5767 /* Pull timing values out of registers */
54648618
ID		 5768 seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
5769 PANEL_POWER_UP_DELAY_SHIFT;
67a54566 5770
54648618
ID		 5771 seq->t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
5772 PANEL_LIGHT_ON_DELAY_SHIFT;
67a54566 5773
54648618
ID		 5774 seq->t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
5775 PANEL_LIGHT_OFF_DELAY_SHIFT;
67a54566 5776
54648618
ID		 5777 seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
5778 PANEL_POWER_DOWN_DELAY_SHIFT;
67a54566 5779
b0d6a0f2
AS		 5780 if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
5781 HAS_PCH_ICP(dev_priv)) {
12c8ca9c
MN		 5782 seq->t11_t12 = ((pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
5783 BXT_POWER_CYCLE_DELAY_SHIFT) * 1000;
b0a08bec 5784 } else {
54648618 5785 seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
67a54566 5786 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
b0a08bec 5787 }
54648618
ID		 5788}
5789
de9c1b6b
ID		 5790static void
5791intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
5792{
5793 DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5794 state_name,
5795 seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
5796}
5797
5798static void
46bd8383 5799intel_pps_verify_state(struct intel_dp *intel_dp)
de9c1b6b
ID		 5800{
5801 struct edp_power_seq hw;
5802 struct edp_power_seq *sw = &intel_dp->pps_delays;
5803
46bd8383 5804 intel_pps_readout_hw_state(intel_dp, &hw);
de9c1b6b
ID		 5805
5806 if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
5807 hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
5808 DRM_ERROR("PPS state mismatch\n");
5809 intel_pps_dump_state("sw", sw);
5810 intel_pps_dump_state("hw", &hw);
5811 }
5812}
5813
54648618 5814static void
46bd8383 5815intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp)
54648618 5816{
de25eb7f 5817 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
54648618
ID		 5818 struct edp_power_seq cur, vbt, spec,
5819 *final = &intel_dp->pps_delays;
5820
5821 lockdep_assert_held(&dev_priv->pps_mutex);
5822
5823 /* already initialized? */
5824 if (final->t11_t12 != 0)
5825 return;
5826
46bd8383 5827 intel_pps_readout_hw_state(intel_dp, &cur);
67a54566 5828
de9c1b6b 5829 intel_pps_dump_state("cur", &cur);
67a54566 5830
6aa23e65 5831 vbt = dev_priv->vbt.edp.pps;
c99a259b
MN		 5832 /* On Toshiba Satellite P50-C-18C system the VBT T12 delay
5833 * of 500ms appears to be too short. Ocassionally the panel
5834 * just fails to power back on. Increasing the delay to 800ms
5835 * seems sufficient to avoid this problem.
5836 */
5837 if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) {
7313f5a9 5838 vbt.t11_t12 = max_t(u16, vbt.t11_t12, 1300 * 10);
c99a259b
MN		 5839 DRM_DEBUG_KMS("Increasing T12 panel delay as per the quirk to %d\n",
5840 vbt.t11_t12);
5841 }
770a17a5
MN		 5842 /* T11_T12 delay is special and actually in units of 100ms, but zero
5843 * based in the hw (so we need to add 100 ms). But the sw vbt
5844 * table multiplies it with 1000 to make it in units of 100usec,
5845 * too. */
5846 vbt.t11_t12 += 100 * 10;
67a54566
DV		 5847
5848 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5849 * our hw here, which are all in 100usec. */
5850 spec.t1_t3 = 210 * 10;
5851 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
5852 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
5853 spec.t10 = 500 * 10;
5854 /* This one is special and actually in units of 100ms, but zero
5855 * based in the hw (so we need to add 100 ms). But the sw vbt
5856 * table multiplies it with 1000 to make it in units of 100usec,
5857 * too. */
5858 spec.t11_t12 = (510 + 100) * 10;
5859
de9c1b6b 5860 intel_pps_dump_state("vbt", &vbt);
67a54566
DV		 5861
5862 /* Use the max of the register settings and vbt. If both are
5863 * unset, fall back to the spec limits. */
36b5f425 5864#define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
67a54566
DV		 5865 spec.field : \
5866 max(cur.field, vbt.field))
5867 assign_final(t1_t3);
5868 assign_final(t8);
5869 assign_final(t9);
5870 assign_final(t10);
5871 assign_final(t11_t12);
5872#undef assign_final
5873
36b5f425 5874#define get_delay(field) (DIV_ROUND_UP(final->field, 10))
67a54566
DV		 5875 intel_dp->panel_power_up_delay = get_delay(t1_t3);
5876 intel_dp->backlight_on_delay = get_delay(t8);
5877 intel_dp->backlight_off_delay = get_delay(t9);
5878 intel_dp->panel_power_down_delay = get_delay(t10);
5879 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
5880#undef get_delay
5881
f30d26e4
JN		 5882 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5883 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
5884 intel_dp->panel_power_cycle_delay);
5885
5886 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5887 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
de9c1b6b
ID		 5888
5889 /*
5890 * We override the HW backlight delays to 1 because we do manual waits
5891 * on them. For T8, even BSpec recommends doing it. For T9, if we
5892 * don't do this, we'll end up waiting for the backlight off delay
5893 * twice: once when we do the manual sleep, and once when we disable
5894 * the panel and wait for the PP_STATUS bit to become zero.
5895 */
5896 final->t8 = 1;
5897 final->t9 = 1;
5643205c
ID		 5898
5899 /*
5900 * HW has only a 100msec granularity for t11_t12 so round it up
5901 * accordingly.
5902 */
5903 final->t11_t12 = roundup(final->t11_t12, 100 * 10);
f30d26e4
JN		 5904}
5905
5906static void
46bd8383 5907intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
5d5ab2d2 5908 bool force_disable_vdd)
f30d26e4 5909{
de25eb7f 5910 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
453c5420 5911 u32 pp_on, pp_off, pp_div, port_sel = 0;
e7dc33f3 5912 int div = dev_priv->rawclk_freq / 1000;
8e8232d5 5913 struct pps_registers regs;
8f4f2797 5914 enum port port = dp_to_dig_port(intel_dp)->base.port;
36b5f425 5915 const struct edp_power_seq *seq = &intel_dp->pps_delays;
453c5420 5916
e39b999a 5917 lockdep_assert_held(&dev_priv->pps_mutex);
453c5420 5918
46bd8383 5919 intel_pps_get_registers(intel_dp, &regs);
453c5420 5920
5d5ab2d2
VS		 5921 /*
5922 * On some VLV machines the BIOS can leave the VDD
e7f2af78 5923 * enabled even on power sequencers which aren't
5d5ab2d2
VS		 5924 * hooked up to any port. This would mess up the
5925 * power domain tracking the first time we pick
5926 * one of these power sequencers for use since
5927 * edp_panel_vdd_on() would notice that the VDD was
5928 * already on and therefore wouldn't grab the power
5929 * domain reference. Disable VDD first to avoid this.
5930 * This also avoids spuriously turning the VDD on as
e7f2af78 5931 * soon as the new power sequencer gets initialized.
5d5ab2d2
VS		 5932 */
5933 if (force_disable_vdd) {
5934 u32 pp = ironlake_get_pp_control(intel_dp);
5935
5936 WARN(pp & PANEL_POWER_ON, "Panel power already on\n");
5937
5938 if (pp & EDP_FORCE_VDD)
5939 DRM_DEBUG_KMS("VDD already on, disabling first\n");
5940
5941 pp &= ~EDP_FORCE_VDD;
5942
5943 I915_WRITE(regs.pp_ctrl, pp);
5944 }
5945
f30d26e4 5946 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
de9c1b6b
ID		 5947 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
5948 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 5949 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 5950 /* Compute the divisor for the pp clock, simply match the Bspec
5951 * formula. */
b0d6a0f2
AS		 5952 if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
5953 HAS_PCH_ICP(dev_priv)) {
8e8232d5 5954 pp_div = I915_READ(regs.pp_ctrl);
b0a08bec 5955 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
12c8ca9c 5956 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
b0a08bec
VK		 5957 << BXT_POWER_CYCLE_DELAY_SHIFT);
5958 } else {
5959 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
5960 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5961 << PANEL_POWER_CYCLE_DELAY_SHIFT);
5962 }
67a54566
DV		 5963
5964 /* Haswell doesn't have any port selection bits for the panel
5965 * power sequencer any more. */
920a14b2 5966 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
ad933b56 5967 port_sel = PANEL_PORT_SELECT_VLV(port);
6e266956 5968 } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
05bf51d3
VS		 5969 switch (port) {
5970 case PORT_A:
a24c144c 5971 port_sel = PANEL_PORT_SELECT_DPA;
05bf51d3
VS		 5972 break;
5973 case PORT_C:
5974 port_sel = PANEL_PORT_SELECT_DPC;
5975 break;
5976 case PORT_D:
a24c144c 5977 port_sel = PANEL_PORT_SELECT_DPD;
05bf51d3
VS		 5978 break;
5979 default:
5980 MISSING_CASE(port);
5981 break;
5982 }
67a54566
DV		 5983 }
5984
453c5420
JB		 5985 pp_on |= port_sel;
5986
8e8232d5
ID		 5987 I915_WRITE(regs.pp_on, pp_on);
5988 I915_WRITE(regs.pp_off, pp_off);
b0d6a0f2
AS		 5989 if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
5990 HAS_PCH_ICP(dev_priv))
8e8232d5 5991 I915_WRITE(regs.pp_ctrl, pp_div);
b0a08bec 5992 else
8e8232d5 5993 I915_WRITE(regs.pp_div, pp_div);
67a54566 5994
67a54566 5995 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
8e8232d5
ID		 5996 I915_READ(regs.pp_on),
5997 I915_READ(regs.pp_off),
b0d6a0f2
AS		 5998 (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
5999 HAS_PCH_ICP(dev_priv)) ?
8e8232d5
ID		 6000 (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
6001 I915_READ(regs.pp_div));
f684960e
CW		 6002}
6003
46bd8383 6004static void intel_dp_pps_init(struct intel_dp *intel_dp)
335f752b 6005{
de25eb7f 6006 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
920a14b2
TU		 6007
6008 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
335f752b
ID		 6009 vlv_initial_power_sequencer_setup(intel_dp);
6010 } else {
46bd8383
VS		 6011 intel_dp_init_panel_power_sequencer(intel_dp);
6012 intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
335f752b
ID		 6013 }
6014}
6015
b33a2815
VK		 6016/**
6017 * intel_dp_set_drrs_state - program registers for RR switch to take effect
5423adf1 6018 * @dev_priv: i915 device
e896402c 6019 * @crtc_state: a pointer to the active intel_crtc_state
b33a2815
VK		 6020 * @refresh_rate: RR to be programmed
6021 *
6022 * This function gets called when refresh rate (RR) has to be changed from
6023 * one frequency to another. Switches can be between high and low RR
6024 * supported by the panel or to any other RR based on media playback (in
6025 * this case, RR value needs to be passed from user space).
6026 *
6027 * The caller of this function needs to take a lock on dev_priv->drrs.
6028 */
85cb48a1 6029static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
5f88a9c6 6030 const struct intel_crtc_state *crtc_state,
85cb48a1 6031 int refresh_rate)
439d7ac0 6032{
439d7ac0 6033 struct intel_encoder *encoder;
96178eeb
VK		 6034 struct intel_digital_port *dig_port = NULL;
6035 struct intel_dp *intel_dp = dev_priv->drrs.dp;
85cb48a1 6036 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
96178eeb 6037 enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
439d7ac0
PB		 6038
6039 if (refresh_rate <= 0) {
6040 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
6041 return;
6042 }
6043
96178eeb
VK		 6044 if (intel_dp == NULL) {
6045 DRM_DEBUG_KMS("DRRS not supported.\n");
439d7ac0
PB		 6046 return;
6047 }
6048
96178eeb
VK		 6049 dig_port = dp_to_dig_port(intel_dp);
6050 encoder = &dig_port->base;
439d7ac0
PB		 6051
6052 if (!intel_crtc) {
6053 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
6054 return;
6055 }
6056
96178eeb 6057 if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
439d7ac0
PB		 6058 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
6059 return;
6060 }
6061
96178eeb
VK		 6062 if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
6063 refresh_rate)
439d7ac0
PB		 6064 index = DRRS_LOW_RR;
6065
96178eeb 6066 if (index == dev_priv->drrs.refresh_rate_type) {
439d7ac0
PB		 6067 DRM_DEBUG_KMS(
6068 "DRRS requested for previously set RR...ignoring\n");
6069 return;
6070 }
6071
85cb48a1 6072 if (!crtc_state->base.active) {
439d7ac0
PB		 6073 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
6074 return;
6075 }
6076
85cb48a1 6077 if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
a4c30b1d
VK		 6078 switch (index) {
6079 case DRRS_HIGH_RR:
6080 intel_dp_set_m_n(intel_crtc, M1_N1);
6081 break;
6082 case DRRS_LOW_RR:
6083 intel_dp_set_m_n(intel_crtc, M2_N2);
6084 break;
6085 case DRRS_MAX_RR:
6086 default:
6087 DRM_ERROR("Unsupported refreshrate type\n");
6088 }
85cb48a1
ML		 6089 } else if (INTEL_GEN(dev_priv) > 6) {
6090 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
649636ef 6091 u32 val;
a4c30b1d 6092
649636ef 6093 val = I915_READ(reg);
439d7ac0 6094 if (index > DRRS_HIGH_RR) {
85cb48a1 6095 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6fa7aec1
VK		 6096 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
6097 else
6098 val |= PIPECONF_EDP_RR_MODE_SWITCH;
439d7ac0 6099 } else {
85cb48a1 6100 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6fa7aec1
VK		 6101 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
6102 else
6103 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
439d7ac0
PB		 6104 }
6105 I915_WRITE(reg, val);
6106 }
6107
4e9ac947
VK		 6108 dev_priv->drrs.refresh_rate_type = index;
6109
6110 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
6111}
6112
b33a2815
VK		 6113/**
6114 * intel_edp_drrs_enable - init drrs struct if supported
6115 * @intel_dp: DP struct
5423adf1 6116 * @crtc_state: A pointer to the active crtc state.
b33a2815
VK		 6117 *
6118 * Initializes frontbuffer_bits and drrs.dp
6119 */
85cb48a1 6120void intel_edp_drrs_enable(struct intel_dp *intel_dp,
5f88a9c6 6121 const struct intel_crtc_state *crtc_state)
c395578e 6122{
de25eb7f 6123 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
c395578e 6124
85cb48a1 6125 if (!crtc_state->has_drrs) {
c395578e
VK		 6126 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
6127 return;
6128 }
6129
da83ef85
RS		 6130 if (dev_priv->psr.enabled) {
6131 DRM_DEBUG_KMS("PSR enabled. Not enabling DRRS.\n");
6132 return;
6133 }
6134
c395578e
VK		 6135 mutex_lock(&dev_priv->drrs.mutex);
6136 if (WARN_ON(dev_priv->drrs.dp)) {
6137 DRM_ERROR("DRRS already enabled\n");
6138 goto unlock;
6139 }
6140
6141 dev_priv->drrs.busy_frontbuffer_bits = 0;
6142
6143 dev_priv->drrs.dp = intel_dp;
6144
6145unlock:
6146 mutex_unlock(&dev_priv->drrs.mutex);
6147}
6148
b33a2815
VK		 6149/**
6150 * intel_edp_drrs_disable - Disable DRRS
6151 * @intel_dp: DP struct
5423adf1 6152 * @old_crtc_state: Pointer to old crtc_state.
b33a2815
VK		 6153 *
6154 */
85cb48a1 6155void intel_edp_drrs_disable(struct intel_dp *intel_dp,
5f88a9c6 6156 const struct intel_crtc_state *old_crtc_state)
c395578e 6157{
de25eb7f 6158 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
c395578e 6159
85cb48a1 6160 if (!old_crtc_state->has_drrs)
c395578e
VK		 6161 return;
6162
6163 mutex_lock(&dev_priv->drrs.mutex);
6164 if (!dev_priv->drrs.dp) {
6165 mutex_unlock(&dev_priv->drrs.mutex);
6166 return;
6167 }
6168
6169 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
85cb48a1
ML		 6170 intel_dp_set_drrs_state(dev_priv, old_crtc_state,
6171 intel_dp->attached_connector->panel.fixed_mode->vrefresh);
c395578e
VK		 6172
6173 dev_priv->drrs.dp = NULL;
6174 mutex_unlock(&dev_priv->drrs.mutex);
6175
6176 cancel_delayed_work_sync(&dev_priv->drrs.work);
6177}
6178
4e9ac947
VK		 6179static void intel_edp_drrs_downclock_work(struct work_struct *work)
6180{
6181 struct drm_i915_private *dev_priv =
6182 container_of(work, typeof(*dev_priv), drrs.work.work);
6183 struct intel_dp *intel_dp;
6184
6185 mutex_lock(&dev_priv->drrs.mutex);
6186
6187 intel_dp = dev_priv->drrs.dp;
6188
6189 if (!intel_dp)
6190 goto unlock;
6191
439d7ac0 6192 /*
4e9ac947
VK		 6193 * The delayed work can race with an invalidate hence we need to
6194 * recheck.
439d7ac0
PB		 6195 */
6196
4e9ac947
VK		 6197 if (dev_priv->drrs.busy_frontbuffer_bits)
6198 goto unlock;
439d7ac0 6199
85cb48a1
ML		 6200 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
6201 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
6202
6203 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
6204 intel_dp->attached_connector->panel.downclock_mode->vrefresh);
6205 }
439d7ac0 6206
4e9ac947 6207unlock:
4e9ac947 6208 mutex_unlock(&dev_priv->drrs.mutex);
439d7ac0
PB		 6209}
6210
b33a2815 6211/**
0ddfd203 6212 * intel_edp_drrs_invalidate - Disable Idleness DRRS
5748b6a1 6213 * @dev_priv: i915 device
b33a2815
VK		 6214 * @frontbuffer_bits: frontbuffer plane tracking bits
6215 *
0ddfd203
R		 6216 * This function gets called everytime rendering on the given planes start.
6217 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
b33a2815
VK		 6218 *
6219 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
6220 */
5748b6a1
CW		 6221void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
6222 unsigned int frontbuffer_bits)
a93fad0f 6223{
a93fad0f
VK		 6224 struct drm_crtc *crtc;
6225 enum pipe pipe;
6226
9da7d693 6227 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
a93fad0f
VK		 6228 return;
6229
88f933a8 6230 cancel_delayed_work(&dev_priv->drrs.work);
3954e733 6231
a93fad0f 6232 mutex_lock(&dev_priv->drrs.mutex);
9da7d693
DV		 6233 if (!dev_priv->drrs.dp) {
6234 mutex_unlock(&dev_priv->drrs.mutex);
6235 return;
6236 }
6237
a93fad0f
VK		 6238 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
6239 pipe = to_intel_crtc(crtc)->pipe;
6240
c1d038c6
DV		 6241 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
6242 dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
6243
0ddfd203 6244 /* invalidate means busy screen hence upclock */
c1d038c6 6245 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
85cb48a1
ML		 6246 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
6247 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
a93fad0f 6248
a93fad0f
VK		 6249 mutex_unlock(&dev_priv->drrs.mutex);
6250}
6251
b33a2815 6252/**
0ddfd203 6253 * intel_edp_drrs_flush - Restart Idleness DRRS
5748b6a1 6254 * @dev_priv: i915 device
b33a2815
VK		 6255 * @frontbuffer_bits: frontbuffer plane tracking bits
6256 *
0ddfd203
R		 6257 * This function gets called every time rendering on the given planes has
6258 * completed or flip on a crtc is completed. So DRRS should be upclocked
6259 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
6260 * if no other planes are dirty.
b33a2815
VK		 6261 *
6262 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
6263 */
5748b6a1
CW		 6264void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
6265 unsigned int frontbuffer_bits)
a93fad0f 6266{
a93fad0f
VK		 6267 struct drm_crtc *crtc;
6268 enum pipe pipe;
6269
9da7d693 6270 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
a93fad0f
VK		 6271 return;
6272
88f933a8 6273 cancel_delayed_work(&dev_priv->drrs.work);
3954e733 6274
a93fad0f 6275 mutex_lock(&dev_priv->drrs.mutex);
9da7d693
DV		 6276 if (!dev_priv->drrs.dp) {
6277 mutex_unlock(&dev_priv->drrs.mutex);
6278 return;
6279 }
6280
a93fad0f
VK		 6281 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
6282 pipe = to_intel_crtc(crtc)->pipe;
c1d038c6
DV		 6283
6284 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
a93fad0f
VK		 6285 dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
6286
0ddfd203 6287 /* flush means busy screen hence upclock */
c1d038c6 6288 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
85cb48a1
ML		 6289 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
6290 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
0ddfd203
R		 6291
6292 /*
6293 * flush also means no more activity hence schedule downclock, if all
6294 * other fbs are quiescent too
6295 */
6296 if (!dev_priv->drrs.busy_frontbuffer_bits)
a93fad0f
VK		 6297 schedule_delayed_work(&dev_priv->drrs.work,
6298 msecs_to_jiffies(1000));
6299 mutex_unlock(&dev_priv->drrs.mutex);
6300}
6301
b33a2815
VK		 6302/**
6303 * DOC: Display Refresh Rate Switching (DRRS)
6304 *
6305 * Display Refresh Rate Switching (DRRS) is a power conservation feature
6306 * which enables swtching between low and high refresh rates,
6307 * dynamically, based on the usage scenario. This feature is applicable
6308 * for internal panels.
6309 *
6310 * Indication that the panel supports DRRS is given by the panel EDID, which
6311 * would list multiple refresh rates for one resolution.
6312 *
6313 * DRRS is of 2 types - static and seamless.
6314 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
6315 * (may appear as a blink on screen) and is used in dock-undock scenario.
6316 * Seamless DRRS involves changing RR without any visual effect to the user
6317 * and can be used during normal system usage. This is done by programming
6318 * certain registers.
6319 *
6320 * Support for static/seamless DRRS may be indicated in the VBT based on
6321 * inputs from the panel spec.
6322 *
6323 * DRRS saves power by switching to low RR based on usage scenarios.
6324 *
2e7a5701
DV		 6325 * The implementation is based on frontbuffer tracking implementation. When
6326 * there is a disturbance on the screen triggered by user activity or a periodic
6327 * system activity, DRRS is disabled (RR is changed to high RR). When there is
6328 * no movement on screen, after a timeout of 1 second, a switch to low RR is
6329 * made.
6330 *
6331 * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
6332 * and intel_edp_drrs_flush() are called.
b33a2815
VK		 6333 *
6334 * DRRS can be further extended to support other internal panels and also
6335 * the scenario of video playback wherein RR is set based on the rate
6336 * requested by userspace.
6337 */
6338
6339/**
6340 * intel_dp_drrs_init - Init basic DRRS work and mutex.
2f773477 6341 * @connector: eDP connector
b33a2815
VK		 6342 * @fixed_mode: preferred mode of panel
6343 *
6344 * This function is called only once at driver load to initialize basic
6345 * DRRS stuff.
6346 *
6347 * Returns:
6348 * Downclock mode if panel supports it, else return NULL.
6349 * DRRS support is determined by the presence of downclock mode (apart
6350 * from VBT setting).
6351 */
4f9db5b5 6352static struct drm_display_mode *
2f773477
VS		 6353intel_dp_drrs_init(struct intel_connector *connector,
6354 struct drm_display_mode *fixed_mode)
4f9db5b5 6355{
2f773477 6356 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
4f9db5b5
PB		 6357 struct drm_display_mode *downclock_mode = NULL;
6358
9da7d693
DV		 6359 INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
6360 mutex_init(&dev_priv->drrs.mutex);
6361
dd11bc10 6362 if (INTEL_GEN(dev_priv) <= 6) {
4f9db5b5
PB		 6363 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
6364 return NULL;
6365 }
6366
6367 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4079b8d1 6368 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4f9db5b5
PB		 6369 return NULL;
6370 }
6371
2f773477
VS		 6372 downclock_mode = intel_find_panel_downclock(dev_priv, fixed_mode,
6373 &connector->base);
4f9db5b5
PB		 6374
6375 if (!downclock_mode) {
a1d26342 6376 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
4f9db5b5
PB		 6377 return NULL;
6378 }
6379
96178eeb 6380 dev_priv->drrs.type = dev_priv->vbt.drrs_type;
4f9db5b5 6381
96178eeb 6382 dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
4079b8d1 6383 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4f9db5b5
PB		 6384 return downclock_mode;
6385}
6386
ed92f0b2 6387static bool intel_edp_init_connector(struct intel_dp *intel_dp,
36b5f425 6388 struct intel_connector *intel_connector)
ed92f0b2 6389{
de25eb7f
RV		 6390 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6391 struct drm_device *dev = &dev_priv->drm;
2f773477 6392 struct drm_connector *connector = &intel_connector->base;
ed92f0b2 6393 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 6394 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 6395 bool has_dpcd;
6396 struct drm_display_mode *scan;
6397 struct edid *edid;
6517d273 6398 enum pipe pipe = INVALID_PIPE;
ed92f0b2 6399
1853a9da 6400 if (!intel_dp_is_edp(intel_dp))
ed92f0b2
PZ		 6401 return true;
6402
97a824e1
ID		 6403 /*
6404 * On IBX/CPT we may get here with LVDS already registered. Since the
6405 * driver uses the only internal power sequencer available for both
6406 * eDP and LVDS bail out early in this case to prevent interfering
6407 * with an already powered-on LVDS power sequencer.
6408 */
2f773477 6409 if (intel_get_lvds_encoder(&dev_priv->drm)) {
97a824e1
ID		 6410 WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
6411 DRM_INFO("LVDS was detected, not registering eDP\n");
6412
6413 return false;
6414 }
6415
49e6bc51 6416 pps_lock(intel_dp);
b4d06ede
ID		 6417
6418 intel_dp_init_panel_power_timestamps(intel_dp);
46bd8383 6419 intel_dp_pps_init(intel_dp);
49e6bc51 6420 intel_edp_panel_vdd_sanitize(intel_dp);
b4d06ede 6421
49e6bc51 6422 pps_unlock(intel_dp);
63635217 6423
ed92f0b2 6424 /* Cache DPCD and EDID for edp. */
fe5a66f9 6425 has_dpcd = intel_edp_init_dpcd(intel_dp);
ed92f0b2 6426
fe5a66f9 6427 if (!has_dpcd) {
ed92f0b2
PZ		 6428 /* if this fails, presume the device is a ghost */
6429 DRM_INFO("failed to retrieve link info, disabling eDP\n");
b4d06ede 6430 goto out_vdd_off;
ed92f0b2
PZ		 6431 }
6432
060c8778 6433 mutex_lock(&dev->mode_config.mutex);
0b99836f 6434 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 6435 if (edid) {
6436 if (drm_add_edid_modes(connector, edid)) {
c555f023 6437 drm_connector_update_edid_property(connector,
ed92f0b2 6438 edid);
ed92f0b2
PZ		 6439 } else {
6440 kfree(edid);
6441 edid = ERR_PTR(-EINVAL);
6442 }
6443 } else {
6444 edid = ERR_PTR(-ENOENT);
6445 }
6446 intel_connector->edid = edid;
6447
d93fa1b4 6448 /* prefer fixed mode from EDID if available */
ed92f0b2
PZ		 6449 list_for_each_entry(scan, &connector->probed_modes, head) {
6450 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
6451 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5 6452 downclock_mode = intel_dp_drrs_init(
4f9db5b5 6453 intel_connector, fixed_mode);
d93fa1b4 6454 break;
ed92f0b2
PZ		 6455 }
6456 }
6457
6458 /* fallback to VBT if available for eDP */
6459 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
6460 fixed_mode = drm_mode_duplicate(dev,
6461 dev_priv->vbt.lfp_lvds_vbt_mode);
df457245 6462 if (fixed_mode) {
ed92f0b2 6463 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
df457245
VS		 6464 connector->display_info.width_mm = fixed_mode->width_mm;
6465 connector->display_info.height_mm = fixed_mode->height_mm;
6466 }
ed92f0b2 6467 }
060c8778 6468 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 6469
920a14b2 6470 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
01527b31
CT		 6471 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
6472 register_reboot_notifier(&intel_dp->edp_notifier);
6517d273
VS		 6473
6474 /*
6475 * Figure out the current pipe for the initial backlight setup.
6476 * If the current pipe isn't valid, try the PPS pipe, and if that
6477 * fails just assume pipe A.
6478 */
9f2bdb00 6479 pipe = vlv_active_pipe(intel_dp);
6517d273
VS		 6480
6481 if (pipe != PIPE_A && pipe != PIPE_B)
6482 pipe = intel_dp->pps_pipe;
6483
6484 if (pipe != PIPE_A && pipe != PIPE_B)
6485 pipe = PIPE_A;
6486
6487 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
6488 pipe_name(pipe));
01527b31
CT		 6489 }
6490
d93fa1b4 6491 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
5507faeb 6492 intel_connector->panel.backlight.power = intel_edp_backlight_power;
6517d273 6493 intel_panel_setup_backlight(connector, pipe);
ed92f0b2 6494
9531221d
HG		 6495 if (fixed_mode)
6496 drm_connector_init_panel_orientation_property(
6497 connector, fixed_mode->hdisplay, fixed_mode->vdisplay);
6498
ed92f0b2 6499 return true;
b4d06ede
ID		 6500
6501out_vdd_off:
6502 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
6503 /*
6504 * vdd might still be enabled do to the delayed vdd off.
6505 * Make sure vdd is actually turned off here.
6506 */
6507 pps_lock(intel_dp);
6508 edp_panel_vdd_off_sync(intel_dp);
6509 pps_unlock(intel_dp);
6510
6511 return false;
ed92f0b2
PZ		 6512}
6513
9301397a
MN		 6514static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
6515{
6516 struct intel_connector *intel_connector;
6517 struct drm_connector *connector;
6518
6519 intel_connector = container_of(work, typeof(*intel_connector),
6520 modeset_retry_work);
6521 connector = &intel_connector->base;
6522 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id,
6523 connector->name);
6524
6525 /* Grab the locks before changing connector property*/
6526 mutex_lock(&connector->dev->mode_config.mutex);
6527 /* Set connector link status to BAD and send a Uevent to notify
6528 * userspace to do a modeset.
6529 */
97e14fbe
DV		 6530 drm_connector_set_link_status_property(connector,
6531 DRM_MODE_LINK_STATUS_BAD);
9301397a
MN		 6532 mutex_unlock(&connector->dev->mode_config.mutex);
6533 /* Send Hotplug uevent so userspace can reprobe */
6534 drm_kms_helper_hotplug_event(connector->dev);
6535}
6536
16c25533 6537bool
f0fec3f2
PZ		 6538intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
6539 struct intel_connector *intel_connector)
a4fc5ed6 6540{
f0fec3f2
PZ		 6541 struct drm_connector *connector = &intel_connector->base;
6542 struct intel_dp *intel_dp = &intel_dig_port->dp;
6543 struct intel_encoder *intel_encoder = &intel_dig_port->base;
6544 struct drm_device *dev = intel_encoder->base.dev;
fac5e23e 6545 struct drm_i915_private *dev_priv = to_i915(dev);
8f4f2797 6546 enum port port = intel_encoder->port;
7a418e34 6547 int type;
a4fc5ed6 6548
9301397a
MN		 6549 /* Initialize the work for modeset in case of link train failure */
6550 INIT_WORK(&intel_connector->modeset_retry_work,
6551 intel_dp_modeset_retry_work_fn);
6552
ccb1a831
VS		 6553 if (WARN(intel_dig_port->max_lanes < 1,
6554 "Not enough lanes (%d) for DP on port %c\n",
6555 intel_dig_port->max_lanes, port_name(port)))
6556 return false;
6557
55cfc580
JN		 6558 intel_dp_set_source_rates(intel_dp);
6559
d7e8ef02 6560 intel_dp->reset_link_params = true;
a4a5d2f8 6561 intel_dp->pps_pipe = INVALID_PIPE;
9f2bdb00 6562 intel_dp->active_pipe = INVALID_PIPE;
a4a5d2f8 6563
ec5b01dd 6564 /* intel_dp vfuncs */
4f8036a2 6565 if (HAS_DDI(dev_priv))
ad64217b
ACO		 6566 intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;
6567
0767935e
DV		 6568 /* Preserve the current hw state. */
6569 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 6570 intel_dp->attached_connector = intel_connector;
3d3dc149 6571
7b91bf7f 6572 if (intel_dp_is_port_edp(dev_priv, port))
b329530c 6573 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 6574 else
6575 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 6576
9f2bdb00
VS		 6577 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6578 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
6579
f7d24902
ID		 6580 /*
6581 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
6582 * for DP the encoder type can be set by the caller to
6583 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
6584 */
6585 if (type == DRM_MODE_CONNECTOR_eDP)
6586 intel_encoder->type = INTEL_OUTPUT_EDP;
6587
c17ed5b5 6588 /* eDP only on port B and/or C on vlv/chv */
920a14b2 6589 if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1853a9da
JN		 6590 intel_dp_is_edp(intel_dp) &&
6591 port != PORT_B && port != PORT_C))
c17ed5b5
VS		 6592 return false;
6593
e7281eab
ID		 6594 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
6595 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
6596 port_name(port));
6597
b329530c 6598 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 6599 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
6600
929168c5 6601 if (!HAS_GMCH_DISPLAY(dev_priv))
05021389 6602 connector->interlace_allowed = true;
a4fc5ed6
KP		 6603 connector->doublescan_allowed = 0;
6604
bdabdb63 6605 intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
5432fcaf 6606
b6339585 6607 intel_dp_aux_init(intel_dp);
7a418e34 6608
f0fec3f2 6609 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 6610 edp_panel_vdd_work);
a4fc5ed6 6611
df0e9248 6612 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6 6613
4f8036a2 6614 if (HAS_DDI(dev_priv))
bcbc889b
PZ		 6615 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
6616 else
6617 intel_connector->get_hw_state = intel_connector_get_hw_state;
6618
0e32b39c 6619 /* init MST on ports that can support it */
1853a9da 6620 if (HAS_DP_MST(dev_priv) && !intel_dp_is_edp(intel_dp) &&
9787e835
RV		 6621 (port == PORT_B || port == PORT_C ||
6622 port == PORT_D || port == PORT_F))
0c9b3715
JN		 6623 intel_dp_mst_encoder_init(intel_dig_port,
6624 intel_connector->base.base.id);
0e32b39c 6625
36b5f425 6626 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
a121f4e5
VS		 6627 intel_dp_aux_fini(intel_dp);
6628 intel_dp_mst_encoder_cleanup(intel_dig_port);
6629 goto fail;
b2f246a8 6630 }
32f9d658 6631
f684960e 6632 intel_dp_add_properties(intel_dp, connector);
20f24d77 6633
fdddd08c 6634 if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
20f24d77
SP		 6635 int ret = intel_hdcp_init(intel_connector, &intel_dp_hdcp_shim);
6636 if (ret)
6637 DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
6638 }
f684960e 6639
a4fc5ed6
KP		 6640 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
6641 * 0xd. Failure to do so will result in spurious interrupts being
6642 * generated on the port when a cable is not attached.
6643 */
1c0f1b3d 6644 if (IS_G45(dev_priv)) {
a4fc5ed6
KP		 6645 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
6646 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
6647 }
16c25533
PZ		 6648
6649 return true;
a121f4e5
VS		 6650
6651fail:
a121f4e5
VS		 6652 drm_connector_cleanup(connector);
6653
6654 return false;
a4fc5ed6 6655}
f0fec3f2 6656
c39055b0 6657bool intel_dp_init(struct drm_i915_private *dev_priv,
457c52d8
CW		 6658 i915_reg_t output_reg,
6659 enum port port)
f0fec3f2
PZ		 6660{
6661 struct intel_digital_port *intel_dig_port;
6662 struct intel_encoder *intel_encoder;
6663 struct drm_encoder *encoder;
6664 struct intel_connector *intel_connector;
6665
b14c5679 6666 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2 6667 if (!intel_dig_port)
457c52d8 6668 return false;
f0fec3f2 6669
08d9bc92 6670 intel_connector = intel_connector_alloc();
11aee0f6
SM		 6671 if (!intel_connector)
6672 goto err_connector_alloc;
f0fec3f2
PZ		 6673
6674 intel_encoder = &intel_dig_port->base;
6675 encoder = &intel_encoder->base;
6676
c39055b0
ACO		 6677 if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
6678 &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,
6679 "DP %c", port_name(port)))
893da0c9 6680 goto err_encoder_init;
f0fec3f2 6681
c85d200e 6682 intel_encoder->hotplug = intel_dp_hotplug;
5bfe2ac0 6683 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70 6684 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 6685 intel_encoder->get_config = intel_dp_get_config;
07f9cd0b 6686 intel_encoder->suspend = intel_dp_encoder_suspend;
920a14b2 6687 if (IS_CHERRYVIEW(dev_priv)) {
9197c88b 6688 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
e4a1d846
CML		 6689 intel_encoder->pre_enable = chv_pre_enable_dp;
6690 intel_encoder->enable = vlv_enable_dp;
1a8ff607 6691 intel_encoder->disable = vlv_disable_dp;
580d3811 6692 intel_encoder->post_disable = chv_post_disable_dp;
d6db995f 6693 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
11a914c2 6694 } else if (IS_VALLEYVIEW(dev_priv)) {
ecff4f3b 6695 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 6696 intel_encoder->pre_enable = vlv_pre_enable_dp;
6697 intel_encoder->enable = vlv_enable_dp;
1a8ff607 6698 intel_encoder->disable = vlv_disable_dp;
49277c31 6699 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 6700 } else {
ecff4f3b
JN		 6701 intel_encoder->pre_enable = g4x_pre_enable_dp;
6702 intel_encoder->enable = g4x_enable_dp;
1a8ff607 6703 intel_encoder->disable = g4x_disable_dp;
51a9f6df 6704 intel_encoder->post_disable = g4x_post_disable_dp;
ab1f90f9 6705 }
f0fec3f2 6706
f0fec3f2 6707 intel_dig_port->dp.output_reg = output_reg;
ccb1a831 6708 intel_dig_port->max_lanes = 4;
f0fec3f2 6709
cca0502b 6710 intel_encoder->type = INTEL_OUTPUT_DP;
79f255a0 6711 intel_encoder->power_domain = intel_port_to_power_domain(port);
920a14b2 6712 if (IS_CHERRYVIEW(dev_priv)) {
882ec384
VS		 6713 if (port == PORT_D)
6714 intel_encoder->crtc_mask = 1 << 2;
6715 else
6716 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
6717 } else {
6718 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
6719 }
bc079e8b 6720 intel_encoder->cloneable = 0;
03cdc1d4 6721 intel_encoder->port = port;
f0fec3f2 6722
13cf5504 6723 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
13cf5504 6724
385e4de0
VS		 6725 if (port != PORT_A)
6726 intel_infoframe_init(intel_dig_port);
6727
11aee0f6
SM		 6728 if (!intel_dp_init_connector(intel_dig_port, intel_connector))
6729 goto err_init_connector;
6730
457c52d8 6731 return true;
11aee0f6
SM		 6732
6733err_init_connector:
6734 drm_encoder_cleanup(encoder);
893da0c9 6735err_encoder_init:
11aee0f6
SM		 6736 kfree(intel_connector);
6737err_connector_alloc:
6738 kfree(intel_dig_port);
457c52d8 6739 return false;
f0fec3f2 6740}
0e32b39c 6741
1a4313d1 6742void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
0e32b39c 6743{
1a4313d1
VS		 6744 struct intel_encoder *encoder;
6745
6746 for_each_intel_encoder(&dev_priv->drm, encoder) {
6747 struct intel_dp *intel_dp;
0e32b39c 6748
1a4313d1
VS		 6749 if (encoder->type != INTEL_OUTPUT_DDI)
6750 continue;
5aa56969 6751
1a4313d1 6752 intel_dp = enc_to_intel_dp(&encoder->base);
5aa56969 6753
1a4313d1 6754 if (!intel_dp->can_mst)
0e32b39c
DA		 6755 continue;
6756
1a4313d1
VS		 6757 if (intel_dp->is_mst)
6758 drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);
0e32b39c
DA		 6759 }
6760}
6761
1a4313d1 6762void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
0e32b39c 6763{
1a4313d1 6764 struct intel_encoder *encoder;
0e32b39c 6765
1a4313d1
VS		 6766 for_each_intel_encoder(&dev_priv->drm, encoder) {
6767 struct intel_dp *intel_dp;
5aa56969 6768 int ret;
0e32b39c 6769
1a4313d1
VS		 6770 if (encoder->type != INTEL_OUTPUT_DDI)
6771 continue;
6772
6773 intel_dp = enc_to_intel_dp(&encoder->base);
6774
6775 if (!intel_dp->can_mst)
5aa56969 6776 continue;
0e32b39c 6777
1a4313d1 6778 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr);
5aa56969 6779 if (ret)
1a4313d1 6780 intel_dp_check_mst_status(intel_dp);
0e32b39c
DA		 6781 }
6782}
Linux 6.x block layer and io_uring tree(s)