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drm/i915: rip out intel_crtc->dpms_mode
[linux-block.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
a4fc5ed6
KP		 31#include "drmP.h"
32#include "drm.h"
33#include "drm_crtc.h"
34#include "drm_crtc_helper.h"
d6f24d0f 35#include "drm_edid.h"
a4fc5ed6
KP		 36#include "intel_drv.h"
37#include "i915_drm.h"
38#include "i915_drv.h"
a4fc5ed6
KP		 39
40#define DP_LINK_STATUS_SIZE 6
41#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42
cfcb0fc9
JB		 43/**
44 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
45 * @intel_dp: DP struct
46 *
47 * If a CPU or PCH DP output is attached to an eDP panel, this function
48 * will return true, and false otherwise.
49 */
50static bool is_edp(struct intel_dp *intel_dp)
51{
52 return intel_dp->base.type == INTEL_OUTPUT_EDP;
53}
54
55/**
56 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
57 * @intel_dp: DP struct
58 *
59 * Returns true if the given DP struct corresponds to a PCH DP port attached
60 * to an eDP panel, false otherwise. Helpful for determining whether we
61 * may need FDI resources for a given DP output or not.
62 */
63static bool is_pch_edp(struct intel_dp *intel_dp)
64{
65 return intel_dp->is_pch_edp;
66}
67
1c95822a
AJ		 68/**
69 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
70 * @intel_dp: DP struct
71 *
72 * Returns true if the given DP struct corresponds to a CPU eDP port.
73 */
74static bool is_cpu_edp(struct intel_dp *intel_dp)
75{
76 return is_edp(intel_dp) && !is_pch_edp(intel_dp);
77}
78
ea5b213a
CW		 79static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
80{
4ef69c7a 81 return container_of(encoder, struct intel_dp, base.base);
ea5b213a 82}
a4fc5ed6 83
df0e9248
CW		 84static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
85{
86 return container_of(intel_attached_encoder(connector),
87 struct intel_dp, base);
88}
89
814948ad
JB		 90/**
91 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
92 * @encoder: DRM encoder
93 *
94 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
95 * by intel_display.c.
96 */
97bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
98{
99 struct intel_dp *intel_dp;
100
101 if (!encoder)
102 return false;
103
104 intel_dp = enc_to_intel_dp(encoder);
105
106 return is_pch_edp(intel_dp);
107}
108
33a34e4e
JB		 109static void intel_dp_start_link_train(struct intel_dp *intel_dp);
110static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
ea5b213a 111static void intel_dp_link_down(struct intel_dp *intel_dp);
a4fc5ed6 112
32f9d658 113void
0206e353 114intel_edp_link_config(struct intel_encoder *intel_encoder,
ea5b213a 115 int *lane_num, int *link_bw)
32f9d658 116{
ea5b213a 117 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
32f9d658 118
ea5b213a
CW		 119 *lane_num = intel_dp->lane_count;
120 if (intel_dp->link_bw == DP_LINK_BW_1_62)
32f9d658 121 *link_bw = 162000;
ea5b213a 122 else if (intel_dp->link_bw == DP_LINK_BW_2_7)
32f9d658
ZW		 123 *link_bw = 270000;
124}
125
94bf2ced
DV		 126int
127intel_edp_target_clock(struct intel_encoder *intel_encoder,
128 struct drm_display_mode *mode)
129{
130 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
131
132 if (intel_dp->panel_fixed_mode)
133 return intel_dp->panel_fixed_mode->clock;
134 else
135 return mode->clock;
136}
137
a4fc5ed6 138static int
ea5b213a 139intel_dp_max_lane_count(struct intel_dp *intel_dp)
a4fc5ed6 140{
9a10f401
KP		 141 int max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
142 switch (max_lane_count) {
143 case 1: case 2: case 4:
144 break;
145 default:
146 max_lane_count = 4;
a4fc5ed6
KP		 147 }
148 return max_lane_count;
149}
150
151static int
ea5b213a 152intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 153{
7183dc29 154 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 155
156 switch (max_link_bw) {
157 case DP_LINK_BW_1_62:
158 case DP_LINK_BW_2_7:
159 break;
160 default:
161 max_link_bw = DP_LINK_BW_1_62;
162 break;
163 }
164 return max_link_bw;
165}
166
167static int
168intel_dp_link_clock(uint8_t link_bw)
169{
170 if (link_bw == DP_LINK_BW_2_7)
171 return 270000;
172 else
173 return 162000;
174}
175
cd9dde44
AJ		 176/*
177 * The units on the numbers in the next two are... bizarre. Examples will
178 * make it clearer; this one parallels an example in the eDP spec.
179 *
180 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
181 *
182 * 270000 * 1 * 8 / 10 == 216000
183 *
184 * The actual data capacity of that configuration is 2.16Gbit/s, so the
185 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
186 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
187 * 119000. At 18bpp that's 2142000 kilobits per second.
188 *
189 * Thus the strange-looking division by 10 in intel_dp_link_required, to
190 * get the result in decakilobits instead of kilobits.
191 */
192
a4fc5ed6 193static int
c898261c 194intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 195{
cd9dde44 196 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 197}
198
fe27d53e
DA		 199static int
200intel_dp_max_data_rate(int max_link_clock, int max_lanes)
201{
202 return (max_link_clock * max_lanes * 8) / 10;
203}
204
c4867936
DV		 205static bool
206intel_dp_adjust_dithering(struct intel_dp *intel_dp,
207 struct drm_display_mode *mode,
cb1793ce 208 bool adjust_mode)
c4867936
DV		 209{
210 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
211 int max_lanes = intel_dp_max_lane_count(intel_dp);
212 int max_rate, mode_rate;
213
214 mode_rate = intel_dp_link_required(mode->clock, 24);
215 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
216
217 if (mode_rate > max_rate) {
218 mode_rate = intel_dp_link_required(mode->clock, 18);
219 if (mode_rate > max_rate)
220 return false;
221
cb1793ce
DV		 222 if (adjust_mode)
223 mode->private_flags
c4867936
DV		 224 |= INTEL_MODE_DP_FORCE_6BPC;
225
226 return true;
227 }
228
229 return true;
230}
231
a4fc5ed6
KP		 232static int
233intel_dp_mode_valid(struct drm_connector *connector,
234 struct drm_display_mode *mode)
235{
df0e9248 236 struct intel_dp *intel_dp = intel_attached_dp(connector);
a4fc5ed6 237
d15456de
KP		 238 if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
239 if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay)
7de56f43
ZY		 240 return MODE_PANEL;
241
d15456de 242 if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay)
7de56f43
ZY		 243 return MODE_PANEL;
244 }
245
cb1793ce 246 if (!intel_dp_adjust_dithering(intel_dp, mode, false))
c4867936 247 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 248
249 if (mode->clock < 10000)
250 return MODE_CLOCK_LOW;
251
0af78a2b
DV		 252 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
253 return MODE_H_ILLEGAL;
254
a4fc5ed6
KP		 255 return MODE_OK;
256}
257
258static uint32_t
259pack_aux(uint8_t *src, int src_bytes)
260{
261 int i;
262 uint32_t v = 0;
263
264 if (src_bytes > 4)
265 src_bytes = 4;
266 for (i = 0; i < src_bytes; i++)
267 v |= ((uint32_t) src[i]) << ((3-i) * 8);
268 return v;
269}
270
271static void
272unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
273{
274 int i;
275 if (dst_bytes > 4)
276 dst_bytes = 4;
277 for (i = 0; i < dst_bytes; i++)
278 dst[i] = src >> ((3-i) * 8);
279}
280
fb0f8fbf
KP		 281/* hrawclock is 1/4 the FSB frequency */
282static int
283intel_hrawclk(struct drm_device *dev)
284{
285 struct drm_i915_private *dev_priv = dev->dev_private;
286 uint32_t clkcfg;
287
288 clkcfg = I915_READ(CLKCFG);
289 switch (clkcfg & CLKCFG_FSB_MASK) {
290 case CLKCFG_FSB_400:
291 return 100;
292 case CLKCFG_FSB_533:
293 return 133;
294 case CLKCFG_FSB_667:
295 return 166;
296 case CLKCFG_FSB_800:
297 return 200;
298 case CLKCFG_FSB_1067:
299 return 266;
300 case CLKCFG_FSB_1333:
301 return 333;
302 /* these two are just a guess; one of them might be right */
303 case CLKCFG_FSB_1600:
304 case CLKCFG_FSB_1600_ALT:
305 return 400;
306 default:
307 return 133;
308 }
309}
310
ebf33b18
KP		 311static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
312{
313 struct drm_device *dev = intel_dp->base.base.dev;
314 struct drm_i915_private *dev_priv = dev->dev_private;
315
316 return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
317}
318
319static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
320{
321 struct drm_device *dev = intel_dp->base.base.dev;
322 struct drm_i915_private *dev_priv = dev->dev_private;
323
324 return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
325}
326
9b984dae
KP		 327static void
328intel_dp_check_edp(struct intel_dp *intel_dp)
329{
330 struct drm_device *dev = intel_dp->base.base.dev;
331 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 332
9b984dae
KP		 333 if (!is_edp(intel_dp))
334 return;
ebf33b18 335 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 336 WARN(1, "eDP powered off while attempting aux channel communication.\n");
337 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
ebf33b18 338 I915_READ(PCH_PP_STATUS),
9b984dae
KP		 339 I915_READ(PCH_PP_CONTROL));
340 }
341}
342
a4fc5ed6 343static int
ea5b213a 344intel_dp_aux_ch(struct intel_dp *intel_dp,
a4fc5ed6
KP		 345 uint8_t *send, int send_bytes,
346 uint8_t *recv, int recv_size)
347{
ea5b213a 348 uint32_t output_reg = intel_dp->output_reg;
4ef69c7a 349 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6
KP		 350 struct drm_i915_private *dev_priv = dev->dev_private;
351 uint32_t ch_ctl = output_reg + 0x10;
352 uint32_t ch_data = ch_ctl + 4;
353 int i;
354 int recv_bytes;
a4fc5ed6 355 uint32_t status;
fb0f8fbf 356 uint32_t aux_clock_divider;
6b4e0a93 357 int try, precharge;
a4fc5ed6 358
9b984dae 359 intel_dp_check_edp(intel_dp);
a4fc5ed6 360 /* The clock divider is based off the hrawclk,
fb0f8fbf
KP		 361 * and would like to run at 2MHz. So, take the
362 * hrawclk value and divide by 2 and use that
6176b8f9
JB		 363 *
364 * Note that PCH attached eDP panels should use a 125MHz input
365 * clock divider.
a4fc5ed6 366 */
1c95822a 367 if (is_cpu_edp(intel_dp)) {
1a2eb460
KP		 368 if (IS_GEN6(dev) || IS_GEN7(dev))
369 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18
ZW		 370 else
371 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
372 } else if (HAS_PCH_SPLIT(dev))
6919132e 373 aux_clock_divider = 63; /* IRL input clock fixed at 125Mhz */
5eb08b69
ZW		 374 else
375 aux_clock_divider = intel_hrawclk(dev) / 2;
376
6b4e0a93
DV		 377 if (IS_GEN6(dev))
378 precharge = 3;
379 else
380 precharge = 5;
381
11bee43e
JB		 382 /* Try to wait for any previous AUX channel activity */
383 for (try = 0; try < 3; try++) {
384 status = I915_READ(ch_ctl);
385 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
386 break;
387 msleep(1);
388 }
389
390 if (try == 3) {
391 WARN(1, "dp_aux_ch not started status 0x%08x\n",
392 I915_READ(ch_ctl));
4f7f7b7e
CW		 393 return -EBUSY;
394 }
395
fb0f8fbf
KP		 396 /* Must try at least 3 times according to DP spec */
397 for (try = 0; try < 5; try++) {
398 /* Load the send data into the aux channel data registers */
4f7f7b7e
CW		 399 for (i = 0; i < send_bytes; i += 4)
400 I915_WRITE(ch_data + i,
401 pack_aux(send + i, send_bytes - i));
0206e353 402
fb0f8fbf 403 /* Send the command and wait for it to complete */
4f7f7b7e
CW		 404 I915_WRITE(ch_ctl,
405 DP_AUX_CH_CTL_SEND_BUSY |
406 DP_AUX_CH_CTL_TIME_OUT_400us |
407 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
408 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
409 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
410 DP_AUX_CH_CTL_DONE |
411 DP_AUX_CH_CTL_TIME_OUT_ERROR |
412 DP_AUX_CH_CTL_RECEIVE_ERROR);
fb0f8fbf 413 for (;;) {
fb0f8fbf
KP		 414 status = I915_READ(ch_ctl);
415 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
416 break;
4f7f7b7e 417 udelay(100);
fb0f8fbf 418 }
0206e353 419
fb0f8fbf 420 /* Clear done status and any errors */
4f7f7b7e
CW		 421 I915_WRITE(ch_ctl,
422 status |
423 DP_AUX_CH_CTL_DONE |
424 DP_AUX_CH_CTL_TIME_OUT_ERROR |
425 DP_AUX_CH_CTL_RECEIVE_ERROR);
d7e96fea
AJ		 426
427 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
428 DP_AUX_CH_CTL_RECEIVE_ERROR))
429 continue;
4f7f7b7e 430 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 431 break;
432 }
433
a4fc5ed6 434 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 435 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
a5b3da54 436 return -EBUSY;
a4fc5ed6
KP		 437 }
438
439 /* Check for timeout or receive error.
440 * Timeouts occur when the sink is not connected
441 */
a5b3da54 442 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 443 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
a5b3da54
KP		 444 return -EIO;
445 }
1ae8c0a5
KP		 446
447 /* Timeouts occur when the device isn't connected, so they're
448 * "normal" -- don't fill the kernel log with these */
a5b3da54 449 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 450 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
a5b3da54 451 return -ETIMEDOUT;
a4fc5ed6
KP		 452 }
453
454 /* Unload any bytes sent back from the other side */
455 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
456 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 457 if (recv_bytes > recv_size)
458 recv_bytes = recv_size;
0206e353 459
4f7f7b7e
CW		 460 for (i = 0; i < recv_bytes; i += 4)
461 unpack_aux(I915_READ(ch_data + i),
462 recv + i, recv_bytes - i);
a4fc5ed6
KP		 463
464 return recv_bytes;
465}
466
467/* Write data to the aux channel in native mode */
468static int
ea5b213a 469intel_dp_aux_native_write(struct intel_dp *intel_dp,
a4fc5ed6
KP		 470 uint16_t address, uint8_t *send, int send_bytes)
471{
472 int ret;
473 uint8_t msg[20];
474 int msg_bytes;
475 uint8_t ack;
476
9b984dae 477 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 478 if (send_bytes > 16)
479 return -1;
480 msg[0] = AUX_NATIVE_WRITE << 4;
481 msg[1] = address >> 8;
eebc863e 482 msg[2] = address & 0xff;
a4fc5ed6
KP		 483 msg[3] = send_bytes - 1;
484 memcpy(&msg[4], send, send_bytes);
485 msg_bytes = send_bytes + 4;
486 for (;;) {
ea5b213a 487 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
a4fc5ed6
KP		 488 if (ret < 0)
489 return ret;
490 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
491 break;
492 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
493 udelay(100);
494 else
a5b3da54 495 return -EIO;
a4fc5ed6
KP		 496 }
497 return send_bytes;
498}
499
500/* Write a single byte to the aux channel in native mode */
501static int
ea5b213a 502intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
a4fc5ed6
KP		 503 uint16_t address, uint8_t byte)
504{
ea5b213a 505 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
a4fc5ed6
KP		 506}
507
508/* read bytes from a native aux channel */
509static int
ea5b213a 510intel_dp_aux_native_read(struct intel_dp *intel_dp,
a4fc5ed6
KP		 511 uint16_t address, uint8_t *recv, int recv_bytes)
512{
513 uint8_t msg[4];
514 int msg_bytes;
515 uint8_t reply[20];
516 int reply_bytes;
517 uint8_t ack;
518 int ret;
519
9b984dae 520 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 521 msg[0] = AUX_NATIVE_READ << 4;
522 msg[1] = address >> 8;
523 msg[2] = address & 0xff;
524 msg[3] = recv_bytes - 1;
525
526 msg_bytes = 4;
527 reply_bytes = recv_bytes + 1;
528
529 for (;;) {
ea5b213a 530 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
a4fc5ed6 531 reply, reply_bytes);
a5b3da54
KP		 532 if (ret == 0)
533 return -EPROTO;
534 if (ret < 0)
a4fc5ed6
KP		 535 return ret;
536 ack = reply[0];
537 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
538 memcpy(recv, reply + 1, ret - 1);
539 return ret - 1;
540 }
541 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
542 udelay(100);
543 else
a5b3da54 544 return -EIO;
a4fc5ed6
KP		 545 }
546}
547
548static int
ab2c0672
DA		 549intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
550 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 551{
ab2c0672 552 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
ea5b213a
CW		 553 struct intel_dp *intel_dp = container_of(adapter,
554 struct intel_dp,
555 adapter);
ab2c0672
DA		 556 uint16_t address = algo_data->address;
557 uint8_t msg[5];
558 uint8_t reply[2];
8316f337 559 unsigned retry;
ab2c0672
DA		 560 int msg_bytes;
561 int reply_bytes;
562 int ret;
563
9b984dae 564 intel_dp_check_edp(intel_dp);
ab2c0672
DA		 565 /* Set up the command byte */
566 if (mode & MODE_I2C_READ)
567 msg[0] = AUX_I2C_READ << 4;
568 else
569 msg[0] = AUX_I2C_WRITE << 4;
570
571 if (!(mode & MODE_I2C_STOP))
572 msg[0] |= AUX_I2C_MOT << 4;
a4fc5ed6 573
ab2c0672
DA		 574 msg[1] = address >> 8;
575 msg[2] = address;
576
577 switch (mode) {
578 case MODE_I2C_WRITE:
579 msg[3] = 0;
580 msg[4] = write_byte;
581 msg_bytes = 5;
582 reply_bytes = 1;
583 break;
584 case MODE_I2C_READ:
585 msg[3] = 0;
586 msg_bytes = 4;
587 reply_bytes = 2;
588 break;
589 default:
590 msg_bytes = 3;
591 reply_bytes = 1;
592 break;
593 }
594
8316f337
DF		 595 for (retry = 0; retry < 5; retry++) {
596 ret = intel_dp_aux_ch(intel_dp,
597 msg, msg_bytes,
598 reply, reply_bytes);
ab2c0672 599 if (ret < 0) {
3ff99164 600 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
ab2c0672
DA		 601 return ret;
602 }
8316f337
DF		 603
604 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
605 case AUX_NATIVE_REPLY_ACK:
606 /* I2C-over-AUX Reply field is only valid
607 * when paired with AUX ACK.
608 */
609 break;
610 case AUX_NATIVE_REPLY_NACK:
611 DRM_DEBUG_KMS("aux_ch native nack\n");
612 return -EREMOTEIO;
613 case AUX_NATIVE_REPLY_DEFER:
614 udelay(100);
615 continue;
616 default:
617 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
618 reply[0]);
619 return -EREMOTEIO;
620 }
621
ab2c0672
DA		 622 switch (reply[0] & AUX_I2C_REPLY_MASK) {
623 case AUX_I2C_REPLY_ACK:
624 if (mode == MODE_I2C_READ) {
625 *read_byte = reply[1];
626 }
627 return reply_bytes - 1;
628 case AUX_I2C_REPLY_NACK:
8316f337 629 DRM_DEBUG_KMS("aux_i2c nack\n");
ab2c0672
DA		 630 return -EREMOTEIO;
631 case AUX_I2C_REPLY_DEFER:
8316f337 632 DRM_DEBUG_KMS("aux_i2c defer\n");
ab2c0672
DA		 633 udelay(100);
634 break;
635 default:
8316f337 636 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
ab2c0672
DA		 637 return -EREMOTEIO;
638 }
639 }
8316f337
DF		 640
641 DRM_ERROR("too many retries, giving up\n");
642 return -EREMOTEIO;
a4fc5ed6
KP		 643}
644
0b5c541b 645static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
bd943159 646static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
0b5c541b 647
a4fc5ed6 648static int
ea5b213a 649intel_dp_i2c_init(struct intel_dp *intel_dp,
55f78c43 650 struct intel_connector *intel_connector, const char *name)
a4fc5ed6 651{
0b5c541b
KP		 652 int ret;
653
d54e9d28 654 DRM_DEBUG_KMS("i2c_init %s\n", name);
ea5b213a
CW		 655 intel_dp->algo.running = false;
656 intel_dp->algo.address = 0;
657 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
658
0206e353 659 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
ea5b213a
CW		 660 intel_dp->adapter.owner = THIS_MODULE;
661 intel_dp->adapter.class = I2C_CLASS_DDC;
0206e353 662 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
ea5b213a
CW		 663 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
664 intel_dp->adapter.algo_data = &intel_dp->algo;
665 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
666
0b5c541b
KP		 667 ironlake_edp_panel_vdd_on(intel_dp);
668 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
bd943159 669 ironlake_edp_panel_vdd_off(intel_dp, false);
0b5c541b 670 return ret;
a4fc5ed6
KP		 671}
672
673static bool
e811f5ae
LP		 674intel_dp_mode_fixup(struct drm_encoder *encoder,
675 const struct drm_display_mode *mode,
a4fc5ed6
KP		 676 struct drm_display_mode *adjusted_mode)
677{
0d3a1bee 678 struct drm_device *dev = encoder->dev;
ea5b213a 679 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
a4fc5ed6 680 int lane_count, clock;
ea5b213a
CW		 681 int max_lane_count = intel_dp_max_lane_count(intel_dp);
682 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
083f9560 683 int bpp, mode_rate;
a4fc5ed6
KP		 684 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
685
d15456de
KP		 686 if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
687 intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode);
1d8e1c75
CW		 688 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
689 mode, adjusted_mode);
0d3a1bee
ZY		 690 }
691
cb1793ce 692 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 693 return false;
694
083f9560
DV		 695 DRM_DEBUG_KMS("DP link computation with max lane count %i "
696 "max bw %02x pixel clock %iKHz\n",
71244653 697 max_lane_count, bws[max_clock], adjusted_mode->clock);
083f9560 698
cb1793ce 699 if (!intel_dp_adjust_dithering(intel_dp, adjusted_mode, true))
c4867936
DV		 700 return false;
701
702 bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
71244653 703 mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
c4867936 704
2514bc51
JB		 705 for (clock = 0; clock <= max_clock; clock++) {
706 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
fe27d53e 707 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
a4fc5ed6 708
083f9560 709 if (mode_rate <= link_avail) {
ea5b213a
CW		 710 intel_dp->link_bw = bws[clock];
711 intel_dp->lane_count = lane_count;
712 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
083f9560
DV		 713 DRM_DEBUG_KMS("DP link bw %02x lane "
714 "count %d clock %d bpp %d\n",
ea5b213a 715 intel_dp->link_bw, intel_dp->lane_count,
083f9560
DV		 716 adjusted_mode->clock, bpp);
717 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
718 mode_rate, link_avail);
a4fc5ed6
KP		 719 return true;
720 }
721 }
722 }
fe27d53e 723
a4fc5ed6
KP		 724 return false;
725}
726
727struct intel_dp_m_n {
728 uint32_t tu;
729 uint32_t gmch_m;
730 uint32_t gmch_n;
731 uint32_t link_m;
732 uint32_t link_n;
733};
734
735static void
736intel_reduce_ratio(uint32_t *num, uint32_t *den)
737{
738 while (*num > 0xffffff || *den > 0xffffff) {
739 *num >>= 1;
740 *den >>= 1;
741 }
742}
743
744static void
36e83a18 745intel_dp_compute_m_n(int bpp,
a4fc5ed6
KP		 746 int nlanes,
747 int pixel_clock,
748 int link_clock,
749 struct intel_dp_m_n *m_n)
750{
751 m_n->tu = 64;
36e83a18 752 m_n->gmch_m = (pixel_clock * bpp) >> 3;
a4fc5ed6
KP		 753 m_n->gmch_n = link_clock * nlanes;
754 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
755 m_n->link_m = pixel_clock;
756 m_n->link_n = link_clock;
757 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
758}
759
760void
761intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
762 struct drm_display_mode *adjusted_mode)
763{
764 struct drm_device *dev = crtc->dev;
6c2b7c12 765 struct intel_encoder *encoder;
a4fc5ed6
KP		 766 struct drm_i915_private *dev_priv = dev->dev_private;
767 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
858fa035 768 int lane_count = 4;
a4fc5ed6 769 struct intel_dp_m_n m_n;
9db4a9c7 770 int pipe = intel_crtc->pipe;
a4fc5ed6
KP		 771
772 /*
21d40d37 773 * Find the lane count in the intel_encoder private
a4fc5ed6 774 */
6c2b7c12
DV		 775 for_each_encoder_on_crtc(dev, crtc, encoder) {
776 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
a4fc5ed6 777
9a10f401
KP		 778 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
779 intel_dp->base.type == INTEL_OUTPUT_EDP)
780 {
ea5b213a 781 lane_count = intel_dp->lane_count;
51190667 782 break;
a4fc5ed6
KP		 783 }
784 }
785
786 /*
787 * Compute the GMCH and Link ratios. The '3' here is
788 * the number of bytes_per_pixel post-LUT, which we always
789 * set up for 8-bits of R/G/B, or 3 bytes total.
790 */
858fa035 791 intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
a4fc5ed6
KP		 792 mode->clock, adjusted_mode->clock, &m_n);
793
c619eed4 794 if (HAS_PCH_SPLIT(dev)) {
9db4a9c7
JB		 795 I915_WRITE(TRANSDATA_M1(pipe),
796 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
797 m_n.gmch_m);
798 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
799 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
800 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
a4fc5ed6 801 } else {
9db4a9c7
JB		 802 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
803 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
804 m_n.gmch_m);
805 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
806 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
807 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
a4fc5ed6
KP		 808 }
809}
810
f01eca2e
KP		 811static void ironlake_edp_pll_on(struct drm_encoder *encoder);
812static void ironlake_edp_pll_off(struct drm_encoder *encoder);
813
a4fc5ed6
KP		 814static void
815intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
816 struct drm_display_mode *adjusted_mode)
817{
e3421a18 818 struct drm_device *dev = encoder->dev;
417e822d 819 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 820 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4ef69c7a 821 struct drm_crtc *crtc = intel_dp->base.base.crtc;
a4fc5ed6
KP		 822 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
823
f01eca2e
KP		 824 /* Turn on the eDP PLL if needed */
825 if (is_edp(intel_dp)) {
826 if (!is_pch_edp(intel_dp))
827 ironlake_edp_pll_on(encoder);
828 else
829 ironlake_edp_pll_off(encoder);
830 }
831
417e822d 832 /*
1a2eb460 833 * There are four kinds of DP registers:
417e822d
KP		 834 *
835 * IBX PCH
1a2eb460
KP		 836 * SNB CPU
837 * IVB CPU
417e822d
KP		 838 * CPT PCH
839 *
840 * IBX PCH and CPU are the same for almost everything,
841 * except that the CPU DP PLL is configured in this
842 * register
843 *
844 * CPT PCH is quite different, having many bits moved
845 * to the TRANS_DP_CTL register instead. That
846 * configuration happens (oddly) in ironlake_pch_enable
847 */
9c9e7927 848
417e822d
KP		 849 /* Preserve the BIOS-computed detected bit. This is
850 * supposed to be read-only.
851 */
852 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
853 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
a4fc5ed6 854
417e822d
KP		 855 /* Handle DP bits in common between all three register formats */
856
857 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
a4fc5ed6 858
ea5b213a 859 switch (intel_dp->lane_count) {
a4fc5ed6 860 case 1:
ea5b213a 861 intel_dp->DP |= DP_PORT_WIDTH_1;
a4fc5ed6
KP		 862 break;
863 case 2:
ea5b213a 864 intel_dp->DP |= DP_PORT_WIDTH_2;
a4fc5ed6
KP		 865 break;
866 case 4:
ea5b213a 867 intel_dp->DP |= DP_PORT_WIDTH_4;
a4fc5ed6
KP		 868 break;
869 }
e0dac65e
WF		 870 if (intel_dp->has_audio) {
871 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
872 pipe_name(intel_crtc->pipe));
ea5b213a 873 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
e0dac65e
WF		 874 intel_write_eld(encoder, adjusted_mode);
875 }
ea5b213a
CW		 876 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
877 intel_dp->link_configuration[0] = intel_dp->link_bw;
878 intel_dp->link_configuration[1] = intel_dp->lane_count;
a2cab1b2 879 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
a4fc5ed6 880 /*
9962c925 881 * Check for DPCD version > 1.1 and enhanced framing support
a4fc5ed6 882 */
7183dc29
JB		 883 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
884 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
ea5b213a 885 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
a4fc5ed6
KP		 886 }
887
417e822d 888 /* Split out the IBX/CPU vs CPT settings */
32f9d658 889
1a2eb460
KP		 890 if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
891 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
892 intel_dp->DP |= DP_SYNC_HS_HIGH;
893 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
894 intel_dp->DP |= DP_SYNC_VS_HIGH;
895 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
896
897 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
898 intel_dp->DP |= DP_ENHANCED_FRAMING;
899
900 intel_dp->DP |= intel_crtc->pipe << 29;
901
902 /* don't miss out required setting for eDP */
903 intel_dp->DP |= DP_PLL_ENABLE;
904 if (adjusted_mode->clock < 200000)
905 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
906 else
907 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
908 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
417e822d
KP		 909 intel_dp->DP |= intel_dp->color_range;
910
911 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
912 intel_dp->DP |= DP_SYNC_HS_HIGH;
913 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
914 intel_dp->DP |= DP_SYNC_VS_HIGH;
915 intel_dp->DP |= DP_LINK_TRAIN_OFF;
916
917 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
918 intel_dp->DP |= DP_ENHANCED_FRAMING;
919
920 if (intel_crtc->pipe == 1)
921 intel_dp->DP |= DP_PIPEB_SELECT;
922
923 if (is_cpu_edp(intel_dp)) {
924 /* don't miss out required setting for eDP */
925 intel_dp->DP |= DP_PLL_ENABLE;
926 if (adjusted_mode->clock < 200000)
927 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
928 else
929 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
930 }
931 } else {
932 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 933 }
a4fc5ed6
KP		 934}
935
99ea7127
KP		 936#define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
937#define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
938
939#define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
940#define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
941
942#define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
943#define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
944
945static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
946 u32 mask,
947 u32 value)
bd943159 948{
99ea7127
KP		 949 struct drm_device *dev = intel_dp->base.base.dev;
950 struct drm_i915_private *dev_priv = dev->dev_private;
32ce697c 951
99ea7127
KP		 952 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
953 mask, value,
954 I915_READ(PCH_PP_STATUS),
955 I915_READ(PCH_PP_CONTROL));
32ce697c 956
99ea7127
KP		 957 if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
958 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
959 I915_READ(PCH_PP_STATUS),
960 I915_READ(PCH_PP_CONTROL));
32ce697c 961 }
99ea7127 962}
32ce697c 963
99ea7127
KP		 964static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
965{
966 DRM_DEBUG_KMS("Wait for panel power on\n");
967 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 968}
969
99ea7127
KP		 970static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
971{
972 DRM_DEBUG_KMS("Wait for panel power off time\n");
973 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
974}
975
976static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
977{
978 DRM_DEBUG_KMS("Wait for panel power cycle\n");
979 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
980}
981
982
832dd3c1
KP		 983/* Read the current pp_control value, unlocking the register if it
984 * is locked
985 */
986
987static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
988{
989 u32 control = I915_READ(PCH_PP_CONTROL);
990
991 control &= ~PANEL_UNLOCK_MASK;
992 control |= PANEL_UNLOCK_REGS;
993 return control;
bd943159
KP		 994}
995
5d613501
JB		 996static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
997{
998 struct drm_device *dev = intel_dp->base.base.dev;
999 struct drm_i915_private *dev_priv = dev->dev_private;
1000 u32 pp;
1001
97af61f5
KP		 1002 if (!is_edp(intel_dp))
1003 return;
f01eca2e 1004 DRM_DEBUG_KMS("Turn eDP VDD on\n");
5d613501 1005
bd943159
KP		 1006 WARN(intel_dp->want_panel_vdd,
1007 "eDP VDD already requested on\n");
1008
1009 intel_dp->want_panel_vdd = true;
99ea7127 1010
bd943159
KP		 1011 if (ironlake_edp_have_panel_vdd(intel_dp)) {
1012 DRM_DEBUG_KMS("eDP VDD already on\n");
1013 return;
1014 }
1015
99ea7127
KP		 1016 if (!ironlake_edp_have_panel_power(intel_dp))
1017 ironlake_wait_panel_power_cycle(intel_dp);
1018
832dd3c1 1019 pp = ironlake_get_pp_control(dev_priv);
5d613501
JB		 1020 pp |= EDP_FORCE_VDD;
1021 I915_WRITE(PCH_PP_CONTROL, pp);
1022 POSTING_READ(PCH_PP_CONTROL);
f01eca2e
KP		 1023 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1024 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
ebf33b18
KP		 1025
1026 /*
1027 * If the panel wasn't on, delay before accessing aux channel
1028 */
1029 if (!ironlake_edp_have_panel_power(intel_dp)) {
bd943159 1030 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1031 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1032 }
5d613501
JB		 1033}
1034
bd943159 1035static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501
JB		 1036{
1037 struct drm_device *dev = intel_dp->base.base.dev;
1038 struct drm_i915_private *dev_priv = dev->dev_private;
1039 u32 pp;
1040
bd943159 1041 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
832dd3c1 1042 pp = ironlake_get_pp_control(dev_priv);
bd943159
KP		 1043 pp &= ~EDP_FORCE_VDD;
1044 I915_WRITE(PCH_PP_CONTROL, pp);
1045 POSTING_READ(PCH_PP_CONTROL);
1046
1047 /* Make sure sequencer is idle before allowing subsequent activity */
1048 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1049 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
99ea7127
KP		 1050
1051 msleep(intel_dp->panel_power_down_delay);
bd943159
KP		 1052 }
1053}
5d613501 1054
bd943159
KP		 1055static void ironlake_panel_vdd_work(struct work_struct *__work)
1056{
1057 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1058 struct intel_dp, panel_vdd_work);
1059 struct drm_device *dev = intel_dp->base.base.dev;
1060
627f7675 1061 mutex_lock(&dev->mode_config.mutex);
bd943159 1062 ironlake_panel_vdd_off_sync(intel_dp);
627f7675 1063 mutex_unlock(&dev->mode_config.mutex);
bd943159
KP		 1064}
1065
1066static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1067{
97af61f5
KP		 1068 if (!is_edp(intel_dp))
1069 return;
5d613501 1070
bd943159
KP		 1071 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1072 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1073
bd943159
KP		 1074 intel_dp->want_panel_vdd = false;
1075
1076 if (sync) {
1077 ironlake_panel_vdd_off_sync(intel_dp);
1078 } else {
1079 /*
1080 * Queue the timer to fire a long
1081 * time from now (relative to the power down delay)
1082 * to keep the panel power up across a sequence of operations
1083 */
1084 schedule_delayed_work(&intel_dp->panel_vdd_work,
1085 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1086 }
5d613501
JB		 1087}
1088
86a3073e 1089static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1090{
01cb9ea6 1091 struct drm_device *dev = intel_dp->base.base.dev;
9934c132 1092 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1093 u32 pp;
9934c132 1094
97af61f5 1095 if (!is_edp(intel_dp))
bd943159 1096 return;
99ea7127
KP		 1097
1098 DRM_DEBUG_KMS("Turn eDP power on\n");
1099
1100 if (ironlake_edp_have_panel_power(intel_dp)) {
1101 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1102 return;
99ea7127 1103 }
9934c132 1104
99ea7127 1105 ironlake_wait_panel_power_cycle(intel_dp);
37c6c9b0 1106
99ea7127 1107 pp = ironlake_get_pp_control(dev_priv);
05ce1a49
KP		 1108 if (IS_GEN5(dev)) {
1109 /* ILK workaround: disable reset around power sequence */
1110 pp &= ~PANEL_POWER_RESET;
1111 I915_WRITE(PCH_PP_CONTROL, pp);
1112 POSTING_READ(PCH_PP_CONTROL);
1113 }
37c6c9b0 1114
1c0ae80a 1115 pp |= POWER_TARGET_ON;
99ea7127
KP		 1116 if (!IS_GEN5(dev))
1117 pp |= PANEL_POWER_RESET;
1118
9934c132 1119 I915_WRITE(PCH_PP_CONTROL, pp);
01cb9ea6 1120 POSTING_READ(PCH_PP_CONTROL);
9934c132 1121
99ea7127 1122 ironlake_wait_panel_on(intel_dp);
9934c132 1123
05ce1a49
KP		 1124 if (IS_GEN5(dev)) {
1125 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1126 I915_WRITE(PCH_PP_CONTROL, pp);
1127 POSTING_READ(PCH_PP_CONTROL);
1128 }
9934c132
JB		 1129}
1130
99ea7127 1131static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1132{
99ea7127 1133 struct drm_device *dev = intel_dp->base.base.dev;
9934c132 1134 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1135 u32 pp;
9934c132 1136
97af61f5
KP		 1137 if (!is_edp(intel_dp))
1138 return;
37c6c9b0 1139
99ea7127 1140 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1141
6cb49835 1142 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
37c6c9b0 1143
99ea7127 1144 pp = ironlake_get_pp_control(dev_priv);
35a38556
DV		 1145 /* We need to switch off panel power _and_ force vdd, for otherwise some
1146 * panels get very unhappy and cease to work. */
1147 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
99ea7127
KP		 1148 I915_WRITE(PCH_PP_CONTROL, pp);
1149 POSTING_READ(PCH_PP_CONTROL);
9934c132 1150
35a38556
DV		 1151 intel_dp->want_panel_vdd = false;
1152
99ea7127 1153 ironlake_wait_panel_off(intel_dp);
9934c132
JB		 1154}
1155
86a3073e 1156static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1157{
f01eca2e 1158 struct drm_device *dev = intel_dp->base.base.dev;
32f9d658
ZW		 1159 struct drm_i915_private *dev_priv = dev->dev_private;
1160 u32 pp;
1161
f01eca2e
KP		 1162 if (!is_edp(intel_dp))
1163 return;
1164
28c97730 1165 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1166 /*
1167 * If we enable the backlight right away following a panel power
1168 * on, we may see slight flicker as the panel syncs with the eDP
1169 * link. So delay a bit to make sure the image is solid before
1170 * allowing it to appear.
1171 */
f01eca2e 1172 msleep(intel_dp->backlight_on_delay);
832dd3c1 1173 pp = ironlake_get_pp_control(dev_priv);
32f9d658
ZW		 1174 pp |= EDP_BLC_ENABLE;
1175 I915_WRITE(PCH_PP_CONTROL, pp);
f01eca2e 1176 POSTING_READ(PCH_PP_CONTROL);
32f9d658
ZW		 1177}
1178
86a3073e 1179static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1180{
f01eca2e 1181 struct drm_device *dev = intel_dp->base.base.dev;
32f9d658
ZW		 1182 struct drm_i915_private *dev_priv = dev->dev_private;
1183 u32 pp;
1184
f01eca2e
KP		 1185 if (!is_edp(intel_dp))
1186 return;
1187
28c97730 1188 DRM_DEBUG_KMS("\n");
832dd3c1 1189 pp = ironlake_get_pp_control(dev_priv);
32f9d658
ZW		 1190 pp &= ~EDP_BLC_ENABLE;
1191 I915_WRITE(PCH_PP_CONTROL, pp);
f01eca2e
KP		 1192 POSTING_READ(PCH_PP_CONTROL);
1193 msleep(intel_dp->backlight_off_delay);
32f9d658 1194}
a4fc5ed6 1195
d240f20f
JB		 1196static void ironlake_edp_pll_on(struct drm_encoder *encoder)
1197{
1198 struct drm_device *dev = encoder->dev;
1199 struct drm_i915_private *dev_priv = dev->dev_private;
1200 u32 dpa_ctl;
1201
1202 DRM_DEBUG_KMS("\n");
1203 dpa_ctl = I915_READ(DP_A);
298b0b39 1204 dpa_ctl |= DP_PLL_ENABLE;
d240f20f 1205 I915_WRITE(DP_A, dpa_ctl);
298b0b39
JB		 1206 POSTING_READ(DP_A);
1207 udelay(200);
d240f20f
JB		 1208}
1209
1210static void ironlake_edp_pll_off(struct drm_encoder *encoder)
1211{
1212 struct drm_device *dev = encoder->dev;
1213 struct drm_i915_private *dev_priv = dev->dev_private;
1214 u32 dpa_ctl;
1215
1216 dpa_ctl = I915_READ(DP_A);
298b0b39 1217 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1218 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1219 POSTING_READ(DP_A);
d240f20f
JB		 1220 udelay(200);
1221}
1222
c7ad3810
JB		 1223/* If the sink supports it, try to set the power state appropriately */
1224static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1225{
1226 int ret, i;
1227
1228 /* Should have a valid DPCD by this point */
1229 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1230 return;
1231
1232 if (mode != DRM_MODE_DPMS_ON) {
1233 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1234 DP_SET_POWER_D3);
1235 if (ret != 1)
1236 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1237 } else {
1238 /*
1239 * When turning on, we need to retry for 1ms to give the sink
1240 * time to wake up.
1241 */
1242 for (i = 0; i < 3; i++) {
1243 ret = intel_dp_aux_native_write_1(intel_dp,
1244 DP_SET_POWER,
1245 DP_SET_POWER_D0);
1246 if (ret == 1)
1247 break;
1248 msleep(1);
1249 }
1250 }
1251}
1252
19d8fe15
DV		 1253static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1254 enum pipe *pipe)
1255{
1256 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1257 struct drm_device *dev = encoder->base.dev;
1258 struct drm_i915_private *dev_priv = dev->dev_private;
1259 u32 tmp = I915_READ(intel_dp->output_reg);
1260
1261 if (!(tmp & DP_PORT_EN))
1262 return false;
1263
1264 if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
1265 *pipe = PORT_TO_PIPE_CPT(tmp);
1266 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
1267 *pipe = PORT_TO_PIPE(tmp);
1268 } else {
1269 u32 trans_sel;
1270 u32 trans_dp;
1271 int i;
1272
1273 switch (intel_dp->output_reg) {
1274 case PCH_DP_B:
1275 trans_sel = TRANS_DP_PORT_SEL_B;
1276 break;
1277 case PCH_DP_C:
1278 trans_sel = TRANS_DP_PORT_SEL_C;
1279 break;
1280 case PCH_DP_D:
1281 trans_sel = TRANS_DP_PORT_SEL_D;
1282 break;
1283 default:
1284 return true;
1285 }
1286
1287 for_each_pipe(i) {
1288 trans_dp = I915_READ(TRANS_DP_CTL(i));
1289 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1290 *pipe = i;
1291 return true;
1292 }
1293 }
1294 }
1295
1296 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", intel_dp->output_reg);
1297
1298 return true;
1299}
1300
e8cb4558 1301static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1302{
e8cb4558 1303 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
6cb49835
DV		 1304
1305 /* Make sure the panel is off before trying to change the mode. But also
1306 * ensure that we have vdd while we switch off the panel. */
1307 ironlake_edp_panel_vdd_on(intel_dp);
21264c63 1308 ironlake_edp_backlight_off(intel_dp);
c7ad3810 1309 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
35a38556 1310 ironlake_edp_panel_off(intel_dp);
21264c63 1311 intel_dp_link_down(intel_dp);
e8cb4558
DV		 1312
1313 intel_dp->dpms_mode = DRM_MODE_DPMS_OFF;
d240f20f
JB		 1314}
1315
e8cb4558 1316static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 1317{
e8cb4558
DV		 1318 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1319 struct drm_device *dev = encoder->base.dev;
1320 struct drm_i915_private *dev_priv = dev->dev_private;
1321 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 1322
97af61f5 1323 ironlake_edp_panel_vdd_on(intel_dp);
f01eca2e 1324 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
e8cb4558
DV		 1325 if (!(dp_reg & DP_PORT_EN)) {
1326 intel_dp_start_link_train(intel_dp);
1327 ironlake_edp_panel_on(intel_dp);
1328 ironlake_edp_panel_vdd_off(intel_dp, true);
1329 intel_dp_complete_link_train(intel_dp);
1330 } else
1331 ironlake_edp_panel_vdd_off(intel_dp, false);
f01eca2e 1332 ironlake_edp_backlight_on(intel_dp);
d2b996ac
KP		 1333
1334 intel_dp->dpms_mode = DRM_MODE_DPMS_ON;
d240f20f
JB		 1335}
1336
a4fc5ed6 1337static void
e8cb4558 1338intel_dp_dpms(struct drm_connector *connector, int mode)
a4fc5ed6 1339{
e8cb4558
DV		 1340 struct intel_dp *intel_dp = intel_attached_dp(connector);
1341
1342 /* DP supports only 2 dpms states. */
1343 if (mode != DRM_MODE_DPMS_ON)
1344 mode = DRM_MODE_DPMS_OFF;
1345
1346 if (mode == connector->dpms)
1347 return;
1348
1349 connector->dpms = mode;
1350
1351 /* Only need to change hw state when actually enabled */
1352 if (!intel_dp->base.base.crtc) {
1353 intel_dp->base.connectors_active = false;
1354 return;
1355 }
a4fc5ed6
KP		 1356
1357 if (mode != DRM_MODE_DPMS_ON) {
e8cb4558
DV		 1358 intel_encoder_dpms(&intel_dp->base, mode);
1359 WARN_ON(intel_dp->dpms_mode != DRM_MODE_DPMS_OFF);
21264c63
KP		 1360
1361 if (is_cpu_edp(intel_dp))
e8cb4558 1362 ironlake_edp_pll_off(&intel_dp->base.base);
a4fc5ed6 1363 } else {
21264c63 1364 if (is_cpu_edp(intel_dp))
e8cb4558 1365 ironlake_edp_pll_on(&intel_dp->base.base);
21264c63 1366
e8cb4558
DV		 1367 intel_encoder_dpms(&intel_dp->base, mode);
1368 WARN_ON(intel_dp->dpms_mode != DRM_MODE_DPMS_ON);
a4fc5ed6 1369 }
0a91ca29
DV		 1370
1371 intel_connector_check_state(to_intel_connector(connector));
a4fc5ed6
KP		 1372}
1373
1374/*
df0c237d
JB		 1375 * Native read with retry for link status and receiver capability reads for
1376 * cases where the sink may still be asleep.
a4fc5ed6
KP		 1377 */
1378static bool
df0c237d
JB		 1379intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1380 uint8_t *recv, int recv_bytes)
a4fc5ed6 1381{
61da5fab
JB		 1382 int ret, i;
1383
df0c237d
JB		 1384 /*
1385 * Sinks are *supposed* to come up within 1ms from an off state,
1386 * but we're also supposed to retry 3 times per the spec.
1387 */
61da5fab 1388 for (i = 0; i < 3; i++) {
df0c237d
JB		 1389 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1390 recv_bytes);
1391 if (ret == recv_bytes)
61da5fab
JB		 1392 return true;
1393 msleep(1);
1394 }
a4fc5ed6 1395
61da5fab 1396 return false;
a4fc5ed6
KP		 1397}
1398
1399/*
1400 * Fetch AUX CH registers 0x202 - 0x207 which contain
1401 * link status information
1402 */
1403static bool
93f62dad 1404intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 1405{
df0c237d
JB		 1406 return intel_dp_aux_native_read_retry(intel_dp,
1407 DP_LANE0_1_STATUS,
93f62dad 1408 link_status,
df0c237d 1409 DP_LINK_STATUS_SIZE);
a4fc5ed6
KP		 1410}
1411
1412static uint8_t
1413intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1414 int r)
1415{
1416 return link_status[r - DP_LANE0_1_STATUS];
1417}
1418
a4fc5ed6 1419static uint8_t
93f62dad 1420intel_get_adjust_request_voltage(uint8_t adjust_request[2],
a4fc5ed6
KP		 1421 int lane)
1422{
a4fc5ed6
KP		 1423 int s = ((lane & 1) ?
1424 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1425 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
93f62dad 1426 uint8_t l = adjust_request[lane>>1];
a4fc5ed6
KP		 1427
1428 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1429}
1430
1431static uint8_t
93f62dad 1432intel_get_adjust_request_pre_emphasis(uint8_t adjust_request[2],
a4fc5ed6
KP		 1433 int lane)
1434{
a4fc5ed6
KP		 1435 int s = ((lane & 1) ?
1436 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1437 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
93f62dad 1438 uint8_t l = adjust_request[lane>>1];
a4fc5ed6
KP		 1439
1440 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1441}
1442
1443
1444#if 0
1445static char *voltage_names[] = {
1446 "0.4V", "0.6V", "0.8V", "1.2V"
1447};
1448static char *pre_emph_names[] = {
1449 "0dB", "3.5dB", "6dB", "9.5dB"
1450};
1451static char *link_train_names[] = {
1452 "pattern 1", "pattern 2", "idle", "off"
1453};
1454#endif
1455
1456/*
1457 * These are source-specific values; current Intel hardware supports
1458 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1459 */
a4fc5ed6
KP		 1460
1461static uint8_t
1a2eb460 1462intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 1463{
1a2eb460
KP		 1464 struct drm_device *dev = intel_dp->base.base.dev;
1465
1466 if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1467 return DP_TRAIN_VOLTAGE_SWING_800;
1468 else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1469 return DP_TRAIN_VOLTAGE_SWING_1200;
1470 else
1471 return DP_TRAIN_VOLTAGE_SWING_800;
1472}
1473
1474static uint8_t
1475intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1476{
1477 struct drm_device *dev = intel_dp->base.base.dev;
1478
1479 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1480 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1481 case DP_TRAIN_VOLTAGE_SWING_400:
1482 return DP_TRAIN_PRE_EMPHASIS_6;
1483 case DP_TRAIN_VOLTAGE_SWING_600:
1484 case DP_TRAIN_VOLTAGE_SWING_800:
1485 return DP_TRAIN_PRE_EMPHASIS_3_5;
1486 default:
1487 return DP_TRAIN_PRE_EMPHASIS_0;
1488 }
1489 } else {
1490 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1491 case DP_TRAIN_VOLTAGE_SWING_400:
1492 return DP_TRAIN_PRE_EMPHASIS_6;
1493 case DP_TRAIN_VOLTAGE_SWING_600:
1494 return DP_TRAIN_PRE_EMPHASIS_6;
1495 case DP_TRAIN_VOLTAGE_SWING_800:
1496 return DP_TRAIN_PRE_EMPHASIS_3_5;
1497 case DP_TRAIN_VOLTAGE_SWING_1200:
1498 default:
1499 return DP_TRAIN_PRE_EMPHASIS_0;
1500 }
a4fc5ed6
KP		 1501 }
1502}
1503
1504static void
93f62dad 1505intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 1506{
1507 uint8_t v = 0;
1508 uint8_t p = 0;
1509 int lane;
93f62dad 1510 uint8_t *adjust_request = link_status + (DP_ADJUST_REQUEST_LANE0_1 - DP_LANE0_1_STATUS);
1a2eb460
KP		 1511 uint8_t voltage_max;
1512 uint8_t preemph_max;
a4fc5ed6 1513
33a34e4e 1514 for (lane = 0; lane < intel_dp->lane_count; lane++) {
93f62dad
KP		 1515 uint8_t this_v = intel_get_adjust_request_voltage(adjust_request, lane);
1516 uint8_t this_p = intel_get_adjust_request_pre_emphasis(adjust_request, lane);
a4fc5ed6
KP		 1517
1518 if (this_v > v)
1519 v = this_v;
1520 if (this_p > p)
1521 p = this_p;
1522 }
1523
1a2eb460 1524 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 1525 if (v >= voltage_max)
1526 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 1527
1a2eb460
KP		 1528 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1529 if (p >= preemph_max)
1530 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 1531
1532 for (lane = 0; lane < 4; lane++)
33a34e4e 1533 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 1534}
1535
1536static uint32_t
93f62dad 1537intel_dp_signal_levels(uint8_t train_set)
a4fc5ed6 1538{
3cf2efb1 1539 uint32_t signal_levels = 0;
a4fc5ed6 1540
3cf2efb1 1541 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 1542 case DP_TRAIN_VOLTAGE_SWING_400:
1543 default:
1544 signal_levels |= DP_VOLTAGE_0_4;
1545 break;
1546 case DP_TRAIN_VOLTAGE_SWING_600:
1547 signal_levels |= DP_VOLTAGE_0_6;
1548 break;
1549 case DP_TRAIN_VOLTAGE_SWING_800:
1550 signal_levels |= DP_VOLTAGE_0_8;
1551 break;
1552 case DP_TRAIN_VOLTAGE_SWING_1200:
1553 signal_levels |= DP_VOLTAGE_1_2;
1554 break;
1555 }
3cf2efb1 1556 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 1557 case DP_TRAIN_PRE_EMPHASIS_0:
1558 default:
1559 signal_levels |= DP_PRE_EMPHASIS_0;
1560 break;
1561 case DP_TRAIN_PRE_EMPHASIS_3_5:
1562 signal_levels |= DP_PRE_EMPHASIS_3_5;
1563 break;
1564 case DP_TRAIN_PRE_EMPHASIS_6:
1565 signal_levels |= DP_PRE_EMPHASIS_6;
1566 break;
1567 case DP_TRAIN_PRE_EMPHASIS_9_5:
1568 signal_levels |= DP_PRE_EMPHASIS_9_5;
1569 break;
1570 }
1571 return signal_levels;
1572}
1573
e3421a18
ZW		 1574/* Gen6's DP voltage swing and pre-emphasis control */
1575static uint32_t
1576intel_gen6_edp_signal_levels(uint8_t train_set)
1577{
3c5a62b5
YL		 1578 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1579 DP_TRAIN_PRE_EMPHASIS_MASK);
1580 switch (signal_levels) {
e3421a18 1581 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1582 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1583 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1584 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1585 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 1586 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 1587 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1588 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 1589 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 1590 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1591 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 1592 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1593 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1594 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 1595 default:
3c5a62b5
YL		 1596 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1597 "0x%x\n", signal_levels);
1598 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 1599 }
1600}
1601
1a2eb460
KP		 1602/* Gen7's DP voltage swing and pre-emphasis control */
1603static uint32_t
1604intel_gen7_edp_signal_levels(uint8_t train_set)
1605{
1606 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1607 DP_TRAIN_PRE_EMPHASIS_MASK);
1608 switch (signal_levels) {
1609 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1610 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1611 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1612 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1613 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1614 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1615
1616 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1617 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1618 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1619 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1620
1621 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1622 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1623 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1624 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1625
1626 default:
1627 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1628 "0x%x\n", signal_levels);
1629 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1630 }
1631}
1632
a4fc5ed6
KP		 1633static uint8_t
1634intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1635 int lane)
1636{
a4fc5ed6 1637 int s = (lane & 1) * 4;
93f62dad 1638 uint8_t l = link_status[lane>>1];
a4fc5ed6
KP		 1639
1640 return (l >> s) & 0xf;
1641}
1642
1643/* Check for clock recovery is done on all channels */
1644static bool
1645intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1646{
1647 int lane;
1648 uint8_t lane_status;
1649
1650 for (lane = 0; lane < lane_count; lane++) {
1651 lane_status = intel_get_lane_status(link_status, lane);
1652 if ((lane_status & DP_LANE_CR_DONE) == 0)
1653 return false;
1654 }
1655 return true;
1656}
1657
1658/* Check to see if channel eq is done on all channels */
1659#define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1660 DP_LANE_CHANNEL_EQ_DONE|\
1661 DP_LANE_SYMBOL_LOCKED)
1662static bool
93f62dad 1663intel_channel_eq_ok(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 1664{
1665 uint8_t lane_align;
1666 uint8_t lane_status;
1667 int lane;
1668
93f62dad 1669 lane_align = intel_dp_link_status(link_status,
a4fc5ed6
KP		 1670 DP_LANE_ALIGN_STATUS_UPDATED);
1671 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1672 return false;
33a34e4e 1673 for (lane = 0; lane < intel_dp->lane_count; lane++) {
93f62dad 1674 lane_status = intel_get_lane_status(link_status, lane);
a4fc5ed6
KP		 1675 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1676 return false;
1677 }
1678 return true;
1679}
1680
1681static bool
ea5b213a 1682intel_dp_set_link_train(struct intel_dp *intel_dp,
a4fc5ed6 1683 uint32_t dp_reg_value,
58e10eb9 1684 uint8_t dp_train_pat)
a4fc5ed6 1685{
4ef69c7a 1686 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6 1687 struct drm_i915_private *dev_priv = dev->dev_private;
a4fc5ed6
KP		 1688 int ret;
1689
47ea7542
PZ		 1690 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
1691 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1692
1693 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1694 case DP_TRAINING_PATTERN_DISABLE:
1695 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1696 break;
1697 case DP_TRAINING_PATTERN_1:
1698 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1699 break;
1700 case DP_TRAINING_PATTERN_2:
1701 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1702 break;
1703 case DP_TRAINING_PATTERN_3:
1704 DRM_ERROR("DP training pattern 3 not supported\n");
1705 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1706 break;
1707 }
1708
1709 } else {
1710 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1711
1712 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1713 case DP_TRAINING_PATTERN_DISABLE:
1714 dp_reg_value |= DP_LINK_TRAIN_OFF;
1715 break;
1716 case DP_TRAINING_PATTERN_1:
1717 dp_reg_value |= DP_LINK_TRAIN_PAT_1;
1718 break;
1719 case DP_TRAINING_PATTERN_2:
1720 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1721 break;
1722 case DP_TRAINING_PATTERN_3:
1723 DRM_ERROR("DP training pattern 3 not supported\n");
1724 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1725 break;
1726 }
1727 }
1728
ea5b213a
CW		 1729 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1730 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 1731
ea5b213a 1732 intel_dp_aux_native_write_1(intel_dp,
a4fc5ed6
KP		 1733 DP_TRAINING_PATTERN_SET,
1734 dp_train_pat);
1735
47ea7542
PZ		 1736 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
1737 DP_TRAINING_PATTERN_DISABLE) {
1738 ret = intel_dp_aux_native_write(intel_dp,
1739 DP_TRAINING_LANE0_SET,
1740 intel_dp->train_set,
1741 intel_dp->lane_count);
1742 if (ret != intel_dp->lane_count)
1743 return false;
1744 }
a4fc5ed6
KP		 1745
1746 return true;
1747}
1748
33a34e4e 1749/* Enable corresponding port and start training pattern 1 */
a4fc5ed6 1750static void
33a34e4e 1751intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 1752{
4ef69c7a 1753 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6 1754 struct drm_i915_private *dev_priv = dev->dev_private;
58e10eb9 1755 struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
a4fc5ed6
KP		 1756 int i;
1757 uint8_t voltage;
1758 bool clock_recovery = false;
cdb0e95b 1759 int voltage_tries, loop_tries;
ea5b213a 1760 uint32_t DP = intel_dp->DP;
a4fc5ed6 1761
e8519464
AJ		 1762 /*
1763 * On CPT we have to enable the port in training pattern 1, which
1764 * will happen below in intel_dp_set_link_train. Otherwise, enable
1765 * the port and wait for it to become active.
1766 */
1767 if (!HAS_PCH_CPT(dev)) {
1768 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
1769 POSTING_READ(intel_dp->output_reg);
1770 intel_wait_for_vblank(dev, intel_crtc->pipe);
1771 }
a4fc5ed6 1772
3cf2efb1
CW		 1773 /* Write the link configuration data */
1774 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1775 intel_dp->link_configuration,
1776 DP_LINK_CONFIGURATION_SIZE);
a4fc5ed6
KP		 1777
1778 DP |= DP_PORT_EN;
1a2eb460 1779
33a34e4e 1780 memset(intel_dp->train_set, 0, 4);
a4fc5ed6 1781 voltage = 0xff;
cdb0e95b
KP		 1782 voltage_tries = 0;
1783 loop_tries = 0;
a4fc5ed6
KP		 1784 clock_recovery = false;
1785 for (;;) {
33a34e4e 1786 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
93f62dad 1787 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 1788 uint32_t signal_levels;
417e822d 1789
1a2eb460
KP		 1790
1791 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1792 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1793 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1794 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
33a34e4e 1795 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1796 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1797 } else {
93f62dad
KP		 1798 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1799 DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n", signal_levels);
e3421a18
ZW		 1800 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1801 }
a4fc5ed6 1802
47ea7542 1803 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 1804 DP_TRAINING_PATTERN_1 |
1805 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6 1806 break;
a4fc5ed6
KP		 1807 /* Set training pattern 1 */
1808
3cf2efb1 1809 udelay(100);
93f62dad
KP		 1810 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1811 DRM_ERROR("failed to get link status\n");
a4fc5ed6 1812 break;
93f62dad 1813 }
a4fc5ed6 1814
93f62dad
KP		 1815 if (intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1816 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 1817 clock_recovery = true;
1818 break;
1819 }
1820
1821 /* Check to see if we've tried the max voltage */
1822 for (i = 0; i < intel_dp->lane_count; i++)
1823 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 1824 break;
0d710688 1825 if (i == intel_dp->lane_count && voltage_tries == 5) {
cdb0e95b
KP		 1826 ++loop_tries;
1827 if (loop_tries == 5) {
1828 DRM_DEBUG_KMS("too many full retries, give up\n");
1829 break;
1830 }
1831 memset(intel_dp->train_set, 0, 4);
1832 voltage_tries = 0;
1833 continue;
1834 }
a4fc5ed6 1835
3cf2efb1
CW		 1836 /* Check to see if we've tried the same voltage 5 times */
1837 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
cdb0e95b
KP		 1838 ++voltage_tries;
1839 if (voltage_tries == 5) {
1840 DRM_DEBUG_KMS("too many voltage retries, give up\n");
a4fc5ed6 1841 break;
cdb0e95b 1842 }
3cf2efb1 1843 } else
cdb0e95b 1844 voltage_tries = 0;
3cf2efb1 1845 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 1846
3cf2efb1 1847 /* Compute new intel_dp->train_set as requested by target */
93f62dad 1848 intel_get_adjust_train(intel_dp, link_status);
a4fc5ed6
KP		 1849 }
1850
33a34e4e
JB		 1851 intel_dp->DP = DP;
1852}
1853
1854static void
1855intel_dp_complete_link_train(struct intel_dp *intel_dp)
1856{
4ef69c7a 1857 struct drm_device *dev = intel_dp->base.base.dev;
33a34e4e 1858 bool channel_eq = false;
37f80975 1859 int tries, cr_tries;
33a34e4e
JB		 1860 uint32_t DP = intel_dp->DP;
1861
a4fc5ed6
KP		 1862 /* channel equalization */
1863 tries = 0;
37f80975 1864 cr_tries = 0;
a4fc5ed6
KP		 1865 channel_eq = false;
1866 for (;;) {
33a34e4e 1867 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
e3421a18 1868 uint32_t signal_levels;
93f62dad 1869 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 1870
37f80975
JB		 1871 if (cr_tries > 5) {
1872 DRM_ERROR("failed to train DP, aborting\n");
1873 intel_dp_link_down(intel_dp);
1874 break;
1875 }
1876
1a2eb460
KP		 1877 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1878 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1879 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1880 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
33a34e4e 1881 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1882 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1883 } else {
93f62dad 1884 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1885 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1886 }
1887
a4fc5ed6 1888 /* channel eq pattern */
47ea7542 1889 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 1890 DP_TRAINING_PATTERN_2 |
1891 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6
KP		 1892 break;
1893
3cf2efb1 1894 udelay(400);
93f62dad 1895 if (!intel_dp_get_link_status(intel_dp, link_status))
a4fc5ed6 1896 break;
a4fc5ed6 1897
37f80975 1898 /* Make sure clock is still ok */
93f62dad 1899 if (!intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975
JB		 1900 intel_dp_start_link_train(intel_dp);
1901 cr_tries++;
1902 continue;
1903 }
1904
93f62dad 1905 if (intel_channel_eq_ok(intel_dp, link_status)) {
3cf2efb1
CW		 1906 channel_eq = true;
1907 break;
1908 }
a4fc5ed6 1909
37f80975
JB		 1910 /* Try 5 times, then try clock recovery if that fails */
1911 if (tries > 5) {
1912 intel_dp_link_down(intel_dp);
1913 intel_dp_start_link_train(intel_dp);
1914 tries = 0;
1915 cr_tries++;
1916 continue;
1917 }
a4fc5ed6 1918
3cf2efb1 1919 /* Compute new intel_dp->train_set as requested by target */
93f62dad 1920 intel_get_adjust_train(intel_dp, link_status);
3cf2efb1 1921 ++tries;
869184a6 1922 }
3cf2efb1 1923
47ea7542 1924 intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 1925}
1926
1927static void
ea5b213a 1928intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 1929{
4ef69c7a 1930 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6 1931 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 1932 uint32_t DP = intel_dp->DP;
a4fc5ed6 1933
1b39d6f3
CW		 1934 if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)
1935 return;
1936
28c97730 1937 DRM_DEBUG_KMS("\n");
32f9d658 1938
cfcb0fc9 1939 if (is_edp(intel_dp)) {
32f9d658 1940 DP &= ~DP_PLL_ENABLE;
ea5b213a
CW		 1941 I915_WRITE(intel_dp->output_reg, DP);
1942 POSTING_READ(intel_dp->output_reg);
32f9d658
ZW		 1943 udelay(100);
1944 }
1945
1a2eb460 1946 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
e3421a18 1947 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 1948 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 1949 } else {
1950 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 1951 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 1952 }
fe255d00 1953 POSTING_READ(intel_dp->output_reg);
5eb08b69 1954
fe255d00 1955 msleep(17);
5eb08b69 1956
417e822d 1957 if (is_edp(intel_dp)) {
1a2eb460 1958 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
417e822d
KP		 1959 DP |= DP_LINK_TRAIN_OFF_CPT;
1960 else
1961 DP |= DP_LINK_TRAIN_OFF;
1962 }
5bddd17f 1963
493a7081 1964 if (HAS_PCH_IBX(dev) &&
1b39d6f3 1965 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
31acbcc4
CW		 1966 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1967
5bddd17f
EA		 1968 /* Hardware workaround: leaving our transcoder select
1969 * set to transcoder B while it's off will prevent the
1970 * corresponding HDMI output on transcoder A.
1971 *
1972 * Combine this with another hardware workaround:
1973 * transcoder select bit can only be cleared while the
1974 * port is enabled.
1975 */
1976 DP &= ~DP_PIPEB_SELECT;
1977 I915_WRITE(intel_dp->output_reg, DP);
1978
1979 /* Changes to enable or select take place the vblank
1980 * after being written.
1981 */
31acbcc4
CW		 1982 if (crtc == NULL) {
1983 /* We can arrive here never having been attached
1984 * to a CRTC, for instance, due to inheriting
1985 * random state from the BIOS.
1986 *
1987 * If the pipe is not running, play safe and
1988 * wait for the clocks to stabilise before
1989 * continuing.
1990 */
1991 POSTING_READ(intel_dp->output_reg);
1992 msleep(50);
1993 } else
1994 intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
5bddd17f
EA		 1995 }
1996
832afda6 1997 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 1998 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1999 POSTING_READ(intel_dp->output_reg);
f01eca2e 2000 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 2001}
2002
26d61aad
KP		 2003static bool
2004intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 2005{
92fd8fd1 2006 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
0206e353 2007 sizeof(intel_dp->dpcd)) &&
92fd8fd1 2008 (intel_dp->dpcd[DP_DPCD_REV] != 0)) {
26d61aad 2009 return true;
92fd8fd1
KP		 2010 }
2011
26d61aad 2012 return false;
92fd8fd1
KP		 2013}
2014
0d198328
AJ		 2015static void
2016intel_dp_probe_oui(struct intel_dp *intel_dp)
2017{
2018 u8 buf[3];
2019
2020 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2021 return;
2022
351cfc34
DV		 2023 ironlake_edp_panel_vdd_on(intel_dp);
2024
0d198328
AJ		 2025 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2026 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2027 buf[0], buf[1], buf[2]);
2028
2029 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2030 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2031 buf[0], buf[1], buf[2]);
351cfc34
DV		 2032
2033 ironlake_edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 2034}
2035
a60f0e38
JB		 2036static bool
2037intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2038{
2039 int ret;
2040
2041 ret = intel_dp_aux_native_read_retry(intel_dp,
2042 DP_DEVICE_SERVICE_IRQ_VECTOR,
2043 sink_irq_vector, 1);
2044 if (!ret)
2045 return false;
2046
2047 return true;
2048}
2049
2050static void
2051intel_dp_handle_test_request(struct intel_dp *intel_dp)
2052{
2053 /* NAK by default */
2054 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_ACK);
2055}
2056
a4fc5ed6
KP		 2057/*
2058 * According to DP spec
2059 * 5.1.2:
2060 * 1. Read DPCD
2061 * 2. Configure link according to Receiver Capabilities
2062 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2063 * 4. Check link status on receipt of hot-plug interrupt
2064 */
2065
2066static void
ea5b213a 2067intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 2068{
a60f0e38 2069 u8 sink_irq_vector;
93f62dad 2070 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 2071
d2b996ac
KP		 2072 if (intel_dp->dpms_mode != DRM_MODE_DPMS_ON)
2073 return;
59cd09e1 2074
4ef69c7a 2075 if (!intel_dp->base.base.crtc)
a4fc5ed6
KP		 2076 return;
2077
92fd8fd1 2078 /* Try to read receiver status if the link appears to be up */
93f62dad 2079 if (!intel_dp_get_link_status(intel_dp, link_status)) {
ea5b213a 2080 intel_dp_link_down(intel_dp);
a4fc5ed6
KP		 2081 return;
2082 }
2083
92fd8fd1 2084 /* Now read the DPCD to see if it's actually running */
26d61aad 2085 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 2086 intel_dp_link_down(intel_dp);
2087 return;
2088 }
2089
a60f0e38
JB		 2090 /* Try to read the source of the interrupt */
2091 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2092 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2093 /* Clear interrupt source */
2094 intel_dp_aux_native_write_1(intel_dp,
2095 DP_DEVICE_SERVICE_IRQ_VECTOR,
2096 sink_irq_vector);
2097
2098 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2099 intel_dp_handle_test_request(intel_dp);
2100 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2101 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2102 }
2103
93f62dad 2104 if (!intel_channel_eq_ok(intel_dp, link_status)) {
92fd8fd1
KP		 2105 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2106 drm_get_encoder_name(&intel_dp->base.base));
33a34e4e
JB		 2107 intel_dp_start_link_train(intel_dp);
2108 intel_dp_complete_link_train(intel_dp);
2109 }
a4fc5ed6 2110}
a4fc5ed6 2111
71ba9000 2112static enum drm_connector_status
26d61aad 2113intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 2114{
26d61aad
KP		 2115 if (intel_dp_get_dpcd(intel_dp))
2116 return connector_status_connected;
2117 return connector_status_disconnected;
71ba9000
AJ		 2118}
2119
5eb08b69 2120static enum drm_connector_status
a9756bb5 2121ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 2122{
5eb08b69
ZW		 2123 enum drm_connector_status status;
2124
fe16d949
CW		 2125 /* Can't disconnect eDP, but you can close the lid... */
2126 if (is_edp(intel_dp)) {
2127 status = intel_panel_detect(intel_dp->base.base.dev);
2128 if (status == connector_status_unknown)
2129 status = connector_status_connected;
2130 return status;
2131 }
01cb9ea6 2132
26d61aad 2133 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 2134}
2135
a4fc5ed6 2136static enum drm_connector_status
a9756bb5 2137g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 2138{
4ef69c7a 2139 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6 2140 struct drm_i915_private *dev_priv = dev->dev_private;
10f76a38 2141 uint32_t bit;
5eb08b69 2142
ea5b213a 2143 switch (intel_dp->output_reg) {
a4fc5ed6 2144 case DP_B:
10f76a38 2145 bit = DPB_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2146 break;
2147 case DP_C:
10f76a38 2148 bit = DPC_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2149 break;
2150 case DP_D:
10f76a38 2151 bit = DPD_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2152 break;
2153 default:
2154 return connector_status_unknown;
2155 }
2156
10f76a38 2157 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 2158 return connector_status_disconnected;
2159
26d61aad 2160 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 2161}
2162
8c241fef
KP		 2163static struct edid *
2164intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2165{
2166 struct intel_dp *intel_dp = intel_attached_dp(connector);
2167 struct edid *edid;
d6f24d0f
JB		 2168 int size;
2169
2170 if (is_edp(intel_dp)) {
2171 if (!intel_dp->edid)
2172 return NULL;
2173
2174 size = (intel_dp->edid->extensions + 1) * EDID_LENGTH;
2175 edid = kmalloc(size, GFP_KERNEL);
2176 if (!edid)
2177 return NULL;
2178
2179 memcpy(edid, intel_dp->edid, size);
2180 return edid;
2181 }
8c241fef 2182
8c241fef 2183 edid = drm_get_edid(connector, adapter);
8c241fef
KP		 2184 return edid;
2185}
2186
2187static int
2188intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2189{
2190 struct intel_dp *intel_dp = intel_attached_dp(connector);
2191 int ret;
2192
d6f24d0f
JB		 2193 if (is_edp(intel_dp)) {
2194 drm_mode_connector_update_edid_property(connector,
2195 intel_dp->edid);
2196 ret = drm_add_edid_modes(connector, intel_dp->edid);
2197 drm_edid_to_eld(connector,
2198 intel_dp->edid);
2199 connector->display_info.raw_edid = NULL;
2200 return intel_dp->edid_mode_count;
2201 }
2202
8c241fef 2203 ret = intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 2204 return ret;
2205}
2206
2207
a9756bb5
ZW		 2208/**
2209 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
2210 *
2211 * \return true if DP port is connected.
2212 * \return false if DP port is disconnected.
2213 */
2214static enum drm_connector_status
2215intel_dp_detect(struct drm_connector *connector, bool force)
2216{
2217 struct intel_dp *intel_dp = intel_attached_dp(connector);
2218 struct drm_device *dev = intel_dp->base.base.dev;
2219 enum drm_connector_status status;
2220 struct edid *edid = NULL;
2221
2222 intel_dp->has_audio = false;
2223
2224 if (HAS_PCH_SPLIT(dev))
2225 status = ironlake_dp_detect(intel_dp);
2226 else
2227 status = g4x_dp_detect(intel_dp);
1b9be9d0 2228
ac66ae83
AJ		 2229 DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
2230 intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
2231 intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
2232 intel_dp->dpcd[6], intel_dp->dpcd[7]);
1b9be9d0 2233
a9756bb5
ZW		 2234 if (status != connector_status_connected)
2235 return status;
2236
0d198328
AJ		 2237 intel_dp_probe_oui(intel_dp);
2238
c3e5f67b
DV		 2239 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2240 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 2241 } else {
8c241fef 2242 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
f684960e
CW		 2243 if (edid) {
2244 intel_dp->has_audio = drm_detect_monitor_audio(edid);
2245 connector->display_info.raw_edid = NULL;
2246 kfree(edid);
2247 }
a9756bb5
ZW		 2248 }
2249
2250 return connector_status_connected;
a4fc5ed6
KP		 2251}
2252
2253static int intel_dp_get_modes(struct drm_connector *connector)
2254{
df0e9248 2255 struct intel_dp *intel_dp = intel_attached_dp(connector);
4ef69c7a 2256 struct drm_device *dev = intel_dp->base.base.dev;
32f9d658
ZW		 2257 struct drm_i915_private *dev_priv = dev->dev_private;
2258 int ret;
a4fc5ed6
KP		 2259
2260 /* We should parse the EDID data and find out if it has an audio sink
2261 */
2262
8c241fef 2263 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
b9efc480 2264 if (ret) {
d15456de 2265 if (is_edp(intel_dp) && !intel_dp->panel_fixed_mode) {
b9efc480
ZY		 2266 struct drm_display_mode *newmode;
2267 list_for_each_entry(newmode, &connector->probed_modes,
2268 head) {
d15456de
KP		 2269 if ((newmode->type & DRM_MODE_TYPE_PREFERRED)) {
2270 intel_dp->panel_fixed_mode =
b9efc480
ZY		 2271 drm_mode_duplicate(dev, newmode);
2272 break;
2273 }
2274 }
2275 }
32f9d658 2276 return ret;
b9efc480 2277 }
32f9d658
ZW		 2278
2279 /* if eDP has no EDID, try to use fixed panel mode from VBT */
4d926461 2280 if (is_edp(intel_dp)) {
47f0eb22 2281 /* initialize panel mode from VBT if available for eDP */
d15456de
KP		 2282 if (intel_dp->panel_fixed_mode == NULL && dev_priv->lfp_lvds_vbt_mode != NULL) {
2283 intel_dp->panel_fixed_mode =
47f0eb22 2284 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
d15456de
KP		 2285 if (intel_dp->panel_fixed_mode) {
2286 intel_dp->panel_fixed_mode->type |=
47f0eb22
KP		 2287 DRM_MODE_TYPE_PREFERRED;
2288 }
2289 }
d15456de 2290 if (intel_dp->panel_fixed_mode) {
32f9d658 2291 struct drm_display_mode *mode;
d15456de 2292 mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode);
32f9d658
ZW		 2293 drm_mode_probed_add(connector, mode);
2294 return 1;
2295 }
2296 }
2297 return 0;
a4fc5ed6
KP		 2298}
2299
1aad7ac0
CW		 2300static bool
2301intel_dp_detect_audio(struct drm_connector *connector)
2302{
2303 struct intel_dp *intel_dp = intel_attached_dp(connector);
2304 struct edid *edid;
2305 bool has_audio = false;
2306
8c241fef 2307 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1aad7ac0
CW		 2308 if (edid) {
2309 has_audio = drm_detect_monitor_audio(edid);
2310
2311 connector->display_info.raw_edid = NULL;
2312 kfree(edid);
2313 }
2314
2315 return has_audio;
2316}
2317
f684960e
CW		 2318static int
2319intel_dp_set_property(struct drm_connector *connector,
2320 struct drm_property *property,
2321 uint64_t val)
2322{
e953fd7b 2323 struct drm_i915_private *dev_priv = connector->dev->dev_private;
f684960e
CW		 2324 struct intel_dp *intel_dp = intel_attached_dp(connector);
2325 int ret;
2326
2327 ret = drm_connector_property_set_value(connector, property, val);
2328 if (ret)
2329 return ret;
2330
3f43c48d 2331 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 2332 int i = val;
2333 bool has_audio;
2334
2335 if (i == intel_dp->force_audio)
f684960e
CW		 2336 return 0;
2337
1aad7ac0 2338 intel_dp->force_audio = i;
f684960e 2339
c3e5f67b 2340 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 2341 has_audio = intel_dp_detect_audio(connector);
2342 else
c3e5f67b 2343 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 2344
2345 if (has_audio == intel_dp->has_audio)
f684960e
CW		 2346 return 0;
2347
1aad7ac0 2348 intel_dp->has_audio = has_audio;
f684960e
CW		 2349 goto done;
2350 }
2351
e953fd7b
CW		 2352 if (property == dev_priv->broadcast_rgb_property) {
2353 if (val == !!intel_dp->color_range)
2354 return 0;
2355
2356 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
2357 goto done;
2358 }
2359
f684960e
CW		 2360 return -EINVAL;
2361
2362done:
2363 if (intel_dp->base.base.crtc) {
2364 struct drm_crtc *crtc = intel_dp->base.base.crtc;
a6778b3c
DV		 2365 intel_set_mode(crtc, &crtc->mode,
2366 crtc->x, crtc->y, crtc->fb);
f684960e
CW		 2367 }
2368
2369 return 0;
2370}
2371
a4fc5ed6 2372static void
0206e353 2373intel_dp_destroy(struct drm_connector *connector)
a4fc5ed6 2374{
aaa6fd2a
MG		 2375 struct drm_device *dev = connector->dev;
2376
2377 if (intel_dpd_is_edp(dev))
2378 intel_panel_destroy_backlight(dev);
2379
a4fc5ed6
KP		 2380 drm_sysfs_connector_remove(connector);
2381 drm_connector_cleanup(connector);
55f78c43 2382 kfree(connector);
a4fc5ed6
KP		 2383}
2384
24d05927
DV		 2385static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2386{
2387 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2388
2389 i2c_del_adapter(&intel_dp->adapter);
2390 drm_encoder_cleanup(encoder);
bd943159 2391 if (is_edp(intel_dp)) {
d6f24d0f 2392 kfree(intel_dp->edid);
bd943159
KP		 2393 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2394 ironlake_panel_vdd_off_sync(intel_dp);
2395 }
24d05927
DV		 2396 kfree(intel_dp);
2397}
2398
a4fc5ed6 2399static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
a4fc5ed6 2400 .mode_fixup = intel_dp_mode_fixup,
a4fc5ed6 2401 .mode_set = intel_dp_mode_set,
e8cb4558 2402 .disable = intel_encoder_disable,
a4fc5ed6
KP		 2403};
2404
2405static const struct drm_connector_funcs intel_dp_connector_funcs = {
e8cb4558 2406 .dpms = intel_dp_dpms,
a4fc5ed6
KP		 2407 .detect = intel_dp_detect,
2408 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 2409 .set_property = intel_dp_set_property,
a4fc5ed6
KP		 2410 .destroy = intel_dp_destroy,
2411};
2412
2413static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2414 .get_modes = intel_dp_get_modes,
2415 .mode_valid = intel_dp_mode_valid,
df0e9248 2416 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 2417};
2418
a4fc5ed6 2419static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 2420 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 2421};
2422
995b6762 2423static void
21d40d37 2424intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 2425{
ea5b213a 2426 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
c8110e52 2427
885a5014 2428 intel_dp_check_link_status(intel_dp);
c8110e52 2429}
6207937d 2430
e3421a18
ZW		 2431/* Return which DP Port should be selected for Transcoder DP control */
2432int
0206e353 2433intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 2434{
2435 struct drm_device *dev = crtc->dev;
6c2b7c12 2436 struct intel_encoder *encoder;
e3421a18 2437
6c2b7c12
DV		 2438 for_each_encoder_on_crtc(dev, crtc, encoder) {
2439 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
e3421a18 2440
417e822d
KP		 2441 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
2442 intel_dp->base.type == INTEL_OUTPUT_EDP)
ea5b213a 2443 return intel_dp->output_reg;
e3421a18 2444 }
ea5b213a 2445
e3421a18
ZW		 2446 return -1;
2447}
2448
36e83a18 2449/* check the VBT to see whether the eDP is on DP-D port */
cb0953d7 2450bool intel_dpd_is_edp(struct drm_device *dev)
36e83a18
ZY		 2451{
2452 struct drm_i915_private *dev_priv = dev->dev_private;
2453 struct child_device_config *p_child;
2454 int i;
2455
2456 if (!dev_priv->child_dev_num)
2457 return false;
2458
2459 for (i = 0; i < dev_priv->child_dev_num; i++) {
2460 p_child = dev_priv->child_dev + i;
2461
2462 if (p_child->dvo_port == PORT_IDPD &&
2463 p_child->device_type == DEVICE_TYPE_eDP)
2464 return true;
2465 }
2466 return false;
2467}
2468
f684960e
CW		 2469static void
2470intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2471{
3f43c48d 2472 intel_attach_force_audio_property(connector);
e953fd7b 2473 intel_attach_broadcast_rgb_property(connector);
f684960e
CW		 2474}
2475
a4fc5ed6 2476void
ab9d7c30 2477intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
a4fc5ed6
KP		 2478{
2479 struct drm_i915_private *dev_priv = dev->dev_private;
2480 struct drm_connector *connector;
ea5b213a 2481 struct intel_dp *intel_dp;
21d40d37 2482 struct intel_encoder *intel_encoder;
55f78c43 2483 struct intel_connector *intel_connector;
5eb08b69 2484 const char *name = NULL;
b329530c 2485 int type;
a4fc5ed6 2486
ea5b213a
CW		 2487 intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
2488 if (!intel_dp)
a4fc5ed6
KP		 2489 return;
2490
3d3dc149 2491 intel_dp->output_reg = output_reg;
ab9d7c30 2492 intel_dp->port = port;
d2b996ac 2493 intel_dp->dpms_mode = -1;
3d3dc149 2494
55f78c43
ZW		 2495 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2496 if (!intel_connector) {
ea5b213a 2497 kfree(intel_dp);
55f78c43
ZW		 2498 return;
2499 }
ea5b213a 2500 intel_encoder = &intel_dp->base;
55f78c43 2501
ea5b213a 2502 if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
b329530c 2503 if (intel_dpd_is_edp(dev))
ea5b213a 2504 intel_dp->is_pch_edp = true;
b329530c 2505
cfcb0fc9 2506 if (output_reg == DP_A || is_pch_edp(intel_dp)) {
b329530c
AJ		 2507 type = DRM_MODE_CONNECTOR_eDP;
2508 intel_encoder->type = INTEL_OUTPUT_EDP;
2509 } else {
2510 type = DRM_MODE_CONNECTOR_DisplayPort;
2511 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2512 }
2513
55f78c43 2514 connector = &intel_connector->base;
b329530c 2515 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 2516 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2517
eb1f8e4f
DA		 2518 connector->polled = DRM_CONNECTOR_POLL_HPD;
2519
66a9278e 2520 intel_encoder->cloneable = false;
f8aed700 2521
66a9278e
DV		 2522 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2523 ironlake_panel_vdd_work);
6251ec0a 2524
27f8227b 2525 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
ee7b9f93 2526
a4fc5ed6
KP		 2527 connector->interlace_allowed = true;
2528 connector->doublescan_allowed = 0;
2529
4ef69c7a 2530 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
a4fc5ed6 2531 DRM_MODE_ENCODER_TMDS);
4ef69c7a 2532 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
a4fc5ed6 2533
df0e9248 2534 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 2535 drm_sysfs_connector_add(connector);
2536
e8cb4558
DV		 2537 intel_encoder->enable = intel_enable_dp;
2538 intel_encoder->disable = intel_disable_dp;
19d8fe15
DV		 2539 intel_encoder->get_hw_state = intel_dp_get_hw_state;
2540 intel_connector->get_hw_state = intel_connector_get_hw_state;
e8cb4558 2541
a4fc5ed6 2542 /* Set up the DDC bus. */
ab9d7c30
PZ		 2543 switch (port) {
2544 case PORT_A:
2545 name = "DPDDC-A";
2546 break;
2547 case PORT_B:
2548 dev_priv->hotplug_supported_mask |= DPB_HOTPLUG_INT_STATUS;
2549 name = "DPDDC-B";
2550 break;
2551 case PORT_C:
2552 dev_priv->hotplug_supported_mask |= DPC_HOTPLUG_INT_STATUS;
2553 name = "DPDDC-C";
2554 break;
2555 case PORT_D:
2556 dev_priv->hotplug_supported_mask |= DPD_HOTPLUG_INT_STATUS;
2557 name = "DPDDC-D";
2558 break;
2559 default:
2560 WARN(1, "Invalid port %c\n", port_name(port));
2561 break;
5eb08b69
ZW		 2562 }
2563
d6f24d0f
JB		 2564 intel_dp_i2c_init(intel_dp, intel_connector, name);
2565
89667383
JB		 2566 /* Cache some DPCD data in the eDP case */
2567 if (is_edp(intel_dp)) {
59f3e272 2568 bool ret;
f01eca2e
KP		 2569 struct edp_power_seq cur, vbt;
2570 u32 pp_on, pp_off, pp_div;
d6f24d0f 2571 struct edid *edid;
5d613501
JB		 2572
2573 pp_on = I915_READ(PCH_PP_ON_DELAYS);
f01eca2e 2574 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
5d613501 2575 pp_div = I915_READ(PCH_PP_DIVISOR);
89667383 2576
bfa3384a
JB		 2577 if (!pp_on || !pp_off || !pp_div) {
2578 DRM_INFO("bad panel power sequencing delays, disabling panel\n");
2579 intel_dp_encoder_destroy(&intel_dp->base.base);
2580 intel_dp_destroy(&intel_connector->base);
2581 return;
2582 }
2583
f01eca2e
KP		 2584 /* Pull timing values out of registers */
2585 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2586 PANEL_POWER_UP_DELAY_SHIFT;
2587
2588 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2589 PANEL_LIGHT_ON_DELAY_SHIFT;
f2e8b18a 2590
f01eca2e
KP		 2591 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2592 PANEL_LIGHT_OFF_DELAY_SHIFT;
2593
2594 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2595 PANEL_POWER_DOWN_DELAY_SHIFT;
2596
2597 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2598 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2599
2600 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2601 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2602
2603 vbt = dev_priv->edp.pps;
2604
2605 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2606 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2607
2608#define get_delay(field) ((max(cur.field, vbt.field) + 9) / 10)
2609
2610 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2611 intel_dp->backlight_on_delay = get_delay(t8);
2612 intel_dp->backlight_off_delay = get_delay(t9);
2613 intel_dp->panel_power_down_delay = get_delay(t10);
2614 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2615
2616 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2617 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2618 intel_dp->panel_power_cycle_delay);
2619
2620 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2621 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
5d613501
JB		 2622
2623 ironlake_edp_panel_vdd_on(intel_dp);
59f3e272 2624 ret = intel_dp_get_dpcd(intel_dp);
bd943159 2625 ironlake_edp_panel_vdd_off(intel_dp, false);
99ea7127 2626
59f3e272 2627 if (ret) {
7183dc29
JB		 2628 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2629 dev_priv->no_aux_handshake =
2630 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
89667383
JB		 2631 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2632 } else {
3d3dc149 2633 /* if this fails, presume the device is a ghost */
48898b03 2634 DRM_INFO("failed to retrieve link info, disabling eDP\n");
3d3dc149 2635 intel_dp_encoder_destroy(&intel_dp->base.base);
48898b03 2636 intel_dp_destroy(&intel_connector->base);
3d3dc149 2637 return;
89667383 2638 }
89667383 2639
d6f24d0f
JB		 2640 ironlake_edp_panel_vdd_on(intel_dp);
2641 edid = drm_get_edid(connector, &intel_dp->adapter);
2642 if (edid) {
2643 drm_mode_connector_update_edid_property(connector,
2644 edid);
2645 intel_dp->edid_mode_count =
2646 drm_add_edid_modes(connector, edid);
2647 drm_edid_to_eld(connector, edid);
2648 intel_dp->edid = edid;
2649 }
2650 ironlake_edp_panel_vdd_off(intel_dp, false);
2651 }
552fb0b7 2652
21d40d37 2653 intel_encoder->hot_plug = intel_dp_hot_plug;
a4fc5ed6 2654
4d926461 2655 if (is_edp(intel_dp)) {
aaa6fd2a
MG		 2656 dev_priv->int_edp_connector = connector;
2657 intel_panel_setup_backlight(dev);
32f9d658
ZW		 2658 }
2659
f684960e
CW		 2660 intel_dp_add_properties(intel_dp, connector);
2661
a4fc5ed6
KP		 2662 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2663 * 0xd. Failure to do so will result in spurious interrupts being
2664 * generated on the port when a cable is not attached.
2665 */
2666 if (IS_G4X(dev) && !IS_GM45(dev)) {
2667 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2668 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2669 }
2670}
Linux 6.x block layer and io_uring tree(s)