Commit | Line | Data |
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a4fc5ed6 KP |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Keith Packard <keithp@keithp.com> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include <linux/i2c.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
2d1a8a48 | 30 | #include <linux/export.h> |
611032bf | 31 | #include <linux/types.h> |
01527b31 CT |
32 | #include <linux/notifier.h> |
33 | #include <linux/reboot.h> | |
611032bf | 34 | #include <asm/byteorder.h> |
760285e7 | 35 | #include <drm/drmP.h> |
c6f95f27 | 36 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
37 | #include <drm/drm_crtc.h> |
38 | #include <drm/drm_crtc_helper.h> | |
20f24d77 | 39 | #include <drm/drm_dp_helper.h> |
760285e7 | 40 | #include <drm/drm_edid.h> |
20f24d77 | 41 | #include <drm/drm_hdcp.h> |
a4fc5ed6 | 42 | #include "intel_drv.h" |
760285e7 | 43 | #include <drm/i915_drm.h> |
a4fc5ed6 | 44 | #include "i915_drv.h" |
a4fc5ed6 | 45 | |
e8b2577c | 46 | #define DP_DPRX_ESI_LEN 14 |
a4fc5ed6 | 47 | |
559be30c TP |
48 | /* Compliance test status bits */ |
49 | #define INTEL_DP_RESOLUTION_SHIFT_MASK 0 | |
50 | #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK) | |
51 | #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK) | |
52 | #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK) | |
53 | ||
9dd4ffdf | 54 | struct dp_link_dpll { |
840b32b7 | 55 | int clock; |
9dd4ffdf CML |
56 | struct dpll dpll; |
57 | }; | |
58 | ||
59 | static const struct dp_link_dpll gen4_dpll[] = { | |
840b32b7 | 60 | { 162000, |
9dd4ffdf | 61 | { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } }, |
840b32b7 | 62 | { 270000, |
9dd4ffdf CML |
63 | { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } } |
64 | }; | |
65 | ||
66 | static const struct dp_link_dpll pch_dpll[] = { | |
840b32b7 | 67 | { 162000, |
9dd4ffdf | 68 | { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } }, |
840b32b7 | 69 | { 270000, |
9dd4ffdf CML |
70 | { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } } |
71 | }; | |
72 | ||
65ce4bf5 | 73 | static const struct dp_link_dpll vlv_dpll[] = { |
840b32b7 | 74 | { 162000, |
58f6e632 | 75 | { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } }, |
840b32b7 | 76 | { 270000, |
65ce4bf5 CML |
77 | { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } } |
78 | }; | |
79 | ||
ef9348c8 CML |
80 | /* |
81 | * CHV supports eDP 1.4 that have more link rates. | |
82 | * Below only provides the fixed rate but exclude variable rate. | |
83 | */ | |
84 | static const struct dp_link_dpll chv_dpll[] = { | |
85 | /* | |
86 | * CHV requires to program fractional division for m2. | |
87 | * m2 is stored in fixed point format using formula below | |
88 | * (m2_int << 22) | m2_fraction | |
89 | */ | |
840b32b7 | 90 | { 162000, /* m2_int = 32, m2_fraction = 1677722 */ |
ef9348c8 | 91 | { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } }, |
840b32b7 | 92 | { 270000, /* m2_int = 27, m2_fraction = 0 */ |
ef9348c8 | 93 | { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }, |
ef9348c8 | 94 | }; |
637a9c63 | 95 | |
cfcb0fc9 | 96 | /** |
1853a9da | 97 | * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH) |
cfcb0fc9 JB |
98 | * @intel_dp: DP struct |
99 | * | |
100 | * If a CPU or PCH DP output is attached to an eDP panel, this function | |
101 | * will return true, and false otherwise. | |
102 | */ | |
1853a9da | 103 | bool intel_dp_is_edp(struct intel_dp *intel_dp) |
cfcb0fc9 | 104 | { |
da63a9f2 PZ |
105 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
106 | ||
107 | return intel_dig_port->base.type == INTEL_OUTPUT_EDP; | |
cfcb0fc9 JB |
108 | } |
109 | ||
68b4d824 | 110 | static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp) |
cfcb0fc9 | 111 | { |
68b4d824 ID |
112 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
113 | ||
114 | return intel_dig_port->base.base.dev; | |
cfcb0fc9 JB |
115 | } |
116 | ||
df0e9248 CW |
117 | static struct intel_dp *intel_attached_dp(struct drm_connector *connector) |
118 | { | |
fa90ecef | 119 | return enc_to_intel_dp(&intel_attached_encoder(connector)->base); |
df0e9248 CW |
120 | } |
121 | ||
adc10304 VS |
122 | static void intel_dp_link_down(struct intel_encoder *encoder, |
123 | const struct intel_crtc_state *old_crtc_state); | |
1e0560e0 | 124 | static bool edp_panel_vdd_on(struct intel_dp *intel_dp); |
4be73780 | 125 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); |
adc10304 VS |
126 | static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder, |
127 | const struct intel_crtc_state *crtc_state); | |
46bd8383 | 128 | static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv, |
a8c3344e | 129 | enum pipe pipe); |
f21a2198 | 130 | static void intel_dp_unset_edid(struct intel_dp *intel_dp); |
a4fc5ed6 | 131 | |
68f357cb JN |
132 | /* update sink rates from dpcd */ |
133 | static void intel_dp_set_sink_rates(struct intel_dp *intel_dp) | |
134 | { | |
229675d5 | 135 | static const int dp_rates[] = { |
c71b53cc | 136 | 162000, 270000, 540000, 810000 |
229675d5 | 137 | }; |
a8a08886 | 138 | int i, max_rate; |
68f357cb | 139 | |
a8a08886 | 140 | max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]); |
68f357cb | 141 | |
229675d5 JN |
142 | for (i = 0; i < ARRAY_SIZE(dp_rates); i++) { |
143 | if (dp_rates[i] > max_rate) | |
a8a08886 | 144 | break; |
229675d5 | 145 | intel_dp->sink_rates[i] = dp_rates[i]; |
a8a08886 | 146 | } |
68f357cb | 147 | |
a8a08886 | 148 | intel_dp->num_sink_rates = i; |
68f357cb JN |
149 | } |
150 | ||
10ebb736 JN |
151 | /* Get length of rates array potentially limited by max_rate. */ |
152 | static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate) | |
153 | { | |
154 | int i; | |
155 | ||
156 | /* Limit results by potentially reduced max rate */ | |
157 | for (i = 0; i < len; i++) { | |
158 | if (rates[len - i - 1] <= max_rate) | |
159 | return len - i; | |
160 | } | |
161 | ||
162 | return 0; | |
163 | } | |
164 | ||
165 | /* Get length of common rates array potentially limited by max_rate. */ | |
166 | static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp, | |
167 | int max_rate) | |
168 | { | |
169 | return intel_dp_rate_limit_len(intel_dp->common_rates, | |
170 | intel_dp->num_common_rates, max_rate); | |
171 | } | |
172 | ||
540b0b7f JN |
173 | /* Theoretical max between source and sink */ |
174 | static int intel_dp_max_common_rate(struct intel_dp *intel_dp) | |
a4fc5ed6 | 175 | { |
540b0b7f | 176 | return intel_dp->common_rates[intel_dp->num_common_rates - 1]; |
a4fc5ed6 KP |
177 | } |
178 | ||
540b0b7f JN |
179 | /* Theoretical max between source and sink */ |
180 | static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp) | |
eeb6324d PZ |
181 | { |
182 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
540b0b7f JN |
183 | int source_max = intel_dig_port->max_lanes; |
184 | int sink_max = drm_dp_max_lane_count(intel_dp->dpcd); | |
eeb6324d PZ |
185 | |
186 | return min(source_max, sink_max); | |
187 | } | |
188 | ||
3d65a735 | 189 | int intel_dp_max_lane_count(struct intel_dp *intel_dp) |
540b0b7f JN |
190 | { |
191 | return intel_dp->max_link_lane_count; | |
192 | } | |
193 | ||
22a2c8e0 | 194 | int |
c898261c | 195 | intel_dp_link_required(int pixel_clock, int bpp) |
a4fc5ed6 | 196 | { |
fd81c44e DP |
197 | /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */ |
198 | return DIV_ROUND_UP(pixel_clock * bpp, 8); | |
a4fc5ed6 KP |
199 | } |
200 | ||
22a2c8e0 | 201 | int |
fe27d53e DA |
202 | intel_dp_max_data_rate(int max_link_clock, int max_lanes) |
203 | { | |
fd81c44e DP |
204 | /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the |
205 | * link rate that is generally expressed in Gbps. Since, 8 bits of data | |
206 | * is transmitted every LS_Clk per lane, there is no need to account for | |
207 | * the channel encoding that is done in the PHY layer here. | |
208 | */ | |
209 | ||
210 | return max_link_clock * max_lanes; | |
fe27d53e DA |
211 | } |
212 | ||
70ec0645 MK |
213 | static int |
214 | intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp) | |
215 | { | |
216 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
217 | struct intel_encoder *encoder = &intel_dig_port->base; | |
218 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
219 | int max_dotclk = dev_priv->max_dotclk_freq; | |
220 | int ds_max_dotclk; | |
221 | ||
222 | int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; | |
223 | ||
224 | if (type != DP_DS_PORT_TYPE_VGA) | |
225 | return max_dotclk; | |
226 | ||
227 | ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd, | |
228 | intel_dp->downstream_ports); | |
229 | ||
230 | if (ds_max_dotclk != 0) | |
231 | max_dotclk = min(max_dotclk, ds_max_dotclk); | |
232 | ||
233 | return max_dotclk; | |
234 | } | |
235 | ||
4ba285d4 | 236 | static int cnl_max_source_rate(struct intel_dp *intel_dp) |
53ddb3cd RV |
237 | { |
238 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
239 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); | |
240 | enum port port = dig_port->base.port; | |
241 | ||
242 | u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; | |
243 | ||
244 | /* Low voltage SKUs are limited to max of 5.4G */ | |
245 | if (voltage == VOLTAGE_INFO_0_85V) | |
4ba285d4 | 246 | return 540000; |
53ddb3cd RV |
247 | |
248 | /* For this SKU 8.1G is supported in all ports */ | |
249 | if (IS_CNL_WITH_PORT_F(dev_priv)) | |
4ba285d4 | 250 | return 810000; |
53ddb3cd | 251 | |
3758d968 | 252 | /* For other SKUs, max rate on ports A and D is 5.4G */ |
53ddb3cd | 253 | if (port == PORT_A || port == PORT_D) |
4ba285d4 | 254 | return 540000; |
53ddb3cd | 255 | |
4ba285d4 | 256 | return 810000; |
53ddb3cd RV |
257 | } |
258 | ||
55cfc580 JN |
259 | static void |
260 | intel_dp_set_source_rates(struct intel_dp *intel_dp) | |
40dba341 | 261 | { |
229675d5 JN |
262 | /* The values must be in increasing order */ |
263 | static const int cnl_rates[] = { | |
264 | 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000 | |
265 | }; | |
266 | static const int bxt_rates[] = { | |
267 | 162000, 216000, 243000, 270000, 324000, 432000, 540000 | |
268 | }; | |
269 | static const int skl_rates[] = { | |
270 | 162000, 216000, 270000, 324000, 432000, 540000 | |
271 | }; | |
272 | static const int hsw_rates[] = { | |
273 | 162000, 270000, 540000 | |
274 | }; | |
275 | static const int g4x_rates[] = { | |
276 | 162000, 270000 | |
277 | }; | |
40dba341 NM |
278 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
279 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); | |
99b91bda JN |
280 | const struct ddi_vbt_port_info *info = |
281 | &dev_priv->vbt.ddi_port_info[dig_port->base.port]; | |
55cfc580 | 282 | const int *source_rates; |
99b91bda | 283 | int size, max_rate = 0, vbt_max_rate = info->dp_max_link_rate; |
40dba341 | 284 | |
55cfc580 JN |
285 | /* This should only be done once */ |
286 | WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates); | |
287 | ||
ba1c06a5 | 288 | if (IS_CANNONLAKE(dev_priv)) { |
d907b665 | 289 | source_rates = cnl_rates; |
4ba285d4 JN |
290 | size = ARRAY_SIZE(cnl_rates); |
291 | max_rate = cnl_max_source_rate(intel_dp); | |
ba1c06a5 MN |
292 | } else if (IS_GEN9_LP(dev_priv)) { |
293 | source_rates = bxt_rates; | |
294 | size = ARRAY_SIZE(bxt_rates); | |
b976dc53 | 295 | } else if (IS_GEN9_BC(dev_priv)) { |
55cfc580 | 296 | source_rates = skl_rates; |
40dba341 | 297 | size = ARRAY_SIZE(skl_rates); |
fc603ca7 JN |
298 | } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) || |
299 | IS_BROADWELL(dev_priv)) { | |
229675d5 JN |
300 | source_rates = hsw_rates; |
301 | size = ARRAY_SIZE(hsw_rates); | |
fc603ca7 | 302 | } else { |
229675d5 JN |
303 | source_rates = g4x_rates; |
304 | size = ARRAY_SIZE(g4x_rates); | |
40dba341 NM |
305 | } |
306 | ||
99b91bda JN |
307 | if (max_rate && vbt_max_rate) |
308 | max_rate = min(max_rate, vbt_max_rate); | |
309 | else if (vbt_max_rate) | |
310 | max_rate = vbt_max_rate; | |
311 | ||
4ba285d4 JN |
312 | if (max_rate) |
313 | size = intel_dp_rate_limit_len(source_rates, size, max_rate); | |
314 | ||
55cfc580 JN |
315 | intel_dp->source_rates = source_rates; |
316 | intel_dp->num_source_rates = size; | |
40dba341 NM |
317 | } |
318 | ||
319 | static int intersect_rates(const int *source_rates, int source_len, | |
320 | const int *sink_rates, int sink_len, | |
321 | int *common_rates) | |
322 | { | |
323 | int i = 0, j = 0, k = 0; | |
324 | ||
325 | while (i < source_len && j < sink_len) { | |
326 | if (source_rates[i] == sink_rates[j]) { | |
327 | if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES)) | |
328 | return k; | |
329 | common_rates[k] = source_rates[i]; | |
330 | ++k; | |
331 | ++i; | |
332 | ++j; | |
333 | } else if (source_rates[i] < sink_rates[j]) { | |
334 | ++i; | |
335 | } else { | |
336 | ++j; | |
337 | } | |
338 | } | |
339 | return k; | |
340 | } | |
341 | ||
8001b754 JN |
342 | /* return index of rate in rates array, or -1 if not found */ |
343 | static int intel_dp_rate_index(const int *rates, int len, int rate) | |
344 | { | |
345 | int i; | |
346 | ||
347 | for (i = 0; i < len; i++) | |
348 | if (rate == rates[i]) | |
349 | return i; | |
350 | ||
351 | return -1; | |
352 | } | |
353 | ||
975ee5fc | 354 | static void intel_dp_set_common_rates(struct intel_dp *intel_dp) |
40dba341 | 355 | { |
975ee5fc | 356 | WARN_ON(!intel_dp->num_source_rates || !intel_dp->num_sink_rates); |
40dba341 | 357 | |
975ee5fc JN |
358 | intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates, |
359 | intel_dp->num_source_rates, | |
360 | intel_dp->sink_rates, | |
361 | intel_dp->num_sink_rates, | |
362 | intel_dp->common_rates); | |
363 | ||
364 | /* Paranoia, there should always be something in common. */ | |
365 | if (WARN_ON(intel_dp->num_common_rates == 0)) { | |
229675d5 | 366 | intel_dp->common_rates[0] = 162000; |
975ee5fc JN |
367 | intel_dp->num_common_rates = 1; |
368 | } | |
369 | } | |
370 | ||
1a92c70e MN |
371 | static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate, |
372 | uint8_t lane_count) | |
14c562c0 MN |
373 | { |
374 | /* | |
375 | * FIXME: we need to synchronize the current link parameters with | |
376 | * hardware readout. Currently fast link training doesn't work on | |
377 | * boot-up. | |
378 | */ | |
1a92c70e MN |
379 | if (link_rate == 0 || |
380 | link_rate > intel_dp->max_link_rate) | |
14c562c0 MN |
381 | return false; |
382 | ||
1a92c70e MN |
383 | if (lane_count == 0 || |
384 | lane_count > intel_dp_max_lane_count(intel_dp)) | |
14c562c0 MN |
385 | return false; |
386 | ||
387 | return true; | |
388 | } | |
389 | ||
fdb14d33 MN |
390 | int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, |
391 | int link_rate, uint8_t lane_count) | |
392 | { | |
b1810a74 | 393 | int index; |
fdb14d33 | 394 | |
b1810a74 JN |
395 | index = intel_dp_rate_index(intel_dp->common_rates, |
396 | intel_dp->num_common_rates, | |
397 | link_rate); | |
398 | if (index > 0) { | |
e6c0c64a JN |
399 | intel_dp->max_link_rate = intel_dp->common_rates[index - 1]; |
400 | intel_dp->max_link_lane_count = lane_count; | |
fdb14d33 | 401 | } else if (lane_count > 1) { |
540b0b7f | 402 | intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp); |
e6c0c64a | 403 | intel_dp->max_link_lane_count = lane_count >> 1; |
fdb14d33 MN |
404 | } else { |
405 | DRM_ERROR("Link Training Unsuccessful\n"); | |
406 | return -1; | |
407 | } | |
408 | ||
409 | return 0; | |
410 | } | |
411 | ||
c19de8eb | 412 | static enum drm_mode_status |
a4fc5ed6 KP |
413 | intel_dp_mode_valid(struct drm_connector *connector, |
414 | struct drm_display_mode *mode) | |
415 | { | |
df0e9248 | 416 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
dd06f90e JN |
417 | struct intel_connector *intel_connector = to_intel_connector(connector); |
418 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; | |
36008365 DV |
419 | int target_clock = mode->clock; |
420 | int max_rate, mode_rate, max_lanes, max_link_clock; | |
70ec0645 MK |
421 | int max_dotclk; |
422 | ||
423 | max_dotclk = intel_dp_downstream_max_dotclock(intel_dp); | |
a4fc5ed6 | 424 | |
1853a9da | 425 | if (intel_dp_is_edp(intel_dp) && fixed_mode) { |
dd06f90e | 426 | if (mode->hdisplay > fixed_mode->hdisplay) |
7de56f43 ZY |
427 | return MODE_PANEL; |
428 | ||
dd06f90e | 429 | if (mode->vdisplay > fixed_mode->vdisplay) |
7de56f43 | 430 | return MODE_PANEL; |
03afc4a2 DV |
431 | |
432 | target_clock = fixed_mode->clock; | |
7de56f43 ZY |
433 | } |
434 | ||
50fec21a | 435 | max_link_clock = intel_dp_max_link_rate(intel_dp); |
eeb6324d | 436 | max_lanes = intel_dp_max_lane_count(intel_dp); |
36008365 DV |
437 | |
438 | max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); | |
439 | mode_rate = intel_dp_link_required(target_clock, 18); | |
440 | ||
799487f5 | 441 | if (mode_rate > max_rate || target_clock > max_dotclk) |
c4867936 | 442 | return MODE_CLOCK_HIGH; |
a4fc5ed6 KP |
443 | |
444 | if (mode->clock < 10000) | |
445 | return MODE_CLOCK_LOW; | |
446 | ||
0af78a2b DV |
447 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
448 | return MODE_H_ILLEGAL; | |
449 | ||
a4fc5ed6 KP |
450 | return MODE_OK; |
451 | } | |
452 | ||
a4f1289e | 453 | uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes) |
a4fc5ed6 KP |
454 | { |
455 | int i; | |
456 | uint32_t v = 0; | |
457 | ||
458 | if (src_bytes > 4) | |
459 | src_bytes = 4; | |
460 | for (i = 0; i < src_bytes; i++) | |
461 | v |= ((uint32_t) src[i]) << ((3-i) * 8); | |
462 | return v; | |
463 | } | |
464 | ||
c2af70e2 | 465 | static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) |
a4fc5ed6 KP |
466 | { |
467 | int i; | |
468 | if (dst_bytes > 4) | |
469 | dst_bytes = 4; | |
470 | for (i = 0; i < dst_bytes; i++) | |
471 | dst[i] = src >> ((3-i) * 8); | |
472 | } | |
473 | ||
bf13e81b | 474 | static void |
46bd8383 | 475 | intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp); |
bf13e81b | 476 | static void |
46bd8383 | 477 | intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp, |
5d5ab2d2 | 478 | bool force_disable_vdd); |
335f752b | 479 | static void |
46bd8383 | 480 | intel_dp_pps_init(struct intel_dp *intel_dp); |
bf13e81b | 481 | |
773538e8 VS |
482 | static void pps_lock(struct intel_dp *intel_dp) |
483 | { | |
2f773477 | 484 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
773538e8 VS |
485 | |
486 | /* | |
40c7ae45 | 487 | * See intel_power_sequencer_reset() why we need |
773538e8 VS |
488 | * a power domain reference here. |
489 | */ | |
5432fcaf | 490 | intel_display_power_get(dev_priv, intel_dp->aux_power_domain); |
773538e8 VS |
491 | |
492 | mutex_lock(&dev_priv->pps_mutex); | |
493 | } | |
494 | ||
495 | static void pps_unlock(struct intel_dp *intel_dp) | |
496 | { | |
2f773477 | 497 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
773538e8 VS |
498 | |
499 | mutex_unlock(&dev_priv->pps_mutex); | |
500 | ||
5432fcaf | 501 | intel_display_power_put(dev_priv, intel_dp->aux_power_domain); |
773538e8 VS |
502 | } |
503 | ||
961a0db0 VS |
504 | static void |
505 | vlv_power_sequencer_kick(struct intel_dp *intel_dp) | |
506 | { | |
2f773477 | 507 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
961a0db0 | 508 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
961a0db0 | 509 | enum pipe pipe = intel_dp->pps_pipe; |
0047eedc VS |
510 | bool pll_enabled, release_cl_override = false; |
511 | enum dpio_phy phy = DPIO_PHY(pipe); | |
512 | enum dpio_channel ch = vlv_pipe_to_channel(pipe); | |
961a0db0 VS |
513 | uint32_t DP; |
514 | ||
515 | if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN, | |
e7f2af78 | 516 | "skipping pipe %c power sequencer kick due to port %c being active\n", |
8f4f2797 | 517 | pipe_name(pipe), port_name(intel_dig_port->base.port))) |
961a0db0 VS |
518 | return; |
519 | ||
520 | DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n", | |
8f4f2797 | 521 | pipe_name(pipe), port_name(intel_dig_port->base.port)); |
961a0db0 VS |
522 | |
523 | /* Preserve the BIOS-computed detected bit. This is | |
524 | * supposed to be read-only. | |
525 | */ | |
526 | DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; | |
527 | DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; | |
528 | DP |= DP_PORT_WIDTH(1); | |
529 | DP |= DP_LINK_TRAIN_PAT_1; | |
530 | ||
920a14b2 | 531 | if (IS_CHERRYVIEW(dev_priv)) |
961a0db0 VS |
532 | DP |= DP_PIPE_SELECT_CHV(pipe); |
533 | else if (pipe == PIPE_B) | |
534 | DP |= DP_PIPEB_SELECT; | |
535 | ||
d288f65f VS |
536 | pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE; |
537 | ||
538 | /* | |
539 | * The DPLL for the pipe must be enabled for this to work. | |
540 | * So enable temporarily it if it's not already enabled. | |
541 | */ | |
0047eedc | 542 | if (!pll_enabled) { |
920a14b2 | 543 | release_cl_override = IS_CHERRYVIEW(dev_priv) && |
0047eedc VS |
544 | !chv_phy_powergate_ch(dev_priv, phy, ch, true); |
545 | ||
30ad9814 | 546 | if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ? |
3f36b937 TU |
547 | &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) { |
548 | DRM_ERROR("Failed to force on pll for pipe %c!\n", | |
549 | pipe_name(pipe)); | |
550 | return; | |
551 | } | |
0047eedc | 552 | } |
d288f65f | 553 | |
961a0db0 VS |
554 | /* |
555 | * Similar magic as in intel_dp_enable_port(). | |
556 | * We _must_ do this port enable + disable trick | |
e7f2af78 | 557 | * to make this power sequencer lock onto the port. |
961a0db0 VS |
558 | * Otherwise even VDD force bit won't work. |
559 | */ | |
560 | I915_WRITE(intel_dp->output_reg, DP); | |
561 | POSTING_READ(intel_dp->output_reg); | |
562 | ||
563 | I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN); | |
564 | POSTING_READ(intel_dp->output_reg); | |
565 | ||
566 | I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); | |
567 | POSTING_READ(intel_dp->output_reg); | |
d288f65f | 568 | |
0047eedc | 569 | if (!pll_enabled) { |
30ad9814 | 570 | vlv_force_pll_off(dev_priv, pipe); |
0047eedc VS |
571 | |
572 | if (release_cl_override) | |
573 | chv_phy_powergate_ch(dev_priv, phy, ch, false); | |
574 | } | |
961a0db0 VS |
575 | } |
576 | ||
9f2bdb00 VS |
577 | static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv) |
578 | { | |
579 | struct intel_encoder *encoder; | |
580 | unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); | |
581 | ||
582 | /* | |
583 | * We don't have power sequencer currently. | |
584 | * Pick one that's not used by other ports. | |
585 | */ | |
586 | for_each_intel_encoder(&dev_priv->drm, encoder) { | |
587 | struct intel_dp *intel_dp; | |
588 | ||
589 | if (encoder->type != INTEL_OUTPUT_DP && | |
590 | encoder->type != INTEL_OUTPUT_EDP) | |
591 | continue; | |
592 | ||
593 | intel_dp = enc_to_intel_dp(&encoder->base); | |
594 | ||
595 | if (encoder->type == INTEL_OUTPUT_EDP) { | |
596 | WARN_ON(intel_dp->active_pipe != INVALID_PIPE && | |
597 | intel_dp->active_pipe != intel_dp->pps_pipe); | |
598 | ||
599 | if (intel_dp->pps_pipe != INVALID_PIPE) | |
600 | pipes &= ~(1 << intel_dp->pps_pipe); | |
601 | } else { | |
602 | WARN_ON(intel_dp->pps_pipe != INVALID_PIPE); | |
603 | ||
604 | if (intel_dp->active_pipe != INVALID_PIPE) | |
605 | pipes &= ~(1 << intel_dp->active_pipe); | |
606 | } | |
607 | } | |
608 | ||
609 | if (pipes == 0) | |
610 | return INVALID_PIPE; | |
611 | ||
612 | return ffs(pipes) - 1; | |
613 | } | |
614 | ||
bf13e81b JN |
615 | static enum pipe |
616 | vlv_power_sequencer_pipe(struct intel_dp *intel_dp) | |
617 | { | |
46bd8383 | 618 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
bf13e81b | 619 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
a8c3344e | 620 | enum pipe pipe; |
bf13e81b | 621 | |
e39b999a | 622 | lockdep_assert_held(&dev_priv->pps_mutex); |
bf13e81b | 623 | |
a8c3344e | 624 | /* We should never land here with regular DP ports */ |
1853a9da | 625 | WARN_ON(!intel_dp_is_edp(intel_dp)); |
a8c3344e | 626 | |
9f2bdb00 VS |
627 | WARN_ON(intel_dp->active_pipe != INVALID_PIPE && |
628 | intel_dp->active_pipe != intel_dp->pps_pipe); | |
629 | ||
a4a5d2f8 VS |
630 | if (intel_dp->pps_pipe != INVALID_PIPE) |
631 | return intel_dp->pps_pipe; | |
632 | ||
9f2bdb00 | 633 | pipe = vlv_find_free_pps(dev_priv); |
a4a5d2f8 VS |
634 | |
635 | /* | |
636 | * Didn't find one. This should not happen since there | |
637 | * are two power sequencers and up to two eDP ports. | |
638 | */ | |
9f2bdb00 | 639 | if (WARN_ON(pipe == INVALID_PIPE)) |
a8c3344e | 640 | pipe = PIPE_A; |
a4a5d2f8 | 641 | |
46bd8383 | 642 | vlv_steal_power_sequencer(dev_priv, pipe); |
a8c3344e | 643 | intel_dp->pps_pipe = pipe; |
a4a5d2f8 VS |
644 | |
645 | DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n", | |
646 | pipe_name(intel_dp->pps_pipe), | |
8f4f2797 | 647 | port_name(intel_dig_port->base.port)); |
a4a5d2f8 VS |
648 | |
649 | /* init power sequencer on this pipe and port */ | |
46bd8383 VS |
650 | intel_dp_init_panel_power_sequencer(intel_dp); |
651 | intel_dp_init_panel_power_sequencer_registers(intel_dp, true); | |
a4a5d2f8 | 652 | |
961a0db0 VS |
653 | /* |
654 | * Even vdd force doesn't work until we've made | |
655 | * the power sequencer lock in on the port. | |
656 | */ | |
657 | vlv_power_sequencer_kick(intel_dp); | |
a4a5d2f8 VS |
658 | |
659 | return intel_dp->pps_pipe; | |
660 | } | |
661 | ||
78597996 ID |
662 | static int |
663 | bxt_power_sequencer_idx(struct intel_dp *intel_dp) | |
664 | { | |
46bd8383 | 665 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
73c0fcac | 666 | int backlight_controller = dev_priv->vbt.backlight.controller; |
78597996 ID |
667 | |
668 | lockdep_assert_held(&dev_priv->pps_mutex); | |
669 | ||
670 | /* We should never land here with regular DP ports */ | |
1853a9da | 671 | WARN_ON(!intel_dp_is_edp(intel_dp)); |
78597996 | 672 | |
78597996 | 673 | if (!intel_dp->pps_reset) |
73c0fcac | 674 | return backlight_controller; |
78597996 ID |
675 | |
676 | intel_dp->pps_reset = false; | |
677 | ||
678 | /* | |
679 | * Only the HW needs to be reprogrammed, the SW state is fixed and | |
680 | * has been setup during connector init. | |
681 | */ | |
46bd8383 | 682 | intel_dp_init_panel_power_sequencer_registers(intel_dp, false); |
78597996 | 683 | |
73c0fcac | 684 | return backlight_controller; |
78597996 ID |
685 | } |
686 | ||
6491ab27 VS |
687 | typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv, |
688 | enum pipe pipe); | |
689 | ||
690 | static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv, | |
691 | enum pipe pipe) | |
692 | { | |
44cb734c | 693 | return I915_READ(PP_STATUS(pipe)) & PP_ON; |
6491ab27 VS |
694 | } |
695 | ||
696 | static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv, | |
697 | enum pipe pipe) | |
698 | { | |
44cb734c | 699 | return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD; |
6491ab27 VS |
700 | } |
701 | ||
702 | static bool vlv_pipe_any(struct drm_i915_private *dev_priv, | |
703 | enum pipe pipe) | |
704 | { | |
705 | return true; | |
706 | } | |
bf13e81b | 707 | |
a4a5d2f8 | 708 | static enum pipe |
6491ab27 VS |
709 | vlv_initial_pps_pipe(struct drm_i915_private *dev_priv, |
710 | enum port port, | |
711 | vlv_pipe_check pipe_check) | |
a4a5d2f8 VS |
712 | { |
713 | enum pipe pipe; | |
bf13e81b | 714 | |
bf13e81b | 715 | for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { |
44cb734c | 716 | u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) & |
bf13e81b | 717 | PANEL_PORT_SELECT_MASK; |
a4a5d2f8 VS |
718 | |
719 | if (port_sel != PANEL_PORT_SELECT_VLV(port)) | |
720 | continue; | |
721 | ||
6491ab27 VS |
722 | if (!pipe_check(dev_priv, pipe)) |
723 | continue; | |
724 | ||
a4a5d2f8 | 725 | return pipe; |
bf13e81b JN |
726 | } |
727 | ||
a4a5d2f8 VS |
728 | return INVALID_PIPE; |
729 | } | |
730 | ||
731 | static void | |
732 | vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp) | |
733 | { | |
46bd8383 | 734 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
a4a5d2f8 | 735 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
8f4f2797 | 736 | enum port port = intel_dig_port->base.port; |
a4a5d2f8 VS |
737 | |
738 | lockdep_assert_held(&dev_priv->pps_mutex); | |
739 | ||
740 | /* try to find a pipe with this port selected */ | |
6491ab27 VS |
741 | /* first pick one where the panel is on */ |
742 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, | |
743 | vlv_pipe_has_pp_on); | |
744 | /* didn't find one? pick one where vdd is on */ | |
745 | if (intel_dp->pps_pipe == INVALID_PIPE) | |
746 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, | |
747 | vlv_pipe_has_vdd_on); | |
748 | /* didn't find one? pick one with just the correct port */ | |
749 | if (intel_dp->pps_pipe == INVALID_PIPE) | |
750 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, | |
751 | vlv_pipe_any); | |
a4a5d2f8 VS |
752 | |
753 | /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */ | |
754 | if (intel_dp->pps_pipe == INVALID_PIPE) { | |
755 | DRM_DEBUG_KMS("no initial power sequencer for port %c\n", | |
756 | port_name(port)); | |
757 | return; | |
bf13e81b JN |
758 | } |
759 | ||
a4a5d2f8 VS |
760 | DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n", |
761 | port_name(port), pipe_name(intel_dp->pps_pipe)); | |
762 | ||
46bd8383 VS |
763 | intel_dp_init_panel_power_sequencer(intel_dp); |
764 | intel_dp_init_panel_power_sequencer_registers(intel_dp, false); | |
bf13e81b JN |
765 | } |
766 | ||
78597996 | 767 | void intel_power_sequencer_reset(struct drm_i915_private *dev_priv) |
773538e8 | 768 | { |
773538e8 VS |
769 | struct intel_encoder *encoder; |
770 | ||
920a14b2 | 771 | if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && |
cc3f90f0 | 772 | !IS_GEN9_LP(dev_priv))) |
773538e8 VS |
773 | return; |
774 | ||
775 | /* | |
776 | * We can't grab pps_mutex here due to deadlock with power_domain | |
777 | * mutex when power_domain functions are called while holding pps_mutex. | |
778 | * That also means that in order to use pps_pipe the code needs to | |
779 | * hold both a power domain reference and pps_mutex, and the power domain | |
780 | * reference get/put must be done while _not_ holding pps_mutex. | |
781 | * pps_{lock,unlock}() do these steps in the correct order, so one | |
782 | * should use them always. | |
783 | */ | |
784 | ||
2f773477 | 785 | for_each_intel_encoder(&dev_priv->drm, encoder) { |
773538e8 VS |
786 | struct intel_dp *intel_dp; |
787 | ||
9f2bdb00 | 788 | if (encoder->type != INTEL_OUTPUT_DP && |
7e732cac VS |
789 | encoder->type != INTEL_OUTPUT_EDP && |
790 | encoder->type != INTEL_OUTPUT_DDI) | |
773538e8 VS |
791 | continue; |
792 | ||
793 | intel_dp = enc_to_intel_dp(&encoder->base); | |
9f2bdb00 | 794 | |
7e732cac VS |
795 | /* Skip pure DVI/HDMI DDI encoders */ |
796 | if (!i915_mmio_reg_valid(intel_dp->output_reg)) | |
797 | continue; | |
798 | ||
9f2bdb00 VS |
799 | WARN_ON(intel_dp->active_pipe != INVALID_PIPE); |
800 | ||
801 | if (encoder->type != INTEL_OUTPUT_EDP) | |
802 | continue; | |
803 | ||
cc3f90f0 | 804 | if (IS_GEN9_LP(dev_priv)) |
78597996 ID |
805 | intel_dp->pps_reset = true; |
806 | else | |
807 | intel_dp->pps_pipe = INVALID_PIPE; | |
773538e8 | 808 | } |
bf13e81b JN |
809 | } |
810 | ||
8e8232d5 ID |
811 | struct pps_registers { |
812 | i915_reg_t pp_ctrl; | |
813 | i915_reg_t pp_stat; | |
814 | i915_reg_t pp_on; | |
815 | i915_reg_t pp_off; | |
816 | i915_reg_t pp_div; | |
817 | }; | |
818 | ||
46bd8383 | 819 | static void intel_pps_get_registers(struct intel_dp *intel_dp, |
8e8232d5 ID |
820 | struct pps_registers *regs) |
821 | { | |
46bd8383 | 822 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
44cb734c ID |
823 | int pps_idx = 0; |
824 | ||
8e8232d5 ID |
825 | memset(regs, 0, sizeof(*regs)); |
826 | ||
cc3f90f0 | 827 | if (IS_GEN9_LP(dev_priv)) |
44cb734c ID |
828 | pps_idx = bxt_power_sequencer_idx(intel_dp); |
829 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
830 | pps_idx = vlv_power_sequencer_pipe(intel_dp); | |
8e8232d5 | 831 | |
44cb734c ID |
832 | regs->pp_ctrl = PP_CONTROL(pps_idx); |
833 | regs->pp_stat = PP_STATUS(pps_idx); | |
834 | regs->pp_on = PP_ON_DELAYS(pps_idx); | |
835 | regs->pp_off = PP_OFF_DELAYS(pps_idx); | |
b0d6a0f2 AS |
836 | if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) && |
837 | !HAS_PCH_ICP(dev_priv)) | |
44cb734c | 838 | regs->pp_div = PP_DIVISOR(pps_idx); |
8e8232d5 ID |
839 | } |
840 | ||
f0f59a00 VS |
841 | static i915_reg_t |
842 | _pp_ctrl_reg(struct intel_dp *intel_dp) | |
bf13e81b | 843 | { |
8e8232d5 | 844 | struct pps_registers regs; |
bf13e81b | 845 | |
46bd8383 | 846 | intel_pps_get_registers(intel_dp, ®s); |
8e8232d5 ID |
847 | |
848 | return regs.pp_ctrl; | |
bf13e81b JN |
849 | } |
850 | ||
f0f59a00 VS |
851 | static i915_reg_t |
852 | _pp_stat_reg(struct intel_dp *intel_dp) | |
bf13e81b | 853 | { |
8e8232d5 | 854 | struct pps_registers regs; |
bf13e81b | 855 | |
46bd8383 | 856 | intel_pps_get_registers(intel_dp, ®s); |
8e8232d5 ID |
857 | |
858 | return regs.pp_stat; | |
bf13e81b JN |
859 | } |
860 | ||
01527b31 CT |
861 | /* Reboot notifier handler to shutdown panel power to guarantee T12 timing |
862 | This function only applicable when panel PM state is not to be tracked */ | |
863 | static int edp_notify_handler(struct notifier_block *this, unsigned long code, | |
864 | void *unused) | |
865 | { | |
866 | struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp), | |
867 | edp_notifier); | |
2f773477 | 868 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
01527b31 | 869 | |
1853a9da | 870 | if (!intel_dp_is_edp(intel_dp) || code != SYS_RESTART) |
01527b31 CT |
871 | return 0; |
872 | ||
773538e8 | 873 | pps_lock(intel_dp); |
e39b999a | 874 | |
920a14b2 | 875 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
e39b999a | 876 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
f0f59a00 | 877 | i915_reg_t pp_ctrl_reg, pp_div_reg; |
649636ef | 878 | u32 pp_div; |
e39b999a | 879 | |
44cb734c ID |
880 | pp_ctrl_reg = PP_CONTROL(pipe); |
881 | pp_div_reg = PP_DIVISOR(pipe); | |
01527b31 CT |
882 | pp_div = I915_READ(pp_div_reg); |
883 | pp_div &= PP_REFERENCE_DIVIDER_MASK; | |
884 | ||
885 | /* 0x1F write to PP_DIV_REG sets max cycle delay */ | |
886 | I915_WRITE(pp_div_reg, pp_div | 0x1F); | |
887 | I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); | |
888 | msleep(intel_dp->panel_power_cycle_delay); | |
889 | } | |
890 | ||
773538e8 | 891 | pps_unlock(intel_dp); |
e39b999a | 892 | |
01527b31 CT |
893 | return 0; |
894 | } | |
895 | ||
4be73780 | 896 | static bool edp_have_panel_power(struct intel_dp *intel_dp) |
ebf33b18 | 897 | { |
2f773477 | 898 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
ebf33b18 | 899 | |
e39b999a VS |
900 | lockdep_assert_held(&dev_priv->pps_mutex); |
901 | ||
920a14b2 | 902 | if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
9a42356b VS |
903 | intel_dp->pps_pipe == INVALID_PIPE) |
904 | return false; | |
905 | ||
bf13e81b | 906 | return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0; |
ebf33b18 KP |
907 | } |
908 | ||
4be73780 | 909 | static bool edp_have_panel_vdd(struct intel_dp *intel_dp) |
ebf33b18 | 910 | { |
2f773477 | 911 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
ebf33b18 | 912 | |
e39b999a VS |
913 | lockdep_assert_held(&dev_priv->pps_mutex); |
914 | ||
920a14b2 | 915 | if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
9a42356b VS |
916 | intel_dp->pps_pipe == INVALID_PIPE) |
917 | return false; | |
918 | ||
773538e8 | 919 | return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD; |
ebf33b18 KP |
920 | } |
921 | ||
9b984dae KP |
922 | static void |
923 | intel_dp_check_edp(struct intel_dp *intel_dp) | |
924 | { | |
2f773477 | 925 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
ebf33b18 | 926 | |
1853a9da | 927 | if (!intel_dp_is_edp(intel_dp)) |
9b984dae | 928 | return; |
453c5420 | 929 | |
4be73780 | 930 | if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) { |
9b984dae KP |
931 | WARN(1, "eDP powered off while attempting aux channel communication.\n"); |
932 | DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", | |
bf13e81b JN |
933 | I915_READ(_pp_stat_reg(intel_dp)), |
934 | I915_READ(_pp_ctrl_reg(intel_dp))); | |
9b984dae KP |
935 | } |
936 | } | |
937 | ||
9ee32fea DV |
938 | static uint32_t |
939 | intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq) | |
940 | { | |
2f773477 | 941 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
4904fa66 | 942 | i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp); |
9ee32fea DV |
943 | uint32_t status; |
944 | bool done; | |
945 | ||
ef04f00d | 946 | #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
9ee32fea | 947 | if (has_aux_irq) |
b18ac466 | 948 | done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, |
3598706b | 949 | msecs_to_jiffies_timeout(10)); |
9ee32fea | 950 | else |
713a6b66 | 951 | done = wait_for(C, 10) == 0; |
9ee32fea DV |
952 | if (!done) |
953 | DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n", | |
954 | has_aux_irq); | |
955 | #undef C | |
956 | ||
957 | return status; | |
958 | } | |
959 | ||
6ffb1be7 | 960 | static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
a4fc5ed6 | 961 | { |
449059a9 | 962 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
9ee32fea | 963 | |
a457f54b VS |
964 | if (index) |
965 | return 0; | |
966 | ||
ec5b01dd DL |
967 | /* |
968 | * The clock divider is based off the hrawclk, and would like to run at | |
a457f54b | 969 | * 2MHz. So, take the hrawclk value and divide by 2000 and use that |
a4fc5ed6 | 970 | */ |
a457f54b | 971 | return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000); |
ec5b01dd DL |
972 | } |
973 | ||
974 | static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) | |
975 | { | |
449059a9 | 976 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
ec5b01dd DL |
977 | |
978 | if (index) | |
979 | return 0; | |
980 | ||
a457f54b VS |
981 | /* |
982 | * The clock divider is based off the cdclk or PCH rawclk, and would | |
983 | * like to run at 2MHz. So, take the cdclk or PCH rawclk value and | |
984 | * divide by 2000 and use that | |
985 | */ | |
449059a9 | 986 | if (intel_dp->aux_ch == AUX_CH_A) |
49cd97a3 | 987 | return DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.cdclk, 2000); |
e7dc33f3 VS |
988 | else |
989 | return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000); | |
ec5b01dd DL |
990 | } |
991 | ||
992 | static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) | |
993 | { | |
449059a9 | 994 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
ec5b01dd | 995 | |
449059a9 | 996 | if (intel_dp->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) { |
2c55c336 | 997 | /* Workaround for non-ULT HSW */ |
bc86625a CW |
998 | switch (index) { |
999 | case 0: return 63; | |
1000 | case 1: return 72; | |
1001 | default: return 0; | |
1002 | } | |
2c55c336 | 1003 | } |
a457f54b VS |
1004 | |
1005 | return ilk_get_aux_clock_divider(intel_dp, index); | |
b84a1cf8 RV |
1006 | } |
1007 | ||
b6b5e383 DL |
1008 | static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
1009 | { | |
1010 | /* | |
1011 | * SKL doesn't need us to program the AUX clock divider (Hardware will | |
1012 | * derive the clock from CDCLK automatically). We still implement the | |
1013 | * get_aux_clock_divider vfunc to plug-in into the existing code. | |
1014 | */ | |
1015 | return index ? 0 : 1; | |
1016 | } | |
1017 | ||
6ffb1be7 VS |
1018 | static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp, |
1019 | bool has_aux_irq, | |
1020 | int send_bytes, | |
1021 | uint32_t aux_clock_divider) | |
5ed12a19 DL |
1022 | { |
1023 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
8652744b TU |
1024 | struct drm_i915_private *dev_priv = |
1025 | to_i915(intel_dig_port->base.base.dev); | |
5ed12a19 DL |
1026 | uint32_t precharge, timeout; |
1027 | ||
8652744b | 1028 | if (IS_GEN6(dev_priv)) |
5ed12a19 DL |
1029 | precharge = 3; |
1030 | else | |
1031 | precharge = 5; | |
1032 | ||
8f5f63d5 | 1033 | if (IS_BROADWELL(dev_priv)) |
5ed12a19 DL |
1034 | timeout = DP_AUX_CH_CTL_TIME_OUT_600us; |
1035 | else | |
1036 | timeout = DP_AUX_CH_CTL_TIME_OUT_400us; | |
1037 | ||
1038 | return DP_AUX_CH_CTL_SEND_BUSY | | |
788d4433 | 1039 | DP_AUX_CH_CTL_DONE | |
5ed12a19 | 1040 | (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | |
788d4433 | 1041 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
5ed12a19 | 1042 | timeout | |
788d4433 | 1043 | DP_AUX_CH_CTL_RECEIVE_ERROR | |
5ed12a19 DL |
1044 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
1045 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | | |
788d4433 | 1046 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT); |
5ed12a19 DL |
1047 | } |
1048 | ||
b9ca5fad DL |
1049 | static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp, |
1050 | bool has_aux_irq, | |
1051 | int send_bytes, | |
1052 | uint32_t unused) | |
1053 | { | |
1054 | return DP_AUX_CH_CTL_SEND_BUSY | | |
1055 | DP_AUX_CH_CTL_DONE | | |
1056 | (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | | |
1057 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
6fa228ba | 1058 | DP_AUX_CH_CTL_TIME_OUT_MAX | |
b9ca5fad DL |
1059 | DP_AUX_CH_CTL_RECEIVE_ERROR | |
1060 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | | |
d4dcbdce | 1061 | DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) | |
b9ca5fad DL |
1062 | DP_AUX_CH_CTL_SYNC_PULSE_SKL(32); |
1063 | } | |
1064 | ||
b84a1cf8 | 1065 | static int |
f7606265 VS |
1066 | intel_dp_aux_xfer(struct intel_dp *intel_dp, |
1067 | const uint8_t *send, int send_bytes, | |
8159c796 VS |
1068 | uint8_t *recv, int recv_size, |
1069 | u32 aux_send_ctl_flags) | |
b84a1cf8 RV |
1070 | { |
1071 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
0031fb96 TU |
1072 | struct drm_i915_private *dev_priv = |
1073 | to_i915(intel_dig_port->base.base.dev); | |
4904fa66 | 1074 | i915_reg_t ch_ctl, ch_data[5]; |
bc86625a | 1075 | uint32_t aux_clock_divider; |
b84a1cf8 RV |
1076 | int i, ret, recv_bytes; |
1077 | uint32_t status; | |
5ed12a19 | 1078 | int try, clock = 0; |
0031fb96 | 1079 | bool has_aux_irq = HAS_AUX_IRQ(dev_priv); |
884f19e9 JN |
1080 | bool vdd; |
1081 | ||
4904fa66 VS |
1082 | ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp); |
1083 | for (i = 0; i < ARRAY_SIZE(ch_data); i++) | |
1084 | ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i); | |
1085 | ||
773538e8 | 1086 | pps_lock(intel_dp); |
e39b999a | 1087 | |
72c3500a VS |
1088 | /* |
1089 | * We will be called with VDD already enabled for dpcd/edid/oui reads. | |
1090 | * In such cases we want to leave VDD enabled and it's up to upper layers | |
1091 | * to turn it off. But for eg. i2c-dev access we need to turn it on/off | |
1092 | * ourselves. | |
1093 | */ | |
1e0560e0 | 1094 | vdd = edp_panel_vdd_on(intel_dp); |
b84a1cf8 RV |
1095 | |
1096 | /* dp aux is extremely sensitive to irq latency, hence request the | |
1097 | * lowest possible wakeup latency and so prevent the cpu from going into | |
1098 | * deep sleep states. | |
1099 | */ | |
1100 | pm_qos_update_request(&dev_priv->pm_qos, 0); | |
1101 | ||
1102 | intel_dp_check_edp(intel_dp); | |
5eb08b69 | 1103 | |
11bee43e JB |
1104 | /* Try to wait for any previous AUX channel activity */ |
1105 | for (try = 0; try < 3; try++) { | |
ef04f00d | 1106 | status = I915_READ_NOTRACE(ch_ctl); |
11bee43e JB |
1107 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
1108 | break; | |
1109 | msleep(1); | |
1110 | } | |
1111 | ||
1112 | if (try == 3) { | |
02196c77 MK |
1113 | static u32 last_status = -1; |
1114 | const u32 status = I915_READ(ch_ctl); | |
1115 | ||
1116 | if (status != last_status) { | |
1117 | WARN(1, "dp_aux_ch not started status 0x%08x\n", | |
1118 | status); | |
1119 | last_status = status; | |
1120 | } | |
1121 | ||
9ee32fea DV |
1122 | ret = -EBUSY; |
1123 | goto out; | |
4f7f7b7e CW |
1124 | } |
1125 | ||
46a5ae9f PZ |
1126 | /* Only 5 data registers! */ |
1127 | if (WARN_ON(send_bytes > 20 || recv_size > 20)) { | |
1128 | ret = -E2BIG; | |
1129 | goto out; | |
1130 | } | |
1131 | ||
ec5b01dd | 1132 | while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) { |
8159c796 VS |
1133 | u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp, |
1134 | has_aux_irq, | |
1135 | send_bytes, | |
1136 | aux_clock_divider); | |
1137 | ||
1138 | send_ctl |= aux_send_ctl_flags; | |
5ed12a19 | 1139 | |
bc86625a CW |
1140 | /* Must try at least 3 times according to DP spec */ |
1141 | for (try = 0; try < 5; try++) { | |
1142 | /* Load the send data into the aux channel data registers */ | |
1143 | for (i = 0; i < send_bytes; i += 4) | |
4904fa66 | 1144 | I915_WRITE(ch_data[i >> 2], |
a4f1289e RV |
1145 | intel_dp_pack_aux(send + i, |
1146 | send_bytes - i)); | |
bc86625a CW |
1147 | |
1148 | /* Send the command and wait for it to complete */ | |
5ed12a19 | 1149 | I915_WRITE(ch_ctl, send_ctl); |
bc86625a CW |
1150 | |
1151 | status = intel_dp_aux_wait_done(intel_dp, has_aux_irq); | |
1152 | ||
1153 | /* Clear done status and any errors */ | |
1154 | I915_WRITE(ch_ctl, | |
1155 | status | | |
1156 | DP_AUX_CH_CTL_DONE | | |
1157 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
1158 | DP_AUX_CH_CTL_RECEIVE_ERROR); | |
1159 | ||
74ebf294 TP |
1160 | /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2 |
1161 | * 400us delay required for errors and timeouts | |
1162 | * Timeout errors from the HW already meet this | |
1163 | * requirement so skip to next iteration | |
1164 | */ | |
3975f0aa DP |
1165 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) |
1166 | continue; | |
1167 | ||
74ebf294 TP |
1168 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
1169 | usleep_range(400, 500); | |
bc86625a | 1170 | continue; |
74ebf294 | 1171 | } |
bc86625a | 1172 | if (status & DP_AUX_CH_CTL_DONE) |
e058c945 | 1173 | goto done; |
bc86625a | 1174 | } |
a4fc5ed6 KP |
1175 | } |
1176 | ||
a4fc5ed6 | 1177 | if ((status & DP_AUX_CH_CTL_DONE) == 0) { |
1ae8c0a5 | 1178 | DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); |
9ee32fea DV |
1179 | ret = -EBUSY; |
1180 | goto out; | |
a4fc5ed6 KP |
1181 | } |
1182 | ||
e058c945 | 1183 | done: |
a4fc5ed6 KP |
1184 | /* Check for timeout or receive error. |
1185 | * Timeouts occur when the sink is not connected | |
1186 | */ | |
a5b3da54 | 1187 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
1ae8c0a5 | 1188 | DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); |
9ee32fea DV |
1189 | ret = -EIO; |
1190 | goto out; | |
a5b3da54 | 1191 | } |
1ae8c0a5 KP |
1192 | |
1193 | /* Timeouts occur when the device isn't connected, so they're | |
1194 | * "normal" -- don't fill the kernel log with these */ | |
a5b3da54 | 1195 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { |
a5570fe5 | 1196 | DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); |
9ee32fea DV |
1197 | ret = -ETIMEDOUT; |
1198 | goto out; | |
a4fc5ed6 KP |
1199 | } |
1200 | ||
1201 | /* Unload any bytes sent back from the other side */ | |
1202 | recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> | |
1203 | DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); | |
14e01889 RV |
1204 | |
1205 | /* | |
1206 | * By BSpec: "Message sizes of 0 or >20 are not allowed." | |
1207 | * We have no idea of what happened so we return -EBUSY so | |
1208 | * drm layer takes care for the necessary retries. | |
1209 | */ | |
1210 | if (recv_bytes == 0 || recv_bytes > 20) { | |
1211 | DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n", | |
1212 | recv_bytes); | |
14e01889 RV |
1213 | ret = -EBUSY; |
1214 | goto out; | |
1215 | } | |
1216 | ||
a4fc5ed6 KP |
1217 | if (recv_bytes > recv_size) |
1218 | recv_bytes = recv_size; | |
0206e353 | 1219 | |
4f7f7b7e | 1220 | for (i = 0; i < recv_bytes; i += 4) |
4904fa66 | 1221 | intel_dp_unpack_aux(I915_READ(ch_data[i >> 2]), |
a4f1289e | 1222 | recv + i, recv_bytes - i); |
a4fc5ed6 | 1223 | |
9ee32fea DV |
1224 | ret = recv_bytes; |
1225 | out: | |
1226 | pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE); | |
1227 | ||
884f19e9 JN |
1228 | if (vdd) |
1229 | edp_panel_vdd_off(intel_dp, false); | |
1230 | ||
773538e8 | 1231 | pps_unlock(intel_dp); |
e39b999a | 1232 | |
9ee32fea | 1233 | return ret; |
a4fc5ed6 KP |
1234 | } |
1235 | ||
a6c8aff0 JN |
1236 | #define BARE_ADDRESS_SIZE 3 |
1237 | #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) | |
32078b72 VS |
1238 | |
1239 | static void | |
1240 | intel_dp_aux_header(u8 txbuf[HEADER_SIZE], | |
1241 | const struct drm_dp_aux_msg *msg) | |
1242 | { | |
1243 | txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf); | |
1244 | txbuf[1] = (msg->address >> 8) & 0xff; | |
1245 | txbuf[2] = msg->address & 0xff; | |
1246 | txbuf[3] = msg->size - 1; | |
1247 | } | |
1248 | ||
9d1a1031 JN |
1249 | static ssize_t |
1250 | intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) | |
a4fc5ed6 | 1251 | { |
9d1a1031 JN |
1252 | struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux); |
1253 | uint8_t txbuf[20], rxbuf[20]; | |
1254 | size_t txsize, rxsize; | |
a4fc5ed6 | 1255 | int ret; |
a4fc5ed6 | 1256 | |
32078b72 | 1257 | intel_dp_aux_header(txbuf, msg); |
46a5ae9f | 1258 | |
9d1a1031 JN |
1259 | switch (msg->request & ~DP_AUX_I2C_MOT) { |
1260 | case DP_AUX_NATIVE_WRITE: | |
1261 | case DP_AUX_I2C_WRITE: | |
c1e74122 | 1262 | case DP_AUX_I2C_WRITE_STATUS_UPDATE: |
a6c8aff0 | 1263 | txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE; |
a1ddefd8 | 1264 | rxsize = 2; /* 0 or 1 data bytes */ |
f51a44b9 | 1265 | |
9d1a1031 JN |
1266 | if (WARN_ON(txsize > 20)) |
1267 | return -E2BIG; | |
a4fc5ed6 | 1268 | |
dd788090 VS |
1269 | WARN_ON(!msg->buffer != !msg->size); |
1270 | ||
d81a67cc ID |
1271 | if (msg->buffer) |
1272 | memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size); | |
a4fc5ed6 | 1273 | |
f7606265 | 1274 | ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize, |
8159c796 | 1275 | rxbuf, rxsize, 0); |
9d1a1031 JN |
1276 | if (ret > 0) { |
1277 | msg->reply = rxbuf[0] >> 4; | |
a4fc5ed6 | 1278 | |
a1ddefd8 JN |
1279 | if (ret > 1) { |
1280 | /* Number of bytes written in a short write. */ | |
1281 | ret = clamp_t(int, rxbuf[1], 0, msg->size); | |
1282 | } else { | |
1283 | /* Return payload size. */ | |
1284 | ret = msg->size; | |
1285 | } | |
9d1a1031 JN |
1286 | } |
1287 | break; | |
46a5ae9f | 1288 | |
9d1a1031 JN |
1289 | case DP_AUX_NATIVE_READ: |
1290 | case DP_AUX_I2C_READ: | |
a6c8aff0 | 1291 | txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE; |
9d1a1031 | 1292 | rxsize = msg->size + 1; |
a4fc5ed6 | 1293 | |
9d1a1031 JN |
1294 | if (WARN_ON(rxsize > 20)) |
1295 | return -E2BIG; | |
a4fc5ed6 | 1296 | |
f7606265 | 1297 | ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize, |
8159c796 | 1298 | rxbuf, rxsize, 0); |
9d1a1031 JN |
1299 | if (ret > 0) { |
1300 | msg->reply = rxbuf[0] >> 4; | |
1301 | /* | |
1302 | * Assume happy day, and copy the data. The caller is | |
1303 | * expected to check msg->reply before touching it. | |
1304 | * | |
1305 | * Return payload size. | |
1306 | */ | |
1307 | ret--; | |
1308 | memcpy(msg->buffer, rxbuf + 1, ret); | |
a4fc5ed6 | 1309 | } |
9d1a1031 JN |
1310 | break; |
1311 | ||
1312 | default: | |
1313 | ret = -EINVAL; | |
1314 | break; | |
a4fc5ed6 | 1315 | } |
f51a44b9 | 1316 | |
9d1a1031 | 1317 | return ret; |
a4fc5ed6 KP |
1318 | } |
1319 | ||
bdabdb63 | 1320 | static enum aux_ch intel_aux_ch(struct intel_dp *intel_dp) |
8f7ce038 | 1321 | { |
bdabdb63 VS |
1322 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; |
1323 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
1324 | enum port port = encoder->port; | |
8f7ce038 VS |
1325 | const struct ddi_vbt_port_info *info = |
1326 | &dev_priv->vbt.ddi_port_info[port]; | |
bdabdb63 | 1327 | enum aux_ch aux_ch; |
8f7ce038 VS |
1328 | |
1329 | if (!info->alternate_aux_channel) { | |
bdabdb63 VS |
1330 | aux_ch = (enum aux_ch) port; |
1331 | ||
8f7ce038 | 1332 | DRM_DEBUG_KMS("using AUX %c for port %c (platform default)\n", |
bdabdb63 VS |
1333 | aux_ch_name(aux_ch), port_name(port)); |
1334 | return aux_ch; | |
8f7ce038 VS |
1335 | } |
1336 | ||
1337 | switch (info->alternate_aux_channel) { | |
1338 | case DP_AUX_A: | |
bdabdb63 | 1339 | aux_ch = AUX_CH_A; |
8f7ce038 VS |
1340 | break; |
1341 | case DP_AUX_B: | |
bdabdb63 | 1342 | aux_ch = AUX_CH_B; |
8f7ce038 VS |
1343 | break; |
1344 | case DP_AUX_C: | |
bdabdb63 | 1345 | aux_ch = AUX_CH_C; |
8f7ce038 VS |
1346 | break; |
1347 | case DP_AUX_D: | |
bdabdb63 | 1348 | aux_ch = AUX_CH_D; |
8f7ce038 | 1349 | break; |
a324fcac | 1350 | case DP_AUX_F: |
bdabdb63 | 1351 | aux_ch = AUX_CH_F; |
a324fcac | 1352 | break; |
8f7ce038 VS |
1353 | default: |
1354 | MISSING_CASE(info->alternate_aux_channel); | |
bdabdb63 | 1355 | aux_ch = AUX_CH_A; |
8f7ce038 VS |
1356 | break; |
1357 | } | |
1358 | ||
1359 | DRM_DEBUG_KMS("using AUX %c for port %c (VBT)\n", | |
bdabdb63 | 1360 | aux_ch_name(aux_ch), port_name(port)); |
8f7ce038 | 1361 | |
bdabdb63 VS |
1362 | return aux_ch; |
1363 | } | |
1364 | ||
1365 | static enum intel_display_power_domain | |
1366 | intel_aux_power_domain(struct intel_dp *intel_dp) | |
1367 | { | |
1368 | switch (intel_dp->aux_ch) { | |
1369 | case AUX_CH_A: | |
1370 | return POWER_DOMAIN_AUX_A; | |
1371 | case AUX_CH_B: | |
1372 | return POWER_DOMAIN_AUX_B; | |
1373 | case AUX_CH_C: | |
1374 | return POWER_DOMAIN_AUX_C; | |
1375 | case AUX_CH_D: | |
1376 | return POWER_DOMAIN_AUX_D; | |
1377 | case AUX_CH_F: | |
1378 | return POWER_DOMAIN_AUX_F; | |
1379 | default: | |
1380 | MISSING_CASE(intel_dp->aux_ch); | |
1381 | return POWER_DOMAIN_AUX_A; | |
1382 | } | |
8f7ce038 VS |
1383 | } |
1384 | ||
4904fa66 | 1385 | static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp) |
da00bdcf | 1386 | { |
4904fa66 VS |
1387 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
1388 | enum aux_ch aux_ch = intel_dp->aux_ch; | |
1389 | ||
bdabdb63 VS |
1390 | switch (aux_ch) { |
1391 | case AUX_CH_B: | |
1392 | case AUX_CH_C: | |
1393 | case AUX_CH_D: | |
1394 | return DP_AUX_CH_CTL(aux_ch); | |
da00bdcf | 1395 | default: |
bdabdb63 VS |
1396 | MISSING_CASE(aux_ch); |
1397 | return DP_AUX_CH_CTL(AUX_CH_B); | |
da00bdcf VS |
1398 | } |
1399 | } | |
1400 | ||
4904fa66 | 1401 | static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index) |
330e20ec | 1402 | { |
4904fa66 VS |
1403 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
1404 | enum aux_ch aux_ch = intel_dp->aux_ch; | |
1405 | ||
bdabdb63 VS |
1406 | switch (aux_ch) { |
1407 | case AUX_CH_B: | |
1408 | case AUX_CH_C: | |
1409 | case AUX_CH_D: | |
1410 | return DP_AUX_CH_DATA(aux_ch, index); | |
330e20ec | 1411 | default: |
bdabdb63 VS |
1412 | MISSING_CASE(aux_ch); |
1413 | return DP_AUX_CH_DATA(AUX_CH_B, index); | |
330e20ec VS |
1414 | } |
1415 | } | |
1416 | ||
4904fa66 | 1417 | static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp) |
bdabdb63 | 1418 | { |
4904fa66 VS |
1419 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
1420 | enum aux_ch aux_ch = intel_dp->aux_ch; | |
1421 | ||
bdabdb63 VS |
1422 | switch (aux_ch) { |
1423 | case AUX_CH_A: | |
1424 | return DP_AUX_CH_CTL(aux_ch); | |
1425 | case AUX_CH_B: | |
1426 | case AUX_CH_C: | |
1427 | case AUX_CH_D: | |
1428 | return PCH_DP_AUX_CH_CTL(aux_ch); | |
da00bdcf | 1429 | default: |
bdabdb63 VS |
1430 | MISSING_CASE(aux_ch); |
1431 | return DP_AUX_CH_CTL(AUX_CH_A); | |
da00bdcf VS |
1432 | } |
1433 | } | |
1434 | ||
4904fa66 | 1435 | static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index) |
bdabdb63 | 1436 | { |
4904fa66 VS |
1437 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
1438 | enum aux_ch aux_ch = intel_dp->aux_ch; | |
1439 | ||
bdabdb63 VS |
1440 | switch (aux_ch) { |
1441 | case AUX_CH_A: | |
1442 | return DP_AUX_CH_DATA(aux_ch, index); | |
1443 | case AUX_CH_B: | |
1444 | case AUX_CH_C: | |
1445 | case AUX_CH_D: | |
1446 | return PCH_DP_AUX_CH_DATA(aux_ch, index); | |
330e20ec | 1447 | default: |
bdabdb63 VS |
1448 | MISSING_CASE(aux_ch); |
1449 | return DP_AUX_CH_DATA(AUX_CH_A, index); | |
330e20ec VS |
1450 | } |
1451 | } | |
1452 | ||
4904fa66 | 1453 | static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp) |
bdabdb63 | 1454 | { |
4904fa66 VS |
1455 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
1456 | enum aux_ch aux_ch = intel_dp->aux_ch; | |
1457 | ||
bdabdb63 VS |
1458 | switch (aux_ch) { |
1459 | case AUX_CH_A: | |
1460 | case AUX_CH_B: | |
1461 | case AUX_CH_C: | |
1462 | case AUX_CH_D: | |
1463 | case AUX_CH_F: | |
1464 | return DP_AUX_CH_CTL(aux_ch); | |
da00bdcf | 1465 | default: |
bdabdb63 VS |
1466 | MISSING_CASE(aux_ch); |
1467 | return DP_AUX_CH_CTL(AUX_CH_A); | |
da00bdcf VS |
1468 | } |
1469 | } | |
1470 | ||
4904fa66 | 1471 | static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index) |
bdabdb63 | 1472 | { |
4904fa66 VS |
1473 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
1474 | enum aux_ch aux_ch = intel_dp->aux_ch; | |
1475 | ||
bdabdb63 VS |
1476 | switch (aux_ch) { |
1477 | case AUX_CH_A: | |
1478 | case AUX_CH_B: | |
1479 | case AUX_CH_C: | |
1480 | case AUX_CH_D: | |
1481 | case AUX_CH_F: | |
1482 | return DP_AUX_CH_DATA(aux_ch, index); | |
330e20ec | 1483 | default: |
bdabdb63 VS |
1484 | MISSING_CASE(aux_ch); |
1485 | return DP_AUX_CH_DATA(AUX_CH_A, index); | |
330e20ec VS |
1486 | } |
1487 | } | |
1488 | ||
91e939ae VS |
1489 | static void |
1490 | intel_dp_aux_fini(struct intel_dp *intel_dp) | |
1491 | { | |
1492 | kfree(intel_dp->aux.name); | |
1493 | } | |
1494 | ||
1495 | static void | |
1496 | intel_dp_aux_init(struct intel_dp *intel_dp) | |
330e20ec VS |
1497 | { |
1498 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); | |
91e939ae VS |
1499 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; |
1500 | ||
1501 | intel_dp->aux_ch = intel_aux_ch(intel_dp); | |
1502 | intel_dp->aux_power_domain = intel_aux_power_domain(intel_dp); | |
330e20ec | 1503 | |
4904fa66 VS |
1504 | if (INTEL_GEN(dev_priv) >= 9) { |
1505 | intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg; | |
1506 | intel_dp->aux_ch_data_reg = skl_aux_data_reg; | |
1507 | } else if (HAS_PCH_SPLIT(dev_priv)) { | |
1508 | intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg; | |
1509 | intel_dp->aux_ch_data_reg = ilk_aux_data_reg; | |
1510 | } else { | |
1511 | intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg; | |
1512 | intel_dp->aux_ch_data_reg = g4x_aux_data_reg; | |
1513 | } | |
330e20ec | 1514 | |
91e939ae VS |
1515 | if (INTEL_GEN(dev_priv) >= 9) |
1516 | intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider; | |
1517 | else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) | |
1518 | intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; | |
1519 | else if (HAS_PCH_SPLIT(dev_priv)) | |
1520 | intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider; | |
1521 | else | |
1522 | intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider; | |
bdabdb63 | 1523 | |
91e939ae VS |
1524 | if (INTEL_GEN(dev_priv) >= 9) |
1525 | intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl; | |
1526 | else | |
1527 | intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl; | |
ab2c0672 | 1528 | |
7a418e34 | 1529 | drm_dp_aux_init(&intel_dp->aux); |
8316f337 | 1530 | |
7a418e34 | 1531 | /* Failure to allocate our preferred name is not critical */ |
bdabdb63 VS |
1532 | intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", |
1533 | port_name(encoder->port)); | |
9d1a1031 | 1534 | intel_dp->aux.transfer = intel_dp_aux_transfer; |
a4fc5ed6 KP |
1535 | } |
1536 | ||
e588fa18 | 1537 | bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp) |
ed63baaf | 1538 | { |
fc603ca7 | 1539 | int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1]; |
e588fa18 | 1540 | |
fc603ca7 | 1541 | return max_rate >= 540000; |
ed63baaf TS |
1542 | } |
1543 | ||
c6bb3538 DV |
1544 | static void |
1545 | intel_dp_set_clock(struct intel_encoder *encoder, | |
840b32b7 | 1546 | struct intel_crtc_state *pipe_config) |
c6bb3538 | 1547 | { |
2f773477 | 1548 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
9dd4ffdf CML |
1549 | const struct dp_link_dpll *divisor = NULL; |
1550 | int i, count = 0; | |
c6bb3538 | 1551 | |
9beb5fea | 1552 | if (IS_G4X(dev_priv)) { |
9dd4ffdf CML |
1553 | divisor = gen4_dpll; |
1554 | count = ARRAY_SIZE(gen4_dpll); | |
6e266956 | 1555 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
9dd4ffdf CML |
1556 | divisor = pch_dpll; |
1557 | count = ARRAY_SIZE(pch_dpll); | |
920a14b2 | 1558 | } else if (IS_CHERRYVIEW(dev_priv)) { |
ef9348c8 CML |
1559 | divisor = chv_dpll; |
1560 | count = ARRAY_SIZE(chv_dpll); | |
11a914c2 | 1561 | } else if (IS_VALLEYVIEW(dev_priv)) { |
65ce4bf5 CML |
1562 | divisor = vlv_dpll; |
1563 | count = ARRAY_SIZE(vlv_dpll); | |
c6bb3538 | 1564 | } |
9dd4ffdf CML |
1565 | |
1566 | if (divisor && count) { | |
1567 | for (i = 0; i < count; i++) { | |
840b32b7 | 1568 | if (pipe_config->port_clock == divisor[i].clock) { |
9dd4ffdf CML |
1569 | pipe_config->dpll = divisor[i].dpll; |
1570 | pipe_config->clock_set = true; | |
1571 | break; | |
1572 | } | |
1573 | } | |
c6bb3538 DV |
1574 | } |
1575 | } | |
1576 | ||
0336400e VS |
1577 | static void snprintf_int_array(char *str, size_t len, |
1578 | const int *array, int nelem) | |
1579 | { | |
1580 | int i; | |
1581 | ||
1582 | str[0] = '\0'; | |
1583 | ||
1584 | for (i = 0; i < nelem; i++) { | |
b2f505be | 1585 | int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]); |
0336400e VS |
1586 | if (r >= len) |
1587 | return; | |
1588 | str += r; | |
1589 | len -= r; | |
1590 | } | |
1591 | } | |
1592 | ||
1593 | static void intel_dp_print_rates(struct intel_dp *intel_dp) | |
1594 | { | |
0336400e VS |
1595 | char str[128]; /* FIXME: too big for stack? */ |
1596 | ||
1597 | if ((drm_debug & DRM_UT_KMS) == 0) | |
1598 | return; | |
1599 | ||
55cfc580 JN |
1600 | snprintf_int_array(str, sizeof(str), |
1601 | intel_dp->source_rates, intel_dp->num_source_rates); | |
0336400e VS |
1602 | DRM_DEBUG_KMS("source rates: %s\n", str); |
1603 | ||
68f357cb JN |
1604 | snprintf_int_array(str, sizeof(str), |
1605 | intel_dp->sink_rates, intel_dp->num_sink_rates); | |
0336400e VS |
1606 | DRM_DEBUG_KMS("sink rates: %s\n", str); |
1607 | ||
975ee5fc JN |
1608 | snprintf_int_array(str, sizeof(str), |
1609 | intel_dp->common_rates, intel_dp->num_common_rates); | |
94ca719e | 1610 | DRM_DEBUG_KMS("common rates: %s\n", str); |
0336400e VS |
1611 | } |
1612 | ||
50fec21a VS |
1613 | int |
1614 | intel_dp_max_link_rate(struct intel_dp *intel_dp) | |
1615 | { | |
50fec21a VS |
1616 | int len; |
1617 | ||
e6c0c64a | 1618 | len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate); |
50fec21a VS |
1619 | if (WARN_ON(len <= 0)) |
1620 | return 162000; | |
1621 | ||
975ee5fc | 1622 | return intel_dp->common_rates[len - 1]; |
50fec21a VS |
1623 | } |
1624 | ||
ed4e9c1d VS |
1625 | int intel_dp_rate_select(struct intel_dp *intel_dp, int rate) |
1626 | { | |
8001b754 JN |
1627 | int i = intel_dp_rate_index(intel_dp->sink_rates, |
1628 | intel_dp->num_sink_rates, rate); | |
b5c72b20 JN |
1629 | |
1630 | if (WARN_ON(i < 0)) | |
1631 | i = 0; | |
1632 | ||
1633 | return i; | |
ed4e9c1d VS |
1634 | } |
1635 | ||
94223d04 ACO |
1636 | void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, |
1637 | uint8_t *link_bw, uint8_t *rate_select) | |
04a60f9f | 1638 | { |
68f357cb JN |
1639 | /* eDP 1.4 rate select method. */ |
1640 | if (intel_dp->use_rate_select) { | |
04a60f9f VS |
1641 | *link_bw = 0; |
1642 | *rate_select = | |
1643 | intel_dp_rate_select(intel_dp, port_clock); | |
1644 | } else { | |
1645 | *link_bw = drm_dp_link_rate_to_bw_code(port_clock); | |
1646 | *rate_select = 0; | |
1647 | } | |
1648 | } | |
1649 | ||
7c2781e4 JN |
1650 | struct link_config_limits { |
1651 | int min_clock, max_clock; | |
1652 | int min_lane_count, max_lane_count; | |
1653 | int min_bpp, max_bpp; | |
1654 | }; | |
1655 | ||
f580bea9 JN |
1656 | static int intel_dp_compute_bpp(struct intel_dp *intel_dp, |
1657 | struct intel_crtc_state *pipe_config) | |
f9bb705e | 1658 | { |
ef32659a JN |
1659 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
1660 | struct intel_connector *intel_connector = intel_dp->attached_connector; | |
f9bb705e MK |
1661 | int bpp, bpc; |
1662 | ||
1663 | bpp = pipe_config->pipe_bpp; | |
1664 | bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports); | |
1665 | ||
1666 | if (bpc > 0) | |
1667 | bpp = min(bpp, 3*bpc); | |
1668 | ||
ef32659a JN |
1669 | if (intel_dp_is_edp(intel_dp)) { |
1670 | /* Get bpp from vbt only for panels that dont have bpp in edid */ | |
1671 | if (intel_connector->base.display_info.bpc == 0 && | |
1672 | dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp) { | |
1673 | DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", | |
1674 | dev_priv->vbt.edp.bpp); | |
1675 | bpp = dev_priv->vbt.edp.bpp; | |
1676 | } | |
1677 | } | |
1678 | ||
f9bb705e MK |
1679 | return bpp; |
1680 | } | |
1681 | ||
dc911f5b JB |
1682 | static bool intel_edp_compare_alt_mode(struct drm_display_mode *m1, |
1683 | struct drm_display_mode *m2) | |
1684 | { | |
1685 | bool bres = false; | |
1686 | ||
1687 | if (m1 && m2) | |
1688 | bres = (m1->hdisplay == m2->hdisplay && | |
1689 | m1->hsync_start == m2->hsync_start && | |
1690 | m1->hsync_end == m2->hsync_end && | |
1691 | m1->htotal == m2->htotal && | |
1692 | m1->vdisplay == m2->vdisplay && | |
1693 | m1->vsync_start == m2->vsync_start && | |
1694 | m1->vsync_end == m2->vsync_end && | |
1695 | m1->vtotal == m2->vtotal); | |
1696 | return bres; | |
1697 | } | |
1698 | ||
a4971453 JN |
1699 | /* Adjust link config limits based on compliance test requests. */ |
1700 | static void | |
1701 | intel_dp_adjust_compliance_config(struct intel_dp *intel_dp, | |
1702 | struct intel_crtc_state *pipe_config, | |
1703 | struct link_config_limits *limits) | |
1704 | { | |
1705 | /* For DP Compliance we override the computed bpp for the pipe */ | |
1706 | if (intel_dp->compliance.test_data.bpc != 0) { | |
1707 | int bpp = 3 * intel_dp->compliance.test_data.bpc; | |
1708 | ||
1709 | limits->min_bpp = limits->max_bpp = bpp; | |
1710 | pipe_config->dither_force_disable = bpp == 6 * 3; | |
1711 | ||
1712 | DRM_DEBUG_KMS("Setting pipe_bpp to %d\n", bpp); | |
1713 | } | |
1714 | ||
1715 | /* Use values requested by Compliance Test Request */ | |
1716 | if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) { | |
1717 | int index; | |
1718 | ||
1719 | /* Validate the compliance test data since max values | |
1720 | * might have changed due to link train fallback. | |
1721 | */ | |
1722 | if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate, | |
1723 | intel_dp->compliance.test_lane_count)) { | |
1724 | index = intel_dp_rate_index(intel_dp->common_rates, | |
1725 | intel_dp->num_common_rates, | |
1726 | intel_dp->compliance.test_link_rate); | |
1727 | if (index >= 0) | |
1728 | limits->min_clock = limits->max_clock = index; | |
1729 | limits->min_lane_count = limits->max_lane_count = | |
1730 | intel_dp->compliance.test_lane_count; | |
1731 | } | |
1732 | } | |
1733 | } | |
1734 | ||
3acd115d JN |
1735 | /* Optimize link config in order: max bpp, min clock, min lanes */ |
1736 | static bool | |
1737 | intel_dp_compute_link_config_wide(struct intel_dp *intel_dp, | |
1738 | struct intel_crtc_state *pipe_config, | |
1739 | const struct link_config_limits *limits) | |
1740 | { | |
1741 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; | |
1742 | int bpp, clock, lane_count; | |
1743 | int mode_rate, link_clock, link_avail; | |
1744 | ||
1745 | for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) { | |
1746 | mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, | |
1747 | bpp); | |
1748 | ||
1749 | for (clock = limits->min_clock; clock <= limits->max_clock; clock++) { | |
1750 | for (lane_count = limits->min_lane_count; | |
1751 | lane_count <= limits->max_lane_count; | |
1752 | lane_count <<= 1) { | |
1753 | link_clock = intel_dp->common_rates[clock]; | |
1754 | link_avail = intel_dp_max_data_rate(link_clock, | |
1755 | lane_count); | |
1756 | ||
1757 | if (mode_rate <= link_avail) { | |
1758 | pipe_config->lane_count = lane_count; | |
1759 | pipe_config->pipe_bpp = bpp; | |
1760 | pipe_config->port_clock = link_clock; | |
1761 | ||
1762 | return true; | |
1763 | } | |
1764 | } | |
1765 | } | |
1766 | } | |
1767 | ||
1768 | return false; | |
1769 | } | |
1770 | ||
981a63eb JN |
1771 | static bool |
1772 | intel_dp_compute_link_config(struct intel_encoder *encoder, | |
1773 | struct intel_crtc_state *pipe_config) | |
a4fc5ed6 | 1774 | { |
2d112de7 | 1775 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
5bfe2ac0 | 1776 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
7c2781e4 | 1777 | struct link_config_limits limits; |
94ca719e | 1778 | int common_len; |
7c2781e4 | 1779 | |
975ee5fc | 1780 | common_len = intel_dp_common_len_rate_limit(intel_dp, |
e6c0c64a | 1781 | intel_dp->max_link_rate); |
a8f3ef61 SJ |
1782 | |
1783 | /* No common link rates between source and sink */ | |
94ca719e | 1784 | WARN_ON(common_len <= 0); |
a8f3ef61 | 1785 | |
7c2781e4 JN |
1786 | limits.min_clock = 0; |
1787 | limits.max_clock = common_len - 1; | |
1788 | ||
1789 | limits.min_lane_count = 1; | |
1790 | limits.max_lane_count = intel_dp_max_lane_count(intel_dp); | |
1791 | ||
1792 | limits.min_bpp = 6 * 3; | |
1793 | limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config); | |
a4fc5ed6 | 1794 | |
1853a9da | 1795 | if (intel_dp_is_edp(intel_dp)) { |
344c5bbc JN |
1796 | /* |
1797 | * Use the maximum clock and number of lanes the eDP panel | |
1798 | * advertizes being capable of. The panels are generally | |
1799 | * designed to support only a single clock and lane | |
1800 | * configuration, and typically these values correspond to the | |
1801 | * native resolution of the panel. | |
1802 | */ | |
7c2781e4 JN |
1803 | limits.min_lane_count = limits.max_lane_count; |
1804 | limits.min_clock = limits.max_clock; | |
7984211e | 1805 | } |
657445fe | 1806 | |
a4971453 JN |
1807 | intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits); |
1808 | ||
7c2781e4 JN |
1809 | DRM_DEBUG_KMS("DP link computation with max lane count %i " |
1810 | "max rate %d max bpp %d pixel clock %iKHz\n", | |
1811 | limits.max_lane_count, | |
1812 | intel_dp->common_rates[limits.max_clock], | |
1813 | limits.max_bpp, adjusted_mode->crtc_clock); | |
1814 | ||
3acd115d JN |
1815 | /* |
1816 | * Optimize for slow and wide. This is the place to add alternative | |
1817 | * optimization policy. | |
1818 | */ | |
1819 | if (!intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits)) | |
1820 | return false; | |
981a63eb JN |
1821 | |
1822 | DRM_DEBUG_KMS("DP lane count %d clock %d bpp %d\n", | |
3acd115d JN |
1823 | pipe_config->lane_count, pipe_config->port_clock, |
1824 | pipe_config->pipe_bpp); | |
1825 | ||
1826 | DRM_DEBUG_KMS("DP link rate required %i available %i\n", | |
1827 | intel_dp_link_required(adjusted_mode->crtc_clock, | |
1828 | pipe_config->pipe_bpp), | |
1829 | intel_dp_max_data_rate(pipe_config->port_clock, | |
1830 | pipe_config->lane_count)); | |
981a63eb JN |
1831 | |
1832 | return true; | |
1833 | } | |
1834 | ||
1835 | bool | |
1836 | intel_dp_compute_config(struct intel_encoder *encoder, | |
1837 | struct intel_crtc_state *pipe_config, | |
1838 | struct drm_connector_state *conn_state) | |
1839 | { | |
1840 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
1841 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; | |
1842 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
1843 | enum port port = encoder->port; | |
1844 | struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); | |
1845 | struct intel_connector *intel_connector = intel_dp->attached_connector; | |
1846 | struct intel_digital_connector_state *intel_conn_state = | |
1847 | to_intel_digital_connector_state(conn_state); | |
1848 | bool reduce_m_n = drm_dp_has_quirk(&intel_dp->desc, | |
1849 | DP_DPCD_QUIRK_LIMITED_M_N); | |
1850 | ||
1851 | if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A) | |
1852 | pipe_config->has_pch_encoder = true; | |
1853 | ||
1854 | pipe_config->has_drrs = false; | |
1855 | if (IS_G4X(dev_priv) || port == PORT_A) | |
1856 | pipe_config->has_audio = false; | |
1857 | else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) | |
1858 | pipe_config->has_audio = intel_dp->has_audio; | |
1859 | else | |
1860 | pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON; | |
1861 | ||
1862 | if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) { | |
1863 | struct drm_display_mode *panel_mode = | |
1864 | intel_connector->panel.alt_fixed_mode; | |
1865 | struct drm_display_mode *req_mode = &pipe_config->base.mode; | |
1866 | ||
1867 | if (!intel_edp_compare_alt_mode(req_mode, panel_mode)) | |
1868 | panel_mode = intel_connector->panel.fixed_mode; | |
1869 | ||
1870 | drm_mode_debug_printmodeline(panel_mode); | |
1871 | ||
1872 | intel_fixed_panel_mode(panel_mode, adjusted_mode); | |
1873 | ||
1874 | if (INTEL_GEN(dev_priv) >= 9) { | |
1875 | int ret; | |
1876 | ||
1877 | ret = skl_update_scaler_crtc(pipe_config); | |
1878 | if (ret) | |
1879 | return ret; | |
1880 | } | |
1881 | ||
1882 | if (HAS_GMCH_DISPLAY(dev_priv)) | |
1883 | intel_gmch_panel_fitting(intel_crtc, pipe_config, | |
1884 | conn_state->scaling_mode); | |
1885 | else | |
1886 | intel_pch_panel_fitting(intel_crtc, pipe_config, | |
1887 | conn_state->scaling_mode); | |
1888 | } | |
1889 | ||
1890 | if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && | |
1891 | adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) | |
1892 | return false; | |
1893 | ||
1894 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) | |
1895 | return false; | |
1896 | ||
1897 | if (!intel_dp_compute_link_config(encoder, pipe_config)) | |
1898 | return false; | |
1899 | ||
8f647a01 | 1900 | if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) { |
55bc60db VS |
1901 | /* |
1902 | * See: | |
1903 | * CEA-861-E - 5.1 Default Encoding Parameters | |
1904 | * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry | |
1905 | */ | |
0f2a2a75 | 1906 | pipe_config->limited_color_range = |
981a63eb | 1907 | pipe_config->pipe_bpp != 18 && |
c8127cf0 VS |
1908 | drm_default_rgb_quant_range(adjusted_mode) == |
1909 | HDMI_QUANTIZATION_RANGE_LIMITED; | |
0f2a2a75 VS |
1910 | } else { |
1911 | pipe_config->limited_color_range = | |
8f647a01 | 1912 | intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED; |
55bc60db VS |
1913 | } |
1914 | ||
981a63eb | 1915 | intel_link_compute_m_n(pipe_config->pipe_bpp, pipe_config->lane_count, |
241bfc38 DL |
1916 | adjusted_mode->crtc_clock, |
1917 | pipe_config->port_clock, | |
b31e85ed JN |
1918 | &pipe_config->dp_m_n, |
1919 | reduce_m_n); | |
9d1a455b | 1920 | |
439d7ac0 | 1921 | if (intel_connector->panel.downclock_mode != NULL && |
96178eeb | 1922 | dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) { |
f769cd24 | 1923 | pipe_config->has_drrs = true; |
981a63eb JN |
1924 | intel_link_compute_m_n(pipe_config->pipe_bpp, |
1925 | pipe_config->lane_count, | |
1926 | intel_connector->panel.downclock_mode->clock, | |
1927 | pipe_config->port_clock, | |
1928 | &pipe_config->dp_m2_n2, | |
1929 | reduce_m_n); | |
439d7ac0 PB |
1930 | } |
1931 | ||
4f8036a2 | 1932 | if (!HAS_DDI(dev_priv)) |
840b32b7 | 1933 | intel_dp_set_clock(encoder, pipe_config); |
c6bb3538 | 1934 | |
4d90f2d5 VS |
1935 | intel_psr_compute_config(intel_dp, pipe_config); |
1936 | ||
03afc4a2 | 1937 | return true; |
a4fc5ed6 KP |
1938 | } |
1939 | ||
901c2daf | 1940 | void intel_dp_set_link_params(struct intel_dp *intel_dp, |
dfa10480 ACO |
1941 | int link_rate, uint8_t lane_count, |
1942 | bool link_mst) | |
901c2daf | 1943 | { |
edb2e530 | 1944 | intel_dp->link_trained = false; |
dfa10480 ACO |
1945 | intel_dp->link_rate = link_rate; |
1946 | intel_dp->lane_count = lane_count; | |
1947 | intel_dp->link_mst = link_mst; | |
901c2daf VS |
1948 | } |
1949 | ||
85cb48a1 | 1950 | static void intel_dp_prepare(struct intel_encoder *encoder, |
5f88a9c6 | 1951 | const struct intel_crtc_state *pipe_config) |
a4fc5ed6 | 1952 | { |
2f773477 | 1953 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
b934223d | 1954 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
8f4f2797 | 1955 | enum port port = encoder->port; |
adc10304 | 1956 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); |
85cb48a1 | 1957 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
a4fc5ed6 | 1958 | |
dfa10480 ACO |
1959 | intel_dp_set_link_params(intel_dp, pipe_config->port_clock, |
1960 | pipe_config->lane_count, | |
1961 | intel_crtc_has_type(pipe_config, | |
1962 | INTEL_OUTPUT_DP_MST)); | |
901c2daf | 1963 | |
417e822d | 1964 | /* |
1a2eb460 | 1965 | * There are four kinds of DP registers: |
417e822d KP |
1966 | * |
1967 | * IBX PCH | |
1a2eb460 KP |
1968 | * SNB CPU |
1969 | * IVB CPU | |
417e822d KP |
1970 | * CPT PCH |
1971 | * | |
1972 | * IBX PCH and CPU are the same for almost everything, | |
1973 | * except that the CPU DP PLL is configured in this | |
1974 | * register | |
1975 | * | |
1976 | * CPT PCH is quite different, having many bits moved | |
1977 | * to the TRANS_DP_CTL register instead. That | |
1978 | * configuration happens (oddly) in ironlake_pch_enable | |
1979 | */ | |
9c9e7927 | 1980 | |
417e822d KP |
1981 | /* Preserve the BIOS-computed detected bit. This is |
1982 | * supposed to be read-only. | |
1983 | */ | |
1984 | intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; | |
a4fc5ed6 | 1985 | |
417e822d | 1986 | /* Handle DP bits in common between all three register formats */ |
417e822d | 1987 | intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
85cb48a1 | 1988 | intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count); |
a4fc5ed6 | 1989 | |
417e822d | 1990 | /* Split out the IBX/CPU vs CPT settings */ |
32f9d658 | 1991 | |
5db94019 | 1992 | if (IS_GEN7(dev_priv) && port == PORT_A) { |
1a2eb460 KP |
1993 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
1994 | intel_dp->DP |= DP_SYNC_HS_HIGH; | |
1995 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
1996 | intel_dp->DP |= DP_SYNC_VS_HIGH; | |
1997 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; | |
1998 | ||
6aba5b6c | 1999 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
1a2eb460 KP |
2000 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
2001 | ||
7c62a164 | 2002 | intel_dp->DP |= crtc->pipe << 29; |
6e266956 | 2003 | } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) { |
e3ef4479 VS |
2004 | u32 trans_dp; |
2005 | ||
39e5fa88 | 2006 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
e3ef4479 VS |
2007 | |
2008 | trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe)); | |
2009 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) | |
2010 | trans_dp |= TRANS_DP_ENH_FRAMING; | |
2011 | else | |
2012 | trans_dp &= ~TRANS_DP_ENH_FRAMING; | |
2013 | I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp); | |
39e5fa88 | 2014 | } else { |
c99f53f7 | 2015 | if (IS_G4X(dev_priv) && pipe_config->limited_color_range) |
0f2a2a75 | 2016 | intel_dp->DP |= DP_COLOR_RANGE_16_235; |
417e822d KP |
2017 | |
2018 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
2019 | intel_dp->DP |= DP_SYNC_HS_HIGH; | |
2020 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
2021 | intel_dp->DP |= DP_SYNC_VS_HIGH; | |
2022 | intel_dp->DP |= DP_LINK_TRAIN_OFF; | |
2023 | ||
6aba5b6c | 2024 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
417e822d KP |
2025 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
2026 | ||
920a14b2 | 2027 | if (IS_CHERRYVIEW(dev_priv)) |
44f37d1f | 2028 | intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe); |
39e5fa88 VS |
2029 | else if (crtc->pipe == PIPE_B) |
2030 | intel_dp->DP |= DP_PIPEB_SELECT; | |
32f9d658 | 2031 | } |
a4fc5ed6 KP |
2032 | } |
2033 | ||
ffd6749d PZ |
2034 | #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) |
2035 | #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) | |
99ea7127 | 2036 | |
1a5ef5b7 PZ |
2037 | #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0) |
2038 | #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0) | |
99ea7127 | 2039 | |
ffd6749d PZ |
2040 | #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) |
2041 | #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) | |
99ea7127 | 2042 | |
46bd8383 | 2043 | static void intel_pps_verify_state(struct intel_dp *intel_dp); |
de9c1b6b | 2044 | |
4be73780 | 2045 | static void wait_panel_status(struct intel_dp *intel_dp, |
99ea7127 KP |
2046 | u32 mask, |
2047 | u32 value) | |
bd943159 | 2048 | { |
2f773477 | 2049 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
f0f59a00 | 2050 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
453c5420 | 2051 | |
e39b999a VS |
2052 | lockdep_assert_held(&dev_priv->pps_mutex); |
2053 | ||
46bd8383 | 2054 | intel_pps_verify_state(intel_dp); |
de9c1b6b | 2055 | |
bf13e81b JN |
2056 | pp_stat_reg = _pp_stat_reg(intel_dp); |
2057 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); | |
32ce697c | 2058 | |
99ea7127 | 2059 | DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", |
453c5420 JB |
2060 | mask, value, |
2061 | I915_READ(pp_stat_reg), | |
2062 | I915_READ(pp_ctrl_reg)); | |
32ce697c | 2063 | |
9036ff06 CW |
2064 | if (intel_wait_for_register(dev_priv, |
2065 | pp_stat_reg, mask, value, | |
2066 | 5000)) | |
99ea7127 | 2067 | DRM_ERROR("Panel status timeout: status %08x control %08x\n", |
453c5420 JB |
2068 | I915_READ(pp_stat_reg), |
2069 | I915_READ(pp_ctrl_reg)); | |
54c136d4 CW |
2070 | |
2071 | DRM_DEBUG_KMS("Wait complete\n"); | |
99ea7127 | 2072 | } |
32ce697c | 2073 | |
4be73780 | 2074 | static void wait_panel_on(struct intel_dp *intel_dp) |
99ea7127 KP |
2075 | { |
2076 | DRM_DEBUG_KMS("Wait for panel power on\n"); | |
4be73780 | 2077 | wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); |
bd943159 KP |
2078 | } |
2079 | ||
4be73780 | 2080 | static void wait_panel_off(struct intel_dp *intel_dp) |
99ea7127 KP |
2081 | { |
2082 | DRM_DEBUG_KMS("Wait for panel power off time\n"); | |
4be73780 | 2083 | wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); |
99ea7127 KP |
2084 | } |
2085 | ||
4be73780 | 2086 | static void wait_panel_power_cycle(struct intel_dp *intel_dp) |
99ea7127 | 2087 | { |
d28d4731 AK |
2088 | ktime_t panel_power_on_time; |
2089 | s64 panel_power_off_duration; | |
2090 | ||
99ea7127 | 2091 | DRM_DEBUG_KMS("Wait for panel power cycle\n"); |
dce56b3c | 2092 | |
d28d4731 AK |
2093 | /* take the difference of currrent time and panel power off time |
2094 | * and then make panel wait for t11_t12 if needed. */ | |
2095 | panel_power_on_time = ktime_get_boottime(); | |
2096 | panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time); | |
2097 | ||
dce56b3c PZ |
2098 | /* When we disable the VDD override bit last we have to do the manual |
2099 | * wait. */ | |
d28d4731 AK |
2100 | if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay) |
2101 | wait_remaining_ms_from_jiffies(jiffies, | |
2102 | intel_dp->panel_power_cycle_delay - panel_power_off_duration); | |
dce56b3c | 2103 | |
4be73780 | 2104 | wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); |
99ea7127 KP |
2105 | } |
2106 | ||
4be73780 | 2107 | static void wait_backlight_on(struct intel_dp *intel_dp) |
dce56b3c PZ |
2108 | { |
2109 | wait_remaining_ms_from_jiffies(intel_dp->last_power_on, | |
2110 | intel_dp->backlight_on_delay); | |
2111 | } | |
2112 | ||
4be73780 | 2113 | static void edp_wait_backlight_off(struct intel_dp *intel_dp) |
dce56b3c PZ |
2114 | { |
2115 | wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off, | |
2116 | intel_dp->backlight_off_delay); | |
2117 | } | |
99ea7127 | 2118 | |
832dd3c1 KP |
2119 | /* Read the current pp_control value, unlocking the register if it |
2120 | * is locked | |
2121 | */ | |
2122 | ||
453c5420 | 2123 | static u32 ironlake_get_pp_control(struct intel_dp *intel_dp) |
832dd3c1 | 2124 | { |
2f773477 | 2125 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
453c5420 | 2126 | u32 control; |
832dd3c1 | 2127 | |
e39b999a VS |
2128 | lockdep_assert_held(&dev_priv->pps_mutex); |
2129 | ||
bf13e81b | 2130 | control = I915_READ(_pp_ctrl_reg(intel_dp)); |
8090ba8c ID |
2131 | if (WARN_ON(!HAS_DDI(dev_priv) && |
2132 | (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) { | |
b0a08bec VK |
2133 | control &= ~PANEL_UNLOCK_MASK; |
2134 | control |= PANEL_UNLOCK_REGS; | |
2135 | } | |
832dd3c1 | 2136 | return control; |
bd943159 KP |
2137 | } |
2138 | ||
951468f3 VS |
2139 | /* |
2140 | * Must be paired with edp_panel_vdd_off(). | |
2141 | * Must hold pps_mutex around the whole on/off sequence. | |
2142 | * Can be nested with intel_edp_panel_vdd_{on,off}() calls. | |
2143 | */ | |
1e0560e0 | 2144 | static bool edp_panel_vdd_on(struct intel_dp *intel_dp) |
5d613501 | 2145 | { |
2f773477 | 2146 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
4e6e1a54 | 2147 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
5d613501 | 2148 | u32 pp; |
f0f59a00 | 2149 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
adddaaf4 | 2150 | bool need_to_disable = !intel_dp->want_panel_vdd; |
5d613501 | 2151 | |
e39b999a VS |
2152 | lockdep_assert_held(&dev_priv->pps_mutex); |
2153 | ||
1853a9da | 2154 | if (!intel_dp_is_edp(intel_dp)) |
adddaaf4 | 2155 | return false; |
bd943159 | 2156 | |
2c623c11 | 2157 | cancel_delayed_work(&intel_dp->panel_vdd_work); |
bd943159 | 2158 | intel_dp->want_panel_vdd = true; |
99ea7127 | 2159 | |
4be73780 | 2160 | if (edp_have_panel_vdd(intel_dp)) |
adddaaf4 | 2161 | return need_to_disable; |
b0665d57 | 2162 | |
5432fcaf | 2163 | intel_display_power_get(dev_priv, intel_dp->aux_power_domain); |
e9cb81a2 | 2164 | |
3936fcf4 | 2165 | DRM_DEBUG_KMS("Turning eDP port %c VDD on\n", |
8f4f2797 | 2166 | port_name(intel_dig_port->base.port)); |
bd943159 | 2167 | |
4be73780 DV |
2168 | if (!edp_have_panel_power(intel_dp)) |
2169 | wait_panel_power_cycle(intel_dp); | |
99ea7127 | 2170 | |
453c5420 | 2171 | pp = ironlake_get_pp_control(intel_dp); |
5d613501 | 2172 | pp |= EDP_FORCE_VDD; |
ebf33b18 | 2173 | |
bf13e81b JN |
2174 | pp_stat_reg = _pp_stat_reg(intel_dp); |
2175 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); | |
453c5420 JB |
2176 | |
2177 | I915_WRITE(pp_ctrl_reg, pp); | |
2178 | POSTING_READ(pp_ctrl_reg); | |
2179 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", | |
2180 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); | |
ebf33b18 KP |
2181 | /* |
2182 | * If the panel wasn't on, delay before accessing aux channel | |
2183 | */ | |
4be73780 | 2184 | if (!edp_have_panel_power(intel_dp)) { |
3936fcf4 | 2185 | DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n", |
8f4f2797 | 2186 | port_name(intel_dig_port->base.port)); |
f01eca2e | 2187 | msleep(intel_dp->panel_power_up_delay); |
f01eca2e | 2188 | } |
adddaaf4 JN |
2189 | |
2190 | return need_to_disable; | |
2191 | } | |
2192 | ||
951468f3 VS |
2193 | /* |
2194 | * Must be paired with intel_edp_panel_vdd_off() or | |
2195 | * intel_edp_panel_off(). | |
2196 | * Nested calls to these functions are not allowed since | |
2197 | * we drop the lock. Caller must use some higher level | |
2198 | * locking to prevent nested calls from other threads. | |
2199 | */ | |
b80d6c78 | 2200 | void intel_edp_panel_vdd_on(struct intel_dp *intel_dp) |
adddaaf4 | 2201 | { |
c695b6b6 | 2202 | bool vdd; |
adddaaf4 | 2203 | |
1853a9da | 2204 | if (!intel_dp_is_edp(intel_dp)) |
c695b6b6 VS |
2205 | return; |
2206 | ||
773538e8 | 2207 | pps_lock(intel_dp); |
c695b6b6 | 2208 | vdd = edp_panel_vdd_on(intel_dp); |
773538e8 | 2209 | pps_unlock(intel_dp); |
c695b6b6 | 2210 | |
e2c719b7 | 2211 | I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n", |
8f4f2797 | 2212 | port_name(dp_to_dig_port(intel_dp)->base.port)); |
5d613501 JB |
2213 | } |
2214 | ||
4be73780 | 2215 | static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) |
5d613501 | 2216 | { |
2f773477 | 2217 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
be2c9196 VS |
2218 | struct intel_digital_port *intel_dig_port = |
2219 | dp_to_dig_port(intel_dp); | |
5d613501 | 2220 | u32 pp; |
f0f59a00 | 2221 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
5d613501 | 2222 | |
e39b999a | 2223 | lockdep_assert_held(&dev_priv->pps_mutex); |
a0e99e68 | 2224 | |
15e899a0 | 2225 | WARN_ON(intel_dp->want_panel_vdd); |
4e6e1a54 | 2226 | |
15e899a0 | 2227 | if (!edp_have_panel_vdd(intel_dp)) |
be2c9196 | 2228 | return; |
b0665d57 | 2229 | |
3936fcf4 | 2230 | DRM_DEBUG_KMS("Turning eDP port %c VDD off\n", |
8f4f2797 | 2231 | port_name(intel_dig_port->base.port)); |
bd943159 | 2232 | |
be2c9196 VS |
2233 | pp = ironlake_get_pp_control(intel_dp); |
2234 | pp &= ~EDP_FORCE_VDD; | |
453c5420 | 2235 | |
be2c9196 VS |
2236 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
2237 | pp_stat_reg = _pp_stat_reg(intel_dp); | |
99ea7127 | 2238 | |
be2c9196 VS |
2239 | I915_WRITE(pp_ctrl_reg, pp); |
2240 | POSTING_READ(pp_ctrl_reg); | |
90791a5c | 2241 | |
be2c9196 VS |
2242 | /* Make sure sequencer is idle before allowing subsequent activity */ |
2243 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", | |
2244 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); | |
e9cb81a2 | 2245 | |
5a162e22 | 2246 | if ((pp & PANEL_POWER_ON) == 0) |
d28d4731 | 2247 | intel_dp->panel_power_off_time = ktime_get_boottime(); |
e9cb81a2 | 2248 | |
5432fcaf | 2249 | intel_display_power_put(dev_priv, intel_dp->aux_power_domain); |
bd943159 | 2250 | } |
5d613501 | 2251 | |
4be73780 | 2252 | static void edp_panel_vdd_work(struct work_struct *__work) |
bd943159 KP |
2253 | { |
2254 | struct intel_dp *intel_dp = container_of(to_delayed_work(__work), | |
2255 | struct intel_dp, panel_vdd_work); | |
bd943159 | 2256 | |
773538e8 | 2257 | pps_lock(intel_dp); |
15e899a0 VS |
2258 | if (!intel_dp->want_panel_vdd) |
2259 | edp_panel_vdd_off_sync(intel_dp); | |
773538e8 | 2260 | pps_unlock(intel_dp); |
bd943159 KP |
2261 | } |
2262 | ||
aba86890 ID |
2263 | static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp) |
2264 | { | |
2265 | unsigned long delay; | |
2266 | ||
2267 | /* | |
2268 | * Queue the timer to fire a long time from now (relative to the power | |
2269 | * down delay) to keep the panel power up across a sequence of | |
2270 | * operations. | |
2271 | */ | |
2272 | delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5); | |
2273 | schedule_delayed_work(&intel_dp->panel_vdd_work, delay); | |
2274 | } | |
2275 | ||
951468f3 VS |
2276 | /* |
2277 | * Must be paired with edp_panel_vdd_on(). | |
2278 | * Must hold pps_mutex around the whole on/off sequence. | |
2279 | * Can be nested with intel_edp_panel_vdd_{on,off}() calls. | |
2280 | */ | |
4be73780 | 2281 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) |
bd943159 | 2282 | { |
fac5e23e | 2283 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
e39b999a VS |
2284 | |
2285 | lockdep_assert_held(&dev_priv->pps_mutex); | |
2286 | ||
1853a9da | 2287 | if (!intel_dp_is_edp(intel_dp)) |
97af61f5 | 2288 | return; |
5d613501 | 2289 | |
e2c719b7 | 2290 | I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on", |
8f4f2797 | 2291 | port_name(dp_to_dig_port(intel_dp)->base.port)); |
f2e8b18a | 2292 | |
bd943159 KP |
2293 | intel_dp->want_panel_vdd = false; |
2294 | ||
aba86890 | 2295 | if (sync) |
4be73780 | 2296 | edp_panel_vdd_off_sync(intel_dp); |
aba86890 ID |
2297 | else |
2298 | edp_panel_vdd_schedule_off(intel_dp); | |
5d613501 JB |
2299 | } |
2300 | ||
9f0fb5be | 2301 | static void edp_panel_on(struct intel_dp *intel_dp) |
9934c132 | 2302 | { |
2f773477 | 2303 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
99ea7127 | 2304 | u32 pp; |
f0f59a00 | 2305 | i915_reg_t pp_ctrl_reg; |
9934c132 | 2306 | |
9f0fb5be VS |
2307 | lockdep_assert_held(&dev_priv->pps_mutex); |
2308 | ||
1853a9da | 2309 | if (!intel_dp_is_edp(intel_dp)) |
bd943159 | 2310 | return; |
99ea7127 | 2311 | |
3936fcf4 | 2312 | DRM_DEBUG_KMS("Turn eDP port %c panel power on\n", |
8f4f2797 | 2313 | port_name(dp_to_dig_port(intel_dp)->base.port)); |
e39b999a | 2314 | |
e7a89ace VS |
2315 | if (WARN(edp_have_panel_power(intel_dp), |
2316 | "eDP port %c panel power already on\n", | |
8f4f2797 | 2317 | port_name(dp_to_dig_port(intel_dp)->base.port))) |
9f0fb5be | 2318 | return; |
9934c132 | 2319 | |
4be73780 | 2320 | wait_panel_power_cycle(intel_dp); |
37c6c9b0 | 2321 | |
bf13e81b | 2322 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 | 2323 | pp = ironlake_get_pp_control(intel_dp); |
5db94019 | 2324 | if (IS_GEN5(dev_priv)) { |
05ce1a49 KP |
2325 | /* ILK workaround: disable reset around power sequence */ |
2326 | pp &= ~PANEL_POWER_RESET; | |
bf13e81b JN |
2327 | I915_WRITE(pp_ctrl_reg, pp); |
2328 | POSTING_READ(pp_ctrl_reg); | |
05ce1a49 | 2329 | } |
37c6c9b0 | 2330 | |
5a162e22 | 2331 | pp |= PANEL_POWER_ON; |
5db94019 | 2332 | if (!IS_GEN5(dev_priv)) |
99ea7127 KP |
2333 | pp |= PANEL_POWER_RESET; |
2334 | ||
453c5420 JB |
2335 | I915_WRITE(pp_ctrl_reg, pp); |
2336 | POSTING_READ(pp_ctrl_reg); | |
9934c132 | 2337 | |
4be73780 | 2338 | wait_panel_on(intel_dp); |
dce56b3c | 2339 | intel_dp->last_power_on = jiffies; |
9934c132 | 2340 | |
5db94019 | 2341 | if (IS_GEN5(dev_priv)) { |
05ce1a49 | 2342 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ |
bf13e81b JN |
2343 | I915_WRITE(pp_ctrl_reg, pp); |
2344 | POSTING_READ(pp_ctrl_reg); | |
05ce1a49 | 2345 | } |
9f0fb5be | 2346 | } |
e39b999a | 2347 | |
9f0fb5be VS |
2348 | void intel_edp_panel_on(struct intel_dp *intel_dp) |
2349 | { | |
1853a9da | 2350 | if (!intel_dp_is_edp(intel_dp)) |
9f0fb5be VS |
2351 | return; |
2352 | ||
2353 | pps_lock(intel_dp); | |
2354 | edp_panel_on(intel_dp); | |
773538e8 | 2355 | pps_unlock(intel_dp); |
9934c132 JB |
2356 | } |
2357 | ||
9f0fb5be VS |
2358 | |
2359 | static void edp_panel_off(struct intel_dp *intel_dp) | |
9934c132 | 2360 | { |
2f773477 | 2361 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
99ea7127 | 2362 | u32 pp; |
f0f59a00 | 2363 | i915_reg_t pp_ctrl_reg; |
9934c132 | 2364 | |
9f0fb5be VS |
2365 | lockdep_assert_held(&dev_priv->pps_mutex); |
2366 | ||
1853a9da | 2367 | if (!intel_dp_is_edp(intel_dp)) |
97af61f5 | 2368 | return; |
37c6c9b0 | 2369 | |
3936fcf4 | 2370 | DRM_DEBUG_KMS("Turn eDP port %c panel power off\n", |
8f4f2797 | 2371 | port_name(dp_to_dig_port(intel_dp)->base.port)); |
37c6c9b0 | 2372 | |
3936fcf4 | 2373 | WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n", |
8f4f2797 | 2374 | port_name(dp_to_dig_port(intel_dp)->base.port)); |
24f3e092 | 2375 | |
453c5420 | 2376 | pp = ironlake_get_pp_control(intel_dp); |
35a38556 DV |
2377 | /* We need to switch off panel power _and_ force vdd, for otherwise some |
2378 | * panels get very unhappy and cease to work. */ | |
5a162e22 | 2379 | pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD | |
b3064154 | 2380 | EDP_BLC_ENABLE); |
453c5420 | 2381 | |
bf13e81b | 2382 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 | 2383 | |
849e39f5 PZ |
2384 | intel_dp->want_panel_vdd = false; |
2385 | ||
453c5420 JB |
2386 | I915_WRITE(pp_ctrl_reg, pp); |
2387 | POSTING_READ(pp_ctrl_reg); | |
9934c132 | 2388 | |
4be73780 | 2389 | wait_panel_off(intel_dp); |
d7ba25bd | 2390 | intel_dp->panel_power_off_time = ktime_get_boottime(); |
849e39f5 PZ |
2391 | |
2392 | /* We got a reference when we enabled the VDD. */ | |
5432fcaf | 2393 | intel_display_power_put(dev_priv, intel_dp->aux_power_domain); |
9f0fb5be | 2394 | } |
e39b999a | 2395 | |
9f0fb5be VS |
2396 | void intel_edp_panel_off(struct intel_dp *intel_dp) |
2397 | { | |
1853a9da | 2398 | if (!intel_dp_is_edp(intel_dp)) |
9f0fb5be | 2399 | return; |
e39b999a | 2400 | |
9f0fb5be VS |
2401 | pps_lock(intel_dp); |
2402 | edp_panel_off(intel_dp); | |
773538e8 | 2403 | pps_unlock(intel_dp); |
9934c132 JB |
2404 | } |
2405 | ||
1250d107 JN |
2406 | /* Enable backlight in the panel power control. */ |
2407 | static void _intel_edp_backlight_on(struct intel_dp *intel_dp) | |
32f9d658 | 2408 | { |
2f773477 | 2409 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
32f9d658 | 2410 | u32 pp; |
f0f59a00 | 2411 | i915_reg_t pp_ctrl_reg; |
32f9d658 | 2412 | |
01cb9ea6 JB |
2413 | /* |
2414 | * If we enable the backlight right away following a panel power | |
2415 | * on, we may see slight flicker as the panel syncs with the eDP | |
2416 | * link. So delay a bit to make sure the image is solid before | |
2417 | * allowing it to appear. | |
2418 | */ | |
4be73780 | 2419 | wait_backlight_on(intel_dp); |
e39b999a | 2420 | |
773538e8 | 2421 | pps_lock(intel_dp); |
e39b999a | 2422 | |
453c5420 | 2423 | pp = ironlake_get_pp_control(intel_dp); |
32f9d658 | 2424 | pp |= EDP_BLC_ENABLE; |
453c5420 | 2425 | |
bf13e81b | 2426 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 JB |
2427 | |
2428 | I915_WRITE(pp_ctrl_reg, pp); | |
2429 | POSTING_READ(pp_ctrl_reg); | |
e39b999a | 2430 | |
773538e8 | 2431 | pps_unlock(intel_dp); |
32f9d658 ZW |
2432 | } |
2433 | ||
1250d107 | 2434 | /* Enable backlight PWM and backlight PP control. */ |
b037d58f ML |
2435 | void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state, |
2436 | const struct drm_connector_state *conn_state) | |
1250d107 | 2437 | { |
b037d58f ML |
2438 | struct intel_dp *intel_dp = enc_to_intel_dp(conn_state->best_encoder); |
2439 | ||
1853a9da | 2440 | if (!intel_dp_is_edp(intel_dp)) |
1250d107 JN |
2441 | return; |
2442 | ||
2443 | DRM_DEBUG_KMS("\n"); | |
2444 | ||
b037d58f | 2445 | intel_panel_enable_backlight(crtc_state, conn_state); |
1250d107 JN |
2446 | _intel_edp_backlight_on(intel_dp); |
2447 | } | |
2448 | ||
2449 | /* Disable backlight in the panel power control. */ | |
2450 | static void _intel_edp_backlight_off(struct intel_dp *intel_dp) | |
32f9d658 | 2451 | { |
2f773477 | 2452 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
32f9d658 | 2453 | u32 pp; |
f0f59a00 | 2454 | i915_reg_t pp_ctrl_reg; |
32f9d658 | 2455 | |
1853a9da | 2456 | if (!intel_dp_is_edp(intel_dp)) |
f01eca2e KP |
2457 | return; |
2458 | ||
773538e8 | 2459 | pps_lock(intel_dp); |
e39b999a | 2460 | |
453c5420 | 2461 | pp = ironlake_get_pp_control(intel_dp); |
32f9d658 | 2462 | pp &= ~EDP_BLC_ENABLE; |
453c5420 | 2463 | |
bf13e81b | 2464 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 JB |
2465 | |
2466 | I915_WRITE(pp_ctrl_reg, pp); | |
2467 | POSTING_READ(pp_ctrl_reg); | |
f7d2323c | 2468 | |
773538e8 | 2469 | pps_unlock(intel_dp); |
e39b999a VS |
2470 | |
2471 | intel_dp->last_backlight_off = jiffies; | |
f7d2323c | 2472 | edp_wait_backlight_off(intel_dp); |
1250d107 | 2473 | } |
f7d2323c | 2474 | |
1250d107 | 2475 | /* Disable backlight PP control and backlight PWM. */ |
b037d58f | 2476 | void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state) |
1250d107 | 2477 | { |
b037d58f ML |
2478 | struct intel_dp *intel_dp = enc_to_intel_dp(old_conn_state->best_encoder); |
2479 | ||
1853a9da | 2480 | if (!intel_dp_is_edp(intel_dp)) |
1250d107 JN |
2481 | return; |
2482 | ||
2483 | DRM_DEBUG_KMS("\n"); | |
f7d2323c | 2484 | |
1250d107 | 2485 | _intel_edp_backlight_off(intel_dp); |
b037d58f | 2486 | intel_panel_disable_backlight(old_conn_state); |
32f9d658 | 2487 | } |
a4fc5ed6 | 2488 | |
73580fb7 JN |
2489 | /* |
2490 | * Hook for controlling the panel power control backlight through the bl_power | |
2491 | * sysfs attribute. Take care to handle multiple calls. | |
2492 | */ | |
2493 | static void intel_edp_backlight_power(struct intel_connector *connector, | |
2494 | bool enable) | |
2495 | { | |
2496 | struct intel_dp *intel_dp = intel_attached_dp(&connector->base); | |
e39b999a VS |
2497 | bool is_enabled; |
2498 | ||
773538e8 | 2499 | pps_lock(intel_dp); |
e39b999a | 2500 | is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE; |
773538e8 | 2501 | pps_unlock(intel_dp); |
73580fb7 JN |
2502 | |
2503 | if (is_enabled == enable) | |
2504 | return; | |
2505 | ||
23ba9373 JN |
2506 | DRM_DEBUG_KMS("panel power control backlight %s\n", |
2507 | enable ? "enable" : "disable"); | |
73580fb7 JN |
2508 | |
2509 | if (enable) | |
2510 | _intel_edp_backlight_on(intel_dp); | |
2511 | else | |
2512 | _intel_edp_backlight_off(intel_dp); | |
2513 | } | |
2514 | ||
64e1077a VS |
2515 | static void assert_dp_port(struct intel_dp *intel_dp, bool state) |
2516 | { | |
2517 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
2518 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); | |
2519 | bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN; | |
2520 | ||
2521 | I915_STATE_WARN(cur_state != state, | |
2522 | "DP port %c state assertion failure (expected %s, current %s)\n", | |
8f4f2797 | 2523 | port_name(dig_port->base.port), |
87ad3212 | 2524 | onoff(state), onoff(cur_state)); |
64e1077a VS |
2525 | } |
2526 | #define assert_dp_port_disabled(d) assert_dp_port((d), false) | |
2527 | ||
2528 | static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state) | |
2529 | { | |
2530 | bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE; | |
2531 | ||
2532 | I915_STATE_WARN(cur_state != state, | |
2533 | "eDP PLL state assertion failure (expected %s, current %s)\n", | |
87ad3212 | 2534 | onoff(state), onoff(cur_state)); |
64e1077a VS |
2535 | } |
2536 | #define assert_edp_pll_enabled(d) assert_edp_pll((d), true) | |
2537 | #define assert_edp_pll_disabled(d) assert_edp_pll((d), false) | |
2538 | ||
85cb48a1 | 2539 | static void ironlake_edp_pll_on(struct intel_dp *intel_dp, |
5f88a9c6 | 2540 | const struct intel_crtc_state *pipe_config) |
d240f20f | 2541 | { |
85cb48a1 | 2542 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); |
64e1077a | 2543 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
d240f20f | 2544 | |
64e1077a VS |
2545 | assert_pipe_disabled(dev_priv, crtc->pipe); |
2546 | assert_dp_port_disabled(intel_dp); | |
2547 | assert_edp_pll_disabled(dev_priv); | |
2bd2ad64 | 2548 | |
abfce949 | 2549 | DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n", |
85cb48a1 | 2550 | pipe_config->port_clock); |
abfce949 VS |
2551 | |
2552 | intel_dp->DP &= ~DP_PLL_FREQ_MASK; | |
2553 | ||
85cb48a1 | 2554 | if (pipe_config->port_clock == 162000) |
abfce949 VS |
2555 | intel_dp->DP |= DP_PLL_FREQ_162MHZ; |
2556 | else | |
2557 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; | |
2558 | ||
2559 | I915_WRITE(DP_A, intel_dp->DP); | |
2560 | POSTING_READ(DP_A); | |
2561 | udelay(500); | |
2562 | ||
6b23f3e8 VS |
2563 | /* |
2564 | * [DevILK] Work around required when enabling DP PLL | |
2565 | * while a pipe is enabled going to FDI: | |
2566 | * 1. Wait for the start of vertical blank on the enabled pipe going to FDI | |
2567 | * 2. Program DP PLL enable | |
2568 | */ | |
2569 | if (IS_GEN5(dev_priv)) | |
0f0f74bc | 2570 | intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe); |
6b23f3e8 | 2571 | |
0767935e | 2572 | intel_dp->DP |= DP_PLL_ENABLE; |
6fec7662 | 2573 | |
0767935e | 2574 | I915_WRITE(DP_A, intel_dp->DP); |
298b0b39 JB |
2575 | POSTING_READ(DP_A); |
2576 | udelay(200); | |
d240f20f JB |
2577 | } |
2578 | ||
adc10304 VS |
2579 | static void ironlake_edp_pll_off(struct intel_dp *intel_dp, |
2580 | const struct intel_crtc_state *old_crtc_state) | |
d240f20f | 2581 | { |
adc10304 | 2582 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); |
64e1077a | 2583 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
d240f20f | 2584 | |
64e1077a VS |
2585 | assert_pipe_disabled(dev_priv, crtc->pipe); |
2586 | assert_dp_port_disabled(intel_dp); | |
2587 | assert_edp_pll_enabled(dev_priv); | |
2bd2ad64 | 2588 | |
abfce949 VS |
2589 | DRM_DEBUG_KMS("disabling eDP PLL\n"); |
2590 | ||
6fec7662 | 2591 | intel_dp->DP &= ~DP_PLL_ENABLE; |
0767935e | 2592 | |
6fec7662 | 2593 | I915_WRITE(DP_A, intel_dp->DP); |
1af5fa1b | 2594 | POSTING_READ(DP_A); |
d240f20f JB |
2595 | udelay(200); |
2596 | } | |
2597 | ||
857c416e VS |
2598 | static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp) |
2599 | { | |
2600 | /* | |
2601 | * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus | |
2602 | * be capable of signalling downstream hpd with a long pulse. | |
2603 | * Whether or not that means D3 is safe to use is not clear, | |
2604 | * but let's assume so until proven otherwise. | |
2605 | * | |
2606 | * FIXME should really check all downstream ports... | |
2607 | */ | |
2608 | return intel_dp->dpcd[DP_DPCD_REV] == 0x11 && | |
2609 | intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT && | |
2610 | intel_dp->downstream_ports[0] & DP_DS_PORT_HPD; | |
2611 | } | |
2612 | ||
c7ad3810 | 2613 | /* If the sink supports it, try to set the power state appropriately */ |
c19b0669 | 2614 | void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) |
c7ad3810 JB |
2615 | { |
2616 | int ret, i; | |
2617 | ||
2618 | /* Should have a valid DPCD by this point */ | |
2619 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) | |
2620 | return; | |
2621 | ||
2622 | if (mode != DRM_MODE_DPMS_ON) { | |
857c416e VS |
2623 | if (downstream_hpd_needs_d0(intel_dp)) |
2624 | return; | |
2625 | ||
9d1a1031 JN |
2626 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
2627 | DP_SET_POWER_D3); | |
c7ad3810 | 2628 | } else { |
357c0ae9 ID |
2629 | struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp); |
2630 | ||
c7ad3810 JB |
2631 | /* |
2632 | * When turning on, we need to retry for 1ms to give the sink | |
2633 | * time to wake up. | |
2634 | */ | |
2635 | for (i = 0; i < 3; i++) { | |
9d1a1031 JN |
2636 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
2637 | DP_SET_POWER_D0); | |
c7ad3810 JB |
2638 | if (ret == 1) |
2639 | break; | |
2640 | msleep(1); | |
2641 | } | |
357c0ae9 ID |
2642 | |
2643 | if (ret == 1 && lspcon->active) | |
2644 | lspcon_wait_pcon_mode(lspcon); | |
c7ad3810 | 2645 | } |
f9cac721 JN |
2646 | |
2647 | if (ret != 1) | |
2648 | DRM_DEBUG_KMS("failed to %s sink power state\n", | |
2649 | mode == DRM_MODE_DPMS_ON ? "enable" : "disable"); | |
c7ad3810 JB |
2650 | } |
2651 | ||
19d8fe15 DV |
2652 | static bool intel_dp_get_hw_state(struct intel_encoder *encoder, |
2653 | enum pipe *pipe) | |
d240f20f | 2654 | { |
2f773477 | 2655 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
19d8fe15 | 2656 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
8f4f2797 | 2657 | enum port port = encoder->port; |
6d129bea | 2658 | u32 tmp; |
6fa9a5ec | 2659 | bool ret; |
6d129bea | 2660 | |
79f255a0 ACO |
2661 | if (!intel_display_power_get_if_enabled(dev_priv, |
2662 | encoder->power_domain)) | |
6d129bea ID |
2663 | return false; |
2664 | ||
6fa9a5ec ID |
2665 | ret = false; |
2666 | ||
6d129bea | 2667 | tmp = I915_READ(intel_dp->output_reg); |
19d8fe15 DV |
2668 | |
2669 | if (!(tmp & DP_PORT_EN)) | |
6fa9a5ec | 2670 | goto out; |
19d8fe15 | 2671 | |
5db94019 | 2672 | if (IS_GEN7(dev_priv) && port == PORT_A) { |
19d8fe15 | 2673 | *pipe = PORT_TO_PIPE_CPT(tmp); |
6e266956 | 2674 | } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) { |
adc289d7 | 2675 | enum pipe p; |
19d8fe15 | 2676 | |
adc289d7 VS |
2677 | for_each_pipe(dev_priv, p) { |
2678 | u32 trans_dp = I915_READ(TRANS_DP_CTL(p)); | |
2679 | if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) { | |
2680 | *pipe = p; | |
6fa9a5ec ID |
2681 | ret = true; |
2682 | ||
2683 | goto out; | |
19d8fe15 DV |
2684 | } |
2685 | } | |
19d8fe15 | 2686 | |
4a0833ec | 2687 | DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", |
f0f59a00 | 2688 | i915_mmio_reg_offset(intel_dp->output_reg)); |
920a14b2 | 2689 | } else if (IS_CHERRYVIEW(dev_priv)) { |
39e5fa88 VS |
2690 | *pipe = DP_PORT_TO_PIPE_CHV(tmp); |
2691 | } else { | |
2692 | *pipe = PORT_TO_PIPE(tmp); | |
4a0833ec | 2693 | } |
d240f20f | 2694 | |
6fa9a5ec ID |
2695 | ret = true; |
2696 | ||
2697 | out: | |
79f255a0 | 2698 | intel_display_power_put(dev_priv, encoder->power_domain); |
6fa9a5ec ID |
2699 | |
2700 | return ret; | |
19d8fe15 | 2701 | } |
d240f20f | 2702 | |
045ac3b5 | 2703 | static void intel_dp_get_config(struct intel_encoder *encoder, |
5cec258b | 2704 | struct intel_crtc_state *pipe_config) |
045ac3b5 | 2705 | { |
2f773477 | 2706 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
045ac3b5 | 2707 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
045ac3b5 | 2708 | u32 tmp, flags = 0; |
8f4f2797 | 2709 | enum port port = encoder->port; |
adc10304 | 2710 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); |
045ac3b5 | 2711 | |
e1214b95 VS |
2712 | if (encoder->type == INTEL_OUTPUT_EDP) |
2713 | pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP); | |
2714 | else | |
2715 | pipe_config->output_types |= BIT(INTEL_OUTPUT_DP); | |
045ac3b5 | 2716 | |
9ed109a7 | 2717 | tmp = I915_READ(intel_dp->output_reg); |
9fcb1704 JN |
2718 | |
2719 | pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A; | |
9ed109a7 | 2720 | |
6e266956 | 2721 | if (HAS_PCH_CPT(dev_priv) && port != PORT_A) { |
b81e34c2 VS |
2722 | u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe)); |
2723 | ||
2724 | if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH) | |
63000ef6 XZ |
2725 | flags |= DRM_MODE_FLAG_PHSYNC; |
2726 | else | |
2727 | flags |= DRM_MODE_FLAG_NHSYNC; | |
045ac3b5 | 2728 | |
b81e34c2 | 2729 | if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH) |
63000ef6 XZ |
2730 | flags |= DRM_MODE_FLAG_PVSYNC; |
2731 | else | |
2732 | flags |= DRM_MODE_FLAG_NVSYNC; | |
2733 | } else { | |
39e5fa88 | 2734 | if (tmp & DP_SYNC_HS_HIGH) |
63000ef6 XZ |
2735 | flags |= DRM_MODE_FLAG_PHSYNC; |
2736 | else | |
2737 | flags |= DRM_MODE_FLAG_NHSYNC; | |
045ac3b5 | 2738 | |
39e5fa88 | 2739 | if (tmp & DP_SYNC_VS_HIGH) |
63000ef6 XZ |
2740 | flags |= DRM_MODE_FLAG_PVSYNC; |
2741 | else | |
2742 | flags |= DRM_MODE_FLAG_NVSYNC; | |
2743 | } | |
045ac3b5 | 2744 | |
2d112de7 | 2745 | pipe_config->base.adjusted_mode.flags |= flags; |
f1f644dc | 2746 | |
c99f53f7 | 2747 | if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235) |
8c875fca VS |
2748 | pipe_config->limited_color_range = true; |
2749 | ||
90a6b7b0 VS |
2750 | pipe_config->lane_count = |
2751 | ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1; | |
2752 | ||
eb14cb74 VS |
2753 | intel_dp_get_m_n(crtc, pipe_config); |
2754 | ||
18442d08 | 2755 | if (port == PORT_A) { |
b377e0df | 2756 | if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ) |
f1f644dc JB |
2757 | pipe_config->port_clock = 162000; |
2758 | else | |
2759 | pipe_config->port_clock = 270000; | |
2760 | } | |
18442d08 | 2761 | |
e3b247da VS |
2762 | pipe_config->base.adjusted_mode.crtc_clock = |
2763 | intel_dotclock_calculate(pipe_config->port_clock, | |
2764 | &pipe_config->dp_m_n); | |
7f16e5c1 | 2765 | |
1853a9da | 2766 | if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp && |
6aa23e65 | 2767 | pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { |
c6cd2ee2 JN |
2768 | /* |
2769 | * This is a big fat ugly hack. | |
2770 | * | |
2771 | * Some machines in UEFI boot mode provide us a VBT that has 18 | |
2772 | * bpp and 1.62 GHz link bandwidth for eDP, which for reasons | |
2773 | * unknown we fail to light up. Yet the same BIOS boots up with | |
2774 | * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as | |
2775 | * max, not what it tells us to use. | |
2776 | * | |
2777 | * Note: This will still be broken if the eDP panel is not lit | |
2778 | * up by the BIOS, and thus we can't get the mode at module | |
2779 | * load. | |
2780 | */ | |
2781 | DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", | |
6aa23e65 JN |
2782 | pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); |
2783 | dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; | |
c6cd2ee2 | 2784 | } |
045ac3b5 JB |
2785 | } |
2786 | ||
fd6bbda9 | 2787 | static void intel_disable_dp(struct intel_encoder *encoder, |
5f88a9c6 VS |
2788 | const struct intel_crtc_state *old_crtc_state, |
2789 | const struct drm_connector_state *old_conn_state) | |
d240f20f | 2790 | { |
e8cb4558 | 2791 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
495a5bb8 | 2792 | |
edb2e530 VS |
2793 | intel_dp->link_trained = false; |
2794 | ||
85cb48a1 | 2795 | if (old_crtc_state->has_audio) |
8ec47de2 VS |
2796 | intel_audio_codec_disable(encoder, |
2797 | old_crtc_state, old_conn_state); | |
6cb49835 DV |
2798 | |
2799 | /* Make sure the panel is off before trying to change the mode. But also | |
2800 | * ensure that we have vdd while we switch off the panel. */ | |
24f3e092 | 2801 | intel_edp_panel_vdd_on(intel_dp); |
b037d58f | 2802 | intel_edp_backlight_off(old_conn_state); |
fdbc3b1f | 2803 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); |
4be73780 | 2804 | intel_edp_panel_off(intel_dp); |
1a8ff607 VS |
2805 | } |
2806 | ||
2807 | static void g4x_disable_dp(struct intel_encoder *encoder, | |
2808 | const struct intel_crtc_state *old_crtc_state, | |
2809 | const struct drm_connector_state *old_conn_state) | |
2810 | { | |
1a8ff607 | 2811 | intel_disable_dp(encoder, old_crtc_state, old_conn_state); |
3739850b | 2812 | |
08aff3fe | 2813 | /* disable the port before the pipe on g4x */ |
adc10304 | 2814 | intel_dp_link_down(encoder, old_crtc_state); |
1a8ff607 VS |
2815 | } |
2816 | ||
2817 | static void ilk_disable_dp(struct intel_encoder *encoder, | |
2818 | const struct intel_crtc_state *old_crtc_state, | |
2819 | const struct drm_connector_state *old_conn_state) | |
2820 | { | |
2821 | intel_disable_dp(encoder, old_crtc_state, old_conn_state); | |
2822 | } | |
2823 | ||
2824 | static void vlv_disable_dp(struct intel_encoder *encoder, | |
2825 | const struct intel_crtc_state *old_crtc_state, | |
2826 | const struct drm_connector_state *old_conn_state) | |
2827 | { | |
2828 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
2829 | ||
2830 | intel_psr_disable(intel_dp, old_crtc_state); | |
2831 | ||
2832 | intel_disable_dp(encoder, old_crtc_state, old_conn_state); | |
d240f20f JB |
2833 | } |
2834 | ||
fd6bbda9 | 2835 | static void ilk_post_disable_dp(struct intel_encoder *encoder, |
5f88a9c6 VS |
2836 | const struct intel_crtc_state *old_crtc_state, |
2837 | const struct drm_connector_state *old_conn_state) | |
d240f20f | 2838 | { |
2bd2ad64 | 2839 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
adc10304 | 2840 | enum port port = encoder->port; |
2bd2ad64 | 2841 | |
adc10304 | 2842 | intel_dp_link_down(encoder, old_crtc_state); |
abfce949 VS |
2843 | |
2844 | /* Only ilk+ has port A */ | |
08aff3fe | 2845 | if (port == PORT_A) |
adc10304 | 2846 | ironlake_edp_pll_off(intel_dp, old_crtc_state); |
49277c31 VS |
2847 | } |
2848 | ||
fd6bbda9 | 2849 | static void vlv_post_disable_dp(struct intel_encoder *encoder, |
5f88a9c6 VS |
2850 | const struct intel_crtc_state *old_crtc_state, |
2851 | const struct drm_connector_state *old_conn_state) | |
49277c31 | 2852 | { |
adc10304 | 2853 | intel_dp_link_down(encoder, old_crtc_state); |
2bd2ad64 DV |
2854 | } |
2855 | ||
fd6bbda9 | 2856 | static void chv_post_disable_dp(struct intel_encoder *encoder, |
5f88a9c6 VS |
2857 | const struct intel_crtc_state *old_crtc_state, |
2858 | const struct drm_connector_state *old_conn_state) | |
a8f327fb | 2859 | { |
adc10304 | 2860 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
97fd4d5c | 2861 | |
adc10304 | 2862 | intel_dp_link_down(encoder, old_crtc_state); |
a8f327fb VS |
2863 | |
2864 | mutex_lock(&dev_priv->sb_lock); | |
2865 | ||
2866 | /* Assert data lane reset */ | |
2e1029c6 | 2867 | chv_data_lane_soft_reset(encoder, old_crtc_state, true); |
580d3811 | 2868 | |
a580516d | 2869 | mutex_unlock(&dev_priv->sb_lock); |
580d3811 VS |
2870 | } |
2871 | ||
7b13b58a VS |
2872 | static void |
2873 | _intel_dp_set_link_train(struct intel_dp *intel_dp, | |
2874 | uint32_t *DP, | |
2875 | uint8_t dp_train_pat) | |
2876 | { | |
2f773477 | 2877 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
7b13b58a | 2878 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
8f4f2797 | 2879 | enum port port = intel_dig_port->base.port; |
7b13b58a | 2880 | |
8b0878a0 PD |
2881 | if (dp_train_pat & DP_TRAINING_PATTERN_MASK) |
2882 | DRM_DEBUG_KMS("Using DP training pattern TPS%d\n", | |
2883 | dp_train_pat & DP_TRAINING_PATTERN_MASK); | |
2884 | ||
4f8036a2 | 2885 | if (HAS_DDI(dev_priv)) { |
7b13b58a VS |
2886 | uint32_t temp = I915_READ(DP_TP_CTL(port)); |
2887 | ||
2888 | if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) | |
2889 | temp |= DP_TP_CTL_SCRAMBLE_DISABLE; | |
2890 | else | |
2891 | temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; | |
2892 | ||
2893 | temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; | |
2894 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { | |
2895 | case DP_TRAINING_PATTERN_DISABLE: | |
2896 | temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; | |
2897 | ||
2898 | break; | |
2899 | case DP_TRAINING_PATTERN_1: | |
2900 | temp |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
2901 | break; | |
2902 | case DP_TRAINING_PATTERN_2: | |
2903 | temp |= DP_TP_CTL_LINK_TRAIN_PAT2; | |
2904 | break; | |
2905 | case DP_TRAINING_PATTERN_3: | |
2906 | temp |= DP_TP_CTL_LINK_TRAIN_PAT3; | |
2907 | break; | |
2908 | } | |
2909 | I915_WRITE(DP_TP_CTL(port), temp); | |
2910 | ||
5db94019 | 2911 | } else if ((IS_GEN7(dev_priv) && port == PORT_A) || |
6e266956 | 2912 | (HAS_PCH_CPT(dev_priv) && port != PORT_A)) { |
7b13b58a VS |
2913 | *DP &= ~DP_LINK_TRAIN_MASK_CPT; |
2914 | ||
2915 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { | |
2916 | case DP_TRAINING_PATTERN_DISABLE: | |
2917 | *DP |= DP_LINK_TRAIN_OFF_CPT; | |
2918 | break; | |
2919 | case DP_TRAINING_PATTERN_1: | |
2920 | *DP |= DP_LINK_TRAIN_PAT_1_CPT; | |
2921 | break; | |
2922 | case DP_TRAINING_PATTERN_2: | |
2923 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; | |
2924 | break; | |
2925 | case DP_TRAINING_PATTERN_3: | |
8b0878a0 | 2926 | DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n"); |
7b13b58a VS |
2927 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; |
2928 | break; | |
2929 | } | |
2930 | ||
2931 | } else { | |
3b358cda | 2932 | *DP &= ~DP_LINK_TRAIN_MASK; |
7b13b58a VS |
2933 | |
2934 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { | |
2935 | case DP_TRAINING_PATTERN_DISABLE: | |
2936 | *DP |= DP_LINK_TRAIN_OFF; | |
2937 | break; | |
2938 | case DP_TRAINING_PATTERN_1: | |
2939 | *DP |= DP_LINK_TRAIN_PAT_1; | |
2940 | break; | |
2941 | case DP_TRAINING_PATTERN_2: | |
2942 | *DP |= DP_LINK_TRAIN_PAT_2; | |
2943 | break; | |
2944 | case DP_TRAINING_PATTERN_3: | |
3b358cda VS |
2945 | DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n"); |
2946 | *DP |= DP_LINK_TRAIN_PAT_2; | |
7b13b58a VS |
2947 | break; |
2948 | } | |
2949 | } | |
2950 | } | |
2951 | ||
85cb48a1 | 2952 | static void intel_dp_enable_port(struct intel_dp *intel_dp, |
5f88a9c6 | 2953 | const struct intel_crtc_state *old_crtc_state) |
7b13b58a | 2954 | { |
2f773477 | 2955 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
7b13b58a | 2956 | |
7b13b58a | 2957 | /* enable with pattern 1 (as per spec) */ |
7b13b58a | 2958 | |
8b0878a0 | 2959 | intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1); |
7b713f50 VS |
2960 | |
2961 | /* | |
2962 | * Magic for VLV/CHV. We _must_ first set up the register | |
2963 | * without actually enabling the port, and then do another | |
2964 | * write to enable the port. Otherwise link training will | |
2965 | * fail when the power sequencer is freshly used for this port. | |
2966 | */ | |
2967 | intel_dp->DP |= DP_PORT_EN; | |
85cb48a1 | 2968 | if (old_crtc_state->has_audio) |
6fec7662 | 2969 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; |
7b713f50 VS |
2970 | |
2971 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); | |
2972 | POSTING_READ(intel_dp->output_reg); | |
580d3811 VS |
2973 | } |
2974 | ||
85cb48a1 | 2975 | static void intel_enable_dp(struct intel_encoder *encoder, |
5f88a9c6 VS |
2976 | const struct intel_crtc_state *pipe_config, |
2977 | const struct drm_connector_state *conn_state) | |
d240f20f | 2978 | { |
2f773477 | 2979 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
e8cb4558 | 2980 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
adc10304 | 2981 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); |
e8cb4558 | 2982 | uint32_t dp_reg = I915_READ(intel_dp->output_reg); |
d6fbdd15 | 2983 | enum pipe pipe = crtc->pipe; |
5d613501 | 2984 | |
0c33d8d7 DV |
2985 | if (WARN_ON(dp_reg & DP_PORT_EN)) |
2986 | return; | |
5d613501 | 2987 | |
093e3f13 VS |
2988 | pps_lock(intel_dp); |
2989 | ||
920a14b2 | 2990 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
adc10304 | 2991 | vlv_init_panel_power_sequencer(encoder, pipe_config); |
093e3f13 | 2992 | |
85cb48a1 | 2993 | intel_dp_enable_port(intel_dp, pipe_config); |
093e3f13 VS |
2994 | |
2995 | edp_panel_vdd_on(intel_dp); | |
2996 | edp_panel_on(intel_dp); | |
2997 | edp_panel_vdd_off(intel_dp, true); | |
2998 | ||
2999 | pps_unlock(intel_dp); | |
3000 | ||
920a14b2 | 3001 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
e0fce78f VS |
3002 | unsigned int lane_mask = 0x0; |
3003 | ||
920a14b2 | 3004 | if (IS_CHERRYVIEW(dev_priv)) |
85cb48a1 | 3005 | lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count); |
e0fce78f | 3006 | |
9b6de0a1 VS |
3007 | vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp), |
3008 | lane_mask); | |
e0fce78f | 3009 | } |
61234fa5 | 3010 | |
f01eca2e | 3011 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
33a34e4e | 3012 | intel_dp_start_link_train(intel_dp); |
3ab9c637 | 3013 | intel_dp_stop_link_train(intel_dp); |
c1dec79a | 3014 | |
85cb48a1 | 3015 | if (pipe_config->has_audio) { |
c1dec79a | 3016 | DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", |
d6fbdd15 | 3017 | pipe_name(pipe)); |
bbf35e9d | 3018 | intel_audio_codec_enable(encoder, pipe_config, conn_state); |
c1dec79a | 3019 | } |
ab1f90f9 | 3020 | } |
89b667f8 | 3021 | |
fd6bbda9 | 3022 | static void g4x_enable_dp(struct intel_encoder *encoder, |
5f88a9c6 VS |
3023 | const struct intel_crtc_state *pipe_config, |
3024 | const struct drm_connector_state *conn_state) | |
ecff4f3b | 3025 | { |
bbf35e9d | 3026 | intel_enable_dp(encoder, pipe_config, conn_state); |
b037d58f | 3027 | intel_edp_backlight_on(pipe_config, conn_state); |
ab1f90f9 | 3028 | } |
89b667f8 | 3029 | |
fd6bbda9 | 3030 | static void vlv_enable_dp(struct intel_encoder *encoder, |
5f88a9c6 VS |
3031 | const struct intel_crtc_state *pipe_config, |
3032 | const struct drm_connector_state *conn_state) | |
ab1f90f9 | 3033 | { |
828f5c6e JN |
3034 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
3035 | ||
b037d58f | 3036 | intel_edp_backlight_on(pipe_config, conn_state); |
d2419ffc | 3037 | intel_psr_enable(intel_dp, pipe_config); |
d240f20f JB |
3038 | } |
3039 | ||
fd6bbda9 | 3040 | static void g4x_pre_enable_dp(struct intel_encoder *encoder, |
5f88a9c6 VS |
3041 | const struct intel_crtc_state *pipe_config, |
3042 | const struct drm_connector_state *conn_state) | |
ab1f90f9 JN |
3043 | { |
3044 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
8f4f2797 | 3045 | enum port port = encoder->port; |
ab1f90f9 | 3046 | |
85cb48a1 | 3047 | intel_dp_prepare(encoder, pipe_config); |
8ac33ed3 | 3048 | |
d41f1efb | 3049 | /* Only ilk+ has port A */ |
abfce949 | 3050 | if (port == PORT_A) |
85cb48a1 | 3051 | ironlake_edp_pll_on(intel_dp, pipe_config); |
ab1f90f9 JN |
3052 | } |
3053 | ||
83b84597 VS |
3054 | static void vlv_detach_power_sequencer(struct intel_dp *intel_dp) |
3055 | { | |
3056 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
fac5e23e | 3057 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); |
83b84597 | 3058 | enum pipe pipe = intel_dp->pps_pipe; |
44cb734c | 3059 | i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe); |
83b84597 | 3060 | |
9f2bdb00 VS |
3061 | WARN_ON(intel_dp->active_pipe != INVALID_PIPE); |
3062 | ||
d158694f VS |
3063 | if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) |
3064 | return; | |
3065 | ||
83b84597 VS |
3066 | edp_panel_vdd_off_sync(intel_dp); |
3067 | ||
3068 | /* | |
e7f2af78 | 3069 | * VLV seems to get confused when multiple power sequencers |
83b84597 VS |
3070 | * have the same port selected (even if only one has power/vdd |
3071 | * enabled). The failure manifests as vlv_wait_port_ready() failing | |
3072 | * CHV on the other hand doesn't seem to mind having the same port | |
e7f2af78 | 3073 | * selected in multiple power sequencers, but let's clear the |
83b84597 VS |
3074 | * port select always when logically disconnecting a power sequencer |
3075 | * from a port. | |
3076 | */ | |
3077 | DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n", | |
8f4f2797 | 3078 | pipe_name(pipe), port_name(intel_dig_port->base.port)); |
83b84597 VS |
3079 | I915_WRITE(pp_on_reg, 0); |
3080 | POSTING_READ(pp_on_reg); | |
3081 | ||
3082 | intel_dp->pps_pipe = INVALID_PIPE; | |
3083 | } | |
3084 | ||
46bd8383 | 3085 | static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv, |
a4a5d2f8 VS |
3086 | enum pipe pipe) |
3087 | { | |
a4a5d2f8 VS |
3088 | struct intel_encoder *encoder; |
3089 | ||
3090 | lockdep_assert_held(&dev_priv->pps_mutex); | |
3091 | ||
46bd8383 | 3092 | for_each_intel_encoder(&dev_priv->drm, encoder) { |
a4a5d2f8 | 3093 | struct intel_dp *intel_dp; |
773538e8 | 3094 | enum port port; |
a4a5d2f8 | 3095 | |
9f2bdb00 VS |
3096 | if (encoder->type != INTEL_OUTPUT_DP && |
3097 | encoder->type != INTEL_OUTPUT_EDP) | |
a4a5d2f8 VS |
3098 | continue; |
3099 | ||
3100 | intel_dp = enc_to_intel_dp(&encoder->base); | |
8f4f2797 | 3101 | port = dp_to_dig_port(intel_dp)->base.port; |
a4a5d2f8 | 3102 | |
9f2bdb00 VS |
3103 | WARN(intel_dp->active_pipe == pipe, |
3104 | "stealing pipe %c power sequencer from active (e)DP port %c\n", | |
3105 | pipe_name(pipe), port_name(port)); | |
3106 | ||
a4a5d2f8 VS |
3107 | if (intel_dp->pps_pipe != pipe) |
3108 | continue; | |
3109 | ||
3110 | DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n", | |
773538e8 | 3111 | pipe_name(pipe), port_name(port)); |
a4a5d2f8 VS |
3112 | |
3113 | /* make sure vdd is off before we steal it */ | |
83b84597 | 3114 | vlv_detach_power_sequencer(intel_dp); |
a4a5d2f8 VS |
3115 | } |
3116 | } | |
3117 | ||
adc10304 VS |
3118 | static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder, |
3119 | const struct intel_crtc_state *crtc_state) | |
a4a5d2f8 | 3120 | { |
46bd8383 | 3121 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
adc10304 | 3122 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
adc10304 | 3123 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a4a5d2f8 VS |
3124 | |
3125 | lockdep_assert_held(&dev_priv->pps_mutex); | |
3126 | ||
9f2bdb00 | 3127 | WARN_ON(intel_dp->active_pipe != INVALID_PIPE); |
093e3f13 | 3128 | |
9f2bdb00 VS |
3129 | if (intel_dp->pps_pipe != INVALID_PIPE && |
3130 | intel_dp->pps_pipe != crtc->pipe) { | |
3131 | /* | |
3132 | * If another power sequencer was being used on this | |
3133 | * port previously make sure to turn off vdd there while | |
3134 | * we still have control of it. | |
3135 | */ | |
83b84597 | 3136 | vlv_detach_power_sequencer(intel_dp); |
9f2bdb00 | 3137 | } |
a4a5d2f8 VS |
3138 | |
3139 | /* | |
3140 | * We may be stealing the power | |
3141 | * sequencer from another port. | |
3142 | */ | |
46bd8383 | 3143 | vlv_steal_power_sequencer(dev_priv, crtc->pipe); |
a4a5d2f8 | 3144 | |
9f2bdb00 VS |
3145 | intel_dp->active_pipe = crtc->pipe; |
3146 | ||
1853a9da | 3147 | if (!intel_dp_is_edp(intel_dp)) |
9f2bdb00 VS |
3148 | return; |
3149 | ||
a4a5d2f8 VS |
3150 | /* now it's all ours */ |
3151 | intel_dp->pps_pipe = crtc->pipe; | |
3152 | ||
3153 | DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n", | |
adc10304 | 3154 | pipe_name(intel_dp->pps_pipe), port_name(encoder->port)); |
a4a5d2f8 VS |
3155 | |
3156 | /* init power sequencer on this pipe and port */ | |
46bd8383 VS |
3157 | intel_dp_init_panel_power_sequencer(intel_dp); |
3158 | intel_dp_init_panel_power_sequencer_registers(intel_dp, true); | |
a4a5d2f8 VS |
3159 | } |
3160 | ||
fd6bbda9 | 3161 | static void vlv_pre_enable_dp(struct intel_encoder *encoder, |
5f88a9c6 VS |
3162 | const struct intel_crtc_state *pipe_config, |
3163 | const struct drm_connector_state *conn_state) | |
a4fc5ed6 | 3164 | { |
2e1029c6 | 3165 | vlv_phy_pre_encoder_enable(encoder, pipe_config); |
ab1f90f9 | 3166 | |
bbf35e9d | 3167 | intel_enable_dp(encoder, pipe_config, conn_state); |
89b667f8 JB |
3168 | } |
3169 | ||
fd6bbda9 | 3170 | static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder, |
5f88a9c6 VS |
3171 | const struct intel_crtc_state *pipe_config, |
3172 | const struct drm_connector_state *conn_state) | |
89b667f8 | 3173 | { |
85cb48a1 | 3174 | intel_dp_prepare(encoder, pipe_config); |
8ac33ed3 | 3175 | |
2e1029c6 | 3176 | vlv_phy_pre_pll_enable(encoder, pipe_config); |
a4fc5ed6 KP |
3177 | } |
3178 | ||
fd6bbda9 | 3179 | static void chv_pre_enable_dp(struct intel_encoder *encoder, |
5f88a9c6 VS |
3180 | const struct intel_crtc_state *pipe_config, |
3181 | const struct drm_connector_state *conn_state) | |
e4a1d846 | 3182 | { |
2e1029c6 | 3183 | chv_phy_pre_encoder_enable(encoder, pipe_config); |
e4a1d846 | 3184 | |
bbf35e9d | 3185 | intel_enable_dp(encoder, pipe_config, conn_state); |
b0b33846 VS |
3186 | |
3187 | /* Second common lane will stay alive on its own now */ | |
e7d2a717 | 3188 | chv_phy_release_cl2_override(encoder); |
e4a1d846 CML |
3189 | } |
3190 | ||
fd6bbda9 | 3191 | static void chv_dp_pre_pll_enable(struct intel_encoder *encoder, |
5f88a9c6 VS |
3192 | const struct intel_crtc_state *pipe_config, |
3193 | const struct drm_connector_state *conn_state) | |
9197c88b | 3194 | { |
85cb48a1 | 3195 | intel_dp_prepare(encoder, pipe_config); |
625695f8 | 3196 | |
2e1029c6 | 3197 | chv_phy_pre_pll_enable(encoder, pipe_config); |
9197c88b VS |
3198 | } |
3199 | ||
fd6bbda9 | 3200 | static void chv_dp_post_pll_disable(struct intel_encoder *encoder, |
2e1029c6 VS |
3201 | const struct intel_crtc_state *old_crtc_state, |
3202 | const struct drm_connector_state *old_conn_state) | |
d6db995f | 3203 | { |
2e1029c6 | 3204 | chv_phy_post_pll_disable(encoder, old_crtc_state); |
d6db995f VS |
3205 | } |
3206 | ||
a4fc5ed6 KP |
3207 | /* |
3208 | * Fetch AUX CH registers 0x202 - 0x207 which contain | |
3209 | * link status information | |
3210 | */ | |
94223d04 | 3211 | bool |
93f62dad | 3212 | intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) |
a4fc5ed6 | 3213 | { |
9f085ebb L |
3214 | return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status, |
3215 | DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE; | |
a4fc5ed6 KP |
3216 | } |
3217 | ||
1100244e | 3218 | /* These are source-specific values. */ |
94223d04 | 3219 | uint8_t |
1a2eb460 | 3220 | intel_dp_voltage_max(struct intel_dp *intel_dp) |
a4fc5ed6 | 3221 | { |
dd11bc10 | 3222 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
8f4f2797 | 3223 | enum port port = dp_to_dig_port(intel_dp)->base.port; |
1a2eb460 | 3224 | |
7d4f37b5 | 3225 | if (INTEL_GEN(dev_priv) >= 9) { |
ffe5111e VS |
3226 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; |
3227 | return intel_ddi_dp_voltage_max(encoder); | |
920a14b2 | 3228 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
bd60018a | 3229 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
5db94019 | 3230 | else if (IS_GEN7(dev_priv) && port == PORT_A) |
bd60018a | 3231 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
6e266956 | 3232 | else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) |
bd60018a | 3233 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
1a2eb460 | 3234 | else |
bd60018a | 3235 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
1a2eb460 KP |
3236 | } |
3237 | ||
94223d04 | 3238 | uint8_t |
1a2eb460 KP |
3239 | intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) |
3240 | { | |
8652744b | 3241 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
8f4f2797 | 3242 | enum port port = dp_to_dig_port(intel_dp)->base.port; |
1a2eb460 | 3243 | |
8652744b | 3244 | if (INTEL_GEN(dev_priv) >= 9) { |
5a9d1f1a DL |
3245 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3246 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: | |
3247 | return DP_TRAIN_PRE_EMPH_LEVEL_3; | |
3248 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
3249 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
3250 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
3251 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
7ad14a29 SJ |
3252 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
3253 | return DP_TRAIN_PRE_EMPH_LEVEL_0; | |
5a9d1f1a DL |
3254 | default: |
3255 | return DP_TRAIN_PRE_EMPH_LEVEL_0; | |
3256 | } | |
8652744b | 3257 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
d6c0d722 | 3258 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a SJ |
3259 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3260 | return DP_TRAIN_PRE_EMPH_LEVEL_3; | |
3261 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
3262 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
3263 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
3264 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
3265 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: | |
d6c0d722 | 3266 | default: |
bd60018a | 3267 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
d6c0d722 | 3268 | } |
8652744b | 3269 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
e2fa6fba | 3270 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a SJ |
3271 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3272 | return DP_TRAIN_PRE_EMPH_LEVEL_3; | |
3273 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
3274 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
3275 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
3276 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
3277 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: | |
e2fa6fba | 3278 | default: |
bd60018a | 3279 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
e2fa6fba | 3280 | } |
8652744b | 3281 | } else if (IS_GEN7(dev_priv) && port == PORT_A) { |
1a2eb460 | 3282 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a SJ |
3283 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3284 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
3285 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
3286 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
3287 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
1a2eb460 | 3288 | default: |
bd60018a | 3289 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
1a2eb460 KP |
3290 | } |
3291 | } else { | |
3292 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a SJ |
3293 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3294 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
3295 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
3296 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
3297 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
3298 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
3299 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: | |
1a2eb460 | 3300 | default: |
bd60018a | 3301 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
1a2eb460 | 3302 | } |
a4fc5ed6 KP |
3303 | } |
3304 | } | |
3305 | ||
5829975c | 3306 | static uint32_t vlv_signal_levels(struct intel_dp *intel_dp) |
e2fa6fba | 3307 | { |
53d98725 | 3308 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; |
e2fa6fba P |
3309 | unsigned long demph_reg_value, preemph_reg_value, |
3310 | uniqtranscale_reg_value; | |
3311 | uint8_t train_set = intel_dp->train_set[0]; | |
e2fa6fba P |
3312 | |
3313 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { | |
bd60018a | 3314 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
e2fa6fba P |
3315 | preemph_reg_value = 0x0004000; |
3316 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a | 3317 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e2fa6fba P |
3318 | demph_reg_value = 0x2B405555; |
3319 | uniqtranscale_reg_value = 0x552AB83A; | |
3320 | break; | |
bd60018a | 3321 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e2fa6fba P |
3322 | demph_reg_value = 0x2B404040; |
3323 | uniqtranscale_reg_value = 0x5548B83A; | |
3324 | break; | |
bd60018a | 3325 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
e2fa6fba P |
3326 | demph_reg_value = 0x2B245555; |
3327 | uniqtranscale_reg_value = 0x5560B83A; | |
3328 | break; | |
bd60018a | 3329 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
e2fa6fba P |
3330 | demph_reg_value = 0x2B405555; |
3331 | uniqtranscale_reg_value = 0x5598DA3A; | |
3332 | break; | |
3333 | default: | |
3334 | return 0; | |
3335 | } | |
3336 | break; | |
bd60018a | 3337 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
e2fa6fba P |
3338 | preemph_reg_value = 0x0002000; |
3339 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a | 3340 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e2fa6fba P |
3341 | demph_reg_value = 0x2B404040; |
3342 | uniqtranscale_reg_value = 0x5552B83A; | |
3343 | break; | |
bd60018a | 3344 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e2fa6fba P |
3345 | demph_reg_value = 0x2B404848; |
3346 | uniqtranscale_reg_value = 0x5580B83A; | |
3347 | break; | |
bd60018a | 3348 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
e2fa6fba P |
3349 | demph_reg_value = 0x2B404040; |
3350 | uniqtranscale_reg_value = 0x55ADDA3A; | |
3351 | break; | |
3352 | default: | |
3353 | return 0; | |
3354 | } | |
3355 | break; | |
bd60018a | 3356 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
e2fa6fba P |
3357 | preemph_reg_value = 0x0000000; |
3358 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a | 3359 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e2fa6fba P |
3360 | demph_reg_value = 0x2B305555; |
3361 | uniqtranscale_reg_value = 0x5570B83A; | |
3362 | break; | |
bd60018a | 3363 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e2fa6fba P |
3364 | demph_reg_value = 0x2B2B4040; |
3365 | uniqtranscale_reg_value = 0x55ADDA3A; | |
3366 | break; | |
3367 | default: | |
3368 | return 0; | |
3369 | } | |
3370 | break; | |
bd60018a | 3371 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
e2fa6fba P |
3372 | preemph_reg_value = 0x0006000; |
3373 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a | 3374 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e2fa6fba P |
3375 | demph_reg_value = 0x1B405555; |
3376 | uniqtranscale_reg_value = 0x55ADDA3A; | |
3377 | break; | |
3378 | default: | |
3379 | return 0; | |
3380 | } | |
3381 | break; | |
3382 | default: | |
3383 | return 0; | |
3384 | } | |
3385 | ||
53d98725 ACO |
3386 | vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value, |
3387 | uniqtranscale_reg_value, 0); | |
e2fa6fba P |
3388 | |
3389 | return 0; | |
3390 | } | |
3391 | ||
5829975c | 3392 | static uint32_t chv_signal_levels(struct intel_dp *intel_dp) |
e4a1d846 | 3393 | { |
b7fa22d8 ACO |
3394 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; |
3395 | u32 deemph_reg_value, margin_reg_value; | |
3396 | bool uniq_trans_scale = false; | |
e4a1d846 | 3397 | uint8_t train_set = intel_dp->train_set[0]; |
e4a1d846 CML |
3398 | |
3399 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { | |
bd60018a | 3400 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
e4a1d846 | 3401 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 3402 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e4a1d846 CML |
3403 | deemph_reg_value = 128; |
3404 | margin_reg_value = 52; | |
3405 | break; | |
bd60018a | 3406 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e4a1d846 CML |
3407 | deemph_reg_value = 128; |
3408 | margin_reg_value = 77; | |
3409 | break; | |
bd60018a | 3410 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
e4a1d846 CML |
3411 | deemph_reg_value = 128; |
3412 | margin_reg_value = 102; | |
3413 | break; | |
bd60018a | 3414 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
e4a1d846 CML |
3415 | deemph_reg_value = 128; |
3416 | margin_reg_value = 154; | |
b7fa22d8 | 3417 | uniq_trans_scale = true; |
e4a1d846 CML |
3418 | break; |
3419 | default: | |
3420 | return 0; | |
3421 | } | |
3422 | break; | |
bd60018a | 3423 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
e4a1d846 | 3424 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 3425 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e4a1d846 CML |
3426 | deemph_reg_value = 85; |
3427 | margin_reg_value = 78; | |
3428 | break; | |
bd60018a | 3429 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e4a1d846 CML |
3430 | deemph_reg_value = 85; |
3431 | margin_reg_value = 116; | |
3432 | break; | |
bd60018a | 3433 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
e4a1d846 CML |
3434 | deemph_reg_value = 85; |
3435 | margin_reg_value = 154; | |
3436 | break; | |
3437 | default: | |
3438 | return 0; | |
3439 | } | |
3440 | break; | |
bd60018a | 3441 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
e4a1d846 | 3442 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 3443 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e4a1d846 CML |
3444 | deemph_reg_value = 64; |
3445 | margin_reg_value = 104; | |
3446 | break; | |
bd60018a | 3447 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e4a1d846 CML |
3448 | deemph_reg_value = 64; |
3449 | margin_reg_value = 154; | |
3450 | break; | |
3451 | default: | |
3452 | return 0; | |
3453 | } | |
3454 | break; | |
bd60018a | 3455 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
e4a1d846 | 3456 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 3457 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e4a1d846 CML |
3458 | deemph_reg_value = 43; |
3459 | margin_reg_value = 154; | |
3460 | break; | |
3461 | default: | |
3462 | return 0; | |
3463 | } | |
3464 | break; | |
3465 | default: | |
3466 | return 0; | |
3467 | } | |
3468 | ||
b7fa22d8 ACO |
3469 | chv_set_phy_signal_level(encoder, deemph_reg_value, |
3470 | margin_reg_value, uniq_trans_scale); | |
e4a1d846 CML |
3471 | |
3472 | return 0; | |
3473 | } | |
3474 | ||
a4fc5ed6 | 3475 | static uint32_t |
5829975c | 3476 | gen4_signal_levels(uint8_t train_set) |
a4fc5ed6 | 3477 | { |
3cf2efb1 | 3478 | uint32_t signal_levels = 0; |
a4fc5ed6 | 3479 | |
3cf2efb1 | 3480 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 3481 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
a4fc5ed6 KP |
3482 | default: |
3483 | signal_levels |= DP_VOLTAGE_0_4; | |
3484 | break; | |
bd60018a | 3485 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
a4fc5ed6 KP |
3486 | signal_levels |= DP_VOLTAGE_0_6; |
3487 | break; | |
bd60018a | 3488 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
a4fc5ed6 KP |
3489 | signal_levels |= DP_VOLTAGE_0_8; |
3490 | break; | |
bd60018a | 3491 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
a4fc5ed6 KP |
3492 | signal_levels |= DP_VOLTAGE_1_2; |
3493 | break; | |
3494 | } | |
3cf2efb1 | 3495 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
bd60018a | 3496 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
a4fc5ed6 KP |
3497 | default: |
3498 | signal_levels |= DP_PRE_EMPHASIS_0; | |
3499 | break; | |
bd60018a | 3500 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
a4fc5ed6 KP |
3501 | signal_levels |= DP_PRE_EMPHASIS_3_5; |
3502 | break; | |
bd60018a | 3503 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
a4fc5ed6 KP |
3504 | signal_levels |= DP_PRE_EMPHASIS_6; |
3505 | break; | |
bd60018a | 3506 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
a4fc5ed6 KP |
3507 | signal_levels |= DP_PRE_EMPHASIS_9_5; |
3508 | break; | |
3509 | } | |
3510 | return signal_levels; | |
3511 | } | |
3512 | ||
e3421a18 ZW |
3513 | /* Gen6's DP voltage swing and pre-emphasis control */ |
3514 | static uint32_t | |
5829975c | 3515 | gen6_edp_signal_levels(uint8_t train_set) |
e3421a18 | 3516 | { |
3c5a62b5 YL |
3517 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
3518 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
3519 | switch (signal_levels) { | |
bd60018a SJ |
3520 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
3521 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: | |
3c5a62b5 | 3522 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; |
bd60018a | 3523 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
3c5a62b5 | 3524 | return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; |
bd60018a SJ |
3525 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
3526 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2: | |
3c5a62b5 | 3527 | return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; |
bd60018a SJ |
3528 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
3529 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: | |
3c5a62b5 | 3530 | return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; |
bd60018a SJ |
3531 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
3532 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0: | |
3c5a62b5 | 3533 | return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; |
e3421a18 | 3534 | default: |
3c5a62b5 YL |
3535 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
3536 | "0x%x\n", signal_levels); | |
3537 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; | |
e3421a18 ZW |
3538 | } |
3539 | } | |
3540 | ||
1a2eb460 KP |
3541 | /* Gen7's DP voltage swing and pre-emphasis control */ |
3542 | static uint32_t | |
5829975c | 3543 | gen7_edp_signal_levels(uint8_t train_set) |
1a2eb460 KP |
3544 | { |
3545 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | | |
3546 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
3547 | switch (signal_levels) { | |
bd60018a | 3548 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
1a2eb460 | 3549 | return EDP_LINK_TRAIN_400MV_0DB_IVB; |
bd60018a | 3550 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
1a2eb460 | 3551 | return EDP_LINK_TRAIN_400MV_3_5DB_IVB; |
bd60018a | 3552 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
1a2eb460 KP |
3553 | return EDP_LINK_TRAIN_400MV_6DB_IVB; |
3554 | ||
bd60018a | 3555 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
1a2eb460 | 3556 | return EDP_LINK_TRAIN_600MV_0DB_IVB; |
bd60018a | 3557 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
1a2eb460 KP |
3558 | return EDP_LINK_TRAIN_600MV_3_5DB_IVB; |
3559 | ||
bd60018a | 3560 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
1a2eb460 | 3561 | return EDP_LINK_TRAIN_800MV_0DB_IVB; |
bd60018a | 3562 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
1a2eb460 KP |
3563 | return EDP_LINK_TRAIN_800MV_3_5DB_IVB; |
3564 | ||
3565 | default: | |
3566 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" | |
3567 | "0x%x\n", signal_levels); | |
3568 | return EDP_LINK_TRAIN_500MV_0DB_IVB; | |
3569 | } | |
3570 | } | |
3571 | ||
94223d04 | 3572 | void |
f4eb692e | 3573 | intel_dp_set_signal_levels(struct intel_dp *intel_dp) |
f0a3424e | 3574 | { |
2f773477 | 3575 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
f0a3424e | 3576 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
8f4f2797 | 3577 | enum port port = intel_dig_port->base.port; |
f8896f5d | 3578 | uint32_t signal_levels, mask = 0; |
f0a3424e PZ |
3579 | uint8_t train_set = intel_dp->train_set[0]; |
3580 | ||
d509af6c RV |
3581 | if (IS_GEN9_LP(dev_priv) || IS_CANNONLAKE(dev_priv)) { |
3582 | signal_levels = bxt_signal_levels(intel_dp); | |
3583 | } else if (HAS_DDI(dev_priv)) { | |
f8896f5d | 3584 | signal_levels = ddi_signal_levels(intel_dp); |
d509af6c | 3585 | mask = DDI_BUF_EMP_MASK; |
920a14b2 | 3586 | } else if (IS_CHERRYVIEW(dev_priv)) { |
5829975c | 3587 | signal_levels = chv_signal_levels(intel_dp); |
11a914c2 | 3588 | } else if (IS_VALLEYVIEW(dev_priv)) { |
5829975c | 3589 | signal_levels = vlv_signal_levels(intel_dp); |
5db94019 | 3590 | } else if (IS_GEN7(dev_priv) && port == PORT_A) { |
5829975c | 3591 | signal_levels = gen7_edp_signal_levels(train_set); |
f0a3424e | 3592 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; |
5db94019 | 3593 | } else if (IS_GEN6(dev_priv) && port == PORT_A) { |
5829975c | 3594 | signal_levels = gen6_edp_signal_levels(train_set); |
f0a3424e PZ |
3595 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; |
3596 | } else { | |
5829975c | 3597 | signal_levels = gen4_signal_levels(train_set); |
f0a3424e PZ |
3598 | mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK; |
3599 | } | |
3600 | ||
96fb9f9b VK |
3601 | if (mask) |
3602 | DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels); | |
3603 | ||
3604 | DRM_DEBUG_KMS("Using vswing level %d\n", | |
3605 | train_set & DP_TRAIN_VOLTAGE_SWING_MASK); | |
3606 | DRM_DEBUG_KMS("Using pre-emphasis level %d\n", | |
3607 | (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >> | |
3608 | DP_TRAIN_PRE_EMPHASIS_SHIFT); | |
f0a3424e | 3609 | |
f4eb692e | 3610 | intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels; |
b905a915 ACO |
3611 | |
3612 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); | |
3613 | POSTING_READ(intel_dp->output_reg); | |
f0a3424e PZ |
3614 | } |
3615 | ||
94223d04 | 3616 | void |
e9c176d5 ACO |
3617 | intel_dp_program_link_training_pattern(struct intel_dp *intel_dp, |
3618 | uint8_t dp_train_pat) | |
a4fc5ed6 | 3619 | { |
174edf1f | 3620 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
90a6b7b0 VS |
3621 | struct drm_i915_private *dev_priv = |
3622 | to_i915(intel_dig_port->base.base.dev); | |
a4fc5ed6 | 3623 | |
f4eb692e | 3624 | _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat); |
47ea7542 | 3625 | |
f4eb692e | 3626 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); |
ea5b213a | 3627 | POSTING_READ(intel_dp->output_reg); |
e9c176d5 ACO |
3628 | } |
3629 | ||
94223d04 | 3630 | void intel_dp_set_idle_link_train(struct intel_dp *intel_dp) |
3ab9c637 | 3631 | { |
2f773477 | 3632 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
3ab9c637 | 3633 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
8f4f2797 | 3634 | enum port port = intel_dig_port->base.port; |
3ab9c637 ID |
3635 | uint32_t val; |
3636 | ||
4f8036a2 | 3637 | if (!HAS_DDI(dev_priv)) |
3ab9c637 ID |
3638 | return; |
3639 | ||
3640 | val = I915_READ(DP_TP_CTL(port)); | |
3641 | val &= ~DP_TP_CTL_LINK_TRAIN_MASK; | |
3642 | val |= DP_TP_CTL_LINK_TRAIN_IDLE; | |
3643 | I915_WRITE(DP_TP_CTL(port), val); | |
3644 | ||
3645 | /* | |
3646 | * On PORT_A we can have only eDP in SST mode. There the only reason | |
3647 | * we need to set idle transmission mode is to work around a HW issue | |
3648 | * where we enable the pipe while not in idle link-training mode. | |
3649 | * In this case there is requirement to wait for a minimum number of | |
3650 | * idle patterns to be sent. | |
3651 | */ | |
3652 | if (port == PORT_A) | |
3653 | return; | |
3654 | ||
a767017f CW |
3655 | if (intel_wait_for_register(dev_priv,DP_TP_STATUS(port), |
3656 | DP_TP_STATUS_IDLE_DONE, | |
3657 | DP_TP_STATUS_IDLE_DONE, | |
3658 | 1)) | |
3ab9c637 ID |
3659 | DRM_ERROR("Timed out waiting for DP idle patterns\n"); |
3660 | } | |
3661 | ||
a4fc5ed6 | 3662 | static void |
adc10304 VS |
3663 | intel_dp_link_down(struct intel_encoder *encoder, |
3664 | const struct intel_crtc_state *old_crtc_state) | |
a4fc5ed6 | 3665 | { |
adc10304 VS |
3666 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
3667 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
3668 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); | |
3669 | enum port port = encoder->port; | |
ea5b213a | 3670 | uint32_t DP = intel_dp->DP; |
a4fc5ed6 | 3671 | |
4f8036a2 | 3672 | if (WARN_ON(HAS_DDI(dev_priv))) |
c19b0669 PZ |
3673 | return; |
3674 | ||
0c33d8d7 | 3675 | if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)) |
1b39d6f3 CW |
3676 | return; |
3677 | ||
28c97730 | 3678 | DRM_DEBUG_KMS("\n"); |
32f9d658 | 3679 | |
5db94019 | 3680 | if ((IS_GEN7(dev_priv) && port == PORT_A) || |
6e266956 | 3681 | (HAS_PCH_CPT(dev_priv) && port != PORT_A)) { |
e3421a18 | 3682 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
1612c8bd | 3683 | DP |= DP_LINK_TRAIN_PAT_IDLE_CPT; |
e3421a18 | 3684 | } else { |
3b358cda | 3685 | DP &= ~DP_LINK_TRAIN_MASK; |
1612c8bd | 3686 | DP |= DP_LINK_TRAIN_PAT_IDLE; |
e3421a18 | 3687 | } |
1612c8bd | 3688 | I915_WRITE(intel_dp->output_reg, DP); |
fe255d00 | 3689 | POSTING_READ(intel_dp->output_reg); |
5eb08b69 | 3690 | |
1612c8bd VS |
3691 | DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); |
3692 | I915_WRITE(intel_dp->output_reg, DP); | |
3693 | POSTING_READ(intel_dp->output_reg); | |
3694 | ||
3695 | /* | |
3696 | * HW workaround for IBX, we need to move the port | |
3697 | * to transcoder A after disabling it to allow the | |
3698 | * matching HDMI port to be enabled on transcoder A. | |
3699 | */ | |
6e266956 | 3700 | if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) { |
0c241d5b VS |
3701 | /* |
3702 | * We get CPU/PCH FIFO underruns on the other pipe when | |
3703 | * doing the workaround. Sweep them under the rug. | |
3704 | */ | |
3705 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); | |
3706 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); | |
3707 | ||
1612c8bd VS |
3708 | /* always enable with pattern 1 (as per spec) */ |
3709 | DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK); | |
3710 | DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1; | |
3711 | I915_WRITE(intel_dp->output_reg, DP); | |
3712 | POSTING_READ(intel_dp->output_reg); | |
3713 | ||
3714 | DP &= ~DP_PORT_EN; | |
5bddd17f | 3715 | I915_WRITE(intel_dp->output_reg, DP); |
0ca09685 | 3716 | POSTING_READ(intel_dp->output_reg); |
0c241d5b | 3717 | |
0f0f74bc | 3718 | intel_wait_for_vblank_if_active(dev_priv, PIPE_A); |
0c241d5b VS |
3719 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); |
3720 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); | |
5bddd17f EA |
3721 | } |
3722 | ||
f01eca2e | 3723 | msleep(intel_dp->panel_power_down_delay); |
6fec7662 VS |
3724 | |
3725 | intel_dp->DP = DP; | |
9f2bdb00 VS |
3726 | |
3727 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { | |
3728 | pps_lock(intel_dp); | |
3729 | intel_dp->active_pipe = INVALID_PIPE; | |
3730 | pps_unlock(intel_dp); | |
3731 | } | |
a4fc5ed6 KP |
3732 | } |
3733 | ||
24e807e7 | 3734 | bool |
fe5a66f9 | 3735 | intel_dp_read_dpcd(struct intel_dp *intel_dp) |
92fd8fd1 | 3736 | { |
9f085ebb L |
3737 | if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd, |
3738 | sizeof(intel_dp->dpcd)) < 0) | |
edb39244 | 3739 | return false; /* aux transfer failed */ |
92fd8fd1 | 3740 | |
a8e98153 | 3741 | DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd); |
577c7a50 | 3742 | |
fe5a66f9 VS |
3743 | return intel_dp->dpcd[DP_DPCD_REV] != 0; |
3744 | } | |
edb39244 | 3745 | |
fe5a66f9 VS |
3746 | static bool |
3747 | intel_edp_init_dpcd(struct intel_dp *intel_dp) | |
3748 | { | |
3749 | struct drm_i915_private *dev_priv = | |
3750 | to_i915(dp_to_dig_port(intel_dp)->base.base.dev); | |
30d9aa42 | 3751 | |
fe5a66f9 VS |
3752 | /* this function is meant to be called only once */ |
3753 | WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0); | |
30d9aa42 | 3754 | |
fe5a66f9 | 3755 | if (!intel_dp_read_dpcd(intel_dp)) |
30d9aa42 SS |
3756 | return false; |
3757 | ||
84c36753 JN |
3758 | drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc, |
3759 | drm_dp_is_branch(intel_dp->dpcd)); | |
12a47a42 | 3760 | |
fe5a66f9 VS |
3761 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) |
3762 | dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] & | |
3763 | DP_NO_AUX_HANDSHAKE_LINK_TRAINING; | |
474d1ec4 | 3764 | |
77fe36ff | 3765 | intel_psr_init_dpcd(intel_dp); |
50003939 | 3766 | |
7c838e2a JN |
3767 | /* |
3768 | * Read the eDP display control registers. | |
3769 | * | |
3770 | * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in | |
3771 | * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it | |
3772 | * set, but require eDP 1.4+ detection (e.g. for supported link rates | |
3773 | * method). The display control registers should read zero if they're | |
3774 | * not supported anyway. | |
3775 | */ | |
3776 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV, | |
f7170e2e DC |
3777 | intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) == |
3778 | sizeof(intel_dp->edp_dpcd)) | |
e6ed2a1b | 3779 | DRM_DEBUG_KMS("eDP DPCD: %*ph\n", (int) sizeof(intel_dp->edp_dpcd), |
fe5a66f9 | 3780 | intel_dp->edp_dpcd); |
06ea66b6 | 3781 | |
e6ed2a1b JN |
3782 | /* Read the eDP 1.4+ supported link rates. */ |
3783 | if (intel_dp->edp_dpcd[0] >= DP_EDP_14) { | |
94ca719e | 3784 | __le16 sink_rates[DP_MAX_SUPPORTED_RATES]; |
ea2d8a42 VS |
3785 | int i; |
3786 | ||
9f085ebb L |
3787 | drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES, |
3788 | sink_rates, sizeof(sink_rates)); | |
ea2d8a42 | 3789 | |
94ca719e VS |
3790 | for (i = 0; i < ARRAY_SIZE(sink_rates); i++) { |
3791 | int val = le16_to_cpu(sink_rates[i]); | |
ea2d8a42 VS |
3792 | |
3793 | if (val == 0) | |
3794 | break; | |
3795 | ||
fd81c44e DP |
3796 | /* Value read multiplied by 200kHz gives the per-lane |
3797 | * link rate in kHz. The source rates are, however, | |
3798 | * stored in terms of LS_Clk kHz. The full conversion | |
3799 | * back to symbols is | |
3800 | * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte) | |
3801 | */ | |
af77b974 | 3802 | intel_dp->sink_rates[i] = (val * 200) / 10; |
ea2d8a42 | 3803 | } |
94ca719e | 3804 | intel_dp->num_sink_rates = i; |
fc0f8e25 | 3805 | } |
0336400e | 3806 | |
e6ed2a1b JN |
3807 | /* |
3808 | * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available, | |
3809 | * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise. | |
3810 | */ | |
68f357cb JN |
3811 | if (intel_dp->num_sink_rates) |
3812 | intel_dp->use_rate_select = true; | |
3813 | else | |
3814 | intel_dp_set_sink_rates(intel_dp); | |
3815 | ||
975ee5fc JN |
3816 | intel_dp_set_common_rates(intel_dp); |
3817 | ||
fe5a66f9 VS |
3818 | return true; |
3819 | } | |
3820 | ||
3821 | ||
3822 | static bool | |
3823 | intel_dp_get_dpcd(struct intel_dp *intel_dp) | |
3824 | { | |
27dbefb9 JN |
3825 | u8 sink_count; |
3826 | ||
fe5a66f9 VS |
3827 | if (!intel_dp_read_dpcd(intel_dp)) |
3828 | return false; | |
3829 | ||
68f357cb | 3830 | /* Don't clobber cached eDP rates. */ |
1853a9da | 3831 | if (!intel_dp_is_edp(intel_dp)) { |
68f357cb | 3832 | intel_dp_set_sink_rates(intel_dp); |
975ee5fc JN |
3833 | intel_dp_set_common_rates(intel_dp); |
3834 | } | |
68f357cb | 3835 | |
27dbefb9 | 3836 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_COUNT, &sink_count) <= 0) |
fe5a66f9 VS |
3837 | return false; |
3838 | ||
3839 | /* | |
3840 | * Sink count can change between short pulse hpd hence | |
3841 | * a member variable in intel_dp will track any changes | |
3842 | * between short pulse interrupts. | |
3843 | */ | |
27dbefb9 | 3844 | intel_dp->sink_count = DP_GET_SINK_COUNT(sink_count); |
fe5a66f9 VS |
3845 | |
3846 | /* | |
3847 | * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that | |
3848 | * a dongle is present but no display. Unless we require to know | |
3849 | * if a dongle is present or not, we don't need to update | |
3850 | * downstream port information. So, an early return here saves | |
3851 | * time from performing other operations which are not required. | |
3852 | */ | |
1853a9da | 3853 | if (!intel_dp_is_edp(intel_dp) && !intel_dp->sink_count) |
fe5a66f9 | 3854 | return false; |
0336400e | 3855 | |
c726ad01 | 3856 | if (!drm_dp_is_branch(intel_dp->dpcd)) |
edb39244 AJ |
3857 | return true; /* native DP sink */ |
3858 | ||
3859 | if (intel_dp->dpcd[DP_DPCD_REV] == 0x10) | |
3860 | return true; /* no per-port downstream info */ | |
3861 | ||
9f085ebb L |
3862 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0, |
3863 | intel_dp->downstream_ports, | |
3864 | DP_MAX_DOWNSTREAM_PORTS) < 0) | |
edb39244 AJ |
3865 | return false; /* downstream port status fetch failed */ |
3866 | ||
3867 | return true; | |
92fd8fd1 KP |
3868 | } |
3869 | ||
0e32b39c | 3870 | static bool |
c4e3170a | 3871 | intel_dp_can_mst(struct intel_dp *intel_dp) |
0e32b39c | 3872 | { |
010b9b39 | 3873 | u8 mstm_cap; |
0e32b39c | 3874 | |
4f044a88 | 3875 | if (!i915_modparams.enable_dp_mst) |
7cc96139 NS |
3876 | return false; |
3877 | ||
0e32b39c DA |
3878 | if (!intel_dp->can_mst) |
3879 | return false; | |
3880 | ||
3881 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x12) | |
3882 | return false; | |
3883 | ||
010b9b39 | 3884 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_MSTM_CAP, &mstm_cap) != 1) |
c4e3170a | 3885 | return false; |
0e32b39c | 3886 | |
010b9b39 | 3887 | return mstm_cap & DP_MST_CAP; |
c4e3170a VS |
3888 | } |
3889 | ||
3890 | static void | |
3891 | intel_dp_configure_mst(struct intel_dp *intel_dp) | |
3892 | { | |
4f044a88 | 3893 | if (!i915_modparams.enable_dp_mst) |
c4e3170a VS |
3894 | return; |
3895 | ||
3896 | if (!intel_dp->can_mst) | |
3897 | return; | |
3898 | ||
3899 | intel_dp->is_mst = intel_dp_can_mst(intel_dp); | |
3900 | ||
3901 | if (intel_dp->is_mst) | |
3902 | DRM_DEBUG_KMS("Sink is MST capable\n"); | |
3903 | else | |
3904 | DRM_DEBUG_KMS("Sink is not MST capable\n"); | |
3905 | ||
3906 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, | |
3907 | intel_dp->is_mst); | |
0e32b39c DA |
3908 | } |
3909 | ||
93313538 ML |
3910 | static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp, |
3911 | struct intel_crtc_state *crtc_state, bool disable_wa) | |
d2e216d0 | 3912 | { |
082dcc7c | 3913 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
0f0f74bc | 3914 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); |
93313538 | 3915 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
ad9dc91b | 3916 | u8 buf; |
e5a1cab5 | 3917 | int ret = 0; |
c6297843 RV |
3918 | int count = 0; |
3919 | int attempts = 10; | |
d2e216d0 | 3920 | |
082dcc7c RV |
3921 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) { |
3922 | DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n"); | |
e5a1cab5 RV |
3923 | ret = -EIO; |
3924 | goto out; | |
4373f0f2 PZ |
3925 | } |
3926 | ||
082dcc7c | 3927 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, |
e5a1cab5 | 3928 | buf & ~DP_TEST_SINK_START) < 0) { |
082dcc7c | 3929 | DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n"); |
e5a1cab5 RV |
3930 | ret = -EIO; |
3931 | goto out; | |
3932 | } | |
d2e216d0 | 3933 | |
c6297843 | 3934 | do { |
0f0f74bc | 3935 | intel_wait_for_vblank(dev_priv, intel_crtc->pipe); |
c6297843 RV |
3936 | |
3937 | if (drm_dp_dpcd_readb(&intel_dp->aux, | |
3938 | DP_TEST_SINK_MISC, &buf) < 0) { | |
3939 | ret = -EIO; | |
3940 | goto out; | |
3941 | } | |
3942 | count = buf & DP_TEST_COUNT_MASK; | |
3943 | } while (--attempts && count); | |
3944 | ||
3945 | if (attempts == 0) { | |
dc5a9037 | 3946 | DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n"); |
c6297843 RV |
3947 | ret = -ETIMEDOUT; |
3948 | } | |
3949 | ||
e5a1cab5 | 3950 | out: |
93313538 | 3951 | if (disable_wa) |
199ea381 | 3952 | hsw_enable_ips(crtc_state); |
e5a1cab5 | 3953 | return ret; |
082dcc7c RV |
3954 | } |
3955 | ||
93313538 ML |
3956 | static int intel_dp_sink_crc_start(struct intel_dp *intel_dp, |
3957 | struct intel_crtc_state *crtc_state) | |
082dcc7c RV |
3958 | { |
3959 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
0f0f74bc | 3960 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); |
93313538 | 3961 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
082dcc7c | 3962 | u8 buf; |
e5a1cab5 RV |
3963 | int ret; |
3964 | ||
082dcc7c RV |
3965 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0) |
3966 | return -EIO; | |
3967 | ||
3968 | if (!(buf & DP_TEST_CRC_SUPPORTED)) | |
3969 | return -ENOTTY; | |
3970 | ||
3971 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) | |
3972 | return -EIO; | |
3973 | ||
6d8175da | 3974 | if (buf & DP_TEST_SINK_START) { |
93313538 | 3975 | ret = intel_dp_sink_crc_stop(intel_dp, crtc_state, false); |
6d8175da RV |
3976 | if (ret) |
3977 | return ret; | |
3978 | } | |
3979 | ||
199ea381 | 3980 | hsw_disable_ips(crtc_state); |
1dda5f93 | 3981 | |
9d1a1031 | 3982 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, |
082dcc7c | 3983 | buf | DP_TEST_SINK_START) < 0) { |
199ea381 | 3984 | hsw_enable_ips(crtc_state); |
082dcc7c | 3985 | return -EIO; |
4373f0f2 PZ |
3986 | } |
3987 | ||
0f0f74bc | 3988 | intel_wait_for_vblank(dev_priv, intel_crtc->pipe); |
082dcc7c RV |
3989 | return 0; |
3990 | } | |
3991 | ||
93313538 | 3992 | int intel_dp_sink_crc(struct intel_dp *intel_dp, struct intel_crtc_state *crtc_state, u8 *crc) |
082dcc7c RV |
3993 | { |
3994 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
0f0f74bc | 3995 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); |
93313538 | 3996 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
082dcc7c | 3997 | u8 buf; |
621d4c76 | 3998 | int count, ret; |
082dcc7c | 3999 | int attempts = 6; |
082dcc7c | 4000 | |
93313538 | 4001 | ret = intel_dp_sink_crc_start(intel_dp, crtc_state); |
082dcc7c RV |
4002 | if (ret) |
4003 | return ret; | |
4004 | ||
ad9dc91b | 4005 | do { |
0f0f74bc | 4006 | intel_wait_for_vblank(dev_priv, intel_crtc->pipe); |
621d4c76 | 4007 | |
1dda5f93 | 4008 | if (drm_dp_dpcd_readb(&intel_dp->aux, |
4373f0f2 PZ |
4009 | DP_TEST_SINK_MISC, &buf) < 0) { |
4010 | ret = -EIO; | |
afe0d67e | 4011 | goto stop; |
4373f0f2 | 4012 | } |
621d4c76 | 4013 | count = buf & DP_TEST_COUNT_MASK; |
aabc95dc | 4014 | |
7e38eeff | 4015 | } while (--attempts && count == 0); |
ad9dc91b RV |
4016 | |
4017 | if (attempts == 0) { | |
7e38eeff RV |
4018 | DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n"); |
4019 | ret = -ETIMEDOUT; | |
4020 | goto stop; | |
4021 | } | |
4022 | ||
4023 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) { | |
4024 | ret = -EIO; | |
4025 | goto stop; | |
ad9dc91b | 4026 | } |
d2e216d0 | 4027 | |
afe0d67e | 4028 | stop: |
93313538 | 4029 | intel_dp_sink_crc_stop(intel_dp, crtc_state, true); |
4373f0f2 | 4030 | return ret; |
d2e216d0 RV |
4031 | } |
4032 | ||
a60f0e38 JB |
4033 | static bool |
4034 | intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) | |
4035 | { | |
010b9b39 JN |
4036 | return drm_dp_dpcd_readb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, |
4037 | sink_irq_vector) == 1; | |
a60f0e38 JB |
4038 | } |
4039 | ||
0e32b39c DA |
4040 | static bool |
4041 | intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector) | |
4042 | { | |
e8b2577c PD |
4043 | return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI, |
4044 | sink_irq_vector, DP_DPRX_ESI_LEN) == | |
4045 | DP_DPRX_ESI_LEN; | |
0e32b39c DA |
4046 | } |
4047 | ||
c5d5ab7a TP |
4048 | static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp) |
4049 | { | |
da15f7cb | 4050 | int status = 0; |
140ef138 | 4051 | int test_link_rate; |
da15f7cb MN |
4052 | uint8_t test_lane_count, test_link_bw; |
4053 | /* (DP CTS 1.2) | |
4054 | * 4.3.1.11 | |
4055 | */ | |
4056 | /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */ | |
4057 | status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT, | |
4058 | &test_lane_count); | |
4059 | ||
4060 | if (status <= 0) { | |
4061 | DRM_DEBUG_KMS("Lane count read failed\n"); | |
4062 | return DP_TEST_NAK; | |
4063 | } | |
4064 | test_lane_count &= DP_MAX_LANE_COUNT_MASK; | |
da15f7cb MN |
4065 | |
4066 | status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE, | |
4067 | &test_link_bw); | |
4068 | if (status <= 0) { | |
4069 | DRM_DEBUG_KMS("Link Rate read failed\n"); | |
4070 | return DP_TEST_NAK; | |
4071 | } | |
da15f7cb | 4072 | test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw); |
140ef138 MN |
4073 | |
4074 | /* Validate the requested link rate and lane count */ | |
4075 | if (!intel_dp_link_params_valid(intel_dp, test_link_rate, | |
4076 | test_lane_count)) | |
da15f7cb MN |
4077 | return DP_TEST_NAK; |
4078 | ||
4079 | intel_dp->compliance.test_lane_count = test_lane_count; | |
4080 | intel_dp->compliance.test_link_rate = test_link_rate; | |
4081 | ||
4082 | return DP_TEST_ACK; | |
c5d5ab7a TP |
4083 | } |
4084 | ||
4085 | static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp) | |
4086 | { | |
611032bf | 4087 | uint8_t test_pattern; |
010b9b39 | 4088 | uint8_t test_misc; |
611032bf MN |
4089 | __be16 h_width, v_height; |
4090 | int status = 0; | |
4091 | ||
4092 | /* Read the TEST_PATTERN (DP CTS 3.1.5) */ | |
010b9b39 JN |
4093 | status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN, |
4094 | &test_pattern); | |
611032bf MN |
4095 | if (status <= 0) { |
4096 | DRM_DEBUG_KMS("Test pattern read failed\n"); | |
4097 | return DP_TEST_NAK; | |
4098 | } | |
4099 | if (test_pattern != DP_COLOR_RAMP) | |
4100 | return DP_TEST_NAK; | |
4101 | ||
4102 | status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI, | |
4103 | &h_width, 2); | |
4104 | if (status <= 0) { | |
4105 | DRM_DEBUG_KMS("H Width read failed\n"); | |
4106 | return DP_TEST_NAK; | |
4107 | } | |
4108 | ||
4109 | status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI, | |
4110 | &v_height, 2); | |
4111 | if (status <= 0) { | |
4112 | DRM_DEBUG_KMS("V Height read failed\n"); | |
4113 | return DP_TEST_NAK; | |
4114 | } | |
4115 | ||
010b9b39 JN |
4116 | status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0, |
4117 | &test_misc); | |
611032bf MN |
4118 | if (status <= 0) { |
4119 | DRM_DEBUG_KMS("TEST MISC read failed\n"); | |
4120 | return DP_TEST_NAK; | |
4121 | } | |
4122 | if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB) | |
4123 | return DP_TEST_NAK; | |
4124 | if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA) | |
4125 | return DP_TEST_NAK; | |
4126 | switch (test_misc & DP_TEST_BIT_DEPTH_MASK) { | |
4127 | case DP_TEST_BIT_DEPTH_6: | |
4128 | intel_dp->compliance.test_data.bpc = 6; | |
4129 | break; | |
4130 | case DP_TEST_BIT_DEPTH_8: | |
4131 | intel_dp->compliance.test_data.bpc = 8; | |
4132 | break; | |
4133 | default: | |
4134 | return DP_TEST_NAK; | |
4135 | } | |
4136 | ||
4137 | intel_dp->compliance.test_data.video_pattern = test_pattern; | |
4138 | intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width); | |
4139 | intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height); | |
4140 | /* Set test active flag here so userspace doesn't interrupt things */ | |
4141 | intel_dp->compliance.test_active = 1; | |
4142 | ||
4143 | return DP_TEST_ACK; | |
c5d5ab7a TP |
4144 | } |
4145 | ||
4146 | static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp) | |
a60f0e38 | 4147 | { |
b48a5ba9 | 4148 | uint8_t test_result = DP_TEST_ACK; |
559be30c TP |
4149 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
4150 | struct drm_connector *connector = &intel_connector->base; | |
4151 | ||
4152 | if (intel_connector->detect_edid == NULL || | |
ac6f2e29 | 4153 | connector->edid_corrupt || |
559be30c TP |
4154 | intel_dp->aux.i2c_defer_count > 6) { |
4155 | /* Check EDID read for NACKs, DEFERs and corruption | |
4156 | * (DP CTS 1.2 Core r1.1) | |
4157 | * 4.2.2.4 : Failed EDID read, I2C_NAK | |
4158 | * 4.2.2.5 : Failed EDID read, I2C_DEFER | |
4159 | * 4.2.2.6 : EDID corruption detected | |
4160 | * Use failsafe mode for all cases | |
4161 | */ | |
4162 | if (intel_dp->aux.i2c_nack_count > 0 || | |
4163 | intel_dp->aux.i2c_defer_count > 0) | |
4164 | DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n", | |
4165 | intel_dp->aux.i2c_nack_count, | |
4166 | intel_dp->aux.i2c_defer_count); | |
c1617abc | 4167 | intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE; |
559be30c | 4168 | } else { |
f79b468e TS |
4169 | struct edid *block = intel_connector->detect_edid; |
4170 | ||
4171 | /* We have to write the checksum | |
4172 | * of the last block read | |
4173 | */ | |
4174 | block += intel_connector->detect_edid->extensions; | |
4175 | ||
010b9b39 JN |
4176 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM, |
4177 | block->checksum) <= 0) | |
559be30c TP |
4178 | DRM_DEBUG_KMS("Failed to write EDID checksum\n"); |
4179 | ||
4180 | test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE; | |
b48a5ba9 | 4181 | intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED; |
559be30c TP |
4182 | } |
4183 | ||
4184 | /* Set test active flag here so userspace doesn't interrupt things */ | |
c1617abc | 4185 | intel_dp->compliance.test_active = 1; |
559be30c | 4186 | |
c5d5ab7a TP |
4187 | return test_result; |
4188 | } | |
4189 | ||
4190 | static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp) | |
a60f0e38 | 4191 | { |
c5d5ab7a TP |
4192 | uint8_t test_result = DP_TEST_NAK; |
4193 | return test_result; | |
4194 | } | |
4195 | ||
4196 | static void intel_dp_handle_test_request(struct intel_dp *intel_dp) | |
4197 | { | |
4198 | uint8_t response = DP_TEST_NAK; | |
5ec63bbd JN |
4199 | uint8_t request = 0; |
4200 | int status; | |
c5d5ab7a | 4201 | |
5ec63bbd | 4202 | status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request); |
c5d5ab7a TP |
4203 | if (status <= 0) { |
4204 | DRM_DEBUG_KMS("Could not read test request from sink\n"); | |
4205 | goto update_status; | |
4206 | } | |
4207 | ||
5ec63bbd | 4208 | switch (request) { |
c5d5ab7a TP |
4209 | case DP_TEST_LINK_TRAINING: |
4210 | DRM_DEBUG_KMS("LINK_TRAINING test requested\n"); | |
c5d5ab7a TP |
4211 | response = intel_dp_autotest_link_training(intel_dp); |
4212 | break; | |
4213 | case DP_TEST_LINK_VIDEO_PATTERN: | |
4214 | DRM_DEBUG_KMS("TEST_PATTERN test requested\n"); | |
c5d5ab7a TP |
4215 | response = intel_dp_autotest_video_pattern(intel_dp); |
4216 | break; | |
4217 | case DP_TEST_LINK_EDID_READ: | |
4218 | DRM_DEBUG_KMS("EDID test requested\n"); | |
c5d5ab7a TP |
4219 | response = intel_dp_autotest_edid(intel_dp); |
4220 | break; | |
4221 | case DP_TEST_LINK_PHY_TEST_PATTERN: | |
4222 | DRM_DEBUG_KMS("PHY_PATTERN test requested\n"); | |
c5d5ab7a TP |
4223 | response = intel_dp_autotest_phy_pattern(intel_dp); |
4224 | break; | |
4225 | default: | |
5ec63bbd | 4226 | DRM_DEBUG_KMS("Invalid test request '%02x'\n", request); |
c5d5ab7a TP |
4227 | break; |
4228 | } | |
4229 | ||
5ec63bbd JN |
4230 | if (response & DP_TEST_ACK) |
4231 | intel_dp->compliance.test_type = request; | |
4232 | ||
c5d5ab7a | 4233 | update_status: |
5ec63bbd | 4234 | status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response); |
c5d5ab7a TP |
4235 | if (status <= 0) |
4236 | DRM_DEBUG_KMS("Could not write test response to sink\n"); | |
a60f0e38 JB |
4237 | } |
4238 | ||
0e32b39c DA |
4239 | static int |
4240 | intel_dp_check_mst_status(struct intel_dp *intel_dp) | |
4241 | { | |
4242 | bool bret; | |
4243 | ||
4244 | if (intel_dp->is_mst) { | |
e8b2577c | 4245 | u8 esi[DP_DPRX_ESI_LEN] = { 0 }; |
0e32b39c DA |
4246 | int ret = 0; |
4247 | int retry; | |
4248 | bool handled; | |
4249 | bret = intel_dp_get_sink_irq_esi(intel_dp, esi); | |
4250 | go_again: | |
4251 | if (bret == true) { | |
4252 | ||
4253 | /* check link status - esi[10] = 0x200c */ | |
19e0b4ca | 4254 | if (intel_dp->active_mst_links && |
901c2daf | 4255 | !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) { |
0e32b39c DA |
4256 | DRM_DEBUG_KMS("channel EQ not ok, retraining\n"); |
4257 | intel_dp_start_link_train(intel_dp); | |
0e32b39c DA |
4258 | intel_dp_stop_link_train(intel_dp); |
4259 | } | |
4260 | ||
6f34cc39 | 4261 | DRM_DEBUG_KMS("got esi %3ph\n", esi); |
0e32b39c DA |
4262 | ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled); |
4263 | ||
4264 | if (handled) { | |
4265 | for (retry = 0; retry < 3; retry++) { | |
4266 | int wret; | |
4267 | wret = drm_dp_dpcd_write(&intel_dp->aux, | |
4268 | DP_SINK_COUNT_ESI+1, | |
4269 | &esi[1], 3); | |
4270 | if (wret == 3) { | |
4271 | break; | |
4272 | } | |
4273 | } | |
4274 | ||
4275 | bret = intel_dp_get_sink_irq_esi(intel_dp, esi); | |
4276 | if (bret == true) { | |
6f34cc39 | 4277 | DRM_DEBUG_KMS("got esi2 %3ph\n", esi); |
0e32b39c DA |
4278 | goto go_again; |
4279 | } | |
4280 | } else | |
4281 | ret = 0; | |
4282 | ||
4283 | return ret; | |
4284 | } else { | |
4285 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
4286 | DRM_DEBUG_KMS("failed to get ESI - device may have failed\n"); | |
4287 | intel_dp->is_mst = false; | |
4288 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); | |
4289 | /* send a hotplug event */ | |
4290 | drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev); | |
4291 | } | |
4292 | } | |
4293 | return -EINVAL; | |
4294 | } | |
4295 | ||
c85d200e VS |
4296 | static bool |
4297 | intel_dp_needs_link_retrain(struct intel_dp *intel_dp) | |
4298 | { | |
4299 | u8 link_status[DP_LINK_STATUS_SIZE]; | |
4300 | ||
edb2e530 VS |
4301 | if (!intel_dp->link_trained) |
4302 | return false; | |
4303 | ||
4304 | if (!intel_dp_get_link_status(intel_dp, link_status)) | |
c85d200e | 4305 | return false; |
c85d200e VS |
4306 | |
4307 | /* | |
4308 | * Validate the cached values of intel_dp->link_rate and | |
4309 | * intel_dp->lane_count before attempting to retrain. | |
4310 | */ | |
4311 | if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate, | |
4312 | intel_dp->lane_count)) | |
4313 | return false; | |
4314 | ||
4315 | /* Retrain if Channel EQ or CR not ok */ | |
4316 | return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count); | |
4317 | } | |
4318 | ||
4319 | /* | |
4320 | * If display is now connected check links status, | |
4321 | * there has been known issues of link loss triggering | |
4322 | * long pulse. | |
4323 | * | |
4324 | * Some sinks (eg. ASUS PB287Q) seem to perform some | |
4325 | * weird HPD ping pong during modesets. So we can apparently | |
4326 | * end up with HPD going low during a modeset, and then | |
4327 | * going back up soon after. And once that happens we must | |
4328 | * retrain the link to get a picture. That's in case no | |
4329 | * userspace component reacted to intermittent HPD dip. | |
4330 | */ | |
4331 | int intel_dp_retrain_link(struct intel_encoder *encoder, | |
4332 | struct drm_modeset_acquire_ctx *ctx) | |
bfd02b3c | 4333 | { |
bfd02b3c | 4334 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
c85d200e VS |
4335 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
4336 | struct intel_connector *connector = intel_dp->attached_connector; | |
4337 | struct drm_connector_state *conn_state; | |
4338 | struct intel_crtc_state *crtc_state; | |
4339 | struct intel_crtc *crtc; | |
4340 | int ret; | |
4341 | ||
4342 | /* FIXME handle the MST connectors as well */ | |
4343 | ||
4344 | if (!connector || connector->base.status != connector_status_connected) | |
4345 | return 0; | |
4346 | ||
4347 | ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, | |
4348 | ctx); | |
4349 | if (ret) | |
4350 | return ret; | |
4351 | ||
4352 | conn_state = connector->base.state; | |
4353 | ||
4354 | crtc = to_intel_crtc(conn_state->crtc); | |
4355 | if (!crtc) | |
4356 | return 0; | |
4357 | ||
4358 | ret = drm_modeset_lock(&crtc->base.mutex, ctx); | |
4359 | if (ret) | |
4360 | return ret; | |
4361 | ||
4362 | crtc_state = to_intel_crtc_state(crtc->base.state); | |
4363 | ||
4364 | WARN_ON(!intel_crtc_has_dp_encoder(crtc_state)); | |
4365 | ||
4366 | if (!crtc_state->base.active) | |
4367 | return 0; | |
4368 | ||
4369 | if (conn_state->commit && | |
4370 | !try_wait_for_completion(&conn_state->commit->hw_done)) | |
4371 | return 0; | |
4372 | ||
4373 | if (!intel_dp_needs_link_retrain(intel_dp)) | |
4374 | return 0; | |
bfd02b3c VS |
4375 | |
4376 | /* Suppress underruns caused by re-training */ | |
4377 | intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false); | |
4378 | if (crtc->config->has_pch_encoder) | |
4379 | intel_set_pch_fifo_underrun_reporting(dev_priv, | |
4380 | intel_crtc_pch_transcoder(crtc), false); | |
4381 | ||
4382 | intel_dp_start_link_train(intel_dp); | |
4383 | intel_dp_stop_link_train(intel_dp); | |
4384 | ||
4385 | /* Keep underrun reporting disabled until things are stable */ | |
0f0f74bc | 4386 | intel_wait_for_vblank(dev_priv, crtc->pipe); |
bfd02b3c VS |
4387 | |
4388 | intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); | |
4389 | if (crtc->config->has_pch_encoder) | |
4390 | intel_set_pch_fifo_underrun_reporting(dev_priv, | |
4391 | intel_crtc_pch_transcoder(crtc), true); | |
c85d200e VS |
4392 | |
4393 | return 0; | |
bfd02b3c VS |
4394 | } |
4395 | ||
c85d200e VS |
4396 | /* |
4397 | * If display is now connected check links status, | |
4398 | * there has been known issues of link loss triggering | |
4399 | * long pulse. | |
4400 | * | |
4401 | * Some sinks (eg. ASUS PB287Q) seem to perform some | |
4402 | * weird HPD ping pong during modesets. So we can apparently | |
4403 | * end up with HPD going low during a modeset, and then | |
4404 | * going back up soon after. And once that happens we must | |
4405 | * retrain the link to get a picture. That's in case no | |
4406 | * userspace component reacted to intermittent HPD dip. | |
4407 | */ | |
4408 | static bool intel_dp_hotplug(struct intel_encoder *encoder, | |
4409 | struct intel_connector *connector) | |
5c9114d0 | 4410 | { |
c85d200e VS |
4411 | struct drm_modeset_acquire_ctx ctx; |
4412 | bool changed; | |
4413 | int ret; | |
5c9114d0 | 4414 | |
c85d200e | 4415 | changed = intel_encoder_hotplug(encoder, connector); |
5c9114d0 | 4416 | |
c85d200e | 4417 | drm_modeset_acquire_init(&ctx, 0); |
42e5e657 | 4418 | |
c85d200e VS |
4419 | for (;;) { |
4420 | ret = intel_dp_retrain_link(encoder, &ctx); | |
5c9114d0 | 4421 | |
c85d200e VS |
4422 | if (ret == -EDEADLK) { |
4423 | drm_modeset_backoff(&ctx); | |
4424 | continue; | |
4425 | } | |
5c9114d0 | 4426 | |
c85d200e VS |
4427 | break; |
4428 | } | |
d4cb3fd9 | 4429 | |
c85d200e VS |
4430 | drm_modeset_drop_locks(&ctx); |
4431 | drm_modeset_acquire_fini(&ctx); | |
4432 | WARN(ret, "Acquiring modeset locks failed with %i\n", ret); | |
bfd02b3c | 4433 | |
c85d200e | 4434 | return changed; |
5c9114d0 SS |
4435 | } |
4436 | ||
a4fc5ed6 KP |
4437 | /* |
4438 | * According to DP spec | |
4439 | * 5.1.2: | |
4440 | * 1. Read DPCD | |
4441 | * 2. Configure link according to Receiver Capabilities | |
4442 | * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 | |
4443 | * 4. Check link status on receipt of hot-plug interrupt | |
39ff747b SS |
4444 | * |
4445 | * intel_dp_short_pulse - handles short pulse interrupts | |
4446 | * when full detection is not required. | |
4447 | * Returns %true if short pulse is handled and full detection | |
4448 | * is NOT required and %false otherwise. | |
a4fc5ed6 | 4449 | */ |
39ff747b | 4450 | static bool |
5c9114d0 | 4451 | intel_dp_short_pulse(struct intel_dp *intel_dp) |
a4fc5ed6 | 4452 | { |
2f773477 | 4453 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
65fbb4e7 | 4454 | u8 sink_irq_vector = 0; |
39ff747b SS |
4455 | u8 old_sink_count = intel_dp->sink_count; |
4456 | bool ret; | |
5b215bcf | 4457 | |
4df6960e SS |
4458 | /* |
4459 | * Clearing compliance test variables to allow capturing | |
4460 | * of values for next automated test request. | |
4461 | */ | |
c1617abc | 4462 | memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance)); |
4df6960e | 4463 | |
39ff747b SS |
4464 | /* |
4465 | * Now read the DPCD to see if it's actually running | |
4466 | * If the current value of sink count doesn't match with | |
4467 | * the value that was stored earlier or dpcd read failed | |
4468 | * we need to do full detection | |
4469 | */ | |
4470 | ret = intel_dp_get_dpcd(intel_dp); | |
4471 | ||
4472 | if ((old_sink_count != intel_dp->sink_count) || !ret) { | |
4473 | /* No need to proceed if we are going to do full detect */ | |
4474 | return false; | |
59cd09e1 JB |
4475 | } |
4476 | ||
a60f0e38 JB |
4477 | /* Try to read the source of the interrupt */ |
4478 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && | |
65fbb4e7 VS |
4479 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) && |
4480 | sink_irq_vector != 0) { | |
a60f0e38 | 4481 | /* Clear interrupt source */ |
9d1a1031 JN |
4482 | drm_dp_dpcd_writeb(&intel_dp->aux, |
4483 | DP_DEVICE_SERVICE_IRQ_VECTOR, | |
4484 | sink_irq_vector); | |
a60f0e38 JB |
4485 | |
4486 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) | |
da15f7cb | 4487 | intel_dp_handle_test_request(intel_dp); |
a60f0e38 JB |
4488 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) |
4489 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); | |
4490 | } | |
4491 | ||
c85d200e VS |
4492 | /* defer to the hotplug work for link retraining if needed */ |
4493 | if (intel_dp_needs_link_retrain(intel_dp)) | |
4494 | return false; | |
42e5e657 | 4495 | |
da15f7cb MN |
4496 | if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) { |
4497 | DRM_DEBUG_KMS("Link Training Compliance Test requested\n"); | |
4498 | /* Send a Hotplug Uevent to userspace to start modeset */ | |
2f773477 | 4499 | drm_kms_helper_hotplug_event(&dev_priv->drm); |
da15f7cb | 4500 | } |
39ff747b SS |
4501 | |
4502 | return true; | |
a4fc5ed6 | 4503 | } |
a4fc5ed6 | 4504 | |
caf9ab24 | 4505 | /* XXX this is probably wrong for multiple downstream ports */ |
71ba9000 | 4506 | static enum drm_connector_status |
26d61aad | 4507 | intel_dp_detect_dpcd(struct intel_dp *intel_dp) |
71ba9000 | 4508 | { |
e393d0d6 | 4509 | struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp); |
caf9ab24 | 4510 | uint8_t *dpcd = intel_dp->dpcd; |
caf9ab24 AJ |
4511 | uint8_t type; |
4512 | ||
e393d0d6 ID |
4513 | if (lspcon->active) |
4514 | lspcon_resume(lspcon); | |
4515 | ||
caf9ab24 AJ |
4516 | if (!intel_dp_get_dpcd(intel_dp)) |
4517 | return connector_status_disconnected; | |
4518 | ||
1853a9da | 4519 | if (intel_dp_is_edp(intel_dp)) |
1034ce70 SS |
4520 | return connector_status_connected; |
4521 | ||
caf9ab24 | 4522 | /* if there's no downstream port, we're done */ |
c726ad01 | 4523 | if (!drm_dp_is_branch(dpcd)) |
26d61aad | 4524 | return connector_status_connected; |
caf9ab24 AJ |
4525 | |
4526 | /* If we're HPD-aware, SINK_COUNT changes dynamically */ | |
c9ff160b JN |
4527 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
4528 | intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { | |
9d1a1031 | 4529 | |
30d9aa42 SS |
4530 | return intel_dp->sink_count ? |
4531 | connector_status_connected : connector_status_disconnected; | |
caf9ab24 AJ |
4532 | } |
4533 | ||
c4e3170a VS |
4534 | if (intel_dp_can_mst(intel_dp)) |
4535 | return connector_status_connected; | |
4536 | ||
caf9ab24 | 4537 | /* If no HPD, poke DDC gently */ |
0b99836f | 4538 | if (drm_probe_ddc(&intel_dp->aux.ddc)) |
26d61aad | 4539 | return connector_status_connected; |
caf9ab24 AJ |
4540 | |
4541 | /* Well we tried, say unknown for unreliable port types */ | |
c9ff160b JN |
4542 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { |
4543 | type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; | |
4544 | if (type == DP_DS_PORT_TYPE_VGA || | |
4545 | type == DP_DS_PORT_TYPE_NON_EDID) | |
4546 | return connector_status_unknown; | |
4547 | } else { | |
4548 | type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & | |
4549 | DP_DWN_STRM_PORT_TYPE_MASK; | |
4550 | if (type == DP_DWN_STRM_PORT_TYPE_ANALOG || | |
4551 | type == DP_DWN_STRM_PORT_TYPE_OTHER) | |
4552 | return connector_status_unknown; | |
4553 | } | |
caf9ab24 AJ |
4554 | |
4555 | /* Anything else is out of spec, warn and ignore */ | |
4556 | DRM_DEBUG_KMS("Broken DP branch device, ignoring\n"); | |
26d61aad | 4557 | return connector_status_disconnected; |
71ba9000 AJ |
4558 | } |
4559 | ||
d410b56d CW |
4560 | static enum drm_connector_status |
4561 | edp_detect(struct intel_dp *intel_dp) | |
4562 | { | |
2f773477 | 4563 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
d410b56d CW |
4564 | enum drm_connector_status status; |
4565 | ||
1650be74 | 4566 | status = intel_panel_detect(dev_priv); |
d410b56d CW |
4567 | if (status == connector_status_unknown) |
4568 | status = connector_status_connected; | |
4569 | ||
4570 | return status; | |
4571 | } | |
4572 | ||
7533eb4f | 4573 | static bool ibx_digital_port_connected(struct intel_encoder *encoder) |
5eb08b69 | 4574 | { |
7533eb4f | 4575 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
b93433cc | 4576 | u32 bit; |
01cb9ea6 | 4577 | |
7533eb4f RV |
4578 | switch (encoder->hpd_pin) { |
4579 | case HPD_PORT_B: | |
0df53b77 JN |
4580 | bit = SDE_PORTB_HOTPLUG; |
4581 | break; | |
7533eb4f | 4582 | case HPD_PORT_C: |
0df53b77 JN |
4583 | bit = SDE_PORTC_HOTPLUG; |
4584 | break; | |
7533eb4f | 4585 | case HPD_PORT_D: |
0df53b77 JN |
4586 | bit = SDE_PORTD_HOTPLUG; |
4587 | break; | |
4588 | default: | |
7533eb4f | 4589 | MISSING_CASE(encoder->hpd_pin); |
0df53b77 JN |
4590 | return false; |
4591 | } | |
4592 | ||
4593 | return I915_READ(SDEISR) & bit; | |
4594 | } | |
4595 | ||
7533eb4f | 4596 | static bool cpt_digital_port_connected(struct intel_encoder *encoder) |
0df53b77 | 4597 | { |
7533eb4f | 4598 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
0df53b77 JN |
4599 | u32 bit; |
4600 | ||
7533eb4f RV |
4601 | switch (encoder->hpd_pin) { |
4602 | case HPD_PORT_B: | |
0df53b77 JN |
4603 | bit = SDE_PORTB_HOTPLUG_CPT; |
4604 | break; | |
7533eb4f | 4605 | case HPD_PORT_C: |
0df53b77 JN |
4606 | bit = SDE_PORTC_HOTPLUG_CPT; |
4607 | break; | |
7533eb4f | 4608 | case HPD_PORT_D: |
0df53b77 JN |
4609 | bit = SDE_PORTD_HOTPLUG_CPT; |
4610 | break; | |
93e5f0b6 | 4611 | default: |
7533eb4f | 4612 | MISSING_CASE(encoder->hpd_pin); |
93e5f0b6 VS |
4613 | return false; |
4614 | } | |
4615 | ||
4616 | return I915_READ(SDEISR) & bit; | |
4617 | } | |
4618 | ||
7533eb4f | 4619 | static bool spt_digital_port_connected(struct intel_encoder *encoder) |
93e5f0b6 | 4620 | { |
7533eb4f | 4621 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
93e5f0b6 VS |
4622 | u32 bit; |
4623 | ||
7533eb4f RV |
4624 | switch (encoder->hpd_pin) { |
4625 | case HPD_PORT_A: | |
93e5f0b6 VS |
4626 | bit = SDE_PORTA_HOTPLUG_SPT; |
4627 | break; | |
7533eb4f | 4628 | case HPD_PORT_E: |
a78695d3 JN |
4629 | bit = SDE_PORTE_HOTPLUG_SPT; |
4630 | break; | |
0df53b77 | 4631 | default: |
7533eb4f | 4632 | return cpt_digital_port_connected(encoder); |
b93433cc | 4633 | } |
1b469639 | 4634 | |
b93433cc | 4635 | return I915_READ(SDEISR) & bit; |
5eb08b69 ZW |
4636 | } |
4637 | ||
7533eb4f | 4638 | static bool g4x_digital_port_connected(struct intel_encoder *encoder) |
a4fc5ed6 | 4639 | { |
7533eb4f | 4640 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
9642c81c | 4641 | u32 bit; |
5eb08b69 | 4642 | |
7533eb4f RV |
4643 | switch (encoder->hpd_pin) { |
4644 | case HPD_PORT_B: | |
9642c81c JN |
4645 | bit = PORTB_HOTPLUG_LIVE_STATUS_G4X; |
4646 | break; | |
7533eb4f | 4647 | case HPD_PORT_C: |
9642c81c JN |
4648 | bit = PORTC_HOTPLUG_LIVE_STATUS_G4X; |
4649 | break; | |
7533eb4f | 4650 | case HPD_PORT_D: |
9642c81c JN |
4651 | bit = PORTD_HOTPLUG_LIVE_STATUS_G4X; |
4652 | break; | |
4653 | default: | |
7533eb4f | 4654 | MISSING_CASE(encoder->hpd_pin); |
9642c81c JN |
4655 | return false; |
4656 | } | |
4657 | ||
4658 | return I915_READ(PORT_HOTPLUG_STAT) & bit; | |
4659 | } | |
4660 | ||
7533eb4f | 4661 | static bool gm45_digital_port_connected(struct intel_encoder *encoder) |
9642c81c | 4662 | { |
7533eb4f | 4663 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
9642c81c JN |
4664 | u32 bit; |
4665 | ||
7533eb4f RV |
4666 | switch (encoder->hpd_pin) { |
4667 | case HPD_PORT_B: | |
0780cd36 | 4668 | bit = PORTB_HOTPLUG_LIVE_STATUS_GM45; |
9642c81c | 4669 | break; |
7533eb4f | 4670 | case HPD_PORT_C: |
0780cd36 | 4671 | bit = PORTC_HOTPLUG_LIVE_STATUS_GM45; |
9642c81c | 4672 | break; |
7533eb4f | 4673 | case HPD_PORT_D: |
0780cd36 | 4674 | bit = PORTD_HOTPLUG_LIVE_STATUS_GM45; |
9642c81c JN |
4675 | break; |
4676 | default: | |
7533eb4f | 4677 | MISSING_CASE(encoder->hpd_pin); |
9642c81c | 4678 | return false; |
a4fc5ed6 KP |
4679 | } |
4680 | ||
1d245987 | 4681 | return I915_READ(PORT_HOTPLUG_STAT) & bit; |
2a592bec DA |
4682 | } |
4683 | ||
7533eb4f | 4684 | static bool ilk_digital_port_connected(struct intel_encoder *encoder) |
93e5f0b6 | 4685 | { |
7533eb4f RV |
4686 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
4687 | ||
4688 | if (encoder->hpd_pin == HPD_PORT_A) | |
93e5f0b6 VS |
4689 | return I915_READ(DEISR) & DE_DP_A_HOTPLUG; |
4690 | else | |
7533eb4f | 4691 | return ibx_digital_port_connected(encoder); |
93e5f0b6 VS |
4692 | } |
4693 | ||
7533eb4f | 4694 | static bool snb_digital_port_connected(struct intel_encoder *encoder) |
93e5f0b6 | 4695 | { |
7533eb4f RV |
4696 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
4697 | ||
4698 | if (encoder->hpd_pin == HPD_PORT_A) | |
93e5f0b6 VS |
4699 | return I915_READ(DEISR) & DE_DP_A_HOTPLUG; |
4700 | else | |
7533eb4f | 4701 | return cpt_digital_port_connected(encoder); |
93e5f0b6 VS |
4702 | } |
4703 | ||
7533eb4f | 4704 | static bool ivb_digital_port_connected(struct intel_encoder *encoder) |
93e5f0b6 | 4705 | { |
7533eb4f RV |
4706 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
4707 | ||
4708 | if (encoder->hpd_pin == HPD_PORT_A) | |
93e5f0b6 VS |
4709 | return I915_READ(DEISR) & DE_DP_A_HOTPLUG_IVB; |
4710 | else | |
7533eb4f | 4711 | return cpt_digital_port_connected(encoder); |
93e5f0b6 VS |
4712 | } |
4713 | ||
7533eb4f | 4714 | static bool bdw_digital_port_connected(struct intel_encoder *encoder) |
93e5f0b6 | 4715 | { |
7533eb4f RV |
4716 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
4717 | ||
4718 | if (encoder->hpd_pin == HPD_PORT_A) | |
93e5f0b6 VS |
4719 | return I915_READ(GEN8_DE_PORT_ISR) & GEN8_PORT_DP_A_HOTPLUG; |
4720 | else | |
7533eb4f | 4721 | return cpt_digital_port_connected(encoder); |
93e5f0b6 VS |
4722 | } |
4723 | ||
7533eb4f | 4724 | static bool bxt_digital_port_connected(struct intel_encoder *encoder) |
e464bfde | 4725 | { |
7533eb4f | 4726 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
e464bfde JN |
4727 | u32 bit; |
4728 | ||
7533eb4f RV |
4729 | switch (encoder->hpd_pin) { |
4730 | case HPD_PORT_A: | |
e464bfde JN |
4731 | bit = BXT_DE_PORT_HP_DDIA; |
4732 | break; | |
7533eb4f | 4733 | case HPD_PORT_B: |
e464bfde JN |
4734 | bit = BXT_DE_PORT_HP_DDIB; |
4735 | break; | |
7533eb4f | 4736 | case HPD_PORT_C: |
e464bfde JN |
4737 | bit = BXT_DE_PORT_HP_DDIC; |
4738 | break; | |
4739 | default: | |
7533eb4f | 4740 | MISSING_CASE(encoder->hpd_pin); |
e464bfde JN |
4741 | return false; |
4742 | } | |
4743 | ||
4744 | return I915_READ(GEN8_DE_PORT_ISR) & bit; | |
4745 | } | |
4746 | ||
7e66bcf2 JN |
4747 | /* |
4748 | * intel_digital_port_connected - is the specified port connected? | |
7533eb4f | 4749 | * @encoder: intel_encoder |
7e66bcf2 | 4750 | * |
7533eb4f | 4751 | * Return %true if port is connected, %false otherwise. |
7e66bcf2 | 4752 | */ |
7533eb4f | 4753 | bool intel_digital_port_connected(struct intel_encoder *encoder) |
7e66bcf2 | 4754 | { |
7533eb4f RV |
4755 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
4756 | ||
93e5f0b6 VS |
4757 | if (HAS_GMCH_DISPLAY(dev_priv)) { |
4758 | if (IS_GM45(dev_priv)) | |
7533eb4f | 4759 | return gm45_digital_port_connected(encoder); |
93e5f0b6 | 4760 | else |
7533eb4f | 4761 | return g4x_digital_port_connected(encoder); |
93e5f0b6 VS |
4762 | } |
4763 | ||
4764 | if (IS_GEN5(dev_priv)) | |
7533eb4f | 4765 | return ilk_digital_port_connected(encoder); |
93e5f0b6 | 4766 | else if (IS_GEN6(dev_priv)) |
7533eb4f | 4767 | return snb_digital_port_connected(encoder); |
93e5f0b6 | 4768 | else if (IS_GEN7(dev_priv)) |
7533eb4f | 4769 | return ivb_digital_port_connected(encoder); |
93e5f0b6 | 4770 | else if (IS_GEN8(dev_priv)) |
7533eb4f | 4771 | return bdw_digital_port_connected(encoder); |
cc3f90f0 | 4772 | else if (IS_GEN9_LP(dev_priv)) |
7533eb4f | 4773 | return bxt_digital_port_connected(encoder); |
7e66bcf2 | 4774 | else |
7533eb4f | 4775 | return spt_digital_port_connected(encoder); |
7e66bcf2 JN |
4776 | } |
4777 | ||
8c241fef | 4778 | static struct edid * |
beb60608 | 4779 | intel_dp_get_edid(struct intel_dp *intel_dp) |
8c241fef | 4780 | { |
beb60608 | 4781 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
d6f24d0f | 4782 | |
9cd300e0 JN |
4783 | /* use cached edid if we have one */ |
4784 | if (intel_connector->edid) { | |
9cd300e0 JN |
4785 | /* invalid edid */ |
4786 | if (IS_ERR(intel_connector->edid)) | |
d6f24d0f JB |
4787 | return NULL; |
4788 | ||
55e9edeb | 4789 | return drm_edid_duplicate(intel_connector->edid); |
beb60608 CW |
4790 | } else |
4791 | return drm_get_edid(&intel_connector->base, | |
4792 | &intel_dp->aux.ddc); | |
4793 | } | |
8c241fef | 4794 | |
beb60608 CW |
4795 | static void |
4796 | intel_dp_set_edid(struct intel_dp *intel_dp) | |
4797 | { | |
4798 | struct intel_connector *intel_connector = intel_dp->attached_connector; | |
4799 | struct edid *edid; | |
8c241fef | 4800 | |
f21a2198 | 4801 | intel_dp_unset_edid(intel_dp); |
beb60608 CW |
4802 | edid = intel_dp_get_edid(intel_dp); |
4803 | intel_connector->detect_edid = edid; | |
4804 | ||
e6b72c94 | 4805 | intel_dp->has_audio = drm_detect_monitor_audio(edid); |
8c241fef KP |
4806 | } |
4807 | ||
beb60608 CW |
4808 | static void |
4809 | intel_dp_unset_edid(struct intel_dp *intel_dp) | |
8c241fef | 4810 | { |
beb60608 | 4811 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
8c241fef | 4812 | |
beb60608 CW |
4813 | kfree(intel_connector->detect_edid); |
4814 | intel_connector->detect_edid = NULL; | |
9cd300e0 | 4815 | |
beb60608 CW |
4816 | intel_dp->has_audio = false; |
4817 | } | |
d6f24d0f | 4818 | |
6c5ed5ae | 4819 | static int |
2f773477 | 4820 | intel_dp_long_pulse(struct intel_connector *connector) |
a9756bb5 | 4821 | { |
2f773477 VS |
4822 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); |
4823 | struct intel_dp *intel_dp = intel_attached_dp(&connector->base); | |
a9756bb5 | 4824 | enum drm_connector_status status; |
65fbb4e7 | 4825 | u8 sink_irq_vector = 0; |
a9756bb5 | 4826 | |
2f773477 | 4827 | WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); |
6c5ed5ae | 4828 | |
2f773477 | 4829 | intel_display_power_get(dev_priv, intel_dp->aux_power_domain); |
a9756bb5 | 4830 | |
d410b56d | 4831 | /* Can't disconnect eDP, but you can close the lid... */ |
1853a9da | 4832 | if (intel_dp_is_edp(intel_dp)) |
d410b56d | 4833 | status = edp_detect(intel_dp); |
7533eb4f | 4834 | else if (intel_digital_port_connected(&dp_to_dig_port(intel_dp)->base)) |
c555a81d | 4835 | status = intel_dp_detect_dpcd(intel_dp); |
a9756bb5 | 4836 | else |
c555a81d ACO |
4837 | status = connector_status_disconnected; |
4838 | ||
5cb651a7 | 4839 | if (status == connector_status_disconnected) { |
c1617abc | 4840 | memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance)); |
4df6960e | 4841 | |
0e505a08 | 4842 | if (intel_dp->is_mst) { |
4843 | DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", | |
4844 | intel_dp->is_mst, | |
4845 | intel_dp->mst_mgr.mst_state); | |
4846 | intel_dp->is_mst = false; | |
4847 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, | |
4848 | intel_dp->is_mst); | |
4849 | } | |
4850 | ||
c8c8fb33 | 4851 | goto out; |
4df6960e | 4852 | } |
a9756bb5 | 4853 | |
d7e8ef02 | 4854 | if (intel_dp->reset_link_params) { |
540b0b7f JN |
4855 | /* Initial max link lane count */ |
4856 | intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp); | |
f482984a | 4857 | |
540b0b7f JN |
4858 | /* Initial max link rate */ |
4859 | intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp); | |
d7e8ef02 MN |
4860 | |
4861 | intel_dp->reset_link_params = false; | |
4862 | } | |
f482984a | 4863 | |
fe5a66f9 VS |
4864 | intel_dp_print_rates(intel_dp); |
4865 | ||
84c36753 JN |
4866 | drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc, |
4867 | drm_dp_is_branch(intel_dp->dpcd)); | |
0e390a33 | 4868 | |
c4e3170a VS |
4869 | intel_dp_configure_mst(intel_dp); |
4870 | ||
4871 | if (intel_dp->is_mst) { | |
f21a2198 SS |
4872 | /* |
4873 | * If we are in MST mode then this connector | |
4874 | * won't appear connected or have anything | |
4875 | * with EDID on it | |
4876 | */ | |
0e32b39c DA |
4877 | status = connector_status_disconnected; |
4878 | goto out; | |
4879 | } | |
4880 | ||
4df6960e SS |
4881 | /* |
4882 | * Clearing NACK and defer counts to get their exact values | |
4883 | * while reading EDID which are required by Compliance tests | |
4884 | * 4.2.2.4 and 4.2.2.5 | |
4885 | */ | |
4886 | intel_dp->aux.i2c_nack_count = 0; | |
4887 | intel_dp->aux.i2c_defer_count = 0; | |
4888 | ||
beb60608 | 4889 | intel_dp_set_edid(intel_dp); |
2f773477 | 4890 | if (intel_dp_is_edp(intel_dp) || connector->detect_edid) |
5cb651a7 | 4891 | status = connector_status_connected; |
7d23e3c3 | 4892 | intel_dp->detect_done = true; |
c8c8fb33 | 4893 | |
09b1eb13 TP |
4894 | /* Try to read the source of the interrupt */ |
4895 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && | |
65fbb4e7 VS |
4896 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) && |
4897 | sink_irq_vector != 0) { | |
09b1eb13 TP |
4898 | /* Clear interrupt source */ |
4899 | drm_dp_dpcd_writeb(&intel_dp->aux, | |
4900 | DP_DEVICE_SERVICE_IRQ_VECTOR, | |
4901 | sink_irq_vector); | |
4902 | ||
4903 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) | |
4904 | intel_dp_handle_test_request(intel_dp); | |
4905 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) | |
4906 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); | |
4907 | } | |
4908 | ||
c8c8fb33 | 4909 | out: |
5cb651a7 | 4910 | if (status != connector_status_connected && !intel_dp->is_mst) |
f21a2198 | 4911 | intel_dp_unset_edid(intel_dp); |
7d23e3c3 | 4912 | |
2f773477 | 4913 | intel_display_power_put(dev_priv, intel_dp->aux_power_domain); |
5cb651a7 | 4914 | return status; |
f21a2198 SS |
4915 | } |
4916 | ||
6c5ed5ae ML |
4917 | static int |
4918 | intel_dp_detect(struct drm_connector *connector, | |
4919 | struct drm_modeset_acquire_ctx *ctx, | |
4920 | bool force) | |
f21a2198 SS |
4921 | { |
4922 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
6c5ed5ae | 4923 | int status = connector->status; |
f21a2198 SS |
4924 | |
4925 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
4926 | connector->base.id, connector->name); | |
4927 | ||
7d23e3c3 | 4928 | /* If full detect is not performed yet, do a full detect */ |
42e5e657 DV |
4929 | if (!intel_dp->detect_done) { |
4930 | struct drm_crtc *crtc; | |
4931 | int ret; | |
4932 | ||
4933 | crtc = connector->state->crtc; | |
4934 | if (crtc) { | |
4935 | ret = drm_modeset_lock(&crtc->mutex, ctx); | |
4936 | if (ret) | |
4937 | return ret; | |
4938 | } | |
4939 | ||
5cb651a7 | 4940 | status = intel_dp_long_pulse(intel_dp->attached_connector); |
42e5e657 | 4941 | } |
7d23e3c3 SS |
4942 | |
4943 | intel_dp->detect_done = false; | |
f21a2198 | 4944 | |
5cb651a7 | 4945 | return status; |
a4fc5ed6 KP |
4946 | } |
4947 | ||
beb60608 CW |
4948 | static void |
4949 | intel_dp_force(struct drm_connector *connector) | |
a4fc5ed6 | 4950 | { |
df0e9248 | 4951 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
beb60608 | 4952 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; |
25f78f58 | 4953 | struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); |
a4fc5ed6 | 4954 | |
beb60608 CW |
4955 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
4956 | connector->base.id, connector->name); | |
4957 | intel_dp_unset_edid(intel_dp); | |
a4fc5ed6 | 4958 | |
beb60608 CW |
4959 | if (connector->status != connector_status_connected) |
4960 | return; | |
671dedd2 | 4961 | |
5432fcaf | 4962 | intel_display_power_get(dev_priv, intel_dp->aux_power_domain); |
beb60608 CW |
4963 | |
4964 | intel_dp_set_edid(intel_dp); | |
4965 | ||
5432fcaf | 4966 | intel_display_power_put(dev_priv, intel_dp->aux_power_domain); |
beb60608 CW |
4967 | } |
4968 | ||
4969 | static int intel_dp_get_modes(struct drm_connector *connector) | |
4970 | { | |
4971 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
4972 | struct edid *edid; | |
4973 | ||
4974 | edid = intel_connector->detect_edid; | |
4975 | if (edid) { | |
4976 | int ret = intel_connector_update_modes(connector, edid); | |
4977 | if (ret) | |
4978 | return ret; | |
4979 | } | |
32f9d658 | 4980 | |
f8779fda | 4981 | /* if eDP has no EDID, fall back to fixed mode */ |
1853a9da | 4982 | if (intel_dp_is_edp(intel_attached_dp(connector)) && |
beb60608 | 4983 | intel_connector->panel.fixed_mode) { |
f8779fda | 4984 | struct drm_display_mode *mode; |
beb60608 CW |
4985 | |
4986 | mode = drm_mode_duplicate(connector->dev, | |
dd06f90e | 4987 | intel_connector->panel.fixed_mode); |
f8779fda | 4988 | if (mode) { |
32f9d658 ZW |
4989 | drm_mode_probed_add(connector, mode); |
4990 | return 1; | |
4991 | } | |
4992 | } | |
beb60608 | 4993 | |
32f9d658 | 4994 | return 0; |
a4fc5ed6 KP |
4995 | } |
4996 | ||
7a418e34 CW |
4997 | static int |
4998 | intel_dp_connector_register(struct drm_connector *connector) | |
4999 | { | |
5000 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
1ebaa0b9 CW |
5001 | int ret; |
5002 | ||
5003 | ret = intel_connector_register(connector); | |
5004 | if (ret) | |
5005 | return ret; | |
7a418e34 CW |
5006 | |
5007 | i915_debugfs_connector_add(connector); | |
5008 | ||
5009 | DRM_DEBUG_KMS("registering %s bus for %s\n", | |
5010 | intel_dp->aux.name, connector->kdev->kobj.name); | |
5011 | ||
5012 | intel_dp->aux.dev = connector->kdev; | |
5013 | return drm_dp_aux_register(&intel_dp->aux); | |
5014 | } | |
5015 | ||
c191eca1 CW |
5016 | static void |
5017 | intel_dp_connector_unregister(struct drm_connector *connector) | |
5018 | { | |
5019 | drm_dp_aux_unregister(&intel_attached_dp(connector)->aux); | |
5020 | intel_connector_unregister(connector); | |
5021 | } | |
5022 | ||
a4fc5ed6 | 5023 | static void |
73845adf | 5024 | intel_dp_connector_destroy(struct drm_connector *connector) |
a4fc5ed6 | 5025 | { |
1d508706 | 5026 | struct intel_connector *intel_connector = to_intel_connector(connector); |
aaa6fd2a | 5027 | |
10e972d3 | 5028 | kfree(intel_connector->detect_edid); |
beb60608 | 5029 | |
9cd300e0 JN |
5030 | if (!IS_ERR_OR_NULL(intel_connector->edid)) |
5031 | kfree(intel_connector->edid); | |
5032 | ||
1853a9da JN |
5033 | /* |
5034 | * Can't call intel_dp_is_edp() since the encoder may have been | |
5035 | * destroyed already. | |
5036 | */ | |
acd8db10 | 5037 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) |
1d508706 | 5038 | intel_panel_fini(&intel_connector->panel); |
aaa6fd2a | 5039 | |
a4fc5ed6 | 5040 | drm_connector_cleanup(connector); |
55f78c43 | 5041 | kfree(connector); |
a4fc5ed6 KP |
5042 | } |
5043 | ||
00c09d70 | 5044 | void intel_dp_encoder_destroy(struct drm_encoder *encoder) |
24d05927 | 5045 | { |
da63a9f2 PZ |
5046 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
5047 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
24d05927 | 5048 | |
0e32b39c | 5049 | intel_dp_mst_encoder_cleanup(intel_dig_port); |
1853a9da | 5050 | if (intel_dp_is_edp(intel_dp)) { |
bd943159 | 5051 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
951468f3 VS |
5052 | /* |
5053 | * vdd might still be enabled do to the delayed vdd off. | |
5054 | * Make sure vdd is actually turned off here. | |
5055 | */ | |
773538e8 | 5056 | pps_lock(intel_dp); |
4be73780 | 5057 | edp_panel_vdd_off_sync(intel_dp); |
773538e8 VS |
5058 | pps_unlock(intel_dp); |
5059 | ||
01527b31 CT |
5060 | if (intel_dp->edp_notifier.notifier_call) { |
5061 | unregister_reboot_notifier(&intel_dp->edp_notifier); | |
5062 | intel_dp->edp_notifier.notifier_call = NULL; | |
5063 | } | |
bd943159 | 5064 | } |
99681886 CW |
5065 | |
5066 | intel_dp_aux_fini(intel_dp); | |
5067 | ||
c8bd0e49 | 5068 | drm_encoder_cleanup(encoder); |
da63a9f2 | 5069 | kfree(intel_dig_port); |
24d05927 DV |
5070 | } |
5071 | ||
bf93ba67 | 5072 | void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder) |
07f9cd0b ID |
5073 | { |
5074 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
5075 | ||
1853a9da | 5076 | if (!intel_dp_is_edp(intel_dp)) |
07f9cd0b ID |
5077 | return; |
5078 | ||
951468f3 VS |
5079 | /* |
5080 | * vdd might still be enabled do to the delayed vdd off. | |
5081 | * Make sure vdd is actually turned off here. | |
5082 | */ | |
afa4e53a | 5083 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
773538e8 | 5084 | pps_lock(intel_dp); |
07f9cd0b | 5085 | edp_panel_vdd_off_sync(intel_dp); |
773538e8 | 5086 | pps_unlock(intel_dp); |
07f9cd0b ID |
5087 | } |
5088 | ||
20f24d77 SP |
5089 | static |
5090 | int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port, | |
5091 | u8 *an) | |
5092 | { | |
5093 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_dig_port->base.base); | |
32078b72 VS |
5094 | static const struct drm_dp_aux_msg msg = { |
5095 | .request = DP_AUX_NATIVE_WRITE, | |
5096 | .address = DP_AUX_HDCP_AKSV, | |
5097 | .size = DRM_HDCP_KSV_LEN, | |
5098 | }; | |
5099 | uint8_t txbuf[HEADER_SIZE + DRM_HDCP_KSV_LEN] = {}, rxbuf[2], reply = 0; | |
20f24d77 SP |
5100 | ssize_t dpcd_ret; |
5101 | int ret; | |
5102 | ||
5103 | /* Output An first, that's easy */ | |
5104 | dpcd_ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux, DP_AUX_HDCP_AN, | |
5105 | an, DRM_HDCP_AN_LEN); | |
5106 | if (dpcd_ret != DRM_HDCP_AN_LEN) { | |
5107 | DRM_ERROR("Failed to write An over DP/AUX (%zd)\n", dpcd_ret); | |
5108 | return dpcd_ret >= 0 ? -EIO : dpcd_ret; | |
5109 | } | |
5110 | ||
5111 | /* | |
5112 | * Since Aksv is Oh-So-Secret, we can't access it in software. So in | |
5113 | * order to get it on the wire, we need to create the AUX header as if | |
5114 | * we were writing the data, and then tickle the hardware to output the | |
5115 | * data once the header is sent out. | |
5116 | */ | |
32078b72 | 5117 | intel_dp_aux_header(txbuf, &msg); |
20f24d77 | 5118 | |
32078b72 | 5119 | ret = intel_dp_aux_xfer(intel_dp, txbuf, HEADER_SIZE + msg.size, |
8159c796 VS |
5120 | rxbuf, sizeof(rxbuf), |
5121 | DP_AUX_CH_CTL_AUX_AKSV_SELECT); | |
20f24d77 SP |
5122 | if (ret < 0) { |
5123 | DRM_ERROR("Write Aksv over DP/AUX failed (%d)\n", ret); | |
5124 | return ret; | |
5125 | } else if (ret == 0) { | |
5126 | DRM_ERROR("Aksv write over DP/AUX was empty\n"); | |
5127 | return -EIO; | |
5128 | } | |
5129 | ||
5130 | reply = (rxbuf[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK; | |
5131 | return reply == DP_AUX_NATIVE_REPLY_ACK ? 0 : -EIO; | |
5132 | } | |
5133 | ||
5134 | static int intel_dp_hdcp_read_bksv(struct intel_digital_port *intel_dig_port, | |
5135 | u8 *bksv) | |
5136 | { | |
5137 | ssize_t ret; | |
5138 | ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv, | |
5139 | DRM_HDCP_KSV_LEN); | |
5140 | if (ret != DRM_HDCP_KSV_LEN) { | |
5141 | DRM_ERROR("Read Bksv from DP/AUX failed (%zd)\n", ret); | |
5142 | return ret >= 0 ? -EIO : ret; | |
5143 | } | |
5144 | return 0; | |
5145 | } | |
5146 | ||
5147 | static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port, | |
5148 | u8 *bstatus) | |
5149 | { | |
5150 | ssize_t ret; | |
5151 | /* | |
5152 | * For some reason the HDMI and DP HDCP specs call this register | |
5153 | * definition by different names. In the HDMI spec, it's called BSTATUS, | |
5154 | * but in DP it's called BINFO. | |
5155 | */ | |
5156 | ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BINFO, | |
5157 | bstatus, DRM_HDCP_BSTATUS_LEN); | |
5158 | if (ret != DRM_HDCP_BSTATUS_LEN) { | |
5159 | DRM_ERROR("Read bstatus from DP/AUX failed (%zd)\n", ret); | |
5160 | return ret >= 0 ? -EIO : ret; | |
5161 | } | |
5162 | return 0; | |
5163 | } | |
5164 | ||
5165 | static | |
791a98dd R |
5166 | int intel_dp_hdcp_read_bcaps(struct intel_digital_port *intel_dig_port, |
5167 | u8 *bcaps) | |
20f24d77 SP |
5168 | { |
5169 | ssize_t ret; | |
791a98dd | 5170 | |
20f24d77 | 5171 | ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BCAPS, |
791a98dd | 5172 | bcaps, 1); |
20f24d77 SP |
5173 | if (ret != 1) { |
5174 | DRM_ERROR("Read bcaps from DP/AUX failed (%zd)\n", ret); | |
5175 | return ret >= 0 ? -EIO : ret; | |
5176 | } | |
791a98dd R |
5177 | |
5178 | return 0; | |
5179 | } | |
5180 | ||
5181 | static | |
5182 | int intel_dp_hdcp_repeater_present(struct intel_digital_port *intel_dig_port, | |
5183 | bool *repeater_present) | |
5184 | { | |
5185 | ssize_t ret; | |
5186 | u8 bcaps; | |
5187 | ||
5188 | ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps); | |
5189 | if (ret) | |
5190 | return ret; | |
5191 | ||
20f24d77 SP |
5192 | *repeater_present = bcaps & DP_BCAPS_REPEATER_PRESENT; |
5193 | return 0; | |
5194 | } | |
5195 | ||
5196 | static | |
5197 | int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port, | |
5198 | u8 *ri_prime) | |
5199 | { | |
5200 | ssize_t ret; | |
5201 | ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME, | |
5202 | ri_prime, DRM_HDCP_RI_LEN); | |
5203 | if (ret != DRM_HDCP_RI_LEN) { | |
5204 | DRM_ERROR("Read Ri' from DP/AUX failed (%zd)\n", ret); | |
5205 | return ret >= 0 ? -EIO : ret; | |
5206 | } | |
5207 | return 0; | |
5208 | } | |
5209 | ||
5210 | static | |
5211 | int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port, | |
5212 | bool *ksv_ready) | |
5213 | { | |
5214 | ssize_t ret; | |
5215 | u8 bstatus; | |
5216 | ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS, | |
5217 | &bstatus, 1); | |
5218 | if (ret != 1) { | |
5219 | DRM_ERROR("Read bstatus from DP/AUX failed (%zd)\n", ret); | |
5220 | return ret >= 0 ? -EIO : ret; | |
5221 | } | |
5222 | *ksv_ready = bstatus & DP_BSTATUS_READY; | |
5223 | return 0; | |
5224 | } | |
5225 | ||
5226 | static | |
5227 | int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port, | |
5228 | int num_downstream, u8 *ksv_fifo) | |
5229 | { | |
5230 | ssize_t ret; | |
5231 | int i; | |
5232 | ||
5233 | /* KSV list is read via 15 byte window (3 entries @ 5 bytes each) */ | |
5234 | for (i = 0; i < num_downstream; i += 3) { | |
5235 | size_t len = min(num_downstream - i, 3) * DRM_HDCP_KSV_LEN; | |
5236 | ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, | |
5237 | DP_AUX_HDCP_KSV_FIFO, | |
5238 | ksv_fifo + i * DRM_HDCP_KSV_LEN, | |
5239 | len); | |
5240 | if (ret != len) { | |
5241 | DRM_ERROR("Read ksv[%d] from DP/AUX failed (%zd)\n", i, | |
5242 | ret); | |
5243 | return ret >= 0 ? -EIO : ret; | |
5244 | } | |
5245 | } | |
5246 | return 0; | |
5247 | } | |
5248 | ||
5249 | static | |
5250 | int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port, | |
5251 | int i, u32 *part) | |
5252 | { | |
5253 | ssize_t ret; | |
5254 | ||
5255 | if (i >= DRM_HDCP_V_PRIME_NUM_PARTS) | |
5256 | return -EINVAL; | |
5257 | ||
5258 | ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, | |
5259 | DP_AUX_HDCP_V_PRIME(i), part, | |
5260 | DRM_HDCP_V_PRIME_PART_LEN); | |
5261 | if (ret != DRM_HDCP_V_PRIME_PART_LEN) { | |
5262 | DRM_ERROR("Read v'[%d] from DP/AUX failed (%zd)\n", i, ret); | |
5263 | return ret >= 0 ? -EIO : ret; | |
5264 | } | |
5265 | return 0; | |
5266 | } | |
5267 | ||
5268 | static | |
5269 | int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port, | |
5270 | bool enable) | |
5271 | { | |
5272 | /* Not used for single stream DisplayPort setups */ | |
5273 | return 0; | |
5274 | } | |
5275 | ||
5276 | static | |
5277 | bool intel_dp_hdcp_check_link(struct intel_digital_port *intel_dig_port) | |
5278 | { | |
5279 | ssize_t ret; | |
5280 | u8 bstatus; | |
b7fc1a9b | 5281 | |
20f24d77 SP |
5282 | ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS, |
5283 | &bstatus, 1); | |
5284 | if (ret != 1) { | |
5285 | DRM_ERROR("Read bstatus from DP/AUX failed (%zd)\n", ret); | |
b7fc1a9b | 5286 | return false; |
20f24d77 | 5287 | } |
b7fc1a9b | 5288 | |
20f24d77 SP |
5289 | return !(bstatus & (DP_BSTATUS_LINK_FAILURE | DP_BSTATUS_REAUTH_REQ)); |
5290 | } | |
5291 | ||
791a98dd R |
5292 | static |
5293 | int intel_dp_hdcp_capable(struct intel_digital_port *intel_dig_port, | |
5294 | bool *hdcp_capable) | |
5295 | { | |
5296 | ssize_t ret; | |
5297 | u8 bcaps; | |
5298 | ||
5299 | ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps); | |
5300 | if (ret) | |
5301 | return ret; | |
5302 | ||
5303 | *hdcp_capable = bcaps & DP_BCAPS_HDCP_CAPABLE; | |
5304 | return 0; | |
5305 | } | |
5306 | ||
20f24d77 SP |
5307 | static const struct intel_hdcp_shim intel_dp_hdcp_shim = { |
5308 | .write_an_aksv = intel_dp_hdcp_write_an_aksv, | |
5309 | .read_bksv = intel_dp_hdcp_read_bksv, | |
5310 | .read_bstatus = intel_dp_hdcp_read_bstatus, | |
5311 | .repeater_present = intel_dp_hdcp_repeater_present, | |
5312 | .read_ri_prime = intel_dp_hdcp_read_ri_prime, | |
5313 | .read_ksv_ready = intel_dp_hdcp_read_ksv_ready, | |
5314 | .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo, | |
5315 | .read_v_prime_part = intel_dp_hdcp_read_v_prime_part, | |
5316 | .toggle_signalling = intel_dp_hdcp_toggle_signalling, | |
5317 | .check_link = intel_dp_hdcp_check_link, | |
791a98dd | 5318 | .hdcp_capable = intel_dp_hdcp_capable, |
20f24d77 SP |
5319 | }; |
5320 | ||
49e6bc51 VS |
5321 | static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp) |
5322 | { | |
2f773477 | 5323 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
49e6bc51 VS |
5324 | |
5325 | lockdep_assert_held(&dev_priv->pps_mutex); | |
5326 | ||
5327 | if (!edp_have_panel_vdd(intel_dp)) | |
5328 | return; | |
5329 | ||
5330 | /* | |
5331 | * The VDD bit needs a power domain reference, so if the bit is | |
5332 | * already enabled when we boot or resume, grab this reference and | |
5333 | * schedule a vdd off, so we don't hold on to the reference | |
5334 | * indefinitely. | |
5335 | */ | |
5336 | DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n"); | |
5432fcaf | 5337 | intel_display_power_get(dev_priv, intel_dp->aux_power_domain); |
49e6bc51 VS |
5338 | |
5339 | edp_panel_vdd_schedule_off(intel_dp); | |
5340 | } | |
5341 | ||
9f2bdb00 VS |
5342 | static enum pipe vlv_active_pipe(struct intel_dp *intel_dp) |
5343 | { | |
5344 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); | |
5345 | ||
5346 | if ((intel_dp->DP & DP_PORT_EN) == 0) | |
5347 | return INVALID_PIPE; | |
5348 | ||
5349 | if (IS_CHERRYVIEW(dev_priv)) | |
5350 | return DP_PORT_TO_PIPE_CHV(intel_dp->DP); | |
5351 | else | |
5352 | return PORT_TO_PIPE(intel_dp->DP); | |
5353 | } | |
5354 | ||
bf93ba67 | 5355 | void intel_dp_encoder_reset(struct drm_encoder *encoder) |
6d93c0c4 | 5356 | { |
64989ca4 | 5357 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
dd75f6dd ID |
5358 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
5359 | struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp); | |
64989ca4 VS |
5360 | |
5361 | if (!HAS_DDI(dev_priv)) | |
5362 | intel_dp->DP = I915_READ(intel_dp->output_reg); | |
49e6bc51 | 5363 | |
dd75f6dd | 5364 | if (lspcon->active) |
910530c0 SS |
5365 | lspcon_resume(lspcon); |
5366 | ||
d7e8ef02 MN |
5367 | intel_dp->reset_link_params = true; |
5368 | ||
49e6bc51 VS |
5369 | pps_lock(intel_dp); |
5370 | ||
9f2bdb00 VS |
5371 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
5372 | intel_dp->active_pipe = vlv_active_pipe(intel_dp); | |
5373 | ||
1853a9da | 5374 | if (intel_dp_is_edp(intel_dp)) { |
9f2bdb00 | 5375 | /* Reinit the power sequencer, in case BIOS did something with it. */ |
46bd8383 | 5376 | intel_dp_pps_init(intel_dp); |
9f2bdb00 VS |
5377 | intel_edp_panel_vdd_sanitize(intel_dp); |
5378 | } | |
49e6bc51 VS |
5379 | |
5380 | pps_unlock(intel_dp); | |
6d93c0c4 ID |
5381 | } |
5382 | ||
a4fc5ed6 | 5383 | static const struct drm_connector_funcs intel_dp_connector_funcs = { |
beb60608 | 5384 | .force = intel_dp_force, |
a4fc5ed6 | 5385 | .fill_modes = drm_helper_probe_single_connector_modes, |
8f647a01 ML |
5386 | .atomic_get_property = intel_digital_connector_atomic_get_property, |
5387 | .atomic_set_property = intel_digital_connector_atomic_set_property, | |
7a418e34 | 5388 | .late_register = intel_dp_connector_register, |
c191eca1 | 5389 | .early_unregister = intel_dp_connector_unregister, |
73845adf | 5390 | .destroy = intel_dp_connector_destroy, |
c6f95f27 | 5391 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
8f647a01 | 5392 | .atomic_duplicate_state = intel_digital_connector_duplicate_state, |
a4fc5ed6 KP |
5393 | }; |
5394 | ||
5395 | static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { | |
6c5ed5ae | 5396 | .detect_ctx = intel_dp_detect, |
a4fc5ed6 KP |
5397 | .get_modes = intel_dp_get_modes, |
5398 | .mode_valid = intel_dp_mode_valid, | |
8f647a01 | 5399 | .atomic_check = intel_digital_connector_atomic_check, |
a4fc5ed6 KP |
5400 | }; |
5401 | ||
a4fc5ed6 | 5402 | static const struct drm_encoder_funcs intel_dp_enc_funcs = { |
6d93c0c4 | 5403 | .reset = intel_dp_encoder_reset, |
24d05927 | 5404 | .destroy = intel_dp_encoder_destroy, |
a4fc5ed6 KP |
5405 | }; |
5406 | ||
b2c5c181 | 5407 | enum irqreturn |
13cf5504 DA |
5408 | intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) |
5409 | { | |
5410 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
2f773477 | 5411 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
b2c5c181 | 5412 | enum irqreturn ret = IRQ_NONE; |
1c767b33 | 5413 | |
7a7f84cc VS |
5414 | if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) { |
5415 | /* | |
5416 | * vdd off can generate a long pulse on eDP which | |
5417 | * would require vdd on to handle it, and thus we | |
5418 | * would end up in an endless cycle of | |
5419 | * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..." | |
5420 | */ | |
5421 | DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n", | |
8f4f2797 | 5422 | port_name(intel_dig_port->base.port)); |
a8b3d52f | 5423 | return IRQ_HANDLED; |
7a7f84cc VS |
5424 | } |
5425 | ||
26fbb774 | 5426 | DRM_DEBUG_KMS("got hpd irq on port %c - %s\n", |
8f4f2797 | 5427 | port_name(intel_dig_port->base.port), |
0e32b39c | 5428 | long_hpd ? "long" : "short"); |
13cf5504 | 5429 | |
27d4efc5 | 5430 | if (long_hpd) { |
d7e8ef02 | 5431 | intel_dp->reset_link_params = true; |
27d4efc5 VS |
5432 | intel_dp->detect_done = false; |
5433 | return IRQ_NONE; | |
5434 | } | |
5435 | ||
5432fcaf | 5436 | intel_display_power_get(dev_priv, intel_dp->aux_power_domain); |
1c767b33 | 5437 | |
27d4efc5 VS |
5438 | if (intel_dp->is_mst) { |
5439 | if (intel_dp_check_mst_status(intel_dp) == -EINVAL) { | |
5440 | /* | |
5441 | * If we were in MST mode, and device is not | |
5442 | * there, get out of MST mode | |
5443 | */ | |
5444 | DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", | |
5445 | intel_dp->is_mst, intel_dp->mst_mgr.mst_state); | |
5446 | intel_dp->is_mst = false; | |
5447 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, | |
5448 | intel_dp->is_mst); | |
5449 | intel_dp->detect_done = false; | |
5450 | goto put_power; | |
0e32b39c | 5451 | } |
27d4efc5 | 5452 | } |
0e32b39c | 5453 | |
27d4efc5 | 5454 | if (!intel_dp->is_mst) { |
c85d200e | 5455 | bool handled; |
42e5e657 DV |
5456 | |
5457 | handled = intel_dp_short_pulse(intel_dp); | |
5458 | ||
20f24d77 SP |
5459 | /* Short pulse can signify loss of hdcp authentication */ |
5460 | intel_hdcp_check_link(intel_dp->attached_connector); | |
5461 | ||
42e5e657 | 5462 | if (!handled) { |
27d4efc5 VS |
5463 | intel_dp->detect_done = false; |
5464 | goto put_power; | |
39ff747b | 5465 | } |
0e32b39c | 5466 | } |
b2c5c181 DV |
5467 | |
5468 | ret = IRQ_HANDLED; | |
5469 | ||
1c767b33 | 5470 | put_power: |
5432fcaf | 5471 | intel_display_power_put(dev_priv, intel_dp->aux_power_domain); |
1c767b33 ID |
5472 | |
5473 | return ret; | |
13cf5504 DA |
5474 | } |
5475 | ||
477ec328 | 5476 | /* check the VBT to see whether the eDP is on another port */ |
7b91bf7f | 5477 | bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port) |
36e83a18 | 5478 | { |
53ce81a7 VS |
5479 | /* |
5480 | * eDP not supported on g4x. so bail out early just | |
5481 | * for a bit extra safety in case the VBT is bonkers. | |
5482 | */ | |
dd11bc10 | 5483 | if (INTEL_GEN(dev_priv) < 5) |
53ce81a7 VS |
5484 | return false; |
5485 | ||
a98d9c1d | 5486 | if (INTEL_GEN(dev_priv) < 9 && port == PORT_A) |
3b32a35b VS |
5487 | return true; |
5488 | ||
951d9efe | 5489 | return intel_bios_is_port_edp(dev_priv, port); |
36e83a18 ZY |
5490 | } |
5491 | ||
200819ab | 5492 | static void |
f684960e CW |
5493 | intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) |
5494 | { | |
8b45330a | 5495 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
68ec0736 VS |
5496 | enum port port = dp_to_dig_port(intel_dp)->base.port; |
5497 | ||
5498 | if (!IS_G4X(dev_priv) && port != PORT_A) | |
5499 | intel_attach_force_audio_property(connector); | |
8b45330a | 5500 | |
e953fd7b | 5501 | intel_attach_broadcast_rgb_property(connector); |
53b41837 | 5502 | |
1853a9da | 5503 | if (intel_dp_is_edp(intel_dp)) { |
8b45330a ML |
5504 | u32 allowed_scalers; |
5505 | ||
5506 | allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN); | |
5507 | if (!HAS_GMCH_DISPLAY(dev_priv)) | |
5508 | allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER); | |
5509 | ||
5510 | drm_connector_attach_scaling_mode_property(connector, allowed_scalers); | |
5511 | ||
eead06df | 5512 | connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT; |
8b45330a | 5513 | |
53b41837 | 5514 | } |
f684960e CW |
5515 | } |
5516 | ||
dada1a9f ID |
5517 | static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp) |
5518 | { | |
d28d4731 | 5519 | intel_dp->panel_power_off_time = ktime_get_boottime(); |
dada1a9f ID |
5520 | intel_dp->last_power_on = jiffies; |
5521 | intel_dp->last_backlight_off = jiffies; | |
5522 | } | |
5523 | ||
67a54566 | 5524 | static void |
46bd8383 | 5525 | intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq) |
67a54566 | 5526 | { |
46bd8383 | 5527 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
b0a08bec | 5528 | u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0; |
8e8232d5 | 5529 | struct pps_registers regs; |
453c5420 | 5530 | |
46bd8383 | 5531 | intel_pps_get_registers(intel_dp, ®s); |
67a54566 DV |
5532 | |
5533 | /* Workaround: Need to write PP_CONTROL with the unlock key as | |
5534 | * the very first thing. */ | |
b0a08bec | 5535 | pp_ctl = ironlake_get_pp_control(intel_dp); |
67a54566 | 5536 | |
8e8232d5 ID |
5537 | pp_on = I915_READ(regs.pp_on); |
5538 | pp_off = I915_READ(regs.pp_off); | |
b0d6a0f2 AS |
5539 | if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) && |
5540 | !HAS_PCH_ICP(dev_priv)) { | |
8e8232d5 ID |
5541 | I915_WRITE(regs.pp_ctrl, pp_ctl); |
5542 | pp_div = I915_READ(regs.pp_div); | |
b0a08bec | 5543 | } |
67a54566 DV |
5544 | |
5545 | /* Pull timing values out of registers */ | |
54648618 ID |
5546 | seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> |
5547 | PANEL_POWER_UP_DELAY_SHIFT; | |
67a54566 | 5548 | |
54648618 ID |
5549 | seq->t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> |
5550 | PANEL_LIGHT_ON_DELAY_SHIFT; | |
67a54566 | 5551 | |
54648618 ID |
5552 | seq->t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> |
5553 | PANEL_LIGHT_OFF_DELAY_SHIFT; | |
67a54566 | 5554 | |
54648618 ID |
5555 | seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> |
5556 | PANEL_POWER_DOWN_DELAY_SHIFT; | |
67a54566 | 5557 | |
b0d6a0f2 AS |
5558 | if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) || |
5559 | HAS_PCH_ICP(dev_priv)) { | |
12c8ca9c MN |
5560 | seq->t11_t12 = ((pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >> |
5561 | BXT_POWER_CYCLE_DELAY_SHIFT) * 1000; | |
b0a08bec | 5562 | } else { |
54648618 | 5563 | seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> |
67a54566 | 5564 | PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; |
b0a08bec | 5565 | } |
54648618 ID |
5566 | } |
5567 | ||
de9c1b6b ID |
5568 | static void |
5569 | intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq) | |
5570 | { | |
5571 | DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", | |
5572 | state_name, | |
5573 | seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12); | |
5574 | } | |
5575 | ||
5576 | static void | |
46bd8383 | 5577 | intel_pps_verify_state(struct intel_dp *intel_dp) |
de9c1b6b ID |
5578 | { |
5579 | struct edp_power_seq hw; | |
5580 | struct edp_power_seq *sw = &intel_dp->pps_delays; | |
5581 | ||
46bd8383 | 5582 | intel_pps_readout_hw_state(intel_dp, &hw); |
de9c1b6b ID |
5583 | |
5584 | if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 || | |
5585 | hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) { | |
5586 | DRM_ERROR("PPS state mismatch\n"); | |
5587 | intel_pps_dump_state("sw", sw); | |
5588 | intel_pps_dump_state("hw", &hw); | |
5589 | } | |
5590 | } | |
5591 | ||
54648618 | 5592 | static void |
46bd8383 | 5593 | intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp) |
54648618 | 5594 | { |
46bd8383 | 5595 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
54648618 ID |
5596 | struct edp_power_seq cur, vbt, spec, |
5597 | *final = &intel_dp->pps_delays; | |
5598 | ||
5599 | lockdep_assert_held(&dev_priv->pps_mutex); | |
5600 | ||
5601 | /* already initialized? */ | |
5602 | if (final->t11_t12 != 0) | |
5603 | return; | |
5604 | ||
46bd8383 | 5605 | intel_pps_readout_hw_state(intel_dp, &cur); |
67a54566 | 5606 | |
de9c1b6b | 5607 | intel_pps_dump_state("cur", &cur); |
67a54566 | 5608 | |
6aa23e65 | 5609 | vbt = dev_priv->vbt.edp.pps; |
c99a259b MN |
5610 | /* On Toshiba Satellite P50-C-18C system the VBT T12 delay |
5611 | * of 500ms appears to be too short. Ocassionally the panel | |
5612 | * just fails to power back on. Increasing the delay to 800ms | |
5613 | * seems sufficient to avoid this problem. | |
5614 | */ | |
5615 | if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) { | |
7313f5a9 | 5616 | vbt.t11_t12 = max_t(u16, vbt.t11_t12, 1300 * 10); |
c99a259b MN |
5617 | DRM_DEBUG_KMS("Increasing T12 panel delay as per the quirk to %d\n", |
5618 | vbt.t11_t12); | |
5619 | } | |
770a17a5 MN |
5620 | /* T11_T12 delay is special and actually in units of 100ms, but zero |
5621 | * based in the hw (so we need to add 100 ms). But the sw vbt | |
5622 | * table multiplies it with 1000 to make it in units of 100usec, | |
5623 | * too. */ | |
5624 | vbt.t11_t12 += 100 * 10; | |
67a54566 DV |
5625 | |
5626 | /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of | |
5627 | * our hw here, which are all in 100usec. */ | |
5628 | spec.t1_t3 = 210 * 10; | |
5629 | spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */ | |
5630 | spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ | |
5631 | spec.t10 = 500 * 10; | |
5632 | /* This one is special and actually in units of 100ms, but zero | |
5633 | * based in the hw (so we need to add 100 ms). But the sw vbt | |
5634 | * table multiplies it with 1000 to make it in units of 100usec, | |
5635 | * too. */ | |
5636 | spec.t11_t12 = (510 + 100) * 10; | |
5637 | ||
de9c1b6b | 5638 | intel_pps_dump_state("vbt", &vbt); |
67a54566 DV |
5639 | |
5640 | /* Use the max of the register settings and vbt. If both are | |
5641 | * unset, fall back to the spec limits. */ | |
36b5f425 | 5642 | #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \ |
67a54566 DV |
5643 | spec.field : \ |
5644 | max(cur.field, vbt.field)) | |
5645 | assign_final(t1_t3); | |
5646 | assign_final(t8); | |
5647 | assign_final(t9); | |
5648 | assign_final(t10); | |
5649 | assign_final(t11_t12); | |
5650 | #undef assign_final | |
5651 | ||
36b5f425 | 5652 | #define get_delay(field) (DIV_ROUND_UP(final->field, 10)) |
67a54566 DV |
5653 | intel_dp->panel_power_up_delay = get_delay(t1_t3); |
5654 | intel_dp->backlight_on_delay = get_delay(t8); | |
5655 | intel_dp->backlight_off_delay = get_delay(t9); | |
5656 | intel_dp->panel_power_down_delay = get_delay(t10); | |
5657 | intel_dp->panel_power_cycle_delay = get_delay(t11_t12); | |
5658 | #undef get_delay | |
5659 | ||
f30d26e4 JN |
5660 | DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", |
5661 | intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, | |
5662 | intel_dp->panel_power_cycle_delay); | |
5663 | ||
5664 | DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", | |
5665 | intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); | |
de9c1b6b ID |
5666 | |
5667 | /* | |
5668 | * We override the HW backlight delays to 1 because we do manual waits | |
5669 | * on them. For T8, even BSpec recommends doing it. For T9, if we | |
5670 | * don't do this, we'll end up waiting for the backlight off delay | |
5671 | * twice: once when we do the manual sleep, and once when we disable | |
5672 | * the panel and wait for the PP_STATUS bit to become zero. | |
5673 | */ | |
5674 | final->t8 = 1; | |
5675 | final->t9 = 1; | |
5643205c ID |
5676 | |
5677 | /* | |
5678 | * HW has only a 100msec granularity for t11_t12 so round it up | |
5679 | * accordingly. | |
5680 | */ | |
5681 | final->t11_t12 = roundup(final->t11_t12, 100 * 10); | |
f30d26e4 JN |
5682 | } |
5683 | ||
5684 | static void | |
46bd8383 | 5685 | intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp, |
5d5ab2d2 | 5686 | bool force_disable_vdd) |
f30d26e4 | 5687 | { |
46bd8383 | 5688 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
453c5420 | 5689 | u32 pp_on, pp_off, pp_div, port_sel = 0; |
e7dc33f3 | 5690 | int div = dev_priv->rawclk_freq / 1000; |
8e8232d5 | 5691 | struct pps_registers regs; |
8f4f2797 | 5692 | enum port port = dp_to_dig_port(intel_dp)->base.port; |
36b5f425 | 5693 | const struct edp_power_seq *seq = &intel_dp->pps_delays; |
453c5420 | 5694 | |
e39b999a | 5695 | lockdep_assert_held(&dev_priv->pps_mutex); |
453c5420 | 5696 | |
46bd8383 | 5697 | intel_pps_get_registers(intel_dp, ®s); |
453c5420 | 5698 | |
5d5ab2d2 VS |
5699 | /* |
5700 | * On some VLV machines the BIOS can leave the VDD | |
e7f2af78 | 5701 | * enabled even on power sequencers which aren't |
5d5ab2d2 VS |
5702 | * hooked up to any port. This would mess up the |
5703 | * power domain tracking the first time we pick | |
5704 | * one of these power sequencers for use since | |
5705 | * edp_panel_vdd_on() would notice that the VDD was | |
5706 | * already on and therefore wouldn't grab the power | |
5707 | * domain reference. Disable VDD first to avoid this. | |
5708 | * This also avoids spuriously turning the VDD on as | |
e7f2af78 | 5709 | * soon as the new power sequencer gets initialized. |
5d5ab2d2 VS |
5710 | */ |
5711 | if (force_disable_vdd) { | |
5712 | u32 pp = ironlake_get_pp_control(intel_dp); | |
5713 | ||
5714 | WARN(pp & PANEL_POWER_ON, "Panel power already on\n"); | |
5715 | ||
5716 | if (pp & EDP_FORCE_VDD) | |
5717 | DRM_DEBUG_KMS("VDD already on, disabling first\n"); | |
5718 | ||
5719 | pp &= ~EDP_FORCE_VDD; | |
5720 | ||
5721 | I915_WRITE(regs.pp_ctrl, pp); | |
5722 | } | |
5723 | ||
f30d26e4 | 5724 | pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) | |
de9c1b6b ID |
5725 | (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT); |
5726 | pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) | | |
f30d26e4 | 5727 | (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT); |
67a54566 DV |
5728 | /* Compute the divisor for the pp clock, simply match the Bspec |
5729 | * formula. */ | |
b0d6a0f2 AS |
5730 | if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) || |
5731 | HAS_PCH_ICP(dev_priv)) { | |
8e8232d5 | 5732 | pp_div = I915_READ(regs.pp_ctrl); |
b0a08bec | 5733 | pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK; |
12c8ca9c | 5734 | pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) |
b0a08bec VK |
5735 | << BXT_POWER_CYCLE_DELAY_SHIFT); |
5736 | } else { | |
5737 | pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT; | |
5738 | pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) | |
5739 | << PANEL_POWER_CYCLE_DELAY_SHIFT); | |
5740 | } | |
67a54566 DV |
5741 | |
5742 | /* Haswell doesn't have any port selection bits for the panel | |
5743 | * power sequencer any more. */ | |
920a14b2 | 5744 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
ad933b56 | 5745 | port_sel = PANEL_PORT_SELECT_VLV(port); |
6e266956 | 5746 | } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) { |
ad933b56 | 5747 | if (port == PORT_A) |
a24c144c | 5748 | port_sel = PANEL_PORT_SELECT_DPA; |
67a54566 | 5749 | else |
a24c144c | 5750 | port_sel = PANEL_PORT_SELECT_DPD; |
67a54566 DV |
5751 | } |
5752 | ||
453c5420 JB |
5753 | pp_on |= port_sel; |
5754 | ||
8e8232d5 ID |
5755 | I915_WRITE(regs.pp_on, pp_on); |
5756 | I915_WRITE(regs.pp_off, pp_off); | |
b0d6a0f2 AS |
5757 | if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) || |
5758 | HAS_PCH_ICP(dev_priv)) | |
8e8232d5 | 5759 | I915_WRITE(regs.pp_ctrl, pp_div); |
b0a08bec | 5760 | else |
8e8232d5 | 5761 | I915_WRITE(regs.pp_div, pp_div); |
67a54566 | 5762 | |
67a54566 | 5763 | DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", |
8e8232d5 ID |
5764 | I915_READ(regs.pp_on), |
5765 | I915_READ(regs.pp_off), | |
b0d6a0f2 AS |
5766 | (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) || |
5767 | HAS_PCH_ICP(dev_priv)) ? | |
8e8232d5 ID |
5768 | (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) : |
5769 | I915_READ(regs.pp_div)); | |
f684960e CW |
5770 | } |
5771 | ||
46bd8383 | 5772 | static void intel_dp_pps_init(struct intel_dp *intel_dp) |
335f752b | 5773 | { |
46bd8383 | 5774 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
920a14b2 TU |
5775 | |
5776 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { | |
335f752b ID |
5777 | vlv_initial_power_sequencer_setup(intel_dp); |
5778 | } else { | |
46bd8383 VS |
5779 | intel_dp_init_panel_power_sequencer(intel_dp); |
5780 | intel_dp_init_panel_power_sequencer_registers(intel_dp, false); | |
335f752b ID |
5781 | } |
5782 | } | |
5783 | ||
b33a2815 VK |
5784 | /** |
5785 | * intel_dp_set_drrs_state - program registers for RR switch to take effect | |
5423adf1 | 5786 | * @dev_priv: i915 device |
e896402c | 5787 | * @crtc_state: a pointer to the active intel_crtc_state |
b33a2815 VK |
5788 | * @refresh_rate: RR to be programmed |
5789 | * | |
5790 | * This function gets called when refresh rate (RR) has to be changed from | |
5791 | * one frequency to another. Switches can be between high and low RR | |
5792 | * supported by the panel or to any other RR based on media playback (in | |
5793 | * this case, RR value needs to be passed from user space). | |
5794 | * | |
5795 | * The caller of this function needs to take a lock on dev_priv->drrs. | |
5796 | */ | |
85cb48a1 | 5797 | static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv, |
5f88a9c6 | 5798 | const struct intel_crtc_state *crtc_state, |
85cb48a1 | 5799 | int refresh_rate) |
439d7ac0 | 5800 | { |
439d7ac0 | 5801 | struct intel_encoder *encoder; |
96178eeb VK |
5802 | struct intel_digital_port *dig_port = NULL; |
5803 | struct intel_dp *intel_dp = dev_priv->drrs.dp; | |
85cb48a1 | 5804 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
96178eeb | 5805 | enum drrs_refresh_rate_type index = DRRS_HIGH_RR; |
439d7ac0 PB |
5806 | |
5807 | if (refresh_rate <= 0) { | |
5808 | DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n"); | |
5809 | return; | |
5810 | } | |
5811 | ||
96178eeb VK |
5812 | if (intel_dp == NULL) { |
5813 | DRM_DEBUG_KMS("DRRS not supported.\n"); | |
439d7ac0 PB |
5814 | return; |
5815 | } | |
5816 | ||
96178eeb VK |
5817 | dig_port = dp_to_dig_port(intel_dp); |
5818 | encoder = &dig_port->base; | |
439d7ac0 PB |
5819 | |
5820 | if (!intel_crtc) { | |
5821 | DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n"); | |
5822 | return; | |
5823 | } | |
5824 | ||
96178eeb | 5825 | if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) { |
439d7ac0 PB |
5826 | DRM_DEBUG_KMS("Only Seamless DRRS supported.\n"); |
5827 | return; | |
5828 | } | |
5829 | ||
96178eeb VK |
5830 | if (intel_dp->attached_connector->panel.downclock_mode->vrefresh == |
5831 | refresh_rate) | |
439d7ac0 PB |
5832 | index = DRRS_LOW_RR; |
5833 | ||
96178eeb | 5834 | if (index == dev_priv->drrs.refresh_rate_type) { |
439d7ac0 PB |
5835 | DRM_DEBUG_KMS( |
5836 | "DRRS requested for previously set RR...ignoring\n"); | |
5837 | return; | |
5838 | } | |
5839 | ||
85cb48a1 | 5840 | if (!crtc_state->base.active) { |
439d7ac0 PB |
5841 | DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n"); |
5842 | return; | |
5843 | } | |
5844 | ||
85cb48a1 | 5845 | if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) { |
a4c30b1d VK |
5846 | switch (index) { |
5847 | case DRRS_HIGH_RR: | |
5848 | intel_dp_set_m_n(intel_crtc, M1_N1); | |
5849 | break; | |
5850 | case DRRS_LOW_RR: | |
5851 | intel_dp_set_m_n(intel_crtc, M2_N2); | |
5852 | break; | |
5853 | case DRRS_MAX_RR: | |
5854 | default: | |
5855 | DRM_ERROR("Unsupported refreshrate type\n"); | |
5856 | } | |
85cb48a1 ML |
5857 | } else if (INTEL_GEN(dev_priv) > 6) { |
5858 | i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder); | |
649636ef | 5859 | u32 val; |
a4c30b1d | 5860 | |
649636ef | 5861 | val = I915_READ(reg); |
439d7ac0 | 5862 | if (index > DRRS_HIGH_RR) { |
85cb48a1 | 5863 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
6fa7aec1 VK |
5864 | val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV; |
5865 | else | |
5866 | val |= PIPECONF_EDP_RR_MODE_SWITCH; | |
439d7ac0 | 5867 | } else { |
85cb48a1 | 5868 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
6fa7aec1 VK |
5869 | val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV; |
5870 | else | |
5871 | val &= ~PIPECONF_EDP_RR_MODE_SWITCH; | |
439d7ac0 PB |
5872 | } |
5873 | I915_WRITE(reg, val); | |
5874 | } | |
5875 | ||
4e9ac947 VK |
5876 | dev_priv->drrs.refresh_rate_type = index; |
5877 | ||
5878 | DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate); | |
5879 | } | |
5880 | ||
b33a2815 VK |
5881 | /** |
5882 | * intel_edp_drrs_enable - init drrs struct if supported | |
5883 | * @intel_dp: DP struct | |
5423adf1 | 5884 | * @crtc_state: A pointer to the active crtc state. |
b33a2815 VK |
5885 | * |
5886 | * Initializes frontbuffer_bits and drrs.dp | |
5887 | */ | |
85cb48a1 | 5888 | void intel_edp_drrs_enable(struct intel_dp *intel_dp, |
5f88a9c6 | 5889 | const struct intel_crtc_state *crtc_state) |
c395578e | 5890 | { |
2f773477 | 5891 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
c395578e | 5892 | |
85cb48a1 | 5893 | if (!crtc_state->has_drrs) { |
c395578e VK |
5894 | DRM_DEBUG_KMS("Panel doesn't support DRRS\n"); |
5895 | return; | |
5896 | } | |
5897 | ||
da83ef85 RS |
5898 | if (dev_priv->psr.enabled) { |
5899 | DRM_DEBUG_KMS("PSR enabled. Not enabling DRRS.\n"); | |
5900 | return; | |
5901 | } | |
5902 | ||
c395578e VK |
5903 | mutex_lock(&dev_priv->drrs.mutex); |
5904 | if (WARN_ON(dev_priv->drrs.dp)) { | |
5905 | DRM_ERROR("DRRS already enabled\n"); | |
5906 | goto unlock; | |
5907 | } | |
5908 | ||
5909 | dev_priv->drrs.busy_frontbuffer_bits = 0; | |
5910 | ||
5911 | dev_priv->drrs.dp = intel_dp; | |
5912 | ||
5913 | unlock: | |
5914 | mutex_unlock(&dev_priv->drrs.mutex); | |
5915 | } | |
5916 | ||
b33a2815 VK |
5917 | /** |
5918 | * intel_edp_drrs_disable - Disable DRRS | |
5919 | * @intel_dp: DP struct | |
5423adf1 | 5920 | * @old_crtc_state: Pointer to old crtc_state. |
b33a2815 VK |
5921 | * |
5922 | */ | |
85cb48a1 | 5923 | void intel_edp_drrs_disable(struct intel_dp *intel_dp, |
5f88a9c6 | 5924 | const struct intel_crtc_state *old_crtc_state) |
c395578e | 5925 | { |
2f773477 | 5926 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
c395578e | 5927 | |
85cb48a1 | 5928 | if (!old_crtc_state->has_drrs) |
c395578e VK |
5929 | return; |
5930 | ||
5931 | mutex_lock(&dev_priv->drrs.mutex); | |
5932 | if (!dev_priv->drrs.dp) { | |
5933 | mutex_unlock(&dev_priv->drrs.mutex); | |
5934 | return; | |
5935 | } | |
5936 | ||
5937 | if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) | |
85cb48a1 ML |
5938 | intel_dp_set_drrs_state(dev_priv, old_crtc_state, |
5939 | intel_dp->attached_connector->panel.fixed_mode->vrefresh); | |
c395578e VK |
5940 | |
5941 | dev_priv->drrs.dp = NULL; | |
5942 | mutex_unlock(&dev_priv->drrs.mutex); | |
5943 | ||
5944 | cancel_delayed_work_sync(&dev_priv->drrs.work); | |
5945 | } | |
5946 | ||
4e9ac947 VK |
5947 | static void intel_edp_drrs_downclock_work(struct work_struct *work) |
5948 | { | |
5949 | struct drm_i915_private *dev_priv = | |
5950 | container_of(work, typeof(*dev_priv), drrs.work.work); | |
5951 | struct intel_dp *intel_dp; | |
5952 | ||
5953 | mutex_lock(&dev_priv->drrs.mutex); | |
5954 | ||
5955 | intel_dp = dev_priv->drrs.dp; | |
5956 | ||
5957 | if (!intel_dp) | |
5958 | goto unlock; | |
5959 | ||
439d7ac0 | 5960 | /* |
4e9ac947 VK |
5961 | * The delayed work can race with an invalidate hence we need to |
5962 | * recheck. | |
439d7ac0 PB |
5963 | */ |
5964 | ||
4e9ac947 VK |
5965 | if (dev_priv->drrs.busy_frontbuffer_bits) |
5966 | goto unlock; | |
439d7ac0 | 5967 | |
85cb48a1 ML |
5968 | if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) { |
5969 | struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc; | |
5970 | ||
5971 | intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config, | |
5972 | intel_dp->attached_connector->panel.downclock_mode->vrefresh); | |
5973 | } | |
439d7ac0 | 5974 | |
4e9ac947 | 5975 | unlock: |
4e9ac947 | 5976 | mutex_unlock(&dev_priv->drrs.mutex); |
439d7ac0 PB |
5977 | } |
5978 | ||
b33a2815 | 5979 | /** |
0ddfd203 | 5980 | * intel_edp_drrs_invalidate - Disable Idleness DRRS |
5748b6a1 | 5981 | * @dev_priv: i915 device |
b33a2815 VK |
5982 | * @frontbuffer_bits: frontbuffer plane tracking bits |
5983 | * | |
0ddfd203 R |
5984 | * This function gets called everytime rendering on the given planes start. |
5985 | * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR). | |
b33a2815 VK |
5986 | * |
5987 | * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. | |
5988 | */ | |
5748b6a1 CW |
5989 | void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv, |
5990 | unsigned int frontbuffer_bits) | |
a93fad0f | 5991 | { |
a93fad0f VK |
5992 | struct drm_crtc *crtc; |
5993 | enum pipe pipe; | |
5994 | ||
9da7d693 | 5995 | if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) |
a93fad0f VK |
5996 | return; |
5997 | ||
88f933a8 | 5998 | cancel_delayed_work(&dev_priv->drrs.work); |
3954e733 | 5999 | |
a93fad0f | 6000 | mutex_lock(&dev_priv->drrs.mutex); |
9da7d693 DV |
6001 | if (!dev_priv->drrs.dp) { |
6002 | mutex_unlock(&dev_priv->drrs.mutex); | |
6003 | return; | |
6004 | } | |
6005 | ||
a93fad0f VK |
6006 | crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc; |
6007 | pipe = to_intel_crtc(crtc)->pipe; | |
6008 | ||
c1d038c6 DV |
6009 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); |
6010 | dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits; | |
6011 | ||
0ddfd203 | 6012 | /* invalidate means busy screen hence upclock */ |
c1d038c6 | 6013 | if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) |
85cb48a1 ML |
6014 | intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config, |
6015 | dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh); | |
a93fad0f | 6016 | |
a93fad0f VK |
6017 | mutex_unlock(&dev_priv->drrs.mutex); |
6018 | } | |
6019 | ||
b33a2815 | 6020 | /** |
0ddfd203 | 6021 | * intel_edp_drrs_flush - Restart Idleness DRRS |
5748b6a1 | 6022 | * @dev_priv: i915 device |
b33a2815 VK |
6023 | * @frontbuffer_bits: frontbuffer plane tracking bits |
6024 | * | |
0ddfd203 R |
6025 | * This function gets called every time rendering on the given planes has |
6026 | * completed or flip on a crtc is completed. So DRRS should be upclocked | |
6027 | * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again, | |
6028 | * if no other planes are dirty. | |
b33a2815 VK |
6029 | * |
6030 | * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. | |
6031 | */ | |
5748b6a1 CW |
6032 | void intel_edp_drrs_flush(struct drm_i915_private *dev_priv, |
6033 | unsigned int frontbuffer_bits) | |
a93fad0f | 6034 | { |
a93fad0f VK |
6035 | struct drm_crtc *crtc; |
6036 | enum pipe pipe; | |
6037 | ||
9da7d693 | 6038 | if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) |
a93fad0f VK |
6039 | return; |
6040 | ||
88f933a8 | 6041 | cancel_delayed_work(&dev_priv->drrs.work); |
3954e733 | 6042 | |
a93fad0f | 6043 | mutex_lock(&dev_priv->drrs.mutex); |
9da7d693 DV |
6044 | if (!dev_priv->drrs.dp) { |
6045 | mutex_unlock(&dev_priv->drrs.mutex); | |
6046 | return; | |
6047 | } | |
6048 | ||
a93fad0f VK |
6049 | crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc; |
6050 | pipe = to_intel_crtc(crtc)->pipe; | |
c1d038c6 DV |
6051 | |
6052 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); | |
a93fad0f VK |
6053 | dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits; |
6054 | ||
0ddfd203 | 6055 | /* flush means busy screen hence upclock */ |
c1d038c6 | 6056 | if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) |
85cb48a1 ML |
6057 | intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config, |
6058 | dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh); | |
0ddfd203 R |
6059 | |
6060 | /* | |
6061 | * flush also means no more activity hence schedule downclock, if all | |
6062 | * other fbs are quiescent too | |
6063 | */ | |
6064 | if (!dev_priv->drrs.busy_frontbuffer_bits) | |
a93fad0f VK |
6065 | schedule_delayed_work(&dev_priv->drrs.work, |
6066 | msecs_to_jiffies(1000)); | |
6067 | mutex_unlock(&dev_priv->drrs.mutex); | |
6068 | } | |
6069 | ||
b33a2815 VK |
6070 | /** |
6071 | * DOC: Display Refresh Rate Switching (DRRS) | |
6072 | * | |
6073 | * Display Refresh Rate Switching (DRRS) is a power conservation feature | |
6074 | * which enables swtching between low and high refresh rates, | |
6075 | * dynamically, based on the usage scenario. This feature is applicable | |
6076 | * for internal panels. | |
6077 | * | |
6078 | * Indication that the panel supports DRRS is given by the panel EDID, which | |
6079 | * would list multiple refresh rates for one resolution. | |
6080 | * | |
6081 | * DRRS is of 2 types - static and seamless. | |
6082 | * Static DRRS involves changing refresh rate (RR) by doing a full modeset | |
6083 | * (may appear as a blink on screen) and is used in dock-undock scenario. | |
6084 | * Seamless DRRS involves changing RR without any visual effect to the user | |
6085 | * and can be used during normal system usage. This is done by programming | |
6086 | * certain registers. | |
6087 | * | |
6088 | * Support for static/seamless DRRS may be indicated in the VBT based on | |
6089 | * inputs from the panel spec. | |
6090 | * | |
6091 | * DRRS saves power by switching to low RR based on usage scenarios. | |
6092 | * | |
2e7a5701 DV |
6093 | * The implementation is based on frontbuffer tracking implementation. When |
6094 | * there is a disturbance on the screen triggered by user activity or a periodic | |
6095 | * system activity, DRRS is disabled (RR is changed to high RR). When there is | |
6096 | * no movement on screen, after a timeout of 1 second, a switch to low RR is | |
6097 | * made. | |
6098 | * | |
6099 | * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate() | |
6100 | * and intel_edp_drrs_flush() are called. | |
b33a2815 VK |
6101 | * |
6102 | * DRRS can be further extended to support other internal panels and also | |
6103 | * the scenario of video playback wherein RR is set based on the rate | |
6104 | * requested by userspace. | |
6105 | */ | |
6106 | ||
6107 | /** | |
6108 | * intel_dp_drrs_init - Init basic DRRS work and mutex. | |
2f773477 | 6109 | * @connector: eDP connector |
b33a2815 VK |
6110 | * @fixed_mode: preferred mode of panel |
6111 | * | |
6112 | * This function is called only once at driver load to initialize basic | |
6113 | * DRRS stuff. | |
6114 | * | |
6115 | * Returns: | |
6116 | * Downclock mode if panel supports it, else return NULL. | |
6117 | * DRRS support is determined by the presence of downclock mode (apart | |
6118 | * from VBT setting). | |
6119 | */ | |
4f9db5b5 | 6120 | static struct drm_display_mode * |
2f773477 VS |
6121 | intel_dp_drrs_init(struct intel_connector *connector, |
6122 | struct drm_display_mode *fixed_mode) | |
4f9db5b5 | 6123 | { |
2f773477 | 6124 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); |
4f9db5b5 PB |
6125 | struct drm_display_mode *downclock_mode = NULL; |
6126 | ||
9da7d693 DV |
6127 | INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work); |
6128 | mutex_init(&dev_priv->drrs.mutex); | |
6129 | ||
dd11bc10 | 6130 | if (INTEL_GEN(dev_priv) <= 6) { |
4f9db5b5 PB |
6131 | DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n"); |
6132 | return NULL; | |
6133 | } | |
6134 | ||
6135 | if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) { | |
4079b8d1 | 6136 | DRM_DEBUG_KMS("VBT doesn't support DRRS\n"); |
4f9db5b5 PB |
6137 | return NULL; |
6138 | } | |
6139 | ||
2f773477 VS |
6140 | downclock_mode = intel_find_panel_downclock(dev_priv, fixed_mode, |
6141 | &connector->base); | |
4f9db5b5 PB |
6142 | |
6143 | if (!downclock_mode) { | |
a1d26342 | 6144 | DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n"); |
4f9db5b5 PB |
6145 | return NULL; |
6146 | } | |
6147 | ||
96178eeb | 6148 | dev_priv->drrs.type = dev_priv->vbt.drrs_type; |
4f9db5b5 | 6149 | |
96178eeb | 6150 | dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR; |
4079b8d1 | 6151 | DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n"); |
4f9db5b5 PB |
6152 | return downclock_mode; |
6153 | } | |
6154 | ||
ed92f0b2 | 6155 | static bool intel_edp_init_connector(struct intel_dp *intel_dp, |
36b5f425 | 6156 | struct intel_connector *intel_connector) |
ed92f0b2 | 6157 | { |
2f773477 | 6158 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 6159 | struct drm_i915_private *dev_priv = to_i915(dev); |
2f773477 | 6160 | struct drm_connector *connector = &intel_connector->base; |
ed92f0b2 | 6161 | struct drm_display_mode *fixed_mode = NULL; |
dc911f5b | 6162 | struct drm_display_mode *alt_fixed_mode = NULL; |
4f9db5b5 | 6163 | struct drm_display_mode *downclock_mode = NULL; |
ed92f0b2 PZ |
6164 | bool has_dpcd; |
6165 | struct drm_display_mode *scan; | |
6166 | struct edid *edid; | |
6517d273 | 6167 | enum pipe pipe = INVALID_PIPE; |
ed92f0b2 | 6168 | |
1853a9da | 6169 | if (!intel_dp_is_edp(intel_dp)) |
ed92f0b2 PZ |
6170 | return true; |
6171 | ||
97a824e1 ID |
6172 | /* |
6173 | * On IBX/CPT we may get here with LVDS already registered. Since the | |
6174 | * driver uses the only internal power sequencer available for both | |
6175 | * eDP and LVDS bail out early in this case to prevent interfering | |
6176 | * with an already powered-on LVDS power sequencer. | |
6177 | */ | |
2f773477 | 6178 | if (intel_get_lvds_encoder(&dev_priv->drm)) { |
97a824e1 ID |
6179 | WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))); |
6180 | DRM_INFO("LVDS was detected, not registering eDP\n"); | |
6181 | ||
6182 | return false; | |
6183 | } | |
6184 | ||
49e6bc51 | 6185 | pps_lock(intel_dp); |
b4d06ede ID |
6186 | |
6187 | intel_dp_init_panel_power_timestamps(intel_dp); | |
46bd8383 | 6188 | intel_dp_pps_init(intel_dp); |
49e6bc51 | 6189 | intel_edp_panel_vdd_sanitize(intel_dp); |
b4d06ede | 6190 | |
49e6bc51 | 6191 | pps_unlock(intel_dp); |
63635217 | 6192 | |
ed92f0b2 | 6193 | /* Cache DPCD and EDID for edp. */ |
fe5a66f9 | 6194 | has_dpcd = intel_edp_init_dpcd(intel_dp); |
ed92f0b2 | 6195 | |
fe5a66f9 | 6196 | if (!has_dpcd) { |
ed92f0b2 PZ |
6197 | /* if this fails, presume the device is a ghost */ |
6198 | DRM_INFO("failed to retrieve link info, disabling eDP\n"); | |
b4d06ede | 6199 | goto out_vdd_off; |
ed92f0b2 PZ |
6200 | } |
6201 | ||
060c8778 | 6202 | mutex_lock(&dev->mode_config.mutex); |
0b99836f | 6203 | edid = drm_get_edid(connector, &intel_dp->aux.ddc); |
ed92f0b2 PZ |
6204 | if (edid) { |
6205 | if (drm_add_edid_modes(connector, edid)) { | |
6206 | drm_mode_connector_update_edid_property(connector, | |
6207 | edid); | |
ed92f0b2 PZ |
6208 | } else { |
6209 | kfree(edid); | |
6210 | edid = ERR_PTR(-EINVAL); | |
6211 | } | |
6212 | } else { | |
6213 | edid = ERR_PTR(-ENOENT); | |
6214 | } | |
6215 | intel_connector->edid = edid; | |
6216 | ||
dc911f5b | 6217 | /* prefer fixed mode from EDID if available, save an alt mode also */ |
ed92f0b2 PZ |
6218 | list_for_each_entry(scan, &connector->probed_modes, head) { |
6219 | if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { | |
6220 | fixed_mode = drm_mode_duplicate(dev, scan); | |
4f9db5b5 | 6221 | downclock_mode = intel_dp_drrs_init( |
4f9db5b5 | 6222 | intel_connector, fixed_mode); |
dc911f5b JB |
6223 | } else if (!alt_fixed_mode) { |
6224 | alt_fixed_mode = drm_mode_duplicate(dev, scan); | |
ed92f0b2 PZ |
6225 | } |
6226 | } | |
6227 | ||
6228 | /* fallback to VBT if available for eDP */ | |
6229 | if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) { | |
6230 | fixed_mode = drm_mode_duplicate(dev, | |
6231 | dev_priv->vbt.lfp_lvds_vbt_mode); | |
df457245 | 6232 | if (fixed_mode) { |
ed92f0b2 | 6233 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; |
df457245 VS |
6234 | connector->display_info.width_mm = fixed_mode->width_mm; |
6235 | connector->display_info.height_mm = fixed_mode->height_mm; | |
6236 | } | |
ed92f0b2 | 6237 | } |
060c8778 | 6238 | mutex_unlock(&dev->mode_config.mutex); |
ed92f0b2 | 6239 | |
920a14b2 | 6240 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
01527b31 CT |
6241 | intel_dp->edp_notifier.notifier_call = edp_notify_handler; |
6242 | register_reboot_notifier(&intel_dp->edp_notifier); | |
6517d273 VS |
6243 | |
6244 | /* | |
6245 | * Figure out the current pipe for the initial backlight setup. | |
6246 | * If the current pipe isn't valid, try the PPS pipe, and if that | |
6247 | * fails just assume pipe A. | |
6248 | */ | |
9f2bdb00 | 6249 | pipe = vlv_active_pipe(intel_dp); |
6517d273 VS |
6250 | |
6251 | if (pipe != PIPE_A && pipe != PIPE_B) | |
6252 | pipe = intel_dp->pps_pipe; | |
6253 | ||
6254 | if (pipe != PIPE_A && pipe != PIPE_B) | |
6255 | pipe = PIPE_A; | |
6256 | ||
6257 | DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n", | |
6258 | pipe_name(pipe)); | |
01527b31 CT |
6259 | } |
6260 | ||
dc911f5b JB |
6261 | intel_panel_init(&intel_connector->panel, fixed_mode, alt_fixed_mode, |
6262 | downclock_mode); | |
5507faeb | 6263 | intel_connector->panel.backlight.power = intel_edp_backlight_power; |
6517d273 | 6264 | intel_panel_setup_backlight(connector, pipe); |
ed92f0b2 PZ |
6265 | |
6266 | return true; | |
b4d06ede ID |
6267 | |
6268 | out_vdd_off: | |
6269 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); | |
6270 | /* | |
6271 | * vdd might still be enabled do to the delayed vdd off. | |
6272 | * Make sure vdd is actually turned off here. | |
6273 | */ | |
6274 | pps_lock(intel_dp); | |
6275 | edp_panel_vdd_off_sync(intel_dp); | |
6276 | pps_unlock(intel_dp); | |
6277 | ||
6278 | return false; | |
ed92f0b2 PZ |
6279 | } |
6280 | ||
9301397a MN |
6281 | static void intel_dp_modeset_retry_work_fn(struct work_struct *work) |
6282 | { | |
6283 | struct intel_connector *intel_connector; | |
6284 | struct drm_connector *connector; | |
6285 | ||
6286 | intel_connector = container_of(work, typeof(*intel_connector), | |
6287 | modeset_retry_work); | |
6288 | connector = &intel_connector->base; | |
6289 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id, | |
6290 | connector->name); | |
6291 | ||
6292 | /* Grab the locks before changing connector property*/ | |
6293 | mutex_lock(&connector->dev->mode_config.mutex); | |
6294 | /* Set connector link status to BAD and send a Uevent to notify | |
6295 | * userspace to do a modeset. | |
6296 | */ | |
6297 | drm_mode_connector_set_link_status_property(connector, | |
6298 | DRM_MODE_LINK_STATUS_BAD); | |
6299 | mutex_unlock(&connector->dev->mode_config.mutex); | |
6300 | /* Send Hotplug uevent so userspace can reprobe */ | |
6301 | drm_kms_helper_hotplug_event(connector->dev); | |
6302 | } | |
6303 | ||
16c25533 | 6304 | bool |
f0fec3f2 PZ |
6305 | intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
6306 | struct intel_connector *intel_connector) | |
a4fc5ed6 | 6307 | { |
f0fec3f2 PZ |
6308 | struct drm_connector *connector = &intel_connector->base; |
6309 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
6310 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
6311 | struct drm_device *dev = intel_encoder->base.dev; | |
fac5e23e | 6312 | struct drm_i915_private *dev_priv = to_i915(dev); |
8f4f2797 | 6313 | enum port port = intel_encoder->port; |
7a418e34 | 6314 | int type; |
a4fc5ed6 | 6315 | |
9301397a MN |
6316 | /* Initialize the work for modeset in case of link train failure */ |
6317 | INIT_WORK(&intel_connector->modeset_retry_work, | |
6318 | intel_dp_modeset_retry_work_fn); | |
6319 | ||
ccb1a831 VS |
6320 | if (WARN(intel_dig_port->max_lanes < 1, |
6321 | "Not enough lanes (%d) for DP on port %c\n", | |
6322 | intel_dig_port->max_lanes, port_name(port))) | |
6323 | return false; | |
6324 | ||
55cfc580 JN |
6325 | intel_dp_set_source_rates(intel_dp); |
6326 | ||
d7e8ef02 | 6327 | intel_dp->reset_link_params = true; |
a4a5d2f8 | 6328 | intel_dp->pps_pipe = INVALID_PIPE; |
9f2bdb00 | 6329 | intel_dp->active_pipe = INVALID_PIPE; |
a4a5d2f8 | 6330 | |
ec5b01dd | 6331 | /* intel_dp vfuncs */ |
4f8036a2 | 6332 | if (HAS_DDI(dev_priv)) |
ad64217b ACO |
6333 | intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain; |
6334 | ||
0767935e DV |
6335 | /* Preserve the current hw state. */ |
6336 | intel_dp->DP = I915_READ(intel_dp->output_reg); | |
dd06f90e | 6337 | intel_dp->attached_connector = intel_connector; |
3d3dc149 | 6338 | |
7b91bf7f | 6339 | if (intel_dp_is_port_edp(dev_priv, port)) |
b329530c | 6340 | type = DRM_MODE_CONNECTOR_eDP; |
3b32a35b VS |
6341 | else |
6342 | type = DRM_MODE_CONNECTOR_DisplayPort; | |
b329530c | 6343 | |
9f2bdb00 VS |
6344 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
6345 | intel_dp->active_pipe = vlv_active_pipe(intel_dp); | |
6346 | ||
f7d24902 ID |
6347 | /* |
6348 | * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but | |
6349 | * for DP the encoder type can be set by the caller to | |
6350 | * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it. | |
6351 | */ | |
6352 | if (type == DRM_MODE_CONNECTOR_eDP) | |
6353 | intel_encoder->type = INTEL_OUTPUT_EDP; | |
6354 | ||
c17ed5b5 | 6355 | /* eDP only on port B and/or C on vlv/chv */ |
920a14b2 | 6356 | if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
1853a9da JN |
6357 | intel_dp_is_edp(intel_dp) && |
6358 | port != PORT_B && port != PORT_C)) | |
c17ed5b5 VS |
6359 | return false; |
6360 | ||
e7281eab ID |
6361 | DRM_DEBUG_KMS("Adding %s connector on port %c\n", |
6362 | type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", | |
6363 | port_name(port)); | |
6364 | ||
b329530c | 6365 | drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); |
a4fc5ed6 KP |
6366 | drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); |
6367 | ||
05021389 VS |
6368 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) |
6369 | connector->interlace_allowed = true; | |
a4fc5ed6 KP |
6370 | connector->doublescan_allowed = 0; |
6371 | ||
bdabdb63 | 6372 | intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); |
5432fcaf | 6373 | |
b6339585 | 6374 | intel_dp_aux_init(intel_dp); |
7a418e34 | 6375 | |
f0fec3f2 | 6376 | INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, |
4be73780 | 6377 | edp_panel_vdd_work); |
a4fc5ed6 | 6378 | |
df0e9248 | 6379 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
a4fc5ed6 | 6380 | |
4f8036a2 | 6381 | if (HAS_DDI(dev_priv)) |
bcbc889b PZ |
6382 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
6383 | else | |
6384 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
6385 | ||
0e32b39c | 6386 | /* init MST on ports that can support it */ |
1853a9da | 6387 | if (HAS_DP_MST(dev_priv) && !intel_dp_is_edp(intel_dp) && |
9787e835 RV |
6388 | (port == PORT_B || port == PORT_C || |
6389 | port == PORT_D || port == PORT_F)) | |
0c9b3715 JN |
6390 | intel_dp_mst_encoder_init(intel_dig_port, |
6391 | intel_connector->base.base.id); | |
0e32b39c | 6392 | |
36b5f425 | 6393 | if (!intel_edp_init_connector(intel_dp, intel_connector)) { |
a121f4e5 VS |
6394 | intel_dp_aux_fini(intel_dp); |
6395 | intel_dp_mst_encoder_cleanup(intel_dig_port); | |
6396 | goto fail; | |
b2f246a8 | 6397 | } |
32f9d658 | 6398 | |
f684960e | 6399 | intel_dp_add_properties(intel_dp, connector); |
20f24d77 | 6400 | |
fdddd08c | 6401 | if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) { |
20f24d77 SP |
6402 | int ret = intel_hdcp_init(intel_connector, &intel_dp_hdcp_shim); |
6403 | if (ret) | |
6404 | DRM_DEBUG_KMS("HDCP init failed, skipping.\n"); | |
6405 | } | |
f684960e | 6406 | |
a4fc5ed6 KP |
6407 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
6408 | * 0xd. Failure to do so will result in spurious interrupts being | |
6409 | * generated on the port when a cable is not attached. | |
6410 | */ | |
50a0bc90 | 6411 | if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) { |
a4fc5ed6 KP |
6412 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); |
6413 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
6414 | } | |
16c25533 PZ |
6415 | |
6416 | return true; | |
a121f4e5 VS |
6417 | |
6418 | fail: | |
a121f4e5 VS |
6419 | drm_connector_cleanup(connector); |
6420 | ||
6421 | return false; | |
a4fc5ed6 | 6422 | } |
f0fec3f2 | 6423 | |
c39055b0 | 6424 | bool intel_dp_init(struct drm_i915_private *dev_priv, |
457c52d8 CW |
6425 | i915_reg_t output_reg, |
6426 | enum port port) | |
f0fec3f2 PZ |
6427 | { |
6428 | struct intel_digital_port *intel_dig_port; | |
6429 | struct intel_encoder *intel_encoder; | |
6430 | struct drm_encoder *encoder; | |
6431 | struct intel_connector *intel_connector; | |
6432 | ||
b14c5679 | 6433 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
f0fec3f2 | 6434 | if (!intel_dig_port) |
457c52d8 | 6435 | return false; |
f0fec3f2 | 6436 | |
08d9bc92 | 6437 | intel_connector = intel_connector_alloc(); |
11aee0f6 SM |
6438 | if (!intel_connector) |
6439 | goto err_connector_alloc; | |
f0fec3f2 PZ |
6440 | |
6441 | intel_encoder = &intel_dig_port->base; | |
6442 | encoder = &intel_encoder->base; | |
6443 | ||
c39055b0 ACO |
6444 | if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base, |
6445 | &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS, | |
6446 | "DP %c", port_name(port))) | |
893da0c9 | 6447 | goto err_encoder_init; |
f0fec3f2 | 6448 | |
c85d200e | 6449 | intel_encoder->hotplug = intel_dp_hotplug; |
5bfe2ac0 | 6450 | intel_encoder->compute_config = intel_dp_compute_config; |
00c09d70 | 6451 | intel_encoder->get_hw_state = intel_dp_get_hw_state; |
045ac3b5 | 6452 | intel_encoder->get_config = intel_dp_get_config; |
07f9cd0b | 6453 | intel_encoder->suspend = intel_dp_encoder_suspend; |
920a14b2 | 6454 | if (IS_CHERRYVIEW(dev_priv)) { |
9197c88b | 6455 | intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable; |
e4a1d846 CML |
6456 | intel_encoder->pre_enable = chv_pre_enable_dp; |
6457 | intel_encoder->enable = vlv_enable_dp; | |
1a8ff607 | 6458 | intel_encoder->disable = vlv_disable_dp; |
580d3811 | 6459 | intel_encoder->post_disable = chv_post_disable_dp; |
d6db995f | 6460 | intel_encoder->post_pll_disable = chv_dp_post_pll_disable; |
11a914c2 | 6461 | } else if (IS_VALLEYVIEW(dev_priv)) { |
ecff4f3b | 6462 | intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable; |
ab1f90f9 JN |
6463 | intel_encoder->pre_enable = vlv_pre_enable_dp; |
6464 | intel_encoder->enable = vlv_enable_dp; | |
1a8ff607 | 6465 | intel_encoder->disable = vlv_disable_dp; |
49277c31 | 6466 | intel_encoder->post_disable = vlv_post_disable_dp; |
1a8ff607 VS |
6467 | } else if (INTEL_GEN(dev_priv) >= 5) { |
6468 | intel_encoder->pre_enable = g4x_pre_enable_dp; | |
6469 | intel_encoder->enable = g4x_enable_dp; | |
6470 | intel_encoder->disable = ilk_disable_dp; | |
6471 | intel_encoder->post_disable = ilk_post_disable_dp; | |
ab1f90f9 | 6472 | } else { |
ecff4f3b JN |
6473 | intel_encoder->pre_enable = g4x_pre_enable_dp; |
6474 | intel_encoder->enable = g4x_enable_dp; | |
1a8ff607 | 6475 | intel_encoder->disable = g4x_disable_dp; |
ab1f90f9 | 6476 | } |
f0fec3f2 | 6477 | |
f0fec3f2 | 6478 | intel_dig_port->dp.output_reg = output_reg; |
ccb1a831 | 6479 | intel_dig_port->max_lanes = 4; |
f0fec3f2 | 6480 | |
cca0502b | 6481 | intel_encoder->type = INTEL_OUTPUT_DP; |
79f255a0 | 6482 | intel_encoder->power_domain = intel_port_to_power_domain(port); |
920a14b2 | 6483 | if (IS_CHERRYVIEW(dev_priv)) { |
882ec384 VS |
6484 | if (port == PORT_D) |
6485 | intel_encoder->crtc_mask = 1 << 2; | |
6486 | else | |
6487 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); | |
6488 | } else { | |
6489 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); | |
6490 | } | |
bc079e8b | 6491 | intel_encoder->cloneable = 0; |
03cdc1d4 | 6492 | intel_encoder->port = port; |
f0fec3f2 | 6493 | |
13cf5504 | 6494 | intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; |
5fcece80 | 6495 | dev_priv->hotplug.irq_port[port] = intel_dig_port; |
13cf5504 | 6496 | |
385e4de0 VS |
6497 | if (port != PORT_A) |
6498 | intel_infoframe_init(intel_dig_port); | |
6499 | ||
11aee0f6 SM |
6500 | if (!intel_dp_init_connector(intel_dig_port, intel_connector)) |
6501 | goto err_init_connector; | |
6502 | ||
457c52d8 | 6503 | return true; |
11aee0f6 SM |
6504 | |
6505 | err_init_connector: | |
6506 | drm_encoder_cleanup(encoder); | |
893da0c9 | 6507 | err_encoder_init: |
11aee0f6 SM |
6508 | kfree(intel_connector); |
6509 | err_connector_alloc: | |
6510 | kfree(intel_dig_port); | |
457c52d8 | 6511 | return false; |
f0fec3f2 | 6512 | } |
0e32b39c DA |
6513 | |
6514 | void intel_dp_mst_suspend(struct drm_device *dev) | |
6515 | { | |
fac5e23e | 6516 | struct drm_i915_private *dev_priv = to_i915(dev); |
0e32b39c DA |
6517 | int i; |
6518 | ||
6519 | /* disable MST */ | |
6520 | for (i = 0; i < I915_MAX_PORTS; i++) { | |
5fcece80 | 6521 | struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i]; |
5aa56969 VS |
6522 | |
6523 | if (!intel_dig_port || !intel_dig_port->dp.can_mst) | |
0e32b39c DA |
6524 | continue; |
6525 | ||
5aa56969 VS |
6526 | if (intel_dig_port->dp.is_mst) |
6527 | drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr); | |
0e32b39c DA |
6528 | } |
6529 | } | |
6530 | ||
6531 | void intel_dp_mst_resume(struct drm_device *dev) | |
6532 | { | |
fac5e23e | 6533 | struct drm_i915_private *dev_priv = to_i915(dev); |
0e32b39c DA |
6534 | int i; |
6535 | ||
6536 | for (i = 0; i < I915_MAX_PORTS; i++) { | |
5fcece80 | 6537 | struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i]; |
5aa56969 | 6538 | int ret; |
0e32b39c | 6539 | |
5aa56969 VS |
6540 | if (!intel_dig_port || !intel_dig_port->dp.can_mst) |
6541 | continue; | |
0e32b39c | 6542 | |
5aa56969 VS |
6543 | ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr); |
6544 | if (ret) | |
6545 | intel_dp_check_mst_status(&intel_dig_port->dp); | |
0e32b39c DA |
6546 | } |
6547 | } |