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drm/i915: adjusted_mode->clock in the dp mode_fixup
[linux-block.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
a4fc5ed6
KP		 31#include "drmP.h"
32#include "drm.h"
33#include "drm_crtc.h"
34#include "drm_crtc_helper.h"
35#include "intel_drv.h"
36#include "i915_drm.h"
37#include "i915_drv.h"
ab2c0672 38#include "drm_dp_helper.h"
a4fc5ed6 39
a2006cf5 40#define DP_RECEIVER_CAP_SIZE 0xf
a4fc5ed6
KP		 41#define DP_LINK_STATUS_SIZE 6
42#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
43
44#define DP_LINK_CONFIGURATION_SIZE 9
45
ea5b213a
CW		 46struct intel_dp {
47 struct intel_encoder base;
a4fc5ed6
KP		 48 uint32_t output_reg;
49 uint32_t DP;
50 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
a4fc5ed6 51 bool has_audio;
c3e5f67b 52 enum hdmi_force_audio force_audio;
e953fd7b 53 uint32_t color_range;
d2b996ac 54 int dpms_mode;
a4fc5ed6
KP		 55 uint8_t link_bw;
56 uint8_t lane_count;
a2006cf5 57 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
a4fc5ed6
KP		 58 struct i2c_adapter adapter;
59 struct i2c_algo_dp_aux_data algo;
f0917379 60 bool is_pch_edp;
33a34e4e 61 uint8_t train_set[4];
f01eca2e
KP		 62 int panel_power_up_delay;
63 int panel_power_down_delay;
64 int panel_power_cycle_delay;
65 int backlight_on_delay;
66 int backlight_off_delay;
d15456de 67 struct drm_display_mode *panel_fixed_mode; /* for eDP */
bd943159
KP		 68 struct delayed_work panel_vdd_work;
69 bool want_panel_vdd;
a4fc5ed6
KP		 70};
71
cfcb0fc9
JB		 72/**
73 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
74 * @intel_dp: DP struct
75 *
76 * If a CPU or PCH DP output is attached to an eDP panel, this function
77 * will return true, and false otherwise.
78 */
79static bool is_edp(struct intel_dp *intel_dp)
80{
81 return intel_dp->base.type == INTEL_OUTPUT_EDP;
82}
83
84/**
85 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
86 * @intel_dp: DP struct
87 *
88 * Returns true if the given DP struct corresponds to a PCH DP port attached
89 * to an eDP panel, false otherwise. Helpful for determining whether we
90 * may need FDI resources for a given DP output or not.
91 */
92static bool is_pch_edp(struct intel_dp *intel_dp)
93{
94 return intel_dp->is_pch_edp;
95}
96
1c95822a
AJ		 97/**
98 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
99 * @intel_dp: DP struct
100 *
101 * Returns true if the given DP struct corresponds to a CPU eDP port.
102 */
103static bool is_cpu_edp(struct intel_dp *intel_dp)
104{
105 return is_edp(intel_dp) && !is_pch_edp(intel_dp);
106}
107
ea5b213a
CW		 108static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
109{
4ef69c7a 110 return container_of(encoder, struct intel_dp, base.base);
ea5b213a 111}
a4fc5ed6 112
df0e9248
CW		 113static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
114{
115 return container_of(intel_attached_encoder(connector),
116 struct intel_dp, base);
117}
118
814948ad
JB		 119/**
120 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
121 * @encoder: DRM encoder
122 *
123 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
124 * by intel_display.c.
125 */
126bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
127{
128 struct intel_dp *intel_dp;
129
130 if (!encoder)
131 return false;
132
133 intel_dp = enc_to_intel_dp(encoder);
134
135 return is_pch_edp(intel_dp);
136}
137
33a34e4e
JB		 138static void intel_dp_start_link_train(struct intel_dp *intel_dp);
139static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
ea5b213a 140static void intel_dp_link_down(struct intel_dp *intel_dp);
a4fc5ed6 141
32f9d658 142void
0206e353 143intel_edp_link_config(struct intel_encoder *intel_encoder,
ea5b213a 144 int *lane_num, int *link_bw)
32f9d658 145{
ea5b213a 146 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
32f9d658 147
ea5b213a
CW		 148 *lane_num = intel_dp->lane_count;
149 if (intel_dp->link_bw == DP_LINK_BW_1_62)
32f9d658 150 *link_bw = 162000;
ea5b213a 151 else if (intel_dp->link_bw == DP_LINK_BW_2_7)
32f9d658
ZW		 152 *link_bw = 270000;
153}
154
94bf2ced
DV		 155int
156intel_edp_target_clock(struct intel_encoder *intel_encoder,
157 struct drm_display_mode *mode)
158{
159 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
160
161 if (intel_dp->panel_fixed_mode)
162 return intel_dp->panel_fixed_mode->clock;
163 else
164 return mode->clock;
165}
166
a4fc5ed6 167static int
ea5b213a 168intel_dp_max_lane_count(struct intel_dp *intel_dp)
a4fc5ed6 169{
9a10f401
KP		 170 int max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
171 switch (max_lane_count) {
172 case 1: case 2: case 4:
173 break;
174 default:
175 max_lane_count = 4;
a4fc5ed6
KP		 176 }
177 return max_lane_count;
178}
179
180static int
ea5b213a 181intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 182{
7183dc29 183 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 184
185 switch (max_link_bw) {
186 case DP_LINK_BW_1_62:
187 case DP_LINK_BW_2_7:
188 break;
189 default:
190 max_link_bw = DP_LINK_BW_1_62;
191 break;
192 }
193 return max_link_bw;
194}
195
196static int
197intel_dp_link_clock(uint8_t link_bw)
198{
199 if (link_bw == DP_LINK_BW_2_7)
200 return 270000;
201 else
202 return 162000;
203}
204
cd9dde44
AJ		 205/*
206 * The units on the numbers in the next two are... bizarre. Examples will
207 * make it clearer; this one parallels an example in the eDP spec.
208 *
209 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
210 *
211 * 270000 * 1 * 8 / 10 == 216000
212 *
213 * The actual data capacity of that configuration is 2.16Gbit/s, so the
214 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
215 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
216 * 119000. At 18bpp that's 2142000 kilobits per second.
217 *
218 * Thus the strange-looking division by 10 in intel_dp_link_required, to
219 * get the result in decakilobits instead of kilobits.
220 */
221
a4fc5ed6 222static int
c898261c 223intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 224{
cd9dde44 225 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 226}
227
fe27d53e
DA		 228static int
229intel_dp_max_data_rate(int max_link_clock, int max_lanes)
230{
231 return (max_link_clock * max_lanes * 8) / 10;
232}
233
c4867936
DV		 234static bool
235intel_dp_adjust_dithering(struct intel_dp *intel_dp,
236 struct drm_display_mode *mode,
237 struct drm_display_mode *adjusted_mode)
238{
239 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
240 int max_lanes = intel_dp_max_lane_count(intel_dp);
241 int max_rate, mode_rate;
242
243 mode_rate = intel_dp_link_required(mode->clock, 24);
244 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
245
246 if (mode_rate > max_rate) {
247 mode_rate = intel_dp_link_required(mode->clock, 18);
248 if (mode_rate > max_rate)
249 return false;
250
251 if (adjusted_mode)
252 adjusted_mode->private_flags
253 |= INTEL_MODE_DP_FORCE_6BPC;
254
255 return true;
256 }
257
258 return true;
259}
260
a4fc5ed6
KP		 261static int
262intel_dp_mode_valid(struct drm_connector *connector,
263 struct drm_display_mode *mode)
264{
df0e9248 265 struct intel_dp *intel_dp = intel_attached_dp(connector);
a4fc5ed6 266
d15456de
KP		 267 if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
268 if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay)
7de56f43
ZY		 269 return MODE_PANEL;
270
d15456de 271 if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay)
7de56f43
ZY		 272 return MODE_PANEL;
273 }
274
c4867936
DV		 275 if (!intel_dp_adjust_dithering(intel_dp, mode, NULL))
276 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 277
278 if (mode->clock < 10000)
279 return MODE_CLOCK_LOW;
280
0af78a2b
DV		 281 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
282 return MODE_H_ILLEGAL;
283
a4fc5ed6
KP		 284 return MODE_OK;
285}
286
287static uint32_t
288pack_aux(uint8_t *src, int src_bytes)
289{
290 int i;
291 uint32_t v = 0;
292
293 if (src_bytes > 4)
294 src_bytes = 4;
295 for (i = 0; i < src_bytes; i++)
296 v |= ((uint32_t) src[i]) << ((3-i) * 8);
297 return v;
298}
299
300static void
301unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
302{
303 int i;
304 if (dst_bytes > 4)
305 dst_bytes = 4;
306 for (i = 0; i < dst_bytes; i++)
307 dst[i] = src >> ((3-i) * 8);
308}
309
fb0f8fbf
KP		 310/* hrawclock is 1/4 the FSB frequency */
311static int
312intel_hrawclk(struct drm_device *dev)
313{
314 struct drm_i915_private *dev_priv = dev->dev_private;
315 uint32_t clkcfg;
316
317 clkcfg = I915_READ(CLKCFG);
318 switch (clkcfg & CLKCFG_FSB_MASK) {
319 case CLKCFG_FSB_400:
320 return 100;
321 case CLKCFG_FSB_533:
322 return 133;
323 case CLKCFG_FSB_667:
324 return 166;
325 case CLKCFG_FSB_800:
326 return 200;
327 case CLKCFG_FSB_1067:
328 return 266;
329 case CLKCFG_FSB_1333:
330 return 333;
331 /* these two are just a guess; one of them might be right */
332 case CLKCFG_FSB_1600:
333 case CLKCFG_FSB_1600_ALT:
334 return 400;
335 default:
336 return 133;
337 }
338}
339
ebf33b18
KP		 340static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
341{
342 struct drm_device *dev = intel_dp->base.base.dev;
343 struct drm_i915_private *dev_priv = dev->dev_private;
344
345 return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
346}
347
348static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
349{
350 struct drm_device *dev = intel_dp->base.base.dev;
351 struct drm_i915_private *dev_priv = dev->dev_private;
352
353 return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
354}
355
9b984dae
KP		 356static void
357intel_dp_check_edp(struct intel_dp *intel_dp)
358{
359 struct drm_device *dev = intel_dp->base.base.dev;
360 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 361
9b984dae
KP		 362 if (!is_edp(intel_dp))
363 return;
ebf33b18 364 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 365 WARN(1, "eDP powered off while attempting aux channel communication.\n");
366 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
ebf33b18 367 I915_READ(PCH_PP_STATUS),
9b984dae
KP		 368 I915_READ(PCH_PP_CONTROL));
369 }
370}
371
a4fc5ed6 372static int
ea5b213a 373intel_dp_aux_ch(struct intel_dp *intel_dp,
a4fc5ed6
KP		 374 uint8_t *send, int send_bytes,
375 uint8_t *recv, int recv_size)
376{
ea5b213a 377 uint32_t output_reg = intel_dp->output_reg;
4ef69c7a 378 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6
KP		 379 struct drm_i915_private *dev_priv = dev->dev_private;
380 uint32_t ch_ctl = output_reg + 0x10;
381 uint32_t ch_data = ch_ctl + 4;
382 int i;
383 int recv_bytes;
a4fc5ed6 384 uint32_t status;
fb0f8fbf 385 uint32_t aux_clock_divider;
092945e1 386 int try, precharge = 5;
a4fc5ed6 387
9b984dae 388 intel_dp_check_edp(intel_dp);
a4fc5ed6 389 /* The clock divider is based off the hrawclk,
fb0f8fbf
KP		 390 * and would like to run at 2MHz. So, take the
391 * hrawclk value and divide by 2 and use that
6176b8f9
JB		 392 *
393 * Note that PCH attached eDP panels should use a 125MHz input
394 * clock divider.
a4fc5ed6 395 */
1c95822a 396 if (is_cpu_edp(intel_dp)) {
1a2eb460
KP		 397 if (IS_GEN6(dev) || IS_GEN7(dev))
398 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18
ZW		 399 else
400 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
401 } else if (HAS_PCH_SPLIT(dev))
6919132e 402 aux_clock_divider = 63; /* IRL input clock fixed at 125Mhz */
5eb08b69
ZW		 403 else
404 aux_clock_divider = intel_hrawclk(dev) / 2;
405
11bee43e
JB		 406 /* Try to wait for any previous AUX channel activity */
407 for (try = 0; try < 3; try++) {
408 status = I915_READ(ch_ctl);
409 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
410 break;
411 msleep(1);
412 }
413
414 if (try == 3) {
415 WARN(1, "dp_aux_ch not started status 0x%08x\n",
416 I915_READ(ch_ctl));
4f7f7b7e
CW		 417 return -EBUSY;
418 }
419
fb0f8fbf
KP		 420 /* Must try at least 3 times according to DP spec */
421 for (try = 0; try < 5; try++) {
422 /* Load the send data into the aux channel data registers */
4f7f7b7e
CW		 423 for (i = 0; i < send_bytes; i += 4)
424 I915_WRITE(ch_data + i,
425 pack_aux(send + i, send_bytes - i));
0206e353 426
fb0f8fbf 427 /* Send the command and wait for it to complete */
4f7f7b7e
CW		 428 I915_WRITE(ch_ctl,
429 DP_AUX_CH_CTL_SEND_BUSY |
430 DP_AUX_CH_CTL_TIME_OUT_400us |
431 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
432 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
433 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
434 DP_AUX_CH_CTL_DONE |
435 DP_AUX_CH_CTL_TIME_OUT_ERROR |
436 DP_AUX_CH_CTL_RECEIVE_ERROR);
fb0f8fbf 437 for (;;) {
fb0f8fbf
KP		 438 status = I915_READ(ch_ctl);
439 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
440 break;
4f7f7b7e 441 udelay(100);
fb0f8fbf 442 }
0206e353 443
fb0f8fbf 444 /* Clear done status and any errors */
4f7f7b7e
CW		 445 I915_WRITE(ch_ctl,
446 status |
447 DP_AUX_CH_CTL_DONE |
448 DP_AUX_CH_CTL_TIME_OUT_ERROR |
449 DP_AUX_CH_CTL_RECEIVE_ERROR);
d7e96fea
AJ		 450
451 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
452 DP_AUX_CH_CTL_RECEIVE_ERROR))
453 continue;
4f7f7b7e 454 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 455 break;
456 }
457
a4fc5ed6 458 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 459 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
a5b3da54 460 return -EBUSY;
a4fc5ed6
KP		 461 }
462
463 /* Check for timeout or receive error.
464 * Timeouts occur when the sink is not connected
465 */
a5b3da54 466 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 467 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
a5b3da54
KP		 468 return -EIO;
469 }
1ae8c0a5
KP		 470
471 /* Timeouts occur when the device isn't connected, so they're
472 * "normal" -- don't fill the kernel log with these */
a5b3da54 473 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 474 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
a5b3da54 475 return -ETIMEDOUT;
a4fc5ed6
KP		 476 }
477
478 /* Unload any bytes sent back from the other side */
479 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
480 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 481 if (recv_bytes > recv_size)
482 recv_bytes = recv_size;
0206e353 483
4f7f7b7e
CW		 484 for (i = 0; i < recv_bytes; i += 4)
485 unpack_aux(I915_READ(ch_data + i),
486 recv + i, recv_bytes - i);
a4fc5ed6
KP		 487
488 return recv_bytes;
489}
490
491/* Write data to the aux channel in native mode */
492static int
ea5b213a 493intel_dp_aux_native_write(struct intel_dp *intel_dp,
a4fc5ed6
KP		 494 uint16_t address, uint8_t *send, int send_bytes)
495{
496 int ret;
497 uint8_t msg[20];
498 int msg_bytes;
499 uint8_t ack;
500
9b984dae 501 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 502 if (send_bytes > 16)
503 return -1;
504 msg[0] = AUX_NATIVE_WRITE << 4;
505 msg[1] = address >> 8;
eebc863e 506 msg[2] = address & 0xff;
a4fc5ed6
KP		 507 msg[3] = send_bytes - 1;
508 memcpy(&msg[4], send, send_bytes);
509 msg_bytes = send_bytes + 4;
510 for (;;) {
ea5b213a 511 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
a4fc5ed6
KP		 512 if (ret < 0)
513 return ret;
514 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
515 break;
516 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
517 udelay(100);
518 else
a5b3da54 519 return -EIO;
a4fc5ed6
KP		 520 }
521 return send_bytes;
522}
523
524/* Write a single byte to the aux channel in native mode */
525static int
ea5b213a 526intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
a4fc5ed6
KP		 527 uint16_t address, uint8_t byte)
528{
ea5b213a 529 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
a4fc5ed6
KP		 530}
531
532/* read bytes from a native aux channel */
533static int
ea5b213a 534intel_dp_aux_native_read(struct intel_dp *intel_dp,
a4fc5ed6
KP		 535 uint16_t address, uint8_t *recv, int recv_bytes)
536{
537 uint8_t msg[4];
538 int msg_bytes;
539 uint8_t reply[20];
540 int reply_bytes;
541 uint8_t ack;
542 int ret;
543
9b984dae 544 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 545 msg[0] = AUX_NATIVE_READ << 4;
546 msg[1] = address >> 8;
547 msg[2] = address & 0xff;
548 msg[3] = recv_bytes - 1;
549
550 msg_bytes = 4;
551 reply_bytes = recv_bytes + 1;
552
553 for (;;) {
ea5b213a 554 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
a4fc5ed6 555 reply, reply_bytes);
a5b3da54
KP		 556 if (ret == 0)
557 return -EPROTO;
558 if (ret < 0)
a4fc5ed6
KP		 559 return ret;
560 ack = reply[0];
561 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
562 memcpy(recv, reply + 1, ret - 1);
563 return ret - 1;
564 }
565 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
566 udelay(100);
567 else
a5b3da54 568 return -EIO;
a4fc5ed6
KP		 569 }
570}
571
572static int
ab2c0672
DA		 573intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
574 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 575{
ab2c0672 576 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
ea5b213a
CW		 577 struct intel_dp *intel_dp = container_of(adapter,
578 struct intel_dp,
579 adapter);
ab2c0672
DA		 580 uint16_t address = algo_data->address;
581 uint8_t msg[5];
582 uint8_t reply[2];
8316f337 583 unsigned retry;
ab2c0672
DA		 584 int msg_bytes;
585 int reply_bytes;
586 int ret;
587
9b984dae 588 intel_dp_check_edp(intel_dp);
ab2c0672
DA		 589 /* Set up the command byte */
590 if (mode & MODE_I2C_READ)
591 msg[0] = AUX_I2C_READ << 4;
592 else
593 msg[0] = AUX_I2C_WRITE << 4;
594
595 if (!(mode & MODE_I2C_STOP))
596 msg[0] |= AUX_I2C_MOT << 4;
a4fc5ed6 597
ab2c0672
DA		 598 msg[1] = address >> 8;
599 msg[2] = address;
600
601 switch (mode) {
602 case MODE_I2C_WRITE:
603 msg[3] = 0;
604 msg[4] = write_byte;
605 msg_bytes = 5;
606 reply_bytes = 1;
607 break;
608 case MODE_I2C_READ:
609 msg[3] = 0;
610 msg_bytes = 4;
611 reply_bytes = 2;
612 break;
613 default:
614 msg_bytes = 3;
615 reply_bytes = 1;
616 break;
617 }
618
8316f337
DF		 619 for (retry = 0; retry < 5; retry++) {
620 ret = intel_dp_aux_ch(intel_dp,
621 msg, msg_bytes,
622 reply, reply_bytes);
ab2c0672 623 if (ret < 0) {
3ff99164 624 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
ab2c0672
DA		 625 return ret;
626 }
8316f337
DF		 627
628 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
629 case AUX_NATIVE_REPLY_ACK:
630 /* I2C-over-AUX Reply field is only valid
631 * when paired with AUX ACK.
632 */
633 break;
634 case AUX_NATIVE_REPLY_NACK:
635 DRM_DEBUG_KMS("aux_ch native nack\n");
636 return -EREMOTEIO;
637 case AUX_NATIVE_REPLY_DEFER:
638 udelay(100);
639 continue;
640 default:
641 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
642 reply[0]);
643 return -EREMOTEIO;
644 }
645
ab2c0672
DA		 646 switch (reply[0] & AUX_I2C_REPLY_MASK) {
647 case AUX_I2C_REPLY_ACK:
648 if (mode == MODE_I2C_READ) {
649 *read_byte = reply[1];
650 }
651 return reply_bytes - 1;
652 case AUX_I2C_REPLY_NACK:
8316f337 653 DRM_DEBUG_KMS("aux_i2c nack\n");
ab2c0672
DA		 654 return -EREMOTEIO;
655 case AUX_I2C_REPLY_DEFER:
8316f337 656 DRM_DEBUG_KMS("aux_i2c defer\n");
ab2c0672
DA		 657 udelay(100);
658 break;
659 default:
8316f337 660 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
ab2c0672
DA		 661 return -EREMOTEIO;
662 }
663 }
8316f337
DF		 664
665 DRM_ERROR("too many retries, giving up\n");
666 return -EREMOTEIO;
a4fc5ed6
KP		 667}
668
0b5c541b 669static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
bd943159 670static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
0b5c541b 671
a4fc5ed6 672static int
ea5b213a 673intel_dp_i2c_init(struct intel_dp *intel_dp,
55f78c43 674 struct intel_connector *intel_connector, const char *name)
a4fc5ed6 675{
0b5c541b
KP		 676 int ret;
677
d54e9d28 678 DRM_DEBUG_KMS("i2c_init %s\n", name);
ea5b213a
CW		 679 intel_dp->algo.running = false;
680 intel_dp->algo.address = 0;
681 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
682
0206e353 683 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
ea5b213a
CW		 684 intel_dp->adapter.owner = THIS_MODULE;
685 intel_dp->adapter.class = I2C_CLASS_DDC;
0206e353 686 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
ea5b213a
CW		 687 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
688 intel_dp->adapter.algo_data = &intel_dp->algo;
689 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
690
0b5c541b
KP		 691 ironlake_edp_panel_vdd_on(intel_dp);
692 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
bd943159 693 ironlake_edp_panel_vdd_off(intel_dp, false);
0b5c541b 694 return ret;
a4fc5ed6
KP		 695}
696
697static bool
698intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
699 struct drm_display_mode *adjusted_mode)
700{
0d3a1bee 701 struct drm_device *dev = encoder->dev;
ea5b213a 702 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
a4fc5ed6 703 int lane_count, clock;
ea5b213a
CW		 704 int max_lane_count = intel_dp_max_lane_count(intel_dp);
705 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
083f9560 706 int bpp, mode_rate;
a4fc5ed6
KP		 707 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
708
d15456de
KP		 709 if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
710 intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode);
1d8e1c75
CW		 711 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
712 mode, adjusted_mode);
0d3a1bee
ZY		 713 }
714
0af78a2b
DV		 715 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
716 return false;
717
083f9560
DV		 718 DRM_DEBUG_KMS("DP link computation with max lane count %i "
719 "max bw %02x pixel clock %iKHz\n",
71244653 720 max_lane_count, bws[max_clock], adjusted_mode->clock);
083f9560 721
71244653 722 if (!intel_dp_adjust_dithering(intel_dp, adjusted_mode, adjusted_mode))
c4867936
DV		 723 return false;
724
725 bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
71244653 726 mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
c4867936 727
a4fc5ed6
KP		 728 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
729 for (clock = 0; clock <= max_clock; clock++) {
fe27d53e 730 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
a4fc5ed6 731
083f9560 732 if (mode_rate <= link_avail) {
ea5b213a
CW		 733 intel_dp->link_bw = bws[clock];
734 intel_dp->lane_count = lane_count;
735 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
083f9560
DV		 736 DRM_DEBUG_KMS("DP link bw %02x lane "
737 "count %d clock %d bpp %d\n",
ea5b213a 738 intel_dp->link_bw, intel_dp->lane_count,
083f9560
DV		 739 adjusted_mode->clock, bpp);
740 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
741 mode_rate, link_avail);
a4fc5ed6
KP		 742 return true;
743 }
744 }
745 }
fe27d53e 746
a4fc5ed6
KP		 747 return false;
748}
749
750struct intel_dp_m_n {
751 uint32_t tu;
752 uint32_t gmch_m;
753 uint32_t gmch_n;
754 uint32_t link_m;
755 uint32_t link_n;
756};
757
758static void
759intel_reduce_ratio(uint32_t *num, uint32_t *den)
760{
761 while (*num > 0xffffff || *den > 0xffffff) {
762 *num >>= 1;
763 *den >>= 1;
764 }
765}
766
767static void
36e83a18 768intel_dp_compute_m_n(int bpp,
a4fc5ed6
KP		 769 int nlanes,
770 int pixel_clock,
771 int link_clock,
772 struct intel_dp_m_n *m_n)
773{
774 m_n->tu = 64;
36e83a18 775 m_n->gmch_m = (pixel_clock * bpp) >> 3;
a4fc5ed6
KP		 776 m_n->gmch_n = link_clock * nlanes;
777 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
778 m_n->link_m = pixel_clock;
779 m_n->link_n = link_clock;
780 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
781}
782
783void
784intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
785 struct drm_display_mode *adjusted_mode)
786{
787 struct drm_device *dev = crtc->dev;
788 struct drm_mode_config *mode_config = &dev->mode_config;
55f78c43 789 struct drm_encoder *encoder;
a4fc5ed6
KP		 790 struct drm_i915_private *dev_priv = dev->dev_private;
791 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
858fa035 792 int lane_count = 4;
a4fc5ed6 793 struct intel_dp_m_n m_n;
9db4a9c7 794 int pipe = intel_crtc->pipe;
a4fc5ed6
KP		 795
796 /*
21d40d37 797 * Find the lane count in the intel_encoder private
a4fc5ed6 798 */
55f78c43 799 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
ea5b213a 800 struct intel_dp *intel_dp;
a4fc5ed6 801
d8201ab6 802 if (encoder->crtc != crtc)
a4fc5ed6
KP		 803 continue;
804
ea5b213a 805 intel_dp = enc_to_intel_dp(encoder);
9a10f401
KP		 806 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
807 intel_dp->base.type == INTEL_OUTPUT_EDP)
808 {
ea5b213a 809 lane_count = intel_dp->lane_count;
51190667 810 break;
a4fc5ed6
KP		 811 }
812 }
813
814 /*
815 * Compute the GMCH and Link ratios. The '3' here is
816 * the number of bytes_per_pixel post-LUT, which we always
817 * set up for 8-bits of R/G/B, or 3 bytes total.
818 */
858fa035 819 intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
a4fc5ed6
KP		 820 mode->clock, adjusted_mode->clock, &m_n);
821
c619eed4 822 if (HAS_PCH_SPLIT(dev)) {
9db4a9c7
JB		 823 I915_WRITE(TRANSDATA_M1(pipe),
824 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
825 m_n.gmch_m);
826 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
827 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
828 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
a4fc5ed6 829 } else {
9db4a9c7
JB		 830 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
831 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
832 m_n.gmch_m);
833 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
834 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
835 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
a4fc5ed6
KP		 836 }
837}
838
f01eca2e
KP		 839static void ironlake_edp_pll_on(struct drm_encoder *encoder);
840static void ironlake_edp_pll_off(struct drm_encoder *encoder);
841
a4fc5ed6
KP		 842static void
843intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
844 struct drm_display_mode *adjusted_mode)
845{
e3421a18 846 struct drm_device *dev = encoder->dev;
417e822d 847 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 848 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4ef69c7a 849 struct drm_crtc *crtc = intel_dp->base.base.crtc;
a4fc5ed6
KP		 850 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
851
f01eca2e
KP		 852 /* Turn on the eDP PLL if needed */
853 if (is_edp(intel_dp)) {
854 if (!is_pch_edp(intel_dp))
855 ironlake_edp_pll_on(encoder);
856 else
857 ironlake_edp_pll_off(encoder);
858 }
859
417e822d 860 /*
1a2eb460 861 * There are four kinds of DP registers:
417e822d
KP		 862 *
863 * IBX PCH
1a2eb460
KP		 864 * SNB CPU
865 * IVB CPU
417e822d
KP		 866 * CPT PCH
867 *
868 * IBX PCH and CPU are the same for almost everything,
869 * except that the CPU DP PLL is configured in this
870 * register
871 *
872 * CPT PCH is quite different, having many bits moved
873 * to the TRANS_DP_CTL register instead. That
874 * configuration happens (oddly) in ironlake_pch_enable
875 */
9c9e7927 876
417e822d
KP		 877 /* Preserve the BIOS-computed detected bit. This is
878 * supposed to be read-only.
879 */
880 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
881 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
a4fc5ed6 882
417e822d
KP		 883 /* Handle DP bits in common between all three register formats */
884
885 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
a4fc5ed6 886
ea5b213a 887 switch (intel_dp->lane_count) {
a4fc5ed6 888 case 1:
ea5b213a 889 intel_dp->DP |= DP_PORT_WIDTH_1;
a4fc5ed6
KP		 890 break;
891 case 2:
ea5b213a 892 intel_dp->DP |= DP_PORT_WIDTH_2;
a4fc5ed6
KP		 893 break;
894 case 4:
ea5b213a 895 intel_dp->DP |= DP_PORT_WIDTH_4;
a4fc5ed6
KP		 896 break;
897 }
e0dac65e
WF		 898 if (intel_dp->has_audio) {
899 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
900 pipe_name(intel_crtc->pipe));
ea5b213a 901 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
e0dac65e
WF		 902 intel_write_eld(encoder, adjusted_mode);
903 }
ea5b213a
CW		 904 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
905 intel_dp->link_configuration[0] = intel_dp->link_bw;
906 intel_dp->link_configuration[1] = intel_dp->lane_count;
a2cab1b2 907 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
a4fc5ed6 908 /*
9962c925 909 * Check for DPCD version > 1.1 and enhanced framing support
a4fc5ed6 910 */
7183dc29
JB		 911 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
912 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
ea5b213a 913 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
a4fc5ed6
KP		 914 }
915
417e822d 916 /* Split out the IBX/CPU vs CPT settings */
32f9d658 917
1a2eb460
KP		 918 if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
919 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
920 intel_dp->DP |= DP_SYNC_HS_HIGH;
921 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
922 intel_dp->DP |= DP_SYNC_VS_HIGH;
923 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
924
925 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
926 intel_dp->DP |= DP_ENHANCED_FRAMING;
927
928 intel_dp->DP |= intel_crtc->pipe << 29;
929
930 /* don't miss out required setting for eDP */
931 intel_dp->DP |= DP_PLL_ENABLE;
932 if (adjusted_mode->clock < 200000)
933 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
934 else
935 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
936 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
417e822d
KP		 937 intel_dp->DP |= intel_dp->color_range;
938
939 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
940 intel_dp->DP |= DP_SYNC_HS_HIGH;
941 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
942 intel_dp->DP |= DP_SYNC_VS_HIGH;
943 intel_dp->DP |= DP_LINK_TRAIN_OFF;
944
945 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
946 intel_dp->DP |= DP_ENHANCED_FRAMING;
947
948 if (intel_crtc->pipe == 1)
949 intel_dp->DP |= DP_PIPEB_SELECT;
950
951 if (is_cpu_edp(intel_dp)) {
952 /* don't miss out required setting for eDP */
953 intel_dp->DP |= DP_PLL_ENABLE;
954 if (adjusted_mode->clock < 200000)
955 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
956 else
957 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
958 }
959 } else {
960 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 961 }
a4fc5ed6
KP		 962}
963
99ea7127
KP		 964#define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
965#define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
966
967#define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
968#define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
969
970#define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
971#define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
972
973static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
974 u32 mask,
975 u32 value)
bd943159 976{
99ea7127
KP		 977 struct drm_device *dev = intel_dp->base.base.dev;
978 struct drm_i915_private *dev_priv = dev->dev_private;
32ce697c 979
99ea7127
KP		 980 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
981 mask, value,
982 I915_READ(PCH_PP_STATUS),
983 I915_READ(PCH_PP_CONTROL));
32ce697c 984
99ea7127
KP		 985 if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
986 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
987 I915_READ(PCH_PP_STATUS),
988 I915_READ(PCH_PP_CONTROL));
32ce697c 989 }
99ea7127 990}
32ce697c 991
99ea7127
KP		 992static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
993{
994 DRM_DEBUG_KMS("Wait for panel power on\n");
995 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 996}
997
99ea7127
KP		 998static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
999{
1000 DRM_DEBUG_KMS("Wait for panel power off time\n");
1001 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1002}
1003
1004static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
1005{
1006 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1007 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1008}
1009
1010
832dd3c1
KP		 1011/* Read the current pp_control value, unlocking the register if it
1012 * is locked
1013 */
1014
1015static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
1016{
1017 u32 control = I915_READ(PCH_PP_CONTROL);
1018
1019 control &= ~PANEL_UNLOCK_MASK;
1020 control |= PANEL_UNLOCK_REGS;
1021 return control;
bd943159
KP		 1022}
1023
5d613501
JB		 1024static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
1025{
1026 struct drm_device *dev = intel_dp->base.base.dev;
1027 struct drm_i915_private *dev_priv = dev->dev_private;
1028 u32 pp;
1029
97af61f5
KP		 1030 if (!is_edp(intel_dp))
1031 return;
f01eca2e 1032 DRM_DEBUG_KMS("Turn eDP VDD on\n");
5d613501 1033
bd943159
KP		 1034 WARN(intel_dp->want_panel_vdd,
1035 "eDP VDD already requested on\n");
1036
1037 intel_dp->want_panel_vdd = true;
99ea7127 1038
bd943159
KP		 1039 if (ironlake_edp_have_panel_vdd(intel_dp)) {
1040 DRM_DEBUG_KMS("eDP VDD already on\n");
1041 return;
1042 }
1043
99ea7127
KP		 1044 if (!ironlake_edp_have_panel_power(intel_dp))
1045 ironlake_wait_panel_power_cycle(intel_dp);
1046
832dd3c1 1047 pp = ironlake_get_pp_control(dev_priv);
5d613501
JB		 1048 pp |= EDP_FORCE_VDD;
1049 I915_WRITE(PCH_PP_CONTROL, pp);
1050 POSTING_READ(PCH_PP_CONTROL);
f01eca2e
KP		 1051 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1052 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
ebf33b18
KP		 1053
1054 /*
1055 * If the panel wasn't on, delay before accessing aux channel
1056 */
1057 if (!ironlake_edp_have_panel_power(intel_dp)) {
bd943159 1058 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1059 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1060 }
5d613501
JB		 1061}
1062
bd943159 1063static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501
JB		 1064{
1065 struct drm_device *dev = intel_dp->base.base.dev;
1066 struct drm_i915_private *dev_priv = dev->dev_private;
1067 u32 pp;
1068
bd943159 1069 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
832dd3c1 1070 pp = ironlake_get_pp_control(dev_priv);
bd943159
KP		 1071 pp &= ~EDP_FORCE_VDD;
1072 I915_WRITE(PCH_PP_CONTROL, pp);
1073 POSTING_READ(PCH_PP_CONTROL);
1074
1075 /* Make sure sequencer is idle before allowing subsequent activity */
1076 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1077 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
99ea7127
KP		 1078
1079 msleep(intel_dp->panel_power_down_delay);
bd943159
KP		 1080 }
1081}
5d613501 1082
bd943159
KP		 1083static void ironlake_panel_vdd_work(struct work_struct *__work)
1084{
1085 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1086 struct intel_dp, panel_vdd_work);
1087 struct drm_device *dev = intel_dp->base.base.dev;
1088
627f7675 1089 mutex_lock(&dev->mode_config.mutex);
bd943159 1090 ironlake_panel_vdd_off_sync(intel_dp);
627f7675 1091 mutex_unlock(&dev->mode_config.mutex);
bd943159
KP		 1092}
1093
1094static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1095{
97af61f5
KP		 1096 if (!is_edp(intel_dp))
1097 return;
5d613501 1098
bd943159
KP		 1099 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1100 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1101
bd943159
KP		 1102 intel_dp->want_panel_vdd = false;
1103
1104 if (sync) {
1105 ironlake_panel_vdd_off_sync(intel_dp);
1106 } else {
1107 /*
1108 * Queue the timer to fire a long
1109 * time from now (relative to the power down delay)
1110 * to keep the panel power up across a sequence of operations
1111 */
1112 schedule_delayed_work(&intel_dp->panel_vdd_work,
1113 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1114 }
5d613501
JB		 1115}
1116
86a3073e 1117static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1118{
01cb9ea6 1119 struct drm_device *dev = intel_dp->base.base.dev;
9934c132 1120 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1121 u32 pp;
9934c132 1122
97af61f5 1123 if (!is_edp(intel_dp))
bd943159 1124 return;
99ea7127
KP		 1125
1126 DRM_DEBUG_KMS("Turn eDP power on\n");
1127
1128 if (ironlake_edp_have_panel_power(intel_dp)) {
1129 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1130 return;
99ea7127 1131 }
9934c132 1132
99ea7127 1133 ironlake_wait_panel_power_cycle(intel_dp);
37c6c9b0 1134
99ea7127 1135 pp = ironlake_get_pp_control(dev_priv);
05ce1a49
KP		 1136 if (IS_GEN5(dev)) {
1137 /* ILK workaround: disable reset around power sequence */
1138 pp &= ~PANEL_POWER_RESET;
1139 I915_WRITE(PCH_PP_CONTROL, pp);
1140 POSTING_READ(PCH_PP_CONTROL);
1141 }
37c6c9b0 1142
1c0ae80a 1143 pp |= POWER_TARGET_ON;
99ea7127
KP		 1144 if (!IS_GEN5(dev))
1145 pp |= PANEL_POWER_RESET;
1146
9934c132 1147 I915_WRITE(PCH_PP_CONTROL, pp);
01cb9ea6 1148 POSTING_READ(PCH_PP_CONTROL);
9934c132 1149
99ea7127 1150 ironlake_wait_panel_on(intel_dp);
9934c132 1151
05ce1a49
KP		 1152 if (IS_GEN5(dev)) {
1153 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1154 I915_WRITE(PCH_PP_CONTROL, pp);
1155 POSTING_READ(PCH_PP_CONTROL);
1156 }
9934c132
JB		 1157}
1158
99ea7127 1159static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1160{
99ea7127 1161 struct drm_device *dev = intel_dp->base.base.dev;
9934c132 1162 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1163 u32 pp;
9934c132 1164
97af61f5
KP		 1165 if (!is_edp(intel_dp))
1166 return;
37c6c9b0 1167
99ea7127 1168 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1169
6cb49835 1170 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
37c6c9b0 1171
99ea7127 1172 pp = ironlake_get_pp_control(dev_priv);
6cb49835 1173 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_BLC_ENABLE);
99ea7127
KP		 1174 I915_WRITE(PCH_PP_CONTROL, pp);
1175 POSTING_READ(PCH_PP_CONTROL);
9934c132 1176
99ea7127 1177 ironlake_wait_panel_off(intel_dp);
9934c132
JB		 1178}
1179
86a3073e 1180static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1181{
f01eca2e 1182 struct drm_device *dev = intel_dp->base.base.dev;
32f9d658
ZW		 1183 struct drm_i915_private *dev_priv = dev->dev_private;
1184 u32 pp;
1185
f01eca2e
KP		 1186 if (!is_edp(intel_dp))
1187 return;
1188
28c97730 1189 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1190 /*
1191 * If we enable the backlight right away following a panel power
1192 * on, we may see slight flicker as the panel syncs with the eDP
1193 * link. So delay a bit to make sure the image is solid before
1194 * allowing it to appear.
1195 */
f01eca2e 1196 msleep(intel_dp->backlight_on_delay);
832dd3c1 1197 pp = ironlake_get_pp_control(dev_priv);
32f9d658
ZW		 1198 pp |= EDP_BLC_ENABLE;
1199 I915_WRITE(PCH_PP_CONTROL, pp);
f01eca2e 1200 POSTING_READ(PCH_PP_CONTROL);
32f9d658
ZW		 1201}
1202
86a3073e 1203static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1204{
f01eca2e 1205 struct drm_device *dev = intel_dp->base.base.dev;
32f9d658
ZW		 1206 struct drm_i915_private *dev_priv = dev->dev_private;
1207 u32 pp;
1208
f01eca2e
KP		 1209 if (!is_edp(intel_dp))
1210 return;
1211
28c97730 1212 DRM_DEBUG_KMS("\n");
832dd3c1 1213 pp = ironlake_get_pp_control(dev_priv);
32f9d658
ZW		 1214 pp &= ~EDP_BLC_ENABLE;
1215 I915_WRITE(PCH_PP_CONTROL, pp);
f01eca2e
KP		 1216 POSTING_READ(PCH_PP_CONTROL);
1217 msleep(intel_dp->backlight_off_delay);
32f9d658 1218}
a4fc5ed6 1219
d240f20f
JB		 1220static void ironlake_edp_pll_on(struct drm_encoder *encoder)
1221{
1222 struct drm_device *dev = encoder->dev;
1223 struct drm_i915_private *dev_priv = dev->dev_private;
1224 u32 dpa_ctl;
1225
1226 DRM_DEBUG_KMS("\n");
1227 dpa_ctl = I915_READ(DP_A);
298b0b39 1228 dpa_ctl |= DP_PLL_ENABLE;
d240f20f 1229 I915_WRITE(DP_A, dpa_ctl);
298b0b39
JB		 1230 POSTING_READ(DP_A);
1231 udelay(200);
d240f20f
JB		 1232}
1233
1234static void ironlake_edp_pll_off(struct drm_encoder *encoder)
1235{
1236 struct drm_device *dev = encoder->dev;
1237 struct drm_i915_private *dev_priv = dev->dev_private;
1238 u32 dpa_ctl;
1239
1240 dpa_ctl = I915_READ(DP_A);
298b0b39 1241 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1242 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1243 POSTING_READ(DP_A);
d240f20f
JB		 1244 udelay(200);
1245}
1246
c7ad3810
JB		 1247/* If the sink supports it, try to set the power state appropriately */
1248static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1249{
1250 int ret, i;
1251
1252 /* Should have a valid DPCD by this point */
1253 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1254 return;
1255
1256 if (mode != DRM_MODE_DPMS_ON) {
1257 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1258 DP_SET_POWER_D3);
1259 if (ret != 1)
1260 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1261 } else {
1262 /*
1263 * When turning on, we need to retry for 1ms to give the sink
1264 * time to wake up.
1265 */
1266 for (i = 0; i < 3; i++) {
1267 ret = intel_dp_aux_native_write_1(intel_dp,
1268 DP_SET_POWER,
1269 DP_SET_POWER_D0);
1270 if (ret == 1)
1271 break;
1272 msleep(1);
1273 }
1274 }
1275}
1276
d240f20f
JB		 1277static void intel_dp_prepare(struct drm_encoder *encoder)
1278{
1279 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
d240f20f 1280
6cb49835
DV		 1281
1282 /* Make sure the panel is off before trying to change the mode. But also
1283 * ensure that we have vdd while we switch off the panel. */
1284 ironlake_edp_panel_vdd_on(intel_dp);
21264c63
KP		 1285 ironlake_edp_backlight_off(intel_dp);
1286 ironlake_edp_panel_off(intel_dp);
1287
c7ad3810 1288 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
21264c63 1289 intel_dp_link_down(intel_dp);
bd943159 1290 ironlake_edp_panel_vdd_off(intel_dp, false);
d240f20f
JB		 1291}
1292
1293static void intel_dp_commit(struct drm_encoder *encoder)
1294{
1295 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
d4270e57
JB		 1296 struct drm_device *dev = encoder->dev;
1297 struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
5d613501 1298
97af61f5 1299 ironlake_edp_panel_vdd_on(intel_dp);
f01eca2e 1300 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 1301 intel_dp_start_link_train(intel_dp);
97af61f5 1302 ironlake_edp_panel_on(intel_dp);
bd943159 1303 ironlake_edp_panel_vdd_off(intel_dp, true);
33a34e4e 1304 intel_dp_complete_link_train(intel_dp);
f01eca2e 1305 ironlake_edp_backlight_on(intel_dp);
d2b996ac
KP		 1306
1307 intel_dp->dpms_mode = DRM_MODE_DPMS_ON;
d4270e57
JB		 1308
1309 if (HAS_PCH_CPT(dev))
1310 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
d240f20f
JB		 1311}
1312
a4fc5ed6
KP		 1313static void
1314intel_dp_dpms(struct drm_encoder *encoder, int mode)
1315{
ea5b213a 1316 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
55f78c43 1317 struct drm_device *dev = encoder->dev;
a4fc5ed6 1318 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 1319 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
a4fc5ed6
KP		 1320
1321 if (mode != DRM_MODE_DPMS_ON) {
6cb49835
DV		 1322 /* Switching the panel off requires vdd. */
1323 ironlake_edp_panel_vdd_on(intel_dp);
21264c63
KP		 1324 ironlake_edp_backlight_off(intel_dp);
1325 ironlake_edp_panel_off(intel_dp);
1326
c7ad3810 1327 intel_dp_sink_dpms(intel_dp, mode);
736085bc 1328 intel_dp_link_down(intel_dp);
bd943159 1329 ironlake_edp_panel_vdd_off(intel_dp, false);
21264c63
KP		 1330
1331 if (is_cpu_edp(intel_dp))
1332 ironlake_edp_pll_off(encoder);
a4fc5ed6 1333 } else {
21264c63
KP		 1334 if (is_cpu_edp(intel_dp))
1335 ironlake_edp_pll_on(encoder);
1336
97af61f5 1337 ironlake_edp_panel_vdd_on(intel_dp);
c7ad3810 1338 intel_dp_sink_dpms(intel_dp, mode);
32f9d658 1339 if (!(dp_reg & DP_PORT_EN)) {
01cb9ea6 1340 intel_dp_start_link_train(intel_dp);
97af61f5 1341 ironlake_edp_panel_on(intel_dp);
bd943159 1342 ironlake_edp_panel_vdd_off(intel_dp, true);
33a34e4e 1343 intel_dp_complete_link_train(intel_dp);
bee7eb2d 1344 } else
bd943159
KP		 1345 ironlake_edp_panel_vdd_off(intel_dp, false);
1346 ironlake_edp_backlight_on(intel_dp);
a4fc5ed6 1347 }
d2b996ac 1348 intel_dp->dpms_mode = mode;
a4fc5ed6
KP		 1349}
1350
1351/*
df0c237d
JB		 1352 * Native read with retry for link status and receiver capability reads for
1353 * cases where the sink may still be asleep.
a4fc5ed6
KP		 1354 */
1355static bool
df0c237d
JB		 1356intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1357 uint8_t *recv, int recv_bytes)
a4fc5ed6 1358{
61da5fab
JB		 1359 int ret, i;
1360
df0c237d
JB		 1361 /*
1362 * Sinks are *supposed* to come up within 1ms from an off state,
1363 * but we're also supposed to retry 3 times per the spec.
1364 */
61da5fab 1365 for (i = 0; i < 3; i++) {
df0c237d
JB		 1366 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1367 recv_bytes);
1368 if (ret == recv_bytes)
61da5fab
JB		 1369 return true;
1370 msleep(1);
1371 }
a4fc5ed6 1372
61da5fab 1373 return false;
a4fc5ed6
KP		 1374}
1375
1376/*
1377 * Fetch AUX CH registers 0x202 - 0x207 which contain
1378 * link status information
1379 */
1380static bool
93f62dad 1381intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 1382{
df0c237d
JB		 1383 return intel_dp_aux_native_read_retry(intel_dp,
1384 DP_LANE0_1_STATUS,
93f62dad 1385 link_status,
df0c237d 1386 DP_LINK_STATUS_SIZE);
a4fc5ed6
KP		 1387}
1388
1389static uint8_t
1390intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1391 int r)
1392{
1393 return link_status[r - DP_LANE0_1_STATUS];
1394}
1395
a4fc5ed6 1396static uint8_t
93f62dad 1397intel_get_adjust_request_voltage(uint8_t adjust_request[2],
a4fc5ed6
KP		 1398 int lane)
1399{
a4fc5ed6
KP		 1400 int s = ((lane & 1) ?
1401 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1402 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
93f62dad 1403 uint8_t l = adjust_request[lane>>1];
a4fc5ed6
KP		 1404
1405 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1406}
1407
1408static uint8_t
93f62dad 1409intel_get_adjust_request_pre_emphasis(uint8_t adjust_request[2],
a4fc5ed6
KP		 1410 int lane)
1411{
a4fc5ed6
KP		 1412 int s = ((lane & 1) ?
1413 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1414 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
93f62dad 1415 uint8_t l = adjust_request[lane>>1];
a4fc5ed6
KP		 1416
1417 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1418}
1419
1420
1421#if 0
1422static char *voltage_names[] = {
1423 "0.4V", "0.6V", "0.8V", "1.2V"
1424};
1425static char *pre_emph_names[] = {
1426 "0dB", "3.5dB", "6dB", "9.5dB"
1427};
1428static char *link_train_names[] = {
1429 "pattern 1", "pattern 2", "idle", "off"
1430};
1431#endif
1432
1433/*
1434 * These are source-specific values; current Intel hardware supports
1435 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1436 */
a4fc5ed6
KP		 1437
1438static uint8_t
1a2eb460 1439intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 1440{
1a2eb460
KP		 1441 struct drm_device *dev = intel_dp->base.base.dev;
1442
1443 if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1444 return DP_TRAIN_VOLTAGE_SWING_800;
1445 else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1446 return DP_TRAIN_VOLTAGE_SWING_1200;
1447 else
1448 return DP_TRAIN_VOLTAGE_SWING_800;
1449}
1450
1451static uint8_t
1452intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1453{
1454 struct drm_device *dev = intel_dp->base.base.dev;
1455
1456 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1457 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1458 case DP_TRAIN_VOLTAGE_SWING_400:
1459 return DP_TRAIN_PRE_EMPHASIS_6;
1460 case DP_TRAIN_VOLTAGE_SWING_600:
1461 case DP_TRAIN_VOLTAGE_SWING_800:
1462 return DP_TRAIN_PRE_EMPHASIS_3_5;
1463 default:
1464 return DP_TRAIN_PRE_EMPHASIS_0;
1465 }
1466 } else {
1467 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1468 case DP_TRAIN_VOLTAGE_SWING_400:
1469 return DP_TRAIN_PRE_EMPHASIS_6;
1470 case DP_TRAIN_VOLTAGE_SWING_600:
1471 return DP_TRAIN_PRE_EMPHASIS_6;
1472 case DP_TRAIN_VOLTAGE_SWING_800:
1473 return DP_TRAIN_PRE_EMPHASIS_3_5;
1474 case DP_TRAIN_VOLTAGE_SWING_1200:
1475 default:
1476 return DP_TRAIN_PRE_EMPHASIS_0;
1477 }
a4fc5ed6
KP		 1478 }
1479}
1480
1481static void
93f62dad 1482intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 1483{
1484 uint8_t v = 0;
1485 uint8_t p = 0;
1486 int lane;
93f62dad 1487 uint8_t *adjust_request = link_status + (DP_ADJUST_REQUEST_LANE0_1 - DP_LANE0_1_STATUS);
1a2eb460
KP		 1488 uint8_t voltage_max;
1489 uint8_t preemph_max;
a4fc5ed6 1490
33a34e4e 1491 for (lane = 0; lane < intel_dp->lane_count; lane++) {
93f62dad
KP		 1492 uint8_t this_v = intel_get_adjust_request_voltage(adjust_request, lane);
1493 uint8_t this_p = intel_get_adjust_request_pre_emphasis(adjust_request, lane);
a4fc5ed6
KP		 1494
1495 if (this_v > v)
1496 v = this_v;
1497 if (this_p > p)
1498 p = this_p;
1499 }
1500
1a2eb460 1501 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 1502 if (v >= voltage_max)
1503 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 1504
1a2eb460
KP		 1505 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1506 if (p >= preemph_max)
1507 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 1508
1509 for (lane = 0; lane < 4; lane++)
33a34e4e 1510 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 1511}
1512
1513static uint32_t
93f62dad 1514intel_dp_signal_levels(uint8_t train_set)
a4fc5ed6 1515{
3cf2efb1 1516 uint32_t signal_levels = 0;
a4fc5ed6 1517
3cf2efb1 1518 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 1519 case DP_TRAIN_VOLTAGE_SWING_400:
1520 default:
1521 signal_levels |= DP_VOLTAGE_0_4;
1522 break;
1523 case DP_TRAIN_VOLTAGE_SWING_600:
1524 signal_levels |= DP_VOLTAGE_0_6;
1525 break;
1526 case DP_TRAIN_VOLTAGE_SWING_800:
1527 signal_levels |= DP_VOLTAGE_0_8;
1528 break;
1529 case DP_TRAIN_VOLTAGE_SWING_1200:
1530 signal_levels |= DP_VOLTAGE_1_2;
1531 break;
1532 }
3cf2efb1 1533 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 1534 case DP_TRAIN_PRE_EMPHASIS_0:
1535 default:
1536 signal_levels |= DP_PRE_EMPHASIS_0;
1537 break;
1538 case DP_TRAIN_PRE_EMPHASIS_3_5:
1539 signal_levels |= DP_PRE_EMPHASIS_3_5;
1540 break;
1541 case DP_TRAIN_PRE_EMPHASIS_6:
1542 signal_levels |= DP_PRE_EMPHASIS_6;
1543 break;
1544 case DP_TRAIN_PRE_EMPHASIS_9_5:
1545 signal_levels |= DP_PRE_EMPHASIS_9_5;
1546 break;
1547 }
1548 return signal_levels;
1549}
1550
e3421a18
ZW		 1551/* Gen6's DP voltage swing and pre-emphasis control */
1552static uint32_t
1553intel_gen6_edp_signal_levels(uint8_t train_set)
1554{
3c5a62b5
YL		 1555 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1556 DP_TRAIN_PRE_EMPHASIS_MASK);
1557 switch (signal_levels) {
e3421a18 1558 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1559 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1560 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1561 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1562 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 1563 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 1564 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1565 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 1566 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 1567 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1568 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 1569 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1570 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1571 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 1572 default:
3c5a62b5
YL		 1573 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1574 "0x%x\n", signal_levels);
1575 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 1576 }
1577}
1578
1a2eb460
KP		 1579/* Gen7's DP voltage swing and pre-emphasis control */
1580static uint32_t
1581intel_gen7_edp_signal_levels(uint8_t train_set)
1582{
1583 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1584 DP_TRAIN_PRE_EMPHASIS_MASK);
1585 switch (signal_levels) {
1586 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1587 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1588 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1589 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1590 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1591 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1592
1593 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1594 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1595 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1596 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1597
1598 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1599 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1600 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1601 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1602
1603 default:
1604 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1605 "0x%x\n", signal_levels);
1606 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1607 }
1608}
1609
a4fc5ed6
KP		 1610static uint8_t
1611intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1612 int lane)
1613{
a4fc5ed6 1614 int s = (lane & 1) * 4;
93f62dad 1615 uint8_t l = link_status[lane>>1];
a4fc5ed6
KP		 1616
1617 return (l >> s) & 0xf;
1618}
1619
1620/* Check for clock recovery is done on all channels */
1621static bool
1622intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1623{
1624 int lane;
1625 uint8_t lane_status;
1626
1627 for (lane = 0; lane < lane_count; lane++) {
1628 lane_status = intel_get_lane_status(link_status, lane);
1629 if ((lane_status & DP_LANE_CR_DONE) == 0)
1630 return false;
1631 }
1632 return true;
1633}
1634
1635/* Check to see if channel eq is done on all channels */
1636#define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1637 DP_LANE_CHANNEL_EQ_DONE|\
1638 DP_LANE_SYMBOL_LOCKED)
1639static bool
93f62dad 1640intel_channel_eq_ok(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 1641{
1642 uint8_t lane_align;
1643 uint8_t lane_status;
1644 int lane;
1645
93f62dad 1646 lane_align = intel_dp_link_status(link_status,
a4fc5ed6
KP		 1647 DP_LANE_ALIGN_STATUS_UPDATED);
1648 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1649 return false;
33a34e4e 1650 for (lane = 0; lane < intel_dp->lane_count; lane++) {
93f62dad 1651 lane_status = intel_get_lane_status(link_status, lane);
a4fc5ed6
KP		 1652 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1653 return false;
1654 }
1655 return true;
1656}
1657
1658static bool
ea5b213a 1659intel_dp_set_link_train(struct intel_dp *intel_dp,
a4fc5ed6 1660 uint32_t dp_reg_value,
58e10eb9 1661 uint8_t dp_train_pat)
a4fc5ed6 1662{
4ef69c7a 1663 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6 1664 struct drm_i915_private *dev_priv = dev->dev_private;
a4fc5ed6
KP		 1665 int ret;
1666
ea5b213a
CW		 1667 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1668 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 1669
ea5b213a 1670 intel_dp_aux_native_write_1(intel_dp,
a4fc5ed6
KP		 1671 DP_TRAINING_PATTERN_SET,
1672 dp_train_pat);
1673
ea5b213a 1674 ret = intel_dp_aux_native_write(intel_dp,
58e10eb9 1675 DP_TRAINING_LANE0_SET,
b34f1f09
KP		 1676 intel_dp->train_set,
1677 intel_dp->lane_count);
1678 if (ret != intel_dp->lane_count)
a4fc5ed6
KP		 1679 return false;
1680
1681 return true;
1682}
1683
33a34e4e 1684/* Enable corresponding port and start training pattern 1 */
a4fc5ed6 1685static void
33a34e4e 1686intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 1687{
4ef69c7a 1688 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6 1689 struct drm_i915_private *dev_priv = dev->dev_private;
58e10eb9 1690 struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
a4fc5ed6
KP		 1691 int i;
1692 uint8_t voltage;
1693 bool clock_recovery = false;
cdb0e95b 1694 int voltage_tries, loop_tries;
e3421a18 1695 u32 reg;
ea5b213a 1696 uint32_t DP = intel_dp->DP;
a4fc5ed6 1697
e8519464
AJ		 1698 /*
1699 * On CPT we have to enable the port in training pattern 1, which
1700 * will happen below in intel_dp_set_link_train. Otherwise, enable
1701 * the port and wait for it to become active.
1702 */
1703 if (!HAS_PCH_CPT(dev)) {
1704 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
1705 POSTING_READ(intel_dp->output_reg);
1706 intel_wait_for_vblank(dev, intel_crtc->pipe);
1707 }
a4fc5ed6 1708
3cf2efb1
CW		 1709 /* Write the link configuration data */
1710 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1711 intel_dp->link_configuration,
1712 DP_LINK_CONFIGURATION_SIZE);
a4fc5ed6
KP		 1713
1714 DP |= DP_PORT_EN;
1a2eb460
KP		 1715
1716 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
e3421a18
ZW		 1717 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1718 else
1719 DP &= ~DP_LINK_TRAIN_MASK;
33a34e4e 1720 memset(intel_dp->train_set, 0, 4);
a4fc5ed6 1721 voltage = 0xff;
cdb0e95b
KP		 1722 voltage_tries = 0;
1723 loop_tries = 0;
a4fc5ed6
KP		 1724 clock_recovery = false;
1725 for (;;) {
33a34e4e 1726 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
93f62dad 1727 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 1728 uint32_t signal_levels;
417e822d 1729
1a2eb460
KP		 1730
1731 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1732 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1733 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1734 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
33a34e4e 1735 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1736 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1737 } else {
93f62dad
KP		 1738 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1739 DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n", signal_levels);
e3421a18
ZW		 1740 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1741 }
a4fc5ed6 1742
1a2eb460 1743 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
e3421a18
ZW		 1744 reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
1745 else
1746 reg = DP | DP_LINK_TRAIN_PAT_1;
1747
ea5b213a 1748 if (!intel_dp_set_link_train(intel_dp, reg,
81055854
AJ		 1749 DP_TRAINING_PATTERN_1 |
1750 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6 1751 break;
a4fc5ed6
KP		 1752 /* Set training pattern 1 */
1753
3cf2efb1 1754 udelay(100);
93f62dad
KP		 1755 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1756 DRM_ERROR("failed to get link status\n");
a4fc5ed6 1757 break;
93f62dad 1758 }
a4fc5ed6 1759
93f62dad
KP		 1760 if (intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1761 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 1762 clock_recovery = true;
1763 break;
1764 }
1765
1766 /* Check to see if we've tried the max voltage */
1767 for (i = 0; i < intel_dp->lane_count; i++)
1768 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 1769 break;
cdb0e95b
KP		 1770 if (i == intel_dp->lane_count) {
1771 ++loop_tries;
1772 if (loop_tries == 5) {
1773 DRM_DEBUG_KMS("too many full retries, give up\n");
1774 break;
1775 }
1776 memset(intel_dp->train_set, 0, 4);
1777 voltage_tries = 0;
1778 continue;
1779 }
a4fc5ed6 1780
3cf2efb1
CW		 1781 /* Check to see if we've tried the same voltage 5 times */
1782 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
cdb0e95b
KP		 1783 ++voltage_tries;
1784 if (voltage_tries == 5) {
1785 DRM_DEBUG_KMS("too many voltage retries, give up\n");
a4fc5ed6 1786 break;
cdb0e95b 1787 }
3cf2efb1 1788 } else
cdb0e95b 1789 voltage_tries = 0;
3cf2efb1 1790 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 1791
3cf2efb1 1792 /* Compute new intel_dp->train_set as requested by target */
93f62dad 1793 intel_get_adjust_train(intel_dp, link_status);
a4fc5ed6
KP		 1794 }
1795
33a34e4e
JB		 1796 intel_dp->DP = DP;
1797}
1798
1799static void
1800intel_dp_complete_link_train(struct intel_dp *intel_dp)
1801{
4ef69c7a 1802 struct drm_device *dev = intel_dp->base.base.dev;
33a34e4e
JB		 1803 struct drm_i915_private *dev_priv = dev->dev_private;
1804 bool channel_eq = false;
37f80975 1805 int tries, cr_tries;
33a34e4e
JB		 1806 u32 reg;
1807 uint32_t DP = intel_dp->DP;
1808
a4fc5ed6
KP		 1809 /* channel equalization */
1810 tries = 0;
37f80975 1811 cr_tries = 0;
a4fc5ed6
KP		 1812 channel_eq = false;
1813 for (;;) {
33a34e4e 1814 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
e3421a18 1815 uint32_t signal_levels;
93f62dad 1816 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 1817
37f80975
JB		 1818 if (cr_tries > 5) {
1819 DRM_ERROR("failed to train DP, aborting\n");
1820 intel_dp_link_down(intel_dp);
1821 break;
1822 }
1823
1a2eb460
KP		 1824 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1825 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1826 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1827 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
33a34e4e 1828 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1829 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1830 } else {
93f62dad 1831 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1832 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1833 }
1834
1a2eb460 1835 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
e3421a18
ZW		 1836 reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
1837 else
1838 reg = DP | DP_LINK_TRAIN_PAT_2;
a4fc5ed6
KP		 1839
1840 /* channel eq pattern */
ea5b213a 1841 if (!intel_dp_set_link_train(intel_dp, reg,
81055854
AJ		 1842 DP_TRAINING_PATTERN_2 |
1843 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6
KP		 1844 break;
1845
3cf2efb1 1846 udelay(400);
93f62dad 1847 if (!intel_dp_get_link_status(intel_dp, link_status))
a4fc5ed6 1848 break;
a4fc5ed6 1849
37f80975 1850 /* Make sure clock is still ok */
93f62dad 1851 if (!intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975
JB		 1852 intel_dp_start_link_train(intel_dp);
1853 cr_tries++;
1854 continue;
1855 }
1856
93f62dad 1857 if (intel_channel_eq_ok(intel_dp, link_status)) {
3cf2efb1
CW		 1858 channel_eq = true;
1859 break;
1860 }
a4fc5ed6 1861
37f80975
JB		 1862 /* Try 5 times, then try clock recovery if that fails */
1863 if (tries > 5) {
1864 intel_dp_link_down(intel_dp);
1865 intel_dp_start_link_train(intel_dp);
1866 tries = 0;
1867 cr_tries++;
1868 continue;
1869 }
a4fc5ed6 1870
3cf2efb1 1871 /* Compute new intel_dp->train_set as requested by target */
93f62dad 1872 intel_get_adjust_train(intel_dp, link_status);
3cf2efb1 1873 ++tries;
869184a6 1874 }
3cf2efb1 1875
1a2eb460 1876 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
e3421a18
ZW		 1877 reg = DP | DP_LINK_TRAIN_OFF_CPT;
1878 else
1879 reg = DP | DP_LINK_TRAIN_OFF;
1880
ea5b213a
CW		 1881 I915_WRITE(intel_dp->output_reg, reg);
1882 POSTING_READ(intel_dp->output_reg);
1883 intel_dp_aux_native_write_1(intel_dp,
a4fc5ed6
KP		 1884 DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1885}
1886
1887static void
ea5b213a 1888intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 1889{
4ef69c7a 1890 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6 1891 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 1892 uint32_t DP = intel_dp->DP;
a4fc5ed6 1893
1b39d6f3
CW		 1894 if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)
1895 return;
1896
28c97730 1897 DRM_DEBUG_KMS("\n");
32f9d658 1898
cfcb0fc9 1899 if (is_edp(intel_dp)) {
32f9d658 1900 DP &= ~DP_PLL_ENABLE;
ea5b213a
CW		 1901 I915_WRITE(intel_dp->output_reg, DP);
1902 POSTING_READ(intel_dp->output_reg);
32f9d658
ZW		 1903 udelay(100);
1904 }
1905
1a2eb460 1906 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
e3421a18 1907 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 1908 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 1909 } else {
1910 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 1911 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 1912 }
fe255d00 1913 POSTING_READ(intel_dp->output_reg);
5eb08b69 1914
fe255d00 1915 msleep(17);
5eb08b69 1916
417e822d 1917 if (is_edp(intel_dp)) {
1a2eb460 1918 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
417e822d
KP		 1919 DP |= DP_LINK_TRAIN_OFF_CPT;
1920 else
1921 DP |= DP_LINK_TRAIN_OFF;
1922 }
5bddd17f 1923
493a7081 1924 if (HAS_PCH_IBX(dev) &&
1b39d6f3 1925 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
31acbcc4
CW		 1926 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1927
5bddd17f
EA		 1928 /* Hardware workaround: leaving our transcoder select
1929 * set to transcoder B while it's off will prevent the
1930 * corresponding HDMI output on transcoder A.
1931 *
1932 * Combine this with another hardware workaround:
1933 * transcoder select bit can only be cleared while the
1934 * port is enabled.
1935 */
1936 DP &= ~DP_PIPEB_SELECT;
1937 I915_WRITE(intel_dp->output_reg, DP);
1938
1939 /* Changes to enable or select take place the vblank
1940 * after being written.
1941 */
31acbcc4
CW		 1942 if (crtc == NULL) {
1943 /* We can arrive here never having been attached
1944 * to a CRTC, for instance, due to inheriting
1945 * random state from the BIOS.
1946 *
1947 * If the pipe is not running, play safe and
1948 * wait for the clocks to stabilise before
1949 * continuing.
1950 */
1951 POSTING_READ(intel_dp->output_reg);
1952 msleep(50);
1953 } else
1954 intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
5bddd17f
EA		 1955 }
1956
832afda6 1957 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 1958 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1959 POSTING_READ(intel_dp->output_reg);
f01eca2e 1960 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 1961}
1962
26d61aad
KP		 1963static bool
1964intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 1965{
92fd8fd1 1966 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
0206e353 1967 sizeof(intel_dp->dpcd)) &&
92fd8fd1 1968 (intel_dp->dpcd[DP_DPCD_REV] != 0)) {
26d61aad 1969 return true;
92fd8fd1
KP		 1970 }
1971
26d61aad 1972 return false;
92fd8fd1
KP		 1973}
1974
0d198328
AJ		 1975static void
1976intel_dp_probe_oui(struct intel_dp *intel_dp)
1977{
1978 u8 buf[3];
1979
1980 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
1981 return;
1982
1983 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
1984 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
1985 buf[0], buf[1], buf[2]);
1986
1987 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
1988 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
1989 buf[0], buf[1], buf[2]);
1990}
1991
a60f0e38
JB		 1992static bool
1993intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
1994{
1995 int ret;
1996
1997 ret = intel_dp_aux_native_read_retry(intel_dp,
1998 DP_DEVICE_SERVICE_IRQ_VECTOR,
1999 sink_irq_vector, 1);
2000 if (!ret)
2001 return false;
2002
2003 return true;
2004}
2005
2006static void
2007intel_dp_handle_test_request(struct intel_dp *intel_dp)
2008{
2009 /* NAK by default */
2010 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_ACK);
2011}
2012
a4fc5ed6
KP		 2013/*
2014 * According to DP spec
2015 * 5.1.2:
2016 * 1. Read DPCD
2017 * 2. Configure link according to Receiver Capabilities
2018 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2019 * 4. Check link status on receipt of hot-plug interrupt
2020 */
2021
2022static void
ea5b213a 2023intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 2024{
a60f0e38 2025 u8 sink_irq_vector;
93f62dad 2026 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 2027
d2b996ac
KP		 2028 if (intel_dp->dpms_mode != DRM_MODE_DPMS_ON)
2029 return;
59cd09e1 2030
4ef69c7a 2031 if (!intel_dp->base.base.crtc)
a4fc5ed6
KP		 2032 return;
2033
92fd8fd1 2034 /* Try to read receiver status if the link appears to be up */
93f62dad 2035 if (!intel_dp_get_link_status(intel_dp, link_status)) {
ea5b213a 2036 intel_dp_link_down(intel_dp);
a4fc5ed6
KP		 2037 return;
2038 }
2039
92fd8fd1 2040 /* Now read the DPCD to see if it's actually running */
26d61aad 2041 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 2042 intel_dp_link_down(intel_dp);
2043 return;
2044 }
2045
a60f0e38
JB		 2046 /* Try to read the source of the interrupt */
2047 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2048 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2049 /* Clear interrupt source */
2050 intel_dp_aux_native_write_1(intel_dp,
2051 DP_DEVICE_SERVICE_IRQ_VECTOR,
2052 sink_irq_vector);
2053
2054 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2055 intel_dp_handle_test_request(intel_dp);
2056 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2057 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2058 }
2059
93f62dad 2060 if (!intel_channel_eq_ok(intel_dp, link_status)) {
92fd8fd1
KP		 2061 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2062 drm_get_encoder_name(&intel_dp->base.base));
33a34e4e
JB		 2063 intel_dp_start_link_train(intel_dp);
2064 intel_dp_complete_link_train(intel_dp);
2065 }
a4fc5ed6 2066}
a4fc5ed6 2067
71ba9000 2068static enum drm_connector_status
26d61aad 2069intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 2070{
26d61aad
KP		 2071 if (intel_dp_get_dpcd(intel_dp))
2072 return connector_status_connected;
2073 return connector_status_disconnected;
71ba9000
AJ		 2074}
2075
5eb08b69 2076static enum drm_connector_status
a9756bb5 2077ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 2078{
5eb08b69
ZW		 2079 enum drm_connector_status status;
2080
fe16d949
CW		 2081 /* Can't disconnect eDP, but you can close the lid... */
2082 if (is_edp(intel_dp)) {
2083 status = intel_panel_detect(intel_dp->base.base.dev);
2084 if (status == connector_status_unknown)
2085 status = connector_status_connected;
2086 return status;
2087 }
01cb9ea6 2088
26d61aad 2089 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 2090}
2091
a4fc5ed6 2092static enum drm_connector_status
a9756bb5 2093g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 2094{
4ef69c7a 2095 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6 2096 struct drm_i915_private *dev_priv = dev->dev_private;
10f76a38 2097 uint32_t bit;
5eb08b69 2098
ea5b213a 2099 switch (intel_dp->output_reg) {
a4fc5ed6 2100 case DP_B:
10f76a38 2101 bit = DPB_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2102 break;
2103 case DP_C:
10f76a38 2104 bit = DPC_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2105 break;
2106 case DP_D:
10f76a38 2107 bit = DPD_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2108 break;
2109 default:
2110 return connector_status_unknown;
2111 }
2112
10f76a38 2113 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 2114 return connector_status_disconnected;
2115
26d61aad 2116 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 2117}
2118
8c241fef
KP		 2119static struct edid *
2120intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2121{
2122 struct intel_dp *intel_dp = intel_attached_dp(connector);
2123 struct edid *edid;
2124
2125 ironlake_edp_panel_vdd_on(intel_dp);
2126 edid = drm_get_edid(connector, adapter);
bd943159 2127 ironlake_edp_panel_vdd_off(intel_dp, false);
8c241fef
KP		 2128 return edid;
2129}
2130
2131static int
2132intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2133{
2134 struct intel_dp *intel_dp = intel_attached_dp(connector);
2135 int ret;
2136
2137 ironlake_edp_panel_vdd_on(intel_dp);
2138 ret = intel_ddc_get_modes(connector, adapter);
bd943159 2139 ironlake_edp_panel_vdd_off(intel_dp, false);
8c241fef
KP		 2140 return ret;
2141}
2142
2143
a9756bb5
ZW		 2144/**
2145 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
2146 *
2147 * \return true if DP port is connected.
2148 * \return false if DP port is disconnected.
2149 */
2150static enum drm_connector_status
2151intel_dp_detect(struct drm_connector *connector, bool force)
2152{
2153 struct intel_dp *intel_dp = intel_attached_dp(connector);
2154 struct drm_device *dev = intel_dp->base.base.dev;
2155 enum drm_connector_status status;
2156 struct edid *edid = NULL;
2157
2158 intel_dp->has_audio = false;
2159
2160 if (HAS_PCH_SPLIT(dev))
2161 status = ironlake_dp_detect(intel_dp);
2162 else
2163 status = g4x_dp_detect(intel_dp);
1b9be9d0 2164
ac66ae83
AJ		 2165 DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
2166 intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
2167 intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
2168 intel_dp->dpcd[6], intel_dp->dpcd[7]);
1b9be9d0 2169
a9756bb5
ZW		 2170 if (status != connector_status_connected)
2171 return status;
2172
0d198328
AJ		 2173 intel_dp_probe_oui(intel_dp);
2174
c3e5f67b
DV		 2175 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2176 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 2177 } else {
8c241fef 2178 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
f684960e
CW		 2179 if (edid) {
2180 intel_dp->has_audio = drm_detect_monitor_audio(edid);
2181 connector->display_info.raw_edid = NULL;
2182 kfree(edid);
2183 }
a9756bb5
ZW		 2184 }
2185
2186 return connector_status_connected;
a4fc5ed6
KP		 2187}
2188
2189static int intel_dp_get_modes(struct drm_connector *connector)
2190{
df0e9248 2191 struct intel_dp *intel_dp = intel_attached_dp(connector);
4ef69c7a 2192 struct drm_device *dev = intel_dp->base.base.dev;
32f9d658
ZW		 2193 struct drm_i915_private *dev_priv = dev->dev_private;
2194 int ret;
a4fc5ed6
KP		 2195
2196 /* We should parse the EDID data and find out if it has an audio sink
2197 */
2198
8c241fef 2199 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
b9efc480 2200 if (ret) {
d15456de 2201 if (is_edp(intel_dp) && !intel_dp->panel_fixed_mode) {
b9efc480
ZY		 2202 struct drm_display_mode *newmode;
2203 list_for_each_entry(newmode, &connector->probed_modes,
2204 head) {
d15456de
KP		 2205 if ((newmode->type & DRM_MODE_TYPE_PREFERRED)) {
2206 intel_dp->panel_fixed_mode =
b9efc480
ZY		 2207 drm_mode_duplicate(dev, newmode);
2208 break;
2209 }
2210 }
2211 }
32f9d658 2212 return ret;
b9efc480 2213 }
32f9d658
ZW		 2214
2215 /* if eDP has no EDID, try to use fixed panel mode from VBT */
4d926461 2216 if (is_edp(intel_dp)) {
47f0eb22 2217 /* initialize panel mode from VBT if available for eDP */
d15456de
KP		 2218 if (intel_dp->panel_fixed_mode == NULL && dev_priv->lfp_lvds_vbt_mode != NULL) {
2219 intel_dp->panel_fixed_mode =
47f0eb22 2220 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
d15456de
KP		 2221 if (intel_dp->panel_fixed_mode) {
2222 intel_dp->panel_fixed_mode->type |=
47f0eb22
KP		 2223 DRM_MODE_TYPE_PREFERRED;
2224 }
2225 }
d15456de 2226 if (intel_dp->panel_fixed_mode) {
32f9d658 2227 struct drm_display_mode *mode;
d15456de 2228 mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode);
32f9d658
ZW		 2229 drm_mode_probed_add(connector, mode);
2230 return 1;
2231 }
2232 }
2233 return 0;
a4fc5ed6
KP		 2234}
2235
1aad7ac0
CW		 2236static bool
2237intel_dp_detect_audio(struct drm_connector *connector)
2238{
2239 struct intel_dp *intel_dp = intel_attached_dp(connector);
2240 struct edid *edid;
2241 bool has_audio = false;
2242
8c241fef 2243 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1aad7ac0
CW		 2244 if (edid) {
2245 has_audio = drm_detect_monitor_audio(edid);
2246
2247 connector->display_info.raw_edid = NULL;
2248 kfree(edid);
2249 }
2250
2251 return has_audio;
2252}
2253
f684960e
CW		 2254static int
2255intel_dp_set_property(struct drm_connector *connector,
2256 struct drm_property *property,
2257 uint64_t val)
2258{
e953fd7b 2259 struct drm_i915_private *dev_priv = connector->dev->dev_private;
f684960e
CW		 2260 struct intel_dp *intel_dp = intel_attached_dp(connector);
2261 int ret;
2262
2263 ret = drm_connector_property_set_value(connector, property, val);
2264 if (ret)
2265 return ret;
2266
3f43c48d 2267 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 2268 int i = val;
2269 bool has_audio;
2270
2271 if (i == intel_dp->force_audio)
f684960e
CW		 2272 return 0;
2273
1aad7ac0 2274 intel_dp->force_audio = i;
f684960e 2275
c3e5f67b 2276 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 2277 has_audio = intel_dp_detect_audio(connector);
2278 else
c3e5f67b 2279 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 2280
2281 if (has_audio == intel_dp->has_audio)
f684960e
CW		 2282 return 0;
2283
1aad7ac0 2284 intel_dp->has_audio = has_audio;
f684960e
CW		 2285 goto done;
2286 }
2287
e953fd7b
CW		 2288 if (property == dev_priv->broadcast_rgb_property) {
2289 if (val == !!intel_dp->color_range)
2290 return 0;
2291
2292 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
2293 goto done;
2294 }
2295
f684960e
CW		 2296 return -EINVAL;
2297
2298done:
2299 if (intel_dp->base.base.crtc) {
2300 struct drm_crtc *crtc = intel_dp->base.base.crtc;
2301 drm_crtc_helper_set_mode(crtc, &crtc->mode,
2302 crtc->x, crtc->y,
2303 crtc->fb);
2304 }
2305
2306 return 0;
2307}
2308
a4fc5ed6 2309static void
0206e353 2310intel_dp_destroy(struct drm_connector *connector)
a4fc5ed6 2311{
aaa6fd2a
MG		 2312 struct drm_device *dev = connector->dev;
2313
2314 if (intel_dpd_is_edp(dev))
2315 intel_panel_destroy_backlight(dev);
2316
a4fc5ed6
KP		 2317 drm_sysfs_connector_remove(connector);
2318 drm_connector_cleanup(connector);
55f78c43 2319 kfree(connector);
a4fc5ed6
KP		 2320}
2321
24d05927
DV		 2322static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2323{
2324 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2325
2326 i2c_del_adapter(&intel_dp->adapter);
2327 drm_encoder_cleanup(encoder);
bd943159
KP		 2328 if (is_edp(intel_dp)) {
2329 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2330 ironlake_panel_vdd_off_sync(intel_dp);
2331 }
24d05927
DV		 2332 kfree(intel_dp);
2333}
2334
a4fc5ed6
KP		 2335static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
2336 .dpms = intel_dp_dpms,
2337 .mode_fixup = intel_dp_mode_fixup,
d240f20f 2338 .prepare = intel_dp_prepare,
a4fc5ed6 2339 .mode_set = intel_dp_mode_set,
d240f20f 2340 .commit = intel_dp_commit,
a4fc5ed6
KP		 2341};
2342
2343static const struct drm_connector_funcs intel_dp_connector_funcs = {
2344 .dpms = drm_helper_connector_dpms,
a4fc5ed6
KP		 2345 .detect = intel_dp_detect,
2346 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 2347 .set_property = intel_dp_set_property,
a4fc5ed6
KP		 2348 .destroy = intel_dp_destroy,
2349};
2350
2351static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2352 .get_modes = intel_dp_get_modes,
2353 .mode_valid = intel_dp_mode_valid,
df0e9248 2354 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 2355};
2356
a4fc5ed6 2357static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 2358 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 2359};
2360
995b6762 2361static void
21d40d37 2362intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 2363{
ea5b213a 2364 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
c8110e52 2365
885a5014 2366 intel_dp_check_link_status(intel_dp);
c8110e52 2367}
6207937d 2368
e3421a18
ZW		 2369/* Return which DP Port should be selected for Transcoder DP control */
2370int
0206e353 2371intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 2372{
2373 struct drm_device *dev = crtc->dev;
2374 struct drm_mode_config *mode_config = &dev->mode_config;
2375 struct drm_encoder *encoder;
e3421a18
ZW		 2376
2377 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
ea5b213a
CW		 2378 struct intel_dp *intel_dp;
2379
d8201ab6 2380 if (encoder->crtc != crtc)
e3421a18
ZW		 2381 continue;
2382
ea5b213a 2383 intel_dp = enc_to_intel_dp(encoder);
417e822d
KP		 2384 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
2385 intel_dp->base.type == INTEL_OUTPUT_EDP)
ea5b213a 2386 return intel_dp->output_reg;
e3421a18 2387 }
ea5b213a 2388
e3421a18
ZW		 2389 return -1;
2390}
2391
36e83a18 2392/* check the VBT to see whether the eDP is on DP-D port */
cb0953d7 2393bool intel_dpd_is_edp(struct drm_device *dev)
36e83a18
ZY		 2394{
2395 struct drm_i915_private *dev_priv = dev->dev_private;
2396 struct child_device_config *p_child;
2397 int i;
2398
2399 if (!dev_priv->child_dev_num)
2400 return false;
2401
2402 for (i = 0; i < dev_priv->child_dev_num; i++) {
2403 p_child = dev_priv->child_dev + i;
2404
2405 if (p_child->dvo_port == PORT_IDPD &&
2406 p_child->device_type == DEVICE_TYPE_eDP)
2407 return true;
2408 }
2409 return false;
2410}
2411
f684960e
CW		 2412static void
2413intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2414{
3f43c48d 2415 intel_attach_force_audio_property(connector);
e953fd7b 2416 intel_attach_broadcast_rgb_property(connector);
f684960e
CW		 2417}
2418
a4fc5ed6
KP		 2419void
2420intel_dp_init(struct drm_device *dev, int output_reg)
2421{
2422 struct drm_i915_private *dev_priv = dev->dev_private;
2423 struct drm_connector *connector;
ea5b213a 2424 struct intel_dp *intel_dp;
21d40d37 2425 struct intel_encoder *intel_encoder;
55f78c43 2426 struct intel_connector *intel_connector;
5eb08b69 2427 const char *name = NULL;
b329530c 2428 int type;
a4fc5ed6 2429
ea5b213a
CW		 2430 intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
2431 if (!intel_dp)
a4fc5ed6
KP		 2432 return;
2433
3d3dc149 2434 intel_dp->output_reg = output_reg;
d2b996ac 2435 intel_dp->dpms_mode = -1;
3d3dc149 2436
55f78c43
ZW		 2437 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2438 if (!intel_connector) {
ea5b213a 2439 kfree(intel_dp);
55f78c43
ZW		 2440 return;
2441 }
ea5b213a 2442 intel_encoder = &intel_dp->base;
55f78c43 2443
ea5b213a 2444 if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
b329530c 2445 if (intel_dpd_is_edp(dev))
ea5b213a 2446 intel_dp->is_pch_edp = true;
b329530c 2447
cfcb0fc9 2448 if (output_reg == DP_A || is_pch_edp(intel_dp)) {
b329530c
AJ		 2449 type = DRM_MODE_CONNECTOR_eDP;
2450 intel_encoder->type = INTEL_OUTPUT_EDP;
2451 } else {
2452 type = DRM_MODE_CONNECTOR_DisplayPort;
2453 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2454 }
2455
55f78c43 2456 connector = &intel_connector->base;
b329530c 2457 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 2458 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2459
eb1f8e4f
DA		 2460 connector->polled = DRM_CONNECTOR_POLL_HPD;
2461
652af9d7 2462 if (output_reg == DP_B || output_reg == PCH_DP_B)
21d40d37 2463 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
652af9d7 2464 else if (output_reg == DP_C || output_reg == PCH_DP_C)
21d40d37 2465 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
652af9d7 2466 else if (output_reg == DP_D || output_reg == PCH_DP_D)
21d40d37 2467 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
f8aed700 2468
bd943159 2469 if (is_edp(intel_dp)) {
21d40d37 2470 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
bd943159
KP		 2471 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2472 ironlake_panel_vdd_work);
2473 }
6251ec0a 2474
27f8227b 2475 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
ee7b9f93 2476
a4fc5ed6
KP		 2477 connector->interlace_allowed = true;
2478 connector->doublescan_allowed = 0;
2479
4ef69c7a 2480 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
a4fc5ed6 2481 DRM_MODE_ENCODER_TMDS);
4ef69c7a 2482 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
a4fc5ed6 2483
df0e9248 2484 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 2485 drm_sysfs_connector_add(connector);
2486
2487 /* Set up the DDC bus. */
5eb08b69 2488 switch (output_reg) {
32f9d658
ZW		 2489 case DP_A:
2490 name = "DPDDC-A";
2491 break;
5eb08b69
ZW		 2492 case DP_B:
2493 case PCH_DP_B:
b01f2c3a 2494 dev_priv->hotplug_supported_mask |=
78d56d78 2495 DPB_HOTPLUG_INT_STATUS;
5eb08b69
ZW		 2496 name = "DPDDC-B";
2497 break;
2498 case DP_C:
2499 case PCH_DP_C:
b01f2c3a 2500 dev_priv->hotplug_supported_mask |=
78d56d78 2501 DPC_HOTPLUG_INT_STATUS;
5eb08b69
ZW		 2502 name = "DPDDC-C";
2503 break;
2504 case DP_D:
2505 case PCH_DP_D:
b01f2c3a 2506 dev_priv->hotplug_supported_mask |=
78d56d78 2507 DPD_HOTPLUG_INT_STATUS;
5eb08b69
ZW		 2508 name = "DPDDC-D";
2509 break;
2510 }
2511
89667383
JB		 2512 /* Cache some DPCD data in the eDP case */
2513 if (is_edp(intel_dp)) {
59f3e272 2514 bool ret;
f01eca2e
KP		 2515 struct edp_power_seq cur, vbt;
2516 u32 pp_on, pp_off, pp_div;
5d613501
JB		 2517
2518 pp_on = I915_READ(PCH_PP_ON_DELAYS);
f01eca2e 2519 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
5d613501 2520 pp_div = I915_READ(PCH_PP_DIVISOR);
89667383 2521
bfa3384a
JB		 2522 if (!pp_on || !pp_off || !pp_div) {
2523 DRM_INFO("bad panel power sequencing delays, disabling panel\n");
2524 intel_dp_encoder_destroy(&intel_dp->base.base);
2525 intel_dp_destroy(&intel_connector->base);
2526 return;
2527 }
2528
f01eca2e
KP		 2529 /* Pull timing values out of registers */
2530 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2531 PANEL_POWER_UP_DELAY_SHIFT;
2532
2533 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2534 PANEL_LIGHT_ON_DELAY_SHIFT;
f2e8b18a 2535
f01eca2e
KP		 2536 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2537 PANEL_LIGHT_OFF_DELAY_SHIFT;
2538
2539 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2540 PANEL_POWER_DOWN_DELAY_SHIFT;
2541
2542 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2543 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2544
2545 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2546 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2547
2548 vbt = dev_priv->edp.pps;
2549
2550 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2551 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2552
2553#define get_delay(field) ((max(cur.field, vbt.field) + 9) / 10)
2554
2555 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2556 intel_dp->backlight_on_delay = get_delay(t8);
2557 intel_dp->backlight_off_delay = get_delay(t9);
2558 intel_dp->panel_power_down_delay = get_delay(t10);
2559 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2560
2561 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2562 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2563 intel_dp->panel_power_cycle_delay);
2564
2565 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2566 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
5d613501
JB		 2567
2568 ironlake_edp_panel_vdd_on(intel_dp);
59f3e272 2569 ret = intel_dp_get_dpcd(intel_dp);
bd943159 2570 ironlake_edp_panel_vdd_off(intel_dp, false);
99ea7127 2571
59f3e272 2572 if (ret) {
7183dc29
JB		 2573 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2574 dev_priv->no_aux_handshake =
2575 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
89667383
JB		 2576 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2577 } else {
3d3dc149 2578 /* if this fails, presume the device is a ghost */
48898b03 2579 DRM_INFO("failed to retrieve link info, disabling eDP\n");
3d3dc149 2580 intel_dp_encoder_destroy(&intel_dp->base.base);
48898b03 2581 intel_dp_destroy(&intel_connector->base);
3d3dc149 2582 return;
89667383 2583 }
89667383
JB		 2584 }
2585
552fb0b7
KP		 2586 intel_dp_i2c_init(intel_dp, intel_connector, name);
2587
21d40d37 2588 intel_encoder->hot_plug = intel_dp_hot_plug;
a4fc5ed6 2589
4d926461 2590 if (is_edp(intel_dp)) {
aaa6fd2a
MG		 2591 dev_priv->int_edp_connector = connector;
2592 intel_panel_setup_backlight(dev);
32f9d658
ZW		 2593 }
2594
f684960e
CW		 2595 intel_dp_add_properties(intel_dp, connector);
2596
a4fc5ed6
KP		 2597 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2598 * 0xd. Failure to do so will result in spurious interrupts being
2599 * generated on the port when a cable is not attached.
2600 */
2601 if (IS_G4X(dev) && !IS_GM45(dev)) {
2602 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2603 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2604 }
2605}
Linux 6.x block layer and io_uring tree(s)