projects / linux-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit...
[linux-block.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
a4fc5ed6
KP		 30#include "drmP.h"
31#include "drm.h"
32#include "drm_crtc.h"
33#include "drm_crtc_helper.h"
34#include "intel_drv.h"
35#include "i915_drm.h"
36#include "i915_drv.h"
ab2c0672 37#include "drm_dp_helper.h"
a4fc5ed6 38
ae266c98 39
a4fc5ed6
KP		 40#define DP_LINK_STATUS_SIZE 6
41#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42
43#define DP_LINK_CONFIGURATION_SIZE 9
44
32f9d658
ZW		 45#define IS_eDP(i) ((i)->type == INTEL_OUTPUT_EDP)
46
a4fc5ed6
KP		 47struct intel_dp_priv {
48 uint32_t output_reg;
49 uint32_t DP;
50 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
51 uint32_t save_DP;
52 uint8_t save_link_configuration[DP_LINK_CONFIGURATION_SIZE];
53 bool has_audio;
c8110e52 54 int dpms_mode;
a4fc5ed6
KP		 55 uint8_t link_bw;
56 uint8_t lane_count;
57 uint8_t dpcd[4];
58 struct intel_output *intel_output;
59 struct i2c_adapter adapter;
60 struct i2c_algo_dp_aux_data algo;
61};
62
63static void
64intel_dp_link_train(struct intel_output *intel_output, uint32_t DP,
65 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]);
66
67static void
68intel_dp_link_down(struct intel_output *intel_output, uint32_t DP);
69
32f9d658
ZW		 70void
71intel_edp_link_config (struct intel_output *intel_output,
72 int *lane_num, int *link_bw)
73{
74 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
75
76 *lane_num = dp_priv->lane_count;
77 if (dp_priv->link_bw == DP_LINK_BW_1_62)
78 *link_bw = 162000;
79 else if (dp_priv->link_bw == DP_LINK_BW_2_7)
80 *link_bw = 270000;
81}
82
a4fc5ed6
KP		 83static int
84intel_dp_max_lane_count(struct intel_output *intel_output)
85{
86 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
87 int max_lane_count = 4;
88
89 if (dp_priv->dpcd[0] >= 0x11) {
90 max_lane_count = dp_priv->dpcd[2] & 0x1f;
91 switch (max_lane_count) {
92 case 1: case 2: case 4:
93 break;
94 default:
95 max_lane_count = 4;
96 }
97 }
98 return max_lane_count;
99}
100
101static int
102intel_dp_max_link_bw(struct intel_output *intel_output)
103{
104 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
105 int max_link_bw = dp_priv->dpcd[1];
106
107 switch (max_link_bw) {
108 case DP_LINK_BW_1_62:
109 case DP_LINK_BW_2_7:
110 break;
111 default:
112 max_link_bw = DP_LINK_BW_1_62;
113 break;
114 }
115 return max_link_bw;
116}
117
118static int
119intel_dp_link_clock(uint8_t link_bw)
120{
121 if (link_bw == DP_LINK_BW_2_7)
122 return 270000;
123 else
124 return 162000;
125}
126
127/* I think this is a fiction */
128static int
885a5fb5
ZW		 129intel_dp_link_required(struct drm_device *dev,
130 struct intel_output *intel_output, int pixel_clock)
a4fc5ed6 131{
885a5fb5
ZW		 132 struct drm_i915_private *dev_priv = dev->dev_private;
133
134 if (IS_eDP(intel_output))
135 return (pixel_clock * dev_priv->edp_bpp) / 8;
136 else
137 return pixel_clock * 3;
a4fc5ed6
KP		 138}
139
140static int
141intel_dp_mode_valid(struct drm_connector *connector,
142 struct drm_display_mode *mode)
143{
144 struct intel_output *intel_output = to_intel_output(connector);
145 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_output));
146 int max_lanes = intel_dp_max_lane_count(intel_output);
147
885a5fb5
ZW		 148 if (intel_dp_link_required(connector->dev, intel_output, mode->clock)
149 > max_link_clock * max_lanes)
a4fc5ed6
KP		 150 return MODE_CLOCK_HIGH;
151
152 if (mode->clock < 10000)
153 return MODE_CLOCK_LOW;
154
155 return MODE_OK;
156}
157
158static uint32_t
159pack_aux(uint8_t *src, int src_bytes)
160{
161 int i;
162 uint32_t v = 0;
163
164 if (src_bytes > 4)
165 src_bytes = 4;
166 for (i = 0; i < src_bytes; i++)
167 v |= ((uint32_t) src[i]) << ((3-i) * 8);
168 return v;
169}
170
171static void
172unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
173{
174 int i;
175 if (dst_bytes > 4)
176 dst_bytes = 4;
177 for (i = 0; i < dst_bytes; i++)
178 dst[i] = src >> ((3-i) * 8);
179}
180
fb0f8fbf
KP		 181/* hrawclock is 1/4 the FSB frequency */
182static int
183intel_hrawclk(struct drm_device *dev)
184{
185 struct drm_i915_private *dev_priv = dev->dev_private;
186 uint32_t clkcfg;
187
188 clkcfg = I915_READ(CLKCFG);
189 switch (clkcfg & CLKCFG_FSB_MASK) {
190 case CLKCFG_FSB_400:
191 return 100;
192 case CLKCFG_FSB_533:
193 return 133;
194 case CLKCFG_FSB_667:
195 return 166;
196 case CLKCFG_FSB_800:
197 return 200;
198 case CLKCFG_FSB_1067:
199 return 266;
200 case CLKCFG_FSB_1333:
201 return 333;
202 /* these two are just a guess; one of them might be right */
203 case CLKCFG_FSB_1600:
204 case CLKCFG_FSB_1600_ALT:
205 return 400;
206 default:
207 return 133;
208 }
209}
210
a4fc5ed6
KP		 211static int
212intel_dp_aux_ch(struct intel_output *intel_output,
213 uint8_t *send, int send_bytes,
214 uint8_t *recv, int recv_size)
215{
216 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
217 uint32_t output_reg = dp_priv->output_reg;
218 struct drm_device *dev = intel_output->base.dev;
219 struct drm_i915_private *dev_priv = dev->dev_private;
220 uint32_t ch_ctl = output_reg + 0x10;
221 uint32_t ch_data = ch_ctl + 4;
222 int i;
223 int recv_bytes;
224 uint32_t ctl;
225 uint32_t status;
fb0f8fbf
KP		 226 uint32_t aux_clock_divider;
227 int try;
a4fc5ed6
KP		 228
229 /* The clock divider is based off the hrawclk,
fb0f8fbf
KP		 230 * and would like to run at 2MHz. So, take the
231 * hrawclk value and divide by 2 and use that
a4fc5ed6 232 */
32f9d658
ZW		 233 if (IS_eDP(intel_output))
234 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
c619eed4 235 else if (HAS_PCH_SPLIT(dev))
f2b115e6 236 aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */
5eb08b69
ZW		 237 else
238 aux_clock_divider = intel_hrawclk(dev) / 2;
239
fb0f8fbf
KP		 240 /* Must try at least 3 times according to DP spec */
241 for (try = 0; try < 5; try++) {
242 /* Load the send data into the aux channel data registers */
243 for (i = 0; i < send_bytes; i += 4) {
a419aef8 244 uint32_t d = pack_aux(send + i, send_bytes - i);
fb0f8fbf
KP		 245
246 I915_WRITE(ch_data + i, d);
247 }
248
249 ctl = (DP_AUX_CH_CTL_SEND_BUSY |
250 DP_AUX_CH_CTL_TIME_OUT_400us |
251 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
252 (5 << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
253 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
254 DP_AUX_CH_CTL_DONE |
255 DP_AUX_CH_CTL_TIME_OUT_ERROR |
256 DP_AUX_CH_CTL_RECEIVE_ERROR);
257
258 /* Send the command and wait for it to complete */
259 I915_WRITE(ch_ctl, ctl);
260 (void) I915_READ(ch_ctl);
261 for (;;) {
262 udelay(100);
263 status = I915_READ(ch_ctl);
264 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
265 break;
266 }
267
268 /* Clear done status and any errors */
eebc863e 269 I915_WRITE(ch_ctl, (status |
fb0f8fbf
KP		 270 DP_AUX_CH_CTL_DONE |
271 DP_AUX_CH_CTL_TIME_OUT_ERROR |
272 DP_AUX_CH_CTL_RECEIVE_ERROR));
273 (void) I915_READ(ch_ctl);
274 if ((status & DP_AUX_CH_CTL_TIME_OUT_ERROR) == 0)
a4fc5ed6
KP		 275 break;
276 }
277
a4fc5ed6 278 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 279 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
a5b3da54 280 return -EBUSY;
a4fc5ed6
KP		 281 }
282
283 /* Check for timeout or receive error.
284 * Timeouts occur when the sink is not connected
285 */
a5b3da54 286 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 287 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
a5b3da54
KP		 288 return -EIO;
289 }
1ae8c0a5
KP		 290
291 /* Timeouts occur when the device isn't connected, so they're
292 * "normal" -- don't fill the kernel log with these */
a5b3da54 293 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 294 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
a5b3da54 295 return -ETIMEDOUT;
a4fc5ed6
KP		 296 }
297
298 /* Unload any bytes sent back from the other side */
299 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
300 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
301
302 if (recv_bytes > recv_size)
303 recv_bytes = recv_size;
304
305 for (i = 0; i < recv_bytes; i += 4) {
306 uint32_t d = I915_READ(ch_data + i);
307
308 unpack_aux(d, recv + i, recv_bytes - i);
309 }
310
311 return recv_bytes;
312}
313
314/* Write data to the aux channel in native mode */
315static int
316intel_dp_aux_native_write(struct intel_output *intel_output,
317 uint16_t address, uint8_t *send, int send_bytes)
318{
319 int ret;
320 uint8_t msg[20];
321 int msg_bytes;
322 uint8_t ack;
323
324 if (send_bytes > 16)
325 return -1;
326 msg[0] = AUX_NATIVE_WRITE << 4;
327 msg[1] = address >> 8;
eebc863e 328 msg[2] = address & 0xff;
a4fc5ed6
KP		 329 msg[3] = send_bytes - 1;
330 memcpy(&msg[4], send, send_bytes);
331 msg_bytes = send_bytes + 4;
332 for (;;) {
333 ret = intel_dp_aux_ch(intel_output, msg, msg_bytes, &ack, 1);
334 if (ret < 0)
335 return ret;
336 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
337 break;
338 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
339 udelay(100);
340 else
a5b3da54 341 return -EIO;
a4fc5ed6
KP		 342 }
343 return send_bytes;
344}
345
346/* Write a single byte to the aux channel in native mode */
347static int
348intel_dp_aux_native_write_1(struct intel_output *intel_output,
349 uint16_t address, uint8_t byte)
350{
351 return intel_dp_aux_native_write(intel_output, address, &byte, 1);
352}
353
354/* read bytes from a native aux channel */
355static int
356intel_dp_aux_native_read(struct intel_output *intel_output,
357 uint16_t address, uint8_t *recv, int recv_bytes)
358{
359 uint8_t msg[4];
360 int msg_bytes;
361 uint8_t reply[20];
362 int reply_bytes;
363 uint8_t ack;
364 int ret;
365
366 msg[0] = AUX_NATIVE_READ << 4;
367 msg[1] = address >> 8;
368 msg[2] = address & 0xff;
369 msg[3] = recv_bytes - 1;
370
371 msg_bytes = 4;
372 reply_bytes = recv_bytes + 1;
373
374 for (;;) {
375 ret = intel_dp_aux_ch(intel_output, msg, msg_bytes,
376 reply, reply_bytes);
a5b3da54
KP		 377 if (ret == 0)
378 return -EPROTO;
379 if (ret < 0)
a4fc5ed6
KP		 380 return ret;
381 ack = reply[0];
382 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
383 memcpy(recv, reply + 1, ret - 1);
384 return ret - 1;
385 }
386 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
387 udelay(100);
388 else
a5b3da54 389 return -EIO;
a4fc5ed6
KP		 390 }
391}
392
393static int
ab2c0672
DA		 394intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
395 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 396{
ab2c0672 397 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
a4fc5ed6
KP		 398 struct intel_dp_priv *dp_priv = container_of(adapter,
399 struct intel_dp_priv,
400 adapter);
401 struct intel_output *intel_output = dp_priv->intel_output;
ab2c0672
DA		 402 uint16_t address = algo_data->address;
403 uint8_t msg[5];
404 uint8_t reply[2];
405 int msg_bytes;
406 int reply_bytes;
407 int ret;
408
409 /* Set up the command byte */
410 if (mode & MODE_I2C_READ)
411 msg[0] = AUX_I2C_READ << 4;
412 else
413 msg[0] = AUX_I2C_WRITE << 4;
414
415 if (!(mode & MODE_I2C_STOP))
416 msg[0] |= AUX_I2C_MOT << 4;
a4fc5ed6 417
ab2c0672
DA		 418 msg[1] = address >> 8;
419 msg[2] = address;
420
421 switch (mode) {
422 case MODE_I2C_WRITE:
423 msg[3] = 0;
424 msg[4] = write_byte;
425 msg_bytes = 5;
426 reply_bytes = 1;
427 break;
428 case MODE_I2C_READ:
429 msg[3] = 0;
430 msg_bytes = 4;
431 reply_bytes = 2;
432 break;
433 default:
434 msg_bytes = 3;
435 reply_bytes = 1;
436 break;
437 }
438
439 for (;;) {
440 ret = intel_dp_aux_ch(intel_output,
441 msg, msg_bytes,
442 reply, reply_bytes);
443 if (ret < 0) {
3ff99164 444 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
ab2c0672
DA		 445 return ret;
446 }
447 switch (reply[0] & AUX_I2C_REPLY_MASK) {
448 case AUX_I2C_REPLY_ACK:
449 if (mode == MODE_I2C_READ) {
450 *read_byte = reply[1];
451 }
452 return reply_bytes - 1;
453 case AUX_I2C_REPLY_NACK:
3ff99164 454 DRM_DEBUG_KMS("aux_ch nack\n");
ab2c0672
DA		 455 return -EREMOTEIO;
456 case AUX_I2C_REPLY_DEFER:
3ff99164 457 DRM_DEBUG_KMS("aux_ch defer\n");
ab2c0672
DA		 458 udelay(100);
459 break;
460 default:
461 DRM_ERROR("aux_ch invalid reply 0x%02x\n", reply[0]);
462 return -EREMOTEIO;
463 }
464 }
a4fc5ed6
KP		 465}
466
467static int
468intel_dp_i2c_init(struct intel_output *intel_output, const char *name)
469{
470 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
471
d54e9d28 472 DRM_DEBUG_KMS("i2c_init %s\n", name);
a4fc5ed6
KP		 473 dp_priv->algo.running = false;
474 dp_priv->algo.address = 0;
475 dp_priv->algo.aux_ch = intel_dp_i2c_aux_ch;
476
477 memset(&dp_priv->adapter, '\0', sizeof (dp_priv->adapter));
478 dp_priv->adapter.owner = THIS_MODULE;
479 dp_priv->adapter.class = I2C_CLASS_DDC;
eebc863e
ZW		 480 strncpy (dp_priv->adapter.name, name, sizeof(dp_priv->adapter.name) - 1);
481 dp_priv->adapter.name[sizeof(dp_priv->adapter.name) - 1] = '\0';
a4fc5ed6
KP		 482 dp_priv->adapter.algo_data = &dp_priv->algo;
483 dp_priv->adapter.dev.parent = &intel_output->base.kdev;
484
485 return i2c_dp_aux_add_bus(&dp_priv->adapter);
486}
487
488static bool
489intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
490 struct drm_display_mode *adjusted_mode)
491{
492 struct intel_output *intel_output = enc_to_intel_output(encoder);
493 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
494 int lane_count, clock;
495 int max_lane_count = intel_dp_max_lane_count(intel_output);
496 int max_clock = intel_dp_max_link_bw(intel_output) == DP_LINK_BW_2_7 ? 1 : 0;
497 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
498
499 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
500 for (clock = 0; clock <= max_clock; clock++) {
501 int link_avail = intel_dp_link_clock(bws[clock]) * lane_count;
502
885a5fb5
ZW		 503 if (intel_dp_link_required(encoder->dev, intel_output, mode->clock)
504 <= link_avail) {
a4fc5ed6
KP		 505 dp_priv->link_bw = bws[clock];
506 dp_priv->lane_count = lane_count;
507 adjusted_mode->clock = intel_dp_link_clock(dp_priv->link_bw);
28c97730
ZY		 508 DRM_DEBUG_KMS("Display port link bw %02x lane "
509 "count %d clock %d\n",
a4fc5ed6
KP		 510 dp_priv->link_bw, dp_priv->lane_count,
511 adjusted_mode->clock);
512 return true;
513 }
514 }
515 }
516 return false;
517}
518
519struct intel_dp_m_n {
520 uint32_t tu;
521 uint32_t gmch_m;
522 uint32_t gmch_n;
523 uint32_t link_m;
524 uint32_t link_n;
525};
526
527static void
528intel_reduce_ratio(uint32_t *num, uint32_t *den)
529{
530 while (*num > 0xffffff || *den > 0xffffff) {
531 *num >>= 1;
532 *den >>= 1;
533 }
534}
535
536static void
537intel_dp_compute_m_n(int bytes_per_pixel,
538 int nlanes,
539 int pixel_clock,
540 int link_clock,
541 struct intel_dp_m_n *m_n)
542{
543 m_n->tu = 64;
544 m_n->gmch_m = pixel_clock * bytes_per_pixel;
545 m_n->gmch_n = link_clock * nlanes;
546 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
547 m_n->link_m = pixel_clock;
548 m_n->link_n = link_clock;
549 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
550}
551
552void
553intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
554 struct drm_display_mode *adjusted_mode)
555{
556 struct drm_device *dev = crtc->dev;
557 struct drm_mode_config *mode_config = &dev->mode_config;
558 struct drm_connector *connector;
559 struct drm_i915_private *dev_priv = dev->dev_private;
560 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
561 int lane_count = 4;
562 struct intel_dp_m_n m_n;
563
564 /*
565 * Find the lane count in the intel_output private
566 */
567 list_for_each_entry(connector, &mode_config->connector_list, head) {
568 struct intel_output *intel_output = to_intel_output(connector);
569 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
570
571 if (!connector->encoder || connector->encoder->crtc != crtc)
572 continue;
573
574 if (intel_output->type == INTEL_OUTPUT_DISPLAYPORT) {
575 lane_count = dp_priv->lane_count;
576 break;
577 }
578 }
579
580 /*
581 * Compute the GMCH and Link ratios. The '3' here is
582 * the number of bytes_per_pixel post-LUT, which we always
583 * set up for 8-bits of R/G/B, or 3 bytes total.
584 */
585 intel_dp_compute_m_n(3, lane_count,
586 mode->clock, adjusted_mode->clock, &m_n);
587
c619eed4 588 if (HAS_PCH_SPLIT(dev)) {
5eb08b69
ZW		 589 if (intel_crtc->pipe == 0) {
590 I915_WRITE(TRANSA_DATA_M1,
591 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
592 m_n.gmch_m);
593 I915_WRITE(TRANSA_DATA_N1, m_n.gmch_n);
594 I915_WRITE(TRANSA_DP_LINK_M1, m_n.link_m);
595 I915_WRITE(TRANSA_DP_LINK_N1, m_n.link_n);
596 } else {
597 I915_WRITE(TRANSB_DATA_M1,
598 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
599 m_n.gmch_m);
600 I915_WRITE(TRANSB_DATA_N1, m_n.gmch_n);
601 I915_WRITE(TRANSB_DP_LINK_M1, m_n.link_m);
602 I915_WRITE(TRANSB_DP_LINK_N1, m_n.link_n);
603 }
a4fc5ed6 604 } else {
5eb08b69
ZW		 605 if (intel_crtc->pipe == 0) {
606 I915_WRITE(PIPEA_GMCH_DATA_M,
607 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
608 m_n.gmch_m);
609 I915_WRITE(PIPEA_GMCH_DATA_N,
610 m_n.gmch_n);
611 I915_WRITE(PIPEA_DP_LINK_M, m_n.link_m);
612 I915_WRITE(PIPEA_DP_LINK_N, m_n.link_n);
613 } else {
614 I915_WRITE(PIPEB_GMCH_DATA_M,
615 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
616 m_n.gmch_m);
617 I915_WRITE(PIPEB_GMCH_DATA_N,
618 m_n.gmch_n);
619 I915_WRITE(PIPEB_DP_LINK_M, m_n.link_m);
620 I915_WRITE(PIPEB_DP_LINK_N, m_n.link_n);
621 }
a4fc5ed6
KP		 622 }
623}
624
625static void
626intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
627 struct drm_display_mode *adjusted_mode)
628{
629 struct intel_output *intel_output = enc_to_intel_output(encoder);
630 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
631 struct drm_crtc *crtc = intel_output->enc.crtc;
632 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
633
634 dp_priv->DP = (DP_LINK_TRAIN_OFF |
635 DP_VOLTAGE_0_4 |
636 DP_PRE_EMPHASIS_0 |
637 DP_SYNC_VS_HIGH |
638 DP_SYNC_HS_HIGH);
639
640 switch (dp_priv->lane_count) {
641 case 1:
642 dp_priv->DP |= DP_PORT_WIDTH_1;
643 break;
644 case 2:
645 dp_priv->DP |= DP_PORT_WIDTH_2;
646 break;
647 case 4:
648 dp_priv->DP |= DP_PORT_WIDTH_4;
649 break;
650 }
651 if (dp_priv->has_audio)
652 dp_priv->DP |= DP_AUDIO_OUTPUT_ENABLE;
653
654 memset(dp_priv->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
655 dp_priv->link_configuration[0] = dp_priv->link_bw;
656 dp_priv->link_configuration[1] = dp_priv->lane_count;
657
658 /*
659 * Check for DPCD version > 1.1,
660 * enable enahanced frame stuff in that case
661 */
662 if (dp_priv->dpcd[0] >= 0x11) {
663 dp_priv->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
664 dp_priv->DP |= DP_ENHANCED_FRAMING;
665 }
666
667 if (intel_crtc->pipe == 1)
668 dp_priv->DP |= DP_PIPEB_SELECT;
32f9d658
ZW		 669
670 if (IS_eDP(intel_output)) {
671 /* don't miss out required setting for eDP */
672 dp_priv->DP |= DP_PLL_ENABLE;
673 if (adjusted_mode->clock < 200000)
674 dp_priv->DP |= DP_PLL_FREQ_160MHZ;
675 else
676 dp_priv->DP |= DP_PLL_FREQ_270MHZ;
677 }
a4fc5ed6
KP		 678}
679
f2b115e6 680static void ironlake_edp_backlight_on (struct drm_device *dev)
32f9d658
ZW		 681{
682 struct drm_i915_private *dev_priv = dev->dev_private;
683 u32 pp;
684
28c97730 685 DRM_DEBUG_KMS("\n");
32f9d658
ZW		 686 pp = I915_READ(PCH_PP_CONTROL);
687 pp |= EDP_BLC_ENABLE;
688 I915_WRITE(PCH_PP_CONTROL, pp);
689}
690
f2b115e6 691static void ironlake_edp_backlight_off (struct drm_device *dev)
32f9d658
ZW		 692{
693 struct drm_i915_private *dev_priv = dev->dev_private;
694 u32 pp;
695
28c97730 696 DRM_DEBUG_KMS("\n");
32f9d658
ZW		 697 pp = I915_READ(PCH_PP_CONTROL);
698 pp &= ~EDP_BLC_ENABLE;
699 I915_WRITE(PCH_PP_CONTROL, pp);
700}
a4fc5ed6
KP		 701
702static void
703intel_dp_dpms(struct drm_encoder *encoder, int mode)
704{
705 struct intel_output *intel_output = enc_to_intel_output(encoder);
706 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
707 struct drm_device *dev = intel_output->base.dev;
708 struct drm_i915_private *dev_priv = dev->dev_private;
709 uint32_t dp_reg = I915_READ(dp_priv->output_reg);
710
711 if (mode != DRM_MODE_DPMS_ON) {
32f9d658 712 if (dp_reg & DP_PORT_EN) {
a4fc5ed6 713 intel_dp_link_down(intel_output, dp_priv->DP);
32f9d658 714 if (IS_eDP(intel_output))
f2b115e6 715 ironlake_edp_backlight_off(dev);
32f9d658 716 }
a4fc5ed6 717 } else {
32f9d658 718 if (!(dp_reg & DP_PORT_EN)) {
a4fc5ed6 719 intel_dp_link_train(intel_output, dp_priv->DP, dp_priv->link_configuration);
32f9d658 720 if (IS_eDP(intel_output))
f2b115e6 721 ironlake_edp_backlight_on(dev);
32f9d658 722 }
a4fc5ed6 723 }
c8110e52 724 dp_priv->dpms_mode = mode;
a4fc5ed6
KP		 725}
726
727/*
728 * Fetch AUX CH registers 0x202 - 0x207 which contain
729 * link status information
730 */
731static bool
732intel_dp_get_link_status(struct intel_output *intel_output,
733 uint8_t link_status[DP_LINK_STATUS_SIZE])
734{
735 int ret;
736
737 ret = intel_dp_aux_native_read(intel_output,
738 DP_LANE0_1_STATUS,
739 link_status, DP_LINK_STATUS_SIZE);
740 if (ret != DP_LINK_STATUS_SIZE)
741 return false;
742 return true;
743}
744
745static uint8_t
746intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
747 int r)
748{
749 return link_status[r - DP_LANE0_1_STATUS];
750}
751
752static void
753intel_dp_save(struct drm_connector *connector)
754{
755 struct intel_output *intel_output = to_intel_output(connector);
756 struct drm_device *dev = intel_output->base.dev;
757 struct drm_i915_private *dev_priv = dev->dev_private;
758 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
759
760 dp_priv->save_DP = I915_READ(dp_priv->output_reg);
761 intel_dp_aux_native_read(intel_output, DP_LINK_BW_SET,
762 dp_priv->save_link_configuration,
763 sizeof (dp_priv->save_link_configuration));
764}
765
766static uint8_t
767intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
768 int lane)
769{
770 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
771 int s = ((lane & 1) ?
772 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
773 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
774 uint8_t l = intel_dp_link_status(link_status, i);
775
776 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
777}
778
779static uint8_t
780intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
781 int lane)
782{
783 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
784 int s = ((lane & 1) ?
785 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
786 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
787 uint8_t l = intel_dp_link_status(link_status, i);
788
789 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
790}
791
792
793#if 0
794static char *voltage_names[] = {
795 "0.4V", "0.6V", "0.8V", "1.2V"
796};
797static char *pre_emph_names[] = {
798 "0dB", "3.5dB", "6dB", "9.5dB"
799};
800static char *link_train_names[] = {
801 "pattern 1", "pattern 2", "idle", "off"
802};
803#endif
804
805/*
806 * These are source-specific values; current Intel hardware supports
807 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
808 */
809#define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800
810
811static uint8_t
812intel_dp_pre_emphasis_max(uint8_t voltage_swing)
813{
814 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
815 case DP_TRAIN_VOLTAGE_SWING_400:
816 return DP_TRAIN_PRE_EMPHASIS_6;
817 case DP_TRAIN_VOLTAGE_SWING_600:
818 return DP_TRAIN_PRE_EMPHASIS_6;
819 case DP_TRAIN_VOLTAGE_SWING_800:
820 return DP_TRAIN_PRE_EMPHASIS_3_5;
821 case DP_TRAIN_VOLTAGE_SWING_1200:
822 default:
823 return DP_TRAIN_PRE_EMPHASIS_0;
824 }
825}
826
827static void
828intel_get_adjust_train(struct intel_output *intel_output,
829 uint8_t link_status[DP_LINK_STATUS_SIZE],
830 int lane_count,
831 uint8_t train_set[4])
832{
833 uint8_t v = 0;
834 uint8_t p = 0;
835 int lane;
836
837 for (lane = 0; lane < lane_count; lane++) {
838 uint8_t this_v = intel_get_adjust_request_voltage(link_status, lane);
839 uint8_t this_p = intel_get_adjust_request_pre_emphasis(link_status, lane);
840
841 if (this_v > v)
842 v = this_v;
843 if (this_p > p)
844 p = this_p;
845 }
846
847 if (v >= I830_DP_VOLTAGE_MAX)
848 v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
849
850 if (p >= intel_dp_pre_emphasis_max(v))
851 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
852
853 for (lane = 0; lane < 4; lane++)
854 train_set[lane] = v | p;
855}
856
857static uint32_t
858intel_dp_signal_levels(uint8_t train_set, int lane_count)
859{
860 uint32_t signal_levels = 0;
861
862 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
863 case DP_TRAIN_VOLTAGE_SWING_400:
864 default:
865 signal_levels |= DP_VOLTAGE_0_4;
866 break;
867 case DP_TRAIN_VOLTAGE_SWING_600:
868 signal_levels |= DP_VOLTAGE_0_6;
869 break;
870 case DP_TRAIN_VOLTAGE_SWING_800:
871 signal_levels |= DP_VOLTAGE_0_8;
872 break;
873 case DP_TRAIN_VOLTAGE_SWING_1200:
874 signal_levels |= DP_VOLTAGE_1_2;
875 break;
876 }
877 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
878 case DP_TRAIN_PRE_EMPHASIS_0:
879 default:
880 signal_levels |= DP_PRE_EMPHASIS_0;
881 break;
882 case DP_TRAIN_PRE_EMPHASIS_3_5:
883 signal_levels |= DP_PRE_EMPHASIS_3_5;
884 break;
885 case DP_TRAIN_PRE_EMPHASIS_6:
886 signal_levels |= DP_PRE_EMPHASIS_6;
887 break;
888 case DP_TRAIN_PRE_EMPHASIS_9_5:
889 signal_levels |= DP_PRE_EMPHASIS_9_5;
890 break;
891 }
892 return signal_levels;
893}
894
895static uint8_t
896intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
897 int lane)
898{
899 int i = DP_LANE0_1_STATUS + (lane >> 1);
900 int s = (lane & 1) * 4;
901 uint8_t l = intel_dp_link_status(link_status, i);
902
903 return (l >> s) & 0xf;
904}
905
906/* Check for clock recovery is done on all channels */
907static bool
908intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
909{
910 int lane;
911 uint8_t lane_status;
912
913 for (lane = 0; lane < lane_count; lane++) {
914 lane_status = intel_get_lane_status(link_status, lane);
915 if ((lane_status & DP_LANE_CR_DONE) == 0)
916 return false;
917 }
918 return true;
919}
920
921/* Check to see if channel eq is done on all channels */
922#define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
923 DP_LANE_CHANNEL_EQ_DONE|\
924 DP_LANE_SYMBOL_LOCKED)
925static bool
926intel_channel_eq_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
927{
928 uint8_t lane_align;
929 uint8_t lane_status;
930 int lane;
931
932 lane_align = intel_dp_link_status(link_status,
933 DP_LANE_ALIGN_STATUS_UPDATED);
934 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
935 return false;
936 for (lane = 0; lane < lane_count; lane++) {
937 lane_status = intel_get_lane_status(link_status, lane);
938 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
939 return false;
940 }
941 return true;
942}
943
944static bool
945intel_dp_set_link_train(struct intel_output *intel_output,
946 uint32_t dp_reg_value,
947 uint8_t dp_train_pat,
948 uint8_t train_set[4],
949 bool first)
950{
951 struct drm_device *dev = intel_output->base.dev;
952 struct drm_i915_private *dev_priv = dev->dev_private;
953 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
954 int ret;
955
956 I915_WRITE(dp_priv->output_reg, dp_reg_value);
957 POSTING_READ(dp_priv->output_reg);
958 if (first)
959 intel_wait_for_vblank(dev);
960
961 intel_dp_aux_native_write_1(intel_output,
962 DP_TRAINING_PATTERN_SET,
963 dp_train_pat);
964
965 ret = intel_dp_aux_native_write(intel_output,
966 DP_TRAINING_LANE0_SET, train_set, 4);
967 if (ret != 4)
968 return false;
969
970 return true;
971}
972
973static void
974intel_dp_link_train(struct intel_output *intel_output, uint32_t DP,
975 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE])
976{
977 struct drm_device *dev = intel_output->base.dev;
978 struct drm_i915_private *dev_priv = dev->dev_private;
979 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
980 uint8_t train_set[4];
981 uint8_t link_status[DP_LINK_STATUS_SIZE];
982 int i;
983 uint8_t voltage;
984 bool clock_recovery = false;
985 bool channel_eq = false;
986 bool first = true;
987 int tries;
988
989 /* Write the link configuration data */
990 intel_dp_aux_native_write(intel_output, 0x100,
991 link_configuration, DP_LINK_CONFIGURATION_SIZE);
992
993 DP |= DP_PORT_EN;
994 DP &= ~DP_LINK_TRAIN_MASK;
995 memset(train_set, 0, 4);
996 voltage = 0xff;
997 tries = 0;
998 clock_recovery = false;
999 for (;;) {
1000 /* Use train_set[0] to set the voltage and pre emphasis values */
1001 uint32_t signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count);
1002 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1003
1004 if (!intel_dp_set_link_train(intel_output, DP | DP_LINK_TRAIN_PAT_1,
1005 DP_TRAINING_PATTERN_1, train_set, first))
1006 break;
1007 first = false;
1008 /* Set training pattern 1 */
1009
1010 udelay(100);
1011 if (!intel_dp_get_link_status(intel_output, link_status))
1012 break;
1013
1014 if (intel_clock_recovery_ok(link_status, dp_priv->lane_count)) {
1015 clock_recovery = true;
1016 break;
1017 }
1018
1019 /* Check to see if we've tried the max voltage */
1020 for (i = 0; i < dp_priv->lane_count; i++)
1021 if ((train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1022 break;
1023 if (i == dp_priv->lane_count)
1024 break;
1025
1026 /* Check to see if we've tried the same voltage 5 times */
1027 if ((train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1028 ++tries;
1029 if (tries == 5)
1030 break;
1031 } else
1032 tries = 0;
1033 voltage = train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1034
1035 /* Compute new train_set as requested by target */
1036 intel_get_adjust_train(intel_output, link_status, dp_priv->lane_count, train_set);
1037 }
1038
1039 /* channel equalization */
1040 tries = 0;
1041 channel_eq = false;
1042 for (;;) {
1043 /* Use train_set[0] to set the voltage and pre emphasis values */
1044 uint32_t signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count);
1045 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1046
1047 /* channel eq pattern */
1048 if (!intel_dp_set_link_train(intel_output, DP | DP_LINK_TRAIN_PAT_2,
1049 DP_TRAINING_PATTERN_2, train_set,
1050 false))
1051 break;
1052
1053 udelay(400);
1054 if (!intel_dp_get_link_status(intel_output, link_status))
1055 break;
1056
1057 if (intel_channel_eq_ok(link_status, dp_priv->lane_count)) {
1058 channel_eq = true;
1059 break;
1060 }
1061
1062 /* Try 5 times */
1063 if (tries > 5)
1064 break;
1065
1066 /* Compute new train_set as requested by target */
1067 intel_get_adjust_train(intel_output, link_status, dp_priv->lane_count, train_set);
1068 ++tries;
1069 }
1070
1071 I915_WRITE(dp_priv->output_reg, DP | DP_LINK_TRAIN_OFF);
1072 POSTING_READ(dp_priv->output_reg);
1073 intel_dp_aux_native_write_1(intel_output,
1074 DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1075}
1076
1077static void
1078intel_dp_link_down(struct intel_output *intel_output, uint32_t DP)
1079{
1080 struct drm_device *dev = intel_output->base.dev;
1081 struct drm_i915_private *dev_priv = dev->dev_private;
1082 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
1083
28c97730 1084 DRM_DEBUG_KMS("\n");
32f9d658
ZW		 1085
1086 if (IS_eDP(intel_output)) {
1087 DP &= ~DP_PLL_ENABLE;
1088 I915_WRITE(dp_priv->output_reg, DP);
1089 POSTING_READ(dp_priv->output_reg);
1090 udelay(100);
1091 }
1092
5eb08b69
ZW		 1093 DP &= ~DP_LINK_TRAIN_MASK;
1094 I915_WRITE(dp_priv->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1095 POSTING_READ(dp_priv->output_reg);
1096
1097 udelay(17000);
1098
32f9d658
ZW		 1099 if (IS_eDP(intel_output))
1100 DP |= DP_LINK_TRAIN_OFF;
a4fc5ed6
KP		 1101 I915_WRITE(dp_priv->output_reg, DP & ~DP_PORT_EN);
1102 POSTING_READ(dp_priv->output_reg);
1103}
1104
1105static void
1106intel_dp_restore(struct drm_connector *connector)
1107{
1108 struct intel_output *intel_output = to_intel_output(connector);
1109 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
1110
1111 if (dp_priv->save_DP & DP_PORT_EN)
1112 intel_dp_link_train(intel_output, dp_priv->save_DP, dp_priv->save_link_configuration);
1113 else
1114 intel_dp_link_down(intel_output, dp_priv->save_DP);
1115}
1116
a4fc5ed6
KP		 1117/*
1118 * According to DP spec
1119 * 5.1.2:
1120 * 1. Read DPCD
1121 * 2. Configure link according to Receiver Capabilities
1122 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
1123 * 4. Check link status on receipt of hot-plug interrupt
1124 */
1125
1126static void
1127intel_dp_check_link_status(struct intel_output *intel_output)
1128{
1129 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
1130 uint8_t link_status[DP_LINK_STATUS_SIZE];
1131
1132 if (!intel_output->enc.crtc)
1133 return;
1134
1135 if (!intel_dp_get_link_status(intel_output, link_status)) {
1136 intel_dp_link_down(intel_output, dp_priv->DP);
1137 return;
1138 }
1139
1140 if (!intel_channel_eq_ok(link_status, dp_priv->lane_count))
1141 intel_dp_link_train(intel_output, dp_priv->DP, dp_priv->link_configuration);
1142}
a4fc5ed6 1143
5eb08b69 1144static enum drm_connector_status
f2b115e6 1145ironlake_dp_detect(struct drm_connector *connector)
5eb08b69
ZW		 1146{
1147 struct intel_output *intel_output = to_intel_output(connector);
1148 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
1149 enum drm_connector_status status;
1150
1151 status = connector_status_disconnected;
1152 if (intel_dp_aux_native_read(intel_output,
1153 0x000, dp_priv->dpcd,
1154 sizeof (dp_priv->dpcd)) == sizeof (dp_priv->dpcd))
1155 {
1156 if (dp_priv->dpcd[0] != 0)
1157 status = connector_status_connected;
1158 }
1159 return status;
1160}
1161
a4fc5ed6
KP		 1162/**
1163 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1164 *
1165 * \return true if DP port is connected.
1166 * \return false if DP port is disconnected.
1167 */
1168static enum drm_connector_status
1169intel_dp_detect(struct drm_connector *connector)
1170{
1171 struct intel_output *intel_output = to_intel_output(connector);
1172 struct drm_device *dev = intel_output->base.dev;
1173 struct drm_i915_private *dev_priv = dev->dev_private;
1174 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
1175 uint32_t temp, bit;
1176 enum drm_connector_status status;
1177
1178 dp_priv->has_audio = false;
1179
c619eed4 1180 if (HAS_PCH_SPLIT(dev))
f2b115e6 1181 return ironlake_dp_detect(connector);
5eb08b69 1182
a4fc5ed6
KP		 1183 temp = I915_READ(PORT_HOTPLUG_EN);
1184
1185 I915_WRITE(PORT_HOTPLUG_EN,
1186 temp |
1187 DPB_HOTPLUG_INT_EN |
1188 DPC_HOTPLUG_INT_EN |
1189 DPD_HOTPLUG_INT_EN);
1190
1191 POSTING_READ(PORT_HOTPLUG_EN);
1192
1193 switch (dp_priv->output_reg) {
1194 case DP_B:
1195 bit = DPB_HOTPLUG_INT_STATUS;
1196 break;
1197 case DP_C:
1198 bit = DPC_HOTPLUG_INT_STATUS;
1199 break;
1200 case DP_D:
1201 bit = DPD_HOTPLUG_INT_STATUS;
1202 break;
1203 default:
1204 return connector_status_unknown;
1205 }
1206
1207 temp = I915_READ(PORT_HOTPLUG_STAT);
1208
1209 if ((temp & bit) == 0)
1210 return connector_status_disconnected;
1211
1212 status = connector_status_disconnected;
1213 if (intel_dp_aux_native_read(intel_output,
1214 0x000, dp_priv->dpcd,
1215 sizeof (dp_priv->dpcd)) == sizeof (dp_priv->dpcd))
1216 {
1217 if (dp_priv->dpcd[0] != 0)
1218 status = connector_status_connected;
1219 }
1220 return status;
1221}
1222
1223static int intel_dp_get_modes(struct drm_connector *connector)
1224{
1225 struct intel_output *intel_output = to_intel_output(connector);
32f9d658
ZW		 1226 struct drm_device *dev = intel_output->base.dev;
1227 struct drm_i915_private *dev_priv = dev->dev_private;
1228 int ret;
a4fc5ed6
KP		 1229
1230 /* We should parse the EDID data and find out if it has an audio sink
1231 */
1232
32f9d658
ZW		 1233 ret = intel_ddc_get_modes(intel_output);
1234 if (ret)
1235 return ret;
1236
1237 /* if eDP has no EDID, try to use fixed panel mode from VBT */
1238 if (IS_eDP(intel_output)) {
1239 if (dev_priv->panel_fixed_mode != NULL) {
1240 struct drm_display_mode *mode;
1241 mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode);
1242 drm_mode_probed_add(connector, mode);
1243 return 1;
1244 }
1245 }
1246 return 0;
a4fc5ed6
KP		 1247}
1248
1249static void
1250intel_dp_destroy (struct drm_connector *connector)
1251{
1252 struct intel_output *intel_output = to_intel_output(connector);
1253
1254 if (intel_output->i2c_bus)
1255 intel_i2c_destroy(intel_output->i2c_bus);
1256 drm_sysfs_connector_remove(connector);
1257 drm_connector_cleanup(connector);
1258 kfree(intel_output);
1259}
1260
1261static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
1262 .dpms = intel_dp_dpms,
1263 .mode_fixup = intel_dp_mode_fixup,
1264 .prepare = intel_encoder_prepare,
1265 .mode_set = intel_dp_mode_set,
1266 .commit = intel_encoder_commit,
1267};
1268
1269static const struct drm_connector_funcs intel_dp_connector_funcs = {
1270 .dpms = drm_helper_connector_dpms,
1271 .save = intel_dp_save,
1272 .restore = intel_dp_restore,
1273 .detect = intel_dp_detect,
1274 .fill_modes = drm_helper_probe_single_connector_modes,
1275 .destroy = intel_dp_destroy,
1276};
1277
1278static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
1279 .get_modes = intel_dp_get_modes,
1280 .mode_valid = intel_dp_mode_valid,
1281 .best_encoder = intel_best_encoder,
1282};
1283
1284static void intel_dp_enc_destroy(struct drm_encoder *encoder)
1285{
1286 drm_encoder_cleanup(encoder);
1287}
1288
1289static const struct drm_encoder_funcs intel_dp_enc_funcs = {
1290 .destroy = intel_dp_enc_destroy,
1291};
1292
c8110e52
KP		 1293void
1294intel_dp_hot_plug(struct intel_output *intel_output)
1295{
1296 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
1297
1298 if (dp_priv->dpms_mode == DRM_MODE_DPMS_ON)
1299 intel_dp_check_link_status(intel_output);
1300}
6207937d 1301
a4fc5ed6
KP		 1302void
1303intel_dp_init(struct drm_device *dev, int output_reg)
1304{
1305 struct drm_i915_private *dev_priv = dev->dev_private;
1306 struct drm_connector *connector;
1307 struct intel_output *intel_output;
1308 struct intel_dp_priv *dp_priv;
5eb08b69 1309 const char *name = NULL;
a4fc5ed6
KP		 1310
1311 intel_output = kcalloc(sizeof(struct intel_output) +
1312 sizeof(struct intel_dp_priv), 1, GFP_KERNEL);
1313 if (!intel_output)
1314 return;
1315
1316 dp_priv = (struct intel_dp_priv *)(intel_output + 1);
1317
1318 connector = &intel_output->base;
1319 drm_connector_init(dev, connector, &intel_dp_connector_funcs,
1320 DRM_MODE_CONNECTOR_DisplayPort);
1321 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
1322
32f9d658
ZW		 1323 if (output_reg == DP_A)
1324 intel_output->type = INTEL_OUTPUT_EDP;
1325 else
1326 intel_output->type = INTEL_OUTPUT_DISPLAYPORT;
a4fc5ed6 1327
652af9d7 1328 if (output_reg == DP_B || output_reg == PCH_DP_B)
f8aed700 1329 intel_output->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
652af9d7 1330 else if (output_reg == DP_C || output_reg == PCH_DP_C)
f8aed700 1331 intel_output->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
652af9d7 1332 else if (output_reg == DP_D || output_reg == PCH_DP_D)
f8aed700
ML		 1333 intel_output->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
1334
6251ec0a 1335 if (IS_eDP(intel_output))
7c8460db 1336 intel_output->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
6251ec0a
ZW		 1337
1338 intel_output->crtc_mask = (1 << 0) | (1 << 1);
a4fc5ed6
KP		 1339 connector->interlace_allowed = true;
1340 connector->doublescan_allowed = 0;
1341
1342 dp_priv->intel_output = intel_output;
1343 dp_priv->output_reg = output_reg;
1344 dp_priv->has_audio = false;
c8110e52 1345 dp_priv->dpms_mode = DRM_MODE_DPMS_ON;
a4fc5ed6
KP		 1346 intel_output->dev_priv = dp_priv;
1347
1348 drm_encoder_init(dev, &intel_output->enc, &intel_dp_enc_funcs,
1349 DRM_MODE_ENCODER_TMDS);
1350 drm_encoder_helper_add(&intel_output->enc, &intel_dp_helper_funcs);
1351
1352 drm_mode_connector_attach_encoder(&intel_output->base,
1353 &intel_output->enc);
1354 drm_sysfs_connector_add(connector);
1355
1356 /* Set up the DDC bus. */
5eb08b69 1357 switch (output_reg) {
32f9d658
ZW		 1358 case DP_A:
1359 name = "DPDDC-A";
1360 break;
5eb08b69
ZW		 1361 case DP_B:
1362 case PCH_DP_B:
b01f2c3a
JB		 1363 dev_priv->hotplug_supported_mask |=
1364 HDMIB_HOTPLUG_INT_STATUS;
5eb08b69
ZW		 1365 name = "DPDDC-B";
1366 break;
1367 case DP_C:
1368 case PCH_DP_C:
b01f2c3a
JB		 1369 dev_priv->hotplug_supported_mask |=
1370 HDMIC_HOTPLUG_INT_STATUS;
5eb08b69
ZW		 1371 name = "DPDDC-C";
1372 break;
1373 case DP_D:
1374 case PCH_DP_D:
b01f2c3a
JB		 1375 dev_priv->hotplug_supported_mask |=
1376 HDMID_HOTPLUG_INT_STATUS;
5eb08b69
ZW		 1377 name = "DPDDC-D";
1378 break;
1379 }
1380
1381 intel_dp_i2c_init(intel_output, name);
32f9d658 1382
a4fc5ed6 1383 intel_output->ddc_bus = &dp_priv->adapter;
c8110e52 1384 intel_output->hot_plug = intel_dp_hot_plug;
a4fc5ed6 1385
32f9d658
ZW		 1386 if (output_reg == DP_A) {
1387 /* initialize panel mode from VBT if available for eDP */
1388 if (dev_priv->lfp_lvds_vbt_mode) {
1389 dev_priv->panel_fixed_mode =
1390 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
1391 if (dev_priv->panel_fixed_mode) {
1392 dev_priv->panel_fixed_mode->type |=
1393 DRM_MODE_TYPE_PREFERRED;
1394 }
1395 }
1396 }
1397
a4fc5ed6
KP		 1398 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1399 * 0xd. Failure to do so will result in spurious interrupts being
1400 * generated on the port when a cable is not attached.
1401 */
1402 if (IS_G4X(dev) && !IS_GM45(dev)) {
1403 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1404 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1405 }
1406}
Linux 6.x block layer and io_uring tree(s)