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drm/i915/lspcon: Fail LSPCON probe if the start of DPCD can't be read
[linux-block.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
01527b31
CT		 31#include <linux/notifier.h>
32#include <linux/reboot.h>
760285e7 33#include <drm/drmP.h>
c6f95f27 34#include <drm/drm_atomic_helper.h>
760285e7
DH		 35#include <drm/drm_crtc.h>
36#include <drm/drm_crtc_helper.h>
37#include <drm/drm_edid.h>
a4fc5ed6 38#include "intel_drv.h"
760285e7 39#include <drm/i915_drm.h>
a4fc5ed6 40#include "i915_drv.h"
a4fc5ed6 41
a4fc5ed6
KP		 42#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
43
559be30c
TP		 44/* Compliance test status bits */
45#define INTEL_DP_RESOLUTION_SHIFT_MASK 0
46#define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
47#define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
48#define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
49
9dd4ffdf 50struct dp_link_dpll {
840b32b7 51 int clock;
9dd4ffdf
CML		 52 struct dpll dpll;
53};
54
55static const struct dp_link_dpll gen4_dpll[] = {
840b32b7 56 { 162000,
9dd4ffdf 57 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
840b32b7 58 { 270000,
9dd4ffdf
CML		 59 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
60};
61
62static const struct dp_link_dpll pch_dpll[] = {
840b32b7 63 { 162000,
9dd4ffdf 64 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
840b32b7 65 { 270000,
9dd4ffdf
CML		 66 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
67};
68
65ce4bf5 69static const struct dp_link_dpll vlv_dpll[] = {
840b32b7 70 { 162000,
58f6e632 71 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
840b32b7 72 { 270000,
65ce4bf5
CML		 73 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
74};
75
ef9348c8
CML		 76/*
77 * CHV supports eDP 1.4 that have more link rates.
78 * Below only provides the fixed rate but exclude variable rate.
79 */
80static const struct dp_link_dpll chv_dpll[] = {
81 /*
82 * CHV requires to program fractional division for m2.
83 * m2 is stored in fixed point format using formula below
84 * (m2_int << 22) | m2_fraction
85 */
840b32b7 86 { 162000, /* m2_int = 32, m2_fraction = 1677722 */
ef9348c8 87 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
840b32b7 88 { 270000, /* m2_int = 27, m2_fraction = 0 */
ef9348c8 89 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
840b32b7 90 { 540000, /* m2_int = 27, m2_fraction = 0 */
ef9348c8
CML		 91 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
92};
637a9c63 93
64987fc5
SJ		 94static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
95 324000, 432000, 540000 };
637a9c63 96static const int skl_rates[] = { 162000, 216000, 270000,
f4896f15
VS		 97 324000, 432000, 540000 };
98static const int default_rates[] = { 162000, 270000, 540000 };
ef9348c8 99
cfcb0fc9
JB		 100/**
101 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
102 * @intel_dp: DP struct
103 *
104 * If a CPU or PCH DP output is attached to an eDP panel, this function
105 * will return true, and false otherwise.
106 */
107static bool is_edp(struct intel_dp *intel_dp)
108{
da63a9f2
PZ		 109 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
110
111 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 112}
113
68b4d824 114static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 115{
68b4d824
ID		 116 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
117
118 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 119}
120
df0e9248
CW		 121static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
122{
fa90ecef 123 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 124}
125
ea5b213a 126static void intel_dp_link_down(struct intel_dp *intel_dp);
1e0560e0 127static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 128static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
093e3f13 129static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
a8c3344e
VS		 130static void vlv_steal_power_sequencer(struct drm_device *dev,
131 enum pipe pipe);
f21a2198 132static void intel_dp_unset_edid(struct intel_dp *intel_dp);
a4fc5ed6 133
ed4e9c1d
VS		 134static int
135intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 136{
7183dc29 137 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 138
139 switch (max_link_bw) {
140 case DP_LINK_BW_1_62:
141 case DP_LINK_BW_2_7:
1db10e28 142 case DP_LINK_BW_5_4:
d4eead50 143 break;
a4fc5ed6 144 default:
d4eead50
ID		 145 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
146 max_link_bw);
a4fc5ed6
KP		 147 max_link_bw = DP_LINK_BW_1_62;
148 break;
149 }
150 return max_link_bw;
151}
152
eeb6324d
PZ		 153static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
154{
155 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
eeb6324d
PZ		 156 u8 source_max, sink_max;
157
ccb1a831 158 source_max = intel_dig_port->max_lanes;
eeb6324d
PZ		 159 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
160
161 return min(source_max, sink_max);
162}
163
cd9dde44
AJ		 164/*
165 * The units on the numbers in the next two are... bizarre. Examples will
166 * make it clearer; this one parallels an example in the eDP spec.
167 *
168 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
169 *
170 * 270000 * 1 * 8 / 10 == 216000
171 *
172 * The actual data capacity of that configuration is 2.16Gbit/s, so the
173 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
174 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
175 * 119000. At 18bpp that's 2142000 kilobits per second.
176 *
177 * Thus the strange-looking division by 10 in intel_dp_link_required, to
178 * get the result in decakilobits instead of kilobits.
179 */
180
a4fc5ed6 181static int
c898261c 182intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 183{
cd9dde44 184 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 185}
186
fe27d53e
DA		 187static int
188intel_dp_max_data_rate(int max_link_clock, int max_lanes)
189{
190 return (max_link_clock * max_lanes * 8) / 10;
191}
192
70ec0645
MK		 193static int
194intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
195{
196 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
197 struct intel_encoder *encoder = &intel_dig_port->base;
198 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
199 int max_dotclk = dev_priv->max_dotclk_freq;
200 int ds_max_dotclk;
201
202 int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
203
204 if (type != DP_DS_PORT_TYPE_VGA)
205 return max_dotclk;
206
207 ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
208 intel_dp->downstream_ports);
209
210 if (ds_max_dotclk != 0)
211 max_dotclk = min(max_dotclk, ds_max_dotclk);
212
213 return max_dotclk;
214}
215
c19de8eb 216static enum drm_mode_status
a4fc5ed6
KP		 217intel_dp_mode_valid(struct drm_connector *connector,
218 struct drm_display_mode *mode)
219{
df0e9248 220 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 221 struct intel_connector *intel_connector = to_intel_connector(connector);
222 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 223 int target_clock = mode->clock;
224 int max_rate, mode_rate, max_lanes, max_link_clock;
70ec0645
MK		 225 int max_dotclk;
226
227 max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
a4fc5ed6 228
dd06f90e
JN		 229 if (is_edp(intel_dp) && fixed_mode) {
230 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 231 return MODE_PANEL;
232
dd06f90e 233 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 234 return MODE_PANEL;
03afc4a2
DV		 235
236 target_clock = fixed_mode->clock;
7de56f43
ZY		 237 }
238
50fec21a 239 max_link_clock = intel_dp_max_link_rate(intel_dp);
eeb6324d 240 max_lanes = intel_dp_max_lane_count(intel_dp);
36008365
DV		 241
242 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
243 mode_rate = intel_dp_link_required(target_clock, 18);
244
799487f5 245 if (mode_rate > max_rate || target_clock > max_dotclk)
c4867936 246 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 247
248 if (mode->clock < 10000)
249 return MODE_CLOCK_LOW;
250
0af78a2b
DV		 251 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
252 return MODE_H_ILLEGAL;
253
a4fc5ed6
KP		 254 return MODE_OK;
255}
256
a4f1289e 257uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
a4fc5ed6
KP		 258{
259 int i;
260 uint32_t v = 0;
261
262 if (src_bytes > 4)
263 src_bytes = 4;
264 for (i = 0; i < src_bytes; i++)
265 v |= ((uint32_t) src[i]) << ((3-i) * 8);
266 return v;
267}
268
c2af70e2 269static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
a4fc5ed6
KP		 270{
271 int i;
272 if (dst_bytes > 4)
273 dst_bytes = 4;
274 for (i = 0; i < dst_bytes; i++)
275 dst[i] = src >> ((3-i) * 8);
276}
277
bf13e81b
JN		 278static void
279intel_dp_init_panel_power_sequencer(struct drm_device *dev,
36b5f425 280 struct intel_dp *intel_dp);
bf13e81b
JN		 281static void
282intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 283 struct intel_dp *intel_dp);
335f752b
ID		 284static void
285intel_dp_pps_init(struct drm_device *dev, struct intel_dp *intel_dp);
bf13e81b 286
773538e8
VS		 287static void pps_lock(struct intel_dp *intel_dp)
288{
289 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
290 struct intel_encoder *encoder = &intel_dig_port->base;
291 struct drm_device *dev = encoder->base.dev;
fac5e23e 292 struct drm_i915_private *dev_priv = to_i915(dev);
773538e8
VS		 293 enum intel_display_power_domain power_domain;
294
295 /*
296 * See vlv_power_sequencer_reset() why we need
297 * a power domain reference here.
298 */
25f78f58 299 power_domain = intel_display_port_aux_power_domain(encoder);
773538e8
VS		 300 intel_display_power_get(dev_priv, power_domain);
301
302 mutex_lock(&dev_priv->pps_mutex);
303}
304
305static void pps_unlock(struct intel_dp *intel_dp)
306{
307 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
308 struct intel_encoder *encoder = &intel_dig_port->base;
309 struct drm_device *dev = encoder->base.dev;
fac5e23e 310 struct drm_i915_private *dev_priv = to_i915(dev);
773538e8
VS		 311 enum intel_display_power_domain power_domain;
312
313 mutex_unlock(&dev_priv->pps_mutex);
314
25f78f58 315 power_domain = intel_display_port_aux_power_domain(encoder);
773538e8
VS		 316 intel_display_power_put(dev_priv, power_domain);
317}
318
961a0db0
VS		 319static void
320vlv_power_sequencer_kick(struct intel_dp *intel_dp)
321{
322 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
323 struct drm_device *dev = intel_dig_port->base.base.dev;
fac5e23e 324 struct drm_i915_private *dev_priv = to_i915(dev);
961a0db0 325 enum pipe pipe = intel_dp->pps_pipe;
0047eedc
VS		 326 bool pll_enabled, release_cl_override = false;
327 enum dpio_phy phy = DPIO_PHY(pipe);
328 enum dpio_channel ch = vlv_pipe_to_channel(pipe);
961a0db0
VS		 329 uint32_t DP;
330
331 if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
332 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
333 pipe_name(pipe), port_name(intel_dig_port->port)))
334 return;
335
336 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
337 pipe_name(pipe), port_name(intel_dig_port->port));
338
339 /* Preserve the BIOS-computed detected bit. This is
340 * supposed to be read-only.
341 */
342 DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
343 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
344 DP |= DP_PORT_WIDTH(1);
345 DP |= DP_LINK_TRAIN_PAT_1;
346
920a14b2 347 if (IS_CHERRYVIEW(dev_priv))
961a0db0
VS		 348 DP |= DP_PIPE_SELECT_CHV(pipe);
349 else if (pipe == PIPE_B)
350 DP |= DP_PIPEB_SELECT;
351
d288f65f
VS		 352 pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
353
354 /*
355 * The DPLL for the pipe must be enabled for this to work.
356 * So enable temporarily it if it's not already enabled.
357 */
0047eedc 358 if (!pll_enabled) {
920a14b2 359 release_cl_override = IS_CHERRYVIEW(dev_priv) &&
0047eedc
VS		 360 !chv_phy_powergate_ch(dev_priv, phy, ch, true);
361
920a14b2 362 if (vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev_priv) ?
3f36b937
TU		 363 &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
364 DRM_ERROR("Failed to force on pll for pipe %c!\n",
365 pipe_name(pipe));
366 return;
367 }
0047eedc 368 }
d288f65f 369
961a0db0
VS		 370 /*
371 * Similar magic as in intel_dp_enable_port().
372 * We _must_ do this port enable + disable trick
373 * to make this power seqeuencer lock onto the port.
374 * Otherwise even VDD force bit won't work.
375 */
376 I915_WRITE(intel_dp->output_reg, DP);
377 POSTING_READ(intel_dp->output_reg);
378
379 I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
380 POSTING_READ(intel_dp->output_reg);
381
382 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
383 POSTING_READ(intel_dp->output_reg);
d288f65f 384
0047eedc 385 if (!pll_enabled) {
d288f65f 386 vlv_force_pll_off(dev, pipe);
0047eedc
VS		 387
388 if (release_cl_override)
389 chv_phy_powergate_ch(dev_priv, phy, ch, false);
390 }
961a0db0
VS		 391}
392
bf13e81b
JN		 393static enum pipe
394vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
395{
396 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bf13e81b 397 struct drm_device *dev = intel_dig_port->base.base.dev;
fac5e23e 398 struct drm_i915_private *dev_priv = to_i915(dev);
a4a5d2f8
VS		 399 struct intel_encoder *encoder;
400 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
a8c3344e 401 enum pipe pipe;
bf13e81b 402
e39b999a 403 lockdep_assert_held(&dev_priv->pps_mutex);
bf13e81b 404
a8c3344e
VS		 405 /* We should never land here with regular DP ports */
406 WARN_ON(!is_edp(intel_dp));
407
a4a5d2f8
VS		 408 if (intel_dp->pps_pipe != INVALID_PIPE)
409 return intel_dp->pps_pipe;
410
411 /*
412 * We don't have power sequencer currently.
413 * Pick one that's not used by other ports.
414 */
19c8054c 415 for_each_intel_encoder(dev, encoder) {
a4a5d2f8
VS		 416 struct intel_dp *tmp;
417
418 if (encoder->type != INTEL_OUTPUT_EDP)
419 continue;
420
421 tmp = enc_to_intel_dp(&encoder->base);
422
423 if (tmp->pps_pipe != INVALID_PIPE)
424 pipes &= ~(1 << tmp->pps_pipe);
425 }
426
427 /*
428 * Didn't find one. This should not happen since there
429 * are two power sequencers and up to two eDP ports.
430 */
431 if (WARN_ON(pipes == 0))
a8c3344e
VS		 432 pipe = PIPE_A;
433 else
434 pipe = ffs(pipes) - 1;
a4a5d2f8 435
a8c3344e
VS		 436 vlv_steal_power_sequencer(dev, pipe);
437 intel_dp->pps_pipe = pipe;
a4a5d2f8
VS		 438
439 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
440 pipe_name(intel_dp->pps_pipe),
441 port_name(intel_dig_port->port));
442
443 /* init power sequencer on this pipe and port */
36b5f425
VS		 444 intel_dp_init_panel_power_sequencer(dev, intel_dp);
445 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8 446
961a0db0
VS		 447 /*
448 * Even vdd force doesn't work until we've made
449 * the power sequencer lock in on the port.
450 */
451 vlv_power_sequencer_kick(intel_dp);
a4a5d2f8
VS		 452
453 return intel_dp->pps_pipe;
454}
455
78597996
ID		 456static int
457bxt_power_sequencer_idx(struct intel_dp *intel_dp)
458{
459 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
460 struct drm_device *dev = intel_dig_port->base.base.dev;
fac5e23e 461 struct drm_i915_private *dev_priv = to_i915(dev);
78597996
ID		 462
463 lockdep_assert_held(&dev_priv->pps_mutex);
464
465 /* We should never land here with regular DP ports */
466 WARN_ON(!is_edp(intel_dp));
467
468 /*
469 * TODO: BXT has 2 PPS instances. The correct port->PPS instance
470 * mapping needs to be retrieved from VBT, for now just hard-code to
471 * use instance #0 always.
472 */
473 if (!intel_dp->pps_reset)
474 return 0;
475
476 intel_dp->pps_reset = false;
477
478 /*
479 * Only the HW needs to be reprogrammed, the SW state is fixed and
480 * has been setup during connector init.
481 */
482 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
483
484 return 0;
485}
486
6491ab27
VS		 487typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
488 enum pipe pipe);
489
490static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
491 enum pipe pipe)
492{
44cb734c 493 return I915_READ(PP_STATUS(pipe)) & PP_ON;
6491ab27
VS		 494}
495
496static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
497 enum pipe pipe)
498{
44cb734c 499 return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD;
6491ab27
VS		 500}
501
502static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
503 enum pipe pipe)
504{
505 return true;
506}
bf13e81b 507
a4a5d2f8 508static enum pipe
6491ab27
VS		 509vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
510 enum port port,
511 vlv_pipe_check pipe_check)
a4a5d2f8
VS		 512{
513 enum pipe pipe;
bf13e81b 514
bf13e81b 515 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
44cb734c 516 u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) &
bf13e81b 517 PANEL_PORT_SELECT_MASK;
a4a5d2f8
VS		 518
519 if (port_sel != PANEL_PORT_SELECT_VLV(port))
520 continue;
521
6491ab27
VS		 522 if (!pipe_check(dev_priv, pipe))
523 continue;
524
a4a5d2f8 525 return pipe;
bf13e81b
JN		 526 }
527
a4a5d2f8
VS		 528 return INVALID_PIPE;
529}
530
531static void
532vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
533{
534 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
535 struct drm_device *dev = intel_dig_port->base.base.dev;
fac5e23e 536 struct drm_i915_private *dev_priv = to_i915(dev);
a4a5d2f8
VS		 537 enum port port = intel_dig_port->port;
538
539 lockdep_assert_held(&dev_priv->pps_mutex);
540
541 /* try to find a pipe with this port selected */
6491ab27
VS		 542 /* first pick one where the panel is on */
543 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
544 vlv_pipe_has_pp_on);
545 /* didn't find one? pick one where vdd is on */
546 if (intel_dp->pps_pipe == INVALID_PIPE)
547 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
548 vlv_pipe_has_vdd_on);
549 /* didn't find one? pick one with just the correct port */
550 if (intel_dp->pps_pipe == INVALID_PIPE)
551 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
552 vlv_pipe_any);
a4a5d2f8
VS		 553
554 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
555 if (intel_dp->pps_pipe == INVALID_PIPE) {
556 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
557 port_name(port));
558 return;
bf13e81b
JN		 559 }
560
a4a5d2f8
VS		 561 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
562 port_name(port), pipe_name(intel_dp->pps_pipe));
563
36b5f425
VS		 564 intel_dp_init_panel_power_sequencer(dev, intel_dp);
565 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
bf13e81b
JN		 566}
567
78597996 568void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
773538e8 569{
91c8a326 570 struct drm_device *dev = &dev_priv->drm;
773538e8
VS		 571 struct intel_encoder *encoder;
572
920a14b2 573 if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
e2d214ae 574 !IS_BROXTON(dev_priv)))
773538e8
VS		 575 return;
576
577 /*
578 * We can't grab pps_mutex here due to deadlock with power_domain
579 * mutex when power_domain functions are called while holding pps_mutex.
580 * That also means that in order to use pps_pipe the code needs to
581 * hold both a power domain reference and pps_mutex, and the power domain
582 * reference get/put must be done while _not_ holding pps_mutex.
583 * pps_{lock,unlock}() do these steps in the correct order, so one
584 * should use them always.
585 */
586
19c8054c 587 for_each_intel_encoder(dev, encoder) {
773538e8
VS		 588 struct intel_dp *intel_dp;
589
590 if (encoder->type != INTEL_OUTPUT_EDP)
591 continue;
592
593 intel_dp = enc_to_intel_dp(&encoder->base);
e2d214ae 594 if (IS_BROXTON(dev_priv))
78597996
ID		 595 intel_dp->pps_reset = true;
596 else
597 intel_dp->pps_pipe = INVALID_PIPE;
773538e8 598 }
bf13e81b
JN		 599}
600
8e8232d5
ID		 601struct pps_registers {
602 i915_reg_t pp_ctrl;
603 i915_reg_t pp_stat;
604 i915_reg_t pp_on;
605 i915_reg_t pp_off;
606 i915_reg_t pp_div;
607};
608
609static void intel_pps_get_registers(struct drm_i915_private *dev_priv,
610 struct intel_dp *intel_dp,
611 struct pps_registers *regs)
612{
44cb734c
ID		 613 int pps_idx = 0;
614
8e8232d5
ID		 615 memset(regs, 0, sizeof(*regs));
616
44cb734c
ID		 617 if (IS_BROXTON(dev_priv))
618 pps_idx = bxt_power_sequencer_idx(intel_dp);
619 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
620 pps_idx = vlv_power_sequencer_pipe(intel_dp);
8e8232d5 621
44cb734c
ID		 622 regs->pp_ctrl = PP_CONTROL(pps_idx);
623 regs->pp_stat = PP_STATUS(pps_idx);
624 regs->pp_on = PP_ON_DELAYS(pps_idx);
625 regs->pp_off = PP_OFF_DELAYS(pps_idx);
626 if (!IS_BROXTON(dev_priv))
627 regs->pp_div = PP_DIVISOR(pps_idx);
8e8232d5
ID		 628}
629
f0f59a00
VS		 630static i915_reg_t
631_pp_ctrl_reg(struct intel_dp *intel_dp)
bf13e81b 632{
8e8232d5 633 struct pps_registers regs;
bf13e81b 634
8e8232d5
ID		 635 intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp,
636 &regs);
637
638 return regs.pp_ctrl;
bf13e81b
JN		 639}
640
f0f59a00
VS		 641static i915_reg_t
642_pp_stat_reg(struct intel_dp *intel_dp)
bf13e81b 643{
8e8232d5 644 struct pps_registers regs;
bf13e81b 645
8e8232d5
ID		 646 intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp,
647 &regs);
648
649 return regs.pp_stat;
bf13e81b
JN		 650}
651
01527b31
CT		 652/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
653 This function only applicable when panel PM state is not to be tracked */
654static int edp_notify_handler(struct notifier_block *this, unsigned long code,
655 void *unused)
656{
657 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
658 edp_notifier);
659 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 660 struct drm_i915_private *dev_priv = to_i915(dev);
01527b31
CT		 661
662 if (!is_edp(intel_dp) || code != SYS_RESTART)
663 return 0;
664
773538e8 665 pps_lock(intel_dp);
e39b999a 666
920a14b2 667 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
e39b999a 668 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
f0f59a00 669 i915_reg_t pp_ctrl_reg, pp_div_reg;
649636ef 670 u32 pp_div;
e39b999a 671
44cb734c
ID		 672 pp_ctrl_reg = PP_CONTROL(pipe);
673 pp_div_reg = PP_DIVISOR(pipe);
01527b31
CT		 674 pp_div = I915_READ(pp_div_reg);
675 pp_div &= PP_REFERENCE_DIVIDER_MASK;
676
677 /* 0x1F write to PP_DIV_REG sets max cycle delay */
678 I915_WRITE(pp_div_reg, pp_div | 0x1F);
679 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
680 msleep(intel_dp->panel_power_cycle_delay);
681 }
682
773538e8 683 pps_unlock(intel_dp);
e39b999a 684
01527b31
CT		 685 return 0;
686}
687
4be73780 688static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 689{
30add22d 690 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 691 struct drm_i915_private *dev_priv = to_i915(dev);
ebf33b18 692
e39b999a
VS		 693 lockdep_assert_held(&dev_priv->pps_mutex);
694
920a14b2 695 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
9a42356b
VS		 696 intel_dp->pps_pipe == INVALID_PIPE)
697 return false;
698
bf13e81b 699 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 700}
701
4be73780 702static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 703{
30add22d 704 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 705 struct drm_i915_private *dev_priv = to_i915(dev);
ebf33b18 706
e39b999a
VS		 707 lockdep_assert_held(&dev_priv->pps_mutex);
708
920a14b2 709 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
9a42356b
VS		 710 intel_dp->pps_pipe == INVALID_PIPE)
711 return false;
712
773538e8 713 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
ebf33b18
KP		 714}
715
9b984dae
KP		 716static void
717intel_dp_check_edp(struct intel_dp *intel_dp)
718{
30add22d 719 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 720 struct drm_i915_private *dev_priv = to_i915(dev);
ebf33b18 721
9b984dae
KP		 722 if (!is_edp(intel_dp))
723 return;
453c5420 724
4be73780 725 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 726 WARN(1, "eDP powered off while attempting aux channel communication.\n");
727 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 728 I915_READ(_pp_stat_reg(intel_dp)),
729 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 730 }
731}
732
9ee32fea
DV		 733static uint32_t
734intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
735{
736 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
737 struct drm_device *dev = intel_dig_port->base.base.dev;
fac5e23e 738 struct drm_i915_private *dev_priv = to_i915(dev);
f0f59a00 739 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 740 uint32_t status;
741 bool done;
742
ef04f00d 743#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 744 if (has_aux_irq)
b18ac466 745 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 746 msecs_to_jiffies_timeout(10));
9ee32fea 747 else
713a6b66 748 done = wait_for(C, 10) == 0;
9ee32fea
DV		 749 if (!done)
750 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
751 has_aux_irq);
752#undef C
753
754 return status;
755}
756
6ffb1be7 757static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 758{
174edf1f 759 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
e7dc33f3 760 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
9ee32fea 761
a457f54b
VS		 762 if (index)
763 return 0;
764
ec5b01dd
DL		 765 /*
766 * The clock divider is based off the hrawclk, and would like to run at
a457f54b 767 * 2MHz. So, take the hrawclk value and divide by 2000 and use that
a4fc5ed6 768 */
a457f54b 769 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
ec5b01dd
DL		 770}
771
772static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
773{
774 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
a457f54b 775 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
ec5b01dd
DL		 776
777 if (index)
778 return 0;
779
a457f54b
VS		 780 /*
781 * The clock divider is based off the cdclk or PCH rawclk, and would
782 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and
783 * divide by 2000 and use that
784 */
e7dc33f3 785 if (intel_dig_port->port == PORT_A)
fce18c4c 786 return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000);
e7dc33f3
VS		 787 else
788 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
ec5b01dd
DL		 789}
790
791static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
792{
793 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
a457f54b 794 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
ec5b01dd 795
a457f54b 796 if (intel_dig_port->port != PORT_A && HAS_PCH_LPT_H(dev_priv)) {
2c55c336 797 /* Workaround for non-ULT HSW */
bc86625a
CW		 798 switch (index) {
799 case 0: return 63;
800 case 1: return 72;
801 default: return 0;
802 }
2c55c336 803 }
a457f54b
VS		 804
805 return ilk_get_aux_clock_divider(intel_dp, index);
b84a1cf8
RV		 806}
807
b6b5e383
DL		 808static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
809{
810 /*
811 * SKL doesn't need us to program the AUX clock divider (Hardware will
812 * derive the clock from CDCLK automatically). We still implement the
813 * get_aux_clock_divider vfunc to plug-in into the existing code.
814 */
815 return index ? 0 : 1;
816}
817
6ffb1be7
VS		 818static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
819 bool has_aux_irq,
820 int send_bytes,
821 uint32_t aux_clock_divider)
5ed12a19
DL		 822{
823 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
8652744b
TU		 824 struct drm_i915_private *dev_priv =
825 to_i915(intel_dig_port->base.base.dev);
5ed12a19
DL		 826 uint32_t precharge, timeout;
827
8652744b 828 if (IS_GEN6(dev_priv))
5ed12a19
DL		 829 precharge = 3;
830 else
831 precharge = 5;
832
8652744b 833 if (IS_BROADWELL(dev_priv) && intel_dig_port->port == PORT_A)
5ed12a19
DL		 834 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
835 else
836 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
837
838 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 839 DP_AUX_CH_CTL_DONE |
5ed12a19 840 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 841 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 842 timeout |
788d4433 843 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 844 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
845 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 846 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 847}
848
b9ca5fad
DL		 849static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
850 bool has_aux_irq,
851 int send_bytes,
852 uint32_t unused)
853{
854 return DP_AUX_CH_CTL_SEND_BUSY |
855 DP_AUX_CH_CTL_DONE |
856 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
857 DP_AUX_CH_CTL_TIME_OUT_ERROR |
858 DP_AUX_CH_CTL_TIME_OUT_1600us |
859 DP_AUX_CH_CTL_RECEIVE_ERROR |
860 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
d4dcbdce 861 DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
b9ca5fad
DL		 862 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
863}
864
b84a1cf8
RV		 865static int
866intel_dp_aux_ch(struct intel_dp *intel_dp,
bd9f74a5 867 const uint8_t *send, int send_bytes,
b84a1cf8
RV		 868 uint8_t *recv, int recv_size)
869{
870 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
871 struct drm_device *dev = intel_dig_port->base.base.dev;
fac5e23e 872 struct drm_i915_private *dev_priv = to_i915(dev);
f0f59a00 873 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
bc86625a 874 uint32_t aux_clock_divider;
b84a1cf8
RV		 875 int i, ret, recv_bytes;
876 uint32_t status;
5ed12a19 877 int try, clock = 0;
4e6b788c 878 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 879 bool vdd;
880
773538e8 881 pps_lock(intel_dp);
e39b999a 882
72c3500a
VS		 883 /*
884 * We will be called with VDD already enabled for dpcd/edid/oui reads.
885 * In such cases we want to leave VDD enabled and it's up to upper layers
886 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
887 * ourselves.
888 */
1e0560e0 889 vdd = edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 890
891 /* dp aux is extremely sensitive to irq latency, hence request the
892 * lowest possible wakeup latency and so prevent the cpu from going into
893 * deep sleep states.
894 */
895 pm_qos_update_request(&dev_priv->pm_qos, 0);
896
897 intel_dp_check_edp(intel_dp);
5eb08b69 898
11bee43e
JB		 899 /* Try to wait for any previous AUX channel activity */
900 for (try = 0; try < 3; try++) {
ef04f00d 901 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 902 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
903 break;
904 msleep(1);
905 }
906
907 if (try == 3) {
02196c77
MK		 908 static u32 last_status = -1;
909 const u32 status = I915_READ(ch_ctl);
910
911 if (status != last_status) {
912 WARN(1, "dp_aux_ch not started status 0x%08x\n",
913 status);
914 last_status = status;
915 }
916
9ee32fea
DV		 917 ret = -EBUSY;
918 goto out;
4f7f7b7e
CW		 919 }
920
46a5ae9f
PZ		 921 /* Only 5 data registers! */
922 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
923 ret = -E2BIG;
924 goto out;
925 }
926
ec5b01dd 927 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 928 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
929 has_aux_irq,
930 send_bytes,
931 aux_clock_divider);
5ed12a19 932
bc86625a
CW		 933 /* Must try at least 3 times according to DP spec */
934 for (try = 0; try < 5; try++) {
935 /* Load the send data into the aux channel data registers */
936 for (i = 0; i < send_bytes; i += 4)
330e20ec 937 I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2],
a4f1289e
RV		 938 intel_dp_pack_aux(send + i,
939 send_bytes - i));
bc86625a
CW		 940
941 /* Send the command and wait for it to complete */
5ed12a19 942 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 943
944 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
945
946 /* Clear done status and any errors */
947 I915_WRITE(ch_ctl,
948 status |
949 DP_AUX_CH_CTL_DONE |
950 DP_AUX_CH_CTL_TIME_OUT_ERROR |
951 DP_AUX_CH_CTL_RECEIVE_ERROR);
952
74ebf294 953 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
bc86625a 954 continue;
74ebf294
TP		 955
956 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
957 * 400us delay required for errors and timeouts
958 * Timeout errors from the HW already meet this
959 * requirement so skip to next iteration
960 */
961 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
962 usleep_range(400, 500);
bc86625a 963 continue;
74ebf294 964 }
bc86625a 965 if (status & DP_AUX_CH_CTL_DONE)
e058c945 966 goto done;
bc86625a 967 }
a4fc5ed6
KP		 968 }
969
a4fc5ed6 970 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 971 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 972 ret = -EBUSY;
973 goto out;
a4fc5ed6
KP		 974 }
975
e058c945 976done:
a4fc5ed6
KP		 977 /* Check for timeout or receive error.
978 * Timeouts occur when the sink is not connected
979 */
a5b3da54 980 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 981 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 982 ret = -EIO;
983 goto out;
a5b3da54 984 }
1ae8c0a5
KP		 985
986 /* Timeouts occur when the device isn't connected, so they're
987 * "normal" -- don't fill the kernel log with these */
a5b3da54 988 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 989 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 990 ret = -ETIMEDOUT;
991 goto out;
a4fc5ed6
KP		 992 }
993
994 /* Unload any bytes sent back from the other side */
995 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
996 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
14e01889
RV		 997
998 /*
999 * By BSpec: "Message sizes of 0 or >20 are not allowed."
1000 * We have no idea of what happened so we return -EBUSY so
1001 * drm layer takes care for the necessary retries.
1002 */
1003 if (recv_bytes == 0 || recv_bytes > 20) {
1004 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
1005 recv_bytes);
1006 /*
1007 * FIXME: This patch was created on top of a series that
1008 * organize the retries at drm level. There EBUSY should
1009 * also take care for 1ms wait before retrying.
1010 * That aux retries re-org is still needed and after that is
1011 * merged we remove this sleep from here.
1012 */
1013 usleep_range(1000, 1500);
1014 ret = -EBUSY;
1015 goto out;
1016 }
1017
a4fc5ed6
KP		 1018 if (recv_bytes > recv_size)
1019 recv_bytes = recv_size;
0206e353 1020
4f7f7b7e 1021 for (i = 0; i < recv_bytes; i += 4)
330e20ec 1022 intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]),
a4f1289e 1023 recv + i, recv_bytes - i);
a4fc5ed6 1024
9ee32fea
DV		 1025 ret = recv_bytes;
1026out:
1027 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
1028
884f19e9
JN		 1029 if (vdd)
1030 edp_panel_vdd_off(intel_dp, false);
1031
773538e8 1032 pps_unlock(intel_dp);
e39b999a 1033
9ee32fea 1034 return ret;
a4fc5ed6
KP		 1035}
1036
a6c8aff0
JN		 1037#define BARE_ADDRESS_SIZE 3
1038#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 1039static ssize_t
1040intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 1041{
9d1a1031
JN		 1042 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1043 uint8_t txbuf[20], rxbuf[20];
1044 size_t txsize, rxsize;
a4fc5ed6 1045 int ret;
a4fc5ed6 1046
d2d9cbbd
VS		 1047 txbuf[0] = (msg->request << 4) |
1048 ((msg->address >> 16) & 0xf);
1049 txbuf[1] = (msg->address >> 8) & 0xff;
9d1a1031
JN		 1050 txbuf[2] = msg->address & 0xff;
1051 txbuf[3] = msg->size - 1;
46a5ae9f 1052
9d1a1031
JN		 1053 switch (msg->request & ~DP_AUX_I2C_MOT) {
1054 case DP_AUX_NATIVE_WRITE:
1055 case DP_AUX_I2C_WRITE:
c1e74122 1056 case DP_AUX_I2C_WRITE_STATUS_UPDATE:
a6c8aff0 1057 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
a1ddefd8 1058 rxsize = 2; /* 0 or 1 data bytes */
f51a44b9 1059
9d1a1031
JN		 1060 if (WARN_ON(txsize > 20))
1061 return -E2BIG;
a4fc5ed6 1062
dd788090
VS		 1063 WARN_ON(!msg->buffer != !msg->size);
1064
d81a67cc
ID		 1065 if (msg->buffer)
1066 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 1067
9d1a1031
JN		 1068 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1069 if (ret > 0) {
1070 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 1071
a1ddefd8
JN		 1072 if (ret > 1) {
1073 /* Number of bytes written in a short write. */
1074 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1075 } else {
1076 /* Return payload size. */
1077 ret = msg->size;
1078 }
9d1a1031
JN		 1079 }
1080 break;
46a5ae9f 1081
9d1a1031
JN		 1082 case DP_AUX_NATIVE_READ:
1083 case DP_AUX_I2C_READ:
a6c8aff0 1084 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 1085 rxsize = msg->size + 1;
a4fc5ed6 1086
9d1a1031
JN		 1087 if (WARN_ON(rxsize > 20))
1088 return -E2BIG;
a4fc5ed6 1089
9d1a1031
JN		 1090 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1091 if (ret > 0) {
1092 msg->reply = rxbuf[0] >> 4;
1093 /*
1094 * Assume happy day, and copy the data. The caller is
1095 * expected to check msg->reply before touching it.
1096 *
1097 * Return payload size.
1098 */
1099 ret--;
1100 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 1101 }
9d1a1031
JN		 1102 break;
1103
1104 default:
1105 ret = -EINVAL;
1106 break;
a4fc5ed6 1107 }
f51a44b9 1108
9d1a1031 1109 return ret;
a4fc5ed6
KP		 1110}
1111
8f7ce038
VS		 1112static enum port intel_aux_port(struct drm_i915_private *dev_priv,
1113 enum port port)
1114{
1115 const struct ddi_vbt_port_info *info =
1116 &dev_priv->vbt.ddi_port_info[port];
1117 enum port aux_port;
1118
1119 if (!info->alternate_aux_channel) {
1120 DRM_DEBUG_KMS("using AUX %c for port %c (platform default)\n",
1121 port_name(port), port_name(port));
1122 return port;
1123 }
1124
1125 switch (info->alternate_aux_channel) {
1126 case DP_AUX_A:
1127 aux_port = PORT_A;
1128 break;
1129 case DP_AUX_B:
1130 aux_port = PORT_B;
1131 break;
1132 case DP_AUX_C:
1133 aux_port = PORT_C;
1134 break;
1135 case DP_AUX_D:
1136 aux_port = PORT_D;
1137 break;
1138 default:
1139 MISSING_CASE(info->alternate_aux_channel);
1140 aux_port = PORT_A;
1141 break;
1142 }
1143
1144 DRM_DEBUG_KMS("using AUX %c for port %c (VBT)\n",
1145 port_name(aux_port), port_name(port));
1146
1147 return aux_port;
1148}
1149
f0f59a00 1150static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
c8a89b08 1151 enum port port)
da00bdcf
VS		 1152{
1153 switch (port) {
1154 case PORT_B:
1155 case PORT_C:
1156 case PORT_D:
1157 return DP_AUX_CH_CTL(port);
1158 default:
1159 MISSING_CASE(port);
1160 return DP_AUX_CH_CTL(PORT_B);
1161 }
1162}
1163
f0f59a00 1164static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv,
c8a89b08 1165 enum port port, int index)
330e20ec
VS		 1166{
1167 switch (port) {
1168 case PORT_B:
1169 case PORT_C:
1170 case PORT_D:
1171 return DP_AUX_CH_DATA(port, index);
1172 default:
1173 MISSING_CASE(port);
1174 return DP_AUX_CH_DATA(PORT_B, index);
1175 }
1176}
1177
f0f59a00 1178static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv,
c8a89b08 1179 enum port port)
da00bdcf
VS		 1180{
1181 switch (port) {
1182 case PORT_A:
1183 return DP_AUX_CH_CTL(port);
1184 case PORT_B:
1185 case PORT_C:
1186 case PORT_D:
1187 return PCH_DP_AUX_CH_CTL(port);
1188 default:
1189 MISSING_CASE(port);
1190 return DP_AUX_CH_CTL(PORT_A);
1191 }
1192}
1193
f0f59a00 1194static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv,
c8a89b08 1195 enum port port, int index)
330e20ec
VS		 1196{
1197 switch (port) {
1198 case PORT_A:
1199 return DP_AUX_CH_DATA(port, index);
1200 case PORT_B:
1201 case PORT_C:
1202 case PORT_D:
1203 return PCH_DP_AUX_CH_DATA(port, index);
1204 default:
1205 MISSING_CASE(port);
1206 return DP_AUX_CH_DATA(PORT_A, index);
1207 }
1208}
1209
f0f59a00 1210static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
c8a89b08 1211 enum port port)
da00bdcf 1212{
da00bdcf
VS		 1213 switch (port) {
1214 case PORT_A:
1215 case PORT_B:
1216 case PORT_C:
1217 case PORT_D:
1218 return DP_AUX_CH_CTL(port);
1219 default:
1220 MISSING_CASE(port);
1221 return DP_AUX_CH_CTL(PORT_A);
1222 }
1223}
1224
f0f59a00 1225static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv,
c8a89b08 1226 enum port port, int index)
330e20ec 1227{
330e20ec
VS		 1228 switch (port) {
1229 case PORT_A:
1230 case PORT_B:
1231 case PORT_C:
1232 case PORT_D:
1233 return DP_AUX_CH_DATA(port, index);
1234 default:
1235 MISSING_CASE(port);
1236 return DP_AUX_CH_DATA(PORT_A, index);
1237 }
1238}
1239
f0f59a00 1240static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv,
c8a89b08 1241 enum port port)
330e20ec
VS		 1242{
1243 if (INTEL_INFO(dev_priv)->gen >= 9)
1244 return skl_aux_ctl_reg(dev_priv, port);
1245 else if (HAS_PCH_SPLIT(dev_priv))
1246 return ilk_aux_ctl_reg(dev_priv, port);
1247 else
1248 return g4x_aux_ctl_reg(dev_priv, port);
1249}
1250
f0f59a00 1251static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv,
c8a89b08 1252 enum port port, int index)
330e20ec
VS		 1253{
1254 if (INTEL_INFO(dev_priv)->gen >= 9)
1255 return skl_aux_data_reg(dev_priv, port, index);
1256 else if (HAS_PCH_SPLIT(dev_priv))
1257 return ilk_aux_data_reg(dev_priv, port, index);
1258 else
1259 return g4x_aux_data_reg(dev_priv, port, index);
1260}
1261
1262static void intel_aux_reg_init(struct intel_dp *intel_dp)
1263{
1264 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
8f7ce038
VS		 1265 enum port port = intel_aux_port(dev_priv,
1266 dp_to_dig_port(intel_dp)->port);
330e20ec
VS		 1267 int i;
1268
1269 intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port);
1270 for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++)
1271 intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i);
1272}
1273
9d1a1031 1274static void
a121f4e5
VS		 1275intel_dp_aux_fini(struct intel_dp *intel_dp)
1276{
a121f4e5
VS		 1277 kfree(intel_dp->aux.name);
1278}
1279
7a418e34 1280static void
b6339585 1281intel_dp_aux_init(struct intel_dp *intel_dp)
9d1a1031 1282{
33ad6626
JN		 1283 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1284 enum port port = intel_dig_port->port;
ab2c0672 1285
330e20ec 1286 intel_aux_reg_init(intel_dp);
7a418e34 1287 drm_dp_aux_init(&intel_dp->aux);
8316f337 1288
7a418e34 1289 /* Failure to allocate our preferred name is not critical */
a121f4e5 1290 intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port));
9d1a1031 1291 intel_dp->aux.transfer = intel_dp_aux_transfer;
a4fc5ed6
KP		 1292}
1293
fc0f8e25 1294static int
12f6a2e2 1295intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
fc0f8e25 1296{
94ca719e
VS		 1297 if (intel_dp->num_sink_rates) {
1298 *sink_rates = intel_dp->sink_rates;
1299 return intel_dp->num_sink_rates;
fc0f8e25 1300 }
12f6a2e2
VS		 1301
1302 *sink_rates = default_rates;
1303
1304 return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
fc0f8e25
SJ		 1305}
1306
e588fa18 1307bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
ed63baaf 1308{
e588fa18 1309 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
577c5430 1310 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
e588fa18 1311
577c5430
NM		 1312 if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
1313 IS_BROADWELL(dev_priv) || (INTEL_GEN(dev_priv) >= 9))
ed63baaf
TS		 1314 return true;
1315 else
1316 return false;
1317}
1318
a8f3ef61 1319static int
e588fa18 1320intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates)
a8f3ef61 1321{
e588fa18 1322 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
577c5430 1323 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
af7080f5
TS		 1324 int size;
1325
577c5430 1326 if (IS_BROXTON(dev_priv)) {
64987fc5 1327 *source_rates = bxt_rates;
af7080f5 1328 size = ARRAY_SIZE(bxt_rates);
577c5430 1329 } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
637a9c63 1330 *source_rates = skl_rates;
af7080f5
TS		 1331 size = ARRAY_SIZE(skl_rates);
1332 } else {
1333 *source_rates = default_rates;
1334 size = ARRAY_SIZE(default_rates);
a8f3ef61 1335 }
636280ba 1336
ed63baaf 1337 /* This depends on the fact that 5.4 is last value in the array */
e588fa18 1338 if (!intel_dp_source_supports_hbr2(intel_dp))
af7080f5 1339 size--;
636280ba 1340
af7080f5 1341 return size;
a8f3ef61
SJ		 1342}
1343
c6bb3538
DV		 1344static void
1345intel_dp_set_clock(struct intel_encoder *encoder,
840b32b7 1346 struct intel_crtc_state *pipe_config)
c6bb3538
DV		 1347{
1348 struct drm_device *dev = encoder->base.dev;
6e266956 1349 struct drm_i915_private *dev_priv = to_i915(dev);
9dd4ffdf
CML		 1350 const struct dp_link_dpll *divisor = NULL;
1351 int i, count = 0;
c6bb3538 1352
9beb5fea 1353 if (IS_G4X(dev_priv)) {
9dd4ffdf
CML		 1354 divisor = gen4_dpll;
1355 count = ARRAY_SIZE(gen4_dpll);
6e266956 1356 } else if (HAS_PCH_SPLIT(dev_priv)) {
9dd4ffdf
CML		 1357 divisor = pch_dpll;
1358 count = ARRAY_SIZE(pch_dpll);
920a14b2 1359 } else if (IS_CHERRYVIEW(dev_priv)) {
ef9348c8
CML		 1360 divisor = chv_dpll;
1361 count = ARRAY_SIZE(chv_dpll);
11a914c2 1362 } else if (IS_VALLEYVIEW(dev_priv)) {
65ce4bf5
CML		 1363 divisor = vlv_dpll;
1364 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 1365 }
9dd4ffdf
CML		 1366
1367 if (divisor && count) {
1368 for (i = 0; i < count; i++) {
840b32b7 1369 if (pipe_config->port_clock == divisor[i].clock) {
9dd4ffdf
CML		 1370 pipe_config->dpll = divisor[i].dpll;
1371 pipe_config->clock_set = true;
1372 break;
1373 }
1374 }
c6bb3538
DV		 1375 }
1376}
1377
2ecae76a
VS		 1378static int intersect_rates(const int *source_rates, int source_len,
1379 const int *sink_rates, int sink_len,
94ca719e 1380 int *common_rates)
a8f3ef61
SJ		 1381{
1382 int i = 0, j = 0, k = 0;
1383
a8f3ef61
SJ		 1384 while (i < source_len && j < sink_len) {
1385 if (source_rates[i] == sink_rates[j]) {
e6bda3e4
VS		 1386 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
1387 return k;
94ca719e 1388 common_rates[k] = source_rates[i];
a8f3ef61
SJ		 1389 ++k;
1390 ++i;
1391 ++j;
1392 } else if (source_rates[i] < sink_rates[j]) {
1393 ++i;
1394 } else {
1395 ++j;
1396 }
1397 }
1398 return k;
1399}
1400
94ca719e
VS		 1401static int intel_dp_common_rates(struct intel_dp *intel_dp,
1402 int *common_rates)
2ecae76a 1403{
2ecae76a
VS		 1404 const int *source_rates, *sink_rates;
1405 int source_len, sink_len;
1406
1407 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
e588fa18 1408 source_len = intel_dp_source_rates(intel_dp, &source_rates);
2ecae76a
VS		 1409
1410 return intersect_rates(source_rates, source_len,
1411 sink_rates, sink_len,
94ca719e 1412 common_rates);
2ecae76a
VS		 1413}
1414
0336400e
VS		 1415static void snprintf_int_array(char *str, size_t len,
1416 const int *array, int nelem)
1417{
1418 int i;
1419
1420 str[0] = '\0';
1421
1422 for (i = 0; i < nelem; i++) {
b2f505be 1423 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
0336400e
VS		 1424 if (r >= len)
1425 return;
1426 str += r;
1427 len -= r;
1428 }
1429}
1430
1431static void intel_dp_print_rates(struct intel_dp *intel_dp)
1432{
0336400e 1433 const int *source_rates, *sink_rates;
94ca719e
VS		 1434 int source_len, sink_len, common_len;
1435 int common_rates[DP_MAX_SUPPORTED_RATES];
0336400e
VS		 1436 char str[128]; /* FIXME: too big for stack? */
1437
1438 if ((drm_debug & DRM_UT_KMS) == 0)
1439 return;
1440
e588fa18 1441 source_len = intel_dp_source_rates(intel_dp, &source_rates);
0336400e
VS		 1442 snprintf_int_array(str, sizeof(str), source_rates, source_len);
1443 DRM_DEBUG_KMS("source rates: %s\n", str);
1444
1445 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1446 snprintf_int_array(str, sizeof(str), sink_rates, sink_len);
1447 DRM_DEBUG_KMS("sink rates: %s\n", str);
1448
94ca719e
VS		 1449 common_len = intel_dp_common_rates(intel_dp, common_rates);
1450 snprintf_int_array(str, sizeof(str), common_rates, common_len);
1451 DRM_DEBUG_KMS("common rates: %s\n", str);
0336400e
VS		 1452}
1453
7b3fc170
ID		 1454static bool
1455__intel_dp_read_desc(struct intel_dp *intel_dp, struct intel_dp_desc *desc)
0e390a33 1456{
7b3fc170
ID		 1457 u32 base = drm_dp_is_branch(intel_dp->dpcd) ? DP_BRANCH_OUI :
1458 DP_SINK_OUI;
0e390a33 1459
7b3fc170
ID		 1460 return drm_dp_dpcd_read(&intel_dp->aux, base, desc, sizeof(*desc)) ==
1461 sizeof(*desc);
0e390a33
MK		 1462}
1463
7b3fc170 1464static bool intel_dp_read_desc(struct intel_dp *intel_dp)
1a2724fa 1465{
7b3fc170
ID		 1466 struct intel_dp_desc *desc = &intel_dp->desc;
1467 bool oui_sup = intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] &
1468 DP_OUI_SUPPORT;
1469 int dev_id_len;
1a2724fa 1470
7b3fc170
ID		 1471 if (!__intel_dp_read_desc(intel_dp, desc))
1472 return false;
1a2724fa 1473
7b3fc170
ID		 1474 dev_id_len = strnlen(desc->device_id, sizeof(desc->device_id));
1475 DRM_DEBUG_KMS("DP %s: OUI %*phD%s dev-ID %*pE HW-rev %d.%d SW-rev %d.%d\n",
1476 drm_dp_is_branch(intel_dp->dpcd) ? "branch" : "sink",
1477 (int)sizeof(desc->oui), desc->oui, oui_sup ? "" : "(NS)",
1478 dev_id_len, desc->device_id,
1479 desc->hw_rev >> 4, desc->hw_rev & 0xf,
1480 desc->sw_major_rev, desc->sw_minor_rev);
1a2724fa 1481
7b3fc170 1482 return true;
1a2724fa
MK		 1483}
1484
f4896f15 1485static int rate_to_index(int find, const int *rates)
a8f3ef61
SJ		 1486{
1487 int i = 0;
1488
1489 for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i)
1490 if (find == rates[i])
1491 break;
1492
1493 return i;
1494}
1495
50fec21a
VS		 1496int
1497intel_dp_max_link_rate(struct intel_dp *intel_dp)
1498{
1499 int rates[DP_MAX_SUPPORTED_RATES] = {};
1500 int len;
1501
94ca719e 1502 len = intel_dp_common_rates(intel_dp, rates);
50fec21a
VS		 1503 if (WARN_ON(len <= 0))
1504 return 162000;
1505
1354f734 1506 return rates[len - 1];
50fec21a
VS		 1507}
1508
ed4e9c1d
VS		 1509int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1510{
94ca719e 1511 return rate_to_index(rate, intel_dp->sink_rates);
ed4e9c1d
VS		 1512}
1513
94223d04
ACO		 1514void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1515 uint8_t *link_bw, uint8_t *rate_select)
04a60f9f
VS		 1516{
1517 if (intel_dp->num_sink_rates) {
1518 *link_bw = 0;
1519 *rate_select =
1520 intel_dp_rate_select(intel_dp, port_clock);
1521 } else {
1522 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1523 *rate_select = 0;
1524 }
1525}
1526
f580bea9
JN		 1527static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
1528 struct intel_crtc_state *pipe_config)
f9bb705e
MK		 1529{
1530 int bpp, bpc;
1531
1532 bpp = pipe_config->pipe_bpp;
1533 bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports);
1534
1535 if (bpc > 0)
1536 bpp = min(bpp, 3*bpc);
1537
1538 return bpp;
1539}
1540
00c09d70 1541bool
5bfe2ac0 1542intel_dp_compute_config(struct intel_encoder *encoder,
0a478c27
ML		 1543 struct intel_crtc_state *pipe_config,
1544 struct drm_connector_state *conn_state)
a4fc5ed6 1545{
5bfe2ac0 1546 struct drm_device *dev = encoder->base.dev;
fac5e23e 1547 struct drm_i915_private *dev_priv = to_i915(dev);
2d112de7 1548 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5bfe2ac0 1549 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1550 enum port port = dp_to_dig_port(intel_dp)->port;
84556d58 1551 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
dd06f90e 1552 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 1553 int lane_count, clock;
56071a20 1554 int min_lane_count = 1;
eeb6324d 1555 int max_lane_count = intel_dp_max_lane_count(intel_dp);
06ea66b6 1556 /* Conveniently, the link BW constants become indices with a shift...*/
56071a20 1557 int min_clock = 0;
a8f3ef61 1558 int max_clock;
083f9560 1559 int bpp, mode_rate;
ff9a6750 1560 int link_avail, link_clock;
94ca719e
VS		 1561 int common_rates[DP_MAX_SUPPORTED_RATES] = {};
1562 int common_len;
04a60f9f 1563 uint8_t link_bw, rate_select;
a8f3ef61 1564
94ca719e 1565 common_len = intel_dp_common_rates(intel_dp, common_rates);
a8f3ef61
SJ		 1566
1567 /* No common link rates between source and sink */
94ca719e 1568 WARN_ON(common_len <= 0);
a8f3ef61 1569
94ca719e 1570 max_clock = common_len - 1;
a4fc5ed6 1571
4f8036a2 1572 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
5bfe2ac0
DV		 1573 pipe_config->has_pch_encoder = true;
1574
f769cd24 1575 pipe_config->has_drrs = false;
9fcb1704 1576 pipe_config->has_audio = intel_dp->has_audio && port != PORT_A;
a4fc5ed6 1577
dd06f90e
JN		 1578 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1579 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1580 adjusted_mode);
a1b2278e
CK		 1581
1582 if (INTEL_INFO(dev)->gen >= 9) {
1583 int ret;
e435d6e5 1584 ret = skl_update_scaler_crtc(pipe_config);
a1b2278e
CK		 1585 if (ret)
1586 return ret;
1587 }
1588
49cff963 1589 if (HAS_GMCH_DISPLAY(dev_priv))
2dd24552
JB		 1590 intel_gmch_panel_fitting(intel_crtc, pipe_config,
1591 intel_connector->panel.fitting_mode);
1592 else
b074cec8
JB		 1593 intel_pch_panel_fitting(intel_crtc, pipe_config,
1594 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 1595 }
1596
cb1793ce 1597 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 1598 return false;
1599
083f9560 1600 DRM_DEBUG_KMS("DP link computation with max lane count %i "
a8f3ef61 1601 "max bw %d pixel clock %iKHz\n",
94ca719e 1602 max_lane_count, common_rates[max_clock],
241bfc38 1603 adjusted_mode->crtc_clock);
083f9560 1604
36008365
DV		 1605 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1606 * bpc in between. */
f9bb705e 1607 bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
56071a20 1608 if (is_edp(intel_dp)) {
22ce5628
TS		 1609
1610 /* Get bpp from vbt only for panels that dont have bpp in edid */
1611 if (intel_connector->base.display_info.bpc == 0 &&
6aa23e65 1612 (dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp)) {
56071a20 1613 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
6aa23e65
JN		 1614 dev_priv->vbt.edp.bpp);
1615 bpp = dev_priv->vbt.edp.bpp;
56071a20
JN		 1616 }
1617
344c5bbc
JN		 1618 /*
1619 * Use the maximum clock and number of lanes the eDP panel
1620 * advertizes being capable of. The panels are generally
1621 * designed to support only a single clock and lane
1622 * configuration, and typically these values correspond to the
1623 * native resolution of the panel.
1624 */
1625 min_lane_count = max_lane_count;
1626 min_clock = max_clock;
7984211e 1627 }
657445fe 1628
36008365 1629 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 1630 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1631 bpp);
36008365 1632
c6930992 1633 for (clock = min_clock; clock <= max_clock; clock++) {
a8f3ef61
SJ		 1634 for (lane_count = min_lane_count;
1635 lane_count <= max_lane_count;
1636 lane_count <<= 1) {
1637
94ca719e 1638 link_clock = common_rates[clock];
36008365
DV		 1639 link_avail = intel_dp_max_data_rate(link_clock,
1640 lane_count);
1641
1642 if (mode_rate <= link_avail) {
1643 goto found;
1644 }
1645 }
1646 }
1647 }
c4867936 1648
36008365 1649 return false;
3685a8f3 1650
36008365 1651found:
55bc60db
VS		 1652 if (intel_dp->color_range_auto) {
1653 /*
1654 * See:
1655 * CEA-861-E - 5.1 Default Encoding Parameters
1656 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1657 */
0f2a2a75
VS		 1658 pipe_config->limited_color_range =
1659 bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1;
1660 } else {
1661 pipe_config->limited_color_range =
1662 intel_dp->limited_color_range;
55bc60db
VS		 1663 }
1664
90a6b7b0 1665 pipe_config->lane_count = lane_count;
a8f3ef61 1666
657445fe 1667 pipe_config->pipe_bpp = bpp;
94ca719e 1668 pipe_config->port_clock = common_rates[clock];
a4fc5ed6 1669
04a60f9f
VS		 1670 intel_dp_compute_rate(intel_dp, pipe_config->port_clock,
1671 &link_bw, &rate_select);
1672
1673 DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
1674 link_bw, rate_select, pipe_config->lane_count,
ff9a6750 1675 pipe_config->port_clock, bpp);
36008365
DV		 1676 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1677 mode_rate, link_avail);
a4fc5ed6 1678
03afc4a2 1679 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 1680 adjusted_mode->crtc_clock,
1681 pipe_config->port_clock,
03afc4a2 1682 &pipe_config->dp_m_n);
9d1a455b 1683
439d7ac0 1684 if (intel_connector->panel.downclock_mode != NULL &&
96178eeb 1685 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
f769cd24 1686 pipe_config->has_drrs = true;
439d7ac0
PB		 1687 intel_link_compute_m_n(bpp, lane_count,
1688 intel_connector->panel.downclock_mode->clock,
1689 pipe_config->port_clock,
1690 &pipe_config->dp_m2_n2);
1691 }
1692
14d41b3b
VS		 1693 /*
1694 * DPLL0 VCO may need to be adjusted to get the correct
1695 * clock for eDP. This will affect cdclk as well.
1696 */
1697 if (is_edp(intel_dp) &&
1698 (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))) {
1699 int vco;
1700
1701 switch (pipe_config->port_clock / 2) {
1702 case 108000:
1703 case 216000:
63911d72 1704 vco = 8640000;
14d41b3b
VS		 1705 break;
1706 default:
63911d72 1707 vco = 8100000;
14d41b3b
VS		 1708 break;
1709 }
1710
1711 to_intel_atomic_state(pipe_config->base.state)->cdclk_pll_vco = vco;
1712 }
1713
4f8036a2 1714 if (!HAS_DDI(dev_priv))
840b32b7 1715 intel_dp_set_clock(encoder, pipe_config);
c6bb3538 1716
03afc4a2 1717 return true;
a4fc5ed6
KP		 1718}
1719
901c2daf 1720void intel_dp_set_link_params(struct intel_dp *intel_dp,
dfa10480
ACO		 1721 int link_rate, uint8_t lane_count,
1722 bool link_mst)
901c2daf 1723{
dfa10480
ACO		 1724 intel_dp->link_rate = link_rate;
1725 intel_dp->lane_count = lane_count;
1726 intel_dp->link_mst = link_mst;
901c2daf
VS		 1727}
1728
85cb48a1
ML		 1729static void intel_dp_prepare(struct intel_encoder *encoder,
1730 struct intel_crtc_state *pipe_config)
a4fc5ed6 1731{
b934223d 1732 struct drm_device *dev = encoder->base.dev;
fac5e23e 1733 struct drm_i915_private *dev_priv = to_i915(dev);
b934223d 1734 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1735 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d 1736 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
85cb48a1 1737 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
a4fc5ed6 1738
dfa10480
ACO		 1739 intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
1740 pipe_config->lane_count,
1741 intel_crtc_has_type(pipe_config,
1742 INTEL_OUTPUT_DP_MST));
901c2daf 1743
417e822d 1744 /*
1a2eb460 1745 * There are four kinds of DP registers:
417e822d
KP		 1746 *
1747 * IBX PCH
1a2eb460
KP		 1748 * SNB CPU
1749 * IVB CPU
417e822d
KP		 1750 * CPT PCH
1751 *
1752 * IBX PCH and CPU are the same for almost everything,
1753 * except that the CPU DP PLL is configured in this
1754 * register
1755 *
1756 * CPT PCH is quite different, having many bits moved
1757 * to the TRANS_DP_CTL register instead. That
1758 * configuration happens (oddly) in ironlake_pch_enable
1759 */
9c9e7927 1760
417e822d
KP		 1761 /* Preserve the BIOS-computed detected bit. This is
1762 * supposed to be read-only.
1763 */
1764 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 1765
417e822d 1766 /* Handle DP bits in common between all three register formats */
417e822d 1767 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
85cb48a1 1768 intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
a4fc5ed6 1769
417e822d 1770 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1771
5db94019 1772 if (IS_GEN7(dev_priv) && port == PORT_A) {
1a2eb460
KP		 1773 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1774 intel_dp->DP |= DP_SYNC_HS_HIGH;
1775 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1776 intel_dp->DP |= DP_SYNC_VS_HIGH;
1777 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1778
6aba5b6c 1779 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1780 intel_dp->DP |= DP_ENHANCED_FRAMING;
1781
7c62a164 1782 intel_dp->DP |= crtc->pipe << 29;
6e266956 1783 } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
e3ef4479
VS		 1784 u32 trans_dp;
1785
39e5fa88 1786 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
e3ef4479
VS		 1787
1788 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1789 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1790 trans_dp |= TRANS_DP_ENH_FRAMING;
1791 else
1792 trans_dp &= ~TRANS_DP_ENH_FRAMING;
1793 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
39e5fa88 1794 } else {
11a914c2 1795 if (!HAS_PCH_SPLIT(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
920a14b2
TU		 1796 !IS_CHERRYVIEW(dev_priv) &&
1797 pipe_config->limited_color_range)
0f2a2a75 1798 intel_dp->DP |= DP_COLOR_RANGE_16_235;
417e822d
KP		 1799
1800 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1801 intel_dp->DP |= DP_SYNC_HS_HIGH;
1802 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1803 intel_dp->DP |= DP_SYNC_VS_HIGH;
1804 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1805
6aba5b6c 1806 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1807 intel_dp->DP |= DP_ENHANCED_FRAMING;
1808
920a14b2 1809 if (IS_CHERRYVIEW(dev_priv))
44f37d1f 1810 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
39e5fa88
VS		 1811 else if (crtc->pipe == PIPE_B)
1812 intel_dp->DP |= DP_PIPEB_SELECT;
32f9d658 1813 }
a4fc5ed6
KP		 1814}
1815
ffd6749d
PZ		 1816#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1817#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1818
1a5ef5b7
PZ		 1819#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1820#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1821
ffd6749d
PZ		 1822#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1823#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1824
de9c1b6b
ID		 1825static void intel_pps_verify_state(struct drm_i915_private *dev_priv,
1826 struct intel_dp *intel_dp);
1827
4be73780 1828static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1829 u32 mask,
1830 u32 value)
bd943159 1831{
30add22d 1832 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 1833 struct drm_i915_private *dev_priv = to_i915(dev);
f0f59a00 1834 i915_reg_t pp_stat_reg, pp_ctrl_reg;
453c5420 1835
e39b999a
VS		 1836 lockdep_assert_held(&dev_priv->pps_mutex);
1837
de9c1b6b
ID		 1838 intel_pps_verify_state(dev_priv, intel_dp);
1839
bf13e81b
JN		 1840 pp_stat_reg = _pp_stat_reg(intel_dp);
1841 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1842
99ea7127 1843 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1844 mask, value,
1845 I915_READ(pp_stat_reg),
1846 I915_READ(pp_ctrl_reg));
32ce697c 1847
9036ff06
CW		 1848 if (intel_wait_for_register(dev_priv,
1849 pp_stat_reg, mask, value,
1850 5000))
99ea7127 1851 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1852 I915_READ(pp_stat_reg),
1853 I915_READ(pp_ctrl_reg));
54c136d4
CW		 1854
1855 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1856}
32ce697c 1857
4be73780 1858static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1859{
1860 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1861 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1862}
1863
4be73780 1864static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1865{
1866 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1867 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1868}
1869
4be73780 1870static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127 1871{
d28d4731
AK		 1872 ktime_t panel_power_on_time;
1873 s64 panel_power_off_duration;
1874
99ea7127 1875 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c 1876
d28d4731
AK		 1877 /* take the difference of currrent time and panel power off time
1878 * and then make panel wait for t11_t12 if needed. */
1879 panel_power_on_time = ktime_get_boottime();
1880 panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
1881
dce56b3c
PZ		 1882 /* When we disable the VDD override bit last we have to do the manual
1883 * wait. */
d28d4731
AK		 1884 if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
1885 wait_remaining_ms_from_jiffies(jiffies,
1886 intel_dp->panel_power_cycle_delay - panel_power_off_duration);
dce56b3c 1887
4be73780 1888 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1889}
1890
4be73780 1891static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1892{
1893 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1894 intel_dp->backlight_on_delay);
1895}
1896
4be73780 1897static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1898{
1899 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1900 intel_dp->backlight_off_delay);
1901}
99ea7127 1902
832dd3c1
KP		 1903/* Read the current pp_control value, unlocking the register if it
1904 * is locked
1905 */
1906
453c5420 1907static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1908{
453c5420 1909 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 1910 struct drm_i915_private *dev_priv = to_i915(dev);
453c5420 1911 u32 control;
832dd3c1 1912
e39b999a
VS		 1913 lockdep_assert_held(&dev_priv->pps_mutex);
1914
bf13e81b 1915 control = I915_READ(_pp_ctrl_reg(intel_dp));
8090ba8c
ID		 1916 if (WARN_ON(!HAS_DDI(dev_priv) &&
1917 (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
b0a08bec
VK		 1918 control &= ~PANEL_UNLOCK_MASK;
1919 control |= PANEL_UNLOCK_REGS;
1920 }
832dd3c1 1921 return control;
bd943159
KP		 1922}
1923
951468f3
VS		 1924/*
1925 * Must be paired with edp_panel_vdd_off().
1926 * Must hold pps_mutex around the whole on/off sequence.
1927 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1928 */
1e0560e0 1929static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1930{
30add22d 1931 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1932 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1933 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fac5e23e 1934 struct drm_i915_private *dev_priv = to_i915(dev);
4e6e1a54 1935 enum intel_display_power_domain power_domain;
5d613501 1936 u32 pp;
f0f59a00 1937 i915_reg_t pp_stat_reg, pp_ctrl_reg;
adddaaf4 1938 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1939
e39b999a
VS		 1940 lockdep_assert_held(&dev_priv->pps_mutex);
1941
97af61f5 1942 if (!is_edp(intel_dp))
adddaaf4 1943 return false;
bd943159 1944
2c623c11 1945 cancel_delayed_work(&intel_dp->panel_vdd_work);
bd943159 1946 intel_dp->want_panel_vdd = true;
99ea7127 1947
4be73780 1948 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1949 return need_to_disable;
b0665d57 1950
25f78f58 1951 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4e6e1a54 1952 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1953
3936fcf4
VS		 1954 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1955 port_name(intel_dig_port->port));
bd943159 1956
4be73780
DV		 1957 if (!edp_have_panel_power(intel_dp))
1958 wait_panel_power_cycle(intel_dp);
99ea7127 1959
453c5420 1960 pp = ironlake_get_pp_control(intel_dp);
5d613501 1961 pp |= EDP_FORCE_VDD;
ebf33b18 1962
bf13e81b
JN		 1963 pp_stat_reg = _pp_stat_reg(intel_dp);
1964 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1965
1966 I915_WRITE(pp_ctrl_reg, pp);
1967 POSTING_READ(pp_ctrl_reg);
1968 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1969 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1970 /*
1971 * If the panel wasn't on, delay before accessing aux channel
1972 */
4be73780 1973 if (!edp_have_panel_power(intel_dp)) {
3936fcf4
VS		 1974 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1975 port_name(intel_dig_port->port));
f01eca2e 1976 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1977 }
adddaaf4
JN		 1978
1979 return need_to_disable;
1980}
1981
951468f3
VS		 1982/*
1983 * Must be paired with intel_edp_panel_vdd_off() or
1984 * intel_edp_panel_off().
1985 * Nested calls to these functions are not allowed since
1986 * we drop the lock. Caller must use some higher level
1987 * locking to prevent nested calls from other threads.
1988 */
b80d6c78 1989void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4 1990{
c695b6b6 1991 bool vdd;
adddaaf4 1992
c695b6b6
VS		 1993 if (!is_edp(intel_dp))
1994 return;
1995
773538e8 1996 pps_lock(intel_dp);
c695b6b6 1997 vdd = edp_panel_vdd_on(intel_dp);
773538e8 1998 pps_unlock(intel_dp);
c695b6b6 1999
e2c719b7 2000 I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
3936fcf4 2001 port_name(dp_to_dig_port(intel_dp)->port));
5d613501
JB		 2002}
2003
4be73780 2004static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 2005{
30add22d 2006 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 2007 struct drm_i915_private *dev_priv = to_i915(dev);
be2c9196
VS		 2008 struct intel_digital_port *intel_dig_port =
2009 dp_to_dig_port(intel_dp);
2010 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2011 enum intel_display_power_domain power_domain;
5d613501 2012 u32 pp;
f0f59a00 2013 i915_reg_t pp_stat_reg, pp_ctrl_reg;
5d613501 2014
e39b999a 2015 lockdep_assert_held(&dev_priv->pps_mutex);
a0e99e68 2016
15e899a0 2017 WARN_ON(intel_dp->want_panel_vdd);
4e6e1a54 2018
15e899a0 2019 if (!edp_have_panel_vdd(intel_dp))
be2c9196 2020 return;
b0665d57 2021
3936fcf4
VS		 2022 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
2023 port_name(intel_dig_port->port));
bd943159 2024
be2c9196
VS		 2025 pp = ironlake_get_pp_control(intel_dp);
2026 pp &= ~EDP_FORCE_VDD;
453c5420 2027
be2c9196
VS		 2028 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2029 pp_stat_reg = _pp_stat_reg(intel_dp);
99ea7127 2030
be2c9196
VS		 2031 I915_WRITE(pp_ctrl_reg, pp);
2032 POSTING_READ(pp_ctrl_reg);
90791a5c 2033
be2c9196
VS		 2034 /* Make sure sequencer is idle before allowing subsequent activity */
2035 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2036 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
e9cb81a2 2037
5a162e22 2038 if ((pp & PANEL_POWER_ON) == 0)
d28d4731 2039 intel_dp->panel_power_off_time = ktime_get_boottime();
e9cb81a2 2040
25f78f58 2041 power_domain = intel_display_port_aux_power_domain(intel_encoder);
be2c9196 2042 intel_display_power_put(dev_priv, power_domain);
bd943159 2043}
5d613501 2044
4be73780 2045static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 2046{
2047 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
2048 struct intel_dp, panel_vdd_work);
bd943159 2049
773538e8 2050 pps_lock(intel_dp);
15e899a0
VS		 2051 if (!intel_dp->want_panel_vdd)
2052 edp_panel_vdd_off_sync(intel_dp);
773538e8 2053 pps_unlock(intel_dp);
bd943159
KP		 2054}
2055
aba86890
ID		 2056static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
2057{
2058 unsigned long delay;
2059
2060 /*
2061 * Queue the timer to fire a long time from now (relative to the power
2062 * down delay) to keep the panel power up across a sequence of
2063 * operations.
2064 */
2065 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
2066 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
2067}
2068
951468f3
VS		 2069/*
2070 * Must be paired with edp_panel_vdd_on().
2071 * Must hold pps_mutex around the whole on/off sequence.
2072 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2073 */
4be73780 2074static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 2075{
fac5e23e 2076 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
e39b999a
VS		 2077
2078 lockdep_assert_held(&dev_priv->pps_mutex);
2079
97af61f5
KP		 2080 if (!is_edp(intel_dp))
2081 return;
5d613501 2082
e2c719b7 2083 I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
3936fcf4 2084 port_name(dp_to_dig_port(intel_dp)->port));
f2e8b18a 2085
bd943159
KP		 2086 intel_dp->want_panel_vdd = false;
2087
aba86890 2088 if (sync)
4be73780 2089 edp_panel_vdd_off_sync(intel_dp);
aba86890
ID		 2090 else
2091 edp_panel_vdd_schedule_off(intel_dp);
5d613501
JB		 2092}
2093
9f0fb5be 2094static void edp_panel_on(struct intel_dp *intel_dp)
9934c132 2095{
30add22d 2096 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 2097 struct drm_i915_private *dev_priv = to_i915(dev);
99ea7127 2098 u32 pp;
f0f59a00 2099 i915_reg_t pp_ctrl_reg;
9934c132 2100
9f0fb5be
VS		 2101 lockdep_assert_held(&dev_priv->pps_mutex);
2102
97af61f5 2103 if (!is_edp(intel_dp))
bd943159 2104 return;
99ea7127 2105
3936fcf4
VS		 2106 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2107 port_name(dp_to_dig_port(intel_dp)->port));
e39b999a 2108
e7a89ace
VS		 2109 if (WARN(edp_have_panel_power(intel_dp),
2110 "eDP port %c panel power already on\n",
2111 port_name(dp_to_dig_port(intel_dp)->port)))
9f0fb5be 2112 return;
9934c132 2113
4be73780 2114 wait_panel_power_cycle(intel_dp);
37c6c9b0 2115
bf13e81b 2116 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 2117 pp = ironlake_get_pp_control(intel_dp);
5db94019 2118 if (IS_GEN5(dev_priv)) {
05ce1a49
KP		 2119 /* ILK workaround: disable reset around power sequence */
2120 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 2121 I915_WRITE(pp_ctrl_reg, pp);
2122 POSTING_READ(pp_ctrl_reg);
05ce1a49 2123 }
37c6c9b0 2124
5a162e22 2125 pp |= PANEL_POWER_ON;
5db94019 2126 if (!IS_GEN5(dev_priv))
99ea7127
KP		 2127 pp |= PANEL_POWER_RESET;
2128
453c5420
JB		 2129 I915_WRITE(pp_ctrl_reg, pp);
2130 POSTING_READ(pp_ctrl_reg);
9934c132 2131
4be73780 2132 wait_panel_on(intel_dp);
dce56b3c 2133 intel_dp->last_power_on = jiffies;
9934c132 2134
5db94019 2135 if (IS_GEN5(dev_priv)) {
05ce1a49 2136 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 2137 I915_WRITE(pp_ctrl_reg, pp);
2138 POSTING_READ(pp_ctrl_reg);
05ce1a49 2139 }
9f0fb5be 2140}
e39b999a 2141
9f0fb5be
VS		 2142void intel_edp_panel_on(struct intel_dp *intel_dp)
2143{
2144 if (!is_edp(intel_dp))
2145 return;
2146
2147 pps_lock(intel_dp);
2148 edp_panel_on(intel_dp);
773538e8 2149 pps_unlock(intel_dp);
9934c132
JB		 2150}
2151
9f0fb5be
VS		 2152
2153static void edp_panel_off(struct intel_dp *intel_dp)
9934c132 2154{
4e6e1a54
ID		 2155 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2156 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 2157 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 2158 struct drm_i915_private *dev_priv = to_i915(dev);
4e6e1a54 2159 enum intel_display_power_domain power_domain;
99ea7127 2160 u32 pp;
f0f59a00 2161 i915_reg_t pp_ctrl_reg;
9934c132 2162
9f0fb5be
VS		 2163 lockdep_assert_held(&dev_priv->pps_mutex);
2164
97af61f5
KP		 2165 if (!is_edp(intel_dp))
2166 return;
37c6c9b0 2167
3936fcf4
VS		 2168 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2169 port_name(dp_to_dig_port(intel_dp)->port));
37c6c9b0 2170
3936fcf4
VS		 2171 WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2172 port_name(dp_to_dig_port(intel_dp)->port));
24f3e092 2173
453c5420 2174 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 2175 /* We need to switch off panel power _and_ force vdd, for otherwise some
2176 * panels get very unhappy and cease to work. */
5a162e22 2177 pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
b3064154 2178 EDP_BLC_ENABLE);
453c5420 2179
bf13e81b 2180 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 2181
849e39f5
PZ		 2182 intel_dp->want_panel_vdd = false;
2183
453c5420
JB		 2184 I915_WRITE(pp_ctrl_reg, pp);
2185 POSTING_READ(pp_ctrl_reg);
9934c132 2186
d28d4731 2187 intel_dp->panel_power_off_time = ktime_get_boottime();
4be73780 2188 wait_panel_off(intel_dp);
849e39f5
PZ		 2189
2190 /* We got a reference when we enabled the VDD. */
25f78f58 2191 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4e6e1a54 2192 intel_display_power_put(dev_priv, power_domain);
9f0fb5be 2193}
e39b999a 2194
9f0fb5be
VS		 2195void intel_edp_panel_off(struct intel_dp *intel_dp)
2196{
2197 if (!is_edp(intel_dp))
2198 return;
e39b999a 2199
9f0fb5be
VS		 2200 pps_lock(intel_dp);
2201 edp_panel_off(intel_dp);
773538e8 2202 pps_unlock(intel_dp);
9934c132
JB		 2203}
2204
1250d107
JN		 2205/* Enable backlight in the panel power control. */
2206static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 2207{
da63a9f2
PZ		 2208 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2209 struct drm_device *dev = intel_dig_port->base.base.dev;
fac5e23e 2210 struct drm_i915_private *dev_priv = to_i915(dev);
32f9d658 2211 u32 pp;
f0f59a00 2212 i915_reg_t pp_ctrl_reg;
32f9d658 2213
01cb9ea6
JB		 2214 /*
2215 * If we enable the backlight right away following a panel power
2216 * on, we may see slight flicker as the panel syncs with the eDP
2217 * link. So delay a bit to make sure the image is solid before
2218 * allowing it to appear.
2219 */
4be73780 2220 wait_backlight_on(intel_dp);
e39b999a 2221
773538e8 2222 pps_lock(intel_dp);
e39b999a 2223
453c5420 2224 pp = ironlake_get_pp_control(intel_dp);
32f9d658 2225 pp |= EDP_BLC_ENABLE;
453c5420 2226
bf13e81b 2227 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 2228
2229 I915_WRITE(pp_ctrl_reg, pp);
2230 POSTING_READ(pp_ctrl_reg);
e39b999a 2231
773538e8 2232 pps_unlock(intel_dp);
32f9d658
ZW		 2233}
2234
1250d107
JN		 2235/* Enable backlight PWM and backlight PP control. */
2236void intel_edp_backlight_on(struct intel_dp *intel_dp)
2237{
2238 if (!is_edp(intel_dp))
2239 return;
2240
2241 DRM_DEBUG_KMS("\n");
2242
2243 intel_panel_enable_backlight(intel_dp->attached_connector);
2244 _intel_edp_backlight_on(intel_dp);
2245}
2246
2247/* Disable backlight in the panel power control. */
2248static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 2249{
30add22d 2250 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 2251 struct drm_i915_private *dev_priv = to_i915(dev);
32f9d658 2252 u32 pp;
f0f59a00 2253 i915_reg_t pp_ctrl_reg;
32f9d658 2254
f01eca2e
KP		 2255 if (!is_edp(intel_dp))
2256 return;
2257
773538e8 2258 pps_lock(intel_dp);
e39b999a 2259
453c5420 2260 pp = ironlake_get_pp_control(intel_dp);
32f9d658 2261 pp &= ~EDP_BLC_ENABLE;
453c5420 2262
bf13e81b 2263 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 2264
2265 I915_WRITE(pp_ctrl_reg, pp);
2266 POSTING_READ(pp_ctrl_reg);
f7d2323c 2267
773538e8 2268 pps_unlock(intel_dp);
e39b999a
VS		 2269
2270 intel_dp->last_backlight_off = jiffies;
f7d2323c 2271 edp_wait_backlight_off(intel_dp);
1250d107 2272}
f7d2323c 2273
1250d107
JN		 2274/* Disable backlight PP control and backlight PWM. */
2275void intel_edp_backlight_off(struct intel_dp *intel_dp)
2276{
2277 if (!is_edp(intel_dp))
2278 return;
2279
2280 DRM_DEBUG_KMS("\n");
f7d2323c 2281
1250d107 2282 _intel_edp_backlight_off(intel_dp);
f7d2323c 2283 intel_panel_disable_backlight(intel_dp->attached_connector);
32f9d658 2284}
a4fc5ed6 2285
73580fb7
JN		 2286/*
2287 * Hook for controlling the panel power control backlight through the bl_power
2288 * sysfs attribute. Take care to handle multiple calls.
2289 */
2290static void intel_edp_backlight_power(struct intel_connector *connector,
2291 bool enable)
2292{
2293 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
e39b999a
VS		 2294 bool is_enabled;
2295
773538e8 2296 pps_lock(intel_dp);
e39b999a 2297 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
773538e8 2298 pps_unlock(intel_dp);
73580fb7
JN		 2299
2300 if (is_enabled == enable)
2301 return;
2302
23ba9373
JN		 2303 DRM_DEBUG_KMS("panel power control backlight %s\n",
2304 enable ? "enable" : "disable");
73580fb7
JN		 2305
2306 if (enable)
2307 _intel_edp_backlight_on(intel_dp);
2308 else
2309 _intel_edp_backlight_off(intel_dp);
2310}
2311
64e1077a
VS		 2312static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2313{
2314 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2315 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2316 bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2317
2318 I915_STATE_WARN(cur_state != state,
2319 "DP port %c state assertion failure (expected %s, current %s)\n",
2320 port_name(dig_port->port),
87ad3212 2321 onoff(state), onoff(cur_state));
64e1077a
VS		 2322}
2323#define assert_dp_port_disabled(d) assert_dp_port((d), false)
2324
2325static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2326{
2327 bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2328
2329 I915_STATE_WARN(cur_state != state,
2330 "eDP PLL state assertion failure (expected %s, current %s)\n",
87ad3212 2331 onoff(state), onoff(cur_state));
64e1077a
VS		 2332}
2333#define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2334#define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2335
85cb48a1
ML		 2336static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
2337 struct intel_crtc_state *pipe_config)
d240f20f 2338{
85cb48a1 2339 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
64e1077a 2340 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
d240f20f 2341
64e1077a
VS		 2342 assert_pipe_disabled(dev_priv, crtc->pipe);
2343 assert_dp_port_disabled(intel_dp);
2344 assert_edp_pll_disabled(dev_priv);
2bd2ad64 2345
abfce949 2346 DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
85cb48a1 2347 pipe_config->port_clock);
abfce949
VS		 2348
2349 intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2350
85cb48a1 2351 if (pipe_config->port_clock == 162000)
abfce949
VS		 2352 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2353 else
2354 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2355
2356 I915_WRITE(DP_A, intel_dp->DP);
2357 POSTING_READ(DP_A);
2358 udelay(500);
2359
6b23f3e8
VS		 2360 /*
2361 * [DevILK] Work around required when enabling DP PLL
2362 * while a pipe is enabled going to FDI:
2363 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2364 * 2. Program DP PLL enable
2365 */
2366 if (IS_GEN5(dev_priv))
91c8a326 2367 intel_wait_for_vblank_if_active(&dev_priv->drm, !crtc->pipe);
6b23f3e8 2368
0767935e 2369 intel_dp->DP |= DP_PLL_ENABLE;
6fec7662 2370
0767935e 2371 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 2372 POSTING_READ(DP_A);
2373 udelay(200);
d240f20f
JB		 2374}
2375
2bd2ad64 2376static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 2377{
da63a9f2 2378 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
64e1077a
VS		 2379 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
2380 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
d240f20f 2381
64e1077a
VS		 2382 assert_pipe_disabled(dev_priv, crtc->pipe);
2383 assert_dp_port_disabled(intel_dp);
2384 assert_edp_pll_enabled(dev_priv);
2bd2ad64 2385
abfce949
VS		 2386 DRM_DEBUG_KMS("disabling eDP PLL\n");
2387
6fec7662 2388 intel_dp->DP &= ~DP_PLL_ENABLE;
0767935e 2389
6fec7662 2390 I915_WRITE(DP_A, intel_dp->DP);
1af5fa1b 2391 POSTING_READ(DP_A);
d240f20f
JB		 2392 udelay(200);
2393}
2394
c7ad3810 2395/* If the sink supports it, try to set the power state appropriately */
c19b0669 2396void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 2397{
2398 int ret, i;
2399
2400 /* Should have a valid DPCD by this point */
2401 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2402 return;
2403
2404 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 2405 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2406 DP_SET_POWER_D3);
c7ad3810
JB		 2407 } else {
2408 /*
2409 * When turning on, we need to retry for 1ms to give the sink
2410 * time to wake up.
2411 */
2412 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2413 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2414 DP_SET_POWER_D0);
c7ad3810
JB		 2415 if (ret == 1)
2416 break;
2417 msleep(1);
2418 }
2419 }
f9cac721
JN		 2420
2421 if (ret != 1)
2422 DRM_DEBUG_KMS("failed to %s sink power state\n",
2423 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
c7ad3810
JB		 2424}
2425
19d8fe15
DV		 2426static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2427 enum pipe *pipe)
d240f20f 2428{
19d8fe15 2429 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2430 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15 2431 struct drm_device *dev = encoder->base.dev;
fac5e23e 2432 struct drm_i915_private *dev_priv = to_i915(dev);
6d129bea
ID		 2433 enum intel_display_power_domain power_domain;
2434 u32 tmp;
6fa9a5ec 2435 bool ret;
6d129bea
ID		 2436
2437 power_domain = intel_display_port_power_domain(encoder);
6fa9a5ec 2438 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
6d129bea
ID		 2439 return false;
2440
6fa9a5ec
ID		 2441 ret = false;
2442
6d129bea 2443 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 2444
2445 if (!(tmp & DP_PORT_EN))
6fa9a5ec 2446 goto out;
19d8fe15 2447
5db94019 2448 if (IS_GEN7(dev_priv) && port == PORT_A) {
19d8fe15 2449 *pipe = PORT_TO_PIPE_CPT(tmp);
6e266956 2450 } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
adc289d7 2451 enum pipe p;
19d8fe15 2452
adc289d7
VS		 2453 for_each_pipe(dev_priv, p) {
2454 u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
2455 if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) {
2456 *pipe = p;
6fa9a5ec
ID		 2457 ret = true;
2458
2459 goto out;
19d8fe15
DV		 2460 }
2461 }
19d8fe15 2462
4a0833ec 2463 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
f0f59a00 2464 i915_mmio_reg_offset(intel_dp->output_reg));
920a14b2 2465 } else if (IS_CHERRYVIEW(dev_priv)) {
39e5fa88
VS		 2466 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
2467 } else {
2468 *pipe = PORT_TO_PIPE(tmp);
4a0833ec 2469 }
d240f20f 2470
6fa9a5ec
ID		 2471 ret = true;
2472
2473out:
2474 intel_display_power_put(dev_priv, power_domain);
2475
2476 return ret;
19d8fe15 2477}
d240f20f 2478
045ac3b5 2479static void intel_dp_get_config(struct intel_encoder *encoder,
5cec258b 2480 struct intel_crtc_state *pipe_config)
045ac3b5
JB		 2481{
2482 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 2483 u32 tmp, flags = 0;
63000ef6 2484 struct drm_device *dev = encoder->base.dev;
fac5e23e 2485 struct drm_i915_private *dev_priv = to_i915(dev);
63000ef6
XZ		 2486 enum port port = dp_to_dig_port(intel_dp)->port;
2487 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
045ac3b5 2488
9ed109a7 2489 tmp = I915_READ(intel_dp->output_reg);
9fcb1704
JN		 2490
2491 pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
9ed109a7 2492
6e266956 2493 if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
b81e34c2
VS		 2494 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2495
2496 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
63000ef6
XZ		 2497 flags |= DRM_MODE_FLAG_PHSYNC;
2498 else
2499 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 2500
b81e34c2 2501 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
63000ef6
XZ		 2502 flags |= DRM_MODE_FLAG_PVSYNC;
2503 else
2504 flags |= DRM_MODE_FLAG_NVSYNC;
2505 } else {
39e5fa88 2506 if (tmp & DP_SYNC_HS_HIGH)
63000ef6
XZ		 2507 flags |= DRM_MODE_FLAG_PHSYNC;
2508 else
2509 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 2510
39e5fa88 2511 if (tmp & DP_SYNC_VS_HIGH)
63000ef6
XZ		 2512 flags |= DRM_MODE_FLAG_PVSYNC;
2513 else
2514 flags |= DRM_MODE_FLAG_NVSYNC;
2515 }
045ac3b5 2516
2d112de7 2517 pipe_config->base.adjusted_mode.flags |= flags;
f1f644dc 2518
6e266956
TU		 2519 if (!HAS_PCH_SPLIT(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
2520 !IS_CHERRYVIEW(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
8c875fca
VS		 2521 pipe_config->limited_color_range = true;
2522
90a6b7b0
VS		 2523 pipe_config->lane_count =
2524 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
2525
eb14cb74
VS		 2526 intel_dp_get_m_n(crtc, pipe_config);
2527
18442d08 2528 if (port == PORT_A) {
b377e0df 2529 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
f1f644dc
JB		 2530 pipe_config->port_clock = 162000;
2531 else
2532 pipe_config->port_clock = 270000;
2533 }
18442d08 2534
e3b247da
VS		 2535 pipe_config->base.adjusted_mode.crtc_clock =
2536 intel_dotclock_calculate(pipe_config->port_clock,
2537 &pipe_config->dp_m_n);
7f16e5c1 2538
6aa23e65
JN		 2539 if (is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
2540 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
c6cd2ee2
JN		 2541 /*
2542 * This is a big fat ugly hack.
2543 *
2544 * Some machines in UEFI boot mode provide us a VBT that has 18
2545 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2546 * unknown we fail to light up. Yet the same BIOS boots up with
2547 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2548 * max, not what it tells us to use.
2549 *
2550 * Note: This will still be broken if the eDP panel is not lit
2551 * up by the BIOS, and thus we can't get the mode at module
2552 * load.
2553 */
2554 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
6aa23e65
JN		 2555 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2556 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
c6cd2ee2 2557 }
045ac3b5
JB		 2558}
2559
fd6bbda9
ML		 2560static void intel_disable_dp(struct intel_encoder *encoder,
2561 struct intel_crtc_state *old_crtc_state,
2562 struct drm_connector_state *old_conn_state)
d240f20f 2563{
e8cb4558 2564 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
85cb48a1 2565 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
495a5bb8 2566
85cb48a1 2567 if (old_crtc_state->has_audio)
495a5bb8 2568 intel_audio_codec_disable(encoder);
6cb49835 2569
85cb48a1 2570 if (HAS_PSR(dev_priv) && !HAS_DDI(dev_priv))
b32c6f48
RV		 2571 intel_psr_disable(intel_dp);
2572
6cb49835
DV		 2573 /* Make sure the panel is off before trying to change the mode. But also
2574 * ensure that we have vdd while we switch off the panel. */
24f3e092 2575 intel_edp_panel_vdd_on(intel_dp);
4be73780 2576 intel_edp_backlight_off(intel_dp);
fdbc3b1f 2577 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 2578 intel_edp_panel_off(intel_dp);
3739850b 2579
08aff3fe 2580 /* disable the port before the pipe on g4x */
85cb48a1 2581 if (INTEL_GEN(dev_priv) < 5)
3739850b 2582 intel_dp_link_down(intel_dp);
d240f20f
JB		 2583}
2584
fd6bbda9
ML		 2585static void ilk_post_disable_dp(struct intel_encoder *encoder,
2586 struct intel_crtc_state *old_crtc_state,
2587 struct drm_connector_state *old_conn_state)
d240f20f 2588{
2bd2ad64 2589 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2590 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 2591
49277c31 2592 intel_dp_link_down(intel_dp);
abfce949
VS		 2593
2594 /* Only ilk+ has port A */
08aff3fe
VS		 2595 if (port == PORT_A)
2596 ironlake_edp_pll_off(intel_dp);
49277c31
VS		 2597}
2598
fd6bbda9
ML		 2599static void vlv_post_disable_dp(struct intel_encoder *encoder,
2600 struct intel_crtc_state *old_crtc_state,
2601 struct drm_connector_state *old_conn_state)
49277c31
VS		 2602{
2603 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2604
2605 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 2606}
2607
fd6bbda9
ML		 2608static void chv_post_disable_dp(struct intel_encoder *encoder,
2609 struct intel_crtc_state *old_crtc_state,
2610 struct drm_connector_state *old_conn_state)
a8f327fb
VS		 2611{
2612 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2613 struct drm_device *dev = encoder->base.dev;
fac5e23e 2614 struct drm_i915_private *dev_priv = to_i915(dev);
97fd4d5c 2615
a8f327fb
VS		 2616 intel_dp_link_down(intel_dp);
2617
2618 mutex_lock(&dev_priv->sb_lock);
2619
2620 /* Assert data lane reset */
2621 chv_data_lane_soft_reset(encoder, true);
580d3811 2622
a580516d 2623 mutex_unlock(&dev_priv->sb_lock);
580d3811
VS		 2624}
2625
7b13b58a
VS		 2626static void
2627_intel_dp_set_link_train(struct intel_dp *intel_dp,
2628 uint32_t *DP,
2629 uint8_t dp_train_pat)
2630{
2631 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2632 struct drm_device *dev = intel_dig_port->base.base.dev;
fac5e23e 2633 struct drm_i915_private *dev_priv = to_i915(dev);
7b13b58a
VS		 2634 enum port port = intel_dig_port->port;
2635
8b0878a0
PD		 2636 if (dp_train_pat & DP_TRAINING_PATTERN_MASK)
2637 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
2638 dp_train_pat & DP_TRAINING_PATTERN_MASK);
2639
4f8036a2 2640 if (HAS_DDI(dev_priv)) {
7b13b58a
VS		 2641 uint32_t temp = I915_READ(DP_TP_CTL(port));
2642
2643 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2644 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2645 else
2646 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2647
2648 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2649 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2650 case DP_TRAINING_PATTERN_DISABLE:
2651 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2652
2653 break;
2654 case DP_TRAINING_PATTERN_1:
2655 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2656 break;
2657 case DP_TRAINING_PATTERN_2:
2658 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2659 break;
2660 case DP_TRAINING_PATTERN_3:
2661 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2662 break;
2663 }
2664 I915_WRITE(DP_TP_CTL(port), temp);
2665
5db94019 2666 } else if ((IS_GEN7(dev_priv) && port == PORT_A) ||
6e266956 2667 (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
7b13b58a
VS		 2668 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2669
2670 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2671 case DP_TRAINING_PATTERN_DISABLE:
2672 *DP |= DP_LINK_TRAIN_OFF_CPT;
2673 break;
2674 case DP_TRAINING_PATTERN_1:
2675 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2676 break;
2677 case DP_TRAINING_PATTERN_2:
2678 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2679 break;
2680 case DP_TRAINING_PATTERN_3:
8b0878a0 2681 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
7b13b58a
VS		 2682 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2683 break;
2684 }
2685
2686 } else {
920a14b2 2687 if (IS_CHERRYVIEW(dev_priv))
7b13b58a
VS		 2688 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2689 else
2690 *DP &= ~DP_LINK_TRAIN_MASK;
2691
2692 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2693 case DP_TRAINING_PATTERN_DISABLE:
2694 *DP |= DP_LINK_TRAIN_OFF;
2695 break;
2696 case DP_TRAINING_PATTERN_1:
2697 *DP |= DP_LINK_TRAIN_PAT_1;
2698 break;
2699 case DP_TRAINING_PATTERN_2:
2700 *DP |= DP_LINK_TRAIN_PAT_2;
2701 break;
2702 case DP_TRAINING_PATTERN_3:
920a14b2 2703 if (IS_CHERRYVIEW(dev_priv)) {
7b13b58a
VS		 2704 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2705 } else {
8b0878a0 2706 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
7b13b58a
VS		 2707 *DP |= DP_LINK_TRAIN_PAT_2;
2708 }
2709 break;
2710 }
2711 }
2712}
2713
85cb48a1
ML		 2714static void intel_dp_enable_port(struct intel_dp *intel_dp,
2715 struct intel_crtc_state *old_crtc_state)
7b13b58a
VS		 2716{
2717 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 2718 struct drm_i915_private *dev_priv = to_i915(dev);
7b13b58a 2719
7b13b58a 2720 /* enable with pattern 1 (as per spec) */
7b13b58a 2721
8b0878a0 2722 intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1);
7b713f50
VS		 2723
2724 /*
2725 * Magic for VLV/CHV. We _must_ first set up the register
2726 * without actually enabling the port, and then do another
2727 * write to enable the port. Otherwise link training will
2728 * fail when the power sequencer is freshly used for this port.
2729 */
2730 intel_dp->DP |= DP_PORT_EN;
85cb48a1 2731 if (old_crtc_state->has_audio)
6fec7662 2732 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
7b713f50
VS		 2733
2734 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2735 POSTING_READ(intel_dp->output_reg);
580d3811
VS		 2736}
2737
85cb48a1
ML		 2738static void intel_enable_dp(struct intel_encoder *encoder,
2739 struct intel_crtc_state *pipe_config)
d240f20f 2740{
e8cb4558
DV		 2741 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2742 struct drm_device *dev = encoder->base.dev;
fac5e23e 2743 struct drm_i915_private *dev_priv = to_i915(dev);
c1dec79a 2744 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
e8cb4558 2745 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
d6fbdd15 2746 enum pipe pipe = crtc->pipe;
5d613501 2747
0c33d8d7
DV		 2748 if (WARN_ON(dp_reg & DP_PORT_EN))
2749 return;
5d613501 2750
093e3f13
VS		 2751 pps_lock(intel_dp);
2752
920a14b2 2753 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
093e3f13
VS		 2754 vlv_init_panel_power_sequencer(intel_dp);
2755
85cb48a1 2756 intel_dp_enable_port(intel_dp, pipe_config);
093e3f13
VS		 2757
2758 edp_panel_vdd_on(intel_dp);
2759 edp_panel_on(intel_dp);
2760 edp_panel_vdd_off(intel_dp, true);
2761
2762 pps_unlock(intel_dp);
2763
920a14b2 2764 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
e0fce78f
VS		 2765 unsigned int lane_mask = 0x0;
2766
920a14b2 2767 if (IS_CHERRYVIEW(dev_priv))
85cb48a1 2768 lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
e0fce78f 2769
9b6de0a1
VS		 2770 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
2771 lane_mask);
e0fce78f 2772 }
61234fa5 2773
f01eca2e 2774 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 2775 intel_dp_start_link_train(intel_dp);
3ab9c637 2776 intel_dp_stop_link_train(intel_dp);
c1dec79a 2777
85cb48a1 2778 if (pipe_config->has_audio) {
c1dec79a 2779 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
d6fbdd15 2780 pipe_name(pipe));
c1dec79a
JN		 2781 intel_audio_codec_enable(encoder);
2782 }
ab1f90f9 2783}
89b667f8 2784
fd6bbda9
ML		 2785static void g4x_enable_dp(struct intel_encoder *encoder,
2786 struct intel_crtc_state *pipe_config,
2787 struct drm_connector_state *conn_state)
ecff4f3b 2788{
828f5c6e
JN		 2789 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2790
85cb48a1 2791 intel_enable_dp(encoder, pipe_config);
4be73780 2792 intel_edp_backlight_on(intel_dp);
ab1f90f9 2793}
89b667f8 2794
fd6bbda9
ML		 2795static void vlv_enable_dp(struct intel_encoder *encoder,
2796 struct intel_crtc_state *pipe_config,
2797 struct drm_connector_state *conn_state)
ab1f90f9 2798{
828f5c6e
JN		 2799 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2800
4be73780 2801 intel_edp_backlight_on(intel_dp);
b32c6f48 2802 intel_psr_enable(intel_dp);
d240f20f
JB		 2803}
2804
fd6bbda9
ML		 2805static void g4x_pre_enable_dp(struct intel_encoder *encoder,
2806 struct intel_crtc_state *pipe_config,
2807 struct drm_connector_state *conn_state)
ab1f90f9
JN		 2808{
2809 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
d6fbdd15 2810 enum port port = dp_to_dig_port(intel_dp)->port;
ab1f90f9 2811
85cb48a1 2812 intel_dp_prepare(encoder, pipe_config);
8ac33ed3 2813
d41f1efb 2814 /* Only ilk+ has port A */
abfce949 2815 if (port == PORT_A)
85cb48a1 2816 ironlake_edp_pll_on(intel_dp, pipe_config);
ab1f90f9
JN		 2817}
2818
83b84597
VS		 2819static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2820{
2821 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
fac5e23e 2822 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
83b84597 2823 enum pipe pipe = intel_dp->pps_pipe;
44cb734c 2824 i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
83b84597
VS		 2825
2826 edp_panel_vdd_off_sync(intel_dp);
2827
2828 /*
2829 * VLV seems to get confused when multiple power seqeuencers
2830 * have the same port selected (even if only one has power/vdd
2831 * enabled). The failure manifests as vlv_wait_port_ready() failing
2832 * CHV on the other hand doesn't seem to mind having the same port
2833 * selected in multiple power seqeuencers, but let's clear the
2834 * port select always when logically disconnecting a power sequencer
2835 * from a port.
2836 */
2837 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2838 pipe_name(pipe), port_name(intel_dig_port->port));
2839 I915_WRITE(pp_on_reg, 0);
2840 POSTING_READ(pp_on_reg);
2841
2842 intel_dp->pps_pipe = INVALID_PIPE;
2843}
2844
a4a5d2f8
VS		 2845static void vlv_steal_power_sequencer(struct drm_device *dev,
2846 enum pipe pipe)
2847{
fac5e23e 2848 struct drm_i915_private *dev_priv = to_i915(dev);
a4a5d2f8
VS		 2849 struct intel_encoder *encoder;
2850
2851 lockdep_assert_held(&dev_priv->pps_mutex);
2852
ac3c12e4
VS		 2853 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2854 return;
2855
19c8054c 2856 for_each_intel_encoder(dev, encoder) {
a4a5d2f8 2857 struct intel_dp *intel_dp;
773538e8 2858 enum port port;
a4a5d2f8
VS		 2859
2860 if (encoder->type != INTEL_OUTPUT_EDP)
2861 continue;
2862
2863 intel_dp = enc_to_intel_dp(&encoder->base);
773538e8 2864 port = dp_to_dig_port(intel_dp)->port;
a4a5d2f8
VS		 2865
2866 if (intel_dp->pps_pipe != pipe)
2867 continue;
2868
2869 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
773538e8 2870 pipe_name(pipe), port_name(port));
a4a5d2f8 2871
e02f9a06 2872 WARN(encoder->base.crtc,
034e43c6
VS		 2873 "stealing pipe %c power sequencer from active eDP port %c\n",
2874 pipe_name(pipe), port_name(port));
a4a5d2f8 2875
a4a5d2f8 2876 /* make sure vdd is off before we steal it */
83b84597 2877 vlv_detach_power_sequencer(intel_dp);
a4a5d2f8
VS		 2878 }
2879}
2880
2881static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2882{
2883 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2884 struct intel_encoder *encoder = &intel_dig_port->base;
2885 struct drm_device *dev = encoder->base.dev;
fac5e23e 2886 struct drm_i915_private *dev_priv = to_i915(dev);
a4a5d2f8 2887 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
a4a5d2f8
VS		 2888
2889 lockdep_assert_held(&dev_priv->pps_mutex);
2890
093e3f13
VS		 2891 if (!is_edp(intel_dp))
2892 return;
2893
a4a5d2f8
VS		 2894 if (intel_dp->pps_pipe == crtc->pipe)
2895 return;
2896
2897 /*
2898 * If another power sequencer was being used on this
2899 * port previously make sure to turn off vdd there while
2900 * we still have control of it.
2901 */
2902 if (intel_dp->pps_pipe != INVALID_PIPE)
83b84597 2903 vlv_detach_power_sequencer(intel_dp);
a4a5d2f8
VS		 2904
2905 /*
2906 * We may be stealing the power
2907 * sequencer from another port.
2908 */
2909 vlv_steal_power_sequencer(dev, crtc->pipe);
2910
2911 /* now it's all ours */
2912 intel_dp->pps_pipe = crtc->pipe;
2913
2914 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2915 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2916
2917 /* init power sequencer on this pipe and port */
36b5f425
VS		 2918 intel_dp_init_panel_power_sequencer(dev, intel_dp);
2919 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8
VS		 2920}
2921
fd6bbda9
ML		 2922static void vlv_pre_enable_dp(struct intel_encoder *encoder,
2923 struct intel_crtc_state *pipe_config,
2924 struct drm_connector_state *conn_state)
a4fc5ed6 2925{
5f68c275 2926 vlv_phy_pre_encoder_enable(encoder);
ab1f90f9 2927
85cb48a1 2928 intel_enable_dp(encoder, pipe_config);
89b667f8
JB		 2929}
2930
fd6bbda9
ML		 2931static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder,
2932 struct intel_crtc_state *pipe_config,
2933 struct drm_connector_state *conn_state)
89b667f8 2934{
85cb48a1 2935 intel_dp_prepare(encoder, pipe_config);
8ac33ed3 2936
6da2e616 2937 vlv_phy_pre_pll_enable(encoder);
a4fc5ed6
KP		 2938}
2939
fd6bbda9
ML		 2940static void chv_pre_enable_dp(struct intel_encoder *encoder,
2941 struct intel_crtc_state *pipe_config,
2942 struct drm_connector_state *conn_state)
e4a1d846 2943{
e7d2a717 2944 chv_phy_pre_encoder_enable(encoder);
e4a1d846 2945
85cb48a1 2946 intel_enable_dp(encoder, pipe_config);
b0b33846
VS		 2947
2948 /* Second common lane will stay alive on its own now */
e7d2a717 2949 chv_phy_release_cl2_override(encoder);
e4a1d846
CML		 2950}
2951
fd6bbda9
ML		 2952static void chv_dp_pre_pll_enable(struct intel_encoder *encoder,
2953 struct intel_crtc_state *pipe_config,
2954 struct drm_connector_state *conn_state)
9197c88b 2955{
85cb48a1 2956 intel_dp_prepare(encoder, pipe_config);
625695f8 2957
419b1b7a 2958 chv_phy_pre_pll_enable(encoder);
9197c88b
VS		 2959}
2960
fd6bbda9
ML		 2961static void chv_dp_post_pll_disable(struct intel_encoder *encoder,
2962 struct intel_crtc_state *pipe_config,
2963 struct drm_connector_state *conn_state)
d6db995f 2964{
204970b5 2965 chv_phy_post_pll_disable(encoder);
d6db995f
VS		 2966}
2967
a4fc5ed6
KP		 2968/*
2969 * Fetch AUX CH registers 0x202 - 0x207 which contain
2970 * link status information
2971 */
94223d04 2972bool
93f62dad 2973intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 2974{
9f085ebb
L		 2975 return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
2976 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 2977}
2978
1100244e 2979/* These are source-specific values. */
94223d04 2980uint8_t
1a2eb460 2981intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 2982{
30add22d 2983 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 2984 struct drm_i915_private *dev_priv = to_i915(dev);
bc7d38a4 2985 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2986
e2d214ae 2987 if (IS_BROXTON(dev_priv))
9314726b
VK		 2988 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2989 else if (INTEL_INFO(dev)->gen >= 9) {
06411f08 2990 if (dev_priv->vbt.edp.low_vswing && port == PORT_A)
7ad14a29 2991 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
5a9d1f1a 2992 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
920a14b2 2993 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
bd60018a 2994 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
5db94019 2995 else if (IS_GEN7(dev_priv) && port == PORT_A)
bd60018a 2996 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
6e266956 2997 else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
bd60018a 2998 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
1a2eb460 2999 else
bd60018a 3000 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
1a2eb460
KP		 3001}
3002
94223d04 3003uint8_t
1a2eb460
KP		 3004intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
3005{
8652744b 3006 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
bc7d38a4 3007 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 3008
8652744b 3009 if (INTEL_GEN(dev_priv) >= 9) {
5a9d1f1a
DL		 3010 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3011 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3012 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3013 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3014 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3015 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3016 return DP_TRAIN_PRE_EMPH_LEVEL_1;
7ad14a29
SJ		 3017 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3018 return DP_TRAIN_PRE_EMPH_LEVEL_0;
5a9d1f1a
DL		 3019 default:
3020 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3021 }
8652744b 3022 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
d6c0d722 3023 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 3024 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3025 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3026 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3027 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3028 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3029 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3030 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
d6c0d722 3031 default:
bd60018a 3032 return DP_TRAIN_PRE_EMPH_LEVEL_0;
d6c0d722 3033 }
8652744b 3034 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
e2fa6fba 3035 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 3036 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3037 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3038 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3039 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3040 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3041 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3042 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba 3043 default:
bd60018a 3044 return DP_TRAIN_PRE_EMPH_LEVEL_0;
e2fa6fba 3045 }
8652744b 3046 } else if (IS_GEN7(dev_priv) && port == PORT_A) {
1a2eb460 3047 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 3048 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3049 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3050 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3051 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3052 return DP_TRAIN_PRE_EMPH_LEVEL_1;
1a2eb460 3053 default:
bd60018a 3054 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460
KP		 3055 }
3056 } else {
3057 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 3058 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3059 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3060 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3061 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3062 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3063 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3064 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
1a2eb460 3065 default:
bd60018a 3066 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460 3067 }
a4fc5ed6
KP		 3068 }
3069}
3070
5829975c 3071static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
e2fa6fba 3072{
53d98725 3073 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
e2fa6fba
P		 3074 unsigned long demph_reg_value, preemph_reg_value,
3075 uniqtranscale_reg_value;
3076 uint8_t train_set = intel_dp->train_set[0];
e2fa6fba
P		 3077
3078 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3079 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e2fa6fba
P		 3080 preemph_reg_value = 0x0004000;
3081 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3082 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3083 demph_reg_value = 0x2B405555;
3084 uniqtranscale_reg_value = 0x552AB83A;
3085 break;
bd60018a 3086 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3087 demph_reg_value = 0x2B404040;
3088 uniqtranscale_reg_value = 0x5548B83A;
3089 break;
bd60018a 3090 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 3091 demph_reg_value = 0x2B245555;
3092 uniqtranscale_reg_value = 0x5560B83A;
3093 break;
bd60018a 3094 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba
P		 3095 demph_reg_value = 0x2B405555;
3096 uniqtranscale_reg_value = 0x5598DA3A;
3097 break;
3098 default:
3099 return 0;
3100 }
3101 break;
bd60018a 3102 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e2fa6fba
P		 3103 preemph_reg_value = 0x0002000;
3104 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3105 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3106 demph_reg_value = 0x2B404040;
3107 uniqtranscale_reg_value = 0x5552B83A;
3108 break;
bd60018a 3109 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3110 demph_reg_value = 0x2B404848;
3111 uniqtranscale_reg_value = 0x5580B83A;
3112 break;
bd60018a 3113 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 3114 demph_reg_value = 0x2B404040;
3115 uniqtranscale_reg_value = 0x55ADDA3A;
3116 break;
3117 default:
3118 return 0;
3119 }
3120 break;
bd60018a 3121 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e2fa6fba
P		 3122 preemph_reg_value = 0x0000000;
3123 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3124 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3125 demph_reg_value = 0x2B305555;
3126 uniqtranscale_reg_value = 0x5570B83A;
3127 break;
bd60018a 3128 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3129 demph_reg_value = 0x2B2B4040;
3130 uniqtranscale_reg_value = 0x55ADDA3A;
3131 break;
3132 default:
3133 return 0;
3134 }
3135 break;
bd60018a 3136 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e2fa6fba
P		 3137 preemph_reg_value = 0x0006000;
3138 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3139 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3140 demph_reg_value = 0x1B405555;
3141 uniqtranscale_reg_value = 0x55ADDA3A;
3142 break;
3143 default:
3144 return 0;
3145 }
3146 break;
3147 default:
3148 return 0;
3149 }
3150
53d98725
ACO		 3151 vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
3152 uniqtranscale_reg_value, 0);
e2fa6fba
P		 3153
3154 return 0;
3155}
3156
5829975c 3157static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
e4a1d846 3158{
b7fa22d8
ACO		 3159 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3160 u32 deemph_reg_value, margin_reg_value;
3161 bool uniq_trans_scale = false;
e4a1d846 3162 uint8_t train_set = intel_dp->train_set[0];
e4a1d846
CML		 3163
3164 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3165 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e4a1d846 3166 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3167 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3168 deemph_reg_value = 128;
3169 margin_reg_value = 52;
3170 break;
bd60018a 3171 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3172 deemph_reg_value = 128;
3173 margin_reg_value = 77;
3174 break;
bd60018a 3175 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3176 deemph_reg_value = 128;
3177 margin_reg_value = 102;
3178 break;
bd60018a 3179 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e4a1d846
CML		 3180 deemph_reg_value = 128;
3181 margin_reg_value = 154;
b7fa22d8 3182 uniq_trans_scale = true;
e4a1d846
CML		 3183 break;
3184 default:
3185 return 0;
3186 }
3187 break;
bd60018a 3188 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e4a1d846 3189 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3190 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3191 deemph_reg_value = 85;
3192 margin_reg_value = 78;
3193 break;
bd60018a 3194 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3195 deemph_reg_value = 85;
3196 margin_reg_value = 116;
3197 break;
bd60018a 3198 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3199 deemph_reg_value = 85;
3200 margin_reg_value = 154;
3201 break;
3202 default:
3203 return 0;
3204 }
3205 break;
bd60018a 3206 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e4a1d846 3207 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3208 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3209 deemph_reg_value = 64;
3210 margin_reg_value = 104;
3211 break;
bd60018a 3212 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3213 deemph_reg_value = 64;
3214 margin_reg_value = 154;
3215 break;
3216 default:
3217 return 0;
3218 }
3219 break;
bd60018a 3220 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e4a1d846 3221 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3222 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3223 deemph_reg_value = 43;
3224 margin_reg_value = 154;
3225 break;
3226 default:
3227 return 0;
3228 }
3229 break;
3230 default:
3231 return 0;
3232 }
3233
b7fa22d8
ACO		 3234 chv_set_phy_signal_level(encoder, deemph_reg_value,
3235 margin_reg_value, uniq_trans_scale);
e4a1d846
CML		 3236
3237 return 0;
3238}
3239
a4fc5ed6 3240static uint32_t
5829975c 3241gen4_signal_levels(uint8_t train_set)
a4fc5ed6 3242{
3cf2efb1 3243 uint32_t signal_levels = 0;
a4fc5ed6 3244
3cf2efb1 3245 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3246 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
a4fc5ed6
KP		 3247 default:
3248 signal_levels |= DP_VOLTAGE_0_4;
3249 break;
bd60018a 3250 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
a4fc5ed6
KP		 3251 signal_levels |= DP_VOLTAGE_0_6;
3252 break;
bd60018a 3253 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
a4fc5ed6
KP		 3254 signal_levels |= DP_VOLTAGE_0_8;
3255 break;
bd60018a 3256 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
a4fc5ed6
KP		 3257 signal_levels |= DP_VOLTAGE_1_2;
3258 break;
3259 }
3cf2efb1 3260 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3261 case DP_TRAIN_PRE_EMPH_LEVEL_0:
a4fc5ed6
KP		 3262 default:
3263 signal_levels |= DP_PRE_EMPHASIS_0;
3264 break;
bd60018a 3265 case DP_TRAIN_PRE_EMPH_LEVEL_1:
a4fc5ed6
KP		 3266 signal_levels |= DP_PRE_EMPHASIS_3_5;
3267 break;
bd60018a 3268 case DP_TRAIN_PRE_EMPH_LEVEL_2:
a4fc5ed6
KP		 3269 signal_levels |= DP_PRE_EMPHASIS_6;
3270 break;
bd60018a 3271 case DP_TRAIN_PRE_EMPH_LEVEL_3:
a4fc5ed6
KP		 3272 signal_levels |= DP_PRE_EMPHASIS_9_5;
3273 break;
3274 }
3275 return signal_levels;
3276}
3277
e3421a18
ZW		 3278/* Gen6's DP voltage swing and pre-emphasis control */
3279static uint32_t
5829975c 3280gen6_edp_signal_levels(uint8_t train_set)
e3421a18 3281{
3c5a62b5
YL		 3282 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3283 DP_TRAIN_PRE_EMPHASIS_MASK);
3284 switch (signal_levels) {
bd60018a
SJ		 3285 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3286 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3287 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
bd60018a 3288 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3289 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
bd60018a
SJ		 3290 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3291 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3c5a62b5 3292 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
bd60018a
SJ		 3293 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3294 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3295 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
bd60018a
SJ		 3296 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3297 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3298 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 3299 default:
3c5a62b5
YL		 3300 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3301 "0x%x\n", signal_levels);
3302 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 3303 }
3304}
3305
1a2eb460
KP		 3306/* Gen7's DP voltage swing and pre-emphasis control */
3307static uint32_t
5829975c 3308gen7_edp_signal_levels(uint8_t train_set)
1a2eb460
KP		 3309{
3310 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3311 DP_TRAIN_PRE_EMPHASIS_MASK);
3312 switch (signal_levels) {
bd60018a 3313 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3314 return EDP_LINK_TRAIN_400MV_0DB_IVB;
bd60018a 3315 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460 3316 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
bd60018a 3317 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1a2eb460
KP		 3318 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3319
bd60018a 3320 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3321 return EDP_LINK_TRAIN_600MV_0DB_IVB;
bd60018a 3322 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3323 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3324
bd60018a 3325 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3326 return EDP_LINK_TRAIN_800MV_0DB_IVB;
bd60018a 3327 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3328 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3329
3330 default:
3331 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3332 "0x%x\n", signal_levels);
3333 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3334 }
3335}
3336
94223d04 3337void
f4eb692e 3338intel_dp_set_signal_levels(struct intel_dp *intel_dp)
f0a3424e
PZ		 3339{
3340 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3341 enum port port = intel_dig_port->port;
f0a3424e 3342 struct drm_device *dev = intel_dig_port->base.base.dev;
b905a915 3343 struct drm_i915_private *dev_priv = to_i915(dev);
f8896f5d 3344 uint32_t signal_levels, mask = 0;
f0a3424e
PZ		 3345 uint8_t train_set = intel_dp->train_set[0];
3346
4f8036a2 3347 if (HAS_DDI(dev_priv)) {
f8896f5d
DW		 3348 signal_levels = ddi_signal_levels(intel_dp);
3349
e2d214ae 3350 if (IS_BROXTON(dev_priv))
f8896f5d
DW		 3351 signal_levels = 0;
3352 else
3353 mask = DDI_BUF_EMP_MASK;
920a14b2 3354 } else if (IS_CHERRYVIEW(dev_priv)) {
5829975c 3355 signal_levels = chv_signal_levels(intel_dp);
11a914c2 3356 } else if (IS_VALLEYVIEW(dev_priv)) {
5829975c 3357 signal_levels = vlv_signal_levels(intel_dp);
5db94019 3358 } else if (IS_GEN7(dev_priv) && port == PORT_A) {
5829975c 3359 signal_levels = gen7_edp_signal_levels(train_set);
f0a3424e 3360 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
5db94019 3361 } else if (IS_GEN6(dev_priv) && port == PORT_A) {
5829975c 3362 signal_levels = gen6_edp_signal_levels(train_set);
f0a3424e
PZ		 3363 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3364 } else {
5829975c 3365 signal_levels = gen4_signal_levels(train_set);
f0a3424e
PZ		 3366 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3367 }
3368
96fb9f9b
VK		 3369 if (mask)
3370 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3371
3372 DRM_DEBUG_KMS("Using vswing level %d\n",
3373 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3374 DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3375 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3376 DP_TRAIN_PRE_EMPHASIS_SHIFT);
f0a3424e 3377
f4eb692e 3378 intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
b905a915
ACO		 3379
3380 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3381 POSTING_READ(intel_dp->output_reg);
f0a3424e
PZ		 3382}
3383
94223d04 3384void
e9c176d5
ACO		 3385intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3386 uint8_t dp_train_pat)
a4fc5ed6 3387{
174edf1f 3388 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
90a6b7b0
VS		 3389 struct drm_i915_private *dev_priv =
3390 to_i915(intel_dig_port->base.base.dev);
a4fc5ed6 3391
f4eb692e 3392 _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
47ea7542 3393
f4eb692e 3394 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
ea5b213a 3395 POSTING_READ(intel_dp->output_reg);
e9c176d5
ACO		 3396}
3397
94223d04 3398void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3ab9c637
ID		 3399{
3400 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3401 struct drm_device *dev = intel_dig_port->base.base.dev;
fac5e23e 3402 struct drm_i915_private *dev_priv = to_i915(dev);
3ab9c637
ID		 3403 enum port port = intel_dig_port->port;
3404 uint32_t val;
3405
4f8036a2 3406 if (!HAS_DDI(dev_priv))
3ab9c637
ID		 3407 return;
3408
3409 val = I915_READ(DP_TP_CTL(port));
3410 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3411 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3412 I915_WRITE(DP_TP_CTL(port), val);
3413
3414 /*
3415 * On PORT_A we can have only eDP in SST mode. There the only reason
3416 * we need to set idle transmission mode is to work around a HW issue
3417 * where we enable the pipe while not in idle link-training mode.
3418 * In this case there is requirement to wait for a minimum number of
3419 * idle patterns to be sent.
3420 */
3421 if (port == PORT_A)
3422 return;
3423
a767017f
CW		 3424 if (intel_wait_for_register(dev_priv,DP_TP_STATUS(port),
3425 DP_TP_STATUS_IDLE_DONE,
3426 DP_TP_STATUS_IDLE_DONE,
3427 1))
3ab9c637
ID		 3428 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3429}
3430
a4fc5ed6 3431static void
ea5b213a 3432intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 3433{
da63a9f2 3434 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1612c8bd 3435 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
bc7d38a4 3436 enum port port = intel_dig_port->port;
da63a9f2 3437 struct drm_device *dev = intel_dig_port->base.base.dev;
fac5e23e 3438 struct drm_i915_private *dev_priv = to_i915(dev);
ea5b213a 3439 uint32_t DP = intel_dp->DP;
a4fc5ed6 3440
4f8036a2 3441 if (WARN_ON(HAS_DDI(dev_priv)))
c19b0669
PZ		 3442 return;
3443
0c33d8d7 3444 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 3445 return;
3446
28c97730 3447 DRM_DEBUG_KMS("\n");
32f9d658 3448
5db94019 3449 if ((IS_GEN7(dev_priv) && port == PORT_A) ||
6e266956 3450 (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
e3421a18 3451 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1612c8bd 3452 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
e3421a18 3453 } else {
920a14b2 3454 if (IS_CHERRYVIEW(dev_priv))
aad3d14d
VS		 3455 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3456 else
3457 DP &= ~DP_LINK_TRAIN_MASK;
1612c8bd 3458 DP |= DP_LINK_TRAIN_PAT_IDLE;
e3421a18 3459 }
1612c8bd 3460 I915_WRITE(intel_dp->output_reg, DP);
fe255d00 3461 POSTING_READ(intel_dp->output_reg);
5eb08b69 3462
1612c8bd
VS		 3463 DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3464 I915_WRITE(intel_dp->output_reg, DP);
3465 POSTING_READ(intel_dp->output_reg);
3466
3467 /*
3468 * HW workaround for IBX, we need to move the port
3469 * to transcoder A after disabling it to allow the
3470 * matching HDMI port to be enabled on transcoder A.
3471 */
6e266956 3472 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
0c241d5b
VS		 3473 /*
3474 * We get CPU/PCH FIFO underruns on the other pipe when
3475 * doing the workaround. Sweep them under the rug.
3476 */
3477 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3478 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3479
1612c8bd
VS		 3480 /* always enable with pattern 1 (as per spec) */
3481 DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);
3482 DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;
3483 I915_WRITE(intel_dp->output_reg, DP);
3484 POSTING_READ(intel_dp->output_reg);
3485
3486 DP &= ~DP_PORT_EN;
5bddd17f 3487 I915_WRITE(intel_dp->output_reg, DP);
0ca09685 3488 POSTING_READ(intel_dp->output_reg);
0c241d5b 3489
91c8a326 3490 intel_wait_for_vblank_if_active(&dev_priv->drm, PIPE_A);
0c241d5b
VS		 3491 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3492 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
5bddd17f
EA		 3493 }
3494
f01eca2e 3495 msleep(intel_dp->panel_power_down_delay);
6fec7662
VS		 3496
3497 intel_dp->DP = DP;
a4fc5ed6
KP		 3498}
3499
24e807e7 3500bool
fe5a66f9 3501intel_dp_read_dpcd(struct intel_dp *intel_dp)
92fd8fd1 3502{
9f085ebb
L		 3503 if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
3504 sizeof(intel_dp->dpcd)) < 0)
edb39244 3505 return false; /* aux transfer failed */
92fd8fd1 3506
a8e98153 3507 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
577c7a50 3508
fe5a66f9
VS		 3509 return intel_dp->dpcd[DP_DPCD_REV] != 0;
3510}
edb39244 3511
fe5a66f9
VS		 3512static bool
3513intel_edp_init_dpcd(struct intel_dp *intel_dp)
3514{
3515 struct drm_i915_private *dev_priv =
3516 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
30d9aa42 3517
fe5a66f9
VS		 3518 /* this function is meant to be called only once */
3519 WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0);
30d9aa42 3520
fe5a66f9 3521 if (!intel_dp_read_dpcd(intel_dp))
30d9aa42
SS		 3522 return false;
3523
fe5a66f9
VS		 3524 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3525 dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3526 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
474d1ec4 3527
fe5a66f9
VS		 3528 /* Check if the panel supports PSR */
3529 drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT,
3530 intel_dp->psr_dpcd,
3531 sizeof(intel_dp->psr_dpcd));
3532 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3533 dev_priv->psr.sink_support = true;
3534 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3535 }
86ee27b5 3536
fe5a66f9
VS		 3537 if (INTEL_GEN(dev_priv) >= 9 &&
3538 (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
3539 uint8_t frame_sync_cap;
3540
3541 dev_priv->psr.sink_support = true;
3542 drm_dp_dpcd_read(&intel_dp->aux,
3543 DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
3544 &frame_sync_cap, 1);
3545 dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
3546 /* PSR2 needs frame sync as well */
3547 dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
3548 DRM_DEBUG_KMS("PSR2 %s on sink",
3549 dev_priv->psr.psr2_support ? "supported" : "not supported");
50003939
JN		 3550 }
3551
fe5a66f9
VS		 3552 /* Read the eDP Display control capabilities registers */
3553 if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
3554 drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
f7170e2e
DC		 3555 intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
3556 sizeof(intel_dp->edp_dpcd))
fe5a66f9
VS		 3557 DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
3558 intel_dp->edp_dpcd);
06ea66b6 3559
fc0f8e25 3560 /* Intermediate frequency support */
fe5a66f9 3561 if (intel_dp->edp_dpcd[0] >= 0x03) { /* eDp v1.4 or higher */
94ca719e 3562 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
ea2d8a42
VS		 3563 int i;
3564
9f085ebb
L		 3565 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
3566 sink_rates, sizeof(sink_rates));
ea2d8a42 3567
94ca719e
VS		 3568 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3569 int val = le16_to_cpu(sink_rates[i]);
ea2d8a42
VS		 3570
3571 if (val == 0)
3572 break;
3573
af77b974
SJ		 3574 /* Value read is in kHz while drm clock is saved in deca-kHz */
3575 intel_dp->sink_rates[i] = (val * 200) / 10;
ea2d8a42 3576 }
94ca719e 3577 intel_dp->num_sink_rates = i;
fc0f8e25 3578 }
0336400e 3579
fe5a66f9
VS		 3580 return true;
3581}
3582
3583
3584static bool
3585intel_dp_get_dpcd(struct intel_dp *intel_dp)
3586{
3587 if (!intel_dp_read_dpcd(intel_dp))
3588 return false;
3589
3590 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT,
3591 &intel_dp->sink_count, 1) < 0)
3592 return false;
3593
3594 /*
3595 * Sink count can change between short pulse hpd hence
3596 * a member variable in intel_dp will track any changes
3597 * between short pulse interrupts.
3598 */
3599 intel_dp->sink_count = DP_GET_SINK_COUNT(intel_dp->sink_count);
3600
3601 /*
3602 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3603 * a dongle is present but no display. Unless we require to know
3604 * if a dongle is present or not, we don't need to update
3605 * downstream port information. So, an early return here saves
3606 * time from performing other operations which are not required.
3607 */
3608 if (!is_edp(intel_dp) && !intel_dp->sink_count)
3609 return false;
0336400e 3610
c726ad01 3611 if (!drm_dp_is_branch(intel_dp->dpcd))
edb39244
AJ		 3612 return true; /* native DP sink */
3613
3614 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3615 return true; /* no per-port downstream info */
3616
9f085ebb
L		 3617 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3618 intel_dp->downstream_ports,
3619 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 3620 return false; /* downstream port status fetch failed */
3621
3622 return true;
92fd8fd1
KP		 3623}
3624
0e32b39c 3625static bool
c4e3170a 3626intel_dp_can_mst(struct intel_dp *intel_dp)
0e32b39c
DA		 3627{
3628 u8 buf[1];
3629
7cc96139
NS		 3630 if (!i915.enable_dp_mst)
3631 return false;
3632
0e32b39c
DA		 3633 if (!intel_dp->can_mst)
3634 return false;
3635
3636 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3637 return false;
3638
c4e3170a
VS		 3639 if (drm_dp_dpcd_read(&intel_dp->aux, DP_MSTM_CAP, buf, 1) != 1)
3640 return false;
0e32b39c 3641
c4e3170a
VS		 3642 return buf[0] & DP_MST_CAP;
3643}
3644
3645static void
3646intel_dp_configure_mst(struct intel_dp *intel_dp)
3647{
3648 if (!i915.enable_dp_mst)
3649 return;
3650
3651 if (!intel_dp->can_mst)
3652 return;
3653
3654 intel_dp->is_mst = intel_dp_can_mst(intel_dp);
3655
3656 if (intel_dp->is_mst)
3657 DRM_DEBUG_KMS("Sink is MST capable\n");
3658 else
3659 DRM_DEBUG_KMS("Sink is not MST capable\n");
3660
3661 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
3662 intel_dp->is_mst);
0e32b39c
DA		 3663}
3664
e5a1cab5 3665static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp)
d2e216d0 3666{
082dcc7c 3667 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
d72f9d91 3668 struct drm_device *dev = dig_port->base.base.dev;
082dcc7c 3669 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
ad9dc91b 3670 u8 buf;
e5a1cab5 3671 int ret = 0;
c6297843
RV		 3672 int count = 0;
3673 int attempts = 10;
d2e216d0 3674
082dcc7c
RV		 3675 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) {
3676 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
e5a1cab5
RV		 3677 ret = -EIO;
3678 goto out;
4373f0f2
PZ		 3679 }
3680
082dcc7c 3681 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
e5a1cab5 3682 buf & ~DP_TEST_SINK_START) < 0) {
082dcc7c 3683 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
e5a1cab5
RV		 3684 ret = -EIO;
3685 goto out;
3686 }
d2e216d0 3687
c6297843
RV		 3688 do {
3689 intel_wait_for_vblank(dev, intel_crtc->pipe);
3690
3691 if (drm_dp_dpcd_readb(&intel_dp->aux,
3692 DP_TEST_SINK_MISC, &buf) < 0) {
3693 ret = -EIO;
3694 goto out;
3695 }
3696 count = buf & DP_TEST_COUNT_MASK;
3697 } while (--attempts && count);
3698
3699 if (attempts == 0) {
dc5a9037 3700 DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n");
c6297843
RV		 3701 ret = -ETIMEDOUT;
3702 }
3703
e5a1cab5 3704 out:
082dcc7c 3705 hsw_enable_ips(intel_crtc);
e5a1cab5 3706 return ret;
082dcc7c
RV		 3707}
3708
3709static int intel_dp_sink_crc_start(struct intel_dp *intel_dp)
3710{
3711 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
d72f9d91 3712 struct drm_device *dev = dig_port->base.base.dev;
082dcc7c
RV		 3713 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3714 u8 buf;
e5a1cab5
RV		 3715 int ret;
3716
082dcc7c
RV		 3717 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
3718 return -EIO;
3719
3720 if (!(buf & DP_TEST_CRC_SUPPORTED))
3721 return -ENOTTY;
3722
3723 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3724 return -EIO;
3725
6d8175da
RV		 3726 if (buf & DP_TEST_SINK_START) {
3727 ret = intel_dp_sink_crc_stop(intel_dp);
3728 if (ret)
3729 return ret;
3730 }
3731
082dcc7c 3732 hsw_disable_ips(intel_crtc);
1dda5f93 3733
9d1a1031 3734 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
082dcc7c
RV		 3735 buf | DP_TEST_SINK_START) < 0) {
3736 hsw_enable_ips(intel_crtc);
3737 return -EIO;
4373f0f2
PZ		 3738 }
3739
d72f9d91 3740 intel_wait_for_vblank(dev, intel_crtc->pipe);
082dcc7c
RV		 3741 return 0;
3742}
3743
3744int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3745{
3746 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3747 struct drm_device *dev = dig_port->base.base.dev;
3748 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3749 u8 buf;
621d4c76 3750 int count, ret;
082dcc7c 3751 int attempts = 6;
082dcc7c
RV		 3752
3753 ret = intel_dp_sink_crc_start(intel_dp);
3754 if (ret)
3755 return ret;
3756
ad9dc91b 3757 do {
621d4c76
RV		 3758 intel_wait_for_vblank(dev, intel_crtc->pipe);
3759
1dda5f93 3760 if (drm_dp_dpcd_readb(&intel_dp->aux,
4373f0f2
PZ		 3761 DP_TEST_SINK_MISC, &buf) < 0) {
3762 ret = -EIO;
afe0d67e 3763 goto stop;
4373f0f2 3764 }
621d4c76 3765 count = buf & DP_TEST_COUNT_MASK;
aabc95dc 3766
7e38eeff 3767 } while (--attempts && count == 0);
ad9dc91b
RV		 3768
3769 if (attempts == 0) {
7e38eeff
RV		 3770 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
3771 ret = -ETIMEDOUT;
3772 goto stop;
3773 }
3774
3775 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
3776 ret = -EIO;
3777 goto stop;
ad9dc91b 3778 }
d2e216d0 3779
afe0d67e 3780stop:
082dcc7c 3781 intel_dp_sink_crc_stop(intel_dp);
4373f0f2 3782 return ret;
d2e216d0
RV		 3783}
3784
a60f0e38
JB		 3785static bool
3786intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3787{
9f085ebb 3788 return drm_dp_dpcd_read(&intel_dp->aux,
9d1a1031
JN		 3789 DP_DEVICE_SERVICE_IRQ_VECTOR,
3790 sink_irq_vector, 1) == 1;
a60f0e38
JB		 3791}
3792
0e32b39c
DA		 3793static bool
3794intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3795{
3796 int ret;
3797
9f085ebb 3798 ret = drm_dp_dpcd_read(&intel_dp->aux,
0e32b39c
DA		 3799 DP_SINK_COUNT_ESI,
3800 sink_irq_vector, 14);
3801 if (ret != 14)
3802 return false;
3803
3804 return true;
3805}
3806
c5d5ab7a
TP		 3807static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
3808{
3809 uint8_t test_result = DP_TEST_ACK;
3810 return test_result;
3811}
3812
3813static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
3814{
3815 uint8_t test_result = DP_TEST_NAK;
3816 return test_result;
3817}
3818
3819static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
a60f0e38 3820{
c5d5ab7a 3821 uint8_t test_result = DP_TEST_NAK;
559be30c
TP		 3822 struct intel_connector *intel_connector = intel_dp->attached_connector;
3823 struct drm_connector *connector = &intel_connector->base;
3824
3825 if (intel_connector->detect_edid == NULL ||
ac6f2e29 3826 connector->edid_corrupt ||
559be30c
TP		 3827 intel_dp->aux.i2c_defer_count > 6) {
3828 /* Check EDID read for NACKs, DEFERs and corruption
3829 * (DP CTS 1.2 Core r1.1)
3830 * 4.2.2.4 : Failed EDID read, I2C_NAK
3831 * 4.2.2.5 : Failed EDID read, I2C_DEFER
3832 * 4.2.2.6 : EDID corruption detected
3833 * Use failsafe mode for all cases
3834 */
3835 if (intel_dp->aux.i2c_nack_count > 0 ||
3836 intel_dp->aux.i2c_defer_count > 0)
3837 DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
3838 intel_dp->aux.i2c_nack_count,
3839 intel_dp->aux.i2c_defer_count);
3840 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE;
3841 } else {
f79b468e
TS		 3842 struct edid *block = intel_connector->detect_edid;
3843
3844 /* We have to write the checksum
3845 * of the last block read
3846 */
3847 block += intel_connector->detect_edid->extensions;
3848
559be30c
TP		 3849 if (!drm_dp_dpcd_write(&intel_dp->aux,
3850 DP_TEST_EDID_CHECKSUM,
f79b468e 3851 &block->checksum,
5a1cc655 3852 1))
559be30c
TP		 3853 DRM_DEBUG_KMS("Failed to write EDID checksum\n");
3854
3855 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
3856 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_STANDARD;
3857 }
3858
3859 /* Set test active flag here so userspace doesn't interrupt things */
3860 intel_dp->compliance_test_active = 1;
3861
c5d5ab7a
TP		 3862 return test_result;
3863}
3864
3865static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
a60f0e38 3866{
c5d5ab7a
TP		 3867 uint8_t test_result = DP_TEST_NAK;
3868 return test_result;
3869}
3870
3871static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
3872{
3873 uint8_t response = DP_TEST_NAK;
3874 uint8_t rxdata = 0;
3875 int status = 0;
3876
c5d5ab7a
TP		 3877 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1);
3878 if (status <= 0) {
3879 DRM_DEBUG_KMS("Could not read test request from sink\n");
3880 goto update_status;
3881 }
3882
3883 switch (rxdata) {
3884 case DP_TEST_LINK_TRAINING:
3885 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
3886 intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING;
3887 response = intel_dp_autotest_link_training(intel_dp);
3888 break;
3889 case DP_TEST_LINK_VIDEO_PATTERN:
3890 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
3891 intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN;
3892 response = intel_dp_autotest_video_pattern(intel_dp);
3893 break;
3894 case DP_TEST_LINK_EDID_READ:
3895 DRM_DEBUG_KMS("EDID test requested\n");
3896 intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ;
3897 response = intel_dp_autotest_edid(intel_dp);
3898 break;
3899 case DP_TEST_LINK_PHY_TEST_PATTERN:
3900 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
3901 intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN;
3902 response = intel_dp_autotest_phy_pattern(intel_dp);
3903 break;
3904 default:
3905 DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata);
3906 break;
3907 }
3908
3909update_status:
3910 status = drm_dp_dpcd_write(&intel_dp->aux,
3911 DP_TEST_RESPONSE,
3912 &response, 1);
3913 if (status <= 0)
3914 DRM_DEBUG_KMS("Could not write test response to sink\n");
a60f0e38
JB		 3915}
3916
0e32b39c
DA		 3917static int
3918intel_dp_check_mst_status(struct intel_dp *intel_dp)
3919{
3920 bool bret;
3921
3922 if (intel_dp->is_mst) {
3923 u8 esi[16] = { 0 };
3924 int ret = 0;
3925 int retry;
3926 bool handled;
3927 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3928go_again:
3929 if (bret == true) {
3930
3931 /* check link status - esi[10] = 0x200c */
19e0b4ca 3932 if (intel_dp->active_mst_links &&
901c2daf 3933 !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
0e32b39c
DA		 3934 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3935 intel_dp_start_link_train(intel_dp);
0e32b39c
DA		 3936 intel_dp_stop_link_train(intel_dp);
3937 }
3938
6f34cc39 3939 DRM_DEBUG_KMS("got esi %3ph\n", esi);
0e32b39c
DA		 3940 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3941
3942 if (handled) {
3943 for (retry = 0; retry < 3; retry++) {
3944 int wret;
3945 wret = drm_dp_dpcd_write(&intel_dp->aux,
3946 DP_SINK_COUNT_ESI+1,
3947 &esi[1], 3);
3948 if (wret == 3) {
3949 break;
3950 }
3951 }
3952
3953 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3954 if (bret == true) {
6f34cc39 3955 DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
0e32b39c
DA		 3956 goto go_again;
3957 }
3958 } else
3959 ret = 0;
3960
3961 return ret;
3962 } else {
3963 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3964 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3965 intel_dp->is_mst = false;
3966 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3967 /* send a hotplug event */
3968 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
3969 }
3970 }
3971 return -EINVAL;
3972}
3973
bfd02b3c
VS		 3974static void
3975intel_dp_retrain_link(struct intel_dp *intel_dp)
3976{
3977 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3978 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3979 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
3980
3981 /* Suppress underruns caused by re-training */
3982 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
3983 if (crtc->config->has_pch_encoder)
3984 intel_set_pch_fifo_underrun_reporting(dev_priv,
3985 intel_crtc_pch_transcoder(crtc), false);
3986
3987 intel_dp_start_link_train(intel_dp);
3988 intel_dp_stop_link_train(intel_dp);
3989
3990 /* Keep underrun reporting disabled until things are stable */
3991 intel_wait_for_vblank(&dev_priv->drm, crtc->pipe);
3992
3993 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
3994 if (crtc->config->has_pch_encoder)
3995 intel_set_pch_fifo_underrun_reporting(dev_priv,
3996 intel_crtc_pch_transcoder(crtc), true);
3997}
3998
5c9114d0
SS		 3999static void
4000intel_dp_check_link_status(struct intel_dp *intel_dp)
4001{
4002 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4003 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4004 u8 link_status[DP_LINK_STATUS_SIZE];
4005
4006 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
4007
4008 if (!intel_dp_get_link_status(intel_dp, link_status)) {
4009 DRM_ERROR("Failed to get link status\n");
4010 return;
4011 }
4012
4013 if (!intel_encoder->base.crtc)
4014 return;
4015
4016 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
4017 return;
4018
d4cb3fd9
MA		 4019 /* FIXME: we need to synchronize this sort of stuff with hardware
4020 * readout */
4021 if (WARN_ON_ONCE(!intel_dp->lane_count))
4022 return;
4023
5c9114d0
SS		 4024 /* if link training is requested we should perform it always */
4025 if ((intel_dp->compliance_test_type == DP_TEST_LINK_TRAINING) ||
4026 (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) {
4027 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4028 intel_encoder->base.name);
bfd02b3c
VS		 4029
4030 intel_dp_retrain_link(intel_dp);
5c9114d0
SS		 4031 }
4032}
4033
a4fc5ed6
KP		 4034/*
4035 * According to DP spec
4036 * 5.1.2:
4037 * 1. Read DPCD
4038 * 2. Configure link according to Receiver Capabilities
4039 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4040 * 4. Check link status on receipt of hot-plug interrupt
39ff747b
SS		 4041 *
4042 * intel_dp_short_pulse - handles short pulse interrupts
4043 * when full detection is not required.
4044 * Returns %true if short pulse is handled and full detection
4045 * is NOT required and %false otherwise.
a4fc5ed6 4046 */
39ff747b 4047static bool
5c9114d0 4048intel_dp_short_pulse(struct intel_dp *intel_dp)
a4fc5ed6 4049{
5b215bcf 4050 struct drm_device *dev = intel_dp_to_dev(intel_dp);
65fbb4e7 4051 u8 sink_irq_vector = 0;
39ff747b
SS		 4052 u8 old_sink_count = intel_dp->sink_count;
4053 bool ret;
5b215bcf 4054
4df6960e
SS		 4055 /*
4056 * Clearing compliance test variables to allow capturing
4057 * of values for next automated test request.
4058 */
4059 intel_dp->compliance_test_active = 0;
4060 intel_dp->compliance_test_type = 0;
4061 intel_dp->compliance_test_data = 0;
4062
39ff747b
SS		 4063 /*
4064 * Now read the DPCD to see if it's actually running
4065 * If the current value of sink count doesn't match with
4066 * the value that was stored earlier or dpcd read failed
4067 * we need to do full detection
4068 */
4069 ret = intel_dp_get_dpcd(intel_dp);
4070
4071 if ((old_sink_count != intel_dp->sink_count) || !ret) {
4072 /* No need to proceed if we are going to do full detect */
4073 return false;
59cd09e1
JB		 4074 }
4075
a60f0e38
JB		 4076 /* Try to read the source of the interrupt */
4077 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
65fbb4e7
VS		 4078 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
4079 sink_irq_vector != 0) {
a60f0e38 4080 /* Clear interrupt source */
9d1a1031
JN		 4081 drm_dp_dpcd_writeb(&intel_dp->aux,
4082 DP_DEVICE_SERVICE_IRQ_VECTOR,
4083 sink_irq_vector);
a60f0e38
JB		 4084
4085 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
09b1eb13 4086 DRM_DEBUG_DRIVER("Test request in short pulse not handled\n");
a60f0e38
JB		 4087 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4088 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4089 }
4090
5c9114d0
SS		 4091 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4092 intel_dp_check_link_status(intel_dp);
4093 drm_modeset_unlock(&dev->mode_config.connection_mutex);
39ff747b
SS		 4094
4095 return true;
a4fc5ed6 4096}
a4fc5ed6 4097
caf9ab24 4098/* XXX this is probably wrong for multiple downstream ports */
71ba9000 4099static enum drm_connector_status
26d61aad 4100intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 4101{
caf9ab24 4102 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 4103 uint8_t type;
4104
4105 if (!intel_dp_get_dpcd(intel_dp))
4106 return connector_status_disconnected;
4107
1034ce70
SS		 4108 if (is_edp(intel_dp))
4109 return connector_status_connected;
4110
caf9ab24 4111 /* if there's no downstream port, we're done */
c726ad01 4112 if (!drm_dp_is_branch(dpcd))
26d61aad 4113 return connector_status_connected;
caf9ab24
AJ		 4114
4115 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 4116 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4117 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
9d1a1031 4118
30d9aa42
SS		 4119 return intel_dp->sink_count ?
4120 connector_status_connected : connector_status_disconnected;
caf9ab24
AJ		 4121 }
4122
c4e3170a
VS		 4123 if (intel_dp_can_mst(intel_dp))
4124 return connector_status_connected;
4125
caf9ab24 4126 /* If no HPD, poke DDC gently */
0b99836f 4127 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 4128 return connector_status_connected;
caf9ab24
AJ		 4129
4130 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 4131 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4132 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4133 if (type == DP_DS_PORT_TYPE_VGA ||
4134 type == DP_DS_PORT_TYPE_NON_EDID)
4135 return connector_status_unknown;
4136 } else {
4137 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4138 DP_DWN_STRM_PORT_TYPE_MASK;
4139 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4140 type == DP_DWN_STRM_PORT_TYPE_OTHER)
4141 return connector_status_unknown;
4142 }
caf9ab24
AJ		 4143
4144 /* Anything else is out of spec, warn and ignore */
4145 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 4146 return connector_status_disconnected;
71ba9000
AJ		 4147}
4148
d410b56d
CW		 4149static enum drm_connector_status
4150edp_detect(struct intel_dp *intel_dp)
4151{
4152 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4153 enum drm_connector_status status;
4154
4155 status = intel_panel_detect(dev);
4156 if (status == connector_status_unknown)
4157 status = connector_status_connected;
4158
4159 return status;
4160}
4161
b93433cc
JN		 4162static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
4163 struct intel_digital_port *port)
5eb08b69 4164{
b93433cc 4165 u32 bit;
01cb9ea6 4166
0df53b77
JN		 4167 switch (port->port) {
4168 case PORT_A:
4169 return true;
4170 case PORT_B:
4171 bit = SDE_PORTB_HOTPLUG;
4172 break;
4173 case PORT_C:
4174 bit = SDE_PORTC_HOTPLUG;
4175 break;
4176 case PORT_D:
4177 bit = SDE_PORTD_HOTPLUG;
4178 break;
4179 default:
4180 MISSING_CASE(port->port);
4181 return false;
4182 }
4183
4184 return I915_READ(SDEISR) & bit;
4185}
4186
4187static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv,
4188 struct intel_digital_port *port)
4189{
4190 u32 bit;
4191
4192 switch (port->port) {
4193 case PORT_A:
4194 return true;
4195 case PORT_B:
4196 bit = SDE_PORTB_HOTPLUG_CPT;
4197 break;
4198 case PORT_C:
4199 bit = SDE_PORTC_HOTPLUG_CPT;
4200 break;
4201 case PORT_D:
4202 bit = SDE_PORTD_HOTPLUG_CPT;
4203 break;
a78695d3
JN		 4204 case PORT_E:
4205 bit = SDE_PORTE_HOTPLUG_SPT;
4206 break;
0df53b77
JN		 4207 default:
4208 MISSING_CASE(port->port);
4209 return false;
b93433cc 4210 }
1b469639 4211
b93433cc 4212 return I915_READ(SDEISR) & bit;
5eb08b69
ZW		 4213}
4214
7e66bcf2 4215static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv,
1d245987 4216 struct intel_digital_port *port)
a4fc5ed6 4217{
9642c81c 4218 u32 bit;
5eb08b69 4219
9642c81c
JN		 4220 switch (port->port) {
4221 case PORT_B:
4222 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4223 break;
4224 case PORT_C:
4225 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4226 break;
4227 case PORT_D:
4228 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4229 break;
4230 default:
4231 MISSING_CASE(port->port);
4232 return false;
4233 }
4234
4235 return I915_READ(PORT_HOTPLUG_STAT) & bit;
4236}
4237
0780cd36
VS		 4238static bool gm45_digital_port_connected(struct drm_i915_private *dev_priv,
4239 struct intel_digital_port *port)
9642c81c
JN		 4240{
4241 u32 bit;
4242
4243 switch (port->port) {
4244 case PORT_B:
0780cd36 4245 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
9642c81c
JN		 4246 break;
4247 case PORT_C:
0780cd36 4248 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
9642c81c
JN		 4249 break;
4250 case PORT_D:
0780cd36 4251 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
9642c81c
JN		 4252 break;
4253 default:
4254 MISSING_CASE(port->port);
4255 return false;
a4fc5ed6
KP		 4256 }
4257
1d245987 4258 return I915_READ(PORT_HOTPLUG_STAT) & bit;
2a592bec
DA		 4259}
4260
e464bfde 4261static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv,
e2ec35a5 4262 struct intel_digital_port *intel_dig_port)
e464bfde 4263{
e2ec35a5
SJ		 4264 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4265 enum port port;
e464bfde
JN		 4266 u32 bit;
4267
e2ec35a5
SJ		 4268 intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port);
4269 switch (port) {
e464bfde
JN		 4270 case PORT_A:
4271 bit = BXT_DE_PORT_HP_DDIA;
4272 break;
4273 case PORT_B:
4274 bit = BXT_DE_PORT_HP_DDIB;
4275 break;
4276 case PORT_C:
4277 bit = BXT_DE_PORT_HP_DDIC;
4278 break;
4279 default:
e2ec35a5 4280 MISSING_CASE(port);
e464bfde
JN		 4281 return false;
4282 }
4283
4284 return I915_READ(GEN8_DE_PORT_ISR) & bit;
4285}
4286
7e66bcf2
JN		 4287/*
4288 * intel_digital_port_connected - is the specified port connected?
4289 * @dev_priv: i915 private structure
4290 * @port: the port to test
4291 *
4292 * Return %true if @port is connected, %false otherwise.
4293 */
23f889bd 4294static bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
7e66bcf2
JN		 4295 struct intel_digital_port *port)
4296{
0df53b77 4297 if (HAS_PCH_IBX(dev_priv))
7e66bcf2 4298 return ibx_digital_port_connected(dev_priv, port);
22824fac 4299 else if (HAS_PCH_SPLIT(dev_priv))
0df53b77 4300 return cpt_digital_port_connected(dev_priv, port);
e464bfde
JN		 4301 else if (IS_BROXTON(dev_priv))
4302 return bxt_digital_port_connected(dev_priv, port);
0780cd36
VS		 4303 else if (IS_GM45(dev_priv))
4304 return gm45_digital_port_connected(dev_priv, port);
7e66bcf2
JN		 4305 else
4306 return g4x_digital_port_connected(dev_priv, port);
4307}
4308
8c241fef 4309static struct edid *
beb60608 4310intel_dp_get_edid(struct intel_dp *intel_dp)
8c241fef 4311{
beb60608 4312 struct intel_connector *intel_connector = intel_dp->attached_connector;
d6f24d0f 4313
9cd300e0
JN		 4314 /* use cached edid if we have one */
4315 if (intel_connector->edid) {
9cd300e0
JN		 4316 /* invalid edid */
4317 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 4318 return NULL;
4319
55e9edeb 4320 return drm_edid_duplicate(intel_connector->edid);
beb60608
CW		 4321 } else
4322 return drm_get_edid(&intel_connector->base,
4323 &intel_dp->aux.ddc);
4324}
8c241fef 4325
beb60608
CW		 4326static void
4327intel_dp_set_edid(struct intel_dp *intel_dp)
4328{
4329 struct intel_connector *intel_connector = intel_dp->attached_connector;
4330 struct edid *edid;
8c241fef 4331
f21a2198 4332 intel_dp_unset_edid(intel_dp);
beb60608
CW		 4333 edid = intel_dp_get_edid(intel_dp);
4334 intel_connector->detect_edid = edid;
4335
4336 if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4337 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4338 else
4339 intel_dp->has_audio = drm_detect_monitor_audio(edid);
8c241fef
KP		 4340}
4341
beb60608
CW		 4342static void
4343intel_dp_unset_edid(struct intel_dp *intel_dp)
8c241fef 4344{
beb60608 4345 struct intel_connector *intel_connector = intel_dp->attached_connector;
8c241fef 4346
beb60608
CW		 4347 kfree(intel_connector->detect_edid);
4348 intel_connector->detect_edid = NULL;
9cd300e0 4349
beb60608
CW		 4350 intel_dp->has_audio = false;
4351}
d6f24d0f 4352
5cb651a7 4353static enum drm_connector_status
f21a2198 4354intel_dp_long_pulse(struct intel_connector *intel_connector)
a9756bb5 4355{
f21a2198 4356 struct drm_connector *connector = &intel_connector->base;
a9756bb5 4357 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 4358 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4359 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 4360 struct drm_device *dev = connector->dev;
a9756bb5 4361 enum drm_connector_status status;
671dedd2 4362 enum intel_display_power_domain power_domain;
65fbb4e7 4363 u8 sink_irq_vector = 0;
a9756bb5 4364
25f78f58
VS		 4365 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4366 intel_display_power_get(to_i915(dev), power_domain);
a9756bb5 4367
d410b56d
CW		 4368 /* Can't disconnect eDP, but you can close the lid... */
4369 if (is_edp(intel_dp))
4370 status = edp_detect(intel_dp);
c555a81d
ACO		 4371 else if (intel_digital_port_connected(to_i915(dev),
4372 dp_to_dig_port(intel_dp)))
4373 status = intel_dp_detect_dpcd(intel_dp);
a9756bb5 4374 else
c555a81d
ACO		 4375 status = connector_status_disconnected;
4376
5cb651a7 4377 if (status == connector_status_disconnected) {
4df6960e
SS		 4378 intel_dp->compliance_test_active = 0;
4379 intel_dp->compliance_test_type = 0;
4380 intel_dp->compliance_test_data = 0;
4381
0e505a08 4382 if (intel_dp->is_mst) {
4383 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4384 intel_dp->is_mst,
4385 intel_dp->mst_mgr.mst_state);
4386 intel_dp->is_mst = false;
4387 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4388 intel_dp->is_mst);
4389 }
4390
c8c8fb33 4391 goto out;
4df6960e 4392 }
a9756bb5 4393
f21a2198 4394 if (intel_encoder->type != INTEL_OUTPUT_EDP)
cca0502b 4395 intel_encoder->type = INTEL_OUTPUT_DP;
f21a2198 4396
fe5a66f9
VS		 4397 DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
4398 yesno(intel_dp_source_supports_hbr2(intel_dp)),
4399 yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
4400
4401 intel_dp_print_rates(intel_dp);
4402
7b3fc170 4403 intel_dp_read_desc(intel_dp);
0e390a33 4404
c4e3170a
VS		 4405 intel_dp_configure_mst(intel_dp);
4406
4407 if (intel_dp->is_mst) {
f21a2198
SS		 4408 /*
4409 * If we are in MST mode then this connector
4410 * won't appear connected or have anything
4411 * with EDID on it
4412 */
0e32b39c
DA		 4413 status = connector_status_disconnected;
4414 goto out;
7d23e3c3
SS		 4415 } else if (connector->status == connector_status_connected) {
4416 /*
4417 * If display was connected already and is still connected
4418 * check links status, there has been known issues of
4419 * link loss triggerring long pulse!!!!
4420 */
4421 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4422 intel_dp_check_link_status(intel_dp);
4423 drm_modeset_unlock(&dev->mode_config.connection_mutex);
4424 goto out;
0e32b39c
DA		 4425 }
4426
4df6960e
SS		 4427 /*
4428 * Clearing NACK and defer counts to get their exact values
4429 * while reading EDID which are required by Compliance tests
4430 * 4.2.2.4 and 4.2.2.5
4431 */
4432 intel_dp->aux.i2c_nack_count = 0;
4433 intel_dp->aux.i2c_defer_count = 0;
4434
beb60608 4435 intel_dp_set_edid(intel_dp);
5cb651a7
VS		 4436 if (is_edp(intel_dp) || intel_connector->detect_edid)
4437 status = connector_status_connected;
7d23e3c3 4438 intel_dp->detect_done = true;
c8c8fb33 4439
09b1eb13
TP		 4440 /* Try to read the source of the interrupt */
4441 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
65fbb4e7
VS		 4442 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
4443 sink_irq_vector != 0) {
09b1eb13
TP		 4444 /* Clear interrupt source */
4445 drm_dp_dpcd_writeb(&intel_dp->aux,
4446 DP_DEVICE_SERVICE_IRQ_VECTOR,
4447 sink_irq_vector);
4448
4449 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4450 intel_dp_handle_test_request(intel_dp);
4451 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4452 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4453 }
4454
c8c8fb33 4455out:
5cb651a7 4456 if (status != connector_status_connected && !intel_dp->is_mst)
f21a2198 4457 intel_dp_unset_edid(intel_dp);
7d23e3c3 4458
25f78f58 4459 intel_display_power_put(to_i915(dev), power_domain);
5cb651a7 4460 return status;
f21a2198
SS		 4461}
4462
4463static enum drm_connector_status
4464intel_dp_detect(struct drm_connector *connector, bool force)
4465{
4466 struct intel_dp *intel_dp = intel_attached_dp(connector);
5cb651a7 4467 enum drm_connector_status status = connector->status;
f21a2198
SS		 4468
4469 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4470 connector->base.id, connector->name);
4471
7d23e3c3
SS		 4472 /* If full detect is not performed yet, do a full detect */
4473 if (!intel_dp->detect_done)
5cb651a7 4474 status = intel_dp_long_pulse(intel_dp->attached_connector);
7d23e3c3
SS		 4475
4476 intel_dp->detect_done = false;
f21a2198 4477
5cb651a7 4478 return status;
a4fc5ed6
KP		 4479}
4480
beb60608
CW		 4481static void
4482intel_dp_force(struct drm_connector *connector)
a4fc5ed6 4483{
df0e9248 4484 struct intel_dp *intel_dp = intel_attached_dp(connector);
beb60608 4485 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
25f78f58 4486 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
671dedd2 4487 enum intel_display_power_domain power_domain;
a4fc5ed6 4488
beb60608
CW		 4489 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4490 connector->base.id, connector->name);
4491 intel_dp_unset_edid(intel_dp);
a4fc5ed6 4492
beb60608
CW		 4493 if (connector->status != connector_status_connected)
4494 return;
671dedd2 4495
25f78f58
VS		 4496 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4497 intel_display_power_get(dev_priv, power_domain);
beb60608
CW		 4498
4499 intel_dp_set_edid(intel_dp);
4500
25f78f58 4501 intel_display_power_put(dev_priv, power_domain);
beb60608
CW		 4502
4503 if (intel_encoder->type != INTEL_OUTPUT_EDP)
cca0502b 4504 intel_encoder->type = INTEL_OUTPUT_DP;
beb60608
CW		 4505}
4506
4507static int intel_dp_get_modes(struct drm_connector *connector)
4508{
4509 struct intel_connector *intel_connector = to_intel_connector(connector);
4510 struct edid *edid;
4511
4512 edid = intel_connector->detect_edid;
4513 if (edid) {
4514 int ret = intel_connector_update_modes(connector, edid);
4515 if (ret)
4516 return ret;
4517 }
32f9d658 4518
f8779fda 4519 /* if eDP has no EDID, fall back to fixed mode */
beb60608
CW		 4520 if (is_edp(intel_attached_dp(connector)) &&
4521 intel_connector->panel.fixed_mode) {
f8779fda 4522 struct drm_display_mode *mode;
beb60608
CW		 4523
4524 mode = drm_mode_duplicate(connector->dev,
dd06f90e 4525 intel_connector->panel.fixed_mode);
f8779fda 4526 if (mode) {
32f9d658
ZW		 4527 drm_mode_probed_add(connector, mode);
4528 return 1;
4529 }
4530 }
beb60608 4531
32f9d658 4532 return 0;
a4fc5ed6
KP		 4533}
4534
1aad7ac0
CW		 4535static bool
4536intel_dp_detect_audio(struct drm_connector *connector)
4537{
1aad7ac0 4538 bool has_audio = false;
beb60608 4539 struct edid *edid;
1aad7ac0 4540
beb60608
CW		 4541 edid = to_intel_connector(connector)->detect_edid;
4542 if (edid)
1aad7ac0 4543 has_audio = drm_detect_monitor_audio(edid);
671dedd2 4544
1aad7ac0
CW		 4545 return has_audio;
4546}
4547
f684960e
CW		 4548static int
4549intel_dp_set_property(struct drm_connector *connector,
4550 struct drm_property *property,
4551 uint64_t val)
4552{
fac5e23e 4553 struct drm_i915_private *dev_priv = to_i915(connector->dev);
53b41837 4554 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 4555 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4556 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 4557 int ret;
4558
662595df 4559 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 4560 if (ret)
4561 return ret;
4562
3f43c48d 4563 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 4564 int i = val;
4565 bool has_audio;
4566
4567 if (i == intel_dp->force_audio)
f684960e
CW		 4568 return 0;
4569
1aad7ac0 4570 intel_dp->force_audio = i;
f684960e 4571
c3e5f67b 4572 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 4573 has_audio = intel_dp_detect_audio(connector);
4574 else
c3e5f67b 4575 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 4576
4577 if (has_audio == intel_dp->has_audio)
f684960e
CW		 4578 return 0;
4579
1aad7ac0 4580 intel_dp->has_audio = has_audio;
f684960e
CW		 4581 goto done;
4582 }
4583
e953fd7b 4584 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80 4585 bool old_auto = intel_dp->color_range_auto;
0f2a2a75 4586 bool old_range = intel_dp->limited_color_range;
ae4edb80 4587
55bc60db
VS		 4588 switch (val) {
4589 case INTEL_BROADCAST_RGB_AUTO:
4590 intel_dp->color_range_auto = true;
4591 break;
4592 case INTEL_BROADCAST_RGB_FULL:
4593 intel_dp->color_range_auto = false;
0f2a2a75 4594 intel_dp->limited_color_range = false;
55bc60db
VS		 4595 break;
4596 case INTEL_BROADCAST_RGB_LIMITED:
4597 intel_dp->color_range_auto = false;
0f2a2a75 4598 intel_dp->limited_color_range = true;
55bc60db
VS		 4599 break;
4600 default:
4601 return -EINVAL;
4602 }
ae4edb80
DV		 4603
4604 if (old_auto == intel_dp->color_range_auto &&
0f2a2a75 4605 old_range == intel_dp->limited_color_range)
ae4edb80
DV		 4606 return 0;
4607
e953fd7b
CW		 4608 goto done;
4609 }
4610
53b41837
YN		 4611 if (is_edp(intel_dp) &&
4612 property == connector->dev->mode_config.scaling_mode_property) {
4613 if (val == DRM_MODE_SCALE_NONE) {
4614 DRM_DEBUG_KMS("no scaling not supported\n");
4615 return -EINVAL;
4616 }
234126c6
VS		 4617 if (HAS_GMCH_DISPLAY(dev_priv) &&
4618 val == DRM_MODE_SCALE_CENTER) {
4619 DRM_DEBUG_KMS("centering not supported\n");
4620 return -EINVAL;
4621 }
53b41837
YN		 4622
4623 if (intel_connector->panel.fitting_mode == val) {
4624 /* the eDP scaling property is not changed */
4625 return 0;
4626 }
4627 intel_connector->panel.fitting_mode = val;
4628
4629 goto done;
4630 }
4631
f684960e
CW		 4632 return -EINVAL;
4633
4634done:
c0c36b94
CW		 4635 if (intel_encoder->base.crtc)
4636 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 4637
4638 return 0;
4639}
4640
7a418e34
CW		 4641static int
4642intel_dp_connector_register(struct drm_connector *connector)
4643{
4644 struct intel_dp *intel_dp = intel_attached_dp(connector);
1ebaa0b9
CW		 4645 int ret;
4646
4647 ret = intel_connector_register(connector);
4648 if (ret)
4649 return ret;
7a418e34
CW		 4650
4651 i915_debugfs_connector_add(connector);
4652
4653 DRM_DEBUG_KMS("registering %s bus for %s\n",
4654 intel_dp->aux.name, connector->kdev->kobj.name);
4655
4656 intel_dp->aux.dev = connector->kdev;
4657 return drm_dp_aux_register(&intel_dp->aux);
4658}
4659
c191eca1
CW		 4660static void
4661intel_dp_connector_unregister(struct drm_connector *connector)
4662{
4663 drm_dp_aux_unregister(&intel_attached_dp(connector)->aux);
4664 intel_connector_unregister(connector);
4665}
4666
a4fc5ed6 4667static void
73845adf 4668intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 4669{
1d508706 4670 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 4671
10e972d3 4672 kfree(intel_connector->detect_edid);
beb60608 4673
9cd300e0
JN		 4674 if (!IS_ERR_OR_NULL(intel_connector->edid))
4675 kfree(intel_connector->edid);
4676
acd8db10
PZ		 4677 /* Can't call is_edp() since the encoder may have been destroyed
4678 * already. */
4679 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 4680 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 4681
a4fc5ed6 4682 drm_connector_cleanup(connector);
55f78c43 4683 kfree(connector);
a4fc5ed6
KP		 4684}
4685
00c09d70 4686void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 4687{
da63a9f2
PZ		 4688 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4689 struct intel_dp *intel_dp = &intel_dig_port->dp;
24d05927 4690
0e32b39c 4691 intel_dp_mst_encoder_cleanup(intel_dig_port);
bd943159
KP		 4692 if (is_edp(intel_dp)) {
4693 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 4694 /*
4695 * vdd might still be enabled do to the delayed vdd off.
4696 * Make sure vdd is actually turned off here.
4697 */
773538e8 4698 pps_lock(intel_dp);
4be73780 4699 edp_panel_vdd_off_sync(intel_dp);
773538e8
VS		 4700 pps_unlock(intel_dp);
4701
01527b31
CT		 4702 if (intel_dp->edp_notifier.notifier_call) {
4703 unregister_reboot_notifier(&intel_dp->edp_notifier);
4704 intel_dp->edp_notifier.notifier_call = NULL;
4705 }
bd943159 4706 }
99681886
CW		 4707
4708 intel_dp_aux_fini(intel_dp);
4709
c8bd0e49 4710 drm_encoder_cleanup(encoder);
da63a9f2 4711 kfree(intel_dig_port);
24d05927
DV		 4712}
4713
bf93ba67 4714void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
07f9cd0b
ID		 4715{
4716 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4717
4718 if (!is_edp(intel_dp))
4719 return;
4720
951468f3
VS		 4721 /*
4722 * vdd might still be enabled do to the delayed vdd off.
4723 * Make sure vdd is actually turned off here.
4724 */
afa4e53a 4725 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
773538e8 4726 pps_lock(intel_dp);
07f9cd0b 4727 edp_panel_vdd_off_sync(intel_dp);
773538e8 4728 pps_unlock(intel_dp);
07f9cd0b
ID		 4729}
4730
49e6bc51
VS		 4731static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
4732{
4733 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4734 struct drm_device *dev = intel_dig_port->base.base.dev;
fac5e23e 4735 struct drm_i915_private *dev_priv = to_i915(dev);
49e6bc51
VS		 4736 enum intel_display_power_domain power_domain;
4737
4738 lockdep_assert_held(&dev_priv->pps_mutex);
4739
4740 if (!edp_have_panel_vdd(intel_dp))
4741 return;
4742
4743 /*
4744 * The VDD bit needs a power domain reference, so if the bit is
4745 * already enabled when we boot or resume, grab this reference and
4746 * schedule a vdd off, so we don't hold on to the reference
4747 * indefinitely.
4748 */
4749 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
25f78f58 4750 power_domain = intel_display_port_aux_power_domain(&intel_dig_port->base);
49e6bc51
VS		 4751 intel_display_power_get(dev_priv, power_domain);
4752
4753 edp_panel_vdd_schedule_off(intel_dp);
4754}
4755
bf93ba67 4756void intel_dp_encoder_reset(struct drm_encoder *encoder)
6d93c0c4 4757{
64989ca4 4758 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
910530c0
SS		 4759 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4760 struct intel_lspcon *lspcon = &intel_dig_port->lspcon;
4761 struct intel_dp *intel_dp = &intel_dig_port->dp;
64989ca4
VS		 4762
4763 if (!HAS_DDI(dev_priv))
4764 intel_dp->DP = I915_READ(intel_dp->output_reg);
49e6bc51 4765
910530c0
SS		 4766 if (IS_GEN9(dev_priv) && lspcon->active)
4767 lspcon_resume(lspcon);
4768
49e6bc51
VS		 4769 if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP)
4770 return;
4771
49e6bc51
VS		 4772 pps_lock(intel_dp);
4773
335f752b
ID		 4774 /* Reinit the power sequencer, in case BIOS did something with it. */
4775 intel_dp_pps_init(encoder->dev, intel_dp);
49e6bc51
VS		 4776 intel_edp_panel_vdd_sanitize(intel_dp);
4777
4778 pps_unlock(intel_dp);
6d93c0c4
ID		 4779}
4780
a4fc5ed6 4781static const struct drm_connector_funcs intel_dp_connector_funcs = {
4d688a2a 4782 .dpms = drm_atomic_helper_connector_dpms,
a4fc5ed6 4783 .detect = intel_dp_detect,
beb60608 4784 .force = intel_dp_force,
a4fc5ed6 4785 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 4786 .set_property = intel_dp_set_property,
2545e4a6 4787 .atomic_get_property = intel_connector_atomic_get_property,
7a418e34 4788 .late_register = intel_dp_connector_register,
c191eca1 4789 .early_unregister = intel_dp_connector_unregister,
73845adf 4790 .destroy = intel_dp_connector_destroy,
c6f95f27 4791 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
98969725 4792 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
a4fc5ed6
KP		 4793};
4794
4795static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4796 .get_modes = intel_dp_get_modes,
4797 .mode_valid = intel_dp_mode_valid,
a4fc5ed6
KP		 4798};
4799
a4fc5ed6 4800static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6d93c0c4 4801 .reset = intel_dp_encoder_reset,
24d05927 4802 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 4803};
4804
b2c5c181 4805enum irqreturn
13cf5504
DA		 4806intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4807{
4808 struct intel_dp *intel_dp = &intel_dig_port->dp;
1c767b33 4809 struct intel_encoder *intel_encoder = &intel_dig_port->base;
0e32b39c 4810 struct drm_device *dev = intel_dig_port->base.base.dev;
fac5e23e 4811 struct drm_i915_private *dev_priv = to_i915(dev);
1c767b33 4812 enum intel_display_power_domain power_domain;
b2c5c181 4813 enum irqreturn ret = IRQ_NONE;
1c767b33 4814
2540058f
TI		 4815 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP &&
4816 intel_dig_port->base.type != INTEL_OUTPUT_HDMI)
cca0502b 4817 intel_dig_port->base.type = INTEL_OUTPUT_DP;
13cf5504 4818
7a7f84cc
VS		 4819 if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
4820 /*
4821 * vdd off can generate a long pulse on eDP which
4822 * would require vdd on to handle it, and thus we
4823 * would end up in an endless cycle of
4824 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4825 */
4826 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4827 port_name(intel_dig_port->port));
a8b3d52f 4828 return IRQ_HANDLED;
7a7f84cc
VS		 4829 }
4830
26fbb774
VS		 4831 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4832 port_name(intel_dig_port->port),
0e32b39c 4833 long_hpd ? "long" : "short");
13cf5504 4834
27d4efc5
VS		 4835 if (long_hpd) {
4836 intel_dp->detect_done = false;
4837 return IRQ_NONE;
4838 }
4839
25f78f58 4840 power_domain = intel_display_port_aux_power_domain(intel_encoder);
1c767b33
ID		 4841 intel_display_power_get(dev_priv, power_domain);
4842
27d4efc5
VS		 4843 if (intel_dp->is_mst) {
4844 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
4845 /*
4846 * If we were in MST mode, and device is not
4847 * there, get out of MST mode
4848 */
4849 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4850 intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4851 intel_dp->is_mst = false;
4852 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4853 intel_dp->is_mst);
4854 intel_dp->detect_done = false;
4855 goto put_power;
0e32b39c 4856 }
27d4efc5 4857 }
0e32b39c 4858
27d4efc5
VS		 4859 if (!intel_dp->is_mst) {
4860 if (!intel_dp_short_pulse(intel_dp)) {
4861 intel_dp->detect_done = false;
4862 goto put_power;
39ff747b 4863 }
0e32b39c 4864 }
b2c5c181
DV		 4865
4866 ret = IRQ_HANDLED;
4867
1c767b33
ID		 4868put_power:
4869 intel_display_power_put(dev_priv, power_domain);
4870
4871 return ret;
13cf5504
DA		 4872}
4873
477ec328 4874/* check the VBT to see whether the eDP is on another port */
5d8a7752 4875bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18 4876{
fac5e23e 4877 struct drm_i915_private *dev_priv = to_i915(dev);
36e83a18 4878
53ce81a7
VS		 4879 /*
4880 * eDP not supported on g4x. so bail out early just
4881 * for a bit extra safety in case the VBT is bonkers.
4882 */
4883 if (INTEL_INFO(dev)->gen < 5)
4884 return false;
4885
3b32a35b
VS		 4886 if (port == PORT_A)
4887 return true;
4888
951d9efe 4889 return intel_bios_is_port_edp(dev_priv, port);
36e83a18
ZY		 4890}
4891
0e32b39c 4892void
f684960e
CW		 4893intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4894{
53b41837
YN		 4895 struct intel_connector *intel_connector = to_intel_connector(connector);
4896
3f43c48d 4897 intel_attach_force_audio_property(connector);
e953fd7b 4898 intel_attach_broadcast_rgb_property(connector);
55bc60db 4899 intel_dp->color_range_auto = true;
53b41837
YN		 4900
4901 if (is_edp(intel_dp)) {
4902 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 4903 drm_object_attach_property(
4904 &connector->base,
53b41837 4905 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 4906 DRM_MODE_SCALE_ASPECT);
4907 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 4908 }
f684960e
CW		 4909}
4910
dada1a9f
ID		 4911static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4912{
d28d4731 4913 intel_dp->panel_power_off_time = ktime_get_boottime();
dada1a9f
ID		 4914 intel_dp->last_power_on = jiffies;
4915 intel_dp->last_backlight_off = jiffies;
4916}
4917
67a54566 4918static void
54648618
ID		 4919intel_pps_readout_hw_state(struct drm_i915_private *dev_priv,
4920 struct intel_dp *intel_dp, struct edp_power_seq *seq)
67a54566 4921{
b0a08bec 4922 u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
8e8232d5 4923 struct pps_registers regs;
453c5420 4924
8e8232d5 4925 intel_pps_get_registers(dev_priv, intel_dp, &regs);
67a54566
DV		 4926
4927 /* Workaround: Need to write PP_CONTROL with the unlock key as
4928 * the very first thing. */
b0a08bec 4929 pp_ctl = ironlake_get_pp_control(intel_dp);
67a54566 4930
8e8232d5
ID		 4931 pp_on = I915_READ(regs.pp_on);
4932 pp_off = I915_READ(regs.pp_off);
54648618 4933 if (!IS_BROXTON(dev_priv)) {
8e8232d5
ID		 4934 I915_WRITE(regs.pp_ctrl, pp_ctl);
4935 pp_div = I915_READ(regs.pp_div);
b0a08bec 4936 }
67a54566
DV		 4937
4938 /* Pull timing values out of registers */
54648618
ID		 4939 seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4940 PANEL_POWER_UP_DELAY_SHIFT;
67a54566 4941
54648618
ID		 4942 seq->t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4943 PANEL_LIGHT_ON_DELAY_SHIFT;
67a54566 4944
54648618
ID		 4945 seq->t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4946 PANEL_LIGHT_OFF_DELAY_SHIFT;
67a54566 4947
54648618
ID		 4948 seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4949 PANEL_POWER_DOWN_DELAY_SHIFT;
67a54566 4950
54648618 4951 if (IS_BROXTON(dev_priv)) {
b0a08bec
VK		 4952 u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
4953 BXT_POWER_CYCLE_DELAY_SHIFT;
4954 if (tmp > 0)
54648618 4955 seq->t11_t12 = (tmp - 1) * 1000;
b0a08bec 4956 else
54648618 4957 seq->t11_t12 = 0;
b0a08bec 4958 } else {
54648618 4959 seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
67a54566 4960 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
b0a08bec 4961 }
54648618
ID		 4962}
4963
de9c1b6b
ID		 4964static void
4965intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
4966{
4967 DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4968 state_name,
4969 seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
4970}
4971
4972static void
4973intel_pps_verify_state(struct drm_i915_private *dev_priv,
4974 struct intel_dp *intel_dp)
4975{
4976 struct edp_power_seq hw;
4977 struct edp_power_seq *sw = &intel_dp->pps_delays;
4978
4979 intel_pps_readout_hw_state(dev_priv, intel_dp, &hw);
4980
4981 if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
4982 hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
4983 DRM_ERROR("PPS state mismatch\n");
4984 intel_pps_dump_state("sw", sw);
4985 intel_pps_dump_state("hw", &hw);
4986 }
4987}
4988
54648618
ID		 4989static void
4990intel_dp_init_panel_power_sequencer(struct drm_device *dev,
4991 struct intel_dp *intel_dp)
4992{
fac5e23e 4993 struct drm_i915_private *dev_priv = to_i915(dev);
54648618
ID		 4994 struct edp_power_seq cur, vbt, spec,
4995 *final = &intel_dp->pps_delays;
4996
4997 lockdep_assert_held(&dev_priv->pps_mutex);
4998
4999 /* already initialized? */
5000 if (final->t11_t12 != 0)
5001 return;
5002
5003 intel_pps_readout_hw_state(dev_priv, intel_dp, &cur);
67a54566 5004
de9c1b6b 5005 intel_pps_dump_state("cur", &cur);
67a54566 5006
6aa23e65 5007 vbt = dev_priv->vbt.edp.pps;
67a54566
DV		 5008
5009 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5010 * our hw here, which are all in 100usec. */
5011 spec.t1_t3 = 210 * 10;
5012 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
5013 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
5014 spec.t10 = 500 * 10;
5015 /* This one is special and actually in units of 100ms, but zero
5016 * based in the hw (so we need to add 100 ms). But the sw vbt
5017 * table multiplies it with 1000 to make it in units of 100usec,
5018 * too. */
5019 spec.t11_t12 = (510 + 100) * 10;
5020
de9c1b6b 5021 intel_pps_dump_state("vbt", &vbt);
67a54566
DV		 5022
5023 /* Use the max of the register settings and vbt. If both are
5024 * unset, fall back to the spec limits. */
36b5f425 5025#define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
67a54566
DV		 5026 spec.field : \
5027 max(cur.field, vbt.field))
5028 assign_final(t1_t3);
5029 assign_final(t8);
5030 assign_final(t9);
5031 assign_final(t10);
5032 assign_final(t11_t12);
5033#undef assign_final
5034
36b5f425 5035#define get_delay(field) (DIV_ROUND_UP(final->field, 10))
67a54566
DV		 5036 intel_dp->panel_power_up_delay = get_delay(t1_t3);
5037 intel_dp->backlight_on_delay = get_delay(t8);
5038 intel_dp->backlight_off_delay = get_delay(t9);
5039 intel_dp->panel_power_down_delay = get_delay(t10);
5040 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
5041#undef get_delay
5042
f30d26e4
JN		 5043 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5044 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
5045 intel_dp->panel_power_cycle_delay);
5046
5047 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5048 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
de9c1b6b
ID		 5049
5050 /*
5051 * We override the HW backlight delays to 1 because we do manual waits
5052 * on them. For T8, even BSpec recommends doing it. For T9, if we
5053 * don't do this, we'll end up waiting for the backlight off delay
5054 * twice: once when we do the manual sleep, and once when we disable
5055 * the panel and wait for the PP_STATUS bit to become zero.
5056 */
5057 final->t8 = 1;
5058 final->t9 = 1;
f30d26e4
JN		 5059}
5060
5061static void
5062intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 5063 struct intel_dp *intel_dp)
f30d26e4 5064{
fac5e23e 5065 struct drm_i915_private *dev_priv = to_i915(dev);
453c5420 5066 u32 pp_on, pp_off, pp_div, port_sel = 0;
e7dc33f3 5067 int div = dev_priv->rawclk_freq / 1000;
8e8232d5 5068 struct pps_registers regs;
ad933b56 5069 enum port port = dp_to_dig_port(intel_dp)->port;
36b5f425 5070 const struct edp_power_seq *seq = &intel_dp->pps_delays;
453c5420 5071
e39b999a 5072 lockdep_assert_held(&dev_priv->pps_mutex);
453c5420 5073
8e8232d5 5074 intel_pps_get_registers(dev_priv, intel_dp, &regs);
453c5420 5075
f30d26e4 5076 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
de9c1b6b
ID		 5077 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
5078 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 5079 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 5080 /* Compute the divisor for the pp clock, simply match the Bspec
5081 * formula. */
e2d214ae 5082 if (IS_BROXTON(dev_priv)) {
8e8232d5 5083 pp_div = I915_READ(regs.pp_ctrl);
b0a08bec
VK		 5084 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
5085 pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
5086 << BXT_POWER_CYCLE_DELAY_SHIFT);
5087 } else {
5088 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
5089 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5090 << PANEL_POWER_CYCLE_DELAY_SHIFT);
5091 }
67a54566
DV		 5092
5093 /* Haswell doesn't have any port selection bits for the panel
5094 * power sequencer any more. */
920a14b2 5095 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
ad933b56 5096 port_sel = PANEL_PORT_SELECT_VLV(port);
6e266956 5097 } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
ad933b56 5098 if (port == PORT_A)
a24c144c 5099 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 5100 else
a24c144c 5101 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 5102 }
5103
453c5420
JB		 5104 pp_on |= port_sel;
5105
8e8232d5
ID		 5106 I915_WRITE(regs.pp_on, pp_on);
5107 I915_WRITE(regs.pp_off, pp_off);
e2d214ae 5108 if (IS_BROXTON(dev_priv))
8e8232d5 5109 I915_WRITE(regs.pp_ctrl, pp_div);
b0a08bec 5110 else
8e8232d5 5111 I915_WRITE(regs.pp_div, pp_div);
67a54566 5112
67a54566 5113 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
8e8232d5
ID		 5114 I915_READ(regs.pp_on),
5115 I915_READ(regs.pp_off),
e2d214ae 5116 IS_BROXTON(dev_priv) ?
8e8232d5
ID		 5117 (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
5118 I915_READ(regs.pp_div));
f684960e
CW		 5119}
5120
335f752b
ID		 5121static void intel_dp_pps_init(struct drm_device *dev,
5122 struct intel_dp *intel_dp)
5123{
920a14b2
TU		 5124 struct drm_i915_private *dev_priv = to_i915(dev);
5125
5126 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
335f752b
ID		 5127 vlv_initial_power_sequencer_setup(intel_dp);
5128 } else {
5129 intel_dp_init_panel_power_sequencer(dev, intel_dp);
5130 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
5131 }
5132}
5133
b33a2815
VK		 5134/**
5135 * intel_dp_set_drrs_state - program registers for RR switch to take effect
5423adf1 5136 * @dev_priv: i915 device
e896402c 5137 * @crtc_state: a pointer to the active intel_crtc_state
b33a2815
VK		 5138 * @refresh_rate: RR to be programmed
5139 *
5140 * This function gets called when refresh rate (RR) has to be changed from
5141 * one frequency to another. Switches can be between high and low RR
5142 * supported by the panel or to any other RR based on media playback (in
5143 * this case, RR value needs to be passed from user space).
5144 *
5145 * The caller of this function needs to take a lock on dev_priv->drrs.
5146 */
85cb48a1
ML		 5147static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
5148 struct intel_crtc_state *crtc_state,
5149 int refresh_rate)
439d7ac0 5150{
439d7ac0 5151 struct intel_encoder *encoder;
96178eeb
VK		 5152 struct intel_digital_port *dig_port = NULL;
5153 struct intel_dp *intel_dp = dev_priv->drrs.dp;
85cb48a1 5154 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
96178eeb 5155 enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
439d7ac0
PB		 5156
5157 if (refresh_rate <= 0) {
5158 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5159 return;
5160 }
5161
96178eeb
VK		 5162 if (intel_dp == NULL) {
5163 DRM_DEBUG_KMS("DRRS not supported.\n");
439d7ac0
PB		 5164 return;
5165 }
5166
1fcc9d1c 5167 /*
e4d59f6b
RV		 5168 * FIXME: This needs proper synchronization with psr state for some
5169 * platforms that cannot have PSR and DRRS enabled at the same time.
1fcc9d1c 5170 */
439d7ac0 5171
96178eeb
VK		 5172 dig_port = dp_to_dig_port(intel_dp);
5173 encoder = &dig_port->base;
723f9aab 5174 intel_crtc = to_intel_crtc(encoder->base.crtc);
439d7ac0
PB		 5175
5176 if (!intel_crtc) {
5177 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5178 return;
5179 }
5180
96178eeb 5181 if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
439d7ac0
PB		 5182 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5183 return;
5184 }
5185
96178eeb
VK		 5186 if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
5187 refresh_rate)
439d7ac0
PB		 5188 index = DRRS_LOW_RR;
5189
96178eeb 5190 if (index == dev_priv->drrs.refresh_rate_type) {
439d7ac0
PB		 5191 DRM_DEBUG_KMS(
5192 "DRRS requested for previously set RR...ignoring\n");
5193 return;
5194 }
5195
85cb48a1 5196 if (!crtc_state->base.active) {
439d7ac0
PB		 5197 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5198 return;
5199 }
5200
85cb48a1 5201 if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
a4c30b1d
VK		 5202 switch (index) {
5203 case DRRS_HIGH_RR:
5204 intel_dp_set_m_n(intel_crtc, M1_N1);
5205 break;
5206 case DRRS_LOW_RR:
5207 intel_dp_set_m_n(intel_crtc, M2_N2);
5208 break;
5209 case DRRS_MAX_RR:
5210 default:
5211 DRM_ERROR("Unsupported refreshrate type\n");
5212 }
85cb48a1
ML		 5213 } else if (INTEL_GEN(dev_priv) > 6) {
5214 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
649636ef 5215 u32 val;
a4c30b1d 5216
649636ef 5217 val = I915_READ(reg);
439d7ac0 5218 if (index > DRRS_HIGH_RR) {
85cb48a1 5219 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6fa7aec1
VK		 5220 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5221 else
5222 val |= PIPECONF_EDP_RR_MODE_SWITCH;
439d7ac0 5223 } else {
85cb48a1 5224 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6fa7aec1
VK		 5225 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5226 else
5227 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
439d7ac0
PB		 5228 }
5229 I915_WRITE(reg, val);
5230 }
5231
4e9ac947
VK		 5232 dev_priv->drrs.refresh_rate_type = index;
5233
5234 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5235}
5236
b33a2815
VK		 5237/**
5238 * intel_edp_drrs_enable - init drrs struct if supported
5239 * @intel_dp: DP struct
5423adf1 5240 * @crtc_state: A pointer to the active crtc state.
b33a2815
VK		 5241 *
5242 * Initializes frontbuffer_bits and drrs.dp
5243 */
85cb48a1
ML		 5244void intel_edp_drrs_enable(struct intel_dp *intel_dp,
5245 struct intel_crtc_state *crtc_state)
c395578e
VK		 5246{
5247 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 5248 struct drm_i915_private *dev_priv = to_i915(dev);
c395578e 5249
85cb48a1 5250 if (!crtc_state->has_drrs) {
c395578e
VK		 5251 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5252 return;
5253 }
5254
5255 mutex_lock(&dev_priv->drrs.mutex);
5256 if (WARN_ON(dev_priv->drrs.dp)) {
5257 DRM_ERROR("DRRS already enabled\n");
5258 goto unlock;
5259 }
5260
5261 dev_priv->drrs.busy_frontbuffer_bits = 0;
5262
5263 dev_priv->drrs.dp = intel_dp;
5264
5265unlock:
5266 mutex_unlock(&dev_priv->drrs.mutex);
5267}
5268
b33a2815
VK		 5269/**
5270 * intel_edp_drrs_disable - Disable DRRS
5271 * @intel_dp: DP struct
5423adf1 5272 * @old_crtc_state: Pointer to old crtc_state.
b33a2815
VK		 5273 *
5274 */
85cb48a1
ML		 5275void intel_edp_drrs_disable(struct intel_dp *intel_dp,
5276 struct intel_crtc_state *old_crtc_state)
c395578e
VK		 5277{
5278 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 5279 struct drm_i915_private *dev_priv = to_i915(dev);
c395578e 5280
85cb48a1 5281 if (!old_crtc_state->has_drrs)
c395578e
VK		 5282 return;
5283
5284 mutex_lock(&dev_priv->drrs.mutex);
5285 if (!dev_priv->drrs.dp) {
5286 mutex_unlock(&dev_priv->drrs.mutex);
5287 return;
5288 }
5289
5290 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
85cb48a1
ML		 5291 intel_dp_set_drrs_state(dev_priv, old_crtc_state,
5292 intel_dp->attached_connector->panel.fixed_mode->vrefresh);
c395578e
VK		 5293
5294 dev_priv->drrs.dp = NULL;
5295 mutex_unlock(&dev_priv->drrs.mutex);
5296
5297 cancel_delayed_work_sync(&dev_priv->drrs.work);
5298}
5299
4e9ac947
VK		 5300static void intel_edp_drrs_downclock_work(struct work_struct *work)
5301{
5302 struct drm_i915_private *dev_priv =
5303 container_of(work, typeof(*dev_priv), drrs.work.work);
5304 struct intel_dp *intel_dp;
5305
5306 mutex_lock(&dev_priv->drrs.mutex);
5307
5308 intel_dp = dev_priv->drrs.dp;
5309
5310 if (!intel_dp)
5311 goto unlock;
5312
439d7ac0 5313 /*
4e9ac947
VK		 5314 * The delayed work can race with an invalidate hence we need to
5315 * recheck.
439d7ac0
PB		 5316 */
5317
4e9ac947
VK		 5318 if (dev_priv->drrs.busy_frontbuffer_bits)
5319 goto unlock;
439d7ac0 5320
85cb48a1
ML		 5321 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
5322 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
5323
5324 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5325 intel_dp->attached_connector->panel.downclock_mode->vrefresh);
5326 }
439d7ac0 5327
4e9ac947 5328unlock:
4e9ac947 5329 mutex_unlock(&dev_priv->drrs.mutex);
439d7ac0
PB		 5330}
5331
b33a2815 5332/**
0ddfd203 5333 * intel_edp_drrs_invalidate - Disable Idleness DRRS
5748b6a1 5334 * @dev_priv: i915 device
b33a2815
VK		 5335 * @frontbuffer_bits: frontbuffer plane tracking bits
5336 *
0ddfd203
R		 5337 * This function gets called everytime rendering on the given planes start.
5338 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
b33a2815
VK		 5339 *
5340 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5341 */
5748b6a1
CW		 5342void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
5343 unsigned int frontbuffer_bits)
a93fad0f 5344{
a93fad0f
VK		 5345 struct drm_crtc *crtc;
5346 enum pipe pipe;
5347
9da7d693 5348 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
a93fad0f
VK		 5349 return;
5350
88f933a8 5351 cancel_delayed_work(&dev_priv->drrs.work);
3954e733 5352
a93fad0f 5353 mutex_lock(&dev_priv->drrs.mutex);
9da7d693
DV		 5354 if (!dev_priv->drrs.dp) {
5355 mutex_unlock(&dev_priv->drrs.mutex);
5356 return;
5357 }
5358
a93fad0f
VK		 5359 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5360 pipe = to_intel_crtc(crtc)->pipe;
5361
c1d038c6
DV		 5362 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5363 dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5364
0ddfd203 5365 /* invalidate means busy screen hence upclock */
c1d038c6 5366 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
85cb48a1
ML		 5367 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5368 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
a93fad0f 5369
a93fad0f
VK		 5370 mutex_unlock(&dev_priv->drrs.mutex);
5371}
5372
b33a2815 5373/**
0ddfd203 5374 * intel_edp_drrs_flush - Restart Idleness DRRS
5748b6a1 5375 * @dev_priv: i915 device
b33a2815
VK		 5376 * @frontbuffer_bits: frontbuffer plane tracking bits
5377 *
0ddfd203
R		 5378 * This function gets called every time rendering on the given planes has
5379 * completed or flip on a crtc is completed. So DRRS should be upclocked
5380 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5381 * if no other planes are dirty.
b33a2815
VK		 5382 *
5383 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5384 */
5748b6a1
CW		 5385void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
5386 unsigned int frontbuffer_bits)
a93fad0f 5387{
a93fad0f
VK		 5388 struct drm_crtc *crtc;
5389 enum pipe pipe;
5390
9da7d693 5391 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
a93fad0f
VK		 5392 return;
5393
88f933a8 5394 cancel_delayed_work(&dev_priv->drrs.work);
3954e733 5395
a93fad0f 5396 mutex_lock(&dev_priv->drrs.mutex);
9da7d693
DV		 5397 if (!dev_priv->drrs.dp) {
5398 mutex_unlock(&dev_priv->drrs.mutex);
5399 return;
5400 }
5401
a93fad0f
VK		 5402 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5403 pipe = to_intel_crtc(crtc)->pipe;
c1d038c6
DV		 5404
5405 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
a93fad0f
VK		 5406 dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5407
0ddfd203 5408 /* flush means busy screen hence upclock */
c1d038c6 5409 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
85cb48a1
ML		 5410 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5411 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
0ddfd203
R		 5412
5413 /*
5414 * flush also means no more activity hence schedule downclock, if all
5415 * other fbs are quiescent too
5416 */
5417 if (!dev_priv->drrs.busy_frontbuffer_bits)
a93fad0f
VK		 5418 schedule_delayed_work(&dev_priv->drrs.work,
5419 msecs_to_jiffies(1000));
5420 mutex_unlock(&dev_priv->drrs.mutex);
5421}
5422
b33a2815
VK		 5423/**
5424 * DOC: Display Refresh Rate Switching (DRRS)
5425 *
5426 * Display Refresh Rate Switching (DRRS) is a power conservation feature
5427 * which enables swtching between low and high refresh rates,
5428 * dynamically, based on the usage scenario. This feature is applicable
5429 * for internal panels.
5430 *
5431 * Indication that the panel supports DRRS is given by the panel EDID, which
5432 * would list multiple refresh rates for one resolution.
5433 *
5434 * DRRS is of 2 types - static and seamless.
5435 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5436 * (may appear as a blink on screen) and is used in dock-undock scenario.
5437 * Seamless DRRS involves changing RR without any visual effect to the user
5438 * and can be used during normal system usage. This is done by programming
5439 * certain registers.
5440 *
5441 * Support for static/seamless DRRS may be indicated in the VBT based on
5442 * inputs from the panel spec.
5443 *
5444 * DRRS saves power by switching to low RR based on usage scenarios.
5445 *
2e7a5701
DV		 5446 * The implementation is based on frontbuffer tracking implementation. When
5447 * there is a disturbance on the screen triggered by user activity or a periodic
5448 * system activity, DRRS is disabled (RR is changed to high RR). When there is
5449 * no movement on screen, after a timeout of 1 second, a switch to low RR is
5450 * made.
5451 *
5452 * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
5453 * and intel_edp_drrs_flush() are called.
b33a2815
VK		 5454 *
5455 * DRRS can be further extended to support other internal panels and also
5456 * the scenario of video playback wherein RR is set based on the rate
5457 * requested by userspace.
5458 */
5459
5460/**
5461 * intel_dp_drrs_init - Init basic DRRS work and mutex.
5462 * @intel_connector: eDP connector
5463 * @fixed_mode: preferred mode of panel
5464 *
5465 * This function is called only once at driver load to initialize basic
5466 * DRRS stuff.
5467 *
5468 * Returns:
5469 * Downclock mode if panel supports it, else return NULL.
5470 * DRRS support is determined by the presence of downclock mode (apart
5471 * from VBT setting).
5472 */
4f9db5b5 5473static struct drm_display_mode *
96178eeb
VK		 5474intel_dp_drrs_init(struct intel_connector *intel_connector,
5475 struct drm_display_mode *fixed_mode)
4f9db5b5
PB		 5476{
5477 struct drm_connector *connector = &intel_connector->base;
96178eeb 5478 struct drm_device *dev = connector->dev;
fac5e23e 5479 struct drm_i915_private *dev_priv = to_i915(dev);
4f9db5b5
PB		 5480 struct drm_display_mode *downclock_mode = NULL;
5481
9da7d693
DV		 5482 INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5483 mutex_init(&dev_priv->drrs.mutex);
5484
4f9db5b5
PB		 5485 if (INTEL_INFO(dev)->gen <= 6) {
5486 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5487 return NULL;
5488 }
5489
5490 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4079b8d1 5491 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4f9db5b5
PB		 5492 return NULL;
5493 }
5494
5495 downclock_mode = intel_find_panel_downclock
5496 (dev, fixed_mode, connector);
5497
5498 if (!downclock_mode) {
a1d26342 5499 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
4f9db5b5
PB		 5500 return NULL;
5501 }
5502
96178eeb 5503 dev_priv->drrs.type = dev_priv->vbt.drrs_type;
4f9db5b5 5504
96178eeb 5505 dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
4079b8d1 5506 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4f9db5b5
PB		 5507 return downclock_mode;
5508}
5509
ed92f0b2 5510static bool intel_edp_init_connector(struct intel_dp *intel_dp,
36b5f425 5511 struct intel_connector *intel_connector)
ed92f0b2
PZ		 5512{
5513 struct drm_connector *connector = &intel_connector->base;
5514 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 5515 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5516 struct drm_device *dev = intel_encoder->base.dev;
fac5e23e 5517 struct drm_i915_private *dev_priv = to_i915(dev);
ed92f0b2 5518 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 5519 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 5520 bool has_dpcd;
5521 struct drm_display_mode *scan;
5522 struct edid *edid;
6517d273 5523 enum pipe pipe = INVALID_PIPE;
ed92f0b2
PZ		 5524
5525 if (!is_edp(intel_dp))
5526 return true;
5527
97a824e1
ID		 5528 /*
5529 * On IBX/CPT we may get here with LVDS already registered. Since the
5530 * driver uses the only internal power sequencer available for both
5531 * eDP and LVDS bail out early in this case to prevent interfering
5532 * with an already powered-on LVDS power sequencer.
5533 */
5534 if (intel_get_lvds_encoder(dev)) {
5535 WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
5536 DRM_INFO("LVDS was detected, not registering eDP\n");
5537
5538 return false;
5539 }
5540
49e6bc51 5541 pps_lock(intel_dp);
b4d06ede
ID		 5542
5543 intel_dp_init_panel_power_timestamps(intel_dp);
335f752b 5544 intel_dp_pps_init(dev, intel_dp);
49e6bc51 5545 intel_edp_panel_vdd_sanitize(intel_dp);
b4d06ede 5546
49e6bc51 5547 pps_unlock(intel_dp);
63635217 5548
ed92f0b2 5549 /* Cache DPCD and EDID for edp. */
fe5a66f9 5550 has_dpcd = intel_edp_init_dpcd(intel_dp);
ed92f0b2 5551
fe5a66f9 5552 if (!has_dpcd) {
ed92f0b2
PZ		 5553 /* if this fails, presume the device is a ghost */
5554 DRM_INFO("failed to retrieve link info, disabling eDP\n");
b4d06ede 5555 goto out_vdd_off;
ed92f0b2
PZ		 5556 }
5557
060c8778 5558 mutex_lock(&dev->mode_config.mutex);
0b99836f 5559 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 5560 if (edid) {
5561 if (drm_add_edid_modes(connector, edid)) {
5562 drm_mode_connector_update_edid_property(connector,
5563 edid);
5564 drm_edid_to_eld(connector, edid);
5565 } else {
5566 kfree(edid);
5567 edid = ERR_PTR(-EINVAL);
5568 }
5569 } else {
5570 edid = ERR_PTR(-ENOENT);
5571 }
5572 intel_connector->edid = edid;
5573
5574 /* prefer fixed mode from EDID if available */
5575 list_for_each_entry(scan, &connector->probed_modes, head) {
5576 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5577 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5 5578 downclock_mode = intel_dp_drrs_init(
4f9db5b5 5579 intel_connector, fixed_mode);
ed92f0b2
PZ		 5580 break;
5581 }
5582 }
5583
5584 /* fallback to VBT if available for eDP */
5585 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5586 fixed_mode = drm_mode_duplicate(dev,
5587 dev_priv->vbt.lfp_lvds_vbt_mode);
df457245 5588 if (fixed_mode) {
ed92f0b2 5589 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
df457245
VS		 5590 connector->display_info.width_mm = fixed_mode->width_mm;
5591 connector->display_info.height_mm = fixed_mode->height_mm;
5592 }
ed92f0b2 5593 }
060c8778 5594 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 5595
920a14b2 5596 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
01527b31
CT		 5597 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5598 register_reboot_notifier(&intel_dp->edp_notifier);
6517d273
VS		 5599
5600 /*
5601 * Figure out the current pipe for the initial backlight setup.
5602 * If the current pipe isn't valid, try the PPS pipe, and if that
5603 * fails just assume pipe A.
5604 */
920a14b2 5605 if (IS_CHERRYVIEW(dev_priv))
6517d273
VS		 5606 pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP);
5607 else
5608 pipe = PORT_TO_PIPE(intel_dp->DP);
5609
5610 if (pipe != PIPE_A && pipe != PIPE_B)
5611 pipe = intel_dp->pps_pipe;
5612
5613 if (pipe != PIPE_A && pipe != PIPE_B)
5614 pipe = PIPE_A;
5615
5616 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5617 pipe_name(pipe));
01527b31
CT		 5618 }
5619
4f9db5b5 5620 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
5507faeb 5621 intel_connector->panel.backlight.power = intel_edp_backlight_power;
6517d273 5622 intel_panel_setup_backlight(connector, pipe);
ed92f0b2
PZ		 5623
5624 return true;
b4d06ede
ID		 5625
5626out_vdd_off:
5627 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5628 /*
5629 * vdd might still be enabled do to the delayed vdd off.
5630 * Make sure vdd is actually turned off here.
5631 */
5632 pps_lock(intel_dp);
5633 edp_panel_vdd_off_sync(intel_dp);
5634 pps_unlock(intel_dp);
5635
5636 return false;
ed92f0b2
PZ		 5637}
5638
16c25533 5639bool
f0fec3f2
PZ		 5640intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5641 struct intel_connector *intel_connector)
a4fc5ed6 5642{
f0fec3f2
PZ		 5643 struct drm_connector *connector = &intel_connector->base;
5644 struct intel_dp *intel_dp = &intel_dig_port->dp;
5645 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5646 struct drm_device *dev = intel_encoder->base.dev;
fac5e23e 5647 struct drm_i915_private *dev_priv = to_i915(dev);
174edf1f 5648 enum port port = intel_dig_port->port;
7a418e34 5649 int type;
a4fc5ed6 5650
ccb1a831
VS		 5651 if (WARN(intel_dig_port->max_lanes < 1,
5652 "Not enough lanes (%d) for DP on port %c\n",
5653 intel_dig_port->max_lanes, port_name(port)))
5654 return false;
5655
a4a5d2f8
VS		 5656 intel_dp->pps_pipe = INVALID_PIPE;
5657
ec5b01dd 5658 /* intel_dp vfuncs */
b6b5e383
DL		 5659 if (INTEL_INFO(dev)->gen >= 9)
5660 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
8652744b 5661 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
ec5b01dd 5662 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
6e266956 5663 else if (HAS_PCH_SPLIT(dev_priv))
ec5b01dd
DL		 5664 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5665 else
6ffb1be7 5666 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
ec5b01dd 5667
b9ca5fad
DL		 5668 if (INTEL_INFO(dev)->gen >= 9)
5669 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5670 else
6ffb1be7 5671 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
153b1100 5672
4f8036a2 5673 if (HAS_DDI(dev_priv))
ad64217b
ACO		 5674 intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;
5675
0767935e
DV		 5676 /* Preserve the current hw state. */
5677 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 5678 intel_dp->attached_connector = intel_connector;
3d3dc149 5679
3b32a35b 5680 if (intel_dp_is_edp(dev, port))
b329530c 5681 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 5682 else
5683 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 5684
f7d24902
ID		 5685 /*
5686 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5687 * for DP the encoder type can be set by the caller to
5688 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5689 */
5690 if (type == DRM_MODE_CONNECTOR_eDP)
5691 intel_encoder->type = INTEL_OUTPUT_EDP;
5692
c17ed5b5 5693 /* eDP only on port B and/or C on vlv/chv */
920a14b2 5694 if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
666a4537 5695 is_edp(intel_dp) && port != PORT_B && port != PORT_C))
c17ed5b5
VS		 5696 return false;
5697
e7281eab
ID		 5698 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5699 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5700 port_name(port));
5701
b329530c 5702 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 5703 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5704
a4fc5ed6
KP		 5705 connector->interlace_allowed = true;
5706 connector->doublescan_allowed = 0;
5707
b6339585 5708 intel_dp_aux_init(intel_dp);
7a418e34 5709
f0fec3f2 5710 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 5711 edp_panel_vdd_work);
a4fc5ed6 5712
df0e9248 5713 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6 5714
4f8036a2 5715 if (HAS_DDI(dev_priv))
bcbc889b
PZ		 5716 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5717 else
5718 intel_connector->get_hw_state = intel_connector_get_hw_state;
5719
0b99836f 5720 /* Set up the hotplug pin. */
ab9d7c30
PZ		 5721 switch (port) {
5722 case PORT_A:
1d843f9d 5723 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 5724 break;
5725 case PORT_B:
1d843f9d 5726 intel_encoder->hpd_pin = HPD_PORT_B;
e2d214ae 5727 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
cf1d5883 5728 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 5729 break;
5730 case PORT_C:
1d843f9d 5731 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 5732 break;
5733 case PORT_D:
1d843f9d 5734 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30 5735 break;
26951caf
XZ		 5736 case PORT_E:
5737 intel_encoder->hpd_pin = HPD_PORT_E;
5738 break;
ab9d7c30 5739 default:
ad1c0b19 5740 BUG();
5eb08b69
ZW		 5741 }
5742
0e32b39c 5743 /* init MST on ports that can support it */
f8e58ddf 5744 if (HAS_DP_MST(dev) && !is_edp(intel_dp) &&
0c9b3715
JN		 5745 (port == PORT_B || port == PORT_C || port == PORT_D))
5746 intel_dp_mst_encoder_init(intel_dig_port,
5747 intel_connector->base.base.id);
0e32b39c 5748
36b5f425 5749 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
a121f4e5
VS		 5750 intel_dp_aux_fini(intel_dp);
5751 intel_dp_mst_encoder_cleanup(intel_dig_port);
5752 goto fail;
b2f246a8 5753 }
32f9d658 5754
f684960e
CW		 5755 intel_dp_add_properties(intel_dp, connector);
5756
a4fc5ed6
KP		 5757 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5758 * 0xd. Failure to do so will result in spurious interrupts being
5759 * generated on the port when a cable is not attached.
5760 */
50a0bc90 5761 if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) {
a4fc5ed6
KP		 5762 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5763 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5764 }
16c25533
PZ		 5765
5766 return true;
a121f4e5
VS		 5767
5768fail:
a121f4e5
VS		 5769 drm_connector_cleanup(connector);
5770
5771 return false;
a4fc5ed6 5772}
f0fec3f2 5773
457c52d8
CW		 5774bool intel_dp_init(struct drm_device *dev,
5775 i915_reg_t output_reg,
5776 enum port port)
f0fec3f2 5777{
fac5e23e 5778 struct drm_i915_private *dev_priv = to_i915(dev);
f0fec3f2
PZ		 5779 struct intel_digital_port *intel_dig_port;
5780 struct intel_encoder *intel_encoder;
5781 struct drm_encoder *encoder;
5782 struct intel_connector *intel_connector;
5783
b14c5679 5784 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2 5785 if (!intel_dig_port)
457c52d8 5786 return false;
f0fec3f2 5787
08d9bc92 5788 intel_connector = intel_connector_alloc();
11aee0f6
SM		 5789 if (!intel_connector)
5790 goto err_connector_alloc;
f0fec3f2
PZ		 5791
5792 intel_encoder = &intel_dig_port->base;
5793 encoder = &intel_encoder->base;
5794
893da0c9 5795 if (drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
580d8ed5 5796 DRM_MODE_ENCODER_TMDS, "DP %c", port_name(port)))
893da0c9 5797 goto err_encoder_init;
f0fec3f2 5798
5bfe2ac0 5799 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70 5800 intel_encoder->disable = intel_disable_dp;
00c09d70 5801 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 5802 intel_encoder->get_config = intel_dp_get_config;
07f9cd0b 5803 intel_encoder->suspend = intel_dp_encoder_suspend;
920a14b2 5804 if (IS_CHERRYVIEW(dev_priv)) {
9197c88b 5805 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
e4a1d846
CML		 5806 intel_encoder->pre_enable = chv_pre_enable_dp;
5807 intel_encoder->enable = vlv_enable_dp;
580d3811 5808 intel_encoder->post_disable = chv_post_disable_dp;
d6db995f 5809 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
11a914c2 5810 } else if (IS_VALLEYVIEW(dev_priv)) {
ecff4f3b 5811 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 5812 intel_encoder->pre_enable = vlv_pre_enable_dp;
5813 intel_encoder->enable = vlv_enable_dp;
49277c31 5814 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 5815 } else {
ecff4f3b
JN		 5816 intel_encoder->pre_enable = g4x_pre_enable_dp;
5817 intel_encoder->enable = g4x_enable_dp;
08aff3fe
VS		 5818 if (INTEL_INFO(dev)->gen >= 5)
5819 intel_encoder->post_disable = ilk_post_disable_dp;
ab1f90f9 5820 }
f0fec3f2 5821
174edf1f 5822 intel_dig_port->port = port;
f0fec3f2 5823 intel_dig_port->dp.output_reg = output_reg;
ccb1a831 5824 intel_dig_port->max_lanes = 4;
f0fec3f2 5825
cca0502b 5826 intel_encoder->type = INTEL_OUTPUT_DP;
920a14b2 5827 if (IS_CHERRYVIEW(dev_priv)) {
882ec384
VS		 5828 if (port == PORT_D)
5829 intel_encoder->crtc_mask = 1 << 2;
5830 else
5831 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5832 } else {
5833 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5834 }
bc079e8b 5835 intel_encoder->cloneable = 0;
03cdc1d4 5836 intel_encoder->port = port;
f0fec3f2 5837
13cf5504 5838 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5fcece80 5839 dev_priv->hotplug.irq_port[port] = intel_dig_port;
13cf5504 5840
11aee0f6
SM		 5841 if (!intel_dp_init_connector(intel_dig_port, intel_connector))
5842 goto err_init_connector;
5843
457c52d8 5844 return true;
11aee0f6
SM		 5845
5846err_init_connector:
5847 drm_encoder_cleanup(encoder);
893da0c9 5848err_encoder_init:
11aee0f6
SM		 5849 kfree(intel_connector);
5850err_connector_alloc:
5851 kfree(intel_dig_port);
457c52d8 5852 return false;
f0fec3f2 5853}
0e32b39c
DA		 5854
5855void intel_dp_mst_suspend(struct drm_device *dev)
5856{
fac5e23e 5857 struct drm_i915_private *dev_priv = to_i915(dev);
0e32b39c
DA		 5858 int i;
5859
5860 /* disable MST */
5861 for (i = 0; i < I915_MAX_PORTS; i++) {
5fcece80 5862 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
5aa56969
VS		 5863
5864 if (!intel_dig_port || !intel_dig_port->dp.can_mst)
0e32b39c
DA		 5865 continue;
5866
5aa56969
VS		 5867 if (intel_dig_port->dp.is_mst)
5868 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
0e32b39c
DA		 5869 }
5870}
5871
5872void intel_dp_mst_resume(struct drm_device *dev)
5873{
fac5e23e 5874 struct drm_i915_private *dev_priv = to_i915(dev);
0e32b39c
DA		 5875 int i;
5876
5877 for (i = 0; i < I915_MAX_PORTS; i++) {
5fcece80 5878 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
5aa56969 5879 int ret;
0e32b39c 5880
5aa56969
VS		 5881 if (!intel_dig_port || !intel_dig_port->dp.can_mst)
5882 continue;
0e32b39c 5883
5aa56969
VS		 5884 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
5885 if (ret)
5886 intel_dp_check_mst_status(&intel_dig_port->dp);
0e32b39c
DA		 5887 }
5888}
Linux 6.x block layer and io_uring tree(s)