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Merge branches 'topic/sc18is602' and 'topic/rspi' of git://git.kernel.org/pub/scm...
[linux-block.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
760285e7
DH		 31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_edid.h>
a4fc5ed6 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
a4fc5ed6 37#include "i915_drv.h"
a4fc5ed6 38
a4fc5ed6
KP		 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
9dd4ffdf
CML		 41struct dp_link_dpll {
42 int link_bw;
43 struct dpll dpll;
44};
45
46static const struct dp_link_dpll gen4_dpll[] = {
47 { DP_LINK_BW_1_62,
48 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
49 { DP_LINK_BW_2_7,
50 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
51};
52
53static const struct dp_link_dpll pch_dpll[] = {
54 { DP_LINK_BW_1_62,
55 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
56 { DP_LINK_BW_2_7,
57 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
58};
59
65ce4bf5
CML		 60static const struct dp_link_dpll vlv_dpll[] = {
61 { DP_LINK_BW_1_62,
58f6e632 62 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 63 { DP_LINK_BW_2_7,
64 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
65};
66
cfcb0fc9
JB		 67/**
68 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
69 * @intel_dp: DP struct
70 *
71 * If a CPU or PCH DP output is attached to an eDP panel, this function
72 * will return true, and false otherwise.
73 */
74static bool is_edp(struct intel_dp *intel_dp)
75{
da63a9f2
PZ		 76 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
77
78 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 79}
80
68b4d824 81static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 82{
68b4d824
ID		 83 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
84
85 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 86}
87
df0e9248
CW		 88static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
89{
fa90ecef 90 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 91}
92
ea5b213a 93static void intel_dp_link_down(struct intel_dp *intel_dp);
a4fc5ed6 94
a4fc5ed6 95static int
ea5b213a 96intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 97{
7183dc29 98 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 99
100 switch (max_link_bw) {
101 case DP_LINK_BW_1_62:
102 case DP_LINK_BW_2_7:
103 break;
d4eead50
ID		 104 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
105 max_link_bw = DP_LINK_BW_2_7;
106 break;
a4fc5ed6 107 default:
d4eead50
ID		 108 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
109 max_link_bw);
a4fc5ed6
KP		 110 max_link_bw = DP_LINK_BW_1_62;
111 break;
112 }
113 return max_link_bw;
114}
115
cd9dde44
AJ		 116/*
117 * The units on the numbers in the next two are... bizarre. Examples will
118 * make it clearer; this one parallels an example in the eDP spec.
119 *
120 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
121 *
122 * 270000 * 1 * 8 / 10 == 216000
123 *
124 * The actual data capacity of that configuration is 2.16Gbit/s, so the
125 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
126 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
127 * 119000. At 18bpp that's 2142000 kilobits per second.
128 *
129 * Thus the strange-looking division by 10 in intel_dp_link_required, to
130 * get the result in decakilobits instead of kilobits.
131 */
132
a4fc5ed6 133static int
c898261c 134intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 135{
cd9dde44 136 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 137}
138
fe27d53e
DA		 139static int
140intel_dp_max_data_rate(int max_link_clock, int max_lanes)
141{
142 return (max_link_clock * max_lanes * 8) / 10;
143}
144
a4fc5ed6
KP		 145static int
146intel_dp_mode_valid(struct drm_connector *connector,
147 struct drm_display_mode *mode)
148{
df0e9248 149 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 150 struct intel_connector *intel_connector = to_intel_connector(connector);
151 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 152 int target_clock = mode->clock;
153 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 154
dd06f90e
JN		 155 if (is_edp(intel_dp) && fixed_mode) {
156 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 157 return MODE_PANEL;
158
dd06f90e 159 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 160 return MODE_PANEL;
03afc4a2
DV		 161
162 target_clock = fixed_mode->clock;
7de56f43
ZY		 163 }
164
36008365
DV		 165 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
166 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
167
168 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
169 mode_rate = intel_dp_link_required(target_clock, 18);
170
171 if (mode_rate > max_rate)
c4867936 172 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 173
174 if (mode->clock < 10000)
175 return MODE_CLOCK_LOW;
176
0af78a2b
DV		 177 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
178 return MODE_H_ILLEGAL;
179
a4fc5ed6
KP		 180 return MODE_OK;
181}
182
183static uint32_t
184pack_aux(uint8_t *src, int src_bytes)
185{
186 int i;
187 uint32_t v = 0;
188
189 if (src_bytes > 4)
190 src_bytes = 4;
191 for (i = 0; i < src_bytes; i++)
192 v |= ((uint32_t) src[i]) << ((3-i) * 8);
193 return v;
194}
195
196static void
197unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
198{
199 int i;
200 if (dst_bytes > 4)
201 dst_bytes = 4;
202 for (i = 0; i < dst_bytes; i++)
203 dst[i] = src >> ((3-i) * 8);
204}
205
fb0f8fbf
KP		 206/* hrawclock is 1/4 the FSB frequency */
207static int
208intel_hrawclk(struct drm_device *dev)
209{
210 struct drm_i915_private *dev_priv = dev->dev_private;
211 uint32_t clkcfg;
212
9473c8f4
VP		 213 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
214 if (IS_VALLEYVIEW(dev))
215 return 200;
216
fb0f8fbf
KP		 217 clkcfg = I915_READ(CLKCFG);
218 switch (clkcfg & CLKCFG_FSB_MASK) {
219 case CLKCFG_FSB_400:
220 return 100;
221 case CLKCFG_FSB_533:
222 return 133;
223 case CLKCFG_FSB_667:
224 return 166;
225 case CLKCFG_FSB_800:
226 return 200;
227 case CLKCFG_FSB_1067:
228 return 266;
229 case CLKCFG_FSB_1333:
230 return 333;
231 /* these two are just a guess; one of them might be right */
232 case CLKCFG_FSB_1600:
233 case CLKCFG_FSB_1600_ALT:
234 return 400;
235 default:
236 return 133;
237 }
238}
239
bf13e81b
JN		 240static void
241intel_dp_init_panel_power_sequencer(struct drm_device *dev,
242 struct intel_dp *intel_dp,
243 struct edp_power_seq *out);
244static void
245intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
246 struct intel_dp *intel_dp,
247 struct edp_power_seq *out);
248
249static enum pipe
250vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
251{
252 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
253 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
254 struct drm_device *dev = intel_dig_port->base.base.dev;
255 struct drm_i915_private *dev_priv = dev->dev_private;
256 enum port port = intel_dig_port->port;
257 enum pipe pipe;
258
259 /* modeset should have pipe */
260 if (crtc)
261 return to_intel_crtc(crtc)->pipe;
262
263 /* init time, try to find a pipe with this port selected */
264 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
265 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
266 PANEL_PORT_SELECT_MASK;
267 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
268 return pipe;
269 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
270 return pipe;
271 }
272
273 /* shrug */
274 return PIPE_A;
275}
276
277static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
278{
279 struct drm_device *dev = intel_dp_to_dev(intel_dp);
280
281 if (HAS_PCH_SPLIT(dev))
282 return PCH_PP_CONTROL;
283 else
284 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
285}
286
287static u32 _pp_stat_reg(struct intel_dp *intel_dp)
288{
289 struct drm_device *dev = intel_dp_to_dev(intel_dp);
290
291 if (HAS_PCH_SPLIT(dev))
292 return PCH_PP_STATUS;
293 else
294 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
295}
296
ebf33b18
KP		 297static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
298{
30add22d 299 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 300 struct drm_i915_private *dev_priv = dev->dev_private;
301
bf13e81b 302 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 303}
304
305static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
306{
30add22d 307 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 308 struct drm_i915_private *dev_priv = dev->dev_private;
309
bf13e81b 310 return (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
ebf33b18
KP		 311}
312
9b984dae
KP		 313static void
314intel_dp_check_edp(struct intel_dp *intel_dp)
315{
30add22d 316 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 317 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 318
9b984dae
KP		 319 if (!is_edp(intel_dp))
320 return;
453c5420 321
ebf33b18 322 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 323 WARN(1, "eDP powered off while attempting aux channel communication.\n");
324 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 325 I915_READ(_pp_stat_reg(intel_dp)),
326 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 327 }
328}
329
9ee32fea
DV		 330static uint32_t
331intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
332{
333 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
334 struct drm_device *dev = intel_dig_port->base.base.dev;
335 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 336 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 337 uint32_t status;
338 bool done;
339
ef04f00d 340#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 341 if (has_aux_irq)
b18ac466 342 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 343 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 344 else
345 done = wait_for_atomic(C, 10) == 0;
346 if (!done)
347 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
348 has_aux_irq);
349#undef C
350
351 return status;
352}
353
bc86625a
CW		 354static uint32_t get_aux_clock_divider(struct intel_dp *intel_dp,
355 int index)
a4fc5ed6 356{
174edf1f
PZ		 357 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
358 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 359 struct drm_i915_private *dev_priv = dev->dev_private;
9ee32fea 360
a4fc5ed6 361 /* The clock divider is based off the hrawclk,
fb0f8fbf
KP		 362 * and would like to run at 2MHz. So, take the
363 * hrawclk value and divide by 2 and use that
6176b8f9
JB		 364 *
365 * Note that PCH attached eDP panels should use a 125MHz input
366 * clock divider.
a4fc5ed6 367 */
a62d0834 368 if (IS_VALLEYVIEW(dev)) {
bc86625a 369 return index ? 0 : 100;
a62d0834 370 } else if (intel_dig_port->port == PORT_A) {
bc86625a
CW		 371 if (index)
372 return 0;
affa9354 373 if (HAS_DDI(dev))
bc86625a 374 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
9473c8f4 375 else if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 376 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 377 else
b84a1cf8 378 return 225; /* eDP input clock at 450Mhz */
2c55c336
JN		 379 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
380 /* Workaround for non-ULT HSW */
bc86625a
CW		 381 switch (index) {
382 case 0: return 63;
383 case 1: return 72;
384 default: return 0;
385 }
2c55c336 386 } else if (HAS_PCH_SPLIT(dev)) {
bc86625a 387 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 388 } else {
bc86625a 389 return index ? 0 :intel_hrawclk(dev) / 2;
2c55c336 390 }
b84a1cf8
RV		 391}
392
393static int
394intel_dp_aux_ch(struct intel_dp *intel_dp,
395 uint8_t *send, int send_bytes,
396 uint8_t *recv, int recv_size)
397{
398 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
399 struct drm_device *dev = intel_dig_port->base.base.dev;
400 struct drm_i915_private *dev_priv = dev->dev_private;
401 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
402 uint32_t ch_data = ch_ctl + 4;
bc86625a 403 uint32_t aux_clock_divider;
b84a1cf8
RV		 404 int i, ret, recv_bytes;
405 uint32_t status;
bc86625a 406 int try, precharge, clock = 0;
b84a1cf8 407 bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
a81a507d 408 uint32_t timeout;
b84a1cf8
RV		 409
410 /* dp aux is extremely sensitive to irq latency, hence request the
411 * lowest possible wakeup latency and so prevent the cpu from going into
412 * deep sleep states.
413 */
414 pm_qos_update_request(&dev_priv->pm_qos, 0);
415
416 intel_dp_check_edp(intel_dp);
5eb08b69 417
6b4e0a93
DV		 418 if (IS_GEN6(dev))
419 precharge = 3;
420 else
421 precharge = 5;
422
a81a507d
BW		 423 if (IS_BROADWELL(dev) && ch_ctl == DPA_AUX_CH_CTL)
424 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
425 else
426 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
427
c67a470b
PZ		 428 intel_aux_display_runtime_get(dev_priv);
429
11bee43e
JB		 430 /* Try to wait for any previous AUX channel activity */
431 for (try = 0; try < 3; try++) {
ef04f00d 432 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 433 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
434 break;
435 msleep(1);
436 }
437
438 if (try == 3) {
439 WARN(1, "dp_aux_ch not started status 0x%08x\n",
440 I915_READ(ch_ctl));
9ee32fea
DV		 441 ret = -EBUSY;
442 goto out;
4f7f7b7e
CW		 443 }
444
46a5ae9f
PZ		 445 /* Only 5 data registers! */
446 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
447 ret = -E2BIG;
448 goto out;
449 }
450
bc86625a
CW		 451 while ((aux_clock_divider = get_aux_clock_divider(intel_dp, clock++))) {
452 /* Must try at least 3 times according to DP spec */
453 for (try = 0; try < 5; try++) {
454 /* Load the send data into the aux channel data registers */
455 for (i = 0; i < send_bytes; i += 4)
456 I915_WRITE(ch_data + i,
457 pack_aux(send + i, send_bytes - i));
458
459 /* Send the command and wait for it to complete */
460 I915_WRITE(ch_ctl,
461 DP_AUX_CH_CTL_SEND_BUSY |
462 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
a81a507d 463 timeout |
bc86625a
CW		 464 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
465 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
466 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
467 DP_AUX_CH_CTL_DONE |
468 DP_AUX_CH_CTL_TIME_OUT_ERROR |
469 DP_AUX_CH_CTL_RECEIVE_ERROR);
470
471 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
472
473 /* Clear done status and any errors */
474 I915_WRITE(ch_ctl,
475 status |
476 DP_AUX_CH_CTL_DONE |
477 DP_AUX_CH_CTL_TIME_OUT_ERROR |
478 DP_AUX_CH_CTL_RECEIVE_ERROR);
479
480 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
481 DP_AUX_CH_CTL_RECEIVE_ERROR))
482 continue;
483 if (status & DP_AUX_CH_CTL_DONE)
484 break;
485 }
4f7f7b7e 486 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 487 break;
488 }
489
a4fc5ed6 490 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 491 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 492 ret = -EBUSY;
493 goto out;
a4fc5ed6
KP		 494 }
495
496 /* Check for timeout or receive error.
497 * Timeouts occur when the sink is not connected
498 */
a5b3da54 499 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 500 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 501 ret = -EIO;
502 goto out;
a5b3da54 503 }
1ae8c0a5
KP		 504
505 /* Timeouts occur when the device isn't connected, so they're
506 * "normal" -- don't fill the kernel log with these */
a5b3da54 507 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 508 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 509 ret = -ETIMEDOUT;
510 goto out;
a4fc5ed6
KP		 511 }
512
513 /* Unload any bytes sent back from the other side */
514 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
515 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 516 if (recv_bytes > recv_size)
517 recv_bytes = recv_size;
0206e353 518
4f7f7b7e
CW		 519 for (i = 0; i < recv_bytes; i += 4)
520 unpack_aux(I915_READ(ch_data + i),
521 recv + i, recv_bytes - i);
a4fc5ed6 522
9ee32fea
DV		 523 ret = recv_bytes;
524out:
525 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 526 intel_aux_display_runtime_put(dev_priv);
9ee32fea
DV		 527
528 return ret;
a4fc5ed6
KP		 529}
530
531/* Write data to the aux channel in native mode */
532static int
ea5b213a 533intel_dp_aux_native_write(struct intel_dp *intel_dp,
a4fc5ed6
KP		 534 uint16_t address, uint8_t *send, int send_bytes)
535{
536 int ret;
537 uint8_t msg[20];
538 int msg_bytes;
539 uint8_t ack;
540
46a5ae9f
PZ		 541 if (WARN_ON(send_bytes > 16))
542 return -E2BIG;
543
9b984dae 544 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 545 msg[0] = AUX_NATIVE_WRITE << 4;
546 msg[1] = address >> 8;
eebc863e 547 msg[2] = address & 0xff;
a4fc5ed6
KP		 548 msg[3] = send_bytes - 1;
549 memcpy(&msg[4], send, send_bytes);
550 msg_bytes = send_bytes + 4;
551 for (;;) {
ea5b213a 552 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
a4fc5ed6
KP		 553 if (ret < 0)
554 return ret;
555 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
556 break;
557 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
558 udelay(100);
559 else
a5b3da54 560 return -EIO;
a4fc5ed6
KP		 561 }
562 return send_bytes;
563}
564
565/* Write a single byte to the aux channel in native mode */
566static int
ea5b213a 567intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
a4fc5ed6
KP		 568 uint16_t address, uint8_t byte)
569{
ea5b213a 570 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
a4fc5ed6
KP		 571}
572
573/* read bytes from a native aux channel */
574static int
ea5b213a 575intel_dp_aux_native_read(struct intel_dp *intel_dp,
a4fc5ed6
KP		 576 uint16_t address, uint8_t *recv, int recv_bytes)
577{
578 uint8_t msg[4];
579 int msg_bytes;
580 uint8_t reply[20];
581 int reply_bytes;
582 uint8_t ack;
583 int ret;
584
46a5ae9f
PZ		 585 if (WARN_ON(recv_bytes > 19))
586 return -E2BIG;
587
9b984dae 588 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 589 msg[0] = AUX_NATIVE_READ << 4;
590 msg[1] = address >> 8;
591 msg[2] = address & 0xff;
592 msg[3] = recv_bytes - 1;
593
594 msg_bytes = 4;
595 reply_bytes = recv_bytes + 1;
596
597 for (;;) {
ea5b213a 598 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
a4fc5ed6 599 reply, reply_bytes);
a5b3da54
KP		 600 if (ret == 0)
601 return -EPROTO;
602 if (ret < 0)
a4fc5ed6
KP		 603 return ret;
604 ack = reply[0];
605 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
606 memcpy(recv, reply + 1, ret - 1);
607 return ret - 1;
608 }
609 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
610 udelay(100);
611 else
a5b3da54 612 return -EIO;
a4fc5ed6
KP		 613 }
614}
615
616static int
ab2c0672
DA		 617intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
618 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 619{
ab2c0672 620 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
ea5b213a
CW		 621 struct intel_dp *intel_dp = container_of(adapter,
622 struct intel_dp,
623 adapter);
ab2c0672
DA		 624 uint16_t address = algo_data->address;
625 uint8_t msg[5];
626 uint8_t reply[2];
8316f337 627 unsigned retry;
ab2c0672
DA		 628 int msg_bytes;
629 int reply_bytes;
630 int ret;
631
8a5e6aeb 632 ironlake_edp_panel_vdd_on(intel_dp);
9b984dae 633 intel_dp_check_edp(intel_dp);
ab2c0672
DA		 634 /* Set up the command byte */
635 if (mode & MODE_I2C_READ)
636 msg[0] = AUX_I2C_READ << 4;
637 else
638 msg[0] = AUX_I2C_WRITE << 4;
639
640 if (!(mode & MODE_I2C_STOP))
641 msg[0] |= AUX_I2C_MOT << 4;
a4fc5ed6 642
ab2c0672
DA		 643 msg[1] = address >> 8;
644 msg[2] = address;
645
646 switch (mode) {
647 case MODE_I2C_WRITE:
648 msg[3] = 0;
649 msg[4] = write_byte;
650 msg_bytes = 5;
651 reply_bytes = 1;
652 break;
653 case MODE_I2C_READ:
654 msg[3] = 0;
655 msg_bytes = 4;
656 reply_bytes = 2;
657 break;
658 default:
659 msg_bytes = 3;
660 reply_bytes = 1;
661 break;
662 }
663
58c67ce9
JN		 664 /*
665 * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device is
666 * required to retry at least seven times upon receiving AUX_DEFER
667 * before giving up the AUX transaction.
668 */
669 for (retry = 0; retry < 7; retry++) {
8316f337
DF		 670 ret = intel_dp_aux_ch(intel_dp,
671 msg, msg_bytes,
672 reply, reply_bytes);
ab2c0672 673 if (ret < 0) {
3ff99164 674 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
8a5e6aeb 675 goto out;
ab2c0672 676 }
8316f337
DF		 677
678 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
679 case AUX_NATIVE_REPLY_ACK:
680 /* I2C-over-AUX Reply field is only valid
681 * when paired with AUX ACK.
682 */
683 break;
684 case AUX_NATIVE_REPLY_NACK:
685 DRM_DEBUG_KMS("aux_ch native nack\n");
8a5e6aeb
PZ		 686 ret = -EREMOTEIO;
687 goto out;
8316f337 688 case AUX_NATIVE_REPLY_DEFER:
8d16f258
JN		 689 /*
690 * For now, just give more slack to branch devices. We
691 * could check the DPCD for I2C bit rate capabilities,
692 * and if available, adjust the interval. We could also
693 * be more careful with DP-to-Legacy adapters where a
694 * long legacy cable may force very low I2C bit rates.
695 */
696 if (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
697 DP_DWN_STRM_PORT_PRESENT)
698 usleep_range(500, 600);
699 else
700 usleep_range(300, 400);
8316f337
DF		 701 continue;
702 default:
703 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
704 reply[0]);
8a5e6aeb
PZ		 705 ret = -EREMOTEIO;
706 goto out;
8316f337
DF		 707 }
708
ab2c0672
DA		 709 switch (reply[0] & AUX_I2C_REPLY_MASK) {
710 case AUX_I2C_REPLY_ACK:
711 if (mode == MODE_I2C_READ) {
712 *read_byte = reply[1];
713 }
8a5e6aeb
PZ		 714 ret = reply_bytes - 1;
715 goto out;
ab2c0672 716 case AUX_I2C_REPLY_NACK:
8316f337 717 DRM_DEBUG_KMS("aux_i2c nack\n");
8a5e6aeb
PZ		 718 ret = -EREMOTEIO;
719 goto out;
ab2c0672 720 case AUX_I2C_REPLY_DEFER:
8316f337 721 DRM_DEBUG_KMS("aux_i2c defer\n");
ab2c0672
DA		 722 udelay(100);
723 break;
724 default:
8316f337 725 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
8a5e6aeb
PZ		 726 ret = -EREMOTEIO;
727 goto out;
ab2c0672
DA		 728 }
729 }
8316f337
DF		 730
731 DRM_ERROR("too many retries, giving up\n");
8a5e6aeb
PZ		 732 ret = -EREMOTEIO;
733
734out:
735 ironlake_edp_panel_vdd_off(intel_dp, false);
736 return ret;
a4fc5ed6
KP		 737}
738
739static int
ea5b213a 740intel_dp_i2c_init(struct intel_dp *intel_dp,
55f78c43 741 struct intel_connector *intel_connector, const char *name)
a4fc5ed6 742{
0b5c541b
KP		 743 int ret;
744
d54e9d28 745 DRM_DEBUG_KMS("i2c_init %s\n", name);
ea5b213a
CW		 746 intel_dp->algo.running = false;
747 intel_dp->algo.address = 0;
748 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
749
0206e353 750 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
ea5b213a
CW		 751 intel_dp->adapter.owner = THIS_MODULE;
752 intel_dp->adapter.class = I2C_CLASS_DDC;
0206e353 753 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
ea5b213a
CW		 754 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
755 intel_dp->adapter.algo_data = &intel_dp->algo;
5bdebb18 756 intel_dp->adapter.dev.parent = intel_connector->base.kdev;
ea5b213a 757
0b5c541b 758 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
0b5c541b 759 return ret;
a4fc5ed6
KP		 760}
761
c6bb3538
DV		 762static void
763intel_dp_set_clock(struct intel_encoder *encoder,
764 struct intel_crtc_config *pipe_config, int link_bw)
765{
766 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 767 const struct dp_link_dpll *divisor = NULL;
768 int i, count = 0;
c6bb3538
DV		 769
770 if (IS_G4X(dev)) {
9dd4ffdf
CML		 771 divisor = gen4_dpll;
772 count = ARRAY_SIZE(gen4_dpll);
c6bb3538
DV		 773 } else if (IS_HASWELL(dev)) {
774 /* Haswell has special-purpose DP DDI clocks. */
775 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 776 divisor = pch_dpll;
777 count = ARRAY_SIZE(pch_dpll);
c6bb3538 778 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 779 divisor = vlv_dpll;
780 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 781 }
9dd4ffdf
CML		 782
783 if (divisor && count) {
784 for (i = 0; i < count; i++) {
785 if (link_bw == divisor[i].link_bw) {
786 pipe_config->dpll = divisor[i].dpll;
787 pipe_config->clock_set = true;
788 break;
789 }
790 }
c6bb3538
DV		 791 }
792}
793
00c09d70 794bool
5bfe2ac0
DV		 795intel_dp_compute_config(struct intel_encoder *encoder,
796 struct intel_crtc_config *pipe_config)
a4fc5ed6 797{
5bfe2ac0 798 struct drm_device *dev = encoder->base.dev;
36008365 799 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 800 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 801 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 802 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 803 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 804 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 805 int lane_count, clock;
397fe157 806 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
ea5b213a 807 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
083f9560 808 int bpp, mode_rate;
a4fc5ed6 809 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
ff9a6750 810 int link_avail, link_clock;
a4fc5ed6 811
bc7d38a4 812 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 813 pipe_config->has_pch_encoder = true;
814
03afc4a2 815 pipe_config->has_dp_encoder = true;
a4fc5ed6 816
dd06f90e
JN		 817 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
818 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
819 adjusted_mode);
2dd24552
JB		 820 if (!HAS_PCH_SPLIT(dev))
821 intel_gmch_panel_fitting(intel_crtc, pipe_config,
822 intel_connector->panel.fitting_mode);
823 else
b074cec8
JB		 824 intel_pch_panel_fitting(intel_crtc, pipe_config,
825 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 826 }
827
cb1793ce 828 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 829 return false;
830
083f9560
DV		 831 DRM_DEBUG_KMS("DP link computation with max lane count %i "
832 "max bw %02x pixel clock %iKHz\n",
241bfc38
DL		 833 max_lane_count, bws[max_clock],
834 adjusted_mode->crtc_clock);
083f9560 835
36008365
DV		 836 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
837 * bpc in between. */
3e7ca985 838 bpp = pipe_config->pipe_bpp;
6da7f10d
JN		 839 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
840 dev_priv->vbt.edp_bpp < bpp) {
7984211e
ID		 841 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
842 dev_priv->vbt.edp_bpp);
6da7f10d 843 bpp = dev_priv->vbt.edp_bpp;
7984211e 844 }
657445fe 845
36008365 846 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 847 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
848 bpp);
36008365
DV		 849
850 for (clock = 0; clock <= max_clock; clock++) {
851 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
852 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
853 link_avail = intel_dp_max_data_rate(link_clock,
854 lane_count);
855
856 if (mode_rate <= link_avail) {
857 goto found;
858 }
859 }
860 }
861 }
c4867936 862
36008365 863 return false;
3685a8f3 864
36008365 865found:
55bc60db
VS		 866 if (intel_dp->color_range_auto) {
867 /*
868 * See:
869 * CEA-861-E - 5.1 Default Encoding Parameters
870 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
871 */
18316c8c 872 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 873 intel_dp->color_range = DP_COLOR_RANGE_16_235;
874 else
875 intel_dp->color_range = 0;
876 }
877
3685a8f3 878 if (intel_dp->color_range)
50f3b016 879 pipe_config->limited_color_range = true;
a4fc5ed6 880
36008365
DV		 881 intel_dp->link_bw = bws[clock];
882 intel_dp->lane_count = lane_count;
657445fe 883 pipe_config->pipe_bpp = bpp;
ff9a6750 884 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 885
36008365
DV		 886 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
887 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 888 pipe_config->port_clock, bpp);
36008365
DV		 889 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
890 mode_rate, link_avail);
a4fc5ed6 891
03afc4a2 892 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 893 adjusted_mode->crtc_clock,
894 pipe_config->port_clock,
03afc4a2 895 &pipe_config->dp_m_n);
9d1a455b 896
c6bb3538
DV		 897 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
898
03afc4a2 899 return true;
a4fc5ed6
KP		 900}
901
7c62a164 902static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 903{
7c62a164
DV		 904 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
905 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
906 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 907 struct drm_i915_private *dev_priv = dev->dev_private;
908 u32 dpa_ctl;
909
ff9a6750 910 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 911 dpa_ctl = I915_READ(DP_A);
912 dpa_ctl &= ~DP_PLL_FREQ_MASK;
913
ff9a6750 914 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 915 /* For a long time we've carried around a ILK-DevA w/a for the
916 * 160MHz clock. If we're really unlucky, it's still required.
917 */
918 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 919 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 920 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 921 } else {
922 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 923 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 924 }
1ce17038 925
ea9b6006
DV		 926 I915_WRITE(DP_A, dpa_ctl);
927
928 POSTING_READ(DP_A);
929 udelay(500);
930}
931
b934223d 932static void intel_dp_mode_set(struct intel_encoder *encoder)
a4fc5ed6 933{
b934223d 934 struct drm_device *dev = encoder->base.dev;
417e822d 935 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 936 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 937 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d
DV		 938 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
939 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
a4fc5ed6 940
417e822d 941 /*
1a2eb460 942 * There are four kinds of DP registers:
417e822d
KP		 943 *
944 * IBX PCH
1a2eb460
KP		 945 * SNB CPU
946 * IVB CPU
417e822d
KP		 947 * CPT PCH
948 *
949 * IBX PCH and CPU are the same for almost everything,
950 * except that the CPU DP PLL is configured in this
951 * register
952 *
953 * CPT PCH is quite different, having many bits moved
954 * to the TRANS_DP_CTL register instead. That
955 * configuration happens (oddly) in ironlake_pch_enable
956 */
9c9e7927 957
417e822d
KP		 958 /* Preserve the BIOS-computed detected bit. This is
959 * supposed to be read-only.
960 */
961 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 962
417e822d 963 /* Handle DP bits in common between all three register formats */
417e822d 964 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 965 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 966
e0dac65e
WF		 967 if (intel_dp->has_audio) {
968 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 969 pipe_name(crtc->pipe));
ea5b213a 970 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
b934223d 971 intel_write_eld(&encoder->base, adjusted_mode);
e0dac65e 972 }
247d89f6 973
417e822d 974 /* Split out the IBX/CPU vs CPT settings */
32f9d658 975
bc7d38a4 976 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 977 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
978 intel_dp->DP |= DP_SYNC_HS_HIGH;
979 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
980 intel_dp->DP |= DP_SYNC_VS_HIGH;
981 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
982
6aba5b6c 983 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 984 intel_dp->DP |= DP_ENHANCED_FRAMING;
985
7c62a164 986 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 987 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 988 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 989 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 990
991 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
992 intel_dp->DP |= DP_SYNC_HS_HIGH;
993 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
994 intel_dp->DP |= DP_SYNC_VS_HIGH;
995 intel_dp->DP |= DP_LINK_TRAIN_OFF;
996
6aba5b6c 997 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 998 intel_dp->DP |= DP_ENHANCED_FRAMING;
999
7c62a164 1000 if (crtc->pipe == 1)
417e822d 1001 intel_dp->DP |= DP_PIPEB_SELECT;
417e822d
KP		 1002 } else {
1003 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 1004 }
ea9b6006 1005
bc7d38a4 1006 if (port == PORT_A && !IS_VALLEYVIEW(dev))
7c62a164 1007 ironlake_set_pll_cpu_edp(intel_dp);
a4fc5ed6
KP		 1008}
1009
99ea7127
KP		 1010#define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1011#define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1012
1013#define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1014#define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1015
1016#define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1017#define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1018
1019static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
1020 u32 mask,
1021 u32 value)
bd943159 1022{
30add22d 1023 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1024 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1025 u32 pp_stat_reg, pp_ctrl_reg;
1026
bf13e81b
JN		 1027 pp_stat_reg = _pp_stat_reg(intel_dp);
1028 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1029
99ea7127 1030 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1031 mask, value,
1032 I915_READ(pp_stat_reg),
1033 I915_READ(pp_ctrl_reg));
32ce697c 1034
453c5420 1035 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1036 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1037 I915_READ(pp_stat_reg),
1038 I915_READ(pp_ctrl_reg));
32ce697c 1039 }
99ea7127 1040}
32ce697c 1041
99ea7127
KP		 1042static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
1043{
1044 DRM_DEBUG_KMS("Wait for panel power on\n");
1045 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1046}
1047
99ea7127
KP		 1048static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
1049{
1050 DRM_DEBUG_KMS("Wait for panel power off time\n");
1051 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1052}
1053
1054static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
1055{
1056 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1057 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1058}
1059
1060
832dd3c1
KP		 1061/* Read the current pp_control value, unlocking the register if it
1062 * is locked
1063 */
1064
453c5420 1065static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1066{
453c5420
JB		 1067 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1068 struct drm_i915_private *dev_priv = dev->dev_private;
1069 u32 control;
832dd3c1 1070
bf13e81b 1071 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1072 control &= ~PANEL_UNLOCK_MASK;
1073 control |= PANEL_UNLOCK_REGS;
1074 return control;
bd943159
KP		 1075}
1076
82a4d9c0 1077void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1078{
30add22d 1079 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1080 struct drm_i915_private *dev_priv = dev->dev_private;
1081 u32 pp;
453c5420 1082 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1083
97af61f5
KP		 1084 if (!is_edp(intel_dp))
1085 return;
5d613501 1086
bd943159
KP		 1087 WARN(intel_dp->want_panel_vdd,
1088 "eDP VDD already requested on\n");
1089
1090 intel_dp->want_panel_vdd = true;
99ea7127 1091
b0665d57 1092 if (ironlake_edp_have_panel_vdd(intel_dp))
bd943159 1093 return;
b0665d57
PZ		 1094
1095 DRM_DEBUG_KMS("Turning eDP VDD on\n");
bd943159 1096
99ea7127
KP		 1097 if (!ironlake_edp_have_panel_power(intel_dp))
1098 ironlake_wait_panel_power_cycle(intel_dp);
1099
453c5420 1100 pp = ironlake_get_pp_control(intel_dp);
5d613501 1101 pp |= EDP_FORCE_VDD;
ebf33b18 1102
bf13e81b
JN		 1103 pp_stat_reg = _pp_stat_reg(intel_dp);
1104 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1105
1106 I915_WRITE(pp_ctrl_reg, pp);
1107 POSTING_READ(pp_ctrl_reg);
1108 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1109 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1110 /*
1111 * If the panel wasn't on, delay before accessing aux channel
1112 */
1113 if (!ironlake_edp_have_panel_power(intel_dp)) {
bd943159 1114 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1115 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1116 }
5d613501
JB		 1117}
1118
bd943159 1119static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1120{
30add22d 1121 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1122 struct drm_i915_private *dev_priv = dev->dev_private;
1123 u32 pp;
453c5420 1124 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1125
a0e99e68
DV		 1126 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1127
bd943159 1128 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
b0665d57
PZ		 1129 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1130
453c5420 1131 pp = ironlake_get_pp_control(intel_dp);
bd943159 1132 pp &= ~EDP_FORCE_VDD;
bd943159 1133
9f08ef59
PZ		 1134 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1135 pp_stat_reg = _pp_stat_reg(intel_dp);
453c5420
JB		 1136
1137 I915_WRITE(pp_ctrl_reg, pp);
1138 POSTING_READ(pp_ctrl_reg);
99ea7127 1139
453c5420
JB		 1140 /* Make sure sequencer is idle before allowing subsequent activity */
1141 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1142 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
99ea7127 1143 msleep(intel_dp->panel_power_down_delay);
bd943159
KP		 1144 }
1145}
5d613501 1146
bd943159
KP		 1147static void ironlake_panel_vdd_work(struct work_struct *__work)
1148{
1149 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1150 struct intel_dp, panel_vdd_work);
30add22d 1151 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bd943159 1152
627f7675 1153 mutex_lock(&dev->mode_config.mutex);
bd943159 1154 ironlake_panel_vdd_off_sync(intel_dp);
627f7675 1155 mutex_unlock(&dev->mode_config.mutex);
bd943159
KP		 1156}
1157
82a4d9c0 1158void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1159{
97af61f5
KP		 1160 if (!is_edp(intel_dp))
1161 return;
5d613501 1162
bd943159 1163 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1164
bd943159
KP		 1165 intel_dp->want_panel_vdd = false;
1166
1167 if (sync) {
1168 ironlake_panel_vdd_off_sync(intel_dp);
1169 } else {
1170 /*
1171 * Queue the timer to fire a long
1172 * time from now (relative to the power down delay)
1173 * to keep the panel power up across a sequence of operations
1174 */
1175 schedule_delayed_work(&intel_dp->panel_vdd_work,
1176 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1177 }
5d613501
JB		 1178}
1179
82a4d9c0 1180void ironlake_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1181{
30add22d 1182 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1183 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1184 u32 pp;
453c5420 1185 u32 pp_ctrl_reg;
9934c132 1186
97af61f5 1187 if (!is_edp(intel_dp))
bd943159 1188 return;
99ea7127
KP		 1189
1190 DRM_DEBUG_KMS("Turn eDP power on\n");
1191
1192 if (ironlake_edp_have_panel_power(intel_dp)) {
1193 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1194 return;
99ea7127 1195 }
9934c132 1196
99ea7127 1197 ironlake_wait_panel_power_cycle(intel_dp);
37c6c9b0 1198
bf13e81b 1199 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1200 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1201 if (IS_GEN5(dev)) {
1202 /* ILK workaround: disable reset around power sequence */
1203 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1204 I915_WRITE(pp_ctrl_reg, pp);
1205 POSTING_READ(pp_ctrl_reg);
05ce1a49 1206 }
37c6c9b0 1207
1c0ae80a 1208 pp |= POWER_TARGET_ON;
99ea7127
KP		 1209 if (!IS_GEN5(dev))
1210 pp |= PANEL_POWER_RESET;
1211
453c5420
JB		 1212 I915_WRITE(pp_ctrl_reg, pp);
1213 POSTING_READ(pp_ctrl_reg);
9934c132 1214
99ea7127 1215 ironlake_wait_panel_on(intel_dp);
9934c132 1216
05ce1a49
KP		 1217 if (IS_GEN5(dev)) {
1218 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1219 I915_WRITE(pp_ctrl_reg, pp);
1220 POSTING_READ(pp_ctrl_reg);
05ce1a49 1221 }
9934c132
JB		 1222}
1223
82a4d9c0 1224void ironlake_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1225{
30add22d 1226 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1227 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1228 u32 pp;
453c5420 1229 u32 pp_ctrl_reg;
9934c132 1230
97af61f5
KP		 1231 if (!is_edp(intel_dp))
1232 return;
37c6c9b0 1233
99ea7127 1234 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1235
6cb49835 1236 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
37c6c9b0 1237
453c5420 1238 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1239 /* We need to switch off panel power _and_ force vdd, for otherwise some
1240 * panels get very unhappy and cease to work. */
1241 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
453c5420 1242
bf13e81b 1243 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1244
1245 I915_WRITE(pp_ctrl_reg, pp);
1246 POSTING_READ(pp_ctrl_reg);
9934c132 1247
35a38556
DV		 1248 intel_dp->want_panel_vdd = false;
1249
99ea7127 1250 ironlake_wait_panel_off(intel_dp);
9934c132
JB		 1251}
1252
d6c50ff8 1253void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1254{
da63a9f2
PZ		 1255 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1256 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1257 struct drm_i915_private *dev_priv = dev->dev_private;
1258 u32 pp;
453c5420 1259 u32 pp_ctrl_reg;
32f9d658 1260
f01eca2e
KP		 1261 if (!is_edp(intel_dp))
1262 return;
1263
28c97730 1264 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1265 /*
1266 * If we enable the backlight right away following a panel power
1267 * on, we may see slight flicker as the panel syncs with the eDP
1268 * link. So delay a bit to make sure the image is solid before
1269 * allowing it to appear.
1270 */
f01eca2e 1271 msleep(intel_dp->backlight_on_delay);
453c5420 1272 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1273 pp |= EDP_BLC_ENABLE;
453c5420 1274
bf13e81b 1275 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1276
1277 I915_WRITE(pp_ctrl_reg, pp);
1278 POSTING_READ(pp_ctrl_reg);
035aa3de 1279
752aa88a 1280 intel_panel_enable_backlight(intel_dp->attached_connector);
32f9d658
ZW		 1281}
1282
d6c50ff8 1283void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1284{
30add22d 1285 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1286 struct drm_i915_private *dev_priv = dev->dev_private;
1287 u32 pp;
453c5420 1288 u32 pp_ctrl_reg;
32f9d658 1289
f01eca2e
KP		 1290 if (!is_edp(intel_dp))
1291 return;
1292
752aa88a 1293 intel_panel_disable_backlight(intel_dp->attached_connector);
035aa3de 1294
28c97730 1295 DRM_DEBUG_KMS("\n");
453c5420 1296 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1297 pp &= ~EDP_BLC_ENABLE;
453c5420 1298
bf13e81b 1299 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1300
1301 I915_WRITE(pp_ctrl_reg, pp);
1302 POSTING_READ(pp_ctrl_reg);
f01eca2e 1303 msleep(intel_dp->backlight_off_delay);
32f9d658 1304}
a4fc5ed6 1305
2bd2ad64 1306static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1307{
da63a9f2
PZ		 1308 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1309 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1310 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1311 struct drm_i915_private *dev_priv = dev->dev_private;
1312 u32 dpa_ctl;
1313
2bd2ad64
DV		 1314 assert_pipe_disabled(dev_priv,
1315 to_intel_crtc(crtc)->pipe);
1316
d240f20f
JB		 1317 DRM_DEBUG_KMS("\n");
1318 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1319 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1320 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1321
1322 /* We don't adjust intel_dp->DP while tearing down the link, to
1323 * facilitate link retraining (e.g. after hotplug). Hence clear all
1324 * enable bits here to ensure that we don't enable too much. */
1325 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1326 intel_dp->DP |= DP_PLL_ENABLE;
1327 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1328 POSTING_READ(DP_A);
1329 udelay(200);
d240f20f
JB		 1330}
1331
2bd2ad64 1332static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1333{
da63a9f2
PZ		 1334 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1335 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1336 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1337 struct drm_i915_private *dev_priv = dev->dev_private;
1338 u32 dpa_ctl;
1339
2bd2ad64
DV		 1340 assert_pipe_disabled(dev_priv,
1341 to_intel_crtc(crtc)->pipe);
1342
d240f20f 1343 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1344 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1345 "dp pll off, should be on\n");
1346 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1347
1348 /* We can't rely on the value tracked for the DP register in
1349 * intel_dp->DP because link_down must not change that (otherwise link
1350 * re-training will fail. */
298b0b39 1351 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1352 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1353 POSTING_READ(DP_A);
d240f20f
JB		 1354 udelay(200);
1355}
1356
c7ad3810 1357/* If the sink supports it, try to set the power state appropriately */
c19b0669 1358void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1359{
1360 int ret, i;
1361
1362 /* Should have a valid DPCD by this point */
1363 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1364 return;
1365
1366 if (mode != DRM_MODE_DPMS_ON) {
1367 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1368 DP_SET_POWER_D3);
1369 if (ret != 1)
1370 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1371 } else {
1372 /*
1373 * When turning on, we need to retry for 1ms to give the sink
1374 * time to wake up.
1375 */
1376 for (i = 0; i < 3; i++) {
1377 ret = intel_dp_aux_native_write_1(intel_dp,
1378 DP_SET_POWER,
1379 DP_SET_POWER_D0);
1380 if (ret == 1)
1381 break;
1382 msleep(1);
1383 }
1384 }
1385}
1386
19d8fe15
DV		 1387static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1388 enum pipe *pipe)
d240f20f 1389{
19d8fe15 1390 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1391 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1392 struct drm_device *dev = encoder->base.dev;
1393 struct drm_i915_private *dev_priv = dev->dev_private;
1394 u32 tmp = I915_READ(intel_dp->output_reg);
1395
1396 if (!(tmp & DP_PORT_EN))
1397 return false;
1398
bc7d38a4 1399 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1400 *pipe = PORT_TO_PIPE_CPT(tmp);
bc7d38a4 1401 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1402 *pipe = PORT_TO_PIPE(tmp);
1403 } else {
1404 u32 trans_sel;
1405 u32 trans_dp;
1406 int i;
1407
1408 switch (intel_dp->output_reg) {
1409 case PCH_DP_B:
1410 trans_sel = TRANS_DP_PORT_SEL_B;
1411 break;
1412 case PCH_DP_C:
1413 trans_sel = TRANS_DP_PORT_SEL_C;
1414 break;
1415 case PCH_DP_D:
1416 trans_sel = TRANS_DP_PORT_SEL_D;
1417 break;
1418 default:
1419 return true;
1420 }
1421
1422 for_each_pipe(i) {
1423 trans_dp = I915_READ(TRANS_DP_CTL(i));
1424 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1425 *pipe = i;
1426 return true;
1427 }
1428 }
19d8fe15 1429
4a0833ec
DV		 1430 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1431 intel_dp->output_reg);
1432 }
d240f20f 1433
19d8fe15
DV		 1434 return true;
1435}
d240f20f 1436
045ac3b5
JB		 1437static void intel_dp_get_config(struct intel_encoder *encoder,
1438 struct intel_crtc_config *pipe_config)
1439{
1440 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1441 u32 tmp, flags = 0;
63000ef6
XZ		 1442 struct drm_device *dev = encoder->base.dev;
1443 struct drm_i915_private *dev_priv = dev->dev_private;
1444 enum port port = dp_to_dig_port(intel_dp)->port;
1445 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 1446 int dotclock;
045ac3b5 1447
63000ef6
XZ		 1448 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1449 tmp = I915_READ(intel_dp->output_reg);
1450 if (tmp & DP_SYNC_HS_HIGH)
1451 flags |= DRM_MODE_FLAG_PHSYNC;
1452 else
1453 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1454
63000ef6
XZ		 1455 if (tmp & DP_SYNC_VS_HIGH)
1456 flags |= DRM_MODE_FLAG_PVSYNC;
1457 else
1458 flags |= DRM_MODE_FLAG_NVSYNC;
1459 } else {
1460 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1461 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1462 flags |= DRM_MODE_FLAG_PHSYNC;
1463 else
1464 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1465
63000ef6
XZ		 1466 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1467 flags |= DRM_MODE_FLAG_PVSYNC;
1468 else
1469 flags |= DRM_MODE_FLAG_NVSYNC;
1470 }
045ac3b5
JB		 1471
1472 pipe_config->adjusted_mode.flags |= flags;
f1f644dc 1473
eb14cb74
VS		 1474 pipe_config->has_dp_encoder = true;
1475
1476 intel_dp_get_m_n(crtc, pipe_config);
1477
18442d08 1478 if (port == PORT_A) {
f1f644dc
JB		 1479 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1480 pipe_config->port_clock = 162000;
1481 else
1482 pipe_config->port_clock = 270000;
1483 }
18442d08
VS		 1484
1485 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1486 &pipe_config->dp_m_n);
1487
1488 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1489 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1490
241bfc38 1491 pipe_config->adjusted_mode.crtc_clock = dotclock;
7f16e5c1 1492
c6cd2ee2
JN		 1493 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1494 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1495 /*
1496 * This is a big fat ugly hack.
1497 *
1498 * Some machines in UEFI boot mode provide us a VBT that has 18
1499 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1500 * unknown we fail to light up. Yet the same BIOS boots up with
1501 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1502 * max, not what it tells us to use.
1503 *
1504 * Note: This will still be broken if the eDP panel is not lit
1505 * up by the BIOS, and thus we can't get the mode at module
1506 * load.
1507 */
1508 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1509 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1510 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1511 }
045ac3b5
JB		 1512}
1513
a031d709 1514static bool is_edp_psr(struct drm_device *dev)
2293bb5c 1515{
a031d709
RV		 1516 struct drm_i915_private *dev_priv = dev->dev_private;
1517
1518 return dev_priv->psr.sink_support;
2293bb5c
SK		 1519}
1520
2b28bb1b
RV		 1521static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1522{
1523 struct drm_i915_private *dev_priv = dev->dev_private;
1524
18b5992c 1525 if (!HAS_PSR(dev))
2b28bb1b
RV		 1526 return false;
1527
18b5992c 1528 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2b28bb1b
RV		 1529}
1530
1531static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1532 struct edp_vsc_psr *vsc_psr)
1533{
1534 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1535 struct drm_device *dev = dig_port->base.base.dev;
1536 struct drm_i915_private *dev_priv = dev->dev_private;
1537 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1538 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1539 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1540 uint32_t *data = (uint32_t *) vsc_psr;
1541 unsigned int i;
1542
1543 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1544 the video DIP being updated before program video DIP data buffer
1545 registers for DIP being updated. */
1546 I915_WRITE(ctl_reg, 0);
1547 POSTING_READ(ctl_reg);
1548
1549 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1550 if (i < sizeof(struct edp_vsc_psr))
1551 I915_WRITE(data_reg + i, *data++);
1552 else
1553 I915_WRITE(data_reg + i, 0);
1554 }
1555
1556 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1557 POSTING_READ(ctl_reg);
1558}
1559
1560static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1561{
1562 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1563 struct drm_i915_private *dev_priv = dev->dev_private;
1564 struct edp_vsc_psr psr_vsc;
1565
1566 if (intel_dp->psr_setup_done)
1567 return;
1568
1569 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1570 memset(&psr_vsc, 0, sizeof(psr_vsc));
1571 psr_vsc.sdp_header.HB0 = 0;
1572 psr_vsc.sdp_header.HB1 = 0x7;
1573 psr_vsc.sdp_header.HB2 = 0x2;
1574 psr_vsc.sdp_header.HB3 = 0x8;
1575 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1576
1577 /* Avoid continuous PSR exit by masking memup and hpd */
18b5992c 1578 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
0cc4b699 1579 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
2b28bb1b
RV		 1580
1581 intel_dp->psr_setup_done = true;
1582}
1583
1584static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1585{
1586 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1587 struct drm_i915_private *dev_priv = dev->dev_private;
bc86625a 1588 uint32_t aux_clock_divider = get_aux_clock_divider(intel_dp, 0);
2b28bb1b
RV		 1589 int precharge = 0x3;
1590 int msg_size = 5; /* Header(4) + Message(1) */
1591
1592 /* Enable PSR in sink */
1593 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
1594 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1595 DP_PSR_ENABLE &
1596 ~DP_PSR_MAIN_LINK_ACTIVE);
1597 else
1598 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1599 DP_PSR_ENABLE |
1600 DP_PSR_MAIN_LINK_ACTIVE);
1601
1602 /* Setup AUX registers */
18b5992c
BW		 1603 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1604 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1605 I915_WRITE(EDP_PSR_AUX_CTL(dev),
2b28bb1b
RV		 1606 DP_AUX_CH_CTL_TIME_OUT_400us |
1607 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1608 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1609 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1610}
1611
1612static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1613{
1614 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1615 struct drm_i915_private *dev_priv = dev->dev_private;
1616 uint32_t max_sleep_time = 0x1f;
1617 uint32_t idle_frames = 1;
1618 uint32_t val = 0x0;
ed8546ac 1619 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
2b28bb1b
RV		 1620
1621 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
1622 val |= EDP_PSR_LINK_STANDBY;
1623 val |= EDP_PSR_TP2_TP3_TIME_0us;
1624 val |= EDP_PSR_TP1_TIME_0us;
1625 val |= EDP_PSR_SKIP_AUX_EXIT;
1626 } else
1627 val |= EDP_PSR_LINK_DISABLE;
1628
18b5992c 1629 I915_WRITE(EDP_PSR_CTL(dev), val |
ed8546ac 1630 IS_BROADWELL(dev) ? 0 : link_entry_time |
2b28bb1b
RV		 1631 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1632 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1633 EDP_PSR_ENABLE);
1634}
1635
3f51e471
RV		 1636static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1637{
1638 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1639 struct drm_device *dev = dig_port->base.base.dev;
1640 struct drm_i915_private *dev_priv = dev->dev_private;
1641 struct drm_crtc *crtc = dig_port->base.base.crtc;
1642 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1643 struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->fb)->obj;
1644 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1645
a031d709
RV		 1646 dev_priv->psr.source_ok = false;
1647
18b5992c 1648 if (!HAS_PSR(dev)) {
3f51e471 1649 DRM_DEBUG_KMS("PSR not supported on this platform\n");
3f51e471
RV		 1650 return false;
1651 }
1652
1653 if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
1654 (dig_port->port != PORT_A)) {
1655 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
3f51e471
RV		 1656 return false;
1657 }
1658
105b7c11
RV		 1659 if (!i915_enable_psr) {
1660 DRM_DEBUG_KMS("PSR disable by flag\n");
105b7c11
RV		 1661 return false;
1662 }
1663
cd234b0b
CW		 1664 crtc = dig_port->base.base.crtc;
1665 if (crtc == NULL) {
1666 DRM_DEBUG_KMS("crtc not active for PSR\n");
cd234b0b
CW		 1667 return false;
1668 }
1669
1670 intel_crtc = to_intel_crtc(crtc);
20ddf665 1671 if (!intel_crtc_active(crtc)) {
3f51e471 1672 DRM_DEBUG_KMS("crtc not active for PSR\n");
3f51e471
RV		 1673 return false;
1674 }
1675
cd234b0b 1676 obj = to_intel_framebuffer(crtc->fb)->obj;
3f51e471
RV		 1677 if (obj->tiling_mode != I915_TILING_X ||
1678 obj->fence_reg == I915_FENCE_REG_NONE) {
1679 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
3f51e471
RV		 1680 return false;
1681 }
1682
1683 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1684 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
3f51e471
RV		 1685 return false;
1686 }
1687
1688 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1689 S3D_ENABLE) {
1690 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
3f51e471
RV		 1691 return false;
1692 }
1693
ca73b4f0 1694 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
3f51e471 1695 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
3f51e471
RV		 1696 return false;
1697 }
1698
a031d709 1699 dev_priv->psr.source_ok = true;
3f51e471
RV		 1700 return true;
1701}
1702
3d739d92 1703static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2b28bb1b
RV		 1704{
1705 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1706
3f51e471
RV		 1707 if (!intel_edp_psr_match_conditions(intel_dp) ||
1708 intel_edp_is_psr_enabled(dev))
2b28bb1b
RV		 1709 return;
1710
1711 /* Setup PSR once */
1712 intel_edp_psr_setup(intel_dp);
1713
1714 /* Enable PSR on the panel */
1715 intel_edp_psr_enable_sink(intel_dp);
1716
1717 /* Enable PSR on the host */
1718 intel_edp_psr_enable_source(intel_dp);
1719}
1720
3d739d92
RV		 1721void intel_edp_psr_enable(struct intel_dp *intel_dp)
1722{
1723 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1724
1725 if (intel_edp_psr_match_conditions(intel_dp) &&
1726 !intel_edp_is_psr_enabled(dev))
1727 intel_edp_psr_do_enable(intel_dp);
1728}
1729
2b28bb1b
RV		 1730void intel_edp_psr_disable(struct intel_dp *intel_dp)
1731{
1732 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1733 struct drm_i915_private *dev_priv = dev->dev_private;
1734
1735 if (!intel_edp_is_psr_enabled(dev))
1736 return;
1737
18b5992c
BW		 1738 I915_WRITE(EDP_PSR_CTL(dev),
1739 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
2b28bb1b
RV		 1740
1741 /* Wait till PSR is idle */
18b5992c 1742 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
2b28bb1b
RV		 1743 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1744 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1745}
1746
3d739d92
RV		 1747void intel_edp_psr_update(struct drm_device *dev)
1748{
1749 struct intel_encoder *encoder;
1750 struct intel_dp *intel_dp = NULL;
1751
1752 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1753 if (encoder->type == INTEL_OUTPUT_EDP) {
1754 intel_dp = enc_to_intel_dp(&encoder->base);
1755
a031d709 1756 if (!is_edp_psr(dev))
3d739d92
RV		 1757 return;
1758
1759 if (!intel_edp_psr_match_conditions(intel_dp))
1760 intel_edp_psr_disable(intel_dp);
1761 else
1762 if (!intel_edp_is_psr_enabled(dev))
1763 intel_edp_psr_do_enable(intel_dp);
1764 }
1765}
1766
e8cb4558 1767static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1768{
e8cb4558 1769 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866
ID		 1770 enum port port = dp_to_dig_port(intel_dp)->port;
1771 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 1772
1773 /* Make sure the panel is off before trying to change the mode. But also
1774 * ensure that we have vdd while we switch off the panel. */
1775 ironlake_edp_panel_vdd_on(intel_dp);
21264c63 1776 ironlake_edp_backlight_off(intel_dp);
fdbc3b1f 1777 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
35a38556 1778 ironlake_edp_panel_off(intel_dp);
3739850b
DV		 1779
1780 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
982a3866 1781 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
3739850b 1782 intel_dp_link_down(intel_dp);
d240f20f
JB		 1783}
1784
2bd2ad64 1785static void intel_post_disable_dp(struct intel_encoder *encoder)
d240f20f 1786{
2bd2ad64 1787 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 1788 enum port port = dp_to_dig_port(intel_dp)->port;
b2634017 1789 struct drm_device *dev = encoder->base.dev;
2bd2ad64 1790
982a3866 1791 if (port == PORT_A || IS_VALLEYVIEW(dev)) {
3739850b 1792 intel_dp_link_down(intel_dp);
b2634017
JB		 1793 if (!IS_VALLEYVIEW(dev))
1794 ironlake_edp_pll_off(intel_dp);
3739850b 1795 }
2bd2ad64
DV		 1796}
1797
e8cb4558 1798static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 1799{
e8cb4558
DV		 1800 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1801 struct drm_device *dev = encoder->base.dev;
1802 struct drm_i915_private *dev_priv = dev->dev_private;
1803 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 1804
0c33d8d7
DV		 1805 if (WARN_ON(dp_reg & DP_PORT_EN))
1806 return;
5d613501 1807
97af61f5 1808 ironlake_edp_panel_vdd_on(intel_dp);
f01eca2e 1809 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 1810 intel_dp_start_link_train(intel_dp);
97af61f5 1811 ironlake_edp_panel_on(intel_dp);
bd943159 1812 ironlake_edp_panel_vdd_off(intel_dp, true);
33a34e4e 1813 intel_dp_complete_link_train(intel_dp);
3ab9c637 1814 intel_dp_stop_link_train(intel_dp);
ab1f90f9 1815}
89b667f8 1816
ecff4f3b
JN		 1817static void g4x_enable_dp(struct intel_encoder *encoder)
1818{
828f5c6e
JN		 1819 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1820
ecff4f3b 1821 intel_enable_dp(encoder);
f01eca2e 1822 ironlake_edp_backlight_on(intel_dp);
ab1f90f9 1823}
89b667f8 1824
ab1f90f9
JN		 1825static void vlv_enable_dp(struct intel_encoder *encoder)
1826{
828f5c6e
JN		 1827 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1828
1829 ironlake_edp_backlight_on(intel_dp);
d240f20f
JB		 1830}
1831
ecff4f3b 1832static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 1833{
1834 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1835 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1836
1837 if (dport->port == PORT_A)
1838 ironlake_edp_pll_on(intel_dp);
1839}
1840
1841static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 1842{
2bd2ad64 1843 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1844 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 1845 struct drm_device *dev = encoder->base.dev;
89b667f8 1846 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9
JN		 1847 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1848 int port = vlv_dport_to_channel(dport);
1849 int pipe = intel_crtc->pipe;
bf13e81b 1850 struct edp_power_seq power_seq;
ab1f90f9 1851 u32 val;
a4fc5ed6 1852
ab1f90f9 1853 mutex_lock(&dev_priv->dpio_lock);
89b667f8 1854
5e69f97f 1855 val = vlv_dpio_read(dev_priv, pipe, DPIO_DATA_LANE_A(port));
ab1f90f9
JN		 1856 val = 0;
1857 if (pipe)
1858 val |= (1<<21);
1859 else
1860 val &= ~(1<<21);
1861 val |= 0x001000c4;
5e69f97f
CML		 1862 vlv_dpio_write(dev_priv, pipe, DPIO_DATA_CHANNEL(port), val);
1863 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLOCKBUF0(port), 0x00760018);
1864 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLOCKBUF8(port), 0x00400888);
89b667f8 1865
ab1f90f9
JN		 1866 mutex_unlock(&dev_priv->dpio_lock);
1867
bf13e81b
JN		 1868 /* init power sequencer on this pipe and port */
1869 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
1870 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
1871 &power_seq);
1872
ab1f90f9
JN		 1873 intel_enable_dp(encoder);
1874
1875 vlv_wait_port_ready(dev_priv, port);
89b667f8
JB		 1876}
1877
ecff4f3b 1878static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 1879{
1880 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1881 struct drm_device *dev = encoder->base.dev;
1882 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 1883 struct intel_crtc *intel_crtc =
1884 to_intel_crtc(encoder->base.crtc);
89b667f8 1885 int port = vlv_dport_to_channel(dport);
5e69f97f 1886 int pipe = intel_crtc->pipe;
89b667f8 1887
89b667f8 1888 /* Program Tx lane resets to default */
0980a60f 1889 mutex_lock(&dev_priv->dpio_lock);
5e69f97f 1890 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_TX(port),
89b667f8
JB		 1891 DPIO_PCS_TX_LANE2_RESET |
1892 DPIO_PCS_TX_LANE1_RESET);
5e69f97f 1893 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLK(port),
89b667f8
JB		 1894 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1895 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1896 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1897 DPIO_PCS_CLK_SOFT_RESET);
1898
1899 /* Fix up inter-pair skew failure */
5e69f97f
CML		 1900 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_STAGGER1(port), 0x00750f00);
1901 vlv_dpio_write(dev_priv, pipe, DPIO_TX_CTL(port), 0x00001500);
1902 vlv_dpio_write(dev_priv, pipe, DPIO_TX_LANE(port), 0x40400000);
0980a60f 1903 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 1904}
1905
1906/*
df0c237d
JB		 1907 * Native read with retry for link status and receiver capability reads for
1908 * cases where the sink may still be asleep.
a4fc5ed6
KP		 1909 */
1910static bool
df0c237d
JB		 1911intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1912 uint8_t *recv, int recv_bytes)
a4fc5ed6 1913{
61da5fab
JB		 1914 int ret, i;
1915
df0c237d
JB		 1916 /*
1917 * Sinks are *supposed* to come up within 1ms from an off state,
1918 * but we're also supposed to retry 3 times per the spec.
1919 */
61da5fab 1920 for (i = 0; i < 3; i++) {
df0c237d
JB		 1921 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1922 recv_bytes);
1923 if (ret == recv_bytes)
61da5fab
JB		 1924 return true;
1925 msleep(1);
1926 }
a4fc5ed6 1927
61da5fab 1928 return false;
a4fc5ed6
KP		 1929}
1930
1931/*
1932 * Fetch AUX CH registers 0x202 - 0x207 which contain
1933 * link status information
1934 */
1935static bool
93f62dad 1936intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 1937{
df0c237d
JB		 1938 return intel_dp_aux_native_read_retry(intel_dp,
1939 DP_LANE0_1_STATUS,
93f62dad 1940 link_status,
df0c237d 1941 DP_LINK_STATUS_SIZE);
a4fc5ed6
KP		 1942}
1943
a4fc5ed6
KP		 1944#if 0
1945static char *voltage_names[] = {
1946 "0.4V", "0.6V", "0.8V", "1.2V"
1947};
1948static char *pre_emph_names[] = {
1949 "0dB", "3.5dB", "6dB", "9.5dB"
1950};
1951static char *link_train_names[] = {
1952 "pattern 1", "pattern 2", "idle", "off"
1953};
1954#endif
1955
1956/*
1957 * These are source-specific values; current Intel hardware supports
1958 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1959 */
a4fc5ed6
KP		 1960
1961static uint8_t
1a2eb460 1962intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 1963{
30add22d 1964 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 1965 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 1966
8f93f4f1 1967 if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev))
e2fa6fba 1968 return DP_TRAIN_VOLTAGE_SWING_1200;
bc7d38a4 1969 else if (IS_GEN7(dev) && port == PORT_A)
1a2eb460 1970 return DP_TRAIN_VOLTAGE_SWING_800;
bc7d38a4 1971 else if (HAS_PCH_CPT(dev) && port != PORT_A)
1a2eb460
KP		 1972 return DP_TRAIN_VOLTAGE_SWING_1200;
1973 else
1974 return DP_TRAIN_VOLTAGE_SWING_800;
1975}
1976
1977static uint8_t
1978intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1979{
30add22d 1980 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 1981 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 1982
8f93f4f1
PZ		 1983 if (IS_BROADWELL(dev)) {
1984 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1985 case DP_TRAIN_VOLTAGE_SWING_400:
1986 case DP_TRAIN_VOLTAGE_SWING_600:
1987 return DP_TRAIN_PRE_EMPHASIS_6;
1988 case DP_TRAIN_VOLTAGE_SWING_800:
1989 return DP_TRAIN_PRE_EMPHASIS_3_5;
1990 case DP_TRAIN_VOLTAGE_SWING_1200:
1991 default:
1992 return DP_TRAIN_PRE_EMPHASIS_0;
1993 }
1994 } else if (IS_HASWELL(dev)) {
d6c0d722
PZ		 1995 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1996 case DP_TRAIN_VOLTAGE_SWING_400:
1997 return DP_TRAIN_PRE_EMPHASIS_9_5;
1998 case DP_TRAIN_VOLTAGE_SWING_600:
1999 return DP_TRAIN_PRE_EMPHASIS_6;
2000 case DP_TRAIN_VOLTAGE_SWING_800:
2001 return DP_TRAIN_PRE_EMPHASIS_3_5;
2002 case DP_TRAIN_VOLTAGE_SWING_1200:
2003 default:
2004 return DP_TRAIN_PRE_EMPHASIS_0;
2005 }
e2fa6fba
P		 2006 } else if (IS_VALLEYVIEW(dev)) {
2007 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2008 case DP_TRAIN_VOLTAGE_SWING_400:
2009 return DP_TRAIN_PRE_EMPHASIS_9_5;
2010 case DP_TRAIN_VOLTAGE_SWING_600:
2011 return DP_TRAIN_PRE_EMPHASIS_6;
2012 case DP_TRAIN_VOLTAGE_SWING_800:
2013 return DP_TRAIN_PRE_EMPHASIS_3_5;
2014 case DP_TRAIN_VOLTAGE_SWING_1200:
2015 default:
2016 return DP_TRAIN_PRE_EMPHASIS_0;
2017 }
bc7d38a4 2018 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460
KP		 2019 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2020 case DP_TRAIN_VOLTAGE_SWING_400:
2021 return DP_TRAIN_PRE_EMPHASIS_6;
2022 case DP_TRAIN_VOLTAGE_SWING_600:
2023 case DP_TRAIN_VOLTAGE_SWING_800:
2024 return DP_TRAIN_PRE_EMPHASIS_3_5;
2025 default:
2026 return DP_TRAIN_PRE_EMPHASIS_0;
2027 }
2028 } else {
2029 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2030 case DP_TRAIN_VOLTAGE_SWING_400:
2031 return DP_TRAIN_PRE_EMPHASIS_6;
2032 case DP_TRAIN_VOLTAGE_SWING_600:
2033 return DP_TRAIN_PRE_EMPHASIS_6;
2034 case DP_TRAIN_VOLTAGE_SWING_800:
2035 return DP_TRAIN_PRE_EMPHASIS_3_5;
2036 case DP_TRAIN_VOLTAGE_SWING_1200:
2037 default:
2038 return DP_TRAIN_PRE_EMPHASIS_0;
2039 }
a4fc5ed6
KP		 2040 }
2041}
2042
e2fa6fba
P		 2043static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2044{
2045 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2046 struct drm_i915_private *dev_priv = dev->dev_private;
2047 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 2048 struct intel_crtc *intel_crtc =
2049 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 2050 unsigned long demph_reg_value, preemph_reg_value,
2051 uniqtranscale_reg_value;
2052 uint8_t train_set = intel_dp->train_set[0];
cece5d58 2053 int port = vlv_dport_to_channel(dport);
5e69f97f 2054 int pipe = intel_crtc->pipe;
e2fa6fba
P		 2055
2056 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2057 case DP_TRAIN_PRE_EMPHASIS_0:
2058 preemph_reg_value = 0x0004000;
2059 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2060 case DP_TRAIN_VOLTAGE_SWING_400:
2061 demph_reg_value = 0x2B405555;
2062 uniqtranscale_reg_value = 0x552AB83A;
2063 break;
2064 case DP_TRAIN_VOLTAGE_SWING_600:
2065 demph_reg_value = 0x2B404040;
2066 uniqtranscale_reg_value = 0x5548B83A;
2067 break;
2068 case DP_TRAIN_VOLTAGE_SWING_800:
2069 demph_reg_value = 0x2B245555;
2070 uniqtranscale_reg_value = 0x5560B83A;
2071 break;
2072 case DP_TRAIN_VOLTAGE_SWING_1200:
2073 demph_reg_value = 0x2B405555;
2074 uniqtranscale_reg_value = 0x5598DA3A;
2075 break;
2076 default:
2077 return 0;
2078 }
2079 break;
2080 case DP_TRAIN_PRE_EMPHASIS_3_5:
2081 preemph_reg_value = 0x0002000;
2082 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2083 case DP_TRAIN_VOLTAGE_SWING_400:
2084 demph_reg_value = 0x2B404040;
2085 uniqtranscale_reg_value = 0x5552B83A;
2086 break;
2087 case DP_TRAIN_VOLTAGE_SWING_600:
2088 demph_reg_value = 0x2B404848;
2089 uniqtranscale_reg_value = 0x5580B83A;
2090 break;
2091 case DP_TRAIN_VOLTAGE_SWING_800:
2092 demph_reg_value = 0x2B404040;
2093 uniqtranscale_reg_value = 0x55ADDA3A;
2094 break;
2095 default:
2096 return 0;
2097 }
2098 break;
2099 case DP_TRAIN_PRE_EMPHASIS_6:
2100 preemph_reg_value = 0x0000000;
2101 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2102 case DP_TRAIN_VOLTAGE_SWING_400:
2103 demph_reg_value = 0x2B305555;
2104 uniqtranscale_reg_value = 0x5570B83A;
2105 break;
2106 case DP_TRAIN_VOLTAGE_SWING_600:
2107 demph_reg_value = 0x2B2B4040;
2108 uniqtranscale_reg_value = 0x55ADDA3A;
2109 break;
2110 default:
2111 return 0;
2112 }
2113 break;
2114 case DP_TRAIN_PRE_EMPHASIS_9_5:
2115 preemph_reg_value = 0x0006000;
2116 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2117 case DP_TRAIN_VOLTAGE_SWING_400:
2118 demph_reg_value = 0x1B405555;
2119 uniqtranscale_reg_value = 0x55ADDA3A;
2120 break;
2121 default:
2122 return 0;
2123 }
2124 break;
2125 default:
2126 return 0;
2127 }
2128
0980a60f 2129 mutex_lock(&dev_priv->dpio_lock);
5e69f97f
CML		 2130 vlv_dpio_write(dev_priv, pipe, DPIO_TX_OCALINIT(port), 0x00000000);
2131 vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL4(port), demph_reg_value);
2132 vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL2(port),
e2fa6fba 2133 uniqtranscale_reg_value);
5e69f97f
CML		 2134 vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL3(port), 0x0C782040);
2135 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_STAGGER0(port), 0x00030000);
2136 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CTL_OVER1(port), preemph_reg_value);
2137 vlv_dpio_write(dev_priv, pipe, DPIO_TX_OCALINIT(port), 0x80000000);
0980a60f 2138 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 2139
2140 return 0;
2141}
2142
a4fc5ed6 2143static void
0301b3ac
JN		 2144intel_get_adjust_train(struct intel_dp *intel_dp,
2145 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 2146{
2147 uint8_t v = 0;
2148 uint8_t p = 0;
2149 int lane;
1a2eb460
KP		 2150 uint8_t voltage_max;
2151 uint8_t preemph_max;
a4fc5ed6 2152
33a34e4e 2153 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 2154 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2155 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 2156
2157 if (this_v > v)
2158 v = this_v;
2159 if (this_p > p)
2160 p = this_p;
2161 }
2162
1a2eb460 2163 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 2164 if (v >= voltage_max)
2165 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 2166
1a2eb460
KP		 2167 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2168 if (p >= preemph_max)
2169 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 2170
2171 for (lane = 0; lane < 4; lane++)
33a34e4e 2172 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 2173}
2174
2175static uint32_t
f0a3424e 2176intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 2177{
3cf2efb1 2178 uint32_t signal_levels = 0;
a4fc5ed6 2179
3cf2efb1 2180 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 2181 case DP_TRAIN_VOLTAGE_SWING_400:
2182 default:
2183 signal_levels |= DP_VOLTAGE_0_4;
2184 break;
2185 case DP_TRAIN_VOLTAGE_SWING_600:
2186 signal_levels |= DP_VOLTAGE_0_6;
2187 break;
2188 case DP_TRAIN_VOLTAGE_SWING_800:
2189 signal_levels |= DP_VOLTAGE_0_8;
2190 break;
2191 case DP_TRAIN_VOLTAGE_SWING_1200:
2192 signal_levels |= DP_VOLTAGE_1_2;
2193 break;
2194 }
3cf2efb1 2195 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 2196 case DP_TRAIN_PRE_EMPHASIS_0:
2197 default:
2198 signal_levels |= DP_PRE_EMPHASIS_0;
2199 break;
2200 case DP_TRAIN_PRE_EMPHASIS_3_5:
2201 signal_levels |= DP_PRE_EMPHASIS_3_5;
2202 break;
2203 case DP_TRAIN_PRE_EMPHASIS_6:
2204 signal_levels |= DP_PRE_EMPHASIS_6;
2205 break;
2206 case DP_TRAIN_PRE_EMPHASIS_9_5:
2207 signal_levels |= DP_PRE_EMPHASIS_9_5;
2208 break;
2209 }
2210 return signal_levels;
2211}
2212
e3421a18
ZW		 2213/* Gen6's DP voltage swing and pre-emphasis control */
2214static uint32_t
2215intel_gen6_edp_signal_levels(uint8_t train_set)
2216{
3c5a62b5
YL		 2217 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2218 DP_TRAIN_PRE_EMPHASIS_MASK);
2219 switch (signal_levels) {
e3421a18 2220 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2221 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2222 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2223 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2224 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 2225 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 2226 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2227 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 2228 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 2229 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2230 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 2231 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2232 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2233 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 2234 default:
3c5a62b5
YL		 2235 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2236 "0x%x\n", signal_levels);
2237 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 2238 }
2239}
2240
1a2eb460
KP		 2241/* Gen7's DP voltage swing and pre-emphasis control */
2242static uint32_t
2243intel_gen7_edp_signal_levels(uint8_t train_set)
2244{
2245 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2246 DP_TRAIN_PRE_EMPHASIS_MASK);
2247 switch (signal_levels) {
2248 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2249 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2250 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2251 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2252 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2253 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2254
2255 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2256 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2257 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2258 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2259
2260 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2261 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2262 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2263 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2264
2265 default:
2266 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2267 "0x%x\n", signal_levels);
2268 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2269 }
2270}
2271
d6c0d722
PZ		 2272/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2273static uint32_t
f0a3424e 2274intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 2275{
d6c0d722
PZ		 2276 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2277 DP_TRAIN_PRE_EMPHASIS_MASK);
2278 switch (signal_levels) {
2279 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2280 return DDI_BUF_EMP_400MV_0DB_HSW;
2281 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2282 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2283 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2284 return DDI_BUF_EMP_400MV_6DB_HSW;
2285 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2286 return DDI_BUF_EMP_400MV_9_5DB_HSW;
a4fc5ed6 2287
d6c0d722
PZ		 2288 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2289 return DDI_BUF_EMP_600MV_0DB_HSW;
2290 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2291 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2292 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2293 return DDI_BUF_EMP_600MV_6DB_HSW;
a4fc5ed6 2294
d6c0d722
PZ		 2295 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2296 return DDI_BUF_EMP_800MV_0DB_HSW;
2297 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2298 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2299 default:
2300 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2301 "0x%x\n", signal_levels);
2302 return DDI_BUF_EMP_400MV_0DB_HSW;
a4fc5ed6 2303 }
a4fc5ed6
KP		 2304}
2305
8f93f4f1
PZ		 2306static uint32_t
2307intel_bdw_signal_levels(uint8_t train_set)
2308{
2309 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2310 DP_TRAIN_PRE_EMPHASIS_MASK);
2311 switch (signal_levels) {
2312 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2313 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2314 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2315 return DDI_BUF_EMP_400MV_3_5DB_BDW; /* Sel1 */
2316 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2317 return DDI_BUF_EMP_400MV_6DB_BDW; /* Sel2 */
2318
2319 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2320 return DDI_BUF_EMP_600MV_0DB_BDW; /* Sel3 */
2321 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2322 return DDI_BUF_EMP_600MV_3_5DB_BDW; /* Sel4 */
2323 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2324 return DDI_BUF_EMP_600MV_6DB_BDW; /* Sel5 */
2325
2326 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2327 return DDI_BUF_EMP_800MV_0DB_BDW; /* Sel6 */
2328 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2329 return DDI_BUF_EMP_800MV_3_5DB_BDW; /* Sel7 */
2330
2331 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2332 return DDI_BUF_EMP_1200MV_0DB_BDW; /* Sel8 */
2333
2334 default:
2335 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2336 "0x%x\n", signal_levels);
2337 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2338 }
2339}
2340
f0a3424e
PZ		 2341/* Properly updates "DP" with the correct signal levels. */
2342static void
2343intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2344{
2345 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2346 enum port port = intel_dig_port->port;
f0a3424e
PZ		 2347 struct drm_device *dev = intel_dig_port->base.base.dev;
2348 uint32_t signal_levels, mask;
2349 uint8_t train_set = intel_dp->train_set[0];
2350
8f93f4f1
PZ		 2351 if (IS_BROADWELL(dev)) {
2352 signal_levels = intel_bdw_signal_levels(train_set);
2353 mask = DDI_BUF_EMP_MASK;
2354 } else if (IS_HASWELL(dev)) {
f0a3424e
PZ		 2355 signal_levels = intel_hsw_signal_levels(train_set);
2356 mask = DDI_BUF_EMP_MASK;
e2fa6fba
P		 2357 } else if (IS_VALLEYVIEW(dev)) {
2358 signal_levels = intel_vlv_signal_levels(intel_dp);
2359 mask = 0;
bc7d38a4 2360 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 2361 signal_levels = intel_gen7_edp_signal_levels(train_set);
2362 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 2363 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 2364 signal_levels = intel_gen6_edp_signal_levels(train_set);
2365 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2366 } else {
2367 signal_levels = intel_gen4_signal_levels(train_set);
2368 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2369 }
2370
2371 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2372
2373 *DP = (*DP & ~mask) | signal_levels;
2374}
2375
a4fc5ed6 2376static bool
ea5b213a 2377intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 2378 uint32_t *DP,
58e10eb9 2379 uint8_t dp_train_pat)
a4fc5ed6 2380{
174edf1f
PZ		 2381 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2382 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2383 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 2384 enum port port = intel_dig_port->port;
2cdfe6c8
JN		 2385 uint8_t buf[sizeof(intel_dp->train_set) + 1];
2386 int ret, len;
a4fc5ed6 2387
22b8bf17 2388 if (HAS_DDI(dev)) {
3ab9c637 2389 uint32_t temp = I915_READ(DP_TP_CTL(port));
d6c0d722
PZ		 2390
2391 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2392 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2393 else
2394 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2395
2396 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2397 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2398 case DP_TRAINING_PATTERN_DISABLE:
d6c0d722
PZ		 2399 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2400
2401 break;
2402 case DP_TRAINING_PATTERN_1:
2403 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2404 break;
2405 case DP_TRAINING_PATTERN_2:
2406 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2407 break;
2408 case DP_TRAINING_PATTERN_3:
2409 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2410 break;
2411 }
174edf1f 2412 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722 2413
bc7d38a4 2414 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
70aff66c 2415 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
47ea7542
PZ		 2416
2417 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2418 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2419 *DP |= DP_LINK_TRAIN_OFF_CPT;
47ea7542
PZ		 2420 break;
2421 case DP_TRAINING_PATTERN_1:
70aff66c 2422 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
47ea7542
PZ		 2423 break;
2424 case DP_TRAINING_PATTERN_2:
70aff66c 2425 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2426 break;
2427 case DP_TRAINING_PATTERN_3:
2428 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 2429 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2430 break;
2431 }
2432
2433 } else {
70aff66c 2434 *DP &= ~DP_LINK_TRAIN_MASK;
47ea7542
PZ		 2435
2436 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2437 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2438 *DP |= DP_LINK_TRAIN_OFF;
47ea7542
PZ		 2439 break;
2440 case DP_TRAINING_PATTERN_1:
70aff66c 2441 *DP |= DP_LINK_TRAIN_PAT_1;
47ea7542
PZ		 2442 break;
2443 case DP_TRAINING_PATTERN_2:
70aff66c 2444 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 2445 break;
2446 case DP_TRAINING_PATTERN_3:
2447 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 2448 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 2449 break;
2450 }
2451 }
2452
70aff66c 2453 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 2454 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 2455
2cdfe6c8
JN		 2456 buf[0] = dp_train_pat;
2457 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 2458 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 2459 /* don't write DP_TRAINING_LANEx_SET on disable */
2460 len = 1;
2461 } else {
2462 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
2463 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
2464 len = intel_dp->lane_count + 1;
47ea7542 2465 }
a4fc5ed6 2466
2cdfe6c8
JN		 2467 ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_PATTERN_SET,
2468 buf, len);
2469
2470 return ret == len;
a4fc5ed6
KP		 2471}
2472
70aff66c
JN		 2473static bool
2474intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2475 uint8_t dp_train_pat)
2476{
953d22e8 2477 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 2478 intel_dp_set_signal_levels(intel_dp, DP);
2479 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
2480}
2481
2482static bool
2483intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 2484 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 2485{
2486 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2487 struct drm_device *dev = intel_dig_port->base.base.dev;
2488 struct drm_i915_private *dev_priv = dev->dev_private;
2489 int ret;
2490
2491 intel_get_adjust_train(intel_dp, link_status);
2492 intel_dp_set_signal_levels(intel_dp, DP);
2493
2494 I915_WRITE(intel_dp->output_reg, *DP);
2495 POSTING_READ(intel_dp->output_reg);
2496
2497 ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_LANE0_SET,
2498 intel_dp->train_set,
2499 intel_dp->lane_count);
2500
2501 return ret == intel_dp->lane_count;
2502}
2503
3ab9c637
ID		 2504static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2505{
2506 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2507 struct drm_device *dev = intel_dig_port->base.base.dev;
2508 struct drm_i915_private *dev_priv = dev->dev_private;
2509 enum port port = intel_dig_port->port;
2510 uint32_t val;
2511
2512 if (!HAS_DDI(dev))
2513 return;
2514
2515 val = I915_READ(DP_TP_CTL(port));
2516 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2517 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2518 I915_WRITE(DP_TP_CTL(port), val);
2519
2520 /*
2521 * On PORT_A we can have only eDP in SST mode. There the only reason
2522 * we need to set idle transmission mode is to work around a HW issue
2523 * where we enable the pipe while not in idle link-training mode.
2524 * In this case there is requirement to wait for a minimum number of
2525 * idle patterns to be sent.
2526 */
2527 if (port == PORT_A)
2528 return;
2529
2530 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2531 1))
2532 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2533}
2534
33a34e4e 2535/* Enable corresponding port and start training pattern 1 */
c19b0669 2536void
33a34e4e 2537intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 2538{
da63a9f2 2539 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 2540 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 2541 int i;
2542 uint8_t voltage;
cdb0e95b 2543 int voltage_tries, loop_tries;
ea5b213a 2544 uint32_t DP = intel_dp->DP;
6aba5b6c 2545 uint8_t link_config[2];
a4fc5ed6 2546
affa9354 2547 if (HAS_DDI(dev))
c19b0669
PZ		 2548 intel_ddi_prepare_link_retrain(encoder);
2549
3cf2efb1 2550 /* Write the link configuration data */
6aba5b6c
JN		 2551 link_config[0] = intel_dp->link_bw;
2552 link_config[1] = intel_dp->lane_count;
2553 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2554 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
2555 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, link_config, 2);
2556
2557 link_config[0] = 0;
2558 link_config[1] = DP_SET_ANSI_8B10B;
2559 intel_dp_aux_native_write(intel_dp, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 2560
2561 DP |= DP_PORT_EN;
1a2eb460 2562
70aff66c
JN		 2563 /* clock recovery */
2564 if (!intel_dp_reset_link_train(intel_dp, &DP,
2565 DP_TRAINING_PATTERN_1 |
2566 DP_LINK_SCRAMBLING_DISABLE)) {
2567 DRM_ERROR("failed to enable link training\n");
2568 return;
2569 }
2570
a4fc5ed6 2571 voltage = 0xff;
cdb0e95b
KP		 2572 voltage_tries = 0;
2573 loop_tries = 0;
a4fc5ed6 2574 for (;;) {
70aff66c 2575 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 2576
a7c9655f 2577 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 2578 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2579 DRM_ERROR("failed to get link status\n");
a4fc5ed6 2580 break;
93f62dad 2581 }
a4fc5ed6 2582
01916270 2583 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 2584 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 2585 break;
2586 }
2587
2588 /* Check to see if we've tried the max voltage */
2589 for (i = 0; i < intel_dp->lane_count; i++)
2590 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 2591 break;
3b4f819d 2592 if (i == intel_dp->lane_count) {
b06fbda3
DV		 2593 ++loop_tries;
2594 if (loop_tries == 5) {
3def84b3 2595 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 2596 break;
2597 }
70aff66c
JN		 2598 intel_dp_reset_link_train(intel_dp, &DP,
2599 DP_TRAINING_PATTERN_1 |
2600 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 2601 voltage_tries = 0;
2602 continue;
2603 }
a4fc5ed6 2604
3cf2efb1 2605 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 2606 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 2607 ++voltage_tries;
b06fbda3 2608 if (voltage_tries == 5) {
3def84b3 2609 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 2610 break;
2611 }
2612 } else
2613 voltage_tries = 0;
2614 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 2615
70aff66c
JN		 2616 /* Update training set as requested by target */
2617 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2618 DRM_ERROR("failed to update link training\n");
2619 break;
2620 }
a4fc5ed6
KP		 2621 }
2622
33a34e4e
JB		 2623 intel_dp->DP = DP;
2624}
2625
c19b0669 2626void
33a34e4e
JB		 2627intel_dp_complete_link_train(struct intel_dp *intel_dp)
2628{
33a34e4e 2629 bool channel_eq = false;
37f80975 2630 int tries, cr_tries;
33a34e4e
JB		 2631 uint32_t DP = intel_dp->DP;
2632
a4fc5ed6 2633 /* channel equalization */
70aff66c
JN		 2634 if (!intel_dp_set_link_train(intel_dp, &DP,
2635 DP_TRAINING_PATTERN_2 |
2636 DP_LINK_SCRAMBLING_DISABLE)) {
2637 DRM_ERROR("failed to start channel equalization\n");
2638 return;
2639 }
2640
a4fc5ed6 2641 tries = 0;
37f80975 2642 cr_tries = 0;
a4fc5ed6
KP		 2643 channel_eq = false;
2644 for (;;) {
70aff66c 2645 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 2646
37f80975
JB		 2647 if (cr_tries > 5) {
2648 DRM_ERROR("failed to train DP, aborting\n");
2649 intel_dp_link_down(intel_dp);
2650 break;
2651 }
2652
a7c9655f 2653 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 2654 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2655 DRM_ERROR("failed to get link status\n");
a4fc5ed6 2656 break;
70aff66c 2657 }
a4fc5ed6 2658
37f80975 2659 /* Make sure clock is still ok */
01916270 2660 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 2661 intel_dp_start_link_train(intel_dp);
70aff66c
JN		 2662 intel_dp_set_link_train(intel_dp, &DP,
2663 DP_TRAINING_PATTERN_2 |
2664 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 2665 cr_tries++;
2666 continue;
2667 }
2668
1ffdff13 2669 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 2670 channel_eq = true;
2671 break;
2672 }
a4fc5ed6 2673
37f80975
JB		 2674 /* Try 5 times, then try clock recovery if that fails */
2675 if (tries > 5) {
2676 intel_dp_link_down(intel_dp);
2677 intel_dp_start_link_train(intel_dp);
70aff66c
JN		 2678 intel_dp_set_link_train(intel_dp, &DP,
2679 DP_TRAINING_PATTERN_2 |
2680 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 2681 tries = 0;
2682 cr_tries++;
2683 continue;
2684 }
a4fc5ed6 2685
70aff66c
JN		 2686 /* Update training set as requested by target */
2687 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2688 DRM_ERROR("failed to update link training\n");
2689 break;
2690 }
3cf2efb1 2691 ++tries;
869184a6 2692 }
3cf2efb1 2693
3ab9c637
ID		 2694 intel_dp_set_idle_link_train(intel_dp);
2695
2696 intel_dp->DP = DP;
2697
d6c0d722 2698 if (channel_eq)
07f42258 2699 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 2700
3ab9c637
ID		 2701}
2702
2703void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2704{
70aff66c 2705 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 2706 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 2707}
2708
2709static void
ea5b213a 2710intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 2711{
da63a9f2 2712 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2713 enum port port = intel_dig_port->port;
da63a9f2 2714 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2715 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 2716 struct intel_crtc *intel_crtc =
2717 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 2718 uint32_t DP = intel_dp->DP;
a4fc5ed6 2719
c19b0669
PZ		 2720 /*
2721 * DDI code has a strict mode set sequence and we should try to respect
2722 * it, otherwise we might hang the machine in many different ways. So we
2723 * really should be disabling the port only on a complete crtc_disable
2724 * sequence. This function is just called under two conditions on DDI
2725 * code:
2726 * - Link train failed while doing crtc_enable, and on this case we
2727 * really should respect the mode set sequence and wait for a
2728 * crtc_disable.
2729 * - Someone turned the monitor off and intel_dp_check_link_status
2730 * called us. We don't need to disable the whole port on this case, so
2731 * when someone turns the monitor on again,
2732 * intel_ddi_prepare_link_retrain will take care of redoing the link
2733 * train.
2734 */
affa9354 2735 if (HAS_DDI(dev))
c19b0669
PZ		 2736 return;
2737
0c33d8d7 2738 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 2739 return;
2740
28c97730 2741 DRM_DEBUG_KMS("\n");
32f9d658 2742
bc7d38a4 2743 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 2744 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 2745 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 2746 } else {
2747 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 2748 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 2749 }
fe255d00 2750 POSTING_READ(intel_dp->output_reg);
5eb08b69 2751
ab527efc
DV		 2752 /* We don't really know why we're doing this */
2753 intel_wait_for_vblank(dev, intel_crtc->pipe);
5eb08b69 2754
493a7081 2755 if (HAS_PCH_IBX(dev) &&
1b39d6f3 2756 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 2757 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 2758
5bddd17f
EA		 2759 /* Hardware workaround: leaving our transcoder select
2760 * set to transcoder B while it's off will prevent the
2761 * corresponding HDMI output on transcoder A.
2762 *
2763 * Combine this with another hardware workaround:
2764 * transcoder select bit can only be cleared while the
2765 * port is enabled.
2766 */
2767 DP &= ~DP_PIPEB_SELECT;
2768 I915_WRITE(intel_dp->output_reg, DP);
2769
2770 /* Changes to enable or select take place the vblank
2771 * after being written.
2772 */
ff50afe9
DV		 2773 if (WARN_ON(crtc == NULL)) {
2774 /* We should never try to disable a port without a crtc
2775 * attached. For paranoia keep the code around for a
2776 * bit. */
31acbcc4
CW		 2777 POSTING_READ(intel_dp->output_reg);
2778 msleep(50);
2779 } else
ab527efc 2780 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 2781 }
2782
832afda6 2783 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 2784 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2785 POSTING_READ(intel_dp->output_reg);
f01eca2e 2786 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 2787}
2788
26d61aad
KP		 2789static bool
2790intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 2791{
a031d709
RV		 2792 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2793 struct drm_device *dev = dig_port->base.base.dev;
2794 struct drm_i915_private *dev_priv = dev->dev_private;
2795
577c7a50
DL		 2796 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2797
92fd8fd1 2798 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
edb39244
AJ		 2799 sizeof(intel_dp->dpcd)) == 0)
2800 return false; /* aux transfer failed */
92fd8fd1 2801
577c7a50
DL		 2802 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2803 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2804 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2805
edb39244
AJ		 2806 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2807 return false; /* DPCD not present */
2808
2293bb5c
SK		 2809 /* Check if the panel supports PSR */
2810 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939
JN		 2811 if (is_edp(intel_dp)) {
2812 intel_dp_aux_native_read_retry(intel_dp, DP_PSR_SUPPORT,
2813 intel_dp->psr_dpcd,
2814 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 2815 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
2816 dev_priv->psr.sink_support = true;
50003939 2817 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 2818 }
50003939
JN		 2819 }
2820
edb39244
AJ		 2821 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2822 DP_DWN_STRM_PORT_PRESENT))
2823 return true; /* native DP sink */
2824
2825 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2826 return true; /* no per-port downstream info */
2827
2828 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2829 intel_dp->downstream_ports,
2830 DP_MAX_DOWNSTREAM_PORTS) == 0)
2831 return false; /* downstream port status fetch failed */
2832
2833 return true;
92fd8fd1
KP		 2834}
2835
0d198328
AJ		 2836static void
2837intel_dp_probe_oui(struct intel_dp *intel_dp)
2838{
2839 u8 buf[3];
2840
2841 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2842 return;
2843
351cfc34
DV		 2844 ironlake_edp_panel_vdd_on(intel_dp);
2845
0d198328
AJ		 2846 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2847 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2848 buf[0], buf[1], buf[2]);
2849
2850 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2851 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2852 buf[0], buf[1], buf[2]);
351cfc34
DV		 2853
2854 ironlake_edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 2855}
2856
a60f0e38
JB		 2857static bool
2858intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2859{
2860 int ret;
2861
2862 ret = intel_dp_aux_native_read_retry(intel_dp,
2863 DP_DEVICE_SERVICE_IRQ_VECTOR,
2864 sink_irq_vector, 1);
2865 if (!ret)
2866 return false;
2867
2868 return true;
2869}
2870
2871static void
2872intel_dp_handle_test_request(struct intel_dp *intel_dp)
2873{
2874 /* NAK by default */
9324cf7f 2875 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 2876}
2877
a4fc5ed6
KP		 2878/*
2879 * According to DP spec
2880 * 5.1.2:
2881 * 1. Read DPCD
2882 * 2. Configure link according to Receiver Capabilities
2883 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2884 * 4. Check link status on receipt of hot-plug interrupt
2885 */
2886
00c09d70 2887void
ea5b213a 2888intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 2889{
da63a9f2 2890 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 2891 u8 sink_irq_vector;
93f62dad 2892 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 2893
da63a9f2 2894 if (!intel_encoder->connectors_active)
d2b996ac 2895 return;
59cd09e1 2896
da63a9f2 2897 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 2898 return;
2899
92fd8fd1 2900 /* Try to read receiver status if the link appears to be up */
93f62dad 2901 if (!intel_dp_get_link_status(intel_dp, link_status)) {
ea5b213a 2902 intel_dp_link_down(intel_dp);
a4fc5ed6
KP		 2903 return;
2904 }
2905
92fd8fd1 2906 /* Now read the DPCD to see if it's actually running */
26d61aad 2907 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 2908 intel_dp_link_down(intel_dp);
2909 return;
2910 }
2911
a60f0e38
JB		 2912 /* Try to read the source of the interrupt */
2913 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2914 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2915 /* Clear interrupt source */
2916 intel_dp_aux_native_write_1(intel_dp,
2917 DP_DEVICE_SERVICE_IRQ_VECTOR,
2918 sink_irq_vector);
2919
2920 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2921 intel_dp_handle_test_request(intel_dp);
2922 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2923 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2924 }
2925
1ffdff13 2926 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 2927 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
da63a9f2 2928 drm_get_encoder_name(&intel_encoder->base));
33a34e4e
JB		 2929 intel_dp_start_link_train(intel_dp);
2930 intel_dp_complete_link_train(intel_dp);
3ab9c637 2931 intel_dp_stop_link_train(intel_dp);
33a34e4e 2932 }
a4fc5ed6 2933}
a4fc5ed6 2934
caf9ab24 2935/* XXX this is probably wrong for multiple downstream ports */
71ba9000 2936static enum drm_connector_status
26d61aad 2937intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 2938{
caf9ab24 2939 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 2940 uint8_t type;
2941
2942 if (!intel_dp_get_dpcd(intel_dp))
2943 return connector_status_disconnected;
2944
2945 /* if there's no downstream port, we're done */
2946 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 2947 return connector_status_connected;
caf9ab24
AJ		 2948
2949 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 2950 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2951 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 2952 uint8_t reg;
caf9ab24 2953 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
23235177 2954 &reg, 1))
caf9ab24 2955 return connector_status_unknown;
23235177
AJ		 2956 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2957 : connector_status_disconnected;
caf9ab24
AJ		 2958 }
2959
2960 /* If no HPD, poke DDC gently */
2961 if (drm_probe_ddc(&intel_dp->adapter))
26d61aad 2962 return connector_status_connected;
caf9ab24
AJ		 2963
2964 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 2965 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
2966 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2967 if (type == DP_DS_PORT_TYPE_VGA ||
2968 type == DP_DS_PORT_TYPE_NON_EDID)
2969 return connector_status_unknown;
2970 } else {
2971 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2972 DP_DWN_STRM_PORT_TYPE_MASK;
2973 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
2974 type == DP_DWN_STRM_PORT_TYPE_OTHER)
2975 return connector_status_unknown;
2976 }
caf9ab24
AJ		 2977
2978 /* Anything else is out of spec, warn and ignore */
2979 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 2980 return connector_status_disconnected;
71ba9000
AJ		 2981}
2982
5eb08b69 2983static enum drm_connector_status
a9756bb5 2984ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 2985{
30add22d 2986 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 2987 struct drm_i915_private *dev_priv = dev->dev_private;
2988 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5eb08b69
ZW		 2989 enum drm_connector_status status;
2990
fe16d949
CW		 2991 /* Can't disconnect eDP, but you can close the lid... */
2992 if (is_edp(intel_dp)) {
30add22d 2993 status = intel_panel_detect(dev);
fe16d949
CW		 2994 if (status == connector_status_unknown)
2995 status = connector_status_connected;
2996 return status;
2997 }
01cb9ea6 2998
1b469639
DL		 2999 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3000 return connector_status_disconnected;
3001
26d61aad 3002 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 3003}
3004
a4fc5ed6 3005static enum drm_connector_status
a9756bb5 3006g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 3007{
30add22d 3008 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a4fc5ed6 3009 struct drm_i915_private *dev_priv = dev->dev_private;
34f2be46 3010 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
10f76a38 3011 uint32_t bit;
5eb08b69 3012
35aad75f
JB		 3013 /* Can't disconnect eDP, but you can close the lid... */
3014 if (is_edp(intel_dp)) {
3015 enum drm_connector_status status;
3016
3017 status = intel_panel_detect(dev);
3018 if (status == connector_status_unknown)
3019 status = connector_status_connected;
3020 return status;
3021 }
3022
34f2be46
VS		 3023 switch (intel_dig_port->port) {
3024 case PORT_B:
26739f12 3025 bit = PORTB_HOTPLUG_LIVE_STATUS;
a4fc5ed6 3026 break;
34f2be46 3027 case PORT_C:
26739f12 3028 bit = PORTC_HOTPLUG_LIVE_STATUS;
a4fc5ed6 3029 break;
34f2be46 3030 case PORT_D:
26739f12 3031 bit = PORTD_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 3032 break;
3033 default:
3034 return connector_status_unknown;
3035 }
3036
10f76a38 3037 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 3038 return connector_status_disconnected;
3039
26d61aad 3040 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 3041}
3042
8c241fef
KP		 3043static struct edid *
3044intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
3045{
9cd300e0 3046 struct intel_connector *intel_connector = to_intel_connector(connector);
d6f24d0f 3047
9cd300e0
JN		 3048 /* use cached edid if we have one */
3049 if (intel_connector->edid) {
9cd300e0
JN		 3050 /* invalid edid */
3051 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 3052 return NULL;
3053
55e9edeb 3054 return drm_edid_duplicate(intel_connector->edid);
d6f24d0f 3055 }
8c241fef 3056
9cd300e0 3057 return drm_get_edid(connector, adapter);
8c241fef
KP		 3058}
3059
3060static int
3061intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
3062{
9cd300e0 3063 struct intel_connector *intel_connector = to_intel_connector(connector);
8c241fef 3064
9cd300e0
JN		 3065 /* use cached edid if we have one */
3066 if (intel_connector->edid) {
3067 /* invalid edid */
3068 if (IS_ERR(intel_connector->edid))
3069 return 0;
3070
3071 return intel_connector_update_modes(connector,
3072 intel_connector->edid);
d6f24d0f
JB		 3073 }
3074
9cd300e0 3075 return intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 3076}
3077
a9756bb5
ZW		 3078static enum drm_connector_status
3079intel_dp_detect(struct drm_connector *connector, bool force)
3080{
3081 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 3082 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3083 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 3084 struct drm_device *dev = connector->dev;
a9756bb5
ZW		 3085 enum drm_connector_status status;
3086 struct edid *edid = NULL;
3087
164c8598
CW		 3088 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3089 connector->base.id, drm_get_connector_name(connector));
3090
a9756bb5
ZW		 3091 intel_dp->has_audio = false;
3092
3093 if (HAS_PCH_SPLIT(dev))
3094 status = ironlake_dp_detect(intel_dp);
3095 else
3096 status = g4x_dp_detect(intel_dp);
1b9be9d0 3097
a9756bb5
ZW		 3098 if (status != connector_status_connected)
3099 return status;
3100
0d198328
AJ		 3101 intel_dp_probe_oui(intel_dp);
3102
c3e5f67b
DV		 3103 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3104 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 3105 } else {
8c241fef 3106 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
f684960e
CW		 3107 if (edid) {
3108 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 3109 kfree(edid);
3110 }
a9756bb5
ZW		 3111 }
3112
d63885da
PZ		 3113 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3114 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
a9756bb5 3115 return connector_status_connected;
a4fc5ed6
KP		 3116}
3117
3118static int intel_dp_get_modes(struct drm_connector *connector)
3119{
df0e9248 3120 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e 3121 struct intel_connector *intel_connector = to_intel_connector(connector);
fa90ecef 3122 struct drm_device *dev = connector->dev;
32f9d658 3123 int ret;
a4fc5ed6
KP		 3124
3125 /* We should parse the EDID data and find out if it has an audio sink
3126 */
3127
8c241fef 3128 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
f8779fda 3129 if (ret)
32f9d658
ZW		 3130 return ret;
3131
f8779fda 3132 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 3133 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 3134 struct drm_display_mode *mode;
dd06f90e
JN		 3135 mode = drm_mode_duplicate(dev,
3136 intel_connector->panel.fixed_mode);
f8779fda 3137 if (mode) {
32f9d658
ZW		 3138 drm_mode_probed_add(connector, mode);
3139 return 1;
3140 }
3141 }
3142 return 0;
a4fc5ed6
KP		 3143}
3144
1aad7ac0
CW		 3145static bool
3146intel_dp_detect_audio(struct drm_connector *connector)
3147{
3148 struct intel_dp *intel_dp = intel_attached_dp(connector);
3149 struct edid *edid;
3150 bool has_audio = false;
3151
8c241fef 3152 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1aad7ac0
CW		 3153 if (edid) {
3154 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 3155 kfree(edid);
3156 }
3157
3158 return has_audio;
3159}
3160
f684960e
CW		 3161static int
3162intel_dp_set_property(struct drm_connector *connector,
3163 struct drm_property *property,
3164 uint64_t val)
3165{
e953fd7b 3166 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 3167 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 3168 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3169 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 3170 int ret;
3171
662595df 3172 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 3173 if (ret)
3174 return ret;
3175
3f43c48d 3176 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 3177 int i = val;
3178 bool has_audio;
3179
3180 if (i == intel_dp->force_audio)
f684960e
CW		 3181 return 0;
3182
1aad7ac0 3183 intel_dp->force_audio = i;
f684960e 3184
c3e5f67b 3185 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 3186 has_audio = intel_dp_detect_audio(connector);
3187 else
c3e5f67b 3188 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 3189
3190 if (has_audio == intel_dp->has_audio)
f684960e
CW		 3191 return 0;
3192
1aad7ac0 3193 intel_dp->has_audio = has_audio;
f684960e
CW		 3194 goto done;
3195 }
3196
e953fd7b 3197 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 3198 bool old_auto = intel_dp->color_range_auto;
3199 uint32_t old_range = intel_dp->color_range;
3200
55bc60db
VS		 3201 switch (val) {
3202 case INTEL_BROADCAST_RGB_AUTO:
3203 intel_dp->color_range_auto = true;
3204 break;
3205 case INTEL_BROADCAST_RGB_FULL:
3206 intel_dp->color_range_auto = false;
3207 intel_dp->color_range = 0;
3208 break;
3209 case INTEL_BROADCAST_RGB_LIMITED:
3210 intel_dp->color_range_auto = false;
3211 intel_dp->color_range = DP_COLOR_RANGE_16_235;
3212 break;
3213 default:
3214 return -EINVAL;
3215 }
ae4edb80
DV		 3216
3217 if (old_auto == intel_dp->color_range_auto &&
3218 old_range == intel_dp->color_range)
3219 return 0;
3220
e953fd7b
CW		 3221 goto done;
3222 }
3223
53b41837
YN		 3224 if (is_edp(intel_dp) &&
3225 property == connector->dev->mode_config.scaling_mode_property) {
3226 if (val == DRM_MODE_SCALE_NONE) {
3227 DRM_DEBUG_KMS("no scaling not supported\n");
3228 return -EINVAL;
3229 }
3230
3231 if (intel_connector->panel.fitting_mode == val) {
3232 /* the eDP scaling property is not changed */
3233 return 0;
3234 }
3235 intel_connector->panel.fitting_mode = val;
3236
3237 goto done;
3238 }
3239
f684960e
CW		 3240 return -EINVAL;
3241
3242done:
c0c36b94
CW		 3243 if (intel_encoder->base.crtc)
3244 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 3245
3246 return 0;
3247}
3248
a4fc5ed6 3249static void
73845adf 3250intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 3251{
1d508706 3252 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 3253
9cd300e0
JN		 3254 if (!IS_ERR_OR_NULL(intel_connector->edid))
3255 kfree(intel_connector->edid);
3256
acd8db10
PZ		 3257 /* Can't call is_edp() since the encoder may have been destroyed
3258 * already. */
3259 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 3260 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 3261
a4fc5ed6 3262 drm_connector_cleanup(connector);
55f78c43 3263 kfree(connector);
a4fc5ed6
KP		 3264}
3265
00c09d70 3266void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 3267{
da63a9f2
PZ		 3268 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3269 struct intel_dp *intel_dp = &intel_dig_port->dp;
bd173813 3270 struct drm_device *dev = intel_dp_to_dev(intel_dp);
24d05927
DV		 3271
3272 i2c_del_adapter(&intel_dp->adapter);
3273 drm_encoder_cleanup(encoder);
bd943159
KP		 3274 if (is_edp(intel_dp)) {
3275 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
bd173813 3276 mutex_lock(&dev->mode_config.mutex);
bd943159 3277 ironlake_panel_vdd_off_sync(intel_dp);
bd173813 3278 mutex_unlock(&dev->mode_config.mutex);
bd943159 3279 }
da63a9f2 3280 kfree(intel_dig_port);
24d05927
DV		 3281}
3282
a4fc5ed6 3283static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 3284 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 3285 .detect = intel_dp_detect,
3286 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 3287 .set_property = intel_dp_set_property,
73845adf 3288 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 3289};
3290
3291static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3292 .get_modes = intel_dp_get_modes,
3293 .mode_valid = intel_dp_mode_valid,
df0e9248 3294 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 3295};
3296
a4fc5ed6 3297static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 3298 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 3299};
3300
995b6762 3301static void
21d40d37 3302intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 3303{
fa90ecef 3304 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
c8110e52 3305
885a5014 3306 intel_dp_check_link_status(intel_dp);
c8110e52 3307}
6207937d 3308
e3421a18
ZW		 3309/* Return which DP Port should be selected for Transcoder DP control */
3310int
0206e353 3311intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 3312{
3313 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 3314 struct intel_encoder *intel_encoder;
3315 struct intel_dp *intel_dp;
e3421a18 3316
fa90ecef
PZ		 3317 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3318 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 3319
fa90ecef
PZ		 3320 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3321 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 3322 return intel_dp->output_reg;
e3421a18 3323 }
ea5b213a 3324
e3421a18
ZW		 3325 return -1;
3326}
3327
36e83a18 3328/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 3329bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 3330{
3331 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 3332 union child_device_config *p_child;
36e83a18 3333 int i;
5d8a7752
VS		 3334 static const short port_mapping[] = {
3335 [PORT_B] = PORT_IDPB,
3336 [PORT_C] = PORT_IDPC,
3337 [PORT_D] = PORT_IDPD,
3338 };
36e83a18 3339
3b32a35b
VS		 3340 if (port == PORT_A)
3341 return true;
3342
41aa3448 3343 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 3344 return false;
3345
41aa3448
RV		 3346 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3347 p_child = dev_priv->vbt.child_dev + i;
36e83a18 3348
5d8a7752 3349 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 3350 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
3351 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 3352 return true;
3353 }
3354 return false;
3355}
3356
f684960e
CW		 3357static void
3358intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3359{
53b41837
YN		 3360 struct intel_connector *intel_connector = to_intel_connector(connector);
3361
3f43c48d 3362 intel_attach_force_audio_property(connector);
e953fd7b 3363 intel_attach_broadcast_rgb_property(connector);
55bc60db 3364 intel_dp->color_range_auto = true;
53b41837
YN		 3365
3366 if (is_edp(intel_dp)) {
3367 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 3368 drm_object_attach_property(
3369 &connector->base,
53b41837 3370 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 3371 DRM_MODE_SCALE_ASPECT);
3372 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 3373 }
f684960e
CW		 3374}
3375
67a54566
DV		 3376static void
3377intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 3378 struct intel_dp *intel_dp,
3379 struct edp_power_seq *out)
67a54566
DV		 3380{
3381 struct drm_i915_private *dev_priv = dev->dev_private;
3382 struct edp_power_seq cur, vbt, spec, final;
3383 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 3384 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420
JB		 3385
3386 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 3387 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 3388 pp_on_reg = PCH_PP_ON_DELAYS;
3389 pp_off_reg = PCH_PP_OFF_DELAYS;
3390 pp_div_reg = PCH_PP_DIVISOR;
3391 } else {
bf13e81b
JN		 3392 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3393
3394 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
3395 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3396 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3397 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 3398 }
67a54566
DV		 3399
3400 /* Workaround: Need to write PP_CONTROL with the unlock key as
3401 * the very first thing. */
453c5420 3402 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 3403 I915_WRITE(pp_ctrl_reg, pp);
67a54566 3404
453c5420
JB		 3405 pp_on = I915_READ(pp_on_reg);
3406 pp_off = I915_READ(pp_off_reg);
3407 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 3408
3409 /* Pull timing values out of registers */
3410 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3411 PANEL_POWER_UP_DELAY_SHIFT;
3412
3413 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3414 PANEL_LIGHT_ON_DELAY_SHIFT;
3415
3416 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3417 PANEL_LIGHT_OFF_DELAY_SHIFT;
3418
3419 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3420 PANEL_POWER_DOWN_DELAY_SHIFT;
3421
3422 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3423 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3424
3425 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3426 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3427
41aa3448 3428 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 3429
3430 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3431 * our hw here, which are all in 100usec. */
3432 spec.t1_t3 = 210 * 10;
3433 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3434 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3435 spec.t10 = 500 * 10;
3436 /* This one is special and actually in units of 100ms, but zero
3437 * based in the hw (so we need to add 100 ms). But the sw vbt
3438 * table multiplies it with 1000 to make it in units of 100usec,
3439 * too. */
3440 spec.t11_t12 = (510 + 100) * 10;
3441
3442 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3443 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3444
3445 /* Use the max of the register settings and vbt. If both are
3446 * unset, fall back to the spec limits. */
3447#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
3448 spec.field : \
3449 max(cur.field, vbt.field))
3450 assign_final(t1_t3);
3451 assign_final(t8);
3452 assign_final(t9);
3453 assign_final(t10);
3454 assign_final(t11_t12);
3455#undef assign_final
3456
3457#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
3458 intel_dp->panel_power_up_delay = get_delay(t1_t3);
3459 intel_dp->backlight_on_delay = get_delay(t8);
3460 intel_dp->backlight_off_delay = get_delay(t9);
3461 intel_dp->panel_power_down_delay = get_delay(t10);
3462 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3463#undef get_delay
3464
f30d26e4
JN		 3465 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3466 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
3467 intel_dp->panel_power_cycle_delay);
3468
3469 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3470 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
3471
3472 if (out)
3473 *out = final;
3474}
3475
3476static void
3477intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
3478 struct intel_dp *intel_dp,
3479 struct edp_power_seq *seq)
3480{
3481 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 3482 u32 pp_on, pp_off, pp_div, port_sel = 0;
3483 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
3484 int pp_on_reg, pp_off_reg, pp_div_reg;
3485
3486 if (HAS_PCH_SPLIT(dev)) {
3487 pp_on_reg = PCH_PP_ON_DELAYS;
3488 pp_off_reg = PCH_PP_OFF_DELAYS;
3489 pp_div_reg = PCH_PP_DIVISOR;
3490 } else {
bf13e81b
JN		 3491 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3492
3493 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3494 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3495 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 3496 }
3497
67a54566 3498 /* And finally store the new values in the power sequencer. */
f30d26e4
JN		 3499 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
3500 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
3501 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
3502 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 3503 /* Compute the divisor for the pp clock, simply match the Bspec
3504 * formula. */
453c5420 3505 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 3506 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 3507 << PANEL_POWER_CYCLE_DELAY_SHIFT);
3508
3509 /* Haswell doesn't have any port selection bits for the panel
3510 * power sequencer any more. */
bc7d38a4 3511 if (IS_VALLEYVIEW(dev)) {
bf13e81b
JN		 3512 if (dp_to_dig_port(intel_dp)->port == PORT_B)
3513 port_sel = PANEL_PORT_SELECT_DPB_VLV;
3514 else
3515 port_sel = PANEL_PORT_SELECT_DPC_VLV;
bc7d38a4
ID		 3516 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
3517 if (dp_to_dig_port(intel_dp)->port == PORT_A)
a24c144c 3518 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 3519 else
a24c144c 3520 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 3521 }
3522
453c5420
JB		 3523 pp_on |= port_sel;
3524
3525 I915_WRITE(pp_on_reg, pp_on);
3526 I915_WRITE(pp_off_reg, pp_off);
3527 I915_WRITE(pp_div_reg, pp_div);
67a54566 3528
67a54566 3529 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 3530 I915_READ(pp_on_reg),
3531 I915_READ(pp_off_reg),
3532 I915_READ(pp_div_reg));
f684960e
CW		 3533}
3534
ed92f0b2
PZ		 3535static bool intel_edp_init_connector(struct intel_dp *intel_dp,
3536 struct intel_connector *intel_connector)
3537{
3538 struct drm_connector *connector = &intel_connector->base;
3539 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3540 struct drm_device *dev = intel_dig_port->base.base.dev;
3541 struct drm_i915_private *dev_priv = dev->dev_private;
3542 struct drm_display_mode *fixed_mode = NULL;
3543 struct edp_power_seq power_seq = { 0 };
3544 bool has_dpcd;
3545 struct drm_display_mode *scan;
3546 struct edid *edid;
3547
3548 if (!is_edp(intel_dp))
3549 return true;
3550
3551 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
3552
3553 /* Cache DPCD and EDID for edp. */
3554 ironlake_edp_panel_vdd_on(intel_dp);
3555 has_dpcd = intel_dp_get_dpcd(intel_dp);
3556 ironlake_edp_panel_vdd_off(intel_dp, false);
3557
3558 if (has_dpcd) {
3559 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3560 dev_priv->no_aux_handshake =
3561 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3562 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3563 } else {
3564 /* if this fails, presume the device is a ghost */
3565 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 3566 return false;
3567 }
3568
3569 /* We now know it's not a ghost, init power sequence regs. */
3570 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
3571 &power_seq);
3572
ed92f0b2
PZ		 3573 edid = drm_get_edid(connector, &intel_dp->adapter);
3574 if (edid) {
3575 if (drm_add_edid_modes(connector, edid)) {
3576 drm_mode_connector_update_edid_property(connector,
3577 edid);
3578 drm_edid_to_eld(connector, edid);
3579 } else {
3580 kfree(edid);
3581 edid = ERR_PTR(-EINVAL);
3582 }
3583 } else {
3584 edid = ERR_PTR(-ENOENT);
3585 }
3586 intel_connector->edid = edid;
3587
3588 /* prefer fixed mode from EDID if available */
3589 list_for_each_entry(scan, &connector->probed_modes, head) {
3590 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3591 fixed_mode = drm_mode_duplicate(dev, scan);
3592 break;
3593 }
3594 }
3595
3596 /* fallback to VBT if available for eDP */
3597 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3598 fixed_mode = drm_mode_duplicate(dev,
3599 dev_priv->vbt.lfp_lvds_vbt_mode);
3600 if (fixed_mode)
3601 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3602 }
3603
ed92f0b2
PZ		 3604 intel_panel_init(&intel_connector->panel, fixed_mode);
3605 intel_panel_setup_backlight(connector);
3606
3607 return true;
3608}
3609
16c25533 3610bool
f0fec3f2
PZ		 3611intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
3612 struct intel_connector *intel_connector)
a4fc5ed6 3613{
f0fec3f2
PZ		 3614 struct drm_connector *connector = &intel_connector->base;
3615 struct intel_dp *intel_dp = &intel_dig_port->dp;
3616 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3617 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 3618 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 3619 enum port port = intel_dig_port->port;
5eb08b69 3620 const char *name = NULL;
b2a14755 3621 int type, error;
a4fc5ed6 3622
0767935e
DV		 3623 /* Preserve the current hw state. */
3624 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 3625 intel_dp->attached_connector = intel_connector;
3d3dc149 3626
3b32a35b 3627 if (intel_dp_is_edp(dev, port))
b329530c 3628 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 3629 else
3630 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 3631
f7d24902
ID		 3632 /*
3633 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3634 * for DP the encoder type can be set by the caller to
3635 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3636 */
3637 if (type == DRM_MODE_CONNECTOR_eDP)
3638 intel_encoder->type = INTEL_OUTPUT_EDP;
3639
e7281eab
ID		 3640 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3641 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3642 port_name(port));
3643
b329530c 3644 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 3645 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3646
a4fc5ed6
KP		 3647 connector->interlace_allowed = true;
3648 connector->doublescan_allowed = 0;
3649
f0fec3f2
PZ		 3650 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
3651 ironlake_panel_vdd_work);
a4fc5ed6 3652
df0e9248 3653 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 3654 drm_sysfs_connector_add(connector);
3655
affa9354 3656 if (HAS_DDI(dev))
bcbc889b
PZ		 3657 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3658 else
3659 intel_connector->get_hw_state = intel_connector_get_hw_state;
3660
9ed35ab1
PZ		 3661 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
3662 if (HAS_DDI(dev)) {
3663 switch (intel_dig_port->port) {
3664 case PORT_A:
3665 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
3666 break;
3667 case PORT_B:
3668 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
3669 break;
3670 case PORT_C:
3671 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
3672 break;
3673 case PORT_D:
3674 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
3675 break;
3676 default:
3677 BUG();
3678 }
3679 }
e8cb4558 3680
a4fc5ed6 3681 /* Set up the DDC bus. */
ab9d7c30
PZ		 3682 switch (port) {
3683 case PORT_A:
1d843f9d 3684 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 3685 name = "DPDDC-A";
3686 break;
3687 case PORT_B:
1d843f9d 3688 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 3689 name = "DPDDC-B";
3690 break;
3691 case PORT_C:
1d843f9d 3692 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 3693 name = "DPDDC-C";
3694 break;
3695 case PORT_D:
1d843f9d 3696 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 3697 name = "DPDDC-D";
3698 break;
3699 default:
ad1c0b19 3700 BUG();
5eb08b69
ZW		 3701 }
3702
b2a14755
PZ		 3703 error = intel_dp_i2c_init(intel_dp, intel_connector, name);
3704 WARN(error, "intel_dp_i2c_init failed with error %d for port %c\n",
3705 error, port_name(port));
c1f05264 3706
2b28bb1b
RV		 3707 intel_dp->psr_setup_done = false;
3708
b2f246a8 3709 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
15b1d171
PZ		 3710 i2c_del_adapter(&intel_dp->adapter);
3711 if (is_edp(intel_dp)) {
3712 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3713 mutex_lock(&dev->mode_config.mutex);
3714 ironlake_panel_vdd_off_sync(intel_dp);
3715 mutex_unlock(&dev->mode_config.mutex);
3716 }
b2f246a8
PZ		 3717 drm_sysfs_connector_remove(connector);
3718 drm_connector_cleanup(connector);
16c25533 3719 return false;
b2f246a8 3720 }
32f9d658 3721
f684960e
CW		 3722 intel_dp_add_properties(intel_dp, connector);
3723
a4fc5ed6
KP		 3724 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3725 * 0xd. Failure to do so will result in spurious interrupts being
3726 * generated on the port when a cable is not attached.
3727 */
3728 if (IS_G4X(dev) && !IS_GM45(dev)) {
3729 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3730 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3731 }
16c25533
PZ		 3732
3733 return true;
a4fc5ed6 3734}
f0fec3f2
PZ		 3735
3736void
3737intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3738{
3739 struct intel_digital_port *intel_dig_port;
3740 struct intel_encoder *intel_encoder;
3741 struct drm_encoder *encoder;
3742 struct intel_connector *intel_connector;
3743
b14c5679 3744 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 3745 if (!intel_dig_port)
3746 return;
3747
b14c5679 3748 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
f0fec3f2
PZ		 3749 if (!intel_connector) {
3750 kfree(intel_dig_port);
3751 return;
3752 }
3753
3754 intel_encoder = &intel_dig_port->base;
3755 encoder = &intel_encoder->base;
3756
3757 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3758 DRM_MODE_ENCODER_TMDS);
3759
5bfe2ac0 3760 intel_encoder->compute_config = intel_dp_compute_config;
b934223d 3761 intel_encoder->mode_set = intel_dp_mode_set;
00c09d70
PZ		 3762 intel_encoder->disable = intel_disable_dp;
3763 intel_encoder->post_disable = intel_post_disable_dp;
3764 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 3765 intel_encoder->get_config = intel_dp_get_config;
ab1f90f9 3766 if (IS_VALLEYVIEW(dev)) {
ecff4f3b 3767 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 3768 intel_encoder->pre_enable = vlv_pre_enable_dp;
3769 intel_encoder->enable = vlv_enable_dp;
3770 } else {
ecff4f3b
JN		 3771 intel_encoder->pre_enable = g4x_pre_enable_dp;
3772 intel_encoder->enable = g4x_enable_dp;
ab1f90f9 3773 }
f0fec3f2 3774
174edf1f 3775 intel_dig_port->port = port;
f0fec3f2
PZ		 3776 intel_dig_port->dp.output_reg = output_reg;
3777
00c09d70 3778 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
f0fec3f2
PZ		 3779 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3780 intel_encoder->cloneable = false;
3781 intel_encoder->hot_plug = intel_dp_hot_plug;
3782
15b1d171
PZ		 3783 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
3784 drm_encoder_cleanup(encoder);
3785 kfree(intel_dig_port);
b2f246a8 3786 kfree(intel_connector);
15b1d171 3787 }
f0fec3f2 3788}
Linux 6.x block layer and io_uring tree(s)