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Merge tag 'arm64-stable' of git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas...
[linux-block.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
760285e7
DH		 31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_edid.h>
a4fc5ed6 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
a4fc5ed6 37#include "i915_drv.h"
a4fc5ed6 38
a4fc5ed6
KP		 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
cfcb0fc9
JB		 41/**
42 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
43 * @intel_dp: DP struct
44 *
45 * If a CPU or PCH DP output is attached to an eDP panel, this function
46 * will return true, and false otherwise.
47 */
48static bool is_edp(struct intel_dp *intel_dp)
49{
da63a9f2
PZ		 50 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
51
52 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 53}
54
68b4d824 55static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 56{
68b4d824
ID		 57 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
58
59 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 60}
61
df0e9248
CW		 62static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
63{
fa90ecef 64 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 65}
66
ea5b213a 67static void intel_dp_link_down(struct intel_dp *intel_dp);
a4fc5ed6 68
a4fc5ed6 69static int
ea5b213a 70intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 71{
7183dc29 72 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 73
74 switch (max_link_bw) {
75 case DP_LINK_BW_1_62:
76 case DP_LINK_BW_2_7:
77 break;
d4eead50
ID		 78 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
79 max_link_bw = DP_LINK_BW_2_7;
80 break;
a4fc5ed6 81 default:
d4eead50
ID		 82 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
83 max_link_bw);
a4fc5ed6
KP		 84 max_link_bw = DP_LINK_BW_1_62;
85 break;
86 }
87 return max_link_bw;
88}
89
cd9dde44
AJ		 90/*
91 * The units on the numbers in the next two are... bizarre. Examples will
92 * make it clearer; this one parallels an example in the eDP spec.
93 *
94 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
95 *
96 * 270000 * 1 * 8 / 10 == 216000
97 *
98 * The actual data capacity of that configuration is 2.16Gbit/s, so the
99 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
100 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
101 * 119000. At 18bpp that's 2142000 kilobits per second.
102 *
103 * Thus the strange-looking division by 10 in intel_dp_link_required, to
104 * get the result in decakilobits instead of kilobits.
105 */
106
a4fc5ed6 107static int
c898261c 108intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 109{
cd9dde44 110 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 111}
112
fe27d53e
DA		 113static int
114intel_dp_max_data_rate(int max_link_clock, int max_lanes)
115{
116 return (max_link_clock * max_lanes * 8) / 10;
117}
118
a4fc5ed6
KP		 119static int
120intel_dp_mode_valid(struct drm_connector *connector,
121 struct drm_display_mode *mode)
122{
df0e9248 123 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 124 struct intel_connector *intel_connector = to_intel_connector(connector);
125 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 126 int target_clock = mode->clock;
127 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 128
dd06f90e
JN		 129 if (is_edp(intel_dp) && fixed_mode) {
130 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 131 return MODE_PANEL;
132
dd06f90e 133 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 134 return MODE_PANEL;
03afc4a2
DV		 135
136 target_clock = fixed_mode->clock;
7de56f43
ZY		 137 }
138
36008365
DV		 139 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
140 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
141
142 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
143 mode_rate = intel_dp_link_required(target_clock, 18);
144
145 if (mode_rate > max_rate)
c4867936 146 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 147
148 if (mode->clock < 10000)
149 return MODE_CLOCK_LOW;
150
0af78a2b
DV		 151 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
152 return MODE_H_ILLEGAL;
153
a4fc5ed6
KP		 154 return MODE_OK;
155}
156
157static uint32_t
158pack_aux(uint8_t *src, int src_bytes)
159{
160 int i;
161 uint32_t v = 0;
162
163 if (src_bytes > 4)
164 src_bytes = 4;
165 for (i = 0; i < src_bytes; i++)
166 v |= ((uint32_t) src[i]) << ((3-i) * 8);
167 return v;
168}
169
170static void
171unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
172{
173 int i;
174 if (dst_bytes > 4)
175 dst_bytes = 4;
176 for (i = 0; i < dst_bytes; i++)
177 dst[i] = src >> ((3-i) * 8);
178}
179
fb0f8fbf
KP		 180/* hrawclock is 1/4 the FSB frequency */
181static int
182intel_hrawclk(struct drm_device *dev)
183{
184 struct drm_i915_private *dev_priv = dev->dev_private;
185 uint32_t clkcfg;
186
9473c8f4
VP		 187 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
188 if (IS_VALLEYVIEW(dev))
189 return 200;
190
fb0f8fbf
KP		 191 clkcfg = I915_READ(CLKCFG);
192 switch (clkcfg & CLKCFG_FSB_MASK) {
193 case CLKCFG_FSB_400:
194 return 100;
195 case CLKCFG_FSB_533:
196 return 133;
197 case CLKCFG_FSB_667:
198 return 166;
199 case CLKCFG_FSB_800:
200 return 200;
201 case CLKCFG_FSB_1067:
202 return 266;
203 case CLKCFG_FSB_1333:
204 return 333;
205 /* these two are just a guess; one of them might be right */
206 case CLKCFG_FSB_1600:
207 case CLKCFG_FSB_1600_ALT:
208 return 400;
209 default:
210 return 133;
211 }
212}
213
ebf33b18
KP		 214static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
215{
30add22d 216 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18 217 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420 218 u32 pp_stat_reg;
ebf33b18 219
453c5420
JB		 220 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
221 return (I915_READ(pp_stat_reg) & PP_ON) != 0;
ebf33b18
KP		 222}
223
224static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
225{
30add22d 226 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18 227 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420 228 u32 pp_ctrl_reg;
ebf33b18 229
453c5420
JB		 230 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
231 return (I915_READ(pp_ctrl_reg) & EDP_FORCE_VDD) != 0;
ebf33b18
KP		 232}
233
9b984dae
KP		 234static void
235intel_dp_check_edp(struct intel_dp *intel_dp)
236{
30add22d 237 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 238 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420 239 u32 pp_stat_reg, pp_ctrl_reg;
ebf33b18 240
9b984dae
KP		 241 if (!is_edp(intel_dp))
242 return;
453c5420
JB		 243
244 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
245 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
246
ebf33b18 247 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 248 WARN(1, "eDP powered off while attempting aux channel communication.\n");
249 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
453c5420
JB		 250 I915_READ(pp_stat_reg),
251 I915_READ(pp_ctrl_reg));
9b984dae
KP		 252 }
253}
254
9ee32fea
DV		 255static uint32_t
256intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
257{
258 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
259 struct drm_device *dev = intel_dig_port->base.base.dev;
260 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 261 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 262 uint32_t status;
263 bool done;
264
ef04f00d 265#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 266 if (has_aux_irq)
b18ac466 267 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 268 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 269 else
270 done = wait_for_atomic(C, 10) == 0;
271 if (!done)
272 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
273 has_aux_irq);
274#undef C
275
276 return status;
277}
278
a4fc5ed6 279static int
ea5b213a 280intel_dp_aux_ch(struct intel_dp *intel_dp,
a4fc5ed6
KP		 281 uint8_t *send, int send_bytes,
282 uint8_t *recv, int recv_size)
283{
174edf1f
PZ		 284 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
285 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 286 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 287 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
a4fc5ed6 288 uint32_t ch_data = ch_ctl + 4;
9ee32fea 289 int i, ret, recv_bytes;
a4fc5ed6 290 uint32_t status;
fb0f8fbf 291 uint32_t aux_clock_divider;
6b4e0a93 292 int try, precharge;
9ee32fea
DV		 293 bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
294
295 /* dp aux is extremely sensitive to irq latency, hence request the
296 * lowest possible wakeup latency and so prevent the cpu from going into
297 * deep sleep states.
298 */
299 pm_qos_update_request(&dev_priv->pm_qos, 0);
a4fc5ed6 300
9b984dae 301 intel_dp_check_edp(intel_dp);
a4fc5ed6 302 /* The clock divider is based off the hrawclk,
fb0f8fbf
KP		 303 * and would like to run at 2MHz. So, take the
304 * hrawclk value and divide by 2 and use that
6176b8f9
JB		 305 *
306 * Note that PCH attached eDP panels should use a 125MHz input
307 * clock divider.
a4fc5ed6 308 */
a62d0834
ID		 309 if (IS_VALLEYVIEW(dev)) {
310 aux_clock_divider = 100;
311 } else if (intel_dig_port->port == PORT_A) {
affa9354 312 if (HAS_DDI(dev))
b2b877ff
PZ		 313 aux_clock_divider = DIV_ROUND_CLOSEST(
314 intel_ddi_get_cdclk_freq(dev_priv), 2000);
9473c8f4 315 else if (IS_GEN6(dev) || IS_GEN7(dev))
1a2eb460 316 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18
ZW		 317 else
318 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
2c55c336
JN		 319 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
320 /* Workaround for non-ULT HSW */
321 aux_clock_divider = 74;
322 } else if (HAS_PCH_SPLIT(dev)) {
6b3ec1c9 323 aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 324 } else {
5eb08b69 325 aux_clock_divider = intel_hrawclk(dev) / 2;
2c55c336 326 }
5eb08b69 327
6b4e0a93
DV		 328 if (IS_GEN6(dev))
329 precharge = 3;
330 else
331 precharge = 5;
332
11bee43e
JB		 333 /* Try to wait for any previous AUX channel activity */
334 for (try = 0; try < 3; try++) {
ef04f00d 335 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 336 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
337 break;
338 msleep(1);
339 }
340
341 if (try == 3) {
342 WARN(1, "dp_aux_ch not started status 0x%08x\n",
343 I915_READ(ch_ctl));
9ee32fea
DV		 344 ret = -EBUSY;
345 goto out;
4f7f7b7e
CW		 346 }
347
fb0f8fbf
KP		 348 /* Must try at least 3 times according to DP spec */
349 for (try = 0; try < 5; try++) {
350 /* Load the send data into the aux channel data registers */
4f7f7b7e
CW		 351 for (i = 0; i < send_bytes; i += 4)
352 I915_WRITE(ch_data + i,
353 pack_aux(send + i, send_bytes - i));
0206e353 354
fb0f8fbf 355 /* Send the command and wait for it to complete */
4f7f7b7e
CW		 356 I915_WRITE(ch_ctl,
357 DP_AUX_CH_CTL_SEND_BUSY |
9ee32fea 358 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
4f7f7b7e
CW		 359 DP_AUX_CH_CTL_TIME_OUT_400us |
360 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
361 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
362 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
363 DP_AUX_CH_CTL_DONE |
364 DP_AUX_CH_CTL_TIME_OUT_ERROR |
365 DP_AUX_CH_CTL_RECEIVE_ERROR);
9ee32fea
DV		 366
367 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
0206e353 368
fb0f8fbf 369 /* Clear done status and any errors */
4f7f7b7e
CW		 370 I915_WRITE(ch_ctl,
371 status |
372 DP_AUX_CH_CTL_DONE |
373 DP_AUX_CH_CTL_TIME_OUT_ERROR |
374 DP_AUX_CH_CTL_RECEIVE_ERROR);
d7e96fea
AJ		 375
376 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
377 DP_AUX_CH_CTL_RECEIVE_ERROR))
378 continue;
4f7f7b7e 379 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 380 break;
381 }
382
a4fc5ed6 383 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 384 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 385 ret = -EBUSY;
386 goto out;
a4fc5ed6
KP		 387 }
388
389 /* Check for timeout or receive error.
390 * Timeouts occur when the sink is not connected
391 */
a5b3da54 392 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 393 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 394 ret = -EIO;
395 goto out;
a5b3da54 396 }
1ae8c0a5
KP		 397
398 /* Timeouts occur when the device isn't connected, so they're
399 * "normal" -- don't fill the kernel log with these */
a5b3da54 400 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 401 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 402 ret = -ETIMEDOUT;
403 goto out;
a4fc5ed6
KP		 404 }
405
406 /* Unload any bytes sent back from the other side */
407 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
408 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 409 if (recv_bytes > recv_size)
410 recv_bytes = recv_size;
0206e353 411
4f7f7b7e
CW		 412 for (i = 0; i < recv_bytes; i += 4)
413 unpack_aux(I915_READ(ch_data + i),
414 recv + i, recv_bytes - i);
a4fc5ed6 415
9ee32fea
DV		 416 ret = recv_bytes;
417out:
418 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
419
420 return ret;
a4fc5ed6
KP		 421}
422
423/* Write data to the aux channel in native mode */
424static int
ea5b213a 425intel_dp_aux_native_write(struct intel_dp *intel_dp,
a4fc5ed6
KP		 426 uint16_t address, uint8_t *send, int send_bytes)
427{
428 int ret;
429 uint8_t msg[20];
430 int msg_bytes;
431 uint8_t ack;
432
9b984dae 433 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 434 if (send_bytes > 16)
435 return -1;
436 msg[0] = AUX_NATIVE_WRITE << 4;
437 msg[1] = address >> 8;
eebc863e 438 msg[2] = address & 0xff;
a4fc5ed6
KP		 439 msg[3] = send_bytes - 1;
440 memcpy(&msg[4], send, send_bytes);
441 msg_bytes = send_bytes + 4;
442 for (;;) {
ea5b213a 443 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
a4fc5ed6
KP		 444 if (ret < 0)
445 return ret;
446 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
447 break;
448 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
449 udelay(100);
450 else
a5b3da54 451 return -EIO;
a4fc5ed6
KP		 452 }
453 return send_bytes;
454}
455
456/* Write a single byte to the aux channel in native mode */
457static int
ea5b213a 458intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
a4fc5ed6
KP		 459 uint16_t address, uint8_t byte)
460{
ea5b213a 461 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
a4fc5ed6
KP		 462}
463
464/* read bytes from a native aux channel */
465static int
ea5b213a 466intel_dp_aux_native_read(struct intel_dp *intel_dp,
a4fc5ed6
KP		 467 uint16_t address, uint8_t *recv, int recv_bytes)
468{
469 uint8_t msg[4];
470 int msg_bytes;
471 uint8_t reply[20];
472 int reply_bytes;
473 uint8_t ack;
474 int ret;
475
9b984dae 476 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 477 msg[0] = AUX_NATIVE_READ << 4;
478 msg[1] = address >> 8;
479 msg[2] = address & 0xff;
480 msg[3] = recv_bytes - 1;
481
482 msg_bytes = 4;
483 reply_bytes = recv_bytes + 1;
484
485 for (;;) {
ea5b213a 486 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
a4fc5ed6 487 reply, reply_bytes);
a5b3da54
KP		 488 if (ret == 0)
489 return -EPROTO;
490 if (ret < 0)
a4fc5ed6
KP		 491 return ret;
492 ack = reply[0];
493 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
494 memcpy(recv, reply + 1, ret - 1);
495 return ret - 1;
496 }
497 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
498 udelay(100);
499 else
a5b3da54 500 return -EIO;
a4fc5ed6
KP		 501 }
502}
503
504static int
ab2c0672
DA		 505intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
506 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 507{
ab2c0672 508 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
ea5b213a
CW		 509 struct intel_dp *intel_dp = container_of(adapter,
510 struct intel_dp,
511 adapter);
ab2c0672
DA		 512 uint16_t address = algo_data->address;
513 uint8_t msg[5];
514 uint8_t reply[2];
8316f337 515 unsigned retry;
ab2c0672
DA		 516 int msg_bytes;
517 int reply_bytes;
518 int ret;
519
9b984dae 520 intel_dp_check_edp(intel_dp);
ab2c0672
DA		 521 /* Set up the command byte */
522 if (mode & MODE_I2C_READ)
523 msg[0] = AUX_I2C_READ << 4;
524 else
525 msg[0] = AUX_I2C_WRITE << 4;
526
527 if (!(mode & MODE_I2C_STOP))
528 msg[0] |= AUX_I2C_MOT << 4;
a4fc5ed6 529
ab2c0672
DA		 530 msg[1] = address >> 8;
531 msg[2] = address;
532
533 switch (mode) {
534 case MODE_I2C_WRITE:
535 msg[3] = 0;
536 msg[4] = write_byte;
537 msg_bytes = 5;
538 reply_bytes = 1;
539 break;
540 case MODE_I2C_READ:
541 msg[3] = 0;
542 msg_bytes = 4;
543 reply_bytes = 2;
544 break;
545 default:
546 msg_bytes = 3;
547 reply_bytes = 1;
548 break;
549 }
550
8316f337
DF		 551 for (retry = 0; retry < 5; retry++) {
552 ret = intel_dp_aux_ch(intel_dp,
553 msg, msg_bytes,
554 reply, reply_bytes);
ab2c0672 555 if (ret < 0) {
3ff99164 556 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
ab2c0672
DA		 557 return ret;
558 }
8316f337
DF		 559
560 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
561 case AUX_NATIVE_REPLY_ACK:
562 /* I2C-over-AUX Reply field is only valid
563 * when paired with AUX ACK.
564 */
565 break;
566 case AUX_NATIVE_REPLY_NACK:
567 DRM_DEBUG_KMS("aux_ch native nack\n");
568 return -EREMOTEIO;
569 case AUX_NATIVE_REPLY_DEFER:
570 udelay(100);
571 continue;
572 default:
573 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
574 reply[0]);
575 return -EREMOTEIO;
576 }
577
ab2c0672
DA		 578 switch (reply[0] & AUX_I2C_REPLY_MASK) {
579 case AUX_I2C_REPLY_ACK:
580 if (mode == MODE_I2C_READ) {
581 *read_byte = reply[1];
582 }
583 return reply_bytes - 1;
584 case AUX_I2C_REPLY_NACK:
8316f337 585 DRM_DEBUG_KMS("aux_i2c nack\n");
ab2c0672
DA		 586 return -EREMOTEIO;
587 case AUX_I2C_REPLY_DEFER:
8316f337 588 DRM_DEBUG_KMS("aux_i2c defer\n");
ab2c0672
DA		 589 udelay(100);
590 break;
591 default:
8316f337 592 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
ab2c0672
DA		 593 return -EREMOTEIO;
594 }
595 }
8316f337
DF		 596
597 DRM_ERROR("too many retries, giving up\n");
598 return -EREMOTEIO;
a4fc5ed6
KP		 599}
600
601static int
ea5b213a 602intel_dp_i2c_init(struct intel_dp *intel_dp,
55f78c43 603 struct intel_connector *intel_connector, const char *name)
a4fc5ed6 604{
0b5c541b
KP		 605 int ret;
606
d54e9d28 607 DRM_DEBUG_KMS("i2c_init %s\n", name);
ea5b213a
CW		 608 intel_dp->algo.running = false;
609 intel_dp->algo.address = 0;
610 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
611
0206e353 612 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
ea5b213a
CW		 613 intel_dp->adapter.owner = THIS_MODULE;
614 intel_dp->adapter.class = I2C_CLASS_DDC;
0206e353 615 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
ea5b213a
CW		 616 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
617 intel_dp->adapter.algo_data = &intel_dp->algo;
618 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
619
0b5c541b
KP		 620 ironlake_edp_panel_vdd_on(intel_dp);
621 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
bd943159 622 ironlake_edp_panel_vdd_off(intel_dp, false);
0b5c541b 623 return ret;
a4fc5ed6
KP		 624}
625
c6bb3538
DV		 626static void
627intel_dp_set_clock(struct intel_encoder *encoder,
628 struct intel_crtc_config *pipe_config, int link_bw)
629{
630 struct drm_device *dev = encoder->base.dev;
631
632 if (IS_G4X(dev)) {
633 if (link_bw == DP_LINK_BW_1_62) {
634 pipe_config->dpll.p1 = 2;
635 pipe_config->dpll.p2 = 10;
636 pipe_config->dpll.n = 2;
637 pipe_config->dpll.m1 = 23;
638 pipe_config->dpll.m2 = 8;
639 } else {
640 pipe_config->dpll.p1 = 1;
641 pipe_config->dpll.p2 = 10;
642 pipe_config->dpll.n = 1;
643 pipe_config->dpll.m1 = 14;
644 pipe_config->dpll.m2 = 2;
645 }
646 pipe_config->clock_set = true;
647 } else if (IS_HASWELL(dev)) {
648 /* Haswell has special-purpose DP DDI clocks. */
649 } else if (HAS_PCH_SPLIT(dev)) {
650 if (link_bw == DP_LINK_BW_1_62) {
651 pipe_config->dpll.n = 1;
652 pipe_config->dpll.p1 = 2;
653 pipe_config->dpll.p2 = 10;
654 pipe_config->dpll.m1 = 12;
655 pipe_config->dpll.m2 = 9;
656 } else {
657 pipe_config->dpll.n = 2;
658 pipe_config->dpll.p1 = 1;
659 pipe_config->dpll.p2 = 10;
660 pipe_config->dpll.m1 = 14;
661 pipe_config->dpll.m2 = 8;
662 }
663 pipe_config->clock_set = true;
664 } else if (IS_VALLEYVIEW(dev)) {
665 /* FIXME: Need to figure out optimized DP clocks for vlv. */
666 }
667}
668
00c09d70 669bool
5bfe2ac0
DV		 670intel_dp_compute_config(struct intel_encoder *encoder,
671 struct intel_crtc_config *pipe_config)
a4fc5ed6 672{
5bfe2ac0 673 struct drm_device *dev = encoder->base.dev;
36008365 674 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 675 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 676 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 677 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 678 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 679 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 680 int lane_count, clock;
397fe157 681 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
ea5b213a 682 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
083f9560 683 int bpp, mode_rate;
a4fc5ed6 684 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
ff9a6750 685 int link_avail, link_clock;
a4fc5ed6 686
bc7d38a4 687 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 688 pipe_config->has_pch_encoder = true;
689
03afc4a2 690 pipe_config->has_dp_encoder = true;
a4fc5ed6 691
dd06f90e
JN		 692 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
693 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
694 adjusted_mode);
2dd24552
JB		 695 if (!HAS_PCH_SPLIT(dev))
696 intel_gmch_panel_fitting(intel_crtc, pipe_config,
697 intel_connector->panel.fitting_mode);
698 else
b074cec8
JB		 699 intel_pch_panel_fitting(intel_crtc, pipe_config,
700 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 701 }
702
cb1793ce 703 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 704 return false;
705
083f9560
DV		 706 DRM_DEBUG_KMS("DP link computation with max lane count %i "
707 "max bw %02x pixel clock %iKHz\n",
71244653 708 max_lane_count, bws[max_clock], adjusted_mode->clock);
083f9560 709
36008365
DV		 710 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
711 * bpc in between. */
3e7ca985 712 bpp = pipe_config->pipe_bpp;
e1b73cba
DV		 713 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp)
714 bpp = min_t(int, bpp, dev_priv->vbt.edp_bpp);
657445fe 715
36008365 716 for (; bpp >= 6*3; bpp -= 2*3) {
ff9a6750 717 mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
36008365
DV		 718
719 for (clock = 0; clock <= max_clock; clock++) {
720 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
721 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
722 link_avail = intel_dp_max_data_rate(link_clock,
723 lane_count);
724
725 if (mode_rate <= link_avail) {
726 goto found;
727 }
728 }
729 }
730 }
c4867936 731
36008365 732 return false;
3685a8f3 733
36008365 734found:
55bc60db
VS		 735 if (intel_dp->color_range_auto) {
736 /*
737 * See:
738 * CEA-861-E - 5.1 Default Encoding Parameters
739 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
740 */
18316c8c 741 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 742 intel_dp->color_range = DP_COLOR_RANGE_16_235;
743 else
744 intel_dp->color_range = 0;
745 }
746
3685a8f3 747 if (intel_dp->color_range)
50f3b016 748 pipe_config->limited_color_range = true;
a4fc5ed6 749
36008365
DV		 750 intel_dp->link_bw = bws[clock];
751 intel_dp->lane_count = lane_count;
657445fe 752 pipe_config->pipe_bpp = bpp;
ff9a6750 753 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 754
36008365
DV		 755 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
756 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 757 pipe_config->port_clock, bpp);
36008365
DV		 758 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
759 mode_rate, link_avail);
a4fc5ed6 760
03afc4a2 761 intel_link_compute_m_n(bpp, lane_count,
ff9a6750 762 adjusted_mode->clock, pipe_config->port_clock,
03afc4a2 763 &pipe_config->dp_m_n);
9d1a455b 764
c6bb3538
DV		 765 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
766
03afc4a2 767 return true;
a4fc5ed6
KP		 768}
769
247d89f6
PZ		 770void intel_dp_init_link_config(struct intel_dp *intel_dp)
771{
772 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
773 intel_dp->link_configuration[0] = intel_dp->link_bw;
774 intel_dp->link_configuration[1] = intel_dp->lane_count;
775 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
776 /*
777 * Check for DPCD version > 1.1 and enhanced framing support
778 */
779 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
780 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
781 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
782 }
783}
784
7c62a164 785static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 786{
7c62a164
DV		 787 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
788 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
789 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 790 struct drm_i915_private *dev_priv = dev->dev_private;
791 u32 dpa_ctl;
792
ff9a6750 793 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 794 dpa_ctl = I915_READ(DP_A);
795 dpa_ctl &= ~DP_PLL_FREQ_MASK;
796
ff9a6750 797 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 798 /* For a long time we've carried around a ILK-DevA w/a for the
799 * 160MHz clock. If we're really unlucky, it's still required.
800 */
801 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 802 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 803 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 804 } else {
805 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 806 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 807 }
1ce17038 808
ea9b6006
DV		 809 I915_WRITE(DP_A, dpa_ctl);
810
811 POSTING_READ(DP_A);
812 udelay(500);
813}
814
a4fc5ed6
KP		 815static void
816intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
817 struct drm_display_mode *adjusted_mode)
818{
e3421a18 819 struct drm_device *dev = encoder->dev;
417e822d 820 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 821 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
bc7d38a4 822 enum port port = dp_to_dig_port(intel_dp)->port;
7c62a164 823 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
a4fc5ed6 824
417e822d 825 /*
1a2eb460 826 * There are four kinds of DP registers:
417e822d
KP		 827 *
828 * IBX PCH
1a2eb460
KP		 829 * SNB CPU
830 * IVB CPU
417e822d
KP		 831 * CPT PCH
832 *
833 * IBX PCH and CPU are the same for almost everything,
834 * except that the CPU DP PLL is configured in this
835 * register
836 *
837 * CPT PCH is quite different, having many bits moved
838 * to the TRANS_DP_CTL register instead. That
839 * configuration happens (oddly) in ironlake_pch_enable
840 */
9c9e7927 841
417e822d
KP		 842 /* Preserve the BIOS-computed detected bit. This is
843 * supposed to be read-only.
844 */
845 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 846
417e822d 847 /* Handle DP bits in common between all three register formats */
417e822d 848 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 849 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 850
e0dac65e
WF		 851 if (intel_dp->has_audio) {
852 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 853 pipe_name(crtc->pipe));
ea5b213a 854 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
e0dac65e
WF		 855 intel_write_eld(encoder, adjusted_mode);
856 }
247d89f6
PZ		 857
858 intel_dp_init_link_config(intel_dp);
a4fc5ed6 859
417e822d 860 /* Split out the IBX/CPU vs CPT settings */
32f9d658 861
bc7d38a4 862 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 863 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
864 intel_dp->DP |= DP_SYNC_HS_HIGH;
865 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
866 intel_dp->DP |= DP_SYNC_VS_HIGH;
867 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
868
869 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
870 intel_dp->DP |= DP_ENHANCED_FRAMING;
871
7c62a164 872 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 873 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 874 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 875 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 876
877 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
878 intel_dp->DP |= DP_SYNC_HS_HIGH;
879 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
880 intel_dp->DP |= DP_SYNC_VS_HIGH;
881 intel_dp->DP |= DP_LINK_TRAIN_OFF;
882
883 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
884 intel_dp->DP |= DP_ENHANCED_FRAMING;
885
7c62a164 886 if (crtc->pipe == 1)
417e822d 887 intel_dp->DP |= DP_PIPEB_SELECT;
417e822d
KP		 888 } else {
889 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 890 }
ea9b6006 891
bc7d38a4 892 if (port == PORT_A && !IS_VALLEYVIEW(dev))
7c62a164 893 ironlake_set_pll_cpu_edp(intel_dp);
a4fc5ed6
KP		 894}
895
99ea7127
KP		 896#define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
897#define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
898
899#define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
900#define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
901
902#define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
903#define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
904
905static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
906 u32 mask,
907 u32 value)
bd943159 908{
30add22d 909 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 910 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 911 u32 pp_stat_reg, pp_ctrl_reg;
912
913 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
914 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
32ce697c 915
99ea7127 916 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 917 mask, value,
918 I915_READ(pp_stat_reg),
919 I915_READ(pp_ctrl_reg));
32ce697c 920
453c5420 921 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 922 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 923 I915_READ(pp_stat_reg),
924 I915_READ(pp_ctrl_reg));
32ce697c 925 }
99ea7127 926}
32ce697c 927
99ea7127
KP		 928static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
929{
930 DRM_DEBUG_KMS("Wait for panel power on\n");
931 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 932}
933
99ea7127
KP		 934static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
935{
936 DRM_DEBUG_KMS("Wait for panel power off time\n");
937 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
938}
939
940static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
941{
942 DRM_DEBUG_KMS("Wait for panel power cycle\n");
943 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
944}
945
946
832dd3c1
KP		 947/* Read the current pp_control value, unlocking the register if it
948 * is locked
949 */
950
453c5420 951static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 952{
453c5420
JB		 953 struct drm_device *dev = intel_dp_to_dev(intel_dp);
954 struct drm_i915_private *dev_priv = dev->dev_private;
955 u32 control;
956 u32 pp_ctrl_reg;
957
958 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
959 control = I915_READ(pp_ctrl_reg);
832dd3c1
KP		 960
961 control &= ~PANEL_UNLOCK_MASK;
962 control |= PANEL_UNLOCK_REGS;
963 return control;
bd943159
KP		 964}
965
82a4d9c0 966void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 967{
30add22d 968 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 969 struct drm_i915_private *dev_priv = dev->dev_private;
970 u32 pp;
453c5420 971 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 972
97af61f5
KP		 973 if (!is_edp(intel_dp))
974 return;
f01eca2e 975 DRM_DEBUG_KMS("Turn eDP VDD on\n");
5d613501 976
bd943159
KP		 977 WARN(intel_dp->want_panel_vdd,
978 "eDP VDD already requested on\n");
979
980 intel_dp->want_panel_vdd = true;
99ea7127 981
bd943159
KP		 982 if (ironlake_edp_have_panel_vdd(intel_dp)) {
983 DRM_DEBUG_KMS("eDP VDD already on\n");
984 return;
985 }
986
99ea7127
KP		 987 if (!ironlake_edp_have_panel_power(intel_dp))
988 ironlake_wait_panel_power_cycle(intel_dp);
989
453c5420 990 pp = ironlake_get_pp_control(intel_dp);
5d613501 991 pp |= EDP_FORCE_VDD;
ebf33b18 992
453c5420
JB		 993 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
994 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
995
996 I915_WRITE(pp_ctrl_reg, pp);
997 POSTING_READ(pp_ctrl_reg);
998 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
999 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1000 /*
1001 * If the panel wasn't on, delay before accessing aux channel
1002 */
1003 if (!ironlake_edp_have_panel_power(intel_dp)) {
bd943159 1004 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1005 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1006 }
5d613501
JB		 1007}
1008
bd943159 1009static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1010{
30add22d 1011 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1012 struct drm_i915_private *dev_priv = dev->dev_private;
1013 u32 pp;
453c5420 1014 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1015
a0e99e68
DV		 1016 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1017
bd943159 1018 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
453c5420 1019 pp = ironlake_get_pp_control(intel_dp);
bd943159 1020 pp &= ~EDP_FORCE_VDD;
bd943159 1021
453c5420
JB		 1022 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1023 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1024
1025 I915_WRITE(pp_ctrl_reg, pp);
1026 POSTING_READ(pp_ctrl_reg);
99ea7127 1027
453c5420
JB		 1028 /* Make sure sequencer is idle before allowing subsequent activity */
1029 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1030 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
99ea7127 1031 msleep(intel_dp->panel_power_down_delay);
bd943159
KP		 1032 }
1033}
5d613501 1034
bd943159
KP		 1035static void ironlake_panel_vdd_work(struct work_struct *__work)
1036{
1037 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1038 struct intel_dp, panel_vdd_work);
30add22d 1039 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bd943159 1040
627f7675 1041 mutex_lock(&dev->mode_config.mutex);
bd943159 1042 ironlake_panel_vdd_off_sync(intel_dp);
627f7675 1043 mutex_unlock(&dev->mode_config.mutex);
bd943159
KP		 1044}
1045
82a4d9c0 1046void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1047{
97af61f5
KP		 1048 if (!is_edp(intel_dp))
1049 return;
5d613501 1050
bd943159
KP		 1051 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1052 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1053
bd943159
KP		 1054 intel_dp->want_panel_vdd = false;
1055
1056 if (sync) {
1057 ironlake_panel_vdd_off_sync(intel_dp);
1058 } else {
1059 /*
1060 * Queue the timer to fire a long
1061 * time from now (relative to the power down delay)
1062 * to keep the panel power up across a sequence of operations
1063 */
1064 schedule_delayed_work(&intel_dp->panel_vdd_work,
1065 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1066 }
5d613501
JB		 1067}
1068
82a4d9c0 1069void ironlake_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1070{
30add22d 1071 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1072 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1073 u32 pp;
453c5420 1074 u32 pp_ctrl_reg;
9934c132 1075
97af61f5 1076 if (!is_edp(intel_dp))
bd943159 1077 return;
99ea7127
KP		 1078
1079 DRM_DEBUG_KMS("Turn eDP power on\n");
1080
1081 if (ironlake_edp_have_panel_power(intel_dp)) {
1082 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1083 return;
99ea7127 1084 }
9934c132 1085
99ea7127 1086 ironlake_wait_panel_power_cycle(intel_dp);
37c6c9b0 1087
453c5420 1088 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1089 if (IS_GEN5(dev)) {
1090 /* ILK workaround: disable reset around power sequence */
1091 pp &= ~PANEL_POWER_RESET;
1092 I915_WRITE(PCH_PP_CONTROL, pp);
1093 POSTING_READ(PCH_PP_CONTROL);
1094 }
37c6c9b0 1095
1c0ae80a 1096 pp |= POWER_TARGET_ON;
99ea7127
KP		 1097 if (!IS_GEN5(dev))
1098 pp |= PANEL_POWER_RESET;
1099
453c5420
JB		 1100 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1101
1102 I915_WRITE(pp_ctrl_reg, pp);
1103 POSTING_READ(pp_ctrl_reg);
9934c132 1104
99ea7127 1105 ironlake_wait_panel_on(intel_dp);
9934c132 1106
05ce1a49
KP		 1107 if (IS_GEN5(dev)) {
1108 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1109 I915_WRITE(PCH_PP_CONTROL, pp);
1110 POSTING_READ(PCH_PP_CONTROL);
1111 }
9934c132
JB		 1112}
1113
82a4d9c0 1114void ironlake_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1115{
30add22d 1116 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1117 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1118 u32 pp;
453c5420 1119 u32 pp_ctrl_reg;
9934c132 1120
97af61f5
KP		 1121 if (!is_edp(intel_dp))
1122 return;
37c6c9b0 1123
99ea7127 1124 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1125
6cb49835 1126 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
37c6c9b0 1127
453c5420 1128 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1129 /* We need to switch off panel power _and_ force vdd, for otherwise some
1130 * panels get very unhappy and cease to work. */
1131 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
453c5420
JB		 1132
1133 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1134
1135 I915_WRITE(pp_ctrl_reg, pp);
1136 POSTING_READ(pp_ctrl_reg);
9934c132 1137
35a38556
DV		 1138 intel_dp->want_panel_vdd = false;
1139
99ea7127 1140 ironlake_wait_panel_off(intel_dp);
9934c132
JB		 1141}
1142
d6c50ff8 1143void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1144{
da63a9f2
PZ		 1145 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1146 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658 1147 struct drm_i915_private *dev_priv = dev->dev_private;
da63a9f2 1148 int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
32f9d658 1149 u32 pp;
453c5420 1150 u32 pp_ctrl_reg;
32f9d658 1151
f01eca2e
KP		 1152 if (!is_edp(intel_dp))
1153 return;
1154
28c97730 1155 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1156 /*
1157 * If we enable the backlight right away following a panel power
1158 * on, we may see slight flicker as the panel syncs with the eDP
1159 * link. So delay a bit to make sure the image is solid before
1160 * allowing it to appear.
1161 */
f01eca2e 1162 msleep(intel_dp->backlight_on_delay);
453c5420 1163 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1164 pp |= EDP_BLC_ENABLE;
453c5420
JB		 1165
1166 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1167
1168 I915_WRITE(pp_ctrl_reg, pp);
1169 POSTING_READ(pp_ctrl_reg);
035aa3de
DV		 1170
1171 intel_panel_enable_backlight(dev, pipe);
32f9d658
ZW		 1172}
1173
d6c50ff8 1174void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1175{
30add22d 1176 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1177 struct drm_i915_private *dev_priv = dev->dev_private;
1178 u32 pp;
453c5420 1179 u32 pp_ctrl_reg;
32f9d658 1180
f01eca2e
KP		 1181 if (!is_edp(intel_dp))
1182 return;
1183
035aa3de
DV		 1184 intel_panel_disable_backlight(dev);
1185
28c97730 1186 DRM_DEBUG_KMS("\n");
453c5420 1187 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1188 pp &= ~EDP_BLC_ENABLE;
453c5420
JB		 1189
1190 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1191
1192 I915_WRITE(pp_ctrl_reg, pp);
1193 POSTING_READ(pp_ctrl_reg);
f01eca2e 1194 msleep(intel_dp->backlight_off_delay);
32f9d658 1195}
a4fc5ed6 1196
2bd2ad64 1197static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1198{
da63a9f2
PZ		 1199 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1200 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1201 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1202 struct drm_i915_private *dev_priv = dev->dev_private;
1203 u32 dpa_ctl;
1204
2bd2ad64
DV		 1205 assert_pipe_disabled(dev_priv,
1206 to_intel_crtc(crtc)->pipe);
1207
d240f20f
JB		 1208 DRM_DEBUG_KMS("\n");
1209 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1210 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1211 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1212
1213 /* We don't adjust intel_dp->DP while tearing down the link, to
1214 * facilitate link retraining (e.g. after hotplug). Hence clear all
1215 * enable bits here to ensure that we don't enable too much. */
1216 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1217 intel_dp->DP |= DP_PLL_ENABLE;
1218 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1219 POSTING_READ(DP_A);
1220 udelay(200);
d240f20f
JB		 1221}
1222
2bd2ad64 1223static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1224{
da63a9f2
PZ		 1225 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1226 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1227 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1228 struct drm_i915_private *dev_priv = dev->dev_private;
1229 u32 dpa_ctl;
1230
2bd2ad64
DV		 1231 assert_pipe_disabled(dev_priv,
1232 to_intel_crtc(crtc)->pipe);
1233
d240f20f 1234 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1235 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1236 "dp pll off, should be on\n");
1237 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1238
1239 /* We can't rely on the value tracked for the DP register in
1240 * intel_dp->DP because link_down must not change that (otherwise link
1241 * re-training will fail. */
298b0b39 1242 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1243 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1244 POSTING_READ(DP_A);
d240f20f
JB		 1245 udelay(200);
1246}
1247
c7ad3810 1248/* If the sink supports it, try to set the power state appropriately */
c19b0669 1249void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1250{
1251 int ret, i;
1252
1253 /* Should have a valid DPCD by this point */
1254 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1255 return;
1256
1257 if (mode != DRM_MODE_DPMS_ON) {
1258 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1259 DP_SET_POWER_D3);
1260 if (ret != 1)
1261 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1262 } else {
1263 /*
1264 * When turning on, we need to retry for 1ms to give the sink
1265 * time to wake up.
1266 */
1267 for (i = 0; i < 3; i++) {
1268 ret = intel_dp_aux_native_write_1(intel_dp,
1269 DP_SET_POWER,
1270 DP_SET_POWER_D0);
1271 if (ret == 1)
1272 break;
1273 msleep(1);
1274 }
1275 }
1276}
1277
19d8fe15
DV		 1278static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1279 enum pipe *pipe)
d240f20f 1280{
19d8fe15 1281 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1282 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1283 struct drm_device *dev = encoder->base.dev;
1284 struct drm_i915_private *dev_priv = dev->dev_private;
1285 u32 tmp = I915_READ(intel_dp->output_reg);
1286
1287 if (!(tmp & DP_PORT_EN))
1288 return false;
1289
bc7d38a4 1290 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1291 *pipe = PORT_TO_PIPE_CPT(tmp);
bc7d38a4 1292 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1293 *pipe = PORT_TO_PIPE(tmp);
1294 } else {
1295 u32 trans_sel;
1296 u32 trans_dp;
1297 int i;
1298
1299 switch (intel_dp->output_reg) {
1300 case PCH_DP_B:
1301 trans_sel = TRANS_DP_PORT_SEL_B;
1302 break;
1303 case PCH_DP_C:
1304 trans_sel = TRANS_DP_PORT_SEL_C;
1305 break;
1306 case PCH_DP_D:
1307 trans_sel = TRANS_DP_PORT_SEL_D;
1308 break;
1309 default:
1310 return true;
1311 }
1312
1313 for_each_pipe(i) {
1314 trans_dp = I915_READ(TRANS_DP_CTL(i));
1315 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1316 *pipe = i;
1317 return true;
1318 }
1319 }
19d8fe15 1320
4a0833ec
DV		 1321 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1322 intel_dp->output_reg);
1323 }
d240f20f 1324
19d8fe15
DV		 1325 return true;
1326}
d240f20f 1327
045ac3b5
JB		 1328static void intel_dp_get_config(struct intel_encoder *encoder,
1329 struct intel_crtc_config *pipe_config)
1330{
1331 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1332 u32 tmp, flags = 0;
63000ef6
XZ		 1333 struct drm_device *dev = encoder->base.dev;
1334 struct drm_i915_private *dev_priv = dev->dev_private;
1335 enum port port = dp_to_dig_port(intel_dp)->port;
1336 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
045ac3b5 1337
63000ef6
XZ		 1338 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1339 tmp = I915_READ(intel_dp->output_reg);
1340 if (tmp & DP_SYNC_HS_HIGH)
1341 flags |= DRM_MODE_FLAG_PHSYNC;
1342 else
1343 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1344
63000ef6
XZ		 1345 if (tmp & DP_SYNC_VS_HIGH)
1346 flags |= DRM_MODE_FLAG_PVSYNC;
1347 else
1348 flags |= DRM_MODE_FLAG_NVSYNC;
1349 } else {
1350 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1351 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1352 flags |= DRM_MODE_FLAG_PHSYNC;
1353 else
1354 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1355
63000ef6
XZ		 1356 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1357 flags |= DRM_MODE_FLAG_PVSYNC;
1358 else
1359 flags |= DRM_MODE_FLAG_NVSYNC;
1360 }
045ac3b5
JB		 1361
1362 pipe_config->adjusted_mode.flags |= flags;
1363}
1364
e8cb4558 1365static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1366{
e8cb4558 1367 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866
ID		 1368 enum port port = dp_to_dig_port(intel_dp)->port;
1369 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 1370
1371 /* Make sure the panel is off before trying to change the mode. But also
1372 * ensure that we have vdd while we switch off the panel. */
1373 ironlake_edp_panel_vdd_on(intel_dp);
21264c63 1374 ironlake_edp_backlight_off(intel_dp);
c7ad3810 1375 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
35a38556 1376 ironlake_edp_panel_off(intel_dp);
3739850b
DV		 1377
1378 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
982a3866 1379 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
3739850b 1380 intel_dp_link_down(intel_dp);
d240f20f
JB		 1381}
1382
2bd2ad64 1383static void intel_post_disable_dp(struct intel_encoder *encoder)
d240f20f 1384{
2bd2ad64 1385 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 1386 enum port port = dp_to_dig_port(intel_dp)->port;
b2634017 1387 struct drm_device *dev = encoder->base.dev;
2bd2ad64 1388
982a3866 1389 if (port == PORT_A || IS_VALLEYVIEW(dev)) {
3739850b 1390 intel_dp_link_down(intel_dp);
b2634017
JB		 1391 if (!IS_VALLEYVIEW(dev))
1392 ironlake_edp_pll_off(intel_dp);
3739850b 1393 }
2bd2ad64
DV		 1394}
1395
e8cb4558 1396static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 1397{
e8cb4558
DV		 1398 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1399 struct drm_device *dev = encoder->base.dev;
1400 struct drm_i915_private *dev_priv = dev->dev_private;
1401 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 1402
0c33d8d7
DV		 1403 if (WARN_ON(dp_reg & DP_PORT_EN))
1404 return;
5d613501 1405
97af61f5 1406 ironlake_edp_panel_vdd_on(intel_dp);
f01eca2e 1407 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 1408 intel_dp_start_link_train(intel_dp);
97af61f5 1409 ironlake_edp_panel_on(intel_dp);
bd943159 1410 ironlake_edp_panel_vdd_off(intel_dp, true);
33a34e4e 1411 intel_dp_complete_link_train(intel_dp);
3ab9c637 1412 intel_dp_stop_link_train(intel_dp);
f01eca2e 1413 ironlake_edp_backlight_on(intel_dp);
89b667f8
JB		 1414
1415 if (IS_VALLEYVIEW(dev)) {
1416 struct intel_digital_port *dport =
1417 enc_to_dig_port(&encoder->base);
1418 int channel = vlv_dport_to_channel(dport);
1419
1420 vlv_wait_port_ready(dev_priv, channel);
1421 }
d240f20f
JB		 1422}
1423
2bd2ad64 1424static void intel_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 1425{
2bd2ad64 1426 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1427 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 1428 struct drm_device *dev = encoder->base.dev;
89b667f8 1429 struct drm_i915_private *dev_priv = dev->dev_private;
a4fc5ed6 1430
bc7d38a4 1431 if (dport->port == PORT_A && !IS_VALLEYVIEW(dev))
2bd2ad64 1432 ironlake_edp_pll_on(intel_dp);
89b667f8
JB		 1433
1434 if (IS_VALLEYVIEW(dev)) {
89b667f8
JB		 1435 struct intel_crtc *intel_crtc =
1436 to_intel_crtc(encoder->base.crtc);
1437 int port = vlv_dport_to_channel(dport);
1438 int pipe = intel_crtc->pipe;
1439 u32 val;
1440
ae99258f 1441 val = vlv_dpio_read(dev_priv, DPIO_DATA_LANE_A(port));
89b667f8
JB		 1442 val = 0;
1443 if (pipe)
1444 val |= (1<<21);
1445 else
1446 val &= ~(1<<21);
1447 val |= 0x001000c4;
ae99258f 1448 vlv_dpio_write(dev_priv, DPIO_DATA_CHANNEL(port), val);
89b667f8 1449
ae99258f 1450 vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF0(port),
89b667f8 1451 0x00760018);
ae99258f 1452 vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF8(port),
89b667f8
JB		 1453 0x00400888);
1454 }
1455}
1456
1457static void intel_dp_pre_pll_enable(struct intel_encoder *encoder)
1458{
1459 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1460 struct drm_device *dev = encoder->base.dev;
1461 struct drm_i915_private *dev_priv = dev->dev_private;
1462 int port = vlv_dport_to_channel(dport);
1463
1464 if (!IS_VALLEYVIEW(dev))
1465 return;
1466
89b667f8 1467 /* Program Tx lane resets to default */
ae99258f 1468 vlv_dpio_write(dev_priv, DPIO_PCS_TX(port),
89b667f8
JB		 1469 DPIO_PCS_TX_LANE2_RESET |
1470 DPIO_PCS_TX_LANE1_RESET);
ae99258f 1471 vlv_dpio_write(dev_priv, DPIO_PCS_CLK(port),
89b667f8
JB		 1472 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1473 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1474 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1475 DPIO_PCS_CLK_SOFT_RESET);
1476
1477 /* Fix up inter-pair skew failure */
ae99258f
JN		 1478 vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER1(port), 0x00750f00);
1479 vlv_dpio_write(dev_priv, DPIO_TX_CTL(port), 0x00001500);
1480 vlv_dpio_write(dev_priv, DPIO_TX_LANE(port), 0x40400000);
a4fc5ed6
KP		 1481}
1482
1483/*
df0c237d
JB		 1484 * Native read with retry for link status and receiver capability reads for
1485 * cases where the sink may still be asleep.
a4fc5ed6
KP		 1486 */
1487static bool
df0c237d
JB		 1488intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1489 uint8_t *recv, int recv_bytes)
a4fc5ed6 1490{
61da5fab
JB		 1491 int ret, i;
1492
df0c237d
JB		 1493 /*
1494 * Sinks are *supposed* to come up within 1ms from an off state,
1495 * but we're also supposed to retry 3 times per the spec.
1496 */
61da5fab 1497 for (i = 0; i < 3; i++) {
df0c237d
JB		 1498 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1499 recv_bytes);
1500 if (ret == recv_bytes)
61da5fab
JB		 1501 return true;
1502 msleep(1);
1503 }
a4fc5ed6 1504
61da5fab 1505 return false;
a4fc5ed6
KP		 1506}
1507
1508/*
1509 * Fetch AUX CH registers 0x202 - 0x207 which contain
1510 * link status information
1511 */
1512static bool
93f62dad 1513intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 1514{
df0c237d
JB		 1515 return intel_dp_aux_native_read_retry(intel_dp,
1516 DP_LANE0_1_STATUS,
93f62dad 1517 link_status,
df0c237d 1518 DP_LINK_STATUS_SIZE);
a4fc5ed6
KP		 1519}
1520
a4fc5ed6
KP		 1521#if 0
1522static char *voltage_names[] = {
1523 "0.4V", "0.6V", "0.8V", "1.2V"
1524};
1525static char *pre_emph_names[] = {
1526 "0dB", "3.5dB", "6dB", "9.5dB"
1527};
1528static char *link_train_names[] = {
1529 "pattern 1", "pattern 2", "idle", "off"
1530};
1531#endif
1532
1533/*
1534 * These are source-specific values; current Intel hardware supports
1535 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1536 */
a4fc5ed6
KP		 1537
1538static uint8_t
1a2eb460 1539intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 1540{
30add22d 1541 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 1542 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 1543
e2fa6fba
P		 1544 if (IS_VALLEYVIEW(dev))
1545 return DP_TRAIN_VOLTAGE_SWING_1200;
bc7d38a4 1546 else if (IS_GEN7(dev) && port == PORT_A)
1a2eb460 1547 return DP_TRAIN_VOLTAGE_SWING_800;
bc7d38a4 1548 else if (HAS_PCH_CPT(dev) && port != PORT_A)
1a2eb460
KP		 1549 return DP_TRAIN_VOLTAGE_SWING_1200;
1550 else
1551 return DP_TRAIN_VOLTAGE_SWING_800;
1552}
1553
1554static uint8_t
1555intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1556{
30add22d 1557 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 1558 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 1559
22b8bf17 1560 if (HAS_DDI(dev)) {
d6c0d722
PZ		 1561 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1562 case DP_TRAIN_VOLTAGE_SWING_400:
1563 return DP_TRAIN_PRE_EMPHASIS_9_5;
1564 case DP_TRAIN_VOLTAGE_SWING_600:
1565 return DP_TRAIN_PRE_EMPHASIS_6;
1566 case DP_TRAIN_VOLTAGE_SWING_800:
1567 return DP_TRAIN_PRE_EMPHASIS_3_5;
1568 case DP_TRAIN_VOLTAGE_SWING_1200:
1569 default:
1570 return DP_TRAIN_PRE_EMPHASIS_0;
1571 }
e2fa6fba
P		 1572 } else if (IS_VALLEYVIEW(dev)) {
1573 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1574 case DP_TRAIN_VOLTAGE_SWING_400:
1575 return DP_TRAIN_PRE_EMPHASIS_9_5;
1576 case DP_TRAIN_VOLTAGE_SWING_600:
1577 return DP_TRAIN_PRE_EMPHASIS_6;
1578 case DP_TRAIN_VOLTAGE_SWING_800:
1579 return DP_TRAIN_PRE_EMPHASIS_3_5;
1580 case DP_TRAIN_VOLTAGE_SWING_1200:
1581 default:
1582 return DP_TRAIN_PRE_EMPHASIS_0;
1583 }
bc7d38a4 1584 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460
KP		 1585 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1586 case DP_TRAIN_VOLTAGE_SWING_400:
1587 return DP_TRAIN_PRE_EMPHASIS_6;
1588 case DP_TRAIN_VOLTAGE_SWING_600:
1589 case DP_TRAIN_VOLTAGE_SWING_800:
1590 return DP_TRAIN_PRE_EMPHASIS_3_5;
1591 default:
1592 return DP_TRAIN_PRE_EMPHASIS_0;
1593 }
1594 } else {
1595 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1596 case DP_TRAIN_VOLTAGE_SWING_400:
1597 return DP_TRAIN_PRE_EMPHASIS_6;
1598 case DP_TRAIN_VOLTAGE_SWING_600:
1599 return DP_TRAIN_PRE_EMPHASIS_6;
1600 case DP_TRAIN_VOLTAGE_SWING_800:
1601 return DP_TRAIN_PRE_EMPHASIS_3_5;
1602 case DP_TRAIN_VOLTAGE_SWING_1200:
1603 default:
1604 return DP_TRAIN_PRE_EMPHASIS_0;
1605 }
a4fc5ed6
KP		 1606 }
1607}
1608
e2fa6fba
P		 1609static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
1610{
1611 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1612 struct drm_i915_private *dev_priv = dev->dev_private;
1613 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1614 unsigned long demph_reg_value, preemph_reg_value,
1615 uniqtranscale_reg_value;
1616 uint8_t train_set = intel_dp->train_set[0];
cece5d58 1617 int port = vlv_dport_to_channel(dport);
e2fa6fba
P		 1618
1619 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1620 case DP_TRAIN_PRE_EMPHASIS_0:
1621 preemph_reg_value = 0x0004000;
1622 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1623 case DP_TRAIN_VOLTAGE_SWING_400:
1624 demph_reg_value = 0x2B405555;
1625 uniqtranscale_reg_value = 0x552AB83A;
1626 break;
1627 case DP_TRAIN_VOLTAGE_SWING_600:
1628 demph_reg_value = 0x2B404040;
1629 uniqtranscale_reg_value = 0x5548B83A;
1630 break;
1631 case DP_TRAIN_VOLTAGE_SWING_800:
1632 demph_reg_value = 0x2B245555;
1633 uniqtranscale_reg_value = 0x5560B83A;
1634 break;
1635 case DP_TRAIN_VOLTAGE_SWING_1200:
1636 demph_reg_value = 0x2B405555;
1637 uniqtranscale_reg_value = 0x5598DA3A;
1638 break;
1639 default:
1640 return 0;
1641 }
1642 break;
1643 case DP_TRAIN_PRE_EMPHASIS_3_5:
1644 preemph_reg_value = 0x0002000;
1645 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1646 case DP_TRAIN_VOLTAGE_SWING_400:
1647 demph_reg_value = 0x2B404040;
1648 uniqtranscale_reg_value = 0x5552B83A;
1649 break;
1650 case DP_TRAIN_VOLTAGE_SWING_600:
1651 demph_reg_value = 0x2B404848;
1652 uniqtranscale_reg_value = 0x5580B83A;
1653 break;
1654 case DP_TRAIN_VOLTAGE_SWING_800:
1655 demph_reg_value = 0x2B404040;
1656 uniqtranscale_reg_value = 0x55ADDA3A;
1657 break;
1658 default:
1659 return 0;
1660 }
1661 break;
1662 case DP_TRAIN_PRE_EMPHASIS_6:
1663 preemph_reg_value = 0x0000000;
1664 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1665 case DP_TRAIN_VOLTAGE_SWING_400:
1666 demph_reg_value = 0x2B305555;
1667 uniqtranscale_reg_value = 0x5570B83A;
1668 break;
1669 case DP_TRAIN_VOLTAGE_SWING_600:
1670 demph_reg_value = 0x2B2B4040;
1671 uniqtranscale_reg_value = 0x55ADDA3A;
1672 break;
1673 default:
1674 return 0;
1675 }
1676 break;
1677 case DP_TRAIN_PRE_EMPHASIS_9_5:
1678 preemph_reg_value = 0x0006000;
1679 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1680 case DP_TRAIN_VOLTAGE_SWING_400:
1681 demph_reg_value = 0x1B405555;
1682 uniqtranscale_reg_value = 0x55ADDA3A;
1683 break;
1684 default:
1685 return 0;
1686 }
1687 break;
1688 default:
1689 return 0;
1690 }
1691
ae99258f
JN		 1692 vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x00000000);
1693 vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL4(port), demph_reg_value);
1694 vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL2(port),
e2fa6fba 1695 uniqtranscale_reg_value);
ae99258f
JN		 1696 vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL3(port), 0x0C782040);
1697 vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER0(port), 0x00030000);
1698 vlv_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port), preemph_reg_value);
1699 vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x80000000);
e2fa6fba
P		 1700
1701 return 0;
1702}
1703
a4fc5ed6 1704static void
93f62dad 1705intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 1706{
1707 uint8_t v = 0;
1708 uint8_t p = 0;
1709 int lane;
1a2eb460
KP		 1710 uint8_t voltage_max;
1711 uint8_t preemph_max;
a4fc5ed6 1712
33a34e4e 1713 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 1714 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
1715 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 1716
1717 if (this_v > v)
1718 v = this_v;
1719 if (this_p > p)
1720 p = this_p;
1721 }
1722
1a2eb460 1723 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 1724 if (v >= voltage_max)
1725 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 1726
1a2eb460
KP		 1727 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1728 if (p >= preemph_max)
1729 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 1730
1731 for (lane = 0; lane < 4; lane++)
33a34e4e 1732 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 1733}
1734
1735static uint32_t
f0a3424e 1736intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 1737{
3cf2efb1 1738 uint32_t signal_levels = 0;
a4fc5ed6 1739
3cf2efb1 1740 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 1741 case DP_TRAIN_VOLTAGE_SWING_400:
1742 default:
1743 signal_levels |= DP_VOLTAGE_0_4;
1744 break;
1745 case DP_TRAIN_VOLTAGE_SWING_600:
1746 signal_levels |= DP_VOLTAGE_0_6;
1747 break;
1748 case DP_TRAIN_VOLTAGE_SWING_800:
1749 signal_levels |= DP_VOLTAGE_0_8;
1750 break;
1751 case DP_TRAIN_VOLTAGE_SWING_1200:
1752 signal_levels |= DP_VOLTAGE_1_2;
1753 break;
1754 }
3cf2efb1 1755 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 1756 case DP_TRAIN_PRE_EMPHASIS_0:
1757 default:
1758 signal_levels |= DP_PRE_EMPHASIS_0;
1759 break;
1760 case DP_TRAIN_PRE_EMPHASIS_3_5:
1761 signal_levels |= DP_PRE_EMPHASIS_3_5;
1762 break;
1763 case DP_TRAIN_PRE_EMPHASIS_6:
1764 signal_levels |= DP_PRE_EMPHASIS_6;
1765 break;
1766 case DP_TRAIN_PRE_EMPHASIS_9_5:
1767 signal_levels |= DP_PRE_EMPHASIS_9_5;
1768 break;
1769 }
1770 return signal_levels;
1771}
1772
e3421a18
ZW		 1773/* Gen6's DP voltage swing and pre-emphasis control */
1774static uint32_t
1775intel_gen6_edp_signal_levels(uint8_t train_set)
1776{
3c5a62b5
YL		 1777 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1778 DP_TRAIN_PRE_EMPHASIS_MASK);
1779 switch (signal_levels) {
e3421a18 1780 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1781 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1782 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1783 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1784 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 1785 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 1786 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1787 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 1788 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 1789 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1790 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 1791 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1792 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1793 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 1794 default:
3c5a62b5
YL		 1795 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1796 "0x%x\n", signal_levels);
1797 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 1798 }
1799}
1800
1a2eb460
KP		 1801/* Gen7's DP voltage swing and pre-emphasis control */
1802static uint32_t
1803intel_gen7_edp_signal_levels(uint8_t train_set)
1804{
1805 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1806 DP_TRAIN_PRE_EMPHASIS_MASK);
1807 switch (signal_levels) {
1808 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1809 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1810 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1811 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1812 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1813 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1814
1815 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1816 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1817 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1818 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1819
1820 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1821 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1822 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1823 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1824
1825 default:
1826 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1827 "0x%x\n", signal_levels);
1828 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1829 }
1830}
1831
d6c0d722
PZ		 1832/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1833static uint32_t
f0a3424e 1834intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 1835{
d6c0d722
PZ		 1836 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1837 DP_TRAIN_PRE_EMPHASIS_MASK);
1838 switch (signal_levels) {
1839 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1840 return DDI_BUF_EMP_400MV_0DB_HSW;
1841 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1842 return DDI_BUF_EMP_400MV_3_5DB_HSW;
1843 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1844 return DDI_BUF_EMP_400MV_6DB_HSW;
1845 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
1846 return DDI_BUF_EMP_400MV_9_5DB_HSW;
a4fc5ed6 1847
d6c0d722
PZ		 1848 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1849 return DDI_BUF_EMP_600MV_0DB_HSW;
1850 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1851 return DDI_BUF_EMP_600MV_3_5DB_HSW;
1852 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1853 return DDI_BUF_EMP_600MV_6DB_HSW;
a4fc5ed6 1854
d6c0d722
PZ		 1855 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1856 return DDI_BUF_EMP_800MV_0DB_HSW;
1857 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1858 return DDI_BUF_EMP_800MV_3_5DB_HSW;
1859 default:
1860 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1861 "0x%x\n", signal_levels);
1862 return DDI_BUF_EMP_400MV_0DB_HSW;
a4fc5ed6 1863 }
a4fc5ed6
KP		 1864}
1865
f0a3424e
PZ		 1866/* Properly updates "DP" with the correct signal levels. */
1867static void
1868intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
1869{
1870 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 1871 enum port port = intel_dig_port->port;
f0a3424e
PZ		 1872 struct drm_device *dev = intel_dig_port->base.base.dev;
1873 uint32_t signal_levels, mask;
1874 uint8_t train_set = intel_dp->train_set[0];
1875
22b8bf17 1876 if (HAS_DDI(dev)) {
f0a3424e
PZ		 1877 signal_levels = intel_hsw_signal_levels(train_set);
1878 mask = DDI_BUF_EMP_MASK;
e2fa6fba
P		 1879 } else if (IS_VALLEYVIEW(dev)) {
1880 signal_levels = intel_vlv_signal_levels(intel_dp);
1881 mask = 0;
bc7d38a4 1882 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 1883 signal_levels = intel_gen7_edp_signal_levels(train_set);
1884 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 1885 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 1886 signal_levels = intel_gen6_edp_signal_levels(train_set);
1887 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
1888 } else {
1889 signal_levels = intel_gen4_signal_levels(train_set);
1890 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
1891 }
1892
1893 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
1894
1895 *DP = (*DP & ~mask) | signal_levels;
1896}
1897
a4fc5ed6 1898static bool
ea5b213a 1899intel_dp_set_link_train(struct intel_dp *intel_dp,
a4fc5ed6 1900 uint32_t dp_reg_value,
58e10eb9 1901 uint8_t dp_train_pat)
a4fc5ed6 1902{
174edf1f
PZ		 1903 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1904 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 1905 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 1906 enum port port = intel_dig_port->port;
a4fc5ed6
KP		 1907 int ret;
1908
22b8bf17 1909 if (HAS_DDI(dev)) {
3ab9c637 1910 uint32_t temp = I915_READ(DP_TP_CTL(port));
d6c0d722
PZ		 1911
1912 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
1913 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
1914 else
1915 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
1916
1917 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1918 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1919 case DP_TRAINING_PATTERN_DISABLE:
d6c0d722
PZ		 1920 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
1921
1922 break;
1923 case DP_TRAINING_PATTERN_1:
1924 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1925 break;
1926 case DP_TRAINING_PATTERN_2:
1927 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
1928 break;
1929 case DP_TRAINING_PATTERN_3:
1930 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
1931 break;
1932 }
174edf1f 1933 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722 1934
bc7d38a4 1935 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
47ea7542
PZ		 1936 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1937
1938 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1939 case DP_TRAINING_PATTERN_DISABLE:
1940 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1941 break;
1942 case DP_TRAINING_PATTERN_1:
1943 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1944 break;
1945 case DP_TRAINING_PATTERN_2:
1946 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1947 break;
1948 case DP_TRAINING_PATTERN_3:
1949 DRM_ERROR("DP training pattern 3 not supported\n");
1950 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1951 break;
1952 }
1953
1954 } else {
1955 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1956
1957 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1958 case DP_TRAINING_PATTERN_DISABLE:
1959 dp_reg_value |= DP_LINK_TRAIN_OFF;
1960 break;
1961 case DP_TRAINING_PATTERN_1:
1962 dp_reg_value |= DP_LINK_TRAIN_PAT_1;
1963 break;
1964 case DP_TRAINING_PATTERN_2:
1965 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1966 break;
1967 case DP_TRAINING_PATTERN_3:
1968 DRM_ERROR("DP training pattern 3 not supported\n");
1969 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1970 break;
1971 }
1972 }
1973
ea5b213a
CW		 1974 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1975 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 1976
ea5b213a 1977 intel_dp_aux_native_write_1(intel_dp,
a4fc5ed6
KP		 1978 DP_TRAINING_PATTERN_SET,
1979 dp_train_pat);
1980
47ea7542
PZ		 1981 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
1982 DP_TRAINING_PATTERN_DISABLE) {
1983 ret = intel_dp_aux_native_write(intel_dp,
1984 DP_TRAINING_LANE0_SET,
1985 intel_dp->train_set,
1986 intel_dp->lane_count);
1987 if (ret != intel_dp->lane_count)
1988 return false;
1989 }
a4fc5ed6
KP		 1990
1991 return true;
1992}
1993
3ab9c637
ID		 1994static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
1995{
1996 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1997 struct drm_device *dev = intel_dig_port->base.base.dev;
1998 struct drm_i915_private *dev_priv = dev->dev_private;
1999 enum port port = intel_dig_port->port;
2000 uint32_t val;
2001
2002 if (!HAS_DDI(dev))
2003 return;
2004
2005 val = I915_READ(DP_TP_CTL(port));
2006 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2007 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2008 I915_WRITE(DP_TP_CTL(port), val);
2009
2010 /*
2011 * On PORT_A we can have only eDP in SST mode. There the only reason
2012 * we need to set idle transmission mode is to work around a HW issue
2013 * where we enable the pipe while not in idle link-training mode.
2014 * In this case there is requirement to wait for a minimum number of
2015 * idle patterns to be sent.
2016 */
2017 if (port == PORT_A)
2018 return;
2019
2020 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2021 1))
2022 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2023}
2024
33a34e4e 2025/* Enable corresponding port and start training pattern 1 */
c19b0669 2026void
33a34e4e 2027intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 2028{
da63a9f2 2029 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 2030 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 2031 int i;
2032 uint8_t voltage;
2033 bool clock_recovery = false;
cdb0e95b 2034 int voltage_tries, loop_tries;
ea5b213a 2035 uint32_t DP = intel_dp->DP;
a4fc5ed6 2036
affa9354 2037 if (HAS_DDI(dev))
c19b0669
PZ		 2038 intel_ddi_prepare_link_retrain(encoder);
2039
3cf2efb1
CW		 2040 /* Write the link configuration data */
2041 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
2042 intel_dp->link_configuration,
2043 DP_LINK_CONFIGURATION_SIZE);
a4fc5ed6
KP		 2044
2045 DP |= DP_PORT_EN;
1a2eb460 2046
33a34e4e 2047 memset(intel_dp->train_set, 0, 4);
a4fc5ed6 2048 voltage = 0xff;
cdb0e95b
KP		 2049 voltage_tries = 0;
2050 loop_tries = 0;
a4fc5ed6
KP		 2051 clock_recovery = false;
2052 for (;;) {
33a34e4e 2053 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
93f62dad 2054 uint8_t link_status[DP_LINK_STATUS_SIZE];
f0a3424e
PZ		 2055
2056 intel_dp_set_signal_levels(intel_dp, &DP);
a4fc5ed6 2057
a7c9655f 2058 /* Set training pattern 1 */
47ea7542 2059 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 2060 DP_TRAINING_PATTERN_1 |
2061 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6 2062 break;
a4fc5ed6 2063
a7c9655f 2064 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 2065 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2066 DRM_ERROR("failed to get link status\n");
a4fc5ed6 2067 break;
93f62dad 2068 }
a4fc5ed6 2069
01916270 2070 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 2071 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 2072 clock_recovery = true;
2073 break;
2074 }
2075
2076 /* Check to see if we've tried the max voltage */
2077 for (i = 0; i < intel_dp->lane_count; i++)
2078 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 2079 break;
3b4f819d 2080 if (i == intel_dp->lane_count) {
b06fbda3
DV		 2081 ++loop_tries;
2082 if (loop_tries == 5) {
cdb0e95b
KP		 2083 DRM_DEBUG_KMS("too many full retries, give up\n");
2084 break;
2085 }
2086 memset(intel_dp->train_set, 0, 4);
2087 voltage_tries = 0;
2088 continue;
2089 }
a4fc5ed6 2090
3cf2efb1 2091 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 2092 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 2093 ++voltage_tries;
b06fbda3
DV		 2094 if (voltage_tries == 5) {
2095 DRM_DEBUG_KMS("too many voltage retries, give up\n");
2096 break;
2097 }
2098 } else
2099 voltage_tries = 0;
2100 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 2101
3cf2efb1 2102 /* Compute new intel_dp->train_set as requested by target */
93f62dad 2103 intel_get_adjust_train(intel_dp, link_status);
a4fc5ed6
KP		 2104 }
2105
33a34e4e
JB		 2106 intel_dp->DP = DP;
2107}
2108
c19b0669 2109void
33a34e4e
JB		 2110intel_dp_complete_link_train(struct intel_dp *intel_dp)
2111{
33a34e4e 2112 bool channel_eq = false;
37f80975 2113 int tries, cr_tries;
33a34e4e
JB		 2114 uint32_t DP = intel_dp->DP;
2115
a4fc5ed6
KP		 2116 /* channel equalization */
2117 tries = 0;
37f80975 2118 cr_tries = 0;
a4fc5ed6
KP		 2119 channel_eq = false;
2120 for (;;) {
93f62dad 2121 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 2122
37f80975
JB		 2123 if (cr_tries > 5) {
2124 DRM_ERROR("failed to train DP, aborting\n");
2125 intel_dp_link_down(intel_dp);
2126 break;
2127 }
2128
f0a3424e 2129 intel_dp_set_signal_levels(intel_dp, &DP);
e3421a18 2130
a4fc5ed6 2131 /* channel eq pattern */
47ea7542 2132 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 2133 DP_TRAINING_PATTERN_2 |
2134 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6
KP		 2135 break;
2136
a7c9655f 2137 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
93f62dad 2138 if (!intel_dp_get_link_status(intel_dp, link_status))
a4fc5ed6 2139 break;
a4fc5ed6 2140
37f80975 2141 /* Make sure clock is still ok */
01916270 2142 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975
JB		 2143 intel_dp_start_link_train(intel_dp);
2144 cr_tries++;
2145 continue;
2146 }
2147
1ffdff13 2148 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 2149 channel_eq = true;
2150 break;
2151 }
a4fc5ed6 2152
37f80975
JB		 2153 /* Try 5 times, then try clock recovery if that fails */
2154 if (tries > 5) {
2155 intel_dp_link_down(intel_dp);
2156 intel_dp_start_link_train(intel_dp);
2157 tries = 0;
2158 cr_tries++;
2159 continue;
2160 }
a4fc5ed6 2161
3cf2efb1 2162 /* Compute new intel_dp->train_set as requested by target */
93f62dad 2163 intel_get_adjust_train(intel_dp, link_status);
3cf2efb1 2164 ++tries;
869184a6 2165 }
3cf2efb1 2166
3ab9c637
ID		 2167 intel_dp_set_idle_link_train(intel_dp);
2168
2169 intel_dp->DP = DP;
2170
d6c0d722 2171 if (channel_eq)
07f42258 2172 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 2173
3ab9c637
ID		 2174}
2175
2176void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2177{
2178 intel_dp_set_link_train(intel_dp, intel_dp->DP,
2179 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 2180}
2181
2182static void
ea5b213a 2183intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 2184{
da63a9f2 2185 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2186 enum port port = intel_dig_port->port;
da63a9f2 2187 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2188 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 2189 struct intel_crtc *intel_crtc =
2190 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 2191 uint32_t DP = intel_dp->DP;
a4fc5ed6 2192
c19b0669
PZ		 2193 /*
2194 * DDI code has a strict mode set sequence and we should try to respect
2195 * it, otherwise we might hang the machine in many different ways. So we
2196 * really should be disabling the port only on a complete crtc_disable
2197 * sequence. This function is just called under two conditions on DDI
2198 * code:
2199 * - Link train failed while doing crtc_enable, and on this case we
2200 * really should respect the mode set sequence and wait for a
2201 * crtc_disable.
2202 * - Someone turned the monitor off and intel_dp_check_link_status
2203 * called us. We don't need to disable the whole port on this case, so
2204 * when someone turns the monitor on again,
2205 * intel_ddi_prepare_link_retrain will take care of redoing the link
2206 * train.
2207 */
affa9354 2208 if (HAS_DDI(dev))
c19b0669
PZ		 2209 return;
2210
0c33d8d7 2211 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 2212 return;
2213
28c97730 2214 DRM_DEBUG_KMS("\n");
32f9d658 2215
bc7d38a4 2216 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 2217 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 2218 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 2219 } else {
2220 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 2221 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 2222 }
fe255d00 2223 POSTING_READ(intel_dp->output_reg);
5eb08b69 2224
ab527efc
DV		 2225 /* We don't really know why we're doing this */
2226 intel_wait_for_vblank(dev, intel_crtc->pipe);
5eb08b69 2227
493a7081 2228 if (HAS_PCH_IBX(dev) &&
1b39d6f3 2229 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 2230 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 2231
5bddd17f
EA		 2232 /* Hardware workaround: leaving our transcoder select
2233 * set to transcoder B while it's off will prevent the
2234 * corresponding HDMI output on transcoder A.
2235 *
2236 * Combine this with another hardware workaround:
2237 * transcoder select bit can only be cleared while the
2238 * port is enabled.
2239 */
2240 DP &= ~DP_PIPEB_SELECT;
2241 I915_WRITE(intel_dp->output_reg, DP);
2242
2243 /* Changes to enable or select take place the vblank
2244 * after being written.
2245 */
ff50afe9
DV		 2246 if (WARN_ON(crtc == NULL)) {
2247 /* We should never try to disable a port without a crtc
2248 * attached. For paranoia keep the code around for a
2249 * bit. */
31acbcc4
CW		 2250 POSTING_READ(intel_dp->output_reg);
2251 msleep(50);
2252 } else
ab527efc 2253 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 2254 }
2255
832afda6 2256 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 2257 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2258 POSTING_READ(intel_dp->output_reg);
f01eca2e 2259 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 2260}
2261
26d61aad
KP		 2262static bool
2263intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 2264{
577c7a50
DL		 2265 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2266
92fd8fd1 2267 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
edb39244
AJ		 2268 sizeof(intel_dp->dpcd)) == 0)
2269 return false; /* aux transfer failed */
92fd8fd1 2270
577c7a50
DL		 2271 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2272 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2273 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2274
edb39244
AJ		 2275 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2276 return false; /* DPCD not present */
2277
2278 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2279 DP_DWN_STRM_PORT_PRESENT))
2280 return true; /* native DP sink */
2281
2282 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2283 return true; /* no per-port downstream info */
2284
2285 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2286 intel_dp->downstream_ports,
2287 DP_MAX_DOWNSTREAM_PORTS) == 0)
2288 return false; /* downstream port status fetch failed */
2289
2290 return true;
92fd8fd1
KP		 2291}
2292
0d198328
AJ		 2293static void
2294intel_dp_probe_oui(struct intel_dp *intel_dp)
2295{
2296 u8 buf[3];
2297
2298 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2299 return;
2300
351cfc34
DV		 2301 ironlake_edp_panel_vdd_on(intel_dp);
2302
0d198328
AJ		 2303 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2304 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2305 buf[0], buf[1], buf[2]);
2306
2307 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2308 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2309 buf[0], buf[1], buf[2]);
351cfc34
DV		 2310
2311 ironlake_edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 2312}
2313
a60f0e38
JB		 2314static bool
2315intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2316{
2317 int ret;
2318
2319 ret = intel_dp_aux_native_read_retry(intel_dp,
2320 DP_DEVICE_SERVICE_IRQ_VECTOR,
2321 sink_irq_vector, 1);
2322 if (!ret)
2323 return false;
2324
2325 return true;
2326}
2327
2328static void
2329intel_dp_handle_test_request(struct intel_dp *intel_dp)
2330{
2331 /* NAK by default */
9324cf7f 2332 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 2333}
2334
a4fc5ed6
KP		 2335/*
2336 * According to DP spec
2337 * 5.1.2:
2338 * 1. Read DPCD
2339 * 2. Configure link according to Receiver Capabilities
2340 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2341 * 4. Check link status on receipt of hot-plug interrupt
2342 */
2343
00c09d70 2344void
ea5b213a 2345intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 2346{
da63a9f2 2347 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 2348 u8 sink_irq_vector;
93f62dad 2349 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 2350
da63a9f2 2351 if (!intel_encoder->connectors_active)
d2b996ac 2352 return;
59cd09e1 2353
da63a9f2 2354 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 2355 return;
2356
92fd8fd1 2357 /* Try to read receiver status if the link appears to be up */
93f62dad 2358 if (!intel_dp_get_link_status(intel_dp, link_status)) {
ea5b213a 2359 intel_dp_link_down(intel_dp);
a4fc5ed6
KP		 2360 return;
2361 }
2362
92fd8fd1 2363 /* Now read the DPCD to see if it's actually running */
26d61aad 2364 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 2365 intel_dp_link_down(intel_dp);
2366 return;
2367 }
2368
a60f0e38
JB		 2369 /* Try to read the source of the interrupt */
2370 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2371 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2372 /* Clear interrupt source */
2373 intel_dp_aux_native_write_1(intel_dp,
2374 DP_DEVICE_SERVICE_IRQ_VECTOR,
2375 sink_irq_vector);
2376
2377 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2378 intel_dp_handle_test_request(intel_dp);
2379 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2380 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2381 }
2382
1ffdff13 2383 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 2384 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
da63a9f2 2385 drm_get_encoder_name(&intel_encoder->base));
33a34e4e
JB		 2386 intel_dp_start_link_train(intel_dp);
2387 intel_dp_complete_link_train(intel_dp);
3ab9c637 2388 intel_dp_stop_link_train(intel_dp);
33a34e4e 2389 }
a4fc5ed6 2390}
a4fc5ed6 2391
caf9ab24 2392/* XXX this is probably wrong for multiple downstream ports */
71ba9000 2393static enum drm_connector_status
26d61aad 2394intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 2395{
caf9ab24
AJ		 2396 uint8_t *dpcd = intel_dp->dpcd;
2397 bool hpd;
2398 uint8_t type;
2399
2400 if (!intel_dp_get_dpcd(intel_dp))
2401 return connector_status_disconnected;
2402
2403 /* if there's no downstream port, we're done */
2404 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 2405 return connector_status_connected;
caf9ab24
AJ		 2406
2407 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2408 hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2409 if (hpd) {
23235177 2410 uint8_t reg;
caf9ab24 2411 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
23235177 2412 &reg, 1))
caf9ab24 2413 return connector_status_unknown;
23235177
AJ		 2414 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2415 : connector_status_disconnected;
caf9ab24
AJ		 2416 }
2417
2418 /* If no HPD, poke DDC gently */
2419 if (drm_probe_ddc(&intel_dp->adapter))
26d61aad 2420 return connector_status_connected;
caf9ab24
AJ		 2421
2422 /* Well we tried, say unknown for unreliable port types */
2423 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2424 if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2425 return connector_status_unknown;
2426
2427 /* Anything else is out of spec, warn and ignore */
2428 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 2429 return connector_status_disconnected;
71ba9000
AJ		 2430}
2431
5eb08b69 2432static enum drm_connector_status
a9756bb5 2433ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 2434{
30add22d 2435 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 2436 struct drm_i915_private *dev_priv = dev->dev_private;
2437 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5eb08b69
ZW		 2438 enum drm_connector_status status;
2439
fe16d949
CW		 2440 /* Can't disconnect eDP, but you can close the lid... */
2441 if (is_edp(intel_dp)) {
30add22d 2442 status = intel_panel_detect(dev);
fe16d949
CW		 2443 if (status == connector_status_unknown)
2444 status = connector_status_connected;
2445 return status;
2446 }
01cb9ea6 2447
1b469639
DL		 2448 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
2449 return connector_status_disconnected;
2450
26d61aad 2451 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 2452}
2453
a4fc5ed6 2454static enum drm_connector_status
a9756bb5 2455g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 2456{
30add22d 2457 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a4fc5ed6 2458 struct drm_i915_private *dev_priv = dev->dev_private;
34f2be46 2459 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
10f76a38 2460 uint32_t bit;
5eb08b69 2461
35aad75f
JB		 2462 /* Can't disconnect eDP, but you can close the lid... */
2463 if (is_edp(intel_dp)) {
2464 enum drm_connector_status status;
2465
2466 status = intel_panel_detect(dev);
2467 if (status == connector_status_unknown)
2468 status = connector_status_connected;
2469 return status;
2470 }
2471
34f2be46
VS		 2472 switch (intel_dig_port->port) {
2473 case PORT_B:
26739f12 2474 bit = PORTB_HOTPLUG_LIVE_STATUS;
a4fc5ed6 2475 break;
34f2be46 2476 case PORT_C:
26739f12 2477 bit = PORTC_HOTPLUG_LIVE_STATUS;
a4fc5ed6 2478 break;
34f2be46 2479 case PORT_D:
26739f12 2480 bit = PORTD_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2481 break;
2482 default:
2483 return connector_status_unknown;
2484 }
2485
10f76a38 2486 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 2487 return connector_status_disconnected;
2488
26d61aad 2489 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 2490}
2491
8c241fef
KP		 2492static struct edid *
2493intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2494{
9cd300e0 2495 struct intel_connector *intel_connector = to_intel_connector(connector);
d6f24d0f 2496
9cd300e0
JN		 2497 /* use cached edid if we have one */
2498 if (intel_connector->edid) {
2499 struct edid *edid;
2500 int size;
2501
2502 /* invalid edid */
2503 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 2504 return NULL;
2505
9cd300e0 2506 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
edbe1581 2507 edid = kmemdup(intel_connector->edid, size, GFP_KERNEL);
d6f24d0f
JB		 2508 if (!edid)
2509 return NULL;
2510
d6f24d0f
JB		 2511 return edid;
2512 }
8c241fef 2513
9cd300e0 2514 return drm_get_edid(connector, adapter);
8c241fef
KP		 2515}
2516
2517static int
2518intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2519{
9cd300e0 2520 struct intel_connector *intel_connector = to_intel_connector(connector);
8c241fef 2521
9cd300e0
JN		 2522 /* use cached edid if we have one */
2523 if (intel_connector->edid) {
2524 /* invalid edid */
2525 if (IS_ERR(intel_connector->edid))
2526 return 0;
2527
2528 return intel_connector_update_modes(connector,
2529 intel_connector->edid);
d6f24d0f
JB		 2530 }
2531
9cd300e0 2532 return intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 2533}
2534
a9756bb5
ZW		 2535static enum drm_connector_status
2536intel_dp_detect(struct drm_connector *connector, bool force)
2537{
2538 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 2539 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2540 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 2541 struct drm_device *dev = connector->dev;
a9756bb5
ZW		 2542 enum drm_connector_status status;
2543 struct edid *edid = NULL;
2544
2545 intel_dp->has_audio = false;
2546
2547 if (HAS_PCH_SPLIT(dev))
2548 status = ironlake_dp_detect(intel_dp);
2549 else
2550 status = g4x_dp_detect(intel_dp);
1b9be9d0 2551
a9756bb5
ZW		 2552 if (status != connector_status_connected)
2553 return status;
2554
0d198328
AJ		 2555 intel_dp_probe_oui(intel_dp);
2556
c3e5f67b
DV		 2557 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2558 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 2559 } else {
8c241fef 2560 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
f684960e
CW		 2561 if (edid) {
2562 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 2563 kfree(edid);
2564 }
a9756bb5
ZW		 2565 }
2566
d63885da
PZ		 2567 if (intel_encoder->type != INTEL_OUTPUT_EDP)
2568 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
a9756bb5 2569 return connector_status_connected;
a4fc5ed6
KP		 2570}
2571
2572static int intel_dp_get_modes(struct drm_connector *connector)
2573{
df0e9248 2574 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e 2575 struct intel_connector *intel_connector = to_intel_connector(connector);
fa90ecef 2576 struct drm_device *dev = connector->dev;
32f9d658 2577 int ret;
a4fc5ed6
KP		 2578
2579 /* We should parse the EDID data and find out if it has an audio sink
2580 */
2581
8c241fef 2582 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
f8779fda 2583 if (ret)
32f9d658
ZW		 2584 return ret;
2585
f8779fda 2586 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 2587 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 2588 struct drm_display_mode *mode;
dd06f90e
JN		 2589 mode = drm_mode_duplicate(dev,
2590 intel_connector->panel.fixed_mode);
f8779fda 2591 if (mode) {
32f9d658
ZW		 2592 drm_mode_probed_add(connector, mode);
2593 return 1;
2594 }
2595 }
2596 return 0;
a4fc5ed6
KP		 2597}
2598
1aad7ac0
CW		 2599static bool
2600intel_dp_detect_audio(struct drm_connector *connector)
2601{
2602 struct intel_dp *intel_dp = intel_attached_dp(connector);
2603 struct edid *edid;
2604 bool has_audio = false;
2605
8c241fef 2606 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1aad7ac0
CW		 2607 if (edid) {
2608 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 2609 kfree(edid);
2610 }
2611
2612 return has_audio;
2613}
2614
f684960e
CW		 2615static int
2616intel_dp_set_property(struct drm_connector *connector,
2617 struct drm_property *property,
2618 uint64_t val)
2619{
e953fd7b 2620 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 2621 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 2622 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
2623 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 2624 int ret;
2625
662595df 2626 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 2627 if (ret)
2628 return ret;
2629
3f43c48d 2630 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 2631 int i = val;
2632 bool has_audio;
2633
2634 if (i == intel_dp->force_audio)
f684960e
CW		 2635 return 0;
2636
1aad7ac0 2637 intel_dp->force_audio = i;
f684960e 2638
c3e5f67b 2639 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 2640 has_audio = intel_dp_detect_audio(connector);
2641 else
c3e5f67b 2642 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 2643
2644 if (has_audio == intel_dp->has_audio)
f684960e
CW		 2645 return 0;
2646
1aad7ac0 2647 intel_dp->has_audio = has_audio;
f684960e
CW		 2648 goto done;
2649 }
2650
e953fd7b 2651 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 2652 bool old_auto = intel_dp->color_range_auto;
2653 uint32_t old_range = intel_dp->color_range;
2654
55bc60db
VS		 2655 switch (val) {
2656 case INTEL_BROADCAST_RGB_AUTO:
2657 intel_dp->color_range_auto = true;
2658 break;
2659 case INTEL_BROADCAST_RGB_FULL:
2660 intel_dp->color_range_auto = false;
2661 intel_dp->color_range = 0;
2662 break;
2663 case INTEL_BROADCAST_RGB_LIMITED:
2664 intel_dp->color_range_auto = false;
2665 intel_dp->color_range = DP_COLOR_RANGE_16_235;
2666 break;
2667 default:
2668 return -EINVAL;
2669 }
ae4edb80
DV		 2670
2671 if (old_auto == intel_dp->color_range_auto &&
2672 old_range == intel_dp->color_range)
2673 return 0;
2674
e953fd7b
CW		 2675 goto done;
2676 }
2677
53b41837
YN		 2678 if (is_edp(intel_dp) &&
2679 property == connector->dev->mode_config.scaling_mode_property) {
2680 if (val == DRM_MODE_SCALE_NONE) {
2681 DRM_DEBUG_KMS("no scaling not supported\n");
2682 return -EINVAL;
2683 }
2684
2685 if (intel_connector->panel.fitting_mode == val) {
2686 /* the eDP scaling property is not changed */
2687 return 0;
2688 }
2689 intel_connector->panel.fitting_mode = val;
2690
2691 goto done;
2692 }
2693
f684960e
CW		 2694 return -EINVAL;
2695
2696done:
c0c36b94
CW		 2697 if (intel_encoder->base.crtc)
2698 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 2699
2700 return 0;
2701}
2702
a4fc5ed6 2703static void
73845adf 2704intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 2705{
1d508706 2706 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 2707
9cd300e0
JN		 2708 if (!IS_ERR_OR_NULL(intel_connector->edid))
2709 kfree(intel_connector->edid);
2710
acd8db10
PZ		 2711 /* Can't call is_edp() since the encoder may have been destroyed
2712 * already. */
2713 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 2714 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 2715
a4fc5ed6
KP		 2716 drm_sysfs_connector_remove(connector);
2717 drm_connector_cleanup(connector);
55f78c43 2718 kfree(connector);
a4fc5ed6
KP		 2719}
2720
00c09d70 2721void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 2722{
da63a9f2
PZ		 2723 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2724 struct intel_dp *intel_dp = &intel_dig_port->dp;
bd173813 2725 struct drm_device *dev = intel_dp_to_dev(intel_dp);
24d05927
DV		 2726
2727 i2c_del_adapter(&intel_dp->adapter);
2728 drm_encoder_cleanup(encoder);
bd943159
KP		 2729 if (is_edp(intel_dp)) {
2730 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
bd173813 2731 mutex_lock(&dev->mode_config.mutex);
bd943159 2732 ironlake_panel_vdd_off_sync(intel_dp);
bd173813 2733 mutex_unlock(&dev->mode_config.mutex);
bd943159 2734 }
da63a9f2 2735 kfree(intel_dig_port);
24d05927
DV		 2736}
2737
a4fc5ed6 2738static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
a4fc5ed6 2739 .mode_set = intel_dp_mode_set,
a4fc5ed6
KP		 2740};
2741
2742static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 2743 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 2744 .detect = intel_dp_detect,
2745 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 2746 .set_property = intel_dp_set_property,
73845adf 2747 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 2748};
2749
2750static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2751 .get_modes = intel_dp_get_modes,
2752 .mode_valid = intel_dp_mode_valid,
df0e9248 2753 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 2754};
2755
a4fc5ed6 2756static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 2757 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 2758};
2759
995b6762 2760static void
21d40d37 2761intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 2762{
fa90ecef 2763 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
c8110e52 2764
885a5014 2765 intel_dp_check_link_status(intel_dp);
c8110e52 2766}
6207937d 2767
e3421a18
ZW		 2768/* Return which DP Port should be selected for Transcoder DP control */
2769int
0206e353 2770intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 2771{
2772 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 2773 struct intel_encoder *intel_encoder;
2774 struct intel_dp *intel_dp;
e3421a18 2775
fa90ecef
PZ		 2776 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2777 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 2778
fa90ecef
PZ		 2779 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2780 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 2781 return intel_dp->output_reg;
e3421a18 2782 }
ea5b213a 2783
e3421a18
ZW		 2784 return -1;
2785}
2786
36e83a18 2787/* check the VBT to see whether the eDP is on DP-D port */
cb0953d7 2788bool intel_dpd_is_edp(struct drm_device *dev)
36e83a18
ZY		 2789{
2790 struct drm_i915_private *dev_priv = dev->dev_private;
2791 struct child_device_config *p_child;
2792 int i;
2793
41aa3448 2794 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 2795 return false;
2796
41aa3448
RV		 2797 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
2798 p_child = dev_priv->vbt.child_dev + i;
36e83a18
ZY		 2799
2800 if (p_child->dvo_port == PORT_IDPD &&
2801 p_child->device_type == DEVICE_TYPE_eDP)
2802 return true;
2803 }
2804 return false;
2805}
2806
f684960e
CW		 2807static void
2808intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2809{
53b41837
YN		 2810 struct intel_connector *intel_connector = to_intel_connector(connector);
2811
3f43c48d 2812 intel_attach_force_audio_property(connector);
e953fd7b 2813 intel_attach_broadcast_rgb_property(connector);
55bc60db 2814 intel_dp->color_range_auto = true;
53b41837
YN		 2815
2816 if (is_edp(intel_dp)) {
2817 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 2818 drm_object_attach_property(
2819 &connector->base,
53b41837 2820 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 2821 DRM_MODE_SCALE_ASPECT);
2822 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 2823 }
f684960e
CW		 2824}
2825
67a54566
DV		 2826static void
2827intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 2828 struct intel_dp *intel_dp,
2829 struct edp_power_seq *out)
67a54566
DV		 2830{
2831 struct drm_i915_private *dev_priv = dev->dev_private;
2832 struct edp_power_seq cur, vbt, spec, final;
2833 u32 pp_on, pp_off, pp_div, pp;
453c5420
JB		 2834 int pp_control_reg, pp_on_reg, pp_off_reg, pp_div_reg;
2835
2836 if (HAS_PCH_SPLIT(dev)) {
2837 pp_control_reg = PCH_PP_CONTROL;
2838 pp_on_reg = PCH_PP_ON_DELAYS;
2839 pp_off_reg = PCH_PP_OFF_DELAYS;
2840 pp_div_reg = PCH_PP_DIVISOR;
2841 } else {
2842 pp_control_reg = PIPEA_PP_CONTROL;
2843 pp_on_reg = PIPEA_PP_ON_DELAYS;
2844 pp_off_reg = PIPEA_PP_OFF_DELAYS;
2845 pp_div_reg = PIPEA_PP_DIVISOR;
2846 }
67a54566
DV		 2847
2848 /* Workaround: Need to write PP_CONTROL with the unlock key as
2849 * the very first thing. */
453c5420
JB		 2850 pp = ironlake_get_pp_control(intel_dp);
2851 I915_WRITE(pp_control_reg, pp);
67a54566 2852
453c5420
JB		 2853 pp_on = I915_READ(pp_on_reg);
2854 pp_off = I915_READ(pp_off_reg);
2855 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 2856
2857 /* Pull timing values out of registers */
2858 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2859 PANEL_POWER_UP_DELAY_SHIFT;
2860
2861 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2862 PANEL_LIGHT_ON_DELAY_SHIFT;
2863
2864 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2865 PANEL_LIGHT_OFF_DELAY_SHIFT;
2866
2867 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2868 PANEL_POWER_DOWN_DELAY_SHIFT;
2869
2870 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2871 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2872
2873 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2874 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2875
41aa3448 2876 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 2877
2878 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
2879 * our hw here, which are all in 100usec. */
2880 spec.t1_t3 = 210 * 10;
2881 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
2882 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
2883 spec.t10 = 500 * 10;
2884 /* This one is special and actually in units of 100ms, but zero
2885 * based in the hw (so we need to add 100 ms). But the sw vbt
2886 * table multiplies it with 1000 to make it in units of 100usec,
2887 * too. */
2888 spec.t11_t12 = (510 + 100) * 10;
2889
2890 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2891 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2892
2893 /* Use the max of the register settings and vbt. If both are
2894 * unset, fall back to the spec limits. */
2895#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
2896 spec.field : \
2897 max(cur.field, vbt.field))
2898 assign_final(t1_t3);
2899 assign_final(t8);
2900 assign_final(t9);
2901 assign_final(t10);
2902 assign_final(t11_t12);
2903#undef assign_final
2904
2905#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
2906 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2907 intel_dp->backlight_on_delay = get_delay(t8);
2908 intel_dp->backlight_off_delay = get_delay(t9);
2909 intel_dp->panel_power_down_delay = get_delay(t10);
2910 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2911#undef get_delay
2912
f30d26e4
JN		 2913 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2914 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2915 intel_dp->panel_power_cycle_delay);
2916
2917 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2918 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2919
2920 if (out)
2921 *out = final;
2922}
2923
2924static void
2925intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
2926 struct intel_dp *intel_dp,
2927 struct edp_power_seq *seq)
2928{
2929 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 2930 u32 pp_on, pp_off, pp_div, port_sel = 0;
2931 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
2932 int pp_on_reg, pp_off_reg, pp_div_reg;
2933
2934 if (HAS_PCH_SPLIT(dev)) {
2935 pp_on_reg = PCH_PP_ON_DELAYS;
2936 pp_off_reg = PCH_PP_OFF_DELAYS;
2937 pp_div_reg = PCH_PP_DIVISOR;
2938 } else {
2939 pp_on_reg = PIPEA_PP_ON_DELAYS;
2940 pp_off_reg = PIPEA_PP_OFF_DELAYS;
2941 pp_div_reg = PIPEA_PP_DIVISOR;
2942 }
2943
67a54566 2944 /* And finally store the new values in the power sequencer. */
f30d26e4
JN		 2945 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
2946 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
2947 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
2948 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 2949 /* Compute the divisor for the pp clock, simply match the Bspec
2950 * formula. */
453c5420 2951 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 2952 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 2953 << PANEL_POWER_CYCLE_DELAY_SHIFT);
2954
2955 /* Haswell doesn't have any port selection bits for the panel
2956 * power sequencer any more. */
bc7d38a4
ID		 2957 if (IS_VALLEYVIEW(dev)) {
2958 port_sel = I915_READ(pp_on_reg) & 0xc0000000;
2959 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
2960 if (dp_to_dig_port(intel_dp)->port == PORT_A)
453c5420 2961 port_sel = PANEL_POWER_PORT_DP_A;
67a54566 2962 else
453c5420 2963 port_sel = PANEL_POWER_PORT_DP_D;
67a54566
DV		 2964 }
2965
453c5420
JB		 2966 pp_on |= port_sel;
2967
2968 I915_WRITE(pp_on_reg, pp_on);
2969 I915_WRITE(pp_off_reg, pp_off);
2970 I915_WRITE(pp_div_reg, pp_div);
67a54566 2971
67a54566 2972 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 2973 I915_READ(pp_on_reg),
2974 I915_READ(pp_off_reg),
2975 I915_READ(pp_div_reg));
f684960e
CW		 2976}
2977
ed92f0b2
PZ		 2978static bool intel_edp_init_connector(struct intel_dp *intel_dp,
2979 struct intel_connector *intel_connector)
2980{
2981 struct drm_connector *connector = &intel_connector->base;
2982 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2983 struct drm_device *dev = intel_dig_port->base.base.dev;
2984 struct drm_i915_private *dev_priv = dev->dev_private;
2985 struct drm_display_mode *fixed_mode = NULL;
2986 struct edp_power_seq power_seq = { 0 };
2987 bool has_dpcd;
2988 struct drm_display_mode *scan;
2989 struct edid *edid;
2990
2991 if (!is_edp(intel_dp))
2992 return true;
2993
2994 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2995
2996 /* Cache DPCD and EDID for edp. */
2997 ironlake_edp_panel_vdd_on(intel_dp);
2998 has_dpcd = intel_dp_get_dpcd(intel_dp);
2999 ironlake_edp_panel_vdd_off(intel_dp, false);
3000
3001 if (has_dpcd) {
3002 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3003 dev_priv->no_aux_handshake =
3004 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3005 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3006 } else {
3007 /* if this fails, presume the device is a ghost */
3008 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 3009 return false;
3010 }
3011
3012 /* We now know it's not a ghost, init power sequence regs. */
3013 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
3014 &power_seq);
3015
3016 ironlake_edp_panel_vdd_on(intel_dp);
3017 edid = drm_get_edid(connector, &intel_dp->adapter);
3018 if (edid) {
3019 if (drm_add_edid_modes(connector, edid)) {
3020 drm_mode_connector_update_edid_property(connector,
3021 edid);
3022 drm_edid_to_eld(connector, edid);
3023 } else {
3024 kfree(edid);
3025 edid = ERR_PTR(-EINVAL);
3026 }
3027 } else {
3028 edid = ERR_PTR(-ENOENT);
3029 }
3030 intel_connector->edid = edid;
3031
3032 /* prefer fixed mode from EDID if available */
3033 list_for_each_entry(scan, &connector->probed_modes, head) {
3034 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3035 fixed_mode = drm_mode_duplicate(dev, scan);
3036 break;
3037 }
3038 }
3039
3040 /* fallback to VBT if available for eDP */
3041 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3042 fixed_mode = drm_mode_duplicate(dev,
3043 dev_priv->vbt.lfp_lvds_vbt_mode);
3044 if (fixed_mode)
3045 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3046 }
3047
3048 ironlake_edp_panel_vdd_off(intel_dp, false);
3049
3050 intel_panel_init(&intel_connector->panel, fixed_mode);
3051 intel_panel_setup_backlight(connector);
3052
3053 return true;
3054}
3055
16c25533 3056bool
f0fec3f2
PZ		 3057intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
3058 struct intel_connector *intel_connector)
a4fc5ed6 3059{
f0fec3f2
PZ		 3060 struct drm_connector *connector = &intel_connector->base;
3061 struct intel_dp *intel_dp = &intel_dig_port->dp;
3062 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3063 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 3064 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 3065 enum port port = intel_dig_port->port;
5eb08b69 3066 const char *name = NULL;
b2a14755 3067 int type, error;
a4fc5ed6 3068
0767935e
DV		 3069 /* Preserve the current hw state. */
3070 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 3071 intel_dp->attached_connector = intel_connector;
3d3dc149 3072
f7d24902 3073 type = DRM_MODE_CONNECTOR_DisplayPort;
19c03924
GB		 3074 /*
3075 * FIXME : We need to initialize built-in panels before external panels.
3076 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
3077 */
f7d24902
ID		 3078 switch (port) {
3079 case PORT_A:
b329530c 3080 type = DRM_MODE_CONNECTOR_eDP;
f7d24902
ID		 3081 break;
3082 case PORT_C:
3083 if (IS_VALLEYVIEW(dev))
3084 type = DRM_MODE_CONNECTOR_eDP;
3085 break;
3086 case PORT_D:
3087 if (HAS_PCH_SPLIT(dev) && intel_dpd_is_edp(dev))
3088 type = DRM_MODE_CONNECTOR_eDP;
3089 break;
3090 default: /* silence GCC warning */
3091 break;
b329530c
AJ		 3092 }
3093
f7d24902
ID		 3094 /*
3095 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3096 * for DP the encoder type can be set by the caller to
3097 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3098 */
3099 if (type == DRM_MODE_CONNECTOR_eDP)
3100 intel_encoder->type = INTEL_OUTPUT_EDP;
3101
e7281eab
ID		 3102 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3103 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3104 port_name(port));
3105
b329530c 3106 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 3107 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3108
a4fc5ed6
KP		 3109 connector->interlace_allowed = true;
3110 connector->doublescan_allowed = 0;
3111
f0fec3f2
PZ		 3112 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
3113 ironlake_panel_vdd_work);
a4fc5ed6 3114
df0e9248 3115 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 3116 drm_sysfs_connector_add(connector);
3117
affa9354 3118 if (HAS_DDI(dev))
bcbc889b
PZ		 3119 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3120 else
3121 intel_connector->get_hw_state = intel_connector_get_hw_state;
3122
9ed35ab1
PZ		 3123 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
3124 if (HAS_DDI(dev)) {
3125 switch (intel_dig_port->port) {
3126 case PORT_A:
3127 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
3128 break;
3129 case PORT_B:
3130 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
3131 break;
3132 case PORT_C:
3133 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
3134 break;
3135 case PORT_D:
3136 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
3137 break;
3138 default:
3139 BUG();
3140 }
3141 }
e8cb4558 3142
a4fc5ed6 3143 /* Set up the DDC bus. */
ab9d7c30
PZ		 3144 switch (port) {
3145 case PORT_A:
1d843f9d 3146 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 3147 name = "DPDDC-A";
3148 break;
3149 case PORT_B:
1d843f9d 3150 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 3151 name = "DPDDC-B";
3152 break;
3153 case PORT_C:
1d843f9d 3154 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 3155 name = "DPDDC-C";
3156 break;
3157 case PORT_D:
1d843f9d 3158 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 3159 name = "DPDDC-D";
3160 break;
3161 default:
ad1c0b19 3162 BUG();
5eb08b69
ZW		 3163 }
3164
b2a14755
PZ		 3165 error = intel_dp_i2c_init(intel_dp, intel_connector, name);
3166 WARN(error, "intel_dp_i2c_init failed with error %d for port %c\n",
3167 error, port_name(port));
c1f05264 3168
b2f246a8 3169 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
15b1d171
PZ		 3170 i2c_del_adapter(&intel_dp->adapter);
3171 if (is_edp(intel_dp)) {
3172 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3173 mutex_lock(&dev->mode_config.mutex);
3174 ironlake_panel_vdd_off_sync(intel_dp);
3175 mutex_unlock(&dev->mode_config.mutex);
3176 }
b2f246a8
PZ		 3177 drm_sysfs_connector_remove(connector);
3178 drm_connector_cleanup(connector);
16c25533 3179 return false;
b2f246a8 3180 }
32f9d658 3181
f684960e
CW		 3182 intel_dp_add_properties(intel_dp, connector);
3183
a4fc5ed6
KP		 3184 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3185 * 0xd. Failure to do so will result in spurious interrupts being
3186 * generated on the port when a cable is not attached.
3187 */
3188 if (IS_G4X(dev) && !IS_GM45(dev)) {
3189 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3190 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3191 }
16c25533
PZ		 3192
3193 return true;
a4fc5ed6 3194}
f0fec3f2
PZ		 3195
3196void
3197intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3198{
3199 struct intel_digital_port *intel_dig_port;
3200 struct intel_encoder *intel_encoder;
3201 struct drm_encoder *encoder;
3202 struct intel_connector *intel_connector;
3203
3204 intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
3205 if (!intel_dig_port)
3206 return;
3207
3208 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
3209 if (!intel_connector) {
3210 kfree(intel_dig_port);
3211 return;
3212 }
3213
3214 intel_encoder = &intel_dig_port->base;
3215 encoder = &intel_encoder->base;
3216
3217 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3218 DRM_MODE_ENCODER_TMDS);
00c09d70 3219 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
f0fec3f2 3220
5bfe2ac0 3221 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70
PZ		 3222 intel_encoder->enable = intel_enable_dp;
3223 intel_encoder->pre_enable = intel_pre_enable_dp;
3224 intel_encoder->disable = intel_disable_dp;
3225 intel_encoder->post_disable = intel_post_disable_dp;
3226 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 3227 intel_encoder->get_config = intel_dp_get_config;
89b667f8
JB		 3228 if (IS_VALLEYVIEW(dev))
3229 intel_encoder->pre_pll_enable = intel_dp_pre_pll_enable;
f0fec3f2 3230
174edf1f 3231 intel_dig_port->port = port;
f0fec3f2
PZ		 3232 intel_dig_port->dp.output_reg = output_reg;
3233
00c09d70 3234 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
f0fec3f2
PZ		 3235 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3236 intel_encoder->cloneable = false;
3237 intel_encoder->hot_plug = intel_dp_hot_plug;
3238
15b1d171
PZ		 3239 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
3240 drm_encoder_cleanup(encoder);
3241 kfree(intel_dig_port);
b2f246a8 3242 kfree(intel_connector);
15b1d171 3243 }
f0fec3f2 3244}
Linux 6.x block layer and io_uring tree(s)