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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
c1c7af60 JB |
27 | #include <linux/module.h> |
28 | #include <linux/input.h> | |
79e53945 | 29 | #include <linux/i2c.h> |
7662c8bd | 30 | #include <linux/kernel.h> |
5a0e3ad6 | 31 | #include <linux/slab.h> |
9cce37f4 | 32 | #include <linux/vgaarb.h> |
79e53945 JB |
33 | #include "drmP.h" |
34 | #include "intel_drv.h" | |
35 | #include "i915_drm.h" | |
36 | #include "i915_drv.h" | |
e5510fac | 37 | #include "i915_trace.h" |
ab2c0672 | 38 | #include "drm_dp_helper.h" |
79e53945 JB |
39 | |
40 | #include "drm_crtc_helper.h" | |
41 | ||
32f9d658 ZW |
42 | #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) |
43 | ||
79e53945 | 44 | bool intel_pipe_has_type (struct drm_crtc *crtc, int type); |
7662c8bd | 45 | static void intel_update_watermarks(struct drm_device *dev); |
3dec0095 | 46 | static void intel_increase_pllclock(struct drm_crtc *crtc); |
6b383a7f | 47 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
79e53945 JB |
48 | |
49 | typedef struct { | |
50 | /* given values */ | |
51 | int n; | |
52 | int m1, m2; | |
53 | int p1, p2; | |
54 | /* derived values */ | |
55 | int dot; | |
56 | int vco; | |
57 | int m; | |
58 | int p; | |
59 | } intel_clock_t; | |
60 | ||
61 | typedef struct { | |
62 | int min, max; | |
63 | } intel_range_t; | |
64 | ||
65 | typedef struct { | |
66 | int dot_limit; | |
67 | int p2_slow, p2_fast; | |
68 | } intel_p2_t; | |
69 | ||
70 | #define INTEL_P2_NUM 2 | |
d4906093 ML |
71 | typedef struct intel_limit intel_limit_t; |
72 | struct intel_limit { | |
79e53945 JB |
73 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
74 | intel_p2_t p2; | |
d4906093 ML |
75 | bool (* find_pll)(const intel_limit_t *, struct drm_crtc *, |
76 | int, int, intel_clock_t *); | |
77 | }; | |
79e53945 JB |
78 | |
79 | #define I8XX_DOT_MIN 25000 | |
80 | #define I8XX_DOT_MAX 350000 | |
81 | #define I8XX_VCO_MIN 930000 | |
82 | #define I8XX_VCO_MAX 1400000 | |
83 | #define I8XX_N_MIN 3 | |
84 | #define I8XX_N_MAX 16 | |
85 | #define I8XX_M_MIN 96 | |
86 | #define I8XX_M_MAX 140 | |
87 | #define I8XX_M1_MIN 18 | |
88 | #define I8XX_M1_MAX 26 | |
89 | #define I8XX_M2_MIN 6 | |
90 | #define I8XX_M2_MAX 16 | |
91 | #define I8XX_P_MIN 4 | |
92 | #define I8XX_P_MAX 128 | |
93 | #define I8XX_P1_MIN 2 | |
94 | #define I8XX_P1_MAX 33 | |
95 | #define I8XX_P1_LVDS_MIN 1 | |
96 | #define I8XX_P1_LVDS_MAX 6 | |
97 | #define I8XX_P2_SLOW 4 | |
98 | #define I8XX_P2_FAST 2 | |
99 | #define I8XX_P2_LVDS_SLOW 14 | |
0c2e3952 | 100 | #define I8XX_P2_LVDS_FAST 7 |
79e53945 JB |
101 | #define I8XX_P2_SLOW_LIMIT 165000 |
102 | ||
103 | #define I9XX_DOT_MIN 20000 | |
104 | #define I9XX_DOT_MAX 400000 | |
105 | #define I9XX_VCO_MIN 1400000 | |
106 | #define I9XX_VCO_MAX 2800000 | |
f2b115e6 AJ |
107 | #define PINEVIEW_VCO_MIN 1700000 |
108 | #define PINEVIEW_VCO_MAX 3500000 | |
f3cade5c KH |
109 | #define I9XX_N_MIN 1 |
110 | #define I9XX_N_MAX 6 | |
f2b115e6 AJ |
111 | /* Pineview's Ncounter is a ring counter */ |
112 | #define PINEVIEW_N_MIN 3 | |
113 | #define PINEVIEW_N_MAX 6 | |
79e53945 JB |
114 | #define I9XX_M_MIN 70 |
115 | #define I9XX_M_MAX 120 | |
f2b115e6 AJ |
116 | #define PINEVIEW_M_MIN 2 |
117 | #define PINEVIEW_M_MAX 256 | |
79e53945 | 118 | #define I9XX_M1_MIN 10 |
f3cade5c | 119 | #define I9XX_M1_MAX 22 |
79e53945 JB |
120 | #define I9XX_M2_MIN 5 |
121 | #define I9XX_M2_MAX 9 | |
f2b115e6 AJ |
122 | /* Pineview M1 is reserved, and must be 0 */ |
123 | #define PINEVIEW_M1_MIN 0 | |
124 | #define PINEVIEW_M1_MAX 0 | |
125 | #define PINEVIEW_M2_MIN 0 | |
126 | #define PINEVIEW_M2_MAX 254 | |
79e53945 JB |
127 | #define I9XX_P_SDVO_DAC_MIN 5 |
128 | #define I9XX_P_SDVO_DAC_MAX 80 | |
129 | #define I9XX_P_LVDS_MIN 7 | |
130 | #define I9XX_P_LVDS_MAX 98 | |
f2b115e6 AJ |
131 | #define PINEVIEW_P_LVDS_MIN 7 |
132 | #define PINEVIEW_P_LVDS_MAX 112 | |
79e53945 JB |
133 | #define I9XX_P1_MIN 1 |
134 | #define I9XX_P1_MAX 8 | |
135 | #define I9XX_P2_SDVO_DAC_SLOW 10 | |
136 | #define I9XX_P2_SDVO_DAC_FAST 5 | |
137 | #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000 | |
138 | #define I9XX_P2_LVDS_SLOW 14 | |
139 | #define I9XX_P2_LVDS_FAST 7 | |
140 | #define I9XX_P2_LVDS_SLOW_LIMIT 112000 | |
141 | ||
044c7c41 ML |
142 | /*The parameter is for SDVO on G4x platform*/ |
143 | #define G4X_DOT_SDVO_MIN 25000 | |
144 | #define G4X_DOT_SDVO_MAX 270000 | |
145 | #define G4X_VCO_MIN 1750000 | |
146 | #define G4X_VCO_MAX 3500000 | |
147 | #define G4X_N_SDVO_MIN 1 | |
148 | #define G4X_N_SDVO_MAX 4 | |
149 | #define G4X_M_SDVO_MIN 104 | |
150 | #define G4X_M_SDVO_MAX 138 | |
151 | #define G4X_M1_SDVO_MIN 17 | |
152 | #define G4X_M1_SDVO_MAX 23 | |
153 | #define G4X_M2_SDVO_MIN 5 | |
154 | #define G4X_M2_SDVO_MAX 11 | |
155 | #define G4X_P_SDVO_MIN 10 | |
156 | #define G4X_P_SDVO_MAX 30 | |
157 | #define G4X_P1_SDVO_MIN 1 | |
158 | #define G4X_P1_SDVO_MAX 3 | |
159 | #define G4X_P2_SDVO_SLOW 10 | |
160 | #define G4X_P2_SDVO_FAST 10 | |
161 | #define G4X_P2_SDVO_LIMIT 270000 | |
162 | ||
163 | /*The parameter is for HDMI_DAC on G4x platform*/ | |
164 | #define G4X_DOT_HDMI_DAC_MIN 22000 | |
165 | #define G4X_DOT_HDMI_DAC_MAX 400000 | |
166 | #define G4X_N_HDMI_DAC_MIN 1 | |
167 | #define G4X_N_HDMI_DAC_MAX 4 | |
168 | #define G4X_M_HDMI_DAC_MIN 104 | |
169 | #define G4X_M_HDMI_DAC_MAX 138 | |
170 | #define G4X_M1_HDMI_DAC_MIN 16 | |
171 | #define G4X_M1_HDMI_DAC_MAX 23 | |
172 | #define G4X_M2_HDMI_DAC_MIN 5 | |
173 | #define G4X_M2_HDMI_DAC_MAX 11 | |
174 | #define G4X_P_HDMI_DAC_MIN 5 | |
175 | #define G4X_P_HDMI_DAC_MAX 80 | |
176 | #define G4X_P1_HDMI_DAC_MIN 1 | |
177 | #define G4X_P1_HDMI_DAC_MAX 8 | |
178 | #define G4X_P2_HDMI_DAC_SLOW 10 | |
179 | #define G4X_P2_HDMI_DAC_FAST 5 | |
180 | #define G4X_P2_HDMI_DAC_LIMIT 165000 | |
181 | ||
182 | /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/ | |
183 | #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000 | |
184 | #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000 | |
185 | #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1 | |
186 | #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3 | |
187 | #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104 | |
188 | #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138 | |
189 | #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17 | |
190 | #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23 | |
191 | #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5 | |
192 | #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11 | |
193 | #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28 | |
194 | #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112 | |
195 | #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2 | |
196 | #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8 | |
197 | #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14 | |
198 | #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14 | |
199 | #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0 | |
200 | ||
201 | /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/ | |
202 | #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000 | |
203 | #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000 | |
204 | #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1 | |
205 | #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3 | |
206 | #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104 | |
207 | #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138 | |
208 | #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17 | |
209 | #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23 | |
210 | #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5 | |
211 | #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11 | |
212 | #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14 | |
213 | #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42 | |
214 | #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2 | |
215 | #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6 | |
216 | #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7 | |
217 | #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7 | |
218 | #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0 | |
219 | ||
a4fc5ed6 KP |
220 | /*The parameter is for DISPLAY PORT on G4x platform*/ |
221 | #define G4X_DOT_DISPLAY_PORT_MIN 161670 | |
222 | #define G4X_DOT_DISPLAY_PORT_MAX 227000 | |
223 | #define G4X_N_DISPLAY_PORT_MIN 1 | |
224 | #define G4X_N_DISPLAY_PORT_MAX 2 | |
225 | #define G4X_M_DISPLAY_PORT_MIN 97 | |
226 | #define G4X_M_DISPLAY_PORT_MAX 108 | |
227 | #define G4X_M1_DISPLAY_PORT_MIN 0x10 | |
228 | #define G4X_M1_DISPLAY_PORT_MAX 0x12 | |
229 | #define G4X_M2_DISPLAY_PORT_MIN 0x05 | |
230 | #define G4X_M2_DISPLAY_PORT_MAX 0x06 | |
231 | #define G4X_P_DISPLAY_PORT_MIN 10 | |
232 | #define G4X_P_DISPLAY_PORT_MAX 20 | |
233 | #define G4X_P1_DISPLAY_PORT_MIN 1 | |
234 | #define G4X_P1_DISPLAY_PORT_MAX 2 | |
235 | #define G4X_P2_DISPLAY_PORT_SLOW 10 | |
236 | #define G4X_P2_DISPLAY_PORT_FAST 10 | |
237 | #define G4X_P2_DISPLAY_PORT_LIMIT 0 | |
238 | ||
bad720ff | 239 | /* Ironlake / Sandybridge */ |
2c07245f ZW |
240 | /* as we calculate clock using (register_value + 2) for |
241 | N/M1/M2, so here the range value for them is (actual_value-2). | |
242 | */ | |
f2b115e6 AJ |
243 | #define IRONLAKE_DOT_MIN 25000 |
244 | #define IRONLAKE_DOT_MAX 350000 | |
245 | #define IRONLAKE_VCO_MIN 1760000 | |
246 | #define IRONLAKE_VCO_MAX 3510000 | |
f2b115e6 | 247 | #define IRONLAKE_M1_MIN 12 |
a59e385e | 248 | #define IRONLAKE_M1_MAX 22 |
f2b115e6 AJ |
249 | #define IRONLAKE_M2_MIN 5 |
250 | #define IRONLAKE_M2_MAX 9 | |
f2b115e6 | 251 | #define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */ |
2c07245f | 252 | |
b91ad0ec ZW |
253 | /* We have parameter ranges for different type of outputs. */ |
254 | ||
255 | /* DAC & HDMI Refclk 120Mhz */ | |
256 | #define IRONLAKE_DAC_N_MIN 1 | |
257 | #define IRONLAKE_DAC_N_MAX 5 | |
258 | #define IRONLAKE_DAC_M_MIN 79 | |
259 | #define IRONLAKE_DAC_M_MAX 127 | |
260 | #define IRONLAKE_DAC_P_MIN 5 | |
261 | #define IRONLAKE_DAC_P_MAX 80 | |
262 | #define IRONLAKE_DAC_P1_MIN 1 | |
263 | #define IRONLAKE_DAC_P1_MAX 8 | |
264 | #define IRONLAKE_DAC_P2_SLOW 10 | |
265 | #define IRONLAKE_DAC_P2_FAST 5 | |
266 | ||
267 | /* LVDS single-channel 120Mhz refclk */ | |
268 | #define IRONLAKE_LVDS_S_N_MIN 1 | |
269 | #define IRONLAKE_LVDS_S_N_MAX 3 | |
270 | #define IRONLAKE_LVDS_S_M_MIN 79 | |
271 | #define IRONLAKE_LVDS_S_M_MAX 118 | |
272 | #define IRONLAKE_LVDS_S_P_MIN 28 | |
273 | #define IRONLAKE_LVDS_S_P_MAX 112 | |
274 | #define IRONLAKE_LVDS_S_P1_MIN 2 | |
275 | #define IRONLAKE_LVDS_S_P1_MAX 8 | |
276 | #define IRONLAKE_LVDS_S_P2_SLOW 14 | |
277 | #define IRONLAKE_LVDS_S_P2_FAST 14 | |
278 | ||
279 | /* LVDS dual-channel 120Mhz refclk */ | |
280 | #define IRONLAKE_LVDS_D_N_MIN 1 | |
281 | #define IRONLAKE_LVDS_D_N_MAX 3 | |
282 | #define IRONLAKE_LVDS_D_M_MIN 79 | |
283 | #define IRONLAKE_LVDS_D_M_MAX 127 | |
284 | #define IRONLAKE_LVDS_D_P_MIN 14 | |
285 | #define IRONLAKE_LVDS_D_P_MAX 56 | |
286 | #define IRONLAKE_LVDS_D_P1_MIN 2 | |
287 | #define IRONLAKE_LVDS_D_P1_MAX 8 | |
288 | #define IRONLAKE_LVDS_D_P2_SLOW 7 | |
289 | #define IRONLAKE_LVDS_D_P2_FAST 7 | |
290 | ||
291 | /* LVDS single-channel 100Mhz refclk */ | |
292 | #define IRONLAKE_LVDS_S_SSC_N_MIN 1 | |
293 | #define IRONLAKE_LVDS_S_SSC_N_MAX 2 | |
294 | #define IRONLAKE_LVDS_S_SSC_M_MIN 79 | |
295 | #define IRONLAKE_LVDS_S_SSC_M_MAX 126 | |
296 | #define IRONLAKE_LVDS_S_SSC_P_MIN 28 | |
297 | #define IRONLAKE_LVDS_S_SSC_P_MAX 112 | |
298 | #define IRONLAKE_LVDS_S_SSC_P1_MIN 2 | |
299 | #define IRONLAKE_LVDS_S_SSC_P1_MAX 8 | |
300 | #define IRONLAKE_LVDS_S_SSC_P2_SLOW 14 | |
301 | #define IRONLAKE_LVDS_S_SSC_P2_FAST 14 | |
302 | ||
303 | /* LVDS dual-channel 100Mhz refclk */ | |
304 | #define IRONLAKE_LVDS_D_SSC_N_MIN 1 | |
305 | #define IRONLAKE_LVDS_D_SSC_N_MAX 3 | |
306 | #define IRONLAKE_LVDS_D_SSC_M_MIN 79 | |
307 | #define IRONLAKE_LVDS_D_SSC_M_MAX 126 | |
308 | #define IRONLAKE_LVDS_D_SSC_P_MIN 14 | |
309 | #define IRONLAKE_LVDS_D_SSC_P_MAX 42 | |
310 | #define IRONLAKE_LVDS_D_SSC_P1_MIN 2 | |
311 | #define IRONLAKE_LVDS_D_SSC_P1_MAX 6 | |
312 | #define IRONLAKE_LVDS_D_SSC_P2_SLOW 7 | |
313 | #define IRONLAKE_LVDS_D_SSC_P2_FAST 7 | |
314 | ||
315 | /* DisplayPort */ | |
316 | #define IRONLAKE_DP_N_MIN 1 | |
317 | #define IRONLAKE_DP_N_MAX 2 | |
318 | #define IRONLAKE_DP_M_MIN 81 | |
319 | #define IRONLAKE_DP_M_MAX 90 | |
320 | #define IRONLAKE_DP_P_MIN 10 | |
321 | #define IRONLAKE_DP_P_MAX 20 | |
322 | #define IRONLAKE_DP_P2_FAST 10 | |
323 | #define IRONLAKE_DP_P2_SLOW 10 | |
324 | #define IRONLAKE_DP_P2_LIMIT 0 | |
325 | #define IRONLAKE_DP_P1_MIN 1 | |
326 | #define IRONLAKE_DP_P1_MAX 2 | |
4547668a | 327 | |
2377b741 JB |
328 | /* FDI */ |
329 | #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */ | |
330 | ||
d4906093 ML |
331 | static bool |
332 | intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
333 | int target, int refclk, intel_clock_t *best_clock); | |
334 | static bool | |
335 | intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
336 | int target, int refclk, intel_clock_t *best_clock); | |
79e53945 | 337 | |
a4fc5ed6 KP |
338 | static bool |
339 | intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc, | |
340 | int target, int refclk, intel_clock_t *best_clock); | |
5eb08b69 | 341 | static bool |
f2b115e6 AJ |
342 | intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc, |
343 | int target, int refclk, intel_clock_t *best_clock); | |
a4fc5ed6 | 344 | |
021357ac CW |
345 | static inline u32 /* units of 100MHz */ |
346 | intel_fdi_link_freq(struct drm_device *dev) | |
347 | { | |
8b99e68c CW |
348 | if (IS_GEN5(dev)) { |
349 | struct drm_i915_private *dev_priv = dev->dev_private; | |
350 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
351 | } else | |
352 | return 27; | |
021357ac CW |
353 | } |
354 | ||
e4b36699 | 355 | static const intel_limit_t intel_limits_i8xx_dvo = { |
79e53945 JB |
356 | .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX }, |
357 | .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX }, | |
358 | .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX }, | |
359 | .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX }, | |
360 | .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX }, | |
361 | .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX }, | |
362 | .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX }, | |
363 | .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX }, | |
364 | .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT, | |
365 | .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST }, | |
d4906093 | 366 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
367 | }; |
368 | ||
369 | static const intel_limit_t intel_limits_i8xx_lvds = { | |
79e53945 JB |
370 | .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX }, |
371 | .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX }, | |
372 | .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX }, | |
373 | .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX }, | |
374 | .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX }, | |
375 | .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX }, | |
376 | .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX }, | |
377 | .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX }, | |
378 | .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT, | |
379 | .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST }, | |
d4906093 | 380 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
381 | }; |
382 | ||
383 | static const intel_limit_t intel_limits_i9xx_sdvo = { | |
79e53945 JB |
384 | .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX }, |
385 | .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX }, | |
386 | .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX }, | |
387 | .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX }, | |
388 | .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX }, | |
389 | .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX }, | |
390 | .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX }, | |
391 | .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX }, | |
392 | .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT, | |
393 | .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST }, | |
d4906093 | 394 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
395 | }; |
396 | ||
397 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
79e53945 JB |
398 | .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX }, |
399 | .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX }, | |
400 | .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX }, | |
401 | .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX }, | |
402 | .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX }, | |
403 | .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX }, | |
404 | .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX }, | |
405 | .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX }, | |
406 | /* The single-channel range is 25-112Mhz, and dual-channel | |
407 | * is 80-224Mhz. Prefer single channel as much as possible. | |
408 | */ | |
409 | .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT, | |
410 | .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST }, | |
d4906093 | 411 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
412 | }; |
413 | ||
044c7c41 | 414 | /* below parameter and function is for G4X Chipset Family*/ |
e4b36699 | 415 | static const intel_limit_t intel_limits_g4x_sdvo = { |
044c7c41 ML |
416 | .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX }, |
417 | .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX}, | |
418 | .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX }, | |
419 | .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX }, | |
420 | .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX }, | |
421 | .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX }, | |
422 | .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX }, | |
423 | .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX}, | |
424 | .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT, | |
425 | .p2_slow = G4X_P2_SDVO_SLOW, | |
426 | .p2_fast = G4X_P2_SDVO_FAST | |
427 | }, | |
d4906093 | 428 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
429 | }; |
430 | ||
431 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
044c7c41 ML |
432 | .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX }, |
433 | .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX}, | |
434 | .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX }, | |
435 | .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX }, | |
436 | .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX }, | |
437 | .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX }, | |
438 | .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX }, | |
439 | .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX}, | |
440 | .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT, | |
441 | .p2_slow = G4X_P2_HDMI_DAC_SLOW, | |
442 | .p2_fast = G4X_P2_HDMI_DAC_FAST | |
443 | }, | |
d4906093 | 444 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
445 | }; |
446 | ||
447 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
044c7c41 ML |
448 | .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN, |
449 | .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX }, | |
450 | .vco = { .min = G4X_VCO_MIN, | |
451 | .max = G4X_VCO_MAX }, | |
452 | .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN, | |
453 | .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX }, | |
454 | .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN, | |
455 | .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX }, | |
456 | .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN, | |
457 | .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX }, | |
458 | .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN, | |
459 | .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX }, | |
460 | .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN, | |
461 | .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX }, | |
462 | .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN, | |
463 | .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX }, | |
464 | .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT, | |
465 | .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW, | |
466 | .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST | |
467 | }, | |
d4906093 | 468 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
469 | }; |
470 | ||
471 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
044c7c41 ML |
472 | .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN, |
473 | .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX }, | |
474 | .vco = { .min = G4X_VCO_MIN, | |
475 | .max = G4X_VCO_MAX }, | |
476 | .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN, | |
477 | .max = G4X_N_DUAL_CHANNEL_LVDS_MAX }, | |
478 | .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN, | |
479 | .max = G4X_M_DUAL_CHANNEL_LVDS_MAX }, | |
480 | .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN, | |
481 | .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX }, | |
482 | .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN, | |
483 | .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX }, | |
484 | .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN, | |
485 | .max = G4X_P_DUAL_CHANNEL_LVDS_MAX }, | |
486 | .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN, | |
487 | .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX }, | |
488 | .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT, | |
489 | .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW, | |
490 | .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST | |
491 | }, | |
d4906093 | 492 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
493 | }; |
494 | ||
495 | static const intel_limit_t intel_limits_g4x_display_port = { | |
a4fc5ed6 KP |
496 | .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN, |
497 | .max = G4X_DOT_DISPLAY_PORT_MAX }, | |
498 | .vco = { .min = G4X_VCO_MIN, | |
499 | .max = G4X_VCO_MAX}, | |
500 | .n = { .min = G4X_N_DISPLAY_PORT_MIN, | |
501 | .max = G4X_N_DISPLAY_PORT_MAX }, | |
502 | .m = { .min = G4X_M_DISPLAY_PORT_MIN, | |
503 | .max = G4X_M_DISPLAY_PORT_MAX }, | |
504 | .m1 = { .min = G4X_M1_DISPLAY_PORT_MIN, | |
505 | .max = G4X_M1_DISPLAY_PORT_MAX }, | |
506 | .m2 = { .min = G4X_M2_DISPLAY_PORT_MIN, | |
507 | .max = G4X_M2_DISPLAY_PORT_MAX }, | |
508 | .p = { .min = G4X_P_DISPLAY_PORT_MIN, | |
509 | .max = G4X_P_DISPLAY_PORT_MAX }, | |
510 | .p1 = { .min = G4X_P1_DISPLAY_PORT_MIN, | |
511 | .max = G4X_P1_DISPLAY_PORT_MAX}, | |
512 | .p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT, | |
513 | .p2_slow = G4X_P2_DISPLAY_PORT_SLOW, | |
514 | .p2_fast = G4X_P2_DISPLAY_PORT_FAST }, | |
515 | .find_pll = intel_find_pll_g4x_dp, | |
e4b36699 KP |
516 | }; |
517 | ||
f2b115e6 | 518 | static const intel_limit_t intel_limits_pineview_sdvo = { |
2177832f | 519 | .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX}, |
f2b115e6 AJ |
520 | .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX }, |
521 | .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX }, | |
522 | .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX }, | |
523 | .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX }, | |
524 | .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX }, | |
2177832f SL |
525 | .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX }, |
526 | .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX }, | |
527 | .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT, | |
528 | .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST }, | |
6115707b | 529 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
530 | }; |
531 | ||
f2b115e6 | 532 | static const intel_limit_t intel_limits_pineview_lvds = { |
2177832f | 533 | .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX }, |
f2b115e6 AJ |
534 | .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX }, |
535 | .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX }, | |
536 | .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX }, | |
537 | .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX }, | |
538 | .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX }, | |
539 | .p = { .min = PINEVIEW_P_LVDS_MIN, .max = PINEVIEW_P_LVDS_MAX }, | |
2177832f | 540 | .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX }, |
f2b115e6 | 541 | /* Pineview only supports single-channel mode. */ |
2177832f SL |
542 | .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT, |
543 | .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW }, | |
6115707b | 544 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
545 | }; |
546 | ||
b91ad0ec | 547 | static const intel_limit_t intel_limits_ironlake_dac = { |
f2b115e6 AJ |
548 | .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX }, |
549 | .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX }, | |
b91ad0ec ZW |
550 | .n = { .min = IRONLAKE_DAC_N_MIN, .max = IRONLAKE_DAC_N_MAX }, |
551 | .m = { .min = IRONLAKE_DAC_M_MIN, .max = IRONLAKE_DAC_M_MAX }, | |
f2b115e6 AJ |
552 | .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX }, |
553 | .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX }, | |
b91ad0ec ZW |
554 | .p = { .min = IRONLAKE_DAC_P_MIN, .max = IRONLAKE_DAC_P_MAX }, |
555 | .p1 = { .min = IRONLAKE_DAC_P1_MIN, .max = IRONLAKE_DAC_P1_MAX }, | |
f2b115e6 | 556 | .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT, |
b91ad0ec ZW |
557 | .p2_slow = IRONLAKE_DAC_P2_SLOW, |
558 | .p2_fast = IRONLAKE_DAC_P2_FAST }, | |
4547668a | 559 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
560 | }; |
561 | ||
b91ad0ec | 562 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
f2b115e6 AJ |
563 | .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX }, |
564 | .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX }, | |
b91ad0ec ZW |
565 | .n = { .min = IRONLAKE_LVDS_S_N_MIN, .max = IRONLAKE_LVDS_S_N_MAX }, |
566 | .m = { .min = IRONLAKE_LVDS_S_M_MIN, .max = IRONLAKE_LVDS_S_M_MAX }, | |
f2b115e6 AJ |
567 | .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX }, |
568 | .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX }, | |
b91ad0ec ZW |
569 | .p = { .min = IRONLAKE_LVDS_S_P_MIN, .max = IRONLAKE_LVDS_S_P_MAX }, |
570 | .p1 = { .min = IRONLAKE_LVDS_S_P1_MIN, .max = IRONLAKE_LVDS_S_P1_MAX }, | |
f2b115e6 | 571 | .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT, |
b91ad0ec ZW |
572 | .p2_slow = IRONLAKE_LVDS_S_P2_SLOW, |
573 | .p2_fast = IRONLAKE_LVDS_S_P2_FAST }, | |
574 | .find_pll = intel_g4x_find_best_PLL, | |
575 | }; | |
576 | ||
577 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
578 | .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX }, | |
579 | .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX }, | |
580 | .n = { .min = IRONLAKE_LVDS_D_N_MIN, .max = IRONLAKE_LVDS_D_N_MAX }, | |
581 | .m = { .min = IRONLAKE_LVDS_D_M_MIN, .max = IRONLAKE_LVDS_D_M_MAX }, | |
582 | .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX }, | |
583 | .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX }, | |
584 | .p = { .min = IRONLAKE_LVDS_D_P_MIN, .max = IRONLAKE_LVDS_D_P_MAX }, | |
585 | .p1 = { .min = IRONLAKE_LVDS_D_P1_MIN, .max = IRONLAKE_LVDS_D_P1_MAX }, | |
586 | .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT, | |
587 | .p2_slow = IRONLAKE_LVDS_D_P2_SLOW, | |
588 | .p2_fast = IRONLAKE_LVDS_D_P2_FAST }, | |
589 | .find_pll = intel_g4x_find_best_PLL, | |
590 | }; | |
591 | ||
592 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { | |
593 | .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX }, | |
594 | .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX }, | |
595 | .n = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX }, | |
596 | .m = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX }, | |
597 | .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX }, | |
598 | .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX }, | |
599 | .p = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX }, | |
600 | .p1 = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX }, | |
601 | .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT, | |
602 | .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW, | |
603 | .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST }, | |
604 | .find_pll = intel_g4x_find_best_PLL, | |
605 | }; | |
606 | ||
607 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
608 | .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX }, | |
609 | .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX }, | |
610 | .n = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX }, | |
611 | .m = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX }, | |
612 | .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX }, | |
613 | .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX }, | |
614 | .p = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX }, | |
615 | .p1 = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX }, | |
616 | .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT, | |
617 | .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW, | |
618 | .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST }, | |
4547668a ZY |
619 | .find_pll = intel_g4x_find_best_PLL, |
620 | }; | |
621 | ||
622 | static const intel_limit_t intel_limits_ironlake_display_port = { | |
623 | .dot = { .min = IRONLAKE_DOT_MIN, | |
624 | .max = IRONLAKE_DOT_MAX }, | |
625 | .vco = { .min = IRONLAKE_VCO_MIN, | |
626 | .max = IRONLAKE_VCO_MAX}, | |
b91ad0ec ZW |
627 | .n = { .min = IRONLAKE_DP_N_MIN, |
628 | .max = IRONLAKE_DP_N_MAX }, | |
629 | .m = { .min = IRONLAKE_DP_M_MIN, | |
630 | .max = IRONLAKE_DP_M_MAX }, | |
4547668a ZY |
631 | .m1 = { .min = IRONLAKE_M1_MIN, |
632 | .max = IRONLAKE_M1_MAX }, | |
633 | .m2 = { .min = IRONLAKE_M2_MIN, | |
634 | .max = IRONLAKE_M2_MAX }, | |
b91ad0ec ZW |
635 | .p = { .min = IRONLAKE_DP_P_MIN, |
636 | .max = IRONLAKE_DP_P_MAX }, | |
637 | .p1 = { .min = IRONLAKE_DP_P1_MIN, | |
638 | .max = IRONLAKE_DP_P1_MAX}, | |
639 | .p2 = { .dot_limit = IRONLAKE_DP_P2_LIMIT, | |
640 | .p2_slow = IRONLAKE_DP_P2_SLOW, | |
641 | .p2_fast = IRONLAKE_DP_P2_FAST }, | |
4547668a | 642 | .find_pll = intel_find_pll_ironlake_dp, |
79e53945 JB |
643 | }; |
644 | ||
f2b115e6 | 645 | static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc) |
2c07245f | 646 | { |
b91ad0ec ZW |
647 | struct drm_device *dev = crtc->dev; |
648 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2c07245f | 649 | const intel_limit_t *limit; |
b91ad0ec ZW |
650 | int refclk = 120; |
651 | ||
652 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
653 | if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100) | |
654 | refclk = 100; | |
655 | ||
656 | if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == | |
657 | LVDS_CLKB_POWER_UP) { | |
658 | /* LVDS dual channel */ | |
659 | if (refclk == 100) | |
660 | limit = &intel_limits_ironlake_dual_lvds_100m; | |
661 | else | |
662 | limit = &intel_limits_ironlake_dual_lvds; | |
663 | } else { | |
664 | if (refclk == 100) | |
665 | limit = &intel_limits_ironlake_single_lvds_100m; | |
666 | else | |
667 | limit = &intel_limits_ironlake_single_lvds; | |
668 | } | |
669 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || | |
4547668a ZY |
670 | HAS_eDP) |
671 | limit = &intel_limits_ironlake_display_port; | |
2c07245f | 672 | else |
b91ad0ec | 673 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
674 | |
675 | return limit; | |
676 | } | |
677 | ||
044c7c41 ML |
678 | static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) |
679 | { | |
680 | struct drm_device *dev = crtc->dev; | |
681 | struct drm_i915_private *dev_priv = dev->dev_private; | |
682 | const intel_limit_t *limit; | |
683 | ||
684 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
685 | if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) == | |
686 | LVDS_CLKB_POWER_UP) | |
687 | /* LVDS with dual channel */ | |
e4b36699 | 688 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 ML |
689 | else |
690 | /* LVDS with dual channel */ | |
e4b36699 | 691 | limit = &intel_limits_g4x_single_channel_lvds; |
044c7c41 ML |
692 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || |
693 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 694 | limit = &intel_limits_g4x_hdmi; |
044c7c41 | 695 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 696 | limit = &intel_limits_g4x_sdvo; |
a4fc5ed6 | 697 | } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
e4b36699 | 698 | limit = &intel_limits_g4x_display_port; |
044c7c41 | 699 | } else /* The option is for other outputs */ |
e4b36699 | 700 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
701 | |
702 | return limit; | |
703 | } | |
704 | ||
79e53945 JB |
705 | static const intel_limit_t *intel_limit(struct drm_crtc *crtc) |
706 | { | |
707 | struct drm_device *dev = crtc->dev; | |
708 | const intel_limit_t *limit; | |
709 | ||
bad720ff | 710 | if (HAS_PCH_SPLIT(dev)) |
f2b115e6 | 711 | limit = intel_ironlake_limit(crtc); |
2c07245f | 712 | else if (IS_G4X(dev)) { |
044c7c41 | 713 | limit = intel_g4x_limit(crtc); |
f2b115e6 | 714 | } else if (IS_PINEVIEW(dev)) { |
2177832f | 715 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 716 | limit = &intel_limits_pineview_lvds; |
2177832f | 717 | else |
f2b115e6 | 718 | limit = &intel_limits_pineview_sdvo; |
a6c45cf0 CW |
719 | } else if (!IS_GEN2(dev)) { |
720 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
721 | limit = &intel_limits_i9xx_lvds; | |
722 | else | |
723 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 JB |
724 | } else { |
725 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
e4b36699 | 726 | limit = &intel_limits_i8xx_lvds; |
79e53945 | 727 | else |
e4b36699 | 728 | limit = &intel_limits_i8xx_dvo; |
79e53945 JB |
729 | } |
730 | return limit; | |
731 | } | |
732 | ||
f2b115e6 AJ |
733 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
734 | static void pineview_clock(int refclk, intel_clock_t *clock) | |
79e53945 | 735 | { |
2177832f SL |
736 | clock->m = clock->m2 + 2; |
737 | clock->p = clock->p1 * clock->p2; | |
738 | clock->vco = refclk * clock->m / clock->n; | |
739 | clock->dot = clock->vco / clock->p; | |
740 | } | |
741 | ||
742 | static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock) | |
743 | { | |
f2b115e6 AJ |
744 | if (IS_PINEVIEW(dev)) { |
745 | pineview_clock(refclk, clock); | |
2177832f SL |
746 | return; |
747 | } | |
79e53945 JB |
748 | clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); |
749 | clock->p = clock->p1 * clock->p2; | |
750 | clock->vco = refclk * clock->m / (clock->n + 2); | |
751 | clock->dot = clock->vco / clock->p; | |
752 | } | |
753 | ||
79e53945 JB |
754 | /** |
755 | * Returns whether any output on the specified pipe is of the specified type | |
756 | */ | |
4ef69c7a | 757 | bool intel_pipe_has_type(struct drm_crtc *crtc, int type) |
79e53945 | 758 | { |
4ef69c7a CW |
759 | struct drm_device *dev = crtc->dev; |
760 | struct drm_mode_config *mode_config = &dev->mode_config; | |
761 | struct intel_encoder *encoder; | |
762 | ||
763 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) | |
764 | if (encoder->base.crtc == crtc && encoder->type == type) | |
765 | return true; | |
766 | ||
767 | return false; | |
79e53945 JB |
768 | } |
769 | ||
7c04d1d9 | 770 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
771 | /** |
772 | * Returns whether the given set of divisors are valid for a given refclk with | |
773 | * the given connectors. | |
774 | */ | |
775 | ||
776 | static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock) | |
777 | { | |
778 | const intel_limit_t *limit = intel_limit (crtc); | |
2177832f | 779 | struct drm_device *dev = crtc->dev; |
79e53945 JB |
780 | |
781 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) | |
782 | INTELPllInvalid ("p1 out of range\n"); | |
783 | if (clock->p < limit->p.min || limit->p.max < clock->p) | |
784 | INTELPllInvalid ("p out of range\n"); | |
785 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) | |
786 | INTELPllInvalid ("m2 out of range\n"); | |
787 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) | |
788 | INTELPllInvalid ("m1 out of range\n"); | |
f2b115e6 | 789 | if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev)) |
79e53945 JB |
790 | INTELPllInvalid ("m1 <= m2\n"); |
791 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
792 | INTELPllInvalid ("m out of range\n"); | |
793 | if (clock->n < limit->n.min || limit->n.max < clock->n) | |
794 | INTELPllInvalid ("n out of range\n"); | |
795 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) | |
796 | INTELPllInvalid ("vco out of range\n"); | |
797 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, | |
798 | * connector, etc., rather than just a single range. | |
799 | */ | |
800 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
801 | INTELPllInvalid ("dot out of range\n"); | |
802 | ||
803 | return true; | |
804 | } | |
805 | ||
d4906093 ML |
806 | static bool |
807 | intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
808 | int target, int refclk, intel_clock_t *best_clock) | |
809 | ||
79e53945 JB |
810 | { |
811 | struct drm_device *dev = crtc->dev; | |
812 | struct drm_i915_private *dev_priv = dev->dev_private; | |
813 | intel_clock_t clock; | |
79e53945 JB |
814 | int err = target; |
815 | ||
bc5e5718 | 816 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
832cc28d | 817 | (I915_READ(LVDS)) != 0) { |
79e53945 JB |
818 | /* |
819 | * For LVDS, if the panel is on, just rely on its current | |
820 | * settings for dual-channel. We haven't figured out how to | |
821 | * reliably set up different single/dual channel state, if we | |
822 | * even can. | |
823 | */ | |
824 | if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) == | |
825 | LVDS_CLKB_POWER_UP) | |
826 | clock.p2 = limit->p2.p2_fast; | |
827 | else | |
828 | clock.p2 = limit->p2.p2_slow; | |
829 | } else { | |
830 | if (target < limit->p2.dot_limit) | |
831 | clock.p2 = limit->p2.p2_slow; | |
832 | else | |
833 | clock.p2 = limit->p2.p2_fast; | |
834 | } | |
835 | ||
836 | memset (best_clock, 0, sizeof (*best_clock)); | |
837 | ||
42158660 ZY |
838 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
839 | clock.m1++) { | |
840 | for (clock.m2 = limit->m2.min; | |
841 | clock.m2 <= limit->m2.max; clock.m2++) { | |
f2b115e6 AJ |
842 | /* m1 is always 0 in Pineview */ |
843 | if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev)) | |
42158660 ZY |
844 | break; |
845 | for (clock.n = limit->n.min; | |
846 | clock.n <= limit->n.max; clock.n++) { | |
847 | for (clock.p1 = limit->p1.min; | |
848 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
849 | int this_err; |
850 | ||
2177832f | 851 | intel_clock(dev, refclk, &clock); |
79e53945 JB |
852 | |
853 | if (!intel_PLL_is_valid(crtc, &clock)) | |
854 | continue; | |
855 | ||
856 | this_err = abs(clock.dot - target); | |
857 | if (this_err < err) { | |
858 | *best_clock = clock; | |
859 | err = this_err; | |
860 | } | |
861 | } | |
862 | } | |
863 | } | |
864 | } | |
865 | ||
866 | return (err != target); | |
867 | } | |
868 | ||
d4906093 ML |
869 | static bool |
870 | intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
871 | int target, int refclk, intel_clock_t *best_clock) | |
872 | { | |
873 | struct drm_device *dev = crtc->dev; | |
874 | struct drm_i915_private *dev_priv = dev->dev_private; | |
875 | intel_clock_t clock; | |
876 | int max_n; | |
877 | bool found; | |
6ba770dc AJ |
878 | /* approximately equals target * 0.00585 */ |
879 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
880 | found = false; |
881 | ||
882 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
4547668a ZY |
883 | int lvds_reg; |
884 | ||
c619eed4 | 885 | if (HAS_PCH_SPLIT(dev)) |
4547668a ZY |
886 | lvds_reg = PCH_LVDS; |
887 | else | |
888 | lvds_reg = LVDS; | |
889 | if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) == | |
d4906093 ML |
890 | LVDS_CLKB_POWER_UP) |
891 | clock.p2 = limit->p2.p2_fast; | |
892 | else | |
893 | clock.p2 = limit->p2.p2_slow; | |
894 | } else { | |
895 | if (target < limit->p2.dot_limit) | |
896 | clock.p2 = limit->p2.p2_slow; | |
897 | else | |
898 | clock.p2 = limit->p2.p2_fast; | |
899 | } | |
900 | ||
901 | memset(best_clock, 0, sizeof(*best_clock)); | |
902 | max_n = limit->n.max; | |
f77f13e2 | 903 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 904 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 905 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
906 | for (clock.m1 = limit->m1.max; |
907 | clock.m1 >= limit->m1.min; clock.m1--) { | |
908 | for (clock.m2 = limit->m2.max; | |
909 | clock.m2 >= limit->m2.min; clock.m2--) { | |
910 | for (clock.p1 = limit->p1.max; | |
911 | clock.p1 >= limit->p1.min; clock.p1--) { | |
912 | int this_err; | |
913 | ||
2177832f | 914 | intel_clock(dev, refclk, &clock); |
d4906093 ML |
915 | if (!intel_PLL_is_valid(crtc, &clock)) |
916 | continue; | |
917 | this_err = abs(clock.dot - target) ; | |
918 | if (this_err < err_most) { | |
919 | *best_clock = clock; | |
920 | err_most = this_err; | |
921 | max_n = clock.n; | |
922 | found = true; | |
923 | } | |
924 | } | |
925 | } | |
926 | } | |
927 | } | |
2c07245f ZW |
928 | return found; |
929 | } | |
930 | ||
5eb08b69 | 931 | static bool |
f2b115e6 AJ |
932 | intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc, |
933 | int target, int refclk, intel_clock_t *best_clock) | |
5eb08b69 ZW |
934 | { |
935 | struct drm_device *dev = crtc->dev; | |
936 | intel_clock_t clock; | |
4547668a | 937 | |
5eb08b69 ZW |
938 | if (target < 200000) { |
939 | clock.n = 1; | |
940 | clock.p1 = 2; | |
941 | clock.p2 = 10; | |
942 | clock.m1 = 12; | |
943 | clock.m2 = 9; | |
944 | } else { | |
945 | clock.n = 2; | |
946 | clock.p1 = 1; | |
947 | clock.p2 = 10; | |
948 | clock.m1 = 14; | |
949 | clock.m2 = 8; | |
950 | } | |
951 | intel_clock(dev, refclk, &clock); | |
952 | memcpy(best_clock, &clock, sizeof(intel_clock_t)); | |
953 | return true; | |
954 | } | |
955 | ||
a4fc5ed6 KP |
956 | /* DisplayPort has only two frequencies, 162MHz and 270MHz */ |
957 | static bool | |
958 | intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc, | |
959 | int target, int refclk, intel_clock_t *best_clock) | |
960 | { | |
5eddb70b CW |
961 | intel_clock_t clock; |
962 | if (target < 200000) { | |
963 | clock.p1 = 2; | |
964 | clock.p2 = 10; | |
965 | clock.n = 2; | |
966 | clock.m1 = 23; | |
967 | clock.m2 = 8; | |
968 | } else { | |
969 | clock.p1 = 1; | |
970 | clock.p2 = 10; | |
971 | clock.n = 1; | |
972 | clock.m1 = 14; | |
973 | clock.m2 = 2; | |
974 | } | |
975 | clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2); | |
976 | clock.p = (clock.p1 * clock.p2); | |
977 | clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p; | |
978 | clock.vco = 0; | |
979 | memcpy(best_clock, &clock, sizeof(intel_clock_t)); | |
980 | return true; | |
a4fc5ed6 KP |
981 | } |
982 | ||
9d0498a2 JB |
983 | /** |
984 | * intel_wait_for_vblank - wait for vblank on a given pipe | |
985 | * @dev: drm device | |
986 | * @pipe: pipe to wait for | |
987 | * | |
988 | * Wait for vblank to occur on a given pipe. Needed for various bits of | |
989 | * mode setting code. | |
990 | */ | |
991 | void intel_wait_for_vblank(struct drm_device *dev, int pipe) | |
79e53945 | 992 | { |
9d0498a2 JB |
993 | struct drm_i915_private *dev_priv = dev->dev_private; |
994 | int pipestat_reg = (pipe == 0 ? PIPEASTAT : PIPEBSTAT); | |
995 | ||
300387c0 CW |
996 | /* Clear existing vblank status. Note this will clear any other |
997 | * sticky status fields as well. | |
998 | * | |
999 | * This races with i915_driver_irq_handler() with the result | |
1000 | * that either function could miss a vblank event. Here it is not | |
1001 | * fatal, as we will either wait upon the next vblank interrupt or | |
1002 | * timeout. Generally speaking intel_wait_for_vblank() is only | |
1003 | * called during modeset at which time the GPU should be idle and | |
1004 | * should *not* be performing page flips and thus not waiting on | |
1005 | * vblanks... | |
1006 | * Currently, the result of us stealing a vblank from the irq | |
1007 | * handler is that a single frame will be skipped during swapbuffers. | |
1008 | */ | |
1009 | I915_WRITE(pipestat_reg, | |
1010 | I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS); | |
1011 | ||
9d0498a2 | 1012 | /* Wait for vblank interrupt bit to set */ |
481b6af3 CW |
1013 | if (wait_for(I915_READ(pipestat_reg) & |
1014 | PIPE_VBLANK_INTERRUPT_STATUS, | |
1015 | 50)) | |
9d0498a2 JB |
1016 | DRM_DEBUG_KMS("vblank wait timed out\n"); |
1017 | } | |
1018 | ||
ab7ad7f6 KP |
1019 | /* |
1020 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
9d0498a2 JB |
1021 | * @dev: drm device |
1022 | * @pipe: pipe to wait for | |
1023 | * | |
1024 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
1025 | * spinning on the vblank interrupt status bit, since we won't actually | |
1026 | * see an interrupt when the pipe is disabled. | |
1027 | * | |
ab7ad7f6 KP |
1028 | * On Gen4 and above: |
1029 | * wait for the pipe register state bit to turn off | |
1030 | * | |
1031 | * Otherwise: | |
1032 | * wait for the display line value to settle (it usually | |
1033 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 1034 | * |
9d0498a2 | 1035 | */ |
58e10eb9 | 1036 | void intel_wait_for_pipe_off(struct drm_device *dev, int pipe) |
9d0498a2 JB |
1037 | { |
1038 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ab7ad7f6 KP |
1039 | |
1040 | if (INTEL_INFO(dev)->gen >= 4) { | |
58e10eb9 | 1041 | int reg = PIPECONF(pipe); |
ab7ad7f6 KP |
1042 | |
1043 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
1044 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
1045 | 100)) | |
ab7ad7f6 KP |
1046 | DRM_DEBUG_KMS("pipe_off wait timed out\n"); |
1047 | } else { | |
1048 | u32 last_line; | |
58e10eb9 | 1049 | int reg = PIPEDSL(pipe); |
ab7ad7f6 KP |
1050 | unsigned long timeout = jiffies + msecs_to_jiffies(100); |
1051 | ||
1052 | /* Wait for the display line to settle */ | |
1053 | do { | |
58e10eb9 | 1054 | last_line = I915_READ(reg) & DSL_LINEMASK; |
ab7ad7f6 | 1055 | mdelay(5); |
58e10eb9 | 1056 | } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) && |
ab7ad7f6 KP |
1057 | time_after(timeout, jiffies)); |
1058 | if (time_after(jiffies, timeout)) | |
1059 | DRM_DEBUG_KMS("pipe_off wait timed out\n"); | |
1060 | } | |
79e53945 JB |
1061 | } |
1062 | ||
80824003 JB |
1063 | static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
1064 | { | |
1065 | struct drm_device *dev = crtc->dev; | |
1066 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1067 | struct drm_framebuffer *fb = crtc->fb; | |
1068 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 1069 | struct drm_i915_gem_object *obj = intel_fb->obj; |
80824003 JB |
1070 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
1071 | int plane, i; | |
1072 | u32 fbc_ctl, fbc_ctl2; | |
1073 | ||
bed4a673 | 1074 | if (fb->pitch == dev_priv->cfb_pitch && |
05394f39 | 1075 | obj->fence_reg == dev_priv->cfb_fence && |
bed4a673 CW |
1076 | intel_crtc->plane == dev_priv->cfb_plane && |
1077 | I915_READ(FBC_CONTROL) & FBC_CTL_EN) | |
1078 | return; | |
1079 | ||
1080 | i8xx_disable_fbc(dev); | |
1081 | ||
80824003 JB |
1082 | dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE; |
1083 | ||
1084 | if (fb->pitch < dev_priv->cfb_pitch) | |
1085 | dev_priv->cfb_pitch = fb->pitch; | |
1086 | ||
1087 | /* FBC_CTL wants 64B units */ | |
1088 | dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1; | |
05394f39 | 1089 | dev_priv->cfb_fence = obj->fence_reg; |
80824003 JB |
1090 | dev_priv->cfb_plane = intel_crtc->plane; |
1091 | plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB; | |
1092 | ||
1093 | /* Clear old tags */ | |
1094 | for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) | |
1095 | I915_WRITE(FBC_TAG + (i * 4), 0); | |
1096 | ||
1097 | /* Set it up... */ | |
1098 | fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane; | |
05394f39 | 1099 | if (obj->tiling_mode != I915_TILING_NONE) |
80824003 JB |
1100 | fbc_ctl2 |= FBC_CTL_CPU_FENCE; |
1101 | I915_WRITE(FBC_CONTROL2, fbc_ctl2); | |
1102 | I915_WRITE(FBC_FENCE_OFF, crtc->y); | |
1103 | ||
1104 | /* enable it... */ | |
1105 | fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC; | |
ee25df2b | 1106 | if (IS_I945GM(dev)) |
49677901 | 1107 | fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ |
80824003 JB |
1108 | fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; |
1109 | fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT; | |
05394f39 | 1110 | if (obj->tiling_mode != I915_TILING_NONE) |
80824003 JB |
1111 | fbc_ctl |= dev_priv->cfb_fence; |
1112 | I915_WRITE(FBC_CONTROL, fbc_ctl); | |
1113 | ||
28c97730 | 1114 | DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ", |
5eddb70b | 1115 | dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane); |
80824003 JB |
1116 | } |
1117 | ||
1118 | void i8xx_disable_fbc(struct drm_device *dev) | |
1119 | { | |
1120 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1121 | u32 fbc_ctl; | |
1122 | ||
1123 | /* Disable compression */ | |
1124 | fbc_ctl = I915_READ(FBC_CONTROL); | |
a5cad620 CW |
1125 | if ((fbc_ctl & FBC_CTL_EN) == 0) |
1126 | return; | |
1127 | ||
80824003 JB |
1128 | fbc_ctl &= ~FBC_CTL_EN; |
1129 | I915_WRITE(FBC_CONTROL, fbc_ctl); | |
1130 | ||
1131 | /* Wait for compressing bit to clear */ | |
481b6af3 | 1132 | if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) { |
913d8d11 CW |
1133 | DRM_DEBUG_KMS("FBC idle timed out\n"); |
1134 | return; | |
9517a92f | 1135 | } |
80824003 | 1136 | |
28c97730 | 1137 | DRM_DEBUG_KMS("disabled FBC\n"); |
80824003 JB |
1138 | } |
1139 | ||
ee5382ae | 1140 | static bool i8xx_fbc_enabled(struct drm_device *dev) |
80824003 | 1141 | { |
80824003 JB |
1142 | struct drm_i915_private *dev_priv = dev->dev_private; |
1143 | ||
1144 | return I915_READ(FBC_CONTROL) & FBC_CTL_EN; | |
1145 | } | |
1146 | ||
74dff282 JB |
1147 | static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
1148 | { | |
1149 | struct drm_device *dev = crtc->dev; | |
1150 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1151 | struct drm_framebuffer *fb = crtc->fb; | |
1152 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 1153 | struct drm_i915_gem_object *obj = intel_fb->obj; |
74dff282 | 1154 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5eddb70b | 1155 | int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB; |
74dff282 JB |
1156 | unsigned long stall_watermark = 200; |
1157 | u32 dpfc_ctl; | |
1158 | ||
bed4a673 CW |
1159 | dpfc_ctl = I915_READ(DPFC_CONTROL); |
1160 | if (dpfc_ctl & DPFC_CTL_EN) { | |
1161 | if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 && | |
05394f39 | 1162 | dev_priv->cfb_fence == obj->fence_reg && |
bed4a673 CW |
1163 | dev_priv->cfb_plane == intel_crtc->plane && |
1164 | dev_priv->cfb_y == crtc->y) | |
1165 | return; | |
1166 | ||
1167 | I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN); | |
1168 | POSTING_READ(DPFC_CONTROL); | |
1169 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
1170 | } | |
1171 | ||
74dff282 | 1172 | dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1; |
05394f39 | 1173 | dev_priv->cfb_fence = obj->fence_reg; |
74dff282 | 1174 | dev_priv->cfb_plane = intel_crtc->plane; |
bed4a673 | 1175 | dev_priv->cfb_y = crtc->y; |
74dff282 JB |
1176 | |
1177 | dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X; | |
05394f39 | 1178 | if (obj->tiling_mode != I915_TILING_NONE) { |
74dff282 JB |
1179 | dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence; |
1180 | I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY); | |
1181 | } else { | |
1182 | I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY); | |
1183 | } | |
1184 | ||
74dff282 JB |
1185 | I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN | |
1186 | (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) | | |
1187 | (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT)); | |
1188 | I915_WRITE(DPFC_FENCE_YOFF, crtc->y); | |
1189 | ||
1190 | /* enable it... */ | |
1191 | I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN); | |
1192 | ||
28c97730 | 1193 | DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane); |
74dff282 JB |
1194 | } |
1195 | ||
1196 | void g4x_disable_fbc(struct drm_device *dev) | |
1197 | { | |
1198 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1199 | u32 dpfc_ctl; | |
1200 | ||
1201 | /* Disable compression */ | |
1202 | dpfc_ctl = I915_READ(DPFC_CONTROL); | |
bed4a673 CW |
1203 | if (dpfc_ctl & DPFC_CTL_EN) { |
1204 | dpfc_ctl &= ~DPFC_CTL_EN; | |
1205 | I915_WRITE(DPFC_CONTROL, dpfc_ctl); | |
74dff282 | 1206 | |
bed4a673 CW |
1207 | DRM_DEBUG_KMS("disabled FBC\n"); |
1208 | } | |
74dff282 JB |
1209 | } |
1210 | ||
ee5382ae | 1211 | static bool g4x_fbc_enabled(struct drm_device *dev) |
74dff282 | 1212 | { |
74dff282 JB |
1213 | struct drm_i915_private *dev_priv = dev->dev_private; |
1214 | ||
1215 | return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN; | |
1216 | } | |
1217 | ||
b52eb4dc ZY |
1218 | static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
1219 | { | |
1220 | struct drm_device *dev = crtc->dev; | |
1221 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1222 | struct drm_framebuffer *fb = crtc->fb; | |
1223 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 1224 | struct drm_i915_gem_object *obj = intel_fb->obj; |
b52eb4dc | 1225 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5eddb70b | 1226 | int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB; |
b52eb4dc ZY |
1227 | unsigned long stall_watermark = 200; |
1228 | u32 dpfc_ctl; | |
1229 | ||
bed4a673 CW |
1230 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); |
1231 | if (dpfc_ctl & DPFC_CTL_EN) { | |
1232 | if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 && | |
05394f39 | 1233 | dev_priv->cfb_fence == obj->fence_reg && |
bed4a673 | 1234 | dev_priv->cfb_plane == intel_crtc->plane && |
05394f39 | 1235 | dev_priv->cfb_offset == obj->gtt_offset && |
bed4a673 CW |
1236 | dev_priv->cfb_y == crtc->y) |
1237 | return; | |
1238 | ||
1239 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN); | |
1240 | POSTING_READ(ILK_DPFC_CONTROL); | |
1241 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
1242 | } | |
1243 | ||
b52eb4dc | 1244 | dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1; |
05394f39 | 1245 | dev_priv->cfb_fence = obj->fence_reg; |
b52eb4dc | 1246 | dev_priv->cfb_plane = intel_crtc->plane; |
05394f39 | 1247 | dev_priv->cfb_offset = obj->gtt_offset; |
bed4a673 | 1248 | dev_priv->cfb_y = crtc->y; |
b52eb4dc | 1249 | |
b52eb4dc ZY |
1250 | dpfc_ctl &= DPFC_RESERVED; |
1251 | dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X); | |
05394f39 | 1252 | if (obj->tiling_mode != I915_TILING_NONE) { |
b52eb4dc ZY |
1253 | dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence); |
1254 | I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY); | |
1255 | } else { | |
1256 | I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY); | |
1257 | } | |
1258 | ||
b52eb4dc ZY |
1259 | I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN | |
1260 | (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) | | |
1261 | (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT)); | |
1262 | I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y); | |
05394f39 | 1263 | I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID); |
b52eb4dc | 1264 | /* enable it... */ |
bed4a673 | 1265 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); |
b52eb4dc ZY |
1266 | |
1267 | DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane); | |
1268 | } | |
1269 | ||
1270 | void ironlake_disable_fbc(struct drm_device *dev) | |
1271 | { | |
1272 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1273 | u32 dpfc_ctl; | |
1274 | ||
1275 | /* Disable compression */ | |
1276 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); | |
bed4a673 CW |
1277 | if (dpfc_ctl & DPFC_CTL_EN) { |
1278 | dpfc_ctl &= ~DPFC_CTL_EN; | |
1279 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); | |
b52eb4dc | 1280 | |
bed4a673 CW |
1281 | DRM_DEBUG_KMS("disabled FBC\n"); |
1282 | } | |
b52eb4dc ZY |
1283 | } |
1284 | ||
1285 | static bool ironlake_fbc_enabled(struct drm_device *dev) | |
1286 | { | |
1287 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1288 | ||
1289 | return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN; | |
1290 | } | |
1291 | ||
ee5382ae AJ |
1292 | bool intel_fbc_enabled(struct drm_device *dev) |
1293 | { | |
1294 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1295 | ||
1296 | if (!dev_priv->display.fbc_enabled) | |
1297 | return false; | |
1298 | ||
1299 | return dev_priv->display.fbc_enabled(dev); | |
1300 | } | |
1301 | ||
1302 | void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval) | |
1303 | { | |
1304 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
1305 | ||
1306 | if (!dev_priv->display.enable_fbc) | |
1307 | return; | |
1308 | ||
1309 | dev_priv->display.enable_fbc(crtc, interval); | |
1310 | } | |
1311 | ||
1312 | void intel_disable_fbc(struct drm_device *dev) | |
1313 | { | |
1314 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1315 | ||
1316 | if (!dev_priv->display.disable_fbc) | |
1317 | return; | |
1318 | ||
1319 | dev_priv->display.disable_fbc(dev); | |
1320 | } | |
1321 | ||
80824003 JB |
1322 | /** |
1323 | * intel_update_fbc - enable/disable FBC as needed | |
bed4a673 | 1324 | * @dev: the drm_device |
80824003 JB |
1325 | * |
1326 | * Set up the framebuffer compression hardware at mode set time. We | |
1327 | * enable it if possible: | |
1328 | * - plane A only (on pre-965) | |
1329 | * - no pixel mulitply/line duplication | |
1330 | * - no alpha buffer discard | |
1331 | * - no dual wide | |
1332 | * - framebuffer <= 2048 in width, 1536 in height | |
1333 | * | |
1334 | * We can't assume that any compression will take place (worst case), | |
1335 | * so the compressed buffer has to be the same size as the uncompressed | |
1336 | * one. It also must reside (along with the line length buffer) in | |
1337 | * stolen memory. | |
1338 | * | |
1339 | * We need to enable/disable FBC on a global basis. | |
1340 | */ | |
bed4a673 | 1341 | static void intel_update_fbc(struct drm_device *dev) |
80824003 | 1342 | { |
80824003 | 1343 | struct drm_i915_private *dev_priv = dev->dev_private; |
bed4a673 CW |
1344 | struct drm_crtc *crtc = NULL, *tmp_crtc; |
1345 | struct intel_crtc *intel_crtc; | |
1346 | struct drm_framebuffer *fb; | |
80824003 | 1347 | struct intel_framebuffer *intel_fb; |
05394f39 | 1348 | struct drm_i915_gem_object *obj; |
9c928d16 JB |
1349 | |
1350 | DRM_DEBUG_KMS("\n"); | |
80824003 JB |
1351 | |
1352 | if (!i915_powersave) | |
1353 | return; | |
1354 | ||
ee5382ae | 1355 | if (!I915_HAS_FBC(dev)) |
e70236a8 JB |
1356 | return; |
1357 | ||
80824003 JB |
1358 | /* |
1359 | * If FBC is already on, we just have to verify that we can | |
1360 | * keep it that way... | |
1361 | * Need to disable if: | |
9c928d16 | 1362 | * - more than one pipe is active |
80824003 JB |
1363 | * - changing FBC params (stride, fence, mode) |
1364 | * - new fb is too large to fit in compressed buffer | |
1365 | * - going to an unsupported config (interlace, pixel multiply, etc.) | |
1366 | */ | |
9c928d16 | 1367 | list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) { |
bed4a673 CW |
1368 | if (tmp_crtc->enabled) { |
1369 | if (crtc) { | |
1370 | DRM_DEBUG_KMS("more than one pipe active, disabling compression\n"); | |
1371 | dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES; | |
1372 | goto out_disable; | |
1373 | } | |
1374 | crtc = tmp_crtc; | |
1375 | } | |
9c928d16 | 1376 | } |
bed4a673 CW |
1377 | |
1378 | if (!crtc || crtc->fb == NULL) { | |
1379 | DRM_DEBUG_KMS("no output, disabling\n"); | |
1380 | dev_priv->no_fbc_reason = FBC_NO_OUTPUT; | |
9c928d16 JB |
1381 | goto out_disable; |
1382 | } | |
bed4a673 CW |
1383 | |
1384 | intel_crtc = to_intel_crtc(crtc); | |
1385 | fb = crtc->fb; | |
1386 | intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 1387 | obj = intel_fb->obj; |
bed4a673 | 1388 | |
05394f39 | 1389 | if (intel_fb->obj->base.size > dev_priv->cfb_size) { |
28c97730 | 1390 | DRM_DEBUG_KMS("framebuffer too large, disabling " |
5eddb70b | 1391 | "compression\n"); |
b5e50c3f | 1392 | dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL; |
80824003 JB |
1393 | goto out_disable; |
1394 | } | |
bed4a673 CW |
1395 | if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) || |
1396 | (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) { | |
28c97730 | 1397 | DRM_DEBUG_KMS("mode incompatible with compression, " |
5eddb70b | 1398 | "disabling\n"); |
b5e50c3f | 1399 | dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE; |
80824003 JB |
1400 | goto out_disable; |
1401 | } | |
bed4a673 CW |
1402 | if ((crtc->mode.hdisplay > 2048) || |
1403 | (crtc->mode.vdisplay > 1536)) { | |
28c97730 | 1404 | DRM_DEBUG_KMS("mode too large for compression, disabling\n"); |
b5e50c3f | 1405 | dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE; |
80824003 JB |
1406 | goto out_disable; |
1407 | } | |
bed4a673 | 1408 | if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) { |
28c97730 | 1409 | DRM_DEBUG_KMS("plane not 0, disabling compression\n"); |
b5e50c3f | 1410 | dev_priv->no_fbc_reason = FBC_BAD_PLANE; |
80824003 JB |
1411 | goto out_disable; |
1412 | } | |
05394f39 | 1413 | if (obj->tiling_mode != I915_TILING_X) { |
28c97730 | 1414 | DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n"); |
b5e50c3f | 1415 | dev_priv->no_fbc_reason = FBC_NOT_TILED; |
80824003 JB |
1416 | goto out_disable; |
1417 | } | |
1418 | ||
c924b934 JW |
1419 | /* If the kernel debugger is active, always disable compression */ |
1420 | if (in_dbg_master()) | |
1421 | goto out_disable; | |
1422 | ||
bed4a673 | 1423 | intel_enable_fbc(crtc, 500); |
80824003 JB |
1424 | return; |
1425 | ||
1426 | out_disable: | |
80824003 | 1427 | /* Multiple disables should be harmless */ |
a939406f CW |
1428 | if (intel_fbc_enabled(dev)) { |
1429 | DRM_DEBUG_KMS("unsupported config, disabling FBC\n"); | |
ee5382ae | 1430 | intel_disable_fbc(dev); |
a939406f | 1431 | } |
80824003 JB |
1432 | } |
1433 | ||
127bd2ac | 1434 | int |
48b956c5 | 1435 | intel_pin_and_fence_fb_obj(struct drm_device *dev, |
05394f39 | 1436 | struct drm_i915_gem_object *obj, |
919926ae | 1437 | struct intel_ring_buffer *pipelined) |
6b95a207 | 1438 | { |
6b95a207 KH |
1439 | u32 alignment; |
1440 | int ret; | |
1441 | ||
05394f39 | 1442 | switch (obj->tiling_mode) { |
6b95a207 | 1443 | case I915_TILING_NONE: |
534843da CW |
1444 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
1445 | alignment = 128 * 1024; | |
a6c45cf0 | 1446 | else if (INTEL_INFO(dev)->gen >= 4) |
534843da CW |
1447 | alignment = 4 * 1024; |
1448 | else | |
1449 | alignment = 64 * 1024; | |
6b95a207 KH |
1450 | break; |
1451 | case I915_TILING_X: | |
1452 | /* pin() will align the object as required by fence */ | |
1453 | alignment = 0; | |
1454 | break; | |
1455 | case I915_TILING_Y: | |
1456 | /* FIXME: Is this true? */ | |
1457 | DRM_ERROR("Y tiled not allowed for scan out buffers\n"); | |
1458 | return -EINVAL; | |
1459 | default: | |
1460 | BUG(); | |
1461 | } | |
1462 | ||
75e9e915 | 1463 | ret = i915_gem_object_pin(obj, alignment, true); |
48b956c5 | 1464 | if (ret) |
6b95a207 KH |
1465 | return ret; |
1466 | ||
48b956c5 CW |
1467 | ret = i915_gem_object_set_to_display_plane(obj, pipelined); |
1468 | if (ret) | |
1469 | goto err_unpin; | |
7213342d | 1470 | |
6b95a207 KH |
1471 | /* Install a fence for tiled scan-out. Pre-i965 always needs a |
1472 | * fence, whereas 965+ only requires a fence if using | |
1473 | * framebuffer compression. For simplicity, we always install | |
1474 | * a fence as the cost is not that onerous. | |
1475 | */ | |
05394f39 | 1476 | if (obj->tiling_mode != I915_TILING_NONE) { |
d9e86c0e | 1477 | ret = i915_gem_object_get_fence(obj, pipelined, false); |
48b956c5 CW |
1478 | if (ret) |
1479 | goto err_unpin; | |
6b95a207 KH |
1480 | } |
1481 | ||
1482 | return 0; | |
48b956c5 CW |
1483 | |
1484 | err_unpin: | |
1485 | i915_gem_object_unpin(obj); | |
1486 | return ret; | |
6b95a207 KH |
1487 | } |
1488 | ||
81255565 JB |
1489 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
1490 | static int | |
1491 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
21c74a8e | 1492 | int x, int y, enum mode_set_atomic state) |
81255565 JB |
1493 | { |
1494 | struct drm_device *dev = crtc->dev; | |
1495 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1496 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1497 | struct intel_framebuffer *intel_fb; | |
05394f39 | 1498 | struct drm_i915_gem_object *obj; |
81255565 JB |
1499 | int plane = intel_crtc->plane; |
1500 | unsigned long Start, Offset; | |
81255565 | 1501 | u32 dspcntr; |
5eddb70b | 1502 | u32 reg; |
81255565 JB |
1503 | |
1504 | switch (plane) { | |
1505 | case 0: | |
1506 | case 1: | |
1507 | break; | |
1508 | default: | |
1509 | DRM_ERROR("Can't update plane %d in SAREA\n", plane); | |
1510 | return -EINVAL; | |
1511 | } | |
1512 | ||
1513 | intel_fb = to_intel_framebuffer(fb); | |
1514 | obj = intel_fb->obj; | |
81255565 | 1515 | |
5eddb70b CW |
1516 | reg = DSPCNTR(plane); |
1517 | dspcntr = I915_READ(reg); | |
81255565 JB |
1518 | /* Mask out pixel format bits in case we change it */ |
1519 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
1520 | switch (fb->bits_per_pixel) { | |
1521 | case 8: | |
1522 | dspcntr |= DISPPLANE_8BPP; | |
1523 | break; | |
1524 | case 16: | |
1525 | if (fb->depth == 15) | |
1526 | dspcntr |= DISPPLANE_15_16BPP; | |
1527 | else | |
1528 | dspcntr |= DISPPLANE_16BPP; | |
1529 | break; | |
1530 | case 24: | |
1531 | case 32: | |
1532 | dspcntr |= DISPPLANE_32BPP_NO_ALPHA; | |
1533 | break; | |
1534 | default: | |
1535 | DRM_ERROR("Unknown color depth\n"); | |
1536 | return -EINVAL; | |
1537 | } | |
a6c45cf0 | 1538 | if (INTEL_INFO(dev)->gen >= 4) { |
05394f39 | 1539 | if (obj->tiling_mode != I915_TILING_NONE) |
81255565 JB |
1540 | dspcntr |= DISPPLANE_TILED; |
1541 | else | |
1542 | dspcntr &= ~DISPPLANE_TILED; | |
1543 | } | |
1544 | ||
4e6cfefc | 1545 | if (HAS_PCH_SPLIT(dev)) |
81255565 JB |
1546 | /* must disable */ |
1547 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
1548 | ||
5eddb70b | 1549 | I915_WRITE(reg, dspcntr); |
81255565 | 1550 | |
05394f39 | 1551 | Start = obj->gtt_offset; |
81255565 JB |
1552 | Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8); |
1553 | ||
4e6cfefc CW |
1554 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
1555 | Start, Offset, x, y, fb->pitch); | |
5eddb70b | 1556 | I915_WRITE(DSPSTRIDE(plane), fb->pitch); |
a6c45cf0 | 1557 | if (INTEL_INFO(dev)->gen >= 4) { |
5eddb70b CW |
1558 | I915_WRITE(DSPSURF(plane), Start); |
1559 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
1560 | I915_WRITE(DSPADDR(plane), Offset); | |
1561 | } else | |
1562 | I915_WRITE(DSPADDR(plane), Start + Offset); | |
1563 | POSTING_READ(reg); | |
81255565 | 1564 | |
bed4a673 | 1565 | intel_update_fbc(dev); |
3dec0095 | 1566 | intel_increase_pllclock(crtc); |
81255565 JB |
1567 | |
1568 | return 0; | |
1569 | } | |
1570 | ||
5c3b82e2 | 1571 | static int |
3c4fdcfb KH |
1572 | intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
1573 | struct drm_framebuffer *old_fb) | |
79e53945 JB |
1574 | { |
1575 | struct drm_device *dev = crtc->dev; | |
79e53945 JB |
1576 | struct drm_i915_master_private *master_priv; |
1577 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5c3b82e2 | 1578 | int ret; |
79e53945 JB |
1579 | |
1580 | /* no fb bound */ | |
1581 | if (!crtc->fb) { | |
28c97730 | 1582 | DRM_DEBUG_KMS("No FB bound\n"); |
5c3b82e2 CW |
1583 | return 0; |
1584 | } | |
1585 | ||
265db958 | 1586 | switch (intel_crtc->plane) { |
5c3b82e2 CW |
1587 | case 0: |
1588 | case 1: | |
1589 | break; | |
1590 | default: | |
5c3b82e2 | 1591 | return -EINVAL; |
79e53945 JB |
1592 | } |
1593 | ||
5c3b82e2 | 1594 | mutex_lock(&dev->struct_mutex); |
265db958 CW |
1595 | ret = intel_pin_and_fence_fb_obj(dev, |
1596 | to_intel_framebuffer(crtc->fb)->obj, | |
919926ae | 1597 | NULL); |
5c3b82e2 CW |
1598 | if (ret != 0) { |
1599 | mutex_unlock(&dev->struct_mutex); | |
1600 | return ret; | |
1601 | } | |
79e53945 | 1602 | |
265db958 | 1603 | if (old_fb) { |
e6c3a2a6 | 1604 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1605 | struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj; |
265db958 | 1606 | |
e6c3a2a6 | 1607 | wait_event(dev_priv->pending_flip_queue, |
05394f39 | 1608 | atomic_read(&obj->pending_flip) == 0); |
85345517 CW |
1609 | |
1610 | /* Big Hammer, we also need to ensure that any pending | |
1611 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
1612 | * current scanout is retired before unpinning the old | |
1613 | * framebuffer. | |
1614 | */ | |
05394f39 | 1615 | ret = i915_gem_object_flush_gpu(obj, false); |
85345517 CW |
1616 | if (ret) { |
1617 | i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj); | |
1618 | mutex_unlock(&dev->struct_mutex); | |
1619 | return ret; | |
1620 | } | |
265db958 CW |
1621 | } |
1622 | ||
21c74a8e JW |
1623 | ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y, |
1624 | LEAVE_ATOMIC_MODE_SET); | |
4e6cfefc | 1625 | if (ret) { |
265db958 | 1626 | i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj); |
5c3b82e2 | 1627 | mutex_unlock(&dev->struct_mutex); |
4e6cfefc | 1628 | return ret; |
79e53945 | 1629 | } |
3c4fdcfb | 1630 | |
265db958 CW |
1631 | if (old_fb) |
1632 | i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj); | |
652c393a | 1633 | |
5c3b82e2 | 1634 | mutex_unlock(&dev->struct_mutex); |
79e53945 JB |
1635 | |
1636 | if (!dev->primary->master) | |
5c3b82e2 | 1637 | return 0; |
79e53945 JB |
1638 | |
1639 | master_priv = dev->primary->master->driver_priv; | |
1640 | if (!master_priv->sarea_priv) | |
5c3b82e2 | 1641 | return 0; |
79e53945 | 1642 | |
265db958 | 1643 | if (intel_crtc->pipe) { |
79e53945 JB |
1644 | master_priv->sarea_priv->pipeB_x = x; |
1645 | master_priv->sarea_priv->pipeB_y = y; | |
5c3b82e2 CW |
1646 | } else { |
1647 | master_priv->sarea_priv->pipeA_x = x; | |
1648 | master_priv->sarea_priv->pipeA_y = y; | |
79e53945 | 1649 | } |
5c3b82e2 CW |
1650 | |
1651 | return 0; | |
79e53945 JB |
1652 | } |
1653 | ||
5eddb70b | 1654 | static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock) |
32f9d658 ZW |
1655 | { |
1656 | struct drm_device *dev = crtc->dev; | |
1657 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1658 | u32 dpa_ctl; | |
1659 | ||
28c97730 | 1660 | DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock); |
32f9d658 ZW |
1661 | dpa_ctl = I915_READ(DP_A); |
1662 | dpa_ctl &= ~DP_PLL_FREQ_MASK; | |
1663 | ||
1664 | if (clock < 200000) { | |
1665 | u32 temp; | |
1666 | dpa_ctl |= DP_PLL_FREQ_160MHZ; | |
1667 | /* workaround for 160Mhz: | |
1668 | 1) program 0x4600c bits 15:0 = 0x8124 | |
1669 | 2) program 0x46010 bit 0 = 1 | |
1670 | 3) program 0x46034 bit 24 = 1 | |
1671 | 4) program 0x64000 bit 14 = 1 | |
1672 | */ | |
1673 | temp = I915_READ(0x4600c); | |
1674 | temp &= 0xffff0000; | |
1675 | I915_WRITE(0x4600c, temp | 0x8124); | |
1676 | ||
1677 | temp = I915_READ(0x46010); | |
1678 | I915_WRITE(0x46010, temp | 1); | |
1679 | ||
1680 | temp = I915_READ(0x46034); | |
1681 | I915_WRITE(0x46034, temp | (1 << 24)); | |
1682 | } else { | |
1683 | dpa_ctl |= DP_PLL_FREQ_270MHZ; | |
1684 | } | |
1685 | I915_WRITE(DP_A, dpa_ctl); | |
1686 | ||
5eddb70b | 1687 | POSTING_READ(DP_A); |
32f9d658 ZW |
1688 | udelay(500); |
1689 | } | |
1690 | ||
5e84e1a4 ZW |
1691 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
1692 | { | |
1693 | struct drm_device *dev = crtc->dev; | |
1694 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1695 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1696 | int pipe = intel_crtc->pipe; | |
1697 | u32 reg, temp; | |
1698 | ||
1699 | /* enable normal train */ | |
1700 | reg = FDI_TX_CTL(pipe); | |
1701 | temp = I915_READ(reg); | |
1702 | temp &= ~FDI_LINK_TRAIN_NONE; | |
1703 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
1704 | I915_WRITE(reg, temp); | |
1705 | ||
1706 | reg = FDI_RX_CTL(pipe); | |
1707 | temp = I915_READ(reg); | |
1708 | if (HAS_PCH_CPT(dev)) { | |
1709 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
1710 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
1711 | } else { | |
1712 | temp &= ~FDI_LINK_TRAIN_NONE; | |
1713 | temp |= FDI_LINK_TRAIN_NONE; | |
1714 | } | |
1715 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
1716 | ||
1717 | /* wait one idle pattern time */ | |
1718 | POSTING_READ(reg); | |
1719 | udelay(1000); | |
1720 | } | |
1721 | ||
8db9d77b ZW |
1722 | /* The FDI link training functions for ILK/Ibexpeak. */ |
1723 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
1724 | { | |
1725 | struct drm_device *dev = crtc->dev; | |
1726 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1727 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1728 | int pipe = intel_crtc->pipe; | |
5eddb70b | 1729 | u32 reg, temp, tries; |
8db9d77b | 1730 | |
e1a44743 AJ |
1731 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
1732 | for train result */ | |
5eddb70b CW |
1733 | reg = FDI_RX_IMR(pipe); |
1734 | temp = I915_READ(reg); | |
e1a44743 AJ |
1735 | temp &= ~FDI_RX_SYMBOL_LOCK; |
1736 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
1737 | I915_WRITE(reg, temp); |
1738 | I915_READ(reg); | |
e1a44743 AJ |
1739 | udelay(150); |
1740 | ||
8db9d77b | 1741 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
1742 | reg = FDI_TX_CTL(pipe); |
1743 | temp = I915_READ(reg); | |
77ffb597 AJ |
1744 | temp &= ~(7 << 19); |
1745 | temp |= (intel_crtc->fdi_lanes - 1) << 19; | |
8db9d77b ZW |
1746 | temp &= ~FDI_LINK_TRAIN_NONE; |
1747 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 1748 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 1749 | |
5eddb70b CW |
1750 | reg = FDI_RX_CTL(pipe); |
1751 | temp = I915_READ(reg); | |
8db9d77b ZW |
1752 | temp &= ~FDI_LINK_TRAIN_NONE; |
1753 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
1754 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
1755 | ||
1756 | POSTING_READ(reg); | |
8db9d77b ZW |
1757 | udelay(150); |
1758 | ||
5b2adf89 JB |
1759 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
1760 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_ENABLE); | |
1761 | ||
5eddb70b | 1762 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 1763 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 1764 | temp = I915_READ(reg); |
8db9d77b ZW |
1765 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
1766 | ||
1767 | if ((temp & FDI_RX_BIT_LOCK)) { | |
1768 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 1769 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
1770 | break; |
1771 | } | |
8db9d77b | 1772 | } |
e1a44743 | 1773 | if (tries == 5) |
5eddb70b | 1774 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
1775 | |
1776 | /* Train 2 */ | |
5eddb70b CW |
1777 | reg = FDI_TX_CTL(pipe); |
1778 | temp = I915_READ(reg); | |
8db9d77b ZW |
1779 | temp &= ~FDI_LINK_TRAIN_NONE; |
1780 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 1781 | I915_WRITE(reg, temp); |
8db9d77b | 1782 | |
5eddb70b CW |
1783 | reg = FDI_RX_CTL(pipe); |
1784 | temp = I915_READ(reg); | |
8db9d77b ZW |
1785 | temp &= ~FDI_LINK_TRAIN_NONE; |
1786 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 1787 | I915_WRITE(reg, temp); |
8db9d77b | 1788 | |
5eddb70b CW |
1789 | POSTING_READ(reg); |
1790 | udelay(150); | |
8db9d77b | 1791 | |
5eddb70b | 1792 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 1793 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 1794 | temp = I915_READ(reg); |
8db9d77b ZW |
1795 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
1796 | ||
1797 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 1798 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
1799 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
1800 | break; | |
1801 | } | |
8db9d77b | 1802 | } |
e1a44743 | 1803 | if (tries == 5) |
5eddb70b | 1804 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
1805 | |
1806 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 1807 | |
8db9d77b ZW |
1808 | } |
1809 | ||
5eddb70b | 1810 | static const int const snb_b_fdi_train_param [] = { |
8db9d77b ZW |
1811 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
1812 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
1813 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
1814 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
1815 | }; | |
1816 | ||
1817 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
1818 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
1819 | { | |
1820 | struct drm_device *dev = crtc->dev; | |
1821 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1822 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1823 | int pipe = intel_crtc->pipe; | |
5eddb70b | 1824 | u32 reg, temp, i; |
8db9d77b | 1825 | |
e1a44743 AJ |
1826 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
1827 | for train result */ | |
5eddb70b CW |
1828 | reg = FDI_RX_IMR(pipe); |
1829 | temp = I915_READ(reg); | |
e1a44743 AJ |
1830 | temp &= ~FDI_RX_SYMBOL_LOCK; |
1831 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
1832 | I915_WRITE(reg, temp); |
1833 | ||
1834 | POSTING_READ(reg); | |
e1a44743 AJ |
1835 | udelay(150); |
1836 | ||
8db9d77b | 1837 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
1838 | reg = FDI_TX_CTL(pipe); |
1839 | temp = I915_READ(reg); | |
77ffb597 AJ |
1840 | temp &= ~(7 << 19); |
1841 | temp |= (intel_crtc->fdi_lanes - 1) << 19; | |
8db9d77b ZW |
1842 | temp &= ~FDI_LINK_TRAIN_NONE; |
1843 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
1844 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
1845 | /* SNB-B */ | |
1846 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 1847 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 1848 | |
5eddb70b CW |
1849 | reg = FDI_RX_CTL(pipe); |
1850 | temp = I915_READ(reg); | |
8db9d77b ZW |
1851 | if (HAS_PCH_CPT(dev)) { |
1852 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
1853 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
1854 | } else { | |
1855 | temp &= ~FDI_LINK_TRAIN_NONE; | |
1856 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
1857 | } | |
5eddb70b CW |
1858 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
1859 | ||
1860 | POSTING_READ(reg); | |
8db9d77b ZW |
1861 | udelay(150); |
1862 | ||
8db9d77b | 1863 | for (i = 0; i < 4; i++ ) { |
5eddb70b CW |
1864 | reg = FDI_TX_CTL(pipe); |
1865 | temp = I915_READ(reg); | |
8db9d77b ZW |
1866 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
1867 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
1868 | I915_WRITE(reg, temp); |
1869 | ||
1870 | POSTING_READ(reg); | |
8db9d77b ZW |
1871 | udelay(500); |
1872 | ||
5eddb70b CW |
1873 | reg = FDI_RX_IIR(pipe); |
1874 | temp = I915_READ(reg); | |
8db9d77b ZW |
1875 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
1876 | ||
1877 | if (temp & FDI_RX_BIT_LOCK) { | |
5eddb70b | 1878 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
1879 | DRM_DEBUG_KMS("FDI train 1 done.\n"); |
1880 | break; | |
1881 | } | |
1882 | } | |
1883 | if (i == 4) | |
5eddb70b | 1884 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
1885 | |
1886 | /* Train 2 */ | |
5eddb70b CW |
1887 | reg = FDI_TX_CTL(pipe); |
1888 | temp = I915_READ(reg); | |
8db9d77b ZW |
1889 | temp &= ~FDI_LINK_TRAIN_NONE; |
1890 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
1891 | if (IS_GEN6(dev)) { | |
1892 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
1893 | /* SNB-B */ | |
1894 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
1895 | } | |
5eddb70b | 1896 | I915_WRITE(reg, temp); |
8db9d77b | 1897 | |
5eddb70b CW |
1898 | reg = FDI_RX_CTL(pipe); |
1899 | temp = I915_READ(reg); | |
8db9d77b ZW |
1900 | if (HAS_PCH_CPT(dev)) { |
1901 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
1902 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
1903 | } else { | |
1904 | temp &= ~FDI_LINK_TRAIN_NONE; | |
1905 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
1906 | } | |
5eddb70b CW |
1907 | I915_WRITE(reg, temp); |
1908 | ||
1909 | POSTING_READ(reg); | |
8db9d77b ZW |
1910 | udelay(150); |
1911 | ||
1912 | for (i = 0; i < 4; i++ ) { | |
5eddb70b CW |
1913 | reg = FDI_TX_CTL(pipe); |
1914 | temp = I915_READ(reg); | |
8db9d77b ZW |
1915 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
1916 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
1917 | I915_WRITE(reg, temp); |
1918 | ||
1919 | POSTING_READ(reg); | |
8db9d77b ZW |
1920 | udelay(500); |
1921 | ||
5eddb70b CW |
1922 | reg = FDI_RX_IIR(pipe); |
1923 | temp = I915_READ(reg); | |
8db9d77b ZW |
1924 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
1925 | ||
1926 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 1927 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
1928 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
1929 | break; | |
1930 | } | |
1931 | } | |
1932 | if (i == 4) | |
5eddb70b | 1933 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
1934 | |
1935 | DRM_DEBUG_KMS("FDI train done.\n"); | |
1936 | } | |
1937 | ||
0e23b99d | 1938 | static void ironlake_fdi_enable(struct drm_crtc *crtc) |
2c07245f ZW |
1939 | { |
1940 | struct drm_device *dev = crtc->dev; | |
1941 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1942 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1943 | int pipe = intel_crtc->pipe; | |
5eddb70b | 1944 | u32 reg, temp; |
79e53945 | 1945 | |
c64e311e | 1946 | /* Write the TU size bits so error detection works */ |
5eddb70b CW |
1947 | I915_WRITE(FDI_RX_TUSIZE1(pipe), |
1948 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
c64e311e | 1949 | |
c98e9dcf | 1950 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
1951 | reg = FDI_RX_CTL(pipe); |
1952 | temp = I915_READ(reg); | |
1953 | temp &= ~((0x7 << 19) | (0x7 << 16)); | |
c98e9dcf | 1954 | temp |= (intel_crtc->fdi_lanes - 1) << 19; |
5eddb70b CW |
1955 | temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; |
1956 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); | |
1957 | ||
1958 | POSTING_READ(reg); | |
c98e9dcf JB |
1959 | udelay(200); |
1960 | ||
1961 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
1962 | temp = I915_READ(reg); |
1963 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
1964 | ||
1965 | POSTING_READ(reg); | |
c98e9dcf JB |
1966 | udelay(200); |
1967 | ||
1968 | /* Enable CPU FDI TX PLL, always on for Ironlake */ | |
5eddb70b CW |
1969 | reg = FDI_TX_CTL(pipe); |
1970 | temp = I915_READ(reg); | |
c98e9dcf | 1971 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { |
5eddb70b CW |
1972 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); |
1973 | ||
1974 | POSTING_READ(reg); | |
c98e9dcf | 1975 | udelay(100); |
6be4a607 | 1976 | } |
0e23b99d JB |
1977 | } |
1978 | ||
5eddb70b CW |
1979 | static void intel_flush_display_plane(struct drm_device *dev, |
1980 | int plane) | |
1981 | { | |
1982 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1983 | u32 reg = DSPADDR(plane); | |
1984 | I915_WRITE(reg, I915_READ(reg)); | |
1985 | } | |
1986 | ||
6b383a7f CW |
1987 | /* |
1988 | * When we disable a pipe, we need to clear any pending scanline wait events | |
1989 | * to avoid hanging the ring, which we assume we are waiting on. | |
1990 | */ | |
1991 | static void intel_clear_scanline_wait(struct drm_device *dev) | |
1992 | { | |
1993 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8168bd48 | 1994 | struct intel_ring_buffer *ring; |
6b383a7f CW |
1995 | u32 tmp; |
1996 | ||
1997 | if (IS_GEN2(dev)) | |
1998 | /* Can't break the hang on i8xx */ | |
1999 | return; | |
2000 | ||
1ec14ad3 | 2001 | ring = LP_RING(dev_priv); |
8168bd48 CW |
2002 | tmp = I915_READ_CTL(ring); |
2003 | if (tmp & RING_WAIT) | |
2004 | I915_WRITE_CTL(ring, tmp); | |
6b383a7f CW |
2005 | } |
2006 | ||
e6c3a2a6 CW |
2007 | static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
2008 | { | |
05394f39 | 2009 | struct drm_i915_gem_object *obj; |
e6c3a2a6 CW |
2010 | struct drm_i915_private *dev_priv; |
2011 | ||
2012 | if (crtc->fb == NULL) | |
2013 | return; | |
2014 | ||
05394f39 | 2015 | obj = to_intel_framebuffer(crtc->fb)->obj; |
e6c3a2a6 CW |
2016 | dev_priv = crtc->dev->dev_private; |
2017 | wait_event(dev_priv->pending_flip_queue, | |
05394f39 | 2018 | atomic_read(&obj->pending_flip) == 0); |
e6c3a2a6 CW |
2019 | } |
2020 | ||
0e23b99d JB |
2021 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
2022 | { | |
2023 | struct drm_device *dev = crtc->dev; | |
2024 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2025 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2026 | int pipe = intel_crtc->pipe; | |
2027 | int plane = intel_crtc->plane; | |
5eddb70b | 2028 | u32 reg, temp; |
0e23b99d | 2029 | |
f7abfe8b CW |
2030 | if (intel_crtc->active) |
2031 | return; | |
2032 | ||
2033 | intel_crtc->active = true; | |
6b383a7f CW |
2034 | intel_update_watermarks(dev); |
2035 | ||
0e23b99d JB |
2036 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
2037 | temp = I915_READ(PCH_LVDS); | |
5eddb70b | 2038 | if ((temp & LVDS_PORT_EN) == 0) |
0e23b99d | 2039 | I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN); |
0e23b99d JB |
2040 | } |
2041 | ||
2042 | ironlake_fdi_enable(crtc); | |
2c07245f | 2043 | |
6be4a607 JB |
2044 | /* Enable panel fitting for LVDS */ |
2045 | if (dev_priv->pch_pf_size && | |
1d850362 | 2046 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) { |
6be4a607 JB |
2047 | /* Force use of hard-coded filter coefficients |
2048 | * as some pre-programmed values are broken, | |
2049 | * e.g. x201. | |
2050 | */ | |
2051 | I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1, | |
2052 | PF_ENABLE | PF_FILTER_MED_3x3); | |
2053 | I915_WRITE(pipe ? PFB_WIN_POS : PFA_WIN_POS, | |
2054 | dev_priv->pch_pf_pos); | |
2055 | I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ, | |
2056 | dev_priv->pch_pf_size); | |
2057 | } | |
2c07245f | 2058 | |
6be4a607 | 2059 | /* Enable CPU pipe */ |
5eddb70b CW |
2060 | reg = PIPECONF(pipe); |
2061 | temp = I915_READ(reg); | |
2062 | if ((temp & PIPECONF_ENABLE) == 0) { | |
2063 | I915_WRITE(reg, temp | PIPECONF_ENABLE); | |
2064 | POSTING_READ(reg); | |
17f6766c | 2065 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
6be4a607 | 2066 | } |
2c07245f | 2067 | |
6be4a607 | 2068 | /* configure and enable CPU plane */ |
5eddb70b CW |
2069 | reg = DSPCNTR(plane); |
2070 | temp = I915_READ(reg); | |
6be4a607 | 2071 | if ((temp & DISPLAY_PLANE_ENABLE) == 0) { |
5eddb70b CW |
2072 | I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE); |
2073 | intel_flush_display_plane(dev, plane); | |
6be4a607 | 2074 | } |
2c07245f | 2075 | |
c98e9dcf JB |
2076 | /* For PCH output, training FDI link */ |
2077 | if (IS_GEN6(dev)) | |
2078 | gen6_fdi_link_train(crtc); | |
2079 | else | |
2080 | ironlake_fdi_link_train(crtc); | |
2c07245f | 2081 | |
c98e9dcf | 2082 | /* enable PCH DPLL */ |
5eddb70b CW |
2083 | reg = PCH_DPLL(pipe); |
2084 | temp = I915_READ(reg); | |
c98e9dcf | 2085 | if ((temp & DPLL_VCO_ENABLE) == 0) { |
5eddb70b CW |
2086 | I915_WRITE(reg, temp | DPLL_VCO_ENABLE); |
2087 | POSTING_READ(reg); | |
8c4223be | 2088 | udelay(200); |
c98e9dcf | 2089 | } |
8db9d77b | 2090 | |
c98e9dcf JB |
2091 | if (HAS_PCH_CPT(dev)) { |
2092 | /* Be sure PCH DPLL SEL is set */ | |
2093 | temp = I915_READ(PCH_DPLL_SEL); | |
5eddb70b | 2094 | if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0) |
c98e9dcf | 2095 | temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL); |
5eddb70b | 2096 | else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0) |
c98e9dcf JB |
2097 | temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL); |
2098 | I915_WRITE(PCH_DPLL_SEL, temp); | |
c98e9dcf | 2099 | } |
5eddb70b | 2100 | |
c98e9dcf | 2101 | /* set transcoder timing */ |
5eddb70b CW |
2102 | I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe))); |
2103 | I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe))); | |
2104 | I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe))); | |
8db9d77b | 2105 | |
5eddb70b CW |
2106 | I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe))); |
2107 | I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe))); | |
2108 | I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe))); | |
8db9d77b | 2109 | |
5e84e1a4 ZW |
2110 | intel_fdi_normal_train(crtc); |
2111 | ||
c98e9dcf JB |
2112 | /* For PCH DP, enable TRANS_DP_CTL */ |
2113 | if (HAS_PCH_CPT(dev) && | |
2114 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { | |
5eddb70b CW |
2115 | reg = TRANS_DP_CTL(pipe); |
2116 | temp = I915_READ(reg); | |
2117 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
2118 | TRANS_DP_SYNC_MASK | |
2119 | TRANS_DP_BPC_MASK); | |
5eddb70b CW |
2120 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
2121 | TRANS_DP_ENH_FRAMING); | |
220cad3c | 2122 | temp |= TRANS_DP_8BPC; |
c98e9dcf JB |
2123 | |
2124 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) | |
5eddb70b | 2125 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
c98e9dcf | 2126 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 2127 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
2128 | |
2129 | switch (intel_trans_dp_port_sel(crtc)) { | |
2130 | case PCH_DP_B: | |
5eddb70b | 2131 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf JB |
2132 | break; |
2133 | case PCH_DP_C: | |
5eddb70b | 2134 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf JB |
2135 | break; |
2136 | case PCH_DP_D: | |
5eddb70b | 2137 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
2138 | break; |
2139 | default: | |
2140 | DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n"); | |
5eddb70b | 2141 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf | 2142 | break; |
32f9d658 | 2143 | } |
2c07245f | 2144 | |
5eddb70b | 2145 | I915_WRITE(reg, temp); |
6be4a607 | 2146 | } |
b52eb4dc | 2147 | |
c98e9dcf | 2148 | /* enable PCH transcoder */ |
5eddb70b CW |
2149 | reg = TRANSCONF(pipe); |
2150 | temp = I915_READ(reg); | |
c98e9dcf JB |
2151 | /* |
2152 | * make the BPC in transcoder be consistent with | |
2153 | * that in pipeconf reg. | |
2154 | */ | |
2155 | temp &= ~PIPE_BPC_MASK; | |
5eddb70b CW |
2156 | temp |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK; |
2157 | I915_WRITE(reg, temp | TRANS_ENABLE); | |
2158 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
17f6766c | 2159 | DRM_ERROR("failed to enable transcoder %d\n", pipe); |
c98e9dcf | 2160 | |
6be4a607 | 2161 | intel_crtc_load_lut(crtc); |
bed4a673 | 2162 | intel_update_fbc(dev); |
6b383a7f | 2163 | intel_crtc_update_cursor(crtc, true); |
6be4a607 JB |
2164 | } |
2165 | ||
2166 | static void ironlake_crtc_disable(struct drm_crtc *crtc) | |
2167 | { | |
2168 | struct drm_device *dev = crtc->dev; | |
2169 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2170 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2171 | int pipe = intel_crtc->pipe; | |
2172 | int plane = intel_crtc->plane; | |
5eddb70b | 2173 | u32 reg, temp; |
b52eb4dc | 2174 | |
f7abfe8b CW |
2175 | if (!intel_crtc->active) |
2176 | return; | |
2177 | ||
e6c3a2a6 | 2178 | intel_crtc_wait_for_pending_flips(crtc); |
6be4a607 | 2179 | drm_vblank_off(dev, pipe); |
6b383a7f | 2180 | intel_crtc_update_cursor(crtc, false); |
5eddb70b | 2181 | |
6be4a607 | 2182 | /* Disable display plane */ |
5eddb70b CW |
2183 | reg = DSPCNTR(plane); |
2184 | temp = I915_READ(reg); | |
2185 | if (temp & DISPLAY_PLANE_ENABLE) { | |
2186 | I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE); | |
2187 | intel_flush_display_plane(dev, plane); | |
6be4a607 | 2188 | } |
913d8d11 | 2189 | |
6be4a607 JB |
2190 | if (dev_priv->cfb_plane == plane && |
2191 | dev_priv->display.disable_fbc) | |
2192 | dev_priv->display.disable_fbc(dev); | |
2c07245f | 2193 | |
6be4a607 | 2194 | /* disable cpu pipe, disable after all planes disabled */ |
5eddb70b CW |
2195 | reg = PIPECONF(pipe); |
2196 | temp = I915_READ(reg); | |
2197 | if (temp & PIPECONF_ENABLE) { | |
2198 | I915_WRITE(reg, temp & ~PIPECONF_ENABLE); | |
17f6766c | 2199 | POSTING_READ(reg); |
6be4a607 | 2200 | /* wait for cpu pipe off, pipe state */ |
17f6766c | 2201 | intel_wait_for_pipe_off(dev, intel_crtc->pipe); |
5eddb70b | 2202 | } |
32f9d658 | 2203 | |
6be4a607 JB |
2204 | /* Disable PF */ |
2205 | I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1, 0); | |
2206 | I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ, 0); | |
2c07245f | 2207 | |
6be4a607 | 2208 | /* disable CPU FDI tx and PCH FDI rx */ |
5eddb70b CW |
2209 | reg = FDI_TX_CTL(pipe); |
2210 | temp = I915_READ(reg); | |
2211 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
2212 | POSTING_READ(reg); | |
249c0e64 | 2213 | |
5eddb70b CW |
2214 | reg = FDI_RX_CTL(pipe); |
2215 | temp = I915_READ(reg); | |
2216 | temp &= ~(0x7 << 16); | |
2217 | temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; | |
2218 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); | |
6be4a607 | 2219 | |
5eddb70b | 2220 | POSTING_READ(reg); |
6be4a607 JB |
2221 | udelay(100); |
2222 | ||
5b2adf89 | 2223 | /* Ironlake workaround, disable clock pointer after downing FDI */ |
e07ac3a0 ZW |
2224 | if (HAS_PCH_IBX(dev)) |
2225 | I915_WRITE(FDI_RX_CHICKEN(pipe), | |
2226 | I915_READ(FDI_RX_CHICKEN(pipe) & | |
2227 | ~FDI_RX_PHASE_SYNC_POINTER_ENABLE)); | |
5b2adf89 | 2228 | |
6be4a607 | 2229 | /* still set train pattern 1 */ |
5eddb70b CW |
2230 | reg = FDI_TX_CTL(pipe); |
2231 | temp = I915_READ(reg); | |
6be4a607 JB |
2232 | temp &= ~FDI_LINK_TRAIN_NONE; |
2233 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 2234 | I915_WRITE(reg, temp); |
6be4a607 | 2235 | |
5eddb70b CW |
2236 | reg = FDI_RX_CTL(pipe); |
2237 | temp = I915_READ(reg); | |
6be4a607 JB |
2238 | if (HAS_PCH_CPT(dev)) { |
2239 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2240 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
2241 | } else { | |
2c07245f ZW |
2242 | temp &= ~FDI_LINK_TRAIN_NONE; |
2243 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
6be4a607 | 2244 | } |
5eddb70b CW |
2245 | /* BPC in FDI rx is consistent with that in PIPECONF */ |
2246 | temp &= ~(0x07 << 16); | |
2247 | temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; | |
2248 | I915_WRITE(reg, temp); | |
2c07245f | 2249 | |
5eddb70b | 2250 | POSTING_READ(reg); |
6be4a607 | 2251 | udelay(100); |
2c07245f | 2252 | |
6be4a607 JB |
2253 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
2254 | temp = I915_READ(PCH_LVDS); | |
5eddb70b CW |
2255 | if (temp & LVDS_PORT_EN) { |
2256 | I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN); | |
2257 | POSTING_READ(PCH_LVDS); | |
2258 | udelay(100); | |
2259 | } | |
6be4a607 | 2260 | } |
249c0e64 | 2261 | |
6be4a607 | 2262 | /* disable PCH transcoder */ |
5eddb70b CW |
2263 | reg = TRANSCONF(plane); |
2264 | temp = I915_READ(reg); | |
2265 | if (temp & TRANS_ENABLE) { | |
2266 | I915_WRITE(reg, temp & ~TRANS_ENABLE); | |
6be4a607 | 2267 | /* wait for PCH transcoder off, transcoder state */ |
5eddb70b | 2268 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) |
6be4a607 JB |
2269 | DRM_ERROR("failed to disable transcoder\n"); |
2270 | } | |
913d8d11 | 2271 | |
6be4a607 JB |
2272 | if (HAS_PCH_CPT(dev)) { |
2273 | /* disable TRANS_DP_CTL */ | |
5eddb70b CW |
2274 | reg = TRANS_DP_CTL(pipe); |
2275 | temp = I915_READ(reg); | |
2276 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK); | |
2277 | I915_WRITE(reg, temp); | |
6be4a607 JB |
2278 | |
2279 | /* disable DPLL_SEL */ | |
2280 | temp = I915_READ(PCH_DPLL_SEL); | |
5eddb70b | 2281 | if (pipe == 0) |
6be4a607 JB |
2282 | temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL); |
2283 | else | |
2284 | temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL); | |
2285 | I915_WRITE(PCH_DPLL_SEL, temp); | |
6be4a607 | 2286 | } |
e3421a18 | 2287 | |
6be4a607 | 2288 | /* disable PCH DPLL */ |
5eddb70b CW |
2289 | reg = PCH_DPLL(pipe); |
2290 | temp = I915_READ(reg); | |
2291 | I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE); | |
8db9d77b | 2292 | |
6be4a607 | 2293 | /* Switch from PCDclk to Rawclk */ |
5eddb70b CW |
2294 | reg = FDI_RX_CTL(pipe); |
2295 | temp = I915_READ(reg); | |
2296 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
8db9d77b | 2297 | |
6be4a607 | 2298 | /* Disable CPU FDI TX PLL */ |
5eddb70b CW |
2299 | reg = FDI_TX_CTL(pipe); |
2300 | temp = I915_READ(reg); | |
2301 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
2302 | ||
2303 | POSTING_READ(reg); | |
6be4a607 | 2304 | udelay(100); |
8db9d77b | 2305 | |
5eddb70b CW |
2306 | reg = FDI_RX_CTL(pipe); |
2307 | temp = I915_READ(reg); | |
2308 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
2c07245f | 2309 | |
6be4a607 | 2310 | /* Wait for the clocks to turn off. */ |
5eddb70b | 2311 | POSTING_READ(reg); |
6be4a607 | 2312 | udelay(100); |
6b383a7f | 2313 | |
f7abfe8b | 2314 | intel_crtc->active = false; |
6b383a7f CW |
2315 | intel_update_watermarks(dev); |
2316 | intel_update_fbc(dev); | |
2317 | intel_clear_scanline_wait(dev); | |
6be4a607 | 2318 | } |
1b3c7a47 | 2319 | |
6be4a607 JB |
2320 | static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode) |
2321 | { | |
2322 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2323 | int pipe = intel_crtc->pipe; | |
2324 | int plane = intel_crtc->plane; | |
8db9d77b | 2325 | |
6be4a607 JB |
2326 | /* XXX: When our outputs are all unaware of DPMS modes other than off |
2327 | * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. | |
2328 | */ | |
2329 | switch (mode) { | |
2330 | case DRM_MODE_DPMS_ON: | |
2331 | case DRM_MODE_DPMS_STANDBY: | |
2332 | case DRM_MODE_DPMS_SUSPEND: | |
2333 | DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane); | |
2334 | ironlake_crtc_enable(crtc); | |
2335 | break; | |
1b3c7a47 | 2336 | |
6be4a607 JB |
2337 | case DRM_MODE_DPMS_OFF: |
2338 | DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane); | |
2339 | ironlake_crtc_disable(crtc); | |
2c07245f ZW |
2340 | break; |
2341 | } | |
2342 | } | |
2343 | ||
02e792fb DV |
2344 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
2345 | { | |
02e792fb | 2346 | if (!enable && intel_crtc->overlay) { |
23f09ce3 | 2347 | struct drm_device *dev = intel_crtc->base.dev; |
03f77ea5 | 2348 | |
23f09ce3 CW |
2349 | mutex_lock(&dev->struct_mutex); |
2350 | (void) intel_overlay_switch_off(intel_crtc->overlay, false); | |
2351 | mutex_unlock(&dev->struct_mutex); | |
02e792fb | 2352 | } |
02e792fb | 2353 | |
5dcdbcb0 CW |
2354 | /* Let userspace switch the overlay on again. In most cases userspace |
2355 | * has to recompute where to put it anyway. | |
2356 | */ | |
02e792fb DV |
2357 | } |
2358 | ||
0b8765c6 | 2359 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
2360 | { |
2361 | struct drm_device *dev = crtc->dev; | |
79e53945 JB |
2362 | struct drm_i915_private *dev_priv = dev->dev_private; |
2363 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2364 | int pipe = intel_crtc->pipe; | |
80824003 | 2365 | int plane = intel_crtc->plane; |
5eddb70b | 2366 | u32 reg, temp; |
79e53945 | 2367 | |
f7abfe8b CW |
2368 | if (intel_crtc->active) |
2369 | return; | |
2370 | ||
2371 | intel_crtc->active = true; | |
6b383a7f CW |
2372 | intel_update_watermarks(dev); |
2373 | ||
0b8765c6 | 2374 | /* Enable the DPLL */ |
5eddb70b CW |
2375 | reg = DPLL(pipe); |
2376 | temp = I915_READ(reg); | |
0b8765c6 | 2377 | if ((temp & DPLL_VCO_ENABLE) == 0) { |
5eddb70b CW |
2378 | I915_WRITE(reg, temp); |
2379 | ||
0b8765c6 | 2380 | /* Wait for the clocks to stabilize. */ |
5eddb70b | 2381 | POSTING_READ(reg); |
0b8765c6 | 2382 | udelay(150); |
5eddb70b CW |
2383 | |
2384 | I915_WRITE(reg, temp | DPLL_VCO_ENABLE); | |
2385 | ||
0b8765c6 | 2386 | /* Wait for the clocks to stabilize. */ |
5eddb70b | 2387 | POSTING_READ(reg); |
0b8765c6 | 2388 | udelay(150); |
5eddb70b CW |
2389 | |
2390 | I915_WRITE(reg, temp | DPLL_VCO_ENABLE); | |
2391 | ||
0b8765c6 | 2392 | /* Wait for the clocks to stabilize. */ |
5eddb70b | 2393 | POSTING_READ(reg); |
0b8765c6 JB |
2394 | udelay(150); |
2395 | } | |
79e53945 | 2396 | |
0b8765c6 | 2397 | /* Enable the pipe */ |
5eddb70b CW |
2398 | reg = PIPECONF(pipe); |
2399 | temp = I915_READ(reg); | |
2400 | if ((temp & PIPECONF_ENABLE) == 0) | |
2401 | I915_WRITE(reg, temp | PIPECONF_ENABLE); | |
79e53945 | 2402 | |
0b8765c6 | 2403 | /* Enable the plane */ |
5eddb70b CW |
2404 | reg = DSPCNTR(plane); |
2405 | temp = I915_READ(reg); | |
0b8765c6 | 2406 | if ((temp & DISPLAY_PLANE_ENABLE) == 0) { |
5eddb70b CW |
2407 | I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE); |
2408 | intel_flush_display_plane(dev, plane); | |
0b8765c6 | 2409 | } |
79e53945 | 2410 | |
0b8765c6 | 2411 | intel_crtc_load_lut(crtc); |
bed4a673 | 2412 | intel_update_fbc(dev); |
79e53945 | 2413 | |
0b8765c6 JB |
2414 | /* Give the overlay scaler a chance to enable if it's on this pipe */ |
2415 | intel_crtc_dpms_overlay(intel_crtc, true); | |
6b383a7f | 2416 | intel_crtc_update_cursor(crtc, true); |
0b8765c6 | 2417 | } |
79e53945 | 2418 | |
0b8765c6 JB |
2419 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
2420 | { | |
2421 | struct drm_device *dev = crtc->dev; | |
2422 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2423 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2424 | int pipe = intel_crtc->pipe; | |
2425 | int plane = intel_crtc->plane; | |
5eddb70b | 2426 | u32 reg, temp; |
b690e96c | 2427 | |
f7abfe8b CW |
2428 | if (!intel_crtc->active) |
2429 | return; | |
2430 | ||
0b8765c6 | 2431 | /* Give the overlay scaler a chance to disable if it's on this pipe */ |
e6c3a2a6 CW |
2432 | intel_crtc_wait_for_pending_flips(crtc); |
2433 | drm_vblank_off(dev, pipe); | |
0b8765c6 | 2434 | intel_crtc_dpms_overlay(intel_crtc, false); |
6b383a7f | 2435 | intel_crtc_update_cursor(crtc, false); |
0b8765c6 JB |
2436 | |
2437 | if (dev_priv->cfb_plane == plane && | |
2438 | dev_priv->display.disable_fbc) | |
2439 | dev_priv->display.disable_fbc(dev); | |
79e53945 | 2440 | |
0b8765c6 | 2441 | /* Disable display plane */ |
5eddb70b CW |
2442 | reg = DSPCNTR(plane); |
2443 | temp = I915_READ(reg); | |
2444 | if (temp & DISPLAY_PLANE_ENABLE) { | |
2445 | I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE); | |
0b8765c6 | 2446 | /* Flush the plane changes */ |
5eddb70b | 2447 | intel_flush_display_plane(dev, plane); |
0b8765c6 | 2448 | |
0b8765c6 | 2449 | /* Wait for vblank for the disable to take effect */ |
a6c45cf0 | 2450 | if (IS_GEN2(dev)) |
ab7ad7f6 | 2451 | intel_wait_for_vblank(dev, pipe); |
0b8765c6 | 2452 | } |
79e53945 | 2453 | |
0b8765c6 | 2454 | /* Don't disable pipe A or pipe A PLLs if needed */ |
5eddb70b | 2455 | if (pipe == 0 && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) |
6b383a7f | 2456 | goto done; |
0b8765c6 JB |
2457 | |
2458 | /* Next, disable display pipes */ | |
5eddb70b CW |
2459 | reg = PIPECONF(pipe); |
2460 | temp = I915_READ(reg); | |
2461 | if (temp & PIPECONF_ENABLE) { | |
2462 | I915_WRITE(reg, temp & ~PIPECONF_ENABLE); | |
2463 | ||
ab7ad7f6 | 2464 | /* Wait for the pipe to turn off */ |
5eddb70b | 2465 | POSTING_READ(reg); |
ab7ad7f6 | 2466 | intel_wait_for_pipe_off(dev, pipe); |
0b8765c6 JB |
2467 | } |
2468 | ||
5eddb70b CW |
2469 | reg = DPLL(pipe); |
2470 | temp = I915_READ(reg); | |
2471 | if (temp & DPLL_VCO_ENABLE) { | |
2472 | I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE); | |
0b8765c6 | 2473 | |
5eddb70b CW |
2474 | /* Wait for the clocks to turn off. */ |
2475 | POSTING_READ(reg); | |
2476 | udelay(150); | |
0b8765c6 | 2477 | } |
6b383a7f CW |
2478 | |
2479 | done: | |
f7abfe8b | 2480 | intel_crtc->active = false; |
6b383a7f CW |
2481 | intel_update_fbc(dev); |
2482 | intel_update_watermarks(dev); | |
2483 | intel_clear_scanline_wait(dev); | |
0b8765c6 JB |
2484 | } |
2485 | ||
2486 | static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode) | |
2487 | { | |
2488 | /* XXX: When our outputs are all unaware of DPMS modes other than off | |
2489 | * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. | |
2490 | */ | |
2491 | switch (mode) { | |
2492 | case DRM_MODE_DPMS_ON: | |
2493 | case DRM_MODE_DPMS_STANDBY: | |
2494 | case DRM_MODE_DPMS_SUSPEND: | |
2495 | i9xx_crtc_enable(crtc); | |
2496 | break; | |
2497 | case DRM_MODE_DPMS_OFF: | |
2498 | i9xx_crtc_disable(crtc); | |
79e53945 JB |
2499 | break; |
2500 | } | |
2c07245f ZW |
2501 | } |
2502 | ||
2503 | /** | |
2504 | * Sets the power management mode of the pipe and plane. | |
2c07245f ZW |
2505 | */ |
2506 | static void intel_crtc_dpms(struct drm_crtc *crtc, int mode) | |
2507 | { | |
2508 | struct drm_device *dev = crtc->dev; | |
e70236a8 | 2509 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f ZW |
2510 | struct drm_i915_master_private *master_priv; |
2511 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2512 | int pipe = intel_crtc->pipe; | |
2513 | bool enabled; | |
2514 | ||
032d2a0d CW |
2515 | if (intel_crtc->dpms_mode == mode) |
2516 | return; | |
2517 | ||
65655d4a | 2518 | intel_crtc->dpms_mode = mode; |
debcaddc | 2519 | |
e70236a8 | 2520 | dev_priv->display.dpms(crtc, mode); |
79e53945 JB |
2521 | |
2522 | if (!dev->primary->master) | |
2523 | return; | |
2524 | ||
2525 | master_priv = dev->primary->master->driver_priv; | |
2526 | if (!master_priv->sarea_priv) | |
2527 | return; | |
2528 | ||
2529 | enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF; | |
2530 | ||
2531 | switch (pipe) { | |
2532 | case 0: | |
2533 | master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; | |
2534 | master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; | |
2535 | break; | |
2536 | case 1: | |
2537 | master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; | |
2538 | master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; | |
2539 | break; | |
2540 | default: | |
2541 | DRM_ERROR("Can't update pipe %d in SAREA\n", pipe); | |
2542 | break; | |
2543 | } | |
79e53945 JB |
2544 | } |
2545 | ||
cdd59983 CW |
2546 | static void intel_crtc_disable(struct drm_crtc *crtc) |
2547 | { | |
2548 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; | |
2549 | struct drm_device *dev = crtc->dev; | |
2550 | ||
2551 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF); | |
2552 | ||
2553 | if (crtc->fb) { | |
2554 | mutex_lock(&dev->struct_mutex); | |
2555 | i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj); | |
2556 | mutex_unlock(&dev->struct_mutex); | |
2557 | } | |
2558 | } | |
2559 | ||
7e7d76c3 JB |
2560 | /* Prepare for a mode set. |
2561 | * | |
2562 | * Note we could be a lot smarter here. We need to figure out which outputs | |
2563 | * will be enabled, which disabled (in short, how the config will changes) | |
2564 | * and perform the minimum necessary steps to accomplish that, e.g. updating | |
2565 | * watermarks, FBC configuration, making sure PLLs are programmed correctly, | |
2566 | * panel fitting is in the proper state, etc. | |
2567 | */ | |
2568 | static void i9xx_crtc_prepare(struct drm_crtc *crtc) | |
79e53945 | 2569 | { |
7e7d76c3 | 2570 | i9xx_crtc_disable(crtc); |
79e53945 JB |
2571 | } |
2572 | ||
7e7d76c3 | 2573 | static void i9xx_crtc_commit(struct drm_crtc *crtc) |
79e53945 | 2574 | { |
7e7d76c3 | 2575 | i9xx_crtc_enable(crtc); |
7e7d76c3 JB |
2576 | } |
2577 | ||
2578 | static void ironlake_crtc_prepare(struct drm_crtc *crtc) | |
2579 | { | |
7e7d76c3 | 2580 | ironlake_crtc_disable(crtc); |
7e7d76c3 JB |
2581 | } |
2582 | ||
2583 | static void ironlake_crtc_commit(struct drm_crtc *crtc) | |
2584 | { | |
7e7d76c3 | 2585 | ironlake_crtc_enable(crtc); |
79e53945 JB |
2586 | } |
2587 | ||
2588 | void intel_encoder_prepare (struct drm_encoder *encoder) | |
2589 | { | |
2590 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
2591 | /* lvds has its own version of prepare see intel_lvds_prepare */ | |
2592 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF); | |
2593 | } | |
2594 | ||
2595 | void intel_encoder_commit (struct drm_encoder *encoder) | |
2596 | { | |
2597 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
2598 | /* lvds has its own version of commit see intel_lvds_commit */ | |
2599 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); | |
2600 | } | |
2601 | ||
ea5b213a CW |
2602 | void intel_encoder_destroy(struct drm_encoder *encoder) |
2603 | { | |
4ef69c7a | 2604 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 2605 | |
ea5b213a CW |
2606 | drm_encoder_cleanup(encoder); |
2607 | kfree(intel_encoder); | |
2608 | } | |
2609 | ||
79e53945 JB |
2610 | static bool intel_crtc_mode_fixup(struct drm_crtc *crtc, |
2611 | struct drm_display_mode *mode, | |
2612 | struct drm_display_mode *adjusted_mode) | |
2613 | { | |
2c07245f | 2614 | struct drm_device *dev = crtc->dev; |
89749350 | 2615 | |
bad720ff | 2616 | if (HAS_PCH_SPLIT(dev)) { |
2c07245f | 2617 | /* FDI link clock is fixed at 2.7G */ |
2377b741 JB |
2618 | if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4) |
2619 | return false; | |
2c07245f | 2620 | } |
89749350 CW |
2621 | |
2622 | /* XXX some encoders set the crtcinfo, others don't. | |
2623 | * Obviously we need some form of conflict resolution here... | |
2624 | */ | |
2625 | if (adjusted_mode->crtc_htotal == 0) | |
2626 | drm_mode_set_crtcinfo(adjusted_mode, 0); | |
2627 | ||
79e53945 JB |
2628 | return true; |
2629 | } | |
2630 | ||
e70236a8 JB |
2631 | static int i945_get_display_clock_speed(struct drm_device *dev) |
2632 | { | |
2633 | return 400000; | |
2634 | } | |
79e53945 | 2635 | |
e70236a8 | 2636 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 2637 | { |
e70236a8 JB |
2638 | return 333000; |
2639 | } | |
79e53945 | 2640 | |
e70236a8 JB |
2641 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
2642 | { | |
2643 | return 200000; | |
2644 | } | |
79e53945 | 2645 | |
e70236a8 JB |
2646 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
2647 | { | |
2648 | u16 gcfgc = 0; | |
79e53945 | 2649 | |
e70236a8 JB |
2650 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
2651 | ||
2652 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
2653 | return 133000; | |
2654 | else { | |
2655 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
2656 | case GC_DISPLAY_CLOCK_333_MHZ: | |
2657 | return 333000; | |
2658 | default: | |
2659 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
2660 | return 190000; | |
79e53945 | 2661 | } |
e70236a8 JB |
2662 | } |
2663 | } | |
2664 | ||
2665 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
2666 | { | |
2667 | return 266000; | |
2668 | } | |
2669 | ||
2670 | static int i855_get_display_clock_speed(struct drm_device *dev) | |
2671 | { | |
2672 | u16 hpllcc = 0; | |
2673 | /* Assume that the hardware is in the high speed state. This | |
2674 | * should be the default. | |
2675 | */ | |
2676 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
2677 | case GC_CLOCK_133_200: | |
2678 | case GC_CLOCK_100_200: | |
2679 | return 200000; | |
2680 | case GC_CLOCK_166_250: | |
2681 | return 250000; | |
2682 | case GC_CLOCK_100_133: | |
79e53945 | 2683 | return 133000; |
e70236a8 | 2684 | } |
79e53945 | 2685 | |
e70236a8 JB |
2686 | /* Shouldn't happen */ |
2687 | return 0; | |
2688 | } | |
79e53945 | 2689 | |
e70236a8 JB |
2690 | static int i830_get_display_clock_speed(struct drm_device *dev) |
2691 | { | |
2692 | return 133000; | |
79e53945 JB |
2693 | } |
2694 | ||
2c07245f ZW |
2695 | struct fdi_m_n { |
2696 | u32 tu; | |
2697 | u32 gmch_m; | |
2698 | u32 gmch_n; | |
2699 | u32 link_m; | |
2700 | u32 link_n; | |
2701 | }; | |
2702 | ||
2703 | static void | |
2704 | fdi_reduce_ratio(u32 *num, u32 *den) | |
2705 | { | |
2706 | while (*num > 0xffffff || *den > 0xffffff) { | |
2707 | *num >>= 1; | |
2708 | *den >>= 1; | |
2709 | } | |
2710 | } | |
2711 | ||
2c07245f | 2712 | static void |
f2b115e6 AJ |
2713 | ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock, |
2714 | int link_clock, struct fdi_m_n *m_n) | |
2c07245f | 2715 | { |
2c07245f ZW |
2716 | m_n->tu = 64; /* default size */ |
2717 | ||
22ed1113 CW |
2718 | /* BUG_ON(pixel_clock > INT_MAX / 36); */ |
2719 | m_n->gmch_m = bits_per_pixel * pixel_clock; | |
2720 | m_n->gmch_n = link_clock * nlanes * 8; | |
2c07245f ZW |
2721 | fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); |
2722 | ||
22ed1113 CW |
2723 | m_n->link_m = pixel_clock; |
2724 | m_n->link_n = link_clock; | |
2c07245f ZW |
2725 | fdi_reduce_ratio(&m_n->link_m, &m_n->link_n); |
2726 | } | |
2727 | ||
2728 | ||
7662c8bd SL |
2729 | struct intel_watermark_params { |
2730 | unsigned long fifo_size; | |
2731 | unsigned long max_wm; | |
2732 | unsigned long default_wm; | |
2733 | unsigned long guard_size; | |
2734 | unsigned long cacheline_size; | |
2735 | }; | |
2736 | ||
f2b115e6 AJ |
2737 | /* Pineview has different values for various configs */ |
2738 | static struct intel_watermark_params pineview_display_wm = { | |
2739 | PINEVIEW_DISPLAY_FIFO, | |
2740 | PINEVIEW_MAX_WM, | |
2741 | PINEVIEW_DFT_WM, | |
2742 | PINEVIEW_GUARD_WM, | |
2743 | PINEVIEW_FIFO_LINE_SIZE | |
7662c8bd | 2744 | }; |
f2b115e6 AJ |
2745 | static struct intel_watermark_params pineview_display_hplloff_wm = { |
2746 | PINEVIEW_DISPLAY_FIFO, | |
2747 | PINEVIEW_MAX_WM, | |
2748 | PINEVIEW_DFT_HPLLOFF_WM, | |
2749 | PINEVIEW_GUARD_WM, | |
2750 | PINEVIEW_FIFO_LINE_SIZE | |
7662c8bd | 2751 | }; |
f2b115e6 AJ |
2752 | static struct intel_watermark_params pineview_cursor_wm = { |
2753 | PINEVIEW_CURSOR_FIFO, | |
2754 | PINEVIEW_CURSOR_MAX_WM, | |
2755 | PINEVIEW_CURSOR_DFT_WM, | |
2756 | PINEVIEW_CURSOR_GUARD_WM, | |
2757 | PINEVIEW_FIFO_LINE_SIZE, | |
7662c8bd | 2758 | }; |
f2b115e6 AJ |
2759 | static struct intel_watermark_params pineview_cursor_hplloff_wm = { |
2760 | PINEVIEW_CURSOR_FIFO, | |
2761 | PINEVIEW_CURSOR_MAX_WM, | |
2762 | PINEVIEW_CURSOR_DFT_WM, | |
2763 | PINEVIEW_CURSOR_GUARD_WM, | |
2764 | PINEVIEW_FIFO_LINE_SIZE | |
7662c8bd | 2765 | }; |
0e442c60 JB |
2766 | static struct intel_watermark_params g4x_wm_info = { |
2767 | G4X_FIFO_SIZE, | |
2768 | G4X_MAX_WM, | |
2769 | G4X_MAX_WM, | |
2770 | 2, | |
2771 | G4X_FIFO_LINE_SIZE, | |
2772 | }; | |
4fe5e611 ZY |
2773 | static struct intel_watermark_params g4x_cursor_wm_info = { |
2774 | I965_CURSOR_FIFO, | |
2775 | I965_CURSOR_MAX_WM, | |
2776 | I965_CURSOR_DFT_WM, | |
2777 | 2, | |
2778 | G4X_FIFO_LINE_SIZE, | |
2779 | }; | |
2780 | static struct intel_watermark_params i965_cursor_wm_info = { | |
2781 | I965_CURSOR_FIFO, | |
2782 | I965_CURSOR_MAX_WM, | |
2783 | I965_CURSOR_DFT_WM, | |
2784 | 2, | |
2785 | I915_FIFO_LINE_SIZE, | |
2786 | }; | |
7662c8bd | 2787 | static struct intel_watermark_params i945_wm_info = { |
dff33cfc | 2788 | I945_FIFO_SIZE, |
7662c8bd SL |
2789 | I915_MAX_WM, |
2790 | 1, | |
dff33cfc JB |
2791 | 2, |
2792 | I915_FIFO_LINE_SIZE | |
7662c8bd SL |
2793 | }; |
2794 | static struct intel_watermark_params i915_wm_info = { | |
dff33cfc | 2795 | I915_FIFO_SIZE, |
7662c8bd SL |
2796 | I915_MAX_WM, |
2797 | 1, | |
dff33cfc | 2798 | 2, |
7662c8bd SL |
2799 | I915_FIFO_LINE_SIZE |
2800 | }; | |
2801 | static struct intel_watermark_params i855_wm_info = { | |
2802 | I855GM_FIFO_SIZE, | |
2803 | I915_MAX_WM, | |
2804 | 1, | |
dff33cfc | 2805 | 2, |
7662c8bd SL |
2806 | I830_FIFO_LINE_SIZE |
2807 | }; | |
2808 | static struct intel_watermark_params i830_wm_info = { | |
2809 | I830_FIFO_SIZE, | |
2810 | I915_MAX_WM, | |
2811 | 1, | |
dff33cfc | 2812 | 2, |
7662c8bd SL |
2813 | I830_FIFO_LINE_SIZE |
2814 | }; | |
2815 | ||
7f8a8569 ZW |
2816 | static struct intel_watermark_params ironlake_display_wm_info = { |
2817 | ILK_DISPLAY_FIFO, | |
2818 | ILK_DISPLAY_MAXWM, | |
2819 | ILK_DISPLAY_DFTWM, | |
2820 | 2, | |
2821 | ILK_FIFO_LINE_SIZE | |
2822 | }; | |
2823 | ||
c936f44d ZY |
2824 | static struct intel_watermark_params ironlake_cursor_wm_info = { |
2825 | ILK_CURSOR_FIFO, | |
2826 | ILK_CURSOR_MAXWM, | |
2827 | ILK_CURSOR_DFTWM, | |
2828 | 2, | |
2829 | ILK_FIFO_LINE_SIZE | |
2830 | }; | |
2831 | ||
7f8a8569 ZW |
2832 | static struct intel_watermark_params ironlake_display_srwm_info = { |
2833 | ILK_DISPLAY_SR_FIFO, | |
2834 | ILK_DISPLAY_MAX_SRWM, | |
2835 | ILK_DISPLAY_DFT_SRWM, | |
2836 | 2, | |
2837 | ILK_FIFO_LINE_SIZE | |
2838 | }; | |
2839 | ||
2840 | static struct intel_watermark_params ironlake_cursor_srwm_info = { | |
2841 | ILK_CURSOR_SR_FIFO, | |
2842 | ILK_CURSOR_MAX_SRWM, | |
2843 | ILK_CURSOR_DFT_SRWM, | |
2844 | 2, | |
2845 | ILK_FIFO_LINE_SIZE | |
2846 | }; | |
2847 | ||
dff33cfc JB |
2848 | /** |
2849 | * intel_calculate_wm - calculate watermark level | |
2850 | * @clock_in_khz: pixel clock | |
2851 | * @wm: chip FIFO params | |
2852 | * @pixel_size: display pixel size | |
2853 | * @latency_ns: memory latency for the platform | |
2854 | * | |
2855 | * Calculate the watermark level (the level at which the display plane will | |
2856 | * start fetching from memory again). Each chip has a different display | |
2857 | * FIFO size and allocation, so the caller needs to figure that out and pass | |
2858 | * in the correct intel_watermark_params structure. | |
2859 | * | |
2860 | * As the pixel clock runs, the FIFO will be drained at a rate that depends | |
2861 | * on the pixel size. When it reaches the watermark level, it'll start | |
2862 | * fetching FIFO line sized based chunks from memory until the FIFO fills | |
2863 | * past the watermark point. If the FIFO drains completely, a FIFO underrun | |
2864 | * will occur, and a display engine hang could result. | |
2865 | */ | |
7662c8bd SL |
2866 | static unsigned long intel_calculate_wm(unsigned long clock_in_khz, |
2867 | struct intel_watermark_params *wm, | |
2868 | int pixel_size, | |
2869 | unsigned long latency_ns) | |
2870 | { | |
390c4dd4 | 2871 | long entries_required, wm_size; |
dff33cfc | 2872 | |
d660467c JB |
2873 | /* |
2874 | * Note: we need to make sure we don't overflow for various clock & | |
2875 | * latency values. | |
2876 | * clocks go from a few thousand to several hundred thousand. | |
2877 | * latency is usually a few thousand | |
2878 | */ | |
2879 | entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) / | |
2880 | 1000; | |
8de9b311 | 2881 | entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size); |
7662c8bd | 2882 | |
28c97730 | 2883 | DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required); |
dff33cfc JB |
2884 | |
2885 | wm_size = wm->fifo_size - (entries_required + wm->guard_size); | |
2886 | ||
28c97730 | 2887 | DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size); |
7662c8bd | 2888 | |
390c4dd4 JB |
2889 | /* Don't promote wm_size to unsigned... */ |
2890 | if (wm_size > (long)wm->max_wm) | |
7662c8bd | 2891 | wm_size = wm->max_wm; |
c3add4b6 | 2892 | if (wm_size <= 0) |
7662c8bd SL |
2893 | wm_size = wm->default_wm; |
2894 | return wm_size; | |
2895 | } | |
2896 | ||
2897 | struct cxsr_latency { | |
2898 | int is_desktop; | |
95534263 | 2899 | int is_ddr3; |
7662c8bd SL |
2900 | unsigned long fsb_freq; |
2901 | unsigned long mem_freq; | |
2902 | unsigned long display_sr; | |
2903 | unsigned long display_hpll_disable; | |
2904 | unsigned long cursor_sr; | |
2905 | unsigned long cursor_hpll_disable; | |
2906 | }; | |
2907 | ||
403c89ff | 2908 | static const struct cxsr_latency cxsr_latency_table[] = { |
95534263 LP |
2909 | {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */ |
2910 | {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */ | |
2911 | {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */ | |
2912 | {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */ | |
2913 | {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */ | |
2914 | ||
2915 | {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */ | |
2916 | {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */ | |
2917 | {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */ | |
2918 | {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */ | |
2919 | {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */ | |
2920 | ||
2921 | {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */ | |
2922 | {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */ | |
2923 | {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */ | |
2924 | {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */ | |
2925 | {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */ | |
2926 | ||
2927 | {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */ | |
2928 | {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */ | |
2929 | {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */ | |
2930 | {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */ | |
2931 | {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */ | |
2932 | ||
2933 | {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */ | |
2934 | {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */ | |
2935 | {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */ | |
2936 | {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */ | |
2937 | {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */ | |
2938 | ||
2939 | {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */ | |
2940 | {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */ | |
2941 | {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */ | |
2942 | {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */ | |
2943 | {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */ | |
7662c8bd SL |
2944 | }; |
2945 | ||
403c89ff CW |
2946 | static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, |
2947 | int is_ddr3, | |
2948 | int fsb, | |
2949 | int mem) | |
7662c8bd | 2950 | { |
403c89ff | 2951 | const struct cxsr_latency *latency; |
7662c8bd | 2952 | int i; |
7662c8bd SL |
2953 | |
2954 | if (fsb == 0 || mem == 0) | |
2955 | return NULL; | |
2956 | ||
2957 | for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) { | |
2958 | latency = &cxsr_latency_table[i]; | |
2959 | if (is_desktop == latency->is_desktop && | |
95534263 | 2960 | is_ddr3 == latency->is_ddr3 && |
decbbcda JSR |
2961 | fsb == latency->fsb_freq && mem == latency->mem_freq) |
2962 | return latency; | |
7662c8bd | 2963 | } |
decbbcda | 2964 | |
28c97730 | 2965 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); |
decbbcda JSR |
2966 | |
2967 | return NULL; | |
7662c8bd SL |
2968 | } |
2969 | ||
f2b115e6 | 2970 | static void pineview_disable_cxsr(struct drm_device *dev) |
7662c8bd SL |
2971 | { |
2972 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7662c8bd SL |
2973 | |
2974 | /* deactivate cxsr */ | |
3e33d94d | 2975 | I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN); |
7662c8bd SL |
2976 | } |
2977 | ||
bcc24fb4 JB |
2978 | /* |
2979 | * Latency for FIFO fetches is dependent on several factors: | |
2980 | * - memory configuration (speed, channels) | |
2981 | * - chipset | |
2982 | * - current MCH state | |
2983 | * It can be fairly high in some situations, so here we assume a fairly | |
2984 | * pessimal value. It's a tradeoff between extra memory fetches (if we | |
2985 | * set this value too high, the FIFO will fetch frequently to stay full) | |
2986 | * and power consumption (set it too low to save power and we might see | |
2987 | * FIFO underruns and display "flicker"). | |
2988 | * | |
2989 | * A value of 5us seems to be a good balance; safe for very low end | |
2990 | * platforms but not overly aggressive on lower latency configs. | |
2991 | */ | |
69e302a9 | 2992 | static const int latency_ns = 5000; |
7662c8bd | 2993 | |
e70236a8 | 2994 | static int i9xx_get_fifo_size(struct drm_device *dev, int plane) |
dff33cfc JB |
2995 | { |
2996 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2997 | uint32_t dsparb = I915_READ(DSPARB); | |
2998 | int size; | |
2999 | ||
8de9b311 CW |
3000 | size = dsparb & 0x7f; |
3001 | if (plane) | |
3002 | size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size; | |
dff33cfc | 3003 | |
28c97730 | 3004 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
5eddb70b | 3005 | plane ? "B" : "A", size); |
dff33cfc JB |
3006 | |
3007 | return size; | |
3008 | } | |
7662c8bd | 3009 | |
e70236a8 JB |
3010 | static int i85x_get_fifo_size(struct drm_device *dev, int plane) |
3011 | { | |
3012 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3013 | uint32_t dsparb = I915_READ(DSPARB); | |
3014 | int size; | |
3015 | ||
8de9b311 CW |
3016 | size = dsparb & 0x1ff; |
3017 | if (plane) | |
3018 | size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size; | |
e70236a8 | 3019 | size >>= 1; /* Convert to cachelines */ |
dff33cfc | 3020 | |
28c97730 | 3021 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
5eddb70b | 3022 | plane ? "B" : "A", size); |
dff33cfc JB |
3023 | |
3024 | return size; | |
3025 | } | |
7662c8bd | 3026 | |
e70236a8 JB |
3027 | static int i845_get_fifo_size(struct drm_device *dev, int plane) |
3028 | { | |
3029 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3030 | uint32_t dsparb = I915_READ(DSPARB); | |
3031 | int size; | |
3032 | ||
3033 | size = dsparb & 0x7f; | |
3034 | size >>= 2; /* Convert to cachelines */ | |
3035 | ||
28c97730 | 3036 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
5eddb70b CW |
3037 | plane ? "B" : "A", |
3038 | size); | |
e70236a8 JB |
3039 | |
3040 | return size; | |
3041 | } | |
3042 | ||
3043 | static int i830_get_fifo_size(struct drm_device *dev, int plane) | |
3044 | { | |
3045 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3046 | uint32_t dsparb = I915_READ(DSPARB); | |
3047 | int size; | |
3048 | ||
3049 | size = dsparb & 0x7f; | |
3050 | size >>= 1; /* Convert to cachelines */ | |
3051 | ||
28c97730 | 3052 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
5eddb70b | 3053 | plane ? "B" : "A", size); |
e70236a8 JB |
3054 | |
3055 | return size; | |
3056 | } | |
3057 | ||
d4294342 | 3058 | static void pineview_update_wm(struct drm_device *dev, int planea_clock, |
5eddb70b CW |
3059 | int planeb_clock, int sr_hdisplay, int unused, |
3060 | int pixel_size) | |
d4294342 ZY |
3061 | { |
3062 | struct drm_i915_private *dev_priv = dev->dev_private; | |
403c89ff | 3063 | const struct cxsr_latency *latency; |
d4294342 ZY |
3064 | u32 reg; |
3065 | unsigned long wm; | |
d4294342 ZY |
3066 | int sr_clock; |
3067 | ||
403c89ff | 3068 | latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3, |
95534263 | 3069 | dev_priv->fsb_freq, dev_priv->mem_freq); |
d4294342 ZY |
3070 | if (!latency) { |
3071 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); | |
3072 | pineview_disable_cxsr(dev); | |
3073 | return; | |
3074 | } | |
3075 | ||
3076 | if (!planea_clock || !planeb_clock) { | |
3077 | sr_clock = planea_clock ? planea_clock : planeb_clock; | |
3078 | ||
3079 | /* Display SR */ | |
3080 | wm = intel_calculate_wm(sr_clock, &pineview_display_wm, | |
3081 | pixel_size, latency->display_sr); | |
3082 | reg = I915_READ(DSPFW1); | |
3083 | reg &= ~DSPFW_SR_MASK; | |
3084 | reg |= wm << DSPFW_SR_SHIFT; | |
3085 | I915_WRITE(DSPFW1, reg); | |
3086 | DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg); | |
3087 | ||
3088 | /* cursor SR */ | |
3089 | wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm, | |
3090 | pixel_size, latency->cursor_sr); | |
3091 | reg = I915_READ(DSPFW3); | |
3092 | reg &= ~DSPFW_CURSOR_SR_MASK; | |
3093 | reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT; | |
3094 | I915_WRITE(DSPFW3, reg); | |
3095 | ||
3096 | /* Display HPLL off SR */ | |
3097 | wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm, | |
3098 | pixel_size, latency->display_hpll_disable); | |
3099 | reg = I915_READ(DSPFW3); | |
3100 | reg &= ~DSPFW_HPLL_SR_MASK; | |
3101 | reg |= wm & DSPFW_HPLL_SR_MASK; | |
3102 | I915_WRITE(DSPFW3, reg); | |
3103 | ||
3104 | /* cursor HPLL off SR */ | |
3105 | wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm, | |
3106 | pixel_size, latency->cursor_hpll_disable); | |
3107 | reg = I915_READ(DSPFW3); | |
3108 | reg &= ~DSPFW_HPLL_CURSOR_MASK; | |
3109 | reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT; | |
3110 | I915_WRITE(DSPFW3, reg); | |
3111 | DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg); | |
3112 | ||
3113 | /* activate cxsr */ | |
3e33d94d CW |
3114 | I915_WRITE(DSPFW3, |
3115 | I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN); | |
d4294342 ZY |
3116 | DRM_DEBUG_KMS("Self-refresh is enabled\n"); |
3117 | } else { | |
3118 | pineview_disable_cxsr(dev); | |
3119 | DRM_DEBUG_KMS("Self-refresh is disabled\n"); | |
3120 | } | |
3121 | } | |
3122 | ||
0e442c60 | 3123 | static void g4x_update_wm(struct drm_device *dev, int planea_clock, |
fa143215 ZY |
3124 | int planeb_clock, int sr_hdisplay, int sr_htotal, |
3125 | int pixel_size) | |
652c393a JB |
3126 | { |
3127 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0e442c60 JB |
3128 | int total_size, cacheline_size; |
3129 | int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr; | |
3130 | struct intel_watermark_params planea_params, planeb_params; | |
3131 | unsigned long line_time_us; | |
3132 | int sr_clock, sr_entries = 0, entries_required; | |
652c393a | 3133 | |
0e442c60 JB |
3134 | /* Create copies of the base settings for each pipe */ |
3135 | planea_params = planeb_params = g4x_wm_info; | |
3136 | ||
3137 | /* Grab a couple of global values before we overwrite them */ | |
3138 | total_size = planea_params.fifo_size; | |
3139 | cacheline_size = planea_params.cacheline_size; | |
3140 | ||
3141 | /* | |
3142 | * Note: we need to make sure we don't overflow for various clock & | |
3143 | * latency values. | |
3144 | * clocks go from a few thousand to several hundred thousand. | |
3145 | * latency is usually a few thousand | |
3146 | */ | |
3147 | entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) / | |
3148 | 1000; | |
8de9b311 | 3149 | entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE); |
0e442c60 JB |
3150 | planea_wm = entries_required + planea_params.guard_size; |
3151 | ||
3152 | entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) / | |
3153 | 1000; | |
8de9b311 | 3154 | entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE); |
0e442c60 JB |
3155 | planeb_wm = entries_required + planeb_params.guard_size; |
3156 | ||
3157 | cursora_wm = cursorb_wm = 16; | |
3158 | cursor_sr = 32; | |
3159 | ||
3160 | DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); | |
3161 | ||
3162 | /* Calc sr entries for one plane configs */ | |
3163 | if (sr_hdisplay && (!planea_clock || !planeb_clock)) { | |
3164 | /* self-refresh has much higher latency */ | |
69e302a9 | 3165 | static const int sr_latency_ns = 12000; |
0e442c60 JB |
3166 | |
3167 | sr_clock = planea_clock ? planea_clock : planeb_clock; | |
fa143215 | 3168 | line_time_us = ((sr_htotal * 1000) / sr_clock); |
0e442c60 JB |
3169 | |
3170 | /* Use ns/us then divide to preserve precision */ | |
fa143215 | 3171 | sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
5eddb70b | 3172 | pixel_size * sr_hdisplay; |
8de9b311 | 3173 | sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size); |
4fe5e611 ZY |
3174 | |
3175 | entries_required = (((sr_latency_ns / line_time_us) + | |
3176 | 1000) / 1000) * pixel_size * 64; | |
8de9b311 | 3177 | entries_required = DIV_ROUND_UP(entries_required, |
5eddb70b | 3178 | g4x_cursor_wm_info.cacheline_size); |
4fe5e611 ZY |
3179 | cursor_sr = entries_required + g4x_cursor_wm_info.guard_size; |
3180 | ||
3181 | if (cursor_sr > g4x_cursor_wm_info.max_wm) | |
3182 | cursor_sr = g4x_cursor_wm_info.max_wm; | |
3183 | DRM_DEBUG_KMS("self-refresh watermark: display plane %d " | |
3184 | "cursor %d\n", sr_entries, cursor_sr); | |
3185 | ||
0e442c60 | 3186 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); |
33c5fd12 DJ |
3187 | } else { |
3188 | /* Turn off self refresh if both pipes are enabled */ | |
3189 | I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) | |
5eddb70b | 3190 | & ~FW_BLC_SELF_EN); |
0e442c60 JB |
3191 | } |
3192 | ||
3193 | DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n", | |
3194 | planea_wm, planeb_wm, sr_entries); | |
3195 | ||
3196 | planea_wm &= 0x3f; | |
3197 | planeb_wm &= 0x3f; | |
3198 | ||
3199 | I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) | | |
3200 | (cursorb_wm << DSPFW_CURSORB_SHIFT) | | |
3201 | (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm); | |
3202 | I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) | | |
3203 | (cursora_wm << DSPFW_CURSORA_SHIFT)); | |
3204 | /* HPLL off in SR has some issues on G4x... disable it */ | |
3205 | I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) | | |
3206 | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); | |
652c393a JB |
3207 | } |
3208 | ||
1dc7546d | 3209 | static void i965_update_wm(struct drm_device *dev, int planea_clock, |
fa143215 ZY |
3210 | int planeb_clock, int sr_hdisplay, int sr_htotal, |
3211 | int pixel_size) | |
7662c8bd SL |
3212 | { |
3213 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1dc7546d JB |
3214 | unsigned long line_time_us; |
3215 | int sr_clock, sr_entries, srwm = 1; | |
4fe5e611 | 3216 | int cursor_sr = 16; |
1dc7546d JB |
3217 | |
3218 | /* Calc sr entries for one plane configs */ | |
3219 | if (sr_hdisplay && (!planea_clock || !planeb_clock)) { | |
3220 | /* self-refresh has much higher latency */ | |
69e302a9 | 3221 | static const int sr_latency_ns = 12000; |
1dc7546d JB |
3222 | |
3223 | sr_clock = planea_clock ? planea_clock : planeb_clock; | |
fa143215 | 3224 | line_time_us = ((sr_htotal * 1000) / sr_clock); |
1dc7546d JB |
3225 | |
3226 | /* Use ns/us then divide to preserve precision */ | |
fa143215 | 3227 | sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
5eddb70b | 3228 | pixel_size * sr_hdisplay; |
8de9b311 | 3229 | sr_entries = DIV_ROUND_UP(sr_entries, I915_FIFO_LINE_SIZE); |
1dc7546d | 3230 | DRM_DEBUG("self-refresh entries: %d\n", sr_entries); |
1b07e04e | 3231 | srwm = I965_FIFO_SIZE - sr_entries; |
1dc7546d JB |
3232 | if (srwm < 0) |
3233 | srwm = 1; | |
1b07e04e | 3234 | srwm &= 0x1ff; |
4fe5e611 ZY |
3235 | |
3236 | sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * | |
5eddb70b | 3237 | pixel_size * 64; |
8de9b311 CW |
3238 | sr_entries = DIV_ROUND_UP(sr_entries, |
3239 | i965_cursor_wm_info.cacheline_size); | |
4fe5e611 | 3240 | cursor_sr = i965_cursor_wm_info.fifo_size - |
5eddb70b | 3241 | (sr_entries + i965_cursor_wm_info.guard_size); |
4fe5e611 ZY |
3242 | |
3243 | if (cursor_sr > i965_cursor_wm_info.max_wm) | |
3244 | cursor_sr = i965_cursor_wm_info.max_wm; | |
3245 | ||
3246 | DRM_DEBUG_KMS("self-refresh watermark: display plane %d " | |
3247 | "cursor %d\n", srwm, cursor_sr); | |
3248 | ||
a6c45cf0 | 3249 | if (IS_CRESTLINE(dev)) |
adcdbc66 | 3250 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); |
33c5fd12 DJ |
3251 | } else { |
3252 | /* Turn off self refresh if both pipes are enabled */ | |
a6c45cf0 | 3253 | if (IS_CRESTLINE(dev)) |
adcdbc66 JB |
3254 | I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) |
3255 | & ~FW_BLC_SELF_EN); | |
1dc7546d | 3256 | } |
7662c8bd | 3257 | |
1dc7546d JB |
3258 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", |
3259 | srwm); | |
7662c8bd SL |
3260 | |
3261 | /* 965 has limitations... */ | |
1dc7546d JB |
3262 | I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) | |
3263 | (8 << 0)); | |
7662c8bd | 3264 | I915_WRITE(DSPFW2, (8 << 8) | (8 << 0)); |
4fe5e611 ZY |
3265 | /* update cursor SR watermark */ |
3266 | I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); | |
7662c8bd SL |
3267 | } |
3268 | ||
3269 | static void i9xx_update_wm(struct drm_device *dev, int planea_clock, | |
fa143215 ZY |
3270 | int planeb_clock, int sr_hdisplay, int sr_htotal, |
3271 | int pixel_size) | |
7662c8bd SL |
3272 | { |
3273 | struct drm_i915_private *dev_priv = dev->dev_private; | |
dff33cfc JB |
3274 | uint32_t fwater_lo; |
3275 | uint32_t fwater_hi; | |
3276 | int total_size, cacheline_size, cwm, srwm = 1; | |
3277 | int planea_wm, planeb_wm; | |
3278 | struct intel_watermark_params planea_params, planeb_params; | |
7662c8bd SL |
3279 | unsigned long line_time_us; |
3280 | int sr_clock, sr_entries = 0; | |
3281 | ||
dff33cfc | 3282 | /* Create copies of the base settings for each pipe */ |
a6c45cf0 | 3283 | if (IS_CRESTLINE(dev) || IS_I945GM(dev)) |
dff33cfc | 3284 | planea_params = planeb_params = i945_wm_info; |
a6c45cf0 | 3285 | else if (!IS_GEN2(dev)) |
dff33cfc | 3286 | planea_params = planeb_params = i915_wm_info; |
7662c8bd | 3287 | else |
dff33cfc | 3288 | planea_params = planeb_params = i855_wm_info; |
7662c8bd | 3289 | |
dff33cfc JB |
3290 | /* Grab a couple of global values before we overwrite them */ |
3291 | total_size = planea_params.fifo_size; | |
3292 | cacheline_size = planea_params.cacheline_size; | |
7662c8bd | 3293 | |
dff33cfc | 3294 | /* Update per-plane FIFO sizes */ |
e70236a8 JB |
3295 | planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0); |
3296 | planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1); | |
7662c8bd | 3297 | |
dff33cfc JB |
3298 | planea_wm = intel_calculate_wm(planea_clock, &planea_params, |
3299 | pixel_size, latency_ns); | |
3300 | planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params, | |
3301 | pixel_size, latency_ns); | |
28c97730 | 3302 | DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); |
7662c8bd SL |
3303 | |
3304 | /* | |
3305 | * Overlay gets an aggressive default since video jitter is bad. | |
3306 | */ | |
3307 | cwm = 2; | |
3308 | ||
dff33cfc | 3309 | /* Calc sr entries for one plane configs */ |
652c393a JB |
3310 | if (HAS_FW_BLC(dev) && sr_hdisplay && |
3311 | (!planea_clock || !planeb_clock)) { | |
dff33cfc | 3312 | /* self-refresh has much higher latency */ |
69e302a9 | 3313 | static const int sr_latency_ns = 6000; |
dff33cfc | 3314 | |
7662c8bd | 3315 | sr_clock = planea_clock ? planea_clock : planeb_clock; |
fa143215 | 3316 | line_time_us = ((sr_htotal * 1000) / sr_clock); |
dff33cfc JB |
3317 | |
3318 | /* Use ns/us then divide to preserve precision */ | |
fa143215 | 3319 | sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
5eddb70b | 3320 | pixel_size * sr_hdisplay; |
8de9b311 | 3321 | sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size); |
28c97730 | 3322 | DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries); |
dff33cfc JB |
3323 | srwm = total_size - sr_entries; |
3324 | if (srwm < 0) | |
3325 | srwm = 1; | |
ee980b80 LP |
3326 | |
3327 | if (IS_I945G(dev) || IS_I945GM(dev)) | |
3328 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff)); | |
3329 | else if (IS_I915GM(dev)) { | |
3330 | /* 915M has a smaller SRWM field */ | |
3331 | I915_WRITE(FW_BLC_SELF, srwm & 0x3f); | |
3332 | I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN); | |
3333 | } | |
33c5fd12 DJ |
3334 | } else { |
3335 | /* Turn off self refresh if both pipes are enabled */ | |
ee980b80 LP |
3336 | if (IS_I945G(dev) || IS_I945GM(dev)) { |
3337 | I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) | |
3338 | & ~FW_BLC_SELF_EN); | |
3339 | } else if (IS_I915GM(dev)) { | |
3340 | I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN); | |
3341 | } | |
7662c8bd SL |
3342 | } |
3343 | ||
28c97730 | 3344 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", |
5eddb70b | 3345 | planea_wm, planeb_wm, cwm, srwm); |
7662c8bd | 3346 | |
dff33cfc JB |
3347 | fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f); |
3348 | fwater_hi = (cwm & 0x1f); | |
3349 | ||
3350 | /* Set request length to 8 cachelines per fetch */ | |
3351 | fwater_lo = fwater_lo | (1 << 24) | (1 << 8); | |
3352 | fwater_hi = fwater_hi | (1 << 8); | |
7662c8bd SL |
3353 | |
3354 | I915_WRITE(FW_BLC, fwater_lo); | |
3355 | I915_WRITE(FW_BLC2, fwater_hi); | |
7662c8bd SL |
3356 | } |
3357 | ||
e70236a8 | 3358 | static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused, |
fa143215 | 3359 | int unused2, int unused3, int pixel_size) |
7662c8bd SL |
3360 | { |
3361 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f3601326 | 3362 | uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff; |
dff33cfc | 3363 | int planea_wm; |
7662c8bd | 3364 | |
e70236a8 | 3365 | i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0); |
7662c8bd | 3366 | |
dff33cfc JB |
3367 | planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info, |
3368 | pixel_size, latency_ns); | |
f3601326 JB |
3369 | fwater_lo |= (3<<8) | planea_wm; |
3370 | ||
28c97730 | 3371 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm); |
7662c8bd SL |
3372 | |
3373 | I915_WRITE(FW_BLC, fwater_lo); | |
3374 | } | |
3375 | ||
7f8a8569 | 3376 | #define ILK_LP0_PLANE_LATENCY 700 |
c936f44d | 3377 | #define ILK_LP0_CURSOR_LATENCY 1300 |
7f8a8569 | 3378 | |
4ed765f9 CW |
3379 | static bool ironlake_compute_wm0(struct drm_device *dev, |
3380 | int pipe, | |
3381 | int *plane_wm, | |
3382 | int *cursor_wm) | |
7f8a8569 | 3383 | { |
c936f44d | 3384 | struct drm_crtc *crtc; |
4ed765f9 CW |
3385 | int htotal, hdisplay, clock, pixel_size = 0; |
3386 | int line_time_us, line_count, entries; | |
c936f44d | 3387 | |
4ed765f9 CW |
3388 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
3389 | if (crtc->fb == NULL || !crtc->enabled) | |
3390 | return false; | |
7f8a8569 | 3391 | |
4ed765f9 CW |
3392 | htotal = crtc->mode.htotal; |
3393 | hdisplay = crtc->mode.hdisplay; | |
3394 | clock = crtc->mode.clock; | |
3395 | pixel_size = crtc->fb->bits_per_pixel / 8; | |
3396 | ||
3397 | /* Use the small buffer method to calculate plane watermark */ | |
3398 | entries = ((clock * pixel_size / 1000) * ILK_LP0_PLANE_LATENCY) / 1000; | |
3399 | entries = DIV_ROUND_UP(entries, | |
3400 | ironlake_display_wm_info.cacheline_size); | |
3401 | *plane_wm = entries + ironlake_display_wm_info.guard_size; | |
3402 | if (*plane_wm > (int)ironlake_display_wm_info.max_wm) | |
3403 | *plane_wm = ironlake_display_wm_info.max_wm; | |
3404 | ||
3405 | /* Use the large buffer method to calculate cursor watermark */ | |
3406 | line_time_us = ((htotal * 1000) / clock); | |
3407 | line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000; | |
3408 | entries = line_count * 64 * pixel_size; | |
3409 | entries = DIV_ROUND_UP(entries, | |
3410 | ironlake_cursor_wm_info.cacheline_size); | |
3411 | *cursor_wm = entries + ironlake_cursor_wm_info.guard_size; | |
3412 | if (*cursor_wm > ironlake_cursor_wm_info.max_wm) | |
3413 | *cursor_wm = ironlake_cursor_wm_info.max_wm; | |
7f8a8569 | 3414 | |
4ed765f9 CW |
3415 | return true; |
3416 | } | |
c936f44d | 3417 | |
4ed765f9 CW |
3418 | static void ironlake_update_wm(struct drm_device *dev, |
3419 | int planea_clock, int planeb_clock, | |
3420 | int sr_hdisplay, int sr_htotal, | |
3421 | int pixel_size) | |
3422 | { | |
3423 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3424 | int plane_wm, cursor_wm, enabled; | |
3425 | int tmp; | |
c936f44d | 3426 | |
4ed765f9 CW |
3427 | enabled = 0; |
3428 | if (ironlake_compute_wm0(dev, 0, &plane_wm, &cursor_wm)) { | |
3429 | I915_WRITE(WM0_PIPEA_ILK, | |
3430 | (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); | |
3431 | DRM_DEBUG_KMS("FIFO watermarks For pipe A -" | |
3432 | " plane %d, " "cursor: %d\n", | |
3433 | plane_wm, cursor_wm); | |
3434 | enabled++; | |
3435 | } | |
c936f44d | 3436 | |
4ed765f9 CW |
3437 | if (ironlake_compute_wm0(dev, 1, &plane_wm, &cursor_wm)) { |
3438 | I915_WRITE(WM0_PIPEB_ILK, | |
3439 | (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); | |
3440 | DRM_DEBUG_KMS("FIFO watermarks For pipe B -" | |
3441 | " plane %d, cursor: %d\n", | |
3442 | plane_wm, cursor_wm); | |
3443 | enabled++; | |
7f8a8569 ZW |
3444 | } |
3445 | ||
3446 | /* | |
3447 | * Calculate and update the self-refresh watermark only when one | |
3448 | * display plane is used. | |
3449 | */ | |
4ed765f9 | 3450 | tmp = 0; |
f7746f0e | 3451 | if (enabled == 1) { |
4ed765f9 CW |
3452 | unsigned long line_time_us; |
3453 | int small, large, plane_fbc; | |
3454 | int sr_clock, entries; | |
3455 | int line_count, line_size; | |
7f8a8569 ZW |
3456 | /* Read the self-refresh latency. The unit is 0.5us */ |
3457 | int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK; | |
3458 | ||
3459 | sr_clock = planea_clock ? planea_clock : planeb_clock; | |
4ed765f9 | 3460 | line_time_us = (sr_htotal * 1000) / sr_clock; |
7f8a8569 ZW |
3461 | |
3462 | /* Use ns/us then divide to preserve precision */ | |
3463 | line_count = ((ilk_sr_latency * 500) / line_time_us + 1000) | |
5eddb70b | 3464 | / 1000; |
4ed765f9 | 3465 | line_size = sr_hdisplay * pixel_size; |
7f8a8569 | 3466 | |
4ed765f9 CW |
3467 | /* Use the minimum of the small and large buffer method for primary */ |
3468 | small = ((sr_clock * pixel_size / 1000) * (ilk_sr_latency * 500)) / 1000; | |
3469 | large = line_count * line_size; | |
7f8a8569 | 3470 | |
4ed765f9 CW |
3471 | entries = DIV_ROUND_UP(min(small, large), |
3472 | ironlake_display_srwm_info.cacheline_size); | |
7f8a8569 | 3473 | |
4ed765f9 CW |
3474 | plane_fbc = entries * 64; |
3475 | plane_fbc = DIV_ROUND_UP(plane_fbc, line_size); | |
7f8a8569 | 3476 | |
4ed765f9 CW |
3477 | plane_wm = entries + ironlake_display_srwm_info.guard_size; |
3478 | if (plane_wm > (int)ironlake_display_srwm_info.max_wm) | |
3479 | plane_wm = ironlake_display_srwm_info.max_wm; | |
7f8a8569 | 3480 | |
4ed765f9 CW |
3481 | /* calculate the self-refresh watermark for display cursor */ |
3482 | entries = line_count * pixel_size * 64; | |
3483 | entries = DIV_ROUND_UP(entries, | |
3484 | ironlake_cursor_srwm_info.cacheline_size); | |
3485 | ||
3486 | cursor_wm = entries + ironlake_cursor_srwm_info.guard_size; | |
3487 | if (cursor_wm > (int)ironlake_cursor_srwm_info.max_wm) | |
3488 | cursor_wm = ironlake_cursor_srwm_info.max_wm; | |
3489 | ||
3490 | /* configure watermark and enable self-refresh */ | |
3491 | tmp = (WM1_LP_SR_EN | | |
3492 | (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) | | |
3493 | (plane_fbc << WM1_LP_FBC_SHIFT) | | |
3494 | (plane_wm << WM1_LP_SR_SHIFT) | | |
3495 | cursor_wm); | |
3496 | DRM_DEBUG_KMS("self-refresh watermark: display plane %d, fbc lines %d," | |
3497 | " cursor %d\n", plane_wm, plane_fbc, cursor_wm); | |
7f8a8569 | 3498 | } |
4ed765f9 CW |
3499 | I915_WRITE(WM1_LP_ILK, tmp); |
3500 | /* XXX setup WM2 and WM3 */ | |
7f8a8569 | 3501 | } |
4ed765f9 | 3502 | |
7662c8bd SL |
3503 | /** |
3504 | * intel_update_watermarks - update FIFO watermark values based on current modes | |
3505 | * | |
3506 | * Calculate watermark values for the various WM regs based on current mode | |
3507 | * and plane configuration. | |
3508 | * | |
3509 | * There are several cases to deal with here: | |
3510 | * - normal (i.e. non-self-refresh) | |
3511 | * - self-refresh (SR) mode | |
3512 | * - lines are large relative to FIFO size (buffer can hold up to 2) | |
3513 | * - lines are small relative to FIFO size (buffer can hold more than 2 | |
3514 | * lines), so need to account for TLB latency | |
3515 | * | |
3516 | * The normal calculation is: | |
3517 | * watermark = dotclock * bytes per pixel * latency | |
3518 | * where latency is platform & configuration dependent (we assume pessimal | |
3519 | * values here). | |
3520 | * | |
3521 | * The SR calculation is: | |
3522 | * watermark = (trunc(latency/line time)+1) * surface width * | |
3523 | * bytes per pixel | |
3524 | * where | |
3525 | * line time = htotal / dotclock | |
fa143215 | 3526 | * surface width = hdisplay for normal plane and 64 for cursor |
7662c8bd SL |
3527 | * and latency is assumed to be high, as above. |
3528 | * | |
3529 | * The final value programmed to the register should always be rounded up, | |
3530 | * and include an extra 2 entries to account for clock crossings. | |
3531 | * | |
3532 | * We don't use the sprite, so we can ignore that. And on Crestline we have | |
3533 | * to set the non-SR watermarks to 8. | |
5eddb70b | 3534 | */ |
7662c8bd SL |
3535 | static void intel_update_watermarks(struct drm_device *dev) |
3536 | { | |
e70236a8 | 3537 | struct drm_i915_private *dev_priv = dev->dev_private; |
7662c8bd | 3538 | struct drm_crtc *crtc; |
7662c8bd SL |
3539 | int sr_hdisplay = 0; |
3540 | unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0; | |
3541 | int enabled = 0, pixel_size = 0; | |
fa143215 | 3542 | int sr_htotal = 0; |
7662c8bd | 3543 | |
c03342fa ZW |
3544 | if (!dev_priv->display.update_wm) |
3545 | return; | |
3546 | ||
7662c8bd SL |
3547 | /* Get the clock config from both planes */ |
3548 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
debcaddc | 3549 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
f7abfe8b | 3550 | if (intel_crtc->active) { |
7662c8bd SL |
3551 | enabled++; |
3552 | if (intel_crtc->plane == 0) { | |
28c97730 | 3553 | DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n", |
5eddb70b | 3554 | intel_crtc->pipe, crtc->mode.clock); |
7662c8bd SL |
3555 | planea_clock = crtc->mode.clock; |
3556 | } else { | |
28c97730 | 3557 | DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n", |
5eddb70b | 3558 | intel_crtc->pipe, crtc->mode.clock); |
7662c8bd SL |
3559 | planeb_clock = crtc->mode.clock; |
3560 | } | |
3561 | sr_hdisplay = crtc->mode.hdisplay; | |
3562 | sr_clock = crtc->mode.clock; | |
fa143215 | 3563 | sr_htotal = crtc->mode.htotal; |
7662c8bd SL |
3564 | if (crtc->fb) |
3565 | pixel_size = crtc->fb->bits_per_pixel / 8; | |
3566 | else | |
3567 | pixel_size = 4; /* by default */ | |
3568 | } | |
3569 | } | |
3570 | ||
3571 | if (enabled <= 0) | |
3572 | return; | |
3573 | ||
e70236a8 | 3574 | dev_priv->display.update_wm(dev, planea_clock, planeb_clock, |
fa143215 | 3575 | sr_hdisplay, sr_htotal, pixel_size); |
7662c8bd SL |
3576 | } |
3577 | ||
5c3b82e2 CW |
3578 | static int intel_crtc_mode_set(struct drm_crtc *crtc, |
3579 | struct drm_display_mode *mode, | |
3580 | struct drm_display_mode *adjusted_mode, | |
3581 | int x, int y, | |
3582 | struct drm_framebuffer *old_fb) | |
79e53945 JB |
3583 | { |
3584 | struct drm_device *dev = crtc->dev; | |
3585 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3586 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3587 | int pipe = intel_crtc->pipe; | |
80824003 | 3588 | int plane = intel_crtc->plane; |
5eddb70b | 3589 | u32 fp_reg, dpll_reg; |
c751ce4f | 3590 | int refclk, num_connectors = 0; |
652c393a | 3591 | intel_clock_t clock, reduced_clock; |
5eddb70b | 3592 | u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf; |
652c393a | 3593 | bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false; |
a4fc5ed6 | 3594 | bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false; |
8e647a27 | 3595 | struct intel_encoder *has_edp_encoder = NULL; |
79e53945 | 3596 | struct drm_mode_config *mode_config = &dev->mode_config; |
5eddb70b | 3597 | struct intel_encoder *encoder; |
d4906093 | 3598 | const intel_limit_t *limit; |
5c3b82e2 | 3599 | int ret; |
2c07245f | 3600 | struct fdi_m_n m_n = {0}; |
5eddb70b | 3601 | u32 reg, temp; |
5eb08b69 | 3602 | int target_clock; |
79e53945 JB |
3603 | |
3604 | drm_vblank_pre_modeset(dev, pipe); | |
3605 | ||
5eddb70b CW |
3606 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { |
3607 | if (encoder->base.crtc != crtc) | |
79e53945 JB |
3608 | continue; |
3609 | ||
5eddb70b | 3610 | switch (encoder->type) { |
79e53945 JB |
3611 | case INTEL_OUTPUT_LVDS: |
3612 | is_lvds = true; | |
3613 | break; | |
3614 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 3615 | case INTEL_OUTPUT_HDMI: |
79e53945 | 3616 | is_sdvo = true; |
5eddb70b | 3617 | if (encoder->needs_tv_clock) |
e2f0ba97 | 3618 | is_tv = true; |
79e53945 JB |
3619 | break; |
3620 | case INTEL_OUTPUT_DVO: | |
3621 | is_dvo = true; | |
3622 | break; | |
3623 | case INTEL_OUTPUT_TVOUT: | |
3624 | is_tv = true; | |
3625 | break; | |
3626 | case INTEL_OUTPUT_ANALOG: | |
3627 | is_crt = true; | |
3628 | break; | |
a4fc5ed6 KP |
3629 | case INTEL_OUTPUT_DISPLAYPORT: |
3630 | is_dp = true; | |
3631 | break; | |
32f9d658 | 3632 | case INTEL_OUTPUT_EDP: |
5eddb70b | 3633 | has_edp_encoder = encoder; |
32f9d658 | 3634 | break; |
79e53945 | 3635 | } |
43565a06 | 3636 | |
c751ce4f | 3637 | num_connectors++; |
79e53945 JB |
3638 | } |
3639 | ||
c751ce4f | 3640 | if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) { |
43565a06 | 3641 | refclk = dev_priv->lvds_ssc_freq * 1000; |
28c97730 | 3642 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", |
5eddb70b | 3643 | refclk / 1000); |
a6c45cf0 | 3644 | } else if (!IS_GEN2(dev)) { |
79e53945 | 3645 | refclk = 96000; |
1cb1b75e JB |
3646 | if (HAS_PCH_SPLIT(dev) && |
3647 | (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base))) | |
2c07245f | 3648 | refclk = 120000; /* 120Mhz refclk */ |
79e53945 JB |
3649 | } else { |
3650 | refclk = 48000; | |
3651 | } | |
3652 | ||
d4906093 ML |
3653 | /* |
3654 | * Returns a set of divisors for the desired target clock with the given | |
3655 | * refclk, or FALSE. The returned values represent the clock equation: | |
3656 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
3657 | */ | |
3658 | limit = intel_limit(crtc); | |
3659 | ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock); | |
79e53945 JB |
3660 | if (!ok) { |
3661 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
1f803ee5 | 3662 | drm_vblank_post_modeset(dev, pipe); |
5c3b82e2 | 3663 | return -EINVAL; |
79e53945 JB |
3664 | } |
3665 | ||
cda4b7d3 | 3666 | /* Ensure that the cursor is valid for the new mode before changing... */ |
6b383a7f | 3667 | intel_crtc_update_cursor(crtc, true); |
cda4b7d3 | 3668 | |
ddc9003c ZY |
3669 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
3670 | has_reduced_clock = limit->find_pll(limit, crtc, | |
5eddb70b CW |
3671 | dev_priv->lvds_downclock, |
3672 | refclk, | |
3673 | &reduced_clock); | |
18f9ed12 ZY |
3674 | if (has_reduced_clock && (clock.p != reduced_clock.p)) { |
3675 | /* | |
3676 | * If the different P is found, it means that we can't | |
3677 | * switch the display clock by using the FP0/FP1. | |
3678 | * In such case we will disable the LVDS downclock | |
3679 | * feature. | |
3680 | */ | |
3681 | DRM_DEBUG_KMS("Different P is found for " | |
5eddb70b | 3682 | "LVDS clock/downclock\n"); |
18f9ed12 ZY |
3683 | has_reduced_clock = 0; |
3684 | } | |
652c393a | 3685 | } |
7026d4ac ZW |
3686 | /* SDVO TV has fixed PLL values depend on its clock range, |
3687 | this mirrors vbios setting. */ | |
3688 | if (is_sdvo && is_tv) { | |
3689 | if (adjusted_mode->clock >= 100000 | |
5eddb70b | 3690 | && adjusted_mode->clock < 140500) { |
7026d4ac ZW |
3691 | clock.p1 = 2; |
3692 | clock.p2 = 10; | |
3693 | clock.n = 3; | |
3694 | clock.m1 = 16; | |
3695 | clock.m2 = 8; | |
3696 | } else if (adjusted_mode->clock >= 140500 | |
5eddb70b | 3697 | && adjusted_mode->clock <= 200000) { |
7026d4ac ZW |
3698 | clock.p1 = 1; |
3699 | clock.p2 = 10; | |
3700 | clock.n = 6; | |
3701 | clock.m1 = 12; | |
3702 | clock.m2 = 8; | |
3703 | } | |
3704 | } | |
3705 | ||
2c07245f | 3706 | /* FDI link */ |
bad720ff | 3707 | if (HAS_PCH_SPLIT(dev)) { |
49078f7d | 3708 | int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); |
77ffb597 | 3709 | int lane = 0, link_bw, bpp; |
5c5313c8 | 3710 | /* CPU eDP doesn't require FDI link, so just set DP M/N |
32f9d658 | 3711 | according to current link config */ |
5c5313c8 | 3712 | if (has_edp_encoder && !intel_encoder_is_pch_edp(&encoder->base)) { |
5eb08b69 | 3713 | target_clock = mode->clock; |
8e647a27 CW |
3714 | intel_edp_link_config(has_edp_encoder, |
3715 | &lane, &link_bw); | |
32f9d658 | 3716 | } else { |
5c5313c8 | 3717 | /* [e]DP over FDI requires target mode clock |
32f9d658 | 3718 | instead of link clock */ |
5c5313c8 | 3719 | if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) |
32f9d658 ZW |
3720 | target_clock = mode->clock; |
3721 | else | |
3722 | target_clock = adjusted_mode->clock; | |
021357ac CW |
3723 | |
3724 | /* FDI is a binary signal running at ~2.7GHz, encoding | |
3725 | * each output octet as 10 bits. The actual frequency | |
3726 | * is stored as a divider into a 100MHz clock, and the | |
3727 | * mode pixel clock is stored in units of 1KHz. | |
3728 | * Hence the bw of each lane in terms of the mode signal | |
3729 | * is: | |
3730 | */ | |
3731 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
32f9d658 | 3732 | } |
58a27471 ZW |
3733 | |
3734 | /* determine panel color depth */ | |
5eddb70b | 3735 | temp = I915_READ(PIPECONF(pipe)); |
e5a95eb7 ZY |
3736 | temp &= ~PIPE_BPC_MASK; |
3737 | if (is_lvds) { | |
e5a95eb7 | 3738 | /* the BPC will be 6 if it is 18-bit LVDS panel */ |
5eddb70b | 3739 | if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP) |
e5a95eb7 ZY |
3740 | temp |= PIPE_8BPC; |
3741 | else | |
3742 | temp |= PIPE_6BPC; | |
1d850362 | 3743 | } else if (has_edp_encoder) { |
5ceb0f9b | 3744 | switch (dev_priv->edp.bpp/3) { |
885a5fb5 ZW |
3745 | case 8: |
3746 | temp |= PIPE_8BPC; | |
3747 | break; | |
3748 | case 10: | |
3749 | temp |= PIPE_10BPC; | |
3750 | break; | |
3751 | case 6: | |
3752 | temp |= PIPE_6BPC; | |
3753 | break; | |
3754 | case 12: | |
3755 | temp |= PIPE_12BPC; | |
3756 | break; | |
3757 | } | |
e5a95eb7 ZY |
3758 | } else |
3759 | temp |= PIPE_8BPC; | |
5eddb70b | 3760 | I915_WRITE(PIPECONF(pipe), temp); |
58a27471 ZW |
3761 | |
3762 | switch (temp & PIPE_BPC_MASK) { | |
3763 | case PIPE_8BPC: | |
3764 | bpp = 24; | |
3765 | break; | |
3766 | case PIPE_10BPC: | |
3767 | bpp = 30; | |
3768 | break; | |
3769 | case PIPE_6BPC: | |
3770 | bpp = 18; | |
3771 | break; | |
3772 | case PIPE_12BPC: | |
3773 | bpp = 36; | |
3774 | break; | |
3775 | default: | |
3776 | DRM_ERROR("unknown pipe bpc value\n"); | |
3777 | bpp = 24; | |
3778 | } | |
3779 | ||
77ffb597 AJ |
3780 | if (!lane) { |
3781 | /* | |
3782 | * Account for spread spectrum to avoid | |
3783 | * oversubscribing the link. Max center spread | |
3784 | * is 2.5%; use 5% for safety's sake. | |
3785 | */ | |
3786 | u32 bps = target_clock * bpp * 21 / 20; | |
3787 | lane = bps / (link_bw * 8) + 1; | |
3788 | } | |
3789 | ||
3790 | intel_crtc->fdi_lanes = lane; | |
3791 | ||
49078f7d CW |
3792 | if (pixel_multiplier > 1) |
3793 | link_bw *= pixel_multiplier; | |
f2b115e6 | 3794 | ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n); |
5eb08b69 | 3795 | } |
2c07245f | 3796 | |
c038e51e ZW |
3797 | /* Ironlake: try to setup display ref clock before DPLL |
3798 | * enabling. This is only under driver's control after | |
3799 | * PCH B stepping, previous chipset stepping should be | |
3800 | * ignoring this setting. | |
3801 | */ | |
bad720ff | 3802 | if (HAS_PCH_SPLIT(dev)) { |
c038e51e ZW |
3803 | temp = I915_READ(PCH_DREF_CONTROL); |
3804 | /* Always enable nonspread source */ | |
3805 | temp &= ~DREF_NONSPREAD_SOURCE_MASK; | |
3806 | temp |= DREF_NONSPREAD_SOURCE_ENABLE; | |
c038e51e ZW |
3807 | temp &= ~DREF_SSC_SOURCE_MASK; |
3808 | temp |= DREF_SSC_SOURCE_ENABLE; | |
3809 | I915_WRITE(PCH_DREF_CONTROL, temp); | |
c038e51e | 3810 | |
5eddb70b | 3811 | POSTING_READ(PCH_DREF_CONTROL); |
c038e51e ZW |
3812 | udelay(200); |
3813 | ||
8e647a27 | 3814 | if (has_edp_encoder) { |
c038e51e ZW |
3815 | if (dev_priv->lvds_use_ssc) { |
3816 | temp |= DREF_SSC1_ENABLE; | |
3817 | I915_WRITE(PCH_DREF_CONTROL, temp); | |
c038e51e | 3818 | |
5eddb70b | 3819 | POSTING_READ(PCH_DREF_CONTROL); |
c038e51e | 3820 | udelay(200); |
7f823282 JB |
3821 | } |
3822 | temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
3823 | ||
3824 | /* Enable CPU source on CPU attached eDP */ | |
3825 | if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) { | |
3826 | if (dev_priv->lvds_use_ssc) | |
3827 | temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
3828 | else | |
3829 | temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
c038e51e | 3830 | } else { |
7f823282 JB |
3831 | /* Enable SSC on PCH eDP if needed */ |
3832 | if (dev_priv->lvds_use_ssc) { | |
3833 | DRM_ERROR("enabling SSC on PCH\n"); | |
3834 | temp |= DREF_SUPERSPREAD_SOURCE_ENABLE; | |
3835 | } | |
c038e51e | 3836 | } |
5eddb70b | 3837 | I915_WRITE(PCH_DREF_CONTROL, temp); |
7f823282 JB |
3838 | POSTING_READ(PCH_DREF_CONTROL); |
3839 | udelay(200); | |
c038e51e ZW |
3840 | } |
3841 | } | |
3842 | ||
f2b115e6 | 3843 | if (IS_PINEVIEW(dev)) { |
2177832f | 3844 | fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2; |
652c393a JB |
3845 | if (has_reduced_clock) |
3846 | fp2 = (1 << reduced_clock.n) << 16 | | |
3847 | reduced_clock.m1 << 8 | reduced_clock.m2; | |
3848 | } else { | |
2177832f | 3849 | fp = clock.n << 16 | clock.m1 << 8 | clock.m2; |
652c393a JB |
3850 | if (has_reduced_clock) |
3851 | fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 | | |
3852 | reduced_clock.m2; | |
3853 | } | |
79e53945 | 3854 | |
c1858123 CW |
3855 | /* Enable autotuning of the PLL clock (if permissible) */ |
3856 | if (HAS_PCH_SPLIT(dev)) { | |
3857 | int factor = 21; | |
3858 | ||
3859 | if (is_lvds) { | |
3860 | if ((dev_priv->lvds_use_ssc && | |
3861 | dev_priv->lvds_ssc_freq == 100) || | |
3862 | (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP) | |
3863 | factor = 25; | |
3864 | } else if (is_sdvo && is_tv) | |
3865 | factor = 20; | |
3866 | ||
3867 | if (clock.m1 < factor * clock.n) | |
3868 | fp |= FP_CB_TUNE; | |
3869 | } | |
3870 | ||
5eddb70b | 3871 | dpll = 0; |
bad720ff | 3872 | if (!HAS_PCH_SPLIT(dev)) |
2c07245f ZW |
3873 | dpll = DPLL_VGA_MODE_DIS; |
3874 | ||
a6c45cf0 | 3875 | if (!IS_GEN2(dev)) { |
79e53945 JB |
3876 | if (is_lvds) |
3877 | dpll |= DPLLB_MODE_LVDS; | |
3878 | else | |
3879 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
3880 | if (is_sdvo) { | |
6c9547ff CW |
3881 | int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); |
3882 | if (pixel_multiplier > 1) { | |
3883 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) | |
3884 | dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES; | |
3885 | else if (HAS_PCH_SPLIT(dev)) | |
3886 | dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; | |
3887 | } | |
79e53945 | 3888 | dpll |= DPLL_DVO_HIGH_SPEED; |
79e53945 | 3889 | } |
83240120 | 3890 | if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) |
a4fc5ed6 | 3891 | dpll |= DPLL_DVO_HIGH_SPEED; |
79e53945 JB |
3892 | |
3893 | /* compute bitmask from p1 value */ | |
f2b115e6 AJ |
3894 | if (IS_PINEVIEW(dev)) |
3895 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
2c07245f | 3896 | else { |
2177832f | 3897 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
2c07245f | 3898 | /* also FPA1 */ |
bad720ff | 3899 | if (HAS_PCH_SPLIT(dev)) |
2c07245f | 3900 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
652c393a JB |
3901 | if (IS_G4X(dev) && has_reduced_clock) |
3902 | dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
2c07245f | 3903 | } |
79e53945 JB |
3904 | switch (clock.p2) { |
3905 | case 5: | |
3906 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
3907 | break; | |
3908 | case 7: | |
3909 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
3910 | break; | |
3911 | case 10: | |
3912 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
3913 | break; | |
3914 | case 14: | |
3915 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
3916 | break; | |
3917 | } | |
a6c45cf0 | 3918 | if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) |
79e53945 JB |
3919 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); |
3920 | } else { | |
3921 | if (is_lvds) { | |
3922 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
3923 | } else { | |
3924 | if (clock.p1 == 2) | |
3925 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
3926 | else | |
3927 | dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
3928 | if (clock.p2 == 4) | |
3929 | dpll |= PLL_P2_DIVIDE_BY_4; | |
3930 | } | |
3931 | } | |
3932 | ||
43565a06 KH |
3933 | if (is_sdvo && is_tv) |
3934 | dpll |= PLL_REF_INPUT_TVCLKINBC; | |
3935 | else if (is_tv) | |
79e53945 | 3936 | /* XXX: just matching BIOS for now */ |
43565a06 | 3937 | /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ |
79e53945 | 3938 | dpll |= 3; |
c751ce4f | 3939 | else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) |
43565a06 | 3940 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
3941 | else |
3942 | dpll |= PLL_REF_INPUT_DREFCLK; | |
3943 | ||
3944 | /* setup pipeconf */ | |
5eddb70b | 3945 | pipeconf = I915_READ(PIPECONF(pipe)); |
79e53945 JB |
3946 | |
3947 | /* Set up the display plane register */ | |
3948 | dspcntr = DISPPLANE_GAMMA_ENABLE; | |
3949 | ||
f2b115e6 | 3950 | /* Ironlake's plane is forced to pipe, bit 24 is to |
2c07245f | 3951 | enable color space conversion */ |
bad720ff | 3952 | if (!HAS_PCH_SPLIT(dev)) { |
2c07245f | 3953 | if (pipe == 0) |
80824003 | 3954 | dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; |
2c07245f ZW |
3955 | else |
3956 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
3957 | } | |
79e53945 | 3958 | |
a6c45cf0 | 3959 | if (pipe == 0 && INTEL_INFO(dev)->gen < 4) { |
79e53945 JB |
3960 | /* Enable pixel doubling when the dot clock is > 90% of the (display) |
3961 | * core speed. | |
3962 | * | |
3963 | * XXX: No double-wide on 915GM pipe B. Is that the only reason for the | |
3964 | * pipe == 0 check? | |
3965 | */ | |
e70236a8 JB |
3966 | if (mode->clock > |
3967 | dev_priv->display.get_display_clock_speed(dev) * 9 / 10) | |
5eddb70b | 3968 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
79e53945 | 3969 | else |
5eddb70b | 3970 | pipeconf &= ~PIPECONF_DOUBLE_WIDE; |
79e53945 JB |
3971 | } |
3972 | ||
8d86dc6a | 3973 | dspcntr |= DISPLAY_PLANE_ENABLE; |
5eddb70b | 3974 | pipeconf |= PIPECONF_ENABLE; |
8d86dc6a LT |
3975 | dpll |= DPLL_VCO_ENABLE; |
3976 | ||
28c97730 | 3977 | DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); |
79e53945 JB |
3978 | drm_mode_debug_printmodeline(mode); |
3979 | ||
f2b115e6 | 3980 | /* assign to Ironlake registers */ |
bad720ff | 3981 | if (HAS_PCH_SPLIT(dev)) { |
5eddb70b CW |
3982 | fp_reg = PCH_FP0(pipe); |
3983 | dpll_reg = PCH_DPLL(pipe); | |
3984 | } else { | |
3985 | fp_reg = FP0(pipe); | |
3986 | dpll_reg = DPLL(pipe); | |
2c07245f | 3987 | } |
79e53945 | 3988 | |
5c5313c8 JB |
3989 | /* PCH eDP needs FDI, but CPU eDP does not */ |
3990 | if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) { | |
79e53945 JB |
3991 | I915_WRITE(fp_reg, fp); |
3992 | I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE); | |
5eddb70b CW |
3993 | |
3994 | POSTING_READ(dpll_reg); | |
79e53945 JB |
3995 | udelay(150); |
3996 | } | |
3997 | ||
8db9d77b ZW |
3998 | /* enable transcoder DPLL */ |
3999 | if (HAS_PCH_CPT(dev)) { | |
4000 | temp = I915_READ(PCH_DPLL_SEL); | |
5eddb70b CW |
4001 | if (pipe == 0) |
4002 | temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL; | |
8db9d77b | 4003 | else |
5eddb70b | 4004 | temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL; |
8db9d77b | 4005 | I915_WRITE(PCH_DPLL_SEL, temp); |
5eddb70b CW |
4006 | |
4007 | POSTING_READ(PCH_DPLL_SEL); | |
8db9d77b ZW |
4008 | udelay(150); |
4009 | } | |
4010 | ||
79e53945 JB |
4011 | /* The LVDS pin pair needs to be on before the DPLLs are enabled. |
4012 | * This is an exception to the general rule that mode_set doesn't turn | |
4013 | * things on. | |
4014 | */ | |
4015 | if (is_lvds) { | |
5eddb70b | 4016 | reg = LVDS; |
bad720ff | 4017 | if (HAS_PCH_SPLIT(dev)) |
5eddb70b | 4018 | reg = PCH_LVDS; |
541998a1 | 4019 | |
5eddb70b CW |
4020 | temp = I915_READ(reg); |
4021 | temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; | |
b3b095b3 ZW |
4022 | if (pipe == 1) { |
4023 | if (HAS_PCH_CPT(dev)) | |
5eddb70b | 4024 | temp |= PORT_TRANS_B_SEL_CPT; |
b3b095b3 | 4025 | else |
5eddb70b | 4026 | temp |= LVDS_PIPEB_SELECT; |
b3b095b3 ZW |
4027 | } else { |
4028 | if (HAS_PCH_CPT(dev)) | |
5eddb70b | 4029 | temp &= ~PORT_TRANS_SEL_MASK; |
b3b095b3 | 4030 | else |
5eddb70b | 4031 | temp &= ~LVDS_PIPEB_SELECT; |
b3b095b3 | 4032 | } |
a3e17eb8 | 4033 | /* set the corresponsding LVDS_BORDER bit */ |
5eddb70b | 4034 | temp |= dev_priv->lvds_border_bits; |
79e53945 JB |
4035 | /* Set the B0-B3 data pairs corresponding to whether we're going to |
4036 | * set the DPLLs for dual-channel mode or not. | |
4037 | */ | |
4038 | if (clock.p2 == 7) | |
5eddb70b | 4039 | temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; |
79e53945 | 4040 | else |
5eddb70b | 4041 | temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); |
79e53945 JB |
4042 | |
4043 | /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) | |
4044 | * appropriately here, but we need to look more thoroughly into how | |
4045 | * panels behave in the two modes. | |
4046 | */ | |
434ed097 | 4047 | /* set the dithering flag on non-PCH LVDS as needed */ |
a6c45cf0 | 4048 | if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) { |
434ed097 | 4049 | if (dev_priv->lvds_dither) |
5eddb70b | 4050 | temp |= LVDS_ENABLE_DITHER; |
434ed097 | 4051 | else |
5eddb70b | 4052 | temp &= ~LVDS_ENABLE_DITHER; |
898822ce | 4053 | } |
5eddb70b | 4054 | I915_WRITE(reg, temp); |
79e53945 | 4055 | } |
434ed097 JB |
4056 | |
4057 | /* set the dithering flag and clear for anything other than a panel. */ | |
4058 | if (HAS_PCH_SPLIT(dev)) { | |
4059 | pipeconf &= ~PIPECONF_DITHER_EN; | |
4060 | pipeconf &= ~PIPECONF_DITHER_TYPE_MASK; | |
4061 | if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) { | |
4062 | pipeconf |= PIPECONF_DITHER_EN; | |
4063 | pipeconf |= PIPECONF_DITHER_TYPE_ST1; | |
4064 | } | |
4065 | } | |
4066 | ||
5c5313c8 | 4067 | if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) { |
a4fc5ed6 | 4068 | intel_dp_set_m_n(crtc, mode, adjusted_mode); |
5c5313c8 | 4069 | } else if (HAS_PCH_SPLIT(dev)) { |
8db9d77b ZW |
4070 | /* For non-DP output, clear any trans DP clock recovery setting.*/ |
4071 | if (pipe == 0) { | |
4072 | I915_WRITE(TRANSA_DATA_M1, 0); | |
4073 | I915_WRITE(TRANSA_DATA_N1, 0); | |
4074 | I915_WRITE(TRANSA_DP_LINK_M1, 0); | |
4075 | I915_WRITE(TRANSA_DP_LINK_N1, 0); | |
4076 | } else { | |
4077 | I915_WRITE(TRANSB_DATA_M1, 0); | |
4078 | I915_WRITE(TRANSB_DATA_N1, 0); | |
4079 | I915_WRITE(TRANSB_DP_LINK_M1, 0); | |
4080 | I915_WRITE(TRANSB_DP_LINK_N1, 0); | |
4081 | } | |
4082 | } | |
79e53945 | 4083 | |
5c5313c8 | 4084 | if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) { |
79e53945 | 4085 | I915_WRITE(dpll_reg, dpll); |
5eddb70b | 4086 | |
32f9d658 | 4087 | /* Wait for the clocks to stabilize. */ |
5eddb70b | 4088 | POSTING_READ(dpll_reg); |
32f9d658 ZW |
4089 | udelay(150); |
4090 | ||
a6c45cf0 | 4091 | if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) { |
5eddb70b | 4092 | temp = 0; |
bb66c512 | 4093 | if (is_sdvo) { |
5eddb70b CW |
4094 | temp = intel_mode_get_pixel_multiplier(adjusted_mode); |
4095 | if (temp > 1) | |
4096 | temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
6c9547ff | 4097 | else |
5eddb70b CW |
4098 | temp = 0; |
4099 | } | |
4100 | I915_WRITE(DPLL_MD(pipe), temp); | |
32f9d658 | 4101 | } else { |
a589b9f4 CW |
4102 | /* The pixel multiplier can only be updated once the |
4103 | * DPLL is enabled and the clocks are stable. | |
4104 | * | |
4105 | * So write it again. | |
4106 | */ | |
32f9d658 ZW |
4107 | I915_WRITE(dpll_reg, dpll); |
4108 | } | |
79e53945 | 4109 | } |
79e53945 | 4110 | |
5eddb70b | 4111 | intel_crtc->lowfreq_avail = false; |
652c393a JB |
4112 | if (is_lvds && has_reduced_clock && i915_powersave) { |
4113 | I915_WRITE(fp_reg + 4, fp2); | |
4114 | intel_crtc->lowfreq_avail = true; | |
4115 | if (HAS_PIPE_CXSR(dev)) { | |
28c97730 | 4116 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); |
652c393a JB |
4117 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; |
4118 | } | |
4119 | } else { | |
4120 | I915_WRITE(fp_reg + 4, fp); | |
652c393a | 4121 | if (HAS_PIPE_CXSR(dev)) { |
28c97730 | 4122 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); |
652c393a JB |
4123 | pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK; |
4124 | } | |
4125 | } | |
4126 | ||
734b4157 KH |
4127 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
4128 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; | |
4129 | /* the chip adds 2 halflines automatically */ | |
4130 | adjusted_mode->crtc_vdisplay -= 1; | |
4131 | adjusted_mode->crtc_vtotal -= 1; | |
4132 | adjusted_mode->crtc_vblank_start -= 1; | |
4133 | adjusted_mode->crtc_vblank_end -= 1; | |
4134 | adjusted_mode->crtc_vsync_end -= 1; | |
4135 | adjusted_mode->crtc_vsync_start -= 1; | |
4136 | } else | |
4137 | pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */ | |
4138 | ||
5eddb70b CW |
4139 | I915_WRITE(HTOTAL(pipe), |
4140 | (adjusted_mode->crtc_hdisplay - 1) | | |
79e53945 | 4141 | ((adjusted_mode->crtc_htotal - 1) << 16)); |
5eddb70b CW |
4142 | I915_WRITE(HBLANK(pipe), |
4143 | (adjusted_mode->crtc_hblank_start - 1) | | |
79e53945 | 4144 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); |
5eddb70b CW |
4145 | I915_WRITE(HSYNC(pipe), |
4146 | (adjusted_mode->crtc_hsync_start - 1) | | |
79e53945 | 4147 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); |
5eddb70b CW |
4148 | |
4149 | I915_WRITE(VTOTAL(pipe), | |
4150 | (adjusted_mode->crtc_vdisplay - 1) | | |
79e53945 | 4151 | ((adjusted_mode->crtc_vtotal - 1) << 16)); |
5eddb70b CW |
4152 | I915_WRITE(VBLANK(pipe), |
4153 | (adjusted_mode->crtc_vblank_start - 1) | | |
79e53945 | 4154 | ((adjusted_mode->crtc_vblank_end - 1) << 16)); |
5eddb70b CW |
4155 | I915_WRITE(VSYNC(pipe), |
4156 | (adjusted_mode->crtc_vsync_start - 1) | | |
79e53945 | 4157 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); |
5eddb70b CW |
4158 | |
4159 | /* pipesrc and dspsize control the size that is scaled from, | |
4160 | * which should always be the user's requested size. | |
79e53945 | 4161 | */ |
bad720ff | 4162 | if (!HAS_PCH_SPLIT(dev)) { |
5eddb70b CW |
4163 | I915_WRITE(DSPSIZE(plane), |
4164 | ((mode->vdisplay - 1) << 16) | | |
4165 | (mode->hdisplay - 1)); | |
4166 | I915_WRITE(DSPPOS(plane), 0); | |
2c07245f | 4167 | } |
5eddb70b CW |
4168 | I915_WRITE(PIPESRC(pipe), |
4169 | ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); | |
2c07245f | 4170 | |
bad720ff | 4171 | if (HAS_PCH_SPLIT(dev)) { |
5eddb70b CW |
4172 | I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m); |
4173 | I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n); | |
4174 | I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m); | |
4175 | I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n); | |
2c07245f | 4176 | |
5c5313c8 | 4177 | if (has_edp_encoder && !intel_encoder_is_pch_edp(&has_edp_encoder->base)) { |
f2b115e6 | 4178 | ironlake_set_pll_edp(crtc, adjusted_mode->clock); |
32f9d658 | 4179 | } |
2c07245f ZW |
4180 | } |
4181 | ||
5eddb70b CW |
4182 | I915_WRITE(PIPECONF(pipe), pipeconf); |
4183 | POSTING_READ(PIPECONF(pipe)); | |
79e53945 | 4184 | |
9d0498a2 | 4185 | intel_wait_for_vblank(dev, pipe); |
79e53945 | 4186 | |
f00a3ddf | 4187 | if (IS_GEN5(dev)) { |
553bd149 ZW |
4188 | /* enable address swizzle for tiling buffer */ |
4189 | temp = I915_READ(DISP_ARB_CTL); | |
4190 | I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING); | |
4191 | } | |
4192 | ||
5eddb70b | 4193 | I915_WRITE(DSPCNTR(plane), dspcntr); |
79e53945 | 4194 | |
5c3b82e2 | 4195 | ret = intel_pipe_set_base(crtc, x, y, old_fb); |
7662c8bd SL |
4196 | |
4197 | intel_update_watermarks(dev); | |
4198 | ||
79e53945 | 4199 | drm_vblank_post_modeset(dev, pipe); |
5c3b82e2 | 4200 | |
1f803ee5 | 4201 | return ret; |
79e53945 JB |
4202 | } |
4203 | ||
4204 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ | |
4205 | void intel_crtc_load_lut(struct drm_crtc *crtc) | |
4206 | { | |
4207 | struct drm_device *dev = crtc->dev; | |
4208 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4209 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4210 | int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B; | |
4211 | int i; | |
4212 | ||
4213 | /* The clocks have to be on to load the palette. */ | |
4214 | if (!crtc->enabled) | |
4215 | return; | |
4216 | ||
f2b115e6 | 4217 | /* use legacy palette for Ironlake */ |
bad720ff | 4218 | if (HAS_PCH_SPLIT(dev)) |
2c07245f ZW |
4219 | palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A : |
4220 | LGC_PALETTE_B; | |
4221 | ||
79e53945 JB |
4222 | for (i = 0; i < 256; i++) { |
4223 | I915_WRITE(palreg + 4 * i, | |
4224 | (intel_crtc->lut_r[i] << 16) | | |
4225 | (intel_crtc->lut_g[i] << 8) | | |
4226 | intel_crtc->lut_b[i]); | |
4227 | } | |
4228 | } | |
4229 | ||
560b85bb CW |
4230 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
4231 | { | |
4232 | struct drm_device *dev = crtc->dev; | |
4233 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4234 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4235 | bool visible = base != 0; | |
4236 | u32 cntl; | |
4237 | ||
4238 | if (intel_crtc->cursor_visible == visible) | |
4239 | return; | |
4240 | ||
4241 | cntl = I915_READ(CURACNTR); | |
4242 | if (visible) { | |
4243 | /* On these chipsets we can only modify the base whilst | |
4244 | * the cursor is disabled. | |
4245 | */ | |
4246 | I915_WRITE(CURABASE, base); | |
4247 | ||
4248 | cntl &= ~(CURSOR_FORMAT_MASK); | |
4249 | /* XXX width must be 64, stride 256 => 0x00 << 28 */ | |
4250 | cntl |= CURSOR_ENABLE | | |
4251 | CURSOR_GAMMA_ENABLE | | |
4252 | CURSOR_FORMAT_ARGB; | |
4253 | } else | |
4254 | cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE); | |
4255 | I915_WRITE(CURACNTR, cntl); | |
4256 | ||
4257 | intel_crtc->cursor_visible = visible; | |
4258 | } | |
4259 | ||
4260 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) | |
4261 | { | |
4262 | struct drm_device *dev = crtc->dev; | |
4263 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4264 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4265 | int pipe = intel_crtc->pipe; | |
4266 | bool visible = base != 0; | |
4267 | ||
4268 | if (intel_crtc->cursor_visible != visible) { | |
4269 | uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR); | |
4270 | if (base) { | |
4271 | cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT); | |
4272 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; | |
4273 | cntl |= pipe << 28; /* Connect to correct pipe */ | |
4274 | } else { | |
4275 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); | |
4276 | cntl |= CURSOR_MODE_DISABLE; | |
4277 | } | |
4278 | I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl); | |
4279 | ||
4280 | intel_crtc->cursor_visible = visible; | |
4281 | } | |
4282 | /* and commit changes on next vblank */ | |
4283 | I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base); | |
4284 | } | |
4285 | ||
cda4b7d3 | 4286 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f CW |
4287 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
4288 | bool on) | |
cda4b7d3 CW |
4289 | { |
4290 | struct drm_device *dev = crtc->dev; | |
4291 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4292 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4293 | int pipe = intel_crtc->pipe; | |
4294 | int x = intel_crtc->cursor_x; | |
4295 | int y = intel_crtc->cursor_y; | |
560b85bb | 4296 | u32 base, pos; |
cda4b7d3 CW |
4297 | bool visible; |
4298 | ||
4299 | pos = 0; | |
4300 | ||
6b383a7f | 4301 | if (on && crtc->enabled && crtc->fb) { |
cda4b7d3 CW |
4302 | base = intel_crtc->cursor_addr; |
4303 | if (x > (int) crtc->fb->width) | |
4304 | base = 0; | |
4305 | ||
4306 | if (y > (int) crtc->fb->height) | |
4307 | base = 0; | |
4308 | } else | |
4309 | base = 0; | |
4310 | ||
4311 | if (x < 0) { | |
4312 | if (x + intel_crtc->cursor_width < 0) | |
4313 | base = 0; | |
4314 | ||
4315 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
4316 | x = -x; | |
4317 | } | |
4318 | pos |= x << CURSOR_X_SHIFT; | |
4319 | ||
4320 | if (y < 0) { | |
4321 | if (y + intel_crtc->cursor_height < 0) | |
4322 | base = 0; | |
4323 | ||
4324 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
4325 | y = -y; | |
4326 | } | |
4327 | pos |= y << CURSOR_Y_SHIFT; | |
4328 | ||
4329 | visible = base != 0; | |
560b85bb | 4330 | if (!visible && !intel_crtc->cursor_visible) |
cda4b7d3 CW |
4331 | return; |
4332 | ||
4333 | I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos); | |
560b85bb CW |
4334 | if (IS_845G(dev) || IS_I865G(dev)) |
4335 | i845_update_cursor(crtc, base); | |
4336 | else | |
4337 | i9xx_update_cursor(crtc, base); | |
cda4b7d3 CW |
4338 | |
4339 | if (visible) | |
4340 | intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj); | |
4341 | } | |
4342 | ||
79e53945 | 4343 | static int intel_crtc_cursor_set(struct drm_crtc *crtc, |
05394f39 | 4344 | struct drm_file *file, |
79e53945 JB |
4345 | uint32_t handle, |
4346 | uint32_t width, uint32_t height) | |
4347 | { | |
4348 | struct drm_device *dev = crtc->dev; | |
4349 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4350 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
05394f39 | 4351 | struct drm_i915_gem_object *obj; |
cda4b7d3 | 4352 | uint32_t addr; |
3f8bc370 | 4353 | int ret; |
79e53945 | 4354 | |
28c97730 | 4355 | DRM_DEBUG_KMS("\n"); |
79e53945 JB |
4356 | |
4357 | /* if we want to turn off the cursor ignore width and height */ | |
4358 | if (!handle) { | |
28c97730 | 4359 | DRM_DEBUG_KMS("cursor off\n"); |
3f8bc370 | 4360 | addr = 0; |
05394f39 | 4361 | obj = NULL; |
5004417d | 4362 | mutex_lock(&dev->struct_mutex); |
3f8bc370 | 4363 | goto finish; |
79e53945 JB |
4364 | } |
4365 | ||
4366 | /* Currently we only support 64x64 cursors */ | |
4367 | if (width != 64 || height != 64) { | |
4368 | DRM_ERROR("we currently only support 64x64 cursors\n"); | |
4369 | return -EINVAL; | |
4370 | } | |
4371 | ||
05394f39 CW |
4372 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
4373 | if (!obj) | |
79e53945 JB |
4374 | return -ENOENT; |
4375 | ||
05394f39 | 4376 | if (obj->base.size < width * height * 4) { |
79e53945 | 4377 | DRM_ERROR("buffer is to small\n"); |
34b8686e DA |
4378 | ret = -ENOMEM; |
4379 | goto fail; | |
79e53945 JB |
4380 | } |
4381 | ||
71acb5eb | 4382 | /* we only need to pin inside GTT if cursor is non-phy */ |
7f9872e0 | 4383 | mutex_lock(&dev->struct_mutex); |
b295d1b6 | 4384 | if (!dev_priv->info->cursor_needs_physical) { |
d9e86c0e CW |
4385 | if (obj->tiling_mode) { |
4386 | DRM_ERROR("cursor cannot be tiled\n"); | |
4387 | ret = -EINVAL; | |
4388 | goto fail_locked; | |
4389 | } | |
4390 | ||
05394f39 | 4391 | ret = i915_gem_object_pin(obj, PAGE_SIZE, true); |
71acb5eb DA |
4392 | if (ret) { |
4393 | DRM_ERROR("failed to pin cursor bo\n"); | |
7f9872e0 | 4394 | goto fail_locked; |
71acb5eb | 4395 | } |
e7b526bb | 4396 | |
05394f39 | 4397 | ret = i915_gem_object_set_to_gtt_domain(obj, 0); |
e7b526bb CW |
4398 | if (ret) { |
4399 | DRM_ERROR("failed to move cursor bo into the GTT\n"); | |
4400 | goto fail_unpin; | |
4401 | } | |
4402 | ||
d9e86c0e CW |
4403 | ret = i915_gem_object_put_fence(obj); |
4404 | if (ret) { | |
4405 | DRM_ERROR("failed to move cursor bo into the GTT\n"); | |
4406 | goto fail_unpin; | |
4407 | } | |
4408 | ||
05394f39 | 4409 | addr = obj->gtt_offset; |
71acb5eb | 4410 | } else { |
6eeefaf3 | 4411 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
05394f39 | 4412 | ret = i915_gem_attach_phys_object(dev, obj, |
6eeefaf3 CW |
4413 | (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1, |
4414 | align); | |
71acb5eb DA |
4415 | if (ret) { |
4416 | DRM_ERROR("failed to attach phys object\n"); | |
7f9872e0 | 4417 | goto fail_locked; |
71acb5eb | 4418 | } |
05394f39 | 4419 | addr = obj->phys_obj->handle->busaddr; |
3f8bc370 KH |
4420 | } |
4421 | ||
a6c45cf0 | 4422 | if (IS_GEN2(dev)) |
14b60391 JB |
4423 | I915_WRITE(CURSIZE, (height << 12) | width); |
4424 | ||
3f8bc370 | 4425 | finish: |
3f8bc370 | 4426 | if (intel_crtc->cursor_bo) { |
b295d1b6 | 4427 | if (dev_priv->info->cursor_needs_physical) { |
05394f39 | 4428 | if (intel_crtc->cursor_bo != obj) |
71acb5eb DA |
4429 | i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo); |
4430 | } else | |
4431 | i915_gem_object_unpin(intel_crtc->cursor_bo); | |
05394f39 | 4432 | drm_gem_object_unreference(&intel_crtc->cursor_bo->base); |
3f8bc370 | 4433 | } |
80824003 | 4434 | |
7f9872e0 | 4435 | mutex_unlock(&dev->struct_mutex); |
3f8bc370 KH |
4436 | |
4437 | intel_crtc->cursor_addr = addr; | |
05394f39 | 4438 | intel_crtc->cursor_bo = obj; |
cda4b7d3 CW |
4439 | intel_crtc->cursor_width = width; |
4440 | intel_crtc->cursor_height = height; | |
4441 | ||
6b383a7f | 4442 | intel_crtc_update_cursor(crtc, true); |
3f8bc370 | 4443 | |
79e53945 | 4444 | return 0; |
e7b526bb | 4445 | fail_unpin: |
05394f39 | 4446 | i915_gem_object_unpin(obj); |
7f9872e0 | 4447 | fail_locked: |
34b8686e | 4448 | mutex_unlock(&dev->struct_mutex); |
bc9025bd | 4449 | fail: |
05394f39 | 4450 | drm_gem_object_unreference_unlocked(&obj->base); |
34b8686e | 4451 | return ret; |
79e53945 JB |
4452 | } |
4453 | ||
4454 | static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) | |
4455 | { | |
79e53945 | 4456 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 4457 | |
cda4b7d3 CW |
4458 | intel_crtc->cursor_x = x; |
4459 | intel_crtc->cursor_y = y; | |
652c393a | 4460 | |
6b383a7f | 4461 | intel_crtc_update_cursor(crtc, true); |
79e53945 JB |
4462 | |
4463 | return 0; | |
4464 | } | |
4465 | ||
4466 | /** Sets the color ramps on behalf of RandR */ | |
4467 | void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, | |
4468 | u16 blue, int regno) | |
4469 | { | |
4470 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4471 | ||
4472 | intel_crtc->lut_r[regno] = red >> 8; | |
4473 | intel_crtc->lut_g[regno] = green >> 8; | |
4474 | intel_crtc->lut_b[regno] = blue >> 8; | |
4475 | } | |
4476 | ||
b8c00ac5 DA |
4477 | void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
4478 | u16 *blue, int regno) | |
4479 | { | |
4480 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4481 | ||
4482 | *red = intel_crtc->lut_r[regno] << 8; | |
4483 | *green = intel_crtc->lut_g[regno] << 8; | |
4484 | *blue = intel_crtc->lut_b[regno] << 8; | |
4485 | } | |
4486 | ||
79e53945 | 4487 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 4488 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 4489 | { |
7203425a | 4490 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 4491 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 4492 | |
7203425a | 4493 | for (i = start; i < end; i++) { |
79e53945 JB |
4494 | intel_crtc->lut_r[i] = red[i] >> 8; |
4495 | intel_crtc->lut_g[i] = green[i] >> 8; | |
4496 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
4497 | } | |
4498 | ||
4499 | intel_crtc_load_lut(crtc); | |
4500 | } | |
4501 | ||
4502 | /** | |
4503 | * Get a pipe with a simple mode set on it for doing load-based monitor | |
4504 | * detection. | |
4505 | * | |
4506 | * It will be up to the load-detect code to adjust the pipe as appropriate for | |
c751ce4f | 4507 | * its requirements. The pipe will be connected to no other encoders. |
79e53945 | 4508 | * |
c751ce4f | 4509 | * Currently this code will only succeed if there is a pipe with no encoders |
79e53945 JB |
4510 | * configured for it. In the future, it could choose to temporarily disable |
4511 | * some outputs to free up a pipe for its use. | |
4512 | * | |
4513 | * \return crtc, or NULL if no pipes are available. | |
4514 | */ | |
4515 | ||
4516 | /* VESA 640x480x72Hz mode to set on the pipe */ | |
4517 | static struct drm_display_mode load_detect_mode = { | |
4518 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
4519 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
4520 | }; | |
4521 | ||
21d40d37 | 4522 | struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder, |
c1c43977 | 4523 | struct drm_connector *connector, |
79e53945 JB |
4524 | struct drm_display_mode *mode, |
4525 | int *dpms_mode) | |
4526 | { | |
4527 | struct intel_crtc *intel_crtc; | |
4528 | struct drm_crtc *possible_crtc; | |
4529 | struct drm_crtc *supported_crtc =NULL; | |
4ef69c7a | 4530 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
4531 | struct drm_crtc *crtc = NULL; |
4532 | struct drm_device *dev = encoder->dev; | |
4533 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
4534 | struct drm_crtc_helper_funcs *crtc_funcs; | |
4535 | int i = -1; | |
4536 | ||
4537 | /* | |
4538 | * Algorithm gets a little messy: | |
4539 | * - if the connector already has an assigned crtc, use it (but make | |
4540 | * sure it's on first) | |
4541 | * - try to find the first unused crtc that can drive this connector, | |
4542 | * and use that if we find one | |
4543 | * - if there are no unused crtcs available, try to use the first | |
4544 | * one we found that supports the connector | |
4545 | */ | |
4546 | ||
4547 | /* See if we already have a CRTC for this connector */ | |
4548 | if (encoder->crtc) { | |
4549 | crtc = encoder->crtc; | |
4550 | /* Make sure the crtc and connector are running */ | |
4551 | intel_crtc = to_intel_crtc(crtc); | |
4552 | *dpms_mode = intel_crtc->dpms_mode; | |
4553 | if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) { | |
4554 | crtc_funcs = crtc->helper_private; | |
4555 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); | |
4556 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); | |
4557 | } | |
4558 | return crtc; | |
4559 | } | |
4560 | ||
4561 | /* Find an unused one (if possible) */ | |
4562 | list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) { | |
4563 | i++; | |
4564 | if (!(encoder->possible_crtcs & (1 << i))) | |
4565 | continue; | |
4566 | if (!possible_crtc->enabled) { | |
4567 | crtc = possible_crtc; | |
4568 | break; | |
4569 | } | |
4570 | if (!supported_crtc) | |
4571 | supported_crtc = possible_crtc; | |
4572 | } | |
4573 | ||
4574 | /* | |
4575 | * If we didn't find an unused CRTC, don't use any. | |
4576 | */ | |
4577 | if (!crtc) { | |
4578 | return NULL; | |
4579 | } | |
4580 | ||
4581 | encoder->crtc = crtc; | |
c1c43977 | 4582 | connector->encoder = encoder; |
21d40d37 | 4583 | intel_encoder->load_detect_temp = true; |
79e53945 JB |
4584 | |
4585 | intel_crtc = to_intel_crtc(crtc); | |
4586 | *dpms_mode = intel_crtc->dpms_mode; | |
4587 | ||
4588 | if (!crtc->enabled) { | |
4589 | if (!mode) | |
4590 | mode = &load_detect_mode; | |
3c4fdcfb | 4591 | drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb); |
79e53945 JB |
4592 | } else { |
4593 | if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) { | |
4594 | crtc_funcs = crtc->helper_private; | |
4595 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); | |
4596 | } | |
4597 | ||
4598 | /* Add this connector to the crtc */ | |
4599 | encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode); | |
4600 | encoder_funcs->commit(encoder); | |
4601 | } | |
4602 | /* let the connector get through one full cycle before testing */ | |
9d0498a2 | 4603 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
79e53945 JB |
4604 | |
4605 | return crtc; | |
4606 | } | |
4607 | ||
c1c43977 ZW |
4608 | void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder, |
4609 | struct drm_connector *connector, int dpms_mode) | |
79e53945 | 4610 | { |
4ef69c7a | 4611 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
4612 | struct drm_device *dev = encoder->dev; |
4613 | struct drm_crtc *crtc = encoder->crtc; | |
4614 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
4615 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; | |
4616 | ||
21d40d37 | 4617 | if (intel_encoder->load_detect_temp) { |
79e53945 | 4618 | encoder->crtc = NULL; |
c1c43977 | 4619 | connector->encoder = NULL; |
21d40d37 | 4620 | intel_encoder->load_detect_temp = false; |
79e53945 JB |
4621 | crtc->enabled = drm_helper_crtc_in_use(crtc); |
4622 | drm_helper_disable_unused_functions(dev); | |
4623 | } | |
4624 | ||
c751ce4f | 4625 | /* Switch crtc and encoder back off if necessary */ |
79e53945 JB |
4626 | if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) { |
4627 | if (encoder->crtc == crtc) | |
4628 | encoder_funcs->dpms(encoder, dpms_mode); | |
4629 | crtc_funcs->dpms(crtc, dpms_mode); | |
4630 | } | |
4631 | } | |
4632 | ||
4633 | /* Returns the clock of the currently programmed mode of the given pipe. */ | |
4634 | static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc) | |
4635 | { | |
4636 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4637 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4638 | int pipe = intel_crtc->pipe; | |
4639 | u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B); | |
4640 | u32 fp; | |
4641 | intel_clock_t clock; | |
4642 | ||
4643 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
4644 | fp = I915_READ((pipe == 0) ? FPA0 : FPB0); | |
4645 | else | |
4646 | fp = I915_READ((pipe == 0) ? FPA1 : FPB1); | |
4647 | ||
4648 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
4649 | if (IS_PINEVIEW(dev)) { |
4650 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
4651 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
4652 | } else { |
4653 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
4654 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
4655 | } | |
4656 | ||
a6c45cf0 | 4657 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
4658 | if (IS_PINEVIEW(dev)) |
4659 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
4660 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
4661 | else |
4662 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
4663 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
4664 | ||
4665 | switch (dpll & DPLL_MODE_MASK) { | |
4666 | case DPLLB_MODE_DAC_SERIAL: | |
4667 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
4668 | 5 : 10; | |
4669 | break; | |
4670 | case DPLLB_MODE_LVDS: | |
4671 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
4672 | 7 : 14; | |
4673 | break; | |
4674 | default: | |
28c97730 | 4675 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 JB |
4676 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
4677 | return 0; | |
4678 | } | |
4679 | ||
4680 | /* XXX: Handle the 100Mhz refclk */ | |
2177832f | 4681 | intel_clock(dev, 96000, &clock); |
79e53945 JB |
4682 | } else { |
4683 | bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN); | |
4684 | ||
4685 | if (is_lvds) { | |
4686 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
4687 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
4688 | clock.p2 = 14; | |
4689 | ||
4690 | if ((dpll & PLL_REF_INPUT_MASK) == | |
4691 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { | |
4692 | /* XXX: might not be 66MHz */ | |
2177832f | 4693 | intel_clock(dev, 66000, &clock); |
79e53945 | 4694 | } else |
2177832f | 4695 | intel_clock(dev, 48000, &clock); |
79e53945 JB |
4696 | } else { |
4697 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
4698 | clock.p1 = 2; | |
4699 | else { | |
4700 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
4701 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
4702 | } | |
4703 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
4704 | clock.p2 = 4; | |
4705 | else | |
4706 | clock.p2 = 2; | |
4707 | ||
2177832f | 4708 | intel_clock(dev, 48000, &clock); |
79e53945 JB |
4709 | } |
4710 | } | |
4711 | ||
4712 | /* XXX: It would be nice to validate the clocks, but we can't reuse | |
4713 | * i830PllIsValid() because it relies on the xf86_config connector | |
4714 | * configuration being accurate, which it isn't necessarily. | |
4715 | */ | |
4716 | ||
4717 | return clock.dot; | |
4718 | } | |
4719 | ||
4720 | /** Returns the currently programmed mode of the given pipe. */ | |
4721 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
4722 | struct drm_crtc *crtc) | |
4723 | { | |
4724 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4725 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4726 | int pipe = intel_crtc->pipe; | |
4727 | struct drm_display_mode *mode; | |
4728 | int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B); | |
4729 | int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B); | |
4730 | int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B); | |
4731 | int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B); | |
4732 | ||
4733 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
4734 | if (!mode) | |
4735 | return NULL; | |
4736 | ||
4737 | mode->clock = intel_crtc_clock_get(dev, crtc); | |
4738 | mode->hdisplay = (htot & 0xffff) + 1; | |
4739 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
4740 | mode->hsync_start = (hsync & 0xffff) + 1; | |
4741 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
4742 | mode->vdisplay = (vtot & 0xffff) + 1; | |
4743 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
4744 | mode->vsync_start = (vsync & 0xffff) + 1; | |
4745 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
4746 | ||
4747 | drm_mode_set_name(mode); | |
4748 | drm_mode_set_crtcinfo(mode, 0); | |
4749 | ||
4750 | return mode; | |
4751 | } | |
4752 | ||
652c393a JB |
4753 | #define GPU_IDLE_TIMEOUT 500 /* ms */ |
4754 | ||
4755 | /* When this timer fires, we've been idle for awhile */ | |
4756 | static void intel_gpu_idle_timer(unsigned long arg) | |
4757 | { | |
4758 | struct drm_device *dev = (struct drm_device *)arg; | |
4759 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4760 | ||
ff7ea4c0 CW |
4761 | if (!list_empty(&dev_priv->mm.active_list)) { |
4762 | /* Still processing requests, so just re-arm the timer. */ | |
4763 | mod_timer(&dev_priv->idle_timer, jiffies + | |
4764 | msecs_to_jiffies(GPU_IDLE_TIMEOUT)); | |
4765 | return; | |
4766 | } | |
652c393a | 4767 | |
ff7ea4c0 | 4768 | dev_priv->busy = false; |
01dfba93 | 4769 | queue_work(dev_priv->wq, &dev_priv->idle_work); |
652c393a JB |
4770 | } |
4771 | ||
652c393a JB |
4772 | #define CRTC_IDLE_TIMEOUT 1000 /* ms */ |
4773 | ||
4774 | static void intel_crtc_idle_timer(unsigned long arg) | |
4775 | { | |
4776 | struct intel_crtc *intel_crtc = (struct intel_crtc *)arg; | |
4777 | struct drm_crtc *crtc = &intel_crtc->base; | |
4778 | drm_i915_private_t *dev_priv = crtc->dev->dev_private; | |
ff7ea4c0 | 4779 | struct intel_framebuffer *intel_fb; |
652c393a | 4780 | |
ff7ea4c0 CW |
4781 | intel_fb = to_intel_framebuffer(crtc->fb); |
4782 | if (intel_fb && intel_fb->obj->active) { | |
4783 | /* The framebuffer is still being accessed by the GPU. */ | |
4784 | mod_timer(&intel_crtc->idle_timer, jiffies + | |
4785 | msecs_to_jiffies(CRTC_IDLE_TIMEOUT)); | |
4786 | return; | |
4787 | } | |
652c393a | 4788 | |
ff7ea4c0 | 4789 | intel_crtc->busy = false; |
01dfba93 | 4790 | queue_work(dev_priv->wq, &dev_priv->idle_work); |
652c393a JB |
4791 | } |
4792 | ||
3dec0095 | 4793 | static void intel_increase_pllclock(struct drm_crtc *crtc) |
652c393a JB |
4794 | { |
4795 | struct drm_device *dev = crtc->dev; | |
4796 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4797 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4798 | int pipe = intel_crtc->pipe; | |
4799 | int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; | |
4800 | int dpll = I915_READ(dpll_reg); | |
4801 | ||
bad720ff | 4802 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
4803 | return; |
4804 | ||
4805 | if (!dev_priv->lvds_downclock_avail) | |
4806 | return; | |
4807 | ||
4808 | if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { | |
44d98a61 | 4809 | DRM_DEBUG_DRIVER("upclocking LVDS\n"); |
652c393a JB |
4810 | |
4811 | /* Unlock panel regs */ | |
4a655f04 JB |
4812 | I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | |
4813 | PANEL_UNLOCK_REGS); | |
652c393a JB |
4814 | |
4815 | dpll &= ~DISPLAY_RATE_SELECT_FPA1; | |
4816 | I915_WRITE(dpll_reg, dpll); | |
4817 | dpll = I915_READ(dpll_reg); | |
9d0498a2 | 4818 | intel_wait_for_vblank(dev, pipe); |
652c393a JB |
4819 | dpll = I915_READ(dpll_reg); |
4820 | if (dpll & DISPLAY_RATE_SELECT_FPA1) | |
44d98a61 | 4821 | DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); |
652c393a JB |
4822 | |
4823 | /* ...and lock them again */ | |
4824 | I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3); | |
4825 | } | |
4826 | ||
4827 | /* Schedule downclock */ | |
3dec0095 DV |
4828 | mod_timer(&intel_crtc->idle_timer, jiffies + |
4829 | msecs_to_jiffies(CRTC_IDLE_TIMEOUT)); | |
652c393a JB |
4830 | } |
4831 | ||
4832 | static void intel_decrease_pllclock(struct drm_crtc *crtc) | |
4833 | { | |
4834 | struct drm_device *dev = crtc->dev; | |
4835 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4836 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4837 | int pipe = intel_crtc->pipe; | |
4838 | int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; | |
4839 | int dpll = I915_READ(dpll_reg); | |
4840 | ||
bad720ff | 4841 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
4842 | return; |
4843 | ||
4844 | if (!dev_priv->lvds_downclock_avail) | |
4845 | return; | |
4846 | ||
4847 | /* | |
4848 | * Since this is called by a timer, we should never get here in | |
4849 | * the manual case. | |
4850 | */ | |
4851 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { | |
44d98a61 | 4852 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
652c393a JB |
4853 | |
4854 | /* Unlock panel regs */ | |
4a655f04 JB |
4855 | I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | |
4856 | PANEL_UNLOCK_REGS); | |
652c393a JB |
4857 | |
4858 | dpll |= DISPLAY_RATE_SELECT_FPA1; | |
4859 | I915_WRITE(dpll_reg, dpll); | |
4860 | dpll = I915_READ(dpll_reg); | |
9d0498a2 | 4861 | intel_wait_for_vblank(dev, pipe); |
652c393a JB |
4862 | dpll = I915_READ(dpll_reg); |
4863 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) | |
44d98a61 | 4864 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
652c393a JB |
4865 | |
4866 | /* ...and lock them again */ | |
4867 | I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3); | |
4868 | } | |
4869 | ||
4870 | } | |
4871 | ||
4872 | /** | |
4873 | * intel_idle_update - adjust clocks for idleness | |
4874 | * @work: work struct | |
4875 | * | |
4876 | * Either the GPU or display (or both) went idle. Check the busy status | |
4877 | * here and adjust the CRTC and GPU clocks as necessary. | |
4878 | */ | |
4879 | static void intel_idle_update(struct work_struct *work) | |
4880 | { | |
4881 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, | |
4882 | idle_work); | |
4883 | struct drm_device *dev = dev_priv->dev; | |
4884 | struct drm_crtc *crtc; | |
4885 | struct intel_crtc *intel_crtc; | |
45ac22c8 | 4886 | int enabled = 0; |
652c393a JB |
4887 | |
4888 | if (!i915_powersave) | |
4889 | return; | |
4890 | ||
4891 | mutex_lock(&dev->struct_mutex); | |
4892 | ||
7648fa99 JB |
4893 | i915_update_gfx_val(dev_priv); |
4894 | ||
652c393a JB |
4895 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
4896 | /* Skip inactive CRTCs */ | |
4897 | if (!crtc->fb) | |
4898 | continue; | |
4899 | ||
45ac22c8 | 4900 | enabled++; |
652c393a JB |
4901 | intel_crtc = to_intel_crtc(crtc); |
4902 | if (!intel_crtc->busy) | |
4903 | intel_decrease_pllclock(crtc); | |
4904 | } | |
4905 | ||
45ac22c8 LP |
4906 | if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) { |
4907 | DRM_DEBUG_DRIVER("enable memory self refresh on 945\n"); | |
4908 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN); | |
4909 | } | |
4910 | ||
652c393a JB |
4911 | mutex_unlock(&dev->struct_mutex); |
4912 | } | |
4913 | ||
4914 | /** | |
4915 | * intel_mark_busy - mark the GPU and possibly the display busy | |
4916 | * @dev: drm device | |
4917 | * @obj: object we're operating on | |
4918 | * | |
4919 | * Callers can use this function to indicate that the GPU is busy processing | |
4920 | * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout | |
4921 | * buffer), we'll also mark the display as busy, so we know to increase its | |
4922 | * clock frequency. | |
4923 | */ | |
05394f39 | 4924 | void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj) |
652c393a JB |
4925 | { |
4926 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4927 | struct drm_crtc *crtc = NULL; | |
4928 | struct intel_framebuffer *intel_fb; | |
4929 | struct intel_crtc *intel_crtc; | |
4930 | ||
5e17ee74 ZW |
4931 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
4932 | return; | |
4933 | ||
060e645a LP |
4934 | if (!dev_priv->busy) { |
4935 | if (IS_I945G(dev) || IS_I945GM(dev)) { | |
4936 | u32 fw_blc_self; | |
ee980b80 | 4937 | |
060e645a LP |
4938 | DRM_DEBUG_DRIVER("disable memory self refresh on 945\n"); |
4939 | fw_blc_self = I915_READ(FW_BLC_SELF); | |
4940 | fw_blc_self &= ~FW_BLC_SELF_EN; | |
4941 | I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK); | |
4942 | } | |
28cf798f | 4943 | dev_priv->busy = true; |
060e645a | 4944 | } else |
28cf798f CW |
4945 | mod_timer(&dev_priv->idle_timer, jiffies + |
4946 | msecs_to_jiffies(GPU_IDLE_TIMEOUT)); | |
652c393a JB |
4947 | |
4948 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
4949 | if (!crtc->fb) | |
4950 | continue; | |
4951 | ||
4952 | intel_crtc = to_intel_crtc(crtc); | |
4953 | intel_fb = to_intel_framebuffer(crtc->fb); | |
4954 | if (intel_fb->obj == obj) { | |
4955 | if (!intel_crtc->busy) { | |
060e645a LP |
4956 | if (IS_I945G(dev) || IS_I945GM(dev)) { |
4957 | u32 fw_blc_self; | |
4958 | ||
4959 | DRM_DEBUG_DRIVER("disable memory self refresh on 945\n"); | |
4960 | fw_blc_self = I915_READ(FW_BLC_SELF); | |
4961 | fw_blc_self &= ~FW_BLC_SELF_EN; | |
4962 | I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK); | |
4963 | } | |
652c393a | 4964 | /* Non-busy -> busy, upclock */ |
3dec0095 | 4965 | intel_increase_pllclock(crtc); |
652c393a JB |
4966 | intel_crtc->busy = true; |
4967 | } else { | |
4968 | /* Busy -> busy, put off timer */ | |
4969 | mod_timer(&intel_crtc->idle_timer, jiffies + | |
4970 | msecs_to_jiffies(CRTC_IDLE_TIMEOUT)); | |
4971 | } | |
4972 | } | |
4973 | } | |
4974 | } | |
4975 | ||
79e53945 JB |
4976 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
4977 | { | |
4978 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
4979 | struct drm_device *dev = crtc->dev; |
4980 | struct intel_unpin_work *work; | |
4981 | unsigned long flags; | |
4982 | ||
4983 | spin_lock_irqsave(&dev->event_lock, flags); | |
4984 | work = intel_crtc->unpin_work; | |
4985 | intel_crtc->unpin_work = NULL; | |
4986 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
4987 | ||
4988 | if (work) { | |
4989 | cancel_work_sync(&work->work); | |
4990 | kfree(work); | |
4991 | } | |
79e53945 JB |
4992 | |
4993 | drm_crtc_cleanup(crtc); | |
67e77c5a | 4994 | |
79e53945 JB |
4995 | kfree(intel_crtc); |
4996 | } | |
4997 | ||
6b95a207 KH |
4998 | static void intel_unpin_work_fn(struct work_struct *__work) |
4999 | { | |
5000 | struct intel_unpin_work *work = | |
5001 | container_of(__work, struct intel_unpin_work, work); | |
5002 | ||
5003 | mutex_lock(&work->dev->struct_mutex); | |
b1b87f6b | 5004 | i915_gem_object_unpin(work->old_fb_obj); |
05394f39 CW |
5005 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
5006 | drm_gem_object_unreference(&work->old_fb_obj->base); | |
d9e86c0e | 5007 | |
6b95a207 KH |
5008 | mutex_unlock(&work->dev->struct_mutex); |
5009 | kfree(work); | |
5010 | } | |
5011 | ||
1afe3e9d JB |
5012 | static void do_intel_finish_page_flip(struct drm_device *dev, |
5013 | struct drm_crtc *crtc) | |
6b95a207 KH |
5014 | { |
5015 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6b95a207 KH |
5016 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5017 | struct intel_unpin_work *work; | |
05394f39 | 5018 | struct drm_i915_gem_object *obj; |
6b95a207 KH |
5019 | struct drm_pending_vblank_event *e; |
5020 | struct timeval now; | |
5021 | unsigned long flags; | |
5022 | ||
5023 | /* Ignore early vblank irqs */ | |
5024 | if (intel_crtc == NULL) | |
5025 | return; | |
5026 | ||
5027 | spin_lock_irqsave(&dev->event_lock, flags); | |
5028 | work = intel_crtc->unpin_work; | |
5029 | if (work == NULL || !work->pending) { | |
5030 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
5031 | return; | |
5032 | } | |
5033 | ||
5034 | intel_crtc->unpin_work = NULL; | |
5035 | drm_vblank_put(dev, intel_crtc->pipe); | |
5036 | ||
5037 | if (work->event) { | |
5038 | e = work->event; | |
5039 | do_gettimeofday(&now); | |
5040 | e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe); | |
5041 | e->event.tv_sec = now.tv_sec; | |
5042 | e->event.tv_usec = now.tv_usec; | |
5043 | list_add_tail(&e->base.link, | |
5044 | &e->base.file_priv->event_list); | |
5045 | wake_up_interruptible(&e->base.file_priv->event_wait); | |
5046 | } | |
5047 | ||
5048 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
5049 | ||
05394f39 | 5050 | obj = work->old_fb_obj; |
d9e86c0e | 5051 | |
e59f2bac | 5052 | atomic_clear_mask(1 << intel_crtc->plane, |
05394f39 CW |
5053 | &obj->pending_flip.counter); |
5054 | if (atomic_read(&obj->pending_flip) == 0) | |
f787a5f5 | 5055 | wake_up(&dev_priv->pending_flip_queue); |
d9e86c0e | 5056 | |
6b95a207 | 5057 | schedule_work(&work->work); |
e5510fac JB |
5058 | |
5059 | trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj); | |
6b95a207 KH |
5060 | } |
5061 | ||
1afe3e9d JB |
5062 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
5063 | { | |
5064 | drm_i915_private_t *dev_priv = dev->dev_private; | |
5065 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
5066 | ||
5067 | do_intel_finish_page_flip(dev, crtc); | |
5068 | } | |
5069 | ||
5070 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
5071 | { | |
5072 | drm_i915_private_t *dev_priv = dev->dev_private; | |
5073 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; | |
5074 | ||
5075 | do_intel_finish_page_flip(dev, crtc); | |
5076 | } | |
5077 | ||
6b95a207 KH |
5078 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
5079 | { | |
5080 | drm_i915_private_t *dev_priv = dev->dev_private; | |
5081 | struct intel_crtc *intel_crtc = | |
5082 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
5083 | unsigned long flags; | |
5084 | ||
5085 | spin_lock_irqsave(&dev->event_lock, flags); | |
de3f440f | 5086 | if (intel_crtc->unpin_work) { |
4e5359cd SF |
5087 | if ((++intel_crtc->unpin_work->pending) > 1) |
5088 | DRM_ERROR("Prepared flip multiple times\n"); | |
de3f440f JB |
5089 | } else { |
5090 | DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n"); | |
5091 | } | |
6b95a207 KH |
5092 | spin_unlock_irqrestore(&dev->event_lock, flags); |
5093 | } | |
5094 | ||
5095 | static int intel_crtc_page_flip(struct drm_crtc *crtc, | |
5096 | struct drm_framebuffer *fb, | |
5097 | struct drm_pending_vblank_event *event) | |
5098 | { | |
5099 | struct drm_device *dev = crtc->dev; | |
5100 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5101 | struct intel_framebuffer *intel_fb; | |
05394f39 | 5102 | struct drm_i915_gem_object *obj; |
6b95a207 KH |
5103 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5104 | struct intel_unpin_work *work; | |
be9a3dbf | 5105 | unsigned long flags, offset; |
52e68630 | 5106 | int pipe = intel_crtc->pipe; |
20f0cd55 | 5107 | u32 pf, pipesrc; |
52e68630 | 5108 | int ret; |
6b95a207 KH |
5109 | |
5110 | work = kzalloc(sizeof *work, GFP_KERNEL); | |
5111 | if (work == NULL) | |
5112 | return -ENOMEM; | |
5113 | ||
6b95a207 KH |
5114 | work->event = event; |
5115 | work->dev = crtc->dev; | |
5116 | intel_fb = to_intel_framebuffer(crtc->fb); | |
b1b87f6b | 5117 | work->old_fb_obj = intel_fb->obj; |
6b95a207 KH |
5118 | INIT_WORK(&work->work, intel_unpin_work_fn); |
5119 | ||
5120 | /* We borrow the event spin lock for protecting unpin_work */ | |
5121 | spin_lock_irqsave(&dev->event_lock, flags); | |
5122 | if (intel_crtc->unpin_work) { | |
5123 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
5124 | kfree(work); | |
468f0b44 CW |
5125 | |
5126 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
6b95a207 KH |
5127 | return -EBUSY; |
5128 | } | |
5129 | intel_crtc->unpin_work = work; | |
5130 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
5131 | ||
5132 | intel_fb = to_intel_framebuffer(fb); | |
5133 | obj = intel_fb->obj; | |
5134 | ||
468f0b44 | 5135 | mutex_lock(&dev->struct_mutex); |
1ec14ad3 | 5136 | ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv)); |
96b099fd CW |
5137 | if (ret) |
5138 | goto cleanup_work; | |
6b95a207 | 5139 | |
75dfca80 | 5140 | /* Reference the objects for the scheduled work. */ |
05394f39 CW |
5141 | drm_gem_object_reference(&work->old_fb_obj->base); |
5142 | drm_gem_object_reference(&obj->base); | |
6b95a207 KH |
5143 | |
5144 | crtc->fb = fb; | |
96b099fd CW |
5145 | |
5146 | ret = drm_vblank_get(dev, intel_crtc->pipe); | |
5147 | if (ret) | |
5148 | goto cleanup_objs; | |
5149 | ||
c7f9f9a8 CW |
5150 | if (IS_GEN3(dev) || IS_GEN2(dev)) { |
5151 | u32 flip_mask; | |
48b956c5 | 5152 | |
c7f9f9a8 CW |
5153 | /* Can't queue multiple flips, so wait for the previous |
5154 | * one to finish before executing the next. | |
5155 | */ | |
e1f99ce6 CW |
5156 | ret = BEGIN_LP_RING(2); |
5157 | if (ret) | |
5158 | goto cleanup_objs; | |
5159 | ||
c7f9f9a8 CW |
5160 | if (intel_crtc->plane) |
5161 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
5162 | else | |
5163 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
5164 | OUT_RING(MI_WAIT_FOR_EVENT | flip_mask); | |
5165 | OUT_RING(MI_NOOP); | |
6146b3d6 DV |
5166 | ADVANCE_LP_RING(); |
5167 | } | |
83f7fd05 | 5168 | |
e1f99ce6 | 5169 | work->pending_flip_obj = obj; |
e1f99ce6 | 5170 | |
4e5359cd SF |
5171 | work->enable_stall_check = true; |
5172 | ||
be9a3dbf | 5173 | /* Offset into the new buffer for cases of shared fbs between CRTCs */ |
52e68630 | 5174 | offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8; |
be9a3dbf | 5175 | |
e1f99ce6 CW |
5176 | ret = BEGIN_LP_RING(4); |
5177 | if (ret) | |
5178 | goto cleanup_objs; | |
5179 | ||
5180 | /* Block clients from rendering to the new back buffer until | |
5181 | * the flip occurs and the object is no longer visible. | |
5182 | */ | |
05394f39 | 5183 | atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip); |
e1f99ce6 CW |
5184 | |
5185 | switch (INTEL_INFO(dev)->gen) { | |
52e68630 | 5186 | case 2: |
1afe3e9d JB |
5187 | OUT_RING(MI_DISPLAY_FLIP | |
5188 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
5189 | OUT_RING(fb->pitch); | |
05394f39 | 5190 | OUT_RING(obj->gtt_offset + offset); |
52e68630 CW |
5191 | OUT_RING(MI_NOOP); |
5192 | break; | |
5193 | ||
5194 | case 3: | |
1afe3e9d JB |
5195 | OUT_RING(MI_DISPLAY_FLIP_I915 | |
5196 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
5197 | OUT_RING(fb->pitch); | |
05394f39 | 5198 | OUT_RING(obj->gtt_offset + offset); |
22fd0fab | 5199 | OUT_RING(MI_NOOP); |
52e68630 CW |
5200 | break; |
5201 | ||
5202 | case 4: | |
5203 | case 5: | |
5204 | /* i965+ uses the linear or tiled offsets from the | |
5205 | * Display Registers (which do not change across a page-flip) | |
5206 | * so we need only reprogram the base address. | |
5207 | */ | |
69d0b96c DV |
5208 | OUT_RING(MI_DISPLAY_FLIP | |
5209 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
5210 | OUT_RING(fb->pitch); | |
05394f39 | 5211 | OUT_RING(obj->gtt_offset | obj->tiling_mode); |
52e68630 CW |
5212 | |
5213 | /* XXX Enabling the panel-fitter across page-flip is so far | |
5214 | * untested on non-native modes, so ignore it for now. | |
5215 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
5216 | */ | |
5217 | pf = 0; | |
5218 | pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff; | |
5219 | OUT_RING(pf | pipesrc); | |
5220 | break; | |
5221 | ||
5222 | case 6: | |
5223 | OUT_RING(MI_DISPLAY_FLIP | | |
5224 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
05394f39 CW |
5225 | OUT_RING(fb->pitch | obj->tiling_mode); |
5226 | OUT_RING(obj->gtt_offset); | |
52e68630 CW |
5227 | |
5228 | pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
5229 | pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff; | |
5230 | OUT_RING(pf | pipesrc); | |
5231 | break; | |
22fd0fab | 5232 | } |
6b95a207 KH |
5233 | ADVANCE_LP_RING(); |
5234 | ||
5235 | mutex_unlock(&dev->struct_mutex); | |
5236 | ||
e5510fac JB |
5237 | trace_i915_flip_request(intel_crtc->plane, obj); |
5238 | ||
6b95a207 | 5239 | return 0; |
96b099fd CW |
5240 | |
5241 | cleanup_objs: | |
05394f39 CW |
5242 | drm_gem_object_unreference(&work->old_fb_obj->base); |
5243 | drm_gem_object_unreference(&obj->base); | |
96b099fd CW |
5244 | cleanup_work: |
5245 | mutex_unlock(&dev->struct_mutex); | |
5246 | ||
5247 | spin_lock_irqsave(&dev->event_lock, flags); | |
5248 | intel_crtc->unpin_work = NULL; | |
5249 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
5250 | ||
5251 | kfree(work); | |
5252 | ||
5253 | return ret; | |
6b95a207 KH |
5254 | } |
5255 | ||
7e7d76c3 | 5256 | static struct drm_crtc_helper_funcs intel_helper_funcs = { |
79e53945 JB |
5257 | .dpms = intel_crtc_dpms, |
5258 | .mode_fixup = intel_crtc_mode_fixup, | |
5259 | .mode_set = intel_crtc_mode_set, | |
5260 | .mode_set_base = intel_pipe_set_base, | |
81255565 | 5261 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
068143d3 | 5262 | .load_lut = intel_crtc_load_lut, |
cdd59983 | 5263 | .disable = intel_crtc_disable, |
79e53945 JB |
5264 | }; |
5265 | ||
5266 | static const struct drm_crtc_funcs intel_crtc_funcs = { | |
5267 | .cursor_set = intel_crtc_cursor_set, | |
5268 | .cursor_move = intel_crtc_cursor_move, | |
5269 | .gamma_set = intel_crtc_gamma_set, | |
5270 | .set_config = drm_crtc_helper_set_config, | |
5271 | .destroy = intel_crtc_destroy, | |
6b95a207 | 5272 | .page_flip = intel_crtc_page_flip, |
79e53945 JB |
5273 | }; |
5274 | ||
47f1c6c9 CW |
5275 | static void intel_sanitize_modesetting(struct drm_device *dev, |
5276 | int pipe, int plane) | |
5277 | { | |
5278 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5279 | u32 reg, val; | |
5280 | ||
5281 | if (HAS_PCH_SPLIT(dev)) | |
5282 | return; | |
5283 | ||
5284 | /* Who knows what state these registers were left in by the BIOS or | |
5285 | * grub? | |
5286 | * | |
5287 | * If we leave the registers in a conflicting state (e.g. with the | |
5288 | * display plane reading from the other pipe than the one we intend | |
5289 | * to use) then when we attempt to teardown the active mode, we will | |
5290 | * not disable the pipes and planes in the correct order -- leaving | |
5291 | * a plane reading from a disabled pipe and possibly leading to | |
5292 | * undefined behaviour. | |
5293 | */ | |
5294 | ||
5295 | reg = DSPCNTR(plane); | |
5296 | val = I915_READ(reg); | |
5297 | ||
5298 | if ((val & DISPLAY_PLANE_ENABLE) == 0) | |
5299 | return; | |
5300 | if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe) | |
5301 | return; | |
5302 | ||
5303 | /* This display plane is active and attached to the other CPU pipe. */ | |
5304 | pipe = !pipe; | |
5305 | ||
5306 | /* Disable the plane and wait for it to stop reading from the pipe. */ | |
5307 | I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE); | |
5308 | intel_flush_display_plane(dev, plane); | |
5309 | ||
5310 | if (IS_GEN2(dev)) | |
5311 | intel_wait_for_vblank(dev, pipe); | |
5312 | ||
5313 | if (pipe == 0 && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
5314 | return; | |
5315 | ||
5316 | /* Switch off the pipe. */ | |
5317 | reg = PIPECONF(pipe); | |
5318 | val = I915_READ(reg); | |
5319 | if (val & PIPECONF_ENABLE) { | |
5320 | I915_WRITE(reg, val & ~PIPECONF_ENABLE); | |
5321 | intel_wait_for_pipe_off(dev, pipe); | |
5322 | } | |
5323 | } | |
79e53945 | 5324 | |
b358d0a6 | 5325 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 5326 | { |
22fd0fab | 5327 | drm_i915_private_t *dev_priv = dev->dev_private; |
79e53945 JB |
5328 | struct intel_crtc *intel_crtc; |
5329 | int i; | |
5330 | ||
5331 | intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); | |
5332 | if (intel_crtc == NULL) | |
5333 | return; | |
5334 | ||
5335 | drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs); | |
5336 | ||
5337 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
5338 | for (i = 0; i < 256; i++) { |
5339 | intel_crtc->lut_r[i] = i; | |
5340 | intel_crtc->lut_g[i] = i; | |
5341 | intel_crtc->lut_b[i] = i; | |
5342 | } | |
5343 | ||
80824003 JB |
5344 | /* Swap pipes & planes for FBC on pre-965 */ |
5345 | intel_crtc->pipe = pipe; | |
5346 | intel_crtc->plane = pipe; | |
e2e767ab | 5347 | if (IS_MOBILE(dev) && IS_GEN3(dev)) { |
28c97730 | 5348 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 5349 | intel_crtc->plane = !pipe; |
80824003 JB |
5350 | } |
5351 | ||
22fd0fab JB |
5352 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
5353 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
5354 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
5355 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
5356 | ||
79e53945 | 5357 | intel_crtc->cursor_addr = 0; |
032d2a0d | 5358 | intel_crtc->dpms_mode = -1; |
e65d9305 | 5359 | intel_crtc->active = true; /* force the pipe off on setup_init_config */ |
7e7d76c3 JB |
5360 | |
5361 | if (HAS_PCH_SPLIT(dev)) { | |
5362 | intel_helper_funcs.prepare = ironlake_crtc_prepare; | |
5363 | intel_helper_funcs.commit = ironlake_crtc_commit; | |
5364 | } else { | |
5365 | intel_helper_funcs.prepare = i9xx_crtc_prepare; | |
5366 | intel_helper_funcs.commit = i9xx_crtc_commit; | |
5367 | } | |
5368 | ||
79e53945 JB |
5369 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
5370 | ||
652c393a JB |
5371 | intel_crtc->busy = false; |
5372 | ||
5373 | setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer, | |
5374 | (unsigned long)intel_crtc); | |
47f1c6c9 CW |
5375 | |
5376 | intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane); | |
79e53945 JB |
5377 | } |
5378 | ||
08d7b3d1 | 5379 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 5380 | struct drm_file *file) |
08d7b3d1 CW |
5381 | { |
5382 | drm_i915_private_t *dev_priv = dev->dev_private; | |
5383 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; | |
c05422d5 DV |
5384 | struct drm_mode_object *drmmode_obj; |
5385 | struct intel_crtc *crtc; | |
08d7b3d1 CW |
5386 | |
5387 | if (!dev_priv) { | |
5388 | DRM_ERROR("called with no initialization\n"); | |
5389 | return -EINVAL; | |
5390 | } | |
5391 | ||
c05422d5 DV |
5392 | drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, |
5393 | DRM_MODE_OBJECT_CRTC); | |
08d7b3d1 | 5394 | |
c05422d5 | 5395 | if (!drmmode_obj) { |
08d7b3d1 CW |
5396 | DRM_ERROR("no such CRTC id\n"); |
5397 | return -EINVAL; | |
5398 | } | |
5399 | ||
c05422d5 DV |
5400 | crtc = to_intel_crtc(obj_to_crtc(drmmode_obj)); |
5401 | pipe_from_crtc_id->pipe = crtc->pipe; | |
08d7b3d1 | 5402 | |
c05422d5 | 5403 | return 0; |
08d7b3d1 CW |
5404 | } |
5405 | ||
c5e4df33 | 5406 | static int intel_encoder_clones(struct drm_device *dev, int type_mask) |
79e53945 | 5407 | { |
4ef69c7a | 5408 | struct intel_encoder *encoder; |
79e53945 | 5409 | int index_mask = 0; |
79e53945 JB |
5410 | int entry = 0; |
5411 | ||
4ef69c7a CW |
5412 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
5413 | if (type_mask & encoder->clone_mask) | |
79e53945 JB |
5414 | index_mask |= (1 << entry); |
5415 | entry++; | |
5416 | } | |
4ef69c7a | 5417 | |
79e53945 JB |
5418 | return index_mask; |
5419 | } | |
5420 | ||
79e53945 JB |
5421 | static void intel_setup_outputs(struct drm_device *dev) |
5422 | { | |
725e30ad | 5423 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 5424 | struct intel_encoder *encoder; |
cb0953d7 | 5425 | bool dpd_is_edp = false; |
c5d1b51d | 5426 | bool has_lvds = false; |
79e53945 | 5427 | |
541998a1 | 5428 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
c5d1b51d CW |
5429 | has_lvds = intel_lvds_init(dev); |
5430 | if (!has_lvds && !HAS_PCH_SPLIT(dev)) { | |
5431 | /* disable the panel fitter on everything but LVDS */ | |
5432 | I915_WRITE(PFIT_CONTROL, 0); | |
5433 | } | |
79e53945 | 5434 | |
bad720ff | 5435 | if (HAS_PCH_SPLIT(dev)) { |
cb0953d7 | 5436 | dpd_is_edp = intel_dpd_is_edp(dev); |
30ad48b7 | 5437 | |
32f9d658 ZW |
5438 | if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED)) |
5439 | intel_dp_init(dev, DP_A); | |
5440 | ||
cb0953d7 AJ |
5441 | if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED)) |
5442 | intel_dp_init(dev, PCH_DP_D); | |
5443 | } | |
5444 | ||
5445 | intel_crt_init(dev); | |
5446 | ||
5447 | if (HAS_PCH_SPLIT(dev)) { | |
5448 | int found; | |
5449 | ||
30ad48b7 | 5450 | if (I915_READ(HDMIB) & PORT_DETECTED) { |
461ed3ca ZY |
5451 | /* PCH SDVOB multiplex with HDMIB */ |
5452 | found = intel_sdvo_init(dev, PCH_SDVOB); | |
30ad48b7 ZW |
5453 | if (!found) |
5454 | intel_hdmi_init(dev, HDMIB); | |
5eb08b69 ZW |
5455 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
5456 | intel_dp_init(dev, PCH_DP_B); | |
30ad48b7 ZW |
5457 | } |
5458 | ||
5459 | if (I915_READ(HDMIC) & PORT_DETECTED) | |
5460 | intel_hdmi_init(dev, HDMIC); | |
5461 | ||
5462 | if (I915_READ(HDMID) & PORT_DETECTED) | |
5463 | intel_hdmi_init(dev, HDMID); | |
5464 | ||
5eb08b69 ZW |
5465 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
5466 | intel_dp_init(dev, PCH_DP_C); | |
5467 | ||
cb0953d7 | 5468 | if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED)) |
5eb08b69 ZW |
5469 | intel_dp_init(dev, PCH_DP_D); |
5470 | ||
103a196f | 5471 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
27185ae1 | 5472 | bool found = false; |
7d57382e | 5473 | |
725e30ad | 5474 | if (I915_READ(SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 5475 | DRM_DEBUG_KMS("probing SDVOB\n"); |
725e30ad | 5476 | found = intel_sdvo_init(dev, SDVOB); |
b01f2c3a JB |
5477 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
5478 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); | |
725e30ad | 5479 | intel_hdmi_init(dev, SDVOB); |
b01f2c3a | 5480 | } |
27185ae1 | 5481 | |
b01f2c3a JB |
5482 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) { |
5483 | DRM_DEBUG_KMS("probing DP_B\n"); | |
a4fc5ed6 | 5484 | intel_dp_init(dev, DP_B); |
b01f2c3a | 5485 | } |
725e30ad | 5486 | } |
13520b05 KH |
5487 | |
5488 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 5489 | |
b01f2c3a JB |
5490 | if (I915_READ(SDVOB) & SDVO_DETECTED) { |
5491 | DRM_DEBUG_KMS("probing SDVOC\n"); | |
725e30ad | 5492 | found = intel_sdvo_init(dev, SDVOC); |
b01f2c3a | 5493 | } |
27185ae1 ML |
5494 | |
5495 | if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) { | |
5496 | ||
b01f2c3a JB |
5497 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
5498 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); | |
725e30ad | 5499 | intel_hdmi_init(dev, SDVOC); |
b01f2c3a JB |
5500 | } |
5501 | if (SUPPORTS_INTEGRATED_DP(dev)) { | |
5502 | DRM_DEBUG_KMS("probing DP_C\n"); | |
a4fc5ed6 | 5503 | intel_dp_init(dev, DP_C); |
b01f2c3a | 5504 | } |
725e30ad | 5505 | } |
27185ae1 | 5506 | |
b01f2c3a JB |
5507 | if (SUPPORTS_INTEGRATED_DP(dev) && |
5508 | (I915_READ(DP_D) & DP_DETECTED)) { | |
5509 | DRM_DEBUG_KMS("probing DP_D\n"); | |
a4fc5ed6 | 5510 | intel_dp_init(dev, DP_D); |
b01f2c3a | 5511 | } |
bad720ff | 5512 | } else if (IS_GEN2(dev)) |
79e53945 JB |
5513 | intel_dvo_init(dev); |
5514 | ||
103a196f | 5515 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
5516 | intel_tv_init(dev); |
5517 | ||
4ef69c7a CW |
5518 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
5519 | encoder->base.possible_crtcs = encoder->crtc_mask; | |
5520 | encoder->base.possible_clones = | |
5521 | intel_encoder_clones(dev, encoder->clone_mask); | |
79e53945 JB |
5522 | } |
5523 | } | |
5524 | ||
5525 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
5526 | { | |
5527 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
79e53945 JB |
5528 | |
5529 | drm_framebuffer_cleanup(fb); | |
05394f39 | 5530 | drm_gem_object_unreference_unlocked(&intel_fb->obj->base); |
79e53945 JB |
5531 | |
5532 | kfree(intel_fb); | |
5533 | } | |
5534 | ||
5535 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 5536 | struct drm_file *file, |
79e53945 JB |
5537 | unsigned int *handle) |
5538 | { | |
5539 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 5540 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 5541 | |
05394f39 | 5542 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
5543 | } |
5544 | ||
5545 | static const struct drm_framebuffer_funcs intel_fb_funcs = { | |
5546 | .destroy = intel_user_framebuffer_destroy, | |
5547 | .create_handle = intel_user_framebuffer_create_handle, | |
5548 | }; | |
5549 | ||
38651674 DA |
5550 | int intel_framebuffer_init(struct drm_device *dev, |
5551 | struct intel_framebuffer *intel_fb, | |
5552 | struct drm_mode_fb_cmd *mode_cmd, | |
05394f39 | 5553 | struct drm_i915_gem_object *obj) |
79e53945 | 5554 | { |
79e53945 JB |
5555 | int ret; |
5556 | ||
05394f39 | 5557 | if (obj->tiling_mode == I915_TILING_Y) |
57cd6508 CW |
5558 | return -EINVAL; |
5559 | ||
5560 | if (mode_cmd->pitch & 63) | |
5561 | return -EINVAL; | |
5562 | ||
5563 | switch (mode_cmd->bpp) { | |
5564 | case 8: | |
5565 | case 16: | |
5566 | case 24: | |
5567 | case 32: | |
5568 | break; | |
5569 | default: | |
5570 | return -EINVAL; | |
5571 | } | |
5572 | ||
79e53945 JB |
5573 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
5574 | if (ret) { | |
5575 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
5576 | return ret; | |
5577 | } | |
5578 | ||
5579 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); | |
79e53945 | 5580 | intel_fb->obj = obj; |
79e53945 JB |
5581 | return 0; |
5582 | } | |
5583 | ||
79e53945 JB |
5584 | static struct drm_framebuffer * |
5585 | intel_user_framebuffer_create(struct drm_device *dev, | |
5586 | struct drm_file *filp, | |
5587 | struct drm_mode_fb_cmd *mode_cmd) | |
5588 | { | |
05394f39 | 5589 | struct drm_i915_gem_object *obj; |
38651674 | 5590 | struct intel_framebuffer *intel_fb; |
79e53945 JB |
5591 | int ret; |
5592 | ||
05394f39 | 5593 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle)); |
79e53945 | 5594 | if (!obj) |
cce13ff7 | 5595 | return ERR_PTR(-ENOENT); |
79e53945 | 5596 | |
38651674 DA |
5597 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
5598 | if (!intel_fb) | |
cce13ff7 | 5599 | return ERR_PTR(-ENOMEM); |
38651674 | 5600 | |
05394f39 | 5601 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); |
79e53945 | 5602 | if (ret) { |
05394f39 | 5603 | drm_gem_object_unreference_unlocked(&obj->base); |
38651674 | 5604 | kfree(intel_fb); |
cce13ff7 | 5605 | return ERR_PTR(ret); |
79e53945 JB |
5606 | } |
5607 | ||
38651674 | 5608 | return &intel_fb->base; |
79e53945 JB |
5609 | } |
5610 | ||
79e53945 | 5611 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 5612 | .fb_create = intel_user_framebuffer_create, |
eb1f8e4f | 5613 | .output_poll_changed = intel_fb_output_poll_changed, |
79e53945 JB |
5614 | }; |
5615 | ||
05394f39 | 5616 | static struct drm_i915_gem_object * |
aa40d6bb | 5617 | intel_alloc_context_page(struct drm_device *dev) |
9ea8d059 | 5618 | { |
05394f39 | 5619 | struct drm_i915_gem_object *ctx; |
9ea8d059 CW |
5620 | int ret; |
5621 | ||
aa40d6bb ZN |
5622 | ctx = i915_gem_alloc_object(dev, 4096); |
5623 | if (!ctx) { | |
9ea8d059 CW |
5624 | DRM_DEBUG("failed to alloc power context, RC6 disabled\n"); |
5625 | return NULL; | |
5626 | } | |
5627 | ||
5628 | mutex_lock(&dev->struct_mutex); | |
75e9e915 | 5629 | ret = i915_gem_object_pin(ctx, 4096, true); |
9ea8d059 CW |
5630 | if (ret) { |
5631 | DRM_ERROR("failed to pin power context: %d\n", ret); | |
5632 | goto err_unref; | |
5633 | } | |
5634 | ||
aa40d6bb | 5635 | ret = i915_gem_object_set_to_gtt_domain(ctx, 1); |
9ea8d059 CW |
5636 | if (ret) { |
5637 | DRM_ERROR("failed to set-domain on power context: %d\n", ret); | |
5638 | goto err_unpin; | |
5639 | } | |
5640 | mutex_unlock(&dev->struct_mutex); | |
5641 | ||
aa40d6bb | 5642 | return ctx; |
9ea8d059 CW |
5643 | |
5644 | err_unpin: | |
aa40d6bb | 5645 | i915_gem_object_unpin(ctx); |
9ea8d059 | 5646 | err_unref: |
05394f39 | 5647 | drm_gem_object_unreference(&ctx->base); |
9ea8d059 CW |
5648 | mutex_unlock(&dev->struct_mutex); |
5649 | return NULL; | |
5650 | } | |
5651 | ||
7648fa99 JB |
5652 | bool ironlake_set_drps(struct drm_device *dev, u8 val) |
5653 | { | |
5654 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5655 | u16 rgvswctl; | |
5656 | ||
5657 | rgvswctl = I915_READ16(MEMSWCTL); | |
5658 | if (rgvswctl & MEMCTL_CMD_STS) { | |
5659 | DRM_DEBUG("gpu busy, RCS change rejected\n"); | |
5660 | return false; /* still busy with another command */ | |
5661 | } | |
5662 | ||
5663 | rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) | | |
5664 | (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM; | |
5665 | I915_WRITE16(MEMSWCTL, rgvswctl); | |
5666 | POSTING_READ16(MEMSWCTL); | |
5667 | ||
5668 | rgvswctl |= MEMCTL_CMD_STS; | |
5669 | I915_WRITE16(MEMSWCTL, rgvswctl); | |
5670 | ||
5671 | return true; | |
5672 | } | |
5673 | ||
f97108d1 JB |
5674 | void ironlake_enable_drps(struct drm_device *dev) |
5675 | { | |
5676 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7648fa99 | 5677 | u32 rgvmodectl = I915_READ(MEMMODECTL); |
f97108d1 | 5678 | u8 fmax, fmin, fstart, vstart; |
f97108d1 | 5679 | |
ea056c14 JB |
5680 | /* Enable temp reporting */ |
5681 | I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN); | |
5682 | I915_WRITE16(TSC1, I915_READ(TSC1) | TSE); | |
5683 | ||
f97108d1 JB |
5684 | /* 100ms RC evaluation intervals */ |
5685 | I915_WRITE(RCUPEI, 100000); | |
5686 | I915_WRITE(RCDNEI, 100000); | |
5687 | ||
5688 | /* Set max/min thresholds to 90ms and 80ms respectively */ | |
5689 | I915_WRITE(RCBMAXAVG, 90000); | |
5690 | I915_WRITE(RCBMINAVG, 80000); | |
5691 | ||
5692 | I915_WRITE(MEMIHYST, 1); | |
5693 | ||
5694 | /* Set up min, max, and cur for interrupt handling */ | |
5695 | fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT; | |
5696 | fmin = (rgvmodectl & MEMMODE_FMIN_MASK); | |
5697 | fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >> | |
5698 | MEMMODE_FSTART_SHIFT; | |
7648fa99 | 5699 | |
f97108d1 JB |
5700 | vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >> |
5701 | PXVFREQ_PX_SHIFT; | |
5702 | ||
80dbf4b7 | 5703 | dev_priv->fmax = fmax; /* IPS callback will increase this */ |
7648fa99 JB |
5704 | dev_priv->fstart = fstart; |
5705 | ||
80dbf4b7 | 5706 | dev_priv->max_delay = fstart; |
f97108d1 JB |
5707 | dev_priv->min_delay = fmin; |
5708 | dev_priv->cur_delay = fstart; | |
5709 | ||
80dbf4b7 JB |
5710 | DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", |
5711 | fmax, fmin, fstart); | |
7648fa99 | 5712 | |
f97108d1 JB |
5713 | I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN); |
5714 | ||
5715 | /* | |
5716 | * Interrupts will be enabled in ironlake_irq_postinstall | |
5717 | */ | |
5718 | ||
5719 | I915_WRITE(VIDSTART, vstart); | |
5720 | POSTING_READ(VIDSTART); | |
5721 | ||
5722 | rgvmodectl |= MEMMODE_SWMODE_EN; | |
5723 | I915_WRITE(MEMMODECTL, rgvmodectl); | |
5724 | ||
481b6af3 | 5725 | if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10)) |
913d8d11 | 5726 | DRM_ERROR("stuck trying to change perf mode\n"); |
f97108d1 JB |
5727 | msleep(1); |
5728 | ||
7648fa99 | 5729 | ironlake_set_drps(dev, fstart); |
f97108d1 | 5730 | |
7648fa99 JB |
5731 | dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) + |
5732 | I915_READ(0x112e0); | |
5733 | dev_priv->last_time1 = jiffies_to_msecs(jiffies); | |
5734 | dev_priv->last_count2 = I915_READ(0x112f4); | |
5735 | getrawmonotonic(&dev_priv->last_time2); | |
f97108d1 JB |
5736 | } |
5737 | ||
5738 | void ironlake_disable_drps(struct drm_device *dev) | |
5739 | { | |
5740 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7648fa99 | 5741 | u16 rgvswctl = I915_READ16(MEMSWCTL); |
f97108d1 JB |
5742 | |
5743 | /* Ack interrupts, disable EFC interrupt */ | |
5744 | I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN); | |
5745 | I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG); | |
5746 | I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT); | |
5747 | I915_WRITE(DEIIR, DE_PCU_EVENT); | |
5748 | I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT); | |
5749 | ||
5750 | /* Go back to the starting frequency */ | |
7648fa99 | 5751 | ironlake_set_drps(dev, dev_priv->fstart); |
f97108d1 JB |
5752 | msleep(1); |
5753 | rgvswctl |= MEMCTL_CMD_STS; | |
5754 | I915_WRITE(MEMSWCTL, rgvswctl); | |
5755 | msleep(1); | |
5756 | ||
5757 | } | |
5758 | ||
7648fa99 JB |
5759 | static unsigned long intel_pxfreq(u32 vidfreq) |
5760 | { | |
5761 | unsigned long freq; | |
5762 | int div = (vidfreq & 0x3f0000) >> 16; | |
5763 | int post = (vidfreq & 0x3000) >> 12; | |
5764 | int pre = (vidfreq & 0x7); | |
5765 | ||
5766 | if (!pre) | |
5767 | return 0; | |
5768 | ||
5769 | freq = ((div * 133333) / ((1<<post) * pre)); | |
5770 | ||
5771 | return freq; | |
5772 | } | |
5773 | ||
5774 | void intel_init_emon(struct drm_device *dev) | |
5775 | { | |
5776 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5777 | u32 lcfuse; | |
5778 | u8 pxw[16]; | |
5779 | int i; | |
5780 | ||
5781 | /* Disable to program */ | |
5782 | I915_WRITE(ECR, 0); | |
5783 | POSTING_READ(ECR); | |
5784 | ||
5785 | /* Program energy weights for various events */ | |
5786 | I915_WRITE(SDEW, 0x15040d00); | |
5787 | I915_WRITE(CSIEW0, 0x007f0000); | |
5788 | I915_WRITE(CSIEW1, 0x1e220004); | |
5789 | I915_WRITE(CSIEW2, 0x04000004); | |
5790 | ||
5791 | for (i = 0; i < 5; i++) | |
5792 | I915_WRITE(PEW + (i * 4), 0); | |
5793 | for (i = 0; i < 3; i++) | |
5794 | I915_WRITE(DEW + (i * 4), 0); | |
5795 | ||
5796 | /* Program P-state weights to account for frequency power adjustment */ | |
5797 | for (i = 0; i < 16; i++) { | |
5798 | u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4)); | |
5799 | unsigned long freq = intel_pxfreq(pxvidfreq); | |
5800 | unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >> | |
5801 | PXVFREQ_PX_SHIFT; | |
5802 | unsigned long val; | |
5803 | ||
5804 | val = vid * vid; | |
5805 | val *= (freq / 1000); | |
5806 | val *= 255; | |
5807 | val /= (127*127*900); | |
5808 | if (val > 0xff) | |
5809 | DRM_ERROR("bad pxval: %ld\n", val); | |
5810 | pxw[i] = val; | |
5811 | } | |
5812 | /* Render standby states get 0 weight */ | |
5813 | pxw[14] = 0; | |
5814 | pxw[15] = 0; | |
5815 | ||
5816 | for (i = 0; i < 4; i++) { | |
5817 | u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) | | |
5818 | (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]); | |
5819 | I915_WRITE(PXW + (i * 4), val); | |
5820 | } | |
5821 | ||
5822 | /* Adjust magic regs to magic values (more experimental results) */ | |
5823 | I915_WRITE(OGW0, 0); | |
5824 | I915_WRITE(OGW1, 0); | |
5825 | I915_WRITE(EG0, 0x00007f00); | |
5826 | I915_WRITE(EG1, 0x0000000e); | |
5827 | I915_WRITE(EG2, 0x000e0000); | |
5828 | I915_WRITE(EG3, 0x68000300); | |
5829 | I915_WRITE(EG4, 0x42000000); | |
5830 | I915_WRITE(EG5, 0x00140031); | |
5831 | I915_WRITE(EG6, 0); | |
5832 | I915_WRITE(EG7, 0); | |
5833 | ||
5834 | for (i = 0; i < 8; i++) | |
5835 | I915_WRITE(PXWL + (i * 4), 0); | |
5836 | ||
5837 | /* Enable PMON + select events */ | |
5838 | I915_WRITE(ECR, 0x80000019); | |
5839 | ||
5840 | lcfuse = I915_READ(LCFUSE02); | |
5841 | ||
5842 | dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK); | |
5843 | } | |
5844 | ||
0cdab21f | 5845 | void intel_enable_clock_gating(struct drm_device *dev) |
652c393a JB |
5846 | { |
5847 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5848 | ||
5849 | /* | |
5850 | * Disable clock gating reported to work incorrectly according to the | |
5851 | * specs, but enable as much else as we can. | |
5852 | */ | |
bad720ff | 5853 | if (HAS_PCH_SPLIT(dev)) { |
8956c8bb EA |
5854 | uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE; |
5855 | ||
f00a3ddf | 5856 | if (IS_GEN5(dev)) { |
8956c8bb EA |
5857 | /* Required for FBC */ |
5858 | dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE; | |
5859 | /* Required for CxSR */ | |
5860 | dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE; | |
5861 | ||
5862 | I915_WRITE(PCH_3DCGDIS0, | |
5863 | MARIUNIT_CLOCK_GATE_DISABLE | | |
5864 | SVSMUNIT_CLOCK_GATE_DISABLE); | |
5865 | } | |
5866 | ||
5867 | I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate); | |
7f8a8569 | 5868 | |
382b0936 JB |
5869 | /* |
5870 | * On Ibex Peak and Cougar Point, we need to disable clock | |
5871 | * gating for the panel power sequencer or it will fail to | |
5872 | * start up when no ports are active. | |
5873 | */ | |
5874 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); | |
5875 | ||
7f8a8569 ZW |
5876 | /* |
5877 | * According to the spec the following bits should be set in | |
5878 | * order to enable memory self-refresh | |
5879 | * The bit 22/21 of 0x42004 | |
5880 | * The bit 5 of 0x42020 | |
5881 | * The bit 15 of 0x45000 | |
5882 | */ | |
f00a3ddf | 5883 | if (IS_GEN5(dev)) { |
7f8a8569 ZW |
5884 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
5885 | (I915_READ(ILK_DISPLAY_CHICKEN2) | | |
5886 | ILK_DPARB_GATE | ILK_VSDPFD_FULL)); | |
5887 | I915_WRITE(ILK_DSPCLK_GATE, | |
5888 | (I915_READ(ILK_DSPCLK_GATE) | | |
5889 | ILK_DPARB_CLK_GATE)); | |
5890 | I915_WRITE(DISP_ARB_CTL, | |
5891 | (I915_READ(DISP_ARB_CTL) | | |
5892 | DISP_FBC_WM_DIS)); | |
dd8849c8 JB |
5893 | I915_WRITE(WM3_LP_ILK, 0); |
5894 | I915_WRITE(WM2_LP_ILK, 0); | |
5895 | I915_WRITE(WM1_LP_ILK, 0); | |
7f8a8569 | 5896 | } |
b52eb4dc ZY |
5897 | /* |
5898 | * Based on the document from hardware guys the following bits | |
5899 | * should be set unconditionally in order to enable FBC. | |
5900 | * The bit 22 of 0x42000 | |
5901 | * The bit 22 of 0x42004 | |
5902 | * The bit 7,8,9 of 0x42020. | |
5903 | */ | |
5904 | if (IS_IRONLAKE_M(dev)) { | |
5905 | I915_WRITE(ILK_DISPLAY_CHICKEN1, | |
5906 | I915_READ(ILK_DISPLAY_CHICKEN1) | | |
5907 | ILK_FBCQ_DIS); | |
5908 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
5909 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
5910 | ILK_DPARB_GATE); | |
5911 | I915_WRITE(ILK_DSPCLK_GATE, | |
5912 | I915_READ(ILK_DSPCLK_GATE) | | |
5913 | ILK_DPFC_DIS1 | | |
5914 | ILK_DPFC_DIS2 | | |
5915 | ILK_CLK_FBC); | |
5916 | } | |
de6e2eaf | 5917 | |
67e92af0 EA |
5918 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
5919 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
5920 | ILK_ELPIN_409_SELECT); | |
5921 | ||
de6e2eaf EA |
5922 | if (IS_GEN5(dev)) { |
5923 | I915_WRITE(_3D_CHICKEN2, | |
5924 | _3D_CHICKEN2_WM_READ_PIPELINED << 16 | | |
5925 | _3D_CHICKEN2_WM_READ_PIPELINED); | |
5926 | } | |
c03342fa | 5927 | } else if (IS_G4X(dev)) { |
652c393a JB |
5928 | uint32_t dspclk_gate; |
5929 | I915_WRITE(RENCLK_GATE_D1, 0); | |
5930 | I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | | |
5931 | GS_UNIT_CLOCK_GATE_DISABLE | | |
5932 | CL_UNIT_CLOCK_GATE_DISABLE); | |
5933 | I915_WRITE(RAMCLK_GATE_D, 0); | |
5934 | dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE | | |
5935 | OVRUNIT_CLOCK_GATE_DISABLE | | |
5936 | OVCUNIT_CLOCK_GATE_DISABLE; | |
5937 | if (IS_GM45(dev)) | |
5938 | dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; | |
5939 | I915_WRITE(DSPCLK_GATE_D, dspclk_gate); | |
a6c45cf0 | 5940 | } else if (IS_CRESTLINE(dev)) { |
652c393a JB |
5941 | I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); |
5942 | I915_WRITE(RENCLK_GATE_D2, 0); | |
5943 | I915_WRITE(DSPCLK_GATE_D, 0); | |
5944 | I915_WRITE(RAMCLK_GATE_D, 0); | |
5945 | I915_WRITE16(DEUC, 0); | |
a6c45cf0 | 5946 | } else if (IS_BROADWATER(dev)) { |
652c393a JB |
5947 | I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | |
5948 | I965_RCC_CLOCK_GATE_DISABLE | | |
5949 | I965_RCPB_CLOCK_GATE_DISABLE | | |
5950 | I965_ISC_CLOCK_GATE_DISABLE | | |
5951 | I965_FBC_CLOCK_GATE_DISABLE); | |
5952 | I915_WRITE(RENCLK_GATE_D2, 0); | |
a6c45cf0 | 5953 | } else if (IS_GEN3(dev)) { |
652c393a JB |
5954 | u32 dstate = I915_READ(D_STATE); |
5955 | ||
5956 | dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | | |
5957 | DSTATE_DOT_CLOCK_GATING; | |
5958 | I915_WRITE(D_STATE, dstate); | |
f0f8a9ce | 5959 | } else if (IS_I85X(dev) || IS_I865G(dev)) { |
652c393a JB |
5960 | I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); |
5961 | } else if (IS_I830(dev)) { | |
5962 | I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); | |
5963 | } | |
97f5ab66 JB |
5964 | |
5965 | /* | |
5966 | * GPU can automatically power down the render unit if given a page | |
5967 | * to save state. | |
5968 | */ | |
c5780270 | 5969 | if (IS_IRONLAKE_M(dev) && 0) { /* XXX causes a failure during suspend */ |
aa40d6bb ZN |
5970 | if (dev_priv->renderctx == NULL) |
5971 | dev_priv->renderctx = intel_alloc_context_page(dev); | |
5972 | if (dev_priv->renderctx) { | |
05394f39 CW |
5973 | struct drm_i915_gem_object *obj = dev_priv->renderctx; |
5974 | if (BEGIN_LP_RING(4) == 0) { | |
5975 | OUT_RING(MI_SET_CONTEXT); | |
5976 | OUT_RING(obj->gtt_offset | | |
5977 | MI_MM_SPACE_GTT | | |
5978 | MI_SAVE_EXT_STATE_EN | | |
5979 | MI_RESTORE_EXT_STATE_EN | | |
5980 | MI_RESTORE_INHIBIT); | |
5981 | OUT_RING(MI_NOOP); | |
5982 | OUT_RING(MI_FLUSH); | |
5983 | ADVANCE_LP_RING(); | |
aa40d6bb | 5984 | } |
bc41606a | 5985 | } else |
aa40d6bb | 5986 | DRM_DEBUG_KMS("Failed to allocate render context." |
bc41606a | 5987 | "Disable RC6\n"); |
aa40d6bb ZN |
5988 | } |
5989 | ||
3c8cdf9b | 5990 | if (IS_GEN4(dev) && IS_MOBILE(dev)) { |
05394f39 CW |
5991 | if (dev_priv->pwrctx == NULL) |
5992 | dev_priv->pwrctx = intel_alloc_context_page(dev); | |
7e8b60fa | 5993 | if (dev_priv->pwrctx) { |
05394f39 CW |
5994 | struct drm_i915_gem_object *obj = dev_priv->pwrctx; |
5995 | I915_WRITE(PWRCTXA, obj->gtt_offset | PWRCTX_EN); | |
9ea8d059 CW |
5996 | I915_WRITE(MCHBAR_RENDER_STANDBY, |
5997 | I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT); | |
5998 | } | |
97f5ab66 | 5999 | } |
652c393a JB |
6000 | } |
6001 | ||
0cdab21f CW |
6002 | void intel_disable_clock_gating(struct drm_device *dev) |
6003 | { | |
6004 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6005 | ||
6006 | if (dev_priv->renderctx) { | |
6007 | struct drm_i915_gem_object *obj = dev_priv->renderctx; | |
6008 | ||
6009 | I915_WRITE(CCID, 0); | |
6010 | POSTING_READ(CCID); | |
6011 | ||
6012 | i915_gem_object_unpin(obj); | |
6013 | drm_gem_object_unreference(&obj->base); | |
6014 | dev_priv->renderctx = NULL; | |
6015 | } | |
6016 | ||
6017 | if (dev_priv->pwrctx) { | |
6018 | struct drm_i915_gem_object *obj = dev_priv->pwrctx; | |
6019 | ||
6020 | I915_WRITE(PWRCTXA, 0); | |
6021 | POSTING_READ(PWRCTXA); | |
6022 | ||
6023 | i915_gem_object_unpin(obj); | |
6024 | drm_gem_object_unreference(&obj->base); | |
6025 | dev_priv->pwrctx = NULL; | |
6026 | } | |
6027 | } | |
6028 | ||
e70236a8 JB |
6029 | /* Set up chip specific display functions */ |
6030 | static void intel_init_display(struct drm_device *dev) | |
6031 | { | |
6032 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6033 | ||
6034 | /* We always want a DPMS function */ | |
bad720ff | 6035 | if (HAS_PCH_SPLIT(dev)) |
f2b115e6 | 6036 | dev_priv->display.dpms = ironlake_crtc_dpms; |
e70236a8 JB |
6037 | else |
6038 | dev_priv->display.dpms = i9xx_crtc_dpms; | |
6039 | ||
ee5382ae | 6040 | if (I915_HAS_FBC(dev)) { |
b52eb4dc ZY |
6041 | if (IS_IRONLAKE_M(dev)) { |
6042 | dev_priv->display.fbc_enabled = ironlake_fbc_enabled; | |
6043 | dev_priv->display.enable_fbc = ironlake_enable_fbc; | |
6044 | dev_priv->display.disable_fbc = ironlake_disable_fbc; | |
6045 | } else if (IS_GM45(dev)) { | |
74dff282 JB |
6046 | dev_priv->display.fbc_enabled = g4x_fbc_enabled; |
6047 | dev_priv->display.enable_fbc = g4x_enable_fbc; | |
6048 | dev_priv->display.disable_fbc = g4x_disable_fbc; | |
a6c45cf0 | 6049 | } else if (IS_CRESTLINE(dev)) { |
e70236a8 JB |
6050 | dev_priv->display.fbc_enabled = i8xx_fbc_enabled; |
6051 | dev_priv->display.enable_fbc = i8xx_enable_fbc; | |
6052 | dev_priv->display.disable_fbc = i8xx_disable_fbc; | |
6053 | } | |
74dff282 | 6054 | /* 855GM needs testing */ |
e70236a8 JB |
6055 | } |
6056 | ||
6057 | /* Returns the core display clock speed */ | |
f2b115e6 | 6058 | if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev))) |
e70236a8 JB |
6059 | dev_priv->display.get_display_clock_speed = |
6060 | i945_get_display_clock_speed; | |
6061 | else if (IS_I915G(dev)) | |
6062 | dev_priv->display.get_display_clock_speed = | |
6063 | i915_get_display_clock_speed; | |
f2b115e6 | 6064 | else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev)) |
e70236a8 JB |
6065 | dev_priv->display.get_display_clock_speed = |
6066 | i9xx_misc_get_display_clock_speed; | |
6067 | else if (IS_I915GM(dev)) | |
6068 | dev_priv->display.get_display_clock_speed = | |
6069 | i915gm_get_display_clock_speed; | |
6070 | else if (IS_I865G(dev)) | |
6071 | dev_priv->display.get_display_clock_speed = | |
6072 | i865_get_display_clock_speed; | |
f0f8a9ce | 6073 | else if (IS_I85X(dev)) |
e70236a8 JB |
6074 | dev_priv->display.get_display_clock_speed = |
6075 | i855_get_display_clock_speed; | |
6076 | else /* 852, 830 */ | |
6077 | dev_priv->display.get_display_clock_speed = | |
6078 | i830_get_display_clock_speed; | |
6079 | ||
6080 | /* For FIFO watermark updates */ | |
7f8a8569 | 6081 | if (HAS_PCH_SPLIT(dev)) { |
f00a3ddf | 6082 | if (IS_GEN5(dev)) { |
7f8a8569 ZW |
6083 | if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK) |
6084 | dev_priv->display.update_wm = ironlake_update_wm; | |
6085 | else { | |
6086 | DRM_DEBUG_KMS("Failed to get proper latency. " | |
6087 | "Disable CxSR\n"); | |
6088 | dev_priv->display.update_wm = NULL; | |
6089 | } | |
6090 | } else | |
6091 | dev_priv->display.update_wm = NULL; | |
6092 | } else if (IS_PINEVIEW(dev)) { | |
d4294342 | 6093 | if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev), |
95534263 | 6094 | dev_priv->is_ddr3, |
d4294342 ZY |
6095 | dev_priv->fsb_freq, |
6096 | dev_priv->mem_freq)) { | |
6097 | DRM_INFO("failed to find known CxSR latency " | |
95534263 | 6098 | "(found ddr%s fsb freq %d, mem freq %d), " |
d4294342 | 6099 | "disabling CxSR\n", |
95534263 | 6100 | (dev_priv->is_ddr3 == 1) ? "3": "2", |
d4294342 ZY |
6101 | dev_priv->fsb_freq, dev_priv->mem_freq); |
6102 | /* Disable CxSR and never update its watermark again */ | |
6103 | pineview_disable_cxsr(dev); | |
6104 | dev_priv->display.update_wm = NULL; | |
6105 | } else | |
6106 | dev_priv->display.update_wm = pineview_update_wm; | |
6107 | } else if (IS_G4X(dev)) | |
e70236a8 | 6108 | dev_priv->display.update_wm = g4x_update_wm; |
a6c45cf0 | 6109 | else if (IS_GEN4(dev)) |
e70236a8 | 6110 | dev_priv->display.update_wm = i965_update_wm; |
a6c45cf0 | 6111 | else if (IS_GEN3(dev)) { |
e70236a8 JB |
6112 | dev_priv->display.update_wm = i9xx_update_wm; |
6113 | dev_priv->display.get_fifo_size = i9xx_get_fifo_size; | |
8f4695ed AJ |
6114 | } else if (IS_I85X(dev)) { |
6115 | dev_priv->display.update_wm = i9xx_update_wm; | |
6116 | dev_priv->display.get_fifo_size = i85x_get_fifo_size; | |
e70236a8 | 6117 | } else { |
8f4695ed AJ |
6118 | dev_priv->display.update_wm = i830_update_wm; |
6119 | if (IS_845G(dev)) | |
e70236a8 JB |
6120 | dev_priv->display.get_fifo_size = i845_get_fifo_size; |
6121 | else | |
6122 | dev_priv->display.get_fifo_size = i830_get_fifo_size; | |
e70236a8 JB |
6123 | } |
6124 | } | |
6125 | ||
b690e96c JB |
6126 | /* |
6127 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
6128 | * resume, or other times. This quirk makes sure that's the case for | |
6129 | * affected systems. | |
6130 | */ | |
6131 | static void quirk_pipea_force (struct drm_device *dev) | |
6132 | { | |
6133 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6134 | ||
6135 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
6136 | DRM_DEBUG_DRIVER("applying pipe a force quirk\n"); | |
6137 | } | |
6138 | ||
6139 | struct intel_quirk { | |
6140 | int device; | |
6141 | int subsystem_vendor; | |
6142 | int subsystem_device; | |
6143 | void (*hook)(struct drm_device *dev); | |
6144 | }; | |
6145 | ||
6146 | struct intel_quirk intel_quirks[] = { | |
6147 | /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */ | |
6148 | { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force }, | |
6149 | /* HP Mini needs pipe A force quirk (LP: #322104) */ | |
6150 | { 0x27ae,0x103c, 0x361a, quirk_pipea_force }, | |
6151 | ||
6152 | /* Thinkpad R31 needs pipe A force quirk */ | |
6153 | { 0x3577, 0x1014, 0x0505, quirk_pipea_force }, | |
6154 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ | |
6155 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
6156 | ||
6157 | /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */ | |
6158 | { 0x3577, 0x1014, 0x0513, quirk_pipea_force }, | |
6159 | /* ThinkPad X40 needs pipe A force quirk */ | |
6160 | ||
6161 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ | |
6162 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
6163 | ||
6164 | /* 855 & before need to leave pipe A & dpll A up */ | |
6165 | { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
6166 | { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
6167 | }; | |
6168 | ||
6169 | static void intel_init_quirks(struct drm_device *dev) | |
6170 | { | |
6171 | struct pci_dev *d = dev->pdev; | |
6172 | int i; | |
6173 | ||
6174 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
6175 | struct intel_quirk *q = &intel_quirks[i]; | |
6176 | ||
6177 | if (d->device == q->device && | |
6178 | (d->subsystem_vendor == q->subsystem_vendor || | |
6179 | q->subsystem_vendor == PCI_ANY_ID) && | |
6180 | (d->subsystem_device == q->subsystem_device || | |
6181 | q->subsystem_device == PCI_ANY_ID)) | |
6182 | q->hook(dev); | |
6183 | } | |
6184 | } | |
6185 | ||
9cce37f4 JB |
6186 | /* Disable the VGA plane that we never use */ |
6187 | static void i915_disable_vga(struct drm_device *dev) | |
6188 | { | |
6189 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6190 | u8 sr1; | |
6191 | u32 vga_reg; | |
6192 | ||
6193 | if (HAS_PCH_SPLIT(dev)) | |
6194 | vga_reg = CPU_VGACNTRL; | |
6195 | else | |
6196 | vga_reg = VGACNTRL; | |
6197 | ||
6198 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); | |
6199 | outb(1, VGA_SR_INDEX); | |
6200 | sr1 = inb(VGA_SR_DATA); | |
6201 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
6202 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
6203 | udelay(300); | |
6204 | ||
6205 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); | |
6206 | POSTING_READ(vga_reg); | |
6207 | } | |
6208 | ||
79e53945 JB |
6209 | void intel_modeset_init(struct drm_device *dev) |
6210 | { | |
652c393a | 6211 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 JB |
6212 | int i; |
6213 | ||
6214 | drm_mode_config_init(dev); | |
6215 | ||
6216 | dev->mode_config.min_width = 0; | |
6217 | dev->mode_config.min_height = 0; | |
6218 | ||
6219 | dev->mode_config.funcs = (void *)&intel_mode_funcs; | |
6220 | ||
b690e96c JB |
6221 | intel_init_quirks(dev); |
6222 | ||
e70236a8 JB |
6223 | intel_init_display(dev); |
6224 | ||
a6c45cf0 CW |
6225 | if (IS_GEN2(dev)) { |
6226 | dev->mode_config.max_width = 2048; | |
6227 | dev->mode_config.max_height = 2048; | |
6228 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
6229 | dev->mode_config.max_width = 4096; |
6230 | dev->mode_config.max_height = 4096; | |
79e53945 | 6231 | } else { |
a6c45cf0 CW |
6232 | dev->mode_config.max_width = 8192; |
6233 | dev->mode_config.max_height = 8192; | |
79e53945 JB |
6234 | } |
6235 | ||
6236 | /* set memory base */ | |
a6c45cf0 | 6237 | if (IS_GEN2(dev)) |
79e53945 | 6238 | dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0); |
a6c45cf0 CW |
6239 | else |
6240 | dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2); | |
79e53945 | 6241 | |
a6c45cf0 | 6242 | if (IS_MOBILE(dev) || !IS_GEN2(dev)) |
a3524f1b | 6243 | dev_priv->num_pipe = 2; |
79e53945 | 6244 | else |
a3524f1b | 6245 | dev_priv->num_pipe = 1; |
28c97730 | 6246 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
a3524f1b | 6247 | dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : ""); |
79e53945 | 6248 | |
a3524f1b | 6249 | for (i = 0; i < dev_priv->num_pipe; i++) { |
79e53945 JB |
6250 | intel_crtc_init(dev, i); |
6251 | } | |
6252 | ||
6253 | intel_setup_outputs(dev); | |
652c393a | 6254 | |
0cdab21f | 6255 | intel_enable_clock_gating(dev); |
652c393a | 6256 | |
9cce37f4 JB |
6257 | /* Just disable it once at startup */ |
6258 | i915_disable_vga(dev); | |
6259 | ||
7648fa99 | 6260 | if (IS_IRONLAKE_M(dev)) { |
f97108d1 | 6261 | ironlake_enable_drps(dev); |
7648fa99 JB |
6262 | intel_init_emon(dev); |
6263 | } | |
f97108d1 | 6264 | |
652c393a JB |
6265 | INIT_WORK(&dev_priv->idle_work, intel_idle_update); |
6266 | setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer, | |
6267 | (unsigned long)dev); | |
02e792fb DV |
6268 | |
6269 | intel_setup_overlay(dev); | |
79e53945 JB |
6270 | } |
6271 | ||
6272 | void intel_modeset_cleanup(struct drm_device *dev) | |
6273 | { | |
652c393a JB |
6274 | struct drm_i915_private *dev_priv = dev->dev_private; |
6275 | struct drm_crtc *crtc; | |
6276 | struct intel_crtc *intel_crtc; | |
6277 | ||
f87ea761 | 6278 | drm_kms_helper_poll_fini(dev); |
652c393a JB |
6279 | mutex_lock(&dev->struct_mutex); |
6280 | ||
723bfd70 JB |
6281 | intel_unregister_dsm_handler(); |
6282 | ||
6283 | ||
652c393a JB |
6284 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
6285 | /* Skip inactive CRTCs */ | |
6286 | if (!crtc->fb) | |
6287 | continue; | |
6288 | ||
6289 | intel_crtc = to_intel_crtc(crtc); | |
3dec0095 | 6290 | intel_increase_pllclock(crtc); |
652c393a JB |
6291 | } |
6292 | ||
e70236a8 JB |
6293 | if (dev_priv->display.disable_fbc) |
6294 | dev_priv->display.disable_fbc(dev); | |
6295 | ||
f97108d1 JB |
6296 | if (IS_IRONLAKE_M(dev)) |
6297 | ironlake_disable_drps(dev); | |
6298 | ||
0cdab21f CW |
6299 | intel_disable_clock_gating(dev); |
6300 | ||
69341a5e KH |
6301 | mutex_unlock(&dev->struct_mutex); |
6302 | ||
6c0d9350 DV |
6303 | /* Disable the irq before mode object teardown, for the irq might |
6304 | * enqueue unpin/hotplug work. */ | |
6305 | drm_irq_uninstall(dev); | |
6306 | cancel_work_sync(&dev_priv->hotplug_work); | |
6307 | ||
3dec0095 DV |
6308 | /* Shut off idle work before the crtcs get freed. */ |
6309 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
6310 | intel_crtc = to_intel_crtc(crtc); | |
6311 | del_timer_sync(&intel_crtc->idle_timer); | |
6312 | } | |
6313 | del_timer_sync(&dev_priv->idle_timer); | |
6314 | cancel_work_sync(&dev_priv->idle_work); | |
6315 | ||
79e53945 JB |
6316 | drm_mode_config_cleanup(dev); |
6317 | } | |
6318 | ||
f1c79df3 ZW |
6319 | /* |
6320 | * Return which encoder is currently attached for connector. | |
6321 | */ | |
df0e9248 | 6322 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 6323 | { |
df0e9248 CW |
6324 | return &intel_attached_encoder(connector)->base; |
6325 | } | |
f1c79df3 | 6326 | |
df0e9248 CW |
6327 | void intel_connector_attach_encoder(struct intel_connector *connector, |
6328 | struct intel_encoder *encoder) | |
6329 | { | |
6330 | connector->encoder = encoder; | |
6331 | drm_mode_connector_attach_encoder(&connector->base, | |
6332 | &encoder->base); | |
79e53945 | 6333 | } |
28d52043 DA |
6334 | |
6335 | /* | |
6336 | * set vga decode state - true == enable VGA decode | |
6337 | */ | |
6338 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
6339 | { | |
6340 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6341 | u16 gmch_ctrl; | |
6342 | ||
6343 | pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl); | |
6344 | if (state) | |
6345 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
6346 | else | |
6347 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
6348 | pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl); | |
6349 | return 0; | |
6350 | } | |
c4a1d9e4 CW |
6351 | |
6352 | #ifdef CONFIG_DEBUG_FS | |
6353 | #include <linux/seq_file.h> | |
6354 | ||
6355 | struct intel_display_error_state { | |
6356 | struct intel_cursor_error_state { | |
6357 | u32 control; | |
6358 | u32 position; | |
6359 | u32 base; | |
6360 | u32 size; | |
6361 | } cursor[2]; | |
6362 | ||
6363 | struct intel_pipe_error_state { | |
6364 | u32 conf; | |
6365 | u32 source; | |
6366 | ||
6367 | u32 htotal; | |
6368 | u32 hblank; | |
6369 | u32 hsync; | |
6370 | u32 vtotal; | |
6371 | u32 vblank; | |
6372 | u32 vsync; | |
6373 | } pipe[2]; | |
6374 | ||
6375 | struct intel_plane_error_state { | |
6376 | u32 control; | |
6377 | u32 stride; | |
6378 | u32 size; | |
6379 | u32 pos; | |
6380 | u32 addr; | |
6381 | u32 surface; | |
6382 | u32 tile_offset; | |
6383 | } plane[2]; | |
6384 | }; | |
6385 | ||
6386 | struct intel_display_error_state * | |
6387 | intel_display_capture_error_state(struct drm_device *dev) | |
6388 | { | |
6389 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6390 | struct intel_display_error_state *error; | |
6391 | int i; | |
6392 | ||
6393 | error = kmalloc(sizeof(*error), GFP_ATOMIC); | |
6394 | if (error == NULL) | |
6395 | return NULL; | |
6396 | ||
6397 | for (i = 0; i < 2; i++) { | |
6398 | error->cursor[i].control = I915_READ(CURCNTR(i)); | |
6399 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
6400 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
6401 | ||
6402 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
6403 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
6404 | error->plane[i].size = I915_READ(DSPSIZE(i)); | |
6405 | error->plane[i].pos= I915_READ(DSPPOS(i)); | |
6406 | error->plane[i].addr = I915_READ(DSPADDR(i)); | |
6407 | if (INTEL_INFO(dev)->gen >= 4) { | |
6408 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
6409 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
6410 | } | |
6411 | ||
6412 | error->pipe[i].conf = I915_READ(PIPECONF(i)); | |
6413 | error->pipe[i].source = I915_READ(PIPESRC(i)); | |
6414 | error->pipe[i].htotal = I915_READ(HTOTAL(i)); | |
6415 | error->pipe[i].hblank = I915_READ(HBLANK(i)); | |
6416 | error->pipe[i].hsync = I915_READ(HSYNC(i)); | |
6417 | error->pipe[i].vtotal = I915_READ(VTOTAL(i)); | |
6418 | error->pipe[i].vblank = I915_READ(VBLANK(i)); | |
6419 | error->pipe[i].vsync = I915_READ(VSYNC(i)); | |
6420 | } | |
6421 | ||
6422 | return error; | |
6423 | } | |
6424 | ||
6425 | void | |
6426 | intel_display_print_error_state(struct seq_file *m, | |
6427 | struct drm_device *dev, | |
6428 | struct intel_display_error_state *error) | |
6429 | { | |
6430 | int i; | |
6431 | ||
6432 | for (i = 0; i < 2; i++) { | |
6433 | seq_printf(m, "Pipe [%d]:\n", i); | |
6434 | seq_printf(m, " CONF: %08x\n", error->pipe[i].conf); | |
6435 | seq_printf(m, " SRC: %08x\n", error->pipe[i].source); | |
6436 | seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal); | |
6437 | seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank); | |
6438 | seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync); | |
6439 | seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal); | |
6440 | seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank); | |
6441 | seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync); | |
6442 | ||
6443 | seq_printf(m, "Plane [%d]:\n", i); | |
6444 | seq_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
6445 | seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
6446 | seq_printf(m, " SIZE: %08x\n", error->plane[i].size); | |
6447 | seq_printf(m, " POS: %08x\n", error->plane[i].pos); | |
6448 | seq_printf(m, " ADDR: %08x\n", error->plane[i].addr); | |
6449 | if (INTEL_INFO(dev)->gen >= 4) { | |
6450 | seq_printf(m, " SURF: %08x\n", error->plane[i].surface); | |
6451 | seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
6452 | } | |
6453 | ||
6454 | seq_printf(m, "Cursor [%d]:\n", i); | |
6455 | seq_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
6456 | seq_printf(m, " POS: %08x\n", error->cursor[i].position); | |
6457 | seq_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
6458 | } | |
6459 | } | |
6460 | #endif |