Commit | Line | Data |
---|---|---|
79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
e5510fac | 39 | #include "i915_trace.h" |
760285e7 DH |
40 | #include <drm/drm_dp_helper.h> |
41 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
42 | #include <drm/drm_plane_helper.h> |
43 | #include <drm/drm_rect.h> | |
c0f372b3 | 44 | #include <linux/dma_remapping.h> |
79e53945 | 45 | |
465c120c MR |
46 | /* Primary plane formats supported by all gen */ |
47 | #define COMMON_PRIMARY_FORMATS \ | |
48 | DRM_FORMAT_C8, \ | |
49 | DRM_FORMAT_RGB565, \ | |
50 | DRM_FORMAT_XRGB8888, \ | |
51 | DRM_FORMAT_ARGB8888 | |
52 | ||
53 | /* Primary plane formats for gen <= 3 */ | |
54 | static const uint32_t intel_primary_formats_gen2[] = { | |
55 | COMMON_PRIMARY_FORMATS, | |
56 | DRM_FORMAT_XRGB1555, | |
57 | DRM_FORMAT_ARGB1555, | |
58 | }; | |
59 | ||
60 | /* Primary plane formats for gen >= 4 */ | |
61 | static const uint32_t intel_primary_formats_gen4[] = { | |
62 | COMMON_PRIMARY_FORMATS, \ | |
63 | DRM_FORMAT_XBGR8888, | |
64 | DRM_FORMAT_ABGR8888, | |
65 | DRM_FORMAT_XRGB2101010, | |
66 | DRM_FORMAT_ARGB2101010, | |
67 | DRM_FORMAT_XBGR2101010, | |
68 | DRM_FORMAT_ABGR2101010, | |
69 | }; | |
70 | ||
ef9348c8 | 71 | #define DIV_ROUND_CLOSEST_ULL(ll, d) \ |
465c120c | 72 | ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; }) |
ef9348c8 | 73 | |
3dec0095 | 74 | static void intel_increase_pllclock(struct drm_crtc *crtc); |
6b383a7f | 75 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
79e53945 | 76 | |
f1f644dc JB |
77 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
78 | struct intel_crtc_config *pipe_config); | |
18442d08 VS |
79 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
80 | struct intel_crtc_config *pipe_config); | |
f1f644dc | 81 | |
e7457a9a DL |
82 | static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode, |
83 | int x, int y, struct drm_framebuffer *old_fb); | |
eb1bfe80 JB |
84 | static int intel_framebuffer_init(struct drm_device *dev, |
85 | struct intel_framebuffer *ifb, | |
86 | struct drm_mode_fb_cmd2 *mode_cmd, | |
87 | struct drm_i915_gem_object *obj); | |
5b18e57c DV |
88 | static void intel_dp_set_m_n(struct intel_crtc *crtc); |
89 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); | |
90 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
29407aab DV |
91 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
92 | struct intel_link_m_n *m_n); | |
93 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); | |
229fca97 DV |
94 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
95 | static void intel_set_pipe_csc(struct drm_crtc *crtc); | |
bdd4b6a6 | 96 | static void vlv_prepare_pll(struct intel_crtc *crtc); |
e7457a9a | 97 | |
79e53945 | 98 | typedef struct { |
0206e353 | 99 | int min, max; |
79e53945 JB |
100 | } intel_range_t; |
101 | ||
102 | typedef struct { | |
0206e353 AJ |
103 | int dot_limit; |
104 | int p2_slow, p2_fast; | |
79e53945 JB |
105 | } intel_p2_t; |
106 | ||
d4906093 ML |
107 | typedef struct intel_limit intel_limit_t; |
108 | struct intel_limit { | |
0206e353 AJ |
109 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
110 | intel_p2_t p2; | |
d4906093 | 111 | }; |
79e53945 | 112 | |
d2acd215 DV |
113 | int |
114 | intel_pch_rawclk(struct drm_device *dev) | |
115 | { | |
116 | struct drm_i915_private *dev_priv = dev->dev_private; | |
117 | ||
118 | WARN_ON(!HAS_PCH_SPLIT(dev)); | |
119 | ||
120 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; | |
121 | } | |
122 | ||
021357ac CW |
123 | static inline u32 /* units of 100MHz */ |
124 | intel_fdi_link_freq(struct drm_device *dev) | |
125 | { | |
8b99e68c CW |
126 | if (IS_GEN5(dev)) { |
127 | struct drm_i915_private *dev_priv = dev->dev_private; | |
128 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
129 | } else | |
130 | return 27; | |
021357ac CW |
131 | } |
132 | ||
5d536e28 | 133 | static const intel_limit_t intel_limits_i8xx_dac = { |
0206e353 | 134 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 135 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 136 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
137 | .m = { .min = 96, .max = 140 }, |
138 | .m1 = { .min = 18, .max = 26 }, | |
139 | .m2 = { .min = 6, .max = 16 }, | |
140 | .p = { .min = 4, .max = 128 }, | |
141 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
142 | .p2 = { .dot_limit = 165000, |
143 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
144 | }; |
145 | ||
5d536e28 DV |
146 | static const intel_limit_t intel_limits_i8xx_dvo = { |
147 | .dot = { .min = 25000, .max = 350000 }, | |
9c333719 | 148 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 149 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
150 | .m = { .min = 96, .max = 140 }, |
151 | .m1 = { .min = 18, .max = 26 }, | |
152 | .m2 = { .min = 6, .max = 16 }, | |
153 | .p = { .min = 4, .max = 128 }, | |
154 | .p1 = { .min = 2, .max = 33 }, | |
155 | .p2 = { .dot_limit = 165000, | |
156 | .p2_slow = 4, .p2_fast = 4 }, | |
157 | }; | |
158 | ||
e4b36699 | 159 | static const intel_limit_t intel_limits_i8xx_lvds = { |
0206e353 | 160 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 161 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 162 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
163 | .m = { .min = 96, .max = 140 }, |
164 | .m1 = { .min = 18, .max = 26 }, | |
165 | .m2 = { .min = 6, .max = 16 }, | |
166 | .p = { .min = 4, .max = 128 }, | |
167 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
168 | .p2 = { .dot_limit = 165000, |
169 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 170 | }; |
273e27ca | 171 | |
e4b36699 | 172 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
173 | .dot = { .min = 20000, .max = 400000 }, |
174 | .vco = { .min = 1400000, .max = 2800000 }, | |
175 | .n = { .min = 1, .max = 6 }, | |
176 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
177 | .m1 = { .min = 8, .max = 18 }, |
178 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
179 | .p = { .min = 5, .max = 80 }, |
180 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
181 | .p2 = { .dot_limit = 200000, |
182 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
183 | }; |
184 | ||
185 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
186 | .dot = { .min = 20000, .max = 400000 }, |
187 | .vco = { .min = 1400000, .max = 2800000 }, | |
188 | .n = { .min = 1, .max = 6 }, | |
189 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
190 | .m1 = { .min = 8, .max = 18 }, |
191 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
192 | .p = { .min = 7, .max = 98 }, |
193 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
194 | .p2 = { .dot_limit = 112000, |
195 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
196 | }; |
197 | ||
273e27ca | 198 | |
e4b36699 | 199 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
200 | .dot = { .min = 25000, .max = 270000 }, |
201 | .vco = { .min = 1750000, .max = 3500000}, | |
202 | .n = { .min = 1, .max = 4 }, | |
203 | .m = { .min = 104, .max = 138 }, | |
204 | .m1 = { .min = 17, .max = 23 }, | |
205 | .m2 = { .min = 5, .max = 11 }, | |
206 | .p = { .min = 10, .max = 30 }, | |
207 | .p1 = { .min = 1, .max = 3}, | |
208 | .p2 = { .dot_limit = 270000, | |
209 | .p2_slow = 10, | |
210 | .p2_fast = 10 | |
044c7c41 | 211 | }, |
e4b36699 KP |
212 | }; |
213 | ||
214 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
215 | .dot = { .min = 22000, .max = 400000 }, |
216 | .vco = { .min = 1750000, .max = 3500000}, | |
217 | .n = { .min = 1, .max = 4 }, | |
218 | .m = { .min = 104, .max = 138 }, | |
219 | .m1 = { .min = 16, .max = 23 }, | |
220 | .m2 = { .min = 5, .max = 11 }, | |
221 | .p = { .min = 5, .max = 80 }, | |
222 | .p1 = { .min = 1, .max = 8}, | |
223 | .p2 = { .dot_limit = 165000, | |
224 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
225 | }; |
226 | ||
227 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
228 | .dot = { .min = 20000, .max = 115000 }, |
229 | .vco = { .min = 1750000, .max = 3500000 }, | |
230 | .n = { .min = 1, .max = 3 }, | |
231 | .m = { .min = 104, .max = 138 }, | |
232 | .m1 = { .min = 17, .max = 23 }, | |
233 | .m2 = { .min = 5, .max = 11 }, | |
234 | .p = { .min = 28, .max = 112 }, | |
235 | .p1 = { .min = 2, .max = 8 }, | |
236 | .p2 = { .dot_limit = 0, | |
237 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 238 | }, |
e4b36699 KP |
239 | }; |
240 | ||
241 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
242 | .dot = { .min = 80000, .max = 224000 }, |
243 | .vco = { .min = 1750000, .max = 3500000 }, | |
244 | .n = { .min = 1, .max = 3 }, | |
245 | .m = { .min = 104, .max = 138 }, | |
246 | .m1 = { .min = 17, .max = 23 }, | |
247 | .m2 = { .min = 5, .max = 11 }, | |
248 | .p = { .min = 14, .max = 42 }, | |
249 | .p1 = { .min = 2, .max = 6 }, | |
250 | .p2 = { .dot_limit = 0, | |
251 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 252 | }, |
e4b36699 KP |
253 | }; |
254 | ||
f2b115e6 | 255 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
256 | .dot = { .min = 20000, .max = 400000}, |
257 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 258 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
259 | .n = { .min = 3, .max = 6 }, |
260 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 261 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
262 | .m1 = { .min = 0, .max = 0 }, |
263 | .m2 = { .min = 0, .max = 254 }, | |
264 | .p = { .min = 5, .max = 80 }, | |
265 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
266 | .p2 = { .dot_limit = 200000, |
267 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
268 | }; |
269 | ||
f2b115e6 | 270 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
271 | .dot = { .min = 20000, .max = 400000 }, |
272 | .vco = { .min = 1700000, .max = 3500000 }, | |
273 | .n = { .min = 3, .max = 6 }, | |
274 | .m = { .min = 2, .max = 256 }, | |
275 | .m1 = { .min = 0, .max = 0 }, | |
276 | .m2 = { .min = 0, .max = 254 }, | |
277 | .p = { .min = 7, .max = 112 }, | |
278 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
279 | .p2 = { .dot_limit = 112000, |
280 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
281 | }; |
282 | ||
273e27ca EA |
283 | /* Ironlake / Sandybridge |
284 | * | |
285 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
286 | * the range value for them is (actual_value - 2). | |
287 | */ | |
b91ad0ec | 288 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
289 | .dot = { .min = 25000, .max = 350000 }, |
290 | .vco = { .min = 1760000, .max = 3510000 }, | |
291 | .n = { .min = 1, .max = 5 }, | |
292 | .m = { .min = 79, .max = 127 }, | |
293 | .m1 = { .min = 12, .max = 22 }, | |
294 | .m2 = { .min = 5, .max = 9 }, | |
295 | .p = { .min = 5, .max = 80 }, | |
296 | .p1 = { .min = 1, .max = 8 }, | |
297 | .p2 = { .dot_limit = 225000, | |
298 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
299 | }; |
300 | ||
b91ad0ec | 301 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
302 | .dot = { .min = 25000, .max = 350000 }, |
303 | .vco = { .min = 1760000, .max = 3510000 }, | |
304 | .n = { .min = 1, .max = 3 }, | |
305 | .m = { .min = 79, .max = 118 }, | |
306 | .m1 = { .min = 12, .max = 22 }, | |
307 | .m2 = { .min = 5, .max = 9 }, | |
308 | .p = { .min = 28, .max = 112 }, | |
309 | .p1 = { .min = 2, .max = 8 }, | |
310 | .p2 = { .dot_limit = 225000, | |
311 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
312 | }; |
313 | ||
314 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
315 | .dot = { .min = 25000, .max = 350000 }, |
316 | .vco = { .min = 1760000, .max = 3510000 }, | |
317 | .n = { .min = 1, .max = 3 }, | |
318 | .m = { .min = 79, .max = 127 }, | |
319 | .m1 = { .min = 12, .max = 22 }, | |
320 | .m2 = { .min = 5, .max = 9 }, | |
321 | .p = { .min = 14, .max = 56 }, | |
322 | .p1 = { .min = 2, .max = 8 }, | |
323 | .p2 = { .dot_limit = 225000, | |
324 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
325 | }; |
326 | ||
273e27ca | 327 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 328 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
329 | .dot = { .min = 25000, .max = 350000 }, |
330 | .vco = { .min = 1760000, .max = 3510000 }, | |
331 | .n = { .min = 1, .max = 2 }, | |
332 | .m = { .min = 79, .max = 126 }, | |
333 | .m1 = { .min = 12, .max = 22 }, | |
334 | .m2 = { .min = 5, .max = 9 }, | |
335 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 336 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
337 | .p2 = { .dot_limit = 225000, |
338 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
339 | }; |
340 | ||
341 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
342 | .dot = { .min = 25000, .max = 350000 }, |
343 | .vco = { .min = 1760000, .max = 3510000 }, | |
344 | .n = { .min = 1, .max = 3 }, | |
345 | .m = { .min = 79, .max = 126 }, | |
346 | .m1 = { .min = 12, .max = 22 }, | |
347 | .m2 = { .min = 5, .max = 9 }, | |
348 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 349 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
350 | .p2 = { .dot_limit = 225000, |
351 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
352 | }; |
353 | ||
dc730512 | 354 | static const intel_limit_t intel_limits_vlv = { |
f01b7962 VS |
355 | /* |
356 | * These are the data rate limits (measured in fast clocks) | |
357 | * since those are the strictest limits we have. The fast | |
358 | * clock and actual rate limits are more relaxed, so checking | |
359 | * them would make no difference. | |
360 | */ | |
361 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 362 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 363 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
364 | .m1 = { .min = 2, .max = 3 }, |
365 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 366 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 367 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
368 | }; |
369 | ||
ef9348c8 CML |
370 | static const intel_limit_t intel_limits_chv = { |
371 | /* | |
372 | * These are the data rate limits (measured in fast clocks) | |
373 | * since those are the strictest limits we have. The fast | |
374 | * clock and actual rate limits are more relaxed, so checking | |
375 | * them would make no difference. | |
376 | */ | |
377 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
378 | .vco = { .min = 4860000, .max = 6700000 }, | |
379 | .n = { .min = 1, .max = 1 }, | |
380 | .m1 = { .min = 2, .max = 2 }, | |
381 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
382 | .p1 = { .min = 2, .max = 4 }, | |
383 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
384 | }; | |
385 | ||
6b4bf1c4 VS |
386 | static void vlv_clock(int refclk, intel_clock_t *clock) |
387 | { | |
388 | clock->m = clock->m1 * clock->m2; | |
389 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
390 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
391 | return; | |
fb03ac01 VS |
392 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
393 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
6b4bf1c4 VS |
394 | } |
395 | ||
e0638cdf PZ |
396 | /** |
397 | * Returns whether any output on the specified pipe is of the specified type | |
398 | */ | |
399 | static bool intel_pipe_has_type(struct drm_crtc *crtc, int type) | |
400 | { | |
401 | struct drm_device *dev = crtc->dev; | |
402 | struct intel_encoder *encoder; | |
403 | ||
404 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
405 | if (encoder->type == type) | |
406 | return true; | |
407 | ||
408 | return false; | |
409 | } | |
410 | ||
1b894b59 CW |
411 | static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, |
412 | int refclk) | |
2c07245f | 413 | { |
b91ad0ec | 414 | struct drm_device *dev = crtc->dev; |
2c07245f | 415 | const intel_limit_t *limit; |
b91ad0ec ZW |
416 | |
417 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 418 | if (intel_is_dual_link_lvds(dev)) { |
1b894b59 | 419 | if (refclk == 100000) |
b91ad0ec ZW |
420 | limit = &intel_limits_ironlake_dual_lvds_100m; |
421 | else | |
422 | limit = &intel_limits_ironlake_dual_lvds; | |
423 | } else { | |
1b894b59 | 424 | if (refclk == 100000) |
b91ad0ec ZW |
425 | limit = &intel_limits_ironlake_single_lvds_100m; |
426 | else | |
427 | limit = &intel_limits_ironlake_single_lvds; | |
428 | } | |
c6bb3538 | 429 | } else |
b91ad0ec | 430 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
431 | |
432 | return limit; | |
433 | } | |
434 | ||
044c7c41 ML |
435 | static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) |
436 | { | |
437 | struct drm_device *dev = crtc->dev; | |
044c7c41 ML |
438 | const intel_limit_t *limit; |
439 | ||
440 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 441 | if (intel_is_dual_link_lvds(dev)) |
e4b36699 | 442 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 | 443 | else |
e4b36699 | 444 | limit = &intel_limits_g4x_single_channel_lvds; |
044c7c41 ML |
445 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || |
446 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 447 | limit = &intel_limits_g4x_hdmi; |
044c7c41 | 448 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 449 | limit = &intel_limits_g4x_sdvo; |
044c7c41 | 450 | } else /* The option is for other outputs */ |
e4b36699 | 451 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
452 | |
453 | return limit; | |
454 | } | |
455 | ||
1b894b59 | 456 | static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk) |
79e53945 JB |
457 | { |
458 | struct drm_device *dev = crtc->dev; | |
459 | const intel_limit_t *limit; | |
460 | ||
bad720ff | 461 | if (HAS_PCH_SPLIT(dev)) |
1b894b59 | 462 | limit = intel_ironlake_limit(crtc, refclk); |
2c07245f | 463 | else if (IS_G4X(dev)) { |
044c7c41 | 464 | limit = intel_g4x_limit(crtc); |
f2b115e6 | 465 | } else if (IS_PINEVIEW(dev)) { |
2177832f | 466 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 467 | limit = &intel_limits_pineview_lvds; |
2177832f | 468 | else |
f2b115e6 | 469 | limit = &intel_limits_pineview_sdvo; |
ef9348c8 CML |
470 | } else if (IS_CHERRYVIEW(dev)) { |
471 | limit = &intel_limits_chv; | |
a0c4da24 | 472 | } else if (IS_VALLEYVIEW(dev)) { |
dc730512 | 473 | limit = &intel_limits_vlv; |
a6c45cf0 CW |
474 | } else if (!IS_GEN2(dev)) { |
475 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
476 | limit = &intel_limits_i9xx_lvds; | |
477 | else | |
478 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 JB |
479 | } else { |
480 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
e4b36699 | 481 | limit = &intel_limits_i8xx_lvds; |
5d536e28 | 482 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO)) |
e4b36699 | 483 | limit = &intel_limits_i8xx_dvo; |
5d536e28 DV |
484 | else |
485 | limit = &intel_limits_i8xx_dac; | |
79e53945 JB |
486 | } |
487 | return limit; | |
488 | } | |
489 | ||
f2b115e6 AJ |
490 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
491 | static void pineview_clock(int refclk, intel_clock_t *clock) | |
79e53945 | 492 | { |
2177832f SL |
493 | clock->m = clock->m2 + 2; |
494 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
495 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
496 | return; | |
fb03ac01 VS |
497 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
498 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
2177832f SL |
499 | } |
500 | ||
7429e9d4 DV |
501 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
502 | { | |
503 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
504 | } | |
505 | ||
ac58c3f0 | 506 | static void i9xx_clock(int refclk, intel_clock_t *clock) |
2177832f | 507 | { |
7429e9d4 | 508 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 509 | clock->p = clock->p1 * clock->p2; |
ed5ca77e VS |
510 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
511 | return; | |
fb03ac01 VS |
512 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
513 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
79e53945 JB |
514 | } |
515 | ||
ef9348c8 CML |
516 | static void chv_clock(int refclk, intel_clock_t *clock) |
517 | { | |
518 | clock->m = clock->m1 * clock->m2; | |
519 | clock->p = clock->p1 * clock->p2; | |
520 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
521 | return; | |
522 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, | |
523 | clock->n << 22); | |
524 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
525 | } | |
526 | ||
7c04d1d9 | 527 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
528 | /** |
529 | * Returns whether the given set of divisors are valid for a given refclk with | |
530 | * the given connectors. | |
531 | */ | |
532 | ||
1b894b59 CW |
533 | static bool intel_PLL_is_valid(struct drm_device *dev, |
534 | const intel_limit_t *limit, | |
535 | const intel_clock_t *clock) | |
79e53945 | 536 | { |
f01b7962 VS |
537 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
538 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 539 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 540 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 541 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 542 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 543 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 544 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 VS |
545 | |
546 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev)) | |
547 | if (clock->m1 <= clock->m2) | |
548 | INTELPllInvalid("m1 <= m2\n"); | |
549 | ||
550 | if (!IS_VALLEYVIEW(dev)) { | |
551 | if (clock->p < limit->p.min || limit->p.max < clock->p) | |
552 | INTELPllInvalid("p out of range\n"); | |
553 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
554 | INTELPllInvalid("m out of range\n"); | |
555 | } | |
556 | ||
79e53945 | 557 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 558 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
559 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
560 | * connector, etc., rather than just a single range. | |
561 | */ | |
562 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 563 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
564 | |
565 | return true; | |
566 | } | |
567 | ||
d4906093 | 568 | static bool |
ee9300bb | 569 | i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
cec2f356 SP |
570 | int target, int refclk, intel_clock_t *match_clock, |
571 | intel_clock_t *best_clock) | |
79e53945 JB |
572 | { |
573 | struct drm_device *dev = crtc->dev; | |
79e53945 | 574 | intel_clock_t clock; |
79e53945 JB |
575 | int err = target; |
576 | ||
a210b028 | 577 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
79e53945 | 578 | /* |
a210b028 DV |
579 | * For LVDS just rely on its current settings for dual-channel. |
580 | * We haven't figured out how to reliably set up different | |
581 | * single/dual channel state, if we even can. | |
79e53945 | 582 | */ |
1974cad0 | 583 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
584 | clock.p2 = limit->p2.p2_fast; |
585 | else | |
586 | clock.p2 = limit->p2.p2_slow; | |
587 | } else { | |
588 | if (target < limit->p2.dot_limit) | |
589 | clock.p2 = limit->p2.p2_slow; | |
590 | else | |
591 | clock.p2 = limit->p2.p2_fast; | |
592 | } | |
593 | ||
0206e353 | 594 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 595 | |
42158660 ZY |
596 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
597 | clock.m1++) { | |
598 | for (clock.m2 = limit->m2.min; | |
599 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 600 | if (clock.m2 >= clock.m1) |
42158660 ZY |
601 | break; |
602 | for (clock.n = limit->n.min; | |
603 | clock.n <= limit->n.max; clock.n++) { | |
604 | for (clock.p1 = limit->p1.min; | |
605 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
606 | int this_err; |
607 | ||
ac58c3f0 DV |
608 | i9xx_clock(refclk, &clock); |
609 | if (!intel_PLL_is_valid(dev, limit, | |
610 | &clock)) | |
611 | continue; | |
612 | if (match_clock && | |
613 | clock.p != match_clock->p) | |
614 | continue; | |
615 | ||
616 | this_err = abs(clock.dot - target); | |
617 | if (this_err < err) { | |
618 | *best_clock = clock; | |
619 | err = this_err; | |
620 | } | |
621 | } | |
622 | } | |
623 | } | |
624 | } | |
625 | ||
626 | return (err != target); | |
627 | } | |
628 | ||
629 | static bool | |
ee9300bb DV |
630 | pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
631 | int target, int refclk, intel_clock_t *match_clock, | |
632 | intel_clock_t *best_clock) | |
79e53945 JB |
633 | { |
634 | struct drm_device *dev = crtc->dev; | |
79e53945 | 635 | intel_clock_t clock; |
79e53945 JB |
636 | int err = target; |
637 | ||
a210b028 | 638 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
79e53945 | 639 | /* |
a210b028 DV |
640 | * For LVDS just rely on its current settings for dual-channel. |
641 | * We haven't figured out how to reliably set up different | |
642 | * single/dual channel state, if we even can. | |
79e53945 | 643 | */ |
1974cad0 | 644 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
645 | clock.p2 = limit->p2.p2_fast; |
646 | else | |
647 | clock.p2 = limit->p2.p2_slow; | |
648 | } else { | |
649 | if (target < limit->p2.dot_limit) | |
650 | clock.p2 = limit->p2.p2_slow; | |
651 | else | |
652 | clock.p2 = limit->p2.p2_fast; | |
653 | } | |
654 | ||
0206e353 | 655 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 656 | |
42158660 ZY |
657 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
658 | clock.m1++) { | |
659 | for (clock.m2 = limit->m2.min; | |
660 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
661 | for (clock.n = limit->n.min; |
662 | clock.n <= limit->n.max; clock.n++) { | |
663 | for (clock.p1 = limit->p1.min; | |
664 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
665 | int this_err; |
666 | ||
ac58c3f0 | 667 | pineview_clock(refclk, &clock); |
1b894b59 CW |
668 | if (!intel_PLL_is_valid(dev, limit, |
669 | &clock)) | |
79e53945 | 670 | continue; |
cec2f356 SP |
671 | if (match_clock && |
672 | clock.p != match_clock->p) | |
673 | continue; | |
79e53945 JB |
674 | |
675 | this_err = abs(clock.dot - target); | |
676 | if (this_err < err) { | |
677 | *best_clock = clock; | |
678 | err = this_err; | |
679 | } | |
680 | } | |
681 | } | |
682 | } | |
683 | } | |
684 | ||
685 | return (err != target); | |
686 | } | |
687 | ||
d4906093 | 688 | static bool |
ee9300bb DV |
689 | g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
690 | int target, int refclk, intel_clock_t *match_clock, | |
691 | intel_clock_t *best_clock) | |
d4906093 ML |
692 | { |
693 | struct drm_device *dev = crtc->dev; | |
d4906093 ML |
694 | intel_clock_t clock; |
695 | int max_n; | |
696 | bool found; | |
6ba770dc AJ |
697 | /* approximately equals target * 0.00585 */ |
698 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
699 | found = false; |
700 | ||
701 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 702 | if (intel_is_dual_link_lvds(dev)) |
d4906093 ML |
703 | clock.p2 = limit->p2.p2_fast; |
704 | else | |
705 | clock.p2 = limit->p2.p2_slow; | |
706 | } else { | |
707 | if (target < limit->p2.dot_limit) | |
708 | clock.p2 = limit->p2.p2_slow; | |
709 | else | |
710 | clock.p2 = limit->p2.p2_fast; | |
711 | } | |
712 | ||
713 | memset(best_clock, 0, sizeof(*best_clock)); | |
714 | max_n = limit->n.max; | |
f77f13e2 | 715 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 716 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 717 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
718 | for (clock.m1 = limit->m1.max; |
719 | clock.m1 >= limit->m1.min; clock.m1--) { | |
720 | for (clock.m2 = limit->m2.max; | |
721 | clock.m2 >= limit->m2.min; clock.m2--) { | |
722 | for (clock.p1 = limit->p1.max; | |
723 | clock.p1 >= limit->p1.min; clock.p1--) { | |
724 | int this_err; | |
725 | ||
ac58c3f0 | 726 | i9xx_clock(refclk, &clock); |
1b894b59 CW |
727 | if (!intel_PLL_is_valid(dev, limit, |
728 | &clock)) | |
d4906093 | 729 | continue; |
1b894b59 CW |
730 | |
731 | this_err = abs(clock.dot - target); | |
d4906093 ML |
732 | if (this_err < err_most) { |
733 | *best_clock = clock; | |
734 | err_most = this_err; | |
735 | max_n = clock.n; | |
736 | found = true; | |
737 | } | |
738 | } | |
739 | } | |
740 | } | |
741 | } | |
2c07245f ZW |
742 | return found; |
743 | } | |
744 | ||
a0c4da24 | 745 | static bool |
ee9300bb DV |
746 | vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
747 | int target, int refclk, intel_clock_t *match_clock, | |
748 | intel_clock_t *best_clock) | |
a0c4da24 | 749 | { |
f01b7962 | 750 | struct drm_device *dev = crtc->dev; |
6b4bf1c4 | 751 | intel_clock_t clock; |
69e4f900 | 752 | unsigned int bestppm = 1000000; |
27e639bf VS |
753 | /* min update 19.2 MHz */ |
754 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 755 | bool found = false; |
a0c4da24 | 756 | |
6b4bf1c4 VS |
757 | target *= 5; /* fast clock */ |
758 | ||
759 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
760 | |
761 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 762 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 763 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 764 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 765 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 766 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 767 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 768 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
69e4f900 VS |
769 | unsigned int ppm, diff; |
770 | ||
6b4bf1c4 VS |
771 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
772 | refclk * clock.m1); | |
773 | ||
774 | vlv_clock(refclk, &clock); | |
43b0ac53 | 775 | |
f01b7962 VS |
776 | if (!intel_PLL_is_valid(dev, limit, |
777 | &clock)) | |
43b0ac53 VS |
778 | continue; |
779 | ||
6b4bf1c4 VS |
780 | diff = abs(clock.dot - target); |
781 | ppm = div_u64(1000000ULL * diff, target); | |
782 | ||
783 | if (ppm < 100 && clock.p > best_clock->p) { | |
43b0ac53 | 784 | bestppm = 0; |
6b4bf1c4 | 785 | *best_clock = clock; |
49e497ef | 786 | found = true; |
43b0ac53 | 787 | } |
6b4bf1c4 | 788 | |
c686122c | 789 | if (bestppm >= 10 && ppm < bestppm - 10) { |
69e4f900 | 790 | bestppm = ppm; |
6b4bf1c4 | 791 | *best_clock = clock; |
49e497ef | 792 | found = true; |
a0c4da24 JB |
793 | } |
794 | } | |
795 | } | |
796 | } | |
797 | } | |
a0c4da24 | 798 | |
49e497ef | 799 | return found; |
a0c4da24 | 800 | } |
a4fc5ed6 | 801 | |
ef9348c8 CML |
802 | static bool |
803 | chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, | |
804 | int target, int refclk, intel_clock_t *match_clock, | |
805 | intel_clock_t *best_clock) | |
806 | { | |
807 | struct drm_device *dev = crtc->dev; | |
808 | intel_clock_t clock; | |
809 | uint64_t m2; | |
810 | int found = false; | |
811 | ||
812 | memset(best_clock, 0, sizeof(*best_clock)); | |
813 | ||
814 | /* | |
815 | * Based on hardware doc, the n always set to 1, and m1 always | |
816 | * set to 2. If requires to support 200Mhz refclk, we need to | |
817 | * revisit this because n may not 1 anymore. | |
818 | */ | |
819 | clock.n = 1, clock.m1 = 2; | |
820 | target *= 5; /* fast clock */ | |
821 | ||
822 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
823 | for (clock.p2 = limit->p2.p2_fast; | |
824 | clock.p2 >= limit->p2.p2_slow; | |
825 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
826 | ||
827 | clock.p = clock.p1 * clock.p2; | |
828 | ||
829 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
830 | clock.n) << 22, refclk * clock.m1); | |
831 | ||
832 | if (m2 > INT_MAX/clock.m1) | |
833 | continue; | |
834 | ||
835 | clock.m2 = m2; | |
836 | ||
837 | chv_clock(refclk, &clock); | |
838 | ||
839 | if (!intel_PLL_is_valid(dev, limit, &clock)) | |
840 | continue; | |
841 | ||
842 | /* based on hardware requirement, prefer bigger p | |
843 | */ | |
844 | if (clock.p > best_clock->p) { | |
845 | *best_clock = clock; | |
846 | found = true; | |
847 | } | |
848 | } | |
849 | } | |
850 | ||
851 | return found; | |
852 | } | |
853 | ||
20ddf665 VS |
854 | bool intel_crtc_active(struct drm_crtc *crtc) |
855 | { | |
856 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
857 | ||
858 | /* Be paranoid as we can arrive here with only partial | |
859 | * state retrieved from the hardware during setup. | |
860 | * | |
241bfc38 | 861 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
862 | * as Haswell has gained clock readout/fastboot support. |
863 | * | |
66e514c1 | 864 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 VS |
865 | * properly reconstruct framebuffers. |
866 | */ | |
f4510a27 | 867 | return intel_crtc->active && crtc->primary->fb && |
241bfc38 | 868 | intel_crtc->config.adjusted_mode.crtc_clock; |
20ddf665 VS |
869 | } |
870 | ||
a5c961d1 PZ |
871 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
872 | enum pipe pipe) | |
873 | { | |
874 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
875 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
876 | ||
3b117c8f | 877 | return intel_crtc->config.cpu_transcoder; |
a5c961d1 PZ |
878 | } |
879 | ||
57e22f4a | 880 | static void g4x_wait_for_vblank(struct drm_device *dev, int pipe) |
a928d536 PZ |
881 | { |
882 | struct drm_i915_private *dev_priv = dev->dev_private; | |
57e22f4a | 883 | u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe); |
a928d536 PZ |
884 | |
885 | frame = I915_READ(frame_reg); | |
886 | ||
887 | if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50)) | |
93937071 | 888 | WARN(1, "vblank wait timed out\n"); |
a928d536 PZ |
889 | } |
890 | ||
9d0498a2 JB |
891 | /** |
892 | * intel_wait_for_vblank - wait for vblank on a given pipe | |
893 | * @dev: drm device | |
894 | * @pipe: pipe to wait for | |
895 | * | |
896 | * Wait for vblank to occur on a given pipe. Needed for various bits of | |
897 | * mode setting code. | |
898 | */ | |
899 | void intel_wait_for_vblank(struct drm_device *dev, int pipe) | |
79e53945 | 900 | { |
9d0498a2 | 901 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 902 | int pipestat_reg = PIPESTAT(pipe); |
9d0498a2 | 903 | |
57e22f4a VS |
904 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
905 | g4x_wait_for_vblank(dev, pipe); | |
a928d536 PZ |
906 | return; |
907 | } | |
908 | ||
300387c0 CW |
909 | /* Clear existing vblank status. Note this will clear any other |
910 | * sticky status fields as well. | |
911 | * | |
912 | * This races with i915_driver_irq_handler() with the result | |
913 | * that either function could miss a vblank event. Here it is not | |
914 | * fatal, as we will either wait upon the next vblank interrupt or | |
915 | * timeout. Generally speaking intel_wait_for_vblank() is only | |
916 | * called during modeset at which time the GPU should be idle and | |
917 | * should *not* be performing page flips and thus not waiting on | |
918 | * vblanks... | |
919 | * Currently, the result of us stealing a vblank from the irq | |
920 | * handler is that a single frame will be skipped during swapbuffers. | |
921 | */ | |
922 | I915_WRITE(pipestat_reg, | |
923 | I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS); | |
924 | ||
9d0498a2 | 925 | /* Wait for vblank interrupt bit to set */ |
481b6af3 CW |
926 | if (wait_for(I915_READ(pipestat_reg) & |
927 | PIPE_VBLANK_INTERRUPT_STATUS, | |
928 | 50)) | |
9d0498a2 JB |
929 | DRM_DEBUG_KMS("vblank wait timed out\n"); |
930 | } | |
931 | ||
fbf49ea2 VS |
932 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
933 | { | |
934 | struct drm_i915_private *dev_priv = dev->dev_private; | |
935 | u32 reg = PIPEDSL(pipe); | |
936 | u32 line1, line2; | |
937 | u32 line_mask; | |
938 | ||
939 | if (IS_GEN2(dev)) | |
940 | line_mask = DSL_LINEMASK_GEN2; | |
941 | else | |
942 | line_mask = DSL_LINEMASK_GEN3; | |
943 | ||
944 | line1 = I915_READ(reg) & line_mask; | |
945 | mdelay(5); | |
946 | line2 = I915_READ(reg) & line_mask; | |
947 | ||
948 | return line1 == line2; | |
949 | } | |
950 | ||
ab7ad7f6 KP |
951 | /* |
952 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
9d0498a2 JB |
953 | * @dev: drm device |
954 | * @pipe: pipe to wait for | |
955 | * | |
956 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
957 | * spinning on the vblank interrupt status bit, since we won't actually | |
958 | * see an interrupt when the pipe is disabled. | |
959 | * | |
ab7ad7f6 KP |
960 | * On Gen4 and above: |
961 | * wait for the pipe register state bit to turn off | |
962 | * | |
963 | * Otherwise: | |
964 | * wait for the display line value to settle (it usually | |
965 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 966 | * |
9d0498a2 | 967 | */ |
58e10eb9 | 968 | void intel_wait_for_pipe_off(struct drm_device *dev, int pipe) |
9d0498a2 JB |
969 | { |
970 | struct drm_i915_private *dev_priv = dev->dev_private; | |
702e7a56 PZ |
971 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
972 | pipe); | |
ab7ad7f6 KP |
973 | |
974 | if (INTEL_INFO(dev)->gen >= 4) { | |
702e7a56 | 975 | int reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
976 | |
977 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
978 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
979 | 100)) | |
284637d9 | 980 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 981 | } else { |
ab7ad7f6 | 982 | /* Wait for the display line to settle */ |
fbf49ea2 | 983 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 984 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 985 | } |
79e53945 JB |
986 | } |
987 | ||
b0ea7d37 DL |
988 | /* |
989 | * ibx_digital_port_connected - is the specified port connected? | |
990 | * @dev_priv: i915 private structure | |
991 | * @port: the port to test | |
992 | * | |
993 | * Returns true if @port is connected, false otherwise. | |
994 | */ | |
995 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, | |
996 | struct intel_digital_port *port) | |
997 | { | |
998 | u32 bit; | |
999 | ||
c36346e3 | 1000 | if (HAS_PCH_IBX(dev_priv->dev)) { |
eba905b2 | 1001 | switch (port->port) { |
c36346e3 DL |
1002 | case PORT_B: |
1003 | bit = SDE_PORTB_HOTPLUG; | |
1004 | break; | |
1005 | case PORT_C: | |
1006 | bit = SDE_PORTC_HOTPLUG; | |
1007 | break; | |
1008 | case PORT_D: | |
1009 | bit = SDE_PORTD_HOTPLUG; | |
1010 | break; | |
1011 | default: | |
1012 | return true; | |
1013 | } | |
1014 | } else { | |
eba905b2 | 1015 | switch (port->port) { |
c36346e3 DL |
1016 | case PORT_B: |
1017 | bit = SDE_PORTB_HOTPLUG_CPT; | |
1018 | break; | |
1019 | case PORT_C: | |
1020 | bit = SDE_PORTC_HOTPLUG_CPT; | |
1021 | break; | |
1022 | case PORT_D: | |
1023 | bit = SDE_PORTD_HOTPLUG_CPT; | |
1024 | break; | |
1025 | default: | |
1026 | return true; | |
1027 | } | |
b0ea7d37 DL |
1028 | } |
1029 | ||
1030 | return I915_READ(SDEISR) & bit; | |
1031 | } | |
1032 | ||
b24e7179 JB |
1033 | static const char *state_string(bool enabled) |
1034 | { | |
1035 | return enabled ? "on" : "off"; | |
1036 | } | |
1037 | ||
1038 | /* Only for pre-ILK configs */ | |
55607e8a DV |
1039 | void assert_pll(struct drm_i915_private *dev_priv, |
1040 | enum pipe pipe, bool state) | |
b24e7179 JB |
1041 | { |
1042 | int reg; | |
1043 | u32 val; | |
1044 | bool cur_state; | |
1045 | ||
1046 | reg = DPLL(pipe); | |
1047 | val = I915_READ(reg); | |
1048 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
1049 | WARN(cur_state != state, | |
1050 | "PLL state assertion failure (expected %s, current %s)\n", | |
1051 | state_string(state), state_string(cur_state)); | |
1052 | } | |
b24e7179 | 1053 | |
23538ef1 JN |
1054 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
1055 | static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) | |
1056 | { | |
1057 | u32 val; | |
1058 | bool cur_state; | |
1059 | ||
1060 | mutex_lock(&dev_priv->dpio_lock); | |
1061 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); | |
1062 | mutex_unlock(&dev_priv->dpio_lock); | |
1063 | ||
1064 | cur_state = val & DSI_PLL_VCO_EN; | |
1065 | WARN(cur_state != state, | |
1066 | "DSI PLL state assertion failure (expected %s, current %s)\n", | |
1067 | state_string(state), state_string(cur_state)); | |
1068 | } | |
1069 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) | |
1070 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) | |
1071 | ||
55607e8a | 1072 | struct intel_shared_dpll * |
e2b78267 DV |
1073 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
1074 | { | |
1075 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
1076 | ||
a43f6e0f | 1077 | if (crtc->config.shared_dpll < 0) |
e2b78267 DV |
1078 | return NULL; |
1079 | ||
a43f6e0f | 1080 | return &dev_priv->shared_dplls[crtc->config.shared_dpll]; |
e2b78267 DV |
1081 | } |
1082 | ||
040484af | 1083 | /* For ILK+ */ |
55607e8a DV |
1084 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
1085 | struct intel_shared_dpll *pll, | |
1086 | bool state) | |
040484af | 1087 | { |
040484af | 1088 | bool cur_state; |
5358901f | 1089 | struct intel_dpll_hw_state hw_state; |
040484af | 1090 | |
9d82aa17 ED |
1091 | if (HAS_PCH_LPT(dev_priv->dev)) { |
1092 | DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n"); | |
1093 | return; | |
1094 | } | |
1095 | ||
92b27b08 | 1096 | if (WARN (!pll, |
46edb027 | 1097 | "asserting DPLL %s with no DPLL\n", state_string(state))) |
ee7b9f93 | 1098 | return; |
ee7b9f93 | 1099 | |
5358901f | 1100 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
92b27b08 | 1101 | WARN(cur_state != state, |
5358901f DV |
1102 | "%s assertion failure (expected %s, current %s)\n", |
1103 | pll->name, state_string(state), state_string(cur_state)); | |
040484af | 1104 | } |
040484af JB |
1105 | |
1106 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
1107 | enum pipe pipe, bool state) | |
1108 | { | |
1109 | int reg; | |
1110 | u32 val; | |
1111 | bool cur_state; | |
ad80a810 PZ |
1112 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1113 | pipe); | |
040484af | 1114 | |
affa9354 PZ |
1115 | if (HAS_DDI(dev_priv->dev)) { |
1116 | /* DDI does not have a specific FDI_TX register */ | |
ad80a810 | 1117 | reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
bf507ef7 | 1118 | val = I915_READ(reg); |
ad80a810 | 1119 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 ED |
1120 | } else { |
1121 | reg = FDI_TX_CTL(pipe); | |
1122 | val = I915_READ(reg); | |
1123 | cur_state = !!(val & FDI_TX_ENABLE); | |
1124 | } | |
040484af JB |
1125 | WARN(cur_state != state, |
1126 | "FDI TX state assertion failure (expected %s, current %s)\n", | |
1127 | state_string(state), state_string(cur_state)); | |
1128 | } | |
1129 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1130 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1131 | ||
1132 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1133 | enum pipe pipe, bool state) | |
1134 | { | |
1135 | int reg; | |
1136 | u32 val; | |
1137 | bool cur_state; | |
1138 | ||
d63fa0dc PZ |
1139 | reg = FDI_RX_CTL(pipe); |
1140 | val = I915_READ(reg); | |
1141 | cur_state = !!(val & FDI_RX_ENABLE); | |
040484af JB |
1142 | WARN(cur_state != state, |
1143 | "FDI RX state assertion failure (expected %s, current %s)\n", | |
1144 | state_string(state), state_string(cur_state)); | |
1145 | } | |
1146 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1147 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1148 | ||
1149 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1150 | enum pipe pipe) | |
1151 | { | |
1152 | int reg; | |
1153 | u32 val; | |
1154 | ||
1155 | /* ILK FDI PLL is always enabled */ | |
3d13ef2e | 1156 | if (INTEL_INFO(dev_priv->dev)->gen == 5) |
040484af JB |
1157 | return; |
1158 | ||
bf507ef7 | 1159 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
affa9354 | 1160 | if (HAS_DDI(dev_priv->dev)) |
bf507ef7 ED |
1161 | return; |
1162 | ||
040484af JB |
1163 | reg = FDI_TX_CTL(pipe); |
1164 | val = I915_READ(reg); | |
1165 | WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); | |
1166 | } | |
1167 | ||
55607e8a DV |
1168 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1169 | enum pipe pipe, bool state) | |
040484af JB |
1170 | { |
1171 | int reg; | |
1172 | u32 val; | |
55607e8a | 1173 | bool cur_state; |
040484af JB |
1174 | |
1175 | reg = FDI_RX_CTL(pipe); | |
1176 | val = I915_READ(reg); | |
55607e8a DV |
1177 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
1178 | WARN(cur_state != state, | |
1179 | "FDI RX PLL assertion failure (expected %s, current %s)\n", | |
1180 | state_string(state), state_string(cur_state)); | |
040484af JB |
1181 | } |
1182 | ||
ea0760cf JB |
1183 | static void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1184 | enum pipe pipe) | |
1185 | { | |
1186 | int pp_reg, lvds_reg; | |
1187 | u32 val; | |
1188 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1189 | bool locked = true; |
ea0760cf JB |
1190 | |
1191 | if (HAS_PCH_SPLIT(dev_priv->dev)) { | |
1192 | pp_reg = PCH_PP_CONTROL; | |
1193 | lvds_reg = PCH_LVDS; | |
1194 | } else { | |
1195 | pp_reg = PP_CONTROL; | |
1196 | lvds_reg = LVDS; | |
1197 | } | |
1198 | ||
1199 | val = I915_READ(pp_reg); | |
1200 | if (!(val & PANEL_POWER_ON) || | |
1201 | ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS)) | |
1202 | locked = false; | |
1203 | ||
1204 | if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT) | |
1205 | panel_pipe = PIPE_B; | |
1206 | ||
1207 | WARN(panel_pipe == pipe && locked, | |
1208 | "panel assertion failure, pipe %c regs locked\n", | |
9db4a9c7 | 1209 | pipe_name(pipe)); |
ea0760cf JB |
1210 | } |
1211 | ||
93ce0ba6 JN |
1212 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1213 | enum pipe pipe, bool state) | |
1214 | { | |
1215 | struct drm_device *dev = dev_priv->dev; | |
1216 | bool cur_state; | |
1217 | ||
d9d82081 | 1218 | if (IS_845G(dev) || IS_I865G(dev)) |
93ce0ba6 | 1219 | cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE; |
d9d82081 | 1220 | else |
5efb3e28 | 1221 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 JN |
1222 | |
1223 | WARN(cur_state != state, | |
1224 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", | |
1225 | pipe_name(pipe), state_string(state), state_string(cur_state)); | |
1226 | } | |
1227 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1228 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1229 | ||
b840d907 JB |
1230 | void assert_pipe(struct drm_i915_private *dev_priv, |
1231 | enum pipe pipe, bool state) | |
b24e7179 JB |
1232 | { |
1233 | int reg; | |
1234 | u32 val; | |
63d7bbe9 | 1235 | bool cur_state; |
702e7a56 PZ |
1236 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1237 | pipe); | |
b24e7179 | 1238 | |
8e636784 DV |
1239 | /* if we need the pipe A quirk it must be always on */ |
1240 | if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) | |
1241 | state = true; | |
1242 | ||
da7e29bd | 1243 | if (!intel_display_power_enabled(dev_priv, |
b97186f0 | 1244 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { |
69310161 PZ |
1245 | cur_state = false; |
1246 | } else { | |
1247 | reg = PIPECONF(cpu_transcoder); | |
1248 | val = I915_READ(reg); | |
1249 | cur_state = !!(val & PIPECONF_ENABLE); | |
1250 | } | |
1251 | ||
63d7bbe9 JB |
1252 | WARN(cur_state != state, |
1253 | "pipe %c assertion failure (expected %s, current %s)\n", | |
9db4a9c7 | 1254 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
b24e7179 JB |
1255 | } |
1256 | ||
931872fc CW |
1257 | static void assert_plane(struct drm_i915_private *dev_priv, |
1258 | enum plane plane, bool state) | |
b24e7179 JB |
1259 | { |
1260 | int reg; | |
1261 | u32 val; | |
931872fc | 1262 | bool cur_state; |
b24e7179 JB |
1263 | |
1264 | reg = DSPCNTR(plane); | |
1265 | val = I915_READ(reg); | |
931872fc CW |
1266 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
1267 | WARN(cur_state != state, | |
1268 | "plane %c assertion failure (expected %s, current %s)\n", | |
1269 | plane_name(plane), state_string(state), state_string(cur_state)); | |
b24e7179 JB |
1270 | } |
1271 | ||
931872fc CW |
1272 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1273 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1274 | ||
b24e7179 JB |
1275 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1276 | enum pipe pipe) | |
1277 | { | |
653e1026 | 1278 | struct drm_device *dev = dev_priv->dev; |
b24e7179 JB |
1279 | int reg, i; |
1280 | u32 val; | |
1281 | int cur_pipe; | |
1282 | ||
653e1026 VS |
1283 | /* Primary planes are fixed to pipes on gen4+ */ |
1284 | if (INTEL_INFO(dev)->gen >= 4) { | |
28c05794 AJ |
1285 | reg = DSPCNTR(pipe); |
1286 | val = I915_READ(reg); | |
83f26f16 | 1287 | WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1288 | "plane %c assertion failure, should be disabled but not\n", |
1289 | plane_name(pipe)); | |
19ec1358 | 1290 | return; |
28c05794 | 1291 | } |
19ec1358 | 1292 | |
b24e7179 | 1293 | /* Need to check both planes against the pipe */ |
08e2a7de | 1294 | for_each_pipe(i) { |
b24e7179 JB |
1295 | reg = DSPCNTR(i); |
1296 | val = I915_READ(reg); | |
1297 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
1298 | DISPPLANE_SEL_PIPE_SHIFT; | |
1299 | WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, | |
9db4a9c7 JB |
1300 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1301 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1302 | } |
1303 | } | |
1304 | ||
19332d7a JB |
1305 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1306 | enum pipe pipe) | |
1307 | { | |
20674eef | 1308 | struct drm_device *dev = dev_priv->dev; |
1fe47785 | 1309 | int reg, sprite; |
19332d7a JB |
1310 | u32 val; |
1311 | ||
20674eef | 1312 | if (IS_VALLEYVIEW(dev)) { |
1fe47785 DL |
1313 | for_each_sprite(pipe, sprite) { |
1314 | reg = SPCNTR(pipe, sprite); | |
20674eef | 1315 | val = I915_READ(reg); |
83f26f16 | 1316 | WARN(val & SP_ENABLE, |
20674eef | 1317 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1318 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef VS |
1319 | } |
1320 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
1321 | reg = SPRCTL(pipe); | |
19332d7a | 1322 | val = I915_READ(reg); |
83f26f16 | 1323 | WARN(val & SPRITE_ENABLE, |
06da8da2 | 1324 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1325 | plane_name(pipe), pipe_name(pipe)); |
1326 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
1327 | reg = DVSCNTR(pipe); | |
19332d7a | 1328 | val = I915_READ(reg); |
83f26f16 | 1329 | WARN(val & DVS_ENABLE, |
06da8da2 | 1330 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1331 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1332 | } |
1333 | } | |
1334 | ||
89eff4be | 1335 | static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
92f2584a JB |
1336 | { |
1337 | u32 val; | |
1338 | bool enabled; | |
1339 | ||
89eff4be | 1340 | WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))); |
9d82aa17 | 1341 | |
92f2584a JB |
1342 | val = I915_READ(PCH_DREF_CONTROL); |
1343 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1344 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
1345 | WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); | |
1346 | } | |
1347 | ||
ab9412ba DV |
1348 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1349 | enum pipe pipe) | |
92f2584a JB |
1350 | { |
1351 | int reg; | |
1352 | u32 val; | |
1353 | bool enabled; | |
1354 | ||
ab9412ba | 1355 | reg = PCH_TRANSCONF(pipe); |
92f2584a JB |
1356 | val = I915_READ(reg); |
1357 | enabled = !!(val & TRANS_ENABLE); | |
9db4a9c7 JB |
1358 | WARN(enabled, |
1359 | "transcoder assertion failed, should be off on pipe %c but is still active\n", | |
1360 | pipe_name(pipe)); | |
92f2584a JB |
1361 | } |
1362 | ||
4e634389 KP |
1363 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1364 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1365 | { |
1366 | if ((val & DP_PORT_EN) == 0) | |
1367 | return false; | |
1368 | ||
1369 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1370 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); | |
1371 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); | |
1372 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) | |
1373 | return false; | |
44f37d1f CML |
1374 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1375 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) | |
1376 | return false; | |
f0575e92 KP |
1377 | } else { |
1378 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1379 | return false; | |
1380 | } | |
1381 | return true; | |
1382 | } | |
1383 | ||
1519b995 KP |
1384 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1385 | enum pipe pipe, u32 val) | |
1386 | { | |
dc0fa718 | 1387 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1388 | return false; |
1389 | ||
1390 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
dc0fa718 | 1391 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1392 | return false; |
44f37d1f CML |
1393 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1394 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) | |
1395 | return false; | |
1519b995 | 1396 | } else { |
dc0fa718 | 1397 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1398 | return false; |
1399 | } | |
1400 | return true; | |
1401 | } | |
1402 | ||
1403 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1404 | enum pipe pipe, u32 val) | |
1405 | { | |
1406 | if ((val & LVDS_PORT_EN) == 0) | |
1407 | return false; | |
1408 | ||
1409 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1410 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1411 | return false; | |
1412 | } else { | |
1413 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1414 | return false; | |
1415 | } | |
1416 | return true; | |
1417 | } | |
1418 | ||
1419 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1420 | enum pipe pipe, u32 val) | |
1421 | { | |
1422 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1423 | return false; | |
1424 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1425 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1426 | return false; | |
1427 | } else { | |
1428 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1429 | return false; | |
1430 | } | |
1431 | return true; | |
1432 | } | |
1433 | ||
291906f1 | 1434 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0575e92 | 1435 | enum pipe pipe, int reg, u32 port_sel) |
291906f1 | 1436 | { |
47a05eca | 1437 | u32 val = I915_READ(reg); |
4e634389 | 1438 | WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1439 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1440 | reg, pipe_name(pipe)); |
de9a35ab | 1441 | |
75c5da27 DV |
1442 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
1443 | && (val & DP_PIPEB_SELECT), | |
de9a35ab | 1444 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1445 | } |
1446 | ||
1447 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
1448 | enum pipe pipe, int reg) | |
1449 | { | |
47a05eca | 1450 | u32 val = I915_READ(reg); |
b70ad586 | 1451 | WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1452 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1453 | reg, pipe_name(pipe)); |
de9a35ab | 1454 | |
dc0fa718 | 1455 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1456 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1457 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1458 | } |
1459 | ||
1460 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1461 | enum pipe pipe) | |
1462 | { | |
1463 | int reg; | |
1464 | u32 val; | |
291906f1 | 1465 | |
f0575e92 KP |
1466 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1467 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1468 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 JB |
1469 | |
1470 | reg = PCH_ADPA; | |
1471 | val = I915_READ(reg); | |
b70ad586 | 1472 | WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1473 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1474 | pipe_name(pipe)); |
291906f1 JB |
1475 | |
1476 | reg = PCH_LVDS; | |
1477 | val = I915_READ(reg); | |
b70ad586 | 1478 | WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1479 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1480 | pipe_name(pipe)); |
291906f1 | 1481 | |
e2debe91 PZ |
1482 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1483 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1484 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1485 | } |
1486 | ||
40e9cf64 JB |
1487 | static void intel_init_dpio(struct drm_device *dev) |
1488 | { | |
1489 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1490 | ||
1491 | if (!IS_VALLEYVIEW(dev)) | |
1492 | return; | |
1493 | ||
a09caddd CML |
1494 | /* |
1495 | * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C), | |
1496 | * CHV x1 PHY (DP/HDMI D) | |
1497 | * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C) | |
1498 | */ | |
1499 | if (IS_CHERRYVIEW(dev)) { | |
1500 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2; | |
1501 | DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO; | |
1502 | } else { | |
1503 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO; | |
1504 | } | |
5382f5f3 JB |
1505 | } |
1506 | ||
1507 | static void intel_reset_dpio(struct drm_device *dev) | |
1508 | { | |
1509 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1510 | ||
1511 | if (!IS_VALLEYVIEW(dev)) | |
1512 | return; | |
1513 | ||
076ed3b2 CML |
1514 | if (IS_CHERRYVIEW(dev)) { |
1515 | enum dpio_phy phy; | |
1516 | u32 val; | |
1517 | ||
1518 | for (phy = DPIO_PHY0; phy < I915_NUM_PHYS_VLV; phy++) { | |
1519 | /* Poll for phypwrgood signal */ | |
1520 | if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & | |
1521 | PHY_POWERGOOD(phy), 1)) | |
1522 | DRM_ERROR("Display PHY %d is not power up\n", phy); | |
1523 | ||
1524 | /* | |
1525 | * Deassert common lane reset for PHY. | |
1526 | * | |
1527 | * This should only be done on init and resume from S3 | |
1528 | * with both PLLs disabled, or we risk losing DPIO and | |
1529 | * PLL synchronization. | |
1530 | */ | |
1531 | val = I915_READ(DISPLAY_PHY_CONTROL); | |
1532 | I915_WRITE(DISPLAY_PHY_CONTROL, | |
1533 | PHY_COM_LANE_RESET_DEASSERT(phy, val)); | |
1534 | } | |
1535 | ||
1536 | } else { | |
1537 | /* | |
57021059 JB |
1538 | * If DPIO has already been reset, e.g. by BIOS, just skip all |
1539 | * this. | |
076ed3b2 | 1540 | */ |
57021059 JB |
1541 | if (I915_READ(DPIO_CTL) & DPIO_CMNRST) |
1542 | return; | |
1543 | ||
1544 | /* | |
1545 | * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx: | |
1546 | * Need to assert and de-assert PHY SB reset by gating the | |
1547 | * common lane power, then un-gating it. | |
1548 | * Simply ungating isn't enough to reset the PHY enough to get | |
1549 | * ports and lanes running. | |
1550 | */ | |
1551 | __vlv_set_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC, | |
1552 | false); | |
1553 | __vlv_set_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC, | |
1554 | true); | |
076ed3b2 | 1555 | } |
40e9cf64 JB |
1556 | } |
1557 | ||
426115cf | 1558 | static void vlv_enable_pll(struct intel_crtc *crtc) |
87442f73 | 1559 | { |
426115cf DV |
1560 | struct drm_device *dev = crtc->base.dev; |
1561 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1562 | int reg = DPLL(crtc->pipe); | |
1563 | u32 dpll = crtc->config.dpll_hw_state.dpll; | |
87442f73 | 1564 | |
426115cf | 1565 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87442f73 DV |
1566 | |
1567 | /* No really, not for ILK+ */ | |
1568 | BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); | |
1569 | ||
1570 | /* PLL is protected by panel, make sure we can write it */ | |
1571 | if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev)) | |
426115cf | 1572 | assert_panel_unlocked(dev_priv, crtc->pipe); |
87442f73 | 1573 | |
426115cf DV |
1574 | I915_WRITE(reg, dpll); |
1575 | POSTING_READ(reg); | |
1576 | udelay(150); | |
1577 | ||
1578 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
1579 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); | |
1580 | ||
1581 | I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md); | |
1582 | POSTING_READ(DPLL_MD(crtc->pipe)); | |
87442f73 DV |
1583 | |
1584 | /* We do this three times for luck */ | |
426115cf | 1585 | I915_WRITE(reg, dpll); |
87442f73 DV |
1586 | POSTING_READ(reg); |
1587 | udelay(150); /* wait for warmup */ | |
426115cf | 1588 | I915_WRITE(reg, dpll); |
87442f73 DV |
1589 | POSTING_READ(reg); |
1590 | udelay(150); /* wait for warmup */ | |
426115cf | 1591 | I915_WRITE(reg, dpll); |
87442f73 DV |
1592 | POSTING_READ(reg); |
1593 | udelay(150); /* wait for warmup */ | |
1594 | } | |
1595 | ||
9d556c99 CML |
1596 | static void chv_enable_pll(struct intel_crtc *crtc) |
1597 | { | |
1598 | struct drm_device *dev = crtc->base.dev; | |
1599 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1600 | int pipe = crtc->pipe; | |
1601 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9d556c99 CML |
1602 | u32 tmp; |
1603 | ||
1604 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
1605 | ||
1606 | BUG_ON(!IS_CHERRYVIEW(dev_priv->dev)); | |
1607 | ||
1608 | mutex_lock(&dev_priv->dpio_lock); | |
1609 | ||
1610 | /* Enable back the 10bit clock to display controller */ | |
1611 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1612 | tmp |= DPIO_DCLKP_EN; | |
1613 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1614 | ||
1615 | /* | |
1616 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1617 | */ | |
1618 | udelay(1); | |
1619 | ||
1620 | /* Enable PLL */ | |
a11b0703 | 1621 | I915_WRITE(DPLL(pipe), crtc->config.dpll_hw_state.dpll); |
9d556c99 CML |
1622 | |
1623 | /* Check PLL is locked */ | |
a11b0703 | 1624 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
9d556c99 CML |
1625 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
1626 | ||
a11b0703 VS |
1627 | /* not sure when this should be written */ |
1628 | I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md); | |
1629 | POSTING_READ(DPLL_MD(pipe)); | |
1630 | ||
9d556c99 CML |
1631 | mutex_unlock(&dev_priv->dpio_lock); |
1632 | } | |
1633 | ||
66e3d5c0 | 1634 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1635 | { |
66e3d5c0 DV |
1636 | struct drm_device *dev = crtc->base.dev; |
1637 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1638 | int reg = DPLL(crtc->pipe); | |
1639 | u32 dpll = crtc->config.dpll_hw_state.dpll; | |
63d7bbe9 | 1640 | |
66e3d5c0 | 1641 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1642 | |
63d7bbe9 | 1643 | /* No really, not for ILK+ */ |
3d13ef2e | 1644 | BUG_ON(INTEL_INFO(dev)->gen >= 5); |
63d7bbe9 JB |
1645 | |
1646 | /* PLL is protected by panel, make sure we can write it */ | |
66e3d5c0 DV |
1647 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1648 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1649 | |
66e3d5c0 DV |
1650 | I915_WRITE(reg, dpll); |
1651 | ||
1652 | /* Wait for the clocks to stabilize. */ | |
1653 | POSTING_READ(reg); | |
1654 | udelay(150); | |
1655 | ||
1656 | if (INTEL_INFO(dev)->gen >= 4) { | |
1657 | I915_WRITE(DPLL_MD(crtc->pipe), | |
1658 | crtc->config.dpll_hw_state.dpll_md); | |
1659 | } else { | |
1660 | /* The pixel multiplier can only be updated once the | |
1661 | * DPLL is enabled and the clocks are stable. | |
1662 | * | |
1663 | * So write it again. | |
1664 | */ | |
1665 | I915_WRITE(reg, dpll); | |
1666 | } | |
63d7bbe9 JB |
1667 | |
1668 | /* We do this three times for luck */ | |
66e3d5c0 | 1669 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1670 | POSTING_READ(reg); |
1671 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1672 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1673 | POSTING_READ(reg); |
1674 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1675 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1676 | POSTING_READ(reg); |
1677 | udelay(150); /* wait for warmup */ | |
1678 | } | |
1679 | ||
1680 | /** | |
50b44a44 | 1681 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1682 | * @dev_priv: i915 private structure |
1683 | * @pipe: pipe PLL to disable | |
1684 | * | |
1685 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1686 | * | |
1687 | * Note! This is for pre-ILK only. | |
1688 | */ | |
50b44a44 | 1689 | static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
63d7bbe9 | 1690 | { |
63d7bbe9 JB |
1691 | /* Don't disable pipe A or pipe A PLLs if needed */ |
1692 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
1693 | return; | |
1694 | ||
1695 | /* Make sure the pipe isn't still relying on us */ | |
1696 | assert_pipe_disabled(dev_priv, pipe); | |
1697 | ||
50b44a44 DV |
1698 | I915_WRITE(DPLL(pipe), 0); |
1699 | POSTING_READ(DPLL(pipe)); | |
63d7bbe9 JB |
1700 | } |
1701 | ||
f6071166 JB |
1702 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1703 | { | |
1704 | u32 val = 0; | |
1705 | ||
1706 | /* Make sure the pipe isn't still relying on us */ | |
1707 | assert_pipe_disabled(dev_priv, pipe); | |
1708 | ||
e5cbfbfb ID |
1709 | /* |
1710 | * Leave integrated clock source and reference clock enabled for pipe B. | |
1711 | * The latter is needed for VGA hotplug / manual detection. | |
1712 | */ | |
f6071166 | 1713 | if (pipe == PIPE_B) |
e5cbfbfb | 1714 | val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV; |
f6071166 JB |
1715 | I915_WRITE(DPLL(pipe), val); |
1716 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1717 | |
1718 | } | |
1719 | ||
1720 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1721 | { | |
d752048d | 1722 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1723 | u32 val; |
1724 | ||
a11b0703 VS |
1725 | /* Make sure the pipe isn't still relying on us */ |
1726 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1727 | |
a11b0703 VS |
1728 | /* Set PLL en = 0 */ |
1729 | val = DPLL_SSC_REF_CLOCK_CHV; | |
1730 | if (pipe != PIPE_A) | |
1731 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1732 | I915_WRITE(DPLL(pipe), val); | |
1733 | POSTING_READ(DPLL(pipe)); | |
d752048d VS |
1734 | |
1735 | mutex_lock(&dev_priv->dpio_lock); | |
1736 | ||
1737 | /* Disable 10bit clock to display controller */ | |
1738 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1739 | val &= ~DPIO_DCLKP_EN; | |
1740 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1741 | ||
61407f6d VS |
1742 | /* disable left/right clock distribution */ |
1743 | if (pipe != PIPE_B) { | |
1744 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); | |
1745 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); | |
1746 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); | |
1747 | } else { | |
1748 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); | |
1749 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); | |
1750 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); | |
1751 | } | |
1752 | ||
d752048d | 1753 | mutex_unlock(&dev_priv->dpio_lock); |
f6071166 JB |
1754 | } |
1755 | ||
e4607fcf CML |
1756 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
1757 | struct intel_digital_port *dport) | |
89b667f8 JB |
1758 | { |
1759 | u32 port_mask; | |
00fc31b7 | 1760 | int dpll_reg; |
89b667f8 | 1761 | |
e4607fcf CML |
1762 | switch (dport->port) { |
1763 | case PORT_B: | |
89b667f8 | 1764 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1765 | dpll_reg = DPLL(0); |
e4607fcf CML |
1766 | break; |
1767 | case PORT_C: | |
89b667f8 | 1768 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 CML |
1769 | dpll_reg = DPLL(0); |
1770 | break; | |
1771 | case PORT_D: | |
1772 | port_mask = DPLL_PORTD_READY_MASK; | |
1773 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1774 | break; |
1775 | default: | |
1776 | BUG(); | |
1777 | } | |
89b667f8 | 1778 | |
00fc31b7 | 1779 | if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000)) |
89b667f8 | 1780 | WARN(1, "timed out waiting for port %c ready: 0x%08x\n", |
00fc31b7 | 1781 | port_name(dport->port), I915_READ(dpll_reg)); |
89b667f8 JB |
1782 | } |
1783 | ||
b14b1055 DV |
1784 | static void intel_prepare_shared_dpll(struct intel_crtc *crtc) |
1785 | { | |
1786 | struct drm_device *dev = crtc->base.dev; | |
1787 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1788 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
1789 | ||
be19f0ff CW |
1790 | if (WARN_ON(pll == NULL)) |
1791 | return; | |
1792 | ||
b14b1055 DV |
1793 | WARN_ON(!pll->refcount); |
1794 | if (pll->active == 0) { | |
1795 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); | |
1796 | WARN_ON(pll->on); | |
1797 | assert_shared_dpll_disabled(dev_priv, pll); | |
1798 | ||
1799 | pll->mode_set(dev_priv, pll); | |
1800 | } | |
1801 | } | |
1802 | ||
92f2584a | 1803 | /** |
85b3894f | 1804 | * intel_enable_shared_dpll - enable PCH PLL |
92f2584a JB |
1805 | * @dev_priv: i915 private structure |
1806 | * @pipe: pipe PLL to enable | |
1807 | * | |
1808 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1809 | * drives the transcoder clock. | |
1810 | */ | |
85b3894f | 1811 | static void intel_enable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1812 | { |
3d13ef2e DL |
1813 | struct drm_device *dev = crtc->base.dev; |
1814 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1815 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
92f2584a | 1816 | |
87a875bb | 1817 | if (WARN_ON(pll == NULL)) |
48da64a8 CW |
1818 | return; |
1819 | ||
1820 | if (WARN_ON(pll->refcount == 0)) | |
1821 | return; | |
ee7b9f93 | 1822 | |
46edb027 DV |
1823 | DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n", |
1824 | pll->name, pll->active, pll->on, | |
e2b78267 | 1825 | crtc->base.base.id); |
92f2584a | 1826 | |
cdbd2316 DV |
1827 | if (pll->active++) { |
1828 | WARN_ON(!pll->on); | |
e9d6944e | 1829 | assert_shared_dpll_enabled(dev_priv, pll); |
ee7b9f93 JB |
1830 | return; |
1831 | } | |
f4a091c7 | 1832 | WARN_ON(pll->on); |
ee7b9f93 | 1833 | |
46edb027 | 1834 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
e7b903d2 | 1835 | pll->enable(dev_priv, pll); |
ee7b9f93 | 1836 | pll->on = true; |
92f2584a JB |
1837 | } |
1838 | ||
e2b78267 | 1839 | static void intel_disable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1840 | { |
3d13ef2e DL |
1841 | struct drm_device *dev = crtc->base.dev; |
1842 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1843 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
4c609cb8 | 1844 | |
92f2584a | 1845 | /* PCH only available on ILK+ */ |
3d13ef2e | 1846 | BUG_ON(INTEL_INFO(dev)->gen < 5); |
87a875bb | 1847 | if (WARN_ON(pll == NULL)) |
ee7b9f93 | 1848 | return; |
92f2584a | 1849 | |
48da64a8 CW |
1850 | if (WARN_ON(pll->refcount == 0)) |
1851 | return; | |
7a419866 | 1852 | |
46edb027 DV |
1853 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
1854 | pll->name, pll->active, pll->on, | |
e2b78267 | 1855 | crtc->base.base.id); |
7a419866 | 1856 | |
48da64a8 | 1857 | if (WARN_ON(pll->active == 0)) { |
e9d6944e | 1858 | assert_shared_dpll_disabled(dev_priv, pll); |
48da64a8 CW |
1859 | return; |
1860 | } | |
1861 | ||
e9d6944e | 1862 | assert_shared_dpll_enabled(dev_priv, pll); |
f4a091c7 | 1863 | WARN_ON(!pll->on); |
cdbd2316 | 1864 | if (--pll->active) |
7a419866 | 1865 | return; |
ee7b9f93 | 1866 | |
46edb027 | 1867 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
e7b903d2 | 1868 | pll->disable(dev_priv, pll); |
ee7b9f93 | 1869 | pll->on = false; |
92f2584a JB |
1870 | } |
1871 | ||
b8a4f404 PZ |
1872 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1873 | enum pipe pipe) | |
040484af | 1874 | { |
23670b32 | 1875 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1876 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1877 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
23670b32 | 1878 | uint32_t reg, val, pipeconf_val; |
040484af JB |
1879 | |
1880 | /* PCH only available on ILK+ */ | |
3d13ef2e | 1881 | BUG_ON(INTEL_INFO(dev)->gen < 5); |
040484af JB |
1882 | |
1883 | /* Make sure PCH DPLL is enabled */ | |
e72f9fbf | 1884 | assert_shared_dpll_enabled(dev_priv, |
e9d6944e | 1885 | intel_crtc_to_shared_dpll(intel_crtc)); |
040484af JB |
1886 | |
1887 | /* FDI must be feeding us bits for PCH ports */ | |
1888 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1889 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1890 | ||
23670b32 DV |
1891 | if (HAS_PCH_CPT(dev)) { |
1892 | /* Workaround: Set the timing override bit before enabling the | |
1893 | * pch transcoder. */ | |
1894 | reg = TRANS_CHICKEN2(pipe); | |
1895 | val = I915_READ(reg); | |
1896 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1897 | I915_WRITE(reg, val); | |
59c859d6 | 1898 | } |
23670b32 | 1899 | |
ab9412ba | 1900 | reg = PCH_TRANSCONF(pipe); |
040484af | 1901 | val = I915_READ(reg); |
5f7f726d | 1902 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
1903 | |
1904 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
1905 | /* | |
1906 | * make the BPC in transcoder be consistent with | |
1907 | * that in pipeconf reg. | |
1908 | */ | |
dfd07d72 DV |
1909 | val &= ~PIPECONF_BPC_MASK; |
1910 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1911 | } |
5f7f726d PZ |
1912 | |
1913 | val &= ~TRANS_INTERLACE_MASK; | |
1914 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 PZ |
1915 | if (HAS_PCH_IBX(dev_priv->dev) && |
1916 | intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) | |
1917 | val |= TRANS_LEGACY_INTERLACED_ILK; | |
1918 | else | |
1919 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1920 | else |
1921 | val |= TRANS_PROGRESSIVE; | |
1922 | ||
040484af JB |
1923 | I915_WRITE(reg, val | TRANS_ENABLE); |
1924 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
4bb6f1f3 | 1925 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
1926 | } |
1927 | ||
8fb033d7 | 1928 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 1929 | enum transcoder cpu_transcoder) |
040484af | 1930 | { |
8fb033d7 | 1931 | u32 val, pipeconf_val; |
8fb033d7 PZ |
1932 | |
1933 | /* PCH only available on ILK+ */ | |
3d13ef2e | 1934 | BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5); |
8fb033d7 | 1935 | |
8fb033d7 | 1936 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 1937 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 1938 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 1939 | |
223a6fdf PZ |
1940 | /* Workaround: set timing override bit. */ |
1941 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 1942 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf PZ |
1943 | I915_WRITE(_TRANSA_CHICKEN2, val); |
1944 | ||
25f3ef11 | 1945 | val = TRANS_ENABLE; |
937bb610 | 1946 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 1947 | |
9a76b1c6 PZ |
1948 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1949 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 1950 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
1951 | else |
1952 | val |= TRANS_PROGRESSIVE; | |
1953 | ||
ab9412ba DV |
1954 | I915_WRITE(LPT_TRANSCONF, val); |
1955 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) | |
937bb610 | 1956 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
1957 | } |
1958 | ||
b8a4f404 PZ |
1959 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1960 | enum pipe pipe) | |
040484af | 1961 | { |
23670b32 DV |
1962 | struct drm_device *dev = dev_priv->dev; |
1963 | uint32_t reg, val; | |
040484af JB |
1964 | |
1965 | /* FDI relies on the transcoder */ | |
1966 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1967 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1968 | ||
291906f1 JB |
1969 | /* Ports must be off as well */ |
1970 | assert_pch_ports_disabled(dev_priv, pipe); | |
1971 | ||
ab9412ba | 1972 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
1973 | val = I915_READ(reg); |
1974 | val &= ~TRANS_ENABLE; | |
1975 | I915_WRITE(reg, val); | |
1976 | /* wait for PCH transcoder off, transcoder state */ | |
1977 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4bb6f1f3 | 1978 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 DV |
1979 | |
1980 | if (!HAS_PCH_IBX(dev)) { | |
1981 | /* Workaround: Clear the timing override chicken bit again. */ | |
1982 | reg = TRANS_CHICKEN2(pipe); | |
1983 | val = I915_READ(reg); | |
1984 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1985 | I915_WRITE(reg, val); | |
1986 | } | |
040484af JB |
1987 | } |
1988 | ||
ab4d966c | 1989 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 1990 | { |
8fb033d7 PZ |
1991 | u32 val; |
1992 | ||
ab9412ba | 1993 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 1994 | val &= ~TRANS_ENABLE; |
ab9412ba | 1995 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 1996 | /* wait for PCH transcoder off, transcoder state */ |
ab9412ba | 1997 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
8a52fd9f | 1998 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
1999 | |
2000 | /* Workaround: clear timing override bit. */ | |
2001 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 2002 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf | 2003 | I915_WRITE(_TRANSA_CHICKEN2, val); |
040484af JB |
2004 | } |
2005 | ||
b24e7179 | 2006 | /** |
309cfea8 | 2007 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 2008 | * @crtc: crtc responsible for the pipe |
b24e7179 | 2009 | * |
0372264a | 2010 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 2011 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 2012 | */ |
e1fdc473 | 2013 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2014 | { |
0372264a PZ |
2015 | struct drm_device *dev = crtc->base.dev; |
2016 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2017 | enum pipe pipe = crtc->pipe; | |
702e7a56 PZ |
2018 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
2019 | pipe); | |
1a240d4d | 2020 | enum pipe pch_transcoder; |
b24e7179 JB |
2021 | int reg; |
2022 | u32 val; | |
2023 | ||
58c6eaa2 | 2024 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 2025 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
2026 | assert_sprites_disabled(dev_priv, pipe); |
2027 | ||
681e5811 | 2028 | if (HAS_PCH_LPT(dev_priv->dev)) |
cc391bbb PZ |
2029 | pch_transcoder = TRANSCODER_A; |
2030 | else | |
2031 | pch_transcoder = pipe; | |
2032 | ||
b24e7179 JB |
2033 | /* |
2034 | * A pipe without a PLL won't actually be able to drive bits from | |
2035 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
2036 | * need the check. | |
2037 | */ | |
2038 | if (!HAS_PCH_SPLIT(dev_priv->dev)) | |
fbf3218a | 2039 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI)) |
23538ef1 JN |
2040 | assert_dsi_pll_enabled(dev_priv); |
2041 | else | |
2042 | assert_pll_enabled(dev_priv, pipe); | |
040484af | 2043 | else { |
30421c4f | 2044 | if (crtc->config.has_pch_encoder) { |
040484af | 2045 | /* if driving the PCH, we need FDI enabled */ |
cc391bbb | 2046 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
2047 | assert_fdi_tx_pll_enabled(dev_priv, |
2048 | (enum pipe) cpu_transcoder); | |
040484af JB |
2049 | } |
2050 | /* FIXME: assert CPU port conditions for SNB+ */ | |
2051 | } | |
b24e7179 | 2052 | |
702e7a56 | 2053 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2054 | val = I915_READ(reg); |
7ad25d48 PZ |
2055 | if (val & PIPECONF_ENABLE) { |
2056 | WARN_ON(!(pipe == PIPE_A && | |
2057 | dev_priv->quirks & QUIRK_PIPEA_FORCE)); | |
00d70b15 | 2058 | return; |
7ad25d48 | 2059 | } |
00d70b15 CW |
2060 | |
2061 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 2062 | POSTING_READ(reg); |
b24e7179 JB |
2063 | } |
2064 | ||
2065 | /** | |
309cfea8 | 2066 | * intel_disable_pipe - disable a pipe, asserting requirements |
b24e7179 JB |
2067 | * @dev_priv: i915 private structure |
2068 | * @pipe: pipe to disable | |
2069 | * | |
2070 | * Disable @pipe, making sure that various hardware specific requirements | |
2071 | * are met, if applicable, e.g. plane disabled, panel fitter off, etc. | |
2072 | * | |
2073 | * @pipe should be %PIPE_A or %PIPE_B. | |
2074 | * | |
2075 | * Will wait until the pipe has shut down before returning. | |
2076 | */ | |
2077 | static void intel_disable_pipe(struct drm_i915_private *dev_priv, | |
2078 | enum pipe pipe) | |
2079 | { | |
702e7a56 PZ |
2080 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
2081 | pipe); | |
b24e7179 JB |
2082 | int reg; |
2083 | u32 val; | |
2084 | ||
2085 | /* | |
2086 | * Make sure planes won't keep trying to pump pixels to us, | |
2087 | * or we might hang the display. | |
2088 | */ | |
2089 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 2090 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 2091 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 JB |
2092 | |
2093 | /* Don't disable pipe A or pipe A PLLs if needed */ | |
2094 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
2095 | return; | |
2096 | ||
702e7a56 | 2097 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2098 | val = I915_READ(reg); |
00d70b15 CW |
2099 | if ((val & PIPECONF_ENABLE) == 0) |
2100 | return; | |
2101 | ||
2102 | I915_WRITE(reg, val & ~PIPECONF_ENABLE); | |
b24e7179 JB |
2103 | intel_wait_for_pipe_off(dev_priv->dev, pipe); |
2104 | } | |
2105 | ||
d74362c9 KP |
2106 | /* |
2107 | * Plane regs are double buffered, going from enabled->disabled needs a | |
2108 | * trigger in order to latch. The display address reg provides this. | |
2109 | */ | |
1dba99f4 VS |
2110 | void intel_flush_primary_plane(struct drm_i915_private *dev_priv, |
2111 | enum plane plane) | |
d74362c9 | 2112 | { |
3d13ef2e DL |
2113 | struct drm_device *dev = dev_priv->dev; |
2114 | u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane); | |
1dba99f4 VS |
2115 | |
2116 | I915_WRITE(reg, I915_READ(reg)); | |
2117 | POSTING_READ(reg); | |
d74362c9 KP |
2118 | } |
2119 | ||
b24e7179 | 2120 | /** |
262ca2b0 | 2121 | * intel_enable_primary_hw_plane - enable the primary plane on a given pipe |
b24e7179 JB |
2122 | * @dev_priv: i915 private structure |
2123 | * @plane: plane to enable | |
2124 | * @pipe: pipe being fed | |
2125 | * | |
2126 | * Enable @plane on @pipe, making sure that @pipe is running first. | |
2127 | */ | |
262ca2b0 MR |
2128 | static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv, |
2129 | enum plane plane, enum pipe pipe) | |
b24e7179 | 2130 | { |
939c2fe8 VS |
2131 | struct intel_crtc *intel_crtc = |
2132 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
b24e7179 JB |
2133 | int reg; |
2134 | u32 val; | |
2135 | ||
2136 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ | |
2137 | assert_pipe_enabled(dev_priv, pipe); | |
2138 | ||
98ec7739 VS |
2139 | if (intel_crtc->primary_enabled) |
2140 | return; | |
0037f71c | 2141 | |
4c445e0e | 2142 | intel_crtc->primary_enabled = true; |
939c2fe8 | 2143 | |
b24e7179 JB |
2144 | reg = DSPCNTR(plane); |
2145 | val = I915_READ(reg); | |
10efa932 | 2146 | WARN_ON(val & DISPLAY_PLANE_ENABLE); |
00d70b15 CW |
2147 | |
2148 | I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE); | |
1dba99f4 | 2149 | intel_flush_primary_plane(dev_priv, plane); |
b24e7179 JB |
2150 | } |
2151 | ||
b24e7179 | 2152 | /** |
262ca2b0 | 2153 | * intel_disable_primary_hw_plane - disable the primary hardware plane |
b24e7179 JB |
2154 | * @dev_priv: i915 private structure |
2155 | * @plane: plane to disable | |
2156 | * @pipe: pipe consuming the data | |
2157 | * | |
2158 | * Disable @plane; should be an independent operation. | |
2159 | */ | |
262ca2b0 MR |
2160 | static void intel_disable_primary_hw_plane(struct drm_i915_private *dev_priv, |
2161 | enum plane plane, enum pipe pipe) | |
b24e7179 | 2162 | { |
939c2fe8 VS |
2163 | struct intel_crtc *intel_crtc = |
2164 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
b24e7179 JB |
2165 | int reg; |
2166 | u32 val; | |
2167 | ||
98ec7739 VS |
2168 | if (!intel_crtc->primary_enabled) |
2169 | return; | |
0037f71c | 2170 | |
4c445e0e | 2171 | intel_crtc->primary_enabled = false; |
939c2fe8 | 2172 | |
b24e7179 JB |
2173 | reg = DSPCNTR(plane); |
2174 | val = I915_READ(reg); | |
10efa932 | 2175 | WARN_ON((val & DISPLAY_PLANE_ENABLE) == 0); |
00d70b15 CW |
2176 | |
2177 | I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE); | |
1dba99f4 | 2178 | intel_flush_primary_plane(dev_priv, plane); |
b24e7179 JB |
2179 | } |
2180 | ||
693db184 CW |
2181 | static bool need_vtd_wa(struct drm_device *dev) |
2182 | { | |
2183 | #ifdef CONFIG_INTEL_IOMMU | |
2184 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) | |
2185 | return true; | |
2186 | #endif | |
2187 | return false; | |
2188 | } | |
2189 | ||
a57ce0b2 JB |
2190 | static int intel_align_height(struct drm_device *dev, int height, bool tiled) |
2191 | { | |
2192 | int tile_height; | |
2193 | ||
2194 | tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1; | |
2195 | return ALIGN(height, tile_height); | |
2196 | } | |
2197 | ||
127bd2ac | 2198 | int |
48b956c5 | 2199 | intel_pin_and_fence_fb_obj(struct drm_device *dev, |
05394f39 | 2200 | struct drm_i915_gem_object *obj, |
a4872ba6 | 2201 | struct intel_engine_cs *pipelined) |
6b95a207 | 2202 | { |
ce453d81 | 2203 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
2204 | u32 alignment; |
2205 | int ret; | |
2206 | ||
05394f39 | 2207 | switch (obj->tiling_mode) { |
6b95a207 | 2208 | case I915_TILING_NONE: |
534843da CW |
2209 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
2210 | alignment = 128 * 1024; | |
a6c45cf0 | 2211 | else if (INTEL_INFO(dev)->gen >= 4) |
534843da CW |
2212 | alignment = 4 * 1024; |
2213 | else | |
2214 | alignment = 64 * 1024; | |
6b95a207 KH |
2215 | break; |
2216 | case I915_TILING_X: | |
2217 | /* pin() will align the object as required by fence */ | |
2218 | alignment = 0; | |
2219 | break; | |
2220 | case I915_TILING_Y: | |
80075d49 | 2221 | WARN(1, "Y tiled bo slipped through, driver bug!\n"); |
6b95a207 KH |
2222 | return -EINVAL; |
2223 | default: | |
2224 | BUG(); | |
2225 | } | |
2226 | ||
693db184 CW |
2227 | /* Note that the w/a also requires 64 PTE of padding following the |
2228 | * bo. We currently fill all unused PTE with the shadow page and so | |
2229 | * we should always have valid PTE following the scanout preventing | |
2230 | * the VT-d warning. | |
2231 | */ | |
2232 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | |
2233 | alignment = 256 * 1024; | |
2234 | ||
ce453d81 | 2235 | dev_priv->mm.interruptible = false; |
2da3b9b9 | 2236 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined); |
48b956c5 | 2237 | if (ret) |
ce453d81 | 2238 | goto err_interruptible; |
6b95a207 KH |
2239 | |
2240 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
2241 | * fence, whereas 965+ only requires a fence if using | |
2242 | * framebuffer compression. For simplicity, we always install | |
2243 | * a fence as the cost is not that onerous. | |
2244 | */ | |
06d98131 | 2245 | ret = i915_gem_object_get_fence(obj); |
9a5a53b3 CW |
2246 | if (ret) |
2247 | goto err_unpin; | |
1690e1eb | 2248 | |
9a5a53b3 | 2249 | i915_gem_object_pin_fence(obj); |
6b95a207 | 2250 | |
ce453d81 | 2251 | dev_priv->mm.interruptible = true; |
6b95a207 | 2252 | return 0; |
48b956c5 CW |
2253 | |
2254 | err_unpin: | |
cc98b413 | 2255 | i915_gem_object_unpin_from_display_plane(obj); |
ce453d81 CW |
2256 | err_interruptible: |
2257 | dev_priv->mm.interruptible = true; | |
48b956c5 | 2258 | return ret; |
6b95a207 KH |
2259 | } |
2260 | ||
1690e1eb CW |
2261 | void intel_unpin_fb_obj(struct drm_i915_gem_object *obj) |
2262 | { | |
2263 | i915_gem_object_unpin_fence(obj); | |
cc98b413 | 2264 | i915_gem_object_unpin_from_display_plane(obj); |
1690e1eb CW |
2265 | } |
2266 | ||
c2c75131 DV |
2267 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
2268 | * is assumed to be a power-of-two. */ | |
bc752862 CW |
2269 | unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
2270 | unsigned int tiling_mode, | |
2271 | unsigned int cpp, | |
2272 | unsigned int pitch) | |
c2c75131 | 2273 | { |
bc752862 CW |
2274 | if (tiling_mode != I915_TILING_NONE) { |
2275 | unsigned int tile_rows, tiles; | |
c2c75131 | 2276 | |
bc752862 CW |
2277 | tile_rows = *y / 8; |
2278 | *y %= 8; | |
c2c75131 | 2279 | |
bc752862 CW |
2280 | tiles = *x / (512/cpp); |
2281 | *x %= 512/cpp; | |
2282 | ||
2283 | return tile_rows * pitch * 8 + tiles * 4096; | |
2284 | } else { | |
2285 | unsigned int offset; | |
2286 | ||
2287 | offset = *y * pitch + *x * cpp; | |
2288 | *y = 0; | |
2289 | *x = (offset & 4095) / cpp; | |
2290 | return offset & -4096; | |
2291 | } | |
c2c75131 DV |
2292 | } |
2293 | ||
46f297fb JB |
2294 | int intel_format_to_fourcc(int format) |
2295 | { | |
2296 | switch (format) { | |
2297 | case DISPPLANE_8BPP: | |
2298 | return DRM_FORMAT_C8; | |
2299 | case DISPPLANE_BGRX555: | |
2300 | return DRM_FORMAT_XRGB1555; | |
2301 | case DISPPLANE_BGRX565: | |
2302 | return DRM_FORMAT_RGB565; | |
2303 | default: | |
2304 | case DISPPLANE_BGRX888: | |
2305 | return DRM_FORMAT_XRGB8888; | |
2306 | case DISPPLANE_RGBX888: | |
2307 | return DRM_FORMAT_XBGR8888; | |
2308 | case DISPPLANE_BGRX101010: | |
2309 | return DRM_FORMAT_XRGB2101010; | |
2310 | case DISPPLANE_RGBX101010: | |
2311 | return DRM_FORMAT_XBGR2101010; | |
2312 | } | |
2313 | } | |
2314 | ||
484b41dd | 2315 | static bool intel_alloc_plane_obj(struct intel_crtc *crtc, |
46f297fb JB |
2316 | struct intel_plane_config *plane_config) |
2317 | { | |
2318 | struct drm_device *dev = crtc->base.dev; | |
2319 | struct drm_i915_gem_object *obj = NULL; | |
2320 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2321 | u32 base = plane_config->base; | |
2322 | ||
ff2652ea CW |
2323 | if (plane_config->size == 0) |
2324 | return false; | |
2325 | ||
46f297fb JB |
2326 | obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base, |
2327 | plane_config->size); | |
2328 | if (!obj) | |
484b41dd | 2329 | return false; |
46f297fb JB |
2330 | |
2331 | if (plane_config->tiled) { | |
2332 | obj->tiling_mode = I915_TILING_X; | |
66e514c1 | 2333 | obj->stride = crtc->base.primary->fb->pitches[0]; |
46f297fb JB |
2334 | } |
2335 | ||
66e514c1 DA |
2336 | mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format; |
2337 | mode_cmd.width = crtc->base.primary->fb->width; | |
2338 | mode_cmd.height = crtc->base.primary->fb->height; | |
2339 | mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0]; | |
46f297fb JB |
2340 | |
2341 | mutex_lock(&dev->struct_mutex); | |
2342 | ||
66e514c1 | 2343 | if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb), |
484b41dd | 2344 | &mode_cmd, obj)) { |
46f297fb JB |
2345 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2346 | goto out_unref_obj; | |
2347 | } | |
2348 | ||
2349 | mutex_unlock(&dev->struct_mutex); | |
484b41dd JB |
2350 | |
2351 | DRM_DEBUG_KMS("plane fb obj %p\n", obj); | |
2352 | return true; | |
46f297fb JB |
2353 | |
2354 | out_unref_obj: | |
2355 | drm_gem_object_unreference(&obj->base); | |
2356 | mutex_unlock(&dev->struct_mutex); | |
484b41dd JB |
2357 | return false; |
2358 | } | |
2359 | ||
2360 | static void intel_find_plane_obj(struct intel_crtc *intel_crtc, | |
2361 | struct intel_plane_config *plane_config) | |
2362 | { | |
2363 | struct drm_device *dev = intel_crtc->base.dev; | |
2364 | struct drm_crtc *c; | |
2365 | struct intel_crtc *i; | |
2366 | struct intel_framebuffer *fb; | |
2367 | ||
66e514c1 | 2368 | if (!intel_crtc->base.primary->fb) |
484b41dd JB |
2369 | return; |
2370 | ||
2371 | if (intel_alloc_plane_obj(intel_crtc, plane_config)) | |
2372 | return; | |
2373 | ||
66e514c1 DA |
2374 | kfree(intel_crtc->base.primary->fb); |
2375 | intel_crtc->base.primary->fb = NULL; | |
484b41dd JB |
2376 | |
2377 | /* | |
2378 | * Failed to alloc the obj, check to see if we should share | |
2379 | * an fb with another CRTC instead | |
2380 | */ | |
70e1e0ec | 2381 | for_each_crtc(dev, c) { |
484b41dd JB |
2382 | i = to_intel_crtc(c); |
2383 | ||
2384 | if (c == &intel_crtc->base) | |
2385 | continue; | |
2386 | ||
66e514c1 | 2387 | if (!i->active || !c->primary->fb) |
484b41dd JB |
2388 | continue; |
2389 | ||
66e514c1 | 2390 | fb = to_intel_framebuffer(c->primary->fb); |
484b41dd | 2391 | if (i915_gem_obj_ggtt_offset(fb->obj) == plane_config->base) { |
66e514c1 DA |
2392 | drm_framebuffer_reference(c->primary->fb); |
2393 | intel_crtc->base.primary->fb = c->primary->fb; | |
484b41dd JB |
2394 | break; |
2395 | } | |
2396 | } | |
46f297fb JB |
2397 | } |
2398 | ||
29b9bde6 DV |
2399 | static void i9xx_update_primary_plane(struct drm_crtc *crtc, |
2400 | struct drm_framebuffer *fb, | |
2401 | int x, int y) | |
81255565 JB |
2402 | { |
2403 | struct drm_device *dev = crtc->dev; | |
2404 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2405 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2406 | struct intel_framebuffer *intel_fb; | |
05394f39 | 2407 | struct drm_i915_gem_object *obj; |
81255565 | 2408 | int plane = intel_crtc->plane; |
e506a0c6 | 2409 | unsigned long linear_offset; |
81255565 | 2410 | u32 dspcntr; |
5eddb70b | 2411 | u32 reg; |
81255565 | 2412 | |
81255565 JB |
2413 | intel_fb = to_intel_framebuffer(fb); |
2414 | obj = intel_fb->obj; | |
81255565 | 2415 | |
5eddb70b CW |
2416 | reg = DSPCNTR(plane); |
2417 | dspcntr = I915_READ(reg); | |
81255565 JB |
2418 | /* Mask out pixel format bits in case we change it */ |
2419 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
57779d06 VS |
2420 | switch (fb->pixel_format) { |
2421 | case DRM_FORMAT_C8: | |
81255565 JB |
2422 | dspcntr |= DISPPLANE_8BPP; |
2423 | break; | |
57779d06 VS |
2424 | case DRM_FORMAT_XRGB1555: |
2425 | case DRM_FORMAT_ARGB1555: | |
2426 | dspcntr |= DISPPLANE_BGRX555; | |
81255565 | 2427 | break; |
57779d06 VS |
2428 | case DRM_FORMAT_RGB565: |
2429 | dspcntr |= DISPPLANE_BGRX565; | |
2430 | break; | |
2431 | case DRM_FORMAT_XRGB8888: | |
2432 | case DRM_FORMAT_ARGB8888: | |
2433 | dspcntr |= DISPPLANE_BGRX888; | |
2434 | break; | |
2435 | case DRM_FORMAT_XBGR8888: | |
2436 | case DRM_FORMAT_ABGR8888: | |
2437 | dspcntr |= DISPPLANE_RGBX888; | |
2438 | break; | |
2439 | case DRM_FORMAT_XRGB2101010: | |
2440 | case DRM_FORMAT_ARGB2101010: | |
2441 | dspcntr |= DISPPLANE_BGRX101010; | |
2442 | break; | |
2443 | case DRM_FORMAT_XBGR2101010: | |
2444 | case DRM_FORMAT_ABGR2101010: | |
2445 | dspcntr |= DISPPLANE_RGBX101010; | |
81255565 JB |
2446 | break; |
2447 | default: | |
baba133a | 2448 | BUG(); |
81255565 | 2449 | } |
57779d06 | 2450 | |
a6c45cf0 | 2451 | if (INTEL_INFO(dev)->gen >= 4) { |
05394f39 | 2452 | if (obj->tiling_mode != I915_TILING_NONE) |
81255565 JB |
2453 | dspcntr |= DISPPLANE_TILED; |
2454 | else | |
2455 | dspcntr &= ~DISPPLANE_TILED; | |
2456 | } | |
2457 | ||
de1aa629 VS |
2458 | if (IS_G4X(dev)) |
2459 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2460 | ||
5eddb70b | 2461 | I915_WRITE(reg, dspcntr); |
81255565 | 2462 | |
e506a0c6 | 2463 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
81255565 | 2464 | |
c2c75131 DV |
2465 | if (INTEL_INFO(dev)->gen >= 4) { |
2466 | intel_crtc->dspaddr_offset = | |
bc752862 CW |
2467 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
2468 | fb->bits_per_pixel / 8, | |
2469 | fb->pitches[0]); | |
c2c75131 DV |
2470 | linear_offset -= intel_crtc->dspaddr_offset; |
2471 | } else { | |
e506a0c6 | 2472 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2473 | } |
e506a0c6 | 2474 | |
f343c5f6 BW |
2475 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2476 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, | |
2477 | fb->pitches[0]); | |
01f2c773 | 2478 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2479 | if (INTEL_INFO(dev)->gen >= 4) { |
85ba7b7d DV |
2480 | I915_WRITE(DSPSURF(plane), |
2481 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
5eddb70b | 2482 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2483 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2484 | } else |
f343c5f6 | 2485 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2486 | POSTING_READ(reg); |
17638cd6 JB |
2487 | } |
2488 | ||
29b9bde6 DV |
2489 | static void ironlake_update_primary_plane(struct drm_crtc *crtc, |
2490 | struct drm_framebuffer *fb, | |
2491 | int x, int y) | |
17638cd6 JB |
2492 | { |
2493 | struct drm_device *dev = crtc->dev; | |
2494 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2495 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2496 | struct intel_framebuffer *intel_fb; | |
2497 | struct drm_i915_gem_object *obj; | |
2498 | int plane = intel_crtc->plane; | |
e506a0c6 | 2499 | unsigned long linear_offset; |
17638cd6 JB |
2500 | u32 dspcntr; |
2501 | u32 reg; | |
2502 | ||
17638cd6 JB |
2503 | intel_fb = to_intel_framebuffer(fb); |
2504 | obj = intel_fb->obj; | |
2505 | ||
2506 | reg = DSPCNTR(plane); | |
2507 | dspcntr = I915_READ(reg); | |
2508 | /* Mask out pixel format bits in case we change it */ | |
2509 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
57779d06 VS |
2510 | switch (fb->pixel_format) { |
2511 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2512 | dspcntr |= DISPPLANE_8BPP; |
2513 | break; | |
57779d06 VS |
2514 | case DRM_FORMAT_RGB565: |
2515 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2516 | break; |
57779d06 VS |
2517 | case DRM_FORMAT_XRGB8888: |
2518 | case DRM_FORMAT_ARGB8888: | |
2519 | dspcntr |= DISPPLANE_BGRX888; | |
2520 | break; | |
2521 | case DRM_FORMAT_XBGR8888: | |
2522 | case DRM_FORMAT_ABGR8888: | |
2523 | dspcntr |= DISPPLANE_RGBX888; | |
2524 | break; | |
2525 | case DRM_FORMAT_XRGB2101010: | |
2526 | case DRM_FORMAT_ARGB2101010: | |
2527 | dspcntr |= DISPPLANE_BGRX101010; | |
2528 | break; | |
2529 | case DRM_FORMAT_XBGR2101010: | |
2530 | case DRM_FORMAT_ABGR2101010: | |
2531 | dspcntr |= DISPPLANE_RGBX101010; | |
17638cd6 JB |
2532 | break; |
2533 | default: | |
baba133a | 2534 | BUG(); |
17638cd6 JB |
2535 | } |
2536 | ||
2537 | if (obj->tiling_mode != I915_TILING_NONE) | |
2538 | dspcntr |= DISPPLANE_TILED; | |
2539 | else | |
2540 | dspcntr &= ~DISPPLANE_TILED; | |
2541 | ||
b42c6009 | 2542 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
1f5d76db PZ |
2543 | dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE; |
2544 | else | |
2545 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
17638cd6 JB |
2546 | |
2547 | I915_WRITE(reg, dspcntr); | |
2548 | ||
e506a0c6 | 2549 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
c2c75131 | 2550 | intel_crtc->dspaddr_offset = |
bc752862 CW |
2551 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
2552 | fb->bits_per_pixel / 8, | |
2553 | fb->pitches[0]); | |
c2c75131 | 2554 | linear_offset -= intel_crtc->dspaddr_offset; |
17638cd6 | 2555 | |
f343c5f6 BW |
2556 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2557 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, | |
2558 | fb->pitches[0]); | |
01f2c773 | 2559 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d DV |
2560 | I915_WRITE(DSPSURF(plane), |
2561 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
b3dc685e | 2562 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
bc1c91eb DL |
2563 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2564 | } else { | |
2565 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2566 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2567 | } | |
17638cd6 | 2568 | POSTING_READ(reg); |
17638cd6 JB |
2569 | } |
2570 | ||
2571 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ | |
2572 | static int | |
2573 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
2574 | int x, int y, enum mode_set_atomic state) | |
2575 | { | |
2576 | struct drm_device *dev = crtc->dev; | |
2577 | struct drm_i915_private *dev_priv = dev->dev_private; | |
17638cd6 | 2578 | |
6b8e6ed0 CW |
2579 | if (dev_priv->display.disable_fbc) |
2580 | dev_priv->display.disable_fbc(dev); | |
3dec0095 | 2581 | intel_increase_pllclock(crtc); |
81255565 | 2582 | |
29b9bde6 DV |
2583 | dev_priv->display.update_primary_plane(crtc, fb, x, y); |
2584 | ||
2585 | return 0; | |
81255565 JB |
2586 | } |
2587 | ||
96a02917 VS |
2588 | void intel_display_handle_reset(struct drm_device *dev) |
2589 | { | |
2590 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2591 | struct drm_crtc *crtc; | |
2592 | ||
2593 | /* | |
2594 | * Flips in the rings have been nuked by the reset, | |
2595 | * so complete all pending flips so that user space | |
2596 | * will get its events and not get stuck. | |
2597 | * | |
2598 | * Also update the base address of all primary | |
2599 | * planes to the the last fb to make sure we're | |
2600 | * showing the correct fb after a reset. | |
2601 | * | |
2602 | * Need to make two loops over the crtcs so that we | |
2603 | * don't try to grab a crtc mutex before the | |
2604 | * pending_flip_queue really got woken up. | |
2605 | */ | |
2606 | ||
70e1e0ec | 2607 | for_each_crtc(dev, crtc) { |
96a02917 VS |
2608 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2609 | enum plane plane = intel_crtc->plane; | |
2610 | ||
2611 | intel_prepare_page_flip(dev, plane); | |
2612 | intel_finish_page_flip_plane(dev, plane); | |
2613 | } | |
2614 | ||
70e1e0ec | 2615 | for_each_crtc(dev, crtc) { |
96a02917 VS |
2616 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2617 | ||
51fd371b | 2618 | drm_modeset_lock(&crtc->mutex, NULL); |
947fdaad CW |
2619 | /* |
2620 | * FIXME: Once we have proper support for primary planes (and | |
2621 | * disabling them without disabling the entire crtc) allow again | |
66e514c1 | 2622 | * a NULL crtc->primary->fb. |
947fdaad | 2623 | */ |
f4510a27 | 2624 | if (intel_crtc->active && crtc->primary->fb) |
262ca2b0 | 2625 | dev_priv->display.update_primary_plane(crtc, |
66e514c1 | 2626 | crtc->primary->fb, |
262ca2b0 MR |
2627 | crtc->x, |
2628 | crtc->y); | |
51fd371b | 2629 | drm_modeset_unlock(&crtc->mutex); |
96a02917 VS |
2630 | } |
2631 | } | |
2632 | ||
14667a4b CW |
2633 | static int |
2634 | intel_finish_fb(struct drm_framebuffer *old_fb) | |
2635 | { | |
2636 | struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj; | |
2637 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2638 | bool was_interruptible = dev_priv->mm.interruptible; | |
2639 | int ret; | |
2640 | ||
14667a4b CW |
2641 | /* Big Hammer, we also need to ensure that any pending |
2642 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
2643 | * current scanout is retired before unpinning the old | |
2644 | * framebuffer. | |
2645 | * | |
2646 | * This should only fail upon a hung GPU, in which case we | |
2647 | * can safely continue. | |
2648 | */ | |
2649 | dev_priv->mm.interruptible = false; | |
2650 | ret = i915_gem_object_finish_gpu(obj); | |
2651 | dev_priv->mm.interruptible = was_interruptible; | |
2652 | ||
2653 | return ret; | |
2654 | } | |
2655 | ||
7d5e3799 CW |
2656 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
2657 | { | |
2658 | struct drm_device *dev = crtc->dev; | |
2659 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2660 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2661 | unsigned long flags; | |
2662 | bool pending; | |
2663 | ||
2664 | if (i915_reset_in_progress(&dev_priv->gpu_error) || | |
2665 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
2666 | return false; | |
2667 | ||
2668 | spin_lock_irqsave(&dev->event_lock, flags); | |
2669 | pending = to_intel_crtc(crtc)->unpin_work != NULL; | |
2670 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
2671 | ||
2672 | return pending; | |
2673 | } | |
2674 | ||
5c3b82e2 | 2675 | static int |
3c4fdcfb | 2676 | intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
94352cf9 | 2677 | struct drm_framebuffer *fb) |
79e53945 JB |
2678 | { |
2679 | struct drm_device *dev = crtc->dev; | |
6b8e6ed0 | 2680 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 2681 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
94352cf9 | 2682 | struct drm_framebuffer *old_fb; |
5c3b82e2 | 2683 | int ret; |
79e53945 | 2684 | |
7d5e3799 CW |
2685 | if (intel_crtc_has_pending_flip(crtc)) { |
2686 | DRM_ERROR("pipe is still busy with an old pageflip\n"); | |
2687 | return -EBUSY; | |
2688 | } | |
2689 | ||
79e53945 | 2690 | /* no fb bound */ |
94352cf9 | 2691 | if (!fb) { |
a5071c2f | 2692 | DRM_ERROR("No FB bound\n"); |
5c3b82e2 CW |
2693 | return 0; |
2694 | } | |
2695 | ||
7eb552ae | 2696 | if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) { |
84f44ce7 VS |
2697 | DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n", |
2698 | plane_name(intel_crtc->plane), | |
2699 | INTEL_INFO(dev)->num_pipes); | |
5c3b82e2 | 2700 | return -EINVAL; |
79e53945 JB |
2701 | } |
2702 | ||
5c3b82e2 | 2703 | mutex_lock(&dev->struct_mutex); |
265db958 | 2704 | ret = intel_pin_and_fence_fb_obj(dev, |
94352cf9 | 2705 | to_intel_framebuffer(fb)->obj, |
919926ae | 2706 | NULL); |
8ac36ec1 | 2707 | mutex_unlock(&dev->struct_mutex); |
5c3b82e2 | 2708 | if (ret != 0) { |
a5071c2f | 2709 | DRM_ERROR("pin & fence failed\n"); |
5c3b82e2 CW |
2710 | return ret; |
2711 | } | |
79e53945 | 2712 | |
bb2043de DL |
2713 | /* |
2714 | * Update pipe size and adjust fitter if needed: the reason for this is | |
2715 | * that in compute_mode_changes we check the native mode (not the pfit | |
2716 | * mode) to see if we can flip rather than do a full mode set. In the | |
2717 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
2718 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
2719 | * sized surface. | |
2720 | * | |
2721 | * To fix this properly, we need to hoist the checks up into | |
2722 | * compute_mode_changes (or above), check the actual pfit state and | |
2723 | * whether the platform allows pfit disable with pipe active, and only | |
2724 | * then update the pipesrc and pfit state, even on the flip path. | |
2725 | */ | |
d330a953 | 2726 | if (i915.fastboot) { |
d7bf63f2 DL |
2727 | const struct drm_display_mode *adjusted_mode = |
2728 | &intel_crtc->config.adjusted_mode; | |
2729 | ||
4d6a3e63 | 2730 | I915_WRITE(PIPESRC(intel_crtc->pipe), |
d7bf63f2 DL |
2731 | ((adjusted_mode->crtc_hdisplay - 1) << 16) | |
2732 | (adjusted_mode->crtc_vdisplay - 1)); | |
fd4daa9c | 2733 | if (!intel_crtc->config.pch_pfit.enabled && |
4d6a3e63 JB |
2734 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || |
2735 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
2736 | I915_WRITE(PF_CTL(intel_crtc->pipe), 0); | |
2737 | I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0); | |
2738 | I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0); | |
2739 | } | |
0637d60d JB |
2740 | intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay; |
2741 | intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay; | |
4d6a3e63 JB |
2742 | } |
2743 | ||
29b9bde6 | 2744 | dev_priv->display.update_primary_plane(crtc, fb, x, y); |
3c4fdcfb | 2745 | |
f4510a27 MR |
2746 | old_fb = crtc->primary->fb; |
2747 | crtc->primary->fb = fb; | |
6c4c86f5 DV |
2748 | crtc->x = x; |
2749 | crtc->y = y; | |
94352cf9 | 2750 | |
b7f1de28 | 2751 | if (old_fb) { |
d7697eea DV |
2752 | if (intel_crtc->active && old_fb != fb) |
2753 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
8ac36ec1 | 2754 | mutex_lock(&dev->struct_mutex); |
1690e1eb | 2755 | intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj); |
8ac36ec1 | 2756 | mutex_unlock(&dev->struct_mutex); |
b7f1de28 | 2757 | } |
652c393a | 2758 | |
8ac36ec1 | 2759 | mutex_lock(&dev->struct_mutex); |
6b8e6ed0 | 2760 | intel_update_fbc(dev); |
4906557e | 2761 | intel_edp_psr_update(dev); |
5c3b82e2 | 2762 | mutex_unlock(&dev->struct_mutex); |
79e53945 | 2763 | |
5c3b82e2 | 2764 | return 0; |
79e53945 JB |
2765 | } |
2766 | ||
5e84e1a4 ZW |
2767 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
2768 | { | |
2769 | struct drm_device *dev = crtc->dev; | |
2770 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2771 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2772 | int pipe = intel_crtc->pipe; | |
2773 | u32 reg, temp; | |
2774 | ||
2775 | /* enable normal train */ | |
2776 | reg = FDI_TX_CTL(pipe); | |
2777 | temp = I915_READ(reg); | |
61e499bf | 2778 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
2779 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
2780 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
2781 | } else { |
2782 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2783 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 2784 | } |
5e84e1a4 ZW |
2785 | I915_WRITE(reg, temp); |
2786 | ||
2787 | reg = FDI_RX_CTL(pipe); | |
2788 | temp = I915_READ(reg); | |
2789 | if (HAS_PCH_CPT(dev)) { | |
2790 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2791 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
2792 | } else { | |
2793 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2794 | temp |= FDI_LINK_TRAIN_NONE; | |
2795 | } | |
2796 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
2797 | ||
2798 | /* wait one idle pattern time */ | |
2799 | POSTING_READ(reg); | |
2800 | udelay(1000); | |
357555c0 JB |
2801 | |
2802 | /* IVB wants error correction enabled */ | |
2803 | if (IS_IVYBRIDGE(dev)) | |
2804 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
2805 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
2806 | } |
2807 | ||
1fbc0d78 | 2808 | static bool pipe_has_enabled_pch(struct intel_crtc *crtc) |
1e833f40 | 2809 | { |
1fbc0d78 DV |
2810 | return crtc->base.enabled && crtc->active && |
2811 | crtc->config.has_pch_encoder; | |
1e833f40 DV |
2812 | } |
2813 | ||
01a415fd DV |
2814 | static void ivb_modeset_global_resources(struct drm_device *dev) |
2815 | { | |
2816 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2817 | struct intel_crtc *pipe_B_crtc = | |
2818 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); | |
2819 | struct intel_crtc *pipe_C_crtc = | |
2820 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]); | |
2821 | uint32_t temp; | |
2822 | ||
1e833f40 DV |
2823 | /* |
2824 | * When everything is off disable fdi C so that we could enable fdi B | |
2825 | * with all lanes. Note that we don't care about enabled pipes without | |
2826 | * an enabled pch encoder. | |
2827 | */ | |
2828 | if (!pipe_has_enabled_pch(pipe_B_crtc) && | |
2829 | !pipe_has_enabled_pch(pipe_C_crtc)) { | |
01a415fd DV |
2830 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); |
2831 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
2832 | ||
2833 | temp = I915_READ(SOUTH_CHICKEN1); | |
2834 | temp &= ~FDI_BC_BIFURCATION_SELECT; | |
2835 | DRM_DEBUG_KMS("disabling fdi C rx\n"); | |
2836 | I915_WRITE(SOUTH_CHICKEN1, temp); | |
2837 | } | |
2838 | } | |
2839 | ||
8db9d77b ZW |
2840 | /* The FDI link training functions for ILK/Ibexpeak. */ |
2841 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
2842 | { | |
2843 | struct drm_device *dev = crtc->dev; | |
2844 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2845 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2846 | int pipe = intel_crtc->pipe; | |
5eddb70b | 2847 | u32 reg, temp, tries; |
8db9d77b | 2848 | |
1c8562f6 | 2849 | /* FDI needs bits from pipe first */ |
0fc932b8 | 2850 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 2851 | |
e1a44743 AJ |
2852 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2853 | for train result */ | |
5eddb70b CW |
2854 | reg = FDI_RX_IMR(pipe); |
2855 | temp = I915_READ(reg); | |
e1a44743 AJ |
2856 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2857 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2858 | I915_WRITE(reg, temp); |
2859 | I915_READ(reg); | |
e1a44743 AJ |
2860 | udelay(150); |
2861 | ||
8db9d77b | 2862 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2863 | reg = FDI_TX_CTL(pipe); |
2864 | temp = I915_READ(reg); | |
627eb5a3 DV |
2865 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2866 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
8db9d77b ZW |
2867 | temp &= ~FDI_LINK_TRAIN_NONE; |
2868 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 2869 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2870 | |
5eddb70b CW |
2871 | reg = FDI_RX_CTL(pipe); |
2872 | temp = I915_READ(reg); | |
8db9d77b ZW |
2873 | temp &= ~FDI_LINK_TRAIN_NONE; |
2874 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
2875 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2876 | ||
2877 | POSTING_READ(reg); | |
8db9d77b ZW |
2878 | udelay(150); |
2879 | ||
5b2adf89 | 2880 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
2881 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
2882 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
2883 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 2884 | |
5eddb70b | 2885 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2886 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2887 | temp = I915_READ(reg); |
8db9d77b ZW |
2888 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2889 | ||
2890 | if ((temp & FDI_RX_BIT_LOCK)) { | |
2891 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 2892 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
2893 | break; |
2894 | } | |
8db9d77b | 2895 | } |
e1a44743 | 2896 | if (tries == 5) |
5eddb70b | 2897 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
2898 | |
2899 | /* Train 2 */ | |
5eddb70b CW |
2900 | reg = FDI_TX_CTL(pipe); |
2901 | temp = I915_READ(reg); | |
8db9d77b ZW |
2902 | temp &= ~FDI_LINK_TRAIN_NONE; |
2903 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2904 | I915_WRITE(reg, temp); |
8db9d77b | 2905 | |
5eddb70b CW |
2906 | reg = FDI_RX_CTL(pipe); |
2907 | temp = I915_READ(reg); | |
8db9d77b ZW |
2908 | temp &= ~FDI_LINK_TRAIN_NONE; |
2909 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2910 | I915_WRITE(reg, temp); |
8db9d77b | 2911 | |
5eddb70b CW |
2912 | POSTING_READ(reg); |
2913 | udelay(150); | |
8db9d77b | 2914 | |
5eddb70b | 2915 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2916 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2917 | temp = I915_READ(reg); |
8db9d77b ZW |
2918 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2919 | ||
2920 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 2921 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
2922 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
2923 | break; | |
2924 | } | |
8db9d77b | 2925 | } |
e1a44743 | 2926 | if (tries == 5) |
5eddb70b | 2927 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
2928 | |
2929 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 2930 | |
8db9d77b ZW |
2931 | } |
2932 | ||
0206e353 | 2933 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
2934 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
2935 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
2936 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
2937 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
2938 | }; | |
2939 | ||
2940 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
2941 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
2942 | { | |
2943 | struct drm_device *dev = crtc->dev; | |
2944 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2945 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2946 | int pipe = intel_crtc->pipe; | |
fa37d39e | 2947 | u32 reg, temp, i, retry; |
8db9d77b | 2948 | |
e1a44743 AJ |
2949 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2950 | for train result */ | |
5eddb70b CW |
2951 | reg = FDI_RX_IMR(pipe); |
2952 | temp = I915_READ(reg); | |
e1a44743 AJ |
2953 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2954 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2955 | I915_WRITE(reg, temp); |
2956 | ||
2957 | POSTING_READ(reg); | |
e1a44743 AJ |
2958 | udelay(150); |
2959 | ||
8db9d77b | 2960 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2961 | reg = FDI_TX_CTL(pipe); |
2962 | temp = I915_READ(reg); | |
627eb5a3 DV |
2963 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2964 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
8db9d77b ZW |
2965 | temp &= ~FDI_LINK_TRAIN_NONE; |
2966 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2967 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2968 | /* SNB-B */ | |
2969 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 2970 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2971 | |
d74cf324 DV |
2972 | I915_WRITE(FDI_RX_MISC(pipe), |
2973 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
2974 | ||
5eddb70b CW |
2975 | reg = FDI_RX_CTL(pipe); |
2976 | temp = I915_READ(reg); | |
8db9d77b ZW |
2977 | if (HAS_PCH_CPT(dev)) { |
2978 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2979 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
2980 | } else { | |
2981 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2982 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2983 | } | |
5eddb70b CW |
2984 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2985 | ||
2986 | POSTING_READ(reg); | |
8db9d77b ZW |
2987 | udelay(150); |
2988 | ||
0206e353 | 2989 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
2990 | reg = FDI_TX_CTL(pipe); |
2991 | temp = I915_READ(reg); | |
8db9d77b ZW |
2992 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2993 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
2994 | I915_WRITE(reg, temp); |
2995 | ||
2996 | POSTING_READ(reg); | |
8db9d77b ZW |
2997 | udelay(500); |
2998 | ||
fa37d39e SP |
2999 | for (retry = 0; retry < 5; retry++) { |
3000 | reg = FDI_RX_IIR(pipe); | |
3001 | temp = I915_READ(reg); | |
3002 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3003 | if (temp & FDI_RX_BIT_LOCK) { | |
3004 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3005 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3006 | break; | |
3007 | } | |
3008 | udelay(50); | |
8db9d77b | 3009 | } |
fa37d39e SP |
3010 | if (retry < 5) |
3011 | break; | |
8db9d77b ZW |
3012 | } |
3013 | if (i == 4) | |
5eddb70b | 3014 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3015 | |
3016 | /* Train 2 */ | |
5eddb70b CW |
3017 | reg = FDI_TX_CTL(pipe); |
3018 | temp = I915_READ(reg); | |
8db9d77b ZW |
3019 | temp &= ~FDI_LINK_TRAIN_NONE; |
3020 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3021 | if (IS_GEN6(dev)) { | |
3022 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3023 | /* SNB-B */ | |
3024 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3025 | } | |
5eddb70b | 3026 | I915_WRITE(reg, temp); |
8db9d77b | 3027 | |
5eddb70b CW |
3028 | reg = FDI_RX_CTL(pipe); |
3029 | temp = I915_READ(reg); | |
8db9d77b ZW |
3030 | if (HAS_PCH_CPT(dev)) { |
3031 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3032 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3033 | } else { | |
3034 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3035 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3036 | } | |
5eddb70b CW |
3037 | I915_WRITE(reg, temp); |
3038 | ||
3039 | POSTING_READ(reg); | |
8db9d77b ZW |
3040 | udelay(150); |
3041 | ||
0206e353 | 3042 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3043 | reg = FDI_TX_CTL(pipe); |
3044 | temp = I915_READ(reg); | |
8db9d77b ZW |
3045 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3046 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3047 | I915_WRITE(reg, temp); |
3048 | ||
3049 | POSTING_READ(reg); | |
8db9d77b ZW |
3050 | udelay(500); |
3051 | ||
fa37d39e SP |
3052 | for (retry = 0; retry < 5; retry++) { |
3053 | reg = FDI_RX_IIR(pipe); | |
3054 | temp = I915_READ(reg); | |
3055 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3056 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3057 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3058 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3059 | break; | |
3060 | } | |
3061 | udelay(50); | |
8db9d77b | 3062 | } |
fa37d39e SP |
3063 | if (retry < 5) |
3064 | break; | |
8db9d77b ZW |
3065 | } |
3066 | if (i == 4) | |
5eddb70b | 3067 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3068 | |
3069 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3070 | } | |
3071 | ||
357555c0 JB |
3072 | /* Manual link training for Ivy Bridge A0 parts */ |
3073 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
3074 | { | |
3075 | struct drm_device *dev = crtc->dev; | |
3076 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3077 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3078 | int pipe = intel_crtc->pipe; | |
139ccd3f | 3079 | u32 reg, temp, i, j; |
357555c0 JB |
3080 | |
3081 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
3082 | for train result */ | |
3083 | reg = FDI_RX_IMR(pipe); | |
3084 | temp = I915_READ(reg); | |
3085 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
3086 | temp &= ~FDI_RX_BIT_LOCK; | |
3087 | I915_WRITE(reg, temp); | |
3088 | ||
3089 | POSTING_READ(reg); | |
3090 | udelay(150); | |
3091 | ||
01a415fd DV |
3092 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
3093 | I915_READ(FDI_RX_IIR(pipe))); | |
3094 | ||
139ccd3f JB |
3095 | /* Try each vswing and preemphasis setting twice before moving on */ |
3096 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
3097 | /* disable first in case we need to retry */ | |
3098 | reg = FDI_TX_CTL(pipe); | |
3099 | temp = I915_READ(reg); | |
3100 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
3101 | temp &= ~FDI_TX_ENABLE; | |
3102 | I915_WRITE(reg, temp); | |
357555c0 | 3103 | |
139ccd3f JB |
3104 | reg = FDI_RX_CTL(pipe); |
3105 | temp = I915_READ(reg); | |
3106 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
3107 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3108 | temp &= ~FDI_RX_ENABLE; | |
3109 | I915_WRITE(reg, temp); | |
357555c0 | 3110 | |
139ccd3f | 3111 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
3112 | reg = FDI_TX_CTL(pipe); |
3113 | temp = I915_READ(reg); | |
139ccd3f JB |
3114 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
3115 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
3116 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; | |
357555c0 | 3117 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
3118 | temp |= snb_b_fdi_train_param[j/2]; |
3119 | temp |= FDI_COMPOSITE_SYNC; | |
3120 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 3121 | |
139ccd3f JB |
3122 | I915_WRITE(FDI_RX_MISC(pipe), |
3123 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 3124 | |
139ccd3f | 3125 | reg = FDI_RX_CTL(pipe); |
357555c0 | 3126 | temp = I915_READ(reg); |
139ccd3f JB |
3127 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
3128 | temp |= FDI_COMPOSITE_SYNC; | |
3129 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 3130 | |
139ccd3f JB |
3131 | POSTING_READ(reg); |
3132 | udelay(1); /* should be 0.5us */ | |
357555c0 | 3133 | |
139ccd3f JB |
3134 | for (i = 0; i < 4; i++) { |
3135 | reg = FDI_RX_IIR(pipe); | |
3136 | temp = I915_READ(reg); | |
3137 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3138 | |
139ccd3f JB |
3139 | if (temp & FDI_RX_BIT_LOCK || |
3140 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
3141 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3142 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
3143 | i); | |
3144 | break; | |
3145 | } | |
3146 | udelay(1); /* should be 0.5us */ | |
3147 | } | |
3148 | if (i == 4) { | |
3149 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
3150 | continue; | |
3151 | } | |
357555c0 | 3152 | |
139ccd3f | 3153 | /* Train 2 */ |
357555c0 JB |
3154 | reg = FDI_TX_CTL(pipe); |
3155 | temp = I915_READ(reg); | |
139ccd3f JB |
3156 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3157 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
3158 | I915_WRITE(reg, temp); | |
3159 | ||
3160 | reg = FDI_RX_CTL(pipe); | |
3161 | temp = I915_READ(reg); | |
3162 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3163 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
3164 | I915_WRITE(reg, temp); |
3165 | ||
3166 | POSTING_READ(reg); | |
139ccd3f | 3167 | udelay(2); /* should be 1.5us */ |
357555c0 | 3168 | |
139ccd3f JB |
3169 | for (i = 0; i < 4; i++) { |
3170 | reg = FDI_RX_IIR(pipe); | |
3171 | temp = I915_READ(reg); | |
3172 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3173 | |
139ccd3f JB |
3174 | if (temp & FDI_RX_SYMBOL_LOCK || |
3175 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
3176 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3177 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
3178 | i); | |
3179 | goto train_done; | |
3180 | } | |
3181 | udelay(2); /* should be 1.5us */ | |
357555c0 | 3182 | } |
139ccd3f JB |
3183 | if (i == 4) |
3184 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 3185 | } |
357555c0 | 3186 | |
139ccd3f | 3187 | train_done: |
357555c0 JB |
3188 | DRM_DEBUG_KMS("FDI train done.\n"); |
3189 | } | |
3190 | ||
88cefb6c | 3191 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 3192 | { |
88cefb6c | 3193 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 3194 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 3195 | int pipe = intel_crtc->pipe; |
5eddb70b | 3196 | u32 reg, temp; |
79e53945 | 3197 | |
c64e311e | 3198 | |
c98e9dcf | 3199 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
3200 | reg = FDI_RX_CTL(pipe); |
3201 | temp = I915_READ(reg); | |
627eb5a3 DV |
3202 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
3203 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
dfd07d72 | 3204 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
3205 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
3206 | ||
3207 | POSTING_READ(reg); | |
c98e9dcf JB |
3208 | udelay(200); |
3209 | ||
3210 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
3211 | temp = I915_READ(reg); |
3212 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
3213 | ||
3214 | POSTING_READ(reg); | |
c98e9dcf JB |
3215 | udelay(200); |
3216 | ||
20749730 PZ |
3217 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
3218 | reg = FDI_TX_CTL(pipe); | |
3219 | temp = I915_READ(reg); | |
3220 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
3221 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 3222 | |
20749730 PZ |
3223 | POSTING_READ(reg); |
3224 | udelay(100); | |
6be4a607 | 3225 | } |
0e23b99d JB |
3226 | } |
3227 | ||
88cefb6c DV |
3228 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
3229 | { | |
3230 | struct drm_device *dev = intel_crtc->base.dev; | |
3231 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3232 | int pipe = intel_crtc->pipe; | |
3233 | u32 reg, temp; | |
3234 | ||
3235 | /* Switch from PCDclk to Rawclk */ | |
3236 | reg = FDI_RX_CTL(pipe); | |
3237 | temp = I915_READ(reg); | |
3238 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
3239 | ||
3240 | /* Disable CPU FDI TX PLL */ | |
3241 | reg = FDI_TX_CTL(pipe); | |
3242 | temp = I915_READ(reg); | |
3243 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
3244 | ||
3245 | POSTING_READ(reg); | |
3246 | udelay(100); | |
3247 | ||
3248 | reg = FDI_RX_CTL(pipe); | |
3249 | temp = I915_READ(reg); | |
3250 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
3251 | ||
3252 | /* Wait for the clocks to turn off. */ | |
3253 | POSTING_READ(reg); | |
3254 | udelay(100); | |
3255 | } | |
3256 | ||
0fc932b8 JB |
3257 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
3258 | { | |
3259 | struct drm_device *dev = crtc->dev; | |
3260 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3261 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3262 | int pipe = intel_crtc->pipe; | |
3263 | u32 reg, temp; | |
3264 | ||
3265 | /* disable CPU FDI tx and PCH FDI rx */ | |
3266 | reg = FDI_TX_CTL(pipe); | |
3267 | temp = I915_READ(reg); | |
3268 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
3269 | POSTING_READ(reg); | |
3270 | ||
3271 | reg = FDI_RX_CTL(pipe); | |
3272 | temp = I915_READ(reg); | |
3273 | temp &= ~(0x7 << 16); | |
dfd07d72 | 3274 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3275 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
3276 | ||
3277 | POSTING_READ(reg); | |
3278 | udelay(100); | |
3279 | ||
3280 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
eba905b2 | 3281 | if (HAS_PCH_IBX(dev)) |
6f06ce18 | 3282 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
3283 | |
3284 | /* still set train pattern 1 */ | |
3285 | reg = FDI_TX_CTL(pipe); | |
3286 | temp = I915_READ(reg); | |
3287 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3288 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3289 | I915_WRITE(reg, temp); | |
3290 | ||
3291 | reg = FDI_RX_CTL(pipe); | |
3292 | temp = I915_READ(reg); | |
3293 | if (HAS_PCH_CPT(dev)) { | |
3294 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3295 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3296 | } else { | |
3297 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3298 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3299 | } | |
3300 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
3301 | temp &= ~(0x07 << 16); | |
dfd07d72 | 3302 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3303 | I915_WRITE(reg, temp); |
3304 | ||
3305 | POSTING_READ(reg); | |
3306 | udelay(100); | |
3307 | } | |
3308 | ||
5dce5b93 CW |
3309 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
3310 | { | |
3311 | struct intel_crtc *crtc; | |
3312 | ||
3313 | /* Note that we don't need to be called with mode_config.lock here | |
3314 | * as our list of CRTC objects is static for the lifetime of the | |
3315 | * device and so cannot disappear as we iterate. Similarly, we can | |
3316 | * happily treat the predicates as racy, atomic checks as userspace | |
3317 | * cannot claim and pin a new fb without at least acquring the | |
3318 | * struct_mutex and so serialising with us. | |
3319 | */ | |
d3fcc808 | 3320 | for_each_intel_crtc(dev, crtc) { |
5dce5b93 CW |
3321 | if (atomic_read(&crtc->unpin_work_count) == 0) |
3322 | continue; | |
3323 | ||
3324 | if (crtc->unpin_work) | |
3325 | intel_wait_for_vblank(dev, crtc->pipe); | |
3326 | ||
3327 | return true; | |
3328 | } | |
3329 | ||
3330 | return false; | |
3331 | } | |
3332 | ||
46a55d30 | 3333 | void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
e6c3a2a6 | 3334 | { |
0f91128d | 3335 | struct drm_device *dev = crtc->dev; |
5bb61643 | 3336 | struct drm_i915_private *dev_priv = dev->dev_private; |
e6c3a2a6 | 3337 | |
f4510a27 | 3338 | if (crtc->primary->fb == NULL) |
e6c3a2a6 CW |
3339 | return; |
3340 | ||
2c10d571 DV |
3341 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
3342 | ||
eed6d67d DV |
3343 | WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue, |
3344 | !intel_crtc_has_pending_flip(crtc), | |
3345 | 60*HZ) == 0); | |
5bb61643 | 3346 | |
0f91128d | 3347 | mutex_lock(&dev->struct_mutex); |
f4510a27 | 3348 | intel_finish_fb(crtc->primary->fb); |
0f91128d | 3349 | mutex_unlock(&dev->struct_mutex); |
e6c3a2a6 CW |
3350 | } |
3351 | ||
e615efe4 ED |
3352 | /* Program iCLKIP clock to the desired frequency */ |
3353 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
3354 | { | |
3355 | struct drm_device *dev = crtc->dev; | |
3356 | struct drm_i915_private *dev_priv = dev->dev_private; | |
241bfc38 | 3357 | int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock; |
e615efe4 ED |
3358 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
3359 | u32 temp; | |
3360 | ||
09153000 DV |
3361 | mutex_lock(&dev_priv->dpio_lock); |
3362 | ||
e615efe4 ED |
3363 | /* It is necessary to ungate the pixclk gate prior to programming |
3364 | * the divisors, and gate it back when it is done. | |
3365 | */ | |
3366 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
3367 | ||
3368 | /* Disable SSCCTL */ | |
3369 | intel_sbi_write(dev_priv, SBI_SSCCTL6, | |
988d6ee8 PZ |
3370 | intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) | |
3371 | SBI_SSCCTL_DISABLE, | |
3372 | SBI_ICLK); | |
e615efe4 ED |
3373 | |
3374 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ | |
12d7ceed | 3375 | if (clock == 20000) { |
e615efe4 ED |
3376 | auxdiv = 1; |
3377 | divsel = 0x41; | |
3378 | phaseinc = 0x20; | |
3379 | } else { | |
3380 | /* The iCLK virtual clock root frequency is in MHz, | |
241bfc38 DL |
3381 | * but the adjusted_mode->crtc_clock in in KHz. To get the |
3382 | * divisors, it is necessary to divide one by another, so we | |
e615efe4 ED |
3383 | * convert the virtual clock precision to KHz here for higher |
3384 | * precision. | |
3385 | */ | |
3386 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
3387 | u32 iclk_pi_range = 64; | |
3388 | u32 desired_divisor, msb_divisor_value, pi_value; | |
3389 | ||
12d7ceed | 3390 | desired_divisor = (iclk_virtual_root_freq / clock); |
e615efe4 ED |
3391 | msb_divisor_value = desired_divisor / iclk_pi_range; |
3392 | pi_value = desired_divisor % iclk_pi_range; | |
3393 | ||
3394 | auxdiv = 0; | |
3395 | divsel = msb_divisor_value - 2; | |
3396 | phaseinc = pi_value; | |
3397 | } | |
3398 | ||
3399 | /* This should not happen with any sane values */ | |
3400 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
3401 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
3402 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
3403 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
3404 | ||
3405 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 3406 | clock, |
e615efe4 ED |
3407 | auxdiv, |
3408 | divsel, | |
3409 | phasedir, | |
3410 | phaseinc); | |
3411 | ||
3412 | /* Program SSCDIVINTPHASE6 */ | |
988d6ee8 | 3413 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
3414 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
3415 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
3416 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
3417 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
3418 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
3419 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 3420 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
3421 | |
3422 | /* Program SSCAUXDIV */ | |
988d6ee8 | 3423 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
3424 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
3425 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 3426 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
3427 | |
3428 | /* Enable modulator and associated divider */ | |
988d6ee8 | 3429 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 3430 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 3431 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 ED |
3432 | |
3433 | /* Wait for initialization time */ | |
3434 | udelay(24); | |
3435 | ||
3436 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
09153000 DV |
3437 | |
3438 | mutex_unlock(&dev_priv->dpio_lock); | |
e615efe4 ED |
3439 | } |
3440 | ||
275f01b2 DV |
3441 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
3442 | enum pipe pch_transcoder) | |
3443 | { | |
3444 | struct drm_device *dev = crtc->base.dev; | |
3445 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3446 | enum transcoder cpu_transcoder = crtc->config.cpu_transcoder; | |
3447 | ||
3448 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
3449 | I915_READ(HTOTAL(cpu_transcoder))); | |
3450 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
3451 | I915_READ(HBLANK(cpu_transcoder))); | |
3452 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
3453 | I915_READ(HSYNC(cpu_transcoder))); | |
3454 | ||
3455 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
3456 | I915_READ(VTOTAL(cpu_transcoder))); | |
3457 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
3458 | I915_READ(VBLANK(cpu_transcoder))); | |
3459 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
3460 | I915_READ(VSYNC(cpu_transcoder))); | |
3461 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
3462 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
3463 | } | |
3464 | ||
1fbc0d78 DV |
3465 | static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev) |
3466 | { | |
3467 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3468 | uint32_t temp; | |
3469 | ||
3470 | temp = I915_READ(SOUTH_CHICKEN1); | |
3471 | if (temp & FDI_BC_BIFURCATION_SELECT) | |
3472 | return; | |
3473 | ||
3474 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
3475 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
3476 | ||
3477 | temp |= FDI_BC_BIFURCATION_SELECT; | |
3478 | DRM_DEBUG_KMS("enabling fdi C rx\n"); | |
3479 | I915_WRITE(SOUTH_CHICKEN1, temp); | |
3480 | POSTING_READ(SOUTH_CHICKEN1); | |
3481 | } | |
3482 | ||
3483 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
3484 | { | |
3485 | struct drm_device *dev = intel_crtc->base.dev; | |
3486 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3487 | ||
3488 | switch (intel_crtc->pipe) { | |
3489 | case PIPE_A: | |
3490 | break; | |
3491 | case PIPE_B: | |
3492 | if (intel_crtc->config.fdi_lanes > 2) | |
3493 | WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT); | |
3494 | else | |
3495 | cpt_enable_fdi_bc_bifurcation(dev); | |
3496 | ||
3497 | break; | |
3498 | case PIPE_C: | |
3499 | cpt_enable_fdi_bc_bifurcation(dev); | |
3500 | ||
3501 | break; | |
3502 | default: | |
3503 | BUG(); | |
3504 | } | |
3505 | } | |
3506 | ||
f67a559d JB |
3507 | /* |
3508 | * Enable PCH resources required for PCH ports: | |
3509 | * - PCH PLLs | |
3510 | * - FDI training & RX/TX | |
3511 | * - update transcoder timings | |
3512 | * - DP transcoding bits | |
3513 | * - transcoder | |
3514 | */ | |
3515 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
3516 | { |
3517 | struct drm_device *dev = crtc->dev; | |
3518 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3519 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3520 | int pipe = intel_crtc->pipe; | |
ee7b9f93 | 3521 | u32 reg, temp; |
2c07245f | 3522 | |
ab9412ba | 3523 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 3524 | |
1fbc0d78 DV |
3525 | if (IS_IVYBRIDGE(dev)) |
3526 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
3527 | ||
cd986abb DV |
3528 | /* Write the TU size bits before fdi link training, so that error |
3529 | * detection works. */ | |
3530 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
3531 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
3532 | ||
c98e9dcf | 3533 | /* For PCH output, training FDI link */ |
674cf967 | 3534 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 3535 | |
3ad8a208 DV |
3536 | /* We need to program the right clock selection before writing the pixel |
3537 | * mutliplier into the DPLL. */ | |
303b81e0 | 3538 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 3539 | u32 sel; |
4b645f14 | 3540 | |
c98e9dcf | 3541 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
3542 | temp |= TRANS_DPLL_ENABLE(pipe); |
3543 | sel = TRANS_DPLLB_SEL(pipe); | |
a43f6e0f | 3544 | if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B) |
ee7b9f93 JB |
3545 | temp |= sel; |
3546 | else | |
3547 | temp &= ~sel; | |
c98e9dcf | 3548 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 3549 | } |
5eddb70b | 3550 | |
3ad8a208 DV |
3551 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
3552 | * transcoder, and we actually should do this to not upset any PCH | |
3553 | * transcoder that already use the clock when we share it. | |
3554 | * | |
3555 | * Note that enable_shared_dpll tries to do the right thing, but | |
3556 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
3557 | * the right LVDS enable sequence. */ | |
85b3894f | 3558 | intel_enable_shared_dpll(intel_crtc); |
3ad8a208 | 3559 | |
d9b6cb56 JB |
3560 | /* set transcoder timing, panel must allow it */ |
3561 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 3562 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 3563 | |
303b81e0 | 3564 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 3565 | |
c98e9dcf JB |
3566 | /* For PCH DP, enable TRANS_DP_CTL */ |
3567 | if (HAS_PCH_CPT(dev) && | |
417e822d KP |
3568 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
3569 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
dfd07d72 | 3570 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
5eddb70b CW |
3571 | reg = TRANS_DP_CTL(pipe); |
3572 | temp = I915_READ(reg); | |
3573 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
3574 | TRANS_DP_SYNC_MASK | |
3575 | TRANS_DP_BPC_MASK); | |
5eddb70b CW |
3576 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
3577 | TRANS_DP_ENH_FRAMING); | |
9325c9f0 | 3578 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf JB |
3579 | |
3580 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) | |
5eddb70b | 3581 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
c98e9dcf | 3582 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 3583 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
3584 | |
3585 | switch (intel_trans_dp_port_sel(crtc)) { | |
3586 | case PCH_DP_B: | |
5eddb70b | 3587 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf JB |
3588 | break; |
3589 | case PCH_DP_C: | |
5eddb70b | 3590 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf JB |
3591 | break; |
3592 | case PCH_DP_D: | |
5eddb70b | 3593 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
3594 | break; |
3595 | default: | |
e95d41e1 | 3596 | BUG(); |
32f9d658 | 3597 | } |
2c07245f | 3598 | |
5eddb70b | 3599 | I915_WRITE(reg, temp); |
6be4a607 | 3600 | } |
b52eb4dc | 3601 | |
b8a4f404 | 3602 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
3603 | } |
3604 | ||
1507e5bd PZ |
3605 | static void lpt_pch_enable(struct drm_crtc *crtc) |
3606 | { | |
3607 | struct drm_device *dev = crtc->dev; | |
3608 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3609 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3b117c8f | 3610 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
1507e5bd | 3611 | |
ab9412ba | 3612 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 3613 | |
8c52b5e8 | 3614 | lpt_program_iclkip(crtc); |
1507e5bd | 3615 | |
0540e488 | 3616 | /* Set transcoder timing. */ |
275f01b2 | 3617 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 3618 | |
937bb610 | 3619 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
3620 | } |
3621 | ||
e2b78267 | 3622 | static void intel_put_shared_dpll(struct intel_crtc *crtc) |
ee7b9f93 | 3623 | { |
e2b78267 | 3624 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
ee7b9f93 JB |
3625 | |
3626 | if (pll == NULL) | |
3627 | return; | |
3628 | ||
3629 | if (pll->refcount == 0) { | |
46edb027 | 3630 | WARN(1, "bad %s refcount\n", pll->name); |
ee7b9f93 JB |
3631 | return; |
3632 | } | |
3633 | ||
f4a091c7 DV |
3634 | if (--pll->refcount == 0) { |
3635 | WARN_ON(pll->on); | |
3636 | WARN_ON(pll->active); | |
3637 | } | |
3638 | ||
a43f6e0f | 3639 | crtc->config.shared_dpll = DPLL_ID_PRIVATE; |
ee7b9f93 JB |
3640 | } |
3641 | ||
b89a1d39 | 3642 | static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc) |
ee7b9f93 | 3643 | { |
e2b78267 DV |
3644 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
3645 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
3646 | enum intel_dpll_id i; | |
ee7b9f93 | 3647 | |
ee7b9f93 | 3648 | if (pll) { |
46edb027 DV |
3649 | DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n", |
3650 | crtc->base.base.id, pll->name); | |
e2b78267 | 3651 | intel_put_shared_dpll(crtc); |
ee7b9f93 JB |
3652 | } |
3653 | ||
98b6bd99 DV |
3654 | if (HAS_PCH_IBX(dev_priv->dev)) { |
3655 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ | |
d94ab068 | 3656 | i = (enum intel_dpll_id) crtc->pipe; |
e72f9fbf | 3657 | pll = &dev_priv->shared_dplls[i]; |
98b6bd99 | 3658 | |
46edb027 DV |
3659 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
3660 | crtc->base.base.id, pll->name); | |
98b6bd99 | 3661 | |
f2a69f44 DV |
3662 | WARN_ON(pll->refcount); |
3663 | ||
98b6bd99 DV |
3664 | goto found; |
3665 | } | |
3666 | ||
e72f9fbf DV |
3667 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
3668 | pll = &dev_priv->shared_dplls[i]; | |
ee7b9f93 JB |
3669 | |
3670 | /* Only want to check enabled timings first */ | |
3671 | if (pll->refcount == 0) | |
3672 | continue; | |
3673 | ||
b89a1d39 DV |
3674 | if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state, |
3675 | sizeof(pll->hw_state)) == 0) { | |
46edb027 | 3676 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n", |
e2b78267 | 3677 | crtc->base.base.id, |
46edb027 | 3678 | pll->name, pll->refcount, pll->active); |
ee7b9f93 JB |
3679 | |
3680 | goto found; | |
3681 | } | |
3682 | } | |
3683 | ||
3684 | /* Ok no matching timings, maybe there's a free one? */ | |
e72f9fbf DV |
3685 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
3686 | pll = &dev_priv->shared_dplls[i]; | |
ee7b9f93 | 3687 | if (pll->refcount == 0) { |
46edb027 DV |
3688 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
3689 | crtc->base.base.id, pll->name); | |
ee7b9f93 JB |
3690 | goto found; |
3691 | } | |
3692 | } | |
3693 | ||
3694 | return NULL; | |
3695 | ||
3696 | found: | |
f2a69f44 DV |
3697 | if (pll->refcount == 0) |
3698 | pll->hw_state = crtc->config.dpll_hw_state; | |
3699 | ||
a43f6e0f | 3700 | crtc->config.shared_dpll = i; |
46edb027 DV |
3701 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
3702 | pipe_name(crtc->pipe)); | |
ee7b9f93 | 3703 | |
cdbd2316 | 3704 | pll->refcount++; |
e04c7350 | 3705 | |
ee7b9f93 JB |
3706 | return pll; |
3707 | } | |
3708 | ||
a1520318 | 3709 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 JB |
3710 | { |
3711 | struct drm_i915_private *dev_priv = dev->dev_private; | |
23670b32 | 3712 | int dslreg = PIPEDSL(pipe); |
d4270e57 JB |
3713 | u32 temp; |
3714 | ||
3715 | temp = I915_READ(dslreg); | |
3716 | udelay(500); | |
3717 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 3718 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 3719 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
3720 | } |
3721 | } | |
3722 | ||
b074cec8 JB |
3723 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
3724 | { | |
3725 | struct drm_device *dev = crtc->base.dev; | |
3726 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3727 | int pipe = crtc->pipe; | |
3728 | ||
fd4daa9c | 3729 | if (crtc->config.pch_pfit.enabled) { |
b074cec8 JB |
3730 | /* Force use of hard-coded filter coefficients |
3731 | * as some pre-programmed values are broken, | |
3732 | * e.g. x201. | |
3733 | */ | |
3734 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
3735 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
3736 | PF_PIPE_SEL_IVB(pipe)); | |
3737 | else | |
3738 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
3739 | I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos); | |
3740 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size); | |
d4270e57 JB |
3741 | } |
3742 | } | |
3743 | ||
bb53d4ae VS |
3744 | static void intel_enable_planes(struct drm_crtc *crtc) |
3745 | { | |
3746 | struct drm_device *dev = crtc->dev; | |
3747 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
af2b653b | 3748 | struct drm_plane *plane; |
bb53d4ae VS |
3749 | struct intel_plane *intel_plane; |
3750 | ||
af2b653b MR |
3751 | drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
3752 | intel_plane = to_intel_plane(plane); | |
bb53d4ae VS |
3753 | if (intel_plane->pipe == pipe) |
3754 | intel_plane_restore(&intel_plane->base); | |
af2b653b | 3755 | } |
bb53d4ae VS |
3756 | } |
3757 | ||
3758 | static void intel_disable_planes(struct drm_crtc *crtc) | |
3759 | { | |
3760 | struct drm_device *dev = crtc->dev; | |
3761 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
af2b653b | 3762 | struct drm_plane *plane; |
bb53d4ae VS |
3763 | struct intel_plane *intel_plane; |
3764 | ||
af2b653b MR |
3765 | drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
3766 | intel_plane = to_intel_plane(plane); | |
bb53d4ae VS |
3767 | if (intel_plane->pipe == pipe) |
3768 | intel_plane_disable(&intel_plane->base); | |
af2b653b | 3769 | } |
bb53d4ae VS |
3770 | } |
3771 | ||
20bc8673 | 3772 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 3773 | { |
cea165c3 VS |
3774 | struct drm_device *dev = crtc->base.dev; |
3775 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d77e4531 PZ |
3776 | |
3777 | if (!crtc->config.ips_enabled) | |
3778 | return; | |
3779 | ||
cea165c3 VS |
3780 | /* We can only enable IPS after we enable a plane and wait for a vblank */ |
3781 | intel_wait_for_vblank(dev, crtc->pipe); | |
3782 | ||
d77e4531 | 3783 | assert_plane_enabled(dev_priv, crtc->plane); |
cea165c3 | 3784 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
3785 | mutex_lock(&dev_priv->rps.hw_lock); |
3786 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
3787 | mutex_unlock(&dev_priv->rps.hw_lock); | |
3788 | /* Quoting Art Runyan: "its not safe to expect any particular | |
3789 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
3790 | * mailbox." Moreover, the mailbox may return a bogus state, |
3791 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
3792 | */ |
3793 | } else { | |
3794 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
3795 | /* The bit only becomes 1 in the next vblank, so this wait here | |
3796 | * is essentially intel_wait_for_vblank. If we don't have this | |
3797 | * and don't wait for vblanks until the end of crtc_enable, then | |
3798 | * the HW state readout code will complain that the expected | |
3799 | * IPS_CTL value is not the one we read. */ | |
3800 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) | |
3801 | DRM_ERROR("Timed out waiting for IPS enable\n"); | |
3802 | } | |
d77e4531 PZ |
3803 | } |
3804 | ||
20bc8673 | 3805 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
3806 | { |
3807 | struct drm_device *dev = crtc->base.dev; | |
3808 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3809 | ||
3810 | if (!crtc->config.ips_enabled) | |
3811 | return; | |
3812 | ||
3813 | assert_plane_enabled(dev_priv, crtc->plane); | |
23d0b130 | 3814 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
3815 | mutex_lock(&dev_priv->rps.hw_lock); |
3816 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
3817 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 BW |
3818 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
3819 | if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42)) | |
3820 | DRM_ERROR("Timed out waiting for IPS disable\n"); | |
e59150dc | 3821 | } else { |
2a114cc1 | 3822 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
3823 | POSTING_READ(IPS_CTL); |
3824 | } | |
d77e4531 PZ |
3825 | |
3826 | /* We need to wait for a vblank before we can disable the plane. */ | |
3827 | intel_wait_for_vblank(dev, crtc->pipe); | |
3828 | } | |
3829 | ||
3830 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ | |
3831 | static void intel_crtc_load_lut(struct drm_crtc *crtc) | |
3832 | { | |
3833 | struct drm_device *dev = crtc->dev; | |
3834 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3835 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3836 | enum pipe pipe = intel_crtc->pipe; | |
3837 | int palreg = PALETTE(pipe); | |
3838 | int i; | |
3839 | bool reenable_ips = false; | |
3840 | ||
3841 | /* The clocks have to be on to load the palette. */ | |
3842 | if (!crtc->enabled || !intel_crtc->active) | |
3843 | return; | |
3844 | ||
3845 | if (!HAS_PCH_SPLIT(dev_priv->dev)) { | |
3846 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) | |
3847 | assert_dsi_pll_enabled(dev_priv); | |
3848 | else | |
3849 | assert_pll_enabled(dev_priv, pipe); | |
3850 | } | |
3851 | ||
3852 | /* use legacy palette for Ironlake */ | |
3853 | if (HAS_PCH_SPLIT(dev)) | |
3854 | palreg = LGC_PALETTE(pipe); | |
3855 | ||
3856 | /* Workaround : Do not read or write the pipe palette/gamma data while | |
3857 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. | |
3858 | */ | |
41e6fc4c | 3859 | if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled && |
d77e4531 PZ |
3860 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == |
3861 | GAMMA_MODE_MODE_SPLIT)) { | |
3862 | hsw_disable_ips(intel_crtc); | |
3863 | reenable_ips = true; | |
3864 | } | |
3865 | ||
3866 | for (i = 0; i < 256; i++) { | |
3867 | I915_WRITE(palreg + 4 * i, | |
3868 | (intel_crtc->lut_r[i] << 16) | | |
3869 | (intel_crtc->lut_g[i] << 8) | | |
3870 | intel_crtc->lut_b[i]); | |
3871 | } | |
3872 | ||
3873 | if (reenable_ips) | |
3874 | hsw_enable_ips(intel_crtc); | |
3875 | } | |
3876 | ||
d3eedb1a VS |
3877 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
3878 | { | |
3879 | if (!enable && intel_crtc->overlay) { | |
3880 | struct drm_device *dev = intel_crtc->base.dev; | |
3881 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3882 | ||
3883 | mutex_lock(&dev->struct_mutex); | |
3884 | dev_priv->mm.interruptible = false; | |
3885 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
3886 | dev_priv->mm.interruptible = true; | |
3887 | mutex_unlock(&dev->struct_mutex); | |
3888 | } | |
3889 | ||
3890 | /* Let userspace switch the overlay on again. In most cases userspace | |
3891 | * has to recompute where to put it anyway. | |
3892 | */ | |
3893 | } | |
3894 | ||
3895 | /** | |
3896 | * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware | |
3897 | * cursor plane briefly if not already running after enabling the display | |
3898 | * plane. | |
3899 | * This workaround avoids occasional blank screens when self refresh is | |
3900 | * enabled. | |
3901 | */ | |
3902 | static void | |
3903 | g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe) | |
3904 | { | |
3905 | u32 cntl = I915_READ(CURCNTR(pipe)); | |
3906 | ||
3907 | if ((cntl & CURSOR_MODE) == 0) { | |
3908 | u32 fw_bcl_self = I915_READ(FW_BLC_SELF); | |
3909 | ||
3910 | I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN); | |
3911 | I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX); | |
3912 | intel_wait_for_vblank(dev_priv->dev, pipe); | |
3913 | I915_WRITE(CURCNTR(pipe), cntl); | |
3914 | I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe))); | |
3915 | I915_WRITE(FW_BLC_SELF, fw_bcl_self); | |
3916 | } | |
3917 | } | |
3918 | ||
3919 | static void intel_crtc_enable_planes(struct drm_crtc *crtc) | |
a5c4d7bc VS |
3920 | { |
3921 | struct drm_device *dev = crtc->dev; | |
3922 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3923 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3924 | int pipe = intel_crtc->pipe; | |
3925 | int plane = intel_crtc->plane; | |
3926 | ||
f98551ae VS |
3927 | drm_vblank_on(dev, pipe); |
3928 | ||
a5c4d7bc VS |
3929 | intel_enable_primary_hw_plane(dev_priv, plane, pipe); |
3930 | intel_enable_planes(crtc); | |
d3eedb1a VS |
3931 | /* The fixup needs to happen before cursor is enabled */ |
3932 | if (IS_G4X(dev)) | |
3933 | g4x_fixup_plane(dev_priv, pipe); | |
a5c4d7bc | 3934 | intel_crtc_update_cursor(crtc, true); |
d3eedb1a | 3935 | intel_crtc_dpms_overlay(intel_crtc, true); |
a5c4d7bc VS |
3936 | |
3937 | hsw_enable_ips(intel_crtc); | |
3938 | ||
3939 | mutex_lock(&dev->struct_mutex); | |
3940 | intel_update_fbc(dev); | |
71b1c373 | 3941 | intel_edp_psr_update(dev); |
a5c4d7bc VS |
3942 | mutex_unlock(&dev->struct_mutex); |
3943 | } | |
3944 | ||
d3eedb1a | 3945 | static void intel_crtc_disable_planes(struct drm_crtc *crtc) |
a5c4d7bc VS |
3946 | { |
3947 | struct drm_device *dev = crtc->dev; | |
3948 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3949 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3950 | int pipe = intel_crtc->pipe; | |
3951 | int plane = intel_crtc->plane; | |
3952 | ||
3953 | intel_crtc_wait_for_pending_flips(crtc); | |
a5c4d7bc VS |
3954 | |
3955 | if (dev_priv->fbc.plane == plane) | |
3956 | intel_disable_fbc(dev); | |
3957 | ||
3958 | hsw_disable_ips(intel_crtc); | |
3959 | ||
d3eedb1a | 3960 | intel_crtc_dpms_overlay(intel_crtc, false); |
a5c4d7bc VS |
3961 | intel_crtc_update_cursor(crtc, false); |
3962 | intel_disable_planes(crtc); | |
3963 | intel_disable_primary_hw_plane(dev_priv, plane, pipe); | |
f98551ae VS |
3964 | |
3965 | drm_vblank_off(dev, pipe); | |
a5c4d7bc VS |
3966 | } |
3967 | ||
f67a559d JB |
3968 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
3969 | { | |
3970 | struct drm_device *dev = crtc->dev; | |
3971 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3972 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 3973 | struct intel_encoder *encoder; |
f67a559d | 3974 | int pipe = intel_crtc->pipe; |
29407aab | 3975 | enum plane plane = intel_crtc->plane; |
f67a559d | 3976 | |
08a48469 DV |
3977 | WARN_ON(!crtc->enabled); |
3978 | ||
f67a559d JB |
3979 | if (intel_crtc->active) |
3980 | return; | |
3981 | ||
b14b1055 DV |
3982 | if (intel_crtc->config.has_pch_encoder) |
3983 | intel_prepare_shared_dpll(intel_crtc); | |
3984 | ||
29407aab DV |
3985 | if (intel_crtc->config.has_dp_encoder) |
3986 | intel_dp_set_m_n(intel_crtc); | |
3987 | ||
3988 | intel_set_pipe_timings(intel_crtc); | |
3989 | ||
3990 | if (intel_crtc->config.has_pch_encoder) { | |
3991 | intel_cpu_transcoder_set_m_n(intel_crtc, | |
3992 | &intel_crtc->config.fdi_m_n); | |
3993 | } | |
3994 | ||
3995 | ironlake_set_pipeconf(crtc); | |
3996 | ||
3997 | /* Set up the display plane register */ | |
3998 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE); | |
3999 | POSTING_READ(DSPCNTR(plane)); | |
4000 | ||
4001 | dev_priv->display.update_primary_plane(crtc, crtc->primary->fb, | |
4002 | crtc->x, crtc->y); | |
4003 | ||
f67a559d | 4004 | intel_crtc->active = true; |
8664281b PZ |
4005 | |
4006 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); | |
4007 | intel_set_pch_fifo_underrun_reporting(dev, pipe, true); | |
4008 | ||
f6736a1a | 4009 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
4010 | if (encoder->pre_enable) |
4011 | encoder->pre_enable(encoder); | |
f67a559d | 4012 | |
5bfe2ac0 | 4013 | if (intel_crtc->config.has_pch_encoder) { |
fff367c7 DV |
4014 | /* Note: FDI PLL enabling _must_ be done before we enable the |
4015 | * cpu pipes, hence this is separate from all the other fdi/pch | |
4016 | * enabling. */ | |
88cefb6c | 4017 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
4018 | } else { |
4019 | assert_fdi_tx_disabled(dev_priv, pipe); | |
4020 | assert_fdi_rx_disabled(dev_priv, pipe); | |
4021 | } | |
f67a559d | 4022 | |
b074cec8 | 4023 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 4024 | |
9c54c0dd JB |
4025 | /* |
4026 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4027 | * clocks enabled | |
4028 | */ | |
4029 | intel_crtc_load_lut(crtc); | |
4030 | ||
f37fcc2a | 4031 | intel_update_watermarks(crtc); |
e1fdc473 | 4032 | intel_enable_pipe(intel_crtc); |
f67a559d | 4033 | |
5bfe2ac0 | 4034 | if (intel_crtc->config.has_pch_encoder) |
f67a559d | 4035 | ironlake_pch_enable(crtc); |
c98e9dcf | 4036 | |
fa5c73b1 DV |
4037 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4038 | encoder->enable(encoder); | |
61b77ddd DV |
4039 | |
4040 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 4041 | cpt_verify_modeset(dev, intel_crtc->pipe); |
6ce94100 | 4042 | |
d3eedb1a | 4043 | intel_crtc_enable_planes(crtc); |
6be4a607 JB |
4044 | } |
4045 | ||
42db64ef PZ |
4046 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
4047 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
4048 | { | |
f5adf94e | 4049 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
4050 | } |
4051 | ||
e4916946 PZ |
4052 | /* |
4053 | * This implements the workaround described in the "notes" section of the mode | |
4054 | * set sequence documentation. When going from no pipes or single pipe to | |
4055 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
4056 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
4057 | */ | |
4058 | static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc) | |
4059 | { | |
4060 | struct drm_device *dev = crtc->base.dev; | |
4061 | struct intel_crtc *crtc_it, *other_active_crtc = NULL; | |
4062 | ||
4063 | /* We want to get the other_active_crtc only if there's only 1 other | |
4064 | * active crtc. */ | |
d3fcc808 | 4065 | for_each_intel_crtc(dev, crtc_it) { |
e4916946 PZ |
4066 | if (!crtc_it->active || crtc_it == crtc) |
4067 | continue; | |
4068 | ||
4069 | if (other_active_crtc) | |
4070 | return; | |
4071 | ||
4072 | other_active_crtc = crtc_it; | |
4073 | } | |
4074 | if (!other_active_crtc) | |
4075 | return; | |
4076 | ||
4077 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
4078 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
4079 | } | |
4080 | ||
4f771f10 PZ |
4081 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
4082 | { | |
4083 | struct drm_device *dev = crtc->dev; | |
4084 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4085 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4086 | struct intel_encoder *encoder; | |
4087 | int pipe = intel_crtc->pipe; | |
229fca97 | 4088 | enum plane plane = intel_crtc->plane; |
4f771f10 PZ |
4089 | |
4090 | WARN_ON(!crtc->enabled); | |
4091 | ||
4092 | if (intel_crtc->active) | |
4093 | return; | |
4094 | ||
229fca97 DV |
4095 | if (intel_crtc->config.has_dp_encoder) |
4096 | intel_dp_set_m_n(intel_crtc); | |
4097 | ||
4098 | intel_set_pipe_timings(intel_crtc); | |
4099 | ||
4100 | if (intel_crtc->config.has_pch_encoder) { | |
4101 | intel_cpu_transcoder_set_m_n(intel_crtc, | |
4102 | &intel_crtc->config.fdi_m_n); | |
4103 | } | |
4104 | ||
4105 | haswell_set_pipeconf(crtc); | |
4106 | ||
4107 | intel_set_pipe_csc(crtc); | |
4108 | ||
4109 | /* Set up the display plane register */ | |
4110 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE); | |
4111 | POSTING_READ(DSPCNTR(plane)); | |
4112 | ||
4113 | dev_priv->display.update_primary_plane(crtc, crtc->primary->fb, | |
4114 | crtc->x, crtc->y); | |
4115 | ||
4f771f10 | 4116 | intel_crtc->active = true; |
8664281b PZ |
4117 | |
4118 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); | |
4119 | if (intel_crtc->config.has_pch_encoder) | |
4120 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); | |
4121 | ||
5bfe2ac0 | 4122 | if (intel_crtc->config.has_pch_encoder) |
04945641 | 4123 | dev_priv->display.fdi_link_train(crtc); |
4f771f10 PZ |
4124 | |
4125 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
4126 | if (encoder->pre_enable) | |
4127 | encoder->pre_enable(encoder); | |
4128 | ||
1f544388 | 4129 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 4130 | |
b074cec8 | 4131 | ironlake_pfit_enable(intel_crtc); |
4f771f10 PZ |
4132 | |
4133 | /* | |
4134 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4135 | * clocks enabled | |
4136 | */ | |
4137 | intel_crtc_load_lut(crtc); | |
4138 | ||
1f544388 | 4139 | intel_ddi_set_pipe_settings(crtc); |
8228c251 | 4140 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 4141 | |
f37fcc2a | 4142 | intel_update_watermarks(crtc); |
e1fdc473 | 4143 | intel_enable_pipe(intel_crtc); |
42db64ef | 4144 | |
5bfe2ac0 | 4145 | if (intel_crtc->config.has_pch_encoder) |
1507e5bd | 4146 | lpt_pch_enable(crtc); |
4f771f10 | 4147 | |
8807e55b | 4148 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 4149 | encoder->enable(encoder); |
8807e55b JN |
4150 | intel_opregion_notify_encoder(encoder, true); |
4151 | } | |
4f771f10 | 4152 | |
e4916946 PZ |
4153 | /* If we change the relative order between pipe/planes enabling, we need |
4154 | * to change the workaround. */ | |
4155 | haswell_mode_set_planes_workaround(intel_crtc); | |
d3eedb1a | 4156 | intel_crtc_enable_planes(crtc); |
4f771f10 PZ |
4157 | } |
4158 | ||
3f8dce3a DV |
4159 | static void ironlake_pfit_disable(struct intel_crtc *crtc) |
4160 | { | |
4161 | struct drm_device *dev = crtc->base.dev; | |
4162 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4163 | int pipe = crtc->pipe; | |
4164 | ||
4165 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
4166 | * it's in use. The hw state code will make sure we get this right. */ | |
fd4daa9c | 4167 | if (crtc->config.pch_pfit.enabled) { |
3f8dce3a DV |
4168 | I915_WRITE(PF_CTL(pipe), 0); |
4169 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
4170 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
4171 | } | |
4172 | } | |
4173 | ||
6be4a607 JB |
4174 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
4175 | { | |
4176 | struct drm_device *dev = crtc->dev; | |
4177 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4178 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4179 | struct intel_encoder *encoder; |
6be4a607 | 4180 | int pipe = intel_crtc->pipe; |
5eddb70b | 4181 | u32 reg, temp; |
b52eb4dc | 4182 | |
f7abfe8b CW |
4183 | if (!intel_crtc->active) |
4184 | return; | |
4185 | ||
d3eedb1a | 4186 | intel_crtc_disable_planes(crtc); |
a5c4d7bc | 4187 | |
ea9d758d DV |
4188 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4189 | encoder->disable(encoder); | |
4190 | ||
d925c59a DV |
4191 | if (intel_crtc->config.has_pch_encoder) |
4192 | intel_set_pch_fifo_underrun_reporting(dev, pipe, false); | |
4193 | ||
b24e7179 | 4194 | intel_disable_pipe(dev_priv, pipe); |
32f9d658 | 4195 | |
3f8dce3a | 4196 | ironlake_pfit_disable(intel_crtc); |
2c07245f | 4197 | |
bf49ec8c DV |
4198 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4199 | if (encoder->post_disable) | |
4200 | encoder->post_disable(encoder); | |
2c07245f | 4201 | |
d925c59a DV |
4202 | if (intel_crtc->config.has_pch_encoder) { |
4203 | ironlake_fdi_disable(crtc); | |
913d8d11 | 4204 | |
d925c59a DV |
4205 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
4206 | intel_set_pch_fifo_underrun_reporting(dev, pipe, true); | |
6be4a607 | 4207 | |
d925c59a DV |
4208 | if (HAS_PCH_CPT(dev)) { |
4209 | /* disable TRANS_DP_CTL */ | |
4210 | reg = TRANS_DP_CTL(pipe); | |
4211 | temp = I915_READ(reg); | |
4212 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
4213 | TRANS_DP_PORT_SEL_MASK); | |
4214 | temp |= TRANS_DP_PORT_SEL_NONE; | |
4215 | I915_WRITE(reg, temp); | |
4216 | ||
4217 | /* disable DPLL_SEL */ | |
4218 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 4219 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 4220 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 4221 | } |
e3421a18 | 4222 | |
d925c59a | 4223 | /* disable PCH DPLL */ |
e72f9fbf | 4224 | intel_disable_shared_dpll(intel_crtc); |
8db9d77b | 4225 | |
d925c59a DV |
4226 | ironlake_fdi_pll_disable(intel_crtc); |
4227 | } | |
6b383a7f | 4228 | |
f7abfe8b | 4229 | intel_crtc->active = false; |
46ba614c | 4230 | intel_update_watermarks(crtc); |
d1ebd816 BW |
4231 | |
4232 | mutex_lock(&dev->struct_mutex); | |
6b383a7f | 4233 | intel_update_fbc(dev); |
71b1c373 | 4234 | intel_edp_psr_update(dev); |
d1ebd816 | 4235 | mutex_unlock(&dev->struct_mutex); |
6be4a607 | 4236 | } |
1b3c7a47 | 4237 | |
4f771f10 | 4238 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 4239 | { |
4f771f10 PZ |
4240 | struct drm_device *dev = crtc->dev; |
4241 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 4242 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 PZ |
4243 | struct intel_encoder *encoder; |
4244 | int pipe = intel_crtc->pipe; | |
3b117c8f | 4245 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
ee7b9f93 | 4246 | |
4f771f10 PZ |
4247 | if (!intel_crtc->active) |
4248 | return; | |
4249 | ||
d3eedb1a | 4250 | intel_crtc_disable_planes(crtc); |
dda9a66a | 4251 | |
8807e55b JN |
4252 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4253 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 4254 | encoder->disable(encoder); |
8807e55b | 4255 | } |
4f771f10 | 4256 | |
8664281b PZ |
4257 | if (intel_crtc->config.has_pch_encoder) |
4258 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false); | |
4f771f10 PZ |
4259 | intel_disable_pipe(dev_priv, pipe); |
4260 | ||
ad80a810 | 4261 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 4262 | |
3f8dce3a | 4263 | ironlake_pfit_disable(intel_crtc); |
4f771f10 | 4264 | |
1f544388 | 4265 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 PZ |
4266 | |
4267 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
4268 | if (encoder->post_disable) | |
4269 | encoder->post_disable(encoder); | |
4270 | ||
88adfff1 | 4271 | if (intel_crtc->config.has_pch_encoder) { |
ab4d966c | 4272 | lpt_disable_pch_transcoder(dev_priv); |
8664281b | 4273 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); |
1ad960f2 | 4274 | intel_ddi_fdi_disable(crtc); |
83616634 | 4275 | } |
4f771f10 PZ |
4276 | |
4277 | intel_crtc->active = false; | |
46ba614c | 4278 | intel_update_watermarks(crtc); |
4f771f10 PZ |
4279 | |
4280 | mutex_lock(&dev->struct_mutex); | |
4281 | intel_update_fbc(dev); | |
71b1c373 | 4282 | intel_edp_psr_update(dev); |
4f771f10 PZ |
4283 | mutex_unlock(&dev->struct_mutex); |
4284 | } | |
4285 | ||
ee7b9f93 JB |
4286 | static void ironlake_crtc_off(struct drm_crtc *crtc) |
4287 | { | |
4288 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
e72f9fbf | 4289 | intel_put_shared_dpll(intel_crtc); |
ee7b9f93 JB |
4290 | } |
4291 | ||
6441ab5f PZ |
4292 | static void haswell_crtc_off(struct drm_crtc *crtc) |
4293 | { | |
4294 | intel_ddi_put_crtc_pll(crtc); | |
4295 | } | |
4296 | ||
2dd24552 JB |
4297 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
4298 | { | |
4299 | struct drm_device *dev = crtc->base.dev; | |
4300 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4301 | struct intel_crtc_config *pipe_config = &crtc->config; | |
4302 | ||
328d8e82 | 4303 | if (!crtc->config.gmch_pfit.control) |
2dd24552 JB |
4304 | return; |
4305 | ||
2dd24552 | 4306 | /* |
c0b03411 DV |
4307 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
4308 | * according to register description and PRM. | |
2dd24552 | 4309 | */ |
c0b03411 DV |
4310 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
4311 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 4312 | |
b074cec8 JB |
4313 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
4314 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
4315 | |
4316 | /* Border color in case we don't scale up to the full screen. Black by | |
4317 | * default, change to something else for debugging. */ | |
4318 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
4319 | } |
4320 | ||
77d22dca ID |
4321 | #define for_each_power_domain(domain, mask) \ |
4322 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ | |
4323 | if ((1 << (domain)) & (mask)) | |
4324 | ||
319be8ae ID |
4325 | enum intel_display_power_domain |
4326 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) | |
4327 | { | |
4328 | struct drm_device *dev = intel_encoder->base.dev; | |
4329 | struct intel_digital_port *intel_dig_port; | |
4330 | ||
4331 | switch (intel_encoder->type) { | |
4332 | case INTEL_OUTPUT_UNKNOWN: | |
4333 | /* Only DDI platforms should ever use this output type */ | |
4334 | WARN_ON_ONCE(!HAS_DDI(dev)); | |
4335 | case INTEL_OUTPUT_DISPLAYPORT: | |
4336 | case INTEL_OUTPUT_HDMI: | |
4337 | case INTEL_OUTPUT_EDP: | |
4338 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
4339 | switch (intel_dig_port->port) { | |
4340 | case PORT_A: | |
4341 | return POWER_DOMAIN_PORT_DDI_A_4_LANES; | |
4342 | case PORT_B: | |
4343 | return POWER_DOMAIN_PORT_DDI_B_4_LANES; | |
4344 | case PORT_C: | |
4345 | return POWER_DOMAIN_PORT_DDI_C_4_LANES; | |
4346 | case PORT_D: | |
4347 | return POWER_DOMAIN_PORT_DDI_D_4_LANES; | |
4348 | default: | |
4349 | WARN_ON_ONCE(1); | |
4350 | return POWER_DOMAIN_PORT_OTHER; | |
4351 | } | |
4352 | case INTEL_OUTPUT_ANALOG: | |
4353 | return POWER_DOMAIN_PORT_CRT; | |
4354 | case INTEL_OUTPUT_DSI: | |
4355 | return POWER_DOMAIN_PORT_DSI; | |
4356 | default: | |
4357 | return POWER_DOMAIN_PORT_OTHER; | |
4358 | } | |
4359 | } | |
4360 | ||
4361 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc) | |
77d22dca | 4362 | { |
319be8ae ID |
4363 | struct drm_device *dev = crtc->dev; |
4364 | struct intel_encoder *intel_encoder; | |
4365 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4366 | enum pipe pipe = intel_crtc->pipe; | |
4367 | bool pfit_enabled = intel_crtc->config.pch_pfit.enabled; | |
77d22dca ID |
4368 | unsigned long mask; |
4369 | enum transcoder transcoder; | |
4370 | ||
4371 | transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe); | |
4372 | ||
4373 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); | |
4374 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
4375 | if (pfit_enabled) | |
4376 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); | |
4377 | ||
319be8ae ID |
4378 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
4379 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); | |
4380 | ||
77d22dca ID |
4381 | return mask; |
4382 | } | |
4383 | ||
4384 | void intel_display_set_init_power(struct drm_i915_private *dev_priv, | |
4385 | bool enable) | |
4386 | { | |
4387 | if (dev_priv->power_domains.init_power_on == enable) | |
4388 | return; | |
4389 | ||
4390 | if (enable) | |
4391 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); | |
4392 | else | |
4393 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); | |
4394 | ||
4395 | dev_priv->power_domains.init_power_on = enable; | |
4396 | } | |
4397 | ||
4398 | static void modeset_update_crtc_power_domains(struct drm_device *dev) | |
4399 | { | |
4400 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4401 | unsigned long pipe_domains[I915_MAX_PIPES] = { 0, }; | |
4402 | struct intel_crtc *crtc; | |
4403 | ||
4404 | /* | |
4405 | * First get all needed power domains, then put all unneeded, to avoid | |
4406 | * any unnecessary toggling of the power wells. | |
4407 | */ | |
d3fcc808 | 4408 | for_each_intel_crtc(dev, crtc) { |
77d22dca ID |
4409 | enum intel_display_power_domain domain; |
4410 | ||
4411 | if (!crtc->base.enabled) | |
4412 | continue; | |
4413 | ||
319be8ae | 4414 | pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base); |
77d22dca ID |
4415 | |
4416 | for_each_power_domain(domain, pipe_domains[crtc->pipe]) | |
4417 | intel_display_power_get(dev_priv, domain); | |
4418 | } | |
4419 | ||
d3fcc808 | 4420 | for_each_intel_crtc(dev, crtc) { |
77d22dca ID |
4421 | enum intel_display_power_domain domain; |
4422 | ||
4423 | for_each_power_domain(domain, crtc->enabled_power_domains) | |
4424 | intel_display_power_put(dev_priv, domain); | |
4425 | ||
4426 | crtc->enabled_power_domains = pipe_domains[crtc->pipe]; | |
4427 | } | |
4428 | ||
4429 | intel_display_set_init_power(dev_priv, false); | |
4430 | } | |
4431 | ||
586f49dc | 4432 | int valleyview_get_vco(struct drm_i915_private *dev_priv) |
30a970c6 | 4433 | { |
586f49dc | 4434 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; |
30a970c6 | 4435 | |
586f49dc JB |
4436 | /* Obtain SKU information */ |
4437 | mutex_lock(&dev_priv->dpio_lock); | |
4438 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
4439 | CCK_FUSE_HPLL_FREQ_MASK; | |
4440 | mutex_unlock(&dev_priv->dpio_lock); | |
30a970c6 | 4441 | |
586f49dc | 4442 | return vco_freq[hpll_freq]; |
30a970c6 JB |
4443 | } |
4444 | ||
4445 | /* Adjust CDclk dividers to allow high res or save power if possible */ | |
4446 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
4447 | { | |
4448 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4449 | u32 val, cmd; | |
4450 | ||
d60c4473 ID |
4451 | WARN_ON(valleyview_cur_cdclk(dev_priv) != dev_priv->vlv_cdclk_freq); |
4452 | dev_priv->vlv_cdclk_freq = cdclk; | |
4453 | ||
30a970c6 JB |
4454 | if (cdclk >= 320) /* jump to highest voltage for 400MHz too */ |
4455 | cmd = 2; | |
4456 | else if (cdclk == 266) | |
4457 | cmd = 1; | |
4458 | else | |
4459 | cmd = 0; | |
4460 | ||
4461 | mutex_lock(&dev_priv->rps.hw_lock); | |
4462 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
4463 | val &= ~DSPFREQGUAR_MASK; | |
4464 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
4465 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
4466 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
4467 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
4468 | 50)) { | |
4469 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
4470 | } | |
4471 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4472 | ||
4473 | if (cdclk == 400) { | |
4474 | u32 divider, vco; | |
4475 | ||
4476 | vco = valleyview_get_vco(dev_priv); | |
4477 | divider = ((vco << 1) / cdclk) - 1; | |
4478 | ||
4479 | mutex_lock(&dev_priv->dpio_lock); | |
4480 | /* adjust cdclk divider */ | |
4481 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
4482 | val &= ~0xf; | |
4483 | val |= divider; | |
4484 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
4485 | mutex_unlock(&dev_priv->dpio_lock); | |
4486 | } | |
4487 | ||
4488 | mutex_lock(&dev_priv->dpio_lock); | |
4489 | /* adjust self-refresh exit latency value */ | |
4490 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
4491 | val &= ~0x7f; | |
4492 | ||
4493 | /* | |
4494 | * For high bandwidth configs, we set a higher latency in the bunit | |
4495 | * so that the core display fetch happens in time to avoid underruns. | |
4496 | */ | |
4497 | if (cdclk == 400) | |
4498 | val |= 4500 / 250; /* 4.5 usec */ | |
4499 | else | |
4500 | val |= 3000 / 250; /* 3.0 usec */ | |
4501 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
4502 | mutex_unlock(&dev_priv->dpio_lock); | |
4503 | ||
4504 | /* Since we changed the CDclk, we need to update the GMBUSFREQ too */ | |
4505 | intel_i2c_reset(dev); | |
4506 | } | |
4507 | ||
d60c4473 | 4508 | int valleyview_cur_cdclk(struct drm_i915_private *dev_priv) |
30a970c6 JB |
4509 | { |
4510 | int cur_cdclk, vco; | |
4511 | int divider; | |
4512 | ||
4513 | vco = valleyview_get_vco(dev_priv); | |
4514 | ||
4515 | mutex_lock(&dev_priv->dpio_lock); | |
4516 | divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
4517 | mutex_unlock(&dev_priv->dpio_lock); | |
4518 | ||
4519 | divider &= 0xf; | |
4520 | ||
4521 | cur_cdclk = (vco << 1) / (divider + 1); | |
4522 | ||
4523 | return cur_cdclk; | |
4524 | } | |
4525 | ||
4526 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, | |
4527 | int max_pixclk) | |
4528 | { | |
30a970c6 JB |
4529 | /* |
4530 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
4531 | * 200MHz | |
4532 | * 267MHz | |
4533 | * 320MHz | |
4534 | * 400MHz | |
4535 | * So we check to see whether we're above 90% of the lower bin and | |
4536 | * adjust if needed. | |
4537 | */ | |
4538 | if (max_pixclk > 288000) { | |
4539 | return 400; | |
4540 | } else if (max_pixclk > 240000) { | |
4541 | return 320; | |
4542 | } else | |
4543 | return 266; | |
4544 | /* Looks like the 200MHz CDclk freq doesn't work on some configs */ | |
4545 | } | |
4546 | ||
2f2d7aa1 VS |
4547 | /* compute the max pixel clock for new configuration */ |
4548 | static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv) | |
30a970c6 JB |
4549 | { |
4550 | struct drm_device *dev = dev_priv->dev; | |
4551 | struct intel_crtc *intel_crtc; | |
4552 | int max_pixclk = 0; | |
4553 | ||
d3fcc808 | 4554 | for_each_intel_crtc(dev, intel_crtc) { |
2f2d7aa1 | 4555 | if (intel_crtc->new_enabled) |
30a970c6 | 4556 | max_pixclk = max(max_pixclk, |
2f2d7aa1 | 4557 | intel_crtc->new_config->adjusted_mode.crtc_clock); |
30a970c6 JB |
4558 | } |
4559 | ||
4560 | return max_pixclk; | |
4561 | } | |
4562 | ||
4563 | static void valleyview_modeset_global_pipes(struct drm_device *dev, | |
2f2d7aa1 | 4564 | unsigned *prepare_pipes) |
30a970c6 JB |
4565 | { |
4566 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4567 | struct intel_crtc *intel_crtc; | |
2f2d7aa1 | 4568 | int max_pixclk = intel_mode_max_pixclk(dev_priv); |
30a970c6 | 4569 | |
d60c4473 ID |
4570 | if (valleyview_calc_cdclk(dev_priv, max_pixclk) == |
4571 | dev_priv->vlv_cdclk_freq) | |
30a970c6 JB |
4572 | return; |
4573 | ||
2f2d7aa1 | 4574 | /* disable/enable all currently active pipes while we change cdclk */ |
d3fcc808 | 4575 | for_each_intel_crtc(dev, intel_crtc) |
30a970c6 JB |
4576 | if (intel_crtc->base.enabled) |
4577 | *prepare_pipes |= (1 << intel_crtc->pipe); | |
4578 | } | |
4579 | ||
4580 | static void valleyview_modeset_global_resources(struct drm_device *dev) | |
4581 | { | |
4582 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2f2d7aa1 | 4583 | int max_pixclk = intel_mode_max_pixclk(dev_priv); |
30a970c6 JB |
4584 | int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk); |
4585 | ||
d60c4473 | 4586 | if (req_cdclk != dev_priv->vlv_cdclk_freq) |
30a970c6 | 4587 | valleyview_set_cdclk(dev, req_cdclk); |
77961eb9 | 4588 | modeset_update_crtc_power_domains(dev); |
30a970c6 JB |
4589 | } |
4590 | ||
89b667f8 JB |
4591 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
4592 | { | |
4593 | struct drm_device *dev = crtc->dev; | |
5b18e57c | 4594 | struct drm_i915_private *dev_priv = dev->dev_private; |
89b667f8 JB |
4595 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4596 | struct intel_encoder *encoder; | |
4597 | int pipe = intel_crtc->pipe; | |
5b18e57c | 4598 | int plane = intel_crtc->plane; |
23538ef1 | 4599 | bool is_dsi; |
5b18e57c | 4600 | u32 dspcntr; |
89b667f8 JB |
4601 | |
4602 | WARN_ON(!crtc->enabled); | |
4603 | ||
4604 | if (intel_crtc->active) | |
4605 | return; | |
4606 | ||
bdd4b6a6 DV |
4607 | vlv_prepare_pll(intel_crtc); |
4608 | ||
5b18e57c DV |
4609 | /* Set up the display plane register */ |
4610 | dspcntr = DISPPLANE_GAMMA_ENABLE; | |
4611 | ||
4612 | if (intel_crtc->config.has_dp_encoder) | |
4613 | intel_dp_set_m_n(intel_crtc); | |
4614 | ||
4615 | intel_set_pipe_timings(intel_crtc); | |
4616 | ||
4617 | /* pipesrc and dspsize control the size that is scaled from, | |
4618 | * which should always be the user's requested size. | |
4619 | */ | |
4620 | I915_WRITE(DSPSIZE(plane), | |
4621 | ((intel_crtc->config.pipe_src_h - 1) << 16) | | |
4622 | (intel_crtc->config.pipe_src_w - 1)); | |
4623 | I915_WRITE(DSPPOS(plane), 0); | |
4624 | ||
4625 | i9xx_set_pipeconf(intel_crtc); | |
4626 | ||
4627 | I915_WRITE(DSPCNTR(plane), dspcntr); | |
4628 | POSTING_READ(DSPCNTR(plane)); | |
4629 | ||
4630 | dev_priv->display.update_primary_plane(crtc, crtc->primary->fb, | |
4631 | crtc->x, crtc->y); | |
4632 | ||
89b667f8 | 4633 | intel_crtc->active = true; |
89b667f8 | 4634 | |
4a3436e8 VS |
4635 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); |
4636 | ||
89b667f8 JB |
4637 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4638 | if (encoder->pre_pll_enable) | |
4639 | encoder->pre_pll_enable(encoder); | |
4640 | ||
23538ef1 JN |
4641 | is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI); |
4642 | ||
9d556c99 CML |
4643 | if (!is_dsi) { |
4644 | if (IS_CHERRYVIEW(dev)) | |
4645 | chv_enable_pll(intel_crtc); | |
4646 | else | |
4647 | vlv_enable_pll(intel_crtc); | |
4648 | } | |
89b667f8 JB |
4649 | |
4650 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
4651 | if (encoder->pre_enable) | |
4652 | encoder->pre_enable(encoder); | |
4653 | ||
2dd24552 JB |
4654 | i9xx_pfit_enable(intel_crtc); |
4655 | ||
63cbb074 VS |
4656 | intel_crtc_load_lut(crtc); |
4657 | ||
f37fcc2a | 4658 | intel_update_watermarks(crtc); |
e1fdc473 | 4659 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 4660 | |
5004945f JN |
4661 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4662 | encoder->enable(encoder); | |
9ab0460b VS |
4663 | |
4664 | intel_crtc_enable_planes(crtc); | |
d40d9187 | 4665 | |
56b80e1f VS |
4666 | /* Underruns don't raise interrupts, so check manually. */ |
4667 | i9xx_check_fifo_underruns(dev); | |
89b667f8 JB |
4668 | } |
4669 | ||
f13c2ef3 DV |
4670 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
4671 | { | |
4672 | struct drm_device *dev = crtc->base.dev; | |
4673 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4674 | ||
4675 | I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0); | |
4676 | I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1); | |
4677 | } | |
4678 | ||
0b8765c6 | 4679 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
4680 | { |
4681 | struct drm_device *dev = crtc->dev; | |
5b18e57c | 4682 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 4683 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 4684 | struct intel_encoder *encoder; |
79e53945 | 4685 | int pipe = intel_crtc->pipe; |
5b18e57c DV |
4686 | int plane = intel_crtc->plane; |
4687 | u32 dspcntr; | |
79e53945 | 4688 | |
08a48469 DV |
4689 | WARN_ON(!crtc->enabled); |
4690 | ||
f7abfe8b CW |
4691 | if (intel_crtc->active) |
4692 | return; | |
4693 | ||
f13c2ef3 DV |
4694 | i9xx_set_pll_dividers(intel_crtc); |
4695 | ||
5b18e57c DV |
4696 | /* Set up the display plane register */ |
4697 | dspcntr = DISPPLANE_GAMMA_ENABLE; | |
4698 | ||
4699 | if (pipe == 0) | |
4700 | dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; | |
4701 | else | |
4702 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
4703 | ||
4704 | if (intel_crtc->config.has_dp_encoder) | |
4705 | intel_dp_set_m_n(intel_crtc); | |
4706 | ||
4707 | intel_set_pipe_timings(intel_crtc); | |
4708 | ||
4709 | /* pipesrc and dspsize control the size that is scaled from, | |
4710 | * which should always be the user's requested size. | |
4711 | */ | |
4712 | I915_WRITE(DSPSIZE(plane), | |
4713 | ((intel_crtc->config.pipe_src_h - 1) << 16) | | |
4714 | (intel_crtc->config.pipe_src_w - 1)); | |
4715 | I915_WRITE(DSPPOS(plane), 0); | |
4716 | ||
4717 | i9xx_set_pipeconf(intel_crtc); | |
4718 | ||
4719 | I915_WRITE(DSPCNTR(plane), dspcntr); | |
4720 | POSTING_READ(DSPCNTR(plane)); | |
4721 | ||
4722 | dev_priv->display.update_primary_plane(crtc, crtc->primary->fb, | |
4723 | crtc->x, crtc->y); | |
4724 | ||
f7abfe8b | 4725 | intel_crtc->active = true; |
6b383a7f | 4726 | |
4a3436e8 VS |
4727 | if (!IS_GEN2(dev)) |
4728 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); | |
4729 | ||
9d6d9f19 MK |
4730 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4731 | if (encoder->pre_enable) | |
4732 | encoder->pre_enable(encoder); | |
4733 | ||
f6736a1a DV |
4734 | i9xx_enable_pll(intel_crtc); |
4735 | ||
2dd24552 JB |
4736 | i9xx_pfit_enable(intel_crtc); |
4737 | ||
63cbb074 VS |
4738 | intel_crtc_load_lut(crtc); |
4739 | ||
f37fcc2a | 4740 | intel_update_watermarks(crtc); |
e1fdc473 | 4741 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 4742 | |
fa5c73b1 DV |
4743 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4744 | encoder->enable(encoder); | |
9ab0460b VS |
4745 | |
4746 | intel_crtc_enable_planes(crtc); | |
d40d9187 | 4747 | |
4a3436e8 VS |
4748 | /* |
4749 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
4750 | * So don't enable underrun reporting before at least some planes | |
4751 | * are enabled. | |
4752 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4753 | * but leave the pipe running. | |
4754 | */ | |
4755 | if (IS_GEN2(dev)) | |
4756 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); | |
4757 | ||
56b80e1f VS |
4758 | /* Underruns don't raise interrupts, so check manually. */ |
4759 | i9xx_check_fifo_underruns(dev); | |
0b8765c6 | 4760 | } |
79e53945 | 4761 | |
87476d63 DV |
4762 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
4763 | { | |
4764 | struct drm_device *dev = crtc->base.dev; | |
4765 | struct drm_i915_private *dev_priv = dev->dev_private; | |
87476d63 | 4766 | |
328d8e82 DV |
4767 | if (!crtc->config.gmch_pfit.control) |
4768 | return; | |
87476d63 | 4769 | |
328d8e82 | 4770 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 4771 | |
328d8e82 DV |
4772 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
4773 | I915_READ(PFIT_CONTROL)); | |
4774 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
4775 | } |
4776 | ||
0b8765c6 JB |
4777 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
4778 | { | |
4779 | struct drm_device *dev = crtc->dev; | |
4780 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4781 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4782 | struct intel_encoder *encoder; |
0b8765c6 | 4783 | int pipe = intel_crtc->pipe; |
ef9c3aee | 4784 | |
f7abfe8b CW |
4785 | if (!intel_crtc->active) |
4786 | return; | |
4787 | ||
4a3436e8 VS |
4788 | /* |
4789 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
4790 | * So diasble underrun reporting before all the planes get disabled. | |
4791 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4792 | * but leave the pipe running. | |
4793 | */ | |
4794 | if (IS_GEN2(dev)) | |
4795 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, false); | |
4796 | ||
9ab0460b VS |
4797 | intel_crtc_disable_planes(crtc); |
4798 | ||
ea9d758d DV |
4799 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4800 | encoder->disable(encoder); | |
4801 | ||
6304cd91 VS |
4802 | /* |
4803 | * On gen2 planes are double buffered but the pipe isn't, so we must | |
4804 | * wait for planes to fully turn off before disabling the pipe. | |
4805 | */ | |
4806 | if (IS_GEN2(dev)) | |
4807 | intel_wait_for_vblank(dev, pipe); | |
4808 | ||
b24e7179 | 4809 | intel_disable_pipe(dev_priv, pipe); |
24a1f16d | 4810 | |
87476d63 | 4811 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 4812 | |
89b667f8 JB |
4813 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4814 | if (encoder->post_disable) | |
4815 | encoder->post_disable(encoder); | |
4816 | ||
076ed3b2 CML |
4817 | if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) { |
4818 | if (IS_CHERRYVIEW(dev)) | |
4819 | chv_disable_pll(dev_priv, pipe); | |
4820 | else if (IS_VALLEYVIEW(dev)) | |
4821 | vlv_disable_pll(dev_priv, pipe); | |
4822 | else | |
4823 | i9xx_disable_pll(dev_priv, pipe); | |
4824 | } | |
0b8765c6 | 4825 | |
4a3436e8 VS |
4826 | if (!IS_GEN2(dev)) |
4827 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, false); | |
4828 | ||
f7abfe8b | 4829 | intel_crtc->active = false; |
46ba614c | 4830 | intel_update_watermarks(crtc); |
f37fcc2a | 4831 | |
efa9624e | 4832 | mutex_lock(&dev->struct_mutex); |
6b383a7f | 4833 | intel_update_fbc(dev); |
71b1c373 | 4834 | intel_edp_psr_update(dev); |
efa9624e | 4835 | mutex_unlock(&dev->struct_mutex); |
0b8765c6 JB |
4836 | } |
4837 | ||
ee7b9f93 JB |
4838 | static void i9xx_crtc_off(struct drm_crtc *crtc) |
4839 | { | |
4840 | } | |
4841 | ||
976f8a20 DV |
4842 | static void intel_crtc_update_sarea(struct drm_crtc *crtc, |
4843 | bool enabled) | |
2c07245f ZW |
4844 | { |
4845 | struct drm_device *dev = crtc->dev; | |
4846 | struct drm_i915_master_private *master_priv; | |
4847 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4848 | int pipe = intel_crtc->pipe; | |
79e53945 JB |
4849 | |
4850 | if (!dev->primary->master) | |
4851 | return; | |
4852 | ||
4853 | master_priv = dev->primary->master->driver_priv; | |
4854 | if (!master_priv->sarea_priv) | |
4855 | return; | |
4856 | ||
79e53945 JB |
4857 | switch (pipe) { |
4858 | case 0: | |
4859 | master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; | |
4860 | master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; | |
4861 | break; | |
4862 | case 1: | |
4863 | master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; | |
4864 | master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; | |
4865 | break; | |
4866 | default: | |
9db4a9c7 | 4867 | DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe)); |
79e53945 JB |
4868 | break; |
4869 | } | |
79e53945 JB |
4870 | } |
4871 | ||
976f8a20 DV |
4872 | /** |
4873 | * Sets the power management mode of the pipe and plane. | |
4874 | */ | |
4875 | void intel_crtc_update_dpms(struct drm_crtc *crtc) | |
4876 | { | |
4877 | struct drm_device *dev = crtc->dev; | |
4878 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0e572fe7 | 4879 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
976f8a20 | 4880 | struct intel_encoder *intel_encoder; |
0e572fe7 DV |
4881 | enum intel_display_power_domain domain; |
4882 | unsigned long domains; | |
976f8a20 DV |
4883 | bool enable = false; |
4884 | ||
4885 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) | |
4886 | enable |= intel_encoder->connectors_active; | |
4887 | ||
0e572fe7 DV |
4888 | if (enable) { |
4889 | if (!intel_crtc->active) { | |
4890 | /* | |
4891 | * FIXME: DDI plls and relevant code isn't converted | |
4892 | * yet, so do runtime PM for DPMS only for all other | |
4893 | * platforms for now. | |
4894 | */ | |
4895 | if (!HAS_DDI(dev)) { | |
4896 | domains = get_crtc_power_domains(crtc); | |
4897 | for_each_power_domain(domain, domains) | |
4898 | intel_display_power_get(dev_priv, domain); | |
4899 | intel_crtc->enabled_power_domains = domains; | |
4900 | } | |
4901 | ||
4902 | dev_priv->display.crtc_enable(crtc); | |
4903 | } | |
4904 | } else { | |
4905 | if (intel_crtc->active) { | |
4906 | dev_priv->display.crtc_disable(crtc); | |
4907 | ||
4908 | if (!HAS_DDI(dev)) { | |
4909 | domains = intel_crtc->enabled_power_domains; | |
4910 | for_each_power_domain(domain, domains) | |
4911 | intel_display_power_put(dev_priv, domain); | |
4912 | intel_crtc->enabled_power_domains = 0; | |
4913 | } | |
4914 | } | |
4915 | } | |
976f8a20 DV |
4916 | |
4917 | intel_crtc_update_sarea(crtc, enable); | |
4918 | } | |
4919 | ||
cdd59983 CW |
4920 | static void intel_crtc_disable(struct drm_crtc *crtc) |
4921 | { | |
cdd59983 | 4922 | struct drm_device *dev = crtc->dev; |
976f8a20 | 4923 | struct drm_connector *connector; |
ee7b9f93 | 4924 | struct drm_i915_private *dev_priv = dev->dev_private; |
cdd59983 | 4925 | |
976f8a20 DV |
4926 | /* crtc should still be enabled when we disable it. */ |
4927 | WARN_ON(!crtc->enabled); | |
4928 | ||
4929 | dev_priv->display.crtc_disable(crtc); | |
4930 | intel_crtc_update_sarea(crtc, false); | |
ee7b9f93 JB |
4931 | dev_priv->display.off(crtc); |
4932 | ||
931872fc | 4933 | assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane); |
93ce0ba6 | 4934 | assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe); |
931872fc | 4935 | assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe); |
cdd59983 | 4936 | |
f4510a27 | 4937 | if (crtc->primary->fb) { |
cdd59983 | 4938 | mutex_lock(&dev->struct_mutex); |
f4510a27 | 4939 | intel_unpin_fb_obj(to_intel_framebuffer(crtc->primary->fb)->obj); |
cdd59983 | 4940 | mutex_unlock(&dev->struct_mutex); |
f4510a27 | 4941 | crtc->primary->fb = NULL; |
976f8a20 DV |
4942 | } |
4943 | ||
4944 | /* Update computed state. */ | |
4945 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
4946 | if (!connector->encoder || !connector->encoder->crtc) | |
4947 | continue; | |
4948 | ||
4949 | if (connector->encoder->crtc != crtc) | |
4950 | continue; | |
4951 | ||
4952 | connector->dpms = DRM_MODE_DPMS_OFF; | |
4953 | to_intel_encoder(connector->encoder)->connectors_active = false; | |
cdd59983 CW |
4954 | } |
4955 | } | |
4956 | ||
ea5b213a | 4957 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 4958 | { |
4ef69c7a | 4959 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 4960 | |
ea5b213a CW |
4961 | drm_encoder_cleanup(encoder); |
4962 | kfree(intel_encoder); | |
7e7d76c3 JB |
4963 | } |
4964 | ||
9237329d | 4965 | /* Simple dpms helper for encoders with just one connector, no cloning and only |
5ab432ef DV |
4966 | * one kind of off state. It clamps all !ON modes to fully OFF and changes the |
4967 | * state of the entire output pipe. */ | |
9237329d | 4968 | static void intel_encoder_dpms(struct intel_encoder *encoder, int mode) |
7e7d76c3 | 4969 | { |
5ab432ef DV |
4970 | if (mode == DRM_MODE_DPMS_ON) { |
4971 | encoder->connectors_active = true; | |
4972 | ||
b2cabb0e | 4973 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef DV |
4974 | } else { |
4975 | encoder->connectors_active = false; | |
4976 | ||
b2cabb0e | 4977 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef | 4978 | } |
79e53945 JB |
4979 | } |
4980 | ||
0a91ca29 DV |
4981 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
4982 | * internal consistency). */ | |
b980514c | 4983 | static void intel_connector_check_state(struct intel_connector *connector) |
79e53945 | 4984 | { |
0a91ca29 DV |
4985 | if (connector->get_hw_state(connector)) { |
4986 | struct intel_encoder *encoder = connector->encoder; | |
4987 | struct drm_crtc *crtc; | |
4988 | bool encoder_enabled; | |
4989 | enum pipe pipe; | |
4990 | ||
4991 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
4992 | connector->base.base.id, | |
c23cc417 | 4993 | connector->base.name); |
0a91ca29 DV |
4994 | |
4995 | WARN(connector->base.dpms == DRM_MODE_DPMS_OFF, | |
4996 | "wrong connector dpms state\n"); | |
4997 | WARN(connector->base.encoder != &encoder->base, | |
4998 | "active connector not linked to encoder\n"); | |
4999 | WARN(!encoder->connectors_active, | |
5000 | "encoder->connectors_active not set\n"); | |
5001 | ||
5002 | encoder_enabled = encoder->get_hw_state(encoder, &pipe); | |
5003 | WARN(!encoder_enabled, "encoder not enabled\n"); | |
5004 | if (WARN_ON(!encoder->base.crtc)) | |
5005 | return; | |
5006 | ||
5007 | crtc = encoder->base.crtc; | |
5008 | ||
5009 | WARN(!crtc->enabled, "crtc not enabled\n"); | |
5010 | WARN(!to_intel_crtc(crtc)->active, "crtc not active\n"); | |
5011 | WARN(pipe != to_intel_crtc(crtc)->pipe, | |
5012 | "encoder active on the wrong pipe\n"); | |
5013 | } | |
79e53945 JB |
5014 | } |
5015 | ||
5ab432ef DV |
5016 | /* Even simpler default implementation, if there's really no special case to |
5017 | * consider. */ | |
5018 | void intel_connector_dpms(struct drm_connector *connector, int mode) | |
79e53945 | 5019 | { |
5ab432ef DV |
5020 | /* All the simple cases only support two dpms states. */ |
5021 | if (mode != DRM_MODE_DPMS_ON) | |
5022 | mode = DRM_MODE_DPMS_OFF; | |
d4270e57 | 5023 | |
5ab432ef DV |
5024 | if (mode == connector->dpms) |
5025 | return; | |
5026 | ||
5027 | connector->dpms = mode; | |
5028 | ||
5029 | /* Only need to change hw state when actually enabled */ | |
c9976dcf CW |
5030 | if (connector->encoder) |
5031 | intel_encoder_dpms(to_intel_encoder(connector->encoder), mode); | |
0a91ca29 | 5032 | |
b980514c | 5033 | intel_modeset_check_state(connector->dev); |
79e53945 JB |
5034 | } |
5035 | ||
f0947c37 DV |
5036 | /* Simple connector->get_hw_state implementation for encoders that support only |
5037 | * one connector and no cloning and hence the encoder state determines the state | |
5038 | * of the connector. */ | |
5039 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 5040 | { |
24929352 | 5041 | enum pipe pipe = 0; |
f0947c37 | 5042 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 5043 | |
f0947c37 | 5044 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
5045 | } |
5046 | ||
1857e1da DV |
5047 | static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5048 | struct intel_crtc_config *pipe_config) | |
5049 | { | |
5050 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5051 | struct intel_crtc *pipe_B_crtc = | |
5052 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); | |
5053 | ||
5054 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", | |
5055 | pipe_name(pipe), pipe_config->fdi_lanes); | |
5056 | if (pipe_config->fdi_lanes > 4) { | |
5057 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
5058 | pipe_name(pipe), pipe_config->fdi_lanes); | |
5059 | return false; | |
5060 | } | |
5061 | ||
bafb6553 | 5062 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1857e1da DV |
5063 | if (pipe_config->fdi_lanes > 2) { |
5064 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
5065 | pipe_config->fdi_lanes); | |
5066 | return false; | |
5067 | } else { | |
5068 | return true; | |
5069 | } | |
5070 | } | |
5071 | ||
5072 | if (INTEL_INFO(dev)->num_pipes == 2) | |
5073 | return true; | |
5074 | ||
5075 | /* Ivybridge 3 pipe is really complicated */ | |
5076 | switch (pipe) { | |
5077 | case PIPE_A: | |
5078 | return true; | |
5079 | case PIPE_B: | |
5080 | if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled && | |
5081 | pipe_config->fdi_lanes > 2) { | |
5082 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", | |
5083 | pipe_name(pipe), pipe_config->fdi_lanes); | |
5084 | return false; | |
5085 | } | |
5086 | return true; | |
5087 | case PIPE_C: | |
1e833f40 | 5088 | if (!pipe_has_enabled_pch(pipe_B_crtc) || |
1857e1da DV |
5089 | pipe_B_crtc->config.fdi_lanes <= 2) { |
5090 | if (pipe_config->fdi_lanes > 2) { | |
5091 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", | |
5092 | pipe_name(pipe), pipe_config->fdi_lanes); | |
5093 | return false; | |
5094 | } | |
5095 | } else { | |
5096 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); | |
5097 | return false; | |
5098 | } | |
5099 | return true; | |
5100 | default: | |
5101 | BUG(); | |
5102 | } | |
5103 | } | |
5104 | ||
e29c22c0 DV |
5105 | #define RETRY 1 |
5106 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5107 | struct intel_crtc_config *pipe_config) | |
877d48d5 | 5108 | { |
1857e1da | 5109 | struct drm_device *dev = intel_crtc->base.dev; |
877d48d5 | 5110 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
ff9a6750 | 5111 | int lane, link_bw, fdi_dotclock; |
e29c22c0 | 5112 | bool setup_ok, needs_recompute = false; |
877d48d5 | 5113 | |
e29c22c0 | 5114 | retry: |
877d48d5 DV |
5115 | /* FDI is a binary signal running at ~2.7GHz, encoding |
5116 | * each output octet as 10 bits. The actual frequency | |
5117 | * is stored as a divider into a 100MHz clock, and the | |
5118 | * mode pixel clock is stored in units of 1KHz. | |
5119 | * Hence the bw of each lane in terms of the mode signal | |
5120 | * is: | |
5121 | */ | |
5122 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
5123 | ||
241bfc38 | 5124 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 5125 | |
2bd89a07 | 5126 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
5127 | pipe_config->pipe_bpp); |
5128 | ||
5129 | pipe_config->fdi_lanes = lane; | |
5130 | ||
2bd89a07 | 5131 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 5132 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 5133 | |
e29c22c0 DV |
5134 | setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
5135 | intel_crtc->pipe, pipe_config); | |
5136 | if (!setup_ok && pipe_config->pipe_bpp > 6*3) { | |
5137 | pipe_config->pipe_bpp -= 2*3; | |
5138 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
5139 | pipe_config->pipe_bpp); | |
5140 | needs_recompute = true; | |
5141 | pipe_config->bw_constrained = true; | |
5142 | ||
5143 | goto retry; | |
5144 | } | |
5145 | ||
5146 | if (needs_recompute) | |
5147 | return RETRY; | |
5148 | ||
5149 | return setup_ok ? 0 : -EINVAL; | |
877d48d5 DV |
5150 | } |
5151 | ||
42db64ef PZ |
5152 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
5153 | struct intel_crtc_config *pipe_config) | |
5154 | { | |
d330a953 | 5155 | pipe_config->ips_enabled = i915.enable_ips && |
3c4ca58c | 5156 | hsw_crtc_supports_ips(crtc) && |
b6dfdc9b | 5157 | pipe_config->pipe_bpp <= 24; |
42db64ef PZ |
5158 | } |
5159 | ||
a43f6e0f | 5160 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
e29c22c0 | 5161 | struct intel_crtc_config *pipe_config) |
79e53945 | 5162 | { |
a43f6e0f | 5163 | struct drm_device *dev = crtc->base.dev; |
b8cecdf5 | 5164 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
89749350 | 5165 | |
ad3a4479 | 5166 | /* FIXME should check pixel clock limits on all platforms */ |
cf532bb2 VS |
5167 | if (INTEL_INFO(dev)->gen < 4) { |
5168 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5169 | int clock_limit = | |
5170 | dev_priv->display.get_display_clock_speed(dev); | |
5171 | ||
5172 | /* | |
5173 | * Enable pixel doubling when the dot clock | |
5174 | * is > 90% of the (display) core speed. | |
5175 | * | |
b397c96b VS |
5176 | * GDG double wide on either pipe, |
5177 | * otherwise pipe A only. | |
cf532bb2 | 5178 | */ |
b397c96b | 5179 | if ((crtc->pipe == PIPE_A || IS_I915G(dev)) && |
241bfc38 | 5180 | adjusted_mode->crtc_clock > clock_limit * 9 / 10) { |
ad3a4479 | 5181 | clock_limit *= 2; |
cf532bb2 | 5182 | pipe_config->double_wide = true; |
ad3a4479 VS |
5183 | } |
5184 | ||
241bfc38 | 5185 | if (adjusted_mode->crtc_clock > clock_limit * 9 / 10) |
e29c22c0 | 5186 | return -EINVAL; |
2c07245f | 5187 | } |
89749350 | 5188 | |
1d1d0e27 VS |
5189 | /* |
5190 | * Pipe horizontal size must be even in: | |
5191 | * - DVO ganged mode | |
5192 | * - LVDS dual channel mode | |
5193 | * - Double wide pipe | |
5194 | */ | |
5195 | if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && | |
5196 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) | |
5197 | pipe_config->pipe_src_w &= ~1; | |
5198 | ||
8693a824 DL |
5199 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
5200 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
5201 | */ |
5202 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
5203 | adjusted_mode->hsync_start == adjusted_mode->hdisplay) | |
e29c22c0 | 5204 | return -EINVAL; |
44f46b42 | 5205 | |
bd080ee5 | 5206 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) { |
5d2d38dd | 5207 | pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */ |
bd080ee5 | 5208 | } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) { |
5d2d38dd DV |
5209 | /* only a 8bpc pipe, with 6bpc dither through the panel fitter |
5210 | * for lvds. */ | |
5211 | pipe_config->pipe_bpp = 8*3; | |
5212 | } | |
5213 | ||
f5adf94e | 5214 | if (HAS_IPS(dev)) |
a43f6e0f DV |
5215 | hsw_compute_ips_config(crtc, pipe_config); |
5216 | ||
5217 | /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old | |
5218 | * clock survives for now. */ | |
5219 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
5220 | pipe_config->shared_dpll = crtc->config.shared_dpll; | |
42db64ef | 5221 | |
877d48d5 | 5222 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 5223 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 5224 | |
e29c22c0 | 5225 | return 0; |
79e53945 JB |
5226 | } |
5227 | ||
25eb05fc JB |
5228 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
5229 | { | |
5230 | return 400000; /* FIXME */ | |
5231 | } | |
5232 | ||
e70236a8 JB |
5233 | static int i945_get_display_clock_speed(struct drm_device *dev) |
5234 | { | |
5235 | return 400000; | |
5236 | } | |
79e53945 | 5237 | |
e70236a8 | 5238 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 5239 | { |
e70236a8 JB |
5240 | return 333000; |
5241 | } | |
79e53945 | 5242 | |
e70236a8 JB |
5243 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
5244 | { | |
5245 | return 200000; | |
5246 | } | |
79e53945 | 5247 | |
257a7ffc DV |
5248 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
5249 | { | |
5250 | u16 gcfgc = 0; | |
5251 | ||
5252 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
5253 | ||
5254 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
5255 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
5256 | return 267000; | |
5257 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: | |
5258 | return 333000; | |
5259 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: | |
5260 | return 444000; | |
5261 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: | |
5262 | return 200000; | |
5263 | default: | |
5264 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
5265 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
5266 | return 133000; | |
5267 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: | |
5268 | return 167000; | |
5269 | } | |
5270 | } | |
5271 | ||
e70236a8 JB |
5272 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
5273 | { | |
5274 | u16 gcfgc = 0; | |
79e53945 | 5275 | |
e70236a8 JB |
5276 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
5277 | ||
5278 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
5279 | return 133000; | |
5280 | else { | |
5281 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
5282 | case GC_DISPLAY_CLOCK_333_MHZ: | |
5283 | return 333000; | |
5284 | default: | |
5285 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
5286 | return 190000; | |
79e53945 | 5287 | } |
e70236a8 JB |
5288 | } |
5289 | } | |
5290 | ||
5291 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
5292 | { | |
5293 | return 266000; | |
5294 | } | |
5295 | ||
5296 | static int i855_get_display_clock_speed(struct drm_device *dev) | |
5297 | { | |
5298 | u16 hpllcc = 0; | |
5299 | /* Assume that the hardware is in the high speed state. This | |
5300 | * should be the default. | |
5301 | */ | |
5302 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
5303 | case GC_CLOCK_133_200: | |
5304 | case GC_CLOCK_100_200: | |
5305 | return 200000; | |
5306 | case GC_CLOCK_166_250: | |
5307 | return 250000; | |
5308 | case GC_CLOCK_100_133: | |
79e53945 | 5309 | return 133000; |
e70236a8 | 5310 | } |
79e53945 | 5311 | |
e70236a8 JB |
5312 | /* Shouldn't happen */ |
5313 | return 0; | |
5314 | } | |
79e53945 | 5315 | |
e70236a8 JB |
5316 | static int i830_get_display_clock_speed(struct drm_device *dev) |
5317 | { | |
5318 | return 133000; | |
79e53945 JB |
5319 | } |
5320 | ||
2c07245f | 5321 | static void |
a65851af | 5322 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 5323 | { |
a65851af VS |
5324 | while (*num > DATA_LINK_M_N_MASK || |
5325 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
5326 | *num >>= 1; |
5327 | *den >>= 1; | |
5328 | } | |
5329 | } | |
5330 | ||
a65851af VS |
5331 | static void compute_m_n(unsigned int m, unsigned int n, |
5332 | uint32_t *ret_m, uint32_t *ret_n) | |
5333 | { | |
5334 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
5335 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
5336 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
5337 | } | |
5338 | ||
e69d0bc1 DV |
5339 | void |
5340 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
5341 | int pixel_clock, int link_clock, | |
5342 | struct intel_link_m_n *m_n) | |
2c07245f | 5343 | { |
e69d0bc1 | 5344 | m_n->tu = 64; |
a65851af VS |
5345 | |
5346 | compute_m_n(bits_per_pixel * pixel_clock, | |
5347 | link_clock * nlanes * 8, | |
5348 | &m_n->gmch_m, &m_n->gmch_n); | |
5349 | ||
5350 | compute_m_n(pixel_clock, link_clock, | |
5351 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
5352 | } |
5353 | ||
a7615030 CW |
5354 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
5355 | { | |
d330a953 JN |
5356 | if (i915.panel_use_ssc >= 0) |
5357 | return i915.panel_use_ssc != 0; | |
41aa3448 | 5358 | return dev_priv->vbt.lvds_use_ssc |
435793df | 5359 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
5360 | } |
5361 | ||
c65d77d8 JB |
5362 | static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors) |
5363 | { | |
5364 | struct drm_device *dev = crtc->dev; | |
5365 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5366 | int refclk; | |
5367 | ||
a0c4da24 | 5368 | if (IS_VALLEYVIEW(dev)) { |
9a0ea498 | 5369 | refclk = 100000; |
a0c4da24 | 5370 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
c65d77d8 | 5371 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
e91e941b VS |
5372 | refclk = dev_priv->vbt.lvds_ssc_freq; |
5373 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
c65d77d8 JB |
5374 | } else if (!IS_GEN2(dev)) { |
5375 | refclk = 96000; | |
5376 | } else { | |
5377 | refclk = 48000; | |
5378 | } | |
5379 | ||
5380 | return refclk; | |
5381 | } | |
5382 | ||
7429e9d4 | 5383 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 5384 | { |
7df00d7a | 5385 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 5386 | } |
f47709a9 | 5387 | |
7429e9d4 DV |
5388 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
5389 | { | |
5390 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
5391 | } |
5392 | ||
f47709a9 | 5393 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
a7516a05 JB |
5394 | intel_clock_t *reduced_clock) |
5395 | { | |
f47709a9 | 5396 | struct drm_device *dev = crtc->base.dev; |
a7516a05 JB |
5397 | u32 fp, fp2 = 0; |
5398 | ||
5399 | if (IS_PINEVIEW(dev)) { | |
7429e9d4 | 5400 | fp = pnv_dpll_compute_fp(&crtc->config.dpll); |
a7516a05 | 5401 | if (reduced_clock) |
7429e9d4 | 5402 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 5403 | } else { |
7429e9d4 | 5404 | fp = i9xx_dpll_compute_fp(&crtc->config.dpll); |
a7516a05 | 5405 | if (reduced_clock) |
7429e9d4 | 5406 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
5407 | } |
5408 | ||
8bcc2795 | 5409 | crtc->config.dpll_hw_state.fp0 = fp; |
a7516a05 | 5410 | |
f47709a9 DV |
5411 | crtc->lowfreq_avail = false; |
5412 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && | |
d330a953 | 5413 | reduced_clock && i915.powersave) { |
8bcc2795 | 5414 | crtc->config.dpll_hw_state.fp1 = fp2; |
f47709a9 | 5415 | crtc->lowfreq_avail = true; |
a7516a05 | 5416 | } else { |
8bcc2795 | 5417 | crtc->config.dpll_hw_state.fp1 = fp; |
a7516a05 JB |
5418 | } |
5419 | } | |
5420 | ||
5e69f97f CML |
5421 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
5422 | pipe) | |
89b667f8 JB |
5423 | { |
5424 | u32 reg_val; | |
5425 | ||
5426 | /* | |
5427 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
5428 | * and set it to a reasonable value instead. | |
5429 | */ | |
ab3c759a | 5430 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
5431 | reg_val &= 0xffffff00; |
5432 | reg_val |= 0x00000030; | |
ab3c759a | 5433 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 5434 | |
ab3c759a | 5435 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
5436 | reg_val &= 0x8cffffff; |
5437 | reg_val = 0x8c000000; | |
ab3c759a | 5438 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 5439 | |
ab3c759a | 5440 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 5441 | reg_val &= 0xffffff00; |
ab3c759a | 5442 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 5443 | |
ab3c759a | 5444 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
5445 | reg_val &= 0x00ffffff; |
5446 | reg_val |= 0xb0000000; | |
ab3c759a | 5447 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
5448 | } |
5449 | ||
b551842d DV |
5450 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
5451 | struct intel_link_m_n *m_n) | |
5452 | { | |
5453 | struct drm_device *dev = crtc->base.dev; | |
5454 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5455 | int pipe = crtc->pipe; | |
5456 | ||
e3b95f1e DV |
5457 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
5458 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
5459 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
5460 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
5461 | } |
5462 | ||
5463 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
5464 | struct intel_link_m_n *m_n) | |
5465 | { | |
5466 | struct drm_device *dev = crtc->base.dev; | |
5467 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5468 | int pipe = crtc->pipe; | |
5469 | enum transcoder transcoder = crtc->config.cpu_transcoder; | |
5470 | ||
5471 | if (INTEL_INFO(dev)->gen >= 5) { | |
5472 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
5473 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
5474 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
5475 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
5476 | } else { | |
e3b95f1e DV |
5477 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
5478 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
5479 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
5480 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
5481 | } |
5482 | } | |
5483 | ||
03afc4a2 DV |
5484 | static void intel_dp_set_m_n(struct intel_crtc *crtc) |
5485 | { | |
5486 | if (crtc->config.has_pch_encoder) | |
5487 | intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); | |
5488 | else | |
5489 | intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); | |
5490 | } | |
5491 | ||
f47709a9 | 5492 | static void vlv_update_pll(struct intel_crtc *crtc) |
bdd4b6a6 DV |
5493 | { |
5494 | u32 dpll, dpll_md; | |
5495 | ||
5496 | /* | |
5497 | * Enable DPIO clock input. We should never disable the reference | |
5498 | * clock for pipe B, since VGA hotplug / manual detection depends | |
5499 | * on it. | |
5500 | */ | |
5501 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | | |
5502 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; | |
5503 | /* We should never disable this, set it here for state tracking */ | |
5504 | if (crtc->pipe == PIPE_B) | |
5505 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
5506 | dpll |= DPLL_VCO_ENABLE; | |
5507 | crtc->config.dpll_hw_state.dpll = dpll; | |
5508 | ||
5509 | dpll_md = (crtc->config.pixel_multiplier - 1) | |
5510 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
5511 | crtc->config.dpll_hw_state.dpll_md = dpll_md; | |
5512 | } | |
5513 | ||
5514 | static void vlv_prepare_pll(struct intel_crtc *crtc) | |
a0c4da24 | 5515 | { |
f47709a9 | 5516 | struct drm_device *dev = crtc->base.dev; |
a0c4da24 | 5517 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 5518 | int pipe = crtc->pipe; |
bdd4b6a6 | 5519 | u32 mdiv; |
a0c4da24 | 5520 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 5521 | u32 coreclk, reg_val; |
a0c4da24 | 5522 | |
09153000 DV |
5523 | mutex_lock(&dev_priv->dpio_lock); |
5524 | ||
f47709a9 DV |
5525 | bestn = crtc->config.dpll.n; |
5526 | bestm1 = crtc->config.dpll.m1; | |
5527 | bestm2 = crtc->config.dpll.m2; | |
5528 | bestp1 = crtc->config.dpll.p1; | |
5529 | bestp2 = crtc->config.dpll.p2; | |
a0c4da24 | 5530 | |
89b667f8 JB |
5531 | /* See eDP HDMI DPIO driver vbios notes doc */ |
5532 | ||
5533 | /* PLL B needs special handling */ | |
bdd4b6a6 | 5534 | if (pipe == PIPE_B) |
5e69f97f | 5535 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
5536 | |
5537 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 5538 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
5539 | |
5540 | /* Disable target IRef on PLL */ | |
ab3c759a | 5541 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 5542 | reg_val &= 0x00ffffff; |
ab3c759a | 5543 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
5544 | |
5545 | /* Disable fast lock */ | |
ab3c759a | 5546 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
5547 | |
5548 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
5549 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
5550 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
5551 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 5552 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
5553 | |
5554 | /* | |
5555 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
5556 | * but we don't support that). | |
5557 | * Note: don't use the DAC post divider as it seems unstable. | |
5558 | */ | |
5559 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 5560 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 5561 | |
a0c4da24 | 5562 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 5563 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 5564 | |
89b667f8 | 5565 | /* Set HBR and RBR LPF coefficients */ |
ff9a6750 | 5566 | if (crtc->config.port_clock == 162000 || |
99750bd4 | 5567 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) || |
89b667f8 | 5568 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) |
ab3c759a | 5569 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 5570 | 0x009f0003); |
89b667f8 | 5571 | else |
ab3c759a | 5572 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
5573 | 0x00d0000f); |
5574 | ||
5575 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) || | |
5576 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) { | |
5577 | /* Use SSC source */ | |
bdd4b6a6 | 5578 | if (pipe == PIPE_A) |
ab3c759a | 5579 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5580 | 0x0df40000); |
5581 | else | |
ab3c759a | 5582 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5583 | 0x0df70000); |
5584 | } else { /* HDMI or VGA */ | |
5585 | /* Use bend source */ | |
bdd4b6a6 | 5586 | if (pipe == PIPE_A) |
ab3c759a | 5587 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5588 | 0x0df70000); |
5589 | else | |
ab3c759a | 5590 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5591 | 0x0df40000); |
5592 | } | |
a0c4da24 | 5593 | |
ab3c759a | 5594 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 JB |
5595 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
5596 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) || | |
5597 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP)) | |
5598 | coreclk |= 0x01000000; | |
ab3c759a | 5599 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 5600 | |
ab3c759a | 5601 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
09153000 | 5602 | mutex_unlock(&dev_priv->dpio_lock); |
a0c4da24 JB |
5603 | } |
5604 | ||
9d556c99 CML |
5605 | static void chv_update_pll(struct intel_crtc *crtc) |
5606 | { | |
5607 | struct drm_device *dev = crtc->base.dev; | |
5608 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5609 | int pipe = crtc->pipe; | |
5610 | int dpll_reg = DPLL(crtc->pipe); | |
5611 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
580d3811 | 5612 | u32 loopfilter, intcoeff; |
9d556c99 CML |
5613 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
5614 | int refclk; | |
5615 | ||
a11b0703 VS |
5616 | crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV | |
5617 | DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS | | |
5618 | DPLL_VCO_ENABLE; | |
5619 | if (pipe != PIPE_A) | |
5620 | crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
5621 | ||
5622 | crtc->config.dpll_hw_state.dpll_md = | |
5623 | (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
9d556c99 CML |
5624 | |
5625 | bestn = crtc->config.dpll.n; | |
5626 | bestm2_frac = crtc->config.dpll.m2 & 0x3fffff; | |
5627 | bestm1 = crtc->config.dpll.m1; | |
5628 | bestm2 = crtc->config.dpll.m2 >> 22; | |
5629 | bestp1 = crtc->config.dpll.p1; | |
5630 | bestp2 = crtc->config.dpll.p2; | |
5631 | ||
5632 | /* | |
5633 | * Enable Refclk and SSC | |
5634 | */ | |
a11b0703 VS |
5635 | I915_WRITE(dpll_reg, |
5636 | crtc->config.dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); | |
5637 | ||
5638 | mutex_lock(&dev_priv->dpio_lock); | |
9d556c99 | 5639 | |
9d556c99 CML |
5640 | /* p1 and p2 divider */ |
5641 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
5642 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
5643 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
5644 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
5645 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
5646 | ||
5647 | /* Feedback post-divider - m2 */ | |
5648 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
5649 | ||
5650 | /* Feedback refclk divider - n and m1 */ | |
5651 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
5652 | DPIO_CHV_M1_DIV_BY_2 | | |
5653 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
5654 | ||
5655 | /* M2 fraction division */ | |
5656 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); | |
5657 | ||
5658 | /* M2 fraction division enable */ | |
5659 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), | |
5660 | DPIO_CHV_FRAC_DIV_EN | | |
5661 | (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT)); | |
5662 | ||
5663 | /* Loop filter */ | |
5664 | refclk = i9xx_get_refclk(&crtc->base, 0); | |
5665 | loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT | | |
5666 | 2 << DPIO_CHV_GAIN_CTRL_SHIFT; | |
5667 | if (refclk == 100000) | |
5668 | intcoeff = 11; | |
5669 | else if (refclk == 38400) | |
5670 | intcoeff = 10; | |
5671 | else | |
5672 | intcoeff = 9; | |
5673 | loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT; | |
5674 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); | |
5675 | ||
5676 | /* AFC Recal */ | |
5677 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
5678 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
5679 | DPIO_AFC_RECAL); | |
5680 | ||
5681 | mutex_unlock(&dev_priv->dpio_lock); | |
5682 | } | |
5683 | ||
f47709a9 DV |
5684 | static void i9xx_update_pll(struct intel_crtc *crtc, |
5685 | intel_clock_t *reduced_clock, | |
eb1cbe48 DV |
5686 | int num_connectors) |
5687 | { | |
f47709a9 | 5688 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 5689 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 DV |
5690 | u32 dpll; |
5691 | bool is_sdvo; | |
f47709a9 | 5692 | struct dpll *clock = &crtc->config.dpll; |
eb1cbe48 | 5693 | |
f47709a9 | 5694 | i9xx_update_pll_dividers(crtc, reduced_clock); |
2a8f64ca | 5695 | |
f47709a9 DV |
5696 | is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) || |
5697 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI); | |
eb1cbe48 DV |
5698 | |
5699 | dpll = DPLL_VGA_MODE_DIS; | |
5700 | ||
f47709a9 | 5701 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
5702 | dpll |= DPLLB_MODE_LVDS; |
5703 | else | |
5704 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 5705 | |
ef1b460d | 5706 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
198a037f DV |
5707 | dpll |= (crtc->config.pixel_multiplier - 1) |
5708 | << SDVO_MULTIPLIER_SHIFT_HIRES; | |
eb1cbe48 | 5709 | } |
198a037f DV |
5710 | |
5711 | if (is_sdvo) | |
4a33e48d | 5712 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 5713 | |
f47709a9 | 5714 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) |
4a33e48d | 5715 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
5716 | |
5717 | /* compute bitmask from p1 value */ | |
5718 | if (IS_PINEVIEW(dev)) | |
5719 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
5720 | else { | |
5721 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
5722 | if (IS_G4X(dev) && reduced_clock) | |
5723 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
5724 | } | |
5725 | switch (clock->p2) { | |
5726 | case 5: | |
5727 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
5728 | break; | |
5729 | case 7: | |
5730 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
5731 | break; | |
5732 | case 10: | |
5733 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
5734 | break; | |
5735 | case 14: | |
5736 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
5737 | break; | |
5738 | } | |
5739 | if (INTEL_INFO(dev)->gen >= 4) | |
5740 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
5741 | ||
09ede541 | 5742 | if (crtc->config.sdvo_tv_clock) |
eb1cbe48 | 5743 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
f47709a9 | 5744 | else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
5745 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
5746 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
5747 | else | |
5748 | dpll |= PLL_REF_INPUT_DREFCLK; | |
5749 | ||
5750 | dpll |= DPLL_VCO_ENABLE; | |
8bcc2795 DV |
5751 | crtc->config.dpll_hw_state.dpll = dpll; |
5752 | ||
eb1cbe48 | 5753 | if (INTEL_INFO(dev)->gen >= 4) { |
ef1b460d DV |
5754 | u32 dpll_md = (crtc->config.pixel_multiplier - 1) |
5755 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
8bcc2795 | 5756 | crtc->config.dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
5757 | } |
5758 | } | |
5759 | ||
f47709a9 | 5760 | static void i8xx_update_pll(struct intel_crtc *crtc, |
f47709a9 | 5761 | intel_clock_t *reduced_clock, |
eb1cbe48 DV |
5762 | int num_connectors) |
5763 | { | |
f47709a9 | 5764 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 5765 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 | 5766 | u32 dpll; |
f47709a9 | 5767 | struct dpll *clock = &crtc->config.dpll; |
eb1cbe48 | 5768 | |
f47709a9 | 5769 | i9xx_update_pll_dividers(crtc, reduced_clock); |
2a8f64ca | 5770 | |
eb1cbe48 DV |
5771 | dpll = DPLL_VGA_MODE_DIS; |
5772 | ||
f47709a9 | 5773 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
5774 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
5775 | } else { | |
5776 | if (clock->p1 == 2) | |
5777 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
5778 | else | |
5779 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
5780 | if (clock->p2 == 4) | |
5781 | dpll |= PLL_P2_DIVIDE_BY_4; | |
5782 | } | |
5783 | ||
4a33e48d DV |
5784 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO)) |
5785 | dpll |= DPLL_DVO_2X_MODE; | |
5786 | ||
f47709a9 | 5787 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
5788 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
5789 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
5790 | else | |
5791 | dpll |= PLL_REF_INPUT_DREFCLK; | |
5792 | ||
5793 | dpll |= DPLL_VCO_ENABLE; | |
8bcc2795 | 5794 | crtc->config.dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
5795 | } |
5796 | ||
8a654f3b | 5797 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
5798 | { |
5799 | struct drm_device *dev = intel_crtc->base.dev; | |
5800 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5801 | enum pipe pipe = intel_crtc->pipe; | |
3b117c8f | 5802 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
8a654f3b DV |
5803 | struct drm_display_mode *adjusted_mode = |
5804 | &intel_crtc->config.adjusted_mode; | |
1caea6e9 VS |
5805 | uint32_t crtc_vtotal, crtc_vblank_end; |
5806 | int vsyncshift = 0; | |
4d8a62ea DV |
5807 | |
5808 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
5809 | * the hw state checker will get angry at the mismatch. */ | |
5810 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
5811 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 5812 | |
609aeaca | 5813 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 5814 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
5815 | crtc_vtotal -= 1; |
5816 | crtc_vblank_end -= 1; | |
609aeaca VS |
5817 | |
5818 | if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO)) | |
5819 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; | |
5820 | else | |
5821 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
5822 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
5823 | if (vsyncshift < 0) |
5824 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
5825 | } |
5826 | ||
5827 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 5828 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 5829 | |
fe2b8f9d | 5830 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
5831 | (adjusted_mode->crtc_hdisplay - 1) | |
5832 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 5833 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
5834 | (adjusted_mode->crtc_hblank_start - 1) | |
5835 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 5836 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
5837 | (adjusted_mode->crtc_hsync_start - 1) | |
5838 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
5839 | ||
fe2b8f9d | 5840 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 5841 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 5842 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 5843 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 5844 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 5845 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 5846 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
5847 | (adjusted_mode->crtc_vsync_start - 1) | |
5848 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
5849 | ||
b5e508d4 PZ |
5850 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
5851 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
5852 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
5853 | * bits. */ | |
5854 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
5855 | (pipe == PIPE_B || pipe == PIPE_C)) | |
5856 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
5857 | ||
b0e77b9c PZ |
5858 | /* pipesrc controls the size that is scaled from, which should |
5859 | * always be the user's requested size. | |
5860 | */ | |
5861 | I915_WRITE(PIPESRC(pipe), | |
37327abd VS |
5862 | ((intel_crtc->config.pipe_src_w - 1) << 16) | |
5863 | (intel_crtc->config.pipe_src_h - 1)); | |
b0e77b9c PZ |
5864 | } |
5865 | ||
1bd1bd80 DV |
5866 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5867 | struct intel_crtc_config *pipe_config) | |
5868 | { | |
5869 | struct drm_device *dev = crtc->base.dev; | |
5870 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5871 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; | |
5872 | uint32_t tmp; | |
5873 | ||
5874 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
5875 | pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; | |
5876 | pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
5877 | tmp = I915_READ(HBLANK(cpu_transcoder)); | |
5878 | pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; | |
5879 | pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
5880 | tmp = I915_READ(HSYNC(cpu_transcoder)); | |
5881 | pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; | |
5882 | pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
5883 | ||
5884 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
5885 | pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; | |
5886 | pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
5887 | tmp = I915_READ(VBLANK(cpu_transcoder)); | |
5888 | pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; | |
5889 | pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
5890 | tmp = I915_READ(VSYNC(cpu_transcoder)); | |
5891 | pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; | |
5892 | pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
5893 | ||
5894 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
5895 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; | |
5896 | pipe_config->adjusted_mode.crtc_vtotal += 1; | |
5897 | pipe_config->adjusted_mode.crtc_vblank_end += 1; | |
5898 | } | |
5899 | ||
5900 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
5901 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
5902 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
5903 | ||
5904 | pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h; | |
5905 | pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
5906 | } |
5907 | ||
f6a83288 DV |
5908 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5909 | struct intel_crtc_config *pipe_config) | |
babea61d | 5910 | { |
f6a83288 DV |
5911 | mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay; |
5912 | mode->htotal = pipe_config->adjusted_mode.crtc_htotal; | |
5913 | mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start; | |
5914 | mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end; | |
babea61d | 5915 | |
f6a83288 DV |
5916 | mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay; |
5917 | mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal; | |
5918 | mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start; | |
5919 | mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end; | |
babea61d | 5920 | |
f6a83288 | 5921 | mode->flags = pipe_config->adjusted_mode.flags; |
babea61d | 5922 | |
f6a83288 DV |
5923 | mode->clock = pipe_config->adjusted_mode.crtc_clock; |
5924 | mode->flags |= pipe_config->adjusted_mode.flags; | |
babea61d JB |
5925 | } |
5926 | ||
84b046f3 DV |
5927 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
5928 | { | |
5929 | struct drm_device *dev = intel_crtc->base.dev; | |
5930 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5931 | uint32_t pipeconf; | |
5932 | ||
9f11a9e4 | 5933 | pipeconf = 0; |
84b046f3 | 5934 | |
67c72a12 DV |
5935 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
5936 | I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE) | |
5937 | pipeconf |= PIPECONF_ENABLE; | |
5938 | ||
cf532bb2 VS |
5939 | if (intel_crtc->config.double_wide) |
5940 | pipeconf |= PIPECONF_DOUBLE_WIDE; | |
84b046f3 | 5941 | |
ff9ce46e DV |
5942 | /* only g4x and later have fancy bpc/dither controls */ |
5943 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { | |
ff9ce46e DV |
5944 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
5945 | if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30) | |
5946 | pipeconf |= PIPECONF_DITHER_EN | | |
84b046f3 | 5947 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 5948 | |
ff9ce46e DV |
5949 | switch (intel_crtc->config.pipe_bpp) { |
5950 | case 18: | |
5951 | pipeconf |= PIPECONF_6BPC; | |
5952 | break; | |
5953 | case 24: | |
5954 | pipeconf |= PIPECONF_8BPC; | |
5955 | break; | |
5956 | case 30: | |
5957 | pipeconf |= PIPECONF_10BPC; | |
5958 | break; | |
5959 | default: | |
5960 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
5961 | BUG(); | |
84b046f3 DV |
5962 | } |
5963 | } | |
5964 | ||
5965 | if (HAS_PIPE_CXSR(dev)) { | |
5966 | if (intel_crtc->lowfreq_avail) { | |
5967 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
5968 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
5969 | } else { | |
5970 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
5971 | } |
5972 | } | |
5973 | ||
efc2cfff VS |
5974 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
5975 | if (INTEL_INFO(dev)->gen < 4 || | |
5976 | intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO)) | |
5977 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; | |
5978 | else | |
5979 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
5980 | } else | |
84b046f3 DV |
5981 | pipeconf |= PIPECONF_PROGRESSIVE; |
5982 | ||
9f11a9e4 DV |
5983 | if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range) |
5984 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; | |
9c8e09b7 | 5985 | |
84b046f3 DV |
5986 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
5987 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
5988 | } | |
5989 | ||
f564048e | 5990 | static int i9xx_crtc_mode_set(struct drm_crtc *crtc, |
f564048e | 5991 | int x, int y, |
94352cf9 | 5992 | struct drm_framebuffer *fb) |
79e53945 JB |
5993 | { |
5994 | struct drm_device *dev = crtc->dev; | |
5995 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5996 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
c751ce4f | 5997 | int refclk, num_connectors = 0; |
652c393a | 5998 | intel_clock_t clock, reduced_clock; |
a16af721 | 5999 | bool ok, has_reduced_clock = false; |
e9fd1c02 | 6000 | bool is_lvds = false, is_dsi = false; |
5eddb70b | 6001 | struct intel_encoder *encoder; |
d4906093 | 6002 | const intel_limit_t *limit; |
79e53945 | 6003 | |
6c2b7c12 | 6004 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5eddb70b | 6005 | switch (encoder->type) { |
79e53945 JB |
6006 | case INTEL_OUTPUT_LVDS: |
6007 | is_lvds = true; | |
6008 | break; | |
e9fd1c02 JN |
6009 | case INTEL_OUTPUT_DSI: |
6010 | is_dsi = true; | |
6011 | break; | |
79e53945 | 6012 | } |
43565a06 | 6013 | |
c751ce4f | 6014 | num_connectors++; |
79e53945 JB |
6015 | } |
6016 | ||
f2335330 | 6017 | if (is_dsi) |
5b18e57c | 6018 | return 0; |
f2335330 JN |
6019 | |
6020 | if (!intel_crtc->config.clock_set) { | |
6021 | refclk = i9xx_get_refclk(crtc, num_connectors); | |
79e53945 | 6022 | |
e9fd1c02 JN |
6023 | /* |
6024 | * Returns a set of divisors for the desired target clock with | |
6025 | * the given refclk, or FALSE. The returned values represent | |
6026 | * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + | |
6027 | * 2) / p1 / p2. | |
6028 | */ | |
6029 | limit = intel_limit(crtc, refclk); | |
6030 | ok = dev_priv->display.find_dpll(limit, crtc, | |
6031 | intel_crtc->config.port_clock, | |
6032 | refclk, NULL, &clock); | |
f2335330 | 6033 | if (!ok) { |
e9fd1c02 JN |
6034 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
6035 | return -EINVAL; | |
6036 | } | |
79e53945 | 6037 | |
f2335330 JN |
6038 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
6039 | /* | |
6040 | * Ensure we match the reduced clock's P to the target | |
6041 | * clock. If the clocks don't match, we can't switch | |
6042 | * the display clock by using the FP0/FP1. In such case | |
6043 | * we will disable the LVDS downclock feature. | |
6044 | */ | |
6045 | has_reduced_clock = | |
6046 | dev_priv->display.find_dpll(limit, crtc, | |
6047 | dev_priv->lvds_downclock, | |
6048 | refclk, &clock, | |
6049 | &reduced_clock); | |
6050 | } | |
6051 | /* Compat-code for transition, will disappear. */ | |
f47709a9 DV |
6052 | intel_crtc->config.dpll.n = clock.n; |
6053 | intel_crtc->config.dpll.m1 = clock.m1; | |
6054 | intel_crtc->config.dpll.m2 = clock.m2; | |
6055 | intel_crtc->config.dpll.p1 = clock.p1; | |
6056 | intel_crtc->config.dpll.p2 = clock.p2; | |
6057 | } | |
7026d4ac | 6058 | |
e9fd1c02 | 6059 | if (IS_GEN2(dev)) { |
8a654f3b | 6060 | i8xx_update_pll(intel_crtc, |
2a8f64ca VP |
6061 | has_reduced_clock ? &reduced_clock : NULL, |
6062 | num_connectors); | |
9d556c99 CML |
6063 | } else if (IS_CHERRYVIEW(dev)) { |
6064 | chv_update_pll(intel_crtc); | |
e9fd1c02 | 6065 | } else if (IS_VALLEYVIEW(dev)) { |
f2335330 | 6066 | vlv_update_pll(intel_crtc); |
e9fd1c02 | 6067 | } else { |
f47709a9 | 6068 | i9xx_update_pll(intel_crtc, |
eb1cbe48 | 6069 | has_reduced_clock ? &reduced_clock : NULL, |
eba905b2 | 6070 | num_connectors); |
e9fd1c02 | 6071 | } |
79e53945 | 6072 | |
c8f7a0db | 6073 | return 0; |
f564048e EA |
6074 | } |
6075 | ||
2fa2fe9a DV |
6076 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
6077 | struct intel_crtc_config *pipe_config) | |
6078 | { | |
6079 | struct drm_device *dev = crtc->base.dev; | |
6080 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6081 | uint32_t tmp; | |
6082 | ||
dc9e7dec VS |
6083 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
6084 | return; | |
6085 | ||
2fa2fe9a | 6086 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
6087 | if (!(tmp & PFIT_ENABLE)) |
6088 | return; | |
2fa2fe9a | 6089 | |
06922821 | 6090 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
6091 | if (INTEL_INFO(dev)->gen < 4) { |
6092 | if (crtc->pipe != PIPE_B) | |
6093 | return; | |
2fa2fe9a DV |
6094 | } else { |
6095 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
6096 | return; | |
6097 | } | |
6098 | ||
06922821 | 6099 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a DV |
6100 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
6101 | if (INTEL_INFO(dev)->gen < 5) | |
6102 | pipe_config->gmch_pfit.lvds_border_bits = | |
6103 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; | |
6104 | } | |
6105 | ||
acbec814 JB |
6106 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
6107 | struct intel_crtc_config *pipe_config) | |
6108 | { | |
6109 | struct drm_device *dev = crtc->base.dev; | |
6110 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6111 | int pipe = pipe_config->cpu_transcoder; | |
6112 | intel_clock_t clock; | |
6113 | u32 mdiv; | |
662c6ecb | 6114 | int refclk = 100000; |
acbec814 JB |
6115 | |
6116 | mutex_lock(&dev_priv->dpio_lock); | |
ab3c759a | 6117 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
acbec814 JB |
6118 | mutex_unlock(&dev_priv->dpio_lock); |
6119 | ||
6120 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
6121 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
6122 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
6123 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
6124 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
6125 | ||
f646628b | 6126 | vlv_clock(refclk, &clock); |
acbec814 | 6127 | |
f646628b VS |
6128 | /* clock.dot is the fast clock */ |
6129 | pipe_config->port_clock = clock.dot / 5; | |
acbec814 JB |
6130 | } |
6131 | ||
1ad292b5 JB |
6132 | static void i9xx_get_plane_config(struct intel_crtc *crtc, |
6133 | struct intel_plane_config *plane_config) | |
6134 | { | |
6135 | struct drm_device *dev = crtc->base.dev; | |
6136 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6137 | u32 val, base, offset; | |
6138 | int pipe = crtc->pipe, plane = crtc->plane; | |
6139 | int fourcc, pixel_format; | |
6140 | int aligned_height; | |
6141 | ||
66e514c1 DA |
6142 | crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL); |
6143 | if (!crtc->base.primary->fb) { | |
1ad292b5 JB |
6144 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
6145 | return; | |
6146 | } | |
6147 | ||
6148 | val = I915_READ(DSPCNTR(plane)); | |
6149 | ||
6150 | if (INTEL_INFO(dev)->gen >= 4) | |
6151 | if (val & DISPPLANE_TILED) | |
6152 | plane_config->tiled = true; | |
6153 | ||
6154 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
6155 | fourcc = intel_format_to_fourcc(pixel_format); | |
66e514c1 DA |
6156 | crtc->base.primary->fb->pixel_format = fourcc; |
6157 | crtc->base.primary->fb->bits_per_pixel = | |
1ad292b5 JB |
6158 | drm_format_plane_cpp(fourcc, 0) * 8; |
6159 | ||
6160 | if (INTEL_INFO(dev)->gen >= 4) { | |
6161 | if (plane_config->tiled) | |
6162 | offset = I915_READ(DSPTILEOFF(plane)); | |
6163 | else | |
6164 | offset = I915_READ(DSPLINOFF(plane)); | |
6165 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
6166 | } else { | |
6167 | base = I915_READ(DSPADDR(plane)); | |
6168 | } | |
6169 | plane_config->base = base; | |
6170 | ||
6171 | val = I915_READ(PIPESRC(pipe)); | |
66e514c1 DA |
6172 | crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1; |
6173 | crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
6174 | |
6175 | val = I915_READ(DSPSTRIDE(pipe)); | |
66e514c1 | 6176 | crtc->base.primary->fb->pitches[0] = val & 0xffffff80; |
1ad292b5 | 6177 | |
66e514c1 | 6178 | aligned_height = intel_align_height(dev, crtc->base.primary->fb->height, |
1ad292b5 JB |
6179 | plane_config->tiled); |
6180 | ||
66e514c1 | 6181 | plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] * |
1ad292b5 JB |
6182 | aligned_height, PAGE_SIZE); |
6183 | ||
6184 | DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
66e514c1 DA |
6185 | pipe, plane, crtc->base.primary->fb->width, |
6186 | crtc->base.primary->fb->height, | |
6187 | crtc->base.primary->fb->bits_per_pixel, base, | |
6188 | crtc->base.primary->fb->pitches[0], | |
1ad292b5 JB |
6189 | plane_config->size); |
6190 | ||
6191 | } | |
6192 | ||
70b23a98 VS |
6193 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
6194 | struct intel_crtc_config *pipe_config) | |
6195 | { | |
6196 | struct drm_device *dev = crtc->base.dev; | |
6197 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6198 | int pipe = pipe_config->cpu_transcoder; | |
6199 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
6200 | intel_clock_t clock; | |
6201 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2; | |
6202 | int refclk = 100000; | |
6203 | ||
6204 | mutex_lock(&dev_priv->dpio_lock); | |
6205 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); | |
6206 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
6207 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
6208 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
6209 | mutex_unlock(&dev_priv->dpio_lock); | |
6210 | ||
6211 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
6212 | clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff); | |
6213 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; | |
6214 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
6215 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
6216 | ||
6217 | chv_clock(refclk, &clock); | |
6218 | ||
6219 | /* clock.dot is the fast clock */ | |
6220 | pipe_config->port_clock = clock.dot / 5; | |
6221 | } | |
6222 | ||
0e8ffe1b DV |
6223 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
6224 | struct intel_crtc_config *pipe_config) | |
6225 | { | |
6226 | struct drm_device *dev = crtc->base.dev; | |
6227 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6228 | uint32_t tmp; | |
6229 | ||
b5482bd0 ID |
6230 | if (!intel_display_power_enabled(dev_priv, |
6231 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
6232 | return false; | |
6233 | ||
e143a21c | 6234 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 6235 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 6236 | |
0e8ffe1b DV |
6237 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
6238 | if (!(tmp & PIPECONF_ENABLE)) | |
6239 | return false; | |
6240 | ||
42571aef VS |
6241 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
6242 | switch (tmp & PIPECONF_BPC_MASK) { | |
6243 | case PIPECONF_6BPC: | |
6244 | pipe_config->pipe_bpp = 18; | |
6245 | break; | |
6246 | case PIPECONF_8BPC: | |
6247 | pipe_config->pipe_bpp = 24; | |
6248 | break; | |
6249 | case PIPECONF_10BPC: | |
6250 | pipe_config->pipe_bpp = 30; | |
6251 | break; | |
6252 | default: | |
6253 | break; | |
6254 | } | |
6255 | } | |
6256 | ||
b5a9fa09 DV |
6257 | if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT)) |
6258 | pipe_config->limited_color_range = true; | |
6259 | ||
282740f7 VS |
6260 | if (INTEL_INFO(dev)->gen < 4) |
6261 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
6262 | ||
1bd1bd80 DV |
6263 | intel_get_pipe_timings(crtc, pipe_config); |
6264 | ||
2fa2fe9a DV |
6265 | i9xx_get_pfit_config(crtc, pipe_config); |
6266 | ||
6c49f241 DV |
6267 | if (INTEL_INFO(dev)->gen >= 4) { |
6268 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
6269 | pipe_config->pixel_multiplier = | |
6270 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
6271 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 6272 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
6273 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
6274 | tmp = I915_READ(DPLL(crtc->pipe)); | |
6275 | pipe_config->pixel_multiplier = | |
6276 | ((tmp & SDVO_MULTIPLIER_MASK) | |
6277 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
6278 | } else { | |
6279 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
6280 | * port and will be fixed up in the encoder->get_config | |
6281 | * function. */ | |
6282 | pipe_config->pixel_multiplier = 1; | |
6283 | } | |
8bcc2795 DV |
6284 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
6285 | if (!IS_VALLEYVIEW(dev)) { | |
6286 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); | |
6287 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
6288 | } else { |
6289 | /* Mask out read-only status bits. */ | |
6290 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
6291 | DPLL_PORTC_READY_MASK | | |
6292 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 6293 | } |
6c49f241 | 6294 | |
70b23a98 VS |
6295 | if (IS_CHERRYVIEW(dev)) |
6296 | chv_crtc_clock_get(crtc, pipe_config); | |
6297 | else if (IS_VALLEYVIEW(dev)) | |
acbec814 JB |
6298 | vlv_crtc_clock_get(crtc, pipe_config); |
6299 | else | |
6300 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 6301 | |
0e8ffe1b DV |
6302 | return true; |
6303 | } | |
6304 | ||
dde86e2d | 6305 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 JB |
6306 | { |
6307 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6308 | struct drm_mode_config *mode_config = &dev->mode_config; | |
13d83a67 | 6309 | struct intel_encoder *encoder; |
74cfd7ac | 6310 | u32 val, final; |
13d83a67 | 6311 | bool has_lvds = false; |
199e5d79 | 6312 | bool has_cpu_edp = false; |
199e5d79 | 6313 | bool has_panel = false; |
99eb6a01 KP |
6314 | bool has_ck505 = false; |
6315 | bool can_ssc = false; | |
13d83a67 JB |
6316 | |
6317 | /* We need to take the global config into account */ | |
199e5d79 KP |
6318 | list_for_each_entry(encoder, &mode_config->encoder_list, |
6319 | base.head) { | |
6320 | switch (encoder->type) { | |
6321 | case INTEL_OUTPUT_LVDS: | |
6322 | has_panel = true; | |
6323 | has_lvds = true; | |
6324 | break; | |
6325 | case INTEL_OUTPUT_EDP: | |
6326 | has_panel = true; | |
2de6905f | 6327 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
6328 | has_cpu_edp = true; |
6329 | break; | |
13d83a67 JB |
6330 | } |
6331 | } | |
6332 | ||
99eb6a01 | 6333 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 6334 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
6335 | can_ssc = has_ck505; |
6336 | } else { | |
6337 | has_ck505 = false; | |
6338 | can_ssc = true; | |
6339 | } | |
6340 | ||
2de6905f ID |
6341 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
6342 | has_panel, has_lvds, has_ck505); | |
13d83a67 JB |
6343 | |
6344 | /* Ironlake: try to setup display ref clock before DPLL | |
6345 | * enabling. This is only under driver's control after | |
6346 | * PCH B stepping, previous chipset stepping should be | |
6347 | * ignoring this setting. | |
6348 | */ | |
74cfd7ac CW |
6349 | val = I915_READ(PCH_DREF_CONTROL); |
6350 | ||
6351 | /* As we must carefully and slowly disable/enable each source in turn, | |
6352 | * compute the final state we want first and check if we need to | |
6353 | * make any changes at all. | |
6354 | */ | |
6355 | final = val; | |
6356 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
6357 | if (has_ck505) | |
6358 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
6359 | else | |
6360 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
6361 | ||
6362 | final &= ~DREF_SSC_SOURCE_MASK; | |
6363 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
6364 | final &= ~DREF_SSC1_ENABLE; | |
6365 | ||
6366 | if (has_panel) { | |
6367 | final |= DREF_SSC_SOURCE_ENABLE; | |
6368 | ||
6369 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
6370 | final |= DREF_SSC1_ENABLE; | |
6371 | ||
6372 | if (has_cpu_edp) { | |
6373 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
6374 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
6375 | else | |
6376 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
6377 | } else | |
6378 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
6379 | } else { | |
6380 | final |= DREF_SSC_SOURCE_DISABLE; | |
6381 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
6382 | } | |
6383 | ||
6384 | if (final == val) | |
6385 | return; | |
6386 | ||
13d83a67 | 6387 | /* Always enable nonspread source */ |
74cfd7ac | 6388 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 6389 | |
99eb6a01 | 6390 | if (has_ck505) |
74cfd7ac | 6391 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 6392 | else |
74cfd7ac | 6393 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 6394 | |
199e5d79 | 6395 | if (has_panel) { |
74cfd7ac CW |
6396 | val &= ~DREF_SSC_SOURCE_MASK; |
6397 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 6398 | |
199e5d79 | 6399 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 6400 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 6401 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 6402 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 6403 | } else |
74cfd7ac | 6404 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
6405 | |
6406 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 6407 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
6408 | POSTING_READ(PCH_DREF_CONTROL); |
6409 | udelay(200); | |
6410 | ||
74cfd7ac | 6411 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
6412 | |
6413 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 6414 | if (has_cpu_edp) { |
99eb6a01 | 6415 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 6416 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 6417 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 6418 | } else |
74cfd7ac | 6419 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 6420 | } else |
74cfd7ac | 6421 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 6422 | |
74cfd7ac | 6423 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
6424 | POSTING_READ(PCH_DREF_CONTROL); |
6425 | udelay(200); | |
6426 | } else { | |
6427 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
6428 | ||
74cfd7ac | 6429 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
6430 | |
6431 | /* Turn off CPU output */ | |
74cfd7ac | 6432 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 6433 | |
74cfd7ac | 6434 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
6435 | POSTING_READ(PCH_DREF_CONTROL); |
6436 | udelay(200); | |
6437 | ||
6438 | /* Turn off the SSC source */ | |
74cfd7ac CW |
6439 | val &= ~DREF_SSC_SOURCE_MASK; |
6440 | val |= DREF_SSC_SOURCE_DISABLE; | |
199e5d79 KP |
6441 | |
6442 | /* Turn off SSC1 */ | |
74cfd7ac | 6443 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 | 6444 | |
74cfd7ac | 6445 | I915_WRITE(PCH_DREF_CONTROL, val); |
13d83a67 JB |
6446 | POSTING_READ(PCH_DREF_CONTROL); |
6447 | udelay(200); | |
6448 | } | |
74cfd7ac CW |
6449 | |
6450 | BUG_ON(val != final); | |
13d83a67 JB |
6451 | } |
6452 | ||
f31f2d55 | 6453 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 6454 | { |
f31f2d55 | 6455 | uint32_t tmp; |
dde86e2d | 6456 | |
0ff066a9 PZ |
6457 | tmp = I915_READ(SOUTH_CHICKEN2); |
6458 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
6459 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 6460 | |
0ff066a9 PZ |
6461 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
6462 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
6463 | DRM_ERROR("FDI mPHY reset assert timeout\n"); | |
dde86e2d | 6464 | |
0ff066a9 PZ |
6465 | tmp = I915_READ(SOUTH_CHICKEN2); |
6466 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
6467 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 6468 | |
0ff066a9 PZ |
6469 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
6470 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
6471 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); | |
f31f2d55 PZ |
6472 | } |
6473 | ||
6474 | /* WaMPhyProgramming:hsw */ | |
6475 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
6476 | { | |
6477 | uint32_t tmp; | |
dde86e2d PZ |
6478 | |
6479 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
6480 | tmp &= ~(0xFF << 24); | |
6481 | tmp |= (0x12 << 24); | |
6482 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
6483 | ||
dde86e2d PZ |
6484 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
6485 | tmp |= (1 << 11); | |
6486 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
6487 | ||
6488 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
6489 | tmp |= (1 << 11); | |
6490 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
6491 | ||
dde86e2d PZ |
6492 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
6493 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
6494 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
6495 | ||
6496 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
6497 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
6498 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
6499 | ||
0ff066a9 PZ |
6500 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
6501 | tmp &= ~(7 << 13); | |
6502 | tmp |= (5 << 13); | |
6503 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 6504 | |
0ff066a9 PZ |
6505 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
6506 | tmp &= ~(7 << 13); | |
6507 | tmp |= (5 << 13); | |
6508 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
6509 | |
6510 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
6511 | tmp &= ~0xFF; | |
6512 | tmp |= 0x1C; | |
6513 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
6514 | ||
6515 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
6516 | tmp &= ~0xFF; | |
6517 | tmp |= 0x1C; | |
6518 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
6519 | ||
6520 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
6521 | tmp &= ~(0xFF << 16); | |
6522 | tmp |= (0x1C << 16); | |
6523 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
6524 | ||
6525 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
6526 | tmp &= ~(0xFF << 16); | |
6527 | tmp |= (0x1C << 16); | |
6528 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
6529 | ||
0ff066a9 PZ |
6530 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
6531 | tmp |= (1 << 27); | |
6532 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 6533 | |
0ff066a9 PZ |
6534 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
6535 | tmp |= (1 << 27); | |
6536 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 6537 | |
0ff066a9 PZ |
6538 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
6539 | tmp &= ~(0xF << 28); | |
6540 | tmp |= (4 << 28); | |
6541 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 6542 | |
0ff066a9 PZ |
6543 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
6544 | tmp &= ~(0xF << 28); | |
6545 | tmp |= (4 << 28); | |
6546 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
6547 | } |
6548 | ||
2fa86a1f PZ |
6549 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
6550 | * Programming" based on the parameters passed: | |
6551 | * - Sequence to enable CLKOUT_DP | |
6552 | * - Sequence to enable CLKOUT_DP without spread | |
6553 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
6554 | */ | |
6555 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
6556 | bool with_fdi) | |
f31f2d55 PZ |
6557 | { |
6558 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa86a1f PZ |
6559 | uint32_t reg, tmp; |
6560 | ||
6561 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
6562 | with_spread = true; | |
6563 | if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE && | |
6564 | with_fdi, "LP PCH doesn't have FDI\n")) | |
6565 | with_fdi = false; | |
f31f2d55 PZ |
6566 | |
6567 | mutex_lock(&dev_priv->dpio_lock); | |
6568 | ||
6569 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
6570 | tmp &= ~SBI_SSCCTL_DISABLE; | |
6571 | tmp |= SBI_SSCCTL_PATHALT; | |
6572 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
6573 | ||
6574 | udelay(24); | |
6575 | ||
2fa86a1f PZ |
6576 | if (with_spread) { |
6577 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
6578 | tmp &= ~SBI_SSCCTL_PATHALT; | |
6579 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 6580 | |
2fa86a1f PZ |
6581 | if (with_fdi) { |
6582 | lpt_reset_fdi_mphy(dev_priv); | |
6583 | lpt_program_fdi_mphy(dev_priv); | |
6584 | } | |
6585 | } | |
dde86e2d | 6586 | |
2fa86a1f PZ |
6587 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? |
6588 | SBI_GEN0 : SBI_DBUFF0; | |
6589 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
6590 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
6591 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 DV |
6592 | |
6593 | mutex_unlock(&dev_priv->dpio_lock); | |
dde86e2d PZ |
6594 | } |
6595 | ||
47701c3b PZ |
6596 | /* Sequence to disable CLKOUT_DP */ |
6597 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
6598 | { | |
6599 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6600 | uint32_t reg, tmp; | |
6601 | ||
6602 | mutex_lock(&dev_priv->dpio_lock); | |
6603 | ||
6604 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? | |
6605 | SBI_GEN0 : SBI_DBUFF0; | |
6606 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
6607 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
6608 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
6609 | ||
6610 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
6611 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
6612 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
6613 | tmp |= SBI_SSCCTL_PATHALT; | |
6614 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
6615 | udelay(32); | |
6616 | } | |
6617 | tmp |= SBI_SSCCTL_DISABLE; | |
6618 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
6619 | } | |
6620 | ||
6621 | mutex_unlock(&dev_priv->dpio_lock); | |
6622 | } | |
6623 | ||
bf8fa3d3 PZ |
6624 | static void lpt_init_pch_refclk(struct drm_device *dev) |
6625 | { | |
6626 | struct drm_mode_config *mode_config = &dev->mode_config; | |
6627 | struct intel_encoder *encoder; | |
6628 | bool has_vga = false; | |
6629 | ||
6630 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { | |
6631 | switch (encoder->type) { | |
6632 | case INTEL_OUTPUT_ANALOG: | |
6633 | has_vga = true; | |
6634 | break; | |
6635 | } | |
6636 | } | |
6637 | ||
47701c3b PZ |
6638 | if (has_vga) |
6639 | lpt_enable_clkout_dp(dev, true, true); | |
6640 | else | |
6641 | lpt_disable_clkout_dp(dev); | |
bf8fa3d3 PZ |
6642 | } |
6643 | ||
dde86e2d PZ |
6644 | /* |
6645 | * Initialize reference clocks when the driver loads | |
6646 | */ | |
6647 | void intel_init_pch_refclk(struct drm_device *dev) | |
6648 | { | |
6649 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
6650 | ironlake_init_pch_refclk(dev); | |
6651 | else if (HAS_PCH_LPT(dev)) | |
6652 | lpt_init_pch_refclk(dev); | |
6653 | } | |
6654 | ||
d9d444cb JB |
6655 | static int ironlake_get_refclk(struct drm_crtc *crtc) |
6656 | { | |
6657 | struct drm_device *dev = crtc->dev; | |
6658 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6659 | struct intel_encoder *encoder; | |
d9d444cb JB |
6660 | int num_connectors = 0; |
6661 | bool is_lvds = false; | |
6662 | ||
6c2b7c12 | 6663 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
d9d444cb JB |
6664 | switch (encoder->type) { |
6665 | case INTEL_OUTPUT_LVDS: | |
6666 | is_lvds = true; | |
6667 | break; | |
d9d444cb JB |
6668 | } |
6669 | num_connectors++; | |
6670 | } | |
6671 | ||
6672 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
e91e941b | 6673 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", |
41aa3448 | 6674 | dev_priv->vbt.lvds_ssc_freq); |
e91e941b | 6675 | return dev_priv->vbt.lvds_ssc_freq; |
d9d444cb JB |
6676 | } |
6677 | ||
6678 | return 120000; | |
6679 | } | |
6680 | ||
6ff93609 | 6681 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 6682 | { |
c8203565 | 6683 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
6684 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6685 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
6686 | uint32_t val; |
6687 | ||
78114071 | 6688 | val = 0; |
c8203565 | 6689 | |
965e0c48 | 6690 | switch (intel_crtc->config.pipe_bpp) { |
c8203565 | 6691 | case 18: |
dfd07d72 | 6692 | val |= PIPECONF_6BPC; |
c8203565 PZ |
6693 | break; |
6694 | case 24: | |
dfd07d72 | 6695 | val |= PIPECONF_8BPC; |
c8203565 PZ |
6696 | break; |
6697 | case 30: | |
dfd07d72 | 6698 | val |= PIPECONF_10BPC; |
c8203565 PZ |
6699 | break; |
6700 | case 36: | |
dfd07d72 | 6701 | val |= PIPECONF_12BPC; |
c8203565 PZ |
6702 | break; |
6703 | default: | |
cc769b62 PZ |
6704 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
6705 | BUG(); | |
c8203565 PZ |
6706 | } |
6707 | ||
d8b32247 | 6708 | if (intel_crtc->config.dither) |
c8203565 PZ |
6709 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
6710 | ||
6ff93609 | 6711 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
6712 | val |= PIPECONF_INTERLACED_ILK; |
6713 | else | |
6714 | val |= PIPECONF_PROGRESSIVE; | |
6715 | ||
50f3b016 | 6716 | if (intel_crtc->config.limited_color_range) |
3685a8f3 | 6717 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 6718 | |
c8203565 PZ |
6719 | I915_WRITE(PIPECONF(pipe), val); |
6720 | POSTING_READ(PIPECONF(pipe)); | |
6721 | } | |
6722 | ||
86d3efce VS |
6723 | /* |
6724 | * Set up the pipe CSC unit. | |
6725 | * | |
6726 | * Currently only full range RGB to limited range RGB conversion | |
6727 | * is supported, but eventually this should handle various | |
6728 | * RGB<->YCbCr scenarios as well. | |
6729 | */ | |
50f3b016 | 6730 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
86d3efce VS |
6731 | { |
6732 | struct drm_device *dev = crtc->dev; | |
6733 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6734 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6735 | int pipe = intel_crtc->pipe; | |
6736 | uint16_t coeff = 0x7800; /* 1.0 */ | |
6737 | ||
6738 | /* | |
6739 | * TODO: Check what kind of values actually come out of the pipe | |
6740 | * with these coeff/postoff values and adjust to get the best | |
6741 | * accuracy. Perhaps we even need to take the bpc value into | |
6742 | * consideration. | |
6743 | */ | |
6744 | ||
50f3b016 | 6745 | if (intel_crtc->config.limited_color_range) |
86d3efce VS |
6746 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
6747 | ||
6748 | /* | |
6749 | * GY/GU and RY/RU should be the other way around according | |
6750 | * to BSpec, but reality doesn't agree. Just set them up in | |
6751 | * a way that results in the correct picture. | |
6752 | */ | |
6753 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); | |
6754 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); | |
6755 | ||
6756 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); | |
6757 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); | |
6758 | ||
6759 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); | |
6760 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); | |
6761 | ||
6762 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); | |
6763 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); | |
6764 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); | |
6765 | ||
6766 | if (INTEL_INFO(dev)->gen > 6) { | |
6767 | uint16_t postoff = 0; | |
6768 | ||
50f3b016 | 6769 | if (intel_crtc->config.limited_color_range) |
32cf0cb0 | 6770 | postoff = (16 * (1 << 12) / 255) & 0x1fff; |
86d3efce VS |
6771 | |
6772 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); | |
6773 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); | |
6774 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); | |
6775 | ||
6776 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); | |
6777 | } else { | |
6778 | uint32_t mode = CSC_MODE_YUV_TO_RGB; | |
6779 | ||
50f3b016 | 6780 | if (intel_crtc->config.limited_color_range) |
86d3efce VS |
6781 | mode |= CSC_BLACK_SCREEN_OFFSET; |
6782 | ||
6783 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); | |
6784 | } | |
6785 | } | |
6786 | ||
6ff93609 | 6787 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 6788 | { |
756f85cf PZ |
6789 | struct drm_device *dev = crtc->dev; |
6790 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee2b0b38 | 6791 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 6792 | enum pipe pipe = intel_crtc->pipe; |
3b117c8f | 6793 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
ee2b0b38 PZ |
6794 | uint32_t val; |
6795 | ||
3eff4faa | 6796 | val = 0; |
ee2b0b38 | 6797 | |
756f85cf | 6798 | if (IS_HASWELL(dev) && intel_crtc->config.dither) |
ee2b0b38 PZ |
6799 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
6800 | ||
6ff93609 | 6801 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
6802 | val |= PIPECONF_INTERLACED_ILK; |
6803 | else | |
6804 | val |= PIPECONF_PROGRESSIVE; | |
6805 | ||
702e7a56 PZ |
6806 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
6807 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
3eff4faa DV |
6808 | |
6809 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); | |
6810 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); | |
756f85cf PZ |
6811 | |
6812 | if (IS_BROADWELL(dev)) { | |
6813 | val = 0; | |
6814 | ||
6815 | switch (intel_crtc->config.pipe_bpp) { | |
6816 | case 18: | |
6817 | val |= PIPEMISC_DITHER_6_BPC; | |
6818 | break; | |
6819 | case 24: | |
6820 | val |= PIPEMISC_DITHER_8_BPC; | |
6821 | break; | |
6822 | case 30: | |
6823 | val |= PIPEMISC_DITHER_10_BPC; | |
6824 | break; | |
6825 | case 36: | |
6826 | val |= PIPEMISC_DITHER_12_BPC; | |
6827 | break; | |
6828 | default: | |
6829 | /* Case prevented by pipe_config_set_bpp. */ | |
6830 | BUG(); | |
6831 | } | |
6832 | ||
6833 | if (intel_crtc->config.dither) | |
6834 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; | |
6835 | ||
6836 | I915_WRITE(PIPEMISC(pipe), val); | |
6837 | } | |
ee2b0b38 PZ |
6838 | } |
6839 | ||
6591c6e4 | 6840 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
6591c6e4 PZ |
6841 | intel_clock_t *clock, |
6842 | bool *has_reduced_clock, | |
6843 | intel_clock_t *reduced_clock) | |
6844 | { | |
6845 | struct drm_device *dev = crtc->dev; | |
6846 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6847 | struct intel_encoder *intel_encoder; | |
6848 | int refclk; | |
d4906093 | 6849 | const intel_limit_t *limit; |
a16af721 | 6850 | bool ret, is_lvds = false; |
79e53945 | 6851 | |
6591c6e4 PZ |
6852 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
6853 | switch (intel_encoder->type) { | |
79e53945 JB |
6854 | case INTEL_OUTPUT_LVDS: |
6855 | is_lvds = true; | |
6856 | break; | |
79e53945 JB |
6857 | } |
6858 | } | |
6859 | ||
d9d444cb | 6860 | refclk = ironlake_get_refclk(crtc); |
79e53945 | 6861 | |
d4906093 ML |
6862 | /* |
6863 | * Returns a set of divisors for the desired target clock with the given | |
6864 | * refclk, or FALSE. The returned values represent the clock equation: | |
6865 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
6866 | */ | |
1b894b59 | 6867 | limit = intel_limit(crtc, refclk); |
ff9a6750 DV |
6868 | ret = dev_priv->display.find_dpll(limit, crtc, |
6869 | to_intel_crtc(crtc)->config.port_clock, | |
ee9300bb | 6870 | refclk, NULL, clock); |
6591c6e4 PZ |
6871 | if (!ret) |
6872 | return false; | |
cda4b7d3 | 6873 | |
ddc9003c | 6874 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
cec2f356 SP |
6875 | /* |
6876 | * Ensure we match the reduced clock's P to the target clock. | |
6877 | * If the clocks don't match, we can't switch the display clock | |
6878 | * by using the FP0/FP1. In such case we will disable the LVDS | |
6879 | * downclock feature. | |
6880 | */ | |
ee9300bb DV |
6881 | *has_reduced_clock = |
6882 | dev_priv->display.find_dpll(limit, crtc, | |
6883 | dev_priv->lvds_downclock, | |
6884 | refclk, clock, | |
6885 | reduced_clock); | |
652c393a | 6886 | } |
61e9653f | 6887 | |
6591c6e4 PZ |
6888 | return true; |
6889 | } | |
6890 | ||
d4b1931c PZ |
6891 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
6892 | { | |
6893 | /* | |
6894 | * Account for spread spectrum to avoid | |
6895 | * oversubscribing the link. Max center spread | |
6896 | * is 2.5%; use 5% for safety's sake. | |
6897 | */ | |
6898 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 6899 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
6900 | } |
6901 | ||
7429e9d4 | 6902 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 6903 | { |
7429e9d4 | 6904 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
6905 | } |
6906 | ||
de13a2e3 | 6907 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
7429e9d4 | 6908 | u32 *fp, |
9a7c7890 | 6909 | intel_clock_t *reduced_clock, u32 *fp2) |
79e53945 | 6910 | { |
de13a2e3 | 6911 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
6912 | struct drm_device *dev = crtc->dev; |
6913 | struct drm_i915_private *dev_priv = dev->dev_private; | |
de13a2e3 PZ |
6914 | struct intel_encoder *intel_encoder; |
6915 | uint32_t dpll; | |
6cc5f341 | 6916 | int factor, num_connectors = 0; |
09ede541 | 6917 | bool is_lvds = false, is_sdvo = false; |
79e53945 | 6918 | |
de13a2e3 PZ |
6919 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
6920 | switch (intel_encoder->type) { | |
79e53945 JB |
6921 | case INTEL_OUTPUT_LVDS: |
6922 | is_lvds = true; | |
6923 | break; | |
6924 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 6925 | case INTEL_OUTPUT_HDMI: |
79e53945 | 6926 | is_sdvo = true; |
79e53945 | 6927 | break; |
79e53945 | 6928 | } |
43565a06 | 6929 | |
c751ce4f | 6930 | num_connectors++; |
79e53945 | 6931 | } |
79e53945 | 6932 | |
c1858123 | 6933 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
6934 | factor = 21; |
6935 | if (is_lvds) { | |
6936 | if ((intel_panel_use_ssc(dev_priv) && | |
e91e941b | 6937 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
f0b44056 | 6938 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 6939 | factor = 25; |
09ede541 | 6940 | } else if (intel_crtc->config.sdvo_tv_clock) |
8febb297 | 6941 | factor = 20; |
c1858123 | 6942 | |
7429e9d4 | 6943 | if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor)) |
7d0ac5b7 | 6944 | *fp |= FP_CB_TUNE; |
2c07245f | 6945 | |
9a7c7890 DV |
6946 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
6947 | *fp2 |= FP_CB_TUNE; | |
6948 | ||
5eddb70b | 6949 | dpll = 0; |
2c07245f | 6950 | |
a07d6787 EA |
6951 | if (is_lvds) |
6952 | dpll |= DPLLB_MODE_LVDS; | |
6953 | else | |
6954 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 6955 | |
ef1b460d DV |
6956 | dpll |= (intel_crtc->config.pixel_multiplier - 1) |
6957 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; | |
198a037f DV |
6958 | |
6959 | if (is_sdvo) | |
4a33e48d | 6960 | dpll |= DPLL_SDVO_HIGH_SPEED; |
9566e9af | 6961 | if (intel_crtc->config.has_dp_encoder) |
4a33e48d | 6962 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 6963 | |
a07d6787 | 6964 | /* compute bitmask from p1 value */ |
7429e9d4 | 6965 | dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 6966 | /* also FPA1 */ |
7429e9d4 | 6967 | dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 6968 | |
7429e9d4 | 6969 | switch (intel_crtc->config.dpll.p2) { |
a07d6787 EA |
6970 | case 5: |
6971 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
6972 | break; | |
6973 | case 7: | |
6974 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
6975 | break; | |
6976 | case 10: | |
6977 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
6978 | break; | |
6979 | case 14: | |
6980 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
6981 | break; | |
79e53945 JB |
6982 | } |
6983 | ||
b4c09f3b | 6984 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 6985 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
6986 | else |
6987 | dpll |= PLL_REF_INPUT_DREFCLK; | |
6988 | ||
959e16d6 | 6989 | return dpll | DPLL_VCO_ENABLE; |
de13a2e3 PZ |
6990 | } |
6991 | ||
6992 | static int ironlake_crtc_mode_set(struct drm_crtc *crtc, | |
de13a2e3 PZ |
6993 | int x, int y, |
6994 | struct drm_framebuffer *fb) | |
6995 | { | |
6996 | struct drm_device *dev = crtc->dev; | |
de13a2e3 | 6997 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
de13a2e3 PZ |
6998 | int num_connectors = 0; |
6999 | intel_clock_t clock, reduced_clock; | |
cbbab5bd | 7000 | u32 dpll = 0, fp = 0, fp2 = 0; |
e2f12b07 | 7001 | bool ok, has_reduced_clock = false; |
8b47047b | 7002 | bool is_lvds = false; |
de13a2e3 | 7003 | struct intel_encoder *encoder; |
e2b78267 | 7004 | struct intel_shared_dpll *pll; |
de13a2e3 PZ |
7005 | |
7006 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
7007 | switch (encoder->type) { | |
7008 | case INTEL_OUTPUT_LVDS: | |
7009 | is_lvds = true; | |
7010 | break; | |
de13a2e3 PZ |
7011 | } |
7012 | ||
7013 | num_connectors++; | |
a07d6787 | 7014 | } |
79e53945 | 7015 | |
5dc5298b PZ |
7016 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
7017 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); | |
a07d6787 | 7018 | |
ff9a6750 | 7019 | ok = ironlake_compute_clocks(crtc, &clock, |
de13a2e3 | 7020 | &has_reduced_clock, &reduced_clock); |
ee9300bb | 7021 | if (!ok && !intel_crtc->config.clock_set) { |
de13a2e3 PZ |
7022 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
7023 | return -EINVAL; | |
79e53945 | 7024 | } |
f47709a9 DV |
7025 | /* Compat-code for transition, will disappear. */ |
7026 | if (!intel_crtc->config.clock_set) { | |
7027 | intel_crtc->config.dpll.n = clock.n; | |
7028 | intel_crtc->config.dpll.m1 = clock.m1; | |
7029 | intel_crtc->config.dpll.m2 = clock.m2; | |
7030 | intel_crtc->config.dpll.p1 = clock.p1; | |
7031 | intel_crtc->config.dpll.p2 = clock.p2; | |
7032 | } | |
79e53945 | 7033 | |
5dc5298b | 7034 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
8b47047b | 7035 | if (intel_crtc->config.has_pch_encoder) { |
7429e9d4 | 7036 | fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll); |
cbbab5bd | 7037 | if (has_reduced_clock) |
7429e9d4 | 7038 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
cbbab5bd | 7039 | |
7429e9d4 | 7040 | dpll = ironlake_compute_dpll(intel_crtc, |
cbbab5bd DV |
7041 | &fp, &reduced_clock, |
7042 | has_reduced_clock ? &fp2 : NULL); | |
7043 | ||
959e16d6 | 7044 | intel_crtc->config.dpll_hw_state.dpll = dpll; |
66e985c0 DV |
7045 | intel_crtc->config.dpll_hw_state.fp0 = fp; |
7046 | if (has_reduced_clock) | |
7047 | intel_crtc->config.dpll_hw_state.fp1 = fp2; | |
7048 | else | |
7049 | intel_crtc->config.dpll_hw_state.fp1 = fp; | |
7050 | ||
b89a1d39 | 7051 | pll = intel_get_shared_dpll(intel_crtc); |
ee7b9f93 | 7052 | if (pll == NULL) { |
84f44ce7 | 7053 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
29407aab | 7054 | pipe_name(intel_crtc->pipe)); |
4b645f14 JB |
7055 | return -EINVAL; |
7056 | } | |
ee7b9f93 | 7057 | } else |
e72f9fbf | 7058 | intel_put_shared_dpll(intel_crtc); |
79e53945 | 7059 | |
d330a953 | 7060 | if (is_lvds && has_reduced_clock && i915.powersave) |
bcd644e0 DV |
7061 | intel_crtc->lowfreq_avail = true; |
7062 | else | |
7063 | intel_crtc->lowfreq_avail = false; | |
e2b78267 | 7064 | |
c8f7a0db | 7065 | return 0; |
79e53945 JB |
7066 | } |
7067 | ||
eb14cb74 VS |
7068 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
7069 | struct intel_link_m_n *m_n) | |
7070 | { | |
7071 | struct drm_device *dev = crtc->base.dev; | |
7072 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7073 | enum pipe pipe = crtc->pipe; | |
7074 | ||
7075 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
7076 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
7077 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
7078 | & ~TU_SIZE_MASK; | |
7079 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
7080 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
7081 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
7082 | } | |
7083 | ||
7084 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
7085 | enum transcoder transcoder, | |
7086 | struct intel_link_m_n *m_n) | |
72419203 DV |
7087 | { |
7088 | struct drm_device *dev = crtc->base.dev; | |
7089 | struct drm_i915_private *dev_priv = dev->dev_private; | |
eb14cb74 | 7090 | enum pipe pipe = crtc->pipe; |
72419203 | 7091 | |
eb14cb74 VS |
7092 | if (INTEL_INFO(dev)->gen >= 5) { |
7093 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
7094 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
7095 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
7096 | & ~TU_SIZE_MASK; | |
7097 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
7098 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
7099 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
7100 | } else { | |
7101 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
7102 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
7103 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
7104 | & ~TU_SIZE_MASK; | |
7105 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
7106 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
7107 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
7108 | } | |
7109 | } | |
7110 | ||
7111 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
7112 | struct intel_crtc_config *pipe_config) | |
7113 | { | |
7114 | if (crtc->config.has_pch_encoder) | |
7115 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); | |
7116 | else | |
7117 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
7118 | &pipe_config->dp_m_n); | |
7119 | } | |
72419203 | 7120 | |
eb14cb74 VS |
7121 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
7122 | struct intel_crtc_config *pipe_config) | |
7123 | { | |
7124 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
7125 | &pipe_config->fdi_m_n); | |
72419203 DV |
7126 | } |
7127 | ||
2fa2fe9a DV |
7128 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
7129 | struct intel_crtc_config *pipe_config) | |
7130 | { | |
7131 | struct drm_device *dev = crtc->base.dev; | |
7132 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7133 | uint32_t tmp; | |
7134 | ||
7135 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
7136 | ||
7137 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 7138 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
7139 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
7140 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
7141 | |
7142 | /* We currently do not free assignements of panel fitters on | |
7143 | * ivb/hsw (since we don't use the higher upscaling modes which | |
7144 | * differentiates them) so just WARN about this case for now. */ | |
7145 | if (IS_GEN7(dev)) { | |
7146 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
7147 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
7148 | } | |
2fa2fe9a | 7149 | } |
79e53945 JB |
7150 | } |
7151 | ||
4c6baa59 JB |
7152 | static void ironlake_get_plane_config(struct intel_crtc *crtc, |
7153 | struct intel_plane_config *plane_config) | |
7154 | { | |
7155 | struct drm_device *dev = crtc->base.dev; | |
7156 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7157 | u32 val, base, offset; | |
7158 | int pipe = crtc->pipe, plane = crtc->plane; | |
7159 | int fourcc, pixel_format; | |
7160 | int aligned_height; | |
7161 | ||
66e514c1 DA |
7162 | crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL); |
7163 | if (!crtc->base.primary->fb) { | |
4c6baa59 JB |
7164 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
7165 | return; | |
7166 | } | |
7167 | ||
7168 | val = I915_READ(DSPCNTR(plane)); | |
7169 | ||
7170 | if (INTEL_INFO(dev)->gen >= 4) | |
7171 | if (val & DISPPLANE_TILED) | |
7172 | plane_config->tiled = true; | |
7173 | ||
7174 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
7175 | fourcc = intel_format_to_fourcc(pixel_format); | |
66e514c1 DA |
7176 | crtc->base.primary->fb->pixel_format = fourcc; |
7177 | crtc->base.primary->fb->bits_per_pixel = | |
4c6baa59 JB |
7178 | drm_format_plane_cpp(fourcc, 0) * 8; |
7179 | ||
7180 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
7181 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { | |
7182 | offset = I915_READ(DSPOFFSET(plane)); | |
7183 | } else { | |
7184 | if (plane_config->tiled) | |
7185 | offset = I915_READ(DSPTILEOFF(plane)); | |
7186 | else | |
7187 | offset = I915_READ(DSPLINOFF(plane)); | |
7188 | } | |
7189 | plane_config->base = base; | |
7190 | ||
7191 | val = I915_READ(PIPESRC(pipe)); | |
66e514c1 DA |
7192 | crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1; |
7193 | crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
7194 | |
7195 | val = I915_READ(DSPSTRIDE(pipe)); | |
66e514c1 | 7196 | crtc->base.primary->fb->pitches[0] = val & 0xffffff80; |
4c6baa59 | 7197 | |
66e514c1 | 7198 | aligned_height = intel_align_height(dev, crtc->base.primary->fb->height, |
4c6baa59 JB |
7199 | plane_config->tiled); |
7200 | ||
66e514c1 | 7201 | plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] * |
4c6baa59 JB |
7202 | aligned_height, PAGE_SIZE); |
7203 | ||
7204 | DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
66e514c1 DA |
7205 | pipe, plane, crtc->base.primary->fb->width, |
7206 | crtc->base.primary->fb->height, | |
7207 | crtc->base.primary->fb->bits_per_pixel, base, | |
7208 | crtc->base.primary->fb->pitches[0], | |
4c6baa59 JB |
7209 | plane_config->size); |
7210 | } | |
7211 | ||
0e8ffe1b DV |
7212 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
7213 | struct intel_crtc_config *pipe_config) | |
7214 | { | |
7215 | struct drm_device *dev = crtc->base.dev; | |
7216 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7217 | uint32_t tmp; | |
7218 | ||
e143a21c | 7219 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 7220 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 7221 | |
0e8ffe1b DV |
7222 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
7223 | if (!(tmp & PIPECONF_ENABLE)) | |
7224 | return false; | |
7225 | ||
42571aef VS |
7226 | switch (tmp & PIPECONF_BPC_MASK) { |
7227 | case PIPECONF_6BPC: | |
7228 | pipe_config->pipe_bpp = 18; | |
7229 | break; | |
7230 | case PIPECONF_8BPC: | |
7231 | pipe_config->pipe_bpp = 24; | |
7232 | break; | |
7233 | case PIPECONF_10BPC: | |
7234 | pipe_config->pipe_bpp = 30; | |
7235 | break; | |
7236 | case PIPECONF_12BPC: | |
7237 | pipe_config->pipe_bpp = 36; | |
7238 | break; | |
7239 | default: | |
7240 | break; | |
7241 | } | |
7242 | ||
b5a9fa09 DV |
7243 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
7244 | pipe_config->limited_color_range = true; | |
7245 | ||
ab9412ba | 7246 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 DV |
7247 | struct intel_shared_dpll *pll; |
7248 | ||
88adfff1 DV |
7249 | pipe_config->has_pch_encoder = true; |
7250 | ||
627eb5a3 DV |
7251 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
7252 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
7253 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
7254 | |
7255 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 7256 | |
c0d43d62 | 7257 | if (HAS_PCH_IBX(dev_priv->dev)) { |
d94ab068 DV |
7258 | pipe_config->shared_dpll = |
7259 | (enum intel_dpll_id) crtc->pipe; | |
c0d43d62 DV |
7260 | } else { |
7261 | tmp = I915_READ(PCH_DPLL_SEL); | |
7262 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
7263 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; | |
7264 | else | |
7265 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; | |
7266 | } | |
66e985c0 DV |
7267 | |
7268 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
7269 | ||
7270 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
7271 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
7272 | |
7273 | tmp = pipe_config->dpll_hw_state.dpll; | |
7274 | pipe_config->pixel_multiplier = | |
7275 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
7276 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
7277 | |
7278 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
7279 | } else { |
7280 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
7281 | } |
7282 | ||
1bd1bd80 DV |
7283 | intel_get_pipe_timings(crtc, pipe_config); |
7284 | ||
2fa2fe9a DV |
7285 | ironlake_get_pfit_config(crtc, pipe_config); |
7286 | ||
0e8ffe1b DV |
7287 | return true; |
7288 | } | |
7289 | ||
be256dc7 PZ |
7290 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
7291 | { | |
7292 | struct drm_device *dev = dev_priv->dev; | |
7293 | struct intel_ddi_plls *plls = &dev_priv->ddi_plls; | |
7294 | struct intel_crtc *crtc; | |
be256dc7 | 7295 | |
d3fcc808 | 7296 | for_each_intel_crtc(dev, crtc) |
798183c5 | 7297 | WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
7298 | pipe_name(crtc->pipe)); |
7299 | ||
7300 | WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); | |
7301 | WARN(plls->spll_refcount, "SPLL enabled\n"); | |
7302 | WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n"); | |
7303 | WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n"); | |
7304 | WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); | |
7305 | WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, | |
7306 | "CPU PWM1 enabled\n"); | |
7307 | WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, | |
7308 | "CPU PWM2 enabled\n"); | |
7309 | WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, | |
7310 | "PCH PWM1 enabled\n"); | |
7311 | WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, | |
7312 | "Utility pin enabled\n"); | |
7313 | WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); | |
7314 | ||
9926ada1 PZ |
7315 | /* |
7316 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
7317 | * interrupts remain enabled. We used to check for that, but since it's | |
7318 | * gen-specific and since we only disable LCPLL after we fully disable | |
7319 | * the interrupts, the check below should be enough. | |
7320 | */ | |
7321 | WARN(!dev_priv->pm.irqs_disabled, "IRQs enabled\n"); | |
be256dc7 PZ |
7322 | } |
7323 | ||
3c4c9b81 PZ |
7324 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
7325 | { | |
7326 | struct drm_device *dev = dev_priv->dev; | |
7327 | ||
7328 | if (IS_HASWELL(dev)) { | |
7329 | mutex_lock(&dev_priv->rps.hw_lock); | |
7330 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
7331 | val)) | |
7332 | DRM_ERROR("Failed to disable D_COMP\n"); | |
7333 | mutex_unlock(&dev_priv->rps.hw_lock); | |
7334 | } else { | |
7335 | I915_WRITE(D_COMP, val); | |
7336 | } | |
7337 | POSTING_READ(D_COMP); | |
be256dc7 PZ |
7338 | } |
7339 | ||
7340 | /* | |
7341 | * This function implements pieces of two sequences from BSpec: | |
7342 | * - Sequence for display software to disable LCPLL | |
7343 | * - Sequence for display software to allow package C8+ | |
7344 | * The steps implemented here are just the steps that actually touch the LCPLL | |
7345 | * register. Callers should take care of disabling all the display engine | |
7346 | * functions, doing the mode unset, fixing interrupts, etc. | |
7347 | */ | |
6ff58d53 PZ |
7348 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
7349 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
7350 | { |
7351 | uint32_t val; | |
7352 | ||
7353 | assert_can_disable_lcpll(dev_priv); | |
7354 | ||
7355 | val = I915_READ(LCPLL_CTL); | |
7356 | ||
7357 | if (switch_to_fclk) { | |
7358 | val |= LCPLL_CD_SOURCE_FCLK; | |
7359 | I915_WRITE(LCPLL_CTL, val); | |
7360 | ||
7361 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
7362 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
7363 | DRM_ERROR("Switching to FCLK failed\n"); | |
7364 | ||
7365 | val = I915_READ(LCPLL_CTL); | |
7366 | } | |
7367 | ||
7368 | val |= LCPLL_PLL_DISABLE; | |
7369 | I915_WRITE(LCPLL_CTL, val); | |
7370 | POSTING_READ(LCPLL_CTL); | |
7371 | ||
7372 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) | |
7373 | DRM_ERROR("LCPLL still locked\n"); | |
7374 | ||
7375 | val = I915_READ(D_COMP); | |
7376 | val |= D_COMP_COMP_DISABLE; | |
3c4c9b81 | 7377 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
7378 | ndelay(100); |
7379 | ||
7380 | if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1)) | |
7381 | DRM_ERROR("D_COMP RCOMP still in progress\n"); | |
7382 | ||
7383 | if (allow_power_down) { | |
7384 | val = I915_READ(LCPLL_CTL); | |
7385 | val |= LCPLL_POWER_DOWN_ALLOW; | |
7386 | I915_WRITE(LCPLL_CTL, val); | |
7387 | POSTING_READ(LCPLL_CTL); | |
7388 | } | |
7389 | } | |
7390 | ||
7391 | /* | |
7392 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
7393 | * source. | |
7394 | */ | |
6ff58d53 | 7395 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
7396 | { |
7397 | uint32_t val; | |
a8a8bd54 | 7398 | unsigned long irqflags; |
be256dc7 PZ |
7399 | |
7400 | val = I915_READ(LCPLL_CTL); | |
7401 | ||
7402 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
7403 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
7404 | return; | |
7405 | ||
a8a8bd54 PZ |
7406 | /* |
7407 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
7408 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
7409 | * | |
7410 | * The other problem is that hsw_restore_lcpll() is called as part of | |
7411 | * the runtime PM resume sequence, so we can't just call | |
7412 | * gen6_gt_force_wake_get() because that function calls | |
7413 | * intel_runtime_pm_get(), and we can't change the runtime PM refcount | |
7414 | * while we are on the resume sequence. So to solve this problem we have | |
7415 | * to call special forcewake code that doesn't touch runtime PM and | |
7416 | * doesn't enable the forcewake delayed work. | |
7417 | */ | |
7418 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
7419 | if (dev_priv->uncore.forcewake_count++ == 0) | |
7420 | dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL); | |
7421 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
215733fa | 7422 | |
be256dc7 PZ |
7423 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
7424 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
7425 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 7426 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
7427 | } |
7428 | ||
7429 | val = I915_READ(D_COMP); | |
7430 | val |= D_COMP_COMP_FORCE; | |
7431 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 7432 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
7433 | |
7434 | val = I915_READ(LCPLL_CTL); | |
7435 | val &= ~LCPLL_PLL_DISABLE; | |
7436 | I915_WRITE(LCPLL_CTL, val); | |
7437 | ||
7438 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) | |
7439 | DRM_ERROR("LCPLL not locked yet\n"); | |
7440 | ||
7441 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
7442 | val = I915_READ(LCPLL_CTL); | |
7443 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
7444 | I915_WRITE(LCPLL_CTL, val); | |
7445 | ||
7446 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
7447 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
7448 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
7449 | } | |
215733fa | 7450 | |
a8a8bd54 PZ |
7451 | /* See the big comment above. */ |
7452 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
7453 | if (--dev_priv->uncore.forcewake_count == 0) | |
7454 | dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL); | |
7455 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
be256dc7 PZ |
7456 | } |
7457 | ||
765dab67 PZ |
7458 | /* |
7459 | * Package states C8 and deeper are really deep PC states that can only be | |
7460 | * reached when all the devices on the system allow it, so even if the graphics | |
7461 | * device allows PC8+, it doesn't mean the system will actually get to these | |
7462 | * states. Our driver only allows PC8+ when going into runtime PM. | |
7463 | * | |
7464 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
7465 | * well is disabled and most interrupts are disabled, and these are also | |
7466 | * requirements for runtime PM. When these conditions are met, we manually do | |
7467 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
7468 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
7469 | * hang the machine. | |
7470 | * | |
7471 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
7472 | * the state of some registers, so when we come back from PC8+ we need to | |
7473 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
7474 | * need to take care of the registers kept by RC6. Notice that this happens even | |
7475 | * if we don't put the device in PCI D3 state (which is what currently happens | |
7476 | * because of the runtime PM support). | |
7477 | * | |
7478 | * For more, read "Display Sequences for Package C8" on the hardware | |
7479 | * documentation. | |
7480 | */ | |
a14cb6fc | 7481 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 7482 | { |
c67a470b PZ |
7483 | struct drm_device *dev = dev_priv->dev; |
7484 | uint32_t val; | |
7485 | ||
c67a470b PZ |
7486 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
7487 | ||
c67a470b PZ |
7488 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
7489 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
7490 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
7491 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
7492 | } | |
7493 | ||
7494 | lpt_disable_clkout_dp(dev); | |
c67a470b PZ |
7495 | hsw_disable_lcpll(dev_priv, true, true); |
7496 | } | |
7497 | ||
a14cb6fc | 7498 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b PZ |
7499 | { |
7500 | struct drm_device *dev = dev_priv->dev; | |
7501 | uint32_t val; | |
7502 | ||
c67a470b PZ |
7503 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
7504 | ||
7505 | hsw_restore_lcpll(dev_priv); | |
c67a470b PZ |
7506 | lpt_init_pch_refclk(dev); |
7507 | ||
7508 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { | |
7509 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
7510 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
7511 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
7512 | } | |
7513 | ||
7514 | intel_prepare_ddi(dev); | |
c67a470b PZ |
7515 | } |
7516 | ||
9a952a0d PZ |
7517 | static void snb_modeset_global_resources(struct drm_device *dev) |
7518 | { | |
7519 | modeset_update_crtc_power_domains(dev); | |
7520 | } | |
7521 | ||
4f074129 ID |
7522 | static void haswell_modeset_global_resources(struct drm_device *dev) |
7523 | { | |
da723569 | 7524 | modeset_update_crtc_power_domains(dev); |
d6dd9eb1 DV |
7525 | } |
7526 | ||
09b4ddf9 | 7527 | static int haswell_crtc_mode_set(struct drm_crtc *crtc, |
09b4ddf9 PZ |
7528 | int x, int y, |
7529 | struct drm_framebuffer *fb) | |
7530 | { | |
09b4ddf9 | 7531 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
09b4ddf9 | 7532 | |
566b734a | 7533 | if (!intel_ddi_pll_select(intel_crtc)) |
6441ab5f | 7534 | return -EINVAL; |
566b734a | 7535 | intel_ddi_pll_enable(intel_crtc); |
6441ab5f | 7536 | |
644cef34 DV |
7537 | intel_crtc->lowfreq_avail = false; |
7538 | ||
c8f7a0db | 7539 | return 0; |
79e53945 JB |
7540 | } |
7541 | ||
0e8ffe1b DV |
7542 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
7543 | struct intel_crtc_config *pipe_config) | |
7544 | { | |
7545 | struct drm_device *dev = crtc->base.dev; | |
7546 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa2fe9a | 7547 | enum intel_display_power_domain pfit_domain; |
0e8ffe1b DV |
7548 | uint32_t tmp; |
7549 | ||
b5482bd0 ID |
7550 | if (!intel_display_power_enabled(dev_priv, |
7551 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
7552 | return false; | |
7553 | ||
e143a21c | 7554 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 DV |
7555 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
7556 | ||
eccb140b DV |
7557 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
7558 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
7559 | enum pipe trans_edp_pipe; | |
7560 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
7561 | default: | |
7562 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
7563 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
7564 | case TRANS_DDI_EDP_INPUT_A_ON: | |
7565 | trans_edp_pipe = PIPE_A; | |
7566 | break; | |
7567 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
7568 | trans_edp_pipe = PIPE_B; | |
7569 | break; | |
7570 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
7571 | trans_edp_pipe = PIPE_C; | |
7572 | break; | |
7573 | } | |
7574 | ||
7575 | if (trans_edp_pipe == crtc->pipe) | |
7576 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
7577 | } | |
7578 | ||
da7e29bd | 7579 | if (!intel_display_power_enabled(dev_priv, |
eccb140b | 7580 | POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) |
2bfce950 PZ |
7581 | return false; |
7582 | ||
eccb140b | 7583 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
0e8ffe1b DV |
7584 | if (!(tmp & PIPECONF_ENABLE)) |
7585 | return false; | |
7586 | ||
88adfff1 | 7587 | /* |
f196e6be | 7588 | * Haswell has only FDI/PCH transcoder A. It is which is connected to |
88adfff1 DV |
7589 | * DDI E. So just check whether this pipe is wired to DDI E and whether |
7590 | * the PCH transcoder is on. | |
7591 | */ | |
eccb140b | 7592 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); |
88adfff1 | 7593 | if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) && |
ab9412ba | 7594 | I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { |
88adfff1 DV |
7595 | pipe_config->has_pch_encoder = true; |
7596 | ||
627eb5a3 DV |
7597 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); |
7598 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
7599 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
7600 | |
7601 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
627eb5a3 DV |
7602 | } |
7603 | ||
1bd1bd80 DV |
7604 | intel_get_pipe_timings(crtc, pipe_config); |
7605 | ||
2fa2fe9a | 7606 | pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
da7e29bd | 7607 | if (intel_display_power_enabled(dev_priv, pfit_domain)) |
2fa2fe9a | 7608 | ironlake_get_pfit_config(crtc, pipe_config); |
88adfff1 | 7609 | |
e59150dc JB |
7610 | if (IS_HASWELL(dev)) |
7611 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && | |
7612 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 7613 | |
6c49f241 DV |
7614 | pipe_config->pixel_multiplier = 1; |
7615 | ||
0e8ffe1b DV |
7616 | return true; |
7617 | } | |
7618 | ||
1a91510d JN |
7619 | static struct { |
7620 | int clock; | |
7621 | u32 config; | |
7622 | } hdmi_audio_clock[] = { | |
7623 | { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 }, | |
7624 | { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */ | |
7625 | { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 }, | |
7626 | { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 }, | |
7627 | { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 }, | |
7628 | { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 }, | |
7629 | { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 }, | |
7630 | { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 }, | |
7631 | { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 }, | |
7632 | { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 }, | |
7633 | }; | |
7634 | ||
7635 | /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ | |
7636 | static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode) | |
7637 | { | |
7638 | int i; | |
7639 | ||
7640 | for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) { | |
7641 | if (mode->clock == hdmi_audio_clock[i].clock) | |
7642 | break; | |
7643 | } | |
7644 | ||
7645 | if (i == ARRAY_SIZE(hdmi_audio_clock)) { | |
7646 | DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock); | |
7647 | i = 1; | |
7648 | } | |
7649 | ||
7650 | DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n", | |
7651 | hdmi_audio_clock[i].clock, | |
7652 | hdmi_audio_clock[i].config); | |
7653 | ||
7654 | return hdmi_audio_clock[i].config; | |
7655 | } | |
7656 | ||
3a9627f4 WF |
7657 | static bool intel_eld_uptodate(struct drm_connector *connector, |
7658 | int reg_eldv, uint32_t bits_eldv, | |
7659 | int reg_elda, uint32_t bits_elda, | |
7660 | int reg_edid) | |
7661 | { | |
7662 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7663 | uint8_t *eld = connector->eld; | |
7664 | uint32_t i; | |
7665 | ||
7666 | i = I915_READ(reg_eldv); | |
7667 | i &= bits_eldv; | |
7668 | ||
7669 | if (!eld[0]) | |
7670 | return !i; | |
7671 | ||
7672 | if (!i) | |
7673 | return false; | |
7674 | ||
7675 | i = I915_READ(reg_elda); | |
7676 | i &= ~bits_elda; | |
7677 | I915_WRITE(reg_elda, i); | |
7678 | ||
7679 | for (i = 0; i < eld[2]; i++) | |
7680 | if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) | |
7681 | return false; | |
7682 | ||
7683 | return true; | |
7684 | } | |
7685 | ||
e0dac65e | 7686 | static void g4x_write_eld(struct drm_connector *connector, |
34427052 JN |
7687 | struct drm_crtc *crtc, |
7688 | struct drm_display_mode *mode) | |
e0dac65e WF |
7689 | { |
7690 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7691 | uint8_t *eld = connector->eld; | |
7692 | uint32_t eldv; | |
7693 | uint32_t len; | |
7694 | uint32_t i; | |
7695 | ||
7696 | i = I915_READ(G4X_AUD_VID_DID); | |
7697 | ||
7698 | if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL) | |
7699 | eldv = G4X_ELDV_DEVCL_DEVBLC; | |
7700 | else | |
7701 | eldv = G4X_ELDV_DEVCTG; | |
7702 | ||
3a9627f4 WF |
7703 | if (intel_eld_uptodate(connector, |
7704 | G4X_AUD_CNTL_ST, eldv, | |
7705 | G4X_AUD_CNTL_ST, G4X_ELD_ADDR, | |
7706 | G4X_HDMIW_HDMIEDID)) | |
7707 | return; | |
7708 | ||
e0dac65e WF |
7709 | i = I915_READ(G4X_AUD_CNTL_ST); |
7710 | i &= ~(eldv | G4X_ELD_ADDR); | |
7711 | len = (i >> 9) & 0x1f; /* ELD buffer size */ | |
7712 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
7713 | ||
7714 | if (!eld[0]) | |
7715 | return; | |
7716 | ||
7717 | len = min_t(uint8_t, eld[2], len); | |
7718 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
7719 | for (i = 0; i < len; i++) | |
7720 | I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); | |
7721 | ||
7722 | i = I915_READ(G4X_AUD_CNTL_ST); | |
7723 | i |= eldv; | |
7724 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
7725 | } | |
7726 | ||
83358c85 | 7727 | static void haswell_write_eld(struct drm_connector *connector, |
34427052 JN |
7728 | struct drm_crtc *crtc, |
7729 | struct drm_display_mode *mode) | |
83358c85 WX |
7730 | { |
7731 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7732 | uint8_t *eld = connector->eld; | |
83358c85 WX |
7733 | uint32_t eldv; |
7734 | uint32_t i; | |
7735 | int len; | |
7736 | int pipe = to_intel_crtc(crtc)->pipe; | |
7737 | int tmp; | |
7738 | ||
7739 | int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe); | |
7740 | int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe); | |
7741 | int aud_config = HSW_AUD_CFG(pipe); | |
7742 | int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD; | |
7743 | ||
83358c85 WX |
7744 | /* Audio output enable */ |
7745 | DRM_DEBUG_DRIVER("HDMI audio: enable codec\n"); | |
7746 | tmp = I915_READ(aud_cntrl_st2); | |
7747 | tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4)); | |
7748 | I915_WRITE(aud_cntrl_st2, tmp); | |
c7905792 | 7749 | POSTING_READ(aud_cntrl_st2); |
83358c85 | 7750 | |
c7905792 | 7751 | assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe); |
83358c85 WX |
7752 | |
7753 | /* Set ELD valid state */ | |
7754 | tmp = I915_READ(aud_cntrl_st2); | |
7e7cb34f | 7755 | DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp); |
83358c85 WX |
7756 | tmp |= (AUDIO_ELD_VALID_A << (pipe * 4)); |
7757 | I915_WRITE(aud_cntrl_st2, tmp); | |
7758 | tmp = I915_READ(aud_cntrl_st2); | |
7e7cb34f | 7759 | DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp); |
83358c85 WX |
7760 | |
7761 | /* Enable HDMI mode */ | |
7762 | tmp = I915_READ(aud_config); | |
7e7cb34f | 7763 | DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp); |
83358c85 WX |
7764 | /* clear N_programing_enable and N_value_index */ |
7765 | tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE); | |
7766 | I915_WRITE(aud_config, tmp); | |
7767 | ||
7768 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); | |
7769 | ||
7770 | eldv = AUDIO_ELD_VALID_A << (pipe * 4); | |
7771 | ||
7772 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { | |
7773 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); | |
7774 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ | |
7775 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ | |
1a91510d JN |
7776 | } else { |
7777 | I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode)); | |
7778 | } | |
83358c85 WX |
7779 | |
7780 | if (intel_eld_uptodate(connector, | |
7781 | aud_cntrl_st2, eldv, | |
7782 | aud_cntl_st, IBX_ELD_ADDRESS, | |
7783 | hdmiw_hdmiedid)) | |
7784 | return; | |
7785 | ||
7786 | i = I915_READ(aud_cntrl_st2); | |
7787 | i &= ~eldv; | |
7788 | I915_WRITE(aud_cntrl_st2, i); | |
7789 | ||
7790 | if (!eld[0]) | |
7791 | return; | |
7792 | ||
7793 | i = I915_READ(aud_cntl_st); | |
7794 | i &= ~IBX_ELD_ADDRESS; | |
7795 | I915_WRITE(aud_cntl_st, i); | |
7796 | i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */ | |
7797 | DRM_DEBUG_DRIVER("port num:%d\n", i); | |
7798 | ||
7799 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ | |
7800 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
7801 | for (i = 0; i < len; i++) | |
7802 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); | |
7803 | ||
7804 | i = I915_READ(aud_cntrl_st2); | |
7805 | i |= eldv; | |
7806 | I915_WRITE(aud_cntrl_st2, i); | |
7807 | ||
7808 | } | |
7809 | ||
e0dac65e | 7810 | static void ironlake_write_eld(struct drm_connector *connector, |
34427052 JN |
7811 | struct drm_crtc *crtc, |
7812 | struct drm_display_mode *mode) | |
e0dac65e WF |
7813 | { |
7814 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7815 | uint8_t *eld = connector->eld; | |
7816 | uint32_t eldv; | |
7817 | uint32_t i; | |
7818 | int len; | |
7819 | int hdmiw_hdmiedid; | |
b6daa025 | 7820 | int aud_config; |
e0dac65e WF |
7821 | int aud_cntl_st; |
7822 | int aud_cntrl_st2; | |
9b138a83 | 7823 | int pipe = to_intel_crtc(crtc)->pipe; |
e0dac65e | 7824 | |
b3f33cbf | 7825 | if (HAS_PCH_IBX(connector->dev)) { |
9b138a83 WX |
7826 | hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); |
7827 | aud_config = IBX_AUD_CFG(pipe); | |
7828 | aud_cntl_st = IBX_AUD_CNTL_ST(pipe); | |
1202b4c6 | 7829 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; |
9ca2fe73 ML |
7830 | } else if (IS_VALLEYVIEW(connector->dev)) { |
7831 | hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe); | |
7832 | aud_config = VLV_AUD_CFG(pipe); | |
7833 | aud_cntl_st = VLV_AUD_CNTL_ST(pipe); | |
7834 | aud_cntrl_st2 = VLV_AUD_CNTL_ST2; | |
e0dac65e | 7835 | } else { |
9b138a83 WX |
7836 | hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); |
7837 | aud_config = CPT_AUD_CFG(pipe); | |
7838 | aud_cntl_st = CPT_AUD_CNTL_ST(pipe); | |
1202b4c6 | 7839 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; |
e0dac65e WF |
7840 | } |
7841 | ||
9b138a83 | 7842 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); |
e0dac65e | 7843 | |
9ca2fe73 ML |
7844 | if (IS_VALLEYVIEW(connector->dev)) { |
7845 | struct intel_encoder *intel_encoder; | |
7846 | struct intel_digital_port *intel_dig_port; | |
7847 | ||
7848 | intel_encoder = intel_attached_encoder(connector); | |
7849 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
7850 | i = intel_dig_port->port; | |
7851 | } else { | |
7852 | i = I915_READ(aud_cntl_st); | |
7853 | i = (i >> 29) & DIP_PORT_SEL_MASK; | |
7854 | /* DIP_Port_Select, 0x1 = PortB */ | |
7855 | } | |
7856 | ||
e0dac65e WF |
7857 | if (!i) { |
7858 | DRM_DEBUG_DRIVER("Audio directed to unknown port\n"); | |
7859 | /* operate blindly on all ports */ | |
1202b4c6 WF |
7860 | eldv = IBX_ELD_VALIDB; |
7861 | eldv |= IBX_ELD_VALIDB << 4; | |
7862 | eldv |= IBX_ELD_VALIDB << 8; | |
e0dac65e | 7863 | } else { |
2582a850 | 7864 | DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i)); |
1202b4c6 | 7865 | eldv = IBX_ELD_VALIDB << ((i - 1) * 4); |
e0dac65e WF |
7866 | } |
7867 | ||
3a9627f4 WF |
7868 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
7869 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); | |
7870 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ | |
b6daa025 | 7871 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ |
1a91510d JN |
7872 | } else { |
7873 | I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode)); | |
7874 | } | |
e0dac65e | 7875 | |
3a9627f4 WF |
7876 | if (intel_eld_uptodate(connector, |
7877 | aud_cntrl_st2, eldv, | |
7878 | aud_cntl_st, IBX_ELD_ADDRESS, | |
7879 | hdmiw_hdmiedid)) | |
7880 | return; | |
7881 | ||
e0dac65e WF |
7882 | i = I915_READ(aud_cntrl_st2); |
7883 | i &= ~eldv; | |
7884 | I915_WRITE(aud_cntrl_st2, i); | |
7885 | ||
7886 | if (!eld[0]) | |
7887 | return; | |
7888 | ||
e0dac65e | 7889 | i = I915_READ(aud_cntl_st); |
1202b4c6 | 7890 | i &= ~IBX_ELD_ADDRESS; |
e0dac65e WF |
7891 | I915_WRITE(aud_cntl_st, i); |
7892 | ||
7893 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ | |
7894 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
7895 | for (i = 0; i < len; i++) | |
7896 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); | |
7897 | ||
7898 | i = I915_READ(aud_cntrl_st2); | |
7899 | i |= eldv; | |
7900 | I915_WRITE(aud_cntrl_st2, i); | |
7901 | } | |
7902 | ||
7903 | void intel_write_eld(struct drm_encoder *encoder, | |
7904 | struct drm_display_mode *mode) | |
7905 | { | |
7906 | struct drm_crtc *crtc = encoder->crtc; | |
7907 | struct drm_connector *connector; | |
7908 | struct drm_device *dev = encoder->dev; | |
7909 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7910 | ||
7911 | connector = drm_select_eld(encoder, mode); | |
7912 | if (!connector) | |
7913 | return; | |
7914 | ||
7915 | DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", | |
7916 | connector->base.id, | |
c23cc417 | 7917 | connector->name, |
e0dac65e | 7918 | connector->encoder->base.id, |
8e329a03 | 7919 | connector->encoder->name); |
e0dac65e WF |
7920 | |
7921 | connector->eld[6] = drm_av_sync_delay(connector, mode) / 2; | |
7922 | ||
7923 | if (dev_priv->display.write_eld) | |
34427052 | 7924 | dev_priv->display.write_eld(connector, crtc, mode); |
e0dac65e WF |
7925 | } |
7926 | ||
560b85bb CW |
7927 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
7928 | { | |
7929 | struct drm_device *dev = crtc->dev; | |
7930 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7931 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4b0e333e | 7932 | uint32_t cntl; |
560b85bb | 7933 | |
4b0e333e | 7934 | if (base != intel_crtc->cursor_base) { |
560b85bb CW |
7935 | /* On these chipsets we can only modify the base whilst |
7936 | * the cursor is disabled. | |
7937 | */ | |
4b0e333e CW |
7938 | if (intel_crtc->cursor_cntl) { |
7939 | I915_WRITE(_CURACNTR, 0); | |
7940 | POSTING_READ(_CURACNTR); | |
7941 | intel_crtc->cursor_cntl = 0; | |
7942 | } | |
7943 | ||
9db4a9c7 | 7944 | I915_WRITE(_CURABASE, base); |
4b0e333e CW |
7945 | POSTING_READ(_CURABASE); |
7946 | } | |
560b85bb | 7947 | |
4b0e333e CW |
7948 | /* XXX width must be 64, stride 256 => 0x00 << 28 */ |
7949 | cntl = 0; | |
7950 | if (base) | |
7951 | cntl = (CURSOR_ENABLE | | |
560b85bb | 7952 | CURSOR_GAMMA_ENABLE | |
4b0e333e CW |
7953 | CURSOR_FORMAT_ARGB); |
7954 | if (intel_crtc->cursor_cntl != cntl) { | |
7955 | I915_WRITE(_CURACNTR, cntl); | |
7956 | POSTING_READ(_CURACNTR); | |
7957 | intel_crtc->cursor_cntl = cntl; | |
7958 | } | |
560b85bb CW |
7959 | } |
7960 | ||
7961 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) | |
7962 | { | |
7963 | struct drm_device *dev = crtc->dev; | |
7964 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7965 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7966 | int pipe = intel_crtc->pipe; | |
4b0e333e | 7967 | uint32_t cntl; |
4726e0b0 | 7968 | |
4b0e333e CW |
7969 | cntl = 0; |
7970 | if (base) { | |
7971 | cntl = MCURSOR_GAMMA_ENABLE; | |
7972 | switch (intel_crtc->cursor_width) { | |
4726e0b0 SK |
7973 | case 64: |
7974 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
7975 | break; | |
7976 | case 128: | |
7977 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
7978 | break; | |
7979 | case 256: | |
7980 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
7981 | break; | |
7982 | default: | |
7983 | WARN_ON(1); | |
7984 | return; | |
560b85bb | 7985 | } |
4b0e333e CW |
7986 | cntl |= pipe << 28; /* Connect to correct pipe */ |
7987 | } | |
7988 | if (intel_crtc->cursor_cntl != cntl) { | |
9db4a9c7 | 7989 | I915_WRITE(CURCNTR(pipe), cntl); |
4b0e333e CW |
7990 | POSTING_READ(CURCNTR(pipe)); |
7991 | intel_crtc->cursor_cntl = cntl; | |
560b85bb | 7992 | } |
4b0e333e | 7993 | |
560b85bb | 7994 | /* and commit changes on next vblank */ |
9db4a9c7 | 7995 | I915_WRITE(CURBASE(pipe), base); |
b2ea8ef5 | 7996 | POSTING_READ(CURBASE(pipe)); |
560b85bb CW |
7997 | } |
7998 | ||
65a21cd6 JB |
7999 | static void ivb_update_cursor(struct drm_crtc *crtc, u32 base) |
8000 | { | |
8001 | struct drm_device *dev = crtc->dev; | |
8002 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8003 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8004 | int pipe = intel_crtc->pipe; | |
4b0e333e CW |
8005 | uint32_t cntl; |
8006 | ||
8007 | cntl = 0; | |
8008 | if (base) { | |
8009 | cntl = MCURSOR_GAMMA_ENABLE; | |
8010 | switch (intel_crtc->cursor_width) { | |
4726e0b0 SK |
8011 | case 64: |
8012 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
8013 | break; | |
8014 | case 128: | |
8015 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
8016 | break; | |
8017 | case 256: | |
8018 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
8019 | break; | |
8020 | default: | |
8021 | WARN_ON(1); | |
8022 | return; | |
65a21cd6 | 8023 | } |
4b0e333e CW |
8024 | } |
8025 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
8026 | cntl |= CURSOR_PIPE_CSC_ENABLE; | |
65a21cd6 | 8027 | |
4b0e333e CW |
8028 | if (intel_crtc->cursor_cntl != cntl) { |
8029 | I915_WRITE(CURCNTR(pipe), cntl); | |
8030 | POSTING_READ(CURCNTR(pipe)); | |
8031 | intel_crtc->cursor_cntl = cntl; | |
65a21cd6 | 8032 | } |
4b0e333e | 8033 | |
65a21cd6 | 8034 | /* and commit changes on next vblank */ |
5efb3e28 VS |
8035 | I915_WRITE(CURBASE(pipe), base); |
8036 | POSTING_READ(CURBASE(pipe)); | |
65a21cd6 JB |
8037 | } |
8038 | ||
cda4b7d3 | 8039 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f CW |
8040 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
8041 | bool on) | |
cda4b7d3 CW |
8042 | { |
8043 | struct drm_device *dev = crtc->dev; | |
8044 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8045 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8046 | int pipe = intel_crtc->pipe; | |
8047 | int x = intel_crtc->cursor_x; | |
8048 | int y = intel_crtc->cursor_y; | |
d6e4db15 | 8049 | u32 base = 0, pos = 0; |
cda4b7d3 | 8050 | |
d6e4db15 | 8051 | if (on) |
cda4b7d3 | 8052 | base = intel_crtc->cursor_addr; |
cda4b7d3 | 8053 | |
d6e4db15 VS |
8054 | if (x >= intel_crtc->config.pipe_src_w) |
8055 | base = 0; | |
8056 | ||
8057 | if (y >= intel_crtc->config.pipe_src_h) | |
cda4b7d3 CW |
8058 | base = 0; |
8059 | ||
8060 | if (x < 0) { | |
efc9064e | 8061 | if (x + intel_crtc->cursor_width <= 0) |
cda4b7d3 CW |
8062 | base = 0; |
8063 | ||
8064 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
8065 | x = -x; | |
8066 | } | |
8067 | pos |= x << CURSOR_X_SHIFT; | |
8068 | ||
8069 | if (y < 0) { | |
efc9064e | 8070 | if (y + intel_crtc->cursor_height <= 0) |
cda4b7d3 CW |
8071 | base = 0; |
8072 | ||
8073 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
8074 | y = -y; | |
8075 | } | |
8076 | pos |= y << CURSOR_Y_SHIFT; | |
8077 | ||
4b0e333e | 8078 | if (base == 0 && intel_crtc->cursor_base == 0) |
cda4b7d3 CW |
8079 | return; |
8080 | ||
5efb3e28 VS |
8081 | I915_WRITE(CURPOS(pipe), pos); |
8082 | ||
8083 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
65a21cd6 | 8084 | ivb_update_cursor(crtc, base); |
5efb3e28 VS |
8085 | else if (IS_845G(dev) || IS_I865G(dev)) |
8086 | i845_update_cursor(crtc, base); | |
8087 | else | |
8088 | i9xx_update_cursor(crtc, base); | |
4b0e333e | 8089 | intel_crtc->cursor_base = base; |
cda4b7d3 CW |
8090 | } |
8091 | ||
e3287951 MR |
8092 | /* |
8093 | * intel_crtc_cursor_set_obj - Set cursor to specified GEM object | |
8094 | * | |
8095 | * Note that the object's reference will be consumed if the update fails. If | |
8096 | * the update succeeds, the reference of the old object (if any) will be | |
8097 | * consumed. | |
8098 | */ | |
8099 | static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc, | |
8100 | struct drm_i915_gem_object *obj, | |
8101 | uint32_t width, uint32_t height) | |
79e53945 JB |
8102 | { |
8103 | struct drm_device *dev = crtc->dev; | |
8104 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8105 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
64f962e3 | 8106 | unsigned old_width; |
cda4b7d3 | 8107 | uint32_t addr; |
3f8bc370 | 8108 | int ret; |
79e53945 | 8109 | |
79e53945 | 8110 | /* if we want to turn off the cursor ignore width and height */ |
e3287951 | 8111 | if (!obj) { |
28c97730 | 8112 | DRM_DEBUG_KMS("cursor off\n"); |
3f8bc370 | 8113 | addr = 0; |
05394f39 | 8114 | obj = NULL; |
5004417d | 8115 | mutex_lock(&dev->struct_mutex); |
3f8bc370 | 8116 | goto finish; |
79e53945 JB |
8117 | } |
8118 | ||
4726e0b0 SK |
8119 | /* Check for which cursor types we support */ |
8120 | if (!((width == 64 && height == 64) || | |
8121 | (width == 128 && height == 128 && !IS_GEN2(dev)) || | |
8122 | (width == 256 && height == 256 && !IS_GEN2(dev)))) { | |
8123 | DRM_DEBUG("Cursor dimension not supported\n"); | |
79e53945 JB |
8124 | return -EINVAL; |
8125 | } | |
8126 | ||
05394f39 | 8127 | if (obj->base.size < width * height * 4) { |
e3287951 | 8128 | DRM_DEBUG_KMS("buffer is too small\n"); |
34b8686e DA |
8129 | ret = -ENOMEM; |
8130 | goto fail; | |
79e53945 JB |
8131 | } |
8132 | ||
71acb5eb | 8133 | /* we only need to pin inside GTT if cursor is non-phy */ |
7f9872e0 | 8134 | mutex_lock(&dev->struct_mutex); |
3d13ef2e | 8135 | if (!INTEL_INFO(dev)->cursor_needs_physical) { |
693db184 CW |
8136 | unsigned alignment; |
8137 | ||
d9e86c0e | 8138 | if (obj->tiling_mode) { |
3b25b31f | 8139 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
d9e86c0e CW |
8140 | ret = -EINVAL; |
8141 | goto fail_locked; | |
8142 | } | |
8143 | ||
693db184 CW |
8144 | /* Note that the w/a also requires 2 PTE of padding following |
8145 | * the bo. We currently fill all unused PTE with the shadow | |
8146 | * page and so we should always have valid PTE following the | |
8147 | * cursor preventing the VT-d warning. | |
8148 | */ | |
8149 | alignment = 0; | |
8150 | if (need_vtd_wa(dev)) | |
8151 | alignment = 64*1024; | |
8152 | ||
8153 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL); | |
e7b526bb | 8154 | if (ret) { |
3b25b31f | 8155 | DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n"); |
2da3b9b9 | 8156 | goto fail_locked; |
e7b526bb CW |
8157 | } |
8158 | ||
d9e86c0e CW |
8159 | ret = i915_gem_object_put_fence(obj); |
8160 | if (ret) { | |
3b25b31f | 8161 | DRM_DEBUG_KMS("failed to release fence for cursor"); |
d9e86c0e CW |
8162 | goto fail_unpin; |
8163 | } | |
8164 | ||
f343c5f6 | 8165 | addr = i915_gem_obj_ggtt_offset(obj); |
71acb5eb | 8166 | } else { |
6eeefaf3 | 8167 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
00731155 | 8168 | ret = i915_gem_object_attach_phys(obj, align); |
71acb5eb | 8169 | if (ret) { |
3b25b31f | 8170 | DRM_DEBUG_KMS("failed to attach phys object\n"); |
7f9872e0 | 8171 | goto fail_locked; |
71acb5eb | 8172 | } |
00731155 | 8173 | addr = obj->phys_handle->busaddr; |
3f8bc370 KH |
8174 | } |
8175 | ||
a6c45cf0 | 8176 | if (IS_GEN2(dev)) |
14b60391 JB |
8177 | I915_WRITE(CURSIZE, (height << 12) | width); |
8178 | ||
3f8bc370 | 8179 | finish: |
3f8bc370 | 8180 | if (intel_crtc->cursor_bo) { |
00731155 | 8181 | if (!INTEL_INFO(dev)->cursor_needs_physical) |
cc98b413 | 8182 | i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo); |
05394f39 | 8183 | drm_gem_object_unreference(&intel_crtc->cursor_bo->base); |
3f8bc370 | 8184 | } |
80824003 | 8185 | |
7f9872e0 | 8186 | mutex_unlock(&dev->struct_mutex); |
3f8bc370 | 8187 | |
64f962e3 CW |
8188 | old_width = intel_crtc->cursor_width; |
8189 | ||
3f8bc370 | 8190 | intel_crtc->cursor_addr = addr; |
05394f39 | 8191 | intel_crtc->cursor_bo = obj; |
cda4b7d3 CW |
8192 | intel_crtc->cursor_width = width; |
8193 | intel_crtc->cursor_height = height; | |
8194 | ||
64f962e3 CW |
8195 | if (intel_crtc->active) { |
8196 | if (old_width != width) | |
8197 | intel_update_watermarks(crtc); | |
f2f5f771 | 8198 | intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL); |
64f962e3 | 8199 | } |
3f8bc370 | 8200 | |
79e53945 | 8201 | return 0; |
e7b526bb | 8202 | fail_unpin: |
cc98b413 | 8203 | i915_gem_object_unpin_from_display_plane(obj); |
7f9872e0 | 8204 | fail_locked: |
34b8686e | 8205 | mutex_unlock(&dev->struct_mutex); |
bc9025bd | 8206 | fail: |
05394f39 | 8207 | drm_gem_object_unreference_unlocked(&obj->base); |
34b8686e | 8208 | return ret; |
79e53945 JB |
8209 | } |
8210 | ||
e3287951 MR |
8211 | static int intel_crtc_cursor_set(struct drm_crtc *crtc, |
8212 | struct drm_file *file, | |
8213 | uint32_t handle, | |
8214 | uint32_t width, uint32_t height) | |
8215 | { | |
8216 | struct drm_device *dev = crtc->dev; | |
8217 | struct drm_i915_gem_object *obj; | |
8218 | ||
8219 | if (handle) { | |
8220 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); | |
8221 | if (&obj->base == NULL) | |
8222 | return -ENOENT; | |
8223 | } else { | |
8224 | obj = NULL; | |
8225 | } | |
8226 | ||
8227 | return intel_crtc_cursor_set_obj(crtc, obj, width, height); | |
8228 | } | |
8229 | ||
79e53945 JB |
8230 | static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) |
8231 | { | |
79e53945 | 8232 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 8233 | |
92e76c8c VS |
8234 | intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX); |
8235 | intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX); | |
652c393a | 8236 | |
f2f5f771 VS |
8237 | if (intel_crtc->active) |
8238 | intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL); | |
79e53945 JB |
8239 | |
8240 | return 0; | |
b8c00ac5 DA |
8241 | } |
8242 | ||
79e53945 | 8243 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 8244 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 8245 | { |
7203425a | 8246 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 8247 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 8248 | |
7203425a | 8249 | for (i = start; i < end; i++) { |
79e53945 JB |
8250 | intel_crtc->lut_r[i] = red[i] >> 8; |
8251 | intel_crtc->lut_g[i] = green[i] >> 8; | |
8252 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
8253 | } | |
8254 | ||
8255 | intel_crtc_load_lut(crtc); | |
8256 | } | |
8257 | ||
79e53945 JB |
8258 | /* VESA 640x480x72Hz mode to set on the pipe */ |
8259 | static struct drm_display_mode load_detect_mode = { | |
8260 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
8261 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
8262 | }; | |
8263 | ||
a8bb6818 DV |
8264 | struct drm_framebuffer * |
8265 | __intel_framebuffer_create(struct drm_device *dev, | |
8266 | struct drm_mode_fb_cmd2 *mode_cmd, | |
8267 | struct drm_i915_gem_object *obj) | |
d2dff872 CW |
8268 | { |
8269 | struct intel_framebuffer *intel_fb; | |
8270 | int ret; | |
8271 | ||
8272 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
8273 | if (!intel_fb) { | |
8274 | drm_gem_object_unreference_unlocked(&obj->base); | |
8275 | return ERR_PTR(-ENOMEM); | |
8276 | } | |
8277 | ||
8278 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
dd4916c5 DV |
8279 | if (ret) |
8280 | goto err; | |
d2dff872 CW |
8281 | |
8282 | return &intel_fb->base; | |
dd4916c5 DV |
8283 | err: |
8284 | drm_gem_object_unreference_unlocked(&obj->base); | |
8285 | kfree(intel_fb); | |
8286 | ||
8287 | return ERR_PTR(ret); | |
d2dff872 CW |
8288 | } |
8289 | ||
b5ea642a | 8290 | static struct drm_framebuffer * |
a8bb6818 DV |
8291 | intel_framebuffer_create(struct drm_device *dev, |
8292 | struct drm_mode_fb_cmd2 *mode_cmd, | |
8293 | struct drm_i915_gem_object *obj) | |
8294 | { | |
8295 | struct drm_framebuffer *fb; | |
8296 | int ret; | |
8297 | ||
8298 | ret = i915_mutex_lock_interruptible(dev); | |
8299 | if (ret) | |
8300 | return ERR_PTR(ret); | |
8301 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
8302 | mutex_unlock(&dev->struct_mutex); | |
8303 | ||
8304 | return fb; | |
8305 | } | |
8306 | ||
d2dff872 CW |
8307 | static u32 |
8308 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
8309 | { | |
8310 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
8311 | return ALIGN(pitch, 64); | |
8312 | } | |
8313 | ||
8314 | static u32 | |
8315 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
8316 | { | |
8317 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
8318 | return ALIGN(pitch * mode->vdisplay, PAGE_SIZE); | |
8319 | } | |
8320 | ||
8321 | static struct drm_framebuffer * | |
8322 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
8323 | struct drm_display_mode *mode, | |
8324 | int depth, int bpp) | |
8325 | { | |
8326 | struct drm_i915_gem_object *obj; | |
0fed39bd | 8327 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 CW |
8328 | |
8329 | obj = i915_gem_alloc_object(dev, | |
8330 | intel_framebuffer_size_for_mode(mode, bpp)); | |
8331 | if (obj == NULL) | |
8332 | return ERR_PTR(-ENOMEM); | |
8333 | ||
8334 | mode_cmd.width = mode->hdisplay; | |
8335 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
8336 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
8337 | bpp); | |
5ca0c34a | 8338 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 CW |
8339 | |
8340 | return intel_framebuffer_create(dev, &mode_cmd, obj); | |
8341 | } | |
8342 | ||
8343 | static struct drm_framebuffer * | |
8344 | mode_fits_in_fbdev(struct drm_device *dev, | |
8345 | struct drm_display_mode *mode) | |
8346 | { | |
4520f53a | 8347 | #ifdef CONFIG_DRM_I915_FBDEV |
d2dff872 CW |
8348 | struct drm_i915_private *dev_priv = dev->dev_private; |
8349 | struct drm_i915_gem_object *obj; | |
8350 | struct drm_framebuffer *fb; | |
8351 | ||
4c0e5528 | 8352 | if (!dev_priv->fbdev) |
d2dff872 CW |
8353 | return NULL; |
8354 | ||
4c0e5528 | 8355 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
8356 | return NULL; |
8357 | ||
4c0e5528 DV |
8358 | obj = dev_priv->fbdev->fb->obj; |
8359 | BUG_ON(!obj); | |
8360 | ||
8bcd4553 | 8361 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
8362 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
8363 | fb->bits_per_pixel)) | |
d2dff872 CW |
8364 | return NULL; |
8365 | ||
01f2c773 | 8366 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
8367 | return NULL; |
8368 | ||
8369 | return fb; | |
4520f53a DV |
8370 | #else |
8371 | return NULL; | |
8372 | #endif | |
d2dff872 CW |
8373 | } |
8374 | ||
d2434ab7 | 8375 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 8376 | struct drm_display_mode *mode, |
51fd371b RC |
8377 | struct intel_load_detect_pipe *old, |
8378 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
8379 | { |
8380 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
8381 | struct intel_encoder *intel_encoder = |
8382 | intel_attached_encoder(connector); | |
79e53945 | 8383 | struct drm_crtc *possible_crtc; |
4ef69c7a | 8384 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
8385 | struct drm_crtc *crtc = NULL; |
8386 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 8387 | struct drm_framebuffer *fb; |
51fd371b RC |
8388 | struct drm_mode_config *config = &dev->mode_config; |
8389 | int ret, i = -1; | |
79e53945 | 8390 | |
d2dff872 | 8391 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 8392 | connector->base.id, connector->name, |
8e329a03 | 8393 | encoder->base.id, encoder->name); |
d2dff872 | 8394 | |
51fd371b RC |
8395 | drm_modeset_acquire_init(ctx, 0); |
8396 | ||
8397 | retry: | |
8398 | ret = drm_modeset_lock(&config->connection_mutex, ctx); | |
8399 | if (ret) | |
8400 | goto fail_unlock; | |
6e9f798d | 8401 | |
79e53945 JB |
8402 | /* |
8403 | * Algorithm gets a little messy: | |
7a5e4805 | 8404 | * |
79e53945 JB |
8405 | * - if the connector already has an assigned crtc, use it (but make |
8406 | * sure it's on first) | |
7a5e4805 | 8407 | * |
79e53945 JB |
8408 | * - try to find the first unused crtc that can drive this connector, |
8409 | * and use that if we find one | |
79e53945 JB |
8410 | */ |
8411 | ||
8412 | /* See if we already have a CRTC for this connector */ | |
8413 | if (encoder->crtc) { | |
8414 | crtc = encoder->crtc; | |
8261b191 | 8415 | |
51fd371b RC |
8416 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
8417 | if (ret) | |
8418 | goto fail_unlock; | |
7b24056b | 8419 | |
24218aac | 8420 | old->dpms_mode = connector->dpms; |
8261b191 CW |
8421 | old->load_detect_temp = false; |
8422 | ||
8423 | /* Make sure the crtc and connector are running */ | |
24218aac DV |
8424 | if (connector->dpms != DRM_MODE_DPMS_ON) |
8425 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); | |
8261b191 | 8426 | |
7173188d | 8427 | return true; |
79e53945 JB |
8428 | } |
8429 | ||
8430 | /* Find an unused one (if possible) */ | |
70e1e0ec | 8431 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
8432 | i++; |
8433 | if (!(encoder->possible_crtcs & (1 << i))) | |
8434 | continue; | |
8435 | if (!possible_crtc->enabled) { | |
8436 | crtc = possible_crtc; | |
8437 | break; | |
8438 | } | |
79e53945 JB |
8439 | } |
8440 | ||
8441 | /* | |
8442 | * If we didn't find an unused CRTC, don't use any. | |
8443 | */ | |
8444 | if (!crtc) { | |
7173188d | 8445 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
51fd371b | 8446 | goto fail_unlock; |
79e53945 JB |
8447 | } |
8448 | ||
51fd371b RC |
8449 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
8450 | if (ret) | |
8451 | goto fail_unlock; | |
fc303101 DV |
8452 | intel_encoder->new_crtc = to_intel_crtc(crtc); |
8453 | to_intel_connector(connector)->new_encoder = intel_encoder; | |
79e53945 JB |
8454 | |
8455 | intel_crtc = to_intel_crtc(crtc); | |
412b61d8 VS |
8456 | intel_crtc->new_enabled = true; |
8457 | intel_crtc->new_config = &intel_crtc->config; | |
24218aac | 8458 | old->dpms_mode = connector->dpms; |
8261b191 | 8459 | old->load_detect_temp = true; |
d2dff872 | 8460 | old->release_fb = NULL; |
79e53945 | 8461 | |
6492711d CW |
8462 | if (!mode) |
8463 | mode = &load_detect_mode; | |
79e53945 | 8464 | |
d2dff872 CW |
8465 | /* We need a framebuffer large enough to accommodate all accesses |
8466 | * that the plane may generate whilst we perform load detection. | |
8467 | * We can not rely on the fbcon either being present (we get called | |
8468 | * during its initialisation to detect all boot displays, or it may | |
8469 | * not even exist) or that it is large enough to satisfy the | |
8470 | * requested mode. | |
8471 | */ | |
94352cf9 DV |
8472 | fb = mode_fits_in_fbdev(dev, mode); |
8473 | if (fb == NULL) { | |
d2dff872 | 8474 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 DV |
8475 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
8476 | old->release_fb = fb; | |
d2dff872 CW |
8477 | } else |
8478 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 8479 | if (IS_ERR(fb)) { |
d2dff872 | 8480 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 8481 | goto fail; |
79e53945 | 8482 | } |
79e53945 | 8483 | |
c0c36b94 | 8484 | if (intel_set_mode(crtc, mode, 0, 0, fb)) { |
6492711d | 8485 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
d2dff872 CW |
8486 | if (old->release_fb) |
8487 | old->release_fb->funcs->destroy(old->release_fb); | |
412b61d8 | 8488 | goto fail; |
79e53945 | 8489 | } |
7173188d | 8490 | |
79e53945 | 8491 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 8492 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 8493 | return true; |
412b61d8 VS |
8494 | |
8495 | fail: | |
8496 | intel_crtc->new_enabled = crtc->enabled; | |
8497 | if (intel_crtc->new_enabled) | |
8498 | intel_crtc->new_config = &intel_crtc->config; | |
8499 | else | |
8500 | intel_crtc->new_config = NULL; | |
51fd371b RC |
8501 | fail_unlock: |
8502 | if (ret == -EDEADLK) { | |
8503 | drm_modeset_backoff(ctx); | |
8504 | goto retry; | |
8505 | } | |
8506 | ||
8507 | drm_modeset_drop_locks(ctx); | |
8508 | drm_modeset_acquire_fini(ctx); | |
6e9f798d | 8509 | |
412b61d8 | 8510 | return false; |
79e53945 JB |
8511 | } |
8512 | ||
d2434ab7 | 8513 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
51fd371b RC |
8514 | struct intel_load_detect_pipe *old, |
8515 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 | 8516 | { |
d2434ab7 DV |
8517 | struct intel_encoder *intel_encoder = |
8518 | intel_attached_encoder(connector); | |
4ef69c7a | 8519 | struct drm_encoder *encoder = &intel_encoder->base; |
7b24056b | 8520 | struct drm_crtc *crtc = encoder->crtc; |
412b61d8 | 8521 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 8522 | |
d2dff872 | 8523 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 8524 | connector->base.id, connector->name, |
8e329a03 | 8525 | encoder->base.id, encoder->name); |
d2dff872 | 8526 | |
8261b191 | 8527 | if (old->load_detect_temp) { |
fc303101 DV |
8528 | to_intel_connector(connector)->new_encoder = NULL; |
8529 | intel_encoder->new_crtc = NULL; | |
412b61d8 VS |
8530 | intel_crtc->new_enabled = false; |
8531 | intel_crtc->new_config = NULL; | |
fc303101 | 8532 | intel_set_mode(crtc, NULL, 0, 0, NULL); |
d2dff872 | 8533 | |
36206361 DV |
8534 | if (old->release_fb) { |
8535 | drm_framebuffer_unregister_private(old->release_fb); | |
8536 | drm_framebuffer_unreference(old->release_fb); | |
8537 | } | |
d2dff872 | 8538 | |
51fd371b | 8539 | goto unlock; |
0622a53c | 8540 | return; |
79e53945 JB |
8541 | } |
8542 | ||
c751ce4f | 8543 | /* Switch crtc and encoder back off if necessary */ |
24218aac DV |
8544 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
8545 | connector->funcs->dpms(connector, old->dpms_mode); | |
7b24056b | 8546 | |
51fd371b RC |
8547 | unlock: |
8548 | drm_modeset_drop_locks(ctx); | |
8549 | drm_modeset_acquire_fini(ctx); | |
79e53945 JB |
8550 | } |
8551 | ||
da4a1efa VS |
8552 | static int i9xx_pll_refclk(struct drm_device *dev, |
8553 | const struct intel_crtc_config *pipe_config) | |
8554 | { | |
8555 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8556 | u32 dpll = pipe_config->dpll_hw_state.dpll; | |
8557 | ||
8558 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 8559 | return dev_priv->vbt.lvds_ssc_freq; |
da4a1efa VS |
8560 | else if (HAS_PCH_SPLIT(dev)) |
8561 | return 120000; | |
8562 | else if (!IS_GEN2(dev)) | |
8563 | return 96000; | |
8564 | else | |
8565 | return 48000; | |
8566 | } | |
8567 | ||
79e53945 | 8568 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc JB |
8569 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
8570 | struct intel_crtc_config *pipe_config) | |
79e53945 | 8571 | { |
f1f644dc | 8572 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 8573 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1f644dc | 8574 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 8575 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 JB |
8576 | u32 fp; |
8577 | intel_clock_t clock; | |
da4a1efa | 8578 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
8579 | |
8580 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 8581 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 8582 | else |
293623f7 | 8583 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
8584 | |
8585 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
8586 | if (IS_PINEVIEW(dev)) { |
8587 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
8588 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
8589 | } else { |
8590 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
8591 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
8592 | } | |
8593 | ||
a6c45cf0 | 8594 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
8595 | if (IS_PINEVIEW(dev)) |
8596 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
8597 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
8598 | else |
8599 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
8600 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
8601 | ||
8602 | switch (dpll & DPLL_MODE_MASK) { | |
8603 | case DPLLB_MODE_DAC_SERIAL: | |
8604 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
8605 | 5 : 10; | |
8606 | break; | |
8607 | case DPLLB_MODE_LVDS: | |
8608 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
8609 | 7 : 14; | |
8610 | break; | |
8611 | default: | |
28c97730 | 8612 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 8613 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 8614 | return; |
79e53945 JB |
8615 | } |
8616 | ||
ac58c3f0 | 8617 | if (IS_PINEVIEW(dev)) |
da4a1efa | 8618 | pineview_clock(refclk, &clock); |
ac58c3f0 | 8619 | else |
da4a1efa | 8620 | i9xx_clock(refclk, &clock); |
79e53945 | 8621 | } else { |
0fb58223 | 8622 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
b1c560d1 | 8623 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
8624 | |
8625 | if (is_lvds) { | |
8626 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
8627 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
8628 | |
8629 | if (lvds & LVDS_CLKB_POWER_UP) | |
8630 | clock.p2 = 7; | |
8631 | else | |
8632 | clock.p2 = 14; | |
79e53945 JB |
8633 | } else { |
8634 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
8635 | clock.p1 = 2; | |
8636 | else { | |
8637 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
8638 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
8639 | } | |
8640 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
8641 | clock.p2 = 4; | |
8642 | else | |
8643 | clock.p2 = 2; | |
79e53945 | 8644 | } |
da4a1efa VS |
8645 | |
8646 | i9xx_clock(refclk, &clock); | |
79e53945 JB |
8647 | } |
8648 | ||
18442d08 VS |
8649 | /* |
8650 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 8651 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
8652 | * encoder's get_config() function. |
8653 | */ | |
8654 | pipe_config->port_clock = clock.dot; | |
f1f644dc JB |
8655 | } |
8656 | ||
6878da05 VS |
8657 | int intel_dotclock_calculate(int link_freq, |
8658 | const struct intel_link_m_n *m_n) | |
f1f644dc | 8659 | { |
f1f644dc JB |
8660 | /* |
8661 | * The calculation for the data clock is: | |
1041a02f | 8662 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 8663 | * But we want to avoid losing precison if possible, so: |
1041a02f | 8664 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
8665 | * |
8666 | * and the link clock is simpler: | |
1041a02f | 8667 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
8668 | */ |
8669 | ||
6878da05 VS |
8670 | if (!m_n->link_n) |
8671 | return 0; | |
f1f644dc | 8672 | |
6878da05 VS |
8673 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
8674 | } | |
f1f644dc | 8675 | |
18442d08 VS |
8676 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
8677 | struct intel_crtc_config *pipe_config) | |
6878da05 VS |
8678 | { |
8679 | struct drm_device *dev = crtc->base.dev; | |
79e53945 | 8680 | |
18442d08 VS |
8681 | /* read out port_clock from the DPLL */ |
8682 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 8683 | |
f1f644dc | 8684 | /* |
18442d08 | 8685 | * This value does not include pixel_multiplier. |
241bfc38 | 8686 | * We will check that port_clock and adjusted_mode.crtc_clock |
18442d08 VS |
8687 | * agree once we know their relationship in the encoder's |
8688 | * get_config() function. | |
79e53945 | 8689 | */ |
241bfc38 | 8690 | pipe_config->adjusted_mode.crtc_clock = |
18442d08 VS |
8691 | intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000, |
8692 | &pipe_config->fdi_m_n); | |
79e53945 JB |
8693 | } |
8694 | ||
8695 | /** Returns the currently programmed mode of the given pipe. */ | |
8696 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
8697 | struct drm_crtc *crtc) | |
8698 | { | |
548f245b | 8699 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 8700 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3b117c8f | 8701 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
79e53945 | 8702 | struct drm_display_mode *mode; |
f1f644dc | 8703 | struct intel_crtc_config pipe_config; |
fe2b8f9d PZ |
8704 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
8705 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
8706 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
8707 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 8708 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
8709 | |
8710 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
8711 | if (!mode) | |
8712 | return NULL; | |
8713 | ||
f1f644dc JB |
8714 | /* |
8715 | * Construct a pipe_config sufficient for getting the clock info | |
8716 | * back out of crtc_clock_get. | |
8717 | * | |
8718 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
8719 | * to use a real value here instead. | |
8720 | */ | |
293623f7 | 8721 | pipe_config.cpu_transcoder = (enum transcoder) pipe; |
f1f644dc | 8722 | pipe_config.pixel_multiplier = 1; |
293623f7 VS |
8723 | pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); |
8724 | pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
8725 | pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
f1f644dc JB |
8726 | i9xx_crtc_clock_get(intel_crtc, &pipe_config); |
8727 | ||
773ae034 | 8728 | mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier; |
79e53945 JB |
8729 | mode->hdisplay = (htot & 0xffff) + 1; |
8730 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
8731 | mode->hsync_start = (hsync & 0xffff) + 1; | |
8732 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
8733 | mode->vdisplay = (vtot & 0xffff) + 1; | |
8734 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
8735 | mode->vsync_start = (vsync & 0xffff) + 1; | |
8736 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
8737 | ||
8738 | drm_mode_set_name(mode); | |
79e53945 JB |
8739 | |
8740 | return mode; | |
8741 | } | |
8742 | ||
3dec0095 | 8743 | static void intel_increase_pllclock(struct drm_crtc *crtc) |
652c393a JB |
8744 | { |
8745 | struct drm_device *dev = crtc->dev; | |
fbee40df | 8746 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a JB |
8747 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8748 | int pipe = intel_crtc->pipe; | |
dbdc6479 JB |
8749 | int dpll_reg = DPLL(pipe); |
8750 | int dpll; | |
652c393a | 8751 | |
bad720ff | 8752 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
8753 | return; |
8754 | ||
8755 | if (!dev_priv->lvds_downclock_avail) | |
8756 | return; | |
8757 | ||
dbdc6479 | 8758 | dpll = I915_READ(dpll_reg); |
652c393a | 8759 | if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { |
44d98a61 | 8760 | DRM_DEBUG_DRIVER("upclocking LVDS\n"); |
652c393a | 8761 | |
8ac5a6d5 | 8762 | assert_panel_unlocked(dev_priv, pipe); |
652c393a JB |
8763 | |
8764 | dpll &= ~DISPLAY_RATE_SELECT_FPA1; | |
8765 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 8766 | intel_wait_for_vblank(dev, pipe); |
dbdc6479 | 8767 | |
652c393a JB |
8768 | dpll = I915_READ(dpll_reg); |
8769 | if (dpll & DISPLAY_RATE_SELECT_FPA1) | |
44d98a61 | 8770 | DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); |
652c393a | 8771 | } |
652c393a JB |
8772 | } |
8773 | ||
8774 | static void intel_decrease_pllclock(struct drm_crtc *crtc) | |
8775 | { | |
8776 | struct drm_device *dev = crtc->dev; | |
fbee40df | 8777 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 8778 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
652c393a | 8779 | |
bad720ff | 8780 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
8781 | return; |
8782 | ||
8783 | if (!dev_priv->lvds_downclock_avail) | |
8784 | return; | |
8785 | ||
8786 | /* | |
8787 | * Since this is called by a timer, we should never get here in | |
8788 | * the manual case. | |
8789 | */ | |
8790 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { | |
dc257cf1 DV |
8791 | int pipe = intel_crtc->pipe; |
8792 | int dpll_reg = DPLL(pipe); | |
8793 | int dpll; | |
f6e5b160 | 8794 | |
44d98a61 | 8795 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
652c393a | 8796 | |
8ac5a6d5 | 8797 | assert_panel_unlocked(dev_priv, pipe); |
652c393a | 8798 | |
dc257cf1 | 8799 | dpll = I915_READ(dpll_reg); |
652c393a JB |
8800 | dpll |= DISPLAY_RATE_SELECT_FPA1; |
8801 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 8802 | intel_wait_for_vblank(dev, pipe); |
652c393a JB |
8803 | dpll = I915_READ(dpll_reg); |
8804 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) | |
44d98a61 | 8805 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
652c393a JB |
8806 | } |
8807 | ||
8808 | } | |
8809 | ||
f047e395 CW |
8810 | void intel_mark_busy(struct drm_device *dev) |
8811 | { | |
c67a470b PZ |
8812 | struct drm_i915_private *dev_priv = dev->dev_private; |
8813 | ||
f62a0076 CW |
8814 | if (dev_priv->mm.busy) |
8815 | return; | |
8816 | ||
43694d69 | 8817 | intel_runtime_pm_get(dev_priv); |
c67a470b | 8818 | i915_update_gfx_val(dev_priv); |
f62a0076 | 8819 | dev_priv->mm.busy = true; |
f047e395 CW |
8820 | } |
8821 | ||
8822 | void intel_mark_idle(struct drm_device *dev) | |
652c393a | 8823 | { |
c67a470b | 8824 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 8825 | struct drm_crtc *crtc; |
652c393a | 8826 | |
f62a0076 CW |
8827 | if (!dev_priv->mm.busy) |
8828 | return; | |
8829 | ||
8830 | dev_priv->mm.busy = false; | |
8831 | ||
d330a953 | 8832 | if (!i915.powersave) |
bb4cdd53 | 8833 | goto out; |
652c393a | 8834 | |
70e1e0ec | 8835 | for_each_crtc(dev, crtc) { |
f4510a27 | 8836 | if (!crtc->primary->fb) |
652c393a JB |
8837 | continue; |
8838 | ||
725a5b54 | 8839 | intel_decrease_pllclock(crtc); |
652c393a | 8840 | } |
b29c19b6 | 8841 | |
3d13ef2e | 8842 | if (INTEL_INFO(dev)->gen >= 6) |
b29c19b6 | 8843 | gen6_rps_idle(dev->dev_private); |
bb4cdd53 PZ |
8844 | |
8845 | out: | |
43694d69 | 8846 | intel_runtime_pm_put(dev_priv); |
652c393a JB |
8847 | } |
8848 | ||
c65355bb | 8849 | void intel_mark_fb_busy(struct drm_i915_gem_object *obj, |
a4872ba6 | 8850 | struct intel_engine_cs *ring) |
652c393a | 8851 | { |
f047e395 CW |
8852 | struct drm_device *dev = obj->base.dev; |
8853 | struct drm_crtc *crtc; | |
652c393a | 8854 | |
d330a953 | 8855 | if (!i915.powersave) |
acb87dfb CW |
8856 | return; |
8857 | ||
70e1e0ec | 8858 | for_each_crtc(dev, crtc) { |
f4510a27 | 8859 | if (!crtc->primary->fb) |
652c393a JB |
8860 | continue; |
8861 | ||
f4510a27 | 8862 | if (to_intel_framebuffer(crtc->primary->fb)->obj != obj) |
c65355bb CW |
8863 | continue; |
8864 | ||
8865 | intel_increase_pllclock(crtc); | |
8866 | if (ring && intel_fbc_enabled(dev)) | |
8867 | ring->fbc_dirty = true; | |
652c393a JB |
8868 | } |
8869 | } | |
8870 | ||
79e53945 JB |
8871 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
8872 | { | |
8873 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
8874 | struct drm_device *dev = crtc->dev; |
8875 | struct intel_unpin_work *work; | |
8876 | unsigned long flags; | |
8877 | ||
8878 | spin_lock_irqsave(&dev->event_lock, flags); | |
8879 | work = intel_crtc->unpin_work; | |
8880 | intel_crtc->unpin_work = NULL; | |
8881 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
8882 | ||
8883 | if (work) { | |
8884 | cancel_work_sync(&work->work); | |
8885 | kfree(work); | |
8886 | } | |
79e53945 | 8887 | |
40ccc72b MK |
8888 | intel_crtc_cursor_set(crtc, NULL, 0, 0, 0); |
8889 | ||
79e53945 | 8890 | drm_crtc_cleanup(crtc); |
67e77c5a | 8891 | |
79e53945 JB |
8892 | kfree(intel_crtc); |
8893 | } | |
8894 | ||
6b95a207 KH |
8895 | static void intel_unpin_work_fn(struct work_struct *__work) |
8896 | { | |
8897 | struct intel_unpin_work *work = | |
8898 | container_of(__work, struct intel_unpin_work, work); | |
b4a98e57 | 8899 | struct drm_device *dev = work->crtc->dev; |
6b95a207 | 8900 | |
b4a98e57 | 8901 | mutex_lock(&dev->struct_mutex); |
1690e1eb | 8902 | intel_unpin_fb_obj(work->old_fb_obj); |
05394f39 CW |
8903 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
8904 | drm_gem_object_unreference(&work->old_fb_obj->base); | |
d9e86c0e | 8905 | |
b4a98e57 CW |
8906 | intel_update_fbc(dev); |
8907 | mutex_unlock(&dev->struct_mutex); | |
8908 | ||
8909 | BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0); | |
8910 | atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count); | |
8911 | ||
6b95a207 KH |
8912 | kfree(work); |
8913 | } | |
8914 | ||
1afe3e9d | 8915 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 8916 | struct drm_crtc *crtc) |
6b95a207 | 8917 | { |
fbee40df | 8918 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
8919 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8920 | struct intel_unpin_work *work; | |
6b95a207 KH |
8921 | unsigned long flags; |
8922 | ||
8923 | /* Ignore early vblank irqs */ | |
8924 | if (intel_crtc == NULL) | |
8925 | return; | |
8926 | ||
8927 | spin_lock_irqsave(&dev->event_lock, flags); | |
8928 | work = intel_crtc->unpin_work; | |
e7d841ca CW |
8929 | |
8930 | /* Ensure we don't miss a work->pending update ... */ | |
8931 | smp_rmb(); | |
8932 | ||
8933 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { | |
6b95a207 KH |
8934 | spin_unlock_irqrestore(&dev->event_lock, flags); |
8935 | return; | |
8936 | } | |
8937 | ||
e7d841ca CW |
8938 | /* and that the unpin work is consistent wrt ->pending. */ |
8939 | smp_rmb(); | |
8940 | ||
6b95a207 | 8941 | intel_crtc->unpin_work = NULL; |
6b95a207 | 8942 | |
45a066eb RC |
8943 | if (work->event) |
8944 | drm_send_vblank_event(dev, intel_crtc->pipe, work->event); | |
6b95a207 | 8945 | |
87b6b101 | 8946 | drm_crtc_vblank_put(crtc); |
0af7e4df | 8947 | |
6b95a207 KH |
8948 | spin_unlock_irqrestore(&dev->event_lock, flags); |
8949 | ||
2c10d571 | 8950 | wake_up_all(&dev_priv->pending_flip_queue); |
b4a98e57 CW |
8951 | |
8952 | queue_work(dev_priv->wq, &work->work); | |
e5510fac JB |
8953 | |
8954 | trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj); | |
6b95a207 KH |
8955 | } |
8956 | ||
1afe3e9d JB |
8957 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
8958 | { | |
fbee40df | 8959 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
8960 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
8961 | ||
49b14a5c | 8962 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
8963 | } |
8964 | ||
8965 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
8966 | { | |
fbee40df | 8967 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
8968 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
8969 | ||
49b14a5c | 8970 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
8971 | } |
8972 | ||
75f7f3ec VS |
8973 | /* Is 'a' after or equal to 'b'? */ |
8974 | static bool g4x_flip_count_after_eq(u32 a, u32 b) | |
8975 | { | |
8976 | return !((a - b) & 0x80000000); | |
8977 | } | |
8978 | ||
8979 | static bool page_flip_finished(struct intel_crtc *crtc) | |
8980 | { | |
8981 | struct drm_device *dev = crtc->base.dev; | |
8982 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8983 | ||
8984 | /* | |
8985 | * The relevant registers doen't exist on pre-ctg. | |
8986 | * As the flip done interrupt doesn't trigger for mmio | |
8987 | * flips on gmch platforms, a flip count check isn't | |
8988 | * really needed there. But since ctg has the registers, | |
8989 | * include it in the check anyway. | |
8990 | */ | |
8991 | if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) | |
8992 | return true; | |
8993 | ||
8994 | /* | |
8995 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips | |
8996 | * used the same base address. In that case the mmio flip might | |
8997 | * have completed, but the CS hasn't even executed the flip yet. | |
8998 | * | |
8999 | * A flip count check isn't enough as the CS might have updated | |
9000 | * the base address just after start of vblank, but before we | |
9001 | * managed to process the interrupt. This means we'd complete the | |
9002 | * CS flip too soon. | |
9003 | * | |
9004 | * Combining both checks should get us a good enough result. It may | |
9005 | * still happen that the CS flip has been executed, but has not | |
9006 | * yet actually completed. But in case the base address is the same | |
9007 | * anyway, we don't really care. | |
9008 | */ | |
9009 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == | |
9010 | crtc->unpin_work->gtt_offset && | |
9011 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)), | |
9012 | crtc->unpin_work->flip_count); | |
9013 | } | |
9014 | ||
6b95a207 KH |
9015 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
9016 | { | |
fbee40df | 9017 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
9018 | struct intel_crtc *intel_crtc = |
9019 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
9020 | unsigned long flags; | |
9021 | ||
e7d841ca CW |
9022 | /* NB: An MMIO update of the plane base pointer will also |
9023 | * generate a page-flip completion irq, i.e. every modeset | |
9024 | * is also accompanied by a spurious intel_prepare_page_flip(). | |
9025 | */ | |
6b95a207 | 9026 | spin_lock_irqsave(&dev->event_lock, flags); |
75f7f3ec | 9027 | if (intel_crtc->unpin_work && page_flip_finished(intel_crtc)) |
e7d841ca | 9028 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); |
6b95a207 KH |
9029 | spin_unlock_irqrestore(&dev->event_lock, flags); |
9030 | } | |
9031 | ||
eba905b2 | 9032 | static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc) |
e7d841ca CW |
9033 | { |
9034 | /* Ensure that the work item is consistent when activating it ... */ | |
9035 | smp_wmb(); | |
9036 | atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING); | |
9037 | /* and that it is marked active as soon as the irq could fire. */ | |
9038 | smp_wmb(); | |
9039 | } | |
9040 | ||
8c9f3aaf JB |
9041 | static int intel_gen2_queue_flip(struct drm_device *dev, |
9042 | struct drm_crtc *crtc, | |
9043 | struct drm_framebuffer *fb, | |
ed8d1975 | 9044 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9045 | struct intel_engine_cs *ring, |
ed8d1975 | 9046 | uint32_t flags) |
8c9f3aaf | 9047 | { |
8c9f3aaf | 9048 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
9049 | u32 flip_mask; |
9050 | int ret; | |
9051 | ||
6d90c952 | 9052 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 9053 | if (ret) |
4fa62c89 | 9054 | return ret; |
8c9f3aaf JB |
9055 | |
9056 | /* Can't queue multiple flips, so wait for the previous | |
9057 | * one to finish before executing the next. | |
9058 | */ | |
9059 | if (intel_crtc->plane) | |
9060 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
9061 | else | |
9062 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
9063 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
9064 | intel_ring_emit(ring, MI_NOOP); | |
9065 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
9066 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9067 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 9068 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 | 9069 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
e7d841ca CW |
9070 | |
9071 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9072 | __intel_ring_advance(ring); |
83d4092b | 9073 | return 0; |
8c9f3aaf JB |
9074 | } |
9075 | ||
9076 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
9077 | struct drm_crtc *crtc, | |
9078 | struct drm_framebuffer *fb, | |
ed8d1975 | 9079 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9080 | struct intel_engine_cs *ring, |
ed8d1975 | 9081 | uint32_t flags) |
8c9f3aaf | 9082 | { |
8c9f3aaf | 9083 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
9084 | u32 flip_mask; |
9085 | int ret; | |
9086 | ||
6d90c952 | 9087 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 9088 | if (ret) |
4fa62c89 | 9089 | return ret; |
8c9f3aaf JB |
9090 | |
9091 | if (intel_crtc->plane) | |
9092 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
9093 | else | |
9094 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
9095 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
9096 | intel_ring_emit(ring, MI_NOOP); | |
9097 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
9098 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9099 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 9100 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 DV |
9101 | intel_ring_emit(ring, MI_NOOP); |
9102 | ||
e7d841ca | 9103 | intel_mark_page_flip_active(intel_crtc); |
09246732 | 9104 | __intel_ring_advance(ring); |
83d4092b | 9105 | return 0; |
8c9f3aaf JB |
9106 | } |
9107 | ||
9108 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
9109 | struct drm_crtc *crtc, | |
9110 | struct drm_framebuffer *fb, | |
ed8d1975 | 9111 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9112 | struct intel_engine_cs *ring, |
ed8d1975 | 9113 | uint32_t flags) |
8c9f3aaf JB |
9114 | { |
9115 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9116 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9117 | uint32_t pf, pipesrc; | |
9118 | int ret; | |
9119 | ||
6d90c952 | 9120 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 9121 | if (ret) |
4fa62c89 | 9122 | return ret; |
8c9f3aaf JB |
9123 | |
9124 | /* i965+ uses the linear or tiled offsets from the | |
9125 | * Display Registers (which do not change across a page-flip) | |
9126 | * so we need only reprogram the base address. | |
9127 | */ | |
6d90c952 DV |
9128 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
9129 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9130 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 9131 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset | |
c2c75131 | 9132 | obj->tiling_mode); |
8c9f3aaf JB |
9133 | |
9134 | /* XXX Enabling the panel-fitter across page-flip is so far | |
9135 | * untested on non-native modes, so ignore it for now. | |
9136 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
9137 | */ | |
9138 | pf = 0; | |
9139 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
6d90c952 | 9140 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
9141 | |
9142 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9143 | __intel_ring_advance(ring); |
83d4092b | 9144 | return 0; |
8c9f3aaf JB |
9145 | } |
9146 | ||
9147 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
9148 | struct drm_crtc *crtc, | |
9149 | struct drm_framebuffer *fb, | |
ed8d1975 | 9150 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9151 | struct intel_engine_cs *ring, |
ed8d1975 | 9152 | uint32_t flags) |
8c9f3aaf JB |
9153 | { |
9154 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9155 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9156 | uint32_t pf, pipesrc; | |
9157 | int ret; | |
9158 | ||
6d90c952 | 9159 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 9160 | if (ret) |
4fa62c89 | 9161 | return ret; |
8c9f3aaf | 9162 | |
6d90c952 DV |
9163 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
9164 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9165 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); | |
75f7f3ec | 9166 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
8c9f3aaf | 9167 | |
dc257cf1 DV |
9168 | /* Contrary to the suggestions in the documentation, |
9169 | * "Enable Panel Fitter" does not seem to be required when page | |
9170 | * flipping with a non-native mode, and worse causes a normal | |
9171 | * modeset to fail. | |
9172 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
9173 | */ | |
9174 | pf = 0; | |
8c9f3aaf | 9175 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
6d90c952 | 9176 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
9177 | |
9178 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9179 | __intel_ring_advance(ring); |
83d4092b | 9180 | return 0; |
8c9f3aaf JB |
9181 | } |
9182 | ||
7c9017e5 JB |
9183 | static int intel_gen7_queue_flip(struct drm_device *dev, |
9184 | struct drm_crtc *crtc, | |
9185 | struct drm_framebuffer *fb, | |
ed8d1975 | 9186 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9187 | struct intel_engine_cs *ring, |
ed8d1975 | 9188 | uint32_t flags) |
7c9017e5 | 9189 | { |
7c9017e5 | 9190 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cb05d8de | 9191 | uint32_t plane_bit = 0; |
ffe74d75 CW |
9192 | int len, ret; |
9193 | ||
eba905b2 | 9194 | switch (intel_crtc->plane) { |
cb05d8de DV |
9195 | case PLANE_A: |
9196 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
9197 | break; | |
9198 | case PLANE_B: | |
9199 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
9200 | break; | |
9201 | case PLANE_C: | |
9202 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
9203 | break; | |
9204 | default: | |
9205 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
4fa62c89 | 9206 | return -ENODEV; |
cb05d8de DV |
9207 | } |
9208 | ||
ffe74d75 | 9209 | len = 4; |
f476828a | 9210 | if (ring->id == RCS) { |
ffe74d75 | 9211 | len += 6; |
f476828a DL |
9212 | /* |
9213 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
9214 | * 48bits addresses, and we need a NOOP for the batch size to | |
9215 | * stay even. | |
9216 | */ | |
9217 | if (IS_GEN8(dev)) | |
9218 | len += 2; | |
9219 | } | |
ffe74d75 | 9220 | |
f66fab8e VS |
9221 | /* |
9222 | * BSpec MI_DISPLAY_FLIP for IVB: | |
9223 | * "The full packet must be contained within the same cache line." | |
9224 | * | |
9225 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
9226 | * cacheline, if we ever start emitting more commands before | |
9227 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
9228 | * then do the cacheline alignment, and finally emit the | |
9229 | * MI_DISPLAY_FLIP. | |
9230 | */ | |
9231 | ret = intel_ring_cacheline_align(ring); | |
9232 | if (ret) | |
4fa62c89 | 9233 | return ret; |
f66fab8e | 9234 | |
ffe74d75 | 9235 | ret = intel_ring_begin(ring, len); |
7c9017e5 | 9236 | if (ret) |
4fa62c89 | 9237 | return ret; |
7c9017e5 | 9238 | |
ffe74d75 CW |
9239 | /* Unmask the flip-done completion message. Note that the bspec says that |
9240 | * we should do this for both the BCS and RCS, and that we must not unmask | |
9241 | * more than one flip event at any time (or ensure that one flip message | |
9242 | * can be sent by waiting for flip-done prior to queueing new flips). | |
9243 | * Experimentation says that BCS works despite DERRMR masking all | |
9244 | * flip-done completion events and that unmasking all planes at once | |
9245 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
9246 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
9247 | */ | |
9248 | if (ring->id == RCS) { | |
9249 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
9250 | intel_ring_emit(ring, DERRMR); | |
9251 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
9252 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
9253 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
f476828a DL |
9254 | if (IS_GEN8(dev)) |
9255 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) | | |
9256 | MI_SRM_LRM_GLOBAL_GTT); | |
9257 | else | |
9258 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | | |
9259 | MI_SRM_LRM_GLOBAL_GTT); | |
ffe74d75 CW |
9260 | intel_ring_emit(ring, DERRMR); |
9261 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); | |
f476828a DL |
9262 | if (IS_GEN8(dev)) { |
9263 | intel_ring_emit(ring, 0); | |
9264 | intel_ring_emit(ring, MI_NOOP); | |
9265 | } | |
ffe74d75 CW |
9266 | } |
9267 | ||
cb05d8de | 9268 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
01f2c773 | 9269 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
75f7f3ec | 9270 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
7c9017e5 | 9271 | intel_ring_emit(ring, (MI_NOOP)); |
e7d841ca CW |
9272 | |
9273 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9274 | __intel_ring_advance(ring); |
83d4092b | 9275 | return 0; |
7c9017e5 JB |
9276 | } |
9277 | ||
8c9f3aaf JB |
9278 | static int intel_default_queue_flip(struct drm_device *dev, |
9279 | struct drm_crtc *crtc, | |
9280 | struct drm_framebuffer *fb, | |
ed8d1975 | 9281 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9282 | struct intel_engine_cs *ring, |
ed8d1975 | 9283 | uint32_t flags) |
8c9f3aaf JB |
9284 | { |
9285 | return -ENODEV; | |
9286 | } | |
9287 | ||
6b95a207 KH |
9288 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
9289 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
9290 | struct drm_pending_vblank_event *event, |
9291 | uint32_t page_flip_flags) | |
6b95a207 KH |
9292 | { |
9293 | struct drm_device *dev = crtc->dev; | |
9294 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f4510a27 | 9295 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
4a35f83b | 9296 | struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj; |
6b95a207 KH |
9297 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
9298 | struct intel_unpin_work *work; | |
a4872ba6 | 9299 | struct intel_engine_cs *ring; |
8c9f3aaf | 9300 | unsigned long flags; |
52e68630 | 9301 | int ret; |
6b95a207 | 9302 | |
e6a595d2 | 9303 | /* Can't change pixel format via MI display flips. */ |
f4510a27 | 9304 | if (fb->pixel_format != crtc->primary->fb->pixel_format) |
e6a595d2 VS |
9305 | return -EINVAL; |
9306 | ||
9307 | /* | |
9308 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
9309 | * Note that pitch changes could also affect these register. | |
9310 | */ | |
9311 | if (INTEL_INFO(dev)->gen > 3 && | |
f4510a27 MR |
9312 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || |
9313 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
e6a595d2 VS |
9314 | return -EINVAL; |
9315 | ||
f900db47 CW |
9316 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
9317 | goto out_hang; | |
9318 | ||
b14c5679 | 9319 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
6b95a207 KH |
9320 | if (work == NULL) |
9321 | return -ENOMEM; | |
9322 | ||
6b95a207 | 9323 | work->event = event; |
b4a98e57 | 9324 | work->crtc = crtc; |
4a35f83b | 9325 | work->old_fb_obj = to_intel_framebuffer(old_fb)->obj; |
6b95a207 KH |
9326 | INIT_WORK(&work->work, intel_unpin_work_fn); |
9327 | ||
87b6b101 | 9328 | ret = drm_crtc_vblank_get(crtc); |
7317c75e JB |
9329 | if (ret) |
9330 | goto free_work; | |
9331 | ||
6b95a207 KH |
9332 | /* We borrow the event spin lock for protecting unpin_work */ |
9333 | spin_lock_irqsave(&dev->event_lock, flags); | |
9334 | if (intel_crtc->unpin_work) { | |
9335 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
9336 | kfree(work); | |
87b6b101 | 9337 | drm_crtc_vblank_put(crtc); |
468f0b44 CW |
9338 | |
9339 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
6b95a207 KH |
9340 | return -EBUSY; |
9341 | } | |
9342 | intel_crtc->unpin_work = work; | |
9343 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
9344 | ||
b4a98e57 CW |
9345 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
9346 | flush_workqueue(dev_priv->wq); | |
9347 | ||
79158103 CW |
9348 | ret = i915_mutex_lock_interruptible(dev); |
9349 | if (ret) | |
9350 | goto cleanup; | |
6b95a207 | 9351 | |
75dfca80 | 9352 | /* Reference the objects for the scheduled work. */ |
05394f39 CW |
9353 | drm_gem_object_reference(&work->old_fb_obj->base); |
9354 | drm_gem_object_reference(&obj->base); | |
6b95a207 | 9355 | |
f4510a27 | 9356 | crtc->primary->fb = fb; |
96b099fd | 9357 | |
e1f99ce6 | 9358 | work->pending_flip_obj = obj; |
e1f99ce6 | 9359 | |
4e5359cd SF |
9360 | work->enable_stall_check = true; |
9361 | ||
b4a98e57 | 9362 | atomic_inc(&intel_crtc->unpin_work_count); |
10d83730 | 9363 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
e1f99ce6 | 9364 | |
75f7f3ec VS |
9365 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) |
9366 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(intel_crtc->pipe)) + 1; | |
9367 | ||
4fa62c89 VS |
9368 | if (IS_VALLEYVIEW(dev)) { |
9369 | ring = &dev_priv->ring[BCS]; | |
9370 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
9371 | ring = obj->ring; | |
9372 | if (ring == NULL || ring->id != RCS) | |
9373 | ring = &dev_priv->ring[BCS]; | |
9374 | } else { | |
9375 | ring = &dev_priv->ring[RCS]; | |
9376 | } | |
9377 | ||
9378 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); | |
8c9f3aaf JB |
9379 | if (ret) |
9380 | goto cleanup_pending; | |
6b95a207 | 9381 | |
4fa62c89 VS |
9382 | work->gtt_offset = |
9383 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset; | |
9384 | ||
9385 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring, page_flip_flags); | |
9386 | if (ret) | |
9387 | goto cleanup_unpin; | |
9388 | ||
7782de3b | 9389 | intel_disable_fbc(dev); |
c65355bb | 9390 | intel_mark_fb_busy(obj, NULL); |
6b95a207 KH |
9391 | mutex_unlock(&dev->struct_mutex); |
9392 | ||
e5510fac JB |
9393 | trace_i915_flip_request(intel_crtc->plane, obj); |
9394 | ||
6b95a207 | 9395 | return 0; |
96b099fd | 9396 | |
4fa62c89 VS |
9397 | cleanup_unpin: |
9398 | intel_unpin_fb_obj(obj); | |
8c9f3aaf | 9399 | cleanup_pending: |
b4a98e57 | 9400 | atomic_dec(&intel_crtc->unpin_work_count); |
f4510a27 | 9401 | crtc->primary->fb = old_fb; |
05394f39 CW |
9402 | drm_gem_object_unreference(&work->old_fb_obj->base); |
9403 | drm_gem_object_unreference(&obj->base); | |
96b099fd CW |
9404 | mutex_unlock(&dev->struct_mutex); |
9405 | ||
79158103 | 9406 | cleanup: |
96b099fd CW |
9407 | spin_lock_irqsave(&dev->event_lock, flags); |
9408 | intel_crtc->unpin_work = NULL; | |
9409 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
9410 | ||
87b6b101 | 9411 | drm_crtc_vblank_put(crtc); |
7317c75e | 9412 | free_work: |
96b099fd CW |
9413 | kfree(work); |
9414 | ||
f900db47 CW |
9415 | if (ret == -EIO) { |
9416 | out_hang: | |
9417 | intel_crtc_wait_for_pending_flips(crtc); | |
9418 | ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb); | |
9419 | if (ret == 0 && event) | |
9420 | drm_send_vblank_event(dev, intel_crtc->pipe, event); | |
9421 | } | |
96b099fd | 9422 | return ret; |
6b95a207 KH |
9423 | } |
9424 | ||
f6e5b160 | 9425 | static struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 CW |
9426 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
9427 | .load_lut = intel_crtc_load_lut, | |
f6e5b160 CW |
9428 | }; |
9429 | ||
9a935856 DV |
9430 | /** |
9431 | * intel_modeset_update_staged_output_state | |
9432 | * | |
9433 | * Updates the staged output configuration state, e.g. after we've read out the | |
9434 | * current hw state. | |
9435 | */ | |
9436 | static void intel_modeset_update_staged_output_state(struct drm_device *dev) | |
f6e5b160 | 9437 | { |
7668851f | 9438 | struct intel_crtc *crtc; |
9a935856 DV |
9439 | struct intel_encoder *encoder; |
9440 | struct intel_connector *connector; | |
f6e5b160 | 9441 | |
9a935856 DV |
9442 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9443 | base.head) { | |
9444 | connector->new_encoder = | |
9445 | to_intel_encoder(connector->base.encoder); | |
9446 | } | |
f6e5b160 | 9447 | |
9a935856 DV |
9448 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9449 | base.head) { | |
9450 | encoder->new_crtc = | |
9451 | to_intel_crtc(encoder->base.crtc); | |
9452 | } | |
7668851f | 9453 | |
d3fcc808 | 9454 | for_each_intel_crtc(dev, crtc) { |
7668851f | 9455 | crtc->new_enabled = crtc->base.enabled; |
7bd0a8e7 VS |
9456 | |
9457 | if (crtc->new_enabled) | |
9458 | crtc->new_config = &crtc->config; | |
9459 | else | |
9460 | crtc->new_config = NULL; | |
7668851f | 9461 | } |
f6e5b160 CW |
9462 | } |
9463 | ||
9a935856 DV |
9464 | /** |
9465 | * intel_modeset_commit_output_state | |
9466 | * | |
9467 | * This function copies the stage display pipe configuration to the real one. | |
9468 | */ | |
9469 | static void intel_modeset_commit_output_state(struct drm_device *dev) | |
9470 | { | |
7668851f | 9471 | struct intel_crtc *crtc; |
9a935856 DV |
9472 | struct intel_encoder *encoder; |
9473 | struct intel_connector *connector; | |
f6e5b160 | 9474 | |
9a935856 DV |
9475 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9476 | base.head) { | |
9477 | connector->base.encoder = &connector->new_encoder->base; | |
9478 | } | |
f6e5b160 | 9479 | |
9a935856 DV |
9480 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9481 | base.head) { | |
9482 | encoder->base.crtc = &encoder->new_crtc->base; | |
9483 | } | |
7668851f | 9484 | |
d3fcc808 | 9485 | for_each_intel_crtc(dev, crtc) { |
7668851f VS |
9486 | crtc->base.enabled = crtc->new_enabled; |
9487 | } | |
9a935856 DV |
9488 | } |
9489 | ||
050f7aeb | 9490 | static void |
eba905b2 | 9491 | connected_sink_compute_bpp(struct intel_connector *connector, |
050f7aeb DV |
9492 | struct intel_crtc_config *pipe_config) |
9493 | { | |
9494 | int bpp = pipe_config->pipe_bpp; | |
9495 | ||
9496 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
9497 | connector->base.base.id, | |
c23cc417 | 9498 | connector->base.name); |
050f7aeb DV |
9499 | |
9500 | /* Don't use an invalid EDID bpc value */ | |
9501 | if (connector->base.display_info.bpc && | |
9502 | connector->base.display_info.bpc * 3 < bpp) { | |
9503 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
9504 | bpp, connector->base.display_info.bpc*3); | |
9505 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
9506 | } | |
9507 | ||
9508 | /* Clamp bpp to 8 on screens without EDID 1.4 */ | |
9509 | if (connector->base.display_info.bpc == 0 && bpp > 24) { | |
9510 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", | |
9511 | bpp); | |
9512 | pipe_config->pipe_bpp = 24; | |
9513 | } | |
9514 | } | |
9515 | ||
4e53c2e0 | 9516 | static int |
050f7aeb DV |
9517 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
9518 | struct drm_framebuffer *fb, | |
9519 | struct intel_crtc_config *pipe_config) | |
4e53c2e0 | 9520 | { |
050f7aeb DV |
9521 | struct drm_device *dev = crtc->base.dev; |
9522 | struct intel_connector *connector; | |
4e53c2e0 DV |
9523 | int bpp; |
9524 | ||
d42264b1 DV |
9525 | switch (fb->pixel_format) { |
9526 | case DRM_FORMAT_C8: | |
4e53c2e0 DV |
9527 | bpp = 8*3; /* since we go through a colormap */ |
9528 | break; | |
d42264b1 DV |
9529 | case DRM_FORMAT_XRGB1555: |
9530 | case DRM_FORMAT_ARGB1555: | |
9531 | /* checked in intel_framebuffer_init already */ | |
9532 | if (WARN_ON(INTEL_INFO(dev)->gen > 3)) | |
9533 | return -EINVAL; | |
9534 | case DRM_FORMAT_RGB565: | |
4e53c2e0 DV |
9535 | bpp = 6*3; /* min is 18bpp */ |
9536 | break; | |
d42264b1 DV |
9537 | case DRM_FORMAT_XBGR8888: |
9538 | case DRM_FORMAT_ABGR8888: | |
9539 | /* checked in intel_framebuffer_init already */ | |
9540 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) | |
9541 | return -EINVAL; | |
9542 | case DRM_FORMAT_XRGB8888: | |
9543 | case DRM_FORMAT_ARGB8888: | |
4e53c2e0 DV |
9544 | bpp = 8*3; |
9545 | break; | |
d42264b1 DV |
9546 | case DRM_FORMAT_XRGB2101010: |
9547 | case DRM_FORMAT_ARGB2101010: | |
9548 | case DRM_FORMAT_XBGR2101010: | |
9549 | case DRM_FORMAT_ABGR2101010: | |
9550 | /* checked in intel_framebuffer_init already */ | |
9551 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) | |
baba133a | 9552 | return -EINVAL; |
4e53c2e0 DV |
9553 | bpp = 10*3; |
9554 | break; | |
baba133a | 9555 | /* TODO: gen4+ supports 16 bpc floating point, too. */ |
4e53c2e0 DV |
9556 | default: |
9557 | DRM_DEBUG_KMS("unsupported depth\n"); | |
9558 | return -EINVAL; | |
9559 | } | |
9560 | ||
4e53c2e0 DV |
9561 | pipe_config->pipe_bpp = bpp; |
9562 | ||
9563 | /* Clamp display bpp to EDID value */ | |
9564 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
050f7aeb | 9565 | base.head) { |
1b829e05 DV |
9566 | if (!connector->new_encoder || |
9567 | connector->new_encoder->new_crtc != crtc) | |
4e53c2e0 DV |
9568 | continue; |
9569 | ||
050f7aeb | 9570 | connected_sink_compute_bpp(connector, pipe_config); |
4e53c2e0 DV |
9571 | } |
9572 | ||
9573 | return bpp; | |
9574 | } | |
9575 | ||
644db711 DV |
9576 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
9577 | { | |
9578 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
9579 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 9580 | mode->crtc_clock, |
644db711 DV |
9581 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
9582 | mode->crtc_hsync_end, mode->crtc_htotal, | |
9583 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
9584 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
9585 | } | |
9586 | ||
c0b03411 DV |
9587 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
9588 | struct intel_crtc_config *pipe_config, | |
9589 | const char *context) | |
9590 | { | |
9591 | DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id, | |
9592 | context, pipe_name(crtc->pipe)); | |
9593 | ||
9594 | DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); | |
9595 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", | |
9596 | pipe_config->pipe_bpp, pipe_config->dither); | |
9597 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
9598 | pipe_config->has_pch_encoder, | |
9599 | pipe_config->fdi_lanes, | |
9600 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
9601 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
9602 | pipe_config->fdi_m_n.tu); | |
eb14cb74 VS |
9603 | DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
9604 | pipe_config->has_dp_encoder, | |
9605 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, | |
9606 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
9607 | pipe_config->dp_m_n.tu); | |
c0b03411 DV |
9608 | DRM_DEBUG_KMS("requested mode:\n"); |
9609 | drm_mode_debug_printmodeline(&pipe_config->requested_mode); | |
9610 | DRM_DEBUG_KMS("adjusted mode:\n"); | |
9611 | drm_mode_debug_printmodeline(&pipe_config->adjusted_mode); | |
644db711 | 9612 | intel_dump_crtc_timings(&pipe_config->adjusted_mode); |
d71b8d4a | 9613 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
9614 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
9615 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
c0b03411 DV |
9616 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
9617 | pipe_config->gmch_pfit.control, | |
9618 | pipe_config->gmch_pfit.pgm_ratios, | |
9619 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 9620 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 9621 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
9622 | pipe_config->pch_pfit.size, |
9623 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 9624 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 9625 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
c0b03411 DV |
9626 | } |
9627 | ||
bc079e8b VS |
9628 | static bool encoders_cloneable(const struct intel_encoder *a, |
9629 | const struct intel_encoder *b) | |
accfc0c5 | 9630 | { |
bc079e8b VS |
9631 | /* masks could be asymmetric, so check both ways */ |
9632 | return a == b || (a->cloneable & (1 << b->type) && | |
9633 | b->cloneable & (1 << a->type)); | |
9634 | } | |
9635 | ||
9636 | static bool check_single_encoder_cloning(struct intel_crtc *crtc, | |
9637 | struct intel_encoder *encoder) | |
9638 | { | |
9639 | struct drm_device *dev = crtc->base.dev; | |
9640 | struct intel_encoder *source_encoder; | |
9641 | ||
9642 | list_for_each_entry(source_encoder, | |
9643 | &dev->mode_config.encoder_list, base.head) { | |
9644 | if (source_encoder->new_crtc != crtc) | |
9645 | continue; | |
9646 | ||
9647 | if (!encoders_cloneable(encoder, source_encoder)) | |
9648 | return false; | |
9649 | } | |
9650 | ||
9651 | return true; | |
9652 | } | |
9653 | ||
9654 | static bool check_encoder_cloning(struct intel_crtc *crtc) | |
9655 | { | |
9656 | struct drm_device *dev = crtc->base.dev; | |
accfc0c5 DV |
9657 | struct intel_encoder *encoder; |
9658 | ||
bc079e8b VS |
9659 | list_for_each_entry(encoder, |
9660 | &dev->mode_config.encoder_list, base.head) { | |
9661 | if (encoder->new_crtc != crtc) | |
accfc0c5 DV |
9662 | continue; |
9663 | ||
bc079e8b VS |
9664 | if (!check_single_encoder_cloning(crtc, encoder)) |
9665 | return false; | |
accfc0c5 DV |
9666 | } |
9667 | ||
bc079e8b | 9668 | return true; |
accfc0c5 DV |
9669 | } |
9670 | ||
b8cecdf5 DV |
9671 | static struct intel_crtc_config * |
9672 | intel_modeset_pipe_config(struct drm_crtc *crtc, | |
4e53c2e0 | 9673 | struct drm_framebuffer *fb, |
b8cecdf5 | 9674 | struct drm_display_mode *mode) |
ee7b9f93 | 9675 | { |
7758a113 | 9676 | struct drm_device *dev = crtc->dev; |
7758a113 | 9677 | struct intel_encoder *encoder; |
b8cecdf5 | 9678 | struct intel_crtc_config *pipe_config; |
e29c22c0 DV |
9679 | int plane_bpp, ret = -EINVAL; |
9680 | bool retry = true; | |
ee7b9f93 | 9681 | |
bc079e8b | 9682 | if (!check_encoder_cloning(to_intel_crtc(crtc))) { |
accfc0c5 DV |
9683 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); |
9684 | return ERR_PTR(-EINVAL); | |
9685 | } | |
9686 | ||
b8cecdf5 DV |
9687 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
9688 | if (!pipe_config) | |
7758a113 DV |
9689 | return ERR_PTR(-ENOMEM); |
9690 | ||
b8cecdf5 DV |
9691 | drm_mode_copy(&pipe_config->adjusted_mode, mode); |
9692 | drm_mode_copy(&pipe_config->requested_mode, mode); | |
37327abd | 9693 | |
e143a21c DV |
9694 | pipe_config->cpu_transcoder = |
9695 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
c0d43d62 | 9696 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
b8cecdf5 | 9697 | |
2960bc9c ID |
9698 | /* |
9699 | * Sanitize sync polarity flags based on requested ones. If neither | |
9700 | * positive or negative polarity is requested, treat this as meaning | |
9701 | * negative polarity. | |
9702 | */ | |
9703 | if (!(pipe_config->adjusted_mode.flags & | |
9704 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) | |
9705 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; | |
9706 | ||
9707 | if (!(pipe_config->adjusted_mode.flags & | |
9708 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) | |
9709 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; | |
9710 | ||
050f7aeb DV |
9711 | /* Compute a starting value for pipe_config->pipe_bpp taking the source |
9712 | * plane pixel format and any sink constraints into account. Returns the | |
9713 | * source plane bpp so that dithering can be selected on mismatches | |
9714 | * after encoders and crtc also have had their say. */ | |
9715 | plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), | |
9716 | fb, pipe_config); | |
4e53c2e0 DV |
9717 | if (plane_bpp < 0) |
9718 | goto fail; | |
9719 | ||
e41a56be VS |
9720 | /* |
9721 | * Determine the real pipe dimensions. Note that stereo modes can | |
9722 | * increase the actual pipe size due to the frame doubling and | |
9723 | * insertion of additional space for blanks between the frame. This | |
9724 | * is stored in the crtc timings. We use the requested mode to do this | |
9725 | * computation to clearly distinguish it from the adjusted mode, which | |
9726 | * can be changed by the connectors in the below retry loop. | |
9727 | */ | |
9728 | drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE); | |
9729 | pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay; | |
9730 | pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay; | |
9731 | ||
e29c22c0 | 9732 | encoder_retry: |
ef1b460d | 9733 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 9734 | pipe_config->port_clock = 0; |
ef1b460d | 9735 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 9736 | |
135c81b8 | 9737 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
6ce70f5e | 9738 | drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE); |
135c81b8 | 9739 | |
7758a113 DV |
9740 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
9741 | * adjust it according to limitations or connector properties, and also | |
9742 | * a chance to reject the mode entirely. | |
47f1c6c9 | 9743 | */ |
7758a113 DV |
9744 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9745 | base.head) { | |
47f1c6c9 | 9746 | |
7758a113 DV |
9747 | if (&encoder->new_crtc->base != crtc) |
9748 | continue; | |
7ae89233 | 9749 | |
efea6e8e DV |
9750 | if (!(encoder->compute_config(encoder, pipe_config))) { |
9751 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
9752 | goto fail; |
9753 | } | |
ee7b9f93 | 9754 | } |
47f1c6c9 | 9755 | |
ff9a6750 DV |
9756 | /* Set default port clock if not overwritten by the encoder. Needs to be |
9757 | * done afterwards in case the encoder adjusts the mode. */ | |
9758 | if (!pipe_config->port_clock) | |
241bfc38 DL |
9759 | pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock |
9760 | * pipe_config->pixel_multiplier; | |
ff9a6750 | 9761 | |
a43f6e0f | 9762 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 9763 | if (ret < 0) { |
7758a113 DV |
9764 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
9765 | goto fail; | |
ee7b9f93 | 9766 | } |
e29c22c0 DV |
9767 | |
9768 | if (ret == RETRY) { | |
9769 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
9770 | ret = -EINVAL; | |
9771 | goto fail; | |
9772 | } | |
9773 | ||
9774 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
9775 | retry = false; | |
9776 | goto encoder_retry; | |
9777 | } | |
9778 | ||
4e53c2e0 DV |
9779 | pipe_config->dither = pipe_config->pipe_bpp != plane_bpp; |
9780 | DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n", | |
9781 | plane_bpp, pipe_config->pipe_bpp, pipe_config->dither); | |
9782 | ||
b8cecdf5 | 9783 | return pipe_config; |
7758a113 | 9784 | fail: |
b8cecdf5 | 9785 | kfree(pipe_config); |
e29c22c0 | 9786 | return ERR_PTR(ret); |
ee7b9f93 | 9787 | } |
47f1c6c9 | 9788 | |
e2e1ed41 DV |
9789 | /* Computes which crtcs are affected and sets the relevant bits in the mask. For |
9790 | * simplicity we use the crtc's pipe number (because it's easier to obtain). */ | |
9791 | static void | |
9792 | intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes, | |
9793 | unsigned *prepare_pipes, unsigned *disable_pipes) | |
79e53945 JB |
9794 | { |
9795 | struct intel_crtc *intel_crtc; | |
e2e1ed41 DV |
9796 | struct drm_device *dev = crtc->dev; |
9797 | struct intel_encoder *encoder; | |
9798 | struct intel_connector *connector; | |
9799 | struct drm_crtc *tmp_crtc; | |
79e53945 | 9800 | |
e2e1ed41 | 9801 | *disable_pipes = *modeset_pipes = *prepare_pipes = 0; |
79e53945 | 9802 | |
e2e1ed41 DV |
9803 | /* Check which crtcs have changed outputs connected to them, these need |
9804 | * to be part of the prepare_pipes mask. We don't (yet) support global | |
9805 | * modeset across multiple crtcs, so modeset_pipes will only have one | |
9806 | * bit set at most. */ | |
9807 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
9808 | base.head) { | |
9809 | if (connector->base.encoder == &connector->new_encoder->base) | |
9810 | continue; | |
79e53945 | 9811 | |
e2e1ed41 DV |
9812 | if (connector->base.encoder) { |
9813 | tmp_crtc = connector->base.encoder->crtc; | |
9814 | ||
9815 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
9816 | } | |
9817 | ||
9818 | if (connector->new_encoder) | |
9819 | *prepare_pipes |= | |
9820 | 1 << connector->new_encoder->new_crtc->pipe; | |
79e53945 JB |
9821 | } |
9822 | ||
e2e1ed41 DV |
9823 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9824 | base.head) { | |
9825 | if (encoder->base.crtc == &encoder->new_crtc->base) | |
9826 | continue; | |
9827 | ||
9828 | if (encoder->base.crtc) { | |
9829 | tmp_crtc = encoder->base.crtc; | |
9830 | ||
9831 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
9832 | } | |
9833 | ||
9834 | if (encoder->new_crtc) | |
9835 | *prepare_pipes |= 1 << encoder->new_crtc->pipe; | |
80824003 JB |
9836 | } |
9837 | ||
7668851f | 9838 | /* Check for pipes that will be enabled/disabled ... */ |
d3fcc808 | 9839 | for_each_intel_crtc(dev, intel_crtc) { |
7668851f | 9840 | if (intel_crtc->base.enabled == intel_crtc->new_enabled) |
e2e1ed41 | 9841 | continue; |
7e7d76c3 | 9842 | |
7668851f | 9843 | if (!intel_crtc->new_enabled) |
e2e1ed41 | 9844 | *disable_pipes |= 1 << intel_crtc->pipe; |
7668851f VS |
9845 | else |
9846 | *prepare_pipes |= 1 << intel_crtc->pipe; | |
7e7d76c3 JB |
9847 | } |
9848 | ||
e2e1ed41 DV |
9849 | |
9850 | /* set_mode is also used to update properties on life display pipes. */ | |
9851 | intel_crtc = to_intel_crtc(crtc); | |
7668851f | 9852 | if (intel_crtc->new_enabled) |
e2e1ed41 DV |
9853 | *prepare_pipes |= 1 << intel_crtc->pipe; |
9854 | ||
b6c5164d DV |
9855 | /* |
9856 | * For simplicity do a full modeset on any pipe where the output routing | |
9857 | * changed. We could be more clever, but that would require us to be | |
9858 | * more careful with calling the relevant encoder->mode_set functions. | |
9859 | */ | |
e2e1ed41 DV |
9860 | if (*prepare_pipes) |
9861 | *modeset_pipes = *prepare_pipes; | |
9862 | ||
9863 | /* ... and mask these out. */ | |
9864 | *modeset_pipes &= ~(*disable_pipes); | |
9865 | *prepare_pipes &= ~(*disable_pipes); | |
b6c5164d DV |
9866 | |
9867 | /* | |
9868 | * HACK: We don't (yet) fully support global modesets. intel_set_config | |
9869 | * obies this rule, but the modeset restore mode of | |
9870 | * intel_modeset_setup_hw_state does not. | |
9871 | */ | |
9872 | *modeset_pipes &= 1 << intel_crtc->pipe; | |
9873 | *prepare_pipes &= 1 << intel_crtc->pipe; | |
e3641d3f DV |
9874 | |
9875 | DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n", | |
9876 | *modeset_pipes, *prepare_pipes, *disable_pipes); | |
47f1c6c9 | 9877 | } |
79e53945 | 9878 | |
ea9d758d | 9879 | static bool intel_crtc_in_use(struct drm_crtc *crtc) |
f6e5b160 | 9880 | { |
ea9d758d | 9881 | struct drm_encoder *encoder; |
f6e5b160 | 9882 | struct drm_device *dev = crtc->dev; |
f6e5b160 | 9883 | |
ea9d758d DV |
9884 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) |
9885 | if (encoder->crtc == crtc) | |
9886 | return true; | |
9887 | ||
9888 | return false; | |
9889 | } | |
9890 | ||
9891 | static void | |
9892 | intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes) | |
9893 | { | |
9894 | struct intel_encoder *intel_encoder; | |
9895 | struct intel_crtc *intel_crtc; | |
9896 | struct drm_connector *connector; | |
9897 | ||
9898 | list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list, | |
9899 | base.head) { | |
9900 | if (!intel_encoder->base.crtc) | |
9901 | continue; | |
9902 | ||
9903 | intel_crtc = to_intel_crtc(intel_encoder->base.crtc); | |
9904 | ||
9905 | if (prepare_pipes & (1 << intel_crtc->pipe)) | |
9906 | intel_encoder->connectors_active = false; | |
9907 | } | |
9908 | ||
9909 | intel_modeset_commit_output_state(dev); | |
9910 | ||
7668851f | 9911 | /* Double check state. */ |
d3fcc808 | 9912 | for_each_intel_crtc(dev, intel_crtc) { |
7668851f | 9913 | WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base)); |
7bd0a8e7 VS |
9914 | WARN_ON(intel_crtc->new_config && |
9915 | intel_crtc->new_config != &intel_crtc->config); | |
9916 | WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config); | |
ea9d758d DV |
9917 | } |
9918 | ||
9919 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
9920 | if (!connector->encoder || !connector->encoder->crtc) | |
9921 | continue; | |
9922 | ||
9923 | intel_crtc = to_intel_crtc(connector->encoder->crtc); | |
9924 | ||
9925 | if (prepare_pipes & (1 << intel_crtc->pipe)) { | |
68d34720 DV |
9926 | struct drm_property *dpms_property = |
9927 | dev->mode_config.dpms_property; | |
9928 | ||
ea9d758d | 9929 | connector->dpms = DRM_MODE_DPMS_ON; |
662595df | 9930 | drm_object_property_set_value(&connector->base, |
68d34720 DV |
9931 | dpms_property, |
9932 | DRM_MODE_DPMS_ON); | |
ea9d758d DV |
9933 | |
9934 | intel_encoder = to_intel_encoder(connector->encoder); | |
9935 | intel_encoder->connectors_active = true; | |
9936 | } | |
9937 | } | |
9938 | ||
9939 | } | |
9940 | ||
3bd26263 | 9941 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 9942 | { |
3bd26263 | 9943 | int diff; |
f1f644dc JB |
9944 | |
9945 | if (clock1 == clock2) | |
9946 | return true; | |
9947 | ||
9948 | if (!clock1 || !clock2) | |
9949 | return false; | |
9950 | ||
9951 | diff = abs(clock1 - clock2); | |
9952 | ||
9953 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
9954 | return true; | |
9955 | ||
9956 | return false; | |
9957 | } | |
9958 | ||
25c5b266 DV |
9959 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
9960 | list_for_each_entry((intel_crtc), \ | |
9961 | &(dev)->mode_config.crtc_list, \ | |
9962 | base.head) \ | |
0973f18f | 9963 | if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 9964 | |
0e8ffe1b | 9965 | static bool |
2fa2fe9a DV |
9966 | intel_pipe_config_compare(struct drm_device *dev, |
9967 | struct intel_crtc_config *current_config, | |
0e8ffe1b DV |
9968 | struct intel_crtc_config *pipe_config) |
9969 | { | |
66e985c0 DV |
9970 | #define PIPE_CONF_CHECK_X(name) \ |
9971 | if (current_config->name != pipe_config->name) { \ | |
9972 | DRM_ERROR("mismatch in " #name " " \ | |
9973 | "(expected 0x%08x, found 0x%08x)\n", \ | |
9974 | current_config->name, \ | |
9975 | pipe_config->name); \ | |
9976 | return false; \ | |
9977 | } | |
9978 | ||
08a24034 DV |
9979 | #define PIPE_CONF_CHECK_I(name) \ |
9980 | if (current_config->name != pipe_config->name) { \ | |
9981 | DRM_ERROR("mismatch in " #name " " \ | |
9982 | "(expected %i, found %i)\n", \ | |
9983 | current_config->name, \ | |
9984 | pipe_config->name); \ | |
9985 | return false; \ | |
88adfff1 DV |
9986 | } |
9987 | ||
1bd1bd80 DV |
9988 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
9989 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
6f02488e | 9990 | DRM_ERROR("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
9991 | "(expected %i, found %i)\n", \ |
9992 | current_config->name & (mask), \ | |
9993 | pipe_config->name & (mask)); \ | |
9994 | return false; \ | |
9995 | } | |
9996 | ||
5e550656 VS |
9997 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
9998 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
9999 | DRM_ERROR("mismatch in " #name " " \ | |
10000 | "(expected %i, found %i)\n", \ | |
10001 | current_config->name, \ | |
10002 | pipe_config->name); \ | |
10003 | return false; \ | |
10004 | } | |
10005 | ||
bb760063 DV |
10006 | #define PIPE_CONF_QUIRK(quirk) \ |
10007 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
10008 | ||
eccb140b DV |
10009 | PIPE_CONF_CHECK_I(cpu_transcoder); |
10010 | ||
08a24034 DV |
10011 | PIPE_CONF_CHECK_I(has_pch_encoder); |
10012 | PIPE_CONF_CHECK_I(fdi_lanes); | |
72419203 DV |
10013 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_m); |
10014 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_n); | |
10015 | PIPE_CONF_CHECK_I(fdi_m_n.link_m); | |
10016 | PIPE_CONF_CHECK_I(fdi_m_n.link_n); | |
10017 | PIPE_CONF_CHECK_I(fdi_m_n.tu); | |
08a24034 | 10018 | |
eb14cb74 VS |
10019 | PIPE_CONF_CHECK_I(has_dp_encoder); |
10020 | PIPE_CONF_CHECK_I(dp_m_n.gmch_m); | |
10021 | PIPE_CONF_CHECK_I(dp_m_n.gmch_n); | |
10022 | PIPE_CONF_CHECK_I(dp_m_n.link_m); | |
10023 | PIPE_CONF_CHECK_I(dp_m_n.link_n); | |
10024 | PIPE_CONF_CHECK_I(dp_m_n.tu); | |
10025 | ||
1bd1bd80 DV |
10026 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay); |
10027 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal); | |
10028 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start); | |
10029 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end); | |
10030 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start); | |
10031 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end); | |
10032 | ||
10033 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay); | |
10034 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal); | |
10035 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start); | |
10036 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end); | |
10037 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start); | |
10038 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end); | |
10039 | ||
c93f54cf | 10040 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 10041 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
b5a9fa09 DV |
10042 | if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || |
10043 | IS_VALLEYVIEW(dev)) | |
10044 | PIPE_CONF_CHECK_I(limited_color_range); | |
6c49f241 | 10045 | |
9ed109a7 DV |
10046 | PIPE_CONF_CHECK_I(has_audio); |
10047 | ||
1bd1bd80 DV |
10048 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
10049 | DRM_MODE_FLAG_INTERLACE); | |
10050 | ||
bb760063 DV |
10051 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
10052 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
10053 | DRM_MODE_FLAG_PHSYNC); | |
10054 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
10055 | DRM_MODE_FLAG_NHSYNC); | |
10056 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
10057 | DRM_MODE_FLAG_PVSYNC); | |
10058 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
10059 | DRM_MODE_FLAG_NVSYNC); | |
10060 | } | |
045ac3b5 | 10061 | |
37327abd VS |
10062 | PIPE_CONF_CHECK_I(pipe_src_w); |
10063 | PIPE_CONF_CHECK_I(pipe_src_h); | |
1bd1bd80 | 10064 | |
9953599b DV |
10065 | /* |
10066 | * FIXME: BIOS likes to set up a cloned config with lvds+external | |
10067 | * screen. Since we don't yet re-compute the pipe config when moving | |
10068 | * just the lvds port away to another pipe the sw tracking won't match. | |
10069 | * | |
10070 | * Proper atomic modesets with recomputed global state will fix this. | |
10071 | * Until then just don't check gmch state for inherited modes. | |
10072 | */ | |
10073 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) { | |
10074 | PIPE_CONF_CHECK_I(gmch_pfit.control); | |
10075 | /* pfit ratios are autocomputed by the hw on gen4+ */ | |
10076 | if (INTEL_INFO(dev)->gen < 4) | |
10077 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); | |
10078 | PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits); | |
10079 | } | |
10080 | ||
fd4daa9c CW |
10081 | PIPE_CONF_CHECK_I(pch_pfit.enabled); |
10082 | if (current_config->pch_pfit.enabled) { | |
10083 | PIPE_CONF_CHECK_I(pch_pfit.pos); | |
10084 | PIPE_CONF_CHECK_I(pch_pfit.size); | |
10085 | } | |
2fa2fe9a | 10086 | |
e59150dc JB |
10087 | /* BDW+ don't expose a synchronous way to read the state */ |
10088 | if (IS_HASWELL(dev)) | |
10089 | PIPE_CONF_CHECK_I(ips_enabled); | |
42db64ef | 10090 | |
282740f7 VS |
10091 | PIPE_CONF_CHECK_I(double_wide); |
10092 | ||
c0d43d62 | 10093 | PIPE_CONF_CHECK_I(shared_dpll); |
66e985c0 | 10094 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 10095 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
10096 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
10097 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
c0d43d62 | 10098 | |
42571aef VS |
10099 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
10100 | PIPE_CONF_CHECK_I(pipe_bpp); | |
10101 | ||
a9a7e98a JB |
10102 | PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock); |
10103 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); | |
5e550656 | 10104 | |
66e985c0 | 10105 | #undef PIPE_CONF_CHECK_X |
08a24034 | 10106 | #undef PIPE_CONF_CHECK_I |
1bd1bd80 | 10107 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 10108 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 10109 | #undef PIPE_CONF_QUIRK |
88adfff1 | 10110 | |
0e8ffe1b DV |
10111 | return true; |
10112 | } | |
10113 | ||
91d1b4bd DV |
10114 | static void |
10115 | check_connector_state(struct drm_device *dev) | |
8af6cf88 | 10116 | { |
8af6cf88 DV |
10117 | struct intel_connector *connector; |
10118 | ||
10119 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
10120 | base.head) { | |
10121 | /* This also checks the encoder/connector hw state with the | |
10122 | * ->get_hw_state callbacks. */ | |
10123 | intel_connector_check_state(connector); | |
10124 | ||
10125 | WARN(&connector->new_encoder->base != connector->base.encoder, | |
10126 | "connector's staged encoder doesn't match current encoder\n"); | |
10127 | } | |
91d1b4bd DV |
10128 | } |
10129 | ||
10130 | static void | |
10131 | check_encoder_state(struct drm_device *dev) | |
10132 | { | |
10133 | struct intel_encoder *encoder; | |
10134 | struct intel_connector *connector; | |
8af6cf88 DV |
10135 | |
10136 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
10137 | base.head) { | |
10138 | bool enabled = false; | |
10139 | bool active = false; | |
10140 | enum pipe pipe, tracked_pipe; | |
10141 | ||
10142 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
10143 | encoder->base.base.id, | |
8e329a03 | 10144 | encoder->base.name); |
8af6cf88 DV |
10145 | |
10146 | WARN(&encoder->new_crtc->base != encoder->base.crtc, | |
10147 | "encoder's stage crtc doesn't match current crtc\n"); | |
10148 | WARN(encoder->connectors_active && !encoder->base.crtc, | |
10149 | "encoder's active_connectors set, but no crtc\n"); | |
10150 | ||
10151 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
10152 | base.head) { | |
10153 | if (connector->base.encoder != &encoder->base) | |
10154 | continue; | |
10155 | enabled = true; | |
10156 | if (connector->base.dpms != DRM_MODE_DPMS_OFF) | |
10157 | active = true; | |
10158 | } | |
10159 | WARN(!!encoder->base.crtc != enabled, | |
10160 | "encoder's enabled state mismatch " | |
10161 | "(expected %i, found %i)\n", | |
10162 | !!encoder->base.crtc, enabled); | |
10163 | WARN(active && !encoder->base.crtc, | |
10164 | "active encoder with no crtc\n"); | |
10165 | ||
10166 | WARN(encoder->connectors_active != active, | |
10167 | "encoder's computed active state doesn't match tracked active state " | |
10168 | "(expected %i, found %i)\n", active, encoder->connectors_active); | |
10169 | ||
10170 | active = encoder->get_hw_state(encoder, &pipe); | |
10171 | WARN(active != encoder->connectors_active, | |
10172 | "encoder's hw state doesn't match sw tracking " | |
10173 | "(expected %i, found %i)\n", | |
10174 | encoder->connectors_active, active); | |
10175 | ||
10176 | if (!encoder->base.crtc) | |
10177 | continue; | |
10178 | ||
10179 | tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe; | |
10180 | WARN(active && pipe != tracked_pipe, | |
10181 | "active encoder's pipe doesn't match" | |
10182 | "(expected %i, found %i)\n", | |
10183 | tracked_pipe, pipe); | |
10184 | ||
10185 | } | |
91d1b4bd DV |
10186 | } |
10187 | ||
10188 | static void | |
10189 | check_crtc_state(struct drm_device *dev) | |
10190 | { | |
fbee40df | 10191 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
10192 | struct intel_crtc *crtc; |
10193 | struct intel_encoder *encoder; | |
10194 | struct intel_crtc_config pipe_config; | |
8af6cf88 | 10195 | |
d3fcc808 | 10196 | for_each_intel_crtc(dev, crtc) { |
8af6cf88 DV |
10197 | bool enabled = false; |
10198 | bool active = false; | |
10199 | ||
045ac3b5 JB |
10200 | memset(&pipe_config, 0, sizeof(pipe_config)); |
10201 | ||
8af6cf88 DV |
10202 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
10203 | crtc->base.base.id); | |
10204 | ||
10205 | WARN(crtc->active && !crtc->base.enabled, | |
10206 | "active crtc, but not enabled in sw tracking\n"); | |
10207 | ||
10208 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
10209 | base.head) { | |
10210 | if (encoder->base.crtc != &crtc->base) | |
10211 | continue; | |
10212 | enabled = true; | |
10213 | if (encoder->connectors_active) | |
10214 | active = true; | |
10215 | } | |
6c49f241 | 10216 | |
8af6cf88 DV |
10217 | WARN(active != crtc->active, |
10218 | "crtc's computed active state doesn't match tracked active state " | |
10219 | "(expected %i, found %i)\n", active, crtc->active); | |
10220 | WARN(enabled != crtc->base.enabled, | |
10221 | "crtc's computed enabled state doesn't match tracked enabled state " | |
10222 | "(expected %i, found %i)\n", enabled, crtc->base.enabled); | |
10223 | ||
0e8ffe1b DV |
10224 | active = dev_priv->display.get_pipe_config(crtc, |
10225 | &pipe_config); | |
d62cf62a DV |
10226 | |
10227 | /* hw state is inconsistent with the pipe A quirk */ | |
10228 | if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) | |
10229 | active = crtc->active; | |
10230 | ||
6c49f241 DV |
10231 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
10232 | base.head) { | |
3eaba51c | 10233 | enum pipe pipe; |
6c49f241 DV |
10234 | if (encoder->base.crtc != &crtc->base) |
10235 | continue; | |
1d37b689 | 10236 | if (encoder->get_hw_state(encoder, &pipe)) |
6c49f241 DV |
10237 | encoder->get_config(encoder, &pipe_config); |
10238 | } | |
10239 | ||
0e8ffe1b DV |
10240 | WARN(crtc->active != active, |
10241 | "crtc active state doesn't match with hw state " | |
10242 | "(expected %i, found %i)\n", crtc->active, active); | |
10243 | ||
c0b03411 DV |
10244 | if (active && |
10245 | !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) { | |
10246 | WARN(1, "pipe state doesn't match!\n"); | |
10247 | intel_dump_pipe_config(crtc, &pipe_config, | |
10248 | "[hw state]"); | |
10249 | intel_dump_pipe_config(crtc, &crtc->config, | |
10250 | "[sw state]"); | |
10251 | } | |
8af6cf88 DV |
10252 | } |
10253 | } | |
10254 | ||
91d1b4bd DV |
10255 | static void |
10256 | check_shared_dpll_state(struct drm_device *dev) | |
10257 | { | |
fbee40df | 10258 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
10259 | struct intel_crtc *crtc; |
10260 | struct intel_dpll_hw_state dpll_hw_state; | |
10261 | int i; | |
5358901f DV |
10262 | |
10263 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
10264 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
10265 | int enabled_crtcs = 0, active_crtcs = 0; | |
10266 | bool active; | |
10267 | ||
10268 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); | |
10269 | ||
10270 | DRM_DEBUG_KMS("%s\n", pll->name); | |
10271 | ||
10272 | active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); | |
10273 | ||
10274 | WARN(pll->active > pll->refcount, | |
10275 | "more active pll users than references: %i vs %i\n", | |
10276 | pll->active, pll->refcount); | |
10277 | WARN(pll->active && !pll->on, | |
10278 | "pll in active use but not on in sw tracking\n"); | |
35c95375 DV |
10279 | WARN(pll->on && !pll->active, |
10280 | "pll in on but not on in use in sw tracking\n"); | |
5358901f DV |
10281 | WARN(pll->on != active, |
10282 | "pll on state mismatch (expected %i, found %i)\n", | |
10283 | pll->on, active); | |
10284 | ||
d3fcc808 | 10285 | for_each_intel_crtc(dev, crtc) { |
5358901f DV |
10286 | if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll) |
10287 | enabled_crtcs++; | |
10288 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) | |
10289 | active_crtcs++; | |
10290 | } | |
10291 | WARN(pll->active != active_crtcs, | |
10292 | "pll active crtcs mismatch (expected %i, found %i)\n", | |
10293 | pll->active, active_crtcs); | |
10294 | WARN(pll->refcount != enabled_crtcs, | |
10295 | "pll enabled crtcs mismatch (expected %i, found %i)\n", | |
10296 | pll->refcount, enabled_crtcs); | |
66e985c0 DV |
10297 | |
10298 | WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state, | |
10299 | sizeof(dpll_hw_state)), | |
10300 | "pll hw state mismatch\n"); | |
5358901f | 10301 | } |
8af6cf88 DV |
10302 | } |
10303 | ||
91d1b4bd DV |
10304 | void |
10305 | intel_modeset_check_state(struct drm_device *dev) | |
10306 | { | |
10307 | check_connector_state(dev); | |
10308 | check_encoder_state(dev); | |
10309 | check_crtc_state(dev); | |
10310 | check_shared_dpll_state(dev); | |
10311 | } | |
10312 | ||
18442d08 VS |
10313 | void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config, |
10314 | int dotclock) | |
10315 | { | |
10316 | /* | |
10317 | * FDI already provided one idea for the dotclock. | |
10318 | * Yell if the encoder disagrees. | |
10319 | */ | |
241bfc38 | 10320 | WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock), |
18442d08 | 10321 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", |
241bfc38 | 10322 | pipe_config->adjusted_mode.crtc_clock, dotclock); |
18442d08 VS |
10323 | } |
10324 | ||
80715b2f VS |
10325 | static void update_scanline_offset(struct intel_crtc *crtc) |
10326 | { | |
10327 | struct drm_device *dev = crtc->base.dev; | |
10328 | ||
10329 | /* | |
10330 | * The scanline counter increments at the leading edge of hsync. | |
10331 | * | |
10332 | * On most platforms it starts counting from vtotal-1 on the | |
10333 | * first active line. That means the scanline counter value is | |
10334 | * always one less than what we would expect. Ie. just after | |
10335 | * start of vblank, which also occurs at start of hsync (on the | |
10336 | * last active line), the scanline counter will read vblank_start-1. | |
10337 | * | |
10338 | * On gen2 the scanline counter starts counting from 1 instead | |
10339 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
10340 | * to keep the value positive), instead of adding one. | |
10341 | * | |
10342 | * On HSW+ the behaviour of the scanline counter depends on the output | |
10343 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
10344 | * there's an extra 1 line difference. So we need to add two instead of | |
10345 | * one to the value. | |
10346 | */ | |
10347 | if (IS_GEN2(dev)) { | |
10348 | const struct drm_display_mode *mode = &crtc->config.adjusted_mode; | |
10349 | int vtotal; | |
10350 | ||
10351 | vtotal = mode->crtc_vtotal; | |
10352 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
10353 | vtotal /= 2; | |
10354 | ||
10355 | crtc->scanline_offset = vtotal - 1; | |
10356 | } else if (HAS_DDI(dev) && | |
10357 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) { | |
10358 | crtc->scanline_offset = 2; | |
10359 | } else | |
10360 | crtc->scanline_offset = 1; | |
10361 | } | |
10362 | ||
f30da187 DV |
10363 | static int __intel_set_mode(struct drm_crtc *crtc, |
10364 | struct drm_display_mode *mode, | |
10365 | int x, int y, struct drm_framebuffer *fb) | |
a6778b3c DV |
10366 | { |
10367 | struct drm_device *dev = crtc->dev; | |
fbee40df | 10368 | struct drm_i915_private *dev_priv = dev->dev_private; |
4b4b9238 | 10369 | struct drm_display_mode *saved_mode; |
b8cecdf5 | 10370 | struct intel_crtc_config *pipe_config = NULL; |
25c5b266 DV |
10371 | struct intel_crtc *intel_crtc; |
10372 | unsigned disable_pipes, prepare_pipes, modeset_pipes; | |
c0c36b94 | 10373 | int ret = 0; |
a6778b3c | 10374 | |
4b4b9238 | 10375 | saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL); |
c0c36b94 CW |
10376 | if (!saved_mode) |
10377 | return -ENOMEM; | |
a6778b3c | 10378 | |
e2e1ed41 | 10379 | intel_modeset_affected_pipes(crtc, &modeset_pipes, |
25c5b266 DV |
10380 | &prepare_pipes, &disable_pipes); |
10381 | ||
3ac18232 | 10382 | *saved_mode = crtc->mode; |
a6778b3c | 10383 | |
25c5b266 DV |
10384 | /* Hack: Because we don't (yet) support global modeset on multiple |
10385 | * crtcs, we don't keep track of the new mode for more than one crtc. | |
10386 | * Hence simply check whether any bit is set in modeset_pipes in all the | |
10387 | * pieces of code that are not yet converted to deal with mutliple crtcs | |
10388 | * changing their mode at the same time. */ | |
25c5b266 | 10389 | if (modeset_pipes) { |
4e53c2e0 | 10390 | pipe_config = intel_modeset_pipe_config(crtc, fb, mode); |
b8cecdf5 DV |
10391 | if (IS_ERR(pipe_config)) { |
10392 | ret = PTR_ERR(pipe_config); | |
10393 | pipe_config = NULL; | |
10394 | ||
3ac18232 | 10395 | goto out; |
25c5b266 | 10396 | } |
c0b03411 DV |
10397 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
10398 | "[modeset]"); | |
50741abc | 10399 | to_intel_crtc(crtc)->new_config = pipe_config; |
25c5b266 | 10400 | } |
a6778b3c | 10401 | |
30a970c6 JB |
10402 | /* |
10403 | * See if the config requires any additional preparation, e.g. | |
10404 | * to adjust global state with pipes off. We need to do this | |
10405 | * here so we can get the modeset_pipe updated config for the new | |
10406 | * mode set on this crtc. For other crtcs we need to use the | |
10407 | * adjusted_mode bits in the crtc directly. | |
10408 | */ | |
c164f833 | 10409 | if (IS_VALLEYVIEW(dev)) { |
2f2d7aa1 | 10410 | valleyview_modeset_global_pipes(dev, &prepare_pipes); |
30a970c6 | 10411 | |
c164f833 VS |
10412 | /* may have added more to prepare_pipes than we should */ |
10413 | prepare_pipes &= ~disable_pipes; | |
10414 | } | |
10415 | ||
460da916 DV |
10416 | for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc) |
10417 | intel_crtc_disable(&intel_crtc->base); | |
10418 | ||
ea9d758d DV |
10419 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
10420 | if (intel_crtc->base.enabled) | |
10421 | dev_priv->display.crtc_disable(&intel_crtc->base); | |
10422 | } | |
a6778b3c | 10423 | |
6c4c86f5 DV |
10424 | /* crtc->mode is already used by the ->mode_set callbacks, hence we need |
10425 | * to set it here already despite that we pass it down the callchain. | |
f6e5b160 | 10426 | */ |
b8cecdf5 | 10427 | if (modeset_pipes) { |
25c5b266 | 10428 | crtc->mode = *mode; |
b8cecdf5 DV |
10429 | /* mode_set/enable/disable functions rely on a correct pipe |
10430 | * config. */ | |
10431 | to_intel_crtc(crtc)->config = *pipe_config; | |
50741abc | 10432 | to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config; |
c326c0a9 VS |
10433 | |
10434 | /* | |
10435 | * Calculate and store various constants which | |
10436 | * are later needed by vblank and swap-completion | |
10437 | * timestamping. They are derived from true hwmode. | |
10438 | */ | |
10439 | drm_calc_timestamping_constants(crtc, | |
10440 | &pipe_config->adjusted_mode); | |
b8cecdf5 | 10441 | } |
7758a113 | 10442 | |
ea9d758d DV |
10443 | /* Only after disabling all output pipelines that will be changed can we |
10444 | * update the the output configuration. */ | |
10445 | intel_modeset_update_state(dev, prepare_pipes); | |
f6e5b160 | 10446 | |
47fab737 DV |
10447 | if (dev_priv->display.modeset_global_resources) |
10448 | dev_priv->display.modeset_global_resources(dev); | |
10449 | ||
a6778b3c DV |
10450 | /* Set up the DPLL and any encoders state that needs to adjust or depend |
10451 | * on the DPLL. | |
f6e5b160 | 10452 | */ |
25c5b266 | 10453 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { |
4c10794f DV |
10454 | struct drm_framebuffer *old_fb; |
10455 | ||
10456 | mutex_lock(&dev->struct_mutex); | |
10457 | ret = intel_pin_and_fence_fb_obj(dev, | |
10458 | to_intel_framebuffer(fb)->obj, | |
10459 | NULL); | |
10460 | if (ret != 0) { | |
10461 | DRM_ERROR("pin & fence failed\n"); | |
10462 | mutex_unlock(&dev->struct_mutex); | |
10463 | goto done; | |
10464 | } | |
10465 | old_fb = crtc->primary->fb; | |
10466 | if (old_fb) | |
10467 | intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj); | |
10468 | mutex_unlock(&dev->struct_mutex); | |
10469 | ||
10470 | crtc->primary->fb = fb; | |
10471 | crtc->x = x; | |
10472 | crtc->y = y; | |
10473 | ||
4271b753 DV |
10474 | ret = dev_priv->display.crtc_mode_set(&intel_crtc->base, |
10475 | x, y, fb); | |
c0c36b94 CW |
10476 | if (ret) |
10477 | goto done; | |
a6778b3c DV |
10478 | } |
10479 | ||
10480 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ | |
80715b2f VS |
10481 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
10482 | update_scanline_offset(intel_crtc); | |
10483 | ||
25c5b266 | 10484 | dev_priv->display.crtc_enable(&intel_crtc->base); |
80715b2f | 10485 | } |
a6778b3c | 10486 | |
a6778b3c DV |
10487 | /* FIXME: add subpixel order */ |
10488 | done: | |
4b4b9238 | 10489 | if (ret && crtc->enabled) |
3ac18232 | 10490 | crtc->mode = *saved_mode; |
a6778b3c | 10491 | |
3ac18232 | 10492 | out: |
b8cecdf5 | 10493 | kfree(pipe_config); |
3ac18232 | 10494 | kfree(saved_mode); |
a6778b3c | 10495 | return ret; |
f6e5b160 CW |
10496 | } |
10497 | ||
e7457a9a DL |
10498 | static int intel_set_mode(struct drm_crtc *crtc, |
10499 | struct drm_display_mode *mode, | |
10500 | int x, int y, struct drm_framebuffer *fb) | |
f30da187 DV |
10501 | { |
10502 | int ret; | |
10503 | ||
10504 | ret = __intel_set_mode(crtc, mode, x, y, fb); | |
10505 | ||
10506 | if (ret == 0) | |
10507 | intel_modeset_check_state(crtc->dev); | |
10508 | ||
10509 | return ret; | |
10510 | } | |
10511 | ||
c0c36b94 CW |
10512 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
10513 | { | |
f4510a27 | 10514 | intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb); |
c0c36b94 CW |
10515 | } |
10516 | ||
25c5b266 DV |
10517 | #undef for_each_intel_crtc_masked |
10518 | ||
d9e55608 DV |
10519 | static void intel_set_config_free(struct intel_set_config *config) |
10520 | { | |
10521 | if (!config) | |
10522 | return; | |
10523 | ||
1aa4b628 DV |
10524 | kfree(config->save_connector_encoders); |
10525 | kfree(config->save_encoder_crtcs); | |
7668851f | 10526 | kfree(config->save_crtc_enabled); |
d9e55608 DV |
10527 | kfree(config); |
10528 | } | |
10529 | ||
85f9eb71 DV |
10530 | static int intel_set_config_save_state(struct drm_device *dev, |
10531 | struct intel_set_config *config) | |
10532 | { | |
7668851f | 10533 | struct drm_crtc *crtc; |
85f9eb71 DV |
10534 | struct drm_encoder *encoder; |
10535 | struct drm_connector *connector; | |
10536 | int count; | |
10537 | ||
7668851f VS |
10538 | config->save_crtc_enabled = |
10539 | kcalloc(dev->mode_config.num_crtc, | |
10540 | sizeof(bool), GFP_KERNEL); | |
10541 | if (!config->save_crtc_enabled) | |
10542 | return -ENOMEM; | |
10543 | ||
1aa4b628 DV |
10544 | config->save_encoder_crtcs = |
10545 | kcalloc(dev->mode_config.num_encoder, | |
10546 | sizeof(struct drm_crtc *), GFP_KERNEL); | |
10547 | if (!config->save_encoder_crtcs) | |
85f9eb71 DV |
10548 | return -ENOMEM; |
10549 | ||
1aa4b628 DV |
10550 | config->save_connector_encoders = |
10551 | kcalloc(dev->mode_config.num_connector, | |
10552 | sizeof(struct drm_encoder *), GFP_KERNEL); | |
10553 | if (!config->save_connector_encoders) | |
85f9eb71 DV |
10554 | return -ENOMEM; |
10555 | ||
10556 | /* Copy data. Note that driver private data is not affected. | |
10557 | * Should anything bad happen only the expected state is | |
10558 | * restored, not the drivers personal bookkeeping. | |
10559 | */ | |
7668851f | 10560 | count = 0; |
70e1e0ec | 10561 | for_each_crtc(dev, crtc) { |
7668851f VS |
10562 | config->save_crtc_enabled[count++] = crtc->enabled; |
10563 | } | |
10564 | ||
85f9eb71 DV |
10565 | count = 0; |
10566 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
1aa4b628 | 10567 | config->save_encoder_crtcs[count++] = encoder->crtc; |
85f9eb71 DV |
10568 | } |
10569 | ||
10570 | count = 0; | |
10571 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
1aa4b628 | 10572 | config->save_connector_encoders[count++] = connector->encoder; |
85f9eb71 DV |
10573 | } |
10574 | ||
10575 | return 0; | |
10576 | } | |
10577 | ||
10578 | static void intel_set_config_restore_state(struct drm_device *dev, | |
10579 | struct intel_set_config *config) | |
10580 | { | |
7668851f | 10581 | struct intel_crtc *crtc; |
9a935856 DV |
10582 | struct intel_encoder *encoder; |
10583 | struct intel_connector *connector; | |
85f9eb71 DV |
10584 | int count; |
10585 | ||
7668851f | 10586 | count = 0; |
d3fcc808 | 10587 | for_each_intel_crtc(dev, crtc) { |
7668851f | 10588 | crtc->new_enabled = config->save_crtc_enabled[count++]; |
7bd0a8e7 VS |
10589 | |
10590 | if (crtc->new_enabled) | |
10591 | crtc->new_config = &crtc->config; | |
10592 | else | |
10593 | crtc->new_config = NULL; | |
7668851f VS |
10594 | } |
10595 | ||
85f9eb71 | 10596 | count = 0; |
9a935856 DV |
10597 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
10598 | encoder->new_crtc = | |
10599 | to_intel_crtc(config->save_encoder_crtcs[count++]); | |
85f9eb71 DV |
10600 | } |
10601 | ||
10602 | count = 0; | |
9a935856 DV |
10603 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { |
10604 | connector->new_encoder = | |
10605 | to_intel_encoder(config->save_connector_encoders[count++]); | |
85f9eb71 DV |
10606 | } |
10607 | } | |
10608 | ||
e3de42b6 | 10609 | static bool |
2e57f47d | 10610 | is_crtc_connector_off(struct drm_mode_set *set) |
e3de42b6 ID |
10611 | { |
10612 | int i; | |
10613 | ||
2e57f47d CW |
10614 | if (set->num_connectors == 0) |
10615 | return false; | |
10616 | ||
10617 | if (WARN_ON(set->connectors == NULL)) | |
10618 | return false; | |
10619 | ||
10620 | for (i = 0; i < set->num_connectors; i++) | |
10621 | if (set->connectors[i]->encoder && | |
10622 | set->connectors[i]->encoder->crtc == set->crtc && | |
10623 | set->connectors[i]->dpms != DRM_MODE_DPMS_ON) | |
e3de42b6 ID |
10624 | return true; |
10625 | ||
10626 | return false; | |
10627 | } | |
10628 | ||
5e2b584e DV |
10629 | static void |
10630 | intel_set_config_compute_mode_changes(struct drm_mode_set *set, | |
10631 | struct intel_set_config *config) | |
10632 | { | |
10633 | ||
10634 | /* We should be able to check here if the fb has the same properties | |
10635 | * and then just flip_or_move it */ | |
2e57f47d CW |
10636 | if (is_crtc_connector_off(set)) { |
10637 | config->mode_changed = true; | |
f4510a27 | 10638 | } else if (set->crtc->primary->fb != set->fb) { |
3b150f08 MR |
10639 | /* |
10640 | * If we have no fb, we can only flip as long as the crtc is | |
10641 | * active, otherwise we need a full mode set. The crtc may | |
10642 | * be active if we've only disabled the primary plane, or | |
10643 | * in fastboot situations. | |
10644 | */ | |
f4510a27 | 10645 | if (set->crtc->primary->fb == NULL) { |
319d9827 JB |
10646 | struct intel_crtc *intel_crtc = |
10647 | to_intel_crtc(set->crtc); | |
10648 | ||
3b150f08 | 10649 | if (intel_crtc->active) { |
319d9827 JB |
10650 | DRM_DEBUG_KMS("crtc has no fb, will flip\n"); |
10651 | config->fb_changed = true; | |
10652 | } else { | |
10653 | DRM_DEBUG_KMS("inactive crtc, full mode set\n"); | |
10654 | config->mode_changed = true; | |
10655 | } | |
5e2b584e DV |
10656 | } else if (set->fb == NULL) { |
10657 | config->mode_changed = true; | |
72f4901e | 10658 | } else if (set->fb->pixel_format != |
f4510a27 | 10659 | set->crtc->primary->fb->pixel_format) { |
5e2b584e | 10660 | config->mode_changed = true; |
e3de42b6 | 10661 | } else { |
5e2b584e | 10662 | config->fb_changed = true; |
e3de42b6 | 10663 | } |
5e2b584e DV |
10664 | } |
10665 | ||
835c5873 | 10666 | if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y)) |
5e2b584e DV |
10667 | config->fb_changed = true; |
10668 | ||
10669 | if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) { | |
10670 | DRM_DEBUG_KMS("modes are different, full mode set\n"); | |
10671 | drm_mode_debug_printmodeline(&set->crtc->mode); | |
10672 | drm_mode_debug_printmodeline(set->mode); | |
10673 | config->mode_changed = true; | |
10674 | } | |
a1d95703 CW |
10675 | |
10676 | DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n", | |
10677 | set->crtc->base.id, config->mode_changed, config->fb_changed); | |
5e2b584e DV |
10678 | } |
10679 | ||
2e431051 | 10680 | static int |
9a935856 DV |
10681 | intel_modeset_stage_output_state(struct drm_device *dev, |
10682 | struct drm_mode_set *set, | |
10683 | struct intel_set_config *config) | |
50f56119 | 10684 | { |
9a935856 DV |
10685 | struct intel_connector *connector; |
10686 | struct intel_encoder *encoder; | |
7668851f | 10687 | struct intel_crtc *crtc; |
f3f08572 | 10688 | int ro; |
50f56119 | 10689 | |
9abdda74 | 10690 | /* The upper layers ensure that we either disable a crtc or have a list |
9a935856 DV |
10691 | * of connectors. For paranoia, double-check this. */ |
10692 | WARN_ON(!set->fb && (set->num_connectors != 0)); | |
10693 | WARN_ON(set->fb && (set->num_connectors == 0)); | |
10694 | ||
9a935856 DV |
10695 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
10696 | base.head) { | |
10697 | /* Otherwise traverse passed in connector list and get encoders | |
10698 | * for them. */ | |
50f56119 | 10699 | for (ro = 0; ro < set->num_connectors; ro++) { |
9a935856 DV |
10700 | if (set->connectors[ro] == &connector->base) { |
10701 | connector->new_encoder = connector->encoder; | |
50f56119 DV |
10702 | break; |
10703 | } | |
10704 | } | |
10705 | ||
9a935856 DV |
10706 | /* If we disable the crtc, disable all its connectors. Also, if |
10707 | * the connector is on the changing crtc but not on the new | |
10708 | * connector list, disable it. */ | |
10709 | if ((!set->fb || ro == set->num_connectors) && | |
10710 | connector->base.encoder && | |
10711 | connector->base.encoder->crtc == set->crtc) { | |
10712 | connector->new_encoder = NULL; | |
10713 | ||
10714 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n", | |
10715 | connector->base.base.id, | |
c23cc417 | 10716 | connector->base.name); |
9a935856 DV |
10717 | } |
10718 | ||
10719 | ||
10720 | if (&connector->new_encoder->base != connector->base.encoder) { | |
50f56119 | 10721 | DRM_DEBUG_KMS("encoder changed, full mode switch\n"); |
5e2b584e | 10722 | config->mode_changed = true; |
50f56119 DV |
10723 | } |
10724 | } | |
9a935856 | 10725 | /* connector->new_encoder is now updated for all connectors. */ |
50f56119 | 10726 | |
9a935856 | 10727 | /* Update crtc of enabled connectors. */ |
9a935856 DV |
10728 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
10729 | base.head) { | |
7668851f VS |
10730 | struct drm_crtc *new_crtc; |
10731 | ||
9a935856 | 10732 | if (!connector->new_encoder) |
50f56119 DV |
10733 | continue; |
10734 | ||
9a935856 | 10735 | new_crtc = connector->new_encoder->base.crtc; |
50f56119 DV |
10736 | |
10737 | for (ro = 0; ro < set->num_connectors; ro++) { | |
9a935856 | 10738 | if (set->connectors[ro] == &connector->base) |
50f56119 DV |
10739 | new_crtc = set->crtc; |
10740 | } | |
10741 | ||
10742 | /* Make sure the new CRTC will work with the encoder */ | |
14509916 TR |
10743 | if (!drm_encoder_crtc_ok(&connector->new_encoder->base, |
10744 | new_crtc)) { | |
5e2b584e | 10745 | return -EINVAL; |
50f56119 | 10746 | } |
9a935856 DV |
10747 | connector->encoder->new_crtc = to_intel_crtc(new_crtc); |
10748 | ||
10749 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n", | |
10750 | connector->base.base.id, | |
c23cc417 | 10751 | connector->base.name, |
9a935856 DV |
10752 | new_crtc->base.id); |
10753 | } | |
10754 | ||
10755 | /* Check for any encoders that needs to be disabled. */ | |
10756 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
10757 | base.head) { | |
5a65f358 | 10758 | int num_connectors = 0; |
9a935856 DV |
10759 | list_for_each_entry(connector, |
10760 | &dev->mode_config.connector_list, | |
10761 | base.head) { | |
10762 | if (connector->new_encoder == encoder) { | |
10763 | WARN_ON(!connector->new_encoder->new_crtc); | |
5a65f358 | 10764 | num_connectors++; |
9a935856 DV |
10765 | } |
10766 | } | |
5a65f358 PZ |
10767 | |
10768 | if (num_connectors == 0) | |
10769 | encoder->new_crtc = NULL; | |
10770 | else if (num_connectors > 1) | |
10771 | return -EINVAL; | |
10772 | ||
9a935856 DV |
10773 | /* Only now check for crtc changes so we don't miss encoders |
10774 | * that will be disabled. */ | |
10775 | if (&encoder->new_crtc->base != encoder->base.crtc) { | |
50f56119 | 10776 | DRM_DEBUG_KMS("crtc changed, full mode switch\n"); |
5e2b584e | 10777 | config->mode_changed = true; |
50f56119 DV |
10778 | } |
10779 | } | |
9a935856 | 10780 | /* Now we've also updated encoder->new_crtc for all encoders. */ |
50f56119 | 10781 | |
d3fcc808 | 10782 | for_each_intel_crtc(dev, crtc) { |
7668851f VS |
10783 | crtc->new_enabled = false; |
10784 | ||
10785 | list_for_each_entry(encoder, | |
10786 | &dev->mode_config.encoder_list, | |
10787 | base.head) { | |
10788 | if (encoder->new_crtc == crtc) { | |
10789 | crtc->new_enabled = true; | |
10790 | break; | |
10791 | } | |
10792 | } | |
10793 | ||
10794 | if (crtc->new_enabled != crtc->base.enabled) { | |
10795 | DRM_DEBUG_KMS("crtc %sabled, full mode switch\n", | |
10796 | crtc->new_enabled ? "en" : "dis"); | |
10797 | config->mode_changed = true; | |
10798 | } | |
7bd0a8e7 VS |
10799 | |
10800 | if (crtc->new_enabled) | |
10801 | crtc->new_config = &crtc->config; | |
10802 | else | |
10803 | crtc->new_config = NULL; | |
7668851f VS |
10804 | } |
10805 | ||
2e431051 DV |
10806 | return 0; |
10807 | } | |
10808 | ||
7d00a1f5 VS |
10809 | static void disable_crtc_nofb(struct intel_crtc *crtc) |
10810 | { | |
10811 | struct drm_device *dev = crtc->base.dev; | |
10812 | struct intel_encoder *encoder; | |
10813 | struct intel_connector *connector; | |
10814 | ||
10815 | DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n", | |
10816 | pipe_name(crtc->pipe)); | |
10817 | ||
10818 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { | |
10819 | if (connector->new_encoder && | |
10820 | connector->new_encoder->new_crtc == crtc) | |
10821 | connector->new_encoder = NULL; | |
10822 | } | |
10823 | ||
10824 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { | |
10825 | if (encoder->new_crtc == crtc) | |
10826 | encoder->new_crtc = NULL; | |
10827 | } | |
10828 | ||
10829 | crtc->new_enabled = false; | |
7bd0a8e7 | 10830 | crtc->new_config = NULL; |
7d00a1f5 VS |
10831 | } |
10832 | ||
2e431051 DV |
10833 | static int intel_crtc_set_config(struct drm_mode_set *set) |
10834 | { | |
10835 | struct drm_device *dev; | |
2e431051 DV |
10836 | struct drm_mode_set save_set; |
10837 | struct intel_set_config *config; | |
10838 | int ret; | |
2e431051 | 10839 | |
8d3e375e DV |
10840 | BUG_ON(!set); |
10841 | BUG_ON(!set->crtc); | |
10842 | BUG_ON(!set->crtc->helper_private); | |
2e431051 | 10843 | |
7e53f3a4 DV |
10844 | /* Enforce sane interface api - has been abused by the fb helper. */ |
10845 | BUG_ON(!set->mode && set->fb); | |
10846 | BUG_ON(set->fb && set->num_connectors == 0); | |
431e50f7 | 10847 | |
2e431051 DV |
10848 | if (set->fb) { |
10849 | DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n", | |
10850 | set->crtc->base.id, set->fb->base.id, | |
10851 | (int)set->num_connectors, set->x, set->y); | |
10852 | } else { | |
10853 | DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id); | |
2e431051 DV |
10854 | } |
10855 | ||
10856 | dev = set->crtc->dev; | |
10857 | ||
10858 | ret = -ENOMEM; | |
10859 | config = kzalloc(sizeof(*config), GFP_KERNEL); | |
10860 | if (!config) | |
10861 | goto out_config; | |
10862 | ||
10863 | ret = intel_set_config_save_state(dev, config); | |
10864 | if (ret) | |
10865 | goto out_config; | |
10866 | ||
10867 | save_set.crtc = set->crtc; | |
10868 | save_set.mode = &set->crtc->mode; | |
10869 | save_set.x = set->crtc->x; | |
10870 | save_set.y = set->crtc->y; | |
f4510a27 | 10871 | save_set.fb = set->crtc->primary->fb; |
2e431051 DV |
10872 | |
10873 | /* Compute whether we need a full modeset, only an fb base update or no | |
10874 | * change at all. In the future we might also check whether only the | |
10875 | * mode changed, e.g. for LVDS where we only change the panel fitter in | |
10876 | * such cases. */ | |
10877 | intel_set_config_compute_mode_changes(set, config); | |
10878 | ||
9a935856 | 10879 | ret = intel_modeset_stage_output_state(dev, set, config); |
2e431051 DV |
10880 | if (ret) |
10881 | goto fail; | |
10882 | ||
5e2b584e | 10883 | if (config->mode_changed) { |
c0c36b94 CW |
10884 | ret = intel_set_mode(set->crtc, set->mode, |
10885 | set->x, set->y, set->fb); | |
5e2b584e | 10886 | } else if (config->fb_changed) { |
3b150f08 MR |
10887 | struct drm_i915_private *dev_priv = dev->dev_private; |
10888 | struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc); | |
10889 | ||
4878cae2 VS |
10890 | intel_crtc_wait_for_pending_flips(set->crtc); |
10891 | ||
4f660f49 | 10892 | ret = intel_pipe_set_base(set->crtc, |
94352cf9 | 10893 | set->x, set->y, set->fb); |
3b150f08 MR |
10894 | |
10895 | /* | |
10896 | * We need to make sure the primary plane is re-enabled if it | |
10897 | * has previously been turned off. | |
10898 | */ | |
10899 | if (!intel_crtc->primary_enabled && ret == 0) { | |
10900 | WARN_ON(!intel_crtc->active); | |
10901 | intel_enable_primary_hw_plane(dev_priv, intel_crtc->plane, | |
10902 | intel_crtc->pipe); | |
10903 | } | |
10904 | ||
7ca51a3a JB |
10905 | /* |
10906 | * In the fastboot case this may be our only check of the | |
10907 | * state after boot. It would be better to only do it on | |
10908 | * the first update, but we don't have a nice way of doing that | |
10909 | * (and really, set_config isn't used much for high freq page | |
10910 | * flipping, so increasing its cost here shouldn't be a big | |
10911 | * deal). | |
10912 | */ | |
d330a953 | 10913 | if (i915.fastboot && ret == 0) |
7ca51a3a | 10914 | intel_modeset_check_state(set->crtc->dev); |
50f56119 DV |
10915 | } |
10916 | ||
2d05eae1 | 10917 | if (ret) { |
bf67dfeb DV |
10918 | DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n", |
10919 | set->crtc->base.id, ret); | |
50f56119 | 10920 | fail: |
2d05eae1 | 10921 | intel_set_config_restore_state(dev, config); |
50f56119 | 10922 | |
7d00a1f5 VS |
10923 | /* |
10924 | * HACK: if the pipe was on, but we didn't have a framebuffer, | |
10925 | * force the pipe off to avoid oopsing in the modeset code | |
10926 | * due to fb==NULL. This should only happen during boot since | |
10927 | * we don't yet reconstruct the FB from the hardware state. | |
10928 | */ | |
10929 | if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb) | |
10930 | disable_crtc_nofb(to_intel_crtc(save_set.crtc)); | |
10931 | ||
2d05eae1 CW |
10932 | /* Try to restore the config */ |
10933 | if (config->mode_changed && | |
10934 | intel_set_mode(save_set.crtc, save_set.mode, | |
10935 | save_set.x, save_set.y, save_set.fb)) | |
10936 | DRM_ERROR("failed to restore config after modeset failure\n"); | |
10937 | } | |
50f56119 | 10938 | |
d9e55608 DV |
10939 | out_config: |
10940 | intel_set_config_free(config); | |
50f56119 DV |
10941 | return ret; |
10942 | } | |
f6e5b160 CW |
10943 | |
10944 | static const struct drm_crtc_funcs intel_crtc_funcs = { | |
f6e5b160 CW |
10945 | .cursor_set = intel_crtc_cursor_set, |
10946 | .cursor_move = intel_crtc_cursor_move, | |
10947 | .gamma_set = intel_crtc_gamma_set, | |
50f56119 | 10948 | .set_config = intel_crtc_set_config, |
f6e5b160 CW |
10949 | .destroy = intel_crtc_destroy, |
10950 | .page_flip = intel_crtc_page_flip, | |
10951 | }; | |
10952 | ||
79f689aa PZ |
10953 | static void intel_cpu_pll_init(struct drm_device *dev) |
10954 | { | |
affa9354 | 10955 | if (HAS_DDI(dev)) |
79f689aa PZ |
10956 | intel_ddi_pll_init(dev); |
10957 | } | |
10958 | ||
5358901f DV |
10959 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
10960 | struct intel_shared_dpll *pll, | |
10961 | struct intel_dpll_hw_state *hw_state) | |
ee7b9f93 | 10962 | { |
5358901f | 10963 | uint32_t val; |
ee7b9f93 | 10964 | |
5358901f | 10965 | val = I915_READ(PCH_DPLL(pll->id)); |
66e985c0 DV |
10966 | hw_state->dpll = val; |
10967 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); | |
10968 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); | |
5358901f DV |
10969 | |
10970 | return val & DPLL_VCO_ENABLE; | |
10971 | } | |
10972 | ||
15bdd4cf DV |
10973 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
10974 | struct intel_shared_dpll *pll) | |
10975 | { | |
10976 | I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0); | |
10977 | I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1); | |
10978 | } | |
10979 | ||
e7b903d2 DV |
10980 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
10981 | struct intel_shared_dpll *pll) | |
10982 | { | |
e7b903d2 | 10983 | /* PCH refclock must be enabled first */ |
89eff4be | 10984 | ibx_assert_pch_refclk_enabled(dev_priv); |
e7b903d2 | 10985 | |
15bdd4cf DV |
10986 | I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll); |
10987 | ||
10988 | /* Wait for the clocks to stabilize. */ | |
10989 | POSTING_READ(PCH_DPLL(pll->id)); | |
10990 | udelay(150); | |
10991 | ||
10992 | /* The pixel multiplier can only be updated once the | |
10993 | * DPLL is enabled and the clocks are stable. | |
10994 | * | |
10995 | * So write it again. | |
10996 | */ | |
10997 | I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll); | |
10998 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
10999 | udelay(200); |
11000 | } | |
11001 | ||
11002 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, | |
11003 | struct intel_shared_dpll *pll) | |
11004 | { | |
11005 | struct drm_device *dev = dev_priv->dev; | |
11006 | struct intel_crtc *crtc; | |
e7b903d2 DV |
11007 | |
11008 | /* Make sure no transcoder isn't still depending on us. */ | |
d3fcc808 | 11009 | for_each_intel_crtc(dev, crtc) { |
e7b903d2 DV |
11010 | if (intel_crtc_to_shared_dpll(crtc) == pll) |
11011 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); | |
ee7b9f93 JB |
11012 | } |
11013 | ||
15bdd4cf DV |
11014 | I915_WRITE(PCH_DPLL(pll->id), 0); |
11015 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
11016 | udelay(200); |
11017 | } | |
11018 | ||
46edb027 DV |
11019 | static char *ibx_pch_dpll_names[] = { |
11020 | "PCH DPLL A", | |
11021 | "PCH DPLL B", | |
11022 | }; | |
11023 | ||
7c74ade1 | 11024 | static void ibx_pch_dpll_init(struct drm_device *dev) |
ee7b9f93 | 11025 | { |
e7b903d2 | 11026 | struct drm_i915_private *dev_priv = dev->dev_private; |
ee7b9f93 JB |
11027 | int i; |
11028 | ||
7c74ade1 | 11029 | dev_priv->num_shared_dpll = 2; |
ee7b9f93 | 11030 | |
e72f9fbf | 11031 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
46edb027 DV |
11032 | dev_priv->shared_dplls[i].id = i; |
11033 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; | |
15bdd4cf | 11034 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
e7b903d2 DV |
11035 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
11036 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; | |
5358901f DV |
11037 | dev_priv->shared_dplls[i].get_hw_state = |
11038 | ibx_pch_dpll_get_hw_state; | |
ee7b9f93 JB |
11039 | } |
11040 | } | |
11041 | ||
7c74ade1 DV |
11042 | static void intel_shared_dpll_init(struct drm_device *dev) |
11043 | { | |
e7b903d2 | 11044 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c74ade1 DV |
11045 | |
11046 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
11047 | ibx_pch_dpll_init(dev); | |
11048 | else | |
11049 | dev_priv->num_shared_dpll = 0; | |
11050 | ||
11051 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); | |
7c74ade1 DV |
11052 | } |
11053 | ||
465c120c MR |
11054 | static int |
11055 | intel_primary_plane_disable(struct drm_plane *plane) | |
11056 | { | |
11057 | struct drm_device *dev = plane->dev; | |
11058 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11059 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
11060 | struct intel_crtc *intel_crtc; | |
11061 | ||
11062 | if (!plane->fb) | |
11063 | return 0; | |
11064 | ||
11065 | BUG_ON(!plane->crtc); | |
11066 | ||
11067 | intel_crtc = to_intel_crtc(plane->crtc); | |
11068 | ||
11069 | /* | |
11070 | * Even though we checked plane->fb above, it's still possible that | |
11071 | * the primary plane has been implicitly disabled because the crtc | |
11072 | * coordinates given weren't visible, or because we detected | |
11073 | * that it was 100% covered by a sprite plane. Or, the CRTC may be | |
11074 | * off and we've set a fb, but haven't actually turned on the CRTC yet. | |
11075 | * In either case, we need to unpin the FB and let the fb pointer get | |
11076 | * updated, but otherwise we don't need to touch the hardware. | |
11077 | */ | |
11078 | if (!intel_crtc->primary_enabled) | |
11079 | goto disable_unpin; | |
11080 | ||
11081 | intel_crtc_wait_for_pending_flips(plane->crtc); | |
11082 | intel_disable_primary_hw_plane(dev_priv, intel_plane->plane, | |
11083 | intel_plane->pipe); | |
11084 | ||
11085 | disable_unpin: | |
11086 | intel_unpin_fb_obj(to_intel_framebuffer(plane->fb)->obj); | |
11087 | plane->fb = NULL; | |
11088 | ||
11089 | return 0; | |
11090 | } | |
11091 | ||
11092 | static int | |
11093 | intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc, | |
11094 | struct drm_framebuffer *fb, int crtc_x, int crtc_y, | |
11095 | unsigned int crtc_w, unsigned int crtc_h, | |
11096 | uint32_t src_x, uint32_t src_y, | |
11097 | uint32_t src_w, uint32_t src_h) | |
11098 | { | |
11099 | struct drm_device *dev = crtc->dev; | |
11100 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11101 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11102 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
11103 | struct drm_rect dest = { | |
11104 | /* integer pixels */ | |
11105 | .x1 = crtc_x, | |
11106 | .y1 = crtc_y, | |
11107 | .x2 = crtc_x + crtc_w, | |
11108 | .y2 = crtc_y + crtc_h, | |
11109 | }; | |
11110 | struct drm_rect src = { | |
11111 | /* 16.16 fixed point */ | |
11112 | .x1 = src_x, | |
11113 | .y1 = src_y, | |
11114 | .x2 = src_x + src_w, | |
11115 | .y2 = src_y + src_h, | |
11116 | }; | |
11117 | const struct drm_rect clip = { | |
11118 | /* integer pixels */ | |
11119 | .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0, | |
11120 | .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0, | |
11121 | }; | |
11122 | bool visible; | |
11123 | int ret; | |
11124 | ||
11125 | ret = drm_plane_helper_check_update(plane, crtc, fb, | |
11126 | &src, &dest, &clip, | |
11127 | DRM_PLANE_HELPER_NO_SCALING, | |
11128 | DRM_PLANE_HELPER_NO_SCALING, | |
11129 | false, true, &visible); | |
11130 | ||
11131 | if (ret) | |
11132 | return ret; | |
11133 | ||
11134 | /* | |
11135 | * If the CRTC isn't enabled, we're just pinning the framebuffer, | |
11136 | * updating the fb pointer, and returning without touching the | |
11137 | * hardware. This allows us to later do a drmModeSetCrtc with fb=-1 to | |
11138 | * turn on the display with all planes setup as desired. | |
11139 | */ | |
11140 | if (!crtc->enabled) { | |
11141 | /* | |
11142 | * If we already called setplane while the crtc was disabled, | |
11143 | * we may have an fb pinned; unpin it. | |
11144 | */ | |
11145 | if (plane->fb) | |
11146 | intel_unpin_fb_obj(to_intel_framebuffer(plane->fb)->obj); | |
11147 | ||
11148 | /* Pin and return without programming hardware */ | |
11149 | return intel_pin_and_fence_fb_obj(dev, | |
11150 | to_intel_framebuffer(fb)->obj, | |
11151 | NULL); | |
11152 | } | |
11153 | ||
11154 | intel_crtc_wait_for_pending_flips(crtc); | |
11155 | ||
11156 | /* | |
11157 | * If clipping results in a non-visible primary plane, we'll disable | |
11158 | * the primary plane. Note that this is a bit different than what | |
11159 | * happens if userspace explicitly disables the plane by passing fb=0 | |
11160 | * because plane->fb still gets set and pinned. | |
11161 | */ | |
11162 | if (!visible) { | |
11163 | /* | |
11164 | * Try to pin the new fb first so that we can bail out if we | |
11165 | * fail. | |
11166 | */ | |
11167 | if (plane->fb != fb) { | |
11168 | ret = intel_pin_and_fence_fb_obj(dev, | |
11169 | to_intel_framebuffer(fb)->obj, | |
11170 | NULL); | |
11171 | if (ret) | |
11172 | return ret; | |
11173 | } | |
11174 | ||
11175 | if (intel_crtc->primary_enabled) | |
11176 | intel_disable_primary_hw_plane(dev_priv, | |
11177 | intel_plane->plane, | |
11178 | intel_plane->pipe); | |
11179 | ||
11180 | ||
11181 | if (plane->fb != fb) | |
11182 | if (plane->fb) | |
11183 | intel_unpin_fb_obj(to_intel_framebuffer(plane->fb)->obj); | |
11184 | ||
11185 | return 0; | |
11186 | } | |
11187 | ||
11188 | ret = intel_pipe_set_base(crtc, src.x1, src.y1, fb); | |
11189 | if (ret) | |
11190 | return ret; | |
11191 | ||
11192 | if (!intel_crtc->primary_enabled) | |
11193 | intel_enable_primary_hw_plane(dev_priv, intel_crtc->plane, | |
11194 | intel_crtc->pipe); | |
11195 | ||
11196 | return 0; | |
11197 | } | |
11198 | ||
11199 | static void intel_primary_plane_destroy(struct drm_plane *plane) | |
11200 | { | |
11201 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
11202 | drm_plane_cleanup(plane); | |
11203 | kfree(intel_plane); | |
11204 | } | |
11205 | ||
11206 | static const struct drm_plane_funcs intel_primary_plane_funcs = { | |
11207 | .update_plane = intel_primary_plane_setplane, | |
11208 | .disable_plane = intel_primary_plane_disable, | |
11209 | .destroy = intel_primary_plane_destroy, | |
11210 | }; | |
11211 | ||
11212 | static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, | |
11213 | int pipe) | |
11214 | { | |
11215 | struct intel_plane *primary; | |
11216 | const uint32_t *intel_primary_formats; | |
11217 | int num_formats; | |
11218 | ||
11219 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
11220 | if (primary == NULL) | |
11221 | return NULL; | |
11222 | ||
11223 | primary->can_scale = false; | |
11224 | primary->max_downscale = 1; | |
11225 | primary->pipe = pipe; | |
11226 | primary->plane = pipe; | |
11227 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) | |
11228 | primary->plane = !pipe; | |
11229 | ||
11230 | if (INTEL_INFO(dev)->gen <= 3) { | |
11231 | intel_primary_formats = intel_primary_formats_gen2; | |
11232 | num_formats = ARRAY_SIZE(intel_primary_formats_gen2); | |
11233 | } else { | |
11234 | intel_primary_formats = intel_primary_formats_gen4; | |
11235 | num_formats = ARRAY_SIZE(intel_primary_formats_gen4); | |
11236 | } | |
11237 | ||
11238 | drm_universal_plane_init(dev, &primary->base, 0, | |
11239 | &intel_primary_plane_funcs, | |
11240 | intel_primary_formats, num_formats, | |
11241 | DRM_PLANE_TYPE_PRIMARY); | |
11242 | return &primary->base; | |
11243 | } | |
11244 | ||
b358d0a6 | 11245 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 11246 | { |
fbee40df | 11247 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 11248 | struct intel_crtc *intel_crtc; |
465c120c MR |
11249 | struct drm_plane *primary; |
11250 | int i, ret; | |
79e53945 | 11251 | |
955382f3 | 11252 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
11253 | if (intel_crtc == NULL) |
11254 | return; | |
11255 | ||
465c120c MR |
11256 | primary = intel_primary_plane_create(dev, pipe); |
11257 | ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, | |
11258 | NULL, &intel_crtc_funcs); | |
11259 | if (ret) { | |
11260 | drm_plane_cleanup(primary); | |
11261 | kfree(intel_crtc); | |
11262 | return; | |
11263 | } | |
79e53945 JB |
11264 | |
11265 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
11266 | for (i = 0; i < 256; i++) { |
11267 | intel_crtc->lut_r[i] = i; | |
11268 | intel_crtc->lut_g[i] = i; | |
11269 | intel_crtc->lut_b[i] = i; | |
11270 | } | |
11271 | ||
1f1c2e24 VS |
11272 | /* |
11273 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port | |
11274 | * is hooked to plane B. Hence we want plane A feeding pipe B. | |
11275 | */ | |
80824003 JB |
11276 | intel_crtc->pipe = pipe; |
11277 | intel_crtc->plane = pipe; | |
3a77c4c4 | 11278 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
28c97730 | 11279 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 11280 | intel_crtc->plane = !pipe; |
80824003 JB |
11281 | } |
11282 | ||
4b0e333e CW |
11283 | intel_crtc->cursor_base = ~0; |
11284 | intel_crtc->cursor_cntl = ~0; | |
11285 | ||
8d7849db VS |
11286 | init_waitqueue_head(&intel_crtc->vbl_wait); |
11287 | ||
22fd0fab JB |
11288 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
11289 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
11290 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
11291 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
11292 | ||
79e53945 | 11293 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 DV |
11294 | |
11295 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); | |
79e53945 JB |
11296 | } |
11297 | ||
752aa88a JB |
11298 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
11299 | { | |
11300 | struct drm_encoder *encoder = connector->base.encoder; | |
6e9f798d | 11301 | struct drm_device *dev = connector->base.dev; |
752aa88a | 11302 | |
51fd371b | 11303 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a JB |
11304 | |
11305 | if (!encoder) | |
11306 | return INVALID_PIPE; | |
11307 | ||
11308 | return to_intel_crtc(encoder->crtc)->pipe; | |
11309 | } | |
11310 | ||
08d7b3d1 | 11311 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 11312 | struct drm_file *file) |
08d7b3d1 | 11313 | { |
08d7b3d1 | 11314 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
c05422d5 DV |
11315 | struct drm_mode_object *drmmode_obj; |
11316 | struct intel_crtc *crtc; | |
08d7b3d1 | 11317 | |
1cff8f6b DV |
11318 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
11319 | return -ENODEV; | |
08d7b3d1 | 11320 | |
c05422d5 DV |
11321 | drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, |
11322 | DRM_MODE_OBJECT_CRTC); | |
08d7b3d1 | 11323 | |
c05422d5 | 11324 | if (!drmmode_obj) { |
08d7b3d1 | 11325 | DRM_ERROR("no such CRTC id\n"); |
3f2c2057 | 11326 | return -ENOENT; |
08d7b3d1 CW |
11327 | } |
11328 | ||
c05422d5 DV |
11329 | crtc = to_intel_crtc(obj_to_crtc(drmmode_obj)); |
11330 | pipe_from_crtc_id->pipe = crtc->pipe; | |
08d7b3d1 | 11331 | |
c05422d5 | 11332 | return 0; |
08d7b3d1 CW |
11333 | } |
11334 | ||
66a9278e | 11335 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 11336 | { |
66a9278e DV |
11337 | struct drm_device *dev = encoder->base.dev; |
11338 | struct intel_encoder *source_encoder; | |
79e53945 | 11339 | int index_mask = 0; |
79e53945 JB |
11340 | int entry = 0; |
11341 | ||
66a9278e DV |
11342 | list_for_each_entry(source_encoder, |
11343 | &dev->mode_config.encoder_list, base.head) { | |
bc079e8b | 11344 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
11345 | index_mask |= (1 << entry); |
11346 | ||
79e53945 JB |
11347 | entry++; |
11348 | } | |
4ef69c7a | 11349 | |
79e53945 JB |
11350 | return index_mask; |
11351 | } | |
11352 | ||
4d302442 CW |
11353 | static bool has_edp_a(struct drm_device *dev) |
11354 | { | |
11355 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11356 | ||
11357 | if (!IS_MOBILE(dev)) | |
11358 | return false; | |
11359 | ||
11360 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
11361 | return false; | |
11362 | ||
e3589908 | 11363 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
11364 | return false; |
11365 | ||
11366 | return true; | |
11367 | } | |
11368 | ||
ba0fbca4 DL |
11369 | const char *intel_output_name(int output) |
11370 | { | |
11371 | static const char *names[] = { | |
11372 | [INTEL_OUTPUT_UNUSED] = "Unused", | |
11373 | [INTEL_OUTPUT_ANALOG] = "Analog", | |
11374 | [INTEL_OUTPUT_DVO] = "DVO", | |
11375 | [INTEL_OUTPUT_SDVO] = "SDVO", | |
11376 | [INTEL_OUTPUT_LVDS] = "LVDS", | |
11377 | [INTEL_OUTPUT_TVOUT] = "TV", | |
11378 | [INTEL_OUTPUT_HDMI] = "HDMI", | |
11379 | [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort", | |
11380 | [INTEL_OUTPUT_EDP] = "eDP", | |
11381 | [INTEL_OUTPUT_DSI] = "DSI", | |
11382 | [INTEL_OUTPUT_UNKNOWN] = "Unknown", | |
11383 | }; | |
11384 | ||
11385 | if (output < 0 || output >= ARRAY_SIZE(names) || !names[output]) | |
11386 | return "Invalid"; | |
11387 | ||
11388 | return names[output]; | |
11389 | } | |
11390 | ||
79e53945 JB |
11391 | static void intel_setup_outputs(struct drm_device *dev) |
11392 | { | |
725e30ad | 11393 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 11394 | struct intel_encoder *encoder; |
cb0953d7 | 11395 | bool dpd_is_edp = false; |
79e53945 | 11396 | |
c9093354 | 11397 | intel_lvds_init(dev); |
79e53945 | 11398 | |
27da3bdf | 11399 | if (!IS_ULT(dev) && !IS_CHERRYVIEW(dev) && dev_priv->vbt.int_crt_support) |
79935fca | 11400 | intel_crt_init(dev); |
cb0953d7 | 11401 | |
affa9354 | 11402 | if (HAS_DDI(dev)) { |
0e72a5b5 ED |
11403 | int found; |
11404 | ||
11405 | /* Haswell uses DDI functions to detect digital outputs */ | |
11406 | found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED; | |
11407 | /* DDI A only supports eDP */ | |
11408 | if (found) | |
11409 | intel_ddi_init(dev, PORT_A); | |
11410 | ||
11411 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
11412 | * register */ | |
11413 | found = I915_READ(SFUSE_STRAP); | |
11414 | ||
11415 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
11416 | intel_ddi_init(dev, PORT_B); | |
11417 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
11418 | intel_ddi_init(dev, PORT_C); | |
11419 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
11420 | intel_ddi_init(dev, PORT_D); | |
11421 | } else if (HAS_PCH_SPLIT(dev)) { | |
cb0953d7 | 11422 | int found; |
5d8a7752 | 11423 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
270b3042 DV |
11424 | |
11425 | if (has_edp_a(dev)) | |
11426 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 11427 | |
dc0fa718 | 11428 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 11429 | /* PCH SDVOB multiplex with HDMIB */ |
eef4eacb | 11430 | found = intel_sdvo_init(dev, PCH_SDVOB, true); |
30ad48b7 | 11431 | if (!found) |
e2debe91 | 11432 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 11433 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 11434 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
11435 | } |
11436 | ||
dc0fa718 | 11437 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 11438 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 11439 | |
dc0fa718 | 11440 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 11441 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 11442 | |
5eb08b69 | 11443 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 11444 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 11445 | |
270b3042 | 11446 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 11447 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
4a87d65d | 11448 | } else if (IS_VALLEYVIEW(dev)) { |
585a94b8 AB |
11449 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) { |
11450 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB, | |
11451 | PORT_B); | |
11452 | if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED) | |
11453 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B); | |
11454 | } | |
11455 | ||
6f6005a5 JB |
11456 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) { |
11457 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC, | |
11458 | PORT_C); | |
11459 | if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED) | |
5d8a7752 | 11460 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C); |
6f6005a5 | 11461 | } |
19c03924 | 11462 | |
9418c1f1 VS |
11463 | if (IS_CHERRYVIEW(dev)) { |
11464 | if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) { | |
11465 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID, | |
11466 | PORT_D); | |
11467 | if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED) | |
11468 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D); | |
11469 | } | |
11470 | } | |
11471 | ||
3cfca973 | 11472 | intel_dsi_init(dev); |
103a196f | 11473 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
27185ae1 | 11474 | bool found = false; |
7d57382e | 11475 | |
e2debe91 | 11476 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 11477 | DRM_DEBUG_KMS("probing SDVOB\n"); |
e2debe91 | 11478 | found = intel_sdvo_init(dev, GEN3_SDVOB, true); |
b01f2c3a JB |
11479 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
11480 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); | |
e2debe91 | 11481 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 11482 | } |
27185ae1 | 11483 | |
e7281eab | 11484 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 11485 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 11486 | } |
13520b05 KH |
11487 | |
11488 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 11489 | |
e2debe91 | 11490 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 11491 | DRM_DEBUG_KMS("probing SDVOC\n"); |
e2debe91 | 11492 | found = intel_sdvo_init(dev, GEN3_SDVOC, false); |
b01f2c3a | 11493 | } |
27185ae1 | 11494 | |
e2debe91 | 11495 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 11496 | |
b01f2c3a JB |
11497 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
11498 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); | |
e2debe91 | 11499 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 11500 | } |
e7281eab | 11501 | if (SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 11502 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 11503 | } |
27185ae1 | 11504 | |
b01f2c3a | 11505 | if (SUPPORTS_INTEGRATED_DP(dev) && |
e7281eab | 11506 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 11507 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 11508 | } else if (IS_GEN2(dev)) |
79e53945 JB |
11509 | intel_dvo_init(dev); |
11510 | ||
103a196f | 11511 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
11512 | intel_tv_init(dev); |
11513 | ||
4ef69c7a CW |
11514 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
11515 | encoder->base.possible_crtcs = encoder->crtc_mask; | |
11516 | encoder->base.possible_clones = | |
66a9278e | 11517 | intel_encoder_clones(encoder); |
79e53945 | 11518 | } |
47356eb6 | 11519 | |
dde86e2d | 11520 | intel_init_pch_refclk(dev); |
270b3042 DV |
11521 | |
11522 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
11523 | } |
11524 | ||
11525 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
11526 | { | |
11527 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
79e53945 | 11528 | |
ef2d633e DV |
11529 | drm_framebuffer_cleanup(fb); |
11530 | WARN_ON(!intel_fb->obj->framebuffer_references--); | |
11531 | drm_gem_object_unreference_unlocked(&intel_fb->obj->base); | |
79e53945 JB |
11532 | kfree(intel_fb); |
11533 | } | |
11534 | ||
11535 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 11536 | struct drm_file *file, |
79e53945 JB |
11537 | unsigned int *handle) |
11538 | { | |
11539 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 11540 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 11541 | |
05394f39 | 11542 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
11543 | } |
11544 | ||
11545 | static const struct drm_framebuffer_funcs intel_fb_funcs = { | |
11546 | .destroy = intel_user_framebuffer_destroy, | |
11547 | .create_handle = intel_user_framebuffer_create_handle, | |
11548 | }; | |
11549 | ||
b5ea642a DV |
11550 | static int intel_framebuffer_init(struct drm_device *dev, |
11551 | struct intel_framebuffer *intel_fb, | |
11552 | struct drm_mode_fb_cmd2 *mode_cmd, | |
11553 | struct drm_i915_gem_object *obj) | |
79e53945 | 11554 | { |
a57ce0b2 | 11555 | int aligned_height; |
a35cdaa0 | 11556 | int pitch_limit; |
79e53945 JB |
11557 | int ret; |
11558 | ||
dd4916c5 DV |
11559 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
11560 | ||
c16ed4be CW |
11561 | if (obj->tiling_mode == I915_TILING_Y) { |
11562 | DRM_DEBUG("hardware does not support tiling Y\n"); | |
57cd6508 | 11563 | return -EINVAL; |
c16ed4be | 11564 | } |
57cd6508 | 11565 | |
c16ed4be CW |
11566 | if (mode_cmd->pitches[0] & 63) { |
11567 | DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n", | |
11568 | mode_cmd->pitches[0]); | |
57cd6508 | 11569 | return -EINVAL; |
c16ed4be | 11570 | } |
57cd6508 | 11571 | |
a35cdaa0 CW |
11572 | if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) { |
11573 | pitch_limit = 32*1024; | |
11574 | } else if (INTEL_INFO(dev)->gen >= 4) { | |
11575 | if (obj->tiling_mode) | |
11576 | pitch_limit = 16*1024; | |
11577 | else | |
11578 | pitch_limit = 32*1024; | |
11579 | } else if (INTEL_INFO(dev)->gen >= 3) { | |
11580 | if (obj->tiling_mode) | |
11581 | pitch_limit = 8*1024; | |
11582 | else | |
11583 | pitch_limit = 16*1024; | |
11584 | } else | |
11585 | /* XXX DSPC is limited to 4k tiled */ | |
11586 | pitch_limit = 8*1024; | |
11587 | ||
11588 | if (mode_cmd->pitches[0] > pitch_limit) { | |
11589 | DRM_DEBUG("%s pitch (%d) must be at less than %d\n", | |
11590 | obj->tiling_mode ? "tiled" : "linear", | |
11591 | mode_cmd->pitches[0], pitch_limit); | |
5d7bd705 | 11592 | return -EINVAL; |
c16ed4be | 11593 | } |
5d7bd705 VS |
11594 | |
11595 | if (obj->tiling_mode != I915_TILING_NONE && | |
c16ed4be CW |
11596 | mode_cmd->pitches[0] != obj->stride) { |
11597 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
11598 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 11599 | return -EINVAL; |
c16ed4be | 11600 | } |
5d7bd705 | 11601 | |
57779d06 | 11602 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 11603 | switch (mode_cmd->pixel_format) { |
57779d06 | 11604 | case DRM_FORMAT_C8: |
04b3924d VS |
11605 | case DRM_FORMAT_RGB565: |
11606 | case DRM_FORMAT_XRGB8888: | |
11607 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
11608 | break; |
11609 | case DRM_FORMAT_XRGB1555: | |
11610 | case DRM_FORMAT_ARGB1555: | |
c16ed4be | 11611 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
11612 | DRM_DEBUG("unsupported pixel format: %s\n", |
11613 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 11614 | return -EINVAL; |
c16ed4be | 11615 | } |
57779d06 VS |
11616 | break; |
11617 | case DRM_FORMAT_XBGR8888: | |
11618 | case DRM_FORMAT_ABGR8888: | |
04b3924d VS |
11619 | case DRM_FORMAT_XRGB2101010: |
11620 | case DRM_FORMAT_ARGB2101010: | |
57779d06 VS |
11621 | case DRM_FORMAT_XBGR2101010: |
11622 | case DRM_FORMAT_ABGR2101010: | |
c16ed4be | 11623 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
11624 | DRM_DEBUG("unsupported pixel format: %s\n", |
11625 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 11626 | return -EINVAL; |
c16ed4be | 11627 | } |
b5626747 | 11628 | break; |
04b3924d VS |
11629 | case DRM_FORMAT_YUYV: |
11630 | case DRM_FORMAT_UYVY: | |
11631 | case DRM_FORMAT_YVYU: | |
11632 | case DRM_FORMAT_VYUY: | |
c16ed4be | 11633 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
11634 | DRM_DEBUG("unsupported pixel format: %s\n", |
11635 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 11636 | return -EINVAL; |
c16ed4be | 11637 | } |
57cd6508 CW |
11638 | break; |
11639 | default: | |
4ee62c76 VS |
11640 | DRM_DEBUG("unsupported pixel format: %s\n", |
11641 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
11642 | return -EINVAL; |
11643 | } | |
11644 | ||
90f9a336 VS |
11645 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
11646 | if (mode_cmd->offsets[0] != 0) | |
11647 | return -EINVAL; | |
11648 | ||
a57ce0b2 JB |
11649 | aligned_height = intel_align_height(dev, mode_cmd->height, |
11650 | obj->tiling_mode); | |
53155c0a DV |
11651 | /* FIXME drm helper for size checks (especially planar formats)? */ |
11652 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) | |
11653 | return -EINVAL; | |
11654 | ||
c7d73f6a DV |
11655 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
11656 | intel_fb->obj = obj; | |
80075d49 | 11657 | intel_fb->obj->framebuffer_references++; |
c7d73f6a | 11658 | |
79e53945 JB |
11659 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
11660 | if (ret) { | |
11661 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
11662 | return ret; | |
11663 | } | |
11664 | ||
79e53945 JB |
11665 | return 0; |
11666 | } | |
11667 | ||
79e53945 JB |
11668 | static struct drm_framebuffer * |
11669 | intel_user_framebuffer_create(struct drm_device *dev, | |
11670 | struct drm_file *filp, | |
308e5bcb | 11671 | struct drm_mode_fb_cmd2 *mode_cmd) |
79e53945 | 11672 | { |
05394f39 | 11673 | struct drm_i915_gem_object *obj; |
79e53945 | 11674 | |
308e5bcb JB |
11675 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
11676 | mode_cmd->handles[0])); | |
c8725226 | 11677 | if (&obj->base == NULL) |
cce13ff7 | 11678 | return ERR_PTR(-ENOENT); |
79e53945 | 11679 | |
d2dff872 | 11680 | return intel_framebuffer_create(dev, mode_cmd, obj); |
79e53945 JB |
11681 | } |
11682 | ||
4520f53a | 11683 | #ifndef CONFIG_DRM_I915_FBDEV |
0632fef6 | 11684 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
4520f53a DV |
11685 | { |
11686 | } | |
11687 | #endif | |
11688 | ||
79e53945 | 11689 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 11690 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 11691 | .output_poll_changed = intel_fbdev_output_poll_changed, |
79e53945 JB |
11692 | }; |
11693 | ||
e70236a8 JB |
11694 | /* Set up chip specific display functions */ |
11695 | static void intel_init_display(struct drm_device *dev) | |
11696 | { | |
11697 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11698 | ||
ee9300bb DV |
11699 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
11700 | dev_priv->display.find_dpll = g4x_find_best_dpll; | |
ef9348c8 CML |
11701 | else if (IS_CHERRYVIEW(dev)) |
11702 | dev_priv->display.find_dpll = chv_find_best_dpll; | |
ee9300bb DV |
11703 | else if (IS_VALLEYVIEW(dev)) |
11704 | dev_priv->display.find_dpll = vlv_find_best_dpll; | |
11705 | else if (IS_PINEVIEW(dev)) | |
11706 | dev_priv->display.find_dpll = pnv_find_best_dpll; | |
11707 | else | |
11708 | dev_priv->display.find_dpll = i9xx_find_best_dpll; | |
11709 | ||
affa9354 | 11710 | if (HAS_DDI(dev)) { |
0e8ffe1b | 11711 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
4c6baa59 | 11712 | dev_priv->display.get_plane_config = ironlake_get_plane_config; |
09b4ddf9 | 11713 | dev_priv->display.crtc_mode_set = haswell_crtc_mode_set; |
4f771f10 PZ |
11714 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
11715 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
6441ab5f | 11716 | dev_priv->display.off = haswell_crtc_off; |
262ca2b0 MR |
11717 | dev_priv->display.update_primary_plane = |
11718 | ironlake_update_primary_plane; | |
09b4ddf9 | 11719 | } else if (HAS_PCH_SPLIT(dev)) { |
0e8ffe1b | 11720 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
4c6baa59 | 11721 | dev_priv->display.get_plane_config = ironlake_get_plane_config; |
f564048e | 11722 | dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set; |
76e5a89c DV |
11723 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
11724 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
ee7b9f93 | 11725 | dev_priv->display.off = ironlake_crtc_off; |
262ca2b0 MR |
11726 | dev_priv->display.update_primary_plane = |
11727 | ironlake_update_primary_plane; | |
89b667f8 JB |
11728 | } else if (IS_VALLEYVIEW(dev)) { |
11729 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
1ad292b5 | 11730 | dev_priv->display.get_plane_config = i9xx_get_plane_config; |
89b667f8 JB |
11731 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
11732 | dev_priv->display.crtc_enable = valleyview_crtc_enable; | |
11733 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
11734 | dev_priv->display.off = i9xx_crtc_off; | |
262ca2b0 MR |
11735 | dev_priv->display.update_primary_plane = |
11736 | i9xx_update_primary_plane; | |
f564048e | 11737 | } else { |
0e8ffe1b | 11738 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
1ad292b5 | 11739 | dev_priv->display.get_plane_config = i9xx_get_plane_config; |
f564048e | 11740 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
76e5a89c DV |
11741 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
11742 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
ee7b9f93 | 11743 | dev_priv->display.off = i9xx_crtc_off; |
262ca2b0 MR |
11744 | dev_priv->display.update_primary_plane = |
11745 | i9xx_update_primary_plane; | |
f564048e | 11746 | } |
e70236a8 | 11747 | |
e70236a8 | 11748 | /* Returns the core display clock speed */ |
25eb05fc JB |
11749 | if (IS_VALLEYVIEW(dev)) |
11750 | dev_priv->display.get_display_clock_speed = | |
11751 | valleyview_get_display_clock_speed; | |
11752 | else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) | |
e70236a8 JB |
11753 | dev_priv->display.get_display_clock_speed = |
11754 | i945_get_display_clock_speed; | |
11755 | else if (IS_I915G(dev)) | |
11756 | dev_priv->display.get_display_clock_speed = | |
11757 | i915_get_display_clock_speed; | |
257a7ffc | 11758 | else if (IS_I945GM(dev) || IS_845G(dev)) |
e70236a8 JB |
11759 | dev_priv->display.get_display_clock_speed = |
11760 | i9xx_misc_get_display_clock_speed; | |
257a7ffc DV |
11761 | else if (IS_PINEVIEW(dev)) |
11762 | dev_priv->display.get_display_clock_speed = | |
11763 | pnv_get_display_clock_speed; | |
e70236a8 JB |
11764 | else if (IS_I915GM(dev)) |
11765 | dev_priv->display.get_display_clock_speed = | |
11766 | i915gm_get_display_clock_speed; | |
11767 | else if (IS_I865G(dev)) | |
11768 | dev_priv->display.get_display_clock_speed = | |
11769 | i865_get_display_clock_speed; | |
f0f8a9ce | 11770 | else if (IS_I85X(dev)) |
e70236a8 JB |
11771 | dev_priv->display.get_display_clock_speed = |
11772 | i855_get_display_clock_speed; | |
11773 | else /* 852, 830 */ | |
11774 | dev_priv->display.get_display_clock_speed = | |
11775 | i830_get_display_clock_speed; | |
11776 | ||
7f8a8569 | 11777 | if (HAS_PCH_SPLIT(dev)) { |
f00a3ddf | 11778 | if (IS_GEN5(dev)) { |
674cf967 | 11779 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
e0dac65e | 11780 | dev_priv->display.write_eld = ironlake_write_eld; |
1398261a | 11781 | } else if (IS_GEN6(dev)) { |
674cf967 | 11782 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
e0dac65e | 11783 | dev_priv->display.write_eld = ironlake_write_eld; |
9a952a0d PZ |
11784 | dev_priv->display.modeset_global_resources = |
11785 | snb_modeset_global_resources; | |
357555c0 JB |
11786 | } else if (IS_IVYBRIDGE(dev)) { |
11787 | /* FIXME: detect B0+ stepping and use auto training */ | |
11788 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
e0dac65e | 11789 | dev_priv->display.write_eld = ironlake_write_eld; |
01a415fd DV |
11790 | dev_priv->display.modeset_global_resources = |
11791 | ivb_modeset_global_resources; | |
4e0bbc31 | 11792 | } else if (IS_HASWELL(dev) || IS_GEN8(dev)) { |
c82e4d26 | 11793 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
83358c85 | 11794 | dev_priv->display.write_eld = haswell_write_eld; |
d6dd9eb1 DV |
11795 | dev_priv->display.modeset_global_resources = |
11796 | haswell_modeset_global_resources; | |
a0e63c22 | 11797 | } |
6067aaea | 11798 | } else if (IS_G4X(dev)) { |
e0dac65e | 11799 | dev_priv->display.write_eld = g4x_write_eld; |
30a970c6 JB |
11800 | } else if (IS_VALLEYVIEW(dev)) { |
11801 | dev_priv->display.modeset_global_resources = | |
11802 | valleyview_modeset_global_resources; | |
9ca2fe73 | 11803 | dev_priv->display.write_eld = ironlake_write_eld; |
e70236a8 | 11804 | } |
8c9f3aaf JB |
11805 | |
11806 | /* Default just returns -ENODEV to indicate unsupported */ | |
11807 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
11808 | ||
11809 | switch (INTEL_INFO(dev)->gen) { | |
11810 | case 2: | |
11811 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
11812 | break; | |
11813 | ||
11814 | case 3: | |
11815 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
11816 | break; | |
11817 | ||
11818 | case 4: | |
11819 | case 5: | |
11820 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
11821 | break; | |
11822 | ||
11823 | case 6: | |
11824 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
11825 | break; | |
7c9017e5 | 11826 | case 7: |
4e0bbc31 | 11827 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ |
7c9017e5 JB |
11828 | dev_priv->display.queue_flip = intel_gen7_queue_flip; |
11829 | break; | |
8c9f3aaf | 11830 | } |
7bd688cd JN |
11831 | |
11832 | intel_panel_init_backlight_funcs(dev); | |
e70236a8 JB |
11833 | } |
11834 | ||
b690e96c JB |
11835 | /* |
11836 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
11837 | * resume, or other times. This quirk makes sure that's the case for | |
11838 | * affected systems. | |
11839 | */ | |
0206e353 | 11840 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
11841 | { |
11842 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11843 | ||
11844 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 11845 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
11846 | } |
11847 | ||
435793df KP |
11848 | /* |
11849 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
11850 | */ | |
11851 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
11852 | { | |
11853 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11854 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 11855 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
11856 | } |
11857 | ||
4dca20ef | 11858 | /* |
5a15ab5b CE |
11859 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
11860 | * brightness value | |
4dca20ef CE |
11861 | */ |
11862 | static void quirk_invert_brightness(struct drm_device *dev) | |
11863 | { | |
11864 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11865 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 11866 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
11867 | } |
11868 | ||
b690e96c JB |
11869 | struct intel_quirk { |
11870 | int device; | |
11871 | int subsystem_vendor; | |
11872 | int subsystem_device; | |
11873 | void (*hook)(struct drm_device *dev); | |
11874 | }; | |
11875 | ||
5f85f176 EE |
11876 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
11877 | struct intel_dmi_quirk { | |
11878 | void (*hook)(struct drm_device *dev); | |
11879 | const struct dmi_system_id (*dmi_id_list)[]; | |
11880 | }; | |
11881 | ||
11882 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
11883 | { | |
11884 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
11885 | return 1; | |
11886 | } | |
11887 | ||
11888 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
11889 | { | |
11890 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
11891 | { | |
11892 | .callback = intel_dmi_reverse_brightness, | |
11893 | .ident = "NCR Corporation", | |
11894 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
11895 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
11896 | }, | |
11897 | }, | |
11898 | { } /* terminating entry */ | |
11899 | }, | |
11900 | .hook = quirk_invert_brightness, | |
11901 | }, | |
11902 | }; | |
11903 | ||
c43b5634 | 11904 | static struct intel_quirk intel_quirks[] = { |
b690e96c | 11905 | /* HP Mini needs pipe A force quirk (LP: #322104) */ |
0206e353 | 11906 | { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, |
b690e96c | 11907 | |
b690e96c JB |
11908 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
11909 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
11910 | ||
b690e96c JB |
11911 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
11912 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
11913 | ||
435793df KP |
11914 | /* Lenovo U160 cannot use SSC on LVDS */ |
11915 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
11916 | |
11917 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
11918 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 11919 | |
be505f64 AH |
11920 | /* Acer Aspire 5734Z must invert backlight brightness */ |
11921 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
11922 | ||
11923 | /* Acer/eMachines G725 */ | |
11924 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
11925 | ||
11926 | /* Acer/eMachines e725 */ | |
11927 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
11928 | ||
11929 | /* Acer/Packard Bell NCL20 */ | |
11930 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
11931 | ||
11932 | /* Acer Aspire 4736Z */ | |
11933 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
11934 | |
11935 | /* Acer Aspire 5336 */ | |
11936 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
b690e96c JB |
11937 | }; |
11938 | ||
11939 | static void intel_init_quirks(struct drm_device *dev) | |
11940 | { | |
11941 | struct pci_dev *d = dev->pdev; | |
11942 | int i; | |
11943 | ||
11944 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
11945 | struct intel_quirk *q = &intel_quirks[i]; | |
11946 | ||
11947 | if (d->device == q->device && | |
11948 | (d->subsystem_vendor == q->subsystem_vendor || | |
11949 | q->subsystem_vendor == PCI_ANY_ID) && | |
11950 | (d->subsystem_device == q->subsystem_device || | |
11951 | q->subsystem_device == PCI_ANY_ID)) | |
11952 | q->hook(dev); | |
11953 | } | |
5f85f176 EE |
11954 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
11955 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
11956 | intel_dmi_quirks[i].hook(dev); | |
11957 | } | |
b690e96c JB |
11958 | } |
11959 | ||
9cce37f4 JB |
11960 | /* Disable the VGA plane that we never use */ |
11961 | static void i915_disable_vga(struct drm_device *dev) | |
11962 | { | |
11963 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11964 | u8 sr1; | |
766aa1c4 | 11965 | u32 vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 | 11966 | |
2b37c616 | 11967 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
9cce37f4 | 11968 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 11969 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
11970 | sr1 = inb(VGA_SR_DATA); |
11971 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
11972 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
11973 | udelay(300); | |
11974 | ||
11975 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); | |
11976 | POSTING_READ(vga_reg); | |
11977 | } | |
11978 | ||
f817586c DV |
11979 | void intel_modeset_init_hw(struct drm_device *dev) |
11980 | { | |
a8f78b58 ED |
11981 | intel_prepare_ddi(dev); |
11982 | ||
f817586c DV |
11983 | intel_init_clock_gating(dev); |
11984 | ||
5382f5f3 | 11985 | intel_reset_dpio(dev); |
40e9cf64 | 11986 | |
8090c6b9 | 11987 | intel_enable_gt_powersave(dev); |
f817586c DV |
11988 | } |
11989 | ||
7d708ee4 ID |
11990 | void intel_modeset_suspend_hw(struct drm_device *dev) |
11991 | { | |
11992 | intel_suspend_hw(dev); | |
11993 | } | |
11994 | ||
79e53945 JB |
11995 | void intel_modeset_init(struct drm_device *dev) |
11996 | { | |
652c393a | 11997 | struct drm_i915_private *dev_priv = dev->dev_private; |
1fe47785 | 11998 | int sprite, ret; |
8cc87b75 | 11999 | enum pipe pipe; |
46f297fb | 12000 | struct intel_crtc *crtc; |
79e53945 JB |
12001 | |
12002 | drm_mode_config_init(dev); | |
12003 | ||
12004 | dev->mode_config.min_width = 0; | |
12005 | dev->mode_config.min_height = 0; | |
12006 | ||
019d96cb DA |
12007 | dev->mode_config.preferred_depth = 24; |
12008 | dev->mode_config.prefer_shadow = 1; | |
12009 | ||
e6ecefaa | 12010 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 12011 | |
b690e96c JB |
12012 | intel_init_quirks(dev); |
12013 | ||
1fa61106 ED |
12014 | intel_init_pm(dev); |
12015 | ||
e3c74757 BW |
12016 | if (INTEL_INFO(dev)->num_pipes == 0) |
12017 | return; | |
12018 | ||
e70236a8 JB |
12019 | intel_init_display(dev); |
12020 | ||
a6c45cf0 CW |
12021 | if (IS_GEN2(dev)) { |
12022 | dev->mode_config.max_width = 2048; | |
12023 | dev->mode_config.max_height = 2048; | |
12024 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
12025 | dev->mode_config.max_width = 4096; |
12026 | dev->mode_config.max_height = 4096; | |
79e53945 | 12027 | } else { |
a6c45cf0 CW |
12028 | dev->mode_config.max_width = 8192; |
12029 | dev->mode_config.max_height = 8192; | |
79e53945 | 12030 | } |
068be561 DL |
12031 | |
12032 | if (IS_GEN2(dev)) { | |
12033 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; | |
12034 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
12035 | } else { | |
12036 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
12037 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
12038 | } | |
12039 | ||
5d4545ae | 12040 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
79e53945 | 12041 | |
28c97730 | 12042 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
12043 | INTEL_INFO(dev)->num_pipes, |
12044 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 12045 | |
8cc87b75 DL |
12046 | for_each_pipe(pipe) { |
12047 | intel_crtc_init(dev, pipe); | |
1fe47785 DL |
12048 | for_each_sprite(pipe, sprite) { |
12049 | ret = intel_plane_init(dev, pipe, sprite); | |
7f1f3851 | 12050 | if (ret) |
06da8da2 | 12051 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
1fe47785 | 12052 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
7f1f3851 | 12053 | } |
79e53945 JB |
12054 | } |
12055 | ||
f42bb70d | 12056 | intel_init_dpio(dev); |
5382f5f3 | 12057 | intel_reset_dpio(dev); |
f42bb70d | 12058 | |
79f689aa | 12059 | intel_cpu_pll_init(dev); |
e72f9fbf | 12060 | intel_shared_dpll_init(dev); |
ee7b9f93 | 12061 | |
9cce37f4 JB |
12062 | /* Just disable it once at startup */ |
12063 | i915_disable_vga(dev); | |
79e53945 | 12064 | intel_setup_outputs(dev); |
11be49eb CW |
12065 | |
12066 | /* Just in case the BIOS is doing something questionable. */ | |
12067 | intel_disable_fbc(dev); | |
fa9fa083 | 12068 | |
6e9f798d | 12069 | drm_modeset_lock_all(dev); |
fa9fa083 | 12070 | intel_modeset_setup_hw_state(dev, false); |
6e9f798d | 12071 | drm_modeset_unlock_all(dev); |
46f297fb | 12072 | |
d3fcc808 | 12073 | for_each_intel_crtc(dev, crtc) { |
46f297fb JB |
12074 | if (!crtc->active) |
12075 | continue; | |
12076 | ||
46f297fb | 12077 | /* |
46f297fb JB |
12078 | * Note that reserving the BIOS fb up front prevents us |
12079 | * from stuffing other stolen allocations like the ring | |
12080 | * on top. This prevents some ugliness at boot time, and | |
12081 | * can even allow for smooth boot transitions if the BIOS | |
12082 | * fb is large enough for the active pipe configuration. | |
12083 | */ | |
12084 | if (dev_priv->display.get_plane_config) { | |
12085 | dev_priv->display.get_plane_config(crtc, | |
12086 | &crtc->plane_config); | |
12087 | /* | |
12088 | * If the fb is shared between multiple heads, we'll | |
12089 | * just get the first one. | |
12090 | */ | |
484b41dd | 12091 | intel_find_plane_obj(crtc, &crtc->plane_config); |
46f297fb | 12092 | } |
46f297fb | 12093 | } |
2c7111db CW |
12094 | } |
12095 | ||
7fad798e DV |
12096 | static void intel_enable_pipe_a(struct drm_device *dev) |
12097 | { | |
12098 | struct intel_connector *connector; | |
12099 | struct drm_connector *crt = NULL; | |
12100 | struct intel_load_detect_pipe load_detect_temp; | |
51fd371b | 12101 | struct drm_modeset_acquire_ctx ctx; |
7fad798e DV |
12102 | |
12103 | /* We can't just switch on the pipe A, we need to set things up with a | |
12104 | * proper mode and output configuration. As a gross hack, enable pipe A | |
12105 | * by enabling the load detect pipe once. */ | |
12106 | list_for_each_entry(connector, | |
12107 | &dev->mode_config.connector_list, | |
12108 | base.head) { | |
12109 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { | |
12110 | crt = &connector->base; | |
12111 | break; | |
12112 | } | |
12113 | } | |
12114 | ||
12115 | if (!crt) | |
12116 | return; | |
12117 | ||
51fd371b RC |
12118 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, &ctx)) |
12119 | intel_release_load_detect_pipe(crt, &load_detect_temp, &ctx); | |
7fad798e | 12120 | |
652c393a | 12121 | |
7fad798e DV |
12122 | } |
12123 | ||
fa555837 DV |
12124 | static bool |
12125 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
12126 | { | |
7eb552ae BW |
12127 | struct drm_device *dev = crtc->base.dev; |
12128 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 DV |
12129 | u32 reg, val; |
12130 | ||
7eb552ae | 12131 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
12132 | return true; |
12133 | ||
12134 | reg = DSPCNTR(!crtc->plane); | |
12135 | val = I915_READ(reg); | |
12136 | ||
12137 | if ((val & DISPLAY_PLANE_ENABLE) && | |
12138 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
12139 | return false; | |
12140 | ||
12141 | return true; | |
12142 | } | |
12143 | ||
24929352 DV |
12144 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
12145 | { | |
12146 | struct drm_device *dev = crtc->base.dev; | |
12147 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 | 12148 | u32 reg; |
24929352 | 12149 | |
24929352 | 12150 | /* Clear any frame start delays used for debugging left by the BIOS */ |
3b117c8f | 12151 | reg = PIPECONF(crtc->config.cpu_transcoder); |
24929352 DV |
12152 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
12153 | ||
d3eaf884 VS |
12154 | /* restore vblank interrupts to correct state */ |
12155 | if (crtc->active) | |
12156 | drm_vblank_on(dev, crtc->pipe); | |
12157 | else | |
12158 | drm_vblank_off(dev, crtc->pipe); | |
12159 | ||
24929352 | 12160 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
12161 | * disable the crtc (and hence change the state) if it is wrong. Note |
12162 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
12163 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
12164 | struct intel_connector *connector; |
12165 | bool plane; | |
12166 | ||
24929352 DV |
12167 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
12168 | crtc->base.base.id); | |
12169 | ||
12170 | /* Pipe has the wrong plane attached and the plane is active. | |
12171 | * Temporarily change the plane mapping and disable everything | |
12172 | * ... */ | |
12173 | plane = crtc->plane; | |
12174 | crtc->plane = !plane; | |
12175 | dev_priv->display.crtc_disable(&crtc->base); | |
12176 | crtc->plane = plane; | |
12177 | ||
12178 | /* ... and break all links. */ | |
12179 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
12180 | base.head) { | |
12181 | if (connector->encoder->base.crtc != &crtc->base) | |
12182 | continue; | |
12183 | ||
7f1950fb EE |
12184 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
12185 | connector->base.encoder = NULL; | |
24929352 | 12186 | } |
7f1950fb EE |
12187 | /* multiple connectors may have the same encoder: |
12188 | * handle them and break crtc link separately */ | |
12189 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
12190 | base.head) | |
12191 | if (connector->encoder->base.crtc == &crtc->base) { | |
12192 | connector->encoder->base.crtc = NULL; | |
12193 | connector->encoder->connectors_active = false; | |
12194 | } | |
24929352 DV |
12195 | |
12196 | WARN_ON(crtc->active); | |
12197 | crtc->base.enabled = false; | |
12198 | } | |
24929352 | 12199 | |
7fad798e DV |
12200 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
12201 | crtc->pipe == PIPE_A && !crtc->active) { | |
12202 | /* BIOS forgot to enable pipe A, this mostly happens after | |
12203 | * resume. Force-enable the pipe to fix this, the update_dpms | |
12204 | * call below we restore the pipe to the right state, but leave | |
12205 | * the required bits on. */ | |
12206 | intel_enable_pipe_a(dev); | |
12207 | } | |
12208 | ||
24929352 DV |
12209 | /* Adjust the state of the output pipe according to whether we |
12210 | * have active connectors/encoders. */ | |
12211 | intel_crtc_update_dpms(&crtc->base); | |
12212 | ||
12213 | if (crtc->active != crtc->base.enabled) { | |
12214 | struct intel_encoder *encoder; | |
12215 | ||
12216 | /* This can happen either due to bugs in the get_hw_state | |
12217 | * functions or because the pipe is force-enabled due to the | |
12218 | * pipe A quirk. */ | |
12219 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", | |
12220 | crtc->base.base.id, | |
12221 | crtc->base.enabled ? "enabled" : "disabled", | |
12222 | crtc->active ? "enabled" : "disabled"); | |
12223 | ||
12224 | crtc->base.enabled = crtc->active; | |
12225 | ||
12226 | /* Because we only establish the connector -> encoder -> | |
12227 | * crtc links if something is active, this means the | |
12228 | * crtc is now deactivated. Break the links. connector | |
12229 | * -> encoder links are only establish when things are | |
12230 | * actually up, hence no need to break them. */ | |
12231 | WARN_ON(crtc->active); | |
12232 | ||
12233 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { | |
12234 | WARN_ON(encoder->connectors_active); | |
12235 | encoder->base.crtc = NULL; | |
12236 | } | |
12237 | } | |
c5ab3bc0 DV |
12238 | |
12239 | if (crtc->active || IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen < 5) { | |
4cc31489 DV |
12240 | /* |
12241 | * We start out with underrun reporting disabled to avoid races. | |
12242 | * For correct bookkeeping mark this on active crtcs. | |
12243 | * | |
c5ab3bc0 DV |
12244 | * Also on gmch platforms we dont have any hardware bits to |
12245 | * disable the underrun reporting. Which means we need to start | |
12246 | * out with underrun reporting disabled also on inactive pipes, | |
12247 | * since otherwise we'll complain about the garbage we read when | |
12248 | * e.g. coming up after runtime pm. | |
12249 | * | |
4cc31489 DV |
12250 | * No protection against concurrent access is required - at |
12251 | * worst a fifo underrun happens which also sets this to false. | |
12252 | */ | |
12253 | crtc->cpu_fifo_underrun_disabled = true; | |
12254 | crtc->pch_fifo_underrun_disabled = true; | |
80715b2f VS |
12255 | |
12256 | update_scanline_offset(crtc); | |
4cc31489 | 12257 | } |
24929352 DV |
12258 | } |
12259 | ||
12260 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
12261 | { | |
12262 | struct intel_connector *connector; | |
12263 | struct drm_device *dev = encoder->base.dev; | |
12264 | ||
12265 | /* We need to check both for a crtc link (meaning that the | |
12266 | * encoder is active and trying to read from a pipe) and the | |
12267 | * pipe itself being active. */ | |
12268 | bool has_active_crtc = encoder->base.crtc && | |
12269 | to_intel_crtc(encoder->base.crtc)->active; | |
12270 | ||
12271 | if (encoder->connectors_active && !has_active_crtc) { | |
12272 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", | |
12273 | encoder->base.base.id, | |
8e329a03 | 12274 | encoder->base.name); |
24929352 DV |
12275 | |
12276 | /* Connector is active, but has no active pipe. This is | |
12277 | * fallout from our resume register restoring. Disable | |
12278 | * the encoder manually again. */ | |
12279 | if (encoder->base.crtc) { | |
12280 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
12281 | encoder->base.base.id, | |
8e329a03 | 12282 | encoder->base.name); |
24929352 DV |
12283 | encoder->disable(encoder); |
12284 | } | |
7f1950fb EE |
12285 | encoder->base.crtc = NULL; |
12286 | encoder->connectors_active = false; | |
24929352 DV |
12287 | |
12288 | /* Inconsistent output/port/pipe state happens presumably due to | |
12289 | * a bug in one of the get_hw_state functions. Or someplace else | |
12290 | * in our code, like the register restore mess on resume. Clamp | |
12291 | * things to off as a safer default. */ | |
12292 | list_for_each_entry(connector, | |
12293 | &dev->mode_config.connector_list, | |
12294 | base.head) { | |
12295 | if (connector->encoder != encoder) | |
12296 | continue; | |
7f1950fb EE |
12297 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
12298 | connector->base.encoder = NULL; | |
24929352 DV |
12299 | } |
12300 | } | |
12301 | /* Enabled encoders without active connectors will be fixed in | |
12302 | * the crtc fixup. */ | |
12303 | } | |
12304 | ||
04098753 | 12305 | void i915_redisable_vga_power_on(struct drm_device *dev) |
0fde901f KM |
12306 | { |
12307 | struct drm_i915_private *dev_priv = dev->dev_private; | |
766aa1c4 | 12308 | u32 vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 12309 | |
04098753 ID |
12310 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
12311 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
12312 | i915_disable_vga(dev); | |
12313 | } | |
12314 | } | |
12315 | ||
12316 | void i915_redisable_vga(struct drm_device *dev) | |
12317 | { | |
12318 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12319 | ||
8dc8a27c PZ |
12320 | /* This function can be called both from intel_modeset_setup_hw_state or |
12321 | * at a very early point in our resume sequence, where the power well | |
12322 | * structures are not yet restored. Since this function is at a very | |
12323 | * paranoid "someone might have enabled VGA while we were not looking" | |
12324 | * level, just check if the power well is enabled instead of trying to | |
12325 | * follow the "don't touch the power well if we don't need it" policy | |
12326 | * the rest of the driver uses. */ | |
04098753 | 12327 | if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
12328 | return; |
12329 | ||
04098753 | 12330 | i915_redisable_vga_power_on(dev); |
0fde901f KM |
12331 | } |
12332 | ||
98ec7739 VS |
12333 | static bool primary_get_hw_state(struct intel_crtc *crtc) |
12334 | { | |
12335 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
12336 | ||
12337 | if (!crtc->active) | |
12338 | return false; | |
12339 | ||
12340 | return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE; | |
12341 | } | |
12342 | ||
30e984df | 12343 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 DV |
12344 | { |
12345 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12346 | enum pipe pipe; | |
24929352 DV |
12347 | struct intel_crtc *crtc; |
12348 | struct intel_encoder *encoder; | |
12349 | struct intel_connector *connector; | |
5358901f | 12350 | int i; |
24929352 | 12351 | |
d3fcc808 | 12352 | for_each_intel_crtc(dev, crtc) { |
88adfff1 | 12353 | memset(&crtc->config, 0, sizeof(crtc->config)); |
3b117c8f | 12354 | |
9953599b DV |
12355 | crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE; |
12356 | ||
0e8ffe1b DV |
12357 | crtc->active = dev_priv->display.get_pipe_config(crtc, |
12358 | &crtc->config); | |
24929352 DV |
12359 | |
12360 | crtc->base.enabled = crtc->active; | |
98ec7739 | 12361 | crtc->primary_enabled = primary_get_hw_state(crtc); |
24929352 DV |
12362 | |
12363 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
12364 | crtc->base.base.id, | |
12365 | crtc->active ? "enabled" : "disabled"); | |
12366 | } | |
12367 | ||
5358901f | 12368 | /* FIXME: Smash this into the new shared dpll infrastructure. */ |
affa9354 | 12369 | if (HAS_DDI(dev)) |
6441ab5f PZ |
12370 | intel_ddi_setup_hw_pll_state(dev); |
12371 | ||
5358901f DV |
12372 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
12373 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
12374 | ||
12375 | pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state); | |
12376 | pll->active = 0; | |
d3fcc808 | 12377 | for_each_intel_crtc(dev, crtc) { |
5358901f DV |
12378 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) |
12379 | pll->active++; | |
12380 | } | |
12381 | pll->refcount = pll->active; | |
12382 | ||
35c95375 DV |
12383 | DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n", |
12384 | pll->name, pll->refcount, pll->on); | |
5358901f DV |
12385 | } |
12386 | ||
24929352 DV |
12387 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
12388 | base.head) { | |
12389 | pipe = 0; | |
12390 | ||
12391 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
12392 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
12393 | encoder->base.crtc = &crtc->base; | |
1d37b689 | 12394 | encoder->get_config(encoder, &crtc->config); |
24929352 DV |
12395 | } else { |
12396 | encoder->base.crtc = NULL; | |
12397 | } | |
12398 | ||
12399 | encoder->connectors_active = false; | |
6f2bcceb | 12400 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
24929352 | 12401 | encoder->base.base.id, |
8e329a03 | 12402 | encoder->base.name, |
24929352 | 12403 | encoder->base.crtc ? "enabled" : "disabled", |
6f2bcceb | 12404 | pipe_name(pipe)); |
24929352 DV |
12405 | } |
12406 | ||
12407 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
12408 | base.head) { | |
12409 | if (connector->get_hw_state(connector)) { | |
12410 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
12411 | connector->encoder->connectors_active = true; | |
12412 | connector->base.encoder = &connector->encoder->base; | |
12413 | } else { | |
12414 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
12415 | connector->base.encoder = NULL; | |
12416 | } | |
12417 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
12418 | connector->base.base.id, | |
c23cc417 | 12419 | connector->base.name, |
24929352 DV |
12420 | connector->base.encoder ? "enabled" : "disabled"); |
12421 | } | |
30e984df DV |
12422 | } |
12423 | ||
12424 | /* Scan out the current hw modeset state, sanitizes it and maps it into the drm | |
12425 | * and i915 state tracking structures. */ | |
12426 | void intel_modeset_setup_hw_state(struct drm_device *dev, | |
12427 | bool force_restore) | |
12428 | { | |
12429 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12430 | enum pipe pipe; | |
30e984df DV |
12431 | struct intel_crtc *crtc; |
12432 | struct intel_encoder *encoder; | |
35c95375 | 12433 | int i; |
30e984df DV |
12434 | |
12435 | intel_modeset_readout_hw_state(dev); | |
24929352 | 12436 | |
babea61d JB |
12437 | /* |
12438 | * Now that we have the config, copy it to each CRTC struct | |
12439 | * Note that this could go away if we move to using crtc_config | |
12440 | * checking everywhere. | |
12441 | */ | |
d3fcc808 | 12442 | for_each_intel_crtc(dev, crtc) { |
d330a953 | 12443 | if (crtc->active && i915.fastboot) { |
f6a83288 | 12444 | intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config); |
babea61d JB |
12445 | DRM_DEBUG_KMS("[CRTC:%d] found active mode: ", |
12446 | crtc->base.base.id); | |
12447 | drm_mode_debug_printmodeline(&crtc->base.mode); | |
12448 | } | |
12449 | } | |
12450 | ||
24929352 DV |
12451 | /* HW state is read out, now we need to sanitize this mess. */ |
12452 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
12453 | base.head) { | |
12454 | intel_sanitize_encoder(encoder); | |
12455 | } | |
12456 | ||
12457 | for_each_pipe(pipe) { | |
12458 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
12459 | intel_sanitize_crtc(crtc); | |
c0b03411 | 12460 | intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]"); |
24929352 | 12461 | } |
9a935856 | 12462 | |
35c95375 DV |
12463 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
12464 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
12465 | ||
12466 | if (!pll->on || pll->active) | |
12467 | continue; | |
12468 | ||
12469 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
12470 | ||
12471 | pll->disable(dev_priv, pll); | |
12472 | pll->on = false; | |
12473 | } | |
12474 | ||
96f90c54 | 12475 | if (HAS_PCH_SPLIT(dev)) |
243e6a44 VS |
12476 | ilk_wm_get_hw_state(dev); |
12477 | ||
45e2b5f6 | 12478 | if (force_restore) { |
7d0bc1ea VS |
12479 | i915_redisable_vga(dev); |
12480 | ||
f30da187 DV |
12481 | /* |
12482 | * We need to use raw interfaces for restoring state to avoid | |
12483 | * checking (bogus) intermediate states. | |
12484 | */ | |
45e2b5f6 | 12485 | for_each_pipe(pipe) { |
b5644d05 JB |
12486 | struct drm_crtc *crtc = |
12487 | dev_priv->pipe_to_crtc_mapping[pipe]; | |
f30da187 DV |
12488 | |
12489 | __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, | |
f4510a27 | 12490 | crtc->primary->fb); |
45e2b5f6 DV |
12491 | } |
12492 | } else { | |
12493 | intel_modeset_update_staged_output_state(dev); | |
12494 | } | |
8af6cf88 DV |
12495 | |
12496 | intel_modeset_check_state(dev); | |
2c7111db CW |
12497 | } |
12498 | ||
12499 | void intel_modeset_gem_init(struct drm_device *dev) | |
12500 | { | |
484b41dd JB |
12501 | struct drm_crtc *c; |
12502 | struct intel_framebuffer *fb; | |
12503 | ||
ae48434c ID |
12504 | mutex_lock(&dev->struct_mutex); |
12505 | intel_init_gt_powersave(dev); | |
12506 | mutex_unlock(&dev->struct_mutex); | |
12507 | ||
1833b134 | 12508 | intel_modeset_init_hw(dev); |
02e792fb DV |
12509 | |
12510 | intel_setup_overlay(dev); | |
484b41dd JB |
12511 | |
12512 | /* | |
12513 | * Make sure any fbs we allocated at startup are properly | |
12514 | * pinned & fenced. When we do the allocation it's too early | |
12515 | * for this. | |
12516 | */ | |
12517 | mutex_lock(&dev->struct_mutex); | |
70e1e0ec | 12518 | for_each_crtc(dev, c) { |
66e514c1 | 12519 | if (!c->primary->fb) |
484b41dd JB |
12520 | continue; |
12521 | ||
66e514c1 | 12522 | fb = to_intel_framebuffer(c->primary->fb); |
484b41dd JB |
12523 | if (intel_pin_and_fence_fb_obj(dev, fb->obj, NULL)) { |
12524 | DRM_ERROR("failed to pin boot fb on pipe %d\n", | |
12525 | to_intel_crtc(c)->pipe); | |
66e514c1 DA |
12526 | drm_framebuffer_unreference(c->primary->fb); |
12527 | c->primary->fb = NULL; | |
484b41dd JB |
12528 | } |
12529 | } | |
12530 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
12531 | } |
12532 | ||
4932e2c3 ID |
12533 | void intel_connector_unregister(struct intel_connector *intel_connector) |
12534 | { | |
12535 | struct drm_connector *connector = &intel_connector->base; | |
12536 | ||
12537 | intel_panel_destroy_backlight(connector); | |
12538 | drm_sysfs_connector_remove(connector); | |
12539 | } | |
12540 | ||
79e53945 JB |
12541 | void intel_modeset_cleanup(struct drm_device *dev) |
12542 | { | |
652c393a JB |
12543 | struct drm_i915_private *dev_priv = dev->dev_private; |
12544 | struct drm_crtc *crtc; | |
d9255d57 | 12545 | struct drm_connector *connector; |
652c393a | 12546 | |
fd0c0642 DV |
12547 | /* |
12548 | * Interrupts and polling as the first thing to avoid creating havoc. | |
12549 | * Too much stuff here (turning of rps, connectors, ...) would | |
12550 | * experience fancy races otherwise. | |
12551 | */ | |
12552 | drm_irq_uninstall(dev); | |
12553 | cancel_work_sync(&dev_priv->hotplug_work); | |
12554 | /* | |
12555 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
12556 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
12557 | */ | |
f87ea761 | 12558 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 12559 | |
652c393a JB |
12560 | mutex_lock(&dev->struct_mutex); |
12561 | ||
723bfd70 JB |
12562 | intel_unregister_dsm_handler(); |
12563 | ||
70e1e0ec | 12564 | for_each_crtc(dev, crtc) { |
652c393a | 12565 | /* Skip inactive CRTCs */ |
f4510a27 | 12566 | if (!crtc->primary->fb) |
652c393a JB |
12567 | continue; |
12568 | ||
3dec0095 | 12569 | intel_increase_pllclock(crtc); |
652c393a JB |
12570 | } |
12571 | ||
973d04f9 | 12572 | intel_disable_fbc(dev); |
e70236a8 | 12573 | |
8090c6b9 | 12574 | intel_disable_gt_powersave(dev); |
0cdab21f | 12575 | |
930ebb46 DV |
12576 | ironlake_teardown_rc6(dev); |
12577 | ||
69341a5e KH |
12578 | mutex_unlock(&dev->struct_mutex); |
12579 | ||
1630fe75 CW |
12580 | /* flush any delayed tasks or pending work */ |
12581 | flush_scheduled_work(); | |
12582 | ||
db31af1d JN |
12583 | /* destroy the backlight and sysfs files before encoders/connectors */ |
12584 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
4932e2c3 ID |
12585 | struct intel_connector *intel_connector; |
12586 | ||
12587 | intel_connector = to_intel_connector(connector); | |
12588 | intel_connector->unregister(intel_connector); | |
db31af1d | 12589 | } |
d9255d57 | 12590 | |
79e53945 | 12591 | drm_mode_config_cleanup(dev); |
4d7bb011 DV |
12592 | |
12593 | intel_cleanup_overlay(dev); | |
ae48434c ID |
12594 | |
12595 | mutex_lock(&dev->struct_mutex); | |
12596 | intel_cleanup_gt_powersave(dev); | |
12597 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
12598 | } |
12599 | ||
f1c79df3 ZW |
12600 | /* |
12601 | * Return which encoder is currently attached for connector. | |
12602 | */ | |
df0e9248 | 12603 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 12604 | { |
df0e9248 CW |
12605 | return &intel_attached_encoder(connector)->base; |
12606 | } | |
f1c79df3 | 12607 | |
df0e9248 CW |
12608 | void intel_connector_attach_encoder(struct intel_connector *connector, |
12609 | struct intel_encoder *encoder) | |
12610 | { | |
12611 | connector->encoder = encoder; | |
12612 | drm_mode_connector_attach_encoder(&connector->base, | |
12613 | &encoder->base); | |
79e53945 | 12614 | } |
28d52043 DA |
12615 | |
12616 | /* | |
12617 | * set vga decode state - true == enable VGA decode | |
12618 | */ | |
12619 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
12620 | { | |
12621 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a885b3cc | 12622 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
12623 | u16 gmch_ctrl; |
12624 | ||
75fa041d CW |
12625 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
12626 | DRM_ERROR("failed to read control word\n"); | |
12627 | return -EIO; | |
12628 | } | |
12629 | ||
c0cc8a55 CW |
12630 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
12631 | return 0; | |
12632 | ||
28d52043 DA |
12633 | if (state) |
12634 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
12635 | else | |
12636 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
12637 | |
12638 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
12639 | DRM_ERROR("failed to write control word\n"); | |
12640 | return -EIO; | |
12641 | } | |
12642 | ||
28d52043 DA |
12643 | return 0; |
12644 | } | |
c4a1d9e4 | 12645 | |
c4a1d9e4 | 12646 | struct intel_display_error_state { |
ff57f1b0 PZ |
12647 | |
12648 | u32 power_well_driver; | |
12649 | ||
63b66e5b CW |
12650 | int num_transcoders; |
12651 | ||
c4a1d9e4 CW |
12652 | struct intel_cursor_error_state { |
12653 | u32 control; | |
12654 | u32 position; | |
12655 | u32 base; | |
12656 | u32 size; | |
52331309 | 12657 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
12658 | |
12659 | struct intel_pipe_error_state { | |
ddf9c536 | 12660 | bool power_domain_on; |
c4a1d9e4 | 12661 | u32 source; |
f301b1e1 | 12662 | u32 stat; |
52331309 | 12663 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
12664 | |
12665 | struct intel_plane_error_state { | |
12666 | u32 control; | |
12667 | u32 stride; | |
12668 | u32 size; | |
12669 | u32 pos; | |
12670 | u32 addr; | |
12671 | u32 surface; | |
12672 | u32 tile_offset; | |
52331309 | 12673 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
12674 | |
12675 | struct intel_transcoder_error_state { | |
ddf9c536 | 12676 | bool power_domain_on; |
63b66e5b CW |
12677 | enum transcoder cpu_transcoder; |
12678 | ||
12679 | u32 conf; | |
12680 | ||
12681 | u32 htotal; | |
12682 | u32 hblank; | |
12683 | u32 hsync; | |
12684 | u32 vtotal; | |
12685 | u32 vblank; | |
12686 | u32 vsync; | |
12687 | } transcoder[4]; | |
c4a1d9e4 CW |
12688 | }; |
12689 | ||
12690 | struct intel_display_error_state * | |
12691 | intel_display_capture_error_state(struct drm_device *dev) | |
12692 | { | |
fbee40df | 12693 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 | 12694 | struct intel_display_error_state *error; |
63b66e5b CW |
12695 | int transcoders[] = { |
12696 | TRANSCODER_A, | |
12697 | TRANSCODER_B, | |
12698 | TRANSCODER_C, | |
12699 | TRANSCODER_EDP, | |
12700 | }; | |
c4a1d9e4 CW |
12701 | int i; |
12702 | ||
63b66e5b CW |
12703 | if (INTEL_INFO(dev)->num_pipes == 0) |
12704 | return NULL; | |
12705 | ||
9d1cb914 | 12706 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
12707 | if (error == NULL) |
12708 | return NULL; | |
12709 | ||
190be112 | 12710 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ff57f1b0 PZ |
12711 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
12712 | ||
52331309 | 12713 | for_each_pipe(i) { |
ddf9c536 | 12714 | error->pipe[i].power_domain_on = |
da7e29bd ID |
12715 | intel_display_power_enabled_sw(dev_priv, |
12716 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 12717 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
12718 | continue; |
12719 | ||
5efb3e28 VS |
12720 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
12721 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
12722 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
12723 | |
12724 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
12725 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
80ca378b | 12726 | if (INTEL_INFO(dev)->gen <= 3) { |
51889b35 | 12727 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
12728 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
12729 | } | |
ca291363 PZ |
12730 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
12731 | error->plane[i].addr = I915_READ(DSPADDR(i)); | |
c4a1d9e4 CW |
12732 | if (INTEL_INFO(dev)->gen >= 4) { |
12733 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
12734 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
12735 | } | |
12736 | ||
c4a1d9e4 | 12737 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 ID |
12738 | |
12739 | if (!HAS_PCH_SPLIT(dev)) | |
12740 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); | |
63b66e5b CW |
12741 | } |
12742 | ||
12743 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; | |
12744 | if (HAS_DDI(dev_priv->dev)) | |
12745 | error->num_transcoders++; /* Account for eDP. */ | |
12746 | ||
12747 | for (i = 0; i < error->num_transcoders; i++) { | |
12748 | enum transcoder cpu_transcoder = transcoders[i]; | |
12749 | ||
ddf9c536 | 12750 | error->transcoder[i].power_domain_on = |
da7e29bd | 12751 | intel_display_power_enabled_sw(dev_priv, |
38cc1daf | 12752 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 12753 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
12754 | continue; |
12755 | ||
63b66e5b CW |
12756 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
12757 | ||
12758 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
12759 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
12760 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
12761 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
12762 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
12763 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
12764 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
12765 | } |
12766 | ||
12767 | return error; | |
12768 | } | |
12769 | ||
edc3d884 MK |
12770 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
12771 | ||
c4a1d9e4 | 12772 | void |
edc3d884 | 12773 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
12774 | struct drm_device *dev, |
12775 | struct intel_display_error_state *error) | |
12776 | { | |
12777 | int i; | |
12778 | ||
63b66e5b CW |
12779 | if (!error) |
12780 | return; | |
12781 | ||
edc3d884 | 12782 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
190be112 | 12783 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
edc3d884 | 12784 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 12785 | error->power_well_driver); |
52331309 | 12786 | for_each_pipe(i) { |
edc3d884 | 12787 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 ID |
12788 | err_printf(m, " Power: %s\n", |
12789 | error->pipe[i].power_domain_on ? "on" : "off"); | |
edc3d884 | 12790 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 12791 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
12792 | |
12793 | err_printf(m, "Plane [%d]:\n", i); | |
12794 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
12795 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 12796 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
12797 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
12798 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 12799 | } |
4b71a570 | 12800 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 12801 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 12802 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
12803 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
12804 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
12805 | } |
12806 | ||
edc3d884 MK |
12807 | err_printf(m, "Cursor [%d]:\n", i); |
12808 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
12809 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
12810 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 12811 | } |
63b66e5b CW |
12812 | |
12813 | for (i = 0; i < error->num_transcoders; i++) { | |
1cf84bb6 | 12814 | err_printf(m, "CPU transcoder: %c\n", |
63b66e5b | 12815 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 ID |
12816 | err_printf(m, " Power: %s\n", |
12817 | error->transcoder[i].power_domain_on ? "on" : "off"); | |
63b66e5b CW |
12818 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
12819 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
12820 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
12821 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
12822 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
12823 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
12824 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
12825 | } | |
c4a1d9e4 | 12826 | } |