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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
23b2f8bb | 27 | #include <linux/cpufreq.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
79e53945 JB |
35 | #include "drmP.h" |
36 | #include "intel_drv.h" | |
37 | #include "i915_drm.h" | |
38 | #include "i915_drv.h" | |
e5510fac | 39 | #include "i915_trace.h" |
ab2c0672 | 40 | #include "drm_dp_helper.h" |
79e53945 JB |
41 | |
42 | #include "drm_crtc_helper.h" | |
43 | ||
32f9d658 ZW |
44 | #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) |
45 | ||
0206e353 | 46 | bool intel_pipe_has_type(struct drm_crtc *crtc, int type); |
7662c8bd | 47 | static void intel_update_watermarks(struct drm_device *dev); |
3dec0095 | 48 | static void intel_increase_pllclock(struct drm_crtc *crtc); |
6b383a7f | 49 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
79e53945 JB |
50 | |
51 | typedef struct { | |
0206e353 AJ |
52 | /* given values */ |
53 | int n; | |
54 | int m1, m2; | |
55 | int p1, p2; | |
56 | /* derived values */ | |
57 | int dot; | |
58 | int vco; | |
59 | int m; | |
60 | int p; | |
79e53945 JB |
61 | } intel_clock_t; |
62 | ||
63 | typedef struct { | |
0206e353 | 64 | int min, max; |
79e53945 JB |
65 | } intel_range_t; |
66 | ||
67 | typedef struct { | |
0206e353 AJ |
68 | int dot_limit; |
69 | int p2_slow, p2_fast; | |
79e53945 JB |
70 | } intel_p2_t; |
71 | ||
72 | #define INTEL_P2_NUM 2 | |
d4906093 ML |
73 | typedef struct intel_limit intel_limit_t; |
74 | struct intel_limit { | |
0206e353 AJ |
75 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
76 | intel_p2_t p2; | |
77 | bool (* find_pll)(const intel_limit_t *, struct drm_crtc *, | |
78 | int, int, intel_clock_t *); | |
d4906093 | 79 | }; |
79e53945 | 80 | |
2377b741 JB |
81 | /* FDI */ |
82 | #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */ | |
83 | ||
d4906093 ML |
84 | static bool |
85 | intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
86 | int target, int refclk, intel_clock_t *best_clock); | |
87 | static bool | |
88 | intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
89 | int target, int refclk, intel_clock_t *best_clock); | |
79e53945 | 90 | |
a4fc5ed6 KP |
91 | static bool |
92 | intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc, | |
93 | int target, int refclk, intel_clock_t *best_clock); | |
5eb08b69 | 94 | static bool |
f2b115e6 AJ |
95 | intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc, |
96 | int target, int refclk, intel_clock_t *best_clock); | |
a4fc5ed6 | 97 | |
021357ac CW |
98 | static inline u32 /* units of 100MHz */ |
99 | intel_fdi_link_freq(struct drm_device *dev) | |
100 | { | |
8b99e68c CW |
101 | if (IS_GEN5(dev)) { |
102 | struct drm_i915_private *dev_priv = dev->dev_private; | |
103 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
104 | } else | |
105 | return 27; | |
021357ac CW |
106 | } |
107 | ||
e4b36699 | 108 | static const intel_limit_t intel_limits_i8xx_dvo = { |
0206e353 AJ |
109 | .dot = { .min = 25000, .max = 350000 }, |
110 | .vco = { .min = 930000, .max = 1400000 }, | |
111 | .n = { .min = 3, .max = 16 }, | |
112 | .m = { .min = 96, .max = 140 }, | |
113 | .m1 = { .min = 18, .max = 26 }, | |
114 | .m2 = { .min = 6, .max = 16 }, | |
115 | .p = { .min = 4, .max = 128 }, | |
116 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
117 | .p2 = { .dot_limit = 165000, |
118 | .p2_slow = 4, .p2_fast = 2 }, | |
d4906093 | 119 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
120 | }; |
121 | ||
122 | static const intel_limit_t intel_limits_i8xx_lvds = { | |
0206e353 AJ |
123 | .dot = { .min = 25000, .max = 350000 }, |
124 | .vco = { .min = 930000, .max = 1400000 }, | |
125 | .n = { .min = 3, .max = 16 }, | |
126 | .m = { .min = 96, .max = 140 }, | |
127 | .m1 = { .min = 18, .max = 26 }, | |
128 | .m2 = { .min = 6, .max = 16 }, | |
129 | .p = { .min = 4, .max = 128 }, | |
130 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
131 | .p2 = { .dot_limit = 165000, |
132 | .p2_slow = 14, .p2_fast = 7 }, | |
d4906093 | 133 | .find_pll = intel_find_best_PLL, |
e4b36699 | 134 | }; |
273e27ca | 135 | |
e4b36699 | 136 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
137 | .dot = { .min = 20000, .max = 400000 }, |
138 | .vco = { .min = 1400000, .max = 2800000 }, | |
139 | .n = { .min = 1, .max = 6 }, | |
140 | .m = { .min = 70, .max = 120 }, | |
141 | .m1 = { .min = 10, .max = 22 }, | |
142 | .m2 = { .min = 5, .max = 9 }, | |
143 | .p = { .min = 5, .max = 80 }, | |
144 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
145 | .p2 = { .dot_limit = 200000, |
146 | .p2_slow = 10, .p2_fast = 5 }, | |
d4906093 | 147 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
148 | }; |
149 | ||
150 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
151 | .dot = { .min = 20000, .max = 400000 }, |
152 | .vco = { .min = 1400000, .max = 2800000 }, | |
153 | .n = { .min = 1, .max = 6 }, | |
154 | .m = { .min = 70, .max = 120 }, | |
155 | .m1 = { .min = 10, .max = 22 }, | |
156 | .m2 = { .min = 5, .max = 9 }, | |
157 | .p = { .min = 7, .max = 98 }, | |
158 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
159 | .p2 = { .dot_limit = 112000, |
160 | .p2_slow = 14, .p2_fast = 7 }, | |
d4906093 | 161 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
162 | }; |
163 | ||
273e27ca | 164 | |
e4b36699 | 165 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
166 | .dot = { .min = 25000, .max = 270000 }, |
167 | .vco = { .min = 1750000, .max = 3500000}, | |
168 | .n = { .min = 1, .max = 4 }, | |
169 | .m = { .min = 104, .max = 138 }, | |
170 | .m1 = { .min = 17, .max = 23 }, | |
171 | .m2 = { .min = 5, .max = 11 }, | |
172 | .p = { .min = 10, .max = 30 }, | |
173 | .p1 = { .min = 1, .max = 3}, | |
174 | .p2 = { .dot_limit = 270000, | |
175 | .p2_slow = 10, | |
176 | .p2_fast = 10 | |
044c7c41 | 177 | }, |
d4906093 | 178 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
179 | }; |
180 | ||
181 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
182 | .dot = { .min = 22000, .max = 400000 }, |
183 | .vco = { .min = 1750000, .max = 3500000}, | |
184 | .n = { .min = 1, .max = 4 }, | |
185 | .m = { .min = 104, .max = 138 }, | |
186 | .m1 = { .min = 16, .max = 23 }, | |
187 | .m2 = { .min = 5, .max = 11 }, | |
188 | .p = { .min = 5, .max = 80 }, | |
189 | .p1 = { .min = 1, .max = 8}, | |
190 | .p2 = { .dot_limit = 165000, | |
191 | .p2_slow = 10, .p2_fast = 5 }, | |
d4906093 | 192 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
193 | }; |
194 | ||
195 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
196 | .dot = { .min = 20000, .max = 115000 }, |
197 | .vco = { .min = 1750000, .max = 3500000 }, | |
198 | .n = { .min = 1, .max = 3 }, | |
199 | .m = { .min = 104, .max = 138 }, | |
200 | .m1 = { .min = 17, .max = 23 }, | |
201 | .m2 = { .min = 5, .max = 11 }, | |
202 | .p = { .min = 28, .max = 112 }, | |
203 | .p1 = { .min = 2, .max = 8 }, | |
204 | .p2 = { .dot_limit = 0, | |
205 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 206 | }, |
d4906093 | 207 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
208 | }; |
209 | ||
210 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
211 | .dot = { .min = 80000, .max = 224000 }, |
212 | .vco = { .min = 1750000, .max = 3500000 }, | |
213 | .n = { .min = 1, .max = 3 }, | |
214 | .m = { .min = 104, .max = 138 }, | |
215 | .m1 = { .min = 17, .max = 23 }, | |
216 | .m2 = { .min = 5, .max = 11 }, | |
217 | .p = { .min = 14, .max = 42 }, | |
218 | .p1 = { .min = 2, .max = 6 }, | |
219 | .p2 = { .dot_limit = 0, | |
220 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 221 | }, |
d4906093 | 222 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
223 | }; |
224 | ||
225 | static const intel_limit_t intel_limits_g4x_display_port = { | |
0206e353 AJ |
226 | .dot = { .min = 161670, .max = 227000 }, |
227 | .vco = { .min = 1750000, .max = 3500000}, | |
228 | .n = { .min = 1, .max = 2 }, | |
229 | .m = { .min = 97, .max = 108 }, | |
230 | .m1 = { .min = 0x10, .max = 0x12 }, | |
231 | .m2 = { .min = 0x05, .max = 0x06 }, | |
232 | .p = { .min = 10, .max = 20 }, | |
233 | .p1 = { .min = 1, .max = 2}, | |
234 | .p2 = { .dot_limit = 0, | |
273e27ca | 235 | .p2_slow = 10, .p2_fast = 10 }, |
0206e353 | 236 | .find_pll = intel_find_pll_g4x_dp, |
e4b36699 KP |
237 | }; |
238 | ||
f2b115e6 | 239 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
240 | .dot = { .min = 20000, .max = 400000}, |
241 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 242 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
243 | .n = { .min = 3, .max = 6 }, |
244 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 245 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
246 | .m1 = { .min = 0, .max = 0 }, |
247 | .m2 = { .min = 0, .max = 254 }, | |
248 | .p = { .min = 5, .max = 80 }, | |
249 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
250 | .p2 = { .dot_limit = 200000, |
251 | .p2_slow = 10, .p2_fast = 5 }, | |
6115707b | 252 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
253 | }; |
254 | ||
f2b115e6 | 255 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
256 | .dot = { .min = 20000, .max = 400000 }, |
257 | .vco = { .min = 1700000, .max = 3500000 }, | |
258 | .n = { .min = 3, .max = 6 }, | |
259 | .m = { .min = 2, .max = 256 }, | |
260 | .m1 = { .min = 0, .max = 0 }, | |
261 | .m2 = { .min = 0, .max = 254 }, | |
262 | .p = { .min = 7, .max = 112 }, | |
263 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
264 | .p2 = { .dot_limit = 112000, |
265 | .p2_slow = 14, .p2_fast = 14 }, | |
6115707b | 266 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
267 | }; |
268 | ||
273e27ca EA |
269 | /* Ironlake / Sandybridge |
270 | * | |
271 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
272 | * the range value for them is (actual_value - 2). | |
273 | */ | |
b91ad0ec | 274 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
275 | .dot = { .min = 25000, .max = 350000 }, |
276 | .vco = { .min = 1760000, .max = 3510000 }, | |
277 | .n = { .min = 1, .max = 5 }, | |
278 | .m = { .min = 79, .max = 127 }, | |
279 | .m1 = { .min = 12, .max = 22 }, | |
280 | .m2 = { .min = 5, .max = 9 }, | |
281 | .p = { .min = 5, .max = 80 }, | |
282 | .p1 = { .min = 1, .max = 8 }, | |
283 | .p2 = { .dot_limit = 225000, | |
284 | .p2_slow = 10, .p2_fast = 5 }, | |
4547668a | 285 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
286 | }; |
287 | ||
b91ad0ec | 288 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
289 | .dot = { .min = 25000, .max = 350000 }, |
290 | .vco = { .min = 1760000, .max = 3510000 }, | |
291 | .n = { .min = 1, .max = 3 }, | |
292 | .m = { .min = 79, .max = 118 }, | |
293 | .m1 = { .min = 12, .max = 22 }, | |
294 | .m2 = { .min = 5, .max = 9 }, | |
295 | .p = { .min = 28, .max = 112 }, | |
296 | .p1 = { .min = 2, .max = 8 }, | |
297 | .p2 = { .dot_limit = 225000, | |
298 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
299 | .find_pll = intel_g4x_find_best_PLL, |
300 | }; | |
301 | ||
302 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
303 | .dot = { .min = 25000, .max = 350000 }, |
304 | .vco = { .min = 1760000, .max = 3510000 }, | |
305 | .n = { .min = 1, .max = 3 }, | |
306 | .m = { .min = 79, .max = 127 }, | |
307 | .m1 = { .min = 12, .max = 22 }, | |
308 | .m2 = { .min = 5, .max = 9 }, | |
309 | .p = { .min = 14, .max = 56 }, | |
310 | .p1 = { .min = 2, .max = 8 }, | |
311 | .p2 = { .dot_limit = 225000, | |
312 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
313 | .find_pll = intel_g4x_find_best_PLL, |
314 | }; | |
315 | ||
273e27ca | 316 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 317 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
318 | .dot = { .min = 25000, .max = 350000 }, |
319 | .vco = { .min = 1760000, .max = 3510000 }, | |
320 | .n = { .min = 1, .max = 2 }, | |
321 | .m = { .min = 79, .max = 126 }, | |
322 | .m1 = { .min = 12, .max = 22 }, | |
323 | .m2 = { .min = 5, .max = 9 }, | |
324 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 325 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
326 | .p2 = { .dot_limit = 225000, |
327 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
328 | .find_pll = intel_g4x_find_best_PLL, |
329 | }; | |
330 | ||
331 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
332 | .dot = { .min = 25000, .max = 350000 }, |
333 | .vco = { .min = 1760000, .max = 3510000 }, | |
334 | .n = { .min = 1, .max = 3 }, | |
335 | .m = { .min = 79, .max = 126 }, | |
336 | .m1 = { .min = 12, .max = 22 }, | |
337 | .m2 = { .min = 5, .max = 9 }, | |
338 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 339 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
340 | .p2 = { .dot_limit = 225000, |
341 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
342 | .find_pll = intel_g4x_find_best_PLL, |
343 | }; | |
344 | ||
345 | static const intel_limit_t intel_limits_ironlake_display_port = { | |
0206e353 AJ |
346 | .dot = { .min = 25000, .max = 350000 }, |
347 | .vco = { .min = 1760000, .max = 3510000}, | |
348 | .n = { .min = 1, .max = 2 }, | |
349 | .m = { .min = 81, .max = 90 }, | |
350 | .m1 = { .min = 12, .max = 22 }, | |
351 | .m2 = { .min = 5, .max = 9 }, | |
352 | .p = { .min = 10, .max = 20 }, | |
353 | .p1 = { .min = 1, .max = 2}, | |
354 | .p2 = { .dot_limit = 0, | |
273e27ca | 355 | .p2_slow = 10, .p2_fast = 10 }, |
0206e353 | 356 | .find_pll = intel_find_pll_ironlake_dp, |
79e53945 JB |
357 | }; |
358 | ||
1b894b59 CW |
359 | static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, |
360 | int refclk) | |
2c07245f | 361 | { |
b91ad0ec ZW |
362 | struct drm_device *dev = crtc->dev; |
363 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2c07245f | 364 | const intel_limit_t *limit; |
b91ad0ec ZW |
365 | |
366 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
b91ad0ec ZW |
367 | if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == |
368 | LVDS_CLKB_POWER_UP) { | |
369 | /* LVDS dual channel */ | |
1b894b59 | 370 | if (refclk == 100000) |
b91ad0ec ZW |
371 | limit = &intel_limits_ironlake_dual_lvds_100m; |
372 | else | |
373 | limit = &intel_limits_ironlake_dual_lvds; | |
374 | } else { | |
1b894b59 | 375 | if (refclk == 100000) |
b91ad0ec ZW |
376 | limit = &intel_limits_ironlake_single_lvds_100m; |
377 | else | |
378 | limit = &intel_limits_ironlake_single_lvds; | |
379 | } | |
380 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || | |
4547668a ZY |
381 | HAS_eDP) |
382 | limit = &intel_limits_ironlake_display_port; | |
2c07245f | 383 | else |
b91ad0ec | 384 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
385 | |
386 | return limit; | |
387 | } | |
388 | ||
044c7c41 ML |
389 | static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) |
390 | { | |
391 | struct drm_device *dev = crtc->dev; | |
392 | struct drm_i915_private *dev_priv = dev->dev_private; | |
393 | const intel_limit_t *limit; | |
394 | ||
395 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
396 | if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) == | |
397 | LVDS_CLKB_POWER_UP) | |
398 | /* LVDS with dual channel */ | |
e4b36699 | 399 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 ML |
400 | else |
401 | /* LVDS with dual channel */ | |
e4b36699 | 402 | limit = &intel_limits_g4x_single_channel_lvds; |
044c7c41 ML |
403 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || |
404 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 405 | limit = &intel_limits_g4x_hdmi; |
044c7c41 | 406 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 407 | limit = &intel_limits_g4x_sdvo; |
0206e353 | 408 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
e4b36699 | 409 | limit = &intel_limits_g4x_display_port; |
044c7c41 | 410 | } else /* The option is for other outputs */ |
e4b36699 | 411 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
412 | |
413 | return limit; | |
414 | } | |
415 | ||
1b894b59 | 416 | static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk) |
79e53945 JB |
417 | { |
418 | struct drm_device *dev = crtc->dev; | |
419 | const intel_limit_t *limit; | |
420 | ||
bad720ff | 421 | if (HAS_PCH_SPLIT(dev)) |
1b894b59 | 422 | limit = intel_ironlake_limit(crtc, refclk); |
2c07245f | 423 | else if (IS_G4X(dev)) { |
044c7c41 | 424 | limit = intel_g4x_limit(crtc); |
f2b115e6 | 425 | } else if (IS_PINEVIEW(dev)) { |
2177832f | 426 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 427 | limit = &intel_limits_pineview_lvds; |
2177832f | 428 | else |
f2b115e6 | 429 | limit = &intel_limits_pineview_sdvo; |
a6c45cf0 CW |
430 | } else if (!IS_GEN2(dev)) { |
431 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
432 | limit = &intel_limits_i9xx_lvds; | |
433 | else | |
434 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 JB |
435 | } else { |
436 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
e4b36699 | 437 | limit = &intel_limits_i8xx_lvds; |
79e53945 | 438 | else |
e4b36699 | 439 | limit = &intel_limits_i8xx_dvo; |
79e53945 JB |
440 | } |
441 | return limit; | |
442 | } | |
443 | ||
f2b115e6 AJ |
444 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
445 | static void pineview_clock(int refclk, intel_clock_t *clock) | |
79e53945 | 446 | { |
2177832f SL |
447 | clock->m = clock->m2 + 2; |
448 | clock->p = clock->p1 * clock->p2; | |
449 | clock->vco = refclk * clock->m / clock->n; | |
450 | clock->dot = clock->vco / clock->p; | |
451 | } | |
452 | ||
453 | static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock) | |
454 | { | |
f2b115e6 AJ |
455 | if (IS_PINEVIEW(dev)) { |
456 | pineview_clock(refclk, clock); | |
2177832f SL |
457 | return; |
458 | } | |
79e53945 JB |
459 | clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); |
460 | clock->p = clock->p1 * clock->p2; | |
461 | clock->vco = refclk * clock->m / (clock->n + 2); | |
462 | clock->dot = clock->vco / clock->p; | |
463 | } | |
464 | ||
79e53945 JB |
465 | /** |
466 | * Returns whether any output on the specified pipe is of the specified type | |
467 | */ | |
4ef69c7a | 468 | bool intel_pipe_has_type(struct drm_crtc *crtc, int type) |
79e53945 | 469 | { |
4ef69c7a CW |
470 | struct drm_device *dev = crtc->dev; |
471 | struct drm_mode_config *mode_config = &dev->mode_config; | |
472 | struct intel_encoder *encoder; | |
473 | ||
474 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) | |
475 | if (encoder->base.crtc == crtc && encoder->type == type) | |
476 | return true; | |
477 | ||
478 | return false; | |
79e53945 JB |
479 | } |
480 | ||
7c04d1d9 | 481 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
482 | /** |
483 | * Returns whether the given set of divisors are valid for a given refclk with | |
484 | * the given connectors. | |
485 | */ | |
486 | ||
1b894b59 CW |
487 | static bool intel_PLL_is_valid(struct drm_device *dev, |
488 | const intel_limit_t *limit, | |
489 | const intel_clock_t *clock) | |
79e53945 | 490 | { |
79e53945 | 491 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 492 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 493 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
0206e353 | 494 | INTELPllInvalid("p out of range\n"); |
79e53945 | 495 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 496 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 497 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 498 | INTELPllInvalid("m1 out of range\n"); |
f2b115e6 | 499 | if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev)) |
0206e353 | 500 | INTELPllInvalid("m1 <= m2\n"); |
79e53945 | 501 | if (clock->m < limit->m.min || limit->m.max < clock->m) |
0206e353 | 502 | INTELPllInvalid("m out of range\n"); |
79e53945 | 503 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
0206e353 | 504 | INTELPllInvalid("n out of range\n"); |
79e53945 | 505 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 506 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
507 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
508 | * connector, etc., rather than just a single range. | |
509 | */ | |
510 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 511 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
512 | |
513 | return true; | |
514 | } | |
515 | ||
d4906093 ML |
516 | static bool |
517 | intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
518 | int target, int refclk, intel_clock_t *best_clock) | |
519 | ||
79e53945 JB |
520 | { |
521 | struct drm_device *dev = crtc->dev; | |
522 | struct drm_i915_private *dev_priv = dev->dev_private; | |
523 | intel_clock_t clock; | |
79e53945 JB |
524 | int err = target; |
525 | ||
bc5e5718 | 526 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
832cc28d | 527 | (I915_READ(LVDS)) != 0) { |
79e53945 JB |
528 | /* |
529 | * For LVDS, if the panel is on, just rely on its current | |
530 | * settings for dual-channel. We haven't figured out how to | |
531 | * reliably set up different single/dual channel state, if we | |
532 | * even can. | |
533 | */ | |
534 | if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) == | |
535 | LVDS_CLKB_POWER_UP) | |
536 | clock.p2 = limit->p2.p2_fast; | |
537 | else | |
538 | clock.p2 = limit->p2.p2_slow; | |
539 | } else { | |
540 | if (target < limit->p2.dot_limit) | |
541 | clock.p2 = limit->p2.p2_slow; | |
542 | else | |
543 | clock.p2 = limit->p2.p2_fast; | |
544 | } | |
545 | ||
0206e353 | 546 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 547 | |
42158660 ZY |
548 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
549 | clock.m1++) { | |
550 | for (clock.m2 = limit->m2.min; | |
551 | clock.m2 <= limit->m2.max; clock.m2++) { | |
f2b115e6 AJ |
552 | /* m1 is always 0 in Pineview */ |
553 | if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev)) | |
42158660 ZY |
554 | break; |
555 | for (clock.n = limit->n.min; | |
556 | clock.n <= limit->n.max; clock.n++) { | |
557 | for (clock.p1 = limit->p1.min; | |
558 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
559 | int this_err; |
560 | ||
2177832f | 561 | intel_clock(dev, refclk, &clock); |
1b894b59 CW |
562 | if (!intel_PLL_is_valid(dev, limit, |
563 | &clock)) | |
79e53945 JB |
564 | continue; |
565 | ||
566 | this_err = abs(clock.dot - target); | |
567 | if (this_err < err) { | |
568 | *best_clock = clock; | |
569 | err = this_err; | |
570 | } | |
571 | } | |
572 | } | |
573 | } | |
574 | } | |
575 | ||
576 | return (err != target); | |
577 | } | |
578 | ||
d4906093 ML |
579 | static bool |
580 | intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
581 | int target, int refclk, intel_clock_t *best_clock) | |
582 | { | |
583 | struct drm_device *dev = crtc->dev; | |
584 | struct drm_i915_private *dev_priv = dev->dev_private; | |
585 | intel_clock_t clock; | |
586 | int max_n; | |
587 | bool found; | |
6ba770dc AJ |
588 | /* approximately equals target * 0.00585 */ |
589 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
590 | found = false; |
591 | ||
592 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
4547668a ZY |
593 | int lvds_reg; |
594 | ||
c619eed4 | 595 | if (HAS_PCH_SPLIT(dev)) |
4547668a ZY |
596 | lvds_reg = PCH_LVDS; |
597 | else | |
598 | lvds_reg = LVDS; | |
599 | if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) == | |
d4906093 ML |
600 | LVDS_CLKB_POWER_UP) |
601 | clock.p2 = limit->p2.p2_fast; | |
602 | else | |
603 | clock.p2 = limit->p2.p2_slow; | |
604 | } else { | |
605 | if (target < limit->p2.dot_limit) | |
606 | clock.p2 = limit->p2.p2_slow; | |
607 | else | |
608 | clock.p2 = limit->p2.p2_fast; | |
609 | } | |
610 | ||
611 | memset(best_clock, 0, sizeof(*best_clock)); | |
612 | max_n = limit->n.max; | |
f77f13e2 | 613 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 614 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 615 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
616 | for (clock.m1 = limit->m1.max; |
617 | clock.m1 >= limit->m1.min; clock.m1--) { | |
618 | for (clock.m2 = limit->m2.max; | |
619 | clock.m2 >= limit->m2.min; clock.m2--) { | |
620 | for (clock.p1 = limit->p1.max; | |
621 | clock.p1 >= limit->p1.min; clock.p1--) { | |
622 | int this_err; | |
623 | ||
2177832f | 624 | intel_clock(dev, refclk, &clock); |
1b894b59 CW |
625 | if (!intel_PLL_is_valid(dev, limit, |
626 | &clock)) | |
d4906093 | 627 | continue; |
1b894b59 CW |
628 | |
629 | this_err = abs(clock.dot - target); | |
d4906093 ML |
630 | if (this_err < err_most) { |
631 | *best_clock = clock; | |
632 | err_most = this_err; | |
633 | max_n = clock.n; | |
634 | found = true; | |
635 | } | |
636 | } | |
637 | } | |
638 | } | |
639 | } | |
2c07245f ZW |
640 | return found; |
641 | } | |
642 | ||
5eb08b69 | 643 | static bool |
f2b115e6 AJ |
644 | intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc, |
645 | int target, int refclk, intel_clock_t *best_clock) | |
5eb08b69 ZW |
646 | { |
647 | struct drm_device *dev = crtc->dev; | |
648 | intel_clock_t clock; | |
4547668a | 649 | |
5eb08b69 ZW |
650 | if (target < 200000) { |
651 | clock.n = 1; | |
652 | clock.p1 = 2; | |
653 | clock.p2 = 10; | |
654 | clock.m1 = 12; | |
655 | clock.m2 = 9; | |
656 | } else { | |
657 | clock.n = 2; | |
658 | clock.p1 = 1; | |
659 | clock.p2 = 10; | |
660 | clock.m1 = 14; | |
661 | clock.m2 = 8; | |
662 | } | |
663 | intel_clock(dev, refclk, &clock); | |
664 | memcpy(best_clock, &clock, sizeof(intel_clock_t)); | |
665 | return true; | |
666 | } | |
667 | ||
a4fc5ed6 KP |
668 | /* DisplayPort has only two frequencies, 162MHz and 270MHz */ |
669 | static bool | |
670 | intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc, | |
671 | int target, int refclk, intel_clock_t *best_clock) | |
672 | { | |
5eddb70b CW |
673 | intel_clock_t clock; |
674 | if (target < 200000) { | |
675 | clock.p1 = 2; | |
676 | clock.p2 = 10; | |
677 | clock.n = 2; | |
678 | clock.m1 = 23; | |
679 | clock.m2 = 8; | |
680 | } else { | |
681 | clock.p1 = 1; | |
682 | clock.p2 = 10; | |
683 | clock.n = 1; | |
684 | clock.m1 = 14; | |
685 | clock.m2 = 2; | |
686 | } | |
687 | clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2); | |
688 | clock.p = (clock.p1 * clock.p2); | |
689 | clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p; | |
690 | clock.vco = 0; | |
691 | memcpy(best_clock, &clock, sizeof(intel_clock_t)); | |
692 | return true; | |
a4fc5ed6 KP |
693 | } |
694 | ||
9d0498a2 JB |
695 | /** |
696 | * intel_wait_for_vblank - wait for vblank on a given pipe | |
697 | * @dev: drm device | |
698 | * @pipe: pipe to wait for | |
699 | * | |
700 | * Wait for vblank to occur on a given pipe. Needed for various bits of | |
701 | * mode setting code. | |
702 | */ | |
703 | void intel_wait_for_vblank(struct drm_device *dev, int pipe) | |
79e53945 | 704 | { |
9d0498a2 | 705 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 706 | int pipestat_reg = PIPESTAT(pipe); |
9d0498a2 | 707 | |
300387c0 CW |
708 | /* Clear existing vblank status. Note this will clear any other |
709 | * sticky status fields as well. | |
710 | * | |
711 | * This races with i915_driver_irq_handler() with the result | |
712 | * that either function could miss a vblank event. Here it is not | |
713 | * fatal, as we will either wait upon the next vblank interrupt or | |
714 | * timeout. Generally speaking intel_wait_for_vblank() is only | |
715 | * called during modeset at which time the GPU should be idle and | |
716 | * should *not* be performing page flips and thus not waiting on | |
717 | * vblanks... | |
718 | * Currently, the result of us stealing a vblank from the irq | |
719 | * handler is that a single frame will be skipped during swapbuffers. | |
720 | */ | |
721 | I915_WRITE(pipestat_reg, | |
722 | I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS); | |
723 | ||
9d0498a2 | 724 | /* Wait for vblank interrupt bit to set */ |
481b6af3 CW |
725 | if (wait_for(I915_READ(pipestat_reg) & |
726 | PIPE_VBLANK_INTERRUPT_STATUS, | |
727 | 50)) | |
9d0498a2 JB |
728 | DRM_DEBUG_KMS("vblank wait timed out\n"); |
729 | } | |
730 | ||
ab7ad7f6 KP |
731 | /* |
732 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
9d0498a2 JB |
733 | * @dev: drm device |
734 | * @pipe: pipe to wait for | |
735 | * | |
736 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
737 | * spinning on the vblank interrupt status bit, since we won't actually | |
738 | * see an interrupt when the pipe is disabled. | |
739 | * | |
ab7ad7f6 KP |
740 | * On Gen4 and above: |
741 | * wait for the pipe register state bit to turn off | |
742 | * | |
743 | * Otherwise: | |
744 | * wait for the display line value to settle (it usually | |
745 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 746 | * |
9d0498a2 | 747 | */ |
58e10eb9 | 748 | void intel_wait_for_pipe_off(struct drm_device *dev, int pipe) |
9d0498a2 JB |
749 | { |
750 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ab7ad7f6 KP |
751 | |
752 | if (INTEL_INFO(dev)->gen >= 4) { | |
58e10eb9 | 753 | int reg = PIPECONF(pipe); |
ab7ad7f6 KP |
754 | |
755 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
756 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
757 | 100)) | |
ab7ad7f6 KP |
758 | DRM_DEBUG_KMS("pipe_off wait timed out\n"); |
759 | } else { | |
760 | u32 last_line; | |
58e10eb9 | 761 | int reg = PIPEDSL(pipe); |
ab7ad7f6 KP |
762 | unsigned long timeout = jiffies + msecs_to_jiffies(100); |
763 | ||
764 | /* Wait for the display line to settle */ | |
765 | do { | |
58e10eb9 | 766 | last_line = I915_READ(reg) & DSL_LINEMASK; |
ab7ad7f6 | 767 | mdelay(5); |
58e10eb9 | 768 | } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) && |
ab7ad7f6 KP |
769 | time_after(timeout, jiffies)); |
770 | if (time_after(jiffies, timeout)) | |
771 | DRM_DEBUG_KMS("pipe_off wait timed out\n"); | |
772 | } | |
79e53945 JB |
773 | } |
774 | ||
b24e7179 JB |
775 | static const char *state_string(bool enabled) |
776 | { | |
777 | return enabled ? "on" : "off"; | |
778 | } | |
779 | ||
780 | /* Only for pre-ILK configs */ | |
781 | static void assert_pll(struct drm_i915_private *dev_priv, | |
782 | enum pipe pipe, bool state) | |
783 | { | |
784 | int reg; | |
785 | u32 val; | |
786 | bool cur_state; | |
787 | ||
788 | reg = DPLL(pipe); | |
789 | val = I915_READ(reg); | |
790 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
791 | WARN(cur_state != state, | |
792 | "PLL state assertion failure (expected %s, current %s)\n", | |
793 | state_string(state), state_string(cur_state)); | |
794 | } | |
795 | #define assert_pll_enabled(d, p) assert_pll(d, p, true) | |
796 | #define assert_pll_disabled(d, p) assert_pll(d, p, false) | |
797 | ||
040484af JB |
798 | /* For ILK+ */ |
799 | static void assert_pch_pll(struct drm_i915_private *dev_priv, | |
800 | enum pipe pipe, bool state) | |
801 | { | |
802 | int reg; | |
803 | u32 val; | |
804 | bool cur_state; | |
805 | ||
d3ccbe86 JB |
806 | if (HAS_PCH_CPT(dev_priv->dev)) { |
807 | u32 pch_dpll; | |
808 | ||
809 | pch_dpll = I915_READ(PCH_DPLL_SEL); | |
810 | ||
811 | /* Make sure the selected PLL is enabled to the transcoder */ | |
812 | WARN(!((pch_dpll >> (4 * pipe)) & 8), | |
813 | "transcoder %d PLL not enabled\n", pipe); | |
814 | ||
815 | /* Convert the transcoder pipe number to a pll pipe number */ | |
816 | pipe = (pch_dpll >> (4 * pipe)) & 1; | |
817 | } | |
818 | ||
040484af JB |
819 | reg = PCH_DPLL(pipe); |
820 | val = I915_READ(reg); | |
821 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
822 | WARN(cur_state != state, | |
823 | "PCH PLL state assertion failure (expected %s, current %s)\n", | |
824 | state_string(state), state_string(cur_state)); | |
825 | } | |
826 | #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true) | |
827 | #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false) | |
828 | ||
829 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
830 | enum pipe pipe, bool state) | |
831 | { | |
832 | int reg; | |
833 | u32 val; | |
834 | bool cur_state; | |
835 | ||
836 | reg = FDI_TX_CTL(pipe); | |
837 | val = I915_READ(reg); | |
838 | cur_state = !!(val & FDI_TX_ENABLE); | |
839 | WARN(cur_state != state, | |
840 | "FDI TX state assertion failure (expected %s, current %s)\n", | |
841 | state_string(state), state_string(cur_state)); | |
842 | } | |
843 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
844 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
845 | ||
846 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
847 | enum pipe pipe, bool state) | |
848 | { | |
849 | int reg; | |
850 | u32 val; | |
851 | bool cur_state; | |
852 | ||
853 | reg = FDI_RX_CTL(pipe); | |
854 | val = I915_READ(reg); | |
855 | cur_state = !!(val & FDI_RX_ENABLE); | |
856 | WARN(cur_state != state, | |
857 | "FDI RX state assertion failure (expected %s, current %s)\n", | |
858 | state_string(state), state_string(cur_state)); | |
859 | } | |
860 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
861 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
862 | ||
863 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
864 | enum pipe pipe) | |
865 | { | |
866 | int reg; | |
867 | u32 val; | |
868 | ||
869 | /* ILK FDI PLL is always enabled */ | |
870 | if (dev_priv->info->gen == 5) | |
871 | return; | |
872 | ||
873 | reg = FDI_TX_CTL(pipe); | |
874 | val = I915_READ(reg); | |
875 | WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); | |
876 | } | |
877 | ||
878 | static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv, | |
879 | enum pipe pipe) | |
880 | { | |
881 | int reg; | |
882 | u32 val; | |
883 | ||
884 | reg = FDI_RX_CTL(pipe); | |
885 | val = I915_READ(reg); | |
886 | WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n"); | |
887 | } | |
888 | ||
ea0760cf JB |
889 | static void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
890 | enum pipe pipe) | |
891 | { | |
892 | int pp_reg, lvds_reg; | |
893 | u32 val; | |
894 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 895 | bool locked = true; |
ea0760cf JB |
896 | |
897 | if (HAS_PCH_SPLIT(dev_priv->dev)) { | |
898 | pp_reg = PCH_PP_CONTROL; | |
899 | lvds_reg = PCH_LVDS; | |
900 | } else { | |
901 | pp_reg = PP_CONTROL; | |
902 | lvds_reg = LVDS; | |
903 | } | |
904 | ||
905 | val = I915_READ(pp_reg); | |
906 | if (!(val & PANEL_POWER_ON) || | |
907 | ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS)) | |
908 | locked = false; | |
909 | ||
910 | if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT) | |
911 | panel_pipe = PIPE_B; | |
912 | ||
913 | WARN(panel_pipe == pipe && locked, | |
914 | "panel assertion failure, pipe %c regs locked\n", | |
9db4a9c7 | 915 | pipe_name(pipe)); |
ea0760cf JB |
916 | } |
917 | ||
63d7bbe9 JB |
918 | static void assert_pipe(struct drm_i915_private *dev_priv, |
919 | enum pipe pipe, bool state) | |
b24e7179 JB |
920 | { |
921 | int reg; | |
922 | u32 val; | |
63d7bbe9 | 923 | bool cur_state; |
b24e7179 JB |
924 | |
925 | reg = PIPECONF(pipe); | |
926 | val = I915_READ(reg); | |
63d7bbe9 JB |
927 | cur_state = !!(val & PIPECONF_ENABLE); |
928 | WARN(cur_state != state, | |
929 | "pipe %c assertion failure (expected %s, current %s)\n", | |
9db4a9c7 | 930 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
b24e7179 | 931 | } |
63d7bbe9 JB |
932 | #define assert_pipe_enabled(d, p) assert_pipe(d, p, true) |
933 | #define assert_pipe_disabled(d, p) assert_pipe(d, p, false) | |
b24e7179 JB |
934 | |
935 | static void assert_plane_enabled(struct drm_i915_private *dev_priv, | |
936 | enum plane plane) | |
937 | { | |
938 | int reg; | |
939 | u32 val; | |
940 | ||
941 | reg = DSPCNTR(plane); | |
942 | val = I915_READ(reg); | |
943 | WARN(!(val & DISPLAY_PLANE_ENABLE), | |
944 | "plane %c assertion failure, should be active but is disabled\n", | |
9db4a9c7 | 945 | plane_name(plane)); |
b24e7179 JB |
946 | } |
947 | ||
948 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, | |
949 | enum pipe pipe) | |
950 | { | |
951 | int reg, i; | |
952 | u32 val; | |
953 | int cur_pipe; | |
954 | ||
19ec1358 JB |
955 | /* Planes are fixed to pipes on ILK+ */ |
956 | if (HAS_PCH_SPLIT(dev_priv->dev)) | |
957 | return; | |
958 | ||
b24e7179 JB |
959 | /* Need to check both planes against the pipe */ |
960 | for (i = 0; i < 2; i++) { | |
961 | reg = DSPCNTR(i); | |
962 | val = I915_READ(reg); | |
963 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
964 | DISPPLANE_SEL_PIPE_SHIFT; | |
965 | WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, | |
9db4a9c7 JB |
966 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
967 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
968 | } |
969 | } | |
970 | ||
92f2584a JB |
971 | static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
972 | { | |
973 | u32 val; | |
974 | bool enabled; | |
975 | ||
976 | val = I915_READ(PCH_DREF_CONTROL); | |
977 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
978 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
979 | WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); | |
980 | } | |
981 | ||
982 | static void assert_transcoder_disabled(struct drm_i915_private *dev_priv, | |
983 | enum pipe pipe) | |
984 | { | |
985 | int reg; | |
986 | u32 val; | |
987 | bool enabled; | |
988 | ||
989 | reg = TRANSCONF(pipe); | |
990 | val = I915_READ(reg); | |
991 | enabled = !!(val & TRANS_ENABLE); | |
9db4a9c7 JB |
992 | WARN(enabled, |
993 | "transcoder assertion failed, should be off on pipe %c but is still active\n", | |
994 | pipe_name(pipe)); | |
92f2584a JB |
995 | } |
996 | ||
4e634389 KP |
997 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
998 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
999 | { |
1000 | if ((val & DP_PORT_EN) == 0) | |
1001 | return false; | |
1002 | ||
1003 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1004 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); | |
1005 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); | |
1006 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) | |
1007 | return false; | |
1008 | } else { | |
1009 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1010 | return false; | |
1011 | } | |
1012 | return true; | |
1013 | } | |
1014 | ||
1519b995 KP |
1015 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1016 | enum pipe pipe, u32 val) | |
1017 | { | |
1018 | if ((val & PORT_ENABLE) == 0) | |
1019 | return false; | |
1020 | ||
1021 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1022 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1023 | return false; | |
1024 | } else { | |
1025 | if ((val & TRANSCODER_MASK) != TRANSCODER(pipe)) | |
1026 | return false; | |
1027 | } | |
1028 | return true; | |
1029 | } | |
1030 | ||
1031 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1032 | enum pipe pipe, u32 val) | |
1033 | { | |
1034 | if ((val & LVDS_PORT_EN) == 0) | |
1035 | return false; | |
1036 | ||
1037 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1038 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1039 | return false; | |
1040 | } else { | |
1041 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1042 | return false; | |
1043 | } | |
1044 | return true; | |
1045 | } | |
1046 | ||
1047 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1048 | enum pipe pipe, u32 val) | |
1049 | { | |
1050 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1051 | return false; | |
1052 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1053 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1054 | return false; | |
1055 | } else { | |
1056 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1057 | return false; | |
1058 | } | |
1059 | return true; | |
1060 | } | |
1061 | ||
291906f1 | 1062 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0575e92 | 1063 | enum pipe pipe, int reg, u32 port_sel) |
291906f1 | 1064 | { |
47a05eca | 1065 | u32 val = I915_READ(reg); |
4e634389 | 1066 | WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1067 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1068 | reg, pipe_name(pipe)); |
291906f1 JB |
1069 | } |
1070 | ||
1071 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
1072 | enum pipe pipe, int reg) | |
1073 | { | |
47a05eca | 1074 | u32 val = I915_READ(reg); |
1519b995 | 1075 | WARN(hdmi_pipe_enabled(dev_priv, val, pipe), |
291906f1 | 1076 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1077 | reg, pipe_name(pipe)); |
291906f1 JB |
1078 | } |
1079 | ||
1080 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1081 | enum pipe pipe) | |
1082 | { | |
1083 | int reg; | |
1084 | u32 val; | |
291906f1 | 1085 | |
f0575e92 KP |
1086 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1087 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1088 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 JB |
1089 | |
1090 | reg = PCH_ADPA; | |
1091 | val = I915_READ(reg); | |
1519b995 | 1092 | WARN(adpa_pipe_enabled(dev_priv, val, pipe), |
291906f1 | 1093 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1094 | pipe_name(pipe)); |
291906f1 JB |
1095 | |
1096 | reg = PCH_LVDS; | |
1097 | val = I915_READ(reg); | |
1519b995 | 1098 | WARN(lvds_pipe_enabled(dev_priv, val, pipe), |
291906f1 | 1099 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1100 | pipe_name(pipe)); |
291906f1 JB |
1101 | |
1102 | assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB); | |
1103 | assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC); | |
1104 | assert_pch_hdmi_disabled(dev_priv, pipe, HDMID); | |
1105 | } | |
1106 | ||
63d7bbe9 JB |
1107 | /** |
1108 | * intel_enable_pll - enable a PLL | |
1109 | * @dev_priv: i915 private structure | |
1110 | * @pipe: pipe PLL to enable | |
1111 | * | |
1112 | * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to | |
1113 | * make sure the PLL reg is writable first though, since the panel write | |
1114 | * protect mechanism may be enabled. | |
1115 | * | |
1116 | * Note! This is for pre-ILK only. | |
1117 | */ | |
1118 | static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1119 | { | |
1120 | int reg; | |
1121 | u32 val; | |
1122 | ||
1123 | /* No really, not for ILK+ */ | |
1124 | BUG_ON(dev_priv->info->gen >= 5); | |
1125 | ||
1126 | /* PLL is protected by panel, make sure we can write it */ | |
1127 | if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev)) | |
1128 | assert_panel_unlocked(dev_priv, pipe); | |
1129 | ||
1130 | reg = DPLL(pipe); | |
1131 | val = I915_READ(reg); | |
1132 | val |= DPLL_VCO_ENABLE; | |
1133 | ||
1134 | /* We do this three times for luck */ | |
1135 | I915_WRITE(reg, val); | |
1136 | POSTING_READ(reg); | |
1137 | udelay(150); /* wait for warmup */ | |
1138 | I915_WRITE(reg, val); | |
1139 | POSTING_READ(reg); | |
1140 | udelay(150); /* wait for warmup */ | |
1141 | I915_WRITE(reg, val); | |
1142 | POSTING_READ(reg); | |
1143 | udelay(150); /* wait for warmup */ | |
1144 | } | |
1145 | ||
1146 | /** | |
1147 | * intel_disable_pll - disable a PLL | |
1148 | * @dev_priv: i915 private structure | |
1149 | * @pipe: pipe PLL to disable | |
1150 | * | |
1151 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1152 | * | |
1153 | * Note! This is for pre-ILK only. | |
1154 | */ | |
1155 | static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1156 | { | |
1157 | int reg; | |
1158 | u32 val; | |
1159 | ||
1160 | /* Don't disable pipe A or pipe A PLLs if needed */ | |
1161 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
1162 | return; | |
1163 | ||
1164 | /* Make sure the pipe isn't still relying on us */ | |
1165 | assert_pipe_disabled(dev_priv, pipe); | |
1166 | ||
1167 | reg = DPLL(pipe); | |
1168 | val = I915_READ(reg); | |
1169 | val &= ~DPLL_VCO_ENABLE; | |
1170 | I915_WRITE(reg, val); | |
1171 | POSTING_READ(reg); | |
1172 | } | |
1173 | ||
92f2584a JB |
1174 | /** |
1175 | * intel_enable_pch_pll - enable PCH PLL | |
1176 | * @dev_priv: i915 private structure | |
1177 | * @pipe: pipe PLL to enable | |
1178 | * | |
1179 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1180 | * drives the transcoder clock. | |
1181 | */ | |
1182 | static void intel_enable_pch_pll(struct drm_i915_private *dev_priv, | |
1183 | enum pipe pipe) | |
1184 | { | |
1185 | int reg; | |
1186 | u32 val; | |
1187 | ||
4c609cb8 JB |
1188 | if (pipe > 1) |
1189 | return; | |
1190 | ||
92f2584a JB |
1191 | /* PCH only available on ILK+ */ |
1192 | BUG_ON(dev_priv->info->gen < 5); | |
1193 | ||
1194 | /* PCH refclock must be enabled first */ | |
1195 | assert_pch_refclk_enabled(dev_priv); | |
1196 | ||
1197 | reg = PCH_DPLL(pipe); | |
1198 | val = I915_READ(reg); | |
1199 | val |= DPLL_VCO_ENABLE; | |
1200 | I915_WRITE(reg, val); | |
1201 | POSTING_READ(reg); | |
1202 | udelay(200); | |
1203 | } | |
1204 | ||
1205 | static void intel_disable_pch_pll(struct drm_i915_private *dev_priv, | |
1206 | enum pipe pipe) | |
1207 | { | |
1208 | int reg; | |
1209 | u32 val; | |
1210 | ||
4c609cb8 JB |
1211 | if (pipe > 1) |
1212 | return; | |
1213 | ||
92f2584a JB |
1214 | /* PCH only available on ILK+ */ |
1215 | BUG_ON(dev_priv->info->gen < 5); | |
1216 | ||
1217 | /* Make sure transcoder isn't still depending on us */ | |
1218 | assert_transcoder_disabled(dev_priv, pipe); | |
1219 | ||
1220 | reg = PCH_DPLL(pipe); | |
1221 | val = I915_READ(reg); | |
1222 | val &= ~DPLL_VCO_ENABLE; | |
1223 | I915_WRITE(reg, val); | |
1224 | POSTING_READ(reg); | |
1225 | udelay(200); | |
1226 | } | |
1227 | ||
040484af JB |
1228 | static void intel_enable_transcoder(struct drm_i915_private *dev_priv, |
1229 | enum pipe pipe) | |
1230 | { | |
1231 | int reg; | |
1232 | u32 val; | |
1233 | ||
1234 | /* PCH only available on ILK+ */ | |
1235 | BUG_ON(dev_priv->info->gen < 5); | |
1236 | ||
1237 | /* Make sure PCH DPLL is enabled */ | |
1238 | assert_pch_pll_enabled(dev_priv, pipe); | |
1239 | ||
1240 | /* FDI must be feeding us bits for PCH ports */ | |
1241 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1242 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1243 | ||
1244 | reg = TRANSCONF(pipe); | |
1245 | val = I915_READ(reg); | |
e9bcff5c JB |
1246 | |
1247 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
1248 | /* | |
1249 | * make the BPC in transcoder be consistent with | |
1250 | * that in pipeconf reg. | |
1251 | */ | |
1252 | val &= ~PIPE_BPC_MASK; | |
1253 | val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK; | |
1254 | } | |
040484af JB |
1255 | I915_WRITE(reg, val | TRANS_ENABLE); |
1256 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
1257 | DRM_ERROR("failed to enable transcoder %d\n", pipe); | |
1258 | } | |
1259 | ||
1260 | static void intel_disable_transcoder(struct drm_i915_private *dev_priv, | |
1261 | enum pipe pipe) | |
1262 | { | |
1263 | int reg; | |
1264 | u32 val; | |
1265 | ||
1266 | /* FDI relies on the transcoder */ | |
1267 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1268 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1269 | ||
291906f1 JB |
1270 | /* Ports must be off as well */ |
1271 | assert_pch_ports_disabled(dev_priv, pipe); | |
1272 | ||
040484af JB |
1273 | reg = TRANSCONF(pipe); |
1274 | val = I915_READ(reg); | |
1275 | val &= ~TRANS_ENABLE; | |
1276 | I915_WRITE(reg, val); | |
1277 | /* wait for PCH transcoder off, transcoder state */ | |
1278 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
1279 | DRM_ERROR("failed to disable transcoder\n"); | |
1280 | } | |
1281 | ||
b24e7179 | 1282 | /** |
309cfea8 | 1283 | * intel_enable_pipe - enable a pipe, asserting requirements |
b24e7179 JB |
1284 | * @dev_priv: i915 private structure |
1285 | * @pipe: pipe to enable | |
040484af | 1286 | * @pch_port: on ILK+, is this pipe driving a PCH port or not |
b24e7179 JB |
1287 | * |
1288 | * Enable @pipe, making sure that various hardware specific requirements | |
1289 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. | |
1290 | * | |
1291 | * @pipe should be %PIPE_A or %PIPE_B. | |
1292 | * | |
1293 | * Will wait until the pipe is actually running (i.e. first vblank) before | |
1294 | * returning. | |
1295 | */ | |
040484af JB |
1296 | static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, |
1297 | bool pch_port) | |
b24e7179 JB |
1298 | { |
1299 | int reg; | |
1300 | u32 val; | |
1301 | ||
1302 | /* | |
1303 | * A pipe without a PLL won't actually be able to drive bits from | |
1304 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
1305 | * need the check. | |
1306 | */ | |
1307 | if (!HAS_PCH_SPLIT(dev_priv->dev)) | |
1308 | assert_pll_enabled(dev_priv, pipe); | |
040484af JB |
1309 | else { |
1310 | if (pch_port) { | |
1311 | /* if driving the PCH, we need FDI enabled */ | |
1312 | assert_fdi_rx_pll_enabled(dev_priv, pipe); | |
1313 | assert_fdi_tx_pll_enabled(dev_priv, pipe); | |
1314 | } | |
1315 | /* FIXME: assert CPU port conditions for SNB+ */ | |
1316 | } | |
b24e7179 JB |
1317 | |
1318 | reg = PIPECONF(pipe); | |
1319 | val = I915_READ(reg); | |
00d70b15 CW |
1320 | if (val & PIPECONF_ENABLE) |
1321 | return; | |
1322 | ||
1323 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
b24e7179 JB |
1324 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1325 | } | |
1326 | ||
1327 | /** | |
309cfea8 | 1328 | * intel_disable_pipe - disable a pipe, asserting requirements |
b24e7179 JB |
1329 | * @dev_priv: i915 private structure |
1330 | * @pipe: pipe to disable | |
1331 | * | |
1332 | * Disable @pipe, making sure that various hardware specific requirements | |
1333 | * are met, if applicable, e.g. plane disabled, panel fitter off, etc. | |
1334 | * | |
1335 | * @pipe should be %PIPE_A or %PIPE_B. | |
1336 | * | |
1337 | * Will wait until the pipe has shut down before returning. | |
1338 | */ | |
1339 | static void intel_disable_pipe(struct drm_i915_private *dev_priv, | |
1340 | enum pipe pipe) | |
1341 | { | |
1342 | int reg; | |
1343 | u32 val; | |
1344 | ||
1345 | /* | |
1346 | * Make sure planes won't keep trying to pump pixels to us, | |
1347 | * or we might hang the display. | |
1348 | */ | |
1349 | assert_planes_disabled(dev_priv, pipe); | |
1350 | ||
1351 | /* Don't disable pipe A or pipe A PLLs if needed */ | |
1352 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
1353 | return; | |
1354 | ||
1355 | reg = PIPECONF(pipe); | |
1356 | val = I915_READ(reg); | |
00d70b15 CW |
1357 | if ((val & PIPECONF_ENABLE) == 0) |
1358 | return; | |
1359 | ||
1360 | I915_WRITE(reg, val & ~PIPECONF_ENABLE); | |
b24e7179 JB |
1361 | intel_wait_for_pipe_off(dev_priv->dev, pipe); |
1362 | } | |
1363 | ||
d74362c9 KP |
1364 | /* |
1365 | * Plane regs are double buffered, going from enabled->disabled needs a | |
1366 | * trigger in order to latch. The display address reg provides this. | |
1367 | */ | |
1368 | static void intel_flush_display_plane(struct drm_i915_private *dev_priv, | |
1369 | enum plane plane) | |
1370 | { | |
1371 | I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane))); | |
1372 | I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane))); | |
1373 | } | |
1374 | ||
b24e7179 JB |
1375 | /** |
1376 | * intel_enable_plane - enable a display plane on a given pipe | |
1377 | * @dev_priv: i915 private structure | |
1378 | * @plane: plane to enable | |
1379 | * @pipe: pipe being fed | |
1380 | * | |
1381 | * Enable @plane on @pipe, making sure that @pipe is running first. | |
1382 | */ | |
1383 | static void intel_enable_plane(struct drm_i915_private *dev_priv, | |
1384 | enum plane plane, enum pipe pipe) | |
1385 | { | |
1386 | int reg; | |
1387 | u32 val; | |
1388 | ||
1389 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ | |
1390 | assert_pipe_enabled(dev_priv, pipe); | |
1391 | ||
1392 | reg = DSPCNTR(plane); | |
1393 | val = I915_READ(reg); | |
00d70b15 CW |
1394 | if (val & DISPLAY_PLANE_ENABLE) |
1395 | return; | |
1396 | ||
1397 | I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE); | |
d74362c9 | 1398 | intel_flush_display_plane(dev_priv, plane); |
b24e7179 JB |
1399 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1400 | } | |
1401 | ||
b24e7179 JB |
1402 | /** |
1403 | * intel_disable_plane - disable a display plane | |
1404 | * @dev_priv: i915 private structure | |
1405 | * @plane: plane to disable | |
1406 | * @pipe: pipe consuming the data | |
1407 | * | |
1408 | * Disable @plane; should be an independent operation. | |
1409 | */ | |
1410 | static void intel_disable_plane(struct drm_i915_private *dev_priv, | |
1411 | enum plane plane, enum pipe pipe) | |
1412 | { | |
1413 | int reg; | |
1414 | u32 val; | |
1415 | ||
1416 | reg = DSPCNTR(plane); | |
1417 | val = I915_READ(reg); | |
00d70b15 CW |
1418 | if ((val & DISPLAY_PLANE_ENABLE) == 0) |
1419 | return; | |
1420 | ||
1421 | I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE); | |
b24e7179 JB |
1422 | intel_flush_display_plane(dev_priv, plane); |
1423 | intel_wait_for_vblank(dev_priv->dev, pipe); | |
1424 | } | |
1425 | ||
47a05eca | 1426 | static void disable_pch_dp(struct drm_i915_private *dev_priv, |
f0575e92 | 1427 | enum pipe pipe, int reg, u32 port_sel) |
47a05eca JB |
1428 | { |
1429 | u32 val = I915_READ(reg); | |
4e634389 | 1430 | if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) { |
f0575e92 | 1431 | DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe); |
47a05eca | 1432 | I915_WRITE(reg, val & ~DP_PORT_EN); |
f0575e92 | 1433 | } |
47a05eca JB |
1434 | } |
1435 | ||
1436 | static void disable_pch_hdmi(struct drm_i915_private *dev_priv, | |
1437 | enum pipe pipe, int reg) | |
1438 | { | |
1439 | u32 val = I915_READ(reg); | |
1519b995 | 1440 | if (hdmi_pipe_enabled(dev_priv, val, pipe)) { |
f0575e92 KP |
1441 | DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n", |
1442 | reg, pipe); | |
47a05eca | 1443 | I915_WRITE(reg, val & ~PORT_ENABLE); |
f0575e92 | 1444 | } |
47a05eca JB |
1445 | } |
1446 | ||
1447 | /* Disable any ports connected to this transcoder */ | |
1448 | static void intel_disable_pch_ports(struct drm_i915_private *dev_priv, | |
1449 | enum pipe pipe) | |
1450 | { | |
1451 | u32 reg, val; | |
1452 | ||
1453 | val = I915_READ(PCH_PP_CONTROL); | |
1454 | I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS); | |
1455 | ||
f0575e92 KP |
1456 | disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1457 | disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1458 | disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
47a05eca JB |
1459 | |
1460 | reg = PCH_ADPA; | |
1461 | val = I915_READ(reg); | |
1519b995 | 1462 | if (adpa_pipe_enabled(dev_priv, val, pipe)) |
47a05eca JB |
1463 | I915_WRITE(reg, val & ~ADPA_DAC_ENABLE); |
1464 | ||
1465 | reg = PCH_LVDS; | |
1466 | val = I915_READ(reg); | |
1519b995 KP |
1467 | if (lvds_pipe_enabled(dev_priv, val, pipe)) { |
1468 | DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val); | |
47a05eca JB |
1469 | I915_WRITE(reg, val & ~LVDS_PORT_EN); |
1470 | POSTING_READ(reg); | |
1471 | udelay(100); | |
1472 | } | |
1473 | ||
1474 | disable_pch_hdmi(dev_priv, pipe, HDMIB); | |
1475 | disable_pch_hdmi(dev_priv, pipe, HDMIC); | |
1476 | disable_pch_hdmi(dev_priv, pipe, HDMID); | |
1477 | } | |
1478 | ||
43a9539f CW |
1479 | static void i8xx_disable_fbc(struct drm_device *dev) |
1480 | { | |
1481 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1482 | u32 fbc_ctl; | |
1483 | ||
1484 | /* Disable compression */ | |
1485 | fbc_ctl = I915_READ(FBC_CONTROL); | |
1486 | if ((fbc_ctl & FBC_CTL_EN) == 0) | |
1487 | return; | |
1488 | ||
1489 | fbc_ctl &= ~FBC_CTL_EN; | |
1490 | I915_WRITE(FBC_CONTROL, fbc_ctl); | |
1491 | ||
1492 | /* Wait for compressing bit to clear */ | |
1493 | if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) { | |
1494 | DRM_DEBUG_KMS("FBC idle timed out\n"); | |
1495 | return; | |
1496 | } | |
1497 | ||
1498 | DRM_DEBUG_KMS("disabled FBC\n"); | |
1499 | } | |
1500 | ||
80824003 JB |
1501 | static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
1502 | { | |
1503 | struct drm_device *dev = crtc->dev; | |
1504 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1505 | struct drm_framebuffer *fb = crtc->fb; | |
1506 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 1507 | struct drm_i915_gem_object *obj = intel_fb->obj; |
80824003 | 1508 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
016b9b61 | 1509 | int cfb_pitch; |
80824003 JB |
1510 | int plane, i; |
1511 | u32 fbc_ctl, fbc_ctl2; | |
1512 | ||
016b9b61 CW |
1513 | cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE; |
1514 | if (fb->pitch < cfb_pitch) | |
1515 | cfb_pitch = fb->pitch; | |
80824003 JB |
1516 | |
1517 | /* FBC_CTL wants 64B units */ | |
016b9b61 CW |
1518 | cfb_pitch = (cfb_pitch / 64) - 1; |
1519 | plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB; | |
80824003 JB |
1520 | |
1521 | /* Clear old tags */ | |
1522 | for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) | |
1523 | I915_WRITE(FBC_TAG + (i * 4), 0); | |
1524 | ||
1525 | /* Set it up... */ | |
de568510 CW |
1526 | fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE; |
1527 | fbc_ctl2 |= plane; | |
80824003 JB |
1528 | I915_WRITE(FBC_CONTROL2, fbc_ctl2); |
1529 | I915_WRITE(FBC_FENCE_OFF, crtc->y); | |
1530 | ||
1531 | /* enable it... */ | |
1532 | fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC; | |
ee25df2b | 1533 | if (IS_I945GM(dev)) |
49677901 | 1534 | fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ |
016b9b61 | 1535 | fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; |
80824003 | 1536 | fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT; |
016b9b61 | 1537 | fbc_ctl |= obj->fence_reg; |
80824003 JB |
1538 | I915_WRITE(FBC_CONTROL, fbc_ctl); |
1539 | ||
016b9b61 CW |
1540 | DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ", |
1541 | cfb_pitch, crtc->y, intel_crtc->plane); | |
80824003 JB |
1542 | } |
1543 | ||
ee5382ae | 1544 | static bool i8xx_fbc_enabled(struct drm_device *dev) |
80824003 | 1545 | { |
80824003 JB |
1546 | struct drm_i915_private *dev_priv = dev->dev_private; |
1547 | ||
1548 | return I915_READ(FBC_CONTROL) & FBC_CTL_EN; | |
1549 | } | |
1550 | ||
74dff282 JB |
1551 | static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
1552 | { | |
1553 | struct drm_device *dev = crtc->dev; | |
1554 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1555 | struct drm_framebuffer *fb = crtc->fb; | |
1556 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 1557 | struct drm_i915_gem_object *obj = intel_fb->obj; |
74dff282 | 1558 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5eddb70b | 1559 | int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB; |
74dff282 JB |
1560 | unsigned long stall_watermark = 200; |
1561 | u32 dpfc_ctl; | |
1562 | ||
74dff282 | 1563 | dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X; |
016b9b61 | 1564 | dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg; |
de568510 | 1565 | I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY); |
74dff282 | 1566 | |
74dff282 JB |
1567 | I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN | |
1568 | (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) | | |
1569 | (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT)); | |
1570 | I915_WRITE(DPFC_FENCE_YOFF, crtc->y); | |
1571 | ||
1572 | /* enable it... */ | |
1573 | I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN); | |
1574 | ||
28c97730 | 1575 | DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane); |
74dff282 JB |
1576 | } |
1577 | ||
43a9539f | 1578 | static void g4x_disable_fbc(struct drm_device *dev) |
74dff282 JB |
1579 | { |
1580 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1581 | u32 dpfc_ctl; | |
1582 | ||
1583 | /* Disable compression */ | |
1584 | dpfc_ctl = I915_READ(DPFC_CONTROL); | |
bed4a673 CW |
1585 | if (dpfc_ctl & DPFC_CTL_EN) { |
1586 | dpfc_ctl &= ~DPFC_CTL_EN; | |
1587 | I915_WRITE(DPFC_CONTROL, dpfc_ctl); | |
74dff282 | 1588 | |
bed4a673 CW |
1589 | DRM_DEBUG_KMS("disabled FBC\n"); |
1590 | } | |
74dff282 JB |
1591 | } |
1592 | ||
ee5382ae | 1593 | static bool g4x_fbc_enabled(struct drm_device *dev) |
74dff282 | 1594 | { |
74dff282 JB |
1595 | struct drm_i915_private *dev_priv = dev->dev_private; |
1596 | ||
1597 | return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN; | |
1598 | } | |
1599 | ||
4efe0708 JB |
1600 | static void sandybridge_blit_fbc_update(struct drm_device *dev) |
1601 | { | |
1602 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1603 | u32 blt_ecoskpd; | |
1604 | ||
1605 | /* Make sure blitter notifies FBC of writes */ | |
fcca7926 | 1606 | gen6_gt_force_wake_get(dev_priv); |
4efe0708 JB |
1607 | blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD); |
1608 | blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY << | |
1609 | GEN6_BLITTER_LOCK_SHIFT; | |
1610 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); | |
1611 | blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY; | |
1612 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); | |
1613 | blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY << | |
1614 | GEN6_BLITTER_LOCK_SHIFT); | |
1615 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); | |
1616 | POSTING_READ(GEN6_BLITTER_ECOSKPD); | |
fcca7926 | 1617 | gen6_gt_force_wake_put(dev_priv); |
4efe0708 JB |
1618 | } |
1619 | ||
b52eb4dc ZY |
1620 | static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
1621 | { | |
1622 | struct drm_device *dev = crtc->dev; | |
1623 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1624 | struct drm_framebuffer *fb = crtc->fb; | |
1625 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 1626 | struct drm_i915_gem_object *obj = intel_fb->obj; |
b52eb4dc | 1627 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5eddb70b | 1628 | int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB; |
b52eb4dc ZY |
1629 | unsigned long stall_watermark = 200; |
1630 | u32 dpfc_ctl; | |
1631 | ||
bed4a673 | 1632 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); |
b52eb4dc ZY |
1633 | dpfc_ctl &= DPFC_RESERVED; |
1634 | dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X); | |
9ce9d069 CW |
1635 | /* Set persistent mode for front-buffer rendering, ala X. */ |
1636 | dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE; | |
016b9b61 | 1637 | dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg); |
de568510 | 1638 | I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY); |
b52eb4dc | 1639 | |
b52eb4dc ZY |
1640 | I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN | |
1641 | (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) | | |
1642 | (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT)); | |
1643 | I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y); | |
05394f39 | 1644 | I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID); |
b52eb4dc | 1645 | /* enable it... */ |
bed4a673 | 1646 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); |
b52eb4dc | 1647 | |
9c04f015 YL |
1648 | if (IS_GEN6(dev)) { |
1649 | I915_WRITE(SNB_DPFC_CTL_SA, | |
016b9b61 | 1650 | SNB_CPU_FENCE_ENABLE | obj->fence_reg); |
9c04f015 | 1651 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y); |
4efe0708 | 1652 | sandybridge_blit_fbc_update(dev); |
9c04f015 YL |
1653 | } |
1654 | ||
b52eb4dc ZY |
1655 | DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane); |
1656 | } | |
1657 | ||
43a9539f | 1658 | static void ironlake_disable_fbc(struct drm_device *dev) |
b52eb4dc ZY |
1659 | { |
1660 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1661 | u32 dpfc_ctl; | |
1662 | ||
1663 | /* Disable compression */ | |
1664 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); | |
bed4a673 CW |
1665 | if (dpfc_ctl & DPFC_CTL_EN) { |
1666 | dpfc_ctl &= ~DPFC_CTL_EN; | |
1667 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); | |
b52eb4dc | 1668 | |
bed4a673 CW |
1669 | DRM_DEBUG_KMS("disabled FBC\n"); |
1670 | } | |
b52eb4dc ZY |
1671 | } |
1672 | ||
1673 | static bool ironlake_fbc_enabled(struct drm_device *dev) | |
1674 | { | |
1675 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1676 | ||
1677 | return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN; | |
1678 | } | |
1679 | ||
ee5382ae AJ |
1680 | bool intel_fbc_enabled(struct drm_device *dev) |
1681 | { | |
1682 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1683 | ||
1684 | if (!dev_priv->display.fbc_enabled) | |
1685 | return false; | |
1686 | ||
1687 | return dev_priv->display.fbc_enabled(dev); | |
1688 | } | |
1689 | ||
1630fe75 CW |
1690 | static void intel_fbc_work_fn(struct work_struct *__work) |
1691 | { | |
1692 | struct intel_fbc_work *work = | |
1693 | container_of(to_delayed_work(__work), | |
1694 | struct intel_fbc_work, work); | |
1695 | struct drm_device *dev = work->crtc->dev; | |
1696 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1697 | ||
1698 | mutex_lock(&dev->struct_mutex); | |
1699 | if (work == dev_priv->fbc_work) { | |
1700 | /* Double check that we haven't switched fb without cancelling | |
1701 | * the prior work. | |
1702 | */ | |
016b9b61 | 1703 | if (work->crtc->fb == work->fb) { |
1630fe75 CW |
1704 | dev_priv->display.enable_fbc(work->crtc, |
1705 | work->interval); | |
1706 | ||
016b9b61 CW |
1707 | dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane; |
1708 | dev_priv->cfb_fb = work->crtc->fb->base.id; | |
1709 | dev_priv->cfb_y = work->crtc->y; | |
1710 | } | |
1711 | ||
1630fe75 CW |
1712 | dev_priv->fbc_work = NULL; |
1713 | } | |
1714 | mutex_unlock(&dev->struct_mutex); | |
1715 | ||
1716 | kfree(work); | |
1717 | } | |
1718 | ||
1719 | static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv) | |
1720 | { | |
1721 | if (dev_priv->fbc_work == NULL) | |
1722 | return; | |
1723 | ||
1724 | DRM_DEBUG_KMS("cancelling pending FBC enable\n"); | |
1725 | ||
1726 | /* Synchronisation is provided by struct_mutex and checking of | |
1727 | * dev_priv->fbc_work, so we can perform the cancellation | |
1728 | * entirely asynchronously. | |
1729 | */ | |
1730 | if (cancel_delayed_work(&dev_priv->fbc_work->work)) | |
1731 | /* tasklet was killed before being run, clean up */ | |
1732 | kfree(dev_priv->fbc_work); | |
1733 | ||
1734 | /* Mark the work as no longer wanted so that if it does | |
1735 | * wake-up (because the work was already running and waiting | |
1736 | * for our mutex), it will discover that is no longer | |
1737 | * necessary to run. | |
1738 | */ | |
1739 | dev_priv->fbc_work = NULL; | |
1740 | } | |
1741 | ||
43a9539f | 1742 | static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
ee5382ae | 1743 | { |
1630fe75 CW |
1744 | struct intel_fbc_work *work; |
1745 | struct drm_device *dev = crtc->dev; | |
1746 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee5382ae AJ |
1747 | |
1748 | if (!dev_priv->display.enable_fbc) | |
1749 | return; | |
1750 | ||
1630fe75 CW |
1751 | intel_cancel_fbc_work(dev_priv); |
1752 | ||
1753 | work = kzalloc(sizeof *work, GFP_KERNEL); | |
1754 | if (work == NULL) { | |
1755 | dev_priv->display.enable_fbc(crtc, interval); | |
1756 | return; | |
1757 | } | |
1758 | ||
1759 | work->crtc = crtc; | |
1760 | work->fb = crtc->fb; | |
1761 | work->interval = interval; | |
1762 | INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn); | |
1763 | ||
1764 | dev_priv->fbc_work = work; | |
1765 | ||
1766 | DRM_DEBUG_KMS("scheduling delayed FBC enable\n"); | |
1767 | ||
1768 | /* Delay the actual enabling to let pageflipping cease and the | |
016b9b61 CW |
1769 | * display to settle before starting the compression. Note that |
1770 | * this delay also serves a second purpose: it allows for a | |
1771 | * vblank to pass after disabling the FBC before we attempt | |
1772 | * to modify the control registers. | |
1630fe75 CW |
1773 | * |
1774 | * A more complicated solution would involve tracking vblanks | |
1775 | * following the termination of the page-flipping sequence | |
1776 | * and indeed performing the enable as a co-routine and not | |
1777 | * waiting synchronously upon the vblank. | |
1778 | */ | |
1779 | schedule_delayed_work(&work->work, msecs_to_jiffies(50)); | |
ee5382ae AJ |
1780 | } |
1781 | ||
1782 | void intel_disable_fbc(struct drm_device *dev) | |
1783 | { | |
1784 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1785 | ||
1630fe75 CW |
1786 | intel_cancel_fbc_work(dev_priv); |
1787 | ||
ee5382ae AJ |
1788 | if (!dev_priv->display.disable_fbc) |
1789 | return; | |
1790 | ||
1791 | dev_priv->display.disable_fbc(dev); | |
016b9b61 | 1792 | dev_priv->cfb_plane = -1; |
ee5382ae AJ |
1793 | } |
1794 | ||
80824003 JB |
1795 | /** |
1796 | * intel_update_fbc - enable/disable FBC as needed | |
bed4a673 | 1797 | * @dev: the drm_device |
80824003 JB |
1798 | * |
1799 | * Set up the framebuffer compression hardware at mode set time. We | |
1800 | * enable it if possible: | |
1801 | * - plane A only (on pre-965) | |
1802 | * - no pixel mulitply/line duplication | |
1803 | * - no alpha buffer discard | |
1804 | * - no dual wide | |
1805 | * - framebuffer <= 2048 in width, 1536 in height | |
1806 | * | |
1807 | * We can't assume that any compression will take place (worst case), | |
1808 | * so the compressed buffer has to be the same size as the uncompressed | |
1809 | * one. It also must reside (along with the line length buffer) in | |
1810 | * stolen memory. | |
1811 | * | |
1812 | * We need to enable/disable FBC on a global basis. | |
1813 | */ | |
bed4a673 | 1814 | static void intel_update_fbc(struct drm_device *dev) |
80824003 | 1815 | { |
80824003 | 1816 | struct drm_i915_private *dev_priv = dev->dev_private; |
bed4a673 CW |
1817 | struct drm_crtc *crtc = NULL, *tmp_crtc; |
1818 | struct intel_crtc *intel_crtc; | |
1819 | struct drm_framebuffer *fb; | |
80824003 | 1820 | struct intel_framebuffer *intel_fb; |
05394f39 | 1821 | struct drm_i915_gem_object *obj; |
cd0de039 | 1822 | int enable_fbc; |
9c928d16 JB |
1823 | |
1824 | DRM_DEBUG_KMS("\n"); | |
80824003 JB |
1825 | |
1826 | if (!i915_powersave) | |
1827 | return; | |
1828 | ||
ee5382ae | 1829 | if (!I915_HAS_FBC(dev)) |
e70236a8 JB |
1830 | return; |
1831 | ||
80824003 JB |
1832 | /* |
1833 | * If FBC is already on, we just have to verify that we can | |
1834 | * keep it that way... | |
1835 | * Need to disable if: | |
9c928d16 | 1836 | * - more than one pipe is active |
80824003 JB |
1837 | * - changing FBC params (stride, fence, mode) |
1838 | * - new fb is too large to fit in compressed buffer | |
1839 | * - going to an unsupported config (interlace, pixel multiply, etc.) | |
1840 | */ | |
9c928d16 | 1841 | list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) { |
d210246a | 1842 | if (tmp_crtc->enabled && tmp_crtc->fb) { |
bed4a673 CW |
1843 | if (crtc) { |
1844 | DRM_DEBUG_KMS("more than one pipe active, disabling compression\n"); | |
1845 | dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES; | |
1846 | goto out_disable; | |
1847 | } | |
1848 | crtc = tmp_crtc; | |
1849 | } | |
9c928d16 | 1850 | } |
bed4a673 CW |
1851 | |
1852 | if (!crtc || crtc->fb == NULL) { | |
1853 | DRM_DEBUG_KMS("no output, disabling\n"); | |
1854 | dev_priv->no_fbc_reason = FBC_NO_OUTPUT; | |
9c928d16 JB |
1855 | goto out_disable; |
1856 | } | |
bed4a673 CW |
1857 | |
1858 | intel_crtc = to_intel_crtc(crtc); | |
1859 | fb = crtc->fb; | |
1860 | intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 1861 | obj = intel_fb->obj; |
bed4a673 | 1862 | |
cd0de039 KP |
1863 | enable_fbc = i915_enable_fbc; |
1864 | if (enable_fbc < 0) { | |
1865 | DRM_DEBUG_KMS("fbc set to per-chip default\n"); | |
1866 | enable_fbc = 1; | |
1867 | if (INTEL_INFO(dev)->gen <= 5) | |
1868 | enable_fbc = 0; | |
1869 | } | |
1870 | if (!enable_fbc) { | |
1871 | DRM_DEBUG_KMS("fbc disabled per module param\n"); | |
c1a9f047 JB |
1872 | dev_priv->no_fbc_reason = FBC_MODULE_PARAM; |
1873 | goto out_disable; | |
1874 | } | |
05394f39 | 1875 | if (intel_fb->obj->base.size > dev_priv->cfb_size) { |
28c97730 | 1876 | DRM_DEBUG_KMS("framebuffer too large, disabling " |
5eddb70b | 1877 | "compression\n"); |
b5e50c3f | 1878 | dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL; |
80824003 JB |
1879 | goto out_disable; |
1880 | } | |
bed4a673 CW |
1881 | if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) || |
1882 | (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) { | |
28c97730 | 1883 | DRM_DEBUG_KMS("mode incompatible with compression, " |
5eddb70b | 1884 | "disabling\n"); |
b5e50c3f | 1885 | dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE; |
80824003 JB |
1886 | goto out_disable; |
1887 | } | |
bed4a673 CW |
1888 | if ((crtc->mode.hdisplay > 2048) || |
1889 | (crtc->mode.vdisplay > 1536)) { | |
28c97730 | 1890 | DRM_DEBUG_KMS("mode too large for compression, disabling\n"); |
b5e50c3f | 1891 | dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE; |
80824003 JB |
1892 | goto out_disable; |
1893 | } | |
bed4a673 | 1894 | if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) { |
28c97730 | 1895 | DRM_DEBUG_KMS("plane not 0, disabling compression\n"); |
b5e50c3f | 1896 | dev_priv->no_fbc_reason = FBC_BAD_PLANE; |
80824003 JB |
1897 | goto out_disable; |
1898 | } | |
de568510 CW |
1899 | |
1900 | /* The use of a CPU fence is mandatory in order to detect writes | |
1901 | * by the CPU to the scanout and trigger updates to the FBC. | |
1902 | */ | |
1903 | if (obj->tiling_mode != I915_TILING_X || | |
1904 | obj->fence_reg == I915_FENCE_REG_NONE) { | |
1905 | DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n"); | |
b5e50c3f | 1906 | dev_priv->no_fbc_reason = FBC_NOT_TILED; |
80824003 JB |
1907 | goto out_disable; |
1908 | } | |
1909 | ||
c924b934 JW |
1910 | /* If the kernel debugger is active, always disable compression */ |
1911 | if (in_dbg_master()) | |
1912 | goto out_disable; | |
1913 | ||
016b9b61 CW |
1914 | /* If the scanout has not changed, don't modify the FBC settings. |
1915 | * Note that we make the fundamental assumption that the fb->obj | |
1916 | * cannot be unpinned (and have its GTT offset and fence revoked) | |
1917 | * without first being decoupled from the scanout and FBC disabled. | |
1918 | */ | |
1919 | if (dev_priv->cfb_plane == intel_crtc->plane && | |
1920 | dev_priv->cfb_fb == fb->base.id && | |
1921 | dev_priv->cfb_y == crtc->y) | |
1922 | return; | |
1923 | ||
1924 | if (intel_fbc_enabled(dev)) { | |
1925 | /* We update FBC along two paths, after changing fb/crtc | |
1926 | * configuration (modeswitching) and after page-flipping | |
1927 | * finishes. For the latter, we know that not only did | |
1928 | * we disable the FBC at the start of the page-flip | |
1929 | * sequence, but also more than one vblank has passed. | |
1930 | * | |
1931 | * For the former case of modeswitching, it is possible | |
1932 | * to switch between two FBC valid configurations | |
1933 | * instantaneously so we do need to disable the FBC | |
1934 | * before we can modify its control registers. We also | |
1935 | * have to wait for the next vblank for that to take | |
1936 | * effect. However, since we delay enabling FBC we can | |
1937 | * assume that a vblank has passed since disabling and | |
1938 | * that we can safely alter the registers in the deferred | |
1939 | * callback. | |
1940 | * | |
1941 | * In the scenario that we go from a valid to invalid | |
1942 | * and then back to valid FBC configuration we have | |
1943 | * no strict enforcement that a vblank occurred since | |
1944 | * disabling the FBC. However, along all current pipe | |
1945 | * disabling paths we do need to wait for a vblank at | |
1946 | * some point. And we wait before enabling FBC anyway. | |
1947 | */ | |
1948 | DRM_DEBUG_KMS("disabling active FBC for update\n"); | |
1949 | intel_disable_fbc(dev); | |
1950 | } | |
1951 | ||
bed4a673 | 1952 | intel_enable_fbc(crtc, 500); |
80824003 JB |
1953 | return; |
1954 | ||
1955 | out_disable: | |
80824003 | 1956 | /* Multiple disables should be harmless */ |
a939406f CW |
1957 | if (intel_fbc_enabled(dev)) { |
1958 | DRM_DEBUG_KMS("unsupported config, disabling FBC\n"); | |
ee5382ae | 1959 | intel_disable_fbc(dev); |
a939406f | 1960 | } |
80824003 JB |
1961 | } |
1962 | ||
127bd2ac | 1963 | int |
48b956c5 | 1964 | intel_pin_and_fence_fb_obj(struct drm_device *dev, |
05394f39 | 1965 | struct drm_i915_gem_object *obj, |
919926ae | 1966 | struct intel_ring_buffer *pipelined) |
6b95a207 | 1967 | { |
ce453d81 | 1968 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
1969 | u32 alignment; |
1970 | int ret; | |
1971 | ||
05394f39 | 1972 | switch (obj->tiling_mode) { |
6b95a207 | 1973 | case I915_TILING_NONE: |
534843da CW |
1974 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
1975 | alignment = 128 * 1024; | |
a6c45cf0 | 1976 | else if (INTEL_INFO(dev)->gen >= 4) |
534843da CW |
1977 | alignment = 4 * 1024; |
1978 | else | |
1979 | alignment = 64 * 1024; | |
6b95a207 KH |
1980 | break; |
1981 | case I915_TILING_X: | |
1982 | /* pin() will align the object as required by fence */ | |
1983 | alignment = 0; | |
1984 | break; | |
1985 | case I915_TILING_Y: | |
1986 | /* FIXME: Is this true? */ | |
1987 | DRM_ERROR("Y tiled not allowed for scan out buffers\n"); | |
1988 | return -EINVAL; | |
1989 | default: | |
1990 | BUG(); | |
1991 | } | |
1992 | ||
ce453d81 | 1993 | dev_priv->mm.interruptible = false; |
2da3b9b9 | 1994 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined); |
48b956c5 | 1995 | if (ret) |
ce453d81 | 1996 | goto err_interruptible; |
6b95a207 KH |
1997 | |
1998 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
1999 | * fence, whereas 965+ only requires a fence if using | |
2000 | * framebuffer compression. For simplicity, we always install | |
2001 | * a fence as the cost is not that onerous. | |
2002 | */ | |
05394f39 | 2003 | if (obj->tiling_mode != I915_TILING_NONE) { |
ce453d81 | 2004 | ret = i915_gem_object_get_fence(obj, pipelined); |
48b956c5 CW |
2005 | if (ret) |
2006 | goto err_unpin; | |
6b95a207 KH |
2007 | } |
2008 | ||
ce453d81 | 2009 | dev_priv->mm.interruptible = true; |
6b95a207 | 2010 | return 0; |
48b956c5 CW |
2011 | |
2012 | err_unpin: | |
2013 | i915_gem_object_unpin(obj); | |
ce453d81 CW |
2014 | err_interruptible: |
2015 | dev_priv->mm.interruptible = true; | |
48b956c5 | 2016 | return ret; |
6b95a207 KH |
2017 | } |
2018 | ||
17638cd6 JB |
2019 | static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
2020 | int x, int y) | |
81255565 JB |
2021 | { |
2022 | struct drm_device *dev = crtc->dev; | |
2023 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2024 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2025 | struct intel_framebuffer *intel_fb; | |
05394f39 | 2026 | struct drm_i915_gem_object *obj; |
81255565 JB |
2027 | int plane = intel_crtc->plane; |
2028 | unsigned long Start, Offset; | |
81255565 | 2029 | u32 dspcntr; |
5eddb70b | 2030 | u32 reg; |
81255565 JB |
2031 | |
2032 | switch (plane) { | |
2033 | case 0: | |
2034 | case 1: | |
2035 | break; | |
2036 | default: | |
2037 | DRM_ERROR("Can't update plane %d in SAREA\n", plane); | |
2038 | return -EINVAL; | |
2039 | } | |
2040 | ||
2041 | intel_fb = to_intel_framebuffer(fb); | |
2042 | obj = intel_fb->obj; | |
81255565 | 2043 | |
5eddb70b CW |
2044 | reg = DSPCNTR(plane); |
2045 | dspcntr = I915_READ(reg); | |
81255565 JB |
2046 | /* Mask out pixel format bits in case we change it */ |
2047 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
2048 | switch (fb->bits_per_pixel) { | |
2049 | case 8: | |
2050 | dspcntr |= DISPPLANE_8BPP; | |
2051 | break; | |
2052 | case 16: | |
2053 | if (fb->depth == 15) | |
2054 | dspcntr |= DISPPLANE_15_16BPP; | |
2055 | else | |
2056 | dspcntr |= DISPPLANE_16BPP; | |
2057 | break; | |
2058 | case 24: | |
2059 | case 32: | |
2060 | dspcntr |= DISPPLANE_32BPP_NO_ALPHA; | |
2061 | break; | |
2062 | default: | |
17638cd6 | 2063 | DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel); |
81255565 JB |
2064 | return -EINVAL; |
2065 | } | |
a6c45cf0 | 2066 | if (INTEL_INFO(dev)->gen >= 4) { |
05394f39 | 2067 | if (obj->tiling_mode != I915_TILING_NONE) |
81255565 JB |
2068 | dspcntr |= DISPPLANE_TILED; |
2069 | else | |
2070 | dspcntr &= ~DISPPLANE_TILED; | |
2071 | } | |
2072 | ||
5eddb70b | 2073 | I915_WRITE(reg, dspcntr); |
81255565 | 2074 | |
05394f39 | 2075 | Start = obj->gtt_offset; |
81255565 JB |
2076 | Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8); |
2077 | ||
4e6cfefc CW |
2078 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2079 | Start, Offset, x, y, fb->pitch); | |
5eddb70b | 2080 | I915_WRITE(DSPSTRIDE(plane), fb->pitch); |
a6c45cf0 | 2081 | if (INTEL_INFO(dev)->gen >= 4) { |
5eddb70b CW |
2082 | I915_WRITE(DSPSURF(plane), Start); |
2083 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2084 | I915_WRITE(DSPADDR(plane), Offset); | |
2085 | } else | |
2086 | I915_WRITE(DSPADDR(plane), Start + Offset); | |
2087 | POSTING_READ(reg); | |
81255565 | 2088 | |
17638cd6 JB |
2089 | return 0; |
2090 | } | |
2091 | ||
2092 | static int ironlake_update_plane(struct drm_crtc *crtc, | |
2093 | struct drm_framebuffer *fb, int x, int y) | |
2094 | { | |
2095 | struct drm_device *dev = crtc->dev; | |
2096 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2097 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2098 | struct intel_framebuffer *intel_fb; | |
2099 | struct drm_i915_gem_object *obj; | |
2100 | int plane = intel_crtc->plane; | |
2101 | unsigned long Start, Offset; | |
2102 | u32 dspcntr; | |
2103 | u32 reg; | |
2104 | ||
2105 | switch (plane) { | |
2106 | case 0: | |
2107 | case 1: | |
27f8227b | 2108 | case 2: |
17638cd6 JB |
2109 | break; |
2110 | default: | |
2111 | DRM_ERROR("Can't update plane %d in SAREA\n", plane); | |
2112 | return -EINVAL; | |
2113 | } | |
2114 | ||
2115 | intel_fb = to_intel_framebuffer(fb); | |
2116 | obj = intel_fb->obj; | |
2117 | ||
2118 | reg = DSPCNTR(plane); | |
2119 | dspcntr = I915_READ(reg); | |
2120 | /* Mask out pixel format bits in case we change it */ | |
2121 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
2122 | switch (fb->bits_per_pixel) { | |
2123 | case 8: | |
2124 | dspcntr |= DISPPLANE_8BPP; | |
2125 | break; | |
2126 | case 16: | |
2127 | if (fb->depth != 16) | |
2128 | return -EINVAL; | |
2129 | ||
2130 | dspcntr |= DISPPLANE_16BPP; | |
2131 | break; | |
2132 | case 24: | |
2133 | case 32: | |
2134 | if (fb->depth == 24) | |
2135 | dspcntr |= DISPPLANE_32BPP_NO_ALPHA; | |
2136 | else if (fb->depth == 30) | |
2137 | dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA; | |
2138 | else | |
2139 | return -EINVAL; | |
2140 | break; | |
2141 | default: | |
2142 | DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel); | |
2143 | return -EINVAL; | |
2144 | } | |
2145 | ||
2146 | if (obj->tiling_mode != I915_TILING_NONE) | |
2147 | dspcntr |= DISPPLANE_TILED; | |
2148 | else | |
2149 | dspcntr &= ~DISPPLANE_TILED; | |
2150 | ||
2151 | /* must disable */ | |
2152 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2153 | ||
2154 | I915_WRITE(reg, dspcntr); | |
2155 | ||
2156 | Start = obj->gtt_offset; | |
2157 | Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8); | |
2158 | ||
2159 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", | |
2160 | Start, Offset, x, y, fb->pitch); | |
2161 | I915_WRITE(DSPSTRIDE(plane), fb->pitch); | |
2162 | I915_WRITE(DSPSURF(plane), Start); | |
2163 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2164 | I915_WRITE(DSPADDR(plane), Offset); | |
2165 | POSTING_READ(reg); | |
2166 | ||
2167 | return 0; | |
2168 | } | |
2169 | ||
2170 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ | |
2171 | static int | |
2172 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
2173 | int x, int y, enum mode_set_atomic state) | |
2174 | { | |
2175 | struct drm_device *dev = crtc->dev; | |
2176 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2177 | int ret; | |
2178 | ||
2179 | ret = dev_priv->display.update_plane(crtc, fb, x, y); | |
2180 | if (ret) | |
2181 | return ret; | |
2182 | ||
bed4a673 | 2183 | intel_update_fbc(dev); |
3dec0095 | 2184 | intel_increase_pllclock(crtc); |
81255565 JB |
2185 | |
2186 | return 0; | |
2187 | } | |
2188 | ||
5c3b82e2 | 2189 | static int |
3c4fdcfb KH |
2190 | intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
2191 | struct drm_framebuffer *old_fb) | |
79e53945 JB |
2192 | { |
2193 | struct drm_device *dev = crtc->dev; | |
79e53945 JB |
2194 | struct drm_i915_master_private *master_priv; |
2195 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5c3b82e2 | 2196 | int ret; |
79e53945 JB |
2197 | |
2198 | /* no fb bound */ | |
2199 | if (!crtc->fb) { | |
a5071c2f | 2200 | DRM_ERROR("No FB bound\n"); |
5c3b82e2 CW |
2201 | return 0; |
2202 | } | |
2203 | ||
265db958 | 2204 | switch (intel_crtc->plane) { |
5c3b82e2 CW |
2205 | case 0: |
2206 | case 1: | |
2207 | break; | |
27f8227b JB |
2208 | case 2: |
2209 | if (IS_IVYBRIDGE(dev)) | |
2210 | break; | |
2211 | /* fall through otherwise */ | |
5c3b82e2 | 2212 | default: |
a5071c2f | 2213 | DRM_ERROR("no plane for crtc\n"); |
5c3b82e2 | 2214 | return -EINVAL; |
79e53945 JB |
2215 | } |
2216 | ||
5c3b82e2 | 2217 | mutex_lock(&dev->struct_mutex); |
265db958 CW |
2218 | ret = intel_pin_and_fence_fb_obj(dev, |
2219 | to_intel_framebuffer(crtc->fb)->obj, | |
919926ae | 2220 | NULL); |
5c3b82e2 CW |
2221 | if (ret != 0) { |
2222 | mutex_unlock(&dev->struct_mutex); | |
a5071c2f | 2223 | DRM_ERROR("pin & fence failed\n"); |
5c3b82e2 CW |
2224 | return ret; |
2225 | } | |
79e53945 | 2226 | |
265db958 | 2227 | if (old_fb) { |
e6c3a2a6 | 2228 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 2229 | struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj; |
265db958 | 2230 | |
e6c3a2a6 | 2231 | wait_event(dev_priv->pending_flip_queue, |
01eec727 | 2232 | atomic_read(&dev_priv->mm.wedged) || |
05394f39 | 2233 | atomic_read(&obj->pending_flip) == 0); |
85345517 CW |
2234 | |
2235 | /* Big Hammer, we also need to ensure that any pending | |
2236 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
2237 | * current scanout is retired before unpinning the old | |
2238 | * framebuffer. | |
01eec727 CW |
2239 | * |
2240 | * This should only fail upon a hung GPU, in which case we | |
2241 | * can safely continue. | |
85345517 | 2242 | */ |
a8198eea | 2243 | ret = i915_gem_object_finish_gpu(obj); |
01eec727 | 2244 | (void) ret; |
265db958 CW |
2245 | } |
2246 | ||
21c74a8e JW |
2247 | ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y, |
2248 | LEAVE_ATOMIC_MODE_SET); | |
4e6cfefc | 2249 | if (ret) { |
265db958 | 2250 | i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj); |
5c3b82e2 | 2251 | mutex_unlock(&dev->struct_mutex); |
a5071c2f | 2252 | DRM_ERROR("failed to update base address\n"); |
4e6cfefc | 2253 | return ret; |
79e53945 | 2254 | } |
3c4fdcfb | 2255 | |
b7f1de28 CW |
2256 | if (old_fb) { |
2257 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
265db958 | 2258 | i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj); |
b7f1de28 | 2259 | } |
652c393a | 2260 | |
5c3b82e2 | 2261 | mutex_unlock(&dev->struct_mutex); |
79e53945 JB |
2262 | |
2263 | if (!dev->primary->master) | |
5c3b82e2 | 2264 | return 0; |
79e53945 JB |
2265 | |
2266 | master_priv = dev->primary->master->driver_priv; | |
2267 | if (!master_priv->sarea_priv) | |
5c3b82e2 | 2268 | return 0; |
79e53945 | 2269 | |
265db958 | 2270 | if (intel_crtc->pipe) { |
79e53945 JB |
2271 | master_priv->sarea_priv->pipeB_x = x; |
2272 | master_priv->sarea_priv->pipeB_y = y; | |
5c3b82e2 CW |
2273 | } else { |
2274 | master_priv->sarea_priv->pipeA_x = x; | |
2275 | master_priv->sarea_priv->pipeA_y = y; | |
79e53945 | 2276 | } |
5c3b82e2 CW |
2277 | |
2278 | return 0; | |
79e53945 JB |
2279 | } |
2280 | ||
5eddb70b | 2281 | static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock) |
32f9d658 ZW |
2282 | { |
2283 | struct drm_device *dev = crtc->dev; | |
2284 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2285 | u32 dpa_ctl; | |
2286 | ||
28c97730 | 2287 | DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock); |
32f9d658 ZW |
2288 | dpa_ctl = I915_READ(DP_A); |
2289 | dpa_ctl &= ~DP_PLL_FREQ_MASK; | |
2290 | ||
2291 | if (clock < 200000) { | |
2292 | u32 temp; | |
2293 | dpa_ctl |= DP_PLL_FREQ_160MHZ; | |
2294 | /* workaround for 160Mhz: | |
2295 | 1) program 0x4600c bits 15:0 = 0x8124 | |
2296 | 2) program 0x46010 bit 0 = 1 | |
2297 | 3) program 0x46034 bit 24 = 1 | |
2298 | 4) program 0x64000 bit 14 = 1 | |
2299 | */ | |
2300 | temp = I915_READ(0x4600c); | |
2301 | temp &= 0xffff0000; | |
2302 | I915_WRITE(0x4600c, temp | 0x8124); | |
2303 | ||
2304 | temp = I915_READ(0x46010); | |
2305 | I915_WRITE(0x46010, temp | 1); | |
2306 | ||
2307 | temp = I915_READ(0x46034); | |
2308 | I915_WRITE(0x46034, temp | (1 << 24)); | |
2309 | } else { | |
2310 | dpa_ctl |= DP_PLL_FREQ_270MHZ; | |
2311 | } | |
2312 | I915_WRITE(DP_A, dpa_ctl); | |
2313 | ||
5eddb70b | 2314 | POSTING_READ(DP_A); |
32f9d658 ZW |
2315 | udelay(500); |
2316 | } | |
2317 | ||
5e84e1a4 ZW |
2318 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
2319 | { | |
2320 | struct drm_device *dev = crtc->dev; | |
2321 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2322 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2323 | int pipe = intel_crtc->pipe; | |
2324 | u32 reg, temp; | |
2325 | ||
2326 | /* enable normal train */ | |
2327 | reg = FDI_TX_CTL(pipe); | |
2328 | temp = I915_READ(reg); | |
61e499bf | 2329 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
2330 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
2331 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
2332 | } else { |
2333 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2334 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 2335 | } |
5e84e1a4 ZW |
2336 | I915_WRITE(reg, temp); |
2337 | ||
2338 | reg = FDI_RX_CTL(pipe); | |
2339 | temp = I915_READ(reg); | |
2340 | if (HAS_PCH_CPT(dev)) { | |
2341 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2342 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
2343 | } else { | |
2344 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2345 | temp |= FDI_LINK_TRAIN_NONE; | |
2346 | } | |
2347 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
2348 | ||
2349 | /* wait one idle pattern time */ | |
2350 | POSTING_READ(reg); | |
2351 | udelay(1000); | |
357555c0 JB |
2352 | |
2353 | /* IVB wants error correction enabled */ | |
2354 | if (IS_IVYBRIDGE(dev)) | |
2355 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
2356 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
2357 | } |
2358 | ||
291427f5 JB |
2359 | static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe) |
2360 | { | |
2361 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2362 | u32 flags = I915_READ(SOUTH_CHICKEN1); | |
2363 | ||
2364 | flags |= FDI_PHASE_SYNC_OVR(pipe); | |
2365 | I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */ | |
2366 | flags |= FDI_PHASE_SYNC_EN(pipe); | |
2367 | I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */ | |
2368 | POSTING_READ(SOUTH_CHICKEN1); | |
2369 | } | |
2370 | ||
8db9d77b ZW |
2371 | /* The FDI link training functions for ILK/Ibexpeak. */ |
2372 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
2373 | { | |
2374 | struct drm_device *dev = crtc->dev; | |
2375 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2376 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2377 | int pipe = intel_crtc->pipe; | |
0fc932b8 | 2378 | int plane = intel_crtc->plane; |
5eddb70b | 2379 | u32 reg, temp, tries; |
8db9d77b | 2380 | |
0fc932b8 JB |
2381 | /* FDI needs bits from pipe & plane first */ |
2382 | assert_pipe_enabled(dev_priv, pipe); | |
2383 | assert_plane_enabled(dev_priv, plane); | |
2384 | ||
e1a44743 AJ |
2385 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2386 | for train result */ | |
5eddb70b CW |
2387 | reg = FDI_RX_IMR(pipe); |
2388 | temp = I915_READ(reg); | |
e1a44743 AJ |
2389 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2390 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2391 | I915_WRITE(reg, temp); |
2392 | I915_READ(reg); | |
e1a44743 AJ |
2393 | udelay(150); |
2394 | ||
8db9d77b | 2395 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2396 | reg = FDI_TX_CTL(pipe); |
2397 | temp = I915_READ(reg); | |
77ffb597 AJ |
2398 | temp &= ~(7 << 19); |
2399 | temp |= (intel_crtc->fdi_lanes - 1) << 19; | |
8db9d77b ZW |
2400 | temp &= ~FDI_LINK_TRAIN_NONE; |
2401 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 2402 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2403 | |
5eddb70b CW |
2404 | reg = FDI_RX_CTL(pipe); |
2405 | temp = I915_READ(reg); | |
8db9d77b ZW |
2406 | temp &= ~FDI_LINK_TRAIN_NONE; |
2407 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
2408 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2409 | ||
2410 | POSTING_READ(reg); | |
8db9d77b ZW |
2411 | udelay(150); |
2412 | ||
5b2adf89 | 2413 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
6f06ce18 JB |
2414 | if (HAS_PCH_IBX(dev)) { |
2415 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); | |
2416 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
2417 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
2418 | } | |
5b2adf89 | 2419 | |
5eddb70b | 2420 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2421 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2422 | temp = I915_READ(reg); |
8db9d77b ZW |
2423 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2424 | ||
2425 | if ((temp & FDI_RX_BIT_LOCK)) { | |
2426 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 2427 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
2428 | break; |
2429 | } | |
8db9d77b | 2430 | } |
e1a44743 | 2431 | if (tries == 5) |
5eddb70b | 2432 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
2433 | |
2434 | /* Train 2 */ | |
5eddb70b CW |
2435 | reg = FDI_TX_CTL(pipe); |
2436 | temp = I915_READ(reg); | |
8db9d77b ZW |
2437 | temp &= ~FDI_LINK_TRAIN_NONE; |
2438 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2439 | I915_WRITE(reg, temp); |
8db9d77b | 2440 | |
5eddb70b CW |
2441 | reg = FDI_RX_CTL(pipe); |
2442 | temp = I915_READ(reg); | |
8db9d77b ZW |
2443 | temp &= ~FDI_LINK_TRAIN_NONE; |
2444 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2445 | I915_WRITE(reg, temp); |
8db9d77b | 2446 | |
5eddb70b CW |
2447 | POSTING_READ(reg); |
2448 | udelay(150); | |
8db9d77b | 2449 | |
5eddb70b | 2450 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2451 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2452 | temp = I915_READ(reg); |
8db9d77b ZW |
2453 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2454 | ||
2455 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 2456 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
2457 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
2458 | break; | |
2459 | } | |
8db9d77b | 2460 | } |
e1a44743 | 2461 | if (tries == 5) |
5eddb70b | 2462 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
2463 | |
2464 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 2465 | |
8db9d77b ZW |
2466 | } |
2467 | ||
0206e353 | 2468 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
2469 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
2470 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
2471 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
2472 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
2473 | }; | |
2474 | ||
2475 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
2476 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
2477 | { | |
2478 | struct drm_device *dev = crtc->dev; | |
2479 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2480 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2481 | int pipe = intel_crtc->pipe; | |
5eddb70b | 2482 | u32 reg, temp, i; |
8db9d77b | 2483 | |
e1a44743 AJ |
2484 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2485 | for train result */ | |
5eddb70b CW |
2486 | reg = FDI_RX_IMR(pipe); |
2487 | temp = I915_READ(reg); | |
e1a44743 AJ |
2488 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2489 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2490 | I915_WRITE(reg, temp); |
2491 | ||
2492 | POSTING_READ(reg); | |
e1a44743 AJ |
2493 | udelay(150); |
2494 | ||
8db9d77b | 2495 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2496 | reg = FDI_TX_CTL(pipe); |
2497 | temp = I915_READ(reg); | |
77ffb597 AJ |
2498 | temp &= ~(7 << 19); |
2499 | temp |= (intel_crtc->fdi_lanes - 1) << 19; | |
8db9d77b ZW |
2500 | temp &= ~FDI_LINK_TRAIN_NONE; |
2501 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2502 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2503 | /* SNB-B */ | |
2504 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 2505 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2506 | |
5eddb70b CW |
2507 | reg = FDI_RX_CTL(pipe); |
2508 | temp = I915_READ(reg); | |
8db9d77b ZW |
2509 | if (HAS_PCH_CPT(dev)) { |
2510 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2511 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
2512 | } else { | |
2513 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2514 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2515 | } | |
5eddb70b CW |
2516 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2517 | ||
2518 | POSTING_READ(reg); | |
8db9d77b ZW |
2519 | udelay(150); |
2520 | ||
291427f5 JB |
2521 | if (HAS_PCH_CPT(dev)) |
2522 | cpt_phase_pointer_enable(dev, pipe); | |
2523 | ||
0206e353 | 2524 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
2525 | reg = FDI_TX_CTL(pipe); |
2526 | temp = I915_READ(reg); | |
8db9d77b ZW |
2527 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2528 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
2529 | I915_WRITE(reg, temp); |
2530 | ||
2531 | POSTING_READ(reg); | |
8db9d77b ZW |
2532 | udelay(500); |
2533 | ||
5eddb70b CW |
2534 | reg = FDI_RX_IIR(pipe); |
2535 | temp = I915_READ(reg); | |
8db9d77b ZW |
2536 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2537 | ||
2538 | if (temp & FDI_RX_BIT_LOCK) { | |
5eddb70b | 2539 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
2540 | DRM_DEBUG_KMS("FDI train 1 done.\n"); |
2541 | break; | |
2542 | } | |
2543 | } | |
2544 | if (i == 4) | |
5eddb70b | 2545 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
2546 | |
2547 | /* Train 2 */ | |
5eddb70b CW |
2548 | reg = FDI_TX_CTL(pipe); |
2549 | temp = I915_READ(reg); | |
8db9d77b ZW |
2550 | temp &= ~FDI_LINK_TRAIN_NONE; |
2551 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
2552 | if (IS_GEN6(dev)) { | |
2553 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2554 | /* SNB-B */ | |
2555 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
2556 | } | |
5eddb70b | 2557 | I915_WRITE(reg, temp); |
8db9d77b | 2558 | |
5eddb70b CW |
2559 | reg = FDI_RX_CTL(pipe); |
2560 | temp = I915_READ(reg); | |
8db9d77b ZW |
2561 | if (HAS_PCH_CPT(dev)) { |
2562 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2563 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
2564 | } else { | |
2565 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2566 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
2567 | } | |
5eddb70b CW |
2568 | I915_WRITE(reg, temp); |
2569 | ||
2570 | POSTING_READ(reg); | |
8db9d77b ZW |
2571 | udelay(150); |
2572 | ||
0206e353 | 2573 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
2574 | reg = FDI_TX_CTL(pipe); |
2575 | temp = I915_READ(reg); | |
8db9d77b ZW |
2576 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2577 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
2578 | I915_WRITE(reg, temp); |
2579 | ||
2580 | POSTING_READ(reg); | |
8db9d77b ZW |
2581 | udelay(500); |
2582 | ||
5eddb70b CW |
2583 | reg = FDI_RX_IIR(pipe); |
2584 | temp = I915_READ(reg); | |
8db9d77b ZW |
2585 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2586 | ||
2587 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 2588 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
2589 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
2590 | break; | |
2591 | } | |
2592 | } | |
2593 | if (i == 4) | |
5eddb70b | 2594 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
2595 | |
2596 | DRM_DEBUG_KMS("FDI train done.\n"); | |
2597 | } | |
2598 | ||
357555c0 JB |
2599 | /* Manual link training for Ivy Bridge A0 parts */ |
2600 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
2601 | { | |
2602 | struct drm_device *dev = crtc->dev; | |
2603 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2604 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2605 | int pipe = intel_crtc->pipe; | |
2606 | u32 reg, temp, i; | |
2607 | ||
2608 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
2609 | for train result */ | |
2610 | reg = FDI_RX_IMR(pipe); | |
2611 | temp = I915_READ(reg); | |
2612 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
2613 | temp &= ~FDI_RX_BIT_LOCK; | |
2614 | I915_WRITE(reg, temp); | |
2615 | ||
2616 | POSTING_READ(reg); | |
2617 | udelay(150); | |
2618 | ||
2619 | /* enable CPU FDI TX and PCH FDI RX */ | |
2620 | reg = FDI_TX_CTL(pipe); | |
2621 | temp = I915_READ(reg); | |
2622 | temp &= ~(7 << 19); | |
2623 | temp |= (intel_crtc->fdi_lanes - 1) << 19; | |
2624 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
2625 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; | |
2626 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2627 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
c4f9c4c2 | 2628 | temp |= FDI_COMPOSITE_SYNC; |
357555c0 JB |
2629 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
2630 | ||
2631 | reg = FDI_RX_CTL(pipe); | |
2632 | temp = I915_READ(reg); | |
2633 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
2634 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2635 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
c4f9c4c2 | 2636 | temp |= FDI_COMPOSITE_SYNC; |
357555c0 JB |
2637 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2638 | ||
2639 | POSTING_READ(reg); | |
2640 | udelay(150); | |
2641 | ||
291427f5 JB |
2642 | if (HAS_PCH_CPT(dev)) |
2643 | cpt_phase_pointer_enable(dev, pipe); | |
2644 | ||
0206e353 | 2645 | for (i = 0; i < 4; i++) { |
357555c0 JB |
2646 | reg = FDI_TX_CTL(pipe); |
2647 | temp = I915_READ(reg); | |
2648 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2649 | temp |= snb_b_fdi_train_param[i]; | |
2650 | I915_WRITE(reg, temp); | |
2651 | ||
2652 | POSTING_READ(reg); | |
2653 | udelay(500); | |
2654 | ||
2655 | reg = FDI_RX_IIR(pipe); | |
2656 | temp = I915_READ(reg); | |
2657 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2658 | ||
2659 | if (temp & FDI_RX_BIT_LOCK || | |
2660 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
2661 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
2662 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
2663 | break; | |
2664 | } | |
2665 | } | |
2666 | if (i == 4) | |
2667 | DRM_ERROR("FDI train 1 fail!\n"); | |
2668 | ||
2669 | /* Train 2 */ | |
2670 | reg = FDI_TX_CTL(pipe); | |
2671 | temp = I915_READ(reg); | |
2672 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; | |
2673 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
2674 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2675 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
2676 | I915_WRITE(reg, temp); | |
2677 | ||
2678 | reg = FDI_RX_CTL(pipe); | |
2679 | temp = I915_READ(reg); | |
2680 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2681 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
2682 | I915_WRITE(reg, temp); | |
2683 | ||
2684 | POSTING_READ(reg); | |
2685 | udelay(150); | |
2686 | ||
0206e353 | 2687 | for (i = 0; i < 4; i++) { |
357555c0 JB |
2688 | reg = FDI_TX_CTL(pipe); |
2689 | temp = I915_READ(reg); | |
2690 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2691 | temp |= snb_b_fdi_train_param[i]; | |
2692 | I915_WRITE(reg, temp); | |
2693 | ||
2694 | POSTING_READ(reg); | |
2695 | udelay(500); | |
2696 | ||
2697 | reg = FDI_RX_IIR(pipe); | |
2698 | temp = I915_READ(reg); | |
2699 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2700 | ||
2701 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
2702 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
2703 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
2704 | break; | |
2705 | } | |
2706 | } | |
2707 | if (i == 4) | |
2708 | DRM_ERROR("FDI train 2 fail!\n"); | |
2709 | ||
2710 | DRM_DEBUG_KMS("FDI train done.\n"); | |
2711 | } | |
2712 | ||
2713 | static void ironlake_fdi_pll_enable(struct drm_crtc *crtc) | |
2c07245f ZW |
2714 | { |
2715 | struct drm_device *dev = crtc->dev; | |
2716 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2717 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2718 | int pipe = intel_crtc->pipe; | |
5eddb70b | 2719 | u32 reg, temp; |
79e53945 | 2720 | |
c64e311e | 2721 | /* Write the TU size bits so error detection works */ |
5eddb70b CW |
2722 | I915_WRITE(FDI_RX_TUSIZE1(pipe), |
2723 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
c64e311e | 2724 | |
c98e9dcf | 2725 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
2726 | reg = FDI_RX_CTL(pipe); |
2727 | temp = I915_READ(reg); | |
2728 | temp &= ~((0x7 << 19) | (0x7 << 16)); | |
c98e9dcf | 2729 | temp |= (intel_crtc->fdi_lanes - 1) << 19; |
5eddb70b CW |
2730 | temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; |
2731 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); | |
2732 | ||
2733 | POSTING_READ(reg); | |
c98e9dcf JB |
2734 | udelay(200); |
2735 | ||
2736 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
2737 | temp = I915_READ(reg); |
2738 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
2739 | ||
2740 | POSTING_READ(reg); | |
c98e9dcf JB |
2741 | udelay(200); |
2742 | ||
2743 | /* Enable CPU FDI TX PLL, always on for Ironlake */ | |
5eddb70b CW |
2744 | reg = FDI_TX_CTL(pipe); |
2745 | temp = I915_READ(reg); | |
c98e9dcf | 2746 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { |
5eddb70b CW |
2747 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); |
2748 | ||
2749 | POSTING_READ(reg); | |
c98e9dcf | 2750 | udelay(100); |
6be4a607 | 2751 | } |
0e23b99d JB |
2752 | } |
2753 | ||
291427f5 JB |
2754 | static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe) |
2755 | { | |
2756 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2757 | u32 flags = I915_READ(SOUTH_CHICKEN1); | |
2758 | ||
2759 | flags &= ~(FDI_PHASE_SYNC_EN(pipe)); | |
2760 | I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */ | |
2761 | flags &= ~(FDI_PHASE_SYNC_OVR(pipe)); | |
2762 | I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */ | |
2763 | POSTING_READ(SOUTH_CHICKEN1); | |
2764 | } | |
0fc932b8 JB |
2765 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
2766 | { | |
2767 | struct drm_device *dev = crtc->dev; | |
2768 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2769 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2770 | int pipe = intel_crtc->pipe; | |
2771 | u32 reg, temp; | |
2772 | ||
2773 | /* disable CPU FDI tx and PCH FDI rx */ | |
2774 | reg = FDI_TX_CTL(pipe); | |
2775 | temp = I915_READ(reg); | |
2776 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
2777 | POSTING_READ(reg); | |
2778 | ||
2779 | reg = FDI_RX_CTL(pipe); | |
2780 | temp = I915_READ(reg); | |
2781 | temp &= ~(0x7 << 16); | |
2782 | temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; | |
2783 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); | |
2784 | ||
2785 | POSTING_READ(reg); | |
2786 | udelay(100); | |
2787 | ||
2788 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
6f06ce18 JB |
2789 | if (HAS_PCH_IBX(dev)) { |
2790 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); | |
0fc932b8 JB |
2791 | I915_WRITE(FDI_RX_CHICKEN(pipe), |
2792 | I915_READ(FDI_RX_CHICKEN(pipe) & | |
6f06ce18 | 2793 | ~FDI_RX_PHASE_SYNC_POINTER_EN)); |
291427f5 JB |
2794 | } else if (HAS_PCH_CPT(dev)) { |
2795 | cpt_phase_pointer_disable(dev, pipe); | |
6f06ce18 | 2796 | } |
0fc932b8 JB |
2797 | |
2798 | /* still set train pattern 1 */ | |
2799 | reg = FDI_TX_CTL(pipe); | |
2800 | temp = I915_READ(reg); | |
2801 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2802 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2803 | I915_WRITE(reg, temp); | |
2804 | ||
2805 | reg = FDI_RX_CTL(pipe); | |
2806 | temp = I915_READ(reg); | |
2807 | if (HAS_PCH_CPT(dev)) { | |
2808 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2809 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
2810 | } else { | |
2811 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2812 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2813 | } | |
2814 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
2815 | temp &= ~(0x07 << 16); | |
2816 | temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; | |
2817 | I915_WRITE(reg, temp); | |
2818 | ||
2819 | POSTING_READ(reg); | |
2820 | udelay(100); | |
2821 | } | |
2822 | ||
6b383a7f CW |
2823 | /* |
2824 | * When we disable a pipe, we need to clear any pending scanline wait events | |
2825 | * to avoid hanging the ring, which we assume we are waiting on. | |
2826 | */ | |
2827 | static void intel_clear_scanline_wait(struct drm_device *dev) | |
2828 | { | |
2829 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8168bd48 | 2830 | struct intel_ring_buffer *ring; |
6b383a7f CW |
2831 | u32 tmp; |
2832 | ||
2833 | if (IS_GEN2(dev)) | |
2834 | /* Can't break the hang on i8xx */ | |
2835 | return; | |
2836 | ||
1ec14ad3 | 2837 | ring = LP_RING(dev_priv); |
8168bd48 CW |
2838 | tmp = I915_READ_CTL(ring); |
2839 | if (tmp & RING_WAIT) | |
2840 | I915_WRITE_CTL(ring, tmp); | |
6b383a7f CW |
2841 | } |
2842 | ||
e6c3a2a6 CW |
2843 | static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
2844 | { | |
05394f39 | 2845 | struct drm_i915_gem_object *obj; |
e6c3a2a6 CW |
2846 | struct drm_i915_private *dev_priv; |
2847 | ||
2848 | if (crtc->fb == NULL) | |
2849 | return; | |
2850 | ||
05394f39 | 2851 | obj = to_intel_framebuffer(crtc->fb)->obj; |
e6c3a2a6 CW |
2852 | dev_priv = crtc->dev->dev_private; |
2853 | wait_event(dev_priv->pending_flip_queue, | |
05394f39 | 2854 | atomic_read(&obj->pending_flip) == 0); |
e6c3a2a6 CW |
2855 | } |
2856 | ||
040484af JB |
2857 | static bool intel_crtc_driving_pch(struct drm_crtc *crtc) |
2858 | { | |
2859 | struct drm_device *dev = crtc->dev; | |
2860 | struct drm_mode_config *mode_config = &dev->mode_config; | |
2861 | struct intel_encoder *encoder; | |
2862 | ||
2863 | /* | |
2864 | * If there's a non-PCH eDP on this crtc, it must be DP_A, and that | |
2865 | * must be driven by its own crtc; no sharing is possible. | |
2866 | */ | |
2867 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { | |
2868 | if (encoder->base.crtc != crtc) | |
2869 | continue; | |
2870 | ||
2871 | switch (encoder->type) { | |
2872 | case INTEL_OUTPUT_EDP: | |
2873 | if (!intel_encoder_is_pch_edp(&encoder->base)) | |
2874 | return false; | |
2875 | continue; | |
2876 | } | |
2877 | } | |
2878 | ||
2879 | return true; | |
2880 | } | |
2881 | ||
f67a559d JB |
2882 | /* |
2883 | * Enable PCH resources required for PCH ports: | |
2884 | * - PCH PLLs | |
2885 | * - FDI training & RX/TX | |
2886 | * - update transcoder timings | |
2887 | * - DP transcoding bits | |
2888 | * - transcoder | |
2889 | */ | |
2890 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
2891 | { |
2892 | struct drm_device *dev = crtc->dev; | |
2893 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2894 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2895 | int pipe = intel_crtc->pipe; | |
4b645f14 | 2896 | u32 reg, temp, transc_sel; |
2c07245f | 2897 | |
c98e9dcf | 2898 | /* For PCH output, training FDI link */ |
674cf967 | 2899 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 2900 | |
92f2584a | 2901 | intel_enable_pch_pll(dev_priv, pipe); |
8db9d77b | 2902 | |
c98e9dcf | 2903 | if (HAS_PCH_CPT(dev)) { |
4b645f14 JB |
2904 | transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL : |
2905 | TRANSC_DPLLB_SEL; | |
2906 | ||
c98e9dcf JB |
2907 | /* Be sure PCH DPLL SEL is set */ |
2908 | temp = I915_READ(PCH_DPLL_SEL); | |
d64311ab JB |
2909 | if (pipe == 0) { |
2910 | temp &= ~(TRANSA_DPLLB_SEL); | |
c98e9dcf | 2911 | temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL); |
d64311ab JB |
2912 | } else if (pipe == 1) { |
2913 | temp &= ~(TRANSB_DPLLB_SEL); | |
c98e9dcf | 2914 | temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL); |
d64311ab JB |
2915 | } else if (pipe == 2) { |
2916 | temp &= ~(TRANSC_DPLLB_SEL); | |
4b645f14 | 2917 | temp |= (TRANSC_DPLL_ENABLE | transc_sel); |
d64311ab | 2918 | } |
c98e9dcf | 2919 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 2920 | } |
5eddb70b | 2921 | |
d9b6cb56 JB |
2922 | /* set transcoder timing, panel must allow it */ |
2923 | assert_panel_unlocked(dev_priv, pipe); | |
5eddb70b CW |
2924 | I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe))); |
2925 | I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe))); | |
2926 | I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe))); | |
8db9d77b | 2927 | |
5eddb70b CW |
2928 | I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe))); |
2929 | I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe))); | |
2930 | I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe))); | |
8db9d77b | 2931 | |
5e84e1a4 ZW |
2932 | intel_fdi_normal_train(crtc); |
2933 | ||
c98e9dcf JB |
2934 | /* For PCH DP, enable TRANS_DP_CTL */ |
2935 | if (HAS_PCH_CPT(dev) && | |
2936 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { | |
9325c9f0 | 2937 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5; |
5eddb70b CW |
2938 | reg = TRANS_DP_CTL(pipe); |
2939 | temp = I915_READ(reg); | |
2940 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
2941 | TRANS_DP_SYNC_MASK | |
2942 | TRANS_DP_BPC_MASK); | |
5eddb70b CW |
2943 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
2944 | TRANS_DP_ENH_FRAMING); | |
9325c9f0 | 2945 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf JB |
2946 | |
2947 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) | |
5eddb70b | 2948 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
c98e9dcf | 2949 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 2950 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
2951 | |
2952 | switch (intel_trans_dp_port_sel(crtc)) { | |
2953 | case PCH_DP_B: | |
5eddb70b | 2954 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf JB |
2955 | break; |
2956 | case PCH_DP_C: | |
5eddb70b | 2957 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf JB |
2958 | break; |
2959 | case PCH_DP_D: | |
5eddb70b | 2960 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
2961 | break; |
2962 | default: | |
2963 | DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n"); | |
5eddb70b | 2964 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf | 2965 | break; |
32f9d658 | 2966 | } |
2c07245f | 2967 | |
5eddb70b | 2968 | I915_WRITE(reg, temp); |
6be4a607 | 2969 | } |
b52eb4dc | 2970 | |
040484af | 2971 | intel_enable_transcoder(dev_priv, pipe); |
f67a559d JB |
2972 | } |
2973 | ||
2974 | static void ironlake_crtc_enable(struct drm_crtc *crtc) | |
2975 | { | |
2976 | struct drm_device *dev = crtc->dev; | |
2977 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2978 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2979 | int pipe = intel_crtc->pipe; | |
2980 | int plane = intel_crtc->plane; | |
2981 | u32 temp; | |
2982 | bool is_pch_port; | |
2983 | ||
2984 | if (intel_crtc->active) | |
2985 | return; | |
2986 | ||
2987 | intel_crtc->active = true; | |
2988 | intel_update_watermarks(dev); | |
2989 | ||
2990 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
2991 | temp = I915_READ(PCH_LVDS); | |
2992 | if ((temp & LVDS_PORT_EN) == 0) | |
2993 | I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN); | |
2994 | } | |
2995 | ||
2996 | is_pch_port = intel_crtc_driving_pch(crtc); | |
2997 | ||
2998 | if (is_pch_port) | |
357555c0 | 2999 | ironlake_fdi_pll_enable(crtc); |
f67a559d JB |
3000 | else |
3001 | ironlake_fdi_disable(crtc); | |
3002 | ||
3003 | /* Enable panel fitting for LVDS */ | |
3004 | if (dev_priv->pch_pf_size && | |
3005 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) { | |
3006 | /* Force use of hard-coded filter coefficients | |
3007 | * as some pre-programmed values are broken, | |
3008 | * e.g. x201. | |
3009 | */ | |
9db4a9c7 JB |
3010 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); |
3011 | I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos); | |
3012 | I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size); | |
f67a559d JB |
3013 | } |
3014 | ||
9c54c0dd JB |
3015 | /* |
3016 | * On ILK+ LUT must be loaded before the pipe is running but with | |
3017 | * clocks enabled | |
3018 | */ | |
3019 | intel_crtc_load_lut(crtc); | |
3020 | ||
f67a559d JB |
3021 | intel_enable_pipe(dev_priv, pipe, is_pch_port); |
3022 | intel_enable_plane(dev_priv, plane, pipe); | |
3023 | ||
3024 | if (is_pch_port) | |
3025 | ironlake_pch_enable(crtc); | |
c98e9dcf | 3026 | |
d1ebd816 | 3027 | mutex_lock(&dev->struct_mutex); |
bed4a673 | 3028 | intel_update_fbc(dev); |
d1ebd816 BW |
3029 | mutex_unlock(&dev->struct_mutex); |
3030 | ||
6b383a7f | 3031 | intel_crtc_update_cursor(crtc, true); |
6be4a607 JB |
3032 | } |
3033 | ||
3034 | static void ironlake_crtc_disable(struct drm_crtc *crtc) | |
3035 | { | |
3036 | struct drm_device *dev = crtc->dev; | |
3037 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3038 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3039 | int pipe = intel_crtc->pipe; | |
3040 | int plane = intel_crtc->plane; | |
5eddb70b | 3041 | u32 reg, temp; |
b52eb4dc | 3042 | |
f7abfe8b CW |
3043 | if (!intel_crtc->active) |
3044 | return; | |
3045 | ||
e6c3a2a6 | 3046 | intel_crtc_wait_for_pending_flips(crtc); |
6be4a607 | 3047 | drm_vblank_off(dev, pipe); |
6b383a7f | 3048 | intel_crtc_update_cursor(crtc, false); |
5eddb70b | 3049 | |
b24e7179 | 3050 | intel_disable_plane(dev_priv, plane, pipe); |
913d8d11 | 3051 | |
973d04f9 CW |
3052 | if (dev_priv->cfb_plane == plane) |
3053 | intel_disable_fbc(dev); | |
2c07245f | 3054 | |
b24e7179 | 3055 | intel_disable_pipe(dev_priv, pipe); |
32f9d658 | 3056 | |
6be4a607 | 3057 | /* Disable PF */ |
9db4a9c7 JB |
3058 | I915_WRITE(PF_CTL(pipe), 0); |
3059 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
2c07245f | 3060 | |
0fc932b8 | 3061 | ironlake_fdi_disable(crtc); |
2c07245f | 3062 | |
47a05eca JB |
3063 | /* This is a horrible layering violation; we should be doing this in |
3064 | * the connector/encoder ->prepare instead, but we don't always have | |
3065 | * enough information there about the config to know whether it will | |
3066 | * actually be necessary or just cause undesired flicker. | |
3067 | */ | |
3068 | intel_disable_pch_ports(dev_priv, pipe); | |
249c0e64 | 3069 | |
040484af | 3070 | intel_disable_transcoder(dev_priv, pipe); |
913d8d11 | 3071 | |
6be4a607 JB |
3072 | if (HAS_PCH_CPT(dev)) { |
3073 | /* disable TRANS_DP_CTL */ | |
5eddb70b CW |
3074 | reg = TRANS_DP_CTL(pipe); |
3075 | temp = I915_READ(reg); | |
3076 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK); | |
cb3543c6 | 3077 | temp |= TRANS_DP_PORT_SEL_NONE; |
5eddb70b | 3078 | I915_WRITE(reg, temp); |
6be4a607 JB |
3079 | |
3080 | /* disable DPLL_SEL */ | |
3081 | temp = I915_READ(PCH_DPLL_SEL); | |
9db4a9c7 JB |
3082 | switch (pipe) { |
3083 | case 0: | |
d64311ab | 3084 | temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL); |
9db4a9c7 JB |
3085 | break; |
3086 | case 1: | |
6be4a607 | 3087 | temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL); |
9db4a9c7 JB |
3088 | break; |
3089 | case 2: | |
4b645f14 | 3090 | /* C shares PLL A or B */ |
d64311ab | 3091 | temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL); |
9db4a9c7 JB |
3092 | break; |
3093 | default: | |
3094 | BUG(); /* wtf */ | |
3095 | } | |
6be4a607 | 3096 | I915_WRITE(PCH_DPLL_SEL, temp); |
6be4a607 | 3097 | } |
e3421a18 | 3098 | |
6be4a607 | 3099 | /* disable PCH DPLL */ |
4b645f14 JB |
3100 | if (!intel_crtc->no_pll) |
3101 | intel_disable_pch_pll(dev_priv, pipe); | |
8db9d77b | 3102 | |
6be4a607 | 3103 | /* Switch from PCDclk to Rawclk */ |
5eddb70b CW |
3104 | reg = FDI_RX_CTL(pipe); |
3105 | temp = I915_READ(reg); | |
3106 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
8db9d77b | 3107 | |
6be4a607 | 3108 | /* Disable CPU FDI TX PLL */ |
5eddb70b CW |
3109 | reg = FDI_TX_CTL(pipe); |
3110 | temp = I915_READ(reg); | |
3111 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
3112 | ||
3113 | POSTING_READ(reg); | |
6be4a607 | 3114 | udelay(100); |
8db9d77b | 3115 | |
5eddb70b CW |
3116 | reg = FDI_RX_CTL(pipe); |
3117 | temp = I915_READ(reg); | |
3118 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
2c07245f | 3119 | |
6be4a607 | 3120 | /* Wait for the clocks to turn off. */ |
5eddb70b | 3121 | POSTING_READ(reg); |
6be4a607 | 3122 | udelay(100); |
6b383a7f | 3123 | |
f7abfe8b | 3124 | intel_crtc->active = false; |
6b383a7f | 3125 | intel_update_watermarks(dev); |
d1ebd816 BW |
3126 | |
3127 | mutex_lock(&dev->struct_mutex); | |
6b383a7f CW |
3128 | intel_update_fbc(dev); |
3129 | intel_clear_scanline_wait(dev); | |
d1ebd816 | 3130 | mutex_unlock(&dev->struct_mutex); |
6be4a607 | 3131 | } |
1b3c7a47 | 3132 | |
6be4a607 JB |
3133 | static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode) |
3134 | { | |
3135 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3136 | int pipe = intel_crtc->pipe; | |
3137 | int plane = intel_crtc->plane; | |
8db9d77b | 3138 | |
6be4a607 JB |
3139 | /* XXX: When our outputs are all unaware of DPMS modes other than off |
3140 | * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. | |
3141 | */ | |
3142 | switch (mode) { | |
3143 | case DRM_MODE_DPMS_ON: | |
3144 | case DRM_MODE_DPMS_STANDBY: | |
3145 | case DRM_MODE_DPMS_SUSPEND: | |
3146 | DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane); | |
3147 | ironlake_crtc_enable(crtc); | |
3148 | break; | |
1b3c7a47 | 3149 | |
6be4a607 JB |
3150 | case DRM_MODE_DPMS_OFF: |
3151 | DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane); | |
3152 | ironlake_crtc_disable(crtc); | |
2c07245f ZW |
3153 | break; |
3154 | } | |
3155 | } | |
3156 | ||
02e792fb DV |
3157 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
3158 | { | |
02e792fb | 3159 | if (!enable && intel_crtc->overlay) { |
23f09ce3 | 3160 | struct drm_device *dev = intel_crtc->base.dev; |
ce453d81 | 3161 | struct drm_i915_private *dev_priv = dev->dev_private; |
03f77ea5 | 3162 | |
23f09ce3 | 3163 | mutex_lock(&dev->struct_mutex); |
ce453d81 CW |
3164 | dev_priv->mm.interruptible = false; |
3165 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
3166 | dev_priv->mm.interruptible = true; | |
23f09ce3 | 3167 | mutex_unlock(&dev->struct_mutex); |
02e792fb | 3168 | } |
02e792fb | 3169 | |
5dcdbcb0 CW |
3170 | /* Let userspace switch the overlay on again. In most cases userspace |
3171 | * has to recompute where to put it anyway. | |
3172 | */ | |
02e792fb DV |
3173 | } |
3174 | ||
0b8765c6 | 3175 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
3176 | { |
3177 | struct drm_device *dev = crtc->dev; | |
79e53945 JB |
3178 | struct drm_i915_private *dev_priv = dev->dev_private; |
3179 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3180 | int pipe = intel_crtc->pipe; | |
80824003 | 3181 | int plane = intel_crtc->plane; |
79e53945 | 3182 | |
f7abfe8b CW |
3183 | if (intel_crtc->active) |
3184 | return; | |
3185 | ||
3186 | intel_crtc->active = true; | |
6b383a7f CW |
3187 | intel_update_watermarks(dev); |
3188 | ||
63d7bbe9 | 3189 | intel_enable_pll(dev_priv, pipe); |
040484af | 3190 | intel_enable_pipe(dev_priv, pipe, false); |
b24e7179 | 3191 | intel_enable_plane(dev_priv, plane, pipe); |
79e53945 | 3192 | |
0b8765c6 | 3193 | intel_crtc_load_lut(crtc); |
bed4a673 | 3194 | intel_update_fbc(dev); |
79e53945 | 3195 | |
0b8765c6 JB |
3196 | /* Give the overlay scaler a chance to enable if it's on this pipe */ |
3197 | intel_crtc_dpms_overlay(intel_crtc, true); | |
6b383a7f | 3198 | intel_crtc_update_cursor(crtc, true); |
0b8765c6 | 3199 | } |
79e53945 | 3200 | |
0b8765c6 JB |
3201 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
3202 | { | |
3203 | struct drm_device *dev = crtc->dev; | |
3204 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3205 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3206 | int pipe = intel_crtc->pipe; | |
3207 | int plane = intel_crtc->plane; | |
b690e96c | 3208 | |
f7abfe8b CW |
3209 | if (!intel_crtc->active) |
3210 | return; | |
3211 | ||
0b8765c6 | 3212 | /* Give the overlay scaler a chance to disable if it's on this pipe */ |
e6c3a2a6 CW |
3213 | intel_crtc_wait_for_pending_flips(crtc); |
3214 | drm_vblank_off(dev, pipe); | |
0b8765c6 | 3215 | intel_crtc_dpms_overlay(intel_crtc, false); |
6b383a7f | 3216 | intel_crtc_update_cursor(crtc, false); |
0b8765c6 | 3217 | |
973d04f9 CW |
3218 | if (dev_priv->cfb_plane == plane) |
3219 | intel_disable_fbc(dev); | |
79e53945 | 3220 | |
b24e7179 | 3221 | intel_disable_plane(dev_priv, plane, pipe); |
b24e7179 | 3222 | intel_disable_pipe(dev_priv, pipe); |
63d7bbe9 | 3223 | intel_disable_pll(dev_priv, pipe); |
0b8765c6 | 3224 | |
f7abfe8b | 3225 | intel_crtc->active = false; |
6b383a7f CW |
3226 | intel_update_fbc(dev); |
3227 | intel_update_watermarks(dev); | |
3228 | intel_clear_scanline_wait(dev); | |
0b8765c6 JB |
3229 | } |
3230 | ||
3231 | static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode) | |
3232 | { | |
3233 | /* XXX: When our outputs are all unaware of DPMS modes other than off | |
3234 | * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. | |
3235 | */ | |
3236 | switch (mode) { | |
3237 | case DRM_MODE_DPMS_ON: | |
3238 | case DRM_MODE_DPMS_STANDBY: | |
3239 | case DRM_MODE_DPMS_SUSPEND: | |
3240 | i9xx_crtc_enable(crtc); | |
3241 | break; | |
3242 | case DRM_MODE_DPMS_OFF: | |
3243 | i9xx_crtc_disable(crtc); | |
79e53945 JB |
3244 | break; |
3245 | } | |
2c07245f ZW |
3246 | } |
3247 | ||
3248 | /** | |
3249 | * Sets the power management mode of the pipe and plane. | |
2c07245f ZW |
3250 | */ |
3251 | static void intel_crtc_dpms(struct drm_crtc *crtc, int mode) | |
3252 | { | |
3253 | struct drm_device *dev = crtc->dev; | |
e70236a8 | 3254 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f ZW |
3255 | struct drm_i915_master_private *master_priv; |
3256 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3257 | int pipe = intel_crtc->pipe; | |
3258 | bool enabled; | |
3259 | ||
032d2a0d CW |
3260 | if (intel_crtc->dpms_mode == mode) |
3261 | return; | |
3262 | ||
65655d4a | 3263 | intel_crtc->dpms_mode = mode; |
debcaddc | 3264 | |
e70236a8 | 3265 | dev_priv->display.dpms(crtc, mode); |
79e53945 JB |
3266 | |
3267 | if (!dev->primary->master) | |
3268 | return; | |
3269 | ||
3270 | master_priv = dev->primary->master->driver_priv; | |
3271 | if (!master_priv->sarea_priv) | |
3272 | return; | |
3273 | ||
3274 | enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF; | |
3275 | ||
3276 | switch (pipe) { | |
3277 | case 0: | |
3278 | master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; | |
3279 | master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; | |
3280 | break; | |
3281 | case 1: | |
3282 | master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; | |
3283 | master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; | |
3284 | break; | |
3285 | default: | |
9db4a9c7 | 3286 | DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe)); |
79e53945 JB |
3287 | break; |
3288 | } | |
79e53945 JB |
3289 | } |
3290 | ||
cdd59983 CW |
3291 | static void intel_crtc_disable(struct drm_crtc *crtc) |
3292 | { | |
3293 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; | |
3294 | struct drm_device *dev = crtc->dev; | |
3295 | ||
3296 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF); | |
3297 | ||
3298 | if (crtc->fb) { | |
3299 | mutex_lock(&dev->struct_mutex); | |
3300 | i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj); | |
3301 | mutex_unlock(&dev->struct_mutex); | |
3302 | } | |
3303 | } | |
3304 | ||
7e7d76c3 JB |
3305 | /* Prepare for a mode set. |
3306 | * | |
3307 | * Note we could be a lot smarter here. We need to figure out which outputs | |
3308 | * will be enabled, which disabled (in short, how the config will changes) | |
3309 | * and perform the minimum necessary steps to accomplish that, e.g. updating | |
3310 | * watermarks, FBC configuration, making sure PLLs are programmed correctly, | |
3311 | * panel fitting is in the proper state, etc. | |
3312 | */ | |
3313 | static void i9xx_crtc_prepare(struct drm_crtc *crtc) | |
79e53945 | 3314 | { |
7e7d76c3 | 3315 | i9xx_crtc_disable(crtc); |
79e53945 JB |
3316 | } |
3317 | ||
7e7d76c3 | 3318 | static void i9xx_crtc_commit(struct drm_crtc *crtc) |
79e53945 | 3319 | { |
7e7d76c3 | 3320 | i9xx_crtc_enable(crtc); |
7e7d76c3 JB |
3321 | } |
3322 | ||
3323 | static void ironlake_crtc_prepare(struct drm_crtc *crtc) | |
3324 | { | |
7e7d76c3 | 3325 | ironlake_crtc_disable(crtc); |
7e7d76c3 JB |
3326 | } |
3327 | ||
3328 | static void ironlake_crtc_commit(struct drm_crtc *crtc) | |
3329 | { | |
7e7d76c3 | 3330 | ironlake_crtc_enable(crtc); |
79e53945 JB |
3331 | } |
3332 | ||
0206e353 | 3333 | void intel_encoder_prepare(struct drm_encoder *encoder) |
79e53945 JB |
3334 | { |
3335 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
3336 | /* lvds has its own version of prepare see intel_lvds_prepare */ | |
3337 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF); | |
3338 | } | |
3339 | ||
0206e353 | 3340 | void intel_encoder_commit(struct drm_encoder *encoder) |
79e53945 JB |
3341 | { |
3342 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
3343 | /* lvds has its own version of commit see intel_lvds_commit */ | |
3344 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); | |
3345 | } | |
3346 | ||
ea5b213a CW |
3347 | void intel_encoder_destroy(struct drm_encoder *encoder) |
3348 | { | |
4ef69c7a | 3349 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 3350 | |
ea5b213a CW |
3351 | drm_encoder_cleanup(encoder); |
3352 | kfree(intel_encoder); | |
3353 | } | |
3354 | ||
79e53945 JB |
3355 | static bool intel_crtc_mode_fixup(struct drm_crtc *crtc, |
3356 | struct drm_display_mode *mode, | |
3357 | struct drm_display_mode *adjusted_mode) | |
3358 | { | |
2c07245f | 3359 | struct drm_device *dev = crtc->dev; |
89749350 | 3360 | |
bad720ff | 3361 | if (HAS_PCH_SPLIT(dev)) { |
2c07245f | 3362 | /* FDI link clock is fixed at 2.7G */ |
2377b741 JB |
3363 | if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4) |
3364 | return false; | |
2c07245f | 3365 | } |
89749350 CW |
3366 | |
3367 | /* XXX some encoders set the crtcinfo, others don't. | |
3368 | * Obviously we need some form of conflict resolution here... | |
3369 | */ | |
3370 | if (adjusted_mode->crtc_htotal == 0) | |
3371 | drm_mode_set_crtcinfo(adjusted_mode, 0); | |
3372 | ||
79e53945 JB |
3373 | return true; |
3374 | } | |
3375 | ||
e70236a8 JB |
3376 | static int i945_get_display_clock_speed(struct drm_device *dev) |
3377 | { | |
3378 | return 400000; | |
3379 | } | |
79e53945 | 3380 | |
e70236a8 | 3381 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 3382 | { |
e70236a8 JB |
3383 | return 333000; |
3384 | } | |
79e53945 | 3385 | |
e70236a8 JB |
3386 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
3387 | { | |
3388 | return 200000; | |
3389 | } | |
79e53945 | 3390 | |
e70236a8 JB |
3391 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
3392 | { | |
3393 | u16 gcfgc = 0; | |
79e53945 | 3394 | |
e70236a8 JB |
3395 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
3396 | ||
3397 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
3398 | return 133000; | |
3399 | else { | |
3400 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
3401 | case GC_DISPLAY_CLOCK_333_MHZ: | |
3402 | return 333000; | |
3403 | default: | |
3404 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
3405 | return 190000; | |
79e53945 | 3406 | } |
e70236a8 JB |
3407 | } |
3408 | } | |
3409 | ||
3410 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
3411 | { | |
3412 | return 266000; | |
3413 | } | |
3414 | ||
3415 | static int i855_get_display_clock_speed(struct drm_device *dev) | |
3416 | { | |
3417 | u16 hpllcc = 0; | |
3418 | /* Assume that the hardware is in the high speed state. This | |
3419 | * should be the default. | |
3420 | */ | |
3421 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
3422 | case GC_CLOCK_133_200: | |
3423 | case GC_CLOCK_100_200: | |
3424 | return 200000; | |
3425 | case GC_CLOCK_166_250: | |
3426 | return 250000; | |
3427 | case GC_CLOCK_100_133: | |
79e53945 | 3428 | return 133000; |
e70236a8 | 3429 | } |
79e53945 | 3430 | |
e70236a8 JB |
3431 | /* Shouldn't happen */ |
3432 | return 0; | |
3433 | } | |
79e53945 | 3434 | |
e70236a8 JB |
3435 | static int i830_get_display_clock_speed(struct drm_device *dev) |
3436 | { | |
3437 | return 133000; | |
79e53945 JB |
3438 | } |
3439 | ||
2c07245f ZW |
3440 | struct fdi_m_n { |
3441 | u32 tu; | |
3442 | u32 gmch_m; | |
3443 | u32 gmch_n; | |
3444 | u32 link_m; | |
3445 | u32 link_n; | |
3446 | }; | |
3447 | ||
3448 | static void | |
3449 | fdi_reduce_ratio(u32 *num, u32 *den) | |
3450 | { | |
3451 | while (*num > 0xffffff || *den > 0xffffff) { | |
3452 | *num >>= 1; | |
3453 | *den >>= 1; | |
3454 | } | |
3455 | } | |
3456 | ||
2c07245f | 3457 | static void |
f2b115e6 AJ |
3458 | ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock, |
3459 | int link_clock, struct fdi_m_n *m_n) | |
2c07245f | 3460 | { |
2c07245f ZW |
3461 | m_n->tu = 64; /* default size */ |
3462 | ||
22ed1113 CW |
3463 | /* BUG_ON(pixel_clock > INT_MAX / 36); */ |
3464 | m_n->gmch_m = bits_per_pixel * pixel_clock; | |
3465 | m_n->gmch_n = link_clock * nlanes * 8; | |
2c07245f ZW |
3466 | fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); |
3467 | ||
22ed1113 CW |
3468 | m_n->link_m = pixel_clock; |
3469 | m_n->link_n = link_clock; | |
2c07245f ZW |
3470 | fdi_reduce_ratio(&m_n->link_m, &m_n->link_n); |
3471 | } | |
3472 | ||
3473 | ||
7662c8bd SL |
3474 | struct intel_watermark_params { |
3475 | unsigned long fifo_size; | |
3476 | unsigned long max_wm; | |
3477 | unsigned long default_wm; | |
3478 | unsigned long guard_size; | |
3479 | unsigned long cacheline_size; | |
3480 | }; | |
3481 | ||
f2b115e6 | 3482 | /* Pineview has different values for various configs */ |
d210246a | 3483 | static const struct intel_watermark_params pineview_display_wm = { |
f2b115e6 AJ |
3484 | PINEVIEW_DISPLAY_FIFO, |
3485 | PINEVIEW_MAX_WM, | |
3486 | PINEVIEW_DFT_WM, | |
3487 | PINEVIEW_GUARD_WM, | |
3488 | PINEVIEW_FIFO_LINE_SIZE | |
7662c8bd | 3489 | }; |
d210246a | 3490 | static const struct intel_watermark_params pineview_display_hplloff_wm = { |
f2b115e6 AJ |
3491 | PINEVIEW_DISPLAY_FIFO, |
3492 | PINEVIEW_MAX_WM, | |
3493 | PINEVIEW_DFT_HPLLOFF_WM, | |
3494 | PINEVIEW_GUARD_WM, | |
3495 | PINEVIEW_FIFO_LINE_SIZE | |
7662c8bd | 3496 | }; |
d210246a | 3497 | static const struct intel_watermark_params pineview_cursor_wm = { |
f2b115e6 AJ |
3498 | PINEVIEW_CURSOR_FIFO, |
3499 | PINEVIEW_CURSOR_MAX_WM, | |
3500 | PINEVIEW_CURSOR_DFT_WM, | |
3501 | PINEVIEW_CURSOR_GUARD_WM, | |
3502 | PINEVIEW_FIFO_LINE_SIZE, | |
7662c8bd | 3503 | }; |
d210246a | 3504 | static const struct intel_watermark_params pineview_cursor_hplloff_wm = { |
f2b115e6 AJ |
3505 | PINEVIEW_CURSOR_FIFO, |
3506 | PINEVIEW_CURSOR_MAX_WM, | |
3507 | PINEVIEW_CURSOR_DFT_WM, | |
3508 | PINEVIEW_CURSOR_GUARD_WM, | |
3509 | PINEVIEW_FIFO_LINE_SIZE | |
7662c8bd | 3510 | }; |
d210246a | 3511 | static const struct intel_watermark_params g4x_wm_info = { |
0e442c60 JB |
3512 | G4X_FIFO_SIZE, |
3513 | G4X_MAX_WM, | |
3514 | G4X_MAX_WM, | |
3515 | 2, | |
3516 | G4X_FIFO_LINE_SIZE, | |
3517 | }; | |
d210246a | 3518 | static const struct intel_watermark_params g4x_cursor_wm_info = { |
4fe5e611 ZY |
3519 | I965_CURSOR_FIFO, |
3520 | I965_CURSOR_MAX_WM, | |
3521 | I965_CURSOR_DFT_WM, | |
3522 | 2, | |
3523 | G4X_FIFO_LINE_SIZE, | |
3524 | }; | |
d210246a | 3525 | static const struct intel_watermark_params i965_cursor_wm_info = { |
4fe5e611 ZY |
3526 | I965_CURSOR_FIFO, |
3527 | I965_CURSOR_MAX_WM, | |
3528 | I965_CURSOR_DFT_WM, | |
3529 | 2, | |
3530 | I915_FIFO_LINE_SIZE, | |
3531 | }; | |
d210246a | 3532 | static const struct intel_watermark_params i945_wm_info = { |
dff33cfc | 3533 | I945_FIFO_SIZE, |
7662c8bd SL |
3534 | I915_MAX_WM, |
3535 | 1, | |
dff33cfc JB |
3536 | 2, |
3537 | I915_FIFO_LINE_SIZE | |
7662c8bd | 3538 | }; |
d210246a | 3539 | static const struct intel_watermark_params i915_wm_info = { |
dff33cfc | 3540 | I915_FIFO_SIZE, |
7662c8bd SL |
3541 | I915_MAX_WM, |
3542 | 1, | |
dff33cfc | 3543 | 2, |
7662c8bd SL |
3544 | I915_FIFO_LINE_SIZE |
3545 | }; | |
d210246a | 3546 | static const struct intel_watermark_params i855_wm_info = { |
7662c8bd SL |
3547 | I855GM_FIFO_SIZE, |
3548 | I915_MAX_WM, | |
3549 | 1, | |
dff33cfc | 3550 | 2, |
7662c8bd SL |
3551 | I830_FIFO_LINE_SIZE |
3552 | }; | |
d210246a | 3553 | static const struct intel_watermark_params i830_wm_info = { |
7662c8bd SL |
3554 | I830_FIFO_SIZE, |
3555 | I915_MAX_WM, | |
3556 | 1, | |
dff33cfc | 3557 | 2, |
7662c8bd SL |
3558 | I830_FIFO_LINE_SIZE |
3559 | }; | |
3560 | ||
d210246a | 3561 | static const struct intel_watermark_params ironlake_display_wm_info = { |
7f8a8569 ZW |
3562 | ILK_DISPLAY_FIFO, |
3563 | ILK_DISPLAY_MAXWM, | |
3564 | ILK_DISPLAY_DFTWM, | |
3565 | 2, | |
3566 | ILK_FIFO_LINE_SIZE | |
3567 | }; | |
d210246a | 3568 | static const struct intel_watermark_params ironlake_cursor_wm_info = { |
c936f44d ZY |
3569 | ILK_CURSOR_FIFO, |
3570 | ILK_CURSOR_MAXWM, | |
3571 | ILK_CURSOR_DFTWM, | |
3572 | 2, | |
3573 | ILK_FIFO_LINE_SIZE | |
3574 | }; | |
d210246a | 3575 | static const struct intel_watermark_params ironlake_display_srwm_info = { |
7f8a8569 ZW |
3576 | ILK_DISPLAY_SR_FIFO, |
3577 | ILK_DISPLAY_MAX_SRWM, | |
3578 | ILK_DISPLAY_DFT_SRWM, | |
3579 | 2, | |
3580 | ILK_FIFO_LINE_SIZE | |
3581 | }; | |
d210246a | 3582 | static const struct intel_watermark_params ironlake_cursor_srwm_info = { |
7f8a8569 ZW |
3583 | ILK_CURSOR_SR_FIFO, |
3584 | ILK_CURSOR_MAX_SRWM, | |
3585 | ILK_CURSOR_DFT_SRWM, | |
3586 | 2, | |
3587 | ILK_FIFO_LINE_SIZE | |
3588 | }; | |
3589 | ||
d210246a | 3590 | static const struct intel_watermark_params sandybridge_display_wm_info = { |
1398261a YL |
3591 | SNB_DISPLAY_FIFO, |
3592 | SNB_DISPLAY_MAXWM, | |
3593 | SNB_DISPLAY_DFTWM, | |
3594 | 2, | |
3595 | SNB_FIFO_LINE_SIZE | |
3596 | }; | |
d210246a | 3597 | static const struct intel_watermark_params sandybridge_cursor_wm_info = { |
1398261a YL |
3598 | SNB_CURSOR_FIFO, |
3599 | SNB_CURSOR_MAXWM, | |
3600 | SNB_CURSOR_DFTWM, | |
3601 | 2, | |
3602 | SNB_FIFO_LINE_SIZE | |
3603 | }; | |
d210246a | 3604 | static const struct intel_watermark_params sandybridge_display_srwm_info = { |
1398261a YL |
3605 | SNB_DISPLAY_SR_FIFO, |
3606 | SNB_DISPLAY_MAX_SRWM, | |
3607 | SNB_DISPLAY_DFT_SRWM, | |
3608 | 2, | |
3609 | SNB_FIFO_LINE_SIZE | |
3610 | }; | |
d210246a | 3611 | static const struct intel_watermark_params sandybridge_cursor_srwm_info = { |
1398261a YL |
3612 | SNB_CURSOR_SR_FIFO, |
3613 | SNB_CURSOR_MAX_SRWM, | |
3614 | SNB_CURSOR_DFT_SRWM, | |
3615 | 2, | |
3616 | SNB_FIFO_LINE_SIZE | |
3617 | }; | |
3618 | ||
3619 | ||
dff33cfc JB |
3620 | /** |
3621 | * intel_calculate_wm - calculate watermark level | |
3622 | * @clock_in_khz: pixel clock | |
3623 | * @wm: chip FIFO params | |
3624 | * @pixel_size: display pixel size | |
3625 | * @latency_ns: memory latency for the platform | |
3626 | * | |
3627 | * Calculate the watermark level (the level at which the display plane will | |
3628 | * start fetching from memory again). Each chip has a different display | |
3629 | * FIFO size and allocation, so the caller needs to figure that out and pass | |
3630 | * in the correct intel_watermark_params structure. | |
3631 | * | |
3632 | * As the pixel clock runs, the FIFO will be drained at a rate that depends | |
3633 | * on the pixel size. When it reaches the watermark level, it'll start | |
3634 | * fetching FIFO line sized based chunks from memory until the FIFO fills | |
3635 | * past the watermark point. If the FIFO drains completely, a FIFO underrun | |
3636 | * will occur, and a display engine hang could result. | |
3637 | */ | |
7662c8bd | 3638 | static unsigned long intel_calculate_wm(unsigned long clock_in_khz, |
d210246a CW |
3639 | const struct intel_watermark_params *wm, |
3640 | int fifo_size, | |
7662c8bd SL |
3641 | int pixel_size, |
3642 | unsigned long latency_ns) | |
3643 | { | |
390c4dd4 | 3644 | long entries_required, wm_size; |
dff33cfc | 3645 | |
d660467c JB |
3646 | /* |
3647 | * Note: we need to make sure we don't overflow for various clock & | |
3648 | * latency values. | |
3649 | * clocks go from a few thousand to several hundred thousand. | |
3650 | * latency is usually a few thousand | |
3651 | */ | |
3652 | entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) / | |
3653 | 1000; | |
8de9b311 | 3654 | entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size); |
7662c8bd | 3655 | |
bbb0aef5 | 3656 | DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required); |
dff33cfc | 3657 | |
d210246a | 3658 | wm_size = fifo_size - (entries_required + wm->guard_size); |
dff33cfc | 3659 | |
bbb0aef5 | 3660 | DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size); |
7662c8bd | 3661 | |
390c4dd4 JB |
3662 | /* Don't promote wm_size to unsigned... */ |
3663 | if (wm_size > (long)wm->max_wm) | |
7662c8bd | 3664 | wm_size = wm->max_wm; |
c3add4b6 | 3665 | if (wm_size <= 0) |
7662c8bd SL |
3666 | wm_size = wm->default_wm; |
3667 | return wm_size; | |
3668 | } | |
3669 | ||
3670 | struct cxsr_latency { | |
3671 | int is_desktop; | |
95534263 | 3672 | int is_ddr3; |
7662c8bd SL |
3673 | unsigned long fsb_freq; |
3674 | unsigned long mem_freq; | |
3675 | unsigned long display_sr; | |
3676 | unsigned long display_hpll_disable; | |
3677 | unsigned long cursor_sr; | |
3678 | unsigned long cursor_hpll_disable; | |
3679 | }; | |
3680 | ||
403c89ff | 3681 | static const struct cxsr_latency cxsr_latency_table[] = { |
95534263 LP |
3682 | {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */ |
3683 | {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */ | |
3684 | {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */ | |
3685 | {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */ | |
3686 | {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */ | |
3687 | ||
3688 | {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */ | |
3689 | {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */ | |
3690 | {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */ | |
3691 | {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */ | |
3692 | {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */ | |
3693 | ||
3694 | {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */ | |
3695 | {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */ | |
3696 | {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */ | |
3697 | {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */ | |
3698 | {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */ | |
3699 | ||
3700 | {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */ | |
3701 | {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */ | |
3702 | {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */ | |
3703 | {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */ | |
3704 | {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */ | |
3705 | ||
3706 | {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */ | |
3707 | {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */ | |
3708 | {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */ | |
3709 | {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */ | |
3710 | {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */ | |
3711 | ||
3712 | {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */ | |
3713 | {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */ | |
3714 | {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */ | |
3715 | {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */ | |
3716 | {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */ | |
7662c8bd SL |
3717 | }; |
3718 | ||
403c89ff CW |
3719 | static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, |
3720 | int is_ddr3, | |
3721 | int fsb, | |
3722 | int mem) | |
7662c8bd | 3723 | { |
403c89ff | 3724 | const struct cxsr_latency *latency; |
7662c8bd | 3725 | int i; |
7662c8bd SL |
3726 | |
3727 | if (fsb == 0 || mem == 0) | |
3728 | return NULL; | |
3729 | ||
3730 | for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) { | |
3731 | latency = &cxsr_latency_table[i]; | |
3732 | if (is_desktop == latency->is_desktop && | |
95534263 | 3733 | is_ddr3 == latency->is_ddr3 && |
decbbcda JSR |
3734 | fsb == latency->fsb_freq && mem == latency->mem_freq) |
3735 | return latency; | |
7662c8bd | 3736 | } |
decbbcda | 3737 | |
28c97730 | 3738 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); |
decbbcda JSR |
3739 | |
3740 | return NULL; | |
7662c8bd SL |
3741 | } |
3742 | ||
f2b115e6 | 3743 | static void pineview_disable_cxsr(struct drm_device *dev) |
7662c8bd SL |
3744 | { |
3745 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7662c8bd SL |
3746 | |
3747 | /* deactivate cxsr */ | |
3e33d94d | 3748 | I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN); |
7662c8bd SL |
3749 | } |
3750 | ||
bcc24fb4 JB |
3751 | /* |
3752 | * Latency for FIFO fetches is dependent on several factors: | |
3753 | * - memory configuration (speed, channels) | |
3754 | * - chipset | |
3755 | * - current MCH state | |
3756 | * It can be fairly high in some situations, so here we assume a fairly | |
3757 | * pessimal value. It's a tradeoff between extra memory fetches (if we | |
3758 | * set this value too high, the FIFO will fetch frequently to stay full) | |
3759 | * and power consumption (set it too low to save power and we might see | |
3760 | * FIFO underruns and display "flicker"). | |
3761 | * | |
3762 | * A value of 5us seems to be a good balance; safe for very low end | |
3763 | * platforms but not overly aggressive on lower latency configs. | |
3764 | */ | |
69e302a9 | 3765 | static const int latency_ns = 5000; |
7662c8bd | 3766 | |
e70236a8 | 3767 | static int i9xx_get_fifo_size(struct drm_device *dev, int plane) |
dff33cfc JB |
3768 | { |
3769 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3770 | uint32_t dsparb = I915_READ(DSPARB); | |
3771 | int size; | |
3772 | ||
8de9b311 CW |
3773 | size = dsparb & 0x7f; |
3774 | if (plane) | |
3775 | size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size; | |
dff33cfc | 3776 | |
28c97730 | 3777 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
5eddb70b | 3778 | plane ? "B" : "A", size); |
dff33cfc JB |
3779 | |
3780 | return size; | |
3781 | } | |
7662c8bd | 3782 | |
e70236a8 JB |
3783 | static int i85x_get_fifo_size(struct drm_device *dev, int plane) |
3784 | { | |
3785 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3786 | uint32_t dsparb = I915_READ(DSPARB); | |
3787 | int size; | |
3788 | ||
8de9b311 CW |
3789 | size = dsparb & 0x1ff; |
3790 | if (plane) | |
3791 | size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size; | |
e70236a8 | 3792 | size >>= 1; /* Convert to cachelines */ |
dff33cfc | 3793 | |
28c97730 | 3794 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
5eddb70b | 3795 | plane ? "B" : "A", size); |
dff33cfc JB |
3796 | |
3797 | return size; | |
3798 | } | |
7662c8bd | 3799 | |
e70236a8 JB |
3800 | static int i845_get_fifo_size(struct drm_device *dev, int plane) |
3801 | { | |
3802 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3803 | uint32_t dsparb = I915_READ(DSPARB); | |
3804 | int size; | |
3805 | ||
3806 | size = dsparb & 0x7f; | |
3807 | size >>= 2; /* Convert to cachelines */ | |
3808 | ||
28c97730 | 3809 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
5eddb70b CW |
3810 | plane ? "B" : "A", |
3811 | size); | |
e70236a8 JB |
3812 | |
3813 | return size; | |
3814 | } | |
3815 | ||
3816 | static int i830_get_fifo_size(struct drm_device *dev, int plane) | |
3817 | { | |
3818 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3819 | uint32_t dsparb = I915_READ(DSPARB); | |
3820 | int size; | |
3821 | ||
3822 | size = dsparb & 0x7f; | |
3823 | size >>= 1; /* Convert to cachelines */ | |
3824 | ||
28c97730 | 3825 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
5eddb70b | 3826 | plane ? "B" : "A", size); |
e70236a8 JB |
3827 | |
3828 | return size; | |
3829 | } | |
3830 | ||
d210246a CW |
3831 | static struct drm_crtc *single_enabled_crtc(struct drm_device *dev) |
3832 | { | |
3833 | struct drm_crtc *crtc, *enabled = NULL; | |
3834 | ||
3835 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
3836 | if (crtc->enabled && crtc->fb) { | |
3837 | if (enabled) | |
3838 | return NULL; | |
3839 | enabled = crtc; | |
3840 | } | |
3841 | } | |
3842 | ||
3843 | return enabled; | |
3844 | } | |
3845 | ||
3846 | static void pineview_update_wm(struct drm_device *dev) | |
d4294342 ZY |
3847 | { |
3848 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d210246a | 3849 | struct drm_crtc *crtc; |
403c89ff | 3850 | const struct cxsr_latency *latency; |
d4294342 ZY |
3851 | u32 reg; |
3852 | unsigned long wm; | |
d4294342 | 3853 | |
403c89ff | 3854 | latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3, |
95534263 | 3855 | dev_priv->fsb_freq, dev_priv->mem_freq); |
d4294342 ZY |
3856 | if (!latency) { |
3857 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); | |
3858 | pineview_disable_cxsr(dev); | |
3859 | return; | |
3860 | } | |
3861 | ||
d210246a CW |
3862 | crtc = single_enabled_crtc(dev); |
3863 | if (crtc) { | |
3864 | int clock = crtc->mode.clock; | |
3865 | int pixel_size = crtc->fb->bits_per_pixel / 8; | |
d4294342 ZY |
3866 | |
3867 | /* Display SR */ | |
d210246a CW |
3868 | wm = intel_calculate_wm(clock, &pineview_display_wm, |
3869 | pineview_display_wm.fifo_size, | |
d4294342 ZY |
3870 | pixel_size, latency->display_sr); |
3871 | reg = I915_READ(DSPFW1); | |
3872 | reg &= ~DSPFW_SR_MASK; | |
3873 | reg |= wm << DSPFW_SR_SHIFT; | |
3874 | I915_WRITE(DSPFW1, reg); | |
3875 | DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg); | |
3876 | ||
3877 | /* cursor SR */ | |
d210246a CW |
3878 | wm = intel_calculate_wm(clock, &pineview_cursor_wm, |
3879 | pineview_display_wm.fifo_size, | |
d4294342 ZY |
3880 | pixel_size, latency->cursor_sr); |
3881 | reg = I915_READ(DSPFW3); | |
3882 | reg &= ~DSPFW_CURSOR_SR_MASK; | |
3883 | reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT; | |
3884 | I915_WRITE(DSPFW3, reg); | |
3885 | ||
3886 | /* Display HPLL off SR */ | |
d210246a CW |
3887 | wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm, |
3888 | pineview_display_hplloff_wm.fifo_size, | |
d4294342 ZY |
3889 | pixel_size, latency->display_hpll_disable); |
3890 | reg = I915_READ(DSPFW3); | |
3891 | reg &= ~DSPFW_HPLL_SR_MASK; | |
3892 | reg |= wm & DSPFW_HPLL_SR_MASK; | |
3893 | I915_WRITE(DSPFW3, reg); | |
3894 | ||
3895 | /* cursor HPLL off SR */ | |
d210246a CW |
3896 | wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, |
3897 | pineview_display_hplloff_wm.fifo_size, | |
d4294342 ZY |
3898 | pixel_size, latency->cursor_hpll_disable); |
3899 | reg = I915_READ(DSPFW3); | |
3900 | reg &= ~DSPFW_HPLL_CURSOR_MASK; | |
3901 | reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT; | |
3902 | I915_WRITE(DSPFW3, reg); | |
3903 | DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg); | |
3904 | ||
3905 | /* activate cxsr */ | |
3e33d94d CW |
3906 | I915_WRITE(DSPFW3, |
3907 | I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN); | |
d4294342 ZY |
3908 | DRM_DEBUG_KMS("Self-refresh is enabled\n"); |
3909 | } else { | |
3910 | pineview_disable_cxsr(dev); | |
3911 | DRM_DEBUG_KMS("Self-refresh is disabled\n"); | |
3912 | } | |
3913 | } | |
3914 | ||
417ae147 CW |
3915 | static bool g4x_compute_wm0(struct drm_device *dev, |
3916 | int plane, | |
3917 | const struct intel_watermark_params *display, | |
3918 | int display_latency_ns, | |
3919 | const struct intel_watermark_params *cursor, | |
3920 | int cursor_latency_ns, | |
3921 | int *plane_wm, | |
3922 | int *cursor_wm) | |
3923 | { | |
3924 | struct drm_crtc *crtc; | |
3925 | int htotal, hdisplay, clock, pixel_size; | |
3926 | int line_time_us, line_count; | |
3927 | int entries, tlb_miss; | |
3928 | ||
3929 | crtc = intel_get_crtc_for_plane(dev, plane); | |
5c72d064 CW |
3930 | if (crtc->fb == NULL || !crtc->enabled) { |
3931 | *cursor_wm = cursor->guard_size; | |
3932 | *plane_wm = display->guard_size; | |
417ae147 | 3933 | return false; |
5c72d064 | 3934 | } |
417ae147 CW |
3935 | |
3936 | htotal = crtc->mode.htotal; | |
3937 | hdisplay = crtc->mode.hdisplay; | |
3938 | clock = crtc->mode.clock; | |
3939 | pixel_size = crtc->fb->bits_per_pixel / 8; | |
3940 | ||
3941 | /* Use the small buffer method to calculate plane watermark */ | |
3942 | entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000; | |
3943 | tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8; | |
3944 | if (tlb_miss > 0) | |
3945 | entries += tlb_miss; | |
3946 | entries = DIV_ROUND_UP(entries, display->cacheline_size); | |
3947 | *plane_wm = entries + display->guard_size; | |
3948 | if (*plane_wm > (int)display->max_wm) | |
3949 | *plane_wm = display->max_wm; | |
3950 | ||
3951 | /* Use the large buffer method to calculate cursor watermark */ | |
3952 | line_time_us = ((htotal * 1000) / clock); | |
3953 | line_count = (cursor_latency_ns / line_time_us + 1000) / 1000; | |
3954 | entries = line_count * 64 * pixel_size; | |
3955 | tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8; | |
3956 | if (tlb_miss > 0) | |
3957 | entries += tlb_miss; | |
3958 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); | |
3959 | *cursor_wm = entries + cursor->guard_size; | |
3960 | if (*cursor_wm > (int)cursor->max_wm) | |
3961 | *cursor_wm = (int)cursor->max_wm; | |
3962 | ||
3963 | return true; | |
3964 | } | |
3965 | ||
3966 | /* | |
3967 | * Check the wm result. | |
3968 | * | |
3969 | * If any calculated watermark values is larger than the maximum value that | |
3970 | * can be programmed into the associated watermark register, that watermark | |
3971 | * must be disabled. | |
3972 | */ | |
3973 | static bool g4x_check_srwm(struct drm_device *dev, | |
3974 | int display_wm, int cursor_wm, | |
3975 | const struct intel_watermark_params *display, | |
3976 | const struct intel_watermark_params *cursor) | |
652c393a | 3977 | { |
417ae147 CW |
3978 | DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n", |
3979 | display_wm, cursor_wm); | |
652c393a | 3980 | |
417ae147 | 3981 | if (display_wm > display->max_wm) { |
bbb0aef5 | 3982 | DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n", |
417ae147 CW |
3983 | display_wm, display->max_wm); |
3984 | return false; | |
3985 | } | |
0e442c60 | 3986 | |
417ae147 | 3987 | if (cursor_wm > cursor->max_wm) { |
bbb0aef5 | 3988 | DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n", |
417ae147 CW |
3989 | cursor_wm, cursor->max_wm); |
3990 | return false; | |
3991 | } | |
0e442c60 | 3992 | |
417ae147 CW |
3993 | if (!(display_wm || cursor_wm)) { |
3994 | DRM_DEBUG_KMS("SR latency is 0, disabling\n"); | |
3995 | return false; | |
3996 | } | |
0e442c60 | 3997 | |
417ae147 CW |
3998 | return true; |
3999 | } | |
0e442c60 | 4000 | |
417ae147 | 4001 | static bool g4x_compute_srwm(struct drm_device *dev, |
d210246a CW |
4002 | int plane, |
4003 | int latency_ns, | |
417ae147 CW |
4004 | const struct intel_watermark_params *display, |
4005 | const struct intel_watermark_params *cursor, | |
4006 | int *display_wm, int *cursor_wm) | |
4007 | { | |
d210246a CW |
4008 | struct drm_crtc *crtc; |
4009 | int hdisplay, htotal, pixel_size, clock; | |
417ae147 CW |
4010 | unsigned long line_time_us; |
4011 | int line_count, line_size; | |
4012 | int small, large; | |
4013 | int entries; | |
0e442c60 | 4014 | |
417ae147 CW |
4015 | if (!latency_ns) { |
4016 | *display_wm = *cursor_wm = 0; | |
4017 | return false; | |
4018 | } | |
0e442c60 | 4019 | |
d210246a CW |
4020 | crtc = intel_get_crtc_for_plane(dev, plane); |
4021 | hdisplay = crtc->mode.hdisplay; | |
4022 | htotal = crtc->mode.htotal; | |
4023 | clock = crtc->mode.clock; | |
4024 | pixel_size = crtc->fb->bits_per_pixel / 8; | |
4025 | ||
417ae147 CW |
4026 | line_time_us = (htotal * 1000) / clock; |
4027 | line_count = (latency_ns / line_time_us + 1000) / 1000; | |
4028 | line_size = hdisplay * pixel_size; | |
0e442c60 | 4029 | |
417ae147 CW |
4030 | /* Use the minimum of the small and large buffer method for primary */ |
4031 | small = ((clock * pixel_size / 1000) * latency_ns) / 1000; | |
4032 | large = line_count * line_size; | |
0e442c60 | 4033 | |
417ae147 CW |
4034 | entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); |
4035 | *display_wm = entries + display->guard_size; | |
4fe5e611 | 4036 | |
417ae147 CW |
4037 | /* calculate the self-refresh watermark for display cursor */ |
4038 | entries = line_count * pixel_size * 64; | |
4039 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); | |
4040 | *cursor_wm = entries + cursor->guard_size; | |
4fe5e611 | 4041 | |
417ae147 CW |
4042 | return g4x_check_srwm(dev, |
4043 | *display_wm, *cursor_wm, | |
4044 | display, cursor); | |
4045 | } | |
4fe5e611 | 4046 | |
7ccb4a53 | 4047 | #define single_plane_enabled(mask) is_power_of_2(mask) |
d210246a CW |
4048 | |
4049 | static void g4x_update_wm(struct drm_device *dev) | |
417ae147 CW |
4050 | { |
4051 | static const int sr_latency_ns = 12000; | |
4052 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4053 | int planea_wm, planeb_wm, cursora_wm, cursorb_wm; | |
d210246a CW |
4054 | int plane_sr, cursor_sr; |
4055 | unsigned int enabled = 0; | |
417ae147 CW |
4056 | |
4057 | if (g4x_compute_wm0(dev, 0, | |
4058 | &g4x_wm_info, latency_ns, | |
4059 | &g4x_cursor_wm_info, latency_ns, | |
4060 | &planea_wm, &cursora_wm)) | |
d210246a | 4061 | enabled |= 1; |
417ae147 CW |
4062 | |
4063 | if (g4x_compute_wm0(dev, 1, | |
4064 | &g4x_wm_info, latency_ns, | |
4065 | &g4x_cursor_wm_info, latency_ns, | |
4066 | &planeb_wm, &cursorb_wm)) | |
d210246a | 4067 | enabled |= 2; |
417ae147 CW |
4068 | |
4069 | plane_sr = cursor_sr = 0; | |
d210246a CW |
4070 | if (single_plane_enabled(enabled) && |
4071 | g4x_compute_srwm(dev, ffs(enabled) - 1, | |
4072 | sr_latency_ns, | |
417ae147 CW |
4073 | &g4x_wm_info, |
4074 | &g4x_cursor_wm_info, | |
4075 | &plane_sr, &cursor_sr)) | |
0e442c60 | 4076 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); |
417ae147 CW |
4077 | else |
4078 | I915_WRITE(FW_BLC_SELF, | |
4079 | I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN); | |
0e442c60 | 4080 | |
308977ac CW |
4081 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", |
4082 | planea_wm, cursora_wm, | |
4083 | planeb_wm, cursorb_wm, | |
4084 | plane_sr, cursor_sr); | |
0e442c60 | 4085 | |
417ae147 CW |
4086 | I915_WRITE(DSPFW1, |
4087 | (plane_sr << DSPFW_SR_SHIFT) | | |
0e442c60 | 4088 | (cursorb_wm << DSPFW_CURSORB_SHIFT) | |
417ae147 CW |
4089 | (planeb_wm << DSPFW_PLANEB_SHIFT) | |
4090 | planea_wm); | |
4091 | I915_WRITE(DSPFW2, | |
4092 | (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) | | |
0e442c60 JB |
4093 | (cursora_wm << DSPFW_CURSORA_SHIFT)); |
4094 | /* HPLL off in SR has some issues on G4x... disable it */ | |
417ae147 CW |
4095 | I915_WRITE(DSPFW3, |
4096 | (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) | | |
0e442c60 | 4097 | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); |
652c393a JB |
4098 | } |
4099 | ||
d210246a | 4100 | static void i965_update_wm(struct drm_device *dev) |
7662c8bd SL |
4101 | { |
4102 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d210246a CW |
4103 | struct drm_crtc *crtc; |
4104 | int srwm = 1; | |
4fe5e611 | 4105 | int cursor_sr = 16; |
1dc7546d JB |
4106 | |
4107 | /* Calc sr entries for one plane configs */ | |
d210246a CW |
4108 | crtc = single_enabled_crtc(dev); |
4109 | if (crtc) { | |
1dc7546d | 4110 | /* self-refresh has much higher latency */ |
69e302a9 | 4111 | static const int sr_latency_ns = 12000; |
d210246a CW |
4112 | int clock = crtc->mode.clock; |
4113 | int htotal = crtc->mode.htotal; | |
4114 | int hdisplay = crtc->mode.hdisplay; | |
4115 | int pixel_size = crtc->fb->bits_per_pixel / 8; | |
4116 | unsigned long line_time_us; | |
4117 | int entries; | |
1dc7546d | 4118 | |
d210246a | 4119 | line_time_us = ((htotal * 1000) / clock); |
1dc7546d JB |
4120 | |
4121 | /* Use ns/us then divide to preserve precision */ | |
d210246a CW |
4122 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
4123 | pixel_size * hdisplay; | |
4124 | entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE); | |
d210246a | 4125 | srwm = I965_FIFO_SIZE - entries; |
1dc7546d JB |
4126 | if (srwm < 0) |
4127 | srwm = 1; | |
1b07e04e | 4128 | srwm &= 0x1ff; |
308977ac CW |
4129 | DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n", |
4130 | entries, srwm); | |
4fe5e611 | 4131 | |
d210246a | 4132 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
5eddb70b | 4133 | pixel_size * 64; |
d210246a | 4134 | entries = DIV_ROUND_UP(entries, |
8de9b311 | 4135 | i965_cursor_wm_info.cacheline_size); |
4fe5e611 | 4136 | cursor_sr = i965_cursor_wm_info.fifo_size - |
d210246a | 4137 | (entries + i965_cursor_wm_info.guard_size); |
4fe5e611 ZY |
4138 | |
4139 | if (cursor_sr > i965_cursor_wm_info.max_wm) | |
4140 | cursor_sr = i965_cursor_wm_info.max_wm; | |
4141 | ||
4142 | DRM_DEBUG_KMS("self-refresh watermark: display plane %d " | |
4143 | "cursor %d\n", srwm, cursor_sr); | |
4144 | ||
a6c45cf0 | 4145 | if (IS_CRESTLINE(dev)) |
adcdbc66 | 4146 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); |
33c5fd12 DJ |
4147 | } else { |
4148 | /* Turn off self refresh if both pipes are enabled */ | |
a6c45cf0 | 4149 | if (IS_CRESTLINE(dev)) |
adcdbc66 JB |
4150 | I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) |
4151 | & ~FW_BLC_SELF_EN); | |
1dc7546d | 4152 | } |
7662c8bd | 4153 | |
1dc7546d JB |
4154 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", |
4155 | srwm); | |
7662c8bd SL |
4156 | |
4157 | /* 965 has limitations... */ | |
417ae147 CW |
4158 | I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | |
4159 | (8 << 16) | (8 << 8) | (8 << 0)); | |
7662c8bd | 4160 | I915_WRITE(DSPFW2, (8 << 8) | (8 << 0)); |
4fe5e611 ZY |
4161 | /* update cursor SR watermark */ |
4162 | I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); | |
7662c8bd SL |
4163 | } |
4164 | ||
d210246a | 4165 | static void i9xx_update_wm(struct drm_device *dev) |
7662c8bd SL |
4166 | { |
4167 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d210246a | 4168 | const struct intel_watermark_params *wm_info; |
dff33cfc JB |
4169 | uint32_t fwater_lo; |
4170 | uint32_t fwater_hi; | |
d210246a CW |
4171 | int cwm, srwm = 1; |
4172 | int fifo_size; | |
dff33cfc | 4173 | int planea_wm, planeb_wm; |
d210246a | 4174 | struct drm_crtc *crtc, *enabled = NULL; |
7662c8bd | 4175 | |
72557b4f | 4176 | if (IS_I945GM(dev)) |
d210246a | 4177 | wm_info = &i945_wm_info; |
a6c45cf0 | 4178 | else if (!IS_GEN2(dev)) |
d210246a | 4179 | wm_info = &i915_wm_info; |
7662c8bd | 4180 | else |
d210246a CW |
4181 | wm_info = &i855_wm_info; |
4182 | ||
4183 | fifo_size = dev_priv->display.get_fifo_size(dev, 0); | |
4184 | crtc = intel_get_crtc_for_plane(dev, 0); | |
4185 | if (crtc->enabled && crtc->fb) { | |
4186 | planea_wm = intel_calculate_wm(crtc->mode.clock, | |
4187 | wm_info, fifo_size, | |
4188 | crtc->fb->bits_per_pixel / 8, | |
4189 | latency_ns); | |
4190 | enabled = crtc; | |
4191 | } else | |
4192 | planea_wm = fifo_size - wm_info->guard_size; | |
4193 | ||
4194 | fifo_size = dev_priv->display.get_fifo_size(dev, 1); | |
4195 | crtc = intel_get_crtc_for_plane(dev, 1); | |
4196 | if (crtc->enabled && crtc->fb) { | |
4197 | planeb_wm = intel_calculate_wm(crtc->mode.clock, | |
4198 | wm_info, fifo_size, | |
4199 | crtc->fb->bits_per_pixel / 8, | |
4200 | latency_ns); | |
4201 | if (enabled == NULL) | |
4202 | enabled = crtc; | |
4203 | else | |
4204 | enabled = NULL; | |
4205 | } else | |
4206 | planeb_wm = fifo_size - wm_info->guard_size; | |
7662c8bd | 4207 | |
28c97730 | 4208 | DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); |
7662c8bd SL |
4209 | |
4210 | /* | |
4211 | * Overlay gets an aggressive default since video jitter is bad. | |
4212 | */ | |
4213 | cwm = 2; | |
4214 | ||
18b2190c AL |
4215 | /* Play safe and disable self-refresh before adjusting watermarks. */ |
4216 | if (IS_I945G(dev) || IS_I945GM(dev)) | |
4217 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0); | |
4218 | else if (IS_I915GM(dev)) | |
4219 | I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN); | |
4220 | ||
dff33cfc | 4221 | /* Calc sr entries for one plane configs */ |
d210246a | 4222 | if (HAS_FW_BLC(dev) && enabled) { |
dff33cfc | 4223 | /* self-refresh has much higher latency */ |
69e302a9 | 4224 | static const int sr_latency_ns = 6000; |
d210246a CW |
4225 | int clock = enabled->mode.clock; |
4226 | int htotal = enabled->mode.htotal; | |
4227 | int hdisplay = enabled->mode.hdisplay; | |
4228 | int pixel_size = enabled->fb->bits_per_pixel / 8; | |
4229 | unsigned long line_time_us; | |
4230 | int entries; | |
dff33cfc | 4231 | |
d210246a | 4232 | line_time_us = (htotal * 1000) / clock; |
dff33cfc JB |
4233 | |
4234 | /* Use ns/us then divide to preserve precision */ | |
d210246a CW |
4235 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
4236 | pixel_size * hdisplay; | |
4237 | entries = DIV_ROUND_UP(entries, wm_info->cacheline_size); | |
4238 | DRM_DEBUG_KMS("self-refresh entries: %d\n", entries); | |
4239 | srwm = wm_info->fifo_size - entries; | |
dff33cfc JB |
4240 | if (srwm < 0) |
4241 | srwm = 1; | |
ee980b80 LP |
4242 | |
4243 | if (IS_I945G(dev) || IS_I945GM(dev)) | |
18b2190c AL |
4244 | I915_WRITE(FW_BLC_SELF, |
4245 | FW_BLC_SELF_FIFO_MASK | (srwm & 0xff)); | |
4246 | else if (IS_I915GM(dev)) | |
ee980b80 | 4247 | I915_WRITE(FW_BLC_SELF, srwm & 0x3f); |
7662c8bd SL |
4248 | } |
4249 | ||
28c97730 | 4250 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", |
5eddb70b | 4251 | planea_wm, planeb_wm, cwm, srwm); |
7662c8bd | 4252 | |
dff33cfc JB |
4253 | fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f); |
4254 | fwater_hi = (cwm & 0x1f); | |
4255 | ||
4256 | /* Set request length to 8 cachelines per fetch */ | |
4257 | fwater_lo = fwater_lo | (1 << 24) | (1 << 8); | |
4258 | fwater_hi = fwater_hi | (1 << 8); | |
7662c8bd SL |
4259 | |
4260 | I915_WRITE(FW_BLC, fwater_lo); | |
4261 | I915_WRITE(FW_BLC2, fwater_hi); | |
18b2190c | 4262 | |
d210246a CW |
4263 | if (HAS_FW_BLC(dev)) { |
4264 | if (enabled) { | |
4265 | if (IS_I945G(dev) || IS_I945GM(dev)) | |
4266 | I915_WRITE(FW_BLC_SELF, | |
4267 | FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN); | |
4268 | else if (IS_I915GM(dev)) | |
4269 | I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN); | |
4270 | DRM_DEBUG_KMS("memory self refresh enabled\n"); | |
4271 | } else | |
4272 | DRM_DEBUG_KMS("memory self refresh disabled\n"); | |
4273 | } | |
7662c8bd SL |
4274 | } |
4275 | ||
d210246a | 4276 | static void i830_update_wm(struct drm_device *dev) |
7662c8bd SL |
4277 | { |
4278 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d210246a CW |
4279 | struct drm_crtc *crtc; |
4280 | uint32_t fwater_lo; | |
dff33cfc | 4281 | int planea_wm; |
7662c8bd | 4282 | |
d210246a CW |
4283 | crtc = single_enabled_crtc(dev); |
4284 | if (crtc == NULL) | |
4285 | return; | |
7662c8bd | 4286 | |
d210246a CW |
4287 | planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info, |
4288 | dev_priv->display.get_fifo_size(dev, 0), | |
4289 | crtc->fb->bits_per_pixel / 8, | |
4290 | latency_ns); | |
4291 | fwater_lo = I915_READ(FW_BLC) & ~0xfff; | |
f3601326 JB |
4292 | fwater_lo |= (3<<8) | planea_wm; |
4293 | ||
28c97730 | 4294 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm); |
7662c8bd SL |
4295 | |
4296 | I915_WRITE(FW_BLC, fwater_lo); | |
4297 | } | |
4298 | ||
7f8a8569 | 4299 | #define ILK_LP0_PLANE_LATENCY 700 |
c936f44d | 4300 | #define ILK_LP0_CURSOR_LATENCY 1300 |
7f8a8569 | 4301 | |
1398261a YL |
4302 | /* |
4303 | * Check the wm result. | |
4304 | * | |
4305 | * If any calculated watermark values is larger than the maximum value that | |
4306 | * can be programmed into the associated watermark register, that watermark | |
4307 | * must be disabled. | |
1398261a | 4308 | */ |
b79d4990 JB |
4309 | static bool ironlake_check_srwm(struct drm_device *dev, int level, |
4310 | int fbc_wm, int display_wm, int cursor_wm, | |
4311 | const struct intel_watermark_params *display, | |
4312 | const struct intel_watermark_params *cursor) | |
1398261a YL |
4313 | { |
4314 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4315 | ||
4316 | DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d," | |
4317 | " cursor %d\n", level, display_wm, fbc_wm, cursor_wm); | |
4318 | ||
4319 | if (fbc_wm > SNB_FBC_MAX_SRWM) { | |
4320 | DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n", | |
b79d4990 | 4321 | fbc_wm, SNB_FBC_MAX_SRWM, level); |
1398261a YL |
4322 | |
4323 | /* fbc has it's own way to disable FBC WM */ | |
4324 | I915_WRITE(DISP_ARB_CTL, | |
4325 | I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS); | |
4326 | return false; | |
4327 | } | |
4328 | ||
b79d4990 | 4329 | if (display_wm > display->max_wm) { |
1398261a | 4330 | DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n", |
b79d4990 | 4331 | display_wm, SNB_DISPLAY_MAX_SRWM, level); |
1398261a YL |
4332 | return false; |
4333 | } | |
4334 | ||
b79d4990 | 4335 | if (cursor_wm > cursor->max_wm) { |
1398261a | 4336 | DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n", |
b79d4990 | 4337 | cursor_wm, SNB_CURSOR_MAX_SRWM, level); |
1398261a YL |
4338 | return false; |
4339 | } | |
4340 | ||
4341 | if (!(fbc_wm || display_wm || cursor_wm)) { | |
4342 | DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level); | |
4343 | return false; | |
4344 | } | |
4345 | ||
4346 | return true; | |
4347 | } | |
4348 | ||
4349 | /* | |
4350 | * Compute watermark values of WM[1-3], | |
4351 | */ | |
d210246a CW |
4352 | static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane, |
4353 | int latency_ns, | |
b79d4990 JB |
4354 | const struct intel_watermark_params *display, |
4355 | const struct intel_watermark_params *cursor, | |
4356 | int *fbc_wm, int *display_wm, int *cursor_wm) | |
1398261a | 4357 | { |
d210246a | 4358 | struct drm_crtc *crtc; |
1398261a | 4359 | unsigned long line_time_us; |
d210246a | 4360 | int hdisplay, htotal, pixel_size, clock; |
b79d4990 | 4361 | int line_count, line_size; |
1398261a YL |
4362 | int small, large; |
4363 | int entries; | |
1398261a YL |
4364 | |
4365 | if (!latency_ns) { | |
4366 | *fbc_wm = *display_wm = *cursor_wm = 0; | |
4367 | return false; | |
4368 | } | |
4369 | ||
d210246a CW |
4370 | crtc = intel_get_crtc_for_plane(dev, plane); |
4371 | hdisplay = crtc->mode.hdisplay; | |
4372 | htotal = crtc->mode.htotal; | |
4373 | clock = crtc->mode.clock; | |
4374 | pixel_size = crtc->fb->bits_per_pixel / 8; | |
4375 | ||
1398261a YL |
4376 | line_time_us = (htotal * 1000) / clock; |
4377 | line_count = (latency_ns / line_time_us + 1000) / 1000; | |
4378 | line_size = hdisplay * pixel_size; | |
4379 | ||
4380 | /* Use the minimum of the small and large buffer method for primary */ | |
4381 | small = ((clock * pixel_size / 1000) * latency_ns) / 1000; | |
4382 | large = line_count * line_size; | |
4383 | ||
b79d4990 JB |
4384 | entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); |
4385 | *display_wm = entries + display->guard_size; | |
1398261a YL |
4386 | |
4387 | /* | |
b79d4990 | 4388 | * Spec says: |
1398261a YL |
4389 | * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2 |
4390 | */ | |
4391 | *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2; | |
4392 | ||
4393 | /* calculate the self-refresh watermark for display cursor */ | |
4394 | entries = line_count * pixel_size * 64; | |
b79d4990 JB |
4395 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); |
4396 | *cursor_wm = entries + cursor->guard_size; | |
1398261a | 4397 | |
b79d4990 JB |
4398 | return ironlake_check_srwm(dev, level, |
4399 | *fbc_wm, *display_wm, *cursor_wm, | |
4400 | display, cursor); | |
4401 | } | |
4402 | ||
d210246a | 4403 | static void ironlake_update_wm(struct drm_device *dev) |
b79d4990 JB |
4404 | { |
4405 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d210246a CW |
4406 | int fbc_wm, plane_wm, cursor_wm; |
4407 | unsigned int enabled; | |
b79d4990 JB |
4408 | |
4409 | enabled = 0; | |
9f405100 CW |
4410 | if (g4x_compute_wm0(dev, 0, |
4411 | &ironlake_display_wm_info, | |
4412 | ILK_LP0_PLANE_LATENCY, | |
4413 | &ironlake_cursor_wm_info, | |
4414 | ILK_LP0_CURSOR_LATENCY, | |
4415 | &plane_wm, &cursor_wm)) { | |
b79d4990 JB |
4416 | I915_WRITE(WM0_PIPEA_ILK, |
4417 | (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); | |
4418 | DRM_DEBUG_KMS("FIFO watermarks For pipe A -" | |
4419 | " plane %d, " "cursor: %d\n", | |
4420 | plane_wm, cursor_wm); | |
d210246a | 4421 | enabled |= 1; |
b79d4990 JB |
4422 | } |
4423 | ||
9f405100 CW |
4424 | if (g4x_compute_wm0(dev, 1, |
4425 | &ironlake_display_wm_info, | |
4426 | ILK_LP0_PLANE_LATENCY, | |
4427 | &ironlake_cursor_wm_info, | |
4428 | ILK_LP0_CURSOR_LATENCY, | |
4429 | &plane_wm, &cursor_wm)) { | |
b79d4990 JB |
4430 | I915_WRITE(WM0_PIPEB_ILK, |
4431 | (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); | |
4432 | DRM_DEBUG_KMS("FIFO watermarks For pipe B -" | |
4433 | " plane %d, cursor: %d\n", | |
4434 | plane_wm, cursor_wm); | |
d210246a | 4435 | enabled |= 2; |
b79d4990 JB |
4436 | } |
4437 | ||
4438 | /* | |
4439 | * Calculate and update the self-refresh watermark only when one | |
4440 | * display plane is used. | |
4441 | */ | |
4442 | I915_WRITE(WM3_LP_ILK, 0); | |
4443 | I915_WRITE(WM2_LP_ILK, 0); | |
4444 | I915_WRITE(WM1_LP_ILK, 0); | |
4445 | ||
d210246a | 4446 | if (!single_plane_enabled(enabled)) |
b79d4990 | 4447 | return; |
d210246a | 4448 | enabled = ffs(enabled) - 1; |
b79d4990 JB |
4449 | |
4450 | /* WM1 */ | |
d210246a CW |
4451 | if (!ironlake_compute_srwm(dev, 1, enabled, |
4452 | ILK_READ_WM1_LATENCY() * 500, | |
b79d4990 JB |
4453 | &ironlake_display_srwm_info, |
4454 | &ironlake_cursor_srwm_info, | |
4455 | &fbc_wm, &plane_wm, &cursor_wm)) | |
4456 | return; | |
4457 | ||
4458 | I915_WRITE(WM1_LP_ILK, | |
4459 | WM1_LP_SR_EN | | |
4460 | (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) | | |
4461 | (fbc_wm << WM1_LP_FBC_SHIFT) | | |
4462 | (plane_wm << WM1_LP_SR_SHIFT) | | |
4463 | cursor_wm); | |
4464 | ||
4465 | /* WM2 */ | |
d210246a CW |
4466 | if (!ironlake_compute_srwm(dev, 2, enabled, |
4467 | ILK_READ_WM2_LATENCY() * 500, | |
b79d4990 JB |
4468 | &ironlake_display_srwm_info, |
4469 | &ironlake_cursor_srwm_info, | |
4470 | &fbc_wm, &plane_wm, &cursor_wm)) | |
4471 | return; | |
4472 | ||
4473 | I915_WRITE(WM2_LP_ILK, | |
4474 | WM2_LP_EN | | |
4475 | (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) | | |
4476 | (fbc_wm << WM1_LP_FBC_SHIFT) | | |
4477 | (plane_wm << WM1_LP_SR_SHIFT) | | |
4478 | cursor_wm); | |
4479 | ||
4480 | /* | |
4481 | * WM3 is unsupported on ILK, probably because we don't have latency | |
4482 | * data for that power state | |
4483 | */ | |
1398261a YL |
4484 | } |
4485 | ||
d210246a | 4486 | static void sandybridge_update_wm(struct drm_device *dev) |
1398261a YL |
4487 | { |
4488 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a0fa62d3 | 4489 | int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */ |
d210246a CW |
4490 | int fbc_wm, plane_wm, cursor_wm; |
4491 | unsigned int enabled; | |
1398261a YL |
4492 | |
4493 | enabled = 0; | |
9f405100 CW |
4494 | if (g4x_compute_wm0(dev, 0, |
4495 | &sandybridge_display_wm_info, latency, | |
4496 | &sandybridge_cursor_wm_info, latency, | |
4497 | &plane_wm, &cursor_wm)) { | |
1398261a YL |
4498 | I915_WRITE(WM0_PIPEA_ILK, |
4499 | (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); | |
4500 | DRM_DEBUG_KMS("FIFO watermarks For pipe A -" | |
4501 | " plane %d, " "cursor: %d\n", | |
4502 | plane_wm, cursor_wm); | |
d210246a | 4503 | enabled |= 1; |
1398261a YL |
4504 | } |
4505 | ||
9f405100 CW |
4506 | if (g4x_compute_wm0(dev, 1, |
4507 | &sandybridge_display_wm_info, latency, | |
4508 | &sandybridge_cursor_wm_info, latency, | |
4509 | &plane_wm, &cursor_wm)) { | |
1398261a YL |
4510 | I915_WRITE(WM0_PIPEB_ILK, |
4511 | (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); | |
4512 | DRM_DEBUG_KMS("FIFO watermarks For pipe B -" | |
4513 | " plane %d, cursor: %d\n", | |
4514 | plane_wm, cursor_wm); | |
d210246a | 4515 | enabled |= 2; |
1398261a YL |
4516 | } |
4517 | ||
4518 | /* | |
4519 | * Calculate and update the self-refresh watermark only when one | |
4520 | * display plane is used. | |
4521 | * | |
4522 | * SNB support 3 levels of watermark. | |
4523 | * | |
4524 | * WM1/WM2/WM2 watermarks have to be enabled in the ascending order, | |
4525 | * and disabled in the descending order | |
4526 | * | |
4527 | */ | |
4528 | I915_WRITE(WM3_LP_ILK, 0); | |
4529 | I915_WRITE(WM2_LP_ILK, 0); | |
4530 | I915_WRITE(WM1_LP_ILK, 0); | |
4531 | ||
d210246a | 4532 | if (!single_plane_enabled(enabled)) |
1398261a | 4533 | return; |
d210246a | 4534 | enabled = ffs(enabled) - 1; |
1398261a YL |
4535 | |
4536 | /* WM1 */ | |
d210246a CW |
4537 | if (!ironlake_compute_srwm(dev, 1, enabled, |
4538 | SNB_READ_WM1_LATENCY() * 500, | |
b79d4990 JB |
4539 | &sandybridge_display_srwm_info, |
4540 | &sandybridge_cursor_srwm_info, | |
4541 | &fbc_wm, &plane_wm, &cursor_wm)) | |
1398261a YL |
4542 | return; |
4543 | ||
4544 | I915_WRITE(WM1_LP_ILK, | |
4545 | WM1_LP_SR_EN | | |
4546 | (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) | | |
4547 | (fbc_wm << WM1_LP_FBC_SHIFT) | | |
4548 | (plane_wm << WM1_LP_SR_SHIFT) | | |
4549 | cursor_wm); | |
4550 | ||
4551 | /* WM2 */ | |
d210246a CW |
4552 | if (!ironlake_compute_srwm(dev, 2, enabled, |
4553 | SNB_READ_WM2_LATENCY() * 500, | |
b79d4990 JB |
4554 | &sandybridge_display_srwm_info, |
4555 | &sandybridge_cursor_srwm_info, | |
4556 | &fbc_wm, &plane_wm, &cursor_wm)) | |
1398261a YL |
4557 | return; |
4558 | ||
4559 | I915_WRITE(WM2_LP_ILK, | |
4560 | WM2_LP_EN | | |
4561 | (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) | | |
4562 | (fbc_wm << WM1_LP_FBC_SHIFT) | | |
4563 | (plane_wm << WM1_LP_SR_SHIFT) | | |
4564 | cursor_wm); | |
4565 | ||
4566 | /* WM3 */ | |
d210246a CW |
4567 | if (!ironlake_compute_srwm(dev, 3, enabled, |
4568 | SNB_READ_WM3_LATENCY() * 500, | |
b79d4990 JB |
4569 | &sandybridge_display_srwm_info, |
4570 | &sandybridge_cursor_srwm_info, | |
4571 | &fbc_wm, &plane_wm, &cursor_wm)) | |
1398261a YL |
4572 | return; |
4573 | ||
4574 | I915_WRITE(WM3_LP_ILK, | |
4575 | WM3_LP_EN | | |
4576 | (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) | | |
4577 | (fbc_wm << WM1_LP_FBC_SHIFT) | | |
4578 | (plane_wm << WM1_LP_SR_SHIFT) | | |
4579 | cursor_wm); | |
4580 | } | |
4581 | ||
7662c8bd SL |
4582 | /** |
4583 | * intel_update_watermarks - update FIFO watermark values based on current modes | |
4584 | * | |
4585 | * Calculate watermark values for the various WM regs based on current mode | |
4586 | * and plane configuration. | |
4587 | * | |
4588 | * There are several cases to deal with here: | |
4589 | * - normal (i.e. non-self-refresh) | |
4590 | * - self-refresh (SR) mode | |
4591 | * - lines are large relative to FIFO size (buffer can hold up to 2) | |
4592 | * - lines are small relative to FIFO size (buffer can hold more than 2 | |
4593 | * lines), so need to account for TLB latency | |
4594 | * | |
4595 | * The normal calculation is: | |
4596 | * watermark = dotclock * bytes per pixel * latency | |
4597 | * where latency is platform & configuration dependent (we assume pessimal | |
4598 | * values here). | |
4599 | * | |
4600 | * The SR calculation is: | |
4601 | * watermark = (trunc(latency/line time)+1) * surface width * | |
4602 | * bytes per pixel | |
4603 | * where | |
4604 | * line time = htotal / dotclock | |
fa143215 | 4605 | * surface width = hdisplay for normal plane and 64 for cursor |
7662c8bd SL |
4606 | * and latency is assumed to be high, as above. |
4607 | * | |
4608 | * The final value programmed to the register should always be rounded up, | |
4609 | * and include an extra 2 entries to account for clock crossings. | |
4610 | * | |
4611 | * We don't use the sprite, so we can ignore that. And on Crestline we have | |
4612 | * to set the non-SR watermarks to 8. | |
5eddb70b | 4613 | */ |
7662c8bd SL |
4614 | static void intel_update_watermarks(struct drm_device *dev) |
4615 | { | |
e70236a8 | 4616 | struct drm_i915_private *dev_priv = dev->dev_private; |
7662c8bd | 4617 | |
d210246a CW |
4618 | if (dev_priv->display.update_wm) |
4619 | dev_priv->display.update_wm(dev); | |
7662c8bd SL |
4620 | } |
4621 | ||
a7615030 CW |
4622 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
4623 | { | |
72bbe58c KP |
4624 | if (i915_panel_use_ssc >= 0) |
4625 | return i915_panel_use_ssc != 0; | |
4626 | return dev_priv->lvds_use_ssc | |
435793df | 4627 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
4628 | } |
4629 | ||
5a354204 JB |
4630 | /** |
4631 | * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send | |
4632 | * @crtc: CRTC structure | |
4633 | * | |
4634 | * A pipe may be connected to one or more outputs. Based on the depth of the | |
4635 | * attached framebuffer, choose a good color depth to use on the pipe. | |
4636 | * | |
4637 | * If possible, match the pipe depth to the fb depth. In some cases, this | |
4638 | * isn't ideal, because the connected output supports a lesser or restricted | |
4639 | * set of depths. Resolve that here: | |
4640 | * LVDS typically supports only 6bpc, so clamp down in that case | |
4641 | * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc | |
4642 | * Displays may support a restricted set as well, check EDID and clamp as | |
4643 | * appropriate. | |
4644 | * | |
4645 | * RETURNS: | |
4646 | * Dithering requirement (i.e. false if display bpc and pipe bpc match, | |
4647 | * true if they don't match). | |
4648 | */ | |
4649 | static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc, | |
4650 | unsigned int *pipe_bpp) | |
4651 | { | |
4652 | struct drm_device *dev = crtc->dev; | |
4653 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4654 | struct drm_encoder *encoder; | |
4655 | struct drm_connector *connector; | |
4656 | unsigned int display_bpc = UINT_MAX, bpc; | |
4657 | ||
4658 | /* Walk the encoders & connectors on this crtc, get min bpc */ | |
4659 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
4660 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); | |
4661 | ||
4662 | if (encoder->crtc != crtc) | |
4663 | continue; | |
4664 | ||
4665 | if (intel_encoder->type == INTEL_OUTPUT_LVDS) { | |
4666 | unsigned int lvds_bpc; | |
4667 | ||
4668 | if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == | |
4669 | LVDS_A3_POWER_UP) | |
4670 | lvds_bpc = 8; | |
4671 | else | |
4672 | lvds_bpc = 6; | |
4673 | ||
4674 | if (lvds_bpc < display_bpc) { | |
4675 | DRM_DEBUG_DRIVER("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc); | |
4676 | display_bpc = lvds_bpc; | |
4677 | } | |
4678 | continue; | |
4679 | } | |
4680 | ||
4681 | if (intel_encoder->type == INTEL_OUTPUT_EDP) { | |
4682 | /* Use VBT settings if we have an eDP panel */ | |
4683 | unsigned int edp_bpc = dev_priv->edp.bpp / 3; | |
4684 | ||
4685 | if (edp_bpc < display_bpc) { | |
4686 | DRM_DEBUG_DRIVER("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc); | |
4687 | display_bpc = edp_bpc; | |
4688 | } | |
4689 | continue; | |
4690 | } | |
4691 | ||
4692 | /* Not one of the known troublemakers, check the EDID */ | |
4693 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
4694 | head) { | |
4695 | if (connector->encoder != encoder) | |
4696 | continue; | |
4697 | ||
62ac41a6 JB |
4698 | /* Don't use an invalid EDID bpc value */ |
4699 | if (connector->display_info.bpc && | |
4700 | connector->display_info.bpc < display_bpc) { | |
5a354204 JB |
4701 | DRM_DEBUG_DRIVER("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc); |
4702 | display_bpc = connector->display_info.bpc; | |
4703 | } | |
4704 | } | |
4705 | ||
4706 | /* | |
4707 | * HDMI is either 12 or 8, so if the display lets 10bpc sneak | |
4708 | * through, clamp it down. (Note: >12bpc will be caught below.) | |
4709 | */ | |
4710 | if (intel_encoder->type == INTEL_OUTPUT_HDMI) { | |
4711 | if (display_bpc > 8 && display_bpc < 12) { | |
4712 | DRM_DEBUG_DRIVER("forcing bpc to 12 for HDMI\n"); | |
4713 | display_bpc = 12; | |
4714 | } else { | |
4715 | DRM_DEBUG_DRIVER("forcing bpc to 8 for HDMI\n"); | |
4716 | display_bpc = 8; | |
4717 | } | |
4718 | } | |
4719 | } | |
4720 | ||
4721 | /* | |
4722 | * We could just drive the pipe at the highest bpc all the time and | |
4723 | * enable dithering as needed, but that costs bandwidth. So choose | |
4724 | * the minimum value that expresses the full color range of the fb but | |
4725 | * also stays within the max display bpc discovered above. | |
4726 | */ | |
4727 | ||
4728 | switch (crtc->fb->depth) { | |
4729 | case 8: | |
4730 | bpc = 8; /* since we go through a colormap */ | |
4731 | break; | |
4732 | case 15: | |
4733 | case 16: | |
4734 | bpc = 6; /* min is 18bpp */ | |
4735 | break; | |
4736 | case 24: | |
578393cd | 4737 | bpc = 8; |
5a354204 JB |
4738 | break; |
4739 | case 30: | |
578393cd | 4740 | bpc = 10; |
5a354204 JB |
4741 | break; |
4742 | case 48: | |
578393cd | 4743 | bpc = 12; |
5a354204 JB |
4744 | break; |
4745 | default: | |
4746 | DRM_DEBUG("unsupported depth, assuming 24 bits\n"); | |
4747 | bpc = min((unsigned int)8, display_bpc); | |
4748 | break; | |
4749 | } | |
4750 | ||
578393cd KP |
4751 | display_bpc = min(display_bpc, bpc); |
4752 | ||
5a354204 JB |
4753 | DRM_DEBUG_DRIVER("setting pipe bpc to %d (max display bpc %d)\n", |
4754 | bpc, display_bpc); | |
4755 | ||
578393cd | 4756 | *pipe_bpp = display_bpc * 3; |
5a354204 JB |
4757 | |
4758 | return display_bpc != bpc; | |
4759 | } | |
4760 | ||
f564048e EA |
4761 | static int i9xx_crtc_mode_set(struct drm_crtc *crtc, |
4762 | struct drm_display_mode *mode, | |
4763 | struct drm_display_mode *adjusted_mode, | |
4764 | int x, int y, | |
4765 | struct drm_framebuffer *old_fb) | |
79e53945 JB |
4766 | { |
4767 | struct drm_device *dev = crtc->dev; | |
4768 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4769 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4770 | int pipe = intel_crtc->pipe; | |
80824003 | 4771 | int plane = intel_crtc->plane; |
c751ce4f | 4772 | int refclk, num_connectors = 0; |
652c393a | 4773 | intel_clock_t clock, reduced_clock; |
5eddb70b | 4774 | u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf; |
652c393a | 4775 | bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false; |
a4fc5ed6 | 4776 | bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false; |
79e53945 | 4777 | struct drm_mode_config *mode_config = &dev->mode_config; |
5eddb70b | 4778 | struct intel_encoder *encoder; |
d4906093 | 4779 | const intel_limit_t *limit; |
5c3b82e2 | 4780 | int ret; |
fae14981 | 4781 | u32 temp; |
aa9b500d | 4782 | u32 lvds_sync = 0; |
79e53945 | 4783 | |
5eddb70b CW |
4784 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { |
4785 | if (encoder->base.crtc != crtc) | |
79e53945 JB |
4786 | continue; |
4787 | ||
5eddb70b | 4788 | switch (encoder->type) { |
79e53945 JB |
4789 | case INTEL_OUTPUT_LVDS: |
4790 | is_lvds = true; | |
4791 | break; | |
4792 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 4793 | case INTEL_OUTPUT_HDMI: |
79e53945 | 4794 | is_sdvo = true; |
5eddb70b | 4795 | if (encoder->needs_tv_clock) |
e2f0ba97 | 4796 | is_tv = true; |
79e53945 JB |
4797 | break; |
4798 | case INTEL_OUTPUT_DVO: | |
4799 | is_dvo = true; | |
4800 | break; | |
4801 | case INTEL_OUTPUT_TVOUT: | |
4802 | is_tv = true; | |
4803 | break; | |
4804 | case INTEL_OUTPUT_ANALOG: | |
4805 | is_crt = true; | |
4806 | break; | |
a4fc5ed6 KP |
4807 | case INTEL_OUTPUT_DISPLAYPORT: |
4808 | is_dp = true; | |
4809 | break; | |
79e53945 | 4810 | } |
43565a06 | 4811 | |
c751ce4f | 4812 | num_connectors++; |
79e53945 JB |
4813 | } |
4814 | ||
a7615030 | 4815 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
43565a06 | 4816 | refclk = dev_priv->lvds_ssc_freq * 1000; |
28c97730 | 4817 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", |
5eddb70b | 4818 | refclk / 1000); |
a6c45cf0 | 4819 | } else if (!IS_GEN2(dev)) { |
79e53945 JB |
4820 | refclk = 96000; |
4821 | } else { | |
4822 | refclk = 48000; | |
4823 | } | |
4824 | ||
d4906093 ML |
4825 | /* |
4826 | * Returns a set of divisors for the desired target clock with the given | |
4827 | * refclk, or FALSE. The returned values represent the clock equation: | |
4828 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
4829 | */ | |
1b894b59 | 4830 | limit = intel_limit(crtc, refclk); |
d4906093 | 4831 | ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock); |
79e53945 JB |
4832 | if (!ok) { |
4833 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
5c3b82e2 | 4834 | return -EINVAL; |
79e53945 JB |
4835 | } |
4836 | ||
cda4b7d3 | 4837 | /* Ensure that the cursor is valid for the new mode before changing... */ |
6b383a7f | 4838 | intel_crtc_update_cursor(crtc, true); |
cda4b7d3 | 4839 | |
ddc9003c ZY |
4840 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
4841 | has_reduced_clock = limit->find_pll(limit, crtc, | |
5eddb70b CW |
4842 | dev_priv->lvds_downclock, |
4843 | refclk, | |
4844 | &reduced_clock); | |
18f9ed12 ZY |
4845 | if (has_reduced_clock && (clock.p != reduced_clock.p)) { |
4846 | /* | |
4847 | * If the different P is found, it means that we can't | |
4848 | * switch the display clock by using the FP0/FP1. | |
4849 | * In such case we will disable the LVDS downclock | |
4850 | * feature. | |
4851 | */ | |
4852 | DRM_DEBUG_KMS("Different P is found for " | |
5eddb70b | 4853 | "LVDS clock/downclock\n"); |
18f9ed12 ZY |
4854 | has_reduced_clock = 0; |
4855 | } | |
652c393a | 4856 | } |
7026d4ac ZW |
4857 | /* SDVO TV has fixed PLL values depend on its clock range, |
4858 | this mirrors vbios setting. */ | |
4859 | if (is_sdvo && is_tv) { | |
4860 | if (adjusted_mode->clock >= 100000 | |
5eddb70b | 4861 | && adjusted_mode->clock < 140500) { |
7026d4ac ZW |
4862 | clock.p1 = 2; |
4863 | clock.p2 = 10; | |
4864 | clock.n = 3; | |
4865 | clock.m1 = 16; | |
4866 | clock.m2 = 8; | |
4867 | } else if (adjusted_mode->clock >= 140500 | |
5eddb70b | 4868 | && adjusted_mode->clock <= 200000) { |
7026d4ac ZW |
4869 | clock.p1 = 1; |
4870 | clock.p2 = 10; | |
4871 | clock.n = 6; | |
4872 | clock.m1 = 12; | |
4873 | clock.m2 = 8; | |
4874 | } | |
4875 | } | |
4876 | ||
f2b115e6 | 4877 | if (IS_PINEVIEW(dev)) { |
2177832f | 4878 | fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2; |
652c393a JB |
4879 | if (has_reduced_clock) |
4880 | fp2 = (1 << reduced_clock.n) << 16 | | |
4881 | reduced_clock.m1 << 8 | reduced_clock.m2; | |
4882 | } else { | |
2177832f | 4883 | fp = clock.n << 16 | clock.m1 << 8 | clock.m2; |
652c393a JB |
4884 | if (has_reduced_clock) |
4885 | fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 | | |
4886 | reduced_clock.m2; | |
4887 | } | |
79e53945 | 4888 | |
929c77fb | 4889 | dpll = DPLL_VGA_MODE_DIS; |
2c07245f | 4890 | |
a6c45cf0 | 4891 | if (!IS_GEN2(dev)) { |
79e53945 JB |
4892 | if (is_lvds) |
4893 | dpll |= DPLLB_MODE_LVDS; | |
4894 | else | |
4895 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
4896 | if (is_sdvo) { | |
6c9547ff CW |
4897 | int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); |
4898 | if (pixel_multiplier > 1) { | |
4899 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) | |
4900 | dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES; | |
6c9547ff | 4901 | } |
79e53945 | 4902 | dpll |= DPLL_DVO_HIGH_SPEED; |
79e53945 | 4903 | } |
929c77fb | 4904 | if (is_dp) |
a4fc5ed6 | 4905 | dpll |= DPLL_DVO_HIGH_SPEED; |
79e53945 JB |
4906 | |
4907 | /* compute bitmask from p1 value */ | |
f2b115e6 AJ |
4908 | if (IS_PINEVIEW(dev)) |
4909 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
2c07245f | 4910 | else { |
2177832f | 4911 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
652c393a JB |
4912 | if (IS_G4X(dev) && has_reduced_clock) |
4913 | dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
2c07245f | 4914 | } |
79e53945 JB |
4915 | switch (clock.p2) { |
4916 | case 5: | |
4917 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
4918 | break; | |
4919 | case 7: | |
4920 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
4921 | break; | |
4922 | case 10: | |
4923 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
4924 | break; | |
4925 | case 14: | |
4926 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
4927 | break; | |
4928 | } | |
929c77fb | 4929 | if (INTEL_INFO(dev)->gen >= 4) |
79e53945 JB |
4930 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); |
4931 | } else { | |
4932 | if (is_lvds) { | |
4933 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
4934 | } else { | |
4935 | if (clock.p1 == 2) | |
4936 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
4937 | else | |
4938 | dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
4939 | if (clock.p2 == 4) | |
4940 | dpll |= PLL_P2_DIVIDE_BY_4; | |
4941 | } | |
4942 | } | |
4943 | ||
43565a06 KH |
4944 | if (is_sdvo && is_tv) |
4945 | dpll |= PLL_REF_INPUT_TVCLKINBC; | |
4946 | else if (is_tv) | |
79e53945 | 4947 | /* XXX: just matching BIOS for now */ |
43565a06 | 4948 | /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ |
79e53945 | 4949 | dpll |= 3; |
a7615030 | 4950 | else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 4951 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
4952 | else |
4953 | dpll |= PLL_REF_INPUT_DREFCLK; | |
4954 | ||
4955 | /* setup pipeconf */ | |
5eddb70b | 4956 | pipeconf = I915_READ(PIPECONF(pipe)); |
79e53945 JB |
4957 | |
4958 | /* Set up the display plane register */ | |
4959 | dspcntr = DISPPLANE_GAMMA_ENABLE; | |
4960 | ||
f2b115e6 | 4961 | /* Ironlake's plane is forced to pipe, bit 24 is to |
2c07245f | 4962 | enable color space conversion */ |
929c77fb EA |
4963 | if (pipe == 0) |
4964 | dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; | |
4965 | else | |
4966 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
79e53945 | 4967 | |
a6c45cf0 | 4968 | if (pipe == 0 && INTEL_INFO(dev)->gen < 4) { |
79e53945 JB |
4969 | /* Enable pixel doubling when the dot clock is > 90% of the (display) |
4970 | * core speed. | |
4971 | * | |
4972 | * XXX: No double-wide on 915GM pipe B. Is that the only reason for the | |
4973 | * pipe == 0 check? | |
4974 | */ | |
e70236a8 JB |
4975 | if (mode->clock > |
4976 | dev_priv->display.get_display_clock_speed(dev) * 9 / 10) | |
5eddb70b | 4977 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
79e53945 | 4978 | else |
5eddb70b | 4979 | pipeconf &= ~PIPECONF_DOUBLE_WIDE; |
79e53945 JB |
4980 | } |
4981 | ||
929c77fb | 4982 | dpll |= DPLL_VCO_ENABLE; |
8d86dc6a | 4983 | |
28c97730 | 4984 | DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); |
79e53945 JB |
4985 | drm_mode_debug_printmodeline(mode); |
4986 | ||
fae14981 EA |
4987 | I915_WRITE(FP0(pipe), fp); |
4988 | I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE); | |
5eddb70b | 4989 | |
fae14981 | 4990 | POSTING_READ(DPLL(pipe)); |
c713bb08 | 4991 | udelay(150); |
8db9d77b | 4992 | |
79e53945 JB |
4993 | /* The LVDS pin pair needs to be on before the DPLLs are enabled. |
4994 | * This is an exception to the general rule that mode_set doesn't turn | |
4995 | * things on. | |
4996 | */ | |
4997 | if (is_lvds) { | |
fae14981 | 4998 | temp = I915_READ(LVDS); |
5eddb70b | 4999 | temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; |
b3b095b3 | 5000 | if (pipe == 1) { |
929c77fb | 5001 | temp |= LVDS_PIPEB_SELECT; |
b3b095b3 | 5002 | } else { |
929c77fb | 5003 | temp &= ~LVDS_PIPEB_SELECT; |
b3b095b3 | 5004 | } |
a3e17eb8 | 5005 | /* set the corresponsding LVDS_BORDER bit */ |
5eddb70b | 5006 | temp |= dev_priv->lvds_border_bits; |
79e53945 JB |
5007 | /* Set the B0-B3 data pairs corresponding to whether we're going to |
5008 | * set the DPLLs for dual-channel mode or not. | |
5009 | */ | |
5010 | if (clock.p2 == 7) | |
5eddb70b | 5011 | temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; |
79e53945 | 5012 | else |
5eddb70b | 5013 | temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); |
79e53945 JB |
5014 | |
5015 | /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) | |
5016 | * appropriately here, but we need to look more thoroughly into how | |
5017 | * panels behave in the two modes. | |
5018 | */ | |
929c77fb EA |
5019 | /* set the dithering flag on LVDS as needed */ |
5020 | if (INTEL_INFO(dev)->gen >= 4) { | |
434ed097 | 5021 | if (dev_priv->lvds_dither) |
5eddb70b | 5022 | temp |= LVDS_ENABLE_DITHER; |
434ed097 | 5023 | else |
5eddb70b | 5024 | temp &= ~LVDS_ENABLE_DITHER; |
898822ce | 5025 | } |
aa9b500d BF |
5026 | if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) |
5027 | lvds_sync |= LVDS_HSYNC_POLARITY; | |
5028 | if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) | |
5029 | lvds_sync |= LVDS_VSYNC_POLARITY; | |
5030 | if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY)) | |
5031 | != lvds_sync) { | |
5032 | char flags[2] = "-+"; | |
5033 | DRM_INFO("Changing LVDS panel from " | |
5034 | "(%chsync, %cvsync) to (%chsync, %cvsync)\n", | |
5035 | flags[!(temp & LVDS_HSYNC_POLARITY)], | |
5036 | flags[!(temp & LVDS_VSYNC_POLARITY)], | |
5037 | flags[!(lvds_sync & LVDS_HSYNC_POLARITY)], | |
5038 | flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]); | |
5039 | temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); | |
5040 | temp |= lvds_sync; | |
5041 | } | |
fae14981 | 5042 | I915_WRITE(LVDS, temp); |
79e53945 | 5043 | } |
434ed097 | 5044 | |
929c77fb | 5045 | if (is_dp) { |
a4fc5ed6 | 5046 | intel_dp_set_m_n(crtc, mode, adjusted_mode); |
434ed097 JB |
5047 | } |
5048 | ||
fae14981 | 5049 | I915_WRITE(DPLL(pipe), dpll); |
5eddb70b | 5050 | |
c713bb08 | 5051 | /* Wait for the clocks to stabilize. */ |
fae14981 | 5052 | POSTING_READ(DPLL(pipe)); |
c713bb08 | 5053 | udelay(150); |
32f9d658 | 5054 | |
c713bb08 EA |
5055 | if (INTEL_INFO(dev)->gen >= 4) { |
5056 | temp = 0; | |
5057 | if (is_sdvo) { | |
5058 | temp = intel_mode_get_pixel_multiplier(adjusted_mode); | |
5059 | if (temp > 1) | |
5060 | temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
5061 | else | |
5062 | temp = 0; | |
32f9d658 | 5063 | } |
c713bb08 EA |
5064 | I915_WRITE(DPLL_MD(pipe), temp); |
5065 | } else { | |
5066 | /* The pixel multiplier can only be updated once the | |
5067 | * DPLL is enabled and the clocks are stable. | |
5068 | * | |
5069 | * So write it again. | |
5070 | */ | |
fae14981 | 5071 | I915_WRITE(DPLL(pipe), dpll); |
79e53945 | 5072 | } |
79e53945 | 5073 | |
5eddb70b | 5074 | intel_crtc->lowfreq_avail = false; |
652c393a | 5075 | if (is_lvds && has_reduced_clock && i915_powersave) { |
fae14981 | 5076 | I915_WRITE(FP1(pipe), fp2); |
652c393a JB |
5077 | intel_crtc->lowfreq_avail = true; |
5078 | if (HAS_PIPE_CXSR(dev)) { | |
28c97730 | 5079 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); |
652c393a JB |
5080 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; |
5081 | } | |
5082 | } else { | |
fae14981 | 5083 | I915_WRITE(FP1(pipe), fp); |
652c393a | 5084 | if (HAS_PIPE_CXSR(dev)) { |
28c97730 | 5085 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); |
652c393a JB |
5086 | pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK; |
5087 | } | |
5088 | } | |
5089 | ||
734b4157 KH |
5090 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
5091 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; | |
5092 | /* the chip adds 2 halflines automatically */ | |
5093 | adjusted_mode->crtc_vdisplay -= 1; | |
5094 | adjusted_mode->crtc_vtotal -= 1; | |
5095 | adjusted_mode->crtc_vblank_start -= 1; | |
5096 | adjusted_mode->crtc_vblank_end -= 1; | |
5097 | adjusted_mode->crtc_vsync_end -= 1; | |
5098 | adjusted_mode->crtc_vsync_start -= 1; | |
5099 | } else | |
5100 | pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */ | |
5101 | ||
5eddb70b CW |
5102 | I915_WRITE(HTOTAL(pipe), |
5103 | (adjusted_mode->crtc_hdisplay - 1) | | |
79e53945 | 5104 | ((adjusted_mode->crtc_htotal - 1) << 16)); |
5eddb70b CW |
5105 | I915_WRITE(HBLANK(pipe), |
5106 | (adjusted_mode->crtc_hblank_start - 1) | | |
79e53945 | 5107 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); |
5eddb70b CW |
5108 | I915_WRITE(HSYNC(pipe), |
5109 | (adjusted_mode->crtc_hsync_start - 1) | | |
79e53945 | 5110 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); |
5eddb70b CW |
5111 | |
5112 | I915_WRITE(VTOTAL(pipe), | |
5113 | (adjusted_mode->crtc_vdisplay - 1) | | |
79e53945 | 5114 | ((adjusted_mode->crtc_vtotal - 1) << 16)); |
5eddb70b CW |
5115 | I915_WRITE(VBLANK(pipe), |
5116 | (adjusted_mode->crtc_vblank_start - 1) | | |
79e53945 | 5117 | ((adjusted_mode->crtc_vblank_end - 1) << 16)); |
5eddb70b CW |
5118 | I915_WRITE(VSYNC(pipe), |
5119 | (adjusted_mode->crtc_vsync_start - 1) | | |
79e53945 | 5120 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); |
5eddb70b CW |
5121 | |
5122 | /* pipesrc and dspsize control the size that is scaled from, | |
5123 | * which should always be the user's requested size. | |
79e53945 | 5124 | */ |
929c77fb EA |
5125 | I915_WRITE(DSPSIZE(plane), |
5126 | ((mode->vdisplay - 1) << 16) | | |
5127 | (mode->hdisplay - 1)); | |
5128 | I915_WRITE(DSPPOS(plane), 0); | |
5eddb70b CW |
5129 | I915_WRITE(PIPESRC(pipe), |
5130 | ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); | |
2c07245f | 5131 | |
f564048e EA |
5132 | I915_WRITE(PIPECONF(pipe), pipeconf); |
5133 | POSTING_READ(PIPECONF(pipe)); | |
929c77fb | 5134 | intel_enable_pipe(dev_priv, pipe, false); |
f564048e EA |
5135 | |
5136 | intel_wait_for_vblank(dev, pipe); | |
5137 | ||
f564048e EA |
5138 | I915_WRITE(DSPCNTR(plane), dspcntr); |
5139 | POSTING_READ(DSPCNTR(plane)); | |
284d9529 | 5140 | intel_enable_plane(dev_priv, plane, pipe); |
f564048e EA |
5141 | |
5142 | ret = intel_pipe_set_base(crtc, x, y, old_fb); | |
5143 | ||
5144 | intel_update_watermarks(dev); | |
5145 | ||
f564048e EA |
5146 | return ret; |
5147 | } | |
5148 | ||
9fb526db KP |
5149 | /* |
5150 | * Initialize reference clocks when the driver loads | |
5151 | */ | |
5152 | void ironlake_init_pch_refclk(struct drm_device *dev) | |
13d83a67 JB |
5153 | { |
5154 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5155 | struct drm_mode_config *mode_config = &dev->mode_config; | |
13d83a67 | 5156 | struct intel_encoder *encoder; |
13d83a67 JB |
5157 | u32 temp; |
5158 | bool has_lvds = false; | |
199e5d79 KP |
5159 | bool has_cpu_edp = false; |
5160 | bool has_pch_edp = false; | |
5161 | bool has_panel = false; | |
99eb6a01 KP |
5162 | bool has_ck505 = false; |
5163 | bool can_ssc = false; | |
13d83a67 JB |
5164 | |
5165 | /* We need to take the global config into account */ | |
199e5d79 KP |
5166 | list_for_each_entry(encoder, &mode_config->encoder_list, |
5167 | base.head) { | |
5168 | switch (encoder->type) { | |
5169 | case INTEL_OUTPUT_LVDS: | |
5170 | has_panel = true; | |
5171 | has_lvds = true; | |
5172 | break; | |
5173 | case INTEL_OUTPUT_EDP: | |
5174 | has_panel = true; | |
5175 | if (intel_encoder_is_pch_edp(&encoder->base)) | |
5176 | has_pch_edp = true; | |
5177 | else | |
5178 | has_cpu_edp = true; | |
5179 | break; | |
13d83a67 JB |
5180 | } |
5181 | } | |
5182 | ||
99eb6a01 KP |
5183 | if (HAS_PCH_IBX(dev)) { |
5184 | has_ck505 = dev_priv->display_clock_mode; | |
5185 | can_ssc = has_ck505; | |
5186 | } else { | |
5187 | has_ck505 = false; | |
5188 | can_ssc = true; | |
5189 | } | |
5190 | ||
5191 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n", | |
5192 | has_panel, has_lvds, has_pch_edp, has_cpu_edp, | |
5193 | has_ck505); | |
13d83a67 JB |
5194 | |
5195 | /* Ironlake: try to setup display ref clock before DPLL | |
5196 | * enabling. This is only under driver's control after | |
5197 | * PCH B stepping, previous chipset stepping should be | |
5198 | * ignoring this setting. | |
5199 | */ | |
5200 | temp = I915_READ(PCH_DREF_CONTROL); | |
5201 | /* Always enable nonspread source */ | |
5202 | temp &= ~DREF_NONSPREAD_SOURCE_MASK; | |
13d83a67 | 5203 | |
99eb6a01 KP |
5204 | if (has_ck505) |
5205 | temp |= DREF_NONSPREAD_CK505_ENABLE; | |
5206 | else | |
5207 | temp |= DREF_NONSPREAD_SOURCE_ENABLE; | |
13d83a67 | 5208 | |
199e5d79 KP |
5209 | if (has_panel) { |
5210 | temp &= ~DREF_SSC_SOURCE_MASK; | |
5211 | temp |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 5212 | |
199e5d79 | 5213 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 5214 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 5215 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
13d83a67 | 5216 | temp |= DREF_SSC1_ENABLE; |
13d83a67 | 5217 | } |
199e5d79 KP |
5218 | |
5219 | /* Get SSC going before enabling the outputs */ | |
5220 | I915_WRITE(PCH_DREF_CONTROL, temp); | |
5221 | POSTING_READ(PCH_DREF_CONTROL); | |
5222 | udelay(200); | |
5223 | ||
13d83a67 JB |
5224 | temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
5225 | ||
5226 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 5227 | if (has_cpu_edp) { |
99eb6a01 | 5228 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 5229 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
13d83a67 | 5230 | temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
199e5d79 | 5231 | } |
13d83a67 JB |
5232 | else |
5233 | temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
199e5d79 KP |
5234 | } else |
5235 | temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
5236 | ||
5237 | I915_WRITE(PCH_DREF_CONTROL, temp); | |
5238 | POSTING_READ(PCH_DREF_CONTROL); | |
5239 | udelay(200); | |
5240 | } else { | |
5241 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
5242 | ||
5243 | temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
5244 | ||
5245 | /* Turn off CPU output */ | |
5246 | temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
5247 | ||
5248 | I915_WRITE(PCH_DREF_CONTROL, temp); | |
5249 | POSTING_READ(PCH_DREF_CONTROL); | |
5250 | udelay(200); | |
5251 | ||
5252 | /* Turn off the SSC source */ | |
5253 | temp &= ~DREF_SSC_SOURCE_MASK; | |
5254 | temp |= DREF_SSC_SOURCE_DISABLE; | |
5255 | ||
5256 | /* Turn off SSC1 */ | |
5257 | temp &= ~ DREF_SSC1_ENABLE; | |
5258 | ||
13d83a67 JB |
5259 | I915_WRITE(PCH_DREF_CONTROL, temp); |
5260 | POSTING_READ(PCH_DREF_CONTROL); | |
5261 | udelay(200); | |
5262 | } | |
5263 | } | |
5264 | ||
d9d444cb JB |
5265 | static int ironlake_get_refclk(struct drm_crtc *crtc) |
5266 | { | |
5267 | struct drm_device *dev = crtc->dev; | |
5268 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5269 | struct intel_encoder *encoder; | |
5270 | struct drm_mode_config *mode_config = &dev->mode_config; | |
5271 | struct intel_encoder *edp_encoder = NULL; | |
5272 | int num_connectors = 0; | |
5273 | bool is_lvds = false; | |
5274 | ||
5275 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { | |
5276 | if (encoder->base.crtc != crtc) | |
5277 | continue; | |
5278 | ||
5279 | switch (encoder->type) { | |
5280 | case INTEL_OUTPUT_LVDS: | |
5281 | is_lvds = true; | |
5282 | break; | |
5283 | case INTEL_OUTPUT_EDP: | |
5284 | edp_encoder = encoder; | |
5285 | break; | |
5286 | } | |
5287 | num_connectors++; | |
5288 | } | |
5289 | ||
5290 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
5291 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", | |
5292 | dev_priv->lvds_ssc_freq); | |
5293 | return dev_priv->lvds_ssc_freq * 1000; | |
5294 | } | |
5295 | ||
5296 | return 120000; | |
5297 | } | |
5298 | ||
f564048e EA |
5299 | static int ironlake_crtc_mode_set(struct drm_crtc *crtc, |
5300 | struct drm_display_mode *mode, | |
5301 | struct drm_display_mode *adjusted_mode, | |
5302 | int x, int y, | |
5303 | struct drm_framebuffer *old_fb) | |
79e53945 JB |
5304 | { |
5305 | struct drm_device *dev = crtc->dev; | |
5306 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5307 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5308 | int pipe = intel_crtc->pipe; | |
80824003 | 5309 | int plane = intel_crtc->plane; |
c751ce4f | 5310 | int refclk, num_connectors = 0; |
652c393a | 5311 | intel_clock_t clock, reduced_clock; |
5eddb70b | 5312 | u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf; |
a07d6787 | 5313 | bool ok, has_reduced_clock = false, is_sdvo = false; |
a4fc5ed6 | 5314 | bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false; |
8e647a27 | 5315 | struct intel_encoder *has_edp_encoder = NULL; |
79e53945 | 5316 | struct drm_mode_config *mode_config = &dev->mode_config; |
5eddb70b | 5317 | struct intel_encoder *encoder; |
d4906093 | 5318 | const intel_limit_t *limit; |
5c3b82e2 | 5319 | int ret; |
2c07245f | 5320 | struct fdi_m_n m_n = {0}; |
fae14981 | 5321 | u32 temp; |
aa9b500d | 5322 | u32 lvds_sync = 0; |
5a354204 JB |
5323 | int target_clock, pixel_multiplier, lane, link_bw, factor; |
5324 | unsigned int pipe_bpp; | |
5325 | bool dither; | |
79e53945 | 5326 | |
5eddb70b CW |
5327 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { |
5328 | if (encoder->base.crtc != crtc) | |
79e53945 JB |
5329 | continue; |
5330 | ||
5eddb70b | 5331 | switch (encoder->type) { |
79e53945 JB |
5332 | case INTEL_OUTPUT_LVDS: |
5333 | is_lvds = true; | |
5334 | break; | |
5335 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 5336 | case INTEL_OUTPUT_HDMI: |
79e53945 | 5337 | is_sdvo = true; |
5eddb70b | 5338 | if (encoder->needs_tv_clock) |
e2f0ba97 | 5339 | is_tv = true; |
79e53945 | 5340 | break; |
79e53945 JB |
5341 | case INTEL_OUTPUT_TVOUT: |
5342 | is_tv = true; | |
5343 | break; | |
5344 | case INTEL_OUTPUT_ANALOG: | |
5345 | is_crt = true; | |
5346 | break; | |
a4fc5ed6 KP |
5347 | case INTEL_OUTPUT_DISPLAYPORT: |
5348 | is_dp = true; | |
5349 | break; | |
32f9d658 | 5350 | case INTEL_OUTPUT_EDP: |
5eddb70b | 5351 | has_edp_encoder = encoder; |
32f9d658 | 5352 | break; |
79e53945 | 5353 | } |
43565a06 | 5354 | |
c751ce4f | 5355 | num_connectors++; |
79e53945 JB |
5356 | } |
5357 | ||
d9d444cb | 5358 | refclk = ironlake_get_refclk(crtc); |
79e53945 | 5359 | |
d4906093 ML |
5360 | /* |
5361 | * Returns a set of divisors for the desired target clock with the given | |
5362 | * refclk, or FALSE. The returned values represent the clock equation: | |
5363 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
5364 | */ | |
1b894b59 | 5365 | limit = intel_limit(crtc, refclk); |
d4906093 | 5366 | ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock); |
79e53945 JB |
5367 | if (!ok) { |
5368 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
5c3b82e2 | 5369 | return -EINVAL; |
79e53945 JB |
5370 | } |
5371 | ||
cda4b7d3 | 5372 | /* Ensure that the cursor is valid for the new mode before changing... */ |
6b383a7f | 5373 | intel_crtc_update_cursor(crtc, true); |
cda4b7d3 | 5374 | |
ddc9003c ZY |
5375 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
5376 | has_reduced_clock = limit->find_pll(limit, crtc, | |
5eddb70b CW |
5377 | dev_priv->lvds_downclock, |
5378 | refclk, | |
5379 | &reduced_clock); | |
18f9ed12 ZY |
5380 | if (has_reduced_clock && (clock.p != reduced_clock.p)) { |
5381 | /* | |
5382 | * If the different P is found, it means that we can't | |
5383 | * switch the display clock by using the FP0/FP1. | |
5384 | * In such case we will disable the LVDS downclock | |
5385 | * feature. | |
5386 | */ | |
5387 | DRM_DEBUG_KMS("Different P is found for " | |
5eddb70b | 5388 | "LVDS clock/downclock\n"); |
18f9ed12 ZY |
5389 | has_reduced_clock = 0; |
5390 | } | |
652c393a | 5391 | } |
7026d4ac ZW |
5392 | /* SDVO TV has fixed PLL values depend on its clock range, |
5393 | this mirrors vbios setting. */ | |
5394 | if (is_sdvo && is_tv) { | |
5395 | if (adjusted_mode->clock >= 100000 | |
5eddb70b | 5396 | && adjusted_mode->clock < 140500) { |
7026d4ac ZW |
5397 | clock.p1 = 2; |
5398 | clock.p2 = 10; | |
5399 | clock.n = 3; | |
5400 | clock.m1 = 16; | |
5401 | clock.m2 = 8; | |
5402 | } else if (adjusted_mode->clock >= 140500 | |
5eddb70b | 5403 | && adjusted_mode->clock <= 200000) { |
7026d4ac ZW |
5404 | clock.p1 = 1; |
5405 | clock.p2 = 10; | |
5406 | clock.n = 6; | |
5407 | clock.m1 = 12; | |
5408 | clock.m2 = 8; | |
5409 | } | |
5410 | } | |
5411 | ||
2c07245f | 5412 | /* FDI link */ |
8febb297 EA |
5413 | pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); |
5414 | lane = 0; | |
5415 | /* CPU eDP doesn't require FDI link, so just set DP M/N | |
5416 | according to current link config */ | |
5417 | if (has_edp_encoder && | |
5418 | !intel_encoder_is_pch_edp(&has_edp_encoder->base)) { | |
5419 | target_clock = mode->clock; | |
5420 | intel_edp_link_config(has_edp_encoder, | |
5421 | &lane, &link_bw); | |
5422 | } else { | |
5423 | /* [e]DP over FDI requires target mode clock | |
5424 | instead of link clock */ | |
5425 | if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) | |
5eb08b69 | 5426 | target_clock = mode->clock; |
8febb297 EA |
5427 | else |
5428 | target_clock = adjusted_mode->clock; | |
5429 | ||
5430 | /* FDI is a binary signal running at ~2.7GHz, encoding | |
5431 | * each output octet as 10 bits. The actual frequency | |
5432 | * is stored as a divider into a 100MHz clock, and the | |
5433 | * mode pixel clock is stored in units of 1KHz. | |
5434 | * Hence the bw of each lane in terms of the mode signal | |
5435 | * is: | |
5436 | */ | |
5437 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
5438 | } | |
58a27471 | 5439 | |
8febb297 EA |
5440 | /* determine panel color depth */ |
5441 | temp = I915_READ(PIPECONF(pipe)); | |
5442 | temp &= ~PIPE_BPC_MASK; | |
5a354204 JB |
5443 | dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp); |
5444 | switch (pipe_bpp) { | |
5445 | case 18: | |
5446 | temp |= PIPE_6BPC; | |
8febb297 | 5447 | break; |
5a354204 JB |
5448 | case 24: |
5449 | temp |= PIPE_8BPC; | |
8febb297 | 5450 | break; |
5a354204 JB |
5451 | case 30: |
5452 | temp |= PIPE_10BPC; | |
8febb297 | 5453 | break; |
5a354204 JB |
5454 | case 36: |
5455 | temp |= PIPE_12BPC; | |
8febb297 EA |
5456 | break; |
5457 | default: | |
62ac41a6 JB |
5458 | WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n", |
5459 | pipe_bpp); | |
5a354204 JB |
5460 | temp |= PIPE_8BPC; |
5461 | pipe_bpp = 24; | |
5462 | break; | |
8febb297 | 5463 | } |
77ffb597 | 5464 | |
5a354204 JB |
5465 | intel_crtc->bpp = pipe_bpp; |
5466 | I915_WRITE(PIPECONF(pipe), temp); | |
5467 | ||
8febb297 EA |
5468 | if (!lane) { |
5469 | /* | |
5470 | * Account for spread spectrum to avoid | |
5471 | * oversubscribing the link. Max center spread | |
5472 | * is 2.5%; use 5% for safety's sake. | |
5473 | */ | |
5a354204 | 5474 | u32 bps = target_clock * intel_crtc->bpp * 21 / 20; |
8febb297 | 5475 | lane = bps / (link_bw * 8) + 1; |
5eb08b69 | 5476 | } |
2c07245f | 5477 | |
8febb297 EA |
5478 | intel_crtc->fdi_lanes = lane; |
5479 | ||
5480 | if (pixel_multiplier > 1) | |
5481 | link_bw *= pixel_multiplier; | |
5a354204 JB |
5482 | ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw, |
5483 | &m_n); | |
8febb297 | 5484 | |
a07d6787 EA |
5485 | fp = clock.n << 16 | clock.m1 << 8 | clock.m2; |
5486 | if (has_reduced_clock) | |
5487 | fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 | | |
5488 | reduced_clock.m2; | |
79e53945 | 5489 | |
c1858123 | 5490 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
5491 | factor = 21; |
5492 | if (is_lvds) { | |
5493 | if ((intel_panel_use_ssc(dev_priv) && | |
5494 | dev_priv->lvds_ssc_freq == 100) || | |
5495 | (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP) | |
5496 | factor = 25; | |
5497 | } else if (is_sdvo && is_tv) | |
5498 | factor = 20; | |
c1858123 | 5499 | |
cb0e0931 | 5500 | if (clock.m < factor * clock.n) |
8febb297 | 5501 | fp |= FP_CB_TUNE; |
2c07245f | 5502 | |
5eddb70b | 5503 | dpll = 0; |
2c07245f | 5504 | |
a07d6787 EA |
5505 | if (is_lvds) |
5506 | dpll |= DPLLB_MODE_LVDS; | |
5507 | else | |
5508 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
5509 | if (is_sdvo) { | |
5510 | int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); | |
5511 | if (pixel_multiplier > 1) { | |
5512 | dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; | |
79e53945 | 5513 | } |
a07d6787 EA |
5514 | dpll |= DPLL_DVO_HIGH_SPEED; |
5515 | } | |
5516 | if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) | |
5517 | dpll |= DPLL_DVO_HIGH_SPEED; | |
79e53945 | 5518 | |
a07d6787 EA |
5519 | /* compute bitmask from p1 value */ |
5520 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
5521 | /* also FPA1 */ | |
5522 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
5523 | ||
5524 | switch (clock.p2) { | |
5525 | case 5: | |
5526 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
5527 | break; | |
5528 | case 7: | |
5529 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
5530 | break; | |
5531 | case 10: | |
5532 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
5533 | break; | |
5534 | case 14: | |
5535 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
5536 | break; | |
79e53945 JB |
5537 | } |
5538 | ||
43565a06 KH |
5539 | if (is_sdvo && is_tv) |
5540 | dpll |= PLL_REF_INPUT_TVCLKINBC; | |
5541 | else if (is_tv) | |
79e53945 | 5542 | /* XXX: just matching BIOS for now */ |
43565a06 | 5543 | /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ |
79e53945 | 5544 | dpll |= 3; |
a7615030 | 5545 | else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 5546 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
5547 | else |
5548 | dpll |= PLL_REF_INPUT_DREFCLK; | |
5549 | ||
5550 | /* setup pipeconf */ | |
5eddb70b | 5551 | pipeconf = I915_READ(PIPECONF(pipe)); |
79e53945 JB |
5552 | |
5553 | /* Set up the display plane register */ | |
5554 | dspcntr = DISPPLANE_GAMMA_ENABLE; | |
5555 | ||
f7cb34d4 | 5556 | DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe); |
79e53945 JB |
5557 | drm_mode_debug_printmodeline(mode); |
5558 | ||
5c5313c8 | 5559 | /* PCH eDP needs FDI, but CPU eDP does not */ |
4b645f14 JB |
5560 | if (!intel_crtc->no_pll) { |
5561 | if (!has_edp_encoder || | |
5562 | intel_encoder_is_pch_edp(&has_edp_encoder->base)) { | |
5563 | I915_WRITE(PCH_FP0(pipe), fp); | |
5564 | I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE); | |
5565 | ||
5566 | POSTING_READ(PCH_DPLL(pipe)); | |
5567 | udelay(150); | |
5568 | } | |
5569 | } else { | |
5570 | if (dpll == (I915_READ(PCH_DPLL(0)) & 0x7fffffff) && | |
5571 | fp == I915_READ(PCH_FP0(0))) { | |
5572 | intel_crtc->use_pll_a = true; | |
5573 | DRM_DEBUG_KMS("using pipe a dpll\n"); | |
5574 | } else if (dpll == (I915_READ(PCH_DPLL(1)) & 0x7fffffff) && | |
5575 | fp == I915_READ(PCH_FP0(1))) { | |
5576 | intel_crtc->use_pll_a = false; | |
5577 | DRM_DEBUG_KMS("using pipe b dpll\n"); | |
5578 | } else { | |
5579 | DRM_DEBUG_KMS("no matching PLL configuration for pipe 2\n"); | |
5580 | return -EINVAL; | |
5581 | } | |
79e53945 JB |
5582 | } |
5583 | ||
8db9d77b ZW |
5584 | /* enable transcoder DPLL */ |
5585 | if (HAS_PCH_CPT(dev)) { | |
4b645f14 JB |
5586 | u32 transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL : |
5587 | TRANSC_DPLLB_SEL; | |
8db9d77b | 5588 | temp = I915_READ(PCH_DPLL_SEL); |
9db4a9c7 JB |
5589 | switch (pipe) { |
5590 | case 0: | |
5eddb70b | 5591 | temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL; |
9db4a9c7 JB |
5592 | break; |
5593 | case 1: | |
5eddb70b | 5594 | temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL; |
9db4a9c7 JB |
5595 | break; |
5596 | case 2: | |
d64311ab | 5597 | temp &= ~(TRANSC_DPLLB_SEL); |
4b645f14 | 5598 | temp |= TRANSC_DPLL_ENABLE | transc_sel; |
9db4a9c7 JB |
5599 | break; |
5600 | default: | |
5601 | BUG(); | |
32f9d658 | 5602 | } |
8db9d77b | 5603 | I915_WRITE(PCH_DPLL_SEL, temp); |
5eddb70b CW |
5604 | |
5605 | POSTING_READ(PCH_DPLL_SEL); | |
8db9d77b ZW |
5606 | udelay(150); |
5607 | } | |
5608 | ||
79e53945 JB |
5609 | /* The LVDS pin pair needs to be on before the DPLLs are enabled. |
5610 | * This is an exception to the general rule that mode_set doesn't turn | |
5611 | * things on. | |
5612 | */ | |
5613 | if (is_lvds) { | |
fae14981 | 5614 | temp = I915_READ(PCH_LVDS); |
5eddb70b | 5615 | temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; |
4b645f14 JB |
5616 | if (HAS_PCH_CPT(dev)) |
5617 | temp |= PORT_TRANS_SEL_CPT(pipe); | |
5618 | else if (pipe == 1) | |
5619 | temp |= LVDS_PIPEB_SELECT; | |
5620 | else | |
5621 | temp &= ~LVDS_PIPEB_SELECT; | |
5622 | ||
a3e17eb8 | 5623 | /* set the corresponsding LVDS_BORDER bit */ |
5eddb70b | 5624 | temp |= dev_priv->lvds_border_bits; |
79e53945 JB |
5625 | /* Set the B0-B3 data pairs corresponding to whether we're going to |
5626 | * set the DPLLs for dual-channel mode or not. | |
5627 | */ | |
5628 | if (clock.p2 == 7) | |
5eddb70b | 5629 | temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; |
79e53945 | 5630 | else |
5eddb70b | 5631 | temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); |
79e53945 JB |
5632 | |
5633 | /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) | |
5634 | * appropriately here, but we need to look more thoroughly into how | |
5635 | * panels behave in the two modes. | |
5636 | */ | |
aa9b500d BF |
5637 | if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) |
5638 | lvds_sync |= LVDS_HSYNC_POLARITY; | |
5639 | if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) | |
5640 | lvds_sync |= LVDS_VSYNC_POLARITY; | |
5641 | if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY)) | |
5642 | != lvds_sync) { | |
5643 | char flags[2] = "-+"; | |
5644 | DRM_INFO("Changing LVDS panel from " | |
5645 | "(%chsync, %cvsync) to (%chsync, %cvsync)\n", | |
5646 | flags[!(temp & LVDS_HSYNC_POLARITY)], | |
5647 | flags[!(temp & LVDS_VSYNC_POLARITY)], | |
5648 | flags[!(lvds_sync & LVDS_HSYNC_POLARITY)], | |
5649 | flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]); | |
5650 | temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); | |
5651 | temp |= lvds_sync; | |
5652 | } | |
fae14981 | 5653 | I915_WRITE(PCH_LVDS, temp); |
79e53945 | 5654 | } |
434ed097 | 5655 | |
8febb297 EA |
5656 | pipeconf &= ~PIPECONF_DITHER_EN; |
5657 | pipeconf &= ~PIPECONF_DITHER_TYPE_MASK; | |
5a354204 | 5658 | if ((is_lvds && dev_priv->lvds_dither) || dither) { |
8febb297 EA |
5659 | pipeconf |= PIPECONF_DITHER_EN; |
5660 | pipeconf |= PIPECONF_DITHER_TYPE_ST1; | |
434ed097 | 5661 | } |
5c5313c8 | 5662 | if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) { |
a4fc5ed6 | 5663 | intel_dp_set_m_n(crtc, mode, adjusted_mode); |
8febb297 | 5664 | } else { |
8db9d77b | 5665 | /* For non-DP output, clear any trans DP clock recovery setting.*/ |
9db4a9c7 JB |
5666 | I915_WRITE(TRANSDATA_M1(pipe), 0); |
5667 | I915_WRITE(TRANSDATA_N1(pipe), 0); | |
5668 | I915_WRITE(TRANSDPLINK_M1(pipe), 0); | |
5669 | I915_WRITE(TRANSDPLINK_N1(pipe), 0); | |
8db9d77b | 5670 | } |
79e53945 | 5671 | |
4b645f14 JB |
5672 | if (!intel_crtc->no_pll && |
5673 | (!has_edp_encoder || | |
5674 | intel_encoder_is_pch_edp(&has_edp_encoder->base))) { | |
fae14981 | 5675 | I915_WRITE(PCH_DPLL(pipe), dpll); |
5eddb70b | 5676 | |
32f9d658 | 5677 | /* Wait for the clocks to stabilize. */ |
fae14981 | 5678 | POSTING_READ(PCH_DPLL(pipe)); |
32f9d658 ZW |
5679 | udelay(150); |
5680 | ||
8febb297 EA |
5681 | /* The pixel multiplier can only be updated once the |
5682 | * DPLL is enabled and the clocks are stable. | |
5683 | * | |
5684 | * So write it again. | |
5685 | */ | |
fae14981 | 5686 | I915_WRITE(PCH_DPLL(pipe), dpll); |
79e53945 | 5687 | } |
79e53945 | 5688 | |
5eddb70b | 5689 | intel_crtc->lowfreq_avail = false; |
4b645f14 JB |
5690 | if (!intel_crtc->no_pll) { |
5691 | if (is_lvds && has_reduced_clock && i915_powersave) { | |
5692 | I915_WRITE(PCH_FP1(pipe), fp2); | |
5693 | intel_crtc->lowfreq_avail = true; | |
5694 | if (HAS_PIPE_CXSR(dev)) { | |
5695 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
5696 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
5697 | } | |
5698 | } else { | |
5699 | I915_WRITE(PCH_FP1(pipe), fp); | |
5700 | if (HAS_PIPE_CXSR(dev)) { | |
5701 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
5702 | pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK; | |
5703 | } | |
652c393a JB |
5704 | } |
5705 | } | |
5706 | ||
734b4157 KH |
5707 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
5708 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; | |
5709 | /* the chip adds 2 halflines automatically */ | |
5710 | adjusted_mode->crtc_vdisplay -= 1; | |
5711 | adjusted_mode->crtc_vtotal -= 1; | |
5712 | adjusted_mode->crtc_vblank_start -= 1; | |
5713 | adjusted_mode->crtc_vblank_end -= 1; | |
5714 | adjusted_mode->crtc_vsync_end -= 1; | |
5715 | adjusted_mode->crtc_vsync_start -= 1; | |
5716 | } else | |
5717 | pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */ | |
5718 | ||
5eddb70b CW |
5719 | I915_WRITE(HTOTAL(pipe), |
5720 | (adjusted_mode->crtc_hdisplay - 1) | | |
79e53945 | 5721 | ((adjusted_mode->crtc_htotal - 1) << 16)); |
5eddb70b CW |
5722 | I915_WRITE(HBLANK(pipe), |
5723 | (adjusted_mode->crtc_hblank_start - 1) | | |
79e53945 | 5724 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); |
5eddb70b CW |
5725 | I915_WRITE(HSYNC(pipe), |
5726 | (adjusted_mode->crtc_hsync_start - 1) | | |
79e53945 | 5727 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); |
5eddb70b CW |
5728 | |
5729 | I915_WRITE(VTOTAL(pipe), | |
5730 | (adjusted_mode->crtc_vdisplay - 1) | | |
79e53945 | 5731 | ((adjusted_mode->crtc_vtotal - 1) << 16)); |
5eddb70b CW |
5732 | I915_WRITE(VBLANK(pipe), |
5733 | (adjusted_mode->crtc_vblank_start - 1) | | |
79e53945 | 5734 | ((adjusted_mode->crtc_vblank_end - 1) << 16)); |
5eddb70b CW |
5735 | I915_WRITE(VSYNC(pipe), |
5736 | (adjusted_mode->crtc_vsync_start - 1) | | |
79e53945 | 5737 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); |
5eddb70b | 5738 | |
8febb297 EA |
5739 | /* pipesrc controls the size that is scaled from, which should |
5740 | * always be the user's requested size. | |
79e53945 | 5741 | */ |
5eddb70b CW |
5742 | I915_WRITE(PIPESRC(pipe), |
5743 | ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); | |
2c07245f | 5744 | |
8febb297 EA |
5745 | I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m); |
5746 | I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n); | |
5747 | I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m); | |
5748 | I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n); | |
2c07245f | 5749 | |
8febb297 EA |
5750 | if (has_edp_encoder && |
5751 | !intel_encoder_is_pch_edp(&has_edp_encoder->base)) { | |
5752 | ironlake_set_pll_edp(crtc, adjusted_mode->clock); | |
2c07245f ZW |
5753 | } |
5754 | ||
5eddb70b CW |
5755 | I915_WRITE(PIPECONF(pipe), pipeconf); |
5756 | POSTING_READ(PIPECONF(pipe)); | |
79e53945 | 5757 | |
9d0498a2 | 5758 | intel_wait_for_vblank(dev, pipe); |
79e53945 | 5759 | |
f00a3ddf | 5760 | if (IS_GEN5(dev)) { |
553bd149 ZW |
5761 | /* enable address swizzle for tiling buffer */ |
5762 | temp = I915_READ(DISP_ARB_CTL); | |
5763 | I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING); | |
5764 | } | |
5765 | ||
5eddb70b | 5766 | I915_WRITE(DSPCNTR(plane), dspcntr); |
b24e7179 | 5767 | POSTING_READ(DSPCNTR(plane)); |
79e53945 | 5768 | |
5c3b82e2 | 5769 | ret = intel_pipe_set_base(crtc, x, y, old_fb); |
7662c8bd SL |
5770 | |
5771 | intel_update_watermarks(dev); | |
5772 | ||
1f803ee5 | 5773 | return ret; |
79e53945 JB |
5774 | } |
5775 | ||
f564048e EA |
5776 | static int intel_crtc_mode_set(struct drm_crtc *crtc, |
5777 | struct drm_display_mode *mode, | |
5778 | struct drm_display_mode *adjusted_mode, | |
5779 | int x, int y, | |
5780 | struct drm_framebuffer *old_fb) | |
5781 | { | |
5782 | struct drm_device *dev = crtc->dev; | |
5783 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0b701d27 EA |
5784 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5785 | int pipe = intel_crtc->pipe; | |
f564048e EA |
5786 | int ret; |
5787 | ||
0b701d27 | 5788 | drm_vblank_pre_modeset(dev, pipe); |
7662c8bd | 5789 | |
f564048e EA |
5790 | ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode, |
5791 | x, y, old_fb); | |
7662c8bd | 5792 | |
79e53945 | 5793 | drm_vblank_post_modeset(dev, pipe); |
5c3b82e2 | 5794 | |
120eced9 KP |
5795 | intel_crtc->dpms_mode = DRM_MODE_DPMS_ON; |
5796 | ||
1f803ee5 | 5797 | return ret; |
79e53945 JB |
5798 | } |
5799 | ||
e0dac65e WF |
5800 | static void g4x_write_eld(struct drm_connector *connector, |
5801 | struct drm_crtc *crtc) | |
5802 | { | |
5803 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
5804 | uint8_t *eld = connector->eld; | |
5805 | uint32_t eldv; | |
5806 | uint32_t len; | |
5807 | uint32_t i; | |
5808 | ||
5809 | i = I915_READ(G4X_AUD_VID_DID); | |
5810 | ||
5811 | if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL) | |
5812 | eldv = G4X_ELDV_DEVCL_DEVBLC; | |
5813 | else | |
5814 | eldv = G4X_ELDV_DEVCTG; | |
5815 | ||
5816 | i = I915_READ(G4X_AUD_CNTL_ST); | |
5817 | i &= ~(eldv | G4X_ELD_ADDR); | |
5818 | len = (i >> 9) & 0x1f; /* ELD buffer size */ | |
5819 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
5820 | ||
5821 | if (!eld[0]) | |
5822 | return; | |
5823 | ||
5824 | len = min_t(uint8_t, eld[2], len); | |
5825 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
5826 | for (i = 0; i < len; i++) | |
5827 | I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); | |
5828 | ||
5829 | i = I915_READ(G4X_AUD_CNTL_ST); | |
5830 | i |= eldv; | |
5831 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
5832 | } | |
5833 | ||
5834 | static void ironlake_write_eld(struct drm_connector *connector, | |
5835 | struct drm_crtc *crtc) | |
5836 | { | |
5837 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
5838 | uint8_t *eld = connector->eld; | |
5839 | uint32_t eldv; | |
5840 | uint32_t i; | |
5841 | int len; | |
5842 | int hdmiw_hdmiedid; | |
5843 | int aud_cntl_st; | |
5844 | int aud_cntrl_st2; | |
5845 | ||
5846 | if (IS_IVYBRIDGE(connector->dev)) { | |
5847 | hdmiw_hdmiedid = GEN7_HDMIW_HDMIEDID_A; | |
5848 | aud_cntl_st = GEN7_AUD_CNTRL_ST_A; | |
5849 | aud_cntrl_st2 = GEN7_AUD_CNTRL_ST2; | |
5850 | } else { | |
5851 | hdmiw_hdmiedid = GEN5_HDMIW_HDMIEDID_A; | |
5852 | aud_cntl_st = GEN5_AUD_CNTL_ST_A; | |
5853 | aud_cntrl_st2 = GEN5_AUD_CNTL_ST2; | |
5854 | } | |
5855 | ||
5856 | i = to_intel_crtc(crtc)->pipe; | |
5857 | hdmiw_hdmiedid += i * 0x100; | |
5858 | aud_cntl_st += i * 0x100; | |
5859 | ||
5860 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i)); | |
5861 | ||
5862 | i = I915_READ(aud_cntl_st); | |
5863 | i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */ | |
5864 | if (!i) { | |
5865 | DRM_DEBUG_DRIVER("Audio directed to unknown port\n"); | |
5866 | /* operate blindly on all ports */ | |
5867 | eldv = GEN5_ELD_VALIDB; | |
5868 | eldv |= GEN5_ELD_VALIDB << 4; | |
5869 | eldv |= GEN5_ELD_VALIDB << 8; | |
5870 | } else { | |
5871 | DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i); | |
5872 | eldv = GEN5_ELD_VALIDB << ((i - 1) * 4); | |
5873 | } | |
5874 | ||
5875 | i = I915_READ(aud_cntrl_st2); | |
5876 | i &= ~eldv; | |
5877 | I915_WRITE(aud_cntrl_st2, i); | |
5878 | ||
5879 | if (!eld[0]) | |
5880 | return; | |
5881 | ||
5882 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { | |
5883 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); | |
5884 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ | |
5885 | } | |
5886 | ||
5887 | i = I915_READ(aud_cntl_st); | |
5888 | i &= ~GEN5_ELD_ADDRESS; | |
5889 | I915_WRITE(aud_cntl_st, i); | |
5890 | ||
5891 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ | |
5892 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
5893 | for (i = 0; i < len; i++) | |
5894 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); | |
5895 | ||
5896 | i = I915_READ(aud_cntrl_st2); | |
5897 | i |= eldv; | |
5898 | I915_WRITE(aud_cntrl_st2, i); | |
5899 | } | |
5900 | ||
5901 | void intel_write_eld(struct drm_encoder *encoder, | |
5902 | struct drm_display_mode *mode) | |
5903 | { | |
5904 | struct drm_crtc *crtc = encoder->crtc; | |
5905 | struct drm_connector *connector; | |
5906 | struct drm_device *dev = encoder->dev; | |
5907 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5908 | ||
5909 | connector = drm_select_eld(encoder, mode); | |
5910 | if (!connector) | |
5911 | return; | |
5912 | ||
5913 | DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", | |
5914 | connector->base.id, | |
5915 | drm_get_connector_name(connector), | |
5916 | connector->encoder->base.id, | |
5917 | drm_get_encoder_name(connector->encoder)); | |
5918 | ||
5919 | connector->eld[6] = drm_av_sync_delay(connector, mode) / 2; | |
5920 | ||
5921 | if (dev_priv->display.write_eld) | |
5922 | dev_priv->display.write_eld(connector, crtc); | |
5923 | } | |
5924 | ||
79e53945 JB |
5925 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ |
5926 | void intel_crtc_load_lut(struct drm_crtc *crtc) | |
5927 | { | |
5928 | struct drm_device *dev = crtc->dev; | |
5929 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5930 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9db4a9c7 | 5931 | int palreg = PALETTE(intel_crtc->pipe); |
79e53945 JB |
5932 | int i; |
5933 | ||
5934 | /* The clocks have to be on to load the palette. */ | |
5935 | if (!crtc->enabled) | |
5936 | return; | |
5937 | ||
f2b115e6 | 5938 | /* use legacy palette for Ironlake */ |
bad720ff | 5939 | if (HAS_PCH_SPLIT(dev)) |
9db4a9c7 | 5940 | palreg = LGC_PALETTE(intel_crtc->pipe); |
2c07245f | 5941 | |
79e53945 JB |
5942 | for (i = 0; i < 256; i++) { |
5943 | I915_WRITE(palreg + 4 * i, | |
5944 | (intel_crtc->lut_r[i] << 16) | | |
5945 | (intel_crtc->lut_g[i] << 8) | | |
5946 | intel_crtc->lut_b[i]); | |
5947 | } | |
5948 | } | |
5949 | ||
560b85bb CW |
5950 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
5951 | { | |
5952 | struct drm_device *dev = crtc->dev; | |
5953 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5954 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5955 | bool visible = base != 0; | |
5956 | u32 cntl; | |
5957 | ||
5958 | if (intel_crtc->cursor_visible == visible) | |
5959 | return; | |
5960 | ||
9db4a9c7 | 5961 | cntl = I915_READ(_CURACNTR); |
560b85bb CW |
5962 | if (visible) { |
5963 | /* On these chipsets we can only modify the base whilst | |
5964 | * the cursor is disabled. | |
5965 | */ | |
9db4a9c7 | 5966 | I915_WRITE(_CURABASE, base); |
560b85bb CW |
5967 | |
5968 | cntl &= ~(CURSOR_FORMAT_MASK); | |
5969 | /* XXX width must be 64, stride 256 => 0x00 << 28 */ | |
5970 | cntl |= CURSOR_ENABLE | | |
5971 | CURSOR_GAMMA_ENABLE | | |
5972 | CURSOR_FORMAT_ARGB; | |
5973 | } else | |
5974 | cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE); | |
9db4a9c7 | 5975 | I915_WRITE(_CURACNTR, cntl); |
560b85bb CW |
5976 | |
5977 | intel_crtc->cursor_visible = visible; | |
5978 | } | |
5979 | ||
5980 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) | |
5981 | { | |
5982 | struct drm_device *dev = crtc->dev; | |
5983 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5984 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5985 | int pipe = intel_crtc->pipe; | |
5986 | bool visible = base != 0; | |
5987 | ||
5988 | if (intel_crtc->cursor_visible != visible) { | |
548f245b | 5989 | uint32_t cntl = I915_READ(CURCNTR(pipe)); |
560b85bb CW |
5990 | if (base) { |
5991 | cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT); | |
5992 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; | |
5993 | cntl |= pipe << 28; /* Connect to correct pipe */ | |
5994 | } else { | |
5995 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); | |
5996 | cntl |= CURSOR_MODE_DISABLE; | |
5997 | } | |
9db4a9c7 | 5998 | I915_WRITE(CURCNTR(pipe), cntl); |
560b85bb CW |
5999 | |
6000 | intel_crtc->cursor_visible = visible; | |
6001 | } | |
6002 | /* and commit changes on next vblank */ | |
9db4a9c7 | 6003 | I915_WRITE(CURBASE(pipe), base); |
560b85bb CW |
6004 | } |
6005 | ||
65a21cd6 JB |
6006 | static void ivb_update_cursor(struct drm_crtc *crtc, u32 base) |
6007 | { | |
6008 | struct drm_device *dev = crtc->dev; | |
6009 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6010 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6011 | int pipe = intel_crtc->pipe; | |
6012 | bool visible = base != 0; | |
6013 | ||
6014 | if (intel_crtc->cursor_visible != visible) { | |
6015 | uint32_t cntl = I915_READ(CURCNTR_IVB(pipe)); | |
6016 | if (base) { | |
6017 | cntl &= ~CURSOR_MODE; | |
6018 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; | |
6019 | } else { | |
6020 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); | |
6021 | cntl |= CURSOR_MODE_DISABLE; | |
6022 | } | |
6023 | I915_WRITE(CURCNTR_IVB(pipe), cntl); | |
6024 | ||
6025 | intel_crtc->cursor_visible = visible; | |
6026 | } | |
6027 | /* and commit changes on next vblank */ | |
6028 | I915_WRITE(CURBASE_IVB(pipe), base); | |
6029 | } | |
6030 | ||
cda4b7d3 | 6031 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f CW |
6032 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
6033 | bool on) | |
cda4b7d3 CW |
6034 | { |
6035 | struct drm_device *dev = crtc->dev; | |
6036 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6037 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6038 | int pipe = intel_crtc->pipe; | |
6039 | int x = intel_crtc->cursor_x; | |
6040 | int y = intel_crtc->cursor_y; | |
560b85bb | 6041 | u32 base, pos; |
cda4b7d3 CW |
6042 | bool visible; |
6043 | ||
6044 | pos = 0; | |
6045 | ||
6b383a7f | 6046 | if (on && crtc->enabled && crtc->fb) { |
cda4b7d3 CW |
6047 | base = intel_crtc->cursor_addr; |
6048 | if (x > (int) crtc->fb->width) | |
6049 | base = 0; | |
6050 | ||
6051 | if (y > (int) crtc->fb->height) | |
6052 | base = 0; | |
6053 | } else | |
6054 | base = 0; | |
6055 | ||
6056 | if (x < 0) { | |
6057 | if (x + intel_crtc->cursor_width < 0) | |
6058 | base = 0; | |
6059 | ||
6060 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
6061 | x = -x; | |
6062 | } | |
6063 | pos |= x << CURSOR_X_SHIFT; | |
6064 | ||
6065 | if (y < 0) { | |
6066 | if (y + intel_crtc->cursor_height < 0) | |
6067 | base = 0; | |
6068 | ||
6069 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
6070 | y = -y; | |
6071 | } | |
6072 | pos |= y << CURSOR_Y_SHIFT; | |
6073 | ||
6074 | visible = base != 0; | |
560b85bb | 6075 | if (!visible && !intel_crtc->cursor_visible) |
cda4b7d3 CW |
6076 | return; |
6077 | ||
65a21cd6 JB |
6078 | if (IS_IVYBRIDGE(dev)) { |
6079 | I915_WRITE(CURPOS_IVB(pipe), pos); | |
6080 | ivb_update_cursor(crtc, base); | |
6081 | } else { | |
6082 | I915_WRITE(CURPOS(pipe), pos); | |
6083 | if (IS_845G(dev) || IS_I865G(dev)) | |
6084 | i845_update_cursor(crtc, base); | |
6085 | else | |
6086 | i9xx_update_cursor(crtc, base); | |
6087 | } | |
cda4b7d3 CW |
6088 | |
6089 | if (visible) | |
6090 | intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj); | |
6091 | } | |
6092 | ||
79e53945 | 6093 | static int intel_crtc_cursor_set(struct drm_crtc *crtc, |
05394f39 | 6094 | struct drm_file *file, |
79e53945 JB |
6095 | uint32_t handle, |
6096 | uint32_t width, uint32_t height) | |
6097 | { | |
6098 | struct drm_device *dev = crtc->dev; | |
6099 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6100 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
05394f39 | 6101 | struct drm_i915_gem_object *obj; |
cda4b7d3 | 6102 | uint32_t addr; |
3f8bc370 | 6103 | int ret; |
79e53945 | 6104 | |
28c97730 | 6105 | DRM_DEBUG_KMS("\n"); |
79e53945 JB |
6106 | |
6107 | /* if we want to turn off the cursor ignore width and height */ | |
6108 | if (!handle) { | |
28c97730 | 6109 | DRM_DEBUG_KMS("cursor off\n"); |
3f8bc370 | 6110 | addr = 0; |
05394f39 | 6111 | obj = NULL; |
5004417d | 6112 | mutex_lock(&dev->struct_mutex); |
3f8bc370 | 6113 | goto finish; |
79e53945 JB |
6114 | } |
6115 | ||
6116 | /* Currently we only support 64x64 cursors */ | |
6117 | if (width != 64 || height != 64) { | |
6118 | DRM_ERROR("we currently only support 64x64 cursors\n"); | |
6119 | return -EINVAL; | |
6120 | } | |
6121 | ||
05394f39 | 6122 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 6123 | if (&obj->base == NULL) |
79e53945 JB |
6124 | return -ENOENT; |
6125 | ||
05394f39 | 6126 | if (obj->base.size < width * height * 4) { |
79e53945 | 6127 | DRM_ERROR("buffer is to small\n"); |
34b8686e DA |
6128 | ret = -ENOMEM; |
6129 | goto fail; | |
79e53945 JB |
6130 | } |
6131 | ||
71acb5eb | 6132 | /* we only need to pin inside GTT if cursor is non-phy */ |
7f9872e0 | 6133 | mutex_lock(&dev->struct_mutex); |
b295d1b6 | 6134 | if (!dev_priv->info->cursor_needs_physical) { |
d9e86c0e CW |
6135 | if (obj->tiling_mode) { |
6136 | DRM_ERROR("cursor cannot be tiled\n"); | |
6137 | ret = -EINVAL; | |
6138 | goto fail_locked; | |
6139 | } | |
6140 | ||
2da3b9b9 | 6141 | ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL); |
e7b526bb CW |
6142 | if (ret) { |
6143 | DRM_ERROR("failed to move cursor bo into the GTT\n"); | |
2da3b9b9 | 6144 | goto fail_locked; |
e7b526bb CW |
6145 | } |
6146 | ||
d9e86c0e CW |
6147 | ret = i915_gem_object_put_fence(obj); |
6148 | if (ret) { | |
2da3b9b9 | 6149 | DRM_ERROR("failed to release fence for cursor"); |
d9e86c0e CW |
6150 | goto fail_unpin; |
6151 | } | |
6152 | ||
05394f39 | 6153 | addr = obj->gtt_offset; |
71acb5eb | 6154 | } else { |
6eeefaf3 | 6155 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
05394f39 | 6156 | ret = i915_gem_attach_phys_object(dev, obj, |
6eeefaf3 CW |
6157 | (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1, |
6158 | align); | |
71acb5eb DA |
6159 | if (ret) { |
6160 | DRM_ERROR("failed to attach phys object\n"); | |
7f9872e0 | 6161 | goto fail_locked; |
71acb5eb | 6162 | } |
05394f39 | 6163 | addr = obj->phys_obj->handle->busaddr; |
3f8bc370 KH |
6164 | } |
6165 | ||
a6c45cf0 | 6166 | if (IS_GEN2(dev)) |
14b60391 JB |
6167 | I915_WRITE(CURSIZE, (height << 12) | width); |
6168 | ||
3f8bc370 | 6169 | finish: |
3f8bc370 | 6170 | if (intel_crtc->cursor_bo) { |
b295d1b6 | 6171 | if (dev_priv->info->cursor_needs_physical) { |
05394f39 | 6172 | if (intel_crtc->cursor_bo != obj) |
71acb5eb DA |
6173 | i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo); |
6174 | } else | |
6175 | i915_gem_object_unpin(intel_crtc->cursor_bo); | |
05394f39 | 6176 | drm_gem_object_unreference(&intel_crtc->cursor_bo->base); |
3f8bc370 | 6177 | } |
80824003 | 6178 | |
7f9872e0 | 6179 | mutex_unlock(&dev->struct_mutex); |
3f8bc370 KH |
6180 | |
6181 | intel_crtc->cursor_addr = addr; | |
05394f39 | 6182 | intel_crtc->cursor_bo = obj; |
cda4b7d3 CW |
6183 | intel_crtc->cursor_width = width; |
6184 | intel_crtc->cursor_height = height; | |
6185 | ||
6b383a7f | 6186 | intel_crtc_update_cursor(crtc, true); |
3f8bc370 | 6187 | |
79e53945 | 6188 | return 0; |
e7b526bb | 6189 | fail_unpin: |
05394f39 | 6190 | i915_gem_object_unpin(obj); |
7f9872e0 | 6191 | fail_locked: |
34b8686e | 6192 | mutex_unlock(&dev->struct_mutex); |
bc9025bd | 6193 | fail: |
05394f39 | 6194 | drm_gem_object_unreference_unlocked(&obj->base); |
34b8686e | 6195 | return ret; |
79e53945 JB |
6196 | } |
6197 | ||
6198 | static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) | |
6199 | { | |
79e53945 | 6200 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 6201 | |
cda4b7d3 CW |
6202 | intel_crtc->cursor_x = x; |
6203 | intel_crtc->cursor_y = y; | |
652c393a | 6204 | |
6b383a7f | 6205 | intel_crtc_update_cursor(crtc, true); |
79e53945 JB |
6206 | |
6207 | return 0; | |
6208 | } | |
6209 | ||
6210 | /** Sets the color ramps on behalf of RandR */ | |
6211 | void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, | |
6212 | u16 blue, int regno) | |
6213 | { | |
6214 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6215 | ||
6216 | intel_crtc->lut_r[regno] = red >> 8; | |
6217 | intel_crtc->lut_g[regno] = green >> 8; | |
6218 | intel_crtc->lut_b[regno] = blue >> 8; | |
6219 | } | |
6220 | ||
b8c00ac5 DA |
6221 | void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
6222 | u16 *blue, int regno) | |
6223 | { | |
6224 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6225 | ||
6226 | *red = intel_crtc->lut_r[regno] << 8; | |
6227 | *green = intel_crtc->lut_g[regno] << 8; | |
6228 | *blue = intel_crtc->lut_b[regno] << 8; | |
6229 | } | |
6230 | ||
79e53945 | 6231 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 6232 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 6233 | { |
7203425a | 6234 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 6235 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 6236 | |
7203425a | 6237 | for (i = start; i < end; i++) { |
79e53945 JB |
6238 | intel_crtc->lut_r[i] = red[i] >> 8; |
6239 | intel_crtc->lut_g[i] = green[i] >> 8; | |
6240 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
6241 | } | |
6242 | ||
6243 | intel_crtc_load_lut(crtc); | |
6244 | } | |
6245 | ||
6246 | /** | |
6247 | * Get a pipe with a simple mode set on it for doing load-based monitor | |
6248 | * detection. | |
6249 | * | |
6250 | * It will be up to the load-detect code to adjust the pipe as appropriate for | |
c751ce4f | 6251 | * its requirements. The pipe will be connected to no other encoders. |
79e53945 | 6252 | * |
c751ce4f | 6253 | * Currently this code will only succeed if there is a pipe with no encoders |
79e53945 JB |
6254 | * configured for it. In the future, it could choose to temporarily disable |
6255 | * some outputs to free up a pipe for its use. | |
6256 | * | |
6257 | * \return crtc, or NULL if no pipes are available. | |
6258 | */ | |
6259 | ||
6260 | /* VESA 640x480x72Hz mode to set on the pipe */ | |
6261 | static struct drm_display_mode load_detect_mode = { | |
6262 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
6263 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
6264 | }; | |
6265 | ||
d2dff872 CW |
6266 | static struct drm_framebuffer * |
6267 | intel_framebuffer_create(struct drm_device *dev, | |
6268 | struct drm_mode_fb_cmd *mode_cmd, | |
6269 | struct drm_i915_gem_object *obj) | |
6270 | { | |
6271 | struct intel_framebuffer *intel_fb; | |
6272 | int ret; | |
6273 | ||
6274 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
6275 | if (!intel_fb) { | |
6276 | drm_gem_object_unreference_unlocked(&obj->base); | |
6277 | return ERR_PTR(-ENOMEM); | |
6278 | } | |
6279 | ||
6280 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
6281 | if (ret) { | |
6282 | drm_gem_object_unreference_unlocked(&obj->base); | |
6283 | kfree(intel_fb); | |
6284 | return ERR_PTR(ret); | |
6285 | } | |
6286 | ||
6287 | return &intel_fb->base; | |
6288 | } | |
6289 | ||
6290 | static u32 | |
6291 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
6292 | { | |
6293 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
6294 | return ALIGN(pitch, 64); | |
6295 | } | |
6296 | ||
6297 | static u32 | |
6298 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
6299 | { | |
6300 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
6301 | return ALIGN(pitch * mode->vdisplay, PAGE_SIZE); | |
6302 | } | |
6303 | ||
6304 | static struct drm_framebuffer * | |
6305 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
6306 | struct drm_display_mode *mode, | |
6307 | int depth, int bpp) | |
6308 | { | |
6309 | struct drm_i915_gem_object *obj; | |
6310 | struct drm_mode_fb_cmd mode_cmd; | |
6311 | ||
6312 | obj = i915_gem_alloc_object(dev, | |
6313 | intel_framebuffer_size_for_mode(mode, bpp)); | |
6314 | if (obj == NULL) | |
6315 | return ERR_PTR(-ENOMEM); | |
6316 | ||
6317 | mode_cmd.width = mode->hdisplay; | |
6318 | mode_cmd.height = mode->vdisplay; | |
6319 | mode_cmd.depth = depth; | |
6320 | mode_cmd.bpp = bpp; | |
6321 | mode_cmd.pitch = intel_framebuffer_pitch_for_width(mode_cmd.width, bpp); | |
6322 | ||
6323 | return intel_framebuffer_create(dev, &mode_cmd, obj); | |
6324 | } | |
6325 | ||
6326 | static struct drm_framebuffer * | |
6327 | mode_fits_in_fbdev(struct drm_device *dev, | |
6328 | struct drm_display_mode *mode) | |
6329 | { | |
6330 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6331 | struct drm_i915_gem_object *obj; | |
6332 | struct drm_framebuffer *fb; | |
6333 | ||
6334 | if (dev_priv->fbdev == NULL) | |
6335 | return NULL; | |
6336 | ||
6337 | obj = dev_priv->fbdev->ifb.obj; | |
6338 | if (obj == NULL) | |
6339 | return NULL; | |
6340 | ||
6341 | fb = &dev_priv->fbdev->ifb.base; | |
6342 | if (fb->pitch < intel_framebuffer_pitch_for_width(mode->hdisplay, | |
6343 | fb->bits_per_pixel)) | |
6344 | return NULL; | |
6345 | ||
6346 | if (obj->base.size < mode->vdisplay * fb->pitch) | |
6347 | return NULL; | |
6348 | ||
6349 | return fb; | |
6350 | } | |
6351 | ||
7173188d CW |
6352 | bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder, |
6353 | struct drm_connector *connector, | |
6354 | struct drm_display_mode *mode, | |
8261b191 | 6355 | struct intel_load_detect_pipe *old) |
79e53945 JB |
6356 | { |
6357 | struct intel_crtc *intel_crtc; | |
6358 | struct drm_crtc *possible_crtc; | |
4ef69c7a | 6359 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
6360 | struct drm_crtc *crtc = NULL; |
6361 | struct drm_device *dev = encoder->dev; | |
d2dff872 | 6362 | struct drm_framebuffer *old_fb; |
79e53945 JB |
6363 | int i = -1; |
6364 | ||
d2dff872 CW |
6365 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
6366 | connector->base.id, drm_get_connector_name(connector), | |
6367 | encoder->base.id, drm_get_encoder_name(encoder)); | |
6368 | ||
79e53945 JB |
6369 | /* |
6370 | * Algorithm gets a little messy: | |
7a5e4805 | 6371 | * |
79e53945 JB |
6372 | * - if the connector already has an assigned crtc, use it (but make |
6373 | * sure it's on first) | |
7a5e4805 | 6374 | * |
79e53945 JB |
6375 | * - try to find the first unused crtc that can drive this connector, |
6376 | * and use that if we find one | |
79e53945 JB |
6377 | */ |
6378 | ||
6379 | /* See if we already have a CRTC for this connector */ | |
6380 | if (encoder->crtc) { | |
6381 | crtc = encoder->crtc; | |
8261b191 | 6382 | |
79e53945 | 6383 | intel_crtc = to_intel_crtc(crtc); |
8261b191 CW |
6384 | old->dpms_mode = intel_crtc->dpms_mode; |
6385 | old->load_detect_temp = false; | |
6386 | ||
6387 | /* Make sure the crtc and connector are running */ | |
79e53945 | 6388 | if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) { |
6492711d CW |
6389 | struct drm_encoder_helper_funcs *encoder_funcs; |
6390 | struct drm_crtc_helper_funcs *crtc_funcs; | |
6391 | ||
79e53945 JB |
6392 | crtc_funcs = crtc->helper_private; |
6393 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); | |
6492711d CW |
6394 | |
6395 | encoder_funcs = encoder->helper_private; | |
79e53945 JB |
6396 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); |
6397 | } | |
8261b191 | 6398 | |
7173188d | 6399 | return true; |
79e53945 JB |
6400 | } |
6401 | ||
6402 | /* Find an unused one (if possible) */ | |
6403 | list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) { | |
6404 | i++; | |
6405 | if (!(encoder->possible_crtcs & (1 << i))) | |
6406 | continue; | |
6407 | if (!possible_crtc->enabled) { | |
6408 | crtc = possible_crtc; | |
6409 | break; | |
6410 | } | |
79e53945 JB |
6411 | } |
6412 | ||
6413 | /* | |
6414 | * If we didn't find an unused CRTC, don't use any. | |
6415 | */ | |
6416 | if (!crtc) { | |
7173188d CW |
6417 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
6418 | return false; | |
79e53945 JB |
6419 | } |
6420 | ||
6421 | encoder->crtc = crtc; | |
c1c43977 | 6422 | connector->encoder = encoder; |
79e53945 JB |
6423 | |
6424 | intel_crtc = to_intel_crtc(crtc); | |
8261b191 CW |
6425 | old->dpms_mode = intel_crtc->dpms_mode; |
6426 | old->load_detect_temp = true; | |
d2dff872 | 6427 | old->release_fb = NULL; |
79e53945 | 6428 | |
6492711d CW |
6429 | if (!mode) |
6430 | mode = &load_detect_mode; | |
79e53945 | 6431 | |
d2dff872 CW |
6432 | old_fb = crtc->fb; |
6433 | ||
6434 | /* We need a framebuffer large enough to accommodate all accesses | |
6435 | * that the plane may generate whilst we perform load detection. | |
6436 | * We can not rely on the fbcon either being present (we get called | |
6437 | * during its initialisation to detect all boot displays, or it may | |
6438 | * not even exist) or that it is large enough to satisfy the | |
6439 | * requested mode. | |
6440 | */ | |
6441 | crtc->fb = mode_fits_in_fbdev(dev, mode); | |
6442 | if (crtc->fb == NULL) { | |
6443 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); | |
6444 | crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); | |
6445 | old->release_fb = crtc->fb; | |
6446 | } else | |
6447 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
6448 | if (IS_ERR(crtc->fb)) { | |
6449 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); | |
6450 | crtc->fb = old_fb; | |
6451 | return false; | |
79e53945 | 6452 | } |
79e53945 | 6453 | |
d2dff872 | 6454 | if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) { |
6492711d | 6455 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
d2dff872 CW |
6456 | if (old->release_fb) |
6457 | old->release_fb->funcs->destroy(old->release_fb); | |
6458 | crtc->fb = old_fb; | |
6492711d | 6459 | return false; |
79e53945 | 6460 | } |
7173188d | 6461 | |
79e53945 | 6462 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 6463 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
79e53945 | 6464 | |
7173188d | 6465 | return true; |
79e53945 JB |
6466 | } |
6467 | ||
c1c43977 | 6468 | void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder, |
8261b191 CW |
6469 | struct drm_connector *connector, |
6470 | struct intel_load_detect_pipe *old) | |
79e53945 | 6471 | { |
4ef69c7a | 6472 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
6473 | struct drm_device *dev = encoder->dev; |
6474 | struct drm_crtc *crtc = encoder->crtc; | |
6475 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
6476 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; | |
6477 | ||
d2dff872 CW |
6478 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
6479 | connector->base.id, drm_get_connector_name(connector), | |
6480 | encoder->base.id, drm_get_encoder_name(encoder)); | |
6481 | ||
8261b191 | 6482 | if (old->load_detect_temp) { |
c1c43977 | 6483 | connector->encoder = NULL; |
79e53945 | 6484 | drm_helper_disable_unused_functions(dev); |
d2dff872 CW |
6485 | |
6486 | if (old->release_fb) | |
6487 | old->release_fb->funcs->destroy(old->release_fb); | |
6488 | ||
0622a53c | 6489 | return; |
79e53945 JB |
6490 | } |
6491 | ||
c751ce4f | 6492 | /* Switch crtc and encoder back off if necessary */ |
0622a53c CW |
6493 | if (old->dpms_mode != DRM_MODE_DPMS_ON) { |
6494 | encoder_funcs->dpms(encoder, old->dpms_mode); | |
8261b191 | 6495 | crtc_funcs->dpms(crtc, old->dpms_mode); |
79e53945 JB |
6496 | } |
6497 | } | |
6498 | ||
6499 | /* Returns the clock of the currently programmed mode of the given pipe. */ | |
6500 | static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc) | |
6501 | { | |
6502 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6503 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6504 | int pipe = intel_crtc->pipe; | |
548f245b | 6505 | u32 dpll = I915_READ(DPLL(pipe)); |
79e53945 JB |
6506 | u32 fp; |
6507 | intel_clock_t clock; | |
6508 | ||
6509 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
39adb7a5 | 6510 | fp = I915_READ(FP0(pipe)); |
79e53945 | 6511 | else |
39adb7a5 | 6512 | fp = I915_READ(FP1(pipe)); |
79e53945 JB |
6513 | |
6514 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
6515 | if (IS_PINEVIEW(dev)) { |
6516 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
6517 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
6518 | } else { |
6519 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
6520 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
6521 | } | |
6522 | ||
a6c45cf0 | 6523 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
6524 | if (IS_PINEVIEW(dev)) |
6525 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
6526 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
6527 | else |
6528 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
6529 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
6530 | ||
6531 | switch (dpll & DPLL_MODE_MASK) { | |
6532 | case DPLLB_MODE_DAC_SERIAL: | |
6533 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
6534 | 5 : 10; | |
6535 | break; | |
6536 | case DPLLB_MODE_LVDS: | |
6537 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
6538 | 7 : 14; | |
6539 | break; | |
6540 | default: | |
28c97730 | 6541 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 JB |
6542 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
6543 | return 0; | |
6544 | } | |
6545 | ||
6546 | /* XXX: Handle the 100Mhz refclk */ | |
2177832f | 6547 | intel_clock(dev, 96000, &clock); |
79e53945 JB |
6548 | } else { |
6549 | bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN); | |
6550 | ||
6551 | if (is_lvds) { | |
6552 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
6553 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
6554 | clock.p2 = 14; | |
6555 | ||
6556 | if ((dpll & PLL_REF_INPUT_MASK) == | |
6557 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { | |
6558 | /* XXX: might not be 66MHz */ | |
2177832f | 6559 | intel_clock(dev, 66000, &clock); |
79e53945 | 6560 | } else |
2177832f | 6561 | intel_clock(dev, 48000, &clock); |
79e53945 JB |
6562 | } else { |
6563 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
6564 | clock.p1 = 2; | |
6565 | else { | |
6566 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
6567 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
6568 | } | |
6569 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
6570 | clock.p2 = 4; | |
6571 | else | |
6572 | clock.p2 = 2; | |
6573 | ||
2177832f | 6574 | intel_clock(dev, 48000, &clock); |
79e53945 JB |
6575 | } |
6576 | } | |
6577 | ||
6578 | /* XXX: It would be nice to validate the clocks, but we can't reuse | |
6579 | * i830PllIsValid() because it relies on the xf86_config connector | |
6580 | * configuration being accurate, which it isn't necessarily. | |
6581 | */ | |
6582 | ||
6583 | return clock.dot; | |
6584 | } | |
6585 | ||
6586 | /** Returns the currently programmed mode of the given pipe. */ | |
6587 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
6588 | struct drm_crtc *crtc) | |
6589 | { | |
548f245b | 6590 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 JB |
6591 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6592 | int pipe = intel_crtc->pipe; | |
6593 | struct drm_display_mode *mode; | |
548f245b JB |
6594 | int htot = I915_READ(HTOTAL(pipe)); |
6595 | int hsync = I915_READ(HSYNC(pipe)); | |
6596 | int vtot = I915_READ(VTOTAL(pipe)); | |
6597 | int vsync = I915_READ(VSYNC(pipe)); | |
79e53945 JB |
6598 | |
6599 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
6600 | if (!mode) | |
6601 | return NULL; | |
6602 | ||
6603 | mode->clock = intel_crtc_clock_get(dev, crtc); | |
6604 | mode->hdisplay = (htot & 0xffff) + 1; | |
6605 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
6606 | mode->hsync_start = (hsync & 0xffff) + 1; | |
6607 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
6608 | mode->vdisplay = (vtot & 0xffff) + 1; | |
6609 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
6610 | mode->vsync_start = (vsync & 0xffff) + 1; | |
6611 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
6612 | ||
6613 | drm_mode_set_name(mode); | |
6614 | drm_mode_set_crtcinfo(mode, 0); | |
6615 | ||
6616 | return mode; | |
6617 | } | |
6618 | ||
652c393a JB |
6619 | #define GPU_IDLE_TIMEOUT 500 /* ms */ |
6620 | ||
6621 | /* When this timer fires, we've been idle for awhile */ | |
6622 | static void intel_gpu_idle_timer(unsigned long arg) | |
6623 | { | |
6624 | struct drm_device *dev = (struct drm_device *)arg; | |
6625 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6626 | ||
ff7ea4c0 CW |
6627 | if (!list_empty(&dev_priv->mm.active_list)) { |
6628 | /* Still processing requests, so just re-arm the timer. */ | |
6629 | mod_timer(&dev_priv->idle_timer, jiffies + | |
6630 | msecs_to_jiffies(GPU_IDLE_TIMEOUT)); | |
6631 | return; | |
6632 | } | |
652c393a | 6633 | |
ff7ea4c0 | 6634 | dev_priv->busy = false; |
01dfba93 | 6635 | queue_work(dev_priv->wq, &dev_priv->idle_work); |
652c393a JB |
6636 | } |
6637 | ||
652c393a JB |
6638 | #define CRTC_IDLE_TIMEOUT 1000 /* ms */ |
6639 | ||
6640 | static void intel_crtc_idle_timer(unsigned long arg) | |
6641 | { | |
6642 | struct intel_crtc *intel_crtc = (struct intel_crtc *)arg; | |
6643 | struct drm_crtc *crtc = &intel_crtc->base; | |
6644 | drm_i915_private_t *dev_priv = crtc->dev->dev_private; | |
ff7ea4c0 | 6645 | struct intel_framebuffer *intel_fb; |
652c393a | 6646 | |
ff7ea4c0 CW |
6647 | intel_fb = to_intel_framebuffer(crtc->fb); |
6648 | if (intel_fb && intel_fb->obj->active) { | |
6649 | /* The framebuffer is still being accessed by the GPU. */ | |
6650 | mod_timer(&intel_crtc->idle_timer, jiffies + | |
6651 | msecs_to_jiffies(CRTC_IDLE_TIMEOUT)); | |
6652 | return; | |
6653 | } | |
652c393a | 6654 | |
ff7ea4c0 | 6655 | intel_crtc->busy = false; |
01dfba93 | 6656 | queue_work(dev_priv->wq, &dev_priv->idle_work); |
652c393a JB |
6657 | } |
6658 | ||
3dec0095 | 6659 | static void intel_increase_pllclock(struct drm_crtc *crtc) |
652c393a JB |
6660 | { |
6661 | struct drm_device *dev = crtc->dev; | |
6662 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6663 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6664 | int pipe = intel_crtc->pipe; | |
dbdc6479 JB |
6665 | int dpll_reg = DPLL(pipe); |
6666 | int dpll; | |
652c393a | 6667 | |
bad720ff | 6668 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
6669 | return; |
6670 | ||
6671 | if (!dev_priv->lvds_downclock_avail) | |
6672 | return; | |
6673 | ||
dbdc6479 | 6674 | dpll = I915_READ(dpll_reg); |
652c393a | 6675 | if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { |
44d98a61 | 6676 | DRM_DEBUG_DRIVER("upclocking LVDS\n"); |
652c393a JB |
6677 | |
6678 | /* Unlock panel regs */ | |
dbdc6479 JB |
6679 | I915_WRITE(PP_CONTROL, |
6680 | I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS); | |
652c393a JB |
6681 | |
6682 | dpll &= ~DISPLAY_RATE_SELECT_FPA1; | |
6683 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 6684 | intel_wait_for_vblank(dev, pipe); |
dbdc6479 | 6685 | |
652c393a JB |
6686 | dpll = I915_READ(dpll_reg); |
6687 | if (dpll & DISPLAY_RATE_SELECT_FPA1) | |
44d98a61 | 6688 | DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); |
652c393a JB |
6689 | |
6690 | /* ...and lock them again */ | |
6691 | I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3); | |
6692 | } | |
6693 | ||
6694 | /* Schedule downclock */ | |
3dec0095 DV |
6695 | mod_timer(&intel_crtc->idle_timer, jiffies + |
6696 | msecs_to_jiffies(CRTC_IDLE_TIMEOUT)); | |
652c393a JB |
6697 | } |
6698 | ||
6699 | static void intel_decrease_pllclock(struct drm_crtc *crtc) | |
6700 | { | |
6701 | struct drm_device *dev = crtc->dev; | |
6702 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6703 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6704 | int pipe = intel_crtc->pipe; | |
9db4a9c7 | 6705 | int dpll_reg = DPLL(pipe); |
652c393a JB |
6706 | int dpll = I915_READ(dpll_reg); |
6707 | ||
bad720ff | 6708 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
6709 | return; |
6710 | ||
6711 | if (!dev_priv->lvds_downclock_avail) | |
6712 | return; | |
6713 | ||
6714 | /* | |
6715 | * Since this is called by a timer, we should never get here in | |
6716 | * the manual case. | |
6717 | */ | |
6718 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { | |
44d98a61 | 6719 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
652c393a JB |
6720 | |
6721 | /* Unlock panel regs */ | |
4a655f04 JB |
6722 | I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | |
6723 | PANEL_UNLOCK_REGS); | |
652c393a JB |
6724 | |
6725 | dpll |= DISPLAY_RATE_SELECT_FPA1; | |
6726 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 6727 | intel_wait_for_vblank(dev, pipe); |
652c393a JB |
6728 | dpll = I915_READ(dpll_reg); |
6729 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) | |
44d98a61 | 6730 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
652c393a JB |
6731 | |
6732 | /* ...and lock them again */ | |
6733 | I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3); | |
6734 | } | |
6735 | ||
6736 | } | |
6737 | ||
6738 | /** | |
6739 | * intel_idle_update - adjust clocks for idleness | |
6740 | * @work: work struct | |
6741 | * | |
6742 | * Either the GPU or display (or both) went idle. Check the busy status | |
6743 | * here and adjust the CRTC and GPU clocks as necessary. | |
6744 | */ | |
6745 | static void intel_idle_update(struct work_struct *work) | |
6746 | { | |
6747 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, | |
6748 | idle_work); | |
6749 | struct drm_device *dev = dev_priv->dev; | |
6750 | struct drm_crtc *crtc; | |
6751 | struct intel_crtc *intel_crtc; | |
6752 | ||
6753 | if (!i915_powersave) | |
6754 | return; | |
6755 | ||
6756 | mutex_lock(&dev->struct_mutex); | |
6757 | ||
7648fa99 JB |
6758 | i915_update_gfx_val(dev_priv); |
6759 | ||
652c393a JB |
6760 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
6761 | /* Skip inactive CRTCs */ | |
6762 | if (!crtc->fb) | |
6763 | continue; | |
6764 | ||
6765 | intel_crtc = to_intel_crtc(crtc); | |
6766 | if (!intel_crtc->busy) | |
6767 | intel_decrease_pllclock(crtc); | |
6768 | } | |
6769 | ||
45ac22c8 | 6770 | |
652c393a JB |
6771 | mutex_unlock(&dev->struct_mutex); |
6772 | } | |
6773 | ||
6774 | /** | |
6775 | * intel_mark_busy - mark the GPU and possibly the display busy | |
6776 | * @dev: drm device | |
6777 | * @obj: object we're operating on | |
6778 | * | |
6779 | * Callers can use this function to indicate that the GPU is busy processing | |
6780 | * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout | |
6781 | * buffer), we'll also mark the display as busy, so we know to increase its | |
6782 | * clock frequency. | |
6783 | */ | |
05394f39 | 6784 | void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj) |
652c393a JB |
6785 | { |
6786 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6787 | struct drm_crtc *crtc = NULL; | |
6788 | struct intel_framebuffer *intel_fb; | |
6789 | struct intel_crtc *intel_crtc; | |
6790 | ||
5e17ee74 ZW |
6791 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
6792 | return; | |
6793 | ||
18b2190c | 6794 | if (!dev_priv->busy) |
28cf798f | 6795 | dev_priv->busy = true; |
18b2190c | 6796 | else |
28cf798f CW |
6797 | mod_timer(&dev_priv->idle_timer, jiffies + |
6798 | msecs_to_jiffies(GPU_IDLE_TIMEOUT)); | |
652c393a JB |
6799 | |
6800 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
6801 | if (!crtc->fb) | |
6802 | continue; | |
6803 | ||
6804 | intel_crtc = to_intel_crtc(crtc); | |
6805 | intel_fb = to_intel_framebuffer(crtc->fb); | |
6806 | if (intel_fb->obj == obj) { | |
6807 | if (!intel_crtc->busy) { | |
6808 | /* Non-busy -> busy, upclock */ | |
3dec0095 | 6809 | intel_increase_pllclock(crtc); |
652c393a JB |
6810 | intel_crtc->busy = true; |
6811 | } else { | |
6812 | /* Busy -> busy, put off timer */ | |
6813 | mod_timer(&intel_crtc->idle_timer, jiffies + | |
6814 | msecs_to_jiffies(CRTC_IDLE_TIMEOUT)); | |
6815 | } | |
6816 | } | |
6817 | } | |
6818 | } | |
6819 | ||
79e53945 JB |
6820 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
6821 | { | |
6822 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
6823 | struct drm_device *dev = crtc->dev; |
6824 | struct intel_unpin_work *work; | |
6825 | unsigned long flags; | |
6826 | ||
6827 | spin_lock_irqsave(&dev->event_lock, flags); | |
6828 | work = intel_crtc->unpin_work; | |
6829 | intel_crtc->unpin_work = NULL; | |
6830 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
6831 | ||
6832 | if (work) { | |
6833 | cancel_work_sync(&work->work); | |
6834 | kfree(work); | |
6835 | } | |
79e53945 JB |
6836 | |
6837 | drm_crtc_cleanup(crtc); | |
67e77c5a | 6838 | |
79e53945 JB |
6839 | kfree(intel_crtc); |
6840 | } | |
6841 | ||
6b95a207 KH |
6842 | static void intel_unpin_work_fn(struct work_struct *__work) |
6843 | { | |
6844 | struct intel_unpin_work *work = | |
6845 | container_of(__work, struct intel_unpin_work, work); | |
6846 | ||
6847 | mutex_lock(&work->dev->struct_mutex); | |
b1b87f6b | 6848 | i915_gem_object_unpin(work->old_fb_obj); |
05394f39 CW |
6849 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
6850 | drm_gem_object_unreference(&work->old_fb_obj->base); | |
d9e86c0e | 6851 | |
7782de3b | 6852 | intel_update_fbc(work->dev); |
6b95a207 KH |
6853 | mutex_unlock(&work->dev->struct_mutex); |
6854 | kfree(work); | |
6855 | } | |
6856 | ||
1afe3e9d | 6857 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 6858 | struct drm_crtc *crtc) |
6b95a207 KH |
6859 | { |
6860 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6b95a207 KH |
6861 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6862 | struct intel_unpin_work *work; | |
05394f39 | 6863 | struct drm_i915_gem_object *obj; |
6b95a207 | 6864 | struct drm_pending_vblank_event *e; |
49b14a5c | 6865 | struct timeval tnow, tvbl; |
6b95a207 KH |
6866 | unsigned long flags; |
6867 | ||
6868 | /* Ignore early vblank irqs */ | |
6869 | if (intel_crtc == NULL) | |
6870 | return; | |
6871 | ||
49b14a5c MK |
6872 | do_gettimeofday(&tnow); |
6873 | ||
6b95a207 KH |
6874 | spin_lock_irqsave(&dev->event_lock, flags); |
6875 | work = intel_crtc->unpin_work; | |
6876 | if (work == NULL || !work->pending) { | |
6877 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
6878 | return; | |
6879 | } | |
6880 | ||
6881 | intel_crtc->unpin_work = NULL; | |
6b95a207 KH |
6882 | |
6883 | if (work->event) { | |
6884 | e = work->event; | |
49b14a5c | 6885 | e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl); |
0af7e4df MK |
6886 | |
6887 | /* Called before vblank count and timestamps have | |
6888 | * been updated for the vblank interval of flip | |
6889 | * completion? Need to increment vblank count and | |
6890 | * add one videorefresh duration to returned timestamp | |
49b14a5c MK |
6891 | * to account for this. We assume this happened if we |
6892 | * get called over 0.9 frame durations after the last | |
6893 | * timestamped vblank. | |
6894 | * | |
6895 | * This calculation can not be used with vrefresh rates | |
6896 | * below 5Hz (10Hz to be on the safe side) without | |
6897 | * promoting to 64 integers. | |
0af7e4df | 6898 | */ |
49b14a5c MK |
6899 | if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) > |
6900 | 9 * crtc->framedur_ns) { | |
0af7e4df | 6901 | e->event.sequence++; |
49b14a5c MK |
6902 | tvbl = ns_to_timeval(timeval_to_ns(&tvbl) + |
6903 | crtc->framedur_ns); | |
0af7e4df MK |
6904 | } |
6905 | ||
49b14a5c MK |
6906 | e->event.tv_sec = tvbl.tv_sec; |
6907 | e->event.tv_usec = tvbl.tv_usec; | |
0af7e4df | 6908 | |
6b95a207 KH |
6909 | list_add_tail(&e->base.link, |
6910 | &e->base.file_priv->event_list); | |
6911 | wake_up_interruptible(&e->base.file_priv->event_wait); | |
6912 | } | |
6913 | ||
0af7e4df MK |
6914 | drm_vblank_put(dev, intel_crtc->pipe); |
6915 | ||
6b95a207 KH |
6916 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6917 | ||
05394f39 | 6918 | obj = work->old_fb_obj; |
d9e86c0e | 6919 | |
e59f2bac | 6920 | atomic_clear_mask(1 << intel_crtc->plane, |
05394f39 CW |
6921 | &obj->pending_flip.counter); |
6922 | if (atomic_read(&obj->pending_flip) == 0) | |
f787a5f5 | 6923 | wake_up(&dev_priv->pending_flip_queue); |
d9e86c0e | 6924 | |
6b95a207 | 6925 | schedule_work(&work->work); |
e5510fac JB |
6926 | |
6927 | trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj); | |
6b95a207 KH |
6928 | } |
6929 | ||
1afe3e9d JB |
6930 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
6931 | { | |
6932 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6933 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
6934 | ||
49b14a5c | 6935 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
6936 | } |
6937 | ||
6938 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
6939 | { | |
6940 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6941 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; | |
6942 | ||
49b14a5c | 6943 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
6944 | } |
6945 | ||
6b95a207 KH |
6946 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
6947 | { | |
6948 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6949 | struct intel_crtc *intel_crtc = | |
6950 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
6951 | unsigned long flags; | |
6952 | ||
6953 | spin_lock_irqsave(&dev->event_lock, flags); | |
de3f440f | 6954 | if (intel_crtc->unpin_work) { |
4e5359cd SF |
6955 | if ((++intel_crtc->unpin_work->pending) > 1) |
6956 | DRM_ERROR("Prepared flip multiple times\n"); | |
de3f440f JB |
6957 | } else { |
6958 | DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n"); | |
6959 | } | |
6b95a207 KH |
6960 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6961 | } | |
6962 | ||
8c9f3aaf JB |
6963 | static int intel_gen2_queue_flip(struct drm_device *dev, |
6964 | struct drm_crtc *crtc, | |
6965 | struct drm_framebuffer *fb, | |
6966 | struct drm_i915_gem_object *obj) | |
6967 | { | |
6968 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6969 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6970 | unsigned long offset; | |
6971 | u32 flip_mask; | |
6972 | int ret; | |
6973 | ||
6974 | ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv)); | |
6975 | if (ret) | |
6976 | goto out; | |
6977 | ||
6978 | /* Offset into the new buffer for cases of shared fbs between CRTCs */ | |
6979 | offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8; | |
6980 | ||
6981 | ret = BEGIN_LP_RING(6); | |
6982 | if (ret) | |
6983 | goto out; | |
6984 | ||
6985 | /* Can't queue multiple flips, so wait for the previous | |
6986 | * one to finish before executing the next. | |
6987 | */ | |
6988 | if (intel_crtc->plane) | |
6989 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
6990 | else | |
6991 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6992 | OUT_RING(MI_WAIT_FOR_EVENT | flip_mask); | |
6993 | OUT_RING(MI_NOOP); | |
6994 | OUT_RING(MI_DISPLAY_FLIP | | |
6995 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
6996 | OUT_RING(fb->pitch); | |
6997 | OUT_RING(obj->gtt_offset + offset); | |
6998 | OUT_RING(MI_NOOP); | |
6999 | ADVANCE_LP_RING(); | |
7000 | out: | |
7001 | return ret; | |
7002 | } | |
7003 | ||
7004 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
7005 | struct drm_crtc *crtc, | |
7006 | struct drm_framebuffer *fb, | |
7007 | struct drm_i915_gem_object *obj) | |
7008 | { | |
7009 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7010 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7011 | unsigned long offset; | |
7012 | u32 flip_mask; | |
7013 | int ret; | |
7014 | ||
7015 | ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv)); | |
7016 | if (ret) | |
7017 | goto out; | |
7018 | ||
7019 | /* Offset into the new buffer for cases of shared fbs between CRTCs */ | |
7020 | offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8; | |
7021 | ||
7022 | ret = BEGIN_LP_RING(6); | |
7023 | if (ret) | |
7024 | goto out; | |
7025 | ||
7026 | if (intel_crtc->plane) | |
7027 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
7028 | else | |
7029 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
7030 | OUT_RING(MI_WAIT_FOR_EVENT | flip_mask); | |
7031 | OUT_RING(MI_NOOP); | |
7032 | OUT_RING(MI_DISPLAY_FLIP_I915 | | |
7033 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
7034 | OUT_RING(fb->pitch); | |
7035 | OUT_RING(obj->gtt_offset + offset); | |
7036 | OUT_RING(MI_NOOP); | |
7037 | ||
7038 | ADVANCE_LP_RING(); | |
7039 | out: | |
7040 | return ret; | |
7041 | } | |
7042 | ||
7043 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
7044 | struct drm_crtc *crtc, | |
7045 | struct drm_framebuffer *fb, | |
7046 | struct drm_i915_gem_object *obj) | |
7047 | { | |
7048 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7049 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7050 | uint32_t pf, pipesrc; | |
7051 | int ret; | |
7052 | ||
7053 | ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv)); | |
7054 | if (ret) | |
7055 | goto out; | |
7056 | ||
7057 | ret = BEGIN_LP_RING(4); | |
7058 | if (ret) | |
7059 | goto out; | |
7060 | ||
7061 | /* i965+ uses the linear or tiled offsets from the | |
7062 | * Display Registers (which do not change across a page-flip) | |
7063 | * so we need only reprogram the base address. | |
7064 | */ | |
7065 | OUT_RING(MI_DISPLAY_FLIP | | |
7066 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
7067 | OUT_RING(fb->pitch); | |
7068 | OUT_RING(obj->gtt_offset | obj->tiling_mode); | |
7069 | ||
7070 | /* XXX Enabling the panel-fitter across page-flip is so far | |
7071 | * untested on non-native modes, so ignore it for now. | |
7072 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
7073 | */ | |
7074 | pf = 0; | |
7075 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
7076 | OUT_RING(pf | pipesrc); | |
7077 | ADVANCE_LP_RING(); | |
7078 | out: | |
7079 | return ret; | |
7080 | } | |
7081 | ||
7082 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
7083 | struct drm_crtc *crtc, | |
7084 | struct drm_framebuffer *fb, | |
7085 | struct drm_i915_gem_object *obj) | |
7086 | { | |
7087 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7088 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7089 | uint32_t pf, pipesrc; | |
7090 | int ret; | |
7091 | ||
7092 | ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv)); | |
7093 | if (ret) | |
7094 | goto out; | |
7095 | ||
7096 | ret = BEGIN_LP_RING(4); | |
7097 | if (ret) | |
7098 | goto out; | |
7099 | ||
7100 | OUT_RING(MI_DISPLAY_FLIP | | |
7101 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
7102 | OUT_RING(fb->pitch | obj->tiling_mode); | |
7103 | OUT_RING(obj->gtt_offset); | |
7104 | ||
7105 | pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
7106 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
7107 | OUT_RING(pf | pipesrc); | |
7108 | ADVANCE_LP_RING(); | |
7109 | out: | |
7110 | return ret; | |
7111 | } | |
7112 | ||
7c9017e5 JB |
7113 | /* |
7114 | * On gen7 we currently use the blit ring because (in early silicon at least) | |
7115 | * the render ring doesn't give us interrpts for page flip completion, which | |
7116 | * means clients will hang after the first flip is queued. Fortunately the | |
7117 | * blit ring generates interrupts properly, so use it instead. | |
7118 | */ | |
7119 | static int intel_gen7_queue_flip(struct drm_device *dev, | |
7120 | struct drm_crtc *crtc, | |
7121 | struct drm_framebuffer *fb, | |
7122 | struct drm_i915_gem_object *obj) | |
7123 | { | |
7124 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7125 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7126 | struct intel_ring_buffer *ring = &dev_priv->ring[BCS]; | |
7127 | int ret; | |
7128 | ||
7129 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); | |
7130 | if (ret) | |
7131 | goto out; | |
7132 | ||
7133 | ret = intel_ring_begin(ring, 4); | |
7134 | if (ret) | |
7135 | goto out; | |
7136 | ||
7137 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19)); | |
7138 | intel_ring_emit(ring, (fb->pitch | obj->tiling_mode)); | |
7139 | intel_ring_emit(ring, (obj->gtt_offset)); | |
7140 | intel_ring_emit(ring, (MI_NOOP)); | |
7141 | intel_ring_advance(ring); | |
7142 | out: | |
7143 | return ret; | |
7144 | } | |
7145 | ||
8c9f3aaf JB |
7146 | static int intel_default_queue_flip(struct drm_device *dev, |
7147 | struct drm_crtc *crtc, | |
7148 | struct drm_framebuffer *fb, | |
7149 | struct drm_i915_gem_object *obj) | |
7150 | { | |
7151 | return -ENODEV; | |
7152 | } | |
7153 | ||
6b95a207 KH |
7154 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
7155 | struct drm_framebuffer *fb, | |
7156 | struct drm_pending_vblank_event *event) | |
7157 | { | |
7158 | struct drm_device *dev = crtc->dev; | |
7159 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7160 | struct intel_framebuffer *intel_fb; | |
05394f39 | 7161 | struct drm_i915_gem_object *obj; |
6b95a207 KH |
7162 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7163 | struct intel_unpin_work *work; | |
8c9f3aaf | 7164 | unsigned long flags; |
52e68630 | 7165 | int ret; |
6b95a207 KH |
7166 | |
7167 | work = kzalloc(sizeof *work, GFP_KERNEL); | |
7168 | if (work == NULL) | |
7169 | return -ENOMEM; | |
7170 | ||
6b95a207 KH |
7171 | work->event = event; |
7172 | work->dev = crtc->dev; | |
7173 | intel_fb = to_intel_framebuffer(crtc->fb); | |
b1b87f6b | 7174 | work->old_fb_obj = intel_fb->obj; |
6b95a207 KH |
7175 | INIT_WORK(&work->work, intel_unpin_work_fn); |
7176 | ||
7177 | /* We borrow the event spin lock for protecting unpin_work */ | |
7178 | spin_lock_irqsave(&dev->event_lock, flags); | |
7179 | if (intel_crtc->unpin_work) { | |
7180 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
7181 | kfree(work); | |
468f0b44 CW |
7182 | |
7183 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
6b95a207 KH |
7184 | return -EBUSY; |
7185 | } | |
7186 | intel_crtc->unpin_work = work; | |
7187 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
7188 | ||
7189 | intel_fb = to_intel_framebuffer(fb); | |
7190 | obj = intel_fb->obj; | |
7191 | ||
468f0b44 | 7192 | mutex_lock(&dev->struct_mutex); |
6b95a207 | 7193 | |
75dfca80 | 7194 | /* Reference the objects for the scheduled work. */ |
05394f39 CW |
7195 | drm_gem_object_reference(&work->old_fb_obj->base); |
7196 | drm_gem_object_reference(&obj->base); | |
6b95a207 KH |
7197 | |
7198 | crtc->fb = fb; | |
96b099fd CW |
7199 | |
7200 | ret = drm_vblank_get(dev, intel_crtc->pipe); | |
7201 | if (ret) | |
7202 | goto cleanup_objs; | |
7203 | ||
e1f99ce6 | 7204 | work->pending_flip_obj = obj; |
e1f99ce6 | 7205 | |
4e5359cd SF |
7206 | work->enable_stall_check = true; |
7207 | ||
e1f99ce6 CW |
7208 | /* Block clients from rendering to the new back buffer until |
7209 | * the flip occurs and the object is no longer visible. | |
7210 | */ | |
05394f39 | 7211 | atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip); |
e1f99ce6 | 7212 | |
8c9f3aaf JB |
7213 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj); |
7214 | if (ret) | |
7215 | goto cleanup_pending; | |
6b95a207 | 7216 | |
7782de3b | 7217 | intel_disable_fbc(dev); |
6b95a207 KH |
7218 | mutex_unlock(&dev->struct_mutex); |
7219 | ||
e5510fac JB |
7220 | trace_i915_flip_request(intel_crtc->plane, obj); |
7221 | ||
6b95a207 | 7222 | return 0; |
96b099fd | 7223 | |
8c9f3aaf JB |
7224 | cleanup_pending: |
7225 | atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip); | |
96b099fd | 7226 | cleanup_objs: |
05394f39 CW |
7227 | drm_gem_object_unreference(&work->old_fb_obj->base); |
7228 | drm_gem_object_unreference(&obj->base); | |
96b099fd CW |
7229 | mutex_unlock(&dev->struct_mutex); |
7230 | ||
7231 | spin_lock_irqsave(&dev->event_lock, flags); | |
7232 | intel_crtc->unpin_work = NULL; | |
7233 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
7234 | ||
7235 | kfree(work); | |
7236 | ||
7237 | return ret; | |
6b95a207 KH |
7238 | } |
7239 | ||
47f1c6c9 CW |
7240 | static void intel_sanitize_modesetting(struct drm_device *dev, |
7241 | int pipe, int plane) | |
7242 | { | |
7243 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7244 | u32 reg, val; | |
7245 | ||
7246 | if (HAS_PCH_SPLIT(dev)) | |
7247 | return; | |
7248 | ||
7249 | /* Who knows what state these registers were left in by the BIOS or | |
7250 | * grub? | |
7251 | * | |
7252 | * If we leave the registers in a conflicting state (e.g. with the | |
7253 | * display plane reading from the other pipe than the one we intend | |
7254 | * to use) then when we attempt to teardown the active mode, we will | |
7255 | * not disable the pipes and planes in the correct order -- leaving | |
7256 | * a plane reading from a disabled pipe and possibly leading to | |
7257 | * undefined behaviour. | |
7258 | */ | |
7259 | ||
7260 | reg = DSPCNTR(plane); | |
7261 | val = I915_READ(reg); | |
7262 | ||
7263 | if ((val & DISPLAY_PLANE_ENABLE) == 0) | |
7264 | return; | |
7265 | if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe) | |
7266 | return; | |
7267 | ||
7268 | /* This display plane is active and attached to the other CPU pipe. */ | |
7269 | pipe = !pipe; | |
7270 | ||
7271 | /* Disable the plane and wait for it to stop reading from the pipe. */ | |
b24e7179 JB |
7272 | intel_disable_plane(dev_priv, plane, pipe); |
7273 | intel_disable_pipe(dev_priv, pipe); | |
47f1c6c9 | 7274 | } |
79e53945 | 7275 | |
f6e5b160 CW |
7276 | static void intel_crtc_reset(struct drm_crtc *crtc) |
7277 | { | |
7278 | struct drm_device *dev = crtc->dev; | |
7279 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7280 | ||
7281 | /* Reset flags back to the 'unknown' status so that they | |
7282 | * will be correctly set on the initial modeset. | |
7283 | */ | |
7284 | intel_crtc->dpms_mode = -1; | |
7285 | ||
7286 | /* We need to fix up any BIOS configuration that conflicts with | |
7287 | * our expectations. | |
7288 | */ | |
7289 | intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane); | |
7290 | } | |
7291 | ||
7292 | static struct drm_crtc_helper_funcs intel_helper_funcs = { | |
7293 | .dpms = intel_crtc_dpms, | |
7294 | .mode_fixup = intel_crtc_mode_fixup, | |
7295 | .mode_set = intel_crtc_mode_set, | |
7296 | .mode_set_base = intel_pipe_set_base, | |
7297 | .mode_set_base_atomic = intel_pipe_set_base_atomic, | |
7298 | .load_lut = intel_crtc_load_lut, | |
7299 | .disable = intel_crtc_disable, | |
7300 | }; | |
7301 | ||
7302 | static const struct drm_crtc_funcs intel_crtc_funcs = { | |
7303 | .reset = intel_crtc_reset, | |
7304 | .cursor_set = intel_crtc_cursor_set, | |
7305 | .cursor_move = intel_crtc_cursor_move, | |
7306 | .gamma_set = intel_crtc_gamma_set, | |
7307 | .set_config = drm_crtc_helper_set_config, | |
7308 | .destroy = intel_crtc_destroy, | |
7309 | .page_flip = intel_crtc_page_flip, | |
7310 | }; | |
7311 | ||
b358d0a6 | 7312 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 7313 | { |
22fd0fab | 7314 | drm_i915_private_t *dev_priv = dev->dev_private; |
79e53945 JB |
7315 | struct intel_crtc *intel_crtc; |
7316 | int i; | |
7317 | ||
7318 | intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); | |
7319 | if (intel_crtc == NULL) | |
7320 | return; | |
7321 | ||
7322 | drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs); | |
7323 | ||
7324 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
7325 | for (i = 0; i < 256; i++) { |
7326 | intel_crtc->lut_r[i] = i; | |
7327 | intel_crtc->lut_g[i] = i; | |
7328 | intel_crtc->lut_b[i] = i; | |
7329 | } | |
7330 | ||
80824003 JB |
7331 | /* Swap pipes & planes for FBC on pre-965 */ |
7332 | intel_crtc->pipe = pipe; | |
7333 | intel_crtc->plane = pipe; | |
e2e767ab | 7334 | if (IS_MOBILE(dev) && IS_GEN3(dev)) { |
28c97730 | 7335 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 7336 | intel_crtc->plane = !pipe; |
80824003 JB |
7337 | } |
7338 | ||
22fd0fab JB |
7339 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
7340 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
7341 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
7342 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
7343 | ||
5d1d0cc8 | 7344 | intel_crtc_reset(&intel_crtc->base); |
04dbff52 | 7345 | intel_crtc->active = true; /* force the pipe off on setup_init_config */ |
5a354204 | 7346 | intel_crtc->bpp = 24; /* default for pre-Ironlake */ |
7e7d76c3 JB |
7347 | |
7348 | if (HAS_PCH_SPLIT(dev)) { | |
4b645f14 JB |
7349 | if (pipe == 2 && IS_IVYBRIDGE(dev)) |
7350 | intel_crtc->no_pll = true; | |
7e7d76c3 JB |
7351 | intel_helper_funcs.prepare = ironlake_crtc_prepare; |
7352 | intel_helper_funcs.commit = ironlake_crtc_commit; | |
7353 | } else { | |
7354 | intel_helper_funcs.prepare = i9xx_crtc_prepare; | |
7355 | intel_helper_funcs.commit = i9xx_crtc_commit; | |
7356 | } | |
7357 | ||
79e53945 JB |
7358 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
7359 | ||
652c393a JB |
7360 | intel_crtc->busy = false; |
7361 | ||
7362 | setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer, | |
7363 | (unsigned long)intel_crtc); | |
79e53945 JB |
7364 | } |
7365 | ||
08d7b3d1 | 7366 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 7367 | struct drm_file *file) |
08d7b3d1 CW |
7368 | { |
7369 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7370 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; | |
c05422d5 DV |
7371 | struct drm_mode_object *drmmode_obj; |
7372 | struct intel_crtc *crtc; | |
08d7b3d1 CW |
7373 | |
7374 | if (!dev_priv) { | |
7375 | DRM_ERROR("called with no initialization\n"); | |
7376 | return -EINVAL; | |
7377 | } | |
7378 | ||
c05422d5 DV |
7379 | drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, |
7380 | DRM_MODE_OBJECT_CRTC); | |
08d7b3d1 | 7381 | |
c05422d5 | 7382 | if (!drmmode_obj) { |
08d7b3d1 CW |
7383 | DRM_ERROR("no such CRTC id\n"); |
7384 | return -EINVAL; | |
7385 | } | |
7386 | ||
c05422d5 DV |
7387 | crtc = to_intel_crtc(obj_to_crtc(drmmode_obj)); |
7388 | pipe_from_crtc_id->pipe = crtc->pipe; | |
08d7b3d1 | 7389 | |
c05422d5 | 7390 | return 0; |
08d7b3d1 CW |
7391 | } |
7392 | ||
c5e4df33 | 7393 | static int intel_encoder_clones(struct drm_device *dev, int type_mask) |
79e53945 | 7394 | { |
4ef69c7a | 7395 | struct intel_encoder *encoder; |
79e53945 | 7396 | int index_mask = 0; |
79e53945 JB |
7397 | int entry = 0; |
7398 | ||
4ef69c7a CW |
7399 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
7400 | if (type_mask & encoder->clone_mask) | |
79e53945 JB |
7401 | index_mask |= (1 << entry); |
7402 | entry++; | |
7403 | } | |
4ef69c7a | 7404 | |
79e53945 JB |
7405 | return index_mask; |
7406 | } | |
7407 | ||
4d302442 CW |
7408 | static bool has_edp_a(struct drm_device *dev) |
7409 | { | |
7410 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7411 | ||
7412 | if (!IS_MOBILE(dev)) | |
7413 | return false; | |
7414 | ||
7415 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
7416 | return false; | |
7417 | ||
7418 | if (IS_GEN5(dev) && | |
7419 | (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE)) | |
7420 | return false; | |
7421 | ||
7422 | return true; | |
7423 | } | |
7424 | ||
79e53945 JB |
7425 | static void intel_setup_outputs(struct drm_device *dev) |
7426 | { | |
725e30ad | 7427 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 7428 | struct intel_encoder *encoder; |
cb0953d7 | 7429 | bool dpd_is_edp = false; |
c5d1b51d | 7430 | bool has_lvds = false; |
79e53945 | 7431 | |
541998a1 | 7432 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
c5d1b51d CW |
7433 | has_lvds = intel_lvds_init(dev); |
7434 | if (!has_lvds && !HAS_PCH_SPLIT(dev)) { | |
7435 | /* disable the panel fitter on everything but LVDS */ | |
7436 | I915_WRITE(PFIT_CONTROL, 0); | |
7437 | } | |
79e53945 | 7438 | |
bad720ff | 7439 | if (HAS_PCH_SPLIT(dev)) { |
cb0953d7 | 7440 | dpd_is_edp = intel_dpd_is_edp(dev); |
30ad48b7 | 7441 | |
4d302442 | 7442 | if (has_edp_a(dev)) |
32f9d658 ZW |
7443 | intel_dp_init(dev, DP_A); |
7444 | ||
cb0953d7 AJ |
7445 | if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED)) |
7446 | intel_dp_init(dev, PCH_DP_D); | |
7447 | } | |
7448 | ||
7449 | intel_crt_init(dev); | |
7450 | ||
7451 | if (HAS_PCH_SPLIT(dev)) { | |
7452 | int found; | |
7453 | ||
30ad48b7 | 7454 | if (I915_READ(HDMIB) & PORT_DETECTED) { |
461ed3ca ZY |
7455 | /* PCH SDVOB multiplex with HDMIB */ |
7456 | found = intel_sdvo_init(dev, PCH_SDVOB); | |
30ad48b7 ZW |
7457 | if (!found) |
7458 | intel_hdmi_init(dev, HDMIB); | |
5eb08b69 ZW |
7459 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
7460 | intel_dp_init(dev, PCH_DP_B); | |
30ad48b7 ZW |
7461 | } |
7462 | ||
7463 | if (I915_READ(HDMIC) & PORT_DETECTED) | |
7464 | intel_hdmi_init(dev, HDMIC); | |
7465 | ||
7466 | if (I915_READ(HDMID) & PORT_DETECTED) | |
7467 | intel_hdmi_init(dev, HDMID); | |
7468 | ||
5eb08b69 ZW |
7469 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
7470 | intel_dp_init(dev, PCH_DP_C); | |
7471 | ||
cb0953d7 | 7472 | if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED)) |
5eb08b69 ZW |
7473 | intel_dp_init(dev, PCH_DP_D); |
7474 | ||
103a196f | 7475 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
27185ae1 | 7476 | bool found = false; |
7d57382e | 7477 | |
725e30ad | 7478 | if (I915_READ(SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 7479 | DRM_DEBUG_KMS("probing SDVOB\n"); |
725e30ad | 7480 | found = intel_sdvo_init(dev, SDVOB); |
b01f2c3a JB |
7481 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
7482 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); | |
725e30ad | 7483 | intel_hdmi_init(dev, SDVOB); |
b01f2c3a | 7484 | } |
27185ae1 | 7485 | |
b01f2c3a JB |
7486 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) { |
7487 | DRM_DEBUG_KMS("probing DP_B\n"); | |
a4fc5ed6 | 7488 | intel_dp_init(dev, DP_B); |
b01f2c3a | 7489 | } |
725e30ad | 7490 | } |
13520b05 KH |
7491 | |
7492 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 7493 | |
b01f2c3a JB |
7494 | if (I915_READ(SDVOB) & SDVO_DETECTED) { |
7495 | DRM_DEBUG_KMS("probing SDVOC\n"); | |
725e30ad | 7496 | found = intel_sdvo_init(dev, SDVOC); |
b01f2c3a | 7497 | } |
27185ae1 ML |
7498 | |
7499 | if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) { | |
7500 | ||
b01f2c3a JB |
7501 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
7502 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); | |
725e30ad | 7503 | intel_hdmi_init(dev, SDVOC); |
b01f2c3a JB |
7504 | } |
7505 | if (SUPPORTS_INTEGRATED_DP(dev)) { | |
7506 | DRM_DEBUG_KMS("probing DP_C\n"); | |
a4fc5ed6 | 7507 | intel_dp_init(dev, DP_C); |
b01f2c3a | 7508 | } |
725e30ad | 7509 | } |
27185ae1 | 7510 | |
b01f2c3a JB |
7511 | if (SUPPORTS_INTEGRATED_DP(dev) && |
7512 | (I915_READ(DP_D) & DP_DETECTED)) { | |
7513 | DRM_DEBUG_KMS("probing DP_D\n"); | |
a4fc5ed6 | 7514 | intel_dp_init(dev, DP_D); |
b01f2c3a | 7515 | } |
bad720ff | 7516 | } else if (IS_GEN2(dev)) |
79e53945 JB |
7517 | intel_dvo_init(dev); |
7518 | ||
103a196f | 7519 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
7520 | intel_tv_init(dev); |
7521 | ||
4ef69c7a CW |
7522 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
7523 | encoder->base.possible_crtcs = encoder->crtc_mask; | |
7524 | encoder->base.possible_clones = | |
7525 | intel_encoder_clones(dev, encoder->clone_mask); | |
79e53945 | 7526 | } |
47356eb6 | 7527 | |
2c7111db CW |
7528 | /* disable all the possible outputs/crtcs before entering KMS mode */ |
7529 | drm_helper_disable_unused_functions(dev); | |
9fb526db KP |
7530 | |
7531 | if (HAS_PCH_SPLIT(dev)) | |
7532 | ironlake_init_pch_refclk(dev); | |
79e53945 JB |
7533 | } |
7534 | ||
7535 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
7536 | { | |
7537 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
79e53945 JB |
7538 | |
7539 | drm_framebuffer_cleanup(fb); | |
05394f39 | 7540 | drm_gem_object_unreference_unlocked(&intel_fb->obj->base); |
79e53945 JB |
7541 | |
7542 | kfree(intel_fb); | |
7543 | } | |
7544 | ||
7545 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 7546 | struct drm_file *file, |
79e53945 JB |
7547 | unsigned int *handle) |
7548 | { | |
7549 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 7550 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 7551 | |
05394f39 | 7552 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
7553 | } |
7554 | ||
7555 | static const struct drm_framebuffer_funcs intel_fb_funcs = { | |
7556 | .destroy = intel_user_framebuffer_destroy, | |
7557 | .create_handle = intel_user_framebuffer_create_handle, | |
7558 | }; | |
7559 | ||
38651674 DA |
7560 | int intel_framebuffer_init(struct drm_device *dev, |
7561 | struct intel_framebuffer *intel_fb, | |
7562 | struct drm_mode_fb_cmd *mode_cmd, | |
05394f39 | 7563 | struct drm_i915_gem_object *obj) |
79e53945 | 7564 | { |
79e53945 JB |
7565 | int ret; |
7566 | ||
05394f39 | 7567 | if (obj->tiling_mode == I915_TILING_Y) |
57cd6508 CW |
7568 | return -EINVAL; |
7569 | ||
7570 | if (mode_cmd->pitch & 63) | |
7571 | return -EINVAL; | |
7572 | ||
7573 | switch (mode_cmd->bpp) { | |
7574 | case 8: | |
7575 | case 16: | |
b5626747 JB |
7576 | /* Only pre-ILK can handle 5:5:5 */ |
7577 | if (mode_cmd->depth == 15 && !HAS_PCH_SPLIT(dev)) | |
7578 | return -EINVAL; | |
7579 | break; | |
7580 | ||
57cd6508 CW |
7581 | case 24: |
7582 | case 32: | |
7583 | break; | |
7584 | default: | |
7585 | return -EINVAL; | |
7586 | } | |
7587 | ||
79e53945 JB |
7588 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
7589 | if (ret) { | |
7590 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
7591 | return ret; | |
7592 | } | |
7593 | ||
7594 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); | |
79e53945 | 7595 | intel_fb->obj = obj; |
79e53945 JB |
7596 | return 0; |
7597 | } | |
7598 | ||
79e53945 JB |
7599 | static struct drm_framebuffer * |
7600 | intel_user_framebuffer_create(struct drm_device *dev, | |
7601 | struct drm_file *filp, | |
7602 | struct drm_mode_fb_cmd *mode_cmd) | |
7603 | { | |
05394f39 | 7604 | struct drm_i915_gem_object *obj; |
79e53945 | 7605 | |
05394f39 | 7606 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle)); |
c8725226 | 7607 | if (&obj->base == NULL) |
cce13ff7 | 7608 | return ERR_PTR(-ENOENT); |
79e53945 | 7609 | |
d2dff872 | 7610 | return intel_framebuffer_create(dev, mode_cmd, obj); |
79e53945 JB |
7611 | } |
7612 | ||
79e53945 | 7613 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 7614 | .fb_create = intel_user_framebuffer_create, |
eb1f8e4f | 7615 | .output_poll_changed = intel_fb_output_poll_changed, |
79e53945 JB |
7616 | }; |
7617 | ||
05394f39 | 7618 | static struct drm_i915_gem_object * |
aa40d6bb | 7619 | intel_alloc_context_page(struct drm_device *dev) |
9ea8d059 | 7620 | { |
05394f39 | 7621 | struct drm_i915_gem_object *ctx; |
9ea8d059 CW |
7622 | int ret; |
7623 | ||
2c34b850 BW |
7624 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
7625 | ||
aa40d6bb ZN |
7626 | ctx = i915_gem_alloc_object(dev, 4096); |
7627 | if (!ctx) { | |
9ea8d059 CW |
7628 | DRM_DEBUG("failed to alloc power context, RC6 disabled\n"); |
7629 | return NULL; | |
7630 | } | |
7631 | ||
75e9e915 | 7632 | ret = i915_gem_object_pin(ctx, 4096, true); |
9ea8d059 CW |
7633 | if (ret) { |
7634 | DRM_ERROR("failed to pin power context: %d\n", ret); | |
7635 | goto err_unref; | |
7636 | } | |
7637 | ||
aa40d6bb | 7638 | ret = i915_gem_object_set_to_gtt_domain(ctx, 1); |
9ea8d059 CW |
7639 | if (ret) { |
7640 | DRM_ERROR("failed to set-domain on power context: %d\n", ret); | |
7641 | goto err_unpin; | |
7642 | } | |
9ea8d059 | 7643 | |
aa40d6bb | 7644 | return ctx; |
9ea8d059 CW |
7645 | |
7646 | err_unpin: | |
aa40d6bb | 7647 | i915_gem_object_unpin(ctx); |
9ea8d059 | 7648 | err_unref: |
05394f39 | 7649 | drm_gem_object_unreference(&ctx->base); |
9ea8d059 CW |
7650 | mutex_unlock(&dev->struct_mutex); |
7651 | return NULL; | |
7652 | } | |
7653 | ||
7648fa99 JB |
7654 | bool ironlake_set_drps(struct drm_device *dev, u8 val) |
7655 | { | |
7656 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7657 | u16 rgvswctl; | |
7658 | ||
7659 | rgvswctl = I915_READ16(MEMSWCTL); | |
7660 | if (rgvswctl & MEMCTL_CMD_STS) { | |
7661 | DRM_DEBUG("gpu busy, RCS change rejected\n"); | |
7662 | return false; /* still busy with another command */ | |
7663 | } | |
7664 | ||
7665 | rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) | | |
7666 | (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM; | |
7667 | I915_WRITE16(MEMSWCTL, rgvswctl); | |
7668 | POSTING_READ16(MEMSWCTL); | |
7669 | ||
7670 | rgvswctl |= MEMCTL_CMD_STS; | |
7671 | I915_WRITE16(MEMSWCTL, rgvswctl); | |
7672 | ||
7673 | return true; | |
7674 | } | |
7675 | ||
f97108d1 JB |
7676 | void ironlake_enable_drps(struct drm_device *dev) |
7677 | { | |
7678 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7648fa99 | 7679 | u32 rgvmodectl = I915_READ(MEMMODECTL); |
f97108d1 | 7680 | u8 fmax, fmin, fstart, vstart; |
f97108d1 | 7681 | |
ea056c14 JB |
7682 | /* Enable temp reporting */ |
7683 | I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN); | |
7684 | I915_WRITE16(TSC1, I915_READ(TSC1) | TSE); | |
7685 | ||
f97108d1 JB |
7686 | /* 100ms RC evaluation intervals */ |
7687 | I915_WRITE(RCUPEI, 100000); | |
7688 | I915_WRITE(RCDNEI, 100000); | |
7689 | ||
7690 | /* Set max/min thresholds to 90ms and 80ms respectively */ | |
7691 | I915_WRITE(RCBMAXAVG, 90000); | |
7692 | I915_WRITE(RCBMINAVG, 80000); | |
7693 | ||
7694 | I915_WRITE(MEMIHYST, 1); | |
7695 | ||
7696 | /* Set up min, max, and cur for interrupt handling */ | |
7697 | fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT; | |
7698 | fmin = (rgvmodectl & MEMMODE_FMIN_MASK); | |
7699 | fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >> | |
7700 | MEMMODE_FSTART_SHIFT; | |
7648fa99 | 7701 | |
f97108d1 JB |
7702 | vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >> |
7703 | PXVFREQ_PX_SHIFT; | |
7704 | ||
80dbf4b7 | 7705 | dev_priv->fmax = fmax; /* IPS callback will increase this */ |
7648fa99 JB |
7706 | dev_priv->fstart = fstart; |
7707 | ||
80dbf4b7 | 7708 | dev_priv->max_delay = fstart; |
f97108d1 JB |
7709 | dev_priv->min_delay = fmin; |
7710 | dev_priv->cur_delay = fstart; | |
7711 | ||
80dbf4b7 JB |
7712 | DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", |
7713 | fmax, fmin, fstart); | |
7648fa99 | 7714 | |
f97108d1 JB |
7715 | I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN); |
7716 | ||
7717 | /* | |
7718 | * Interrupts will be enabled in ironlake_irq_postinstall | |
7719 | */ | |
7720 | ||
7721 | I915_WRITE(VIDSTART, vstart); | |
7722 | POSTING_READ(VIDSTART); | |
7723 | ||
7724 | rgvmodectl |= MEMMODE_SWMODE_EN; | |
7725 | I915_WRITE(MEMMODECTL, rgvmodectl); | |
7726 | ||
481b6af3 | 7727 | if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10)) |
913d8d11 | 7728 | DRM_ERROR("stuck trying to change perf mode\n"); |
f97108d1 JB |
7729 | msleep(1); |
7730 | ||
7648fa99 | 7731 | ironlake_set_drps(dev, fstart); |
f97108d1 | 7732 | |
7648fa99 JB |
7733 | dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) + |
7734 | I915_READ(0x112e0); | |
7735 | dev_priv->last_time1 = jiffies_to_msecs(jiffies); | |
7736 | dev_priv->last_count2 = I915_READ(0x112f4); | |
7737 | getrawmonotonic(&dev_priv->last_time2); | |
f97108d1 JB |
7738 | } |
7739 | ||
7740 | void ironlake_disable_drps(struct drm_device *dev) | |
7741 | { | |
7742 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7648fa99 | 7743 | u16 rgvswctl = I915_READ16(MEMSWCTL); |
f97108d1 JB |
7744 | |
7745 | /* Ack interrupts, disable EFC interrupt */ | |
7746 | I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN); | |
7747 | I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG); | |
7748 | I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT); | |
7749 | I915_WRITE(DEIIR, DE_PCU_EVENT); | |
7750 | I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT); | |
7751 | ||
7752 | /* Go back to the starting frequency */ | |
7648fa99 | 7753 | ironlake_set_drps(dev, dev_priv->fstart); |
f97108d1 JB |
7754 | msleep(1); |
7755 | rgvswctl |= MEMCTL_CMD_STS; | |
7756 | I915_WRITE(MEMSWCTL, rgvswctl); | |
7757 | msleep(1); | |
7758 | ||
7759 | } | |
7760 | ||
3b8d8d91 JB |
7761 | void gen6_set_rps(struct drm_device *dev, u8 val) |
7762 | { | |
7763 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7764 | u32 swreq; | |
7765 | ||
7766 | swreq = (val & 0x3ff) << 25; | |
7767 | I915_WRITE(GEN6_RPNSWREQ, swreq); | |
7768 | } | |
7769 | ||
7770 | void gen6_disable_rps(struct drm_device *dev) | |
7771 | { | |
7772 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7773 | ||
7774 | I915_WRITE(GEN6_RPNSWREQ, 1 << 31); | |
7775 | I915_WRITE(GEN6_PMINTRMSK, 0xffffffff); | |
7776 | I915_WRITE(GEN6_PMIER, 0); | |
6fdd4d98 DV |
7777 | /* Complete PM interrupt masking here doesn't race with the rps work |
7778 | * item again unmasking PM interrupts because that is using a different | |
7779 | * register (PMIMR) to mask PM interrupts. The only risk is in leaving | |
7780 | * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */ | |
4912d041 BW |
7781 | |
7782 | spin_lock_irq(&dev_priv->rps_lock); | |
7783 | dev_priv->pm_iir = 0; | |
7784 | spin_unlock_irq(&dev_priv->rps_lock); | |
7785 | ||
3b8d8d91 JB |
7786 | I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR)); |
7787 | } | |
7788 | ||
7648fa99 JB |
7789 | static unsigned long intel_pxfreq(u32 vidfreq) |
7790 | { | |
7791 | unsigned long freq; | |
7792 | int div = (vidfreq & 0x3f0000) >> 16; | |
7793 | int post = (vidfreq & 0x3000) >> 12; | |
7794 | int pre = (vidfreq & 0x7); | |
7795 | ||
7796 | if (!pre) | |
7797 | return 0; | |
7798 | ||
7799 | freq = ((div * 133333) / ((1<<post) * pre)); | |
7800 | ||
7801 | return freq; | |
7802 | } | |
7803 | ||
7804 | void intel_init_emon(struct drm_device *dev) | |
7805 | { | |
7806 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7807 | u32 lcfuse; | |
7808 | u8 pxw[16]; | |
7809 | int i; | |
7810 | ||
7811 | /* Disable to program */ | |
7812 | I915_WRITE(ECR, 0); | |
7813 | POSTING_READ(ECR); | |
7814 | ||
7815 | /* Program energy weights for various events */ | |
7816 | I915_WRITE(SDEW, 0x15040d00); | |
7817 | I915_WRITE(CSIEW0, 0x007f0000); | |
7818 | I915_WRITE(CSIEW1, 0x1e220004); | |
7819 | I915_WRITE(CSIEW2, 0x04000004); | |
7820 | ||
7821 | for (i = 0; i < 5; i++) | |
7822 | I915_WRITE(PEW + (i * 4), 0); | |
7823 | for (i = 0; i < 3; i++) | |
7824 | I915_WRITE(DEW + (i * 4), 0); | |
7825 | ||
7826 | /* Program P-state weights to account for frequency power adjustment */ | |
7827 | for (i = 0; i < 16; i++) { | |
7828 | u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4)); | |
7829 | unsigned long freq = intel_pxfreq(pxvidfreq); | |
7830 | unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >> | |
7831 | PXVFREQ_PX_SHIFT; | |
7832 | unsigned long val; | |
7833 | ||
7834 | val = vid * vid; | |
7835 | val *= (freq / 1000); | |
7836 | val *= 255; | |
7837 | val /= (127*127*900); | |
7838 | if (val > 0xff) | |
7839 | DRM_ERROR("bad pxval: %ld\n", val); | |
7840 | pxw[i] = val; | |
7841 | } | |
7842 | /* Render standby states get 0 weight */ | |
7843 | pxw[14] = 0; | |
7844 | pxw[15] = 0; | |
7845 | ||
7846 | for (i = 0; i < 4; i++) { | |
7847 | u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) | | |
7848 | (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]); | |
7849 | I915_WRITE(PXW + (i * 4), val); | |
7850 | } | |
7851 | ||
7852 | /* Adjust magic regs to magic values (more experimental results) */ | |
7853 | I915_WRITE(OGW0, 0); | |
7854 | I915_WRITE(OGW1, 0); | |
7855 | I915_WRITE(EG0, 0x00007f00); | |
7856 | I915_WRITE(EG1, 0x0000000e); | |
7857 | I915_WRITE(EG2, 0x000e0000); | |
7858 | I915_WRITE(EG3, 0x68000300); | |
7859 | I915_WRITE(EG4, 0x42000000); | |
7860 | I915_WRITE(EG5, 0x00140031); | |
7861 | I915_WRITE(EG6, 0); | |
7862 | I915_WRITE(EG7, 0); | |
7863 | ||
7864 | for (i = 0; i < 8; i++) | |
7865 | I915_WRITE(PXWL + (i * 4), 0); | |
7866 | ||
7867 | /* Enable PMON + select events */ | |
7868 | I915_WRITE(ECR, 0x80000019); | |
7869 | ||
7870 | lcfuse = I915_READ(LCFUSE02); | |
7871 | ||
7872 | dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK); | |
7873 | } | |
7874 | ||
3b8d8d91 | 7875 | void gen6_enable_rps(struct drm_i915_private *dev_priv) |
8fd26859 | 7876 | { |
a6044e23 JB |
7877 | u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); |
7878 | u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); | |
7df8721b | 7879 | u32 pcu_mbox, rc6_mask = 0; |
a6044e23 | 7880 | int cur_freq, min_freq, max_freq; |
8fd26859 CW |
7881 | int i; |
7882 | ||
7883 | /* Here begins a magic sequence of register writes to enable | |
7884 | * auto-downclocking. | |
7885 | * | |
7886 | * Perhaps there might be some value in exposing these to | |
7887 | * userspace... | |
7888 | */ | |
7889 | I915_WRITE(GEN6_RC_STATE, 0); | |
d1ebd816 | 7890 | mutex_lock(&dev_priv->dev->struct_mutex); |
fcca7926 | 7891 | gen6_gt_force_wake_get(dev_priv); |
8fd26859 | 7892 | |
3b8d8d91 | 7893 | /* disable the counters and set deterministic thresholds */ |
8fd26859 CW |
7894 | I915_WRITE(GEN6_RC_CONTROL, 0); |
7895 | ||
7896 | I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16); | |
7897 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30); | |
7898 | I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30); | |
7899 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); | |
7900 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); | |
7901 | ||
7902 | for (i = 0; i < I915_NUM_RINGS; i++) | |
7903 | I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10); | |
7904 | ||
7905 | I915_WRITE(GEN6_RC_SLEEP, 0); | |
7906 | I915_WRITE(GEN6_RC1e_THRESHOLD, 1000); | |
7907 | I915_WRITE(GEN6_RC6_THRESHOLD, 50000); | |
7908 | I915_WRITE(GEN6_RC6p_THRESHOLD, 100000); | |
7909 | I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */ | |
7910 | ||
7df8721b JB |
7911 | if (i915_enable_rc6) |
7912 | rc6_mask = GEN6_RC_CTL_RC6p_ENABLE | | |
7913 | GEN6_RC_CTL_RC6_ENABLE; | |
7914 | ||
8fd26859 | 7915 | I915_WRITE(GEN6_RC_CONTROL, |
7df8721b | 7916 | rc6_mask | |
9c3d2f7f | 7917 | GEN6_RC_CTL_EI_MODE(1) | |
8fd26859 CW |
7918 | GEN6_RC_CTL_HW_ENABLE); |
7919 | ||
3b8d8d91 | 7920 | I915_WRITE(GEN6_RPNSWREQ, |
8fd26859 CW |
7921 | GEN6_FREQUENCY(10) | |
7922 | GEN6_OFFSET(0) | | |
7923 | GEN6_AGGRESSIVE_TURBO); | |
7924 | I915_WRITE(GEN6_RC_VIDEO_FREQ, | |
7925 | GEN6_FREQUENCY(12)); | |
7926 | ||
7927 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); | |
7928 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, | |
7929 | 18 << 24 | | |
7930 | 6 << 16); | |
ccab5c82 JB |
7931 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000); |
7932 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000); | |
8fd26859 | 7933 | I915_WRITE(GEN6_RP_UP_EI, 100000); |
ccab5c82 | 7934 | I915_WRITE(GEN6_RP_DOWN_EI, 5000000); |
8fd26859 CW |
7935 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); |
7936 | I915_WRITE(GEN6_RP_CONTROL, | |
7937 | GEN6_RP_MEDIA_TURBO | | |
7938 | GEN6_RP_USE_NORMAL_FREQ | | |
7939 | GEN6_RP_MEDIA_IS_GFX | | |
7940 | GEN6_RP_ENABLE | | |
ccab5c82 JB |
7941 | GEN6_RP_UP_BUSY_AVG | |
7942 | GEN6_RP_DOWN_IDLE_CONT); | |
8fd26859 CW |
7943 | |
7944 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, | |
7945 | 500)) | |
7946 | DRM_ERROR("timeout waiting for pcode mailbox to become idle\n"); | |
7947 | ||
7948 | I915_WRITE(GEN6_PCODE_DATA, 0); | |
7949 | I915_WRITE(GEN6_PCODE_MAILBOX, | |
7950 | GEN6_PCODE_READY | | |
7951 | GEN6_PCODE_WRITE_MIN_FREQ_TABLE); | |
7952 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, | |
7953 | 500)) | |
7954 | DRM_ERROR("timeout waiting for pcode mailbox to finish\n"); | |
7955 | ||
a6044e23 JB |
7956 | min_freq = (rp_state_cap & 0xff0000) >> 16; |
7957 | max_freq = rp_state_cap & 0xff; | |
7958 | cur_freq = (gt_perf_status & 0xff00) >> 8; | |
7959 | ||
7960 | /* Check for overclock support */ | |
7961 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, | |
7962 | 500)) | |
7963 | DRM_ERROR("timeout waiting for pcode mailbox to become idle\n"); | |
7964 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS); | |
7965 | pcu_mbox = I915_READ(GEN6_PCODE_DATA); | |
7966 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, | |
7967 | 500)) | |
7968 | DRM_ERROR("timeout waiting for pcode mailbox to finish\n"); | |
7969 | if (pcu_mbox & (1<<31)) { /* OC supported */ | |
7970 | max_freq = pcu_mbox & 0xff; | |
e281fcaa | 7971 | DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50); |
a6044e23 JB |
7972 | } |
7973 | ||
7974 | /* In units of 100MHz */ | |
7975 | dev_priv->max_delay = max_freq; | |
7976 | dev_priv->min_delay = min_freq; | |
7977 | dev_priv->cur_delay = cur_freq; | |
7978 | ||
8fd26859 CW |
7979 | /* requires MSI enabled */ |
7980 | I915_WRITE(GEN6_PMIER, | |
7981 | GEN6_PM_MBOX_EVENT | | |
7982 | GEN6_PM_THERMAL_EVENT | | |
7983 | GEN6_PM_RP_DOWN_TIMEOUT | | |
7984 | GEN6_PM_RP_UP_THRESHOLD | | |
7985 | GEN6_PM_RP_DOWN_THRESHOLD | | |
7986 | GEN6_PM_RP_UP_EI_EXPIRED | | |
7987 | GEN6_PM_RP_DOWN_EI_EXPIRED); | |
4912d041 BW |
7988 | spin_lock_irq(&dev_priv->rps_lock); |
7989 | WARN_ON(dev_priv->pm_iir != 0); | |
3b8d8d91 | 7990 | I915_WRITE(GEN6_PMIMR, 0); |
4912d041 | 7991 | spin_unlock_irq(&dev_priv->rps_lock); |
3b8d8d91 JB |
7992 | /* enable all PM interrupts */ |
7993 | I915_WRITE(GEN6_PMINTRMSK, 0); | |
8fd26859 | 7994 | |
fcca7926 | 7995 | gen6_gt_force_wake_put(dev_priv); |
d1ebd816 | 7996 | mutex_unlock(&dev_priv->dev->struct_mutex); |
8fd26859 CW |
7997 | } |
7998 | ||
23b2f8bb JB |
7999 | void gen6_update_ring_freq(struct drm_i915_private *dev_priv) |
8000 | { | |
8001 | int min_freq = 15; | |
8002 | int gpu_freq, ia_freq, max_ia_freq; | |
8003 | int scaling_factor = 180; | |
8004 | ||
8005 | max_ia_freq = cpufreq_quick_get_max(0); | |
8006 | /* | |
8007 | * Default to measured freq if none found, PCU will ensure we don't go | |
8008 | * over | |
8009 | */ | |
8010 | if (!max_ia_freq) | |
8011 | max_ia_freq = tsc_khz; | |
8012 | ||
8013 | /* Convert from kHz to MHz */ | |
8014 | max_ia_freq /= 1000; | |
8015 | ||
8016 | mutex_lock(&dev_priv->dev->struct_mutex); | |
8017 | ||
8018 | /* | |
8019 | * For each potential GPU frequency, load a ring frequency we'd like | |
8020 | * to use for memory access. We do this by specifying the IA frequency | |
8021 | * the PCU should use as a reference to determine the ring frequency. | |
8022 | */ | |
8023 | for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay; | |
8024 | gpu_freq--) { | |
8025 | int diff = dev_priv->max_delay - gpu_freq; | |
8026 | ||
8027 | /* | |
8028 | * For GPU frequencies less than 750MHz, just use the lowest | |
8029 | * ring freq. | |
8030 | */ | |
8031 | if (gpu_freq < min_freq) | |
8032 | ia_freq = 800; | |
8033 | else | |
8034 | ia_freq = max_ia_freq - ((diff * scaling_factor) / 2); | |
8035 | ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100); | |
8036 | ||
8037 | I915_WRITE(GEN6_PCODE_DATA, | |
8038 | (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) | | |
8039 | gpu_freq); | |
8040 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | | |
8041 | GEN6_PCODE_WRITE_MIN_FREQ_TABLE); | |
8042 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & | |
8043 | GEN6_PCODE_READY) == 0, 10)) { | |
8044 | DRM_ERROR("pcode write of freq table timed out\n"); | |
8045 | continue; | |
8046 | } | |
8047 | } | |
8048 | ||
8049 | mutex_unlock(&dev_priv->dev->struct_mutex); | |
8050 | } | |
8051 | ||
6067aaea JB |
8052 | static void ironlake_init_clock_gating(struct drm_device *dev) |
8053 | { | |
8054 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8055 | uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE; | |
8056 | ||
8057 | /* Required for FBC */ | |
8058 | dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE | | |
8059 | DPFCRUNIT_CLOCK_GATE_DISABLE | | |
8060 | DPFDUNIT_CLOCK_GATE_DISABLE; | |
8061 | /* Required for CxSR */ | |
8062 | dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE; | |
8063 | ||
8064 | I915_WRITE(PCH_3DCGDIS0, | |
8065 | MARIUNIT_CLOCK_GATE_DISABLE | | |
8066 | SVSMUNIT_CLOCK_GATE_DISABLE); | |
8067 | I915_WRITE(PCH_3DCGDIS1, | |
8068 | VFMUNIT_CLOCK_GATE_DISABLE); | |
8069 | ||
8070 | I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate); | |
8071 | ||
6067aaea JB |
8072 | /* |
8073 | * According to the spec the following bits should be set in | |
8074 | * order to enable memory self-refresh | |
8075 | * The bit 22/21 of 0x42004 | |
8076 | * The bit 5 of 0x42020 | |
8077 | * The bit 15 of 0x45000 | |
8078 | */ | |
8079 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
8080 | (I915_READ(ILK_DISPLAY_CHICKEN2) | | |
8081 | ILK_DPARB_GATE | ILK_VSDPFD_FULL)); | |
8082 | I915_WRITE(ILK_DSPCLK_GATE, | |
8083 | (I915_READ(ILK_DSPCLK_GATE) | | |
8084 | ILK_DPARB_CLK_GATE)); | |
8085 | I915_WRITE(DISP_ARB_CTL, | |
8086 | (I915_READ(DISP_ARB_CTL) | | |
8087 | DISP_FBC_WM_DIS)); | |
8088 | I915_WRITE(WM3_LP_ILK, 0); | |
8089 | I915_WRITE(WM2_LP_ILK, 0); | |
8090 | I915_WRITE(WM1_LP_ILK, 0); | |
8091 | ||
8092 | /* | |
8093 | * Based on the document from hardware guys the following bits | |
8094 | * should be set unconditionally in order to enable FBC. | |
8095 | * The bit 22 of 0x42000 | |
8096 | * The bit 22 of 0x42004 | |
8097 | * The bit 7,8,9 of 0x42020. | |
8098 | */ | |
8099 | if (IS_IRONLAKE_M(dev)) { | |
8100 | I915_WRITE(ILK_DISPLAY_CHICKEN1, | |
8101 | I915_READ(ILK_DISPLAY_CHICKEN1) | | |
8102 | ILK_FBCQ_DIS); | |
8103 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
8104 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
8105 | ILK_DPARB_GATE); | |
8106 | I915_WRITE(ILK_DSPCLK_GATE, | |
8107 | I915_READ(ILK_DSPCLK_GATE) | | |
8108 | ILK_DPFC_DIS1 | | |
8109 | ILK_DPFC_DIS2 | | |
8110 | ILK_CLK_FBC); | |
8111 | } | |
8112 | ||
8113 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
8114 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
8115 | ILK_ELPIN_409_SELECT); | |
8116 | I915_WRITE(_3D_CHICKEN2, | |
8117 | _3D_CHICKEN2_WM_READ_PIPELINED << 16 | | |
8118 | _3D_CHICKEN2_WM_READ_PIPELINED); | |
8fd26859 CW |
8119 | } |
8120 | ||
6067aaea | 8121 | static void gen6_init_clock_gating(struct drm_device *dev) |
652c393a JB |
8122 | { |
8123 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9db4a9c7 | 8124 | int pipe; |
6067aaea JB |
8125 | uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE; |
8126 | ||
8127 | I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate); | |
652c393a | 8128 | |
6067aaea JB |
8129 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
8130 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
8131 | ILK_ELPIN_409_SELECT); | |
8956c8bb | 8132 | |
6067aaea JB |
8133 | I915_WRITE(WM3_LP_ILK, 0); |
8134 | I915_WRITE(WM2_LP_ILK, 0); | |
8135 | I915_WRITE(WM1_LP_ILK, 0); | |
652c393a JB |
8136 | |
8137 | /* | |
6067aaea JB |
8138 | * According to the spec the following bits should be |
8139 | * set in order to enable memory self-refresh and fbc: | |
8140 | * The bit21 and bit22 of 0x42000 | |
8141 | * The bit21 and bit22 of 0x42004 | |
8142 | * The bit5 and bit7 of 0x42020 | |
8143 | * The bit14 of 0x70180 | |
8144 | * The bit14 of 0x71180 | |
652c393a | 8145 | */ |
6067aaea JB |
8146 | I915_WRITE(ILK_DISPLAY_CHICKEN1, |
8147 | I915_READ(ILK_DISPLAY_CHICKEN1) | | |
8148 | ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS); | |
8149 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
8150 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
8151 | ILK_DPARB_GATE | ILK_VSDPFD_FULL); | |
8152 | I915_WRITE(ILK_DSPCLK_GATE, | |
8153 | I915_READ(ILK_DSPCLK_GATE) | | |
8154 | ILK_DPARB_CLK_GATE | | |
8155 | ILK_DPFD_CLK_GATE); | |
8956c8bb | 8156 | |
d74362c9 | 8157 | for_each_pipe(pipe) { |
6067aaea JB |
8158 | I915_WRITE(DSPCNTR(pipe), |
8159 | I915_READ(DSPCNTR(pipe)) | | |
8160 | DISPPLANE_TRICKLE_FEED_DISABLE); | |
d74362c9 KP |
8161 | intel_flush_display_plane(dev_priv, pipe); |
8162 | } | |
6067aaea | 8163 | } |
8956c8bb | 8164 | |
28963a3e JB |
8165 | static void ivybridge_init_clock_gating(struct drm_device *dev) |
8166 | { | |
8167 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8168 | int pipe; | |
8169 | uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE; | |
7f8a8569 | 8170 | |
28963a3e | 8171 | I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate); |
382b0936 | 8172 | |
28963a3e JB |
8173 | I915_WRITE(WM3_LP_ILK, 0); |
8174 | I915_WRITE(WM2_LP_ILK, 0); | |
8175 | I915_WRITE(WM1_LP_ILK, 0); | |
de6e2eaf | 8176 | |
28963a3e | 8177 | I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE); |
67e92af0 | 8178 | |
d74362c9 | 8179 | for_each_pipe(pipe) { |
28963a3e JB |
8180 | I915_WRITE(DSPCNTR(pipe), |
8181 | I915_READ(DSPCNTR(pipe)) | | |
8182 | DISPPLANE_TRICKLE_FEED_DISABLE); | |
d74362c9 KP |
8183 | intel_flush_display_plane(dev_priv, pipe); |
8184 | } | |
28963a3e JB |
8185 | } |
8186 | ||
6067aaea JB |
8187 | static void g4x_init_clock_gating(struct drm_device *dev) |
8188 | { | |
8189 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8190 | uint32_t dspclk_gate; | |
8fd26859 | 8191 | |
6067aaea JB |
8192 | I915_WRITE(RENCLK_GATE_D1, 0); |
8193 | I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | | |
8194 | GS_UNIT_CLOCK_GATE_DISABLE | | |
8195 | CL_UNIT_CLOCK_GATE_DISABLE); | |
8196 | I915_WRITE(RAMCLK_GATE_D, 0); | |
8197 | dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE | | |
8198 | OVRUNIT_CLOCK_GATE_DISABLE | | |
8199 | OVCUNIT_CLOCK_GATE_DISABLE; | |
8200 | if (IS_GM45(dev)) | |
8201 | dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; | |
8202 | I915_WRITE(DSPCLK_GATE_D, dspclk_gate); | |
8203 | } | |
1398261a | 8204 | |
6067aaea JB |
8205 | static void crestline_init_clock_gating(struct drm_device *dev) |
8206 | { | |
8207 | struct drm_i915_private *dev_priv = dev->dev_private; | |
652c393a | 8208 | |
6067aaea JB |
8209 | I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); |
8210 | I915_WRITE(RENCLK_GATE_D2, 0); | |
8211 | I915_WRITE(DSPCLK_GATE_D, 0); | |
8212 | I915_WRITE(RAMCLK_GATE_D, 0); | |
8213 | I915_WRITE16(DEUC, 0); | |
8214 | } | |
652c393a | 8215 | |
6067aaea JB |
8216 | static void broadwater_init_clock_gating(struct drm_device *dev) |
8217 | { | |
8218 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8219 | ||
8220 | I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | | |
8221 | I965_RCC_CLOCK_GATE_DISABLE | | |
8222 | I965_RCPB_CLOCK_GATE_DISABLE | | |
8223 | I965_ISC_CLOCK_GATE_DISABLE | | |
8224 | I965_FBC_CLOCK_GATE_DISABLE); | |
8225 | I915_WRITE(RENCLK_GATE_D2, 0); | |
8226 | } | |
8227 | ||
8228 | static void gen3_init_clock_gating(struct drm_device *dev) | |
8229 | { | |
8230 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8231 | u32 dstate = I915_READ(D_STATE); | |
8232 | ||
8233 | dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | | |
8234 | DSTATE_DOT_CLOCK_GATING; | |
8235 | I915_WRITE(D_STATE, dstate); | |
8236 | } | |
8237 | ||
8238 | static void i85x_init_clock_gating(struct drm_device *dev) | |
8239 | { | |
8240 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8241 | ||
8242 | I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); | |
8243 | } | |
8244 | ||
8245 | static void i830_init_clock_gating(struct drm_device *dev) | |
8246 | { | |
8247 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8248 | ||
8249 | I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); | |
652c393a JB |
8250 | } |
8251 | ||
645c62a5 JB |
8252 | static void ibx_init_clock_gating(struct drm_device *dev) |
8253 | { | |
8254 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8255 | ||
8256 | /* | |
8257 | * On Ibex Peak and Cougar Point, we need to disable clock | |
8258 | * gating for the panel power sequencer or it will fail to | |
8259 | * start up when no ports are active. | |
8260 | */ | |
8261 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); | |
8262 | } | |
8263 | ||
8264 | static void cpt_init_clock_gating(struct drm_device *dev) | |
8265 | { | |
8266 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3bcf603f | 8267 | int pipe; |
645c62a5 JB |
8268 | |
8269 | /* | |
8270 | * On Ibex Peak and Cougar Point, we need to disable clock | |
8271 | * gating for the panel power sequencer or it will fail to | |
8272 | * start up when no ports are active. | |
8273 | */ | |
8274 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); | |
8275 | I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) | | |
8276 | DPLS_EDP_PPS_FIX_DIS); | |
3bcf603f JB |
8277 | /* Without this, mode sets may fail silently on FDI */ |
8278 | for_each_pipe(pipe) | |
8279 | I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS); | |
652c393a JB |
8280 | } |
8281 | ||
ac668088 | 8282 | static void ironlake_teardown_rc6(struct drm_device *dev) |
0cdab21f CW |
8283 | { |
8284 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8285 | ||
8286 | if (dev_priv->renderctx) { | |
ac668088 CW |
8287 | i915_gem_object_unpin(dev_priv->renderctx); |
8288 | drm_gem_object_unreference(&dev_priv->renderctx->base); | |
0cdab21f CW |
8289 | dev_priv->renderctx = NULL; |
8290 | } | |
8291 | ||
8292 | if (dev_priv->pwrctx) { | |
ac668088 CW |
8293 | i915_gem_object_unpin(dev_priv->pwrctx); |
8294 | drm_gem_object_unreference(&dev_priv->pwrctx->base); | |
8295 | dev_priv->pwrctx = NULL; | |
8296 | } | |
8297 | } | |
8298 | ||
8299 | static void ironlake_disable_rc6(struct drm_device *dev) | |
8300 | { | |
8301 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8302 | ||
8303 | if (I915_READ(PWRCTXA)) { | |
8304 | /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */ | |
8305 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT); | |
8306 | wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON), | |
8307 | 50); | |
0cdab21f CW |
8308 | |
8309 | I915_WRITE(PWRCTXA, 0); | |
8310 | POSTING_READ(PWRCTXA); | |
8311 | ||
ac668088 CW |
8312 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); |
8313 | POSTING_READ(RSTDBYCTL); | |
0cdab21f | 8314 | } |
ac668088 | 8315 | |
99507307 | 8316 | ironlake_teardown_rc6(dev); |
0cdab21f CW |
8317 | } |
8318 | ||
ac668088 | 8319 | static int ironlake_setup_rc6(struct drm_device *dev) |
d5bb081b JB |
8320 | { |
8321 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8322 | ||
ac668088 CW |
8323 | if (dev_priv->renderctx == NULL) |
8324 | dev_priv->renderctx = intel_alloc_context_page(dev); | |
8325 | if (!dev_priv->renderctx) | |
8326 | return -ENOMEM; | |
8327 | ||
8328 | if (dev_priv->pwrctx == NULL) | |
8329 | dev_priv->pwrctx = intel_alloc_context_page(dev); | |
8330 | if (!dev_priv->pwrctx) { | |
8331 | ironlake_teardown_rc6(dev); | |
8332 | return -ENOMEM; | |
8333 | } | |
8334 | ||
8335 | return 0; | |
d5bb081b JB |
8336 | } |
8337 | ||
8338 | void ironlake_enable_rc6(struct drm_device *dev) | |
8339 | { | |
8340 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8341 | int ret; | |
8342 | ||
ac668088 CW |
8343 | /* rc6 disabled by default due to repeated reports of hanging during |
8344 | * boot and resume. | |
8345 | */ | |
8346 | if (!i915_enable_rc6) | |
8347 | return; | |
8348 | ||
2c34b850 | 8349 | mutex_lock(&dev->struct_mutex); |
ac668088 | 8350 | ret = ironlake_setup_rc6(dev); |
2c34b850 BW |
8351 | if (ret) { |
8352 | mutex_unlock(&dev->struct_mutex); | |
ac668088 | 8353 | return; |
2c34b850 | 8354 | } |
ac668088 | 8355 | |
d5bb081b JB |
8356 | /* |
8357 | * GPU can automatically power down the render unit if given a page | |
8358 | * to save state. | |
8359 | */ | |
8360 | ret = BEGIN_LP_RING(6); | |
8361 | if (ret) { | |
ac668088 | 8362 | ironlake_teardown_rc6(dev); |
2c34b850 | 8363 | mutex_unlock(&dev->struct_mutex); |
d5bb081b JB |
8364 | return; |
8365 | } | |
ac668088 | 8366 | |
d5bb081b JB |
8367 | OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN); |
8368 | OUT_RING(MI_SET_CONTEXT); | |
8369 | OUT_RING(dev_priv->renderctx->gtt_offset | | |
8370 | MI_MM_SPACE_GTT | | |
8371 | MI_SAVE_EXT_STATE_EN | | |
8372 | MI_RESTORE_EXT_STATE_EN | | |
8373 | MI_RESTORE_INHIBIT); | |
8374 | OUT_RING(MI_SUSPEND_FLUSH); | |
8375 | OUT_RING(MI_NOOP); | |
8376 | OUT_RING(MI_FLUSH); | |
8377 | ADVANCE_LP_RING(); | |
8378 | ||
4a246cfc BW |
8379 | /* |
8380 | * Wait for the command parser to advance past MI_SET_CONTEXT. The HW | |
8381 | * does an implicit flush, combined with MI_FLUSH above, it should be | |
8382 | * safe to assume that renderctx is valid | |
8383 | */ | |
8384 | ret = intel_wait_ring_idle(LP_RING(dev_priv)); | |
8385 | if (ret) { | |
8386 | DRM_ERROR("failed to enable ironlake power power savings\n"); | |
8387 | ironlake_teardown_rc6(dev); | |
8388 | mutex_unlock(&dev->struct_mutex); | |
8389 | return; | |
8390 | } | |
8391 | ||
d5bb081b JB |
8392 | I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN); |
8393 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); | |
2c34b850 | 8394 | mutex_unlock(&dev->struct_mutex); |
d5bb081b JB |
8395 | } |
8396 | ||
645c62a5 JB |
8397 | void intel_init_clock_gating(struct drm_device *dev) |
8398 | { | |
8399 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8400 | ||
8401 | dev_priv->display.init_clock_gating(dev); | |
8402 | ||
8403 | if (dev_priv->display.init_pch_clock_gating) | |
8404 | dev_priv->display.init_pch_clock_gating(dev); | |
8405 | } | |
ac668088 | 8406 | |
e70236a8 JB |
8407 | /* Set up chip specific display functions */ |
8408 | static void intel_init_display(struct drm_device *dev) | |
8409 | { | |
8410 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8411 | ||
8412 | /* We always want a DPMS function */ | |
f564048e | 8413 | if (HAS_PCH_SPLIT(dev)) { |
f2b115e6 | 8414 | dev_priv->display.dpms = ironlake_crtc_dpms; |
f564048e | 8415 | dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set; |
17638cd6 | 8416 | dev_priv->display.update_plane = ironlake_update_plane; |
f564048e | 8417 | } else { |
e70236a8 | 8418 | dev_priv->display.dpms = i9xx_crtc_dpms; |
f564048e | 8419 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
17638cd6 | 8420 | dev_priv->display.update_plane = i9xx_update_plane; |
f564048e | 8421 | } |
e70236a8 | 8422 | |
ee5382ae | 8423 | if (I915_HAS_FBC(dev)) { |
9c04f015 | 8424 | if (HAS_PCH_SPLIT(dev)) { |
b52eb4dc ZY |
8425 | dev_priv->display.fbc_enabled = ironlake_fbc_enabled; |
8426 | dev_priv->display.enable_fbc = ironlake_enable_fbc; | |
8427 | dev_priv->display.disable_fbc = ironlake_disable_fbc; | |
8428 | } else if (IS_GM45(dev)) { | |
74dff282 JB |
8429 | dev_priv->display.fbc_enabled = g4x_fbc_enabled; |
8430 | dev_priv->display.enable_fbc = g4x_enable_fbc; | |
8431 | dev_priv->display.disable_fbc = g4x_disable_fbc; | |
a6c45cf0 | 8432 | } else if (IS_CRESTLINE(dev)) { |
e70236a8 JB |
8433 | dev_priv->display.fbc_enabled = i8xx_fbc_enabled; |
8434 | dev_priv->display.enable_fbc = i8xx_enable_fbc; | |
8435 | dev_priv->display.disable_fbc = i8xx_disable_fbc; | |
8436 | } | |
74dff282 | 8437 | /* 855GM needs testing */ |
e70236a8 JB |
8438 | } |
8439 | ||
8440 | /* Returns the core display clock speed */ | |
0206e353 | 8441 | if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) |
e70236a8 JB |
8442 | dev_priv->display.get_display_clock_speed = |
8443 | i945_get_display_clock_speed; | |
8444 | else if (IS_I915G(dev)) | |
8445 | dev_priv->display.get_display_clock_speed = | |
8446 | i915_get_display_clock_speed; | |
f2b115e6 | 8447 | else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev)) |
e70236a8 JB |
8448 | dev_priv->display.get_display_clock_speed = |
8449 | i9xx_misc_get_display_clock_speed; | |
8450 | else if (IS_I915GM(dev)) | |
8451 | dev_priv->display.get_display_clock_speed = | |
8452 | i915gm_get_display_clock_speed; | |
8453 | else if (IS_I865G(dev)) | |
8454 | dev_priv->display.get_display_clock_speed = | |
8455 | i865_get_display_clock_speed; | |
f0f8a9ce | 8456 | else if (IS_I85X(dev)) |
e70236a8 JB |
8457 | dev_priv->display.get_display_clock_speed = |
8458 | i855_get_display_clock_speed; | |
8459 | else /* 852, 830 */ | |
8460 | dev_priv->display.get_display_clock_speed = | |
8461 | i830_get_display_clock_speed; | |
8462 | ||
8463 | /* For FIFO watermark updates */ | |
7f8a8569 | 8464 | if (HAS_PCH_SPLIT(dev)) { |
645c62a5 JB |
8465 | if (HAS_PCH_IBX(dev)) |
8466 | dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating; | |
8467 | else if (HAS_PCH_CPT(dev)) | |
8468 | dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating; | |
8469 | ||
f00a3ddf | 8470 | if (IS_GEN5(dev)) { |
7f8a8569 ZW |
8471 | if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK) |
8472 | dev_priv->display.update_wm = ironlake_update_wm; | |
8473 | else { | |
8474 | DRM_DEBUG_KMS("Failed to get proper latency. " | |
8475 | "Disable CxSR\n"); | |
8476 | dev_priv->display.update_wm = NULL; | |
1398261a | 8477 | } |
674cf967 | 8478 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
6067aaea | 8479 | dev_priv->display.init_clock_gating = ironlake_init_clock_gating; |
e0dac65e | 8480 | dev_priv->display.write_eld = ironlake_write_eld; |
1398261a YL |
8481 | } else if (IS_GEN6(dev)) { |
8482 | if (SNB_READ_WM0_LATENCY()) { | |
8483 | dev_priv->display.update_wm = sandybridge_update_wm; | |
8484 | } else { | |
8485 | DRM_DEBUG_KMS("Failed to read display plane latency. " | |
8486 | "Disable CxSR\n"); | |
8487 | dev_priv->display.update_wm = NULL; | |
7f8a8569 | 8488 | } |
674cf967 | 8489 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
6067aaea | 8490 | dev_priv->display.init_clock_gating = gen6_init_clock_gating; |
e0dac65e | 8491 | dev_priv->display.write_eld = ironlake_write_eld; |
357555c0 JB |
8492 | } else if (IS_IVYBRIDGE(dev)) { |
8493 | /* FIXME: detect B0+ stepping and use auto training */ | |
8494 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
fe100d4d JB |
8495 | if (SNB_READ_WM0_LATENCY()) { |
8496 | dev_priv->display.update_wm = sandybridge_update_wm; | |
8497 | } else { | |
8498 | DRM_DEBUG_KMS("Failed to read display plane latency. " | |
8499 | "Disable CxSR\n"); | |
8500 | dev_priv->display.update_wm = NULL; | |
8501 | } | |
28963a3e | 8502 | dev_priv->display.init_clock_gating = ivybridge_init_clock_gating; |
e0dac65e | 8503 | dev_priv->display.write_eld = ironlake_write_eld; |
7f8a8569 ZW |
8504 | } else |
8505 | dev_priv->display.update_wm = NULL; | |
8506 | } else if (IS_PINEVIEW(dev)) { | |
d4294342 | 8507 | if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev), |
95534263 | 8508 | dev_priv->is_ddr3, |
d4294342 ZY |
8509 | dev_priv->fsb_freq, |
8510 | dev_priv->mem_freq)) { | |
8511 | DRM_INFO("failed to find known CxSR latency " | |
95534263 | 8512 | "(found ddr%s fsb freq %d, mem freq %d), " |
d4294342 | 8513 | "disabling CxSR\n", |
0206e353 | 8514 | (dev_priv->is_ddr3 == 1) ? "3" : "2", |
d4294342 ZY |
8515 | dev_priv->fsb_freq, dev_priv->mem_freq); |
8516 | /* Disable CxSR and never update its watermark again */ | |
8517 | pineview_disable_cxsr(dev); | |
8518 | dev_priv->display.update_wm = NULL; | |
8519 | } else | |
8520 | dev_priv->display.update_wm = pineview_update_wm; | |
95e0ee92 | 8521 | dev_priv->display.init_clock_gating = gen3_init_clock_gating; |
6067aaea | 8522 | } else if (IS_G4X(dev)) { |
e0dac65e | 8523 | dev_priv->display.write_eld = g4x_write_eld; |
e70236a8 | 8524 | dev_priv->display.update_wm = g4x_update_wm; |
6067aaea JB |
8525 | dev_priv->display.init_clock_gating = g4x_init_clock_gating; |
8526 | } else if (IS_GEN4(dev)) { | |
e70236a8 | 8527 | dev_priv->display.update_wm = i965_update_wm; |
6067aaea JB |
8528 | if (IS_CRESTLINE(dev)) |
8529 | dev_priv->display.init_clock_gating = crestline_init_clock_gating; | |
8530 | else if (IS_BROADWATER(dev)) | |
8531 | dev_priv->display.init_clock_gating = broadwater_init_clock_gating; | |
8532 | } else if (IS_GEN3(dev)) { | |
e70236a8 JB |
8533 | dev_priv->display.update_wm = i9xx_update_wm; |
8534 | dev_priv->display.get_fifo_size = i9xx_get_fifo_size; | |
6067aaea JB |
8535 | dev_priv->display.init_clock_gating = gen3_init_clock_gating; |
8536 | } else if (IS_I865G(dev)) { | |
8537 | dev_priv->display.update_wm = i830_update_wm; | |
8538 | dev_priv->display.init_clock_gating = i85x_init_clock_gating; | |
8539 | dev_priv->display.get_fifo_size = i830_get_fifo_size; | |
8f4695ed AJ |
8540 | } else if (IS_I85X(dev)) { |
8541 | dev_priv->display.update_wm = i9xx_update_wm; | |
8542 | dev_priv->display.get_fifo_size = i85x_get_fifo_size; | |
6067aaea | 8543 | dev_priv->display.init_clock_gating = i85x_init_clock_gating; |
e70236a8 | 8544 | } else { |
8f4695ed | 8545 | dev_priv->display.update_wm = i830_update_wm; |
6067aaea | 8546 | dev_priv->display.init_clock_gating = i830_init_clock_gating; |
8f4695ed | 8547 | if (IS_845G(dev)) |
e70236a8 JB |
8548 | dev_priv->display.get_fifo_size = i845_get_fifo_size; |
8549 | else | |
8550 | dev_priv->display.get_fifo_size = i830_get_fifo_size; | |
e70236a8 | 8551 | } |
8c9f3aaf JB |
8552 | |
8553 | /* Default just returns -ENODEV to indicate unsupported */ | |
8554 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
8555 | ||
8556 | switch (INTEL_INFO(dev)->gen) { | |
8557 | case 2: | |
8558 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
8559 | break; | |
8560 | ||
8561 | case 3: | |
8562 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
8563 | break; | |
8564 | ||
8565 | case 4: | |
8566 | case 5: | |
8567 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
8568 | break; | |
8569 | ||
8570 | case 6: | |
8571 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
8572 | break; | |
7c9017e5 JB |
8573 | case 7: |
8574 | dev_priv->display.queue_flip = intel_gen7_queue_flip; | |
8575 | break; | |
8c9f3aaf | 8576 | } |
e70236a8 JB |
8577 | } |
8578 | ||
b690e96c JB |
8579 | /* |
8580 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
8581 | * resume, or other times. This quirk makes sure that's the case for | |
8582 | * affected systems. | |
8583 | */ | |
0206e353 | 8584 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
8585 | { |
8586 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8587 | ||
8588 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
8589 | DRM_DEBUG_DRIVER("applying pipe a force quirk\n"); | |
8590 | } | |
8591 | ||
435793df KP |
8592 | /* |
8593 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
8594 | */ | |
8595 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
8596 | { | |
8597 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8598 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
8599 | } | |
8600 | ||
b690e96c JB |
8601 | struct intel_quirk { |
8602 | int device; | |
8603 | int subsystem_vendor; | |
8604 | int subsystem_device; | |
8605 | void (*hook)(struct drm_device *dev); | |
8606 | }; | |
8607 | ||
8608 | struct intel_quirk intel_quirks[] = { | |
8609 | /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */ | |
8610 | { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force }, | |
8611 | /* HP Mini needs pipe A force quirk (LP: #322104) */ | |
0206e353 | 8612 | { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, |
b690e96c JB |
8613 | |
8614 | /* Thinkpad R31 needs pipe A force quirk */ | |
8615 | { 0x3577, 0x1014, 0x0505, quirk_pipea_force }, | |
8616 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ | |
8617 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
8618 | ||
8619 | /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */ | |
8620 | { 0x3577, 0x1014, 0x0513, quirk_pipea_force }, | |
8621 | /* ThinkPad X40 needs pipe A force quirk */ | |
8622 | ||
8623 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ | |
8624 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
8625 | ||
8626 | /* 855 & before need to leave pipe A & dpll A up */ | |
8627 | { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
8628 | { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
435793df KP |
8629 | |
8630 | /* Lenovo U160 cannot use SSC on LVDS */ | |
8631 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
8632 | |
8633 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
8634 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
b690e96c JB |
8635 | }; |
8636 | ||
8637 | static void intel_init_quirks(struct drm_device *dev) | |
8638 | { | |
8639 | struct pci_dev *d = dev->pdev; | |
8640 | int i; | |
8641 | ||
8642 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
8643 | struct intel_quirk *q = &intel_quirks[i]; | |
8644 | ||
8645 | if (d->device == q->device && | |
8646 | (d->subsystem_vendor == q->subsystem_vendor || | |
8647 | q->subsystem_vendor == PCI_ANY_ID) && | |
8648 | (d->subsystem_device == q->subsystem_device || | |
8649 | q->subsystem_device == PCI_ANY_ID)) | |
8650 | q->hook(dev); | |
8651 | } | |
8652 | } | |
8653 | ||
9cce37f4 JB |
8654 | /* Disable the VGA plane that we never use */ |
8655 | static void i915_disable_vga(struct drm_device *dev) | |
8656 | { | |
8657 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8658 | u8 sr1; | |
8659 | u32 vga_reg; | |
8660 | ||
8661 | if (HAS_PCH_SPLIT(dev)) | |
8662 | vga_reg = CPU_VGACNTRL; | |
8663 | else | |
8664 | vga_reg = VGACNTRL; | |
8665 | ||
8666 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); | |
8667 | outb(1, VGA_SR_INDEX); | |
8668 | sr1 = inb(VGA_SR_DATA); | |
8669 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
8670 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
8671 | udelay(300); | |
8672 | ||
8673 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); | |
8674 | POSTING_READ(vga_reg); | |
8675 | } | |
8676 | ||
79e53945 JB |
8677 | void intel_modeset_init(struct drm_device *dev) |
8678 | { | |
652c393a | 8679 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 JB |
8680 | int i; |
8681 | ||
8682 | drm_mode_config_init(dev); | |
8683 | ||
8684 | dev->mode_config.min_width = 0; | |
8685 | dev->mode_config.min_height = 0; | |
8686 | ||
8687 | dev->mode_config.funcs = (void *)&intel_mode_funcs; | |
8688 | ||
b690e96c JB |
8689 | intel_init_quirks(dev); |
8690 | ||
e70236a8 JB |
8691 | intel_init_display(dev); |
8692 | ||
a6c45cf0 CW |
8693 | if (IS_GEN2(dev)) { |
8694 | dev->mode_config.max_width = 2048; | |
8695 | dev->mode_config.max_height = 2048; | |
8696 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
8697 | dev->mode_config.max_width = 4096; |
8698 | dev->mode_config.max_height = 4096; | |
79e53945 | 8699 | } else { |
a6c45cf0 CW |
8700 | dev->mode_config.max_width = 8192; |
8701 | dev->mode_config.max_height = 8192; | |
79e53945 | 8702 | } |
35c3047a | 8703 | dev->mode_config.fb_base = dev->agp->base; |
79e53945 | 8704 | |
28c97730 | 8705 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
a3524f1b | 8706 | dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : ""); |
79e53945 | 8707 | |
a3524f1b | 8708 | for (i = 0; i < dev_priv->num_pipe; i++) { |
79e53945 JB |
8709 | intel_crtc_init(dev, i); |
8710 | } | |
8711 | ||
9cce37f4 JB |
8712 | /* Just disable it once at startup */ |
8713 | i915_disable_vga(dev); | |
79e53945 | 8714 | intel_setup_outputs(dev); |
652c393a | 8715 | |
645c62a5 | 8716 | intel_init_clock_gating(dev); |
9cce37f4 | 8717 | |
7648fa99 | 8718 | if (IS_IRONLAKE_M(dev)) { |
f97108d1 | 8719 | ironlake_enable_drps(dev); |
7648fa99 JB |
8720 | intel_init_emon(dev); |
8721 | } | |
f97108d1 | 8722 | |
1c70c0ce | 8723 | if (IS_GEN6(dev) || IS_GEN7(dev)) { |
3b8d8d91 | 8724 | gen6_enable_rps(dev_priv); |
23b2f8bb JB |
8725 | gen6_update_ring_freq(dev_priv); |
8726 | } | |
3b8d8d91 | 8727 | |
652c393a JB |
8728 | INIT_WORK(&dev_priv->idle_work, intel_idle_update); |
8729 | setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer, | |
8730 | (unsigned long)dev); | |
2c7111db CW |
8731 | } |
8732 | ||
8733 | void intel_modeset_gem_init(struct drm_device *dev) | |
8734 | { | |
8735 | if (IS_IRONLAKE_M(dev)) | |
8736 | ironlake_enable_rc6(dev); | |
02e792fb DV |
8737 | |
8738 | intel_setup_overlay(dev); | |
79e53945 JB |
8739 | } |
8740 | ||
8741 | void intel_modeset_cleanup(struct drm_device *dev) | |
8742 | { | |
652c393a JB |
8743 | struct drm_i915_private *dev_priv = dev->dev_private; |
8744 | struct drm_crtc *crtc; | |
8745 | struct intel_crtc *intel_crtc; | |
8746 | ||
f87ea761 | 8747 | drm_kms_helper_poll_fini(dev); |
652c393a JB |
8748 | mutex_lock(&dev->struct_mutex); |
8749 | ||
723bfd70 JB |
8750 | intel_unregister_dsm_handler(); |
8751 | ||
8752 | ||
652c393a JB |
8753 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
8754 | /* Skip inactive CRTCs */ | |
8755 | if (!crtc->fb) | |
8756 | continue; | |
8757 | ||
8758 | intel_crtc = to_intel_crtc(crtc); | |
3dec0095 | 8759 | intel_increase_pllclock(crtc); |
652c393a JB |
8760 | } |
8761 | ||
973d04f9 | 8762 | intel_disable_fbc(dev); |
e70236a8 | 8763 | |
f97108d1 JB |
8764 | if (IS_IRONLAKE_M(dev)) |
8765 | ironlake_disable_drps(dev); | |
1c70c0ce | 8766 | if (IS_GEN6(dev) || IS_GEN7(dev)) |
3b8d8d91 | 8767 | gen6_disable_rps(dev); |
f97108d1 | 8768 | |
d5bb081b JB |
8769 | if (IS_IRONLAKE_M(dev)) |
8770 | ironlake_disable_rc6(dev); | |
0cdab21f | 8771 | |
69341a5e KH |
8772 | mutex_unlock(&dev->struct_mutex); |
8773 | ||
6c0d9350 DV |
8774 | /* Disable the irq before mode object teardown, for the irq might |
8775 | * enqueue unpin/hotplug work. */ | |
8776 | drm_irq_uninstall(dev); | |
8777 | cancel_work_sync(&dev_priv->hotplug_work); | |
6fdd4d98 | 8778 | cancel_work_sync(&dev_priv->rps_work); |
6c0d9350 | 8779 | |
1630fe75 CW |
8780 | /* flush any delayed tasks or pending work */ |
8781 | flush_scheduled_work(); | |
8782 | ||
3dec0095 DV |
8783 | /* Shut off idle work before the crtcs get freed. */ |
8784 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
8785 | intel_crtc = to_intel_crtc(crtc); | |
8786 | del_timer_sync(&intel_crtc->idle_timer); | |
8787 | } | |
8788 | del_timer_sync(&dev_priv->idle_timer); | |
8789 | cancel_work_sync(&dev_priv->idle_work); | |
8790 | ||
79e53945 JB |
8791 | drm_mode_config_cleanup(dev); |
8792 | } | |
8793 | ||
f1c79df3 ZW |
8794 | /* |
8795 | * Return which encoder is currently attached for connector. | |
8796 | */ | |
df0e9248 | 8797 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 8798 | { |
df0e9248 CW |
8799 | return &intel_attached_encoder(connector)->base; |
8800 | } | |
f1c79df3 | 8801 | |
df0e9248 CW |
8802 | void intel_connector_attach_encoder(struct intel_connector *connector, |
8803 | struct intel_encoder *encoder) | |
8804 | { | |
8805 | connector->encoder = encoder; | |
8806 | drm_mode_connector_attach_encoder(&connector->base, | |
8807 | &encoder->base); | |
79e53945 | 8808 | } |
28d52043 DA |
8809 | |
8810 | /* | |
8811 | * set vga decode state - true == enable VGA decode | |
8812 | */ | |
8813 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
8814 | { | |
8815 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8816 | u16 gmch_ctrl; | |
8817 | ||
8818 | pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl); | |
8819 | if (state) | |
8820 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
8821 | else | |
8822 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
8823 | pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl); | |
8824 | return 0; | |
8825 | } | |
c4a1d9e4 CW |
8826 | |
8827 | #ifdef CONFIG_DEBUG_FS | |
8828 | #include <linux/seq_file.h> | |
8829 | ||
8830 | struct intel_display_error_state { | |
8831 | struct intel_cursor_error_state { | |
8832 | u32 control; | |
8833 | u32 position; | |
8834 | u32 base; | |
8835 | u32 size; | |
8836 | } cursor[2]; | |
8837 | ||
8838 | struct intel_pipe_error_state { | |
8839 | u32 conf; | |
8840 | u32 source; | |
8841 | ||
8842 | u32 htotal; | |
8843 | u32 hblank; | |
8844 | u32 hsync; | |
8845 | u32 vtotal; | |
8846 | u32 vblank; | |
8847 | u32 vsync; | |
8848 | } pipe[2]; | |
8849 | ||
8850 | struct intel_plane_error_state { | |
8851 | u32 control; | |
8852 | u32 stride; | |
8853 | u32 size; | |
8854 | u32 pos; | |
8855 | u32 addr; | |
8856 | u32 surface; | |
8857 | u32 tile_offset; | |
8858 | } plane[2]; | |
8859 | }; | |
8860 | ||
8861 | struct intel_display_error_state * | |
8862 | intel_display_capture_error_state(struct drm_device *dev) | |
8863 | { | |
0206e353 | 8864 | drm_i915_private_t *dev_priv = dev->dev_private; |
c4a1d9e4 CW |
8865 | struct intel_display_error_state *error; |
8866 | int i; | |
8867 | ||
8868 | error = kmalloc(sizeof(*error), GFP_ATOMIC); | |
8869 | if (error == NULL) | |
8870 | return NULL; | |
8871 | ||
8872 | for (i = 0; i < 2; i++) { | |
8873 | error->cursor[i].control = I915_READ(CURCNTR(i)); | |
8874 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
8875 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
8876 | ||
8877 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
8878 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
8879 | error->plane[i].size = I915_READ(DSPSIZE(i)); | |
0206e353 | 8880 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
c4a1d9e4 CW |
8881 | error->plane[i].addr = I915_READ(DSPADDR(i)); |
8882 | if (INTEL_INFO(dev)->gen >= 4) { | |
8883 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
8884 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
8885 | } | |
8886 | ||
8887 | error->pipe[i].conf = I915_READ(PIPECONF(i)); | |
8888 | error->pipe[i].source = I915_READ(PIPESRC(i)); | |
8889 | error->pipe[i].htotal = I915_READ(HTOTAL(i)); | |
8890 | error->pipe[i].hblank = I915_READ(HBLANK(i)); | |
8891 | error->pipe[i].hsync = I915_READ(HSYNC(i)); | |
8892 | error->pipe[i].vtotal = I915_READ(VTOTAL(i)); | |
8893 | error->pipe[i].vblank = I915_READ(VBLANK(i)); | |
8894 | error->pipe[i].vsync = I915_READ(VSYNC(i)); | |
8895 | } | |
8896 | ||
8897 | return error; | |
8898 | } | |
8899 | ||
8900 | void | |
8901 | intel_display_print_error_state(struct seq_file *m, | |
8902 | struct drm_device *dev, | |
8903 | struct intel_display_error_state *error) | |
8904 | { | |
8905 | int i; | |
8906 | ||
8907 | for (i = 0; i < 2; i++) { | |
8908 | seq_printf(m, "Pipe [%d]:\n", i); | |
8909 | seq_printf(m, " CONF: %08x\n", error->pipe[i].conf); | |
8910 | seq_printf(m, " SRC: %08x\n", error->pipe[i].source); | |
8911 | seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal); | |
8912 | seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank); | |
8913 | seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync); | |
8914 | seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal); | |
8915 | seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank); | |
8916 | seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync); | |
8917 | ||
8918 | seq_printf(m, "Plane [%d]:\n", i); | |
8919 | seq_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
8920 | seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
8921 | seq_printf(m, " SIZE: %08x\n", error->plane[i].size); | |
8922 | seq_printf(m, " POS: %08x\n", error->plane[i].pos); | |
8923 | seq_printf(m, " ADDR: %08x\n", error->plane[i].addr); | |
8924 | if (INTEL_INFO(dev)->gen >= 4) { | |
8925 | seq_printf(m, " SURF: %08x\n", error->plane[i].surface); | |
8926 | seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
8927 | } | |
8928 | ||
8929 | seq_printf(m, "Cursor [%d]:\n", i); | |
8930 | seq_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
8931 | seq_printf(m, " POS: %08x\n", error->cursor[i].position); | |
8932 | seq_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
8933 | } | |
8934 | } | |
8935 | #endif |