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drm/i915: fix PCH PLL assertion check for 3 pipes
[linux-block.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
23b2f8bb 27#include <linux/cpufreq.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
79e53945
JB		 35#include "drmP.h"
36#include "intel_drv.h"
37#include "i915_drm.h"
38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
ab2c0672 40#include "drm_dp_helper.h"
79e53945
JB		 41
42#include "drm_crtc_helper.h"
43
32f9d658
ZW		 44#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
0206e353 46bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
7662c8bd 47static void intel_update_watermarks(struct drm_device *dev);
3dec0095 48static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 49static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 50
51typedef struct {
0206e353
AJ		 52 /* given values */
53 int n;
54 int m1, m2;
55 int p1, p2;
56 /* derived values */
57 int dot;
58 int vco;
59 int m;
60 int p;
79e53945
JB		 61} intel_clock_t;
62
63typedef struct {
0206e353 64 int min, max;
79e53945
JB		 65} intel_range_t;
66
67typedef struct {
0206e353
AJ		 68 int dot_limit;
69 int p2_slow, p2_fast;
79e53945
JB		 70} intel_p2_t;
71
72#define INTEL_P2_NUM 2
d4906093
ML		 73typedef struct intel_limit intel_limit_t;
74struct intel_limit {
0206e353
AJ		 75 intel_range_t dot, vco, n, m, m1, m2, p, p1;
76 intel_p2_t p2;
77 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
78 int, int, intel_clock_t *);
d4906093 79};
79e53945 80
2377b741
JB		 81/* FDI */
82#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
83
d4906093
ML		 84static bool
85intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
86 int target, int refclk, intel_clock_t *best_clock);
87static bool
88intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
89 int target, int refclk, intel_clock_t *best_clock);
79e53945 90
a4fc5ed6
KP		 91static bool
92intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
93 int target, int refclk, intel_clock_t *best_clock);
5eb08b69 94static bool
f2b115e6
AJ		 95intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
96 int target, int refclk, intel_clock_t *best_clock);
a4fc5ed6 97
021357ac
CW		 98static inline u32 /* units of 100MHz */
99intel_fdi_link_freq(struct drm_device *dev)
100{
8b99e68c
CW		 101 if (IS_GEN5(dev)) {
102 struct drm_i915_private *dev_priv = dev->dev_private;
103 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
104 } else
105 return 27;
021357ac
CW		 106}
107
e4b36699 108static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 109 .dot = { .min = 25000, .max = 350000 },
110 .vco = { .min = 930000, .max = 1400000 },
111 .n = { .min = 3, .max = 16 },
112 .m = { .min = 96, .max = 140 },
113 .m1 = { .min = 18, .max = 26 },
114 .m2 = { .min = 6, .max = 16 },
115 .p = { .min = 4, .max = 128 },
116 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 117 .p2 = { .dot_limit = 165000,
118 .p2_slow = 4, .p2_fast = 2 },
d4906093 119 .find_pll = intel_find_best_PLL,
e4b36699
KP		 120};
121
122static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 123 .dot = { .min = 25000, .max = 350000 },
124 .vco = { .min = 930000, .max = 1400000 },
125 .n = { .min = 3, .max = 16 },
126 .m = { .min = 96, .max = 140 },
127 .m1 = { .min = 18, .max = 26 },
128 .m2 = { .min = 6, .max = 16 },
129 .p = { .min = 4, .max = 128 },
130 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 131 .p2 = { .dot_limit = 165000,
132 .p2_slow = 14, .p2_fast = 7 },
d4906093 133 .find_pll = intel_find_best_PLL,
e4b36699 134};
273e27ca 135
e4b36699 136static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 137 .dot = { .min = 20000, .max = 400000 },
138 .vco = { .min = 1400000, .max = 2800000 },
139 .n = { .min = 1, .max = 6 },
140 .m = { .min = 70, .max = 120 },
141 .m1 = { .min = 10, .max = 22 },
142 .m2 = { .min = 5, .max = 9 },
143 .p = { .min = 5, .max = 80 },
144 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 145 .p2 = { .dot_limit = 200000,
146 .p2_slow = 10, .p2_fast = 5 },
d4906093 147 .find_pll = intel_find_best_PLL,
e4b36699
KP		 148};
149
150static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 151 .dot = { .min = 20000, .max = 400000 },
152 .vco = { .min = 1400000, .max = 2800000 },
153 .n = { .min = 1, .max = 6 },
154 .m = { .min = 70, .max = 120 },
155 .m1 = { .min = 10, .max = 22 },
156 .m2 = { .min = 5, .max = 9 },
157 .p = { .min = 7, .max = 98 },
158 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 159 .p2 = { .dot_limit = 112000,
160 .p2_slow = 14, .p2_fast = 7 },
d4906093 161 .find_pll = intel_find_best_PLL,
e4b36699
KP		 162};
163
273e27ca 164
e4b36699 165static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 166 .dot = { .min = 25000, .max = 270000 },
167 .vco = { .min = 1750000, .max = 3500000},
168 .n = { .min = 1, .max = 4 },
169 .m = { .min = 104, .max = 138 },
170 .m1 = { .min = 17, .max = 23 },
171 .m2 = { .min = 5, .max = 11 },
172 .p = { .min = 10, .max = 30 },
173 .p1 = { .min = 1, .max = 3},
174 .p2 = { .dot_limit = 270000,
175 .p2_slow = 10,
176 .p2_fast = 10
044c7c41 177 },
d4906093 178 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 179};
180
181static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 182 .dot = { .min = 22000, .max = 400000 },
183 .vco = { .min = 1750000, .max = 3500000},
184 .n = { .min = 1, .max = 4 },
185 .m = { .min = 104, .max = 138 },
186 .m1 = { .min = 16, .max = 23 },
187 .m2 = { .min = 5, .max = 11 },
188 .p = { .min = 5, .max = 80 },
189 .p1 = { .min = 1, .max = 8},
190 .p2 = { .dot_limit = 165000,
191 .p2_slow = 10, .p2_fast = 5 },
d4906093 192 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 193};
194
195static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 196 .dot = { .min = 20000, .max = 115000 },
197 .vco = { .min = 1750000, .max = 3500000 },
198 .n = { .min = 1, .max = 3 },
199 .m = { .min = 104, .max = 138 },
200 .m1 = { .min = 17, .max = 23 },
201 .m2 = { .min = 5, .max = 11 },
202 .p = { .min = 28, .max = 112 },
203 .p1 = { .min = 2, .max = 8 },
204 .p2 = { .dot_limit = 0,
205 .p2_slow = 14, .p2_fast = 14
044c7c41 206 },
d4906093 207 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 208};
209
210static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 211 .dot = { .min = 80000, .max = 224000 },
212 .vco = { .min = 1750000, .max = 3500000 },
213 .n = { .min = 1, .max = 3 },
214 .m = { .min = 104, .max = 138 },
215 .m1 = { .min = 17, .max = 23 },
216 .m2 = { .min = 5, .max = 11 },
217 .p = { .min = 14, .max = 42 },
218 .p1 = { .min = 2, .max = 6 },
219 .p2 = { .dot_limit = 0,
220 .p2_slow = 7, .p2_fast = 7
044c7c41 221 },
d4906093 222 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 223};
224
225static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 226 .dot = { .min = 161670, .max = 227000 },
227 .vco = { .min = 1750000, .max = 3500000},
228 .n = { .min = 1, .max = 2 },
229 .m = { .min = 97, .max = 108 },
230 .m1 = { .min = 0x10, .max = 0x12 },
231 .m2 = { .min = 0x05, .max = 0x06 },
232 .p = { .min = 10, .max = 20 },
233 .p1 = { .min = 1, .max = 2},
234 .p2 = { .dot_limit = 0,
273e27ca 235 .p2_slow = 10, .p2_fast = 10 },
0206e353 236 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 237};
238
f2b115e6 239static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 240 .dot = { .min = 20000, .max = 400000},
241 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 242 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 243 .n = { .min = 3, .max = 6 },
244 .m = { .min = 2, .max = 256 },
273e27ca 245 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 246 .m1 = { .min = 0, .max = 0 },
247 .m2 = { .min = 0, .max = 254 },
248 .p = { .min = 5, .max = 80 },
249 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 250 .p2 = { .dot_limit = 200000,
251 .p2_slow = 10, .p2_fast = 5 },
6115707b 252 .find_pll = intel_find_best_PLL,
e4b36699
KP		 253};
254
f2b115e6 255static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 256 .dot = { .min = 20000, .max = 400000 },
257 .vco = { .min = 1700000, .max = 3500000 },
258 .n = { .min = 3, .max = 6 },
259 .m = { .min = 2, .max = 256 },
260 .m1 = { .min = 0, .max = 0 },
261 .m2 = { .min = 0, .max = 254 },
262 .p = { .min = 7, .max = 112 },
263 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 264 .p2 = { .dot_limit = 112000,
265 .p2_slow = 14, .p2_fast = 14 },
6115707b 266 .find_pll = intel_find_best_PLL,
e4b36699
KP		 267};
268
273e27ca
EA		 269/* Ironlake / Sandybridge
270 *
271 * We calculate clock using (register_value + 2) for N/M1/M2, so here
272 * the range value for them is (actual_value - 2).
273 */
b91ad0ec 274static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 275 .dot = { .min = 25000, .max = 350000 },
276 .vco = { .min = 1760000, .max = 3510000 },
277 .n = { .min = 1, .max = 5 },
278 .m = { .min = 79, .max = 127 },
279 .m1 = { .min = 12, .max = 22 },
280 .m2 = { .min = 5, .max = 9 },
281 .p = { .min = 5, .max = 80 },
282 .p1 = { .min = 1, .max = 8 },
283 .p2 = { .dot_limit = 225000,
284 .p2_slow = 10, .p2_fast = 5 },
4547668a 285 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 286};
287
b91ad0ec 288static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 289 .dot = { .min = 25000, .max = 350000 },
290 .vco = { .min = 1760000, .max = 3510000 },
291 .n = { .min = 1, .max = 3 },
292 .m = { .min = 79, .max = 118 },
293 .m1 = { .min = 12, .max = 22 },
294 .m2 = { .min = 5, .max = 9 },
295 .p = { .min = 28, .max = 112 },
296 .p1 = { .min = 2, .max = 8 },
297 .p2 = { .dot_limit = 225000,
298 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 299 .find_pll = intel_g4x_find_best_PLL,
300};
301
302static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 303 .dot = { .min = 25000, .max = 350000 },
304 .vco = { .min = 1760000, .max = 3510000 },
305 .n = { .min = 1, .max = 3 },
306 .m = { .min = 79, .max = 127 },
307 .m1 = { .min = 12, .max = 22 },
308 .m2 = { .min = 5, .max = 9 },
309 .p = { .min = 14, .max = 56 },
310 .p1 = { .min = 2, .max = 8 },
311 .p2 = { .dot_limit = 225000,
312 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 313 .find_pll = intel_g4x_find_best_PLL,
314};
315
273e27ca 316/* LVDS 100mhz refclk limits. */
b91ad0ec 317static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 318 .dot = { .min = 25000, .max = 350000 },
319 .vco = { .min = 1760000, .max = 3510000 },
320 .n = { .min = 1, .max = 2 },
321 .m = { .min = 79, .max = 126 },
322 .m1 = { .min = 12, .max = 22 },
323 .m2 = { .min = 5, .max = 9 },
324 .p = { .min = 28, .max = 112 },
0206e353 325 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 326 .p2 = { .dot_limit = 225000,
327 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 328 .find_pll = intel_g4x_find_best_PLL,
329};
330
331static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 332 .dot = { .min = 25000, .max = 350000 },
333 .vco = { .min = 1760000, .max = 3510000 },
334 .n = { .min = 1, .max = 3 },
335 .m = { .min = 79, .max = 126 },
336 .m1 = { .min = 12, .max = 22 },
337 .m2 = { .min = 5, .max = 9 },
338 .p = { .min = 14, .max = 42 },
0206e353 339 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 340 .p2 = { .dot_limit = 225000,
341 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 342 .find_pll = intel_g4x_find_best_PLL,
343};
344
345static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 346 .dot = { .min = 25000, .max = 350000 },
347 .vco = { .min = 1760000, .max = 3510000},
348 .n = { .min = 1, .max = 2 },
349 .m = { .min = 81, .max = 90 },
350 .m1 = { .min = 12, .max = 22 },
351 .m2 = { .min = 5, .max = 9 },
352 .p = { .min = 10, .max = 20 },
353 .p1 = { .min = 1, .max = 2},
354 .p2 = { .dot_limit = 0,
273e27ca 355 .p2_slow = 10, .p2_fast = 10 },
0206e353 356 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 357};
358
1b894b59
CW		 359static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
360 int refclk)
2c07245f 361{
b91ad0ec
ZW		 362 struct drm_device *dev = crtc->dev;
363 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 364 const intel_limit_t *limit;
b91ad0ec
ZW		 365
366 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b91ad0ec
ZW		 367 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
368 LVDS_CLKB_POWER_UP) {
369 /* LVDS dual channel */
1b894b59 370 if (refclk == 100000)
b91ad0ec
ZW		 371 limit = &intel_limits_ironlake_dual_lvds_100m;
372 else
373 limit = &intel_limits_ironlake_dual_lvds;
374 } else {
1b894b59 375 if (refclk == 100000)
b91ad0ec
ZW		 376 limit = &intel_limits_ironlake_single_lvds_100m;
377 else
378 limit = &intel_limits_ironlake_single_lvds;
379 }
380 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
4547668a
ZY		 381 HAS_eDP)
382 limit = &intel_limits_ironlake_display_port;
2c07245f 383 else
b91ad0ec 384 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 385
386 return limit;
387}
388
044c7c41
ML		 389static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
390{
391 struct drm_device *dev = crtc->dev;
392 struct drm_i915_private *dev_priv = dev->dev_private;
393 const intel_limit_t *limit;
394
395 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
396 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
397 LVDS_CLKB_POWER_UP)
398 /* LVDS with dual channel */
e4b36699 399 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 400 else
401 /* LVDS with dual channel */
e4b36699 402 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 403 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
404 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 405 limit = &intel_limits_g4x_hdmi;
044c7c41 406 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 407 limit = &intel_limits_g4x_sdvo;
0206e353 408 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 409 limit = &intel_limits_g4x_display_port;
044c7c41 410 } else /* The option is for other outputs */
e4b36699 411 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 412
413 return limit;
414}
415
1b894b59 416static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 417{
418 struct drm_device *dev = crtc->dev;
419 const intel_limit_t *limit;
420
bad720ff 421 if (HAS_PCH_SPLIT(dev))
1b894b59 422 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 423 else if (IS_G4X(dev)) {
044c7c41 424 limit = intel_g4x_limit(crtc);
f2b115e6 425 } else if (IS_PINEVIEW(dev)) {
2177832f 426 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 427 limit = &intel_limits_pineview_lvds;
2177832f 428 else
f2b115e6 429 limit = &intel_limits_pineview_sdvo;
a6c45cf0
CW		 430 } else if (!IS_GEN2(dev)) {
431 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
432 limit = &intel_limits_i9xx_lvds;
433 else
434 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 435 } else {
436 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 437 limit = &intel_limits_i8xx_lvds;
79e53945 438 else
e4b36699 439 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 440 }
441 return limit;
442}
443
f2b115e6
AJ		 444/* m1 is reserved as 0 in Pineview, n is a ring counter */
445static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 446{
2177832f
SL		 447 clock->m = clock->m2 + 2;
448 clock->p = clock->p1 * clock->p2;
449 clock->vco = refclk * clock->m / clock->n;
450 clock->dot = clock->vco / clock->p;
451}
452
453static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
454{
f2b115e6
AJ		 455 if (IS_PINEVIEW(dev)) {
456 pineview_clock(refclk, clock);
2177832f
SL		 457 return;
458 }
79e53945
JB		 459 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
460 clock->p = clock->p1 * clock->p2;
461 clock->vco = refclk * clock->m / (clock->n + 2);
462 clock->dot = clock->vco / clock->p;
463}
464
79e53945
JB		 465/**
466 * Returns whether any output on the specified pipe is of the specified type
467 */
4ef69c7a 468bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 469{
4ef69c7a
CW		 470 struct drm_device *dev = crtc->dev;
471 struct drm_mode_config *mode_config = &dev->mode_config;
472 struct intel_encoder *encoder;
473
474 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
475 if (encoder->base.crtc == crtc && encoder->type == type)
476 return true;
477
478 return false;
79e53945
JB		 479}
480
7c04d1d9 481#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 482/**
483 * Returns whether the given set of divisors are valid for a given refclk with
484 * the given connectors.
485 */
486
1b894b59
CW		 487static bool intel_PLL_is_valid(struct drm_device *dev,
488 const intel_limit_t *limit,
489 const intel_clock_t *clock)
79e53945 490{
79e53945 491 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 492 INTELPllInvalid("p1 out of range\n");
79e53945 493 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 494 INTELPllInvalid("p out of range\n");
79e53945 495 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 496 INTELPllInvalid("m2 out of range\n");
79e53945 497 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 498 INTELPllInvalid("m1 out of range\n");
f2b115e6 499 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 500 INTELPllInvalid("m1 <= m2\n");
79e53945 501 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 502 INTELPllInvalid("m out of range\n");
79e53945 503 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 504 INTELPllInvalid("n out of range\n");
79e53945 505 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 506 INTELPllInvalid("vco out of range\n");
79e53945
JB		 507 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
508 * connector, etc., rather than just a single range.
509 */
510 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 511 INTELPllInvalid("dot out of range\n");
79e53945
JB		 512
513 return true;
514}
515
d4906093
ML		 516static bool
517intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
518 int target, int refclk, intel_clock_t *best_clock)
519
79e53945
JB		 520{
521 struct drm_device *dev = crtc->dev;
522 struct drm_i915_private *dev_priv = dev->dev_private;
523 intel_clock_t clock;
79e53945
JB		 524 int err = target;
525
bc5e5718 526 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
832cc28d 527 (I915_READ(LVDS)) != 0) {
79e53945
JB		 528 /*
529 * For LVDS, if the panel is on, just rely on its current
530 * settings for dual-channel. We haven't figured out how to
531 * reliably set up different single/dual channel state, if we
532 * even can.
533 */
534 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
535 LVDS_CLKB_POWER_UP)
536 clock.p2 = limit->p2.p2_fast;
537 else
538 clock.p2 = limit->p2.p2_slow;
539 } else {
540 if (target < limit->p2.dot_limit)
541 clock.p2 = limit->p2.p2_slow;
542 else
543 clock.p2 = limit->p2.p2_fast;
544 }
545
0206e353 546 memset(best_clock, 0, sizeof(*best_clock));
79e53945 547
42158660
ZY		 548 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
549 clock.m1++) {
550 for (clock.m2 = limit->m2.min;
551 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 552 /* m1 is always 0 in Pineview */
553 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 554 break;
555 for (clock.n = limit->n.min;
556 clock.n <= limit->n.max; clock.n++) {
557 for (clock.p1 = limit->p1.min;
558 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 559 int this_err;
560
2177832f 561 intel_clock(dev, refclk, &clock);
1b894b59
CW		 562 if (!intel_PLL_is_valid(dev, limit,
563 &clock))
79e53945
JB		 564 continue;
565
566 this_err = abs(clock.dot - target);
567 if (this_err < err) {
568 *best_clock = clock;
569 err = this_err;
570 }
571 }
572 }
573 }
574 }
575
576 return (err != target);
577}
578
d4906093
ML		 579static bool
580intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
581 int target, int refclk, intel_clock_t *best_clock)
582{
583 struct drm_device *dev = crtc->dev;
584 struct drm_i915_private *dev_priv = dev->dev_private;
585 intel_clock_t clock;
586 int max_n;
587 bool found;
6ba770dc
AJ		 588 /* approximately equals target * 0.00585 */
589 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 590 found = false;
591
592 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 593 int lvds_reg;
594
c619eed4 595 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 596 lvds_reg = PCH_LVDS;
597 else
598 lvds_reg = LVDS;
599 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
d4906093
ML		 600 LVDS_CLKB_POWER_UP)
601 clock.p2 = limit->p2.p2_fast;
602 else
603 clock.p2 = limit->p2.p2_slow;
604 } else {
605 if (target < limit->p2.dot_limit)
606 clock.p2 = limit->p2.p2_slow;
607 else
608 clock.p2 = limit->p2.p2_fast;
609 }
610
611 memset(best_clock, 0, sizeof(*best_clock));
612 max_n = limit->n.max;
f77f13e2 613 /* based on hardware requirement, prefer smaller n to precision */
d4906093 614 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 615 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 616 for (clock.m1 = limit->m1.max;
617 clock.m1 >= limit->m1.min; clock.m1--) {
618 for (clock.m2 = limit->m2.max;
619 clock.m2 >= limit->m2.min; clock.m2--) {
620 for (clock.p1 = limit->p1.max;
621 clock.p1 >= limit->p1.min; clock.p1--) {
622 int this_err;
623
2177832f 624 intel_clock(dev, refclk, &clock);
1b894b59
CW		 625 if (!intel_PLL_is_valid(dev, limit,
626 &clock))
d4906093 627 continue;
1b894b59
CW		 628
629 this_err = abs(clock.dot - target);
d4906093
ML		 630 if (this_err < err_most) {
631 *best_clock = clock;
632 err_most = this_err;
633 max_n = clock.n;
634 found = true;
635 }
636 }
637 }
638 }
639 }
2c07245f
ZW		 640 return found;
641}
642
5eb08b69 643static bool
f2b115e6
AJ		 644intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
645 int target, int refclk, intel_clock_t *best_clock)
5eb08b69
ZW		 646{
647 struct drm_device *dev = crtc->dev;
648 intel_clock_t clock;
4547668a 649
5eb08b69
ZW		 650 if (target < 200000) {
651 clock.n = 1;
652 clock.p1 = 2;
653 clock.p2 = 10;
654 clock.m1 = 12;
655 clock.m2 = 9;
656 } else {
657 clock.n = 2;
658 clock.p1 = 1;
659 clock.p2 = 10;
660 clock.m1 = 14;
661 clock.m2 = 8;
662 }
663 intel_clock(dev, refclk, &clock);
664 memcpy(best_clock, &clock, sizeof(intel_clock_t));
665 return true;
666}
667
a4fc5ed6
KP		 668/* DisplayPort has only two frequencies, 162MHz and 270MHz */
669static bool
670intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
671 int target, int refclk, intel_clock_t *best_clock)
672{
5eddb70b
CW		 673 intel_clock_t clock;
674 if (target < 200000) {
675 clock.p1 = 2;
676 clock.p2 = 10;
677 clock.n = 2;
678 clock.m1 = 23;
679 clock.m2 = 8;
680 } else {
681 clock.p1 = 1;
682 clock.p2 = 10;
683 clock.n = 1;
684 clock.m1 = 14;
685 clock.m2 = 2;
686 }
687 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
688 clock.p = (clock.p1 * clock.p2);
689 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
690 clock.vco = 0;
691 memcpy(best_clock, &clock, sizeof(intel_clock_t));
692 return true;
a4fc5ed6
KP		 693}
694
9d0498a2
JB		 695/**
696 * intel_wait_for_vblank - wait for vblank on a given pipe
697 * @dev: drm device
698 * @pipe: pipe to wait for
699 *
700 * Wait for vblank to occur on a given pipe. Needed for various bits of
701 * mode setting code.
702 */
703void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 704{
9d0498a2 705 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 706 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 707
300387c0
CW		 708 /* Clear existing vblank status. Note this will clear any other
709 * sticky status fields as well.
710 *
711 * This races with i915_driver_irq_handler() with the result
712 * that either function could miss a vblank event. Here it is not
713 * fatal, as we will either wait upon the next vblank interrupt or
714 * timeout. Generally speaking intel_wait_for_vblank() is only
715 * called during modeset at which time the GPU should be idle and
716 * should *not* be performing page flips and thus not waiting on
717 * vblanks...
718 * Currently, the result of us stealing a vblank from the irq
719 * handler is that a single frame will be skipped during swapbuffers.
720 */
721 I915_WRITE(pipestat_reg,
722 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
723
9d0498a2 724 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 725 if (wait_for(I915_READ(pipestat_reg) &
726 PIPE_VBLANK_INTERRUPT_STATUS,
727 50))
9d0498a2
JB		 728 DRM_DEBUG_KMS("vblank wait timed out\n");
729}
730
ab7ad7f6
KP		 731/*
732 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 733 * @dev: drm device
734 * @pipe: pipe to wait for
735 *
736 * After disabling a pipe, we can't wait for vblank in the usual way,
737 * spinning on the vblank interrupt status bit, since we won't actually
738 * see an interrupt when the pipe is disabled.
739 *
ab7ad7f6
KP		 740 * On Gen4 and above:
741 * wait for the pipe register state bit to turn off
742 *
743 * Otherwise:
744 * wait for the display line value to settle (it usually
745 * ends up stopping at the start of the next frame).
58e10eb9 746 *
9d0498a2 747 */
58e10eb9 748void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 749{
750 struct drm_i915_private *dev_priv = dev->dev_private;
ab7ad7f6
KP		 751
752 if (INTEL_INFO(dev)->gen >= 4) {
58e10eb9 753 int reg = PIPECONF(pipe);
ab7ad7f6
KP		 754
755 /* Wait for the Pipe State to go off */
58e10eb9
CW		 756 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
757 100))
ab7ad7f6
KP		 758 DRM_DEBUG_KMS("pipe_off wait timed out\n");
759 } else {
760 u32 last_line;
58e10eb9 761 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 762 unsigned long timeout = jiffies + msecs_to_jiffies(100);
763
764 /* Wait for the display line to settle */
765 do {
58e10eb9 766 last_line = I915_READ(reg) & DSL_LINEMASK;
ab7ad7f6 767 mdelay(5);
58e10eb9 768 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
ab7ad7f6
KP		 769 time_after(timeout, jiffies));
770 if (time_after(jiffies, timeout))
771 DRM_DEBUG_KMS("pipe_off wait timed out\n");
772 }
79e53945
JB		 773}
774
b24e7179
JB		 775static const char *state_string(bool enabled)
776{
777 return enabled ? "on" : "off";
778}
779
780/* Only for pre-ILK configs */
781static void assert_pll(struct drm_i915_private *dev_priv,
782 enum pipe pipe, bool state)
783{
784 int reg;
785 u32 val;
786 bool cur_state;
787
788 reg = DPLL(pipe);
789 val = I915_READ(reg);
790 cur_state = !!(val & DPLL_VCO_ENABLE);
791 WARN(cur_state != state,
792 "PLL state assertion failure (expected %s, current %s)\n",
793 state_string(state), state_string(cur_state));
794}
795#define assert_pll_enabled(d, p) assert_pll(d, p, true)
796#define assert_pll_disabled(d, p) assert_pll(d, p, false)
797
040484af
JB		 798/* For ILK+ */
799static void assert_pch_pll(struct drm_i915_private *dev_priv,
800 enum pipe pipe, bool state)
801{
802 int reg;
803 u32 val;
804 bool cur_state;
805
d3ccbe86
JB		 806 if (HAS_PCH_CPT(dev_priv->dev)) {
807 u32 pch_dpll;
808
809 pch_dpll = I915_READ(PCH_DPLL_SEL);
810
811 /* Make sure the selected PLL is enabled to the transcoder */
812 WARN(!((pch_dpll >> (4 * pipe)) & 8),
813 "transcoder %d PLL not enabled\n", pipe);
814
815 /* Convert the transcoder pipe number to a pll pipe number */
816 pipe = (pch_dpll >> (4 * pipe)) & 1;
817 }
818
040484af
JB		 819 reg = PCH_DPLL(pipe);
820 val = I915_READ(reg);
821 cur_state = !!(val & DPLL_VCO_ENABLE);
822 WARN(cur_state != state,
823 "PCH PLL state assertion failure (expected %s, current %s)\n",
824 state_string(state), state_string(cur_state));
825}
826#define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
827#define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
828
829static void assert_fdi_tx(struct drm_i915_private *dev_priv,
830 enum pipe pipe, bool state)
831{
832 int reg;
833 u32 val;
834 bool cur_state;
835
836 reg = FDI_TX_CTL(pipe);
837 val = I915_READ(reg);
838 cur_state = !!(val & FDI_TX_ENABLE);
839 WARN(cur_state != state,
840 "FDI TX state assertion failure (expected %s, current %s)\n",
841 state_string(state), state_string(cur_state));
842}
843#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
844#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
845
846static void assert_fdi_rx(struct drm_i915_private *dev_priv,
847 enum pipe pipe, bool state)
848{
849 int reg;
850 u32 val;
851 bool cur_state;
852
853 reg = FDI_RX_CTL(pipe);
854 val = I915_READ(reg);
855 cur_state = !!(val & FDI_RX_ENABLE);
856 WARN(cur_state != state,
857 "FDI RX state assertion failure (expected %s, current %s)\n",
858 state_string(state), state_string(cur_state));
859}
860#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
861#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
862
863static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
864 enum pipe pipe)
865{
866 int reg;
867 u32 val;
868
869 /* ILK FDI PLL is always enabled */
870 if (dev_priv->info->gen == 5)
871 return;
872
873 reg = FDI_TX_CTL(pipe);
874 val = I915_READ(reg);
875 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
876}
877
878static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
879 enum pipe pipe)
880{
881 int reg;
882 u32 val;
883
884 reg = FDI_RX_CTL(pipe);
885 val = I915_READ(reg);
886 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
887}
888
ea0760cf
JB		 889static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
890 enum pipe pipe)
891{
892 int pp_reg, lvds_reg;
893 u32 val;
894 enum pipe panel_pipe = PIPE_A;
0de3b485 895 bool locked = true;
ea0760cf
JB		 896
897 if (HAS_PCH_SPLIT(dev_priv->dev)) {
898 pp_reg = PCH_PP_CONTROL;
899 lvds_reg = PCH_LVDS;
900 } else {
901 pp_reg = PP_CONTROL;
902 lvds_reg = LVDS;
903 }
904
905 val = I915_READ(pp_reg);
906 if (!(val & PANEL_POWER_ON) ||
907 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
908 locked = false;
909
910 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
911 panel_pipe = PIPE_B;
912
913 WARN(panel_pipe == pipe && locked,
914 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 915 pipe_name(pipe));
ea0760cf
JB		 916}
917
63d7bbe9
JB		 918static void assert_pipe(struct drm_i915_private *dev_priv,
919 enum pipe pipe, bool state)
b24e7179
JB		 920{
921 int reg;
922 u32 val;
63d7bbe9 923 bool cur_state;
b24e7179
JB		 924
925 reg = PIPECONF(pipe);
926 val = I915_READ(reg);
63d7bbe9
JB		 927 cur_state = !!(val & PIPECONF_ENABLE);
928 WARN(cur_state != state,
929 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 930 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179 931}
63d7bbe9
JB		 932#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
933#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
b24e7179
JB		 934
935static void assert_plane_enabled(struct drm_i915_private *dev_priv,
936 enum plane plane)
937{
938 int reg;
939 u32 val;
940
941 reg = DSPCNTR(plane);
942 val = I915_READ(reg);
943 WARN(!(val & DISPLAY_PLANE_ENABLE),
944 "plane %c assertion failure, should be active but is disabled\n",
9db4a9c7 945 plane_name(plane));
b24e7179
JB		 946}
947
948static void assert_planes_disabled(struct drm_i915_private *dev_priv,
949 enum pipe pipe)
950{
951 int reg, i;
952 u32 val;
953 int cur_pipe;
954
19ec1358
JB		 955 /* Planes are fixed to pipes on ILK+ */
956 if (HAS_PCH_SPLIT(dev_priv->dev))
957 return;
958
b24e7179
JB		 959 /* Need to check both planes against the pipe */
960 for (i = 0; i < 2; i++) {
961 reg = DSPCNTR(i);
962 val = I915_READ(reg);
963 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
964 DISPPLANE_SEL_PIPE_SHIFT;
965 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 966 "plane %c assertion failure, should be off on pipe %c but is still active\n",
967 plane_name(i), pipe_name(pipe));
b24e7179
JB		 968 }
969}
970
92f2584a
JB		 971static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
972{
973 u32 val;
974 bool enabled;
975
976 val = I915_READ(PCH_DREF_CONTROL);
977 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
978 DREF_SUPERSPREAD_SOURCE_MASK));
979 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
980}
981
982static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
983 enum pipe pipe)
984{
985 int reg;
986 u32 val;
987 bool enabled;
988
989 reg = TRANSCONF(pipe);
990 val = I915_READ(reg);
991 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 992 WARN(enabled,
993 "transcoder assertion failed, should be off on pipe %c but is still active\n",
994 pipe_name(pipe));
92f2584a
JB		 995}
996
4e634389
KP		 997static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
998 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 999{
1000 if ((val & DP_PORT_EN) == 0)
1001 return false;
1002
1003 if (HAS_PCH_CPT(dev_priv->dev)) {
1004 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1005 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1006 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1007 return false;
1008 } else {
1009 if ((val & DP_PIPE_MASK) != (pipe << 30))
1010 return false;
1011 }
1012 return true;
1013}
1014
1519b995
KP		 1015static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1016 enum pipe pipe, u32 val)
1017{
1018 if ((val & PORT_ENABLE) == 0)
1019 return false;
1020
1021 if (HAS_PCH_CPT(dev_priv->dev)) {
1022 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1023 return false;
1024 } else {
1025 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1026 return false;
1027 }
1028 return true;
1029}
1030
1031static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1032 enum pipe pipe, u32 val)
1033{
1034 if ((val & LVDS_PORT_EN) == 0)
1035 return false;
1036
1037 if (HAS_PCH_CPT(dev_priv->dev)) {
1038 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1039 return false;
1040 } else {
1041 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1042 return false;
1043 }
1044 return true;
1045}
1046
1047static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1048 enum pipe pipe, u32 val)
1049{
1050 if ((val & ADPA_DAC_ENABLE) == 0)
1051 return false;
1052 if (HAS_PCH_CPT(dev_priv->dev)) {
1053 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1054 return false;
1055 } else {
1056 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1057 return false;
1058 }
1059 return true;
1060}
1061
291906f1 1062static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1063 enum pipe pipe, int reg, u32 port_sel)
291906f1 1064{
47a05eca 1065 u32 val = I915_READ(reg);
4e634389 1066 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1067 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1068 reg, pipe_name(pipe));
291906f1
JB		 1069}
1070
1071static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1072 enum pipe pipe, int reg)
1073{
47a05eca 1074 u32 val = I915_READ(reg);
1519b995 1075 WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
291906f1 1076 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1077 reg, pipe_name(pipe));
291906f1
JB		 1078}
1079
1080static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1081 enum pipe pipe)
1082{
1083 int reg;
1084 u32 val;
291906f1 1085
f0575e92
KP		 1086 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1087 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1088 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1089
1090 reg = PCH_ADPA;
1091 val = I915_READ(reg);
1519b995 1092 WARN(adpa_pipe_enabled(dev_priv, val, pipe),
291906f1 1093 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1094 pipe_name(pipe));
291906f1
JB		 1095
1096 reg = PCH_LVDS;
1097 val = I915_READ(reg);
1519b995 1098 WARN(lvds_pipe_enabled(dev_priv, val, pipe),
291906f1 1099 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1100 pipe_name(pipe));
291906f1
JB		 1101
1102 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1103 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1104 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1105}
1106
63d7bbe9
JB		 1107/**
1108 * intel_enable_pll - enable a PLL
1109 * @dev_priv: i915 private structure
1110 * @pipe: pipe PLL to enable
1111 *
1112 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1113 * make sure the PLL reg is writable first though, since the panel write
1114 * protect mechanism may be enabled.
1115 *
1116 * Note! This is for pre-ILK only.
1117 */
1118static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1119{
1120 int reg;
1121 u32 val;
1122
1123 /* No really, not for ILK+ */
1124 BUG_ON(dev_priv->info->gen >= 5);
1125
1126 /* PLL is protected by panel, make sure we can write it */
1127 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1128 assert_panel_unlocked(dev_priv, pipe);
1129
1130 reg = DPLL(pipe);
1131 val = I915_READ(reg);
1132 val |= DPLL_VCO_ENABLE;
1133
1134 /* We do this three times for luck */
1135 I915_WRITE(reg, val);
1136 POSTING_READ(reg);
1137 udelay(150); /* wait for warmup */
1138 I915_WRITE(reg, val);
1139 POSTING_READ(reg);
1140 udelay(150); /* wait for warmup */
1141 I915_WRITE(reg, val);
1142 POSTING_READ(reg);
1143 udelay(150); /* wait for warmup */
1144}
1145
1146/**
1147 * intel_disable_pll - disable a PLL
1148 * @dev_priv: i915 private structure
1149 * @pipe: pipe PLL to disable
1150 *
1151 * Disable the PLL for @pipe, making sure the pipe is off first.
1152 *
1153 * Note! This is for pre-ILK only.
1154 */
1155static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1156{
1157 int reg;
1158 u32 val;
1159
1160 /* Don't disable pipe A or pipe A PLLs if needed */
1161 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1162 return;
1163
1164 /* Make sure the pipe isn't still relying on us */
1165 assert_pipe_disabled(dev_priv, pipe);
1166
1167 reg = DPLL(pipe);
1168 val = I915_READ(reg);
1169 val &= ~DPLL_VCO_ENABLE;
1170 I915_WRITE(reg, val);
1171 POSTING_READ(reg);
1172}
1173
92f2584a
JB		 1174/**
1175 * intel_enable_pch_pll - enable PCH PLL
1176 * @dev_priv: i915 private structure
1177 * @pipe: pipe PLL to enable
1178 *
1179 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1180 * drives the transcoder clock.
1181 */
1182static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1183 enum pipe pipe)
1184{
1185 int reg;
1186 u32 val;
1187
4c609cb8
JB		 1188 if (pipe > 1)
1189 return;
1190
92f2584a
JB		 1191 /* PCH only available on ILK+ */
1192 BUG_ON(dev_priv->info->gen < 5);
1193
1194 /* PCH refclock must be enabled first */
1195 assert_pch_refclk_enabled(dev_priv);
1196
1197 reg = PCH_DPLL(pipe);
1198 val = I915_READ(reg);
1199 val |= DPLL_VCO_ENABLE;
1200 I915_WRITE(reg, val);
1201 POSTING_READ(reg);
1202 udelay(200);
1203}
1204
1205static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1206 enum pipe pipe)
1207{
1208 int reg;
1209 u32 val;
1210
4c609cb8
JB		 1211 if (pipe > 1)
1212 return;
1213
92f2584a
JB		 1214 /* PCH only available on ILK+ */
1215 BUG_ON(dev_priv->info->gen < 5);
1216
1217 /* Make sure transcoder isn't still depending on us */
1218 assert_transcoder_disabled(dev_priv, pipe);
1219
1220 reg = PCH_DPLL(pipe);
1221 val = I915_READ(reg);
1222 val &= ~DPLL_VCO_ENABLE;
1223 I915_WRITE(reg, val);
1224 POSTING_READ(reg);
1225 udelay(200);
1226}
1227
040484af
JB		 1228static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1229 enum pipe pipe)
1230{
1231 int reg;
1232 u32 val;
1233
1234 /* PCH only available on ILK+ */
1235 BUG_ON(dev_priv->info->gen < 5);
1236
1237 /* Make sure PCH DPLL is enabled */
1238 assert_pch_pll_enabled(dev_priv, pipe);
1239
1240 /* FDI must be feeding us bits for PCH ports */
1241 assert_fdi_tx_enabled(dev_priv, pipe);
1242 assert_fdi_rx_enabled(dev_priv, pipe);
1243
1244 reg = TRANSCONF(pipe);
1245 val = I915_READ(reg);
e9bcff5c
JB		 1246
1247 if (HAS_PCH_IBX(dev_priv->dev)) {
1248 /*
1249 * make the BPC in transcoder be consistent with
1250 * that in pipeconf reg.
1251 */
1252 val &= ~PIPE_BPC_MASK;
1253 val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1254 }
040484af
JB		 1255 I915_WRITE(reg, val | TRANS_ENABLE);
1256 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1257 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1258}
1259
1260static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1261 enum pipe pipe)
1262{
1263 int reg;
1264 u32 val;
1265
1266 /* FDI relies on the transcoder */
1267 assert_fdi_tx_disabled(dev_priv, pipe);
1268 assert_fdi_rx_disabled(dev_priv, pipe);
1269
291906f1
JB		 1270 /* Ports must be off as well */
1271 assert_pch_ports_disabled(dev_priv, pipe);
1272
040484af
JB		 1273 reg = TRANSCONF(pipe);
1274 val = I915_READ(reg);
1275 val &= ~TRANS_ENABLE;
1276 I915_WRITE(reg, val);
1277 /* wait for PCH transcoder off, transcoder state */
1278 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1279 DRM_ERROR("failed to disable transcoder\n");
1280}
1281
b24e7179 1282/**
309cfea8 1283 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1284 * @dev_priv: i915 private structure
1285 * @pipe: pipe to enable
040484af 1286 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1287 *
1288 * Enable @pipe, making sure that various hardware specific requirements
1289 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1290 *
1291 * @pipe should be %PIPE_A or %PIPE_B.
1292 *
1293 * Will wait until the pipe is actually running (i.e. first vblank) before
1294 * returning.
1295 */
040484af
JB		 1296static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1297 bool pch_port)
b24e7179
JB		 1298{
1299 int reg;
1300 u32 val;
1301
1302 /*
1303 * A pipe without a PLL won't actually be able to drive bits from
1304 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1305 * need the check.
1306 */
1307 if (!HAS_PCH_SPLIT(dev_priv->dev))
1308 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1309 else {
1310 if (pch_port) {
1311 /* if driving the PCH, we need FDI enabled */
1312 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1313 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1314 }
1315 /* FIXME: assert CPU port conditions for SNB+ */
1316 }
b24e7179
JB		 1317
1318 reg = PIPECONF(pipe);
1319 val = I915_READ(reg);
00d70b15
CW		 1320 if (val & PIPECONF_ENABLE)
1321 return;
1322
1323 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1324 intel_wait_for_vblank(dev_priv->dev, pipe);
1325}
1326
1327/**
309cfea8 1328 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1329 * @dev_priv: i915 private structure
1330 * @pipe: pipe to disable
1331 *
1332 * Disable @pipe, making sure that various hardware specific requirements
1333 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1334 *
1335 * @pipe should be %PIPE_A or %PIPE_B.
1336 *
1337 * Will wait until the pipe has shut down before returning.
1338 */
1339static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1340 enum pipe pipe)
1341{
1342 int reg;
1343 u32 val;
1344
1345 /*
1346 * Make sure planes won't keep trying to pump pixels to us,
1347 * or we might hang the display.
1348 */
1349 assert_planes_disabled(dev_priv, pipe);
1350
1351 /* Don't disable pipe A or pipe A PLLs if needed */
1352 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1353 return;
1354
1355 reg = PIPECONF(pipe);
1356 val = I915_READ(reg);
00d70b15
CW		 1357 if ((val & PIPECONF_ENABLE) == 0)
1358 return;
1359
1360 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1361 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1362}
1363
d74362c9
KP		 1364/*
1365 * Plane regs are double buffered, going from enabled->disabled needs a
1366 * trigger in order to latch. The display address reg provides this.
1367 */
1368static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1369 enum plane plane)
1370{
1371 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1372 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1373}
1374
b24e7179
JB		 1375/**
1376 * intel_enable_plane - enable a display plane on a given pipe
1377 * @dev_priv: i915 private structure
1378 * @plane: plane to enable
1379 * @pipe: pipe being fed
1380 *
1381 * Enable @plane on @pipe, making sure that @pipe is running first.
1382 */
1383static void intel_enable_plane(struct drm_i915_private *dev_priv,
1384 enum plane plane, enum pipe pipe)
1385{
1386 int reg;
1387 u32 val;
1388
1389 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1390 assert_pipe_enabled(dev_priv, pipe);
1391
1392 reg = DSPCNTR(plane);
1393 val = I915_READ(reg);
00d70b15
CW		 1394 if (val & DISPLAY_PLANE_ENABLE)
1395 return;
1396
1397 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1398 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1399 intel_wait_for_vblank(dev_priv->dev, pipe);
1400}
1401
b24e7179
JB		 1402/**
1403 * intel_disable_plane - disable a display plane
1404 * @dev_priv: i915 private structure
1405 * @plane: plane to disable
1406 * @pipe: pipe consuming the data
1407 *
1408 * Disable @plane; should be an independent operation.
1409 */
1410static void intel_disable_plane(struct drm_i915_private *dev_priv,
1411 enum plane plane, enum pipe pipe)
1412{
1413 int reg;
1414 u32 val;
1415
1416 reg = DSPCNTR(plane);
1417 val = I915_READ(reg);
00d70b15
CW		 1418 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1419 return;
1420
1421 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1422 intel_flush_display_plane(dev_priv, plane);
1423 intel_wait_for_vblank(dev_priv->dev, pipe);
1424}
1425
47a05eca 1426static void disable_pch_dp(struct drm_i915_private *dev_priv,
f0575e92 1427 enum pipe pipe, int reg, u32 port_sel)
47a05eca
JB		 1428{
1429 u32 val = I915_READ(reg);
4e634389 1430 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
f0575e92 1431 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
47a05eca 1432 I915_WRITE(reg, val & ~DP_PORT_EN);
f0575e92 1433 }
47a05eca
JB		 1434}
1435
1436static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1437 enum pipe pipe, int reg)
1438{
1439 u32 val = I915_READ(reg);
1519b995 1440 if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
f0575e92
KP		 1441 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1442 reg, pipe);
47a05eca 1443 I915_WRITE(reg, val & ~PORT_ENABLE);
f0575e92 1444 }
47a05eca
JB		 1445}
1446
1447/* Disable any ports connected to this transcoder */
1448static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1449 enum pipe pipe)
1450{
1451 u32 reg, val;
1452
1453 val = I915_READ(PCH_PP_CONTROL);
1454 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1455
f0575e92
KP		 1456 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1457 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1458 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
47a05eca
JB		 1459
1460 reg = PCH_ADPA;
1461 val = I915_READ(reg);
1519b995 1462 if (adpa_pipe_enabled(dev_priv, val, pipe))
47a05eca
JB		 1463 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1464
1465 reg = PCH_LVDS;
1466 val = I915_READ(reg);
1519b995
KP		 1467 if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1468 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
47a05eca
JB		 1469 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1470 POSTING_READ(reg);
1471 udelay(100);
1472 }
1473
1474 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1475 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1476 disable_pch_hdmi(dev_priv, pipe, HDMID);
1477}
1478
43a9539f
CW		 1479static void i8xx_disable_fbc(struct drm_device *dev)
1480{
1481 struct drm_i915_private *dev_priv = dev->dev_private;
1482 u32 fbc_ctl;
1483
1484 /* Disable compression */
1485 fbc_ctl = I915_READ(FBC_CONTROL);
1486 if ((fbc_ctl & FBC_CTL_EN) == 0)
1487 return;
1488
1489 fbc_ctl &= ~FBC_CTL_EN;
1490 I915_WRITE(FBC_CONTROL, fbc_ctl);
1491
1492 /* Wait for compressing bit to clear */
1493 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1494 DRM_DEBUG_KMS("FBC idle timed out\n");
1495 return;
1496 }
1497
1498 DRM_DEBUG_KMS("disabled FBC\n");
1499}
1500
80824003
JB		 1501static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1502{
1503 struct drm_device *dev = crtc->dev;
1504 struct drm_i915_private *dev_priv = dev->dev_private;
1505 struct drm_framebuffer *fb = crtc->fb;
1506 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1507 struct drm_i915_gem_object *obj = intel_fb->obj;
80824003 1508 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
016b9b61 1509 int cfb_pitch;
80824003
JB		 1510 int plane, i;
1511 u32 fbc_ctl, fbc_ctl2;
1512
016b9b61
CW		 1513 cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1514 if (fb->pitch < cfb_pitch)
1515 cfb_pitch = fb->pitch;
80824003
JB		 1516
1517 /* FBC_CTL wants 64B units */
016b9b61
CW		 1518 cfb_pitch = (cfb_pitch / 64) - 1;
1519 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
80824003
JB		 1520
1521 /* Clear old tags */
1522 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1523 I915_WRITE(FBC_TAG + (i * 4), 0);
1524
1525 /* Set it up... */
de568510
CW		 1526 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
1527 fbc_ctl2 |= plane;
80824003
JB		 1528 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1529 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1530
1531 /* enable it... */
1532 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
ee25df2b 1533 if (IS_I945GM(dev))
49677901 1534 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
016b9b61 1535 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
80824003 1536 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
016b9b61 1537 fbc_ctl |= obj->fence_reg;
80824003
JB		 1538 I915_WRITE(FBC_CONTROL, fbc_ctl);
1539
016b9b61
CW		 1540 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
1541 cfb_pitch, crtc->y, intel_crtc->plane);
80824003
JB		 1542}
1543
ee5382ae 1544static bool i8xx_fbc_enabled(struct drm_device *dev)
80824003 1545{
80824003
JB		 1546 struct drm_i915_private *dev_priv = dev->dev_private;
1547
1548 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1549}
1550
74dff282
JB		 1551static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1552{
1553 struct drm_device *dev = crtc->dev;
1554 struct drm_i915_private *dev_priv = dev->dev_private;
1555 struct drm_framebuffer *fb = crtc->fb;
1556 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1557 struct drm_i915_gem_object *obj = intel_fb->obj;
74dff282 1558 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5eddb70b 1559 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
74dff282
JB		 1560 unsigned long stall_watermark = 200;
1561 u32 dpfc_ctl;
1562
74dff282 1563 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
016b9b61 1564 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
de568510 1565 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
74dff282 1566
74dff282
JB		 1567 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1568 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1569 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1570 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1571
1572 /* enable it... */
1573 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1574
28c97730 1575 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
74dff282
JB		 1576}
1577
43a9539f 1578static void g4x_disable_fbc(struct drm_device *dev)
74dff282
JB		 1579{
1580 struct drm_i915_private *dev_priv = dev->dev_private;
1581 u32 dpfc_ctl;
1582
1583 /* Disable compression */
1584 dpfc_ctl = I915_READ(DPFC_CONTROL);
bed4a673
CW		 1585 if (dpfc_ctl & DPFC_CTL_EN) {
1586 dpfc_ctl &= ~DPFC_CTL_EN;
1587 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
74dff282 1588
bed4a673
CW		 1589 DRM_DEBUG_KMS("disabled FBC\n");
1590 }
74dff282
JB		 1591}
1592
ee5382ae 1593static bool g4x_fbc_enabled(struct drm_device *dev)
74dff282 1594{
74dff282
JB		 1595 struct drm_i915_private *dev_priv = dev->dev_private;
1596
1597 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1598}
1599
4efe0708
JB		 1600static void sandybridge_blit_fbc_update(struct drm_device *dev)
1601{
1602 struct drm_i915_private *dev_priv = dev->dev_private;
1603 u32 blt_ecoskpd;
1604
1605 /* Make sure blitter notifies FBC of writes */
fcca7926 1606 gen6_gt_force_wake_get(dev_priv);
4efe0708
JB		 1607 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1608 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1609 GEN6_BLITTER_LOCK_SHIFT;
1610 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1611 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1612 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1613 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1614 GEN6_BLITTER_LOCK_SHIFT);
1615 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1616 POSTING_READ(GEN6_BLITTER_ECOSKPD);
fcca7926 1617 gen6_gt_force_wake_put(dev_priv);
4efe0708
JB		 1618}
1619
b52eb4dc
ZY		 1620static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1621{
1622 struct drm_device *dev = crtc->dev;
1623 struct drm_i915_private *dev_priv = dev->dev_private;
1624 struct drm_framebuffer *fb = crtc->fb;
1625 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1626 struct drm_i915_gem_object *obj = intel_fb->obj;
b52eb4dc 1627 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5eddb70b 1628 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
b52eb4dc
ZY		 1629 unsigned long stall_watermark = 200;
1630 u32 dpfc_ctl;
1631
bed4a673 1632 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
b52eb4dc
ZY		 1633 dpfc_ctl &= DPFC_RESERVED;
1634 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
9ce9d069
CW		 1635 /* Set persistent mode for front-buffer rendering, ala X. */
1636 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
016b9b61 1637 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
de568510 1638 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
b52eb4dc 1639
b52eb4dc
ZY		 1640 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1641 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1642 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1643 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
05394f39 1644 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
b52eb4dc 1645 /* enable it... */
bed4a673 1646 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
b52eb4dc 1647
9c04f015
YL		 1648 if (IS_GEN6(dev)) {
1649 I915_WRITE(SNB_DPFC_CTL_SA,
016b9b61 1650 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
9c04f015 1651 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
4efe0708 1652 sandybridge_blit_fbc_update(dev);
9c04f015
YL		 1653 }
1654
b52eb4dc
ZY		 1655 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1656}
1657
43a9539f 1658static void ironlake_disable_fbc(struct drm_device *dev)
b52eb4dc
ZY		 1659{
1660 struct drm_i915_private *dev_priv = dev->dev_private;
1661 u32 dpfc_ctl;
1662
1663 /* Disable compression */
1664 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
bed4a673
CW		 1665 if (dpfc_ctl & DPFC_CTL_EN) {
1666 dpfc_ctl &= ~DPFC_CTL_EN;
1667 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
b52eb4dc 1668
bed4a673
CW		 1669 DRM_DEBUG_KMS("disabled FBC\n");
1670 }
b52eb4dc
ZY		 1671}
1672
1673static bool ironlake_fbc_enabled(struct drm_device *dev)
1674{
1675 struct drm_i915_private *dev_priv = dev->dev_private;
1676
1677 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1678}
1679
ee5382ae
AJ		 1680bool intel_fbc_enabled(struct drm_device *dev)
1681{
1682 struct drm_i915_private *dev_priv = dev->dev_private;
1683
1684 if (!dev_priv->display.fbc_enabled)
1685 return false;
1686
1687 return dev_priv->display.fbc_enabled(dev);
1688}
1689
1630fe75
CW		 1690static void intel_fbc_work_fn(struct work_struct *__work)
1691{
1692 struct intel_fbc_work *work =
1693 container_of(to_delayed_work(__work),
1694 struct intel_fbc_work, work);
1695 struct drm_device *dev = work->crtc->dev;
1696 struct drm_i915_private *dev_priv = dev->dev_private;
1697
1698 mutex_lock(&dev->struct_mutex);
1699 if (work == dev_priv->fbc_work) {
1700 /* Double check that we haven't switched fb without cancelling
1701 * the prior work.
1702 */
016b9b61 1703 if (work->crtc->fb == work->fb) {
1630fe75
CW		 1704 dev_priv->display.enable_fbc(work->crtc,
1705 work->interval);
1706
016b9b61
CW		 1707 dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
1708 dev_priv->cfb_fb = work->crtc->fb->base.id;
1709 dev_priv->cfb_y = work->crtc->y;
1710 }
1711
1630fe75
CW		 1712 dev_priv->fbc_work = NULL;
1713 }
1714 mutex_unlock(&dev->struct_mutex);
1715
1716 kfree(work);
1717}
1718
1719static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
1720{
1721 if (dev_priv->fbc_work == NULL)
1722 return;
1723
1724 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
1725
1726 /* Synchronisation is provided by struct_mutex and checking of
1727 * dev_priv->fbc_work, so we can perform the cancellation
1728 * entirely asynchronously.
1729 */
1730 if (cancel_delayed_work(&dev_priv->fbc_work->work))
1731 /* tasklet was killed before being run, clean up */
1732 kfree(dev_priv->fbc_work);
1733
1734 /* Mark the work as no longer wanted so that if it does
1735 * wake-up (because the work was already running and waiting
1736 * for our mutex), it will discover that is no longer
1737 * necessary to run.
1738 */
1739 dev_priv->fbc_work = NULL;
1740}
1741
43a9539f 1742static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
ee5382ae 1743{
1630fe75
CW		 1744 struct intel_fbc_work *work;
1745 struct drm_device *dev = crtc->dev;
1746 struct drm_i915_private *dev_priv = dev->dev_private;
ee5382ae
AJ		 1747
1748 if (!dev_priv->display.enable_fbc)
1749 return;
1750
1630fe75
CW		 1751 intel_cancel_fbc_work(dev_priv);
1752
1753 work = kzalloc(sizeof *work, GFP_KERNEL);
1754 if (work == NULL) {
1755 dev_priv->display.enable_fbc(crtc, interval);
1756 return;
1757 }
1758
1759 work->crtc = crtc;
1760 work->fb = crtc->fb;
1761 work->interval = interval;
1762 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
1763
1764 dev_priv->fbc_work = work;
1765
1766 DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
1767
1768 /* Delay the actual enabling to let pageflipping cease and the
016b9b61
CW		 1769 * display to settle before starting the compression. Note that
1770 * this delay also serves a second purpose: it allows for a
1771 * vblank to pass after disabling the FBC before we attempt
1772 * to modify the control registers.
1630fe75
CW		 1773 *
1774 * A more complicated solution would involve tracking vblanks
1775 * following the termination of the page-flipping sequence
1776 * and indeed performing the enable as a co-routine and not
1777 * waiting synchronously upon the vblank.
1778 */
1779 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
ee5382ae
AJ		 1780}
1781
1782void intel_disable_fbc(struct drm_device *dev)
1783{
1784 struct drm_i915_private *dev_priv = dev->dev_private;
1785
1630fe75
CW		 1786 intel_cancel_fbc_work(dev_priv);
1787
ee5382ae
AJ		 1788 if (!dev_priv->display.disable_fbc)
1789 return;
1790
1791 dev_priv->display.disable_fbc(dev);
016b9b61 1792 dev_priv->cfb_plane = -1;
ee5382ae
AJ		 1793}
1794
80824003
JB		 1795/**
1796 * intel_update_fbc - enable/disable FBC as needed
bed4a673 1797 * @dev: the drm_device
80824003
JB		 1798 *
1799 * Set up the framebuffer compression hardware at mode set time. We
1800 * enable it if possible:
1801 * - plane A only (on pre-965)
1802 * - no pixel mulitply/line duplication
1803 * - no alpha buffer discard
1804 * - no dual wide
1805 * - framebuffer <= 2048 in width, 1536 in height
1806 *
1807 * We can't assume that any compression will take place (worst case),
1808 * so the compressed buffer has to be the same size as the uncompressed
1809 * one. It also must reside (along with the line length buffer) in
1810 * stolen memory.
1811 *
1812 * We need to enable/disable FBC on a global basis.
1813 */
bed4a673 1814static void intel_update_fbc(struct drm_device *dev)
80824003 1815{
80824003 1816 struct drm_i915_private *dev_priv = dev->dev_private;
bed4a673
CW		 1817 struct drm_crtc *crtc = NULL, *tmp_crtc;
1818 struct intel_crtc *intel_crtc;
1819 struct drm_framebuffer *fb;
80824003 1820 struct intel_framebuffer *intel_fb;
05394f39 1821 struct drm_i915_gem_object *obj;
cd0de039 1822 int enable_fbc;
9c928d16
JB		 1823
1824 DRM_DEBUG_KMS("\n");
80824003
JB		 1825
1826 if (!i915_powersave)
1827 return;
1828
ee5382ae 1829 if (!I915_HAS_FBC(dev))
e70236a8
JB		 1830 return;
1831
80824003
JB		 1832 /*
1833 * If FBC is already on, we just have to verify that we can
1834 * keep it that way...
1835 * Need to disable if:
9c928d16 1836 * - more than one pipe is active
80824003
JB		 1837 * - changing FBC params (stride, fence, mode)
1838 * - new fb is too large to fit in compressed buffer
1839 * - going to an unsupported config (interlace, pixel multiply, etc.)
1840 */
9c928d16 1841 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
d210246a 1842 if (tmp_crtc->enabled && tmp_crtc->fb) {
bed4a673
CW		 1843 if (crtc) {
1844 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1845 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1846 goto out_disable;
1847 }
1848 crtc = tmp_crtc;
1849 }
9c928d16 1850 }
bed4a673
CW		 1851
1852 if (!crtc || crtc->fb == NULL) {
1853 DRM_DEBUG_KMS("no output, disabling\n");
1854 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
9c928d16
JB		 1855 goto out_disable;
1856 }
bed4a673
CW		 1857
1858 intel_crtc = to_intel_crtc(crtc);
1859 fb = crtc->fb;
1860 intel_fb = to_intel_framebuffer(fb);
05394f39 1861 obj = intel_fb->obj;
bed4a673 1862
cd0de039
KP		 1863 enable_fbc = i915_enable_fbc;
1864 if (enable_fbc < 0) {
1865 DRM_DEBUG_KMS("fbc set to per-chip default\n");
1866 enable_fbc = 1;
1867 if (INTEL_INFO(dev)->gen <= 5)
1868 enable_fbc = 0;
1869 }
1870 if (!enable_fbc) {
1871 DRM_DEBUG_KMS("fbc disabled per module param\n");
c1a9f047
JB		 1872 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1873 goto out_disable;
1874 }
05394f39 1875 if (intel_fb->obj->base.size > dev_priv->cfb_size) {
28c97730 1876 DRM_DEBUG_KMS("framebuffer too large, disabling "
5eddb70b 1877 "compression\n");
b5e50c3f 1878 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
80824003
JB		 1879 goto out_disable;
1880 }
bed4a673
CW		 1881 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1882 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
28c97730 1883 DRM_DEBUG_KMS("mode incompatible with compression, "
5eddb70b 1884 "disabling\n");
b5e50c3f 1885 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
80824003
JB		 1886 goto out_disable;
1887 }
bed4a673
CW		 1888 if ((crtc->mode.hdisplay > 2048) ||
1889 (crtc->mode.vdisplay > 1536)) {
28c97730 1890 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
b5e50c3f 1891 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
80824003
JB		 1892 goto out_disable;
1893 }
bed4a673 1894 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
28c97730 1895 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
b5e50c3f 1896 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
80824003
JB		 1897 goto out_disable;
1898 }
de568510
CW		 1899
1900 /* The use of a CPU fence is mandatory in order to detect writes
1901 * by the CPU to the scanout and trigger updates to the FBC.
1902 */
1903 if (obj->tiling_mode != I915_TILING_X ||
1904 obj->fence_reg == I915_FENCE_REG_NONE) {
1905 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
b5e50c3f 1906 dev_priv->no_fbc_reason = FBC_NOT_TILED;
80824003
JB		 1907 goto out_disable;
1908 }
1909
c924b934
JW		 1910 /* If the kernel debugger is active, always disable compression */
1911 if (in_dbg_master())
1912 goto out_disable;
1913
016b9b61
CW		 1914 /* If the scanout has not changed, don't modify the FBC settings.
1915 * Note that we make the fundamental assumption that the fb->obj
1916 * cannot be unpinned (and have its GTT offset and fence revoked)
1917 * without first being decoupled from the scanout and FBC disabled.
1918 */
1919 if (dev_priv->cfb_plane == intel_crtc->plane &&
1920 dev_priv->cfb_fb == fb->base.id &&
1921 dev_priv->cfb_y == crtc->y)
1922 return;
1923
1924 if (intel_fbc_enabled(dev)) {
1925 /* We update FBC along two paths, after changing fb/crtc
1926 * configuration (modeswitching) and after page-flipping
1927 * finishes. For the latter, we know that not only did
1928 * we disable the FBC at the start of the page-flip
1929 * sequence, but also more than one vblank has passed.
1930 *
1931 * For the former case of modeswitching, it is possible
1932 * to switch between two FBC valid configurations
1933 * instantaneously so we do need to disable the FBC
1934 * before we can modify its control registers. We also
1935 * have to wait for the next vblank for that to take
1936 * effect. However, since we delay enabling FBC we can
1937 * assume that a vblank has passed since disabling and
1938 * that we can safely alter the registers in the deferred
1939 * callback.
1940 *
1941 * In the scenario that we go from a valid to invalid
1942 * and then back to valid FBC configuration we have
1943 * no strict enforcement that a vblank occurred since
1944 * disabling the FBC. However, along all current pipe
1945 * disabling paths we do need to wait for a vblank at
1946 * some point. And we wait before enabling FBC anyway.
1947 */
1948 DRM_DEBUG_KMS("disabling active FBC for update\n");
1949 intel_disable_fbc(dev);
1950 }
1951
bed4a673 1952 intel_enable_fbc(crtc, 500);
80824003
JB		 1953 return;
1954
1955out_disable:
80824003 1956 /* Multiple disables should be harmless */
a939406f
CW		 1957 if (intel_fbc_enabled(dev)) {
1958 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
ee5382ae 1959 intel_disable_fbc(dev);
a939406f 1960 }
80824003
JB		 1961}
1962
127bd2ac 1963int
48b956c5 1964intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1965 struct drm_i915_gem_object *obj,
919926ae 1966 struct intel_ring_buffer *pipelined)
6b95a207 1967{
ce453d81 1968 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1969 u32 alignment;
1970 int ret;
1971
05394f39 1972 switch (obj->tiling_mode) {
6b95a207 1973 case I915_TILING_NONE:
534843da
CW		 1974 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1975 alignment = 128 * 1024;
a6c45cf0 1976 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1977 alignment = 4 * 1024;
1978 else
1979 alignment = 64 * 1024;
6b95a207
KH		 1980 break;
1981 case I915_TILING_X:
1982 /* pin() will align the object as required by fence */
1983 alignment = 0;
1984 break;
1985 case I915_TILING_Y:
1986 /* FIXME: Is this true? */
1987 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1988 return -EINVAL;
1989 default:
1990 BUG();
1991 }
1992
ce453d81 1993 dev_priv->mm.interruptible = false;
2da3b9b9 1994 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1995 if (ret)
ce453d81 1996 goto err_interruptible;
6b95a207
KH		 1997
1998 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1999 * fence, whereas 965+ only requires a fence if using
2000 * framebuffer compression. For simplicity, we always install
2001 * a fence as the cost is not that onerous.
2002 */
05394f39 2003 if (obj->tiling_mode != I915_TILING_NONE) {
ce453d81 2004 ret = i915_gem_object_get_fence(obj, pipelined);
48b956c5
CW		 2005 if (ret)
2006 goto err_unpin;
6b95a207
KH		 2007 }
2008
ce453d81 2009 dev_priv->mm.interruptible = true;
6b95a207 2010 return 0;
48b956c5
CW		 2011
2012err_unpin:
2013 i915_gem_object_unpin(obj);
ce453d81
CW		 2014err_interruptible:
2015 dev_priv->mm.interruptible = true;
48b956c5 2016 return ret;
6b95a207
KH		 2017}
2018
17638cd6
JB		 2019static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2020 int x, int y)
81255565
JB		 2021{
2022 struct drm_device *dev = crtc->dev;
2023 struct drm_i915_private *dev_priv = dev->dev_private;
2024 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2025 struct intel_framebuffer *intel_fb;
05394f39 2026 struct drm_i915_gem_object *obj;
81255565
JB		 2027 int plane = intel_crtc->plane;
2028 unsigned long Start, Offset;
81255565 2029 u32 dspcntr;
5eddb70b 2030 u32 reg;
81255565
JB		 2031
2032 switch (plane) {
2033 case 0:
2034 case 1:
2035 break;
2036 default:
2037 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2038 return -EINVAL;
2039 }
2040
2041 intel_fb = to_intel_framebuffer(fb);
2042 obj = intel_fb->obj;
81255565 2043
5eddb70b
CW		 2044 reg = DSPCNTR(plane);
2045 dspcntr = I915_READ(reg);
81255565
JB		 2046 /* Mask out pixel format bits in case we change it */
2047 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2048 switch (fb->bits_per_pixel) {
2049 case 8:
2050 dspcntr |= DISPPLANE_8BPP;
2051 break;
2052 case 16:
2053 if (fb->depth == 15)
2054 dspcntr |= DISPPLANE_15_16BPP;
2055 else
2056 dspcntr |= DISPPLANE_16BPP;
2057 break;
2058 case 24:
2059 case 32:
2060 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2061 break;
2062 default:
17638cd6 2063 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
81255565
JB		 2064 return -EINVAL;
2065 }
a6c45cf0 2066 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2067 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2068 dspcntr |= DISPPLANE_TILED;
2069 else
2070 dspcntr &= ~DISPPLANE_TILED;
2071 }
2072
5eddb70b 2073 I915_WRITE(reg, dspcntr);
81255565 2074
05394f39 2075 Start = obj->gtt_offset;
81255565
JB		 2076 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
2077
4e6cfefc
CW		 2078 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2079 Start, Offset, x, y, fb->pitch);
5eddb70b 2080 I915_WRITE(DSPSTRIDE(plane), fb->pitch);
a6c45cf0 2081 if (INTEL_INFO(dev)->gen >= 4) {
5eddb70b
CW		 2082 I915_WRITE(DSPSURF(plane), Start);
2083 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2084 I915_WRITE(DSPADDR(plane), Offset);
2085 } else
2086 I915_WRITE(DSPADDR(plane), Start + Offset);
2087 POSTING_READ(reg);
81255565 2088
17638cd6
JB		 2089 return 0;
2090}
2091
2092static int ironlake_update_plane(struct drm_crtc *crtc,
2093 struct drm_framebuffer *fb, int x, int y)
2094{
2095 struct drm_device *dev = crtc->dev;
2096 struct drm_i915_private *dev_priv = dev->dev_private;
2097 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2098 struct intel_framebuffer *intel_fb;
2099 struct drm_i915_gem_object *obj;
2100 int plane = intel_crtc->plane;
2101 unsigned long Start, Offset;
2102 u32 dspcntr;
2103 u32 reg;
2104
2105 switch (plane) {
2106 case 0:
2107 case 1:
27f8227b 2108 case 2:
17638cd6
JB		 2109 break;
2110 default:
2111 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2112 return -EINVAL;
2113 }
2114
2115 intel_fb = to_intel_framebuffer(fb);
2116 obj = intel_fb->obj;
2117
2118 reg = DSPCNTR(plane);
2119 dspcntr = I915_READ(reg);
2120 /* Mask out pixel format bits in case we change it */
2121 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2122 switch (fb->bits_per_pixel) {
2123 case 8:
2124 dspcntr |= DISPPLANE_8BPP;
2125 break;
2126 case 16:
2127 if (fb->depth != 16)
2128 return -EINVAL;
2129
2130 dspcntr |= DISPPLANE_16BPP;
2131 break;
2132 case 24:
2133 case 32:
2134 if (fb->depth == 24)
2135 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2136 else if (fb->depth == 30)
2137 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2138 else
2139 return -EINVAL;
2140 break;
2141 default:
2142 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2143 return -EINVAL;
2144 }
2145
2146 if (obj->tiling_mode != I915_TILING_NONE)
2147 dspcntr |= DISPPLANE_TILED;
2148 else
2149 dspcntr &= ~DISPPLANE_TILED;
2150
2151 /* must disable */
2152 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2153
2154 I915_WRITE(reg, dspcntr);
2155
2156 Start = obj->gtt_offset;
2157 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
2158
2159 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2160 Start, Offset, x, y, fb->pitch);
2161 I915_WRITE(DSPSTRIDE(plane), fb->pitch);
2162 I915_WRITE(DSPSURF(plane), Start);
2163 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2164 I915_WRITE(DSPADDR(plane), Offset);
2165 POSTING_READ(reg);
2166
2167 return 0;
2168}
2169
2170/* Assume fb object is pinned & idle & fenced and just update base pointers */
2171static int
2172intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2173 int x, int y, enum mode_set_atomic state)
2174{
2175 struct drm_device *dev = crtc->dev;
2176 struct drm_i915_private *dev_priv = dev->dev_private;
2177 int ret;
2178
2179 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2180 if (ret)
2181 return ret;
2182
bed4a673 2183 intel_update_fbc(dev);
3dec0095 2184 intel_increase_pllclock(crtc);
81255565
JB		 2185
2186 return 0;
2187}
2188
5c3b82e2 2189static int
3c4fdcfb
KH		 2190intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2191 struct drm_framebuffer *old_fb)
79e53945
JB		 2192{
2193 struct drm_device *dev = crtc->dev;
79e53945
JB		 2194 struct drm_i915_master_private *master_priv;
2195 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5c3b82e2 2196 int ret;
79e53945
JB		 2197
2198 /* no fb bound */
2199 if (!crtc->fb) {
a5071c2f 2200 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2201 return 0;
2202 }
2203
265db958 2204 switch (intel_crtc->plane) {
5c3b82e2
CW		 2205 case 0:
2206 case 1:
2207 break;
27f8227b
JB		 2208 case 2:
2209 if (IS_IVYBRIDGE(dev))
2210 break;
2211 /* fall through otherwise */
5c3b82e2 2212 default:
a5071c2f 2213 DRM_ERROR("no plane for crtc\n");
5c3b82e2 2214 return -EINVAL;
79e53945
JB		 2215 }
2216
5c3b82e2 2217 mutex_lock(&dev->struct_mutex);
265db958
CW		 2218 ret = intel_pin_and_fence_fb_obj(dev,
2219 to_intel_framebuffer(crtc->fb)->obj,
919926ae 2220 NULL);
5c3b82e2
CW		 2221 if (ret != 0) {
2222 mutex_unlock(&dev->struct_mutex);
a5071c2f 2223 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2224 return ret;
2225 }
79e53945 2226
265db958 2227 if (old_fb) {
e6c3a2a6 2228 struct drm_i915_private *dev_priv = dev->dev_private;
05394f39 2229 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
265db958 2230
e6c3a2a6 2231 wait_event(dev_priv->pending_flip_queue,
01eec727 2232 atomic_read(&dev_priv->mm.wedged) ||
05394f39 2233 atomic_read(&obj->pending_flip) == 0);
85345517
CW		 2234
2235 /* Big Hammer, we also need to ensure that any pending
2236 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2237 * current scanout is retired before unpinning the old
2238 * framebuffer.
01eec727
CW		 2239 *
2240 * This should only fail upon a hung GPU, in which case we
2241 * can safely continue.
85345517 2242 */
a8198eea 2243 ret = i915_gem_object_finish_gpu(obj);
01eec727 2244 (void) ret;
265db958
CW		 2245 }
2246
21c74a8e
JW		 2247 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2248 LEAVE_ATOMIC_MODE_SET);
4e6cfefc 2249 if (ret) {
265db958 2250 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
5c3b82e2 2251 mutex_unlock(&dev->struct_mutex);
a5071c2f 2252 DRM_ERROR("failed to update base address\n");
4e6cfefc 2253 return ret;
79e53945 2254 }
3c4fdcfb 2255
b7f1de28
CW		 2256 if (old_fb) {
2257 intel_wait_for_vblank(dev, intel_crtc->pipe);
265db958 2258 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2259 }
652c393a 2260
5c3b82e2 2261 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 2262
2263 if (!dev->primary->master)
5c3b82e2 2264 return 0;
79e53945
JB		 2265
2266 master_priv = dev->primary->master->driver_priv;
2267 if (!master_priv->sarea_priv)
5c3b82e2 2268 return 0;
79e53945 2269
265db958 2270 if (intel_crtc->pipe) {
79e53945
JB		 2271 master_priv->sarea_priv->pipeB_x = x;
2272 master_priv->sarea_priv->pipeB_y = y;
5c3b82e2
CW		 2273 } else {
2274 master_priv->sarea_priv->pipeA_x = x;
2275 master_priv->sarea_priv->pipeA_y = y;
79e53945 2276 }
5c3b82e2
CW		 2277
2278 return 0;
79e53945
JB		 2279}
2280
5eddb70b 2281static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
32f9d658
ZW		 2282{
2283 struct drm_device *dev = crtc->dev;
2284 struct drm_i915_private *dev_priv = dev->dev_private;
2285 u32 dpa_ctl;
2286
28c97730 2287 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
32f9d658
ZW		 2288 dpa_ctl = I915_READ(DP_A);
2289 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2290
2291 if (clock < 200000) {
2292 u32 temp;
2293 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2294 /* workaround for 160Mhz:
2295 1) program 0x4600c bits 15:0 = 0x8124
2296 2) program 0x46010 bit 0 = 1
2297 3) program 0x46034 bit 24 = 1
2298 4) program 0x64000 bit 14 = 1
2299 */
2300 temp = I915_READ(0x4600c);
2301 temp &= 0xffff0000;
2302 I915_WRITE(0x4600c, temp | 0x8124);
2303
2304 temp = I915_READ(0x46010);
2305 I915_WRITE(0x46010, temp | 1);
2306
2307 temp = I915_READ(0x46034);
2308 I915_WRITE(0x46034, temp | (1 << 24));
2309 } else {
2310 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2311 }
2312 I915_WRITE(DP_A, dpa_ctl);
2313
5eddb70b 2314 POSTING_READ(DP_A);
32f9d658
ZW		 2315 udelay(500);
2316}
2317
5e84e1a4
ZW		 2318static void intel_fdi_normal_train(struct drm_crtc *crtc)
2319{
2320 struct drm_device *dev = crtc->dev;
2321 struct drm_i915_private *dev_priv = dev->dev_private;
2322 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2323 int pipe = intel_crtc->pipe;
2324 u32 reg, temp;
2325
2326 /* enable normal train */
2327 reg = FDI_TX_CTL(pipe);
2328 temp = I915_READ(reg);
61e499bf 2329 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2330 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2331 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2332 } else {
2333 temp &= ~FDI_LINK_TRAIN_NONE;
2334 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2335 }
5e84e1a4
ZW		 2336 I915_WRITE(reg, temp);
2337
2338 reg = FDI_RX_CTL(pipe);
2339 temp = I915_READ(reg);
2340 if (HAS_PCH_CPT(dev)) {
2341 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2342 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2343 } else {
2344 temp &= ~FDI_LINK_TRAIN_NONE;
2345 temp |= FDI_LINK_TRAIN_NONE;
2346 }
2347 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2348
2349 /* wait one idle pattern time */
2350 POSTING_READ(reg);
2351 udelay(1000);
357555c0
JB		 2352
2353 /* IVB wants error correction enabled */
2354 if (IS_IVYBRIDGE(dev))
2355 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2356 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2357}
2358
291427f5
JB		 2359static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2360{
2361 struct drm_i915_private *dev_priv = dev->dev_private;
2362 u32 flags = I915_READ(SOUTH_CHICKEN1);
2363
2364 flags |= FDI_PHASE_SYNC_OVR(pipe);
2365 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2366 flags |= FDI_PHASE_SYNC_EN(pipe);
2367 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2368 POSTING_READ(SOUTH_CHICKEN1);
2369}
2370
8db9d77b
ZW		 2371/* The FDI link training functions for ILK/Ibexpeak. */
2372static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2373{
2374 struct drm_device *dev = crtc->dev;
2375 struct drm_i915_private *dev_priv = dev->dev_private;
2376 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2377 int pipe = intel_crtc->pipe;
0fc932b8 2378 int plane = intel_crtc->plane;
5eddb70b 2379 u32 reg, temp, tries;
8db9d77b 2380
0fc932b8
JB		 2381 /* FDI needs bits from pipe & plane first */
2382 assert_pipe_enabled(dev_priv, pipe);
2383 assert_plane_enabled(dev_priv, plane);
2384
e1a44743
AJ		 2385 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2386 for train result */
5eddb70b
CW		 2387 reg = FDI_RX_IMR(pipe);
2388 temp = I915_READ(reg);
e1a44743
AJ		 2389 temp &= ~FDI_RX_SYMBOL_LOCK;
2390 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2391 I915_WRITE(reg, temp);
2392 I915_READ(reg);
e1a44743
AJ		 2393 udelay(150);
2394
8db9d77b 2395 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2396 reg = FDI_TX_CTL(pipe);
2397 temp = I915_READ(reg);
77ffb597
AJ		 2398 temp &= ~(7 << 19);
2399 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2400 temp &= ~FDI_LINK_TRAIN_NONE;
2401 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2402 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2403
5eddb70b
CW		 2404 reg = FDI_RX_CTL(pipe);
2405 temp = I915_READ(reg);
8db9d77b
ZW		 2406 temp &= ~FDI_LINK_TRAIN_NONE;
2407 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2408 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2409
2410 POSTING_READ(reg);
8db9d77b
ZW		 2411 udelay(150);
2412
5b2adf89 2413 /* Ironlake workaround, enable clock pointer after FDI enable*/
6f06ce18
JB		 2414 if (HAS_PCH_IBX(dev)) {
2415 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2416 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2417 FDI_RX_PHASE_SYNC_POINTER_EN);
2418 }
5b2adf89 2419
5eddb70b 2420 reg = FDI_RX_IIR(pipe);
e1a44743 2421 for (tries = 0; tries < 5; tries++) {
5eddb70b 2422 temp = I915_READ(reg);
8db9d77b
ZW		 2423 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2424
2425 if ((temp & FDI_RX_BIT_LOCK)) {
2426 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2427 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2428 break;
2429 }
8db9d77b 2430 }
e1a44743 2431 if (tries == 5)
5eddb70b 2432 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2433
2434 /* Train 2 */
5eddb70b
CW		 2435 reg = FDI_TX_CTL(pipe);
2436 temp = I915_READ(reg);
8db9d77b
ZW		 2437 temp &= ~FDI_LINK_TRAIN_NONE;
2438 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2439 I915_WRITE(reg, temp);
8db9d77b 2440
5eddb70b
CW		 2441 reg = FDI_RX_CTL(pipe);
2442 temp = I915_READ(reg);
8db9d77b
ZW		 2443 temp &= ~FDI_LINK_TRAIN_NONE;
2444 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2445 I915_WRITE(reg, temp);
8db9d77b 2446
5eddb70b
CW		 2447 POSTING_READ(reg);
2448 udelay(150);
8db9d77b 2449
5eddb70b 2450 reg = FDI_RX_IIR(pipe);
e1a44743 2451 for (tries = 0; tries < 5; tries++) {
5eddb70b 2452 temp = I915_READ(reg);
8db9d77b
ZW		 2453 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2454
2455 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2456 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2457 DRM_DEBUG_KMS("FDI train 2 done.\n");
2458 break;
2459 }
8db9d77b 2460 }
e1a44743 2461 if (tries == 5)
5eddb70b 2462 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2463
2464 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2465
8db9d77b
ZW		 2466}
2467
0206e353 2468static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2469 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2470 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2471 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2472 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2473};
2474
2475/* The FDI link training functions for SNB/Cougarpoint. */
2476static void gen6_fdi_link_train(struct drm_crtc *crtc)
2477{
2478 struct drm_device *dev = crtc->dev;
2479 struct drm_i915_private *dev_priv = dev->dev_private;
2480 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2481 int pipe = intel_crtc->pipe;
5eddb70b 2482 u32 reg, temp, i;
8db9d77b 2483
e1a44743
AJ		 2484 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2485 for train result */
5eddb70b
CW		 2486 reg = FDI_RX_IMR(pipe);
2487 temp = I915_READ(reg);
e1a44743
AJ		 2488 temp &= ~FDI_RX_SYMBOL_LOCK;
2489 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2490 I915_WRITE(reg, temp);
2491
2492 POSTING_READ(reg);
e1a44743
AJ		 2493 udelay(150);
2494
8db9d77b 2495 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2496 reg = FDI_TX_CTL(pipe);
2497 temp = I915_READ(reg);
77ffb597
AJ		 2498 temp &= ~(7 << 19);
2499 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2500 temp &= ~FDI_LINK_TRAIN_NONE;
2501 temp |= FDI_LINK_TRAIN_PATTERN_1;
2502 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2503 /* SNB-B */
2504 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2505 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2506
5eddb70b
CW		 2507 reg = FDI_RX_CTL(pipe);
2508 temp = I915_READ(reg);
8db9d77b
ZW		 2509 if (HAS_PCH_CPT(dev)) {
2510 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2511 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2512 } else {
2513 temp &= ~FDI_LINK_TRAIN_NONE;
2514 temp |= FDI_LINK_TRAIN_PATTERN_1;
2515 }
5eddb70b
CW		 2516 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2517
2518 POSTING_READ(reg);
8db9d77b
ZW		 2519 udelay(150);
2520
291427f5
JB		 2521 if (HAS_PCH_CPT(dev))
2522 cpt_phase_pointer_enable(dev, pipe);
2523
0206e353 2524 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2525 reg = FDI_TX_CTL(pipe);
2526 temp = I915_READ(reg);
8db9d77b
ZW		 2527 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2528 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2529 I915_WRITE(reg, temp);
2530
2531 POSTING_READ(reg);
8db9d77b
ZW		 2532 udelay(500);
2533
5eddb70b
CW		 2534 reg = FDI_RX_IIR(pipe);
2535 temp = I915_READ(reg);
8db9d77b
ZW		 2536 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2537
2538 if (temp & FDI_RX_BIT_LOCK) {
5eddb70b 2539 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2540 DRM_DEBUG_KMS("FDI train 1 done.\n");
2541 break;
2542 }
2543 }
2544 if (i == 4)
5eddb70b 2545 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2546
2547 /* Train 2 */
5eddb70b
CW		 2548 reg = FDI_TX_CTL(pipe);
2549 temp = I915_READ(reg);
8db9d77b
ZW		 2550 temp &= ~FDI_LINK_TRAIN_NONE;
2551 temp |= FDI_LINK_TRAIN_PATTERN_2;
2552 if (IS_GEN6(dev)) {
2553 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2554 /* SNB-B */
2555 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2556 }
5eddb70b 2557 I915_WRITE(reg, temp);
8db9d77b 2558
5eddb70b
CW		 2559 reg = FDI_RX_CTL(pipe);
2560 temp = I915_READ(reg);
8db9d77b
ZW		 2561 if (HAS_PCH_CPT(dev)) {
2562 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2563 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2564 } else {
2565 temp &= ~FDI_LINK_TRAIN_NONE;
2566 temp |= FDI_LINK_TRAIN_PATTERN_2;
2567 }
5eddb70b
CW		 2568 I915_WRITE(reg, temp);
2569
2570 POSTING_READ(reg);
8db9d77b
ZW		 2571 udelay(150);
2572
0206e353 2573 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2574 reg = FDI_TX_CTL(pipe);
2575 temp = I915_READ(reg);
8db9d77b
ZW		 2576 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2577 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2578 I915_WRITE(reg, temp);
2579
2580 POSTING_READ(reg);
8db9d77b
ZW		 2581 udelay(500);
2582
5eddb70b
CW		 2583 reg = FDI_RX_IIR(pipe);
2584 temp = I915_READ(reg);
8db9d77b
ZW		 2585 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2586
2587 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2588 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2589 DRM_DEBUG_KMS("FDI train 2 done.\n");
2590 break;
2591 }
2592 }
2593 if (i == 4)
5eddb70b 2594 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2595
2596 DRM_DEBUG_KMS("FDI train done.\n");
2597}
2598
357555c0
JB		 2599/* Manual link training for Ivy Bridge A0 parts */
2600static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2601{
2602 struct drm_device *dev = crtc->dev;
2603 struct drm_i915_private *dev_priv = dev->dev_private;
2604 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2605 int pipe = intel_crtc->pipe;
2606 u32 reg, temp, i;
2607
2608 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2609 for train result */
2610 reg = FDI_RX_IMR(pipe);
2611 temp = I915_READ(reg);
2612 temp &= ~FDI_RX_SYMBOL_LOCK;
2613 temp &= ~FDI_RX_BIT_LOCK;
2614 I915_WRITE(reg, temp);
2615
2616 POSTING_READ(reg);
2617 udelay(150);
2618
2619 /* enable CPU FDI TX and PCH FDI RX */
2620 reg = FDI_TX_CTL(pipe);
2621 temp = I915_READ(reg);
2622 temp &= ~(7 << 19);
2623 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2624 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2625 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2626 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2627 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2628 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2629 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2630
2631 reg = FDI_RX_CTL(pipe);
2632 temp = I915_READ(reg);
2633 temp &= ~FDI_LINK_TRAIN_AUTO;
2634 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2635 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2636 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2637 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2638
2639 POSTING_READ(reg);
2640 udelay(150);
2641
291427f5
JB		 2642 if (HAS_PCH_CPT(dev))
2643 cpt_phase_pointer_enable(dev, pipe);
2644
0206e353 2645 for (i = 0; i < 4; i++) {
357555c0
JB		 2646 reg = FDI_TX_CTL(pipe);
2647 temp = I915_READ(reg);
2648 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2649 temp |= snb_b_fdi_train_param[i];
2650 I915_WRITE(reg, temp);
2651
2652 POSTING_READ(reg);
2653 udelay(500);
2654
2655 reg = FDI_RX_IIR(pipe);
2656 temp = I915_READ(reg);
2657 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2658
2659 if (temp & FDI_RX_BIT_LOCK ||
2660 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2661 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2662 DRM_DEBUG_KMS("FDI train 1 done.\n");
2663 break;
2664 }
2665 }
2666 if (i == 4)
2667 DRM_ERROR("FDI train 1 fail!\n");
2668
2669 /* Train 2 */
2670 reg = FDI_TX_CTL(pipe);
2671 temp = I915_READ(reg);
2672 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2673 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2674 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2675 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2676 I915_WRITE(reg, temp);
2677
2678 reg = FDI_RX_CTL(pipe);
2679 temp = I915_READ(reg);
2680 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2681 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2682 I915_WRITE(reg, temp);
2683
2684 POSTING_READ(reg);
2685 udelay(150);
2686
0206e353 2687 for (i = 0; i < 4; i++) {
357555c0
JB		 2688 reg = FDI_TX_CTL(pipe);
2689 temp = I915_READ(reg);
2690 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2691 temp |= snb_b_fdi_train_param[i];
2692 I915_WRITE(reg, temp);
2693
2694 POSTING_READ(reg);
2695 udelay(500);
2696
2697 reg = FDI_RX_IIR(pipe);
2698 temp = I915_READ(reg);
2699 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2700
2701 if (temp & FDI_RX_SYMBOL_LOCK) {
2702 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2703 DRM_DEBUG_KMS("FDI train 2 done.\n");
2704 break;
2705 }
2706 }
2707 if (i == 4)
2708 DRM_ERROR("FDI train 2 fail!\n");
2709
2710 DRM_DEBUG_KMS("FDI train done.\n");
2711}
2712
2713static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2c07245f
ZW		 2714{
2715 struct drm_device *dev = crtc->dev;
2716 struct drm_i915_private *dev_priv = dev->dev_private;
2717 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2718 int pipe = intel_crtc->pipe;
5eddb70b 2719 u32 reg, temp;
79e53945 2720
c64e311e 2721 /* Write the TU size bits so error detection works */
5eddb70b
CW		 2722 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2723 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
c64e311e 2724
c98e9dcf 2725 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2726 reg = FDI_RX_CTL(pipe);
2727 temp = I915_READ(reg);
2728 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2729 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW		 2730 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2731 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2732
2733 POSTING_READ(reg);
c98e9dcf
JB		 2734 udelay(200);
2735
2736 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2737 temp = I915_READ(reg);
2738 I915_WRITE(reg, temp | FDI_PCDCLK);
2739
2740 POSTING_READ(reg);
c98e9dcf
JB		 2741 udelay(200);
2742
2743 /* Enable CPU FDI TX PLL, always on for Ironlake */
5eddb70b
CW		 2744 reg = FDI_TX_CTL(pipe);
2745 temp = I915_READ(reg);
c98e9dcf 2746 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
5eddb70b
CW		 2747 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2748
2749 POSTING_READ(reg);
c98e9dcf 2750 udelay(100);
6be4a607 2751 }
0e23b99d
JB		 2752}
2753
291427f5
JB		 2754static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2755{
2756 struct drm_i915_private *dev_priv = dev->dev_private;
2757 u32 flags = I915_READ(SOUTH_CHICKEN1);
2758
2759 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2760 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2761 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2762 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2763 POSTING_READ(SOUTH_CHICKEN1);
2764}
0fc932b8
JB		 2765static void ironlake_fdi_disable(struct drm_crtc *crtc)
2766{
2767 struct drm_device *dev = crtc->dev;
2768 struct drm_i915_private *dev_priv = dev->dev_private;
2769 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2770 int pipe = intel_crtc->pipe;
2771 u32 reg, temp;
2772
2773 /* disable CPU FDI tx and PCH FDI rx */
2774 reg = FDI_TX_CTL(pipe);
2775 temp = I915_READ(reg);
2776 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2777 POSTING_READ(reg);
2778
2779 reg = FDI_RX_CTL(pipe);
2780 temp = I915_READ(reg);
2781 temp &= ~(0x7 << 16);
2782 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2783 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2784
2785 POSTING_READ(reg);
2786 udelay(100);
2787
2788 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2789 if (HAS_PCH_IBX(dev)) {
2790 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 2791 I915_WRITE(FDI_RX_CHICKEN(pipe),
2792 I915_READ(FDI_RX_CHICKEN(pipe) &
6f06ce18 2793 ~FDI_RX_PHASE_SYNC_POINTER_EN));
291427f5
JB		 2794 } else if (HAS_PCH_CPT(dev)) {
2795 cpt_phase_pointer_disable(dev, pipe);
6f06ce18 2796 }
0fc932b8
JB		 2797
2798 /* still set train pattern 1 */
2799 reg = FDI_TX_CTL(pipe);
2800 temp = I915_READ(reg);
2801 temp &= ~FDI_LINK_TRAIN_NONE;
2802 temp |= FDI_LINK_TRAIN_PATTERN_1;
2803 I915_WRITE(reg, temp);
2804
2805 reg = FDI_RX_CTL(pipe);
2806 temp = I915_READ(reg);
2807 if (HAS_PCH_CPT(dev)) {
2808 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2809 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2810 } else {
2811 temp &= ~FDI_LINK_TRAIN_NONE;
2812 temp |= FDI_LINK_TRAIN_PATTERN_1;
2813 }
2814 /* BPC in FDI rx is consistent with that in PIPECONF */
2815 temp &= ~(0x07 << 16);
2816 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2817 I915_WRITE(reg, temp);
2818
2819 POSTING_READ(reg);
2820 udelay(100);
2821}
2822
6b383a7f
CW		 2823/*
2824 * When we disable a pipe, we need to clear any pending scanline wait events
2825 * to avoid hanging the ring, which we assume we are waiting on.
2826 */
2827static void intel_clear_scanline_wait(struct drm_device *dev)
2828{
2829 struct drm_i915_private *dev_priv = dev->dev_private;
8168bd48 2830 struct intel_ring_buffer *ring;
6b383a7f
CW		 2831 u32 tmp;
2832
2833 if (IS_GEN2(dev))
2834 /* Can't break the hang on i8xx */
2835 return;
2836
1ec14ad3 2837 ring = LP_RING(dev_priv);
8168bd48
CW		 2838 tmp = I915_READ_CTL(ring);
2839 if (tmp & RING_WAIT)
2840 I915_WRITE_CTL(ring, tmp);
6b383a7f
CW		 2841}
2842
e6c3a2a6
CW		 2843static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2844{
05394f39 2845 struct drm_i915_gem_object *obj;
e6c3a2a6
CW		 2846 struct drm_i915_private *dev_priv;
2847
2848 if (crtc->fb == NULL)
2849 return;
2850
05394f39 2851 obj = to_intel_framebuffer(crtc->fb)->obj;
e6c3a2a6
CW		 2852 dev_priv = crtc->dev->dev_private;
2853 wait_event(dev_priv->pending_flip_queue,
05394f39 2854 atomic_read(&obj->pending_flip) == 0);
e6c3a2a6
CW		 2855}
2856
040484af
JB		 2857static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2858{
2859 struct drm_device *dev = crtc->dev;
2860 struct drm_mode_config *mode_config = &dev->mode_config;
2861 struct intel_encoder *encoder;
2862
2863 /*
2864 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2865 * must be driven by its own crtc; no sharing is possible.
2866 */
2867 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2868 if (encoder->base.crtc != crtc)
2869 continue;
2870
2871 switch (encoder->type) {
2872 case INTEL_OUTPUT_EDP:
2873 if (!intel_encoder_is_pch_edp(&encoder->base))
2874 return false;
2875 continue;
2876 }
2877 }
2878
2879 return true;
2880}
2881
f67a559d
JB		 2882/*
2883 * Enable PCH resources required for PCH ports:
2884 * - PCH PLLs
2885 * - FDI training & RX/TX
2886 * - update transcoder timings
2887 * - DP transcoding bits
2888 * - transcoder
2889 */
2890static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2891{
2892 struct drm_device *dev = crtc->dev;
2893 struct drm_i915_private *dev_priv = dev->dev_private;
2894 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2895 int pipe = intel_crtc->pipe;
5eddb70b 2896 u32 reg, temp;
2c07245f 2897
c98e9dcf 2898 /* For PCH output, training FDI link */
674cf967 2899 dev_priv->display.fdi_link_train(crtc);
2c07245f 2900
92f2584a 2901 intel_enable_pch_pll(dev_priv, pipe);
8db9d77b 2902
c98e9dcf
JB		 2903 if (HAS_PCH_CPT(dev)) {
2904 /* Be sure PCH DPLL SEL is set */
2905 temp = I915_READ(PCH_DPLL_SEL);
5eddb70b 2906 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
c98e9dcf 2907 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
5eddb70b 2908 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
c98e9dcf 2909 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
27f8227b
JB		 2910 else if (pipe == 2 && (temp & TRANSC_DPLL_ENABLE) == 0)
2911 temp |= (TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
c98e9dcf 2912 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 2913 }
5eddb70b 2914
d9b6cb56
JB		 2915 /* set transcoder timing, panel must allow it */
2916 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 2917 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2918 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2919 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 2920
5eddb70b
CW		 2921 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2922 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2923 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
8db9d77b 2924
5e84e1a4
ZW		 2925 intel_fdi_normal_train(crtc);
2926
c98e9dcf
JB		 2927 /* For PCH DP, enable TRANS_DP_CTL */
2928 if (HAS_PCH_CPT(dev) &&
2929 intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
9325c9f0 2930 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
5eddb70b
CW		 2931 reg = TRANS_DP_CTL(pipe);
2932 temp = I915_READ(reg);
2933 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 2934 TRANS_DP_SYNC_MASK |
2935 TRANS_DP_BPC_MASK);
5eddb70b
CW		 2936 temp |= (TRANS_DP_OUTPUT_ENABLE |
2937 TRANS_DP_ENH_FRAMING);
9325c9f0 2938 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 2939
2940 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 2941 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 2942 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 2943 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 2944
2945 switch (intel_trans_dp_port_sel(crtc)) {
2946 case PCH_DP_B:
5eddb70b 2947 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 2948 break;
2949 case PCH_DP_C:
5eddb70b 2950 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 2951 break;
2952 case PCH_DP_D:
5eddb70b 2953 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 2954 break;
2955 default:
2956 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
5eddb70b 2957 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf 2958 break;
32f9d658 2959 }
2c07245f 2960
5eddb70b 2961 I915_WRITE(reg, temp);
6be4a607 2962 }
b52eb4dc 2963
040484af 2964 intel_enable_transcoder(dev_priv, pipe);
f67a559d
JB		 2965}
2966
2967static void ironlake_crtc_enable(struct drm_crtc *crtc)
2968{
2969 struct drm_device *dev = crtc->dev;
2970 struct drm_i915_private *dev_priv = dev->dev_private;
2971 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2972 int pipe = intel_crtc->pipe;
2973 int plane = intel_crtc->plane;
2974 u32 temp;
2975 bool is_pch_port;
2976
2977 if (intel_crtc->active)
2978 return;
2979
2980 intel_crtc->active = true;
2981 intel_update_watermarks(dev);
2982
2983 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2984 temp = I915_READ(PCH_LVDS);
2985 if ((temp & LVDS_PORT_EN) == 0)
2986 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2987 }
2988
2989 is_pch_port = intel_crtc_driving_pch(crtc);
2990
2991 if (is_pch_port)
357555c0 2992 ironlake_fdi_pll_enable(crtc);
f67a559d
JB		 2993 else
2994 ironlake_fdi_disable(crtc);
2995
2996 /* Enable panel fitting for LVDS */
2997 if (dev_priv->pch_pf_size &&
2998 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2999 /* Force use of hard-coded filter coefficients
3000 * as some pre-programmed values are broken,
3001 * e.g. x201.
3002 */
9db4a9c7
JB		 3003 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3004 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3005 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3006 }
3007
9c54c0dd
JB		 3008 /*
3009 * On ILK+ LUT must be loaded before the pipe is running but with
3010 * clocks enabled
3011 */
3012 intel_crtc_load_lut(crtc);
3013
f67a559d
JB		 3014 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3015 intel_enable_plane(dev_priv, plane, pipe);
3016
3017 if (is_pch_port)
3018 ironlake_pch_enable(crtc);
c98e9dcf 3019
d1ebd816 3020 mutex_lock(&dev->struct_mutex);
bed4a673 3021 intel_update_fbc(dev);
d1ebd816
BW		 3022 mutex_unlock(&dev->struct_mutex);
3023
6b383a7f 3024 intel_crtc_update_cursor(crtc, true);
6be4a607
JB		 3025}
3026
3027static void ironlake_crtc_disable(struct drm_crtc *crtc)
3028{
3029 struct drm_device *dev = crtc->dev;
3030 struct drm_i915_private *dev_priv = dev->dev_private;
3031 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3032 int pipe = intel_crtc->pipe;
3033 int plane = intel_crtc->plane;
5eddb70b 3034 u32 reg, temp;
b52eb4dc 3035
f7abfe8b
CW		 3036 if (!intel_crtc->active)
3037 return;
3038
e6c3a2a6 3039 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3040 drm_vblank_off(dev, pipe);
6b383a7f 3041 intel_crtc_update_cursor(crtc, false);
5eddb70b 3042
b24e7179 3043 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3044
973d04f9
CW		 3045 if (dev_priv->cfb_plane == plane)
3046 intel_disable_fbc(dev);
2c07245f 3047
b24e7179 3048 intel_disable_pipe(dev_priv, pipe);
32f9d658 3049
6be4a607 3050 /* Disable PF */
9db4a9c7
JB		 3051 I915_WRITE(PF_CTL(pipe), 0);
3052 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3053
0fc932b8 3054 ironlake_fdi_disable(crtc);
2c07245f 3055
47a05eca
JB		 3056 /* This is a horrible layering violation; we should be doing this in
3057 * the connector/encoder ->prepare instead, but we don't always have
3058 * enough information there about the config to know whether it will
3059 * actually be necessary or just cause undesired flicker.
3060 */
3061 intel_disable_pch_ports(dev_priv, pipe);
249c0e64 3062
040484af 3063 intel_disable_transcoder(dev_priv, pipe);
913d8d11 3064
6be4a607
JB		 3065 if (HAS_PCH_CPT(dev)) {
3066 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3067 reg = TRANS_DP_CTL(pipe);
3068 temp = I915_READ(reg);
3069 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3070 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3071 I915_WRITE(reg, temp);
6be4a607
JB		 3072
3073 /* disable DPLL_SEL */
3074 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3075 switch (pipe) {
3076 case 0:
3077 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
3078 break;
3079 case 1:
6be4a607 3080 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3081 break;
3082 case 2:
3083 /* FIXME: manage transcoder PLLs? */
3084 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3085 break;
3086 default:
3087 BUG(); /* wtf */
3088 }
6be4a607 3089 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3090 }
e3421a18 3091
6be4a607 3092 /* disable PCH DPLL */
92f2584a 3093 intel_disable_pch_pll(dev_priv, pipe);
8db9d77b 3094
6be4a607 3095 /* Switch from PCDclk to Rawclk */
5eddb70b
CW		 3096 reg = FDI_RX_CTL(pipe);
3097 temp = I915_READ(reg);
3098 I915_WRITE(reg, temp & ~FDI_PCDCLK);
8db9d77b 3099
6be4a607 3100 /* Disable CPU FDI TX PLL */
5eddb70b
CW		 3101 reg = FDI_TX_CTL(pipe);
3102 temp = I915_READ(reg);
3103 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3104
3105 POSTING_READ(reg);
6be4a607 3106 udelay(100);
8db9d77b 3107
5eddb70b
CW		 3108 reg = FDI_RX_CTL(pipe);
3109 temp = I915_READ(reg);
3110 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2c07245f 3111
6be4a607 3112 /* Wait for the clocks to turn off. */
5eddb70b 3113 POSTING_READ(reg);
6be4a607 3114 udelay(100);
6b383a7f 3115
f7abfe8b 3116 intel_crtc->active = false;
6b383a7f 3117 intel_update_watermarks(dev);
d1ebd816
BW		 3118
3119 mutex_lock(&dev->struct_mutex);
6b383a7f
CW		 3120 intel_update_fbc(dev);
3121 intel_clear_scanline_wait(dev);
d1ebd816 3122 mutex_unlock(&dev->struct_mutex);
6be4a607 3123}
1b3c7a47 3124
6be4a607
JB		 3125static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3126{
3127 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3128 int pipe = intel_crtc->pipe;
3129 int plane = intel_crtc->plane;
8db9d77b 3130
6be4a607
JB		 3131 /* XXX: When our outputs are all unaware of DPMS modes other than off
3132 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3133 */
3134 switch (mode) {
3135 case DRM_MODE_DPMS_ON:
3136 case DRM_MODE_DPMS_STANDBY:
3137 case DRM_MODE_DPMS_SUSPEND:
3138 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3139 ironlake_crtc_enable(crtc);
3140 break;
1b3c7a47 3141
6be4a607
JB		 3142 case DRM_MODE_DPMS_OFF:
3143 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3144 ironlake_crtc_disable(crtc);
2c07245f
ZW		 3145 break;
3146 }
3147}
3148
02e792fb
DV		 3149static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3150{
02e792fb 3151 if (!enable && intel_crtc->overlay) {
23f09ce3 3152 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3153 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3154
23f09ce3 3155 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3156 dev_priv->mm.interruptible = false;
3157 (void) intel_overlay_switch_off(intel_crtc->overlay);
3158 dev_priv->mm.interruptible = true;
23f09ce3 3159 mutex_unlock(&dev->struct_mutex);
02e792fb 3160 }
02e792fb 3161
5dcdbcb0
CW		 3162 /* Let userspace switch the overlay on again. In most cases userspace
3163 * has to recompute where to put it anyway.
3164 */
02e792fb
DV		 3165}
3166
0b8765c6 3167static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3168{
3169 struct drm_device *dev = crtc->dev;
79e53945
JB		 3170 struct drm_i915_private *dev_priv = dev->dev_private;
3171 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3172 int pipe = intel_crtc->pipe;
80824003 3173 int plane = intel_crtc->plane;
79e53945 3174
f7abfe8b
CW		 3175 if (intel_crtc->active)
3176 return;
3177
3178 intel_crtc->active = true;
6b383a7f
CW		 3179 intel_update_watermarks(dev);
3180
63d7bbe9 3181 intel_enable_pll(dev_priv, pipe);
040484af 3182 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3183 intel_enable_plane(dev_priv, plane, pipe);
79e53945 3184
0b8765c6 3185 intel_crtc_load_lut(crtc);
bed4a673 3186 intel_update_fbc(dev);
79e53945 3187
0b8765c6
JB		 3188 /* Give the overlay scaler a chance to enable if it's on this pipe */
3189 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3190 intel_crtc_update_cursor(crtc, true);
0b8765c6 3191}
79e53945 3192
0b8765c6
JB		 3193static void i9xx_crtc_disable(struct drm_crtc *crtc)
3194{
3195 struct drm_device *dev = crtc->dev;
3196 struct drm_i915_private *dev_priv = dev->dev_private;
3197 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3198 int pipe = intel_crtc->pipe;
3199 int plane = intel_crtc->plane;
b690e96c 3200
f7abfe8b
CW		 3201 if (!intel_crtc->active)
3202 return;
3203
0b8765c6 3204 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3205 intel_crtc_wait_for_pending_flips(crtc);
3206 drm_vblank_off(dev, pipe);
0b8765c6 3207 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3208 intel_crtc_update_cursor(crtc, false);
0b8765c6 3209
973d04f9
CW		 3210 if (dev_priv->cfb_plane == plane)
3211 intel_disable_fbc(dev);
79e53945 3212
b24e7179 3213 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3214 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 3215 intel_disable_pll(dev_priv, pipe);
0b8765c6 3216
f7abfe8b 3217 intel_crtc->active = false;
6b383a7f
CW		 3218 intel_update_fbc(dev);
3219 intel_update_watermarks(dev);
3220 intel_clear_scanline_wait(dev);
0b8765c6
JB		 3221}
3222
3223static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3224{
3225 /* XXX: When our outputs are all unaware of DPMS modes other than off
3226 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3227 */
3228 switch (mode) {
3229 case DRM_MODE_DPMS_ON:
3230 case DRM_MODE_DPMS_STANDBY:
3231 case DRM_MODE_DPMS_SUSPEND:
3232 i9xx_crtc_enable(crtc);
3233 break;
3234 case DRM_MODE_DPMS_OFF:
3235 i9xx_crtc_disable(crtc);
79e53945
JB		 3236 break;
3237 }
2c07245f
ZW		 3238}
3239
3240/**
3241 * Sets the power management mode of the pipe and plane.
2c07245f
ZW		 3242 */
3243static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3244{
3245 struct drm_device *dev = crtc->dev;
e70236a8 3246 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f
ZW		 3247 struct drm_i915_master_private *master_priv;
3248 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3249 int pipe = intel_crtc->pipe;
3250 bool enabled;
3251
032d2a0d
CW		 3252 if (intel_crtc->dpms_mode == mode)
3253 return;
3254
65655d4a 3255 intel_crtc->dpms_mode = mode;
debcaddc 3256
e70236a8 3257 dev_priv->display.dpms(crtc, mode);
79e53945
JB		 3258
3259 if (!dev->primary->master)
3260 return;
3261
3262 master_priv = dev->primary->master->driver_priv;
3263 if (!master_priv->sarea_priv)
3264 return;
3265
3266 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3267
3268 switch (pipe) {
3269 case 0:
3270 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3271 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3272 break;
3273 case 1:
3274 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3275 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3276 break;
3277 default:
9db4a9c7 3278 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3279 break;
3280 }
79e53945
JB		 3281}
3282
cdd59983
CW		 3283static void intel_crtc_disable(struct drm_crtc *crtc)
3284{
3285 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3286 struct drm_device *dev = crtc->dev;
3287
3288 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3289
3290 if (crtc->fb) {
3291 mutex_lock(&dev->struct_mutex);
3292 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
3293 mutex_unlock(&dev->struct_mutex);
3294 }
3295}
3296
7e7d76c3
JB		 3297/* Prepare for a mode set.
3298 *
3299 * Note we could be a lot smarter here. We need to figure out which outputs
3300 * will be enabled, which disabled (in short, how the config will changes)
3301 * and perform the minimum necessary steps to accomplish that, e.g. updating
3302 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3303 * panel fitting is in the proper state, etc.
3304 */
3305static void i9xx_crtc_prepare(struct drm_crtc *crtc)
79e53945 3306{
7e7d76c3 3307 i9xx_crtc_disable(crtc);
79e53945
JB		 3308}
3309
7e7d76c3 3310static void i9xx_crtc_commit(struct drm_crtc *crtc)
79e53945 3311{
7e7d76c3 3312 i9xx_crtc_enable(crtc);
7e7d76c3
JB		 3313}
3314
3315static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3316{
7e7d76c3 3317 ironlake_crtc_disable(crtc);
7e7d76c3
JB		 3318}
3319
3320static void ironlake_crtc_commit(struct drm_crtc *crtc)
3321{
7e7d76c3 3322 ironlake_crtc_enable(crtc);
79e53945
JB		 3323}
3324
0206e353 3325void intel_encoder_prepare(struct drm_encoder *encoder)
79e53945
JB		 3326{
3327 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3328 /* lvds has its own version of prepare see intel_lvds_prepare */
3329 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3330}
3331
0206e353 3332void intel_encoder_commit(struct drm_encoder *encoder)
79e53945
JB		 3333{
3334 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3335 /* lvds has its own version of commit see intel_lvds_commit */
3336 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3337}
3338
ea5b213a
CW		 3339void intel_encoder_destroy(struct drm_encoder *encoder)
3340{
4ef69c7a 3341 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3342
ea5b213a
CW		 3343 drm_encoder_cleanup(encoder);
3344 kfree(intel_encoder);
3345}
3346
79e53945
JB		 3347static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3348 struct drm_display_mode *mode,
3349 struct drm_display_mode *adjusted_mode)
3350{
2c07245f 3351 struct drm_device *dev = crtc->dev;
89749350 3352
bad720ff 3353 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3354 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3355 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3356 return false;
2c07245f 3357 }
89749350
CW		 3358
3359 /* XXX some encoders set the crtcinfo, others don't.
3360 * Obviously we need some form of conflict resolution here...
3361 */
3362 if (adjusted_mode->crtc_htotal == 0)
3363 drm_mode_set_crtcinfo(adjusted_mode, 0);
3364
79e53945
JB		 3365 return true;
3366}
3367
e70236a8
JB		 3368static int i945_get_display_clock_speed(struct drm_device *dev)
3369{
3370 return 400000;
3371}
79e53945 3372
e70236a8 3373static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3374{
e70236a8
JB		 3375 return 333000;
3376}
79e53945 3377
e70236a8
JB		 3378static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3379{
3380 return 200000;
3381}
79e53945 3382
e70236a8
JB		 3383static int i915gm_get_display_clock_speed(struct drm_device *dev)
3384{
3385 u16 gcfgc = 0;
79e53945 3386
e70236a8
JB		 3387 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3388
3389 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3390 return 133000;
3391 else {
3392 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3393 case GC_DISPLAY_CLOCK_333_MHZ:
3394 return 333000;
3395 default:
3396 case GC_DISPLAY_CLOCK_190_200_MHZ:
3397 return 190000;
79e53945 3398 }
e70236a8
JB		 3399 }
3400}
3401
3402static int i865_get_display_clock_speed(struct drm_device *dev)
3403{
3404 return 266000;
3405}
3406
3407static int i855_get_display_clock_speed(struct drm_device *dev)
3408{
3409 u16 hpllcc = 0;
3410 /* Assume that the hardware is in the high speed state. This
3411 * should be the default.
3412 */
3413 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3414 case GC_CLOCK_133_200:
3415 case GC_CLOCK_100_200:
3416 return 200000;
3417 case GC_CLOCK_166_250:
3418 return 250000;
3419 case GC_CLOCK_100_133:
79e53945 3420 return 133000;
e70236a8 3421 }
79e53945 3422
e70236a8
JB		 3423 /* Shouldn't happen */
3424 return 0;
3425}
79e53945 3426
e70236a8
JB		 3427static int i830_get_display_clock_speed(struct drm_device *dev)
3428{
3429 return 133000;
79e53945
JB		 3430}
3431
2c07245f
ZW		 3432struct fdi_m_n {
3433 u32 tu;
3434 u32 gmch_m;
3435 u32 gmch_n;
3436 u32 link_m;
3437 u32 link_n;
3438};
3439
3440static void
3441fdi_reduce_ratio(u32 *num, u32 *den)
3442{
3443 while (*num > 0xffffff || *den > 0xffffff) {
3444 *num >>= 1;
3445 *den >>= 1;
3446 }
3447}
3448
2c07245f 3449static void
f2b115e6
AJ		 3450ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3451 int link_clock, struct fdi_m_n *m_n)
2c07245f 3452{
2c07245f
ZW		 3453 m_n->tu = 64; /* default size */
3454
22ed1113
CW		 3455 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3456 m_n->gmch_m = bits_per_pixel * pixel_clock;
3457 m_n->gmch_n = link_clock * nlanes * 8;
2c07245f
ZW		 3458 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3459
22ed1113
CW		 3460 m_n->link_m = pixel_clock;
3461 m_n->link_n = link_clock;
2c07245f
ZW		 3462 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3463}
3464
3465
7662c8bd
SL		 3466struct intel_watermark_params {
3467 unsigned long fifo_size;
3468 unsigned long max_wm;
3469 unsigned long default_wm;
3470 unsigned long guard_size;
3471 unsigned long cacheline_size;
3472};
3473
f2b115e6 3474/* Pineview has different values for various configs */
d210246a 3475static const struct intel_watermark_params pineview_display_wm = {
f2b115e6
AJ		 3476 PINEVIEW_DISPLAY_FIFO,
3477 PINEVIEW_MAX_WM,
3478 PINEVIEW_DFT_WM,
3479 PINEVIEW_GUARD_WM,
3480 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3481};
d210246a 3482static const struct intel_watermark_params pineview_display_hplloff_wm = {
f2b115e6
AJ		 3483 PINEVIEW_DISPLAY_FIFO,
3484 PINEVIEW_MAX_WM,
3485 PINEVIEW_DFT_HPLLOFF_WM,
3486 PINEVIEW_GUARD_WM,
3487 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3488};
d210246a 3489static const struct intel_watermark_params pineview_cursor_wm = {
f2b115e6
AJ		 3490 PINEVIEW_CURSOR_FIFO,
3491 PINEVIEW_CURSOR_MAX_WM,
3492 PINEVIEW_CURSOR_DFT_WM,
3493 PINEVIEW_CURSOR_GUARD_WM,
3494 PINEVIEW_FIFO_LINE_SIZE,
7662c8bd 3495};
d210246a 3496static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
f2b115e6
AJ		 3497 PINEVIEW_CURSOR_FIFO,
3498 PINEVIEW_CURSOR_MAX_WM,
3499 PINEVIEW_CURSOR_DFT_WM,
3500 PINEVIEW_CURSOR_GUARD_WM,
3501 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3502};
d210246a 3503static const struct intel_watermark_params g4x_wm_info = {
0e442c60
JB		 3504 G4X_FIFO_SIZE,
3505 G4X_MAX_WM,
3506 G4X_MAX_WM,
3507 2,
3508 G4X_FIFO_LINE_SIZE,
3509};
d210246a 3510static const struct intel_watermark_params g4x_cursor_wm_info = {
4fe5e611
ZY		 3511 I965_CURSOR_FIFO,
3512 I965_CURSOR_MAX_WM,
3513 I965_CURSOR_DFT_WM,
3514 2,
3515 G4X_FIFO_LINE_SIZE,
3516};
d210246a 3517static const struct intel_watermark_params i965_cursor_wm_info = {
4fe5e611
ZY		 3518 I965_CURSOR_FIFO,
3519 I965_CURSOR_MAX_WM,
3520 I965_CURSOR_DFT_WM,
3521 2,
3522 I915_FIFO_LINE_SIZE,
3523};
d210246a 3524static const struct intel_watermark_params i945_wm_info = {
dff33cfc 3525 I945_FIFO_SIZE,
7662c8bd
SL		 3526 I915_MAX_WM,
3527 1,
dff33cfc
JB		 3528 2,
3529 I915_FIFO_LINE_SIZE
7662c8bd 3530};
d210246a 3531static const struct intel_watermark_params i915_wm_info = {
dff33cfc 3532 I915_FIFO_SIZE,
7662c8bd
SL		 3533 I915_MAX_WM,
3534 1,
dff33cfc 3535 2,
7662c8bd
SL		 3536 I915_FIFO_LINE_SIZE
3537};
d210246a 3538static const struct intel_watermark_params i855_wm_info = {
7662c8bd
SL		 3539 I855GM_FIFO_SIZE,
3540 I915_MAX_WM,
3541 1,
dff33cfc 3542 2,
7662c8bd
SL		 3543 I830_FIFO_LINE_SIZE
3544};
d210246a 3545static const struct intel_watermark_params i830_wm_info = {
7662c8bd
SL		 3546 I830_FIFO_SIZE,
3547 I915_MAX_WM,
3548 1,
dff33cfc 3549 2,
7662c8bd
SL		 3550 I830_FIFO_LINE_SIZE
3551};
3552
d210246a 3553static const struct intel_watermark_params ironlake_display_wm_info = {
7f8a8569
ZW		 3554 ILK_DISPLAY_FIFO,
3555 ILK_DISPLAY_MAXWM,
3556 ILK_DISPLAY_DFTWM,
3557 2,
3558 ILK_FIFO_LINE_SIZE
3559};
d210246a 3560static const struct intel_watermark_params ironlake_cursor_wm_info = {
c936f44d
ZY		 3561 ILK_CURSOR_FIFO,
3562 ILK_CURSOR_MAXWM,
3563 ILK_CURSOR_DFTWM,
3564 2,
3565 ILK_FIFO_LINE_SIZE
3566};
d210246a 3567static const struct intel_watermark_params ironlake_display_srwm_info = {
7f8a8569
ZW		 3568 ILK_DISPLAY_SR_FIFO,
3569 ILK_DISPLAY_MAX_SRWM,
3570 ILK_DISPLAY_DFT_SRWM,
3571 2,
3572 ILK_FIFO_LINE_SIZE
3573};
d210246a 3574static const struct intel_watermark_params ironlake_cursor_srwm_info = {
7f8a8569
ZW		 3575 ILK_CURSOR_SR_FIFO,
3576 ILK_CURSOR_MAX_SRWM,
3577 ILK_CURSOR_DFT_SRWM,
3578 2,
3579 ILK_FIFO_LINE_SIZE
3580};
3581
d210246a 3582static const struct intel_watermark_params sandybridge_display_wm_info = {
1398261a
YL		 3583 SNB_DISPLAY_FIFO,
3584 SNB_DISPLAY_MAXWM,
3585 SNB_DISPLAY_DFTWM,
3586 2,
3587 SNB_FIFO_LINE_SIZE
3588};
d210246a 3589static const struct intel_watermark_params sandybridge_cursor_wm_info = {
1398261a
YL		 3590 SNB_CURSOR_FIFO,
3591 SNB_CURSOR_MAXWM,
3592 SNB_CURSOR_DFTWM,
3593 2,
3594 SNB_FIFO_LINE_SIZE
3595};
d210246a 3596static const struct intel_watermark_params sandybridge_display_srwm_info = {
1398261a
YL		 3597 SNB_DISPLAY_SR_FIFO,
3598 SNB_DISPLAY_MAX_SRWM,
3599 SNB_DISPLAY_DFT_SRWM,
3600 2,
3601 SNB_FIFO_LINE_SIZE
3602};
d210246a 3603static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
1398261a
YL		 3604 SNB_CURSOR_SR_FIFO,
3605 SNB_CURSOR_MAX_SRWM,
3606 SNB_CURSOR_DFT_SRWM,
3607 2,
3608 SNB_FIFO_LINE_SIZE
3609};
3610
3611
dff33cfc
JB		 3612/**
3613 * intel_calculate_wm - calculate watermark level
3614 * @clock_in_khz: pixel clock
3615 * @wm: chip FIFO params
3616 * @pixel_size: display pixel size
3617 * @latency_ns: memory latency for the platform
3618 *
3619 * Calculate the watermark level (the level at which the display plane will
3620 * start fetching from memory again). Each chip has a different display
3621 * FIFO size and allocation, so the caller needs to figure that out and pass
3622 * in the correct intel_watermark_params structure.
3623 *
3624 * As the pixel clock runs, the FIFO will be drained at a rate that depends
3625 * on the pixel size. When it reaches the watermark level, it'll start
3626 * fetching FIFO line sized based chunks from memory until the FIFO fills
3627 * past the watermark point. If the FIFO drains completely, a FIFO underrun
3628 * will occur, and a display engine hang could result.
3629 */
7662c8bd 3630static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
d210246a
CW		 3631 const struct intel_watermark_params *wm,
3632 int fifo_size,
7662c8bd
SL		 3633 int pixel_size,
3634 unsigned long latency_ns)
3635{
390c4dd4 3636 long entries_required, wm_size;
dff33cfc 3637
d660467c
JB		 3638 /*
3639 * Note: we need to make sure we don't overflow for various clock &
3640 * latency values.
3641 * clocks go from a few thousand to several hundred thousand.
3642 * latency is usually a few thousand
3643 */
3644 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3645 1000;
8de9b311 3646 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
7662c8bd 3647
bbb0aef5 3648 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
dff33cfc 3649
d210246a 3650 wm_size = fifo_size - (entries_required + wm->guard_size);
dff33cfc 3651
bbb0aef5 3652 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
7662c8bd 3653
390c4dd4
JB		 3654 /* Don't promote wm_size to unsigned... */
3655 if (wm_size > (long)wm->max_wm)
7662c8bd 3656 wm_size = wm->max_wm;
c3add4b6 3657 if (wm_size <= 0)
7662c8bd
SL		 3658 wm_size = wm->default_wm;
3659 return wm_size;
3660}
3661
3662struct cxsr_latency {
3663 int is_desktop;
95534263 3664 int is_ddr3;
7662c8bd
SL		 3665 unsigned long fsb_freq;
3666 unsigned long mem_freq;
3667 unsigned long display_sr;
3668 unsigned long display_hpll_disable;
3669 unsigned long cursor_sr;
3670 unsigned long cursor_hpll_disable;
3671};
3672
403c89ff 3673static const struct cxsr_latency cxsr_latency_table[] = {
95534263
LP		 3674 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
3675 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
3676 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
3677 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
3678 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
3679
3680 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
3681 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
3682 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
3683 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
3684 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
3685
3686 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
3687 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
3688 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
3689 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
3690 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
3691
3692 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
3693 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
3694 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
3695 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
3696 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
3697
3698 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
3699 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
3700 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
3701 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
3702 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
3703
3704 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
3705 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
3706 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
3707 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
3708 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
7662c8bd
SL		 3709};
3710
403c89ff
CW		 3711static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3712 int is_ddr3,
3713 int fsb,
3714 int mem)
7662c8bd 3715{
403c89ff 3716 const struct cxsr_latency *latency;
7662c8bd 3717 int i;
7662c8bd
SL		 3718
3719 if (fsb == 0 || mem == 0)
3720 return NULL;
3721
3722 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3723 latency = &cxsr_latency_table[i];
3724 if (is_desktop == latency->is_desktop &&
95534263 3725 is_ddr3 == latency->is_ddr3 &&
decbbcda
JSR		 3726 fsb == latency->fsb_freq && mem == latency->mem_freq)
3727 return latency;
7662c8bd 3728 }
decbbcda 3729
28c97730 3730 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
decbbcda
JSR		 3731
3732 return NULL;
7662c8bd
SL		 3733}
3734
f2b115e6 3735static void pineview_disable_cxsr(struct drm_device *dev)
7662c8bd
SL		 3736{
3737 struct drm_i915_private *dev_priv = dev->dev_private;
7662c8bd
SL		 3738
3739 /* deactivate cxsr */
3e33d94d 3740 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
7662c8bd
SL		 3741}
3742
bcc24fb4
JB		 3743/*
3744 * Latency for FIFO fetches is dependent on several factors:
3745 * - memory configuration (speed, channels)
3746 * - chipset
3747 * - current MCH state
3748 * It can be fairly high in some situations, so here we assume a fairly
3749 * pessimal value. It's a tradeoff between extra memory fetches (if we
3750 * set this value too high, the FIFO will fetch frequently to stay full)
3751 * and power consumption (set it too low to save power and we might see
3752 * FIFO underruns and display "flicker").
3753 *
3754 * A value of 5us seems to be a good balance; safe for very low end
3755 * platforms but not overly aggressive on lower latency configs.
3756 */
69e302a9 3757static const int latency_ns = 5000;
7662c8bd 3758
e70236a8 3759static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
dff33cfc
JB		 3760{
3761 struct drm_i915_private *dev_priv = dev->dev_private;
3762 uint32_t dsparb = I915_READ(DSPARB);
3763 int size;
3764
8de9b311
CW		 3765 size = dsparb & 0x7f;
3766 if (plane)
3767 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
dff33cfc 3768
28c97730 3769 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3770 plane ? "B" : "A", size);
dff33cfc
JB		 3771
3772 return size;
3773}
7662c8bd 3774
e70236a8
JB		 3775static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3776{
3777 struct drm_i915_private *dev_priv = dev->dev_private;
3778 uint32_t dsparb = I915_READ(DSPARB);
3779 int size;
3780
8de9b311
CW		 3781 size = dsparb & 0x1ff;
3782 if (plane)
3783 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
e70236a8 3784 size >>= 1; /* Convert to cachelines */
dff33cfc 3785
28c97730 3786 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3787 plane ? "B" : "A", size);
dff33cfc
JB		 3788
3789 return size;
3790}
7662c8bd 3791
e70236a8
JB		 3792static int i845_get_fifo_size(struct drm_device *dev, int plane)
3793{
3794 struct drm_i915_private *dev_priv = dev->dev_private;
3795 uint32_t dsparb = I915_READ(DSPARB);
3796 int size;
3797
3798 size = dsparb & 0x7f;
3799 size >>= 2; /* Convert to cachelines */
3800
28c97730 3801 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b
CW		 3802 plane ? "B" : "A",
3803 size);
e70236a8
JB		 3804
3805 return size;
3806}
3807
3808static int i830_get_fifo_size(struct drm_device *dev, int plane)
3809{
3810 struct drm_i915_private *dev_priv = dev->dev_private;
3811 uint32_t dsparb = I915_READ(DSPARB);
3812 int size;
3813
3814 size = dsparb & 0x7f;
3815 size >>= 1; /* Convert to cachelines */
3816
28c97730 3817 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3818 plane ? "B" : "A", size);
e70236a8
JB		 3819
3820 return size;
3821}
3822
d210246a
CW		 3823static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3824{
3825 struct drm_crtc *crtc, *enabled = NULL;
3826
3827 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3828 if (crtc->enabled && crtc->fb) {
3829 if (enabled)
3830 return NULL;
3831 enabled = crtc;
3832 }
3833 }
3834
3835 return enabled;
3836}
3837
3838static void pineview_update_wm(struct drm_device *dev)
d4294342
ZY		 3839{
3840 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a 3841 struct drm_crtc *crtc;
403c89ff 3842 const struct cxsr_latency *latency;
d4294342
ZY		 3843 u32 reg;
3844 unsigned long wm;
d4294342 3845
403c89ff 3846 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
95534263 3847 dev_priv->fsb_freq, dev_priv->mem_freq);
d4294342
ZY		 3848 if (!latency) {
3849 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3850 pineview_disable_cxsr(dev);
3851 return;
3852 }
3853
d210246a
CW		 3854 crtc = single_enabled_crtc(dev);
3855 if (crtc) {
3856 int clock = crtc->mode.clock;
3857 int pixel_size = crtc->fb->bits_per_pixel / 8;
d4294342
ZY		 3858
3859 /* Display SR */
d210246a
CW		 3860 wm = intel_calculate_wm(clock, &pineview_display_wm,
3861 pineview_display_wm.fifo_size,
d4294342
ZY		 3862 pixel_size, latency->display_sr);
3863 reg = I915_READ(DSPFW1);
3864 reg &= ~DSPFW_SR_MASK;
3865 reg |= wm << DSPFW_SR_SHIFT;
3866 I915_WRITE(DSPFW1, reg);
3867 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3868
3869 /* cursor SR */
d210246a
CW		 3870 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3871 pineview_display_wm.fifo_size,
d4294342
ZY		 3872 pixel_size, latency->cursor_sr);
3873 reg = I915_READ(DSPFW3);
3874 reg &= ~DSPFW_CURSOR_SR_MASK;
3875 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3876 I915_WRITE(DSPFW3, reg);
3877
3878 /* Display HPLL off SR */
d210246a
CW		 3879 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3880 pineview_display_hplloff_wm.fifo_size,
d4294342
ZY		 3881 pixel_size, latency->display_hpll_disable);
3882 reg = I915_READ(DSPFW3);
3883 reg &= ~DSPFW_HPLL_SR_MASK;
3884 reg |= wm & DSPFW_HPLL_SR_MASK;
3885 I915_WRITE(DSPFW3, reg);
3886
3887 /* cursor HPLL off SR */
d210246a
CW		 3888 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3889 pineview_display_hplloff_wm.fifo_size,
d4294342
ZY		 3890 pixel_size, latency->cursor_hpll_disable);
3891 reg = I915_READ(DSPFW3);
3892 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3893 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3894 I915_WRITE(DSPFW3, reg);
3895 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3896
3897 /* activate cxsr */
3e33d94d
CW		 3898 I915_WRITE(DSPFW3,
3899 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
d4294342
ZY		 3900 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3901 } else {
3902 pineview_disable_cxsr(dev);
3903 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3904 }
3905}
3906
417ae147
CW		 3907static bool g4x_compute_wm0(struct drm_device *dev,
3908 int plane,
3909 const struct intel_watermark_params *display,
3910 int display_latency_ns,
3911 const struct intel_watermark_params *cursor,
3912 int cursor_latency_ns,
3913 int *plane_wm,
3914 int *cursor_wm)
3915{
3916 struct drm_crtc *crtc;
3917 int htotal, hdisplay, clock, pixel_size;
3918 int line_time_us, line_count;
3919 int entries, tlb_miss;
3920
3921 crtc = intel_get_crtc_for_plane(dev, plane);
5c72d064
CW		 3922 if (crtc->fb == NULL || !crtc->enabled) {
3923 *cursor_wm = cursor->guard_size;
3924 *plane_wm = display->guard_size;
417ae147 3925 return false;
5c72d064 3926 }
417ae147
CW		 3927
3928 htotal = crtc->mode.htotal;
3929 hdisplay = crtc->mode.hdisplay;
3930 clock = crtc->mode.clock;
3931 pixel_size = crtc->fb->bits_per_pixel / 8;
3932
3933 /* Use the small buffer method to calculate plane watermark */
3934 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3935 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3936 if (tlb_miss > 0)
3937 entries += tlb_miss;
3938 entries = DIV_ROUND_UP(entries, display->cacheline_size);
3939 *plane_wm = entries + display->guard_size;
3940 if (*plane_wm > (int)display->max_wm)
3941 *plane_wm = display->max_wm;
3942
3943 /* Use the large buffer method to calculate cursor watermark */
3944 line_time_us = ((htotal * 1000) / clock);
3945 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3946 entries = line_count * 64 * pixel_size;
3947 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
3948 if (tlb_miss > 0)
3949 entries += tlb_miss;
3950 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3951 *cursor_wm = entries + cursor->guard_size;
3952 if (*cursor_wm > (int)cursor->max_wm)
3953 *cursor_wm = (int)cursor->max_wm;
3954
3955 return true;
3956}
3957
3958/*
3959 * Check the wm result.
3960 *
3961 * If any calculated watermark values is larger than the maximum value that
3962 * can be programmed into the associated watermark register, that watermark
3963 * must be disabled.
3964 */
3965static bool g4x_check_srwm(struct drm_device *dev,
3966 int display_wm, int cursor_wm,
3967 const struct intel_watermark_params *display,
3968 const struct intel_watermark_params *cursor)
652c393a 3969{
417ae147
CW		 3970 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
3971 display_wm, cursor_wm);
652c393a 3972
417ae147 3973 if (display_wm > display->max_wm) {
bbb0aef5 3974 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
417ae147
CW		 3975 display_wm, display->max_wm);
3976 return false;
3977 }
0e442c60 3978
417ae147 3979 if (cursor_wm > cursor->max_wm) {
bbb0aef5 3980 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
417ae147
CW		 3981 cursor_wm, cursor->max_wm);
3982 return false;
3983 }
0e442c60 3984
417ae147
CW		 3985 if (!(display_wm || cursor_wm)) {
3986 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
3987 return false;
3988 }
0e442c60 3989
417ae147
CW		 3990 return true;
3991}
0e442c60 3992
417ae147 3993static bool g4x_compute_srwm(struct drm_device *dev,
d210246a
CW		 3994 int plane,
3995 int latency_ns,
417ae147
CW		 3996 const struct intel_watermark_params *display,
3997 const struct intel_watermark_params *cursor,
3998 int *display_wm, int *cursor_wm)
3999{
d210246a
CW		 4000 struct drm_crtc *crtc;
4001 int hdisplay, htotal, pixel_size, clock;
417ae147
CW		 4002 unsigned long line_time_us;
4003 int line_count, line_size;
4004 int small, large;
4005 int entries;
0e442c60 4006
417ae147
CW		 4007 if (!latency_ns) {
4008 *display_wm = *cursor_wm = 0;
4009 return false;
4010 }
0e442c60 4011
d210246a
CW		 4012 crtc = intel_get_crtc_for_plane(dev, plane);
4013 hdisplay = crtc->mode.hdisplay;
4014 htotal = crtc->mode.htotal;
4015 clock = crtc->mode.clock;
4016 pixel_size = crtc->fb->bits_per_pixel / 8;
4017
417ae147
CW		 4018 line_time_us = (htotal * 1000) / clock;
4019 line_count = (latency_ns / line_time_us + 1000) / 1000;
4020 line_size = hdisplay * pixel_size;
0e442c60 4021
417ae147
CW		 4022 /* Use the minimum of the small and large buffer method for primary */
4023 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4024 large = line_count * line_size;
0e442c60 4025
417ae147
CW		 4026 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4027 *display_wm = entries + display->guard_size;
4fe5e611 4028
417ae147
CW		 4029 /* calculate the self-refresh watermark for display cursor */
4030 entries = line_count * pixel_size * 64;
4031 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4032 *cursor_wm = entries + cursor->guard_size;
4fe5e611 4033
417ae147
CW		 4034 return g4x_check_srwm(dev,
4035 *display_wm, *cursor_wm,
4036 display, cursor);
4037}
4fe5e611 4038
7ccb4a53 4039#define single_plane_enabled(mask) is_power_of_2(mask)
d210246a
CW		 4040
4041static void g4x_update_wm(struct drm_device *dev)
417ae147
CW		 4042{
4043 static const int sr_latency_ns = 12000;
4044 struct drm_i915_private *dev_priv = dev->dev_private;
4045 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
d210246a
CW		 4046 int plane_sr, cursor_sr;
4047 unsigned int enabled = 0;
417ae147
CW		 4048
4049 if (g4x_compute_wm0(dev, 0,
4050 &g4x_wm_info, latency_ns,
4051 &g4x_cursor_wm_info, latency_ns,
4052 &planea_wm, &cursora_wm))
d210246a 4053 enabled |= 1;
417ae147
CW		 4054
4055 if (g4x_compute_wm0(dev, 1,
4056 &g4x_wm_info, latency_ns,
4057 &g4x_cursor_wm_info, latency_ns,
4058 &planeb_wm, &cursorb_wm))
d210246a 4059 enabled |= 2;
417ae147
CW		 4060
4061 plane_sr = cursor_sr = 0;
d210246a
CW		 4062 if (single_plane_enabled(enabled) &&
4063 g4x_compute_srwm(dev, ffs(enabled) - 1,
4064 sr_latency_ns,
417ae147
CW		 4065 &g4x_wm_info,
4066 &g4x_cursor_wm_info,
4067 &plane_sr, &cursor_sr))
0e442c60 4068 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
417ae147
CW		 4069 else
4070 I915_WRITE(FW_BLC_SELF,
4071 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
0e442c60 4072
308977ac
CW		 4073 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
4074 planea_wm, cursora_wm,
4075 planeb_wm, cursorb_wm,
4076 plane_sr, cursor_sr);
0e442c60 4077
417ae147
CW		 4078 I915_WRITE(DSPFW1,
4079 (plane_sr << DSPFW_SR_SHIFT) |
0e442c60 4080 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
417ae147
CW		 4081 (planeb_wm << DSPFW_PLANEB_SHIFT) |
4082 planea_wm);
4083 I915_WRITE(DSPFW2,
4084 (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
0e442c60
JB		 4085 (cursora_wm << DSPFW_CURSORA_SHIFT));
4086 /* HPLL off in SR has some issues on G4x... disable it */
417ae147
CW		 4087 I915_WRITE(DSPFW3,
4088 (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
0e442c60 4089 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
652c393a
JB		 4090}
4091
d210246a 4092static void i965_update_wm(struct drm_device *dev)
7662c8bd
SL		 4093{
4094 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 4095 struct drm_crtc *crtc;
4096 int srwm = 1;
4fe5e611 4097 int cursor_sr = 16;
1dc7546d
JB		 4098
4099 /* Calc sr entries for one plane configs */
d210246a
CW		 4100 crtc = single_enabled_crtc(dev);
4101 if (crtc) {
1dc7546d 4102 /* self-refresh has much higher latency */
69e302a9 4103 static const int sr_latency_ns = 12000;
d210246a
CW		 4104 int clock = crtc->mode.clock;
4105 int htotal = crtc->mode.htotal;
4106 int hdisplay = crtc->mode.hdisplay;
4107 int pixel_size = crtc->fb->bits_per_pixel / 8;
4108 unsigned long line_time_us;
4109 int entries;
1dc7546d 4110
d210246a 4111 line_time_us = ((htotal * 1000) / clock);
1dc7546d
JB		 4112
4113 /* Use ns/us then divide to preserve precision */
d210246a
CW		 4114 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4115 pixel_size * hdisplay;
4116 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
d210246a 4117 srwm = I965_FIFO_SIZE - entries;
1dc7546d
JB		 4118 if (srwm < 0)
4119 srwm = 1;
1b07e04e 4120 srwm &= 0x1ff;
308977ac
CW		 4121 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
4122 entries, srwm);
4fe5e611 4123
d210246a 4124 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
5eddb70b 4125 pixel_size * 64;
d210246a 4126 entries = DIV_ROUND_UP(entries,
8de9b311 4127 i965_cursor_wm_info.cacheline_size);
4fe5e611 4128 cursor_sr = i965_cursor_wm_info.fifo_size -
d210246a 4129 (entries + i965_cursor_wm_info.guard_size);
4fe5e611
ZY		 4130
4131 if (cursor_sr > i965_cursor_wm_info.max_wm)
4132 cursor_sr = i965_cursor_wm_info.max_wm;
4133
4134 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
4135 "cursor %d\n", srwm, cursor_sr);
4136
a6c45cf0 4137 if (IS_CRESTLINE(dev))
adcdbc66 4138 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
33c5fd12
DJ		 4139 } else {
4140 /* Turn off self refresh if both pipes are enabled */
a6c45cf0 4141 if (IS_CRESTLINE(dev))
adcdbc66
JB		 4142 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
4143 & ~FW_BLC_SELF_EN);
1dc7546d 4144 }
7662c8bd 4145
1dc7546d
JB		 4146 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
4147 srwm);
7662c8bd
SL		 4148
4149 /* 965 has limitations... */
417ae147
CW		 4150 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
4151 (8 << 16) | (8 << 8) | (8 << 0));
7662c8bd 4152 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4fe5e611
ZY		 4153 /* update cursor SR watermark */
4154 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
7662c8bd
SL		 4155}
4156
d210246a 4157static void i9xx_update_wm(struct drm_device *dev)
7662c8bd
SL		 4158{
4159 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a 4160 const struct intel_watermark_params *wm_info;
dff33cfc
JB		 4161 uint32_t fwater_lo;
4162 uint32_t fwater_hi;
d210246a
CW		 4163 int cwm, srwm = 1;
4164 int fifo_size;
dff33cfc 4165 int planea_wm, planeb_wm;
d210246a 4166 struct drm_crtc *crtc, *enabled = NULL;
7662c8bd 4167
72557b4f 4168 if (IS_I945GM(dev))
d210246a 4169 wm_info = &i945_wm_info;
a6c45cf0 4170 else if (!IS_GEN2(dev))
d210246a 4171 wm_info = &i915_wm_info;
7662c8bd 4172 else
d210246a
CW		 4173 wm_info = &i855_wm_info;
4174
4175 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
4176 crtc = intel_get_crtc_for_plane(dev, 0);
4177 if (crtc->enabled && crtc->fb) {
4178 planea_wm = intel_calculate_wm(crtc->mode.clock,
4179 wm_info, fifo_size,
4180 crtc->fb->bits_per_pixel / 8,
4181 latency_ns);
4182 enabled = crtc;
4183 } else
4184 planea_wm = fifo_size - wm_info->guard_size;
4185
4186 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
4187 crtc = intel_get_crtc_for_plane(dev, 1);
4188 if (crtc->enabled && crtc->fb) {
4189 planeb_wm = intel_calculate_wm(crtc->mode.clock,
4190 wm_info, fifo_size,
4191 crtc->fb->bits_per_pixel / 8,
4192 latency_ns);
4193 if (enabled == NULL)
4194 enabled = crtc;
4195 else
4196 enabled = NULL;
4197 } else
4198 planeb_wm = fifo_size - wm_info->guard_size;
7662c8bd 4199
28c97730 4200 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
7662c8bd
SL		 4201
4202 /*
4203 * Overlay gets an aggressive default since video jitter is bad.
4204 */
4205 cwm = 2;
4206
18b2190c
AL		 4207 /* Play safe and disable self-refresh before adjusting watermarks. */
4208 if (IS_I945G(dev) || IS_I945GM(dev))
4209 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
4210 else if (IS_I915GM(dev))
4211 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
4212
dff33cfc 4213 /* Calc sr entries for one plane configs */
d210246a 4214 if (HAS_FW_BLC(dev) && enabled) {
dff33cfc 4215 /* self-refresh has much higher latency */
69e302a9 4216 static const int sr_latency_ns = 6000;
d210246a
CW		 4217 int clock = enabled->mode.clock;
4218 int htotal = enabled->mode.htotal;
4219 int hdisplay = enabled->mode.hdisplay;
4220 int pixel_size = enabled->fb->bits_per_pixel / 8;
4221 unsigned long line_time_us;
4222 int entries;
dff33cfc 4223
d210246a 4224 line_time_us = (htotal * 1000) / clock;
dff33cfc
JB		 4225
4226 /* Use ns/us then divide to preserve precision */
d210246a
CW		 4227 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4228 pixel_size * hdisplay;
4229 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
4230 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4231 srwm = wm_info->fifo_size - entries;
dff33cfc
JB		 4232 if (srwm < 0)
4233 srwm = 1;
ee980b80
LP		 4234
4235 if (IS_I945G(dev) || IS_I945GM(dev))
18b2190c
AL		 4236 I915_WRITE(FW_BLC_SELF,
4237 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4238 else if (IS_I915GM(dev))
ee980b80 4239 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
7662c8bd
SL		 4240 }
4241
28c97730 4242 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
5eddb70b 4243 planea_wm, planeb_wm, cwm, srwm);
7662c8bd 4244
dff33cfc
JB		 4245 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4246 fwater_hi = (cwm & 0x1f);
4247
4248 /* Set request length to 8 cachelines per fetch */
4249 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4250 fwater_hi = fwater_hi | (1 << 8);
7662c8bd
SL		 4251
4252 I915_WRITE(FW_BLC, fwater_lo);
4253 I915_WRITE(FW_BLC2, fwater_hi);
18b2190c 4254
d210246a
CW		 4255 if (HAS_FW_BLC(dev)) {
4256 if (enabled) {
4257 if (IS_I945G(dev) || IS_I945GM(dev))
4258 I915_WRITE(FW_BLC_SELF,
4259 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4260 else if (IS_I915GM(dev))
4261 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4262 DRM_DEBUG_KMS("memory self refresh enabled\n");
4263 } else
4264 DRM_DEBUG_KMS("memory self refresh disabled\n");
4265 }
7662c8bd
SL		 4266}
4267
d210246a 4268static void i830_update_wm(struct drm_device *dev)
7662c8bd
SL		 4269{
4270 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 4271 struct drm_crtc *crtc;
4272 uint32_t fwater_lo;
dff33cfc 4273 int planea_wm;
7662c8bd 4274
d210246a
CW		 4275 crtc = single_enabled_crtc(dev);
4276 if (crtc == NULL)
4277 return;
7662c8bd 4278
d210246a
CW		 4279 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4280 dev_priv->display.get_fifo_size(dev, 0),
4281 crtc->fb->bits_per_pixel / 8,
4282 latency_ns);
4283 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
f3601326
JB		 4284 fwater_lo |= (3<<8) | planea_wm;
4285
28c97730 4286 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
7662c8bd
SL		 4287
4288 I915_WRITE(FW_BLC, fwater_lo);
4289}
4290
7f8a8569 4291#define ILK_LP0_PLANE_LATENCY 700
c936f44d 4292#define ILK_LP0_CURSOR_LATENCY 1300
7f8a8569 4293
1398261a
YL		 4294/*
4295 * Check the wm result.
4296 *
4297 * If any calculated watermark values is larger than the maximum value that
4298 * can be programmed into the associated watermark register, that watermark
4299 * must be disabled.
1398261a 4300 */
b79d4990
JB		 4301static bool ironlake_check_srwm(struct drm_device *dev, int level,
4302 int fbc_wm, int display_wm, int cursor_wm,
4303 const struct intel_watermark_params *display,
4304 const struct intel_watermark_params *cursor)
1398261a
YL		 4305{
4306 struct drm_i915_private *dev_priv = dev->dev_private;
4307
4308 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4309 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4310
4311 if (fbc_wm > SNB_FBC_MAX_SRWM) {
4312 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 4313 fbc_wm, SNB_FBC_MAX_SRWM, level);
1398261a
YL		 4314
4315 /* fbc has it's own way to disable FBC WM */
4316 I915_WRITE(DISP_ARB_CTL,
4317 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4318 return false;
4319 }
4320
b79d4990 4321 if (display_wm > display->max_wm) {
1398261a 4322 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 4323 display_wm, SNB_DISPLAY_MAX_SRWM, level);
1398261a
YL		 4324 return false;
4325 }
4326
b79d4990 4327 if (cursor_wm > cursor->max_wm) {
1398261a 4328 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 4329 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1398261a
YL		 4330 return false;
4331 }
4332
4333 if (!(fbc_wm || display_wm || cursor_wm)) {
4334 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4335 return false;
4336 }
4337
4338 return true;
4339}
4340
4341/*
4342 * Compute watermark values of WM[1-3],
4343 */
d210246a
CW		 4344static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4345 int latency_ns,
b79d4990
JB		 4346 const struct intel_watermark_params *display,
4347 const struct intel_watermark_params *cursor,
4348 int *fbc_wm, int *display_wm, int *cursor_wm)
1398261a 4349{
d210246a 4350 struct drm_crtc *crtc;
1398261a 4351 unsigned long line_time_us;
d210246a 4352 int hdisplay, htotal, pixel_size, clock;
b79d4990 4353 int line_count, line_size;
1398261a
YL		 4354 int small, large;
4355 int entries;
1398261a
YL		 4356
4357 if (!latency_ns) {
4358 *fbc_wm = *display_wm = *cursor_wm = 0;
4359 return false;
4360 }
4361
d210246a
CW		 4362 crtc = intel_get_crtc_for_plane(dev, plane);
4363 hdisplay = crtc->mode.hdisplay;
4364 htotal = crtc->mode.htotal;
4365 clock = crtc->mode.clock;
4366 pixel_size = crtc->fb->bits_per_pixel / 8;
4367
1398261a
YL		 4368 line_time_us = (htotal * 1000) / clock;
4369 line_count = (latency_ns / line_time_us + 1000) / 1000;
4370 line_size = hdisplay * pixel_size;
4371
4372 /* Use the minimum of the small and large buffer method for primary */
4373 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4374 large = line_count * line_size;
4375
b79d4990
JB		 4376 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4377 *display_wm = entries + display->guard_size;
1398261a
YL		 4378
4379 /*
b79d4990 4380 * Spec says:
1398261a
YL		 4381 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4382 */
4383 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4384
4385 /* calculate the self-refresh watermark for display cursor */
4386 entries = line_count * pixel_size * 64;
b79d4990
JB		 4387 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4388 *cursor_wm = entries + cursor->guard_size;
1398261a 4389
b79d4990
JB		 4390 return ironlake_check_srwm(dev, level,
4391 *fbc_wm, *display_wm, *cursor_wm,
4392 display, cursor);
4393}
4394
d210246a 4395static void ironlake_update_wm(struct drm_device *dev)
b79d4990
JB		 4396{
4397 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 4398 int fbc_wm, plane_wm, cursor_wm;
4399 unsigned int enabled;
b79d4990
JB		 4400
4401 enabled = 0;
9f405100
CW		 4402 if (g4x_compute_wm0(dev, 0,
4403 &ironlake_display_wm_info,
4404 ILK_LP0_PLANE_LATENCY,
4405 &ironlake_cursor_wm_info,
4406 ILK_LP0_CURSOR_LATENCY,
4407 &plane_wm, &cursor_wm)) {
b79d4990
JB		 4408 I915_WRITE(WM0_PIPEA_ILK,
4409 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4410 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4411 " plane %d, " "cursor: %d\n",
4412 plane_wm, cursor_wm);
d210246a 4413 enabled |= 1;
b79d4990
JB		 4414 }
4415
9f405100
CW		 4416 if (g4x_compute_wm0(dev, 1,
4417 &ironlake_display_wm_info,
4418 ILK_LP0_PLANE_LATENCY,
4419 &ironlake_cursor_wm_info,
4420 ILK_LP0_CURSOR_LATENCY,
4421 &plane_wm, &cursor_wm)) {
b79d4990
JB		 4422 I915_WRITE(WM0_PIPEB_ILK,
4423 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4424 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4425 " plane %d, cursor: %d\n",
4426 plane_wm, cursor_wm);
d210246a 4427 enabled |= 2;
b79d4990
JB		 4428 }
4429
4430 /*
4431 * Calculate and update the self-refresh watermark only when one
4432 * display plane is used.
4433 */
4434 I915_WRITE(WM3_LP_ILK, 0);
4435 I915_WRITE(WM2_LP_ILK, 0);
4436 I915_WRITE(WM1_LP_ILK, 0);
4437
d210246a 4438 if (!single_plane_enabled(enabled))
b79d4990 4439 return;
d210246a 4440 enabled = ffs(enabled) - 1;
b79d4990
JB		 4441
4442 /* WM1 */
d210246a
CW		 4443 if (!ironlake_compute_srwm(dev, 1, enabled,
4444 ILK_READ_WM1_LATENCY() * 500,
b79d4990
JB		 4445 &ironlake_display_srwm_info,
4446 &ironlake_cursor_srwm_info,
4447 &fbc_wm, &plane_wm, &cursor_wm))
4448 return;
4449
4450 I915_WRITE(WM1_LP_ILK,
4451 WM1_LP_SR_EN |
4452 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4453 (fbc_wm << WM1_LP_FBC_SHIFT) |
4454 (plane_wm << WM1_LP_SR_SHIFT) |
4455 cursor_wm);
4456
4457 /* WM2 */
d210246a
CW		 4458 if (!ironlake_compute_srwm(dev, 2, enabled,
4459 ILK_READ_WM2_LATENCY() * 500,
b79d4990
JB		 4460 &ironlake_display_srwm_info,
4461 &ironlake_cursor_srwm_info,
4462 &fbc_wm, &plane_wm, &cursor_wm))
4463 return;
4464
4465 I915_WRITE(WM2_LP_ILK,
4466 WM2_LP_EN |
4467 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4468 (fbc_wm << WM1_LP_FBC_SHIFT) |
4469 (plane_wm << WM1_LP_SR_SHIFT) |
4470 cursor_wm);
4471
4472 /*
4473 * WM3 is unsupported on ILK, probably because we don't have latency
4474 * data for that power state
4475 */
1398261a
YL		 4476}
4477
d210246a 4478static void sandybridge_update_wm(struct drm_device *dev)
1398261a
YL		 4479{
4480 struct drm_i915_private *dev_priv = dev->dev_private;
a0fa62d3 4481 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
d210246a
CW		 4482 int fbc_wm, plane_wm, cursor_wm;
4483 unsigned int enabled;
1398261a
YL		 4484
4485 enabled = 0;
9f405100
CW		 4486 if (g4x_compute_wm0(dev, 0,
4487 &sandybridge_display_wm_info, latency,
4488 &sandybridge_cursor_wm_info, latency,
4489 &plane_wm, &cursor_wm)) {
1398261a
YL		 4490 I915_WRITE(WM0_PIPEA_ILK,
4491 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4492 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4493 " plane %d, " "cursor: %d\n",
4494 plane_wm, cursor_wm);
d210246a 4495 enabled |= 1;
1398261a
YL		 4496 }
4497
9f405100
CW		 4498 if (g4x_compute_wm0(dev, 1,
4499 &sandybridge_display_wm_info, latency,
4500 &sandybridge_cursor_wm_info, latency,
4501 &plane_wm, &cursor_wm)) {
1398261a
YL		 4502 I915_WRITE(WM0_PIPEB_ILK,
4503 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4504 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4505 " plane %d, cursor: %d\n",
4506 plane_wm, cursor_wm);
d210246a 4507 enabled |= 2;
1398261a
YL		 4508 }
4509
4510 /*
4511 * Calculate and update the self-refresh watermark only when one
4512 * display plane is used.
4513 *
4514 * SNB support 3 levels of watermark.
4515 *
4516 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4517 * and disabled in the descending order
4518 *
4519 */
4520 I915_WRITE(WM3_LP_ILK, 0);
4521 I915_WRITE(WM2_LP_ILK, 0);
4522 I915_WRITE(WM1_LP_ILK, 0);
4523
d210246a 4524 if (!single_plane_enabled(enabled))
1398261a 4525 return;
d210246a 4526 enabled = ffs(enabled) - 1;
1398261a
YL		 4527
4528 /* WM1 */
d210246a
CW		 4529 if (!ironlake_compute_srwm(dev, 1, enabled,
4530 SNB_READ_WM1_LATENCY() * 500,
b79d4990
JB		 4531 &sandybridge_display_srwm_info,
4532 &sandybridge_cursor_srwm_info,
4533 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4534 return;
4535
4536 I915_WRITE(WM1_LP_ILK,
4537 WM1_LP_SR_EN |
4538 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4539 (fbc_wm << WM1_LP_FBC_SHIFT) |
4540 (plane_wm << WM1_LP_SR_SHIFT) |
4541 cursor_wm);
4542
4543 /* WM2 */
d210246a
CW		 4544 if (!ironlake_compute_srwm(dev, 2, enabled,
4545 SNB_READ_WM2_LATENCY() * 500,
b79d4990
JB		 4546 &sandybridge_display_srwm_info,
4547 &sandybridge_cursor_srwm_info,
4548 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4549 return;
4550
4551 I915_WRITE(WM2_LP_ILK,
4552 WM2_LP_EN |
4553 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4554 (fbc_wm << WM1_LP_FBC_SHIFT) |
4555 (plane_wm << WM1_LP_SR_SHIFT) |
4556 cursor_wm);
4557
4558 /* WM3 */
d210246a
CW		 4559 if (!ironlake_compute_srwm(dev, 3, enabled,
4560 SNB_READ_WM3_LATENCY() * 500,
b79d4990
JB		 4561 &sandybridge_display_srwm_info,
4562 &sandybridge_cursor_srwm_info,
4563 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4564 return;
4565
4566 I915_WRITE(WM3_LP_ILK,
4567 WM3_LP_EN |
4568 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4569 (fbc_wm << WM1_LP_FBC_SHIFT) |
4570 (plane_wm << WM1_LP_SR_SHIFT) |
4571 cursor_wm);
4572}
4573
7662c8bd
SL		 4574/**
4575 * intel_update_watermarks - update FIFO watermark values based on current modes
4576 *
4577 * Calculate watermark values for the various WM regs based on current mode
4578 * and plane configuration.
4579 *
4580 * There are several cases to deal with here:
4581 * - normal (i.e. non-self-refresh)
4582 * - self-refresh (SR) mode
4583 * - lines are large relative to FIFO size (buffer can hold up to 2)
4584 * - lines are small relative to FIFO size (buffer can hold more than 2
4585 * lines), so need to account for TLB latency
4586 *
4587 * The normal calculation is:
4588 * watermark = dotclock * bytes per pixel * latency
4589 * where latency is platform & configuration dependent (we assume pessimal
4590 * values here).
4591 *
4592 * The SR calculation is:
4593 * watermark = (trunc(latency/line time)+1) * surface width *
4594 * bytes per pixel
4595 * where
4596 * line time = htotal / dotclock
fa143215 4597 * surface width = hdisplay for normal plane and 64 for cursor
7662c8bd
SL		 4598 * and latency is assumed to be high, as above.
4599 *
4600 * The final value programmed to the register should always be rounded up,
4601 * and include an extra 2 entries to account for clock crossings.
4602 *
4603 * We don't use the sprite, so we can ignore that. And on Crestline we have
4604 * to set the non-SR watermarks to 8.
5eddb70b 4605 */
7662c8bd
SL		 4606static void intel_update_watermarks(struct drm_device *dev)
4607{
e70236a8 4608 struct drm_i915_private *dev_priv = dev->dev_private;
7662c8bd 4609
d210246a
CW		 4610 if (dev_priv->display.update_wm)
4611 dev_priv->display.update_wm(dev);
7662c8bd
SL		 4612}
4613
a7615030
CW		 4614static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4615{
72bbe58c
KP		 4616 if (i915_panel_use_ssc >= 0)
4617 return i915_panel_use_ssc != 0;
4618 return dev_priv->lvds_use_ssc
435793df 4619 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4620}
4621
5a354204
JB		 4622/**
4623 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4624 * @crtc: CRTC structure
4625 *
4626 * A pipe may be connected to one or more outputs. Based on the depth of the
4627 * attached framebuffer, choose a good color depth to use on the pipe.
4628 *
4629 * If possible, match the pipe depth to the fb depth. In some cases, this
4630 * isn't ideal, because the connected output supports a lesser or restricted
4631 * set of depths. Resolve that here:
4632 * LVDS typically supports only 6bpc, so clamp down in that case
4633 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4634 * Displays may support a restricted set as well, check EDID and clamp as
4635 * appropriate.
4636 *
4637 * RETURNS:
4638 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4639 * true if they don't match).
4640 */
4641static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4642 unsigned int *pipe_bpp)
4643{
4644 struct drm_device *dev = crtc->dev;
4645 struct drm_i915_private *dev_priv = dev->dev_private;
4646 struct drm_encoder *encoder;
4647 struct drm_connector *connector;
4648 unsigned int display_bpc = UINT_MAX, bpc;
4649
4650 /* Walk the encoders & connectors on this crtc, get min bpc */
4651 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4652 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4653
4654 if (encoder->crtc != crtc)
4655 continue;
4656
4657 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4658 unsigned int lvds_bpc;
4659
4660 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4661 LVDS_A3_POWER_UP)
4662 lvds_bpc = 8;
4663 else
4664 lvds_bpc = 6;
4665
4666 if (lvds_bpc < display_bpc) {
4667 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4668 display_bpc = lvds_bpc;
4669 }
4670 continue;
4671 }
4672
4673 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4674 /* Use VBT settings if we have an eDP panel */
4675 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4676
4677 if (edp_bpc < display_bpc) {
4678 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4679 display_bpc = edp_bpc;
4680 }
4681 continue;
4682 }
4683
4684 /* Not one of the known troublemakers, check the EDID */
4685 list_for_each_entry(connector, &dev->mode_config.connector_list,
4686 head) {
4687 if (connector->encoder != encoder)
4688 continue;
4689
62ac41a6
JB		 4690 /* Don't use an invalid EDID bpc value */
4691 if (connector->display_info.bpc &&
4692 connector->display_info.bpc < display_bpc) {
5a354204
JB		 4693 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4694 display_bpc = connector->display_info.bpc;
4695 }
4696 }
4697
4698 /*
4699 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4700 * through, clamp it down. (Note: >12bpc will be caught below.)
4701 */
4702 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4703 if (display_bpc > 8 && display_bpc < 12) {
4704 DRM_DEBUG_DRIVER("forcing bpc to 12 for HDMI\n");
4705 display_bpc = 12;
4706 } else {
4707 DRM_DEBUG_DRIVER("forcing bpc to 8 for HDMI\n");
4708 display_bpc = 8;
4709 }
4710 }
4711 }
4712
4713 /*
4714 * We could just drive the pipe at the highest bpc all the time and
4715 * enable dithering as needed, but that costs bandwidth. So choose
4716 * the minimum value that expresses the full color range of the fb but
4717 * also stays within the max display bpc discovered above.
4718 */
4719
4720 switch (crtc->fb->depth) {
4721 case 8:
4722 bpc = 8; /* since we go through a colormap */
4723 break;
4724 case 15:
4725 case 16:
4726 bpc = 6; /* min is 18bpp */
4727 break;
4728 case 24:
578393cd 4729 bpc = 8;
5a354204
JB		 4730 break;
4731 case 30:
578393cd 4732 bpc = 10;
5a354204
JB		 4733 break;
4734 case 48:
578393cd 4735 bpc = 12;
5a354204
JB		 4736 break;
4737 default:
4738 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4739 bpc = min((unsigned int)8, display_bpc);
4740 break;
4741 }
4742
578393cd
KP		 4743 display_bpc = min(display_bpc, bpc);
4744
5a354204
JB		 4745 DRM_DEBUG_DRIVER("setting pipe bpc to %d (max display bpc %d)\n",
4746 bpc, display_bpc);
4747
578393cd 4748 *pipe_bpp = display_bpc * 3;
5a354204
JB		 4749
4750 return display_bpc != bpc;
4751}
4752
f564048e
EA		 4753static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4754 struct drm_display_mode *mode,
4755 struct drm_display_mode *adjusted_mode,
4756 int x, int y,
4757 struct drm_framebuffer *old_fb)
79e53945
JB		 4758{
4759 struct drm_device *dev = crtc->dev;
4760 struct drm_i915_private *dev_priv = dev->dev_private;
4761 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4762 int pipe = intel_crtc->pipe;
80824003 4763 int plane = intel_crtc->plane;
c751ce4f 4764 int refclk, num_connectors = 0;
652c393a 4765 intel_clock_t clock, reduced_clock;
5eddb70b 4766 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
652c393a 4767 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
a4fc5ed6 4768 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
79e53945 4769 struct drm_mode_config *mode_config = &dev->mode_config;
5eddb70b 4770 struct intel_encoder *encoder;
d4906093 4771 const intel_limit_t *limit;
5c3b82e2 4772 int ret;
fae14981 4773 u32 temp;
aa9b500d 4774 u32 lvds_sync = 0;
79e53945 4775
5eddb70b
CW		 4776 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4777 if (encoder->base.crtc != crtc)
79e53945
JB		 4778 continue;
4779
5eddb70b 4780 switch (encoder->type) {
79e53945
JB		 4781 case INTEL_OUTPUT_LVDS:
4782 is_lvds = true;
4783 break;
4784 case INTEL_OUTPUT_SDVO:
7d57382e 4785 case INTEL_OUTPUT_HDMI:
79e53945 4786 is_sdvo = true;
5eddb70b 4787 if (encoder->needs_tv_clock)
e2f0ba97 4788 is_tv = true;
79e53945
JB		 4789 break;
4790 case INTEL_OUTPUT_DVO:
4791 is_dvo = true;
4792 break;
4793 case INTEL_OUTPUT_TVOUT:
4794 is_tv = true;
4795 break;
4796 case INTEL_OUTPUT_ANALOG:
4797 is_crt = true;
4798 break;
a4fc5ed6
KP		 4799 case INTEL_OUTPUT_DISPLAYPORT:
4800 is_dp = true;
4801 break;
79e53945 4802 }
43565a06 4803
c751ce4f 4804 num_connectors++;
79e53945
JB		 4805 }
4806
a7615030 4807 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
43565a06 4808 refclk = dev_priv->lvds_ssc_freq * 1000;
28c97730 4809 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5eddb70b 4810 refclk / 1000);
a6c45cf0 4811 } else if (!IS_GEN2(dev)) {
79e53945
JB		 4812 refclk = 96000;
4813 } else {
4814 refclk = 48000;
4815 }
4816
d4906093
ML		 4817 /*
4818 * Returns a set of divisors for the desired target clock with the given
4819 * refclk, or FALSE. The returned values represent the clock equation:
4820 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4821 */
1b894b59 4822 limit = intel_limit(crtc, refclk);
d4906093 4823 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
79e53945
JB		 4824 if (!ok) {
4825 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4826 return -EINVAL;
79e53945
JB		 4827 }
4828
cda4b7d3 4829 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4830 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4831
ddc9003c
ZY		 4832 if (is_lvds && dev_priv->lvds_downclock_avail) {
4833 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4834 dev_priv->lvds_downclock,
4835 refclk,
4836 &reduced_clock);
18f9ed12
ZY		 4837 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4838 /*
4839 * If the different P is found, it means that we can't
4840 * switch the display clock by using the FP0/FP1.
4841 * In such case we will disable the LVDS downclock
4842 * feature.
4843 */
4844 DRM_DEBUG_KMS("Different P is found for "
5eddb70b 4845 "LVDS clock/downclock\n");
18f9ed12
ZY		 4846 has_reduced_clock = 0;
4847 }
652c393a 4848 }
7026d4ac
ZW		 4849 /* SDVO TV has fixed PLL values depend on its clock range,
4850 this mirrors vbios setting. */
4851 if (is_sdvo && is_tv) {
4852 if (adjusted_mode->clock >= 100000
5eddb70b 4853 && adjusted_mode->clock < 140500) {
7026d4ac
ZW		 4854 clock.p1 = 2;
4855 clock.p2 = 10;
4856 clock.n = 3;
4857 clock.m1 = 16;
4858 clock.m2 = 8;
4859 } else if (adjusted_mode->clock >= 140500
5eddb70b 4860 && adjusted_mode->clock <= 200000) {
7026d4ac
ZW		 4861 clock.p1 = 1;
4862 clock.p2 = 10;
4863 clock.n = 6;
4864 clock.m1 = 12;
4865 clock.m2 = 8;
4866 }
4867 }
4868
f2b115e6 4869 if (IS_PINEVIEW(dev)) {
2177832f 4870 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
652c393a
JB		 4871 if (has_reduced_clock)
4872 fp2 = (1 << reduced_clock.n) << 16 |
4873 reduced_clock.m1 << 8 | reduced_clock.m2;
4874 } else {
2177832f 4875 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
652c393a
JB		 4876 if (has_reduced_clock)
4877 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4878 reduced_clock.m2;
4879 }
79e53945 4880
929c77fb 4881 dpll = DPLL_VGA_MODE_DIS;
2c07245f 4882
a6c45cf0 4883 if (!IS_GEN2(dev)) {
79e53945
JB		 4884 if (is_lvds)
4885 dpll |= DPLLB_MODE_LVDS;
4886 else
4887 dpll |= DPLLB_MODE_DAC_SERIAL;
4888 if (is_sdvo) {
6c9547ff
CW		 4889 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4890 if (pixel_multiplier > 1) {
4891 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4892 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
6c9547ff 4893 }
79e53945 4894 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 4895 }
929c77fb 4896 if (is_dp)
a4fc5ed6 4897 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945
JB		 4898
4899 /* compute bitmask from p1 value */
f2b115e6
AJ		 4900 if (IS_PINEVIEW(dev))
4901 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
2c07245f 4902 else {
2177832f 4903 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
652c393a
JB		 4904 if (IS_G4X(dev) && has_reduced_clock)
4905 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
2c07245f 4906 }
79e53945
JB		 4907 switch (clock.p2) {
4908 case 5:
4909 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4910 break;
4911 case 7:
4912 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4913 break;
4914 case 10:
4915 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4916 break;
4917 case 14:
4918 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4919 break;
4920 }
929c77fb 4921 if (INTEL_INFO(dev)->gen >= 4)
79e53945
JB		 4922 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4923 } else {
4924 if (is_lvds) {
4925 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4926 } else {
4927 if (clock.p1 == 2)
4928 dpll |= PLL_P1_DIVIDE_BY_TWO;
4929 else
4930 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4931 if (clock.p2 == 4)
4932 dpll |= PLL_P2_DIVIDE_BY_4;
4933 }
4934 }
4935
43565a06
KH		 4936 if (is_sdvo && is_tv)
4937 dpll |= PLL_REF_INPUT_TVCLKINBC;
4938 else if (is_tv)
79e53945 4939 /* XXX: just matching BIOS for now */
43565a06 4940 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 4941 dpll |= 3;
a7615030 4942 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 4943 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 4944 else
4945 dpll |= PLL_REF_INPUT_DREFCLK;
4946
4947 /* setup pipeconf */
5eddb70b 4948 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4949
4950 /* Set up the display plane register */
4951 dspcntr = DISPPLANE_GAMMA_ENABLE;
4952
f2b115e6 4953 /* Ironlake's plane is forced to pipe, bit 24 is to
2c07245f 4954 enable color space conversion */
929c77fb
EA		 4955 if (pipe == 0)
4956 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4957 else
4958 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 4959
a6c45cf0 4960 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 4961 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4962 * core speed.
4963 *
4964 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4965 * pipe == 0 check?
4966 */
e70236a8
JB		 4967 if (mode->clock >
4968 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 4969 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 4970 else
5eddb70b 4971 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 4972 }
4973
929c77fb 4974 dpll |= DPLL_VCO_ENABLE;
8d86dc6a 4975
28c97730 4976 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4977 drm_mode_debug_printmodeline(mode);
4978
fae14981
EA		 4979 I915_WRITE(FP0(pipe), fp);
4980 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5eddb70b 4981
fae14981 4982 POSTING_READ(DPLL(pipe));
c713bb08 4983 udelay(150);
8db9d77b 4984
79e53945
JB		 4985 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4986 * This is an exception to the general rule that mode_set doesn't turn
4987 * things on.
4988 */
4989 if (is_lvds) {
fae14981 4990 temp = I915_READ(LVDS);
5eddb70b 4991 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
b3b095b3 4992 if (pipe == 1) {
929c77fb 4993 temp |= LVDS_PIPEB_SELECT;
b3b095b3 4994 } else {
929c77fb 4995 temp &= ~LVDS_PIPEB_SELECT;
b3b095b3 4996 }
a3e17eb8 4997 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 4998 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 4999 /* Set the B0-B3 data pairs corresponding to whether we're going to
5000 * set the DPLLs for dual-channel mode or not.
5001 */
5002 if (clock.p2 == 7)
5eddb70b 5003 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 5004 else
5eddb70b 5005 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 5006
5007 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5008 * appropriately here, but we need to look more thoroughly into how
5009 * panels behave in the two modes.
5010 */
929c77fb
EA		 5011 /* set the dithering flag on LVDS as needed */
5012 if (INTEL_INFO(dev)->gen >= 4) {
434ed097 5013 if (dev_priv->lvds_dither)
5eddb70b 5014 temp |= LVDS_ENABLE_DITHER;
434ed097 5015 else
5eddb70b 5016 temp &= ~LVDS_ENABLE_DITHER;
898822ce 5017 }
aa9b500d
BF		 5018 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5019 lvds_sync |= LVDS_HSYNC_POLARITY;
5020 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5021 lvds_sync |= LVDS_VSYNC_POLARITY;
5022 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5023 != lvds_sync) {
5024 char flags[2] = "-+";
5025 DRM_INFO("Changing LVDS panel from "
5026 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5027 flags[!(temp & LVDS_HSYNC_POLARITY)],
5028 flags[!(temp & LVDS_VSYNC_POLARITY)],
5029 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5030 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5031 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5032 temp |= lvds_sync;
5033 }
fae14981 5034 I915_WRITE(LVDS, temp);
79e53945 5035 }
434ed097 5036
929c77fb 5037 if (is_dp) {
a4fc5ed6 5038 intel_dp_set_m_n(crtc, mode, adjusted_mode);
434ed097
JB		 5039 }
5040
fae14981 5041 I915_WRITE(DPLL(pipe), dpll);
5eddb70b 5042
c713bb08 5043 /* Wait for the clocks to stabilize. */
fae14981 5044 POSTING_READ(DPLL(pipe));
c713bb08 5045 udelay(150);
32f9d658 5046
c713bb08
EA		 5047 if (INTEL_INFO(dev)->gen >= 4) {
5048 temp = 0;
5049 if (is_sdvo) {
5050 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
5051 if (temp > 1)
5052 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5053 else
5054 temp = 0;
32f9d658 5055 }
c713bb08
EA		 5056 I915_WRITE(DPLL_MD(pipe), temp);
5057 } else {
5058 /* The pixel multiplier can only be updated once the
5059 * DPLL is enabled and the clocks are stable.
5060 *
5061 * So write it again.
5062 */
fae14981 5063 I915_WRITE(DPLL(pipe), dpll);
79e53945 5064 }
79e53945 5065
5eddb70b 5066 intel_crtc->lowfreq_avail = false;
652c393a 5067 if (is_lvds && has_reduced_clock && i915_powersave) {
fae14981 5068 I915_WRITE(FP1(pipe), fp2);
652c393a
JB		 5069 intel_crtc->lowfreq_avail = true;
5070 if (HAS_PIPE_CXSR(dev)) {
28c97730 5071 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a
JB		 5072 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5073 }
5074 } else {
fae14981 5075 I915_WRITE(FP1(pipe), fp);
652c393a 5076 if (HAS_PIPE_CXSR(dev)) {
28c97730 5077 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 5078 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5079 }
5080 }
5081
734b4157
KH		 5082 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5083 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5084 /* the chip adds 2 halflines automatically */
5085 adjusted_mode->crtc_vdisplay -= 1;
5086 adjusted_mode->crtc_vtotal -= 1;
5087 adjusted_mode->crtc_vblank_start -= 1;
5088 adjusted_mode->crtc_vblank_end -= 1;
5089 adjusted_mode->crtc_vsync_end -= 1;
5090 adjusted_mode->crtc_vsync_start -= 1;
5091 } else
5092 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5093
5eddb70b
CW		 5094 I915_WRITE(HTOTAL(pipe),
5095 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 5096 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 5097 I915_WRITE(HBLANK(pipe),
5098 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 5099 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 5100 I915_WRITE(HSYNC(pipe),
5101 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 5102 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 5103
5104 I915_WRITE(VTOTAL(pipe),
5105 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 5106 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 5107 I915_WRITE(VBLANK(pipe),
5108 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 5109 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 5110 I915_WRITE(VSYNC(pipe),
5111 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 5112 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b
CW		 5113
5114 /* pipesrc and dspsize control the size that is scaled from,
5115 * which should always be the user's requested size.
79e53945 5116 */
929c77fb
EA		 5117 I915_WRITE(DSPSIZE(plane),
5118 ((mode->vdisplay - 1) << 16) |
5119 (mode->hdisplay - 1));
5120 I915_WRITE(DSPPOS(plane), 0);
5eddb70b
CW		 5121 I915_WRITE(PIPESRC(pipe),
5122 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 5123
f564048e
EA		 5124 I915_WRITE(PIPECONF(pipe), pipeconf);
5125 POSTING_READ(PIPECONF(pipe));
929c77fb 5126 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 5127
5128 intel_wait_for_vblank(dev, pipe);
5129
f564048e
EA		 5130 I915_WRITE(DSPCNTR(plane), dspcntr);
5131 POSTING_READ(DSPCNTR(plane));
284d9529 5132 intel_enable_plane(dev_priv, plane, pipe);
f564048e
EA		 5133
5134 ret = intel_pipe_set_base(crtc, x, y, old_fb);
5135
5136 intel_update_watermarks(dev);
5137
f564048e
EA		 5138 return ret;
5139}
5140
9fb526db
KP		 5141/*
5142 * Initialize reference clocks when the driver loads
5143 */
5144void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 5145{
5146 struct drm_i915_private *dev_priv = dev->dev_private;
5147 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 5148 struct intel_encoder *encoder;
13d83a67
JB		 5149 u32 temp;
5150 bool has_lvds = false;
199e5d79
KP		 5151 bool has_cpu_edp = false;
5152 bool has_pch_edp = false;
5153 bool has_panel = false;
99eb6a01
KP		 5154 bool has_ck505 = false;
5155 bool can_ssc = false;
13d83a67
JB		 5156
5157 /* We need to take the global config into account */
199e5d79
KP		 5158 list_for_each_entry(encoder, &mode_config->encoder_list,
5159 base.head) {
5160 switch (encoder->type) {
5161 case INTEL_OUTPUT_LVDS:
5162 has_panel = true;
5163 has_lvds = true;
5164 break;
5165 case INTEL_OUTPUT_EDP:
5166 has_panel = true;
5167 if (intel_encoder_is_pch_edp(&encoder->base))
5168 has_pch_edp = true;
5169 else
5170 has_cpu_edp = true;
5171 break;
13d83a67
JB		 5172 }
5173 }
5174
99eb6a01
KP		 5175 if (HAS_PCH_IBX(dev)) {
5176 has_ck505 = dev_priv->display_clock_mode;
5177 can_ssc = has_ck505;
5178 } else {
5179 has_ck505 = false;
5180 can_ssc = true;
5181 }
5182
5183 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
5184 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
5185 has_ck505);
13d83a67
JB		 5186
5187 /* Ironlake: try to setup display ref clock before DPLL
5188 * enabling. This is only under driver's control after
5189 * PCH B stepping, previous chipset stepping should be
5190 * ignoring this setting.
5191 */
5192 temp = I915_READ(PCH_DREF_CONTROL);
5193 /* Always enable nonspread source */
5194 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5195
99eb6a01
KP		 5196 if (has_ck505)
5197 temp |= DREF_NONSPREAD_CK505_ENABLE;
5198 else
5199 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5200
199e5d79
KP		 5201 if (has_panel) {
5202 temp &= ~DREF_SSC_SOURCE_MASK;
5203 temp |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5204
199e5d79 5205 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5206 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5207 DRM_DEBUG_KMS("Using SSC on panel\n");
13d83a67 5208 temp |= DREF_SSC1_ENABLE;
13d83a67 5209 }
199e5d79
KP		 5210
5211 /* Get SSC going before enabling the outputs */
5212 I915_WRITE(PCH_DREF_CONTROL, temp);
5213 POSTING_READ(PCH_DREF_CONTROL);
5214 udelay(200);
5215
13d83a67
JB		 5216 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5217
5218 /* Enable CPU source on CPU attached eDP */
199e5d79 5219 if (has_cpu_edp) {
99eb6a01 5220 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5221 DRM_DEBUG_KMS("Using SSC on eDP\n");
13d83a67 5222 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5223 }
13d83a67
JB		 5224 else
5225 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79
KP		 5226 } else
5227 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5228
5229 I915_WRITE(PCH_DREF_CONTROL, temp);
5230 POSTING_READ(PCH_DREF_CONTROL);
5231 udelay(200);
5232 } else {
5233 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5234
5235 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5236
5237 /* Turn off CPU output */
5238 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5239
5240 I915_WRITE(PCH_DREF_CONTROL, temp);
5241 POSTING_READ(PCH_DREF_CONTROL);
5242 udelay(200);
5243
5244 /* Turn off the SSC source */
5245 temp &= ~DREF_SSC_SOURCE_MASK;
5246 temp |= DREF_SSC_SOURCE_DISABLE;
5247
5248 /* Turn off SSC1 */
5249 temp &= ~ DREF_SSC1_ENABLE;
5250
13d83a67
JB		 5251 I915_WRITE(PCH_DREF_CONTROL, temp);
5252 POSTING_READ(PCH_DREF_CONTROL);
5253 udelay(200);
5254 }
5255}
5256
d9d444cb
JB		 5257static int ironlake_get_refclk(struct drm_crtc *crtc)
5258{
5259 struct drm_device *dev = crtc->dev;
5260 struct drm_i915_private *dev_priv = dev->dev_private;
5261 struct intel_encoder *encoder;
5262 struct drm_mode_config *mode_config = &dev->mode_config;
5263 struct intel_encoder *edp_encoder = NULL;
5264 int num_connectors = 0;
5265 bool is_lvds = false;
5266
5267 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5268 if (encoder->base.crtc != crtc)
5269 continue;
5270
5271 switch (encoder->type) {
5272 case INTEL_OUTPUT_LVDS:
5273 is_lvds = true;
5274 break;
5275 case INTEL_OUTPUT_EDP:
5276 edp_encoder = encoder;
5277 break;
5278 }
5279 num_connectors++;
5280 }
5281
5282 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5283 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5284 dev_priv->lvds_ssc_freq);
5285 return dev_priv->lvds_ssc_freq * 1000;
5286 }
5287
5288 return 120000;
5289}
5290
f564048e
EA		 5291static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5292 struct drm_display_mode *mode,
5293 struct drm_display_mode *adjusted_mode,
5294 int x, int y,
5295 struct drm_framebuffer *old_fb)
79e53945
JB		 5296{
5297 struct drm_device *dev = crtc->dev;
5298 struct drm_i915_private *dev_priv = dev->dev_private;
5299 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5300 int pipe = intel_crtc->pipe;
80824003 5301 int plane = intel_crtc->plane;
c751ce4f 5302 int refclk, num_connectors = 0;
652c393a 5303 intel_clock_t clock, reduced_clock;
5eddb70b 5304 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
a07d6787 5305 bool ok, has_reduced_clock = false, is_sdvo = false;
a4fc5ed6 5306 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
8e647a27 5307 struct intel_encoder *has_edp_encoder = NULL;
79e53945 5308 struct drm_mode_config *mode_config = &dev->mode_config;
5eddb70b 5309 struct intel_encoder *encoder;
d4906093 5310 const intel_limit_t *limit;
5c3b82e2 5311 int ret;
2c07245f 5312 struct fdi_m_n m_n = {0};
fae14981 5313 u32 temp;
aa9b500d 5314 u32 lvds_sync = 0;
5a354204
JB		 5315 int target_clock, pixel_multiplier, lane, link_bw, factor;
5316 unsigned int pipe_bpp;
5317 bool dither;
79e53945 5318
5eddb70b
CW		 5319 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5320 if (encoder->base.crtc != crtc)
79e53945
JB		 5321 continue;
5322
5eddb70b 5323 switch (encoder->type) {
79e53945
JB		 5324 case INTEL_OUTPUT_LVDS:
5325 is_lvds = true;
5326 break;
5327 case INTEL_OUTPUT_SDVO:
7d57382e 5328 case INTEL_OUTPUT_HDMI:
79e53945 5329 is_sdvo = true;
5eddb70b 5330 if (encoder->needs_tv_clock)
e2f0ba97 5331 is_tv = true;
79e53945 5332 break;
79e53945
JB		 5333 case INTEL_OUTPUT_TVOUT:
5334 is_tv = true;
5335 break;
5336 case INTEL_OUTPUT_ANALOG:
5337 is_crt = true;
5338 break;
a4fc5ed6
KP		 5339 case INTEL_OUTPUT_DISPLAYPORT:
5340 is_dp = true;
5341 break;
32f9d658 5342 case INTEL_OUTPUT_EDP:
5eddb70b 5343 has_edp_encoder = encoder;
32f9d658 5344 break;
79e53945 5345 }
43565a06 5346
c751ce4f 5347 num_connectors++;
79e53945
JB		 5348 }
5349
d9d444cb 5350 refclk = ironlake_get_refclk(crtc);
79e53945 5351
d4906093
ML		 5352 /*
5353 * Returns a set of divisors for the desired target clock with the given
5354 * refclk, or FALSE. The returned values represent the clock equation:
5355 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5356 */
1b894b59 5357 limit = intel_limit(crtc, refclk);
d4906093 5358 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
79e53945
JB		 5359 if (!ok) {
5360 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 5361 return -EINVAL;
79e53945
JB		 5362 }
5363
cda4b7d3 5364 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 5365 intel_crtc_update_cursor(crtc, true);
cda4b7d3 5366
ddc9003c
ZY		 5367 if (is_lvds && dev_priv->lvds_downclock_avail) {
5368 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 5369 dev_priv->lvds_downclock,
5370 refclk,
5371 &reduced_clock);
18f9ed12
ZY		 5372 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
5373 /*
5374 * If the different P is found, it means that we can't
5375 * switch the display clock by using the FP0/FP1.
5376 * In such case we will disable the LVDS downclock
5377 * feature.
5378 */
5379 DRM_DEBUG_KMS("Different P is found for "
5eddb70b 5380 "LVDS clock/downclock\n");
18f9ed12
ZY		 5381 has_reduced_clock = 0;
5382 }
652c393a 5383 }
7026d4ac
ZW		 5384 /* SDVO TV has fixed PLL values depend on its clock range,
5385 this mirrors vbios setting. */
5386 if (is_sdvo && is_tv) {
5387 if (adjusted_mode->clock >= 100000
5eddb70b 5388 && adjusted_mode->clock < 140500) {
7026d4ac
ZW		 5389 clock.p1 = 2;
5390 clock.p2 = 10;
5391 clock.n = 3;
5392 clock.m1 = 16;
5393 clock.m2 = 8;
5394 } else if (adjusted_mode->clock >= 140500
5eddb70b 5395 && adjusted_mode->clock <= 200000) {
7026d4ac
ZW		 5396 clock.p1 = 1;
5397 clock.p2 = 10;
5398 clock.n = 6;
5399 clock.m1 = 12;
5400 clock.m2 = 8;
5401 }
5402 }
5403
2c07245f 5404 /* FDI link */
8febb297
EA		 5405 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5406 lane = 0;
5407 /* CPU eDP doesn't require FDI link, so just set DP M/N
5408 according to current link config */
5409 if (has_edp_encoder &&
5410 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5411 target_clock = mode->clock;
5412 intel_edp_link_config(has_edp_encoder,
5413 &lane, &link_bw);
5414 } else {
5415 /* [e]DP over FDI requires target mode clock
5416 instead of link clock */
5417 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5eb08b69 5418 target_clock = mode->clock;
8febb297
EA		 5419 else
5420 target_clock = adjusted_mode->clock;
5421
5422 /* FDI is a binary signal running at ~2.7GHz, encoding
5423 * each output octet as 10 bits. The actual frequency
5424 * is stored as a divider into a 100MHz clock, and the
5425 * mode pixel clock is stored in units of 1KHz.
5426 * Hence the bw of each lane in terms of the mode signal
5427 * is:
5428 */
5429 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5430 }
58a27471 5431
8febb297
EA		 5432 /* determine panel color depth */
5433 temp = I915_READ(PIPECONF(pipe));
5434 temp &= ~PIPE_BPC_MASK;
5a354204
JB		 5435 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp);
5436 switch (pipe_bpp) {
5437 case 18:
5438 temp |= PIPE_6BPC;
8febb297 5439 break;
5a354204
JB		 5440 case 24:
5441 temp |= PIPE_8BPC;
8febb297 5442 break;
5a354204
JB		 5443 case 30:
5444 temp |= PIPE_10BPC;
8febb297 5445 break;
5a354204
JB		 5446 case 36:
5447 temp |= PIPE_12BPC;
8febb297
EA		 5448 break;
5449 default:
62ac41a6
JB		 5450 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
5451 pipe_bpp);
5a354204
JB		 5452 temp |= PIPE_8BPC;
5453 pipe_bpp = 24;
5454 break;
8febb297 5455 }
77ffb597 5456
5a354204
JB		 5457 intel_crtc->bpp = pipe_bpp;
5458 I915_WRITE(PIPECONF(pipe), temp);
5459
8febb297
EA		 5460 if (!lane) {
5461 /*
5462 * Account for spread spectrum to avoid
5463 * oversubscribing the link. Max center spread
5464 * is 2.5%; use 5% for safety's sake.
5465 */
5a354204 5466 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
8febb297 5467 lane = bps / (link_bw * 8) + 1;
5eb08b69 5468 }
2c07245f 5469
8febb297
EA		 5470 intel_crtc->fdi_lanes = lane;
5471
5472 if (pixel_multiplier > 1)
5473 link_bw *= pixel_multiplier;
5a354204
JB		 5474 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5475 &m_n);
8febb297 5476
a07d6787
EA		 5477 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5478 if (has_reduced_clock)
5479 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5480 reduced_clock.m2;
79e53945 5481
c1858123 5482 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5483 factor = 21;
5484 if (is_lvds) {
5485 if ((intel_panel_use_ssc(dev_priv) &&
5486 dev_priv->lvds_ssc_freq == 100) ||
5487 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5488 factor = 25;
5489 } else if (is_sdvo && is_tv)
5490 factor = 20;
c1858123 5491
cb0e0931 5492 if (clock.m < factor * clock.n)
8febb297 5493 fp |= FP_CB_TUNE;
2c07245f 5494
5eddb70b 5495 dpll = 0;
2c07245f 5496
a07d6787
EA		 5497 if (is_lvds)
5498 dpll |= DPLLB_MODE_LVDS;
5499 else
5500 dpll |= DPLLB_MODE_DAC_SERIAL;
5501 if (is_sdvo) {
5502 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5503 if (pixel_multiplier > 1) {
5504 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 5505 }
a07d6787
EA		 5506 dpll |= DPLL_DVO_HIGH_SPEED;
5507 }
5508 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5509 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5510
a07d6787
EA		 5511 /* compute bitmask from p1 value */
5512 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5513 /* also FPA1 */
5514 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5515
5516 switch (clock.p2) {
5517 case 5:
5518 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5519 break;
5520 case 7:
5521 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5522 break;
5523 case 10:
5524 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5525 break;
5526 case 14:
5527 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5528 break;
79e53945
JB		 5529 }
5530
43565a06
KH		 5531 if (is_sdvo && is_tv)
5532 dpll |= PLL_REF_INPUT_TVCLKINBC;
5533 else if (is_tv)
79e53945 5534 /* XXX: just matching BIOS for now */
43565a06 5535 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5536 dpll |= 3;
a7615030 5537 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5538 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5539 else
5540 dpll |= PLL_REF_INPUT_DREFCLK;
5541
5542 /* setup pipeconf */
5eddb70b 5543 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 5544
5545 /* Set up the display plane register */
5546 dspcntr = DISPPLANE_GAMMA_ENABLE;
5547
28c97730 5548 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 5549 drm_mode_debug_printmodeline(mode);
5550
5c5313c8
JB		 5551 /* PCH eDP needs FDI, but CPU eDP does not */
5552 if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
fae14981
EA		 5553 I915_WRITE(PCH_FP0(pipe), fp);
5554 I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5eddb70b 5555
fae14981 5556 POSTING_READ(PCH_DPLL(pipe));
79e53945
JB		 5557 udelay(150);
5558 }
5559
8db9d77b
ZW		 5560 /* enable transcoder DPLL */
5561 if (HAS_PCH_CPT(dev)) {
5562 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 5563 switch (pipe) {
5564 case 0:
5eddb70b 5565 temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
9db4a9c7
JB		 5566 break;
5567 case 1:
5eddb70b 5568 temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
9db4a9c7
JB		 5569 break;
5570 case 2:
5571 /* FIXME: manage transcoder PLLs? */
5572 temp |= TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL;
5573 break;
5574 default:
5575 BUG();
32f9d658 5576 }
8db9d77b 5577 I915_WRITE(PCH_DPLL_SEL, temp);
5eddb70b
CW		 5578
5579 POSTING_READ(PCH_DPLL_SEL);
8db9d77b
ZW		 5580 udelay(150);
5581 }
5582
79e53945
JB		 5583 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5584 * This is an exception to the general rule that mode_set doesn't turn
5585 * things on.
5586 */
5587 if (is_lvds) {
fae14981 5588 temp = I915_READ(PCH_LVDS);
5eddb70b 5589 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
b3b095b3
ZW		 5590 if (pipe == 1) {
5591 if (HAS_PCH_CPT(dev))
5eddb70b 5592 temp |= PORT_TRANS_B_SEL_CPT;
b3b095b3 5593 else
5eddb70b 5594 temp |= LVDS_PIPEB_SELECT;
b3b095b3
ZW		 5595 } else {
5596 if (HAS_PCH_CPT(dev))
5eddb70b 5597 temp &= ~PORT_TRANS_SEL_MASK;
b3b095b3 5598 else
5eddb70b 5599 temp &= ~LVDS_PIPEB_SELECT;
b3b095b3 5600 }
a3e17eb8 5601 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 5602 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 5603 /* Set the B0-B3 data pairs corresponding to whether we're going to
5604 * set the DPLLs for dual-channel mode or not.
5605 */
5606 if (clock.p2 == 7)
5eddb70b 5607 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 5608 else
5eddb70b 5609 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 5610
5611 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5612 * appropriately here, but we need to look more thoroughly into how
5613 * panels behave in the two modes.
5614 */
aa9b500d
BF		 5615 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5616 lvds_sync |= LVDS_HSYNC_POLARITY;
5617 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5618 lvds_sync |= LVDS_VSYNC_POLARITY;
5619 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5620 != lvds_sync) {
5621 char flags[2] = "-+";
5622 DRM_INFO("Changing LVDS panel from "
5623 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5624 flags[!(temp & LVDS_HSYNC_POLARITY)],
5625 flags[!(temp & LVDS_VSYNC_POLARITY)],
5626 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5627 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5628 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5629 temp |= lvds_sync;
5630 }
fae14981 5631 I915_WRITE(PCH_LVDS, temp);
79e53945 5632 }
434ed097 5633
8febb297
EA		 5634 pipeconf &= ~PIPECONF_DITHER_EN;
5635 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5a354204 5636 if ((is_lvds && dev_priv->lvds_dither) || dither) {
8febb297
EA		 5637 pipeconf |= PIPECONF_DITHER_EN;
5638 pipeconf |= PIPECONF_DITHER_TYPE_ST1;
434ed097 5639 }
5c5313c8 5640 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
a4fc5ed6 5641 intel_dp_set_m_n(crtc, mode, adjusted_mode);
8febb297 5642 } else {
8db9d77b 5643 /* For non-DP output, clear any trans DP clock recovery setting.*/
9db4a9c7
JB		 5644 I915_WRITE(TRANSDATA_M1(pipe), 0);
5645 I915_WRITE(TRANSDATA_N1(pipe), 0);
5646 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5647 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
8db9d77b 5648 }
79e53945 5649
8febb297
EA		 5650 if (!has_edp_encoder ||
5651 intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
fae14981 5652 I915_WRITE(PCH_DPLL(pipe), dpll);
5eddb70b 5653
32f9d658 5654 /* Wait for the clocks to stabilize. */
fae14981 5655 POSTING_READ(PCH_DPLL(pipe));
32f9d658
ZW		 5656 udelay(150);
5657
8febb297
EA		 5658 /* The pixel multiplier can only be updated once the
5659 * DPLL is enabled and the clocks are stable.
5660 *
5661 * So write it again.
5662 */
fae14981 5663 I915_WRITE(PCH_DPLL(pipe), dpll);
79e53945 5664 }
79e53945 5665
5eddb70b 5666 intel_crtc->lowfreq_avail = false;
652c393a 5667 if (is_lvds && has_reduced_clock && i915_powersave) {
fae14981 5668 I915_WRITE(PCH_FP1(pipe), fp2);
652c393a
JB		 5669 intel_crtc->lowfreq_avail = true;
5670 if (HAS_PIPE_CXSR(dev)) {
28c97730 5671 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a
JB		 5672 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5673 }
5674 } else {
fae14981 5675 I915_WRITE(PCH_FP1(pipe), fp);
652c393a 5676 if (HAS_PIPE_CXSR(dev)) {
28c97730 5677 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 5678 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5679 }
5680 }
5681
734b4157
KH		 5682 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5683 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5684 /* the chip adds 2 halflines automatically */
5685 adjusted_mode->crtc_vdisplay -= 1;
5686 adjusted_mode->crtc_vtotal -= 1;
5687 adjusted_mode->crtc_vblank_start -= 1;
5688 adjusted_mode->crtc_vblank_end -= 1;
5689 adjusted_mode->crtc_vsync_end -= 1;
5690 adjusted_mode->crtc_vsync_start -= 1;
5691 } else
5692 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5693
5eddb70b
CW		 5694 I915_WRITE(HTOTAL(pipe),
5695 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 5696 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 5697 I915_WRITE(HBLANK(pipe),
5698 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 5699 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 5700 I915_WRITE(HSYNC(pipe),
5701 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 5702 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 5703
5704 I915_WRITE(VTOTAL(pipe),
5705 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 5706 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 5707 I915_WRITE(VBLANK(pipe),
5708 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 5709 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 5710 I915_WRITE(VSYNC(pipe),
5711 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 5712 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b 5713
8febb297
EA		 5714 /* pipesrc controls the size that is scaled from, which should
5715 * always be the user's requested size.
79e53945 5716 */
5eddb70b
CW		 5717 I915_WRITE(PIPESRC(pipe),
5718 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 5719
8febb297
EA		 5720 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5721 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5722 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5723 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
2c07245f 5724
8febb297
EA		 5725 if (has_edp_encoder &&
5726 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5727 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
2c07245f
ZW		 5728 }
5729
5eddb70b
CW		 5730 I915_WRITE(PIPECONF(pipe), pipeconf);
5731 POSTING_READ(PIPECONF(pipe));
79e53945 5732
9d0498a2 5733 intel_wait_for_vblank(dev, pipe);
79e53945 5734
f00a3ddf 5735 if (IS_GEN5(dev)) {
553bd149
ZW		 5736 /* enable address swizzle for tiling buffer */
5737 temp = I915_READ(DISP_ARB_CTL);
5738 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
5739 }
5740
5eddb70b 5741 I915_WRITE(DSPCNTR(plane), dspcntr);
b24e7179 5742 POSTING_READ(DSPCNTR(plane));
79e53945 5743
5c3b82e2 5744 ret = intel_pipe_set_base(crtc, x, y, old_fb);
7662c8bd
SL		 5745
5746 intel_update_watermarks(dev);
5747
1f803ee5 5748 return ret;
79e53945
JB		 5749}
5750
f564048e
EA		 5751static int intel_crtc_mode_set(struct drm_crtc *crtc,
5752 struct drm_display_mode *mode,
5753 struct drm_display_mode *adjusted_mode,
5754 int x, int y,
5755 struct drm_framebuffer *old_fb)
5756{
5757 struct drm_device *dev = crtc->dev;
5758 struct drm_i915_private *dev_priv = dev->dev_private;
0b701d27
EA		 5759 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5760 int pipe = intel_crtc->pipe;
f564048e
EA		 5761 int ret;
5762
0b701d27 5763 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5764
f564048e
EA		 5765 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5766 x, y, old_fb);
7662c8bd 5767
79e53945 5768 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5769
120eced9
KP		 5770 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
5771
1f803ee5 5772 return ret;
79e53945
JB		 5773}
5774
e0dac65e
WF		 5775static void g4x_write_eld(struct drm_connector *connector,
5776 struct drm_crtc *crtc)
5777{
5778 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5779 uint8_t *eld = connector->eld;
5780 uint32_t eldv;
5781 uint32_t len;
5782 uint32_t i;
5783
5784 i = I915_READ(G4X_AUD_VID_DID);
5785
5786 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5787 eldv = G4X_ELDV_DEVCL_DEVBLC;
5788 else
5789 eldv = G4X_ELDV_DEVCTG;
5790
5791 i = I915_READ(G4X_AUD_CNTL_ST);
5792 i &= ~(eldv | G4X_ELD_ADDR);
5793 len = (i >> 9) & 0x1f; /* ELD buffer size */
5794 I915_WRITE(G4X_AUD_CNTL_ST, i);
5795
5796 if (!eld[0])
5797 return;
5798
5799 len = min_t(uint8_t, eld[2], len);
5800 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5801 for (i = 0; i < len; i++)
5802 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5803
5804 i = I915_READ(G4X_AUD_CNTL_ST);
5805 i |= eldv;
5806 I915_WRITE(G4X_AUD_CNTL_ST, i);
5807}
5808
5809static void ironlake_write_eld(struct drm_connector *connector,
5810 struct drm_crtc *crtc)
5811{
5812 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5813 uint8_t *eld = connector->eld;
5814 uint32_t eldv;
5815 uint32_t i;
5816 int len;
5817 int hdmiw_hdmiedid;
5818 int aud_cntl_st;
5819 int aud_cntrl_st2;
5820
5821 if (IS_IVYBRIDGE(connector->dev)) {
5822 hdmiw_hdmiedid = GEN7_HDMIW_HDMIEDID_A;
5823 aud_cntl_st = GEN7_AUD_CNTRL_ST_A;
5824 aud_cntrl_st2 = GEN7_AUD_CNTRL_ST2;
5825 } else {
5826 hdmiw_hdmiedid = GEN5_HDMIW_HDMIEDID_A;
5827 aud_cntl_st = GEN5_AUD_CNTL_ST_A;
5828 aud_cntrl_st2 = GEN5_AUD_CNTL_ST2;
5829 }
5830
5831 i = to_intel_crtc(crtc)->pipe;
5832 hdmiw_hdmiedid += i * 0x100;
5833 aud_cntl_st += i * 0x100;
5834
5835 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
5836
5837 i = I915_READ(aud_cntl_st);
5838 i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */
5839 if (!i) {
5840 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5841 /* operate blindly on all ports */
5842 eldv = GEN5_ELD_VALIDB;
5843 eldv |= GEN5_ELD_VALIDB << 4;
5844 eldv |= GEN5_ELD_VALIDB << 8;
5845 } else {
5846 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
5847 eldv = GEN5_ELD_VALIDB << ((i - 1) * 4);
5848 }
5849
5850 i = I915_READ(aud_cntrl_st2);
5851 i &= ~eldv;
5852 I915_WRITE(aud_cntrl_st2, i);
5853
5854 if (!eld[0])
5855 return;
5856
5857 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5858 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5859 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5860 }
5861
5862 i = I915_READ(aud_cntl_st);
5863 i &= ~GEN5_ELD_ADDRESS;
5864 I915_WRITE(aud_cntl_st, i);
5865
5866 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5867 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5868 for (i = 0; i < len; i++)
5869 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5870
5871 i = I915_READ(aud_cntrl_st2);
5872 i |= eldv;
5873 I915_WRITE(aud_cntrl_st2, i);
5874}
5875
5876void intel_write_eld(struct drm_encoder *encoder,
5877 struct drm_display_mode *mode)
5878{
5879 struct drm_crtc *crtc = encoder->crtc;
5880 struct drm_connector *connector;
5881 struct drm_device *dev = encoder->dev;
5882 struct drm_i915_private *dev_priv = dev->dev_private;
5883
5884 connector = drm_select_eld(encoder, mode);
5885 if (!connector)
5886 return;
5887
5888 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5889 connector->base.id,
5890 drm_get_connector_name(connector),
5891 connector->encoder->base.id,
5892 drm_get_encoder_name(connector->encoder));
5893
5894 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5895
5896 if (dev_priv->display.write_eld)
5897 dev_priv->display.write_eld(connector, crtc);
5898}
5899
79e53945
JB		 5900/** Loads the palette/gamma unit for the CRTC with the prepared values */
5901void intel_crtc_load_lut(struct drm_crtc *crtc)
5902{
5903 struct drm_device *dev = crtc->dev;
5904 struct drm_i915_private *dev_priv = dev->dev_private;
5905 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 5906 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 5907 int i;
5908
5909 /* The clocks have to be on to load the palette. */
5910 if (!crtc->enabled)
5911 return;
5912
f2b115e6 5913 /* use legacy palette for Ironlake */
bad720ff 5914 if (HAS_PCH_SPLIT(dev))
9db4a9c7 5915 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 5916
79e53945
JB		 5917 for (i = 0; i < 256; i++) {
5918 I915_WRITE(palreg + 4 * i,
5919 (intel_crtc->lut_r[i] << 16) |
5920 (intel_crtc->lut_g[i] << 8) |
5921 intel_crtc->lut_b[i]);
5922 }
5923}
5924
560b85bb
CW		 5925static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5926{
5927 struct drm_device *dev = crtc->dev;
5928 struct drm_i915_private *dev_priv = dev->dev_private;
5929 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5930 bool visible = base != 0;
5931 u32 cntl;
5932
5933 if (intel_crtc->cursor_visible == visible)
5934 return;
5935
9db4a9c7 5936 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 5937 if (visible) {
5938 /* On these chipsets we can only modify the base whilst
5939 * the cursor is disabled.
5940 */
9db4a9c7 5941 I915_WRITE(_CURABASE, base);
560b85bb
CW		 5942
5943 cntl &= ~(CURSOR_FORMAT_MASK);
5944 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5945 cntl |= CURSOR_ENABLE |
5946 CURSOR_GAMMA_ENABLE |
5947 CURSOR_FORMAT_ARGB;
5948 } else
5949 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 5950 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 5951
5952 intel_crtc->cursor_visible = visible;
5953}
5954
5955static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5956{
5957 struct drm_device *dev = crtc->dev;
5958 struct drm_i915_private *dev_priv = dev->dev_private;
5959 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5960 int pipe = intel_crtc->pipe;
5961 bool visible = base != 0;
5962
5963 if (intel_crtc->cursor_visible != visible) {
548f245b 5964 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 5965 if (base) {
5966 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5967 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5968 cntl |= pipe << 28; /* Connect to correct pipe */
5969 } else {
5970 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5971 cntl |= CURSOR_MODE_DISABLE;
5972 }
9db4a9c7 5973 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 5974
5975 intel_crtc->cursor_visible = visible;
5976 }
5977 /* and commit changes on next vblank */
9db4a9c7 5978 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 5979}
5980
cda4b7d3 5981/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 5982static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5983 bool on)
cda4b7d3
CW		 5984{
5985 struct drm_device *dev = crtc->dev;
5986 struct drm_i915_private *dev_priv = dev->dev_private;
5987 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5988 int pipe = intel_crtc->pipe;
5989 int x = intel_crtc->cursor_x;
5990 int y = intel_crtc->cursor_y;
560b85bb 5991 u32 base, pos;
cda4b7d3
CW		 5992 bool visible;
5993
5994 pos = 0;
5995
6b383a7f 5996 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 5997 base = intel_crtc->cursor_addr;
5998 if (x > (int) crtc->fb->width)
5999 base = 0;
6000
6001 if (y > (int) crtc->fb->height)
6002 base = 0;
6003 } else
6004 base = 0;
6005
6006 if (x < 0) {
6007 if (x + intel_crtc->cursor_width < 0)
6008 base = 0;
6009
6010 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6011 x = -x;
6012 }
6013 pos |= x << CURSOR_X_SHIFT;
6014
6015 if (y < 0) {
6016 if (y + intel_crtc->cursor_height < 0)
6017 base = 0;
6018
6019 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6020 y = -y;
6021 }
6022 pos |= y << CURSOR_Y_SHIFT;
6023
6024 visible = base != 0;
560b85bb 6025 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6026 return;
6027
9db4a9c7 6028 I915_WRITE(CURPOS(pipe), pos);
560b85bb
CW		 6029 if (IS_845G(dev) || IS_I865G(dev))
6030 i845_update_cursor(crtc, base);
6031 else
6032 i9xx_update_cursor(crtc, base);
cda4b7d3
CW		 6033
6034 if (visible)
6035 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
6036}
6037
79e53945 6038static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6039 struct drm_file *file,
79e53945
JB		 6040 uint32_t handle,
6041 uint32_t width, uint32_t height)
6042{
6043 struct drm_device *dev = crtc->dev;
6044 struct drm_i915_private *dev_priv = dev->dev_private;
6045 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6046 struct drm_i915_gem_object *obj;
cda4b7d3 6047 uint32_t addr;
3f8bc370 6048 int ret;
79e53945 6049
28c97730 6050 DRM_DEBUG_KMS("\n");
79e53945
JB		 6051
6052 /* if we want to turn off the cursor ignore width and height */
6053 if (!handle) {
28c97730 6054 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6055 addr = 0;
05394f39 6056 obj = NULL;
5004417d 6057 mutex_lock(&dev->struct_mutex);
3f8bc370 6058 goto finish;
79e53945
JB		 6059 }
6060
6061 /* Currently we only support 64x64 cursors */
6062 if (width != 64 || height != 64) {
6063 DRM_ERROR("we currently only support 64x64 cursors\n");
6064 return -EINVAL;
6065 }
6066
05394f39 6067 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6068 if (&obj->base == NULL)
79e53945
JB		 6069 return -ENOENT;
6070
05394f39 6071 if (obj->base.size < width * height * 4) {
79e53945 6072 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6073 ret = -ENOMEM;
6074 goto fail;
79e53945
JB		 6075 }
6076
71acb5eb 6077 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6078 mutex_lock(&dev->struct_mutex);
b295d1b6 6079 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 6080 if (obj->tiling_mode) {
6081 DRM_ERROR("cursor cannot be tiled\n");
6082 ret = -EINVAL;
6083 goto fail_locked;
6084 }
6085
2da3b9b9 6086 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 6087 if (ret) {
6088 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6089 goto fail_locked;
e7b526bb
CW		 6090 }
6091
d9e86c0e
CW		 6092 ret = i915_gem_object_put_fence(obj);
6093 if (ret) {
2da3b9b9 6094 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6095 goto fail_unpin;
6096 }
6097
05394f39 6098 addr = obj->gtt_offset;
71acb5eb 6099 } else {
6eeefaf3 6100 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6101 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6102 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6103 align);
71acb5eb
DA		 6104 if (ret) {
6105 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6106 goto fail_locked;
71acb5eb 6107 }
05394f39 6108 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6109 }
6110
a6c45cf0 6111 if (IS_GEN2(dev))
14b60391
JB		 6112 I915_WRITE(CURSIZE, (height << 12) | width);
6113
3f8bc370 6114 finish:
3f8bc370 6115 if (intel_crtc->cursor_bo) {
b295d1b6 6116 if (dev_priv->info->cursor_needs_physical) {
05394f39 6117 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6118 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6119 } else
6120 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6121 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6122 }
80824003 6123
7f9872e0 6124 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6125
6126 intel_crtc->cursor_addr = addr;
05394f39 6127 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6128 intel_crtc->cursor_width = width;
6129 intel_crtc->cursor_height = height;
6130
6b383a7f 6131 intel_crtc_update_cursor(crtc, true);
3f8bc370 6132
79e53945 6133 return 0;
e7b526bb 6134fail_unpin:
05394f39 6135 i915_gem_object_unpin(obj);
7f9872e0 6136fail_locked:
34b8686e 6137 mutex_unlock(&dev->struct_mutex);
bc9025bd 6138fail:
05394f39 6139 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6140 return ret;
79e53945
JB		 6141}
6142
6143static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6144{
79e53945 6145 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6146
cda4b7d3
CW		 6147 intel_crtc->cursor_x = x;
6148 intel_crtc->cursor_y = y;
652c393a 6149
6b383a7f 6150 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 6151
6152 return 0;
6153}
6154
6155/** Sets the color ramps on behalf of RandR */
6156void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6157 u16 blue, int regno)
6158{
6159 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6160
6161 intel_crtc->lut_r[regno] = red >> 8;
6162 intel_crtc->lut_g[regno] = green >> 8;
6163 intel_crtc->lut_b[regno] = blue >> 8;
6164}
6165
b8c00ac5
DA		 6166void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6167 u16 *blue, int regno)
6168{
6169 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6170
6171 *red = intel_crtc->lut_r[regno] << 8;
6172 *green = intel_crtc->lut_g[regno] << 8;
6173 *blue = intel_crtc->lut_b[regno] << 8;
6174}
6175
79e53945 6176static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6177 u16 *blue, uint32_t start, uint32_t size)
79e53945 6178{
7203425a 6179 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6180 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6181
7203425a 6182 for (i = start; i < end; i++) {
79e53945
JB		 6183 intel_crtc->lut_r[i] = red[i] >> 8;
6184 intel_crtc->lut_g[i] = green[i] >> 8;
6185 intel_crtc->lut_b[i] = blue[i] >> 8;
6186 }
6187
6188 intel_crtc_load_lut(crtc);
6189}
6190
6191/**
6192 * Get a pipe with a simple mode set on it for doing load-based monitor
6193 * detection.
6194 *
6195 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 6196 * its requirements. The pipe will be connected to no other encoders.
79e53945 6197 *
c751ce4f 6198 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 6199 * configured for it. In the future, it could choose to temporarily disable
6200 * some outputs to free up a pipe for its use.
6201 *
6202 * \return crtc, or NULL if no pipes are available.
6203 */
6204
6205/* VESA 640x480x72Hz mode to set on the pipe */
6206static struct drm_display_mode load_detect_mode = {
6207 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6208 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6209};
6210
d2dff872
CW		 6211static struct drm_framebuffer *
6212intel_framebuffer_create(struct drm_device *dev,
6213 struct drm_mode_fb_cmd *mode_cmd,
6214 struct drm_i915_gem_object *obj)
6215{
6216 struct intel_framebuffer *intel_fb;
6217 int ret;
6218
6219 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6220 if (!intel_fb) {
6221 drm_gem_object_unreference_unlocked(&obj->base);
6222 return ERR_PTR(-ENOMEM);
6223 }
6224
6225 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6226 if (ret) {
6227 drm_gem_object_unreference_unlocked(&obj->base);
6228 kfree(intel_fb);
6229 return ERR_PTR(ret);
6230 }
6231
6232 return &intel_fb->base;
6233}
6234
6235static u32
6236intel_framebuffer_pitch_for_width(int width, int bpp)
6237{
6238 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6239 return ALIGN(pitch, 64);
6240}
6241
6242static u32
6243intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6244{
6245 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6246 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6247}
6248
6249static struct drm_framebuffer *
6250intel_framebuffer_create_for_mode(struct drm_device *dev,
6251 struct drm_display_mode *mode,
6252 int depth, int bpp)
6253{
6254 struct drm_i915_gem_object *obj;
6255 struct drm_mode_fb_cmd mode_cmd;
6256
6257 obj = i915_gem_alloc_object(dev,
6258 intel_framebuffer_size_for_mode(mode, bpp));
6259 if (obj == NULL)
6260 return ERR_PTR(-ENOMEM);
6261
6262 mode_cmd.width = mode->hdisplay;
6263 mode_cmd.height = mode->vdisplay;
6264 mode_cmd.depth = depth;
6265 mode_cmd.bpp = bpp;
6266 mode_cmd.pitch = intel_framebuffer_pitch_for_width(mode_cmd.width, bpp);
6267
6268 return intel_framebuffer_create(dev, &mode_cmd, obj);
6269}
6270
6271static struct drm_framebuffer *
6272mode_fits_in_fbdev(struct drm_device *dev,
6273 struct drm_display_mode *mode)
6274{
6275 struct drm_i915_private *dev_priv = dev->dev_private;
6276 struct drm_i915_gem_object *obj;
6277 struct drm_framebuffer *fb;
6278
6279 if (dev_priv->fbdev == NULL)
6280 return NULL;
6281
6282 obj = dev_priv->fbdev->ifb.obj;
6283 if (obj == NULL)
6284 return NULL;
6285
6286 fb = &dev_priv->fbdev->ifb.base;
6287 if (fb->pitch < intel_framebuffer_pitch_for_width(mode->hdisplay,
6288 fb->bits_per_pixel))
6289 return NULL;
6290
6291 if (obj->base.size < mode->vdisplay * fb->pitch)
6292 return NULL;
6293
6294 return fb;
6295}
6296
7173188d
CW		 6297bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
6298 struct drm_connector *connector,
6299 struct drm_display_mode *mode,
8261b191 6300 struct intel_load_detect_pipe *old)
79e53945
JB		 6301{
6302 struct intel_crtc *intel_crtc;
6303 struct drm_crtc *possible_crtc;
4ef69c7a 6304 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6305 struct drm_crtc *crtc = NULL;
6306 struct drm_device *dev = encoder->dev;
d2dff872 6307 struct drm_framebuffer *old_fb;
79e53945
JB		 6308 int i = -1;
6309
d2dff872
CW		 6310 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6311 connector->base.id, drm_get_connector_name(connector),
6312 encoder->base.id, drm_get_encoder_name(encoder));
6313
79e53945
JB		 6314 /*
6315 * Algorithm gets a little messy:
7a5e4805 6316 *
79e53945
JB		 6317 * - if the connector already has an assigned crtc, use it (but make
6318 * sure it's on first)
7a5e4805 6319 *
79e53945
JB		 6320 * - try to find the first unused crtc that can drive this connector,
6321 * and use that if we find one
79e53945
JB		 6322 */
6323
6324 /* See if we already have a CRTC for this connector */
6325 if (encoder->crtc) {
6326 crtc = encoder->crtc;
8261b191 6327
79e53945 6328 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 6329 old->dpms_mode = intel_crtc->dpms_mode;
6330 old->load_detect_temp = false;
6331
6332 /* Make sure the crtc and connector are running */
79e53945 6333 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6492711d
CW		 6334 struct drm_encoder_helper_funcs *encoder_funcs;
6335 struct drm_crtc_helper_funcs *crtc_funcs;
6336
79e53945
JB		 6337 crtc_funcs = crtc->helper_private;
6338 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6492711d
CW		 6339
6340 encoder_funcs = encoder->helper_private;
79e53945
JB		 6341 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
6342 }
8261b191 6343
7173188d 6344 return true;
79e53945
JB		 6345 }
6346
6347 /* Find an unused one (if possible) */
6348 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6349 i++;
6350 if (!(encoder->possible_crtcs & (1 << i)))
6351 continue;
6352 if (!possible_crtc->enabled) {
6353 crtc = possible_crtc;
6354 break;
6355 }
79e53945
JB		 6356 }
6357
6358 /*
6359 * If we didn't find an unused CRTC, don't use any.
6360 */
6361 if (!crtc) {
7173188d
CW		 6362 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6363 return false;
79e53945
JB		 6364 }
6365
6366 encoder->crtc = crtc;
c1c43977 6367 connector->encoder = encoder;
79e53945
JB		 6368
6369 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 6370 old->dpms_mode = intel_crtc->dpms_mode;
6371 old->load_detect_temp = true;
d2dff872 6372 old->release_fb = NULL;
79e53945 6373
6492711d
CW		 6374 if (!mode)
6375 mode = &load_detect_mode;
79e53945 6376
d2dff872
CW		 6377 old_fb = crtc->fb;
6378
6379 /* We need a framebuffer large enough to accommodate all accesses
6380 * that the plane may generate whilst we perform load detection.
6381 * We can not rely on the fbcon either being present (we get called
6382 * during its initialisation to detect all boot displays, or it may
6383 * not even exist) or that it is large enough to satisfy the
6384 * requested mode.
6385 */
6386 crtc->fb = mode_fits_in_fbdev(dev, mode);
6387 if (crtc->fb == NULL) {
6388 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6389 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6390 old->release_fb = crtc->fb;
6391 } else
6392 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6393 if (IS_ERR(crtc->fb)) {
6394 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6395 crtc->fb = old_fb;
6396 return false;
79e53945 6397 }
79e53945 6398
d2dff872 6399 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6492711d 6400 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6401 if (old->release_fb)
6402 old->release_fb->funcs->destroy(old->release_fb);
6403 crtc->fb = old_fb;
6492711d 6404 return false;
79e53945 6405 }
7173188d 6406
79e53945 6407 /* let the connector get through one full cycle before testing */
9d0498a2 6408 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 6409
7173188d 6410 return true;
79e53945
JB		 6411}
6412
c1c43977 6413void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
8261b191
CW		 6414 struct drm_connector *connector,
6415 struct intel_load_detect_pipe *old)
79e53945 6416{
4ef69c7a 6417 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6418 struct drm_device *dev = encoder->dev;
6419 struct drm_crtc *crtc = encoder->crtc;
6420 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
6421 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
6422
d2dff872
CW		 6423 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6424 connector->base.id, drm_get_connector_name(connector),
6425 encoder->base.id, drm_get_encoder_name(encoder));
6426
8261b191 6427 if (old->load_detect_temp) {
c1c43977 6428 connector->encoder = NULL;
79e53945 6429 drm_helper_disable_unused_functions(dev);
d2dff872
CW		 6430
6431 if (old->release_fb)
6432 old->release_fb->funcs->destroy(old->release_fb);
6433
0622a53c 6434 return;
79e53945
JB		 6435 }
6436
c751ce4f 6437 /* Switch crtc and encoder back off if necessary */
0622a53c
CW		 6438 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
6439 encoder_funcs->dpms(encoder, old->dpms_mode);
8261b191 6440 crtc_funcs->dpms(crtc, old->dpms_mode);
79e53945
JB		 6441 }
6442}
6443
6444/* Returns the clock of the currently programmed mode of the given pipe. */
6445static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6446{
6447 struct drm_i915_private *dev_priv = dev->dev_private;
6448 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6449 int pipe = intel_crtc->pipe;
548f245b 6450 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6451 u32 fp;
6452 intel_clock_t clock;
6453
6454 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6455 fp = I915_READ(FP0(pipe));
79e53945 6456 else
39adb7a5 6457 fp = I915_READ(FP1(pipe));
79e53945
JB		 6458
6459 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6460 if (IS_PINEVIEW(dev)) {
6461 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6462 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6463 } else {
6464 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6465 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6466 }
6467
a6c45cf0 6468 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6469 if (IS_PINEVIEW(dev))
6470 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6471 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6472 else
6473 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6474 DPLL_FPA01_P1_POST_DIV_SHIFT);
6475
6476 switch (dpll & DPLL_MODE_MASK) {
6477 case DPLLB_MODE_DAC_SERIAL:
6478 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6479 5 : 10;
6480 break;
6481 case DPLLB_MODE_LVDS:
6482 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6483 7 : 14;
6484 break;
6485 default:
28c97730 6486 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6487 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6488 return 0;
6489 }
6490
6491 /* XXX: Handle the 100Mhz refclk */
2177832f 6492 intel_clock(dev, 96000, &clock);
79e53945
JB		 6493 } else {
6494 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6495
6496 if (is_lvds) {
6497 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6498 DPLL_FPA01_P1_POST_DIV_SHIFT);
6499 clock.p2 = 14;
6500
6501 if ((dpll & PLL_REF_INPUT_MASK) ==
6502 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6503 /* XXX: might not be 66MHz */
2177832f 6504 intel_clock(dev, 66000, &clock);
79e53945 6505 } else
2177832f 6506 intel_clock(dev, 48000, &clock);
79e53945
JB		 6507 } else {
6508 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6509 clock.p1 = 2;
6510 else {
6511 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6512 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6513 }
6514 if (dpll & PLL_P2_DIVIDE_BY_4)
6515 clock.p2 = 4;
6516 else
6517 clock.p2 = 2;
6518
2177832f 6519 intel_clock(dev, 48000, &clock);
79e53945
JB		 6520 }
6521 }
6522
6523 /* XXX: It would be nice to validate the clocks, but we can't reuse
6524 * i830PllIsValid() because it relies on the xf86_config connector
6525 * configuration being accurate, which it isn't necessarily.
6526 */
6527
6528 return clock.dot;
6529}
6530
6531/** Returns the currently programmed mode of the given pipe. */
6532struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6533 struct drm_crtc *crtc)
6534{
548f245b 6535 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 6536 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6537 int pipe = intel_crtc->pipe;
6538 struct drm_display_mode *mode;
548f245b
JB		 6539 int htot = I915_READ(HTOTAL(pipe));
6540 int hsync = I915_READ(HSYNC(pipe));
6541 int vtot = I915_READ(VTOTAL(pipe));
6542 int vsync = I915_READ(VSYNC(pipe));
79e53945
JB		 6543
6544 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6545 if (!mode)
6546 return NULL;
6547
6548 mode->clock = intel_crtc_clock_get(dev, crtc);
6549 mode->hdisplay = (htot & 0xffff) + 1;
6550 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6551 mode->hsync_start = (hsync & 0xffff) + 1;
6552 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6553 mode->vdisplay = (vtot & 0xffff) + 1;
6554 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6555 mode->vsync_start = (vsync & 0xffff) + 1;
6556 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6557
6558 drm_mode_set_name(mode);
6559 drm_mode_set_crtcinfo(mode, 0);
6560
6561 return mode;
6562}
6563
652c393a
JB		 6564#define GPU_IDLE_TIMEOUT 500 /* ms */
6565
6566/* When this timer fires, we've been idle for awhile */
6567static void intel_gpu_idle_timer(unsigned long arg)
6568{
6569 struct drm_device *dev = (struct drm_device *)arg;
6570 drm_i915_private_t *dev_priv = dev->dev_private;
6571
ff7ea4c0
CW		 6572 if (!list_empty(&dev_priv->mm.active_list)) {
6573 /* Still processing requests, so just re-arm the timer. */
6574 mod_timer(&dev_priv->idle_timer, jiffies +
6575 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6576 return;
6577 }
652c393a 6578
ff7ea4c0 6579 dev_priv->busy = false;
01dfba93 6580 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 6581}
6582
652c393a
JB		 6583#define CRTC_IDLE_TIMEOUT 1000 /* ms */
6584
6585static void intel_crtc_idle_timer(unsigned long arg)
6586{
6587 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
6588 struct drm_crtc *crtc = &intel_crtc->base;
6589 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
ff7ea4c0 6590 struct intel_framebuffer *intel_fb;
652c393a 6591
ff7ea4c0
CW		 6592 intel_fb = to_intel_framebuffer(crtc->fb);
6593 if (intel_fb && intel_fb->obj->active) {
6594 /* The framebuffer is still being accessed by the GPU. */
6595 mod_timer(&intel_crtc->idle_timer, jiffies +
6596 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6597 return;
6598 }
652c393a 6599
ff7ea4c0 6600 intel_crtc->busy = false;
01dfba93 6601 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 6602}
6603
3dec0095 6604static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6605{
6606 struct drm_device *dev = crtc->dev;
6607 drm_i915_private_t *dev_priv = dev->dev_private;
6608 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6609 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6610 int dpll_reg = DPLL(pipe);
6611 int dpll;
652c393a 6612
bad720ff 6613 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6614 return;
6615
6616 if (!dev_priv->lvds_downclock_avail)
6617 return;
6618
dbdc6479 6619 dpll = I915_READ(dpll_reg);
652c393a 6620 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6621 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a
JB		 6622
6623 /* Unlock panel regs */
dbdc6479
JB		 6624 I915_WRITE(PP_CONTROL,
6625 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
652c393a
JB		 6626
6627 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6628 I915_WRITE(dpll_reg, dpll);
9d0498a2 6629 intel_wait_for_vblank(dev, pipe);
dbdc6479 6630
652c393a
JB		 6631 dpll = I915_READ(dpll_reg);
6632 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6633 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a
JB		 6634
6635 /* ...and lock them again */
6636 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6637 }
6638
6639 /* Schedule downclock */
3dec0095
DV		 6640 mod_timer(&intel_crtc->idle_timer, jiffies +
6641 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
652c393a
JB		 6642}
6643
6644static void intel_decrease_pllclock(struct drm_crtc *crtc)
6645{
6646 struct drm_device *dev = crtc->dev;
6647 drm_i915_private_t *dev_priv = dev->dev_private;
6648 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6649 int pipe = intel_crtc->pipe;
9db4a9c7 6650 int dpll_reg = DPLL(pipe);
652c393a
JB		 6651 int dpll = I915_READ(dpll_reg);
6652
bad720ff 6653 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6654 return;
6655
6656 if (!dev_priv->lvds_downclock_avail)
6657 return;
6658
6659 /*
6660 * Since this is called by a timer, we should never get here in
6661 * the manual case.
6662 */
6663 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
44d98a61 6664 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a
JB		 6665
6666 /* Unlock panel regs */
4a655f04
JB		 6667 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
6668 PANEL_UNLOCK_REGS);
652c393a
JB		 6669
6670 dpll |= DISPLAY_RATE_SELECT_FPA1;
6671 I915_WRITE(dpll_reg, dpll);
9d0498a2 6672 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 6673 dpll = I915_READ(dpll_reg);
6674 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 6675 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 6676
6677 /* ...and lock them again */
6678 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6679 }
6680
6681}
6682
6683/**
6684 * intel_idle_update - adjust clocks for idleness
6685 * @work: work struct
6686 *
6687 * Either the GPU or display (or both) went idle. Check the busy status
6688 * here and adjust the CRTC and GPU clocks as necessary.
6689 */
6690static void intel_idle_update(struct work_struct *work)
6691{
6692 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
6693 idle_work);
6694 struct drm_device *dev = dev_priv->dev;
6695 struct drm_crtc *crtc;
6696 struct intel_crtc *intel_crtc;
6697
6698 if (!i915_powersave)
6699 return;
6700
6701 mutex_lock(&dev->struct_mutex);
6702
7648fa99
JB		 6703 i915_update_gfx_val(dev_priv);
6704
652c393a
JB		 6705 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6706 /* Skip inactive CRTCs */
6707 if (!crtc->fb)
6708 continue;
6709
6710 intel_crtc = to_intel_crtc(crtc);
6711 if (!intel_crtc->busy)
6712 intel_decrease_pllclock(crtc);
6713 }
6714
45ac22c8 6715
652c393a
JB		 6716 mutex_unlock(&dev->struct_mutex);
6717}
6718
6719/**
6720 * intel_mark_busy - mark the GPU and possibly the display busy
6721 * @dev: drm device
6722 * @obj: object we're operating on
6723 *
6724 * Callers can use this function to indicate that the GPU is busy processing
6725 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
6726 * buffer), we'll also mark the display as busy, so we know to increase its
6727 * clock frequency.
6728 */
05394f39 6729void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
652c393a
JB		 6730{
6731 drm_i915_private_t *dev_priv = dev->dev_private;
6732 struct drm_crtc *crtc = NULL;
6733 struct intel_framebuffer *intel_fb;
6734 struct intel_crtc *intel_crtc;
6735
5e17ee74
ZW		 6736 if (!drm_core_check_feature(dev, DRIVER_MODESET))
6737 return;
6738
18b2190c 6739 if (!dev_priv->busy)
28cf798f 6740 dev_priv->busy = true;
18b2190c 6741 else
28cf798f
CW		 6742 mod_timer(&dev_priv->idle_timer, jiffies +
6743 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
652c393a
JB		 6744
6745 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6746 if (!crtc->fb)
6747 continue;
6748
6749 intel_crtc = to_intel_crtc(crtc);
6750 intel_fb = to_intel_framebuffer(crtc->fb);
6751 if (intel_fb->obj == obj) {
6752 if (!intel_crtc->busy) {
6753 /* Non-busy -> busy, upclock */
3dec0095 6754 intel_increase_pllclock(crtc);
652c393a
JB		 6755 intel_crtc->busy = true;
6756 } else {
6757 /* Busy -> busy, put off timer */
6758 mod_timer(&intel_crtc->idle_timer, jiffies +
6759 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6760 }
6761 }
6762 }
6763}
6764
79e53945
JB		 6765static void intel_crtc_destroy(struct drm_crtc *crtc)
6766{
6767 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6768 struct drm_device *dev = crtc->dev;
6769 struct intel_unpin_work *work;
6770 unsigned long flags;
6771
6772 spin_lock_irqsave(&dev->event_lock, flags);
6773 work = intel_crtc->unpin_work;
6774 intel_crtc->unpin_work = NULL;
6775 spin_unlock_irqrestore(&dev->event_lock, flags);
6776
6777 if (work) {
6778 cancel_work_sync(&work->work);
6779 kfree(work);
6780 }
79e53945
JB		 6781
6782 drm_crtc_cleanup(crtc);
67e77c5a 6783
79e53945
JB		 6784 kfree(intel_crtc);
6785}
6786
6b95a207
KH		 6787static void intel_unpin_work_fn(struct work_struct *__work)
6788{
6789 struct intel_unpin_work *work =
6790 container_of(__work, struct intel_unpin_work, work);
6791
6792 mutex_lock(&work->dev->struct_mutex);
b1b87f6b 6793 i915_gem_object_unpin(work->old_fb_obj);
05394f39
CW		 6794 drm_gem_object_unreference(&work->pending_flip_obj->base);
6795 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 6796
7782de3b 6797 intel_update_fbc(work->dev);
6b95a207
KH		 6798 mutex_unlock(&work->dev->struct_mutex);
6799 kfree(work);
6800}
6801
1afe3e9d 6802static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 6803 struct drm_crtc *crtc)
6b95a207
KH		 6804{
6805 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 6806 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6807 struct intel_unpin_work *work;
05394f39 6808 struct drm_i915_gem_object *obj;
6b95a207 6809 struct drm_pending_vblank_event *e;
49b14a5c 6810 struct timeval tnow, tvbl;
6b95a207
KH		 6811 unsigned long flags;
6812
6813 /* Ignore early vblank irqs */
6814 if (intel_crtc == NULL)
6815 return;
6816
49b14a5c
MK		 6817 do_gettimeofday(&tnow);
6818
6b95a207
KH		 6819 spin_lock_irqsave(&dev->event_lock, flags);
6820 work = intel_crtc->unpin_work;
6821 if (work == NULL || !work->pending) {
6822 spin_unlock_irqrestore(&dev->event_lock, flags);
6823 return;
6824 }
6825
6826 intel_crtc->unpin_work = NULL;
6b95a207
KH		 6827
6828 if (work->event) {
6829 e = work->event;
49b14a5c 6830 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
0af7e4df
MK		 6831
6832 /* Called before vblank count and timestamps have
6833 * been updated for the vblank interval of flip
6834 * completion? Need to increment vblank count and
6835 * add one videorefresh duration to returned timestamp
49b14a5c
MK		 6836 * to account for this. We assume this happened if we
6837 * get called over 0.9 frame durations after the last
6838 * timestamped vblank.
6839 *
6840 * This calculation can not be used with vrefresh rates
6841 * below 5Hz (10Hz to be on the safe side) without
6842 * promoting to 64 integers.
0af7e4df 6843 */
49b14a5c
MK		 6844 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6845 9 * crtc->framedur_ns) {
0af7e4df 6846 e->event.sequence++;
49b14a5c
MK		 6847 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6848 crtc->framedur_ns);
0af7e4df
MK		 6849 }
6850
49b14a5c
MK		 6851 e->event.tv_sec = tvbl.tv_sec;
6852 e->event.tv_usec = tvbl.tv_usec;
0af7e4df 6853
6b95a207
KH		 6854 list_add_tail(&e->base.link,
6855 &e->base.file_priv->event_list);
6856 wake_up_interruptible(&e->base.file_priv->event_wait);
6857 }
6858
0af7e4df
MK		 6859 drm_vblank_put(dev, intel_crtc->pipe);
6860
6b95a207
KH		 6861 spin_unlock_irqrestore(&dev->event_lock, flags);
6862
05394f39 6863 obj = work->old_fb_obj;
d9e86c0e 6864
e59f2bac 6865 atomic_clear_mask(1 << intel_crtc->plane,
05394f39
CW		 6866 &obj->pending_flip.counter);
6867 if (atomic_read(&obj->pending_flip) == 0)
f787a5f5 6868 wake_up(&dev_priv->pending_flip_queue);
d9e86c0e 6869
6b95a207 6870 schedule_work(&work->work);
e5510fac
JB		 6871
6872 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 6873}
6874
1afe3e9d
JB		 6875void intel_finish_page_flip(struct drm_device *dev, int pipe)
6876{
6877 drm_i915_private_t *dev_priv = dev->dev_private;
6878 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6879
49b14a5c 6880 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6881}
6882
6883void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6884{
6885 drm_i915_private_t *dev_priv = dev->dev_private;
6886 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6887
49b14a5c 6888 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6889}
6890
6b95a207
KH		 6891void intel_prepare_page_flip(struct drm_device *dev, int plane)
6892{
6893 drm_i915_private_t *dev_priv = dev->dev_private;
6894 struct intel_crtc *intel_crtc =
6895 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6896 unsigned long flags;
6897
6898 spin_lock_irqsave(&dev->event_lock, flags);
de3f440f 6899 if (intel_crtc->unpin_work) {
4e5359cd
SF		 6900 if ((++intel_crtc->unpin_work->pending) > 1)
6901 DRM_ERROR("Prepared flip multiple times\n");
de3f440f
JB		 6902 } else {
6903 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6904 }
6b95a207
KH		 6905 spin_unlock_irqrestore(&dev->event_lock, flags);
6906}
6907
8c9f3aaf
JB		 6908static int intel_gen2_queue_flip(struct drm_device *dev,
6909 struct drm_crtc *crtc,
6910 struct drm_framebuffer *fb,
6911 struct drm_i915_gem_object *obj)
6912{
6913 struct drm_i915_private *dev_priv = dev->dev_private;
6914 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6915 unsigned long offset;
6916 u32 flip_mask;
6917 int ret;
6918
6919 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6920 if (ret)
6921 goto out;
6922
6923 /* Offset into the new buffer for cases of shared fbs between CRTCs */
6924 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6925
6926 ret = BEGIN_LP_RING(6);
6927 if (ret)
6928 goto out;
6929
6930 /* Can't queue multiple flips, so wait for the previous
6931 * one to finish before executing the next.
6932 */
6933 if (intel_crtc->plane)
6934 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6935 else
6936 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6937 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6938 OUT_RING(MI_NOOP);
6939 OUT_RING(MI_DISPLAY_FLIP |
6940 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6941 OUT_RING(fb->pitch);
6942 OUT_RING(obj->gtt_offset + offset);
6943 OUT_RING(MI_NOOP);
6944 ADVANCE_LP_RING();
6945out:
6946 return ret;
6947}
6948
6949static int intel_gen3_queue_flip(struct drm_device *dev,
6950 struct drm_crtc *crtc,
6951 struct drm_framebuffer *fb,
6952 struct drm_i915_gem_object *obj)
6953{
6954 struct drm_i915_private *dev_priv = dev->dev_private;
6955 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6956 unsigned long offset;
6957 u32 flip_mask;
6958 int ret;
6959
6960 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6961 if (ret)
6962 goto out;
6963
6964 /* Offset into the new buffer for cases of shared fbs between CRTCs */
6965 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6966
6967 ret = BEGIN_LP_RING(6);
6968 if (ret)
6969 goto out;
6970
6971 if (intel_crtc->plane)
6972 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6973 else
6974 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6975 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6976 OUT_RING(MI_NOOP);
6977 OUT_RING(MI_DISPLAY_FLIP_I915 |
6978 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6979 OUT_RING(fb->pitch);
6980 OUT_RING(obj->gtt_offset + offset);
6981 OUT_RING(MI_NOOP);
6982
6983 ADVANCE_LP_RING();
6984out:
6985 return ret;
6986}
6987
6988static int intel_gen4_queue_flip(struct drm_device *dev,
6989 struct drm_crtc *crtc,
6990 struct drm_framebuffer *fb,
6991 struct drm_i915_gem_object *obj)
6992{
6993 struct drm_i915_private *dev_priv = dev->dev_private;
6994 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6995 uint32_t pf, pipesrc;
6996 int ret;
6997
6998 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6999 if (ret)
7000 goto out;
7001
7002 ret = BEGIN_LP_RING(4);
7003 if (ret)
7004 goto out;
7005
7006 /* i965+ uses the linear or tiled offsets from the
7007 * Display Registers (which do not change across a page-flip)
7008 * so we need only reprogram the base address.
7009 */
7010 OUT_RING(MI_DISPLAY_FLIP |
7011 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7012 OUT_RING(fb->pitch);
7013 OUT_RING(obj->gtt_offset | obj->tiling_mode);
7014
7015 /* XXX Enabling the panel-fitter across page-flip is so far
7016 * untested on non-native modes, so ignore it for now.
7017 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7018 */
7019 pf = 0;
7020 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7021 OUT_RING(pf | pipesrc);
7022 ADVANCE_LP_RING();
7023out:
7024 return ret;
7025}
7026
7027static int intel_gen6_queue_flip(struct drm_device *dev,
7028 struct drm_crtc *crtc,
7029 struct drm_framebuffer *fb,
7030 struct drm_i915_gem_object *obj)
7031{
7032 struct drm_i915_private *dev_priv = dev->dev_private;
7033 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7034 uint32_t pf, pipesrc;
7035 int ret;
7036
7037 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7038 if (ret)
7039 goto out;
7040
7041 ret = BEGIN_LP_RING(4);
7042 if (ret)
7043 goto out;
7044
7045 OUT_RING(MI_DISPLAY_FLIP |
7046 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7047 OUT_RING(fb->pitch | obj->tiling_mode);
7048 OUT_RING(obj->gtt_offset);
7049
7050 pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7051 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7052 OUT_RING(pf | pipesrc);
7053 ADVANCE_LP_RING();
7054out:
7055 return ret;
7056}
7057
7c9017e5
JB		 7058/*
7059 * On gen7 we currently use the blit ring because (in early silicon at least)
7060 * the render ring doesn't give us interrpts for page flip completion, which
7061 * means clients will hang after the first flip is queued. Fortunately the
7062 * blit ring generates interrupts properly, so use it instead.
7063 */
7064static int intel_gen7_queue_flip(struct drm_device *dev,
7065 struct drm_crtc *crtc,
7066 struct drm_framebuffer *fb,
7067 struct drm_i915_gem_object *obj)
7068{
7069 struct drm_i915_private *dev_priv = dev->dev_private;
7070 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7071 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7072 int ret;
7073
7074 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7075 if (ret)
7076 goto out;
7077
7078 ret = intel_ring_begin(ring, 4);
7079 if (ret)
7080 goto out;
7081
7082 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
7083 intel_ring_emit(ring, (fb->pitch | obj->tiling_mode));
7084 intel_ring_emit(ring, (obj->gtt_offset));
7085 intel_ring_emit(ring, (MI_NOOP));
7086 intel_ring_advance(ring);
7087out:
7088 return ret;
7089}
7090
8c9f3aaf
JB		 7091static int intel_default_queue_flip(struct drm_device *dev,
7092 struct drm_crtc *crtc,
7093 struct drm_framebuffer *fb,
7094 struct drm_i915_gem_object *obj)
7095{
7096 return -ENODEV;
7097}
7098
6b95a207
KH		 7099static int intel_crtc_page_flip(struct drm_crtc *crtc,
7100 struct drm_framebuffer *fb,
7101 struct drm_pending_vblank_event *event)
7102{
7103 struct drm_device *dev = crtc->dev;
7104 struct drm_i915_private *dev_priv = dev->dev_private;
7105 struct intel_framebuffer *intel_fb;
05394f39 7106 struct drm_i915_gem_object *obj;
6b95a207
KH		 7107 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7108 struct intel_unpin_work *work;
8c9f3aaf 7109 unsigned long flags;
52e68630 7110 int ret;
6b95a207
KH		 7111
7112 work = kzalloc(sizeof *work, GFP_KERNEL);
7113 if (work == NULL)
7114 return -ENOMEM;
7115
6b95a207
KH		 7116 work->event = event;
7117 work->dev = crtc->dev;
7118 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 7119 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 7120 INIT_WORK(&work->work, intel_unpin_work_fn);
7121
7122 /* We borrow the event spin lock for protecting unpin_work */
7123 spin_lock_irqsave(&dev->event_lock, flags);
7124 if (intel_crtc->unpin_work) {
7125 spin_unlock_irqrestore(&dev->event_lock, flags);
7126 kfree(work);
468f0b44
CW		 7127
7128 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7129 return -EBUSY;
7130 }
7131 intel_crtc->unpin_work = work;
7132 spin_unlock_irqrestore(&dev->event_lock, flags);
7133
7134 intel_fb = to_intel_framebuffer(fb);
7135 obj = intel_fb->obj;
7136
468f0b44 7137 mutex_lock(&dev->struct_mutex);
6b95a207 7138
75dfca80 7139 /* Reference the objects for the scheduled work. */
05394f39
CW		 7140 drm_gem_object_reference(&work->old_fb_obj->base);
7141 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7142
7143 crtc->fb = fb;
96b099fd
CW		 7144
7145 ret = drm_vblank_get(dev, intel_crtc->pipe);
7146 if (ret)
7147 goto cleanup_objs;
7148
e1f99ce6 7149 work->pending_flip_obj = obj;
e1f99ce6 7150
4e5359cd
SF		 7151 work->enable_stall_check = true;
7152
e1f99ce6
CW		 7153 /* Block clients from rendering to the new back buffer until
7154 * the flip occurs and the object is no longer visible.
7155 */
05394f39 7156 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
e1f99ce6 7157
8c9f3aaf
JB		 7158 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7159 if (ret)
7160 goto cleanup_pending;
6b95a207 7161
7782de3b 7162 intel_disable_fbc(dev);
6b95a207
KH		 7163 mutex_unlock(&dev->struct_mutex);
7164
e5510fac
JB		 7165 trace_i915_flip_request(intel_crtc->plane, obj);
7166
6b95a207 7167 return 0;
96b099fd 7168
8c9f3aaf
JB		 7169cleanup_pending:
7170 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
96b099fd 7171cleanup_objs:
05394f39
CW		 7172 drm_gem_object_unreference(&work->old_fb_obj->base);
7173 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7174 mutex_unlock(&dev->struct_mutex);
7175
7176 spin_lock_irqsave(&dev->event_lock, flags);
7177 intel_crtc->unpin_work = NULL;
7178 spin_unlock_irqrestore(&dev->event_lock, flags);
7179
7180 kfree(work);
7181
7182 return ret;
6b95a207
KH		 7183}
7184
47f1c6c9
CW		 7185static void intel_sanitize_modesetting(struct drm_device *dev,
7186 int pipe, int plane)
7187{
7188 struct drm_i915_private *dev_priv = dev->dev_private;
7189 u32 reg, val;
7190
7191 if (HAS_PCH_SPLIT(dev))
7192 return;
7193
7194 /* Who knows what state these registers were left in by the BIOS or
7195 * grub?
7196 *
7197 * If we leave the registers in a conflicting state (e.g. with the
7198 * display plane reading from the other pipe than the one we intend
7199 * to use) then when we attempt to teardown the active mode, we will
7200 * not disable the pipes and planes in the correct order -- leaving
7201 * a plane reading from a disabled pipe and possibly leading to
7202 * undefined behaviour.
7203 */
7204
7205 reg = DSPCNTR(plane);
7206 val = I915_READ(reg);
7207
7208 if ((val & DISPLAY_PLANE_ENABLE) == 0)
7209 return;
7210 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
7211 return;
7212
7213 /* This display plane is active and attached to the other CPU pipe. */
7214 pipe = !pipe;
7215
7216 /* Disable the plane and wait for it to stop reading from the pipe. */
b24e7179
JB		 7217 intel_disable_plane(dev_priv, plane, pipe);
7218 intel_disable_pipe(dev_priv, pipe);
47f1c6c9 7219}
79e53945 7220
f6e5b160
CW		 7221static void intel_crtc_reset(struct drm_crtc *crtc)
7222{
7223 struct drm_device *dev = crtc->dev;
7224 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7225
7226 /* Reset flags back to the 'unknown' status so that they
7227 * will be correctly set on the initial modeset.
7228 */
7229 intel_crtc->dpms_mode = -1;
7230
7231 /* We need to fix up any BIOS configuration that conflicts with
7232 * our expectations.
7233 */
7234 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
7235}
7236
7237static struct drm_crtc_helper_funcs intel_helper_funcs = {
7238 .dpms = intel_crtc_dpms,
7239 .mode_fixup = intel_crtc_mode_fixup,
7240 .mode_set = intel_crtc_mode_set,
7241 .mode_set_base = intel_pipe_set_base,
7242 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7243 .load_lut = intel_crtc_load_lut,
7244 .disable = intel_crtc_disable,
7245};
7246
7247static const struct drm_crtc_funcs intel_crtc_funcs = {
7248 .reset = intel_crtc_reset,
7249 .cursor_set = intel_crtc_cursor_set,
7250 .cursor_move = intel_crtc_cursor_move,
7251 .gamma_set = intel_crtc_gamma_set,
7252 .set_config = drm_crtc_helper_set_config,
7253 .destroy = intel_crtc_destroy,
7254 .page_flip = intel_crtc_page_flip,
7255};
7256
b358d0a6 7257static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 7258{
22fd0fab 7259 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 7260 struct intel_crtc *intel_crtc;
7261 int i;
7262
7263 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7264 if (intel_crtc == NULL)
7265 return;
7266
7267 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7268
7269 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 7270 for (i = 0; i < 256; i++) {
7271 intel_crtc->lut_r[i] = i;
7272 intel_crtc->lut_g[i] = i;
7273 intel_crtc->lut_b[i] = i;
7274 }
7275
80824003
JB		 7276 /* Swap pipes & planes for FBC on pre-965 */
7277 intel_crtc->pipe = pipe;
7278 intel_crtc->plane = pipe;
e2e767ab 7279 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 7280 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 7281 intel_crtc->plane = !pipe;
80824003
JB		 7282 }
7283
22fd0fab
JB		 7284 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7285 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7286 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7287 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7288
5d1d0cc8 7289 intel_crtc_reset(&intel_crtc->base);
04dbff52 7290 intel_crtc->active = true; /* force the pipe off on setup_init_config */
5a354204 7291 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3
JB		 7292
7293 if (HAS_PCH_SPLIT(dev)) {
7294 intel_helper_funcs.prepare = ironlake_crtc_prepare;
7295 intel_helper_funcs.commit = ironlake_crtc_commit;
7296 } else {
7297 intel_helper_funcs.prepare = i9xx_crtc_prepare;
7298 intel_helper_funcs.commit = i9xx_crtc_commit;
7299 }
7300
79e53945
JB		 7301 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7302
652c393a
JB		 7303 intel_crtc->busy = false;
7304
7305 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
7306 (unsigned long)intel_crtc);
79e53945
JB		 7307}
7308
08d7b3d1 7309int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 7310 struct drm_file *file)
08d7b3d1
CW		 7311{
7312 drm_i915_private_t *dev_priv = dev->dev_private;
7313 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 7314 struct drm_mode_object *drmmode_obj;
7315 struct intel_crtc *crtc;
08d7b3d1
CW		 7316
7317 if (!dev_priv) {
7318 DRM_ERROR("called with no initialization\n");
7319 return -EINVAL;
7320 }
7321
c05422d5
DV		 7322 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7323 DRM_MODE_OBJECT_CRTC);
08d7b3d1 7324
c05422d5 7325 if (!drmmode_obj) {
08d7b3d1
CW		 7326 DRM_ERROR("no such CRTC id\n");
7327 return -EINVAL;
7328 }
7329
c05422d5
DV		 7330 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7331 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 7332
c05422d5 7333 return 0;
08d7b3d1
CW		 7334}
7335
c5e4df33 7336static int intel_encoder_clones(struct drm_device *dev, int type_mask)
79e53945 7337{
4ef69c7a 7338 struct intel_encoder *encoder;
79e53945 7339 int index_mask = 0;
79e53945
JB		 7340 int entry = 0;
7341
4ef69c7a
CW		 7342 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7343 if (type_mask & encoder->clone_mask)
79e53945
JB		 7344 index_mask |= (1 << entry);
7345 entry++;
7346 }
4ef69c7a 7347
79e53945
JB		 7348 return index_mask;
7349}
7350
4d302442
CW		 7351static bool has_edp_a(struct drm_device *dev)
7352{
7353 struct drm_i915_private *dev_priv = dev->dev_private;
7354
7355 if (!IS_MOBILE(dev))
7356 return false;
7357
7358 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7359 return false;
7360
7361 if (IS_GEN5(dev) &&
7362 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7363 return false;
7364
7365 return true;
7366}
7367
79e53945
JB		 7368static void intel_setup_outputs(struct drm_device *dev)
7369{
725e30ad 7370 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 7371 struct intel_encoder *encoder;
cb0953d7 7372 bool dpd_is_edp = false;
c5d1b51d 7373 bool has_lvds = false;
79e53945 7374
541998a1 7375 if (IS_MOBILE(dev) && !IS_I830(dev))
c5d1b51d
CW		 7376 has_lvds = intel_lvds_init(dev);
7377 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7378 /* disable the panel fitter on everything but LVDS */
7379 I915_WRITE(PFIT_CONTROL, 0);
7380 }
79e53945 7381
bad720ff 7382 if (HAS_PCH_SPLIT(dev)) {
cb0953d7 7383 dpd_is_edp = intel_dpd_is_edp(dev);
30ad48b7 7384
4d302442 7385 if (has_edp_a(dev))
32f9d658
ZW		 7386 intel_dp_init(dev, DP_A);
7387
cb0953d7
AJ		 7388 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7389 intel_dp_init(dev, PCH_DP_D);
7390 }
7391
7392 intel_crt_init(dev);
7393
7394 if (HAS_PCH_SPLIT(dev)) {
7395 int found;
7396
30ad48b7 7397 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca
ZY		 7398 /* PCH SDVOB multiplex with HDMIB */
7399 found = intel_sdvo_init(dev, PCH_SDVOB);
30ad48b7
ZW		 7400 if (!found)
7401 intel_hdmi_init(dev, HDMIB);
5eb08b69
ZW		 7402 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7403 intel_dp_init(dev, PCH_DP_B);
30ad48b7
ZW		 7404 }
7405
7406 if (I915_READ(HDMIC) & PORT_DETECTED)
7407 intel_hdmi_init(dev, HDMIC);
7408
7409 if (I915_READ(HDMID) & PORT_DETECTED)
7410 intel_hdmi_init(dev, HDMID);
7411
5eb08b69
ZW		 7412 if (I915_READ(PCH_DP_C) & DP_DETECTED)
7413 intel_dp_init(dev, PCH_DP_C);
7414
cb0953d7 7415 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5eb08b69
ZW		 7416 intel_dp_init(dev, PCH_DP_D);
7417
103a196f 7418 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 7419 bool found = false;
7d57382e 7420
725e30ad 7421 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 7422 DRM_DEBUG_KMS("probing SDVOB\n");
725e30ad 7423 found = intel_sdvo_init(dev, SDVOB);
b01f2c3a
JB		 7424 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7425 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
725e30ad 7426 intel_hdmi_init(dev, SDVOB);
b01f2c3a 7427 }
27185ae1 7428
b01f2c3a
JB		 7429 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7430 DRM_DEBUG_KMS("probing DP_B\n");
a4fc5ed6 7431 intel_dp_init(dev, DP_B);
b01f2c3a 7432 }
725e30ad 7433 }
13520b05
KH		 7434
7435 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 7436
b01f2c3a
JB		 7437 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7438 DRM_DEBUG_KMS("probing SDVOC\n");
725e30ad 7439 found = intel_sdvo_init(dev, SDVOC);
b01f2c3a 7440 }
27185ae1
ML		 7441
7442 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7443
b01f2c3a
JB		 7444 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7445 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
725e30ad 7446 intel_hdmi_init(dev, SDVOC);
b01f2c3a
JB		 7447 }
7448 if (SUPPORTS_INTEGRATED_DP(dev)) {
7449 DRM_DEBUG_KMS("probing DP_C\n");
a4fc5ed6 7450 intel_dp_init(dev, DP_C);
b01f2c3a 7451 }
725e30ad 7452 }
27185ae1 7453
b01f2c3a
JB		 7454 if (SUPPORTS_INTEGRATED_DP(dev) &&
7455 (I915_READ(DP_D) & DP_DETECTED)) {
7456 DRM_DEBUG_KMS("probing DP_D\n");
a4fc5ed6 7457 intel_dp_init(dev, DP_D);
b01f2c3a 7458 }
bad720ff 7459 } else if (IS_GEN2(dev))
79e53945
JB		 7460 intel_dvo_init(dev);
7461
103a196f 7462 if (SUPPORTS_TV(dev))
79e53945
JB		 7463 intel_tv_init(dev);
7464
4ef69c7a
CW		 7465 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7466 encoder->base.possible_crtcs = encoder->crtc_mask;
7467 encoder->base.possible_clones =
7468 intel_encoder_clones(dev, encoder->clone_mask);
79e53945 7469 }
47356eb6 7470
2c7111db
CW		 7471 /* disable all the possible outputs/crtcs before entering KMS mode */
7472 drm_helper_disable_unused_functions(dev);
9fb526db
KP		 7473
7474 if (HAS_PCH_SPLIT(dev))
7475 ironlake_init_pch_refclk(dev);
79e53945
JB		 7476}
7477
7478static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7479{
7480 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 7481
7482 drm_framebuffer_cleanup(fb);
05394f39 7483 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 7484
7485 kfree(intel_fb);
7486}
7487
7488static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 7489 struct drm_file *file,
79e53945
JB		 7490 unsigned int *handle)
7491{
7492 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 7493 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 7494
05394f39 7495 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 7496}
7497
7498static const struct drm_framebuffer_funcs intel_fb_funcs = {
7499 .destroy = intel_user_framebuffer_destroy,
7500 .create_handle = intel_user_framebuffer_create_handle,
7501};
7502
38651674
DA		 7503int intel_framebuffer_init(struct drm_device *dev,
7504 struct intel_framebuffer *intel_fb,
7505 struct drm_mode_fb_cmd *mode_cmd,
05394f39 7506 struct drm_i915_gem_object *obj)
79e53945 7507{
79e53945
JB		 7508 int ret;
7509
05394f39 7510 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 7511 return -EINVAL;
7512
7513 if (mode_cmd->pitch & 63)
7514 return -EINVAL;
7515
7516 switch (mode_cmd->bpp) {
7517 case 8:
7518 case 16:
b5626747
JB		 7519 /* Only pre-ILK can handle 5:5:5 */
7520 if (mode_cmd->depth == 15 && !HAS_PCH_SPLIT(dev))
7521 return -EINVAL;
7522 break;
7523
57cd6508
CW		 7524 case 24:
7525 case 32:
7526 break;
7527 default:
7528 return -EINVAL;
7529 }
7530
79e53945
JB		 7531 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7532 if (ret) {
7533 DRM_ERROR("framebuffer init failed %d\n", ret);
7534 return ret;
7535 }
7536
7537 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 7538 intel_fb->obj = obj;
79e53945
JB		 7539 return 0;
7540}
7541
79e53945
JB		 7542static struct drm_framebuffer *
7543intel_user_framebuffer_create(struct drm_device *dev,
7544 struct drm_file *filp,
7545 struct drm_mode_fb_cmd *mode_cmd)
7546{
05394f39 7547 struct drm_i915_gem_object *obj;
79e53945 7548
05394f39 7549 obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
c8725226 7550 if (&obj->base == NULL)
cce13ff7 7551 return ERR_PTR(-ENOENT);
79e53945 7552
d2dff872 7553 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 7554}
7555
79e53945 7556static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 7557 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 7558 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 7559};
7560
05394f39 7561static struct drm_i915_gem_object *
aa40d6bb 7562intel_alloc_context_page(struct drm_device *dev)
9ea8d059 7563{
05394f39 7564 struct drm_i915_gem_object *ctx;
9ea8d059
CW		 7565 int ret;
7566
2c34b850
BW		 7567 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
7568
aa40d6bb
ZN		 7569 ctx = i915_gem_alloc_object(dev, 4096);
7570 if (!ctx) {
9ea8d059
CW		 7571 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
7572 return NULL;
7573 }
7574
75e9e915 7575 ret = i915_gem_object_pin(ctx, 4096, true);
9ea8d059
CW		 7576 if (ret) {
7577 DRM_ERROR("failed to pin power context: %d\n", ret);
7578 goto err_unref;
7579 }
7580
aa40d6bb 7581 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
9ea8d059
CW		 7582 if (ret) {
7583 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
7584 goto err_unpin;
7585 }
9ea8d059 7586
aa40d6bb 7587 return ctx;
9ea8d059
CW		 7588
7589err_unpin:
aa40d6bb 7590 i915_gem_object_unpin(ctx);
9ea8d059 7591err_unref:
05394f39 7592 drm_gem_object_unreference(&ctx->base);
9ea8d059
CW		 7593 mutex_unlock(&dev->struct_mutex);
7594 return NULL;
7595}
7596
7648fa99
JB		 7597bool ironlake_set_drps(struct drm_device *dev, u8 val)
7598{
7599 struct drm_i915_private *dev_priv = dev->dev_private;
7600 u16 rgvswctl;
7601
7602 rgvswctl = I915_READ16(MEMSWCTL);
7603 if (rgvswctl & MEMCTL_CMD_STS) {
7604 DRM_DEBUG("gpu busy, RCS change rejected\n");
7605 return false; /* still busy with another command */
7606 }
7607
7608 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
7609 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
7610 I915_WRITE16(MEMSWCTL, rgvswctl);
7611 POSTING_READ16(MEMSWCTL);
7612
7613 rgvswctl |= MEMCTL_CMD_STS;
7614 I915_WRITE16(MEMSWCTL, rgvswctl);
7615
7616 return true;
7617}
7618
f97108d1
JB		 7619void ironlake_enable_drps(struct drm_device *dev)
7620{
7621 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 7622 u32 rgvmodectl = I915_READ(MEMMODECTL);
f97108d1 7623 u8 fmax, fmin, fstart, vstart;
f97108d1 7624
ea056c14
JB		 7625 /* Enable temp reporting */
7626 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
7627 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
7628
f97108d1
JB		 7629 /* 100ms RC evaluation intervals */
7630 I915_WRITE(RCUPEI, 100000);
7631 I915_WRITE(RCDNEI, 100000);
7632
7633 /* Set max/min thresholds to 90ms and 80ms respectively */
7634 I915_WRITE(RCBMAXAVG, 90000);
7635 I915_WRITE(RCBMINAVG, 80000);
7636
7637 I915_WRITE(MEMIHYST, 1);
7638
7639 /* Set up min, max, and cur for interrupt handling */
7640 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
7641 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
7642 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
7643 MEMMODE_FSTART_SHIFT;
7648fa99 7644
f97108d1
JB		 7645 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
7646 PXVFREQ_PX_SHIFT;
7647
80dbf4b7 7648 dev_priv->fmax = fmax; /* IPS callback will increase this */
7648fa99
JB		 7649 dev_priv->fstart = fstart;
7650
80dbf4b7 7651 dev_priv->max_delay = fstart;
f97108d1
JB		 7652 dev_priv->min_delay = fmin;
7653 dev_priv->cur_delay = fstart;
7654
80dbf4b7
JB		 7655 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
7656 fmax, fmin, fstart);
7648fa99 7657
f97108d1
JB		 7658 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
7659
7660 /*
7661 * Interrupts will be enabled in ironlake_irq_postinstall
7662 */
7663
7664 I915_WRITE(VIDSTART, vstart);
7665 POSTING_READ(VIDSTART);
7666
7667 rgvmodectl |= MEMMODE_SWMODE_EN;
7668 I915_WRITE(MEMMODECTL, rgvmodectl);
7669
481b6af3 7670 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
913d8d11 7671 DRM_ERROR("stuck trying to change perf mode\n");
f97108d1
JB		 7672 msleep(1);
7673
7648fa99 7674 ironlake_set_drps(dev, fstart);
f97108d1 7675
7648fa99
JB		 7676 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
7677 I915_READ(0x112e0);
7678 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
7679 dev_priv->last_count2 = I915_READ(0x112f4);
7680 getrawmonotonic(&dev_priv->last_time2);
f97108d1
JB		 7681}
7682
7683void ironlake_disable_drps(struct drm_device *dev)
7684{
7685 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 7686 u16 rgvswctl = I915_READ16(MEMSWCTL);
f97108d1
JB		 7687
7688 /* Ack interrupts, disable EFC interrupt */
7689 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
7690 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
7691 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
7692 I915_WRITE(DEIIR, DE_PCU_EVENT);
7693 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
7694
7695 /* Go back to the starting frequency */
7648fa99 7696 ironlake_set_drps(dev, dev_priv->fstart);
f97108d1
JB		 7697 msleep(1);
7698 rgvswctl |= MEMCTL_CMD_STS;
7699 I915_WRITE(MEMSWCTL, rgvswctl);
7700 msleep(1);
7701
7702}
7703
3b8d8d91
JB		 7704void gen6_set_rps(struct drm_device *dev, u8 val)
7705{
7706 struct drm_i915_private *dev_priv = dev->dev_private;
7707 u32 swreq;
7708
7709 swreq = (val & 0x3ff) << 25;
7710 I915_WRITE(GEN6_RPNSWREQ, swreq);
7711}
7712
7713void gen6_disable_rps(struct drm_device *dev)
7714{
7715 struct drm_i915_private *dev_priv = dev->dev_private;
7716
7717 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
7718 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
7719 I915_WRITE(GEN6_PMIER, 0);
6fdd4d98
DV		 7720 /* Complete PM interrupt masking here doesn't race with the rps work
7721 * item again unmasking PM interrupts because that is using a different
7722 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
7723 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
4912d041
BW		 7724
7725 spin_lock_irq(&dev_priv->rps_lock);
7726 dev_priv->pm_iir = 0;
7727 spin_unlock_irq(&dev_priv->rps_lock);
7728
3b8d8d91
JB		 7729 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
7730}
7731
7648fa99
JB		 7732static unsigned long intel_pxfreq(u32 vidfreq)
7733{
7734 unsigned long freq;
7735 int div = (vidfreq & 0x3f0000) >> 16;
7736 int post = (vidfreq & 0x3000) >> 12;
7737 int pre = (vidfreq & 0x7);
7738
7739 if (!pre)
7740 return 0;
7741
7742 freq = ((div * 133333) / ((1<<post) * pre));
7743
7744 return freq;
7745}
7746
7747void intel_init_emon(struct drm_device *dev)
7748{
7749 struct drm_i915_private *dev_priv = dev->dev_private;
7750 u32 lcfuse;
7751 u8 pxw[16];
7752 int i;
7753
7754 /* Disable to program */
7755 I915_WRITE(ECR, 0);
7756 POSTING_READ(ECR);
7757
7758 /* Program energy weights for various events */
7759 I915_WRITE(SDEW, 0x15040d00);
7760 I915_WRITE(CSIEW0, 0x007f0000);
7761 I915_WRITE(CSIEW1, 0x1e220004);
7762 I915_WRITE(CSIEW2, 0x04000004);
7763
7764 for (i = 0; i < 5; i++)
7765 I915_WRITE(PEW + (i * 4), 0);
7766 for (i = 0; i < 3; i++)
7767 I915_WRITE(DEW + (i * 4), 0);
7768
7769 /* Program P-state weights to account for frequency power adjustment */
7770 for (i = 0; i < 16; i++) {
7771 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
7772 unsigned long freq = intel_pxfreq(pxvidfreq);
7773 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
7774 PXVFREQ_PX_SHIFT;
7775 unsigned long val;
7776
7777 val = vid * vid;
7778 val *= (freq / 1000);
7779 val *= 255;
7780 val /= (127*127*900);
7781 if (val > 0xff)
7782 DRM_ERROR("bad pxval: %ld\n", val);
7783 pxw[i] = val;
7784 }
7785 /* Render standby states get 0 weight */
7786 pxw[14] = 0;
7787 pxw[15] = 0;
7788
7789 for (i = 0; i < 4; i++) {
7790 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
7791 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
7792 I915_WRITE(PXW + (i * 4), val);
7793 }
7794
7795 /* Adjust magic regs to magic values (more experimental results) */
7796 I915_WRITE(OGW0, 0);
7797 I915_WRITE(OGW1, 0);
7798 I915_WRITE(EG0, 0x00007f00);
7799 I915_WRITE(EG1, 0x0000000e);
7800 I915_WRITE(EG2, 0x000e0000);
7801 I915_WRITE(EG3, 0x68000300);
7802 I915_WRITE(EG4, 0x42000000);
7803 I915_WRITE(EG5, 0x00140031);
7804 I915_WRITE(EG6, 0);
7805 I915_WRITE(EG7, 0);
7806
7807 for (i = 0; i < 8; i++)
7808 I915_WRITE(PXWL + (i * 4), 0);
7809
7810 /* Enable PMON + select events */
7811 I915_WRITE(ECR, 0x80000019);
7812
7813 lcfuse = I915_READ(LCFUSE02);
7814
7815 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
7816}
7817
3b8d8d91 7818void gen6_enable_rps(struct drm_i915_private *dev_priv)
8fd26859 7819{
a6044e23
JB		 7820 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
7821 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
7df8721b 7822 u32 pcu_mbox, rc6_mask = 0;
a6044e23 7823 int cur_freq, min_freq, max_freq;
8fd26859
CW		 7824 int i;
7825
7826 /* Here begins a magic sequence of register writes to enable
7827 * auto-downclocking.
7828 *
7829 * Perhaps there might be some value in exposing these to
7830 * userspace...
7831 */
7832 I915_WRITE(GEN6_RC_STATE, 0);
d1ebd816 7833 mutex_lock(&dev_priv->dev->struct_mutex);
fcca7926 7834 gen6_gt_force_wake_get(dev_priv);
8fd26859 7835
3b8d8d91 7836 /* disable the counters and set deterministic thresholds */
8fd26859
CW		 7837 I915_WRITE(GEN6_RC_CONTROL, 0);
7838
7839 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
7840 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
7841 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
7842 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
7843 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
7844
7845 for (i = 0; i < I915_NUM_RINGS; i++)
7846 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
7847
7848 I915_WRITE(GEN6_RC_SLEEP, 0);
7849 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
7850 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
7851 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
7852 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
7853
7df8721b
JB		 7854 if (i915_enable_rc6)
7855 rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
7856 GEN6_RC_CTL_RC6_ENABLE;
7857
8fd26859 7858 I915_WRITE(GEN6_RC_CONTROL,
7df8721b 7859 rc6_mask |
9c3d2f7f 7860 GEN6_RC_CTL_EI_MODE(1) |
8fd26859
CW		 7861 GEN6_RC_CTL_HW_ENABLE);
7862
3b8d8d91 7863 I915_WRITE(GEN6_RPNSWREQ,
8fd26859
CW		 7864 GEN6_FREQUENCY(10) |
7865 GEN6_OFFSET(0) |
7866 GEN6_AGGRESSIVE_TURBO);
7867 I915_WRITE(GEN6_RC_VIDEO_FREQ,
7868 GEN6_FREQUENCY(12));
7869
7870 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
7871 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
7872 18 << 24 |
7873 6 << 16);
ccab5c82
JB		 7874 I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
7875 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
8fd26859 7876 I915_WRITE(GEN6_RP_UP_EI, 100000);
ccab5c82 7877 I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
8fd26859
CW		 7878 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
7879 I915_WRITE(GEN6_RP_CONTROL,
7880 GEN6_RP_MEDIA_TURBO |
7881 GEN6_RP_USE_NORMAL_FREQ |
7882 GEN6_RP_MEDIA_IS_GFX |
7883 GEN6_RP_ENABLE |
ccab5c82
JB		 7884 GEN6_RP_UP_BUSY_AVG |
7885 GEN6_RP_DOWN_IDLE_CONT);
8fd26859
CW		 7886
7887 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7888 500))
7889 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7890
7891 I915_WRITE(GEN6_PCODE_DATA, 0);
7892 I915_WRITE(GEN6_PCODE_MAILBOX,
7893 GEN6_PCODE_READY |
7894 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
7895 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7896 500))
7897 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7898
a6044e23
JB		 7899 min_freq = (rp_state_cap & 0xff0000) >> 16;
7900 max_freq = rp_state_cap & 0xff;
7901 cur_freq = (gt_perf_status & 0xff00) >> 8;
7902
7903 /* Check for overclock support */
7904 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7905 500))
7906 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7907 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
7908 pcu_mbox = I915_READ(GEN6_PCODE_DATA);
7909 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7910 500))
7911 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7912 if (pcu_mbox & (1<<31)) { /* OC supported */
7913 max_freq = pcu_mbox & 0xff;
e281fcaa 7914 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
a6044e23
JB		 7915 }
7916
7917 /* In units of 100MHz */
7918 dev_priv->max_delay = max_freq;
7919 dev_priv->min_delay = min_freq;
7920 dev_priv->cur_delay = cur_freq;
7921
8fd26859
CW		 7922 /* requires MSI enabled */
7923 I915_WRITE(GEN6_PMIER,
7924 GEN6_PM_MBOX_EVENT |
7925 GEN6_PM_THERMAL_EVENT |
7926 GEN6_PM_RP_DOWN_TIMEOUT |
7927 GEN6_PM_RP_UP_THRESHOLD |
7928 GEN6_PM_RP_DOWN_THRESHOLD |
7929 GEN6_PM_RP_UP_EI_EXPIRED |
7930 GEN6_PM_RP_DOWN_EI_EXPIRED);
4912d041
BW		 7931 spin_lock_irq(&dev_priv->rps_lock);
7932 WARN_ON(dev_priv->pm_iir != 0);
3b8d8d91 7933 I915_WRITE(GEN6_PMIMR, 0);
4912d041 7934 spin_unlock_irq(&dev_priv->rps_lock);
3b8d8d91
JB		 7935 /* enable all PM interrupts */
7936 I915_WRITE(GEN6_PMINTRMSK, 0);
8fd26859 7937
fcca7926 7938 gen6_gt_force_wake_put(dev_priv);
d1ebd816 7939 mutex_unlock(&dev_priv->dev->struct_mutex);
8fd26859
CW		 7940}
7941
23b2f8bb
JB		 7942void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
7943{
7944 int min_freq = 15;
7945 int gpu_freq, ia_freq, max_ia_freq;
7946 int scaling_factor = 180;
7947
7948 max_ia_freq = cpufreq_quick_get_max(0);
7949 /*
7950 * Default to measured freq if none found, PCU will ensure we don't go
7951 * over
7952 */
7953 if (!max_ia_freq)
7954 max_ia_freq = tsc_khz;
7955
7956 /* Convert from kHz to MHz */
7957 max_ia_freq /= 1000;
7958
7959 mutex_lock(&dev_priv->dev->struct_mutex);
7960
7961 /*
7962 * For each potential GPU frequency, load a ring frequency we'd like
7963 * to use for memory access. We do this by specifying the IA frequency
7964 * the PCU should use as a reference to determine the ring frequency.
7965 */
7966 for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
7967 gpu_freq--) {
7968 int diff = dev_priv->max_delay - gpu_freq;
7969
7970 /*
7971 * For GPU frequencies less than 750MHz, just use the lowest
7972 * ring freq.
7973 */
7974 if (gpu_freq < min_freq)
7975 ia_freq = 800;
7976 else
7977 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
7978 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
7979
7980 I915_WRITE(GEN6_PCODE_DATA,
7981 (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
7982 gpu_freq);
7983 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
7984 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
7985 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
7986 GEN6_PCODE_READY) == 0, 10)) {
7987 DRM_ERROR("pcode write of freq table timed out\n");
7988 continue;
7989 }
7990 }
7991
7992 mutex_unlock(&dev_priv->dev->struct_mutex);
7993}
7994
6067aaea
JB		 7995static void ironlake_init_clock_gating(struct drm_device *dev)
7996{
7997 struct drm_i915_private *dev_priv = dev->dev_private;
7998 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7999
8000 /* Required for FBC */
8001 dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
8002 DPFCRUNIT_CLOCK_GATE_DISABLE |
8003 DPFDUNIT_CLOCK_GATE_DISABLE;
8004 /* Required for CxSR */
8005 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
8006
8007 I915_WRITE(PCH_3DCGDIS0,
8008 MARIUNIT_CLOCK_GATE_DISABLE |
8009 SVSMUNIT_CLOCK_GATE_DISABLE);
8010 I915_WRITE(PCH_3DCGDIS1,
8011 VFMUNIT_CLOCK_GATE_DISABLE);
8012
8013 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8014
6067aaea
JB		 8015 /*
8016 * According to the spec the following bits should be set in
8017 * order to enable memory self-refresh
8018 * The bit 22/21 of 0x42004
8019 * The bit 5 of 0x42020
8020 * The bit 15 of 0x45000
8021 */
8022 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8023 (I915_READ(ILK_DISPLAY_CHICKEN2) |
8024 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
8025 I915_WRITE(ILK_DSPCLK_GATE,
8026 (I915_READ(ILK_DSPCLK_GATE) |
8027 ILK_DPARB_CLK_GATE));
8028 I915_WRITE(DISP_ARB_CTL,
8029 (I915_READ(DISP_ARB_CTL) |
8030 DISP_FBC_WM_DIS));
8031 I915_WRITE(WM3_LP_ILK, 0);
8032 I915_WRITE(WM2_LP_ILK, 0);
8033 I915_WRITE(WM1_LP_ILK, 0);
8034
8035 /*
8036 * Based on the document from hardware guys the following bits
8037 * should be set unconditionally in order to enable FBC.
8038 * The bit 22 of 0x42000
8039 * The bit 22 of 0x42004
8040 * The bit 7,8,9 of 0x42020.
8041 */
8042 if (IS_IRONLAKE_M(dev)) {
8043 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8044 I915_READ(ILK_DISPLAY_CHICKEN1) |
8045 ILK_FBCQ_DIS);
8046 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8047 I915_READ(ILK_DISPLAY_CHICKEN2) |
8048 ILK_DPARB_GATE);
8049 I915_WRITE(ILK_DSPCLK_GATE,
8050 I915_READ(ILK_DSPCLK_GATE) |
8051 ILK_DPFC_DIS1 |
8052 ILK_DPFC_DIS2 |
8053 ILK_CLK_FBC);
8054 }
8055
8056 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8057 I915_READ(ILK_DISPLAY_CHICKEN2) |
8058 ILK_ELPIN_409_SELECT);
8059 I915_WRITE(_3D_CHICKEN2,
8060 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
8061 _3D_CHICKEN2_WM_READ_PIPELINED);
8fd26859
CW		 8062}
8063
6067aaea 8064static void gen6_init_clock_gating(struct drm_device *dev)
652c393a
JB		 8065{
8066 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 8067 int pipe;
6067aaea
JB		 8068 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8069
8070 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
652c393a 8071
6067aaea
JB		 8072 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8073 I915_READ(ILK_DISPLAY_CHICKEN2) |
8074 ILK_ELPIN_409_SELECT);
8956c8bb 8075
6067aaea
JB		 8076 I915_WRITE(WM3_LP_ILK, 0);
8077 I915_WRITE(WM2_LP_ILK, 0);
8078 I915_WRITE(WM1_LP_ILK, 0);
652c393a
JB		 8079
8080 /*
6067aaea
JB		 8081 * According to the spec the following bits should be
8082 * set in order to enable memory self-refresh and fbc:
8083 * The bit21 and bit22 of 0x42000
8084 * The bit21 and bit22 of 0x42004
8085 * The bit5 and bit7 of 0x42020
8086 * The bit14 of 0x70180
8087 * The bit14 of 0x71180
652c393a 8088 */
6067aaea
JB		 8089 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8090 I915_READ(ILK_DISPLAY_CHICKEN1) |
8091 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
8092 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8093 I915_READ(ILK_DISPLAY_CHICKEN2) |
8094 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
8095 I915_WRITE(ILK_DSPCLK_GATE,
8096 I915_READ(ILK_DSPCLK_GATE) |
8097 ILK_DPARB_CLK_GATE |
8098 ILK_DPFD_CLK_GATE);
8956c8bb 8099
d74362c9 8100 for_each_pipe(pipe) {
6067aaea
JB		 8101 I915_WRITE(DSPCNTR(pipe),
8102 I915_READ(DSPCNTR(pipe)) |
8103 DISPPLANE_TRICKLE_FEED_DISABLE);
d74362c9
KP		 8104 intel_flush_display_plane(dev_priv, pipe);
8105 }
6067aaea 8106}
8956c8bb 8107
28963a3e
JB		 8108static void ivybridge_init_clock_gating(struct drm_device *dev)
8109{
8110 struct drm_i915_private *dev_priv = dev->dev_private;
8111 int pipe;
8112 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7f8a8569 8113
28963a3e 8114 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
382b0936 8115
28963a3e
JB		 8116 I915_WRITE(WM3_LP_ILK, 0);
8117 I915_WRITE(WM2_LP_ILK, 0);
8118 I915_WRITE(WM1_LP_ILK, 0);
de6e2eaf 8119
28963a3e 8120 I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
67e92af0 8121
d74362c9 8122 for_each_pipe(pipe) {
28963a3e
JB		 8123 I915_WRITE(DSPCNTR(pipe),
8124 I915_READ(DSPCNTR(pipe)) |
8125 DISPPLANE_TRICKLE_FEED_DISABLE);
d74362c9
KP		 8126 intel_flush_display_plane(dev_priv, pipe);
8127 }
28963a3e
JB		 8128}
8129
6067aaea
JB		 8130static void g4x_init_clock_gating(struct drm_device *dev)
8131{
8132 struct drm_i915_private *dev_priv = dev->dev_private;
8133 uint32_t dspclk_gate;
8fd26859 8134
6067aaea
JB		 8135 I915_WRITE(RENCLK_GATE_D1, 0);
8136 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
8137 GS_UNIT_CLOCK_GATE_DISABLE |
8138 CL_UNIT_CLOCK_GATE_DISABLE);
8139 I915_WRITE(RAMCLK_GATE_D, 0);
8140 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
8141 OVRUNIT_CLOCK_GATE_DISABLE |
8142 OVCUNIT_CLOCK_GATE_DISABLE;
8143 if (IS_GM45(dev))
8144 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
8145 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
8146}
1398261a 8147
6067aaea
JB		 8148static void crestline_init_clock_gating(struct drm_device *dev)
8149{
8150 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 8151
6067aaea
JB		 8152 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
8153 I915_WRITE(RENCLK_GATE_D2, 0);
8154 I915_WRITE(DSPCLK_GATE_D, 0);
8155 I915_WRITE(RAMCLK_GATE_D, 0);
8156 I915_WRITE16(DEUC, 0);
8157}
652c393a 8158
6067aaea
JB		 8159static void broadwater_init_clock_gating(struct drm_device *dev)
8160{
8161 struct drm_i915_private *dev_priv = dev->dev_private;
8162
8163 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
8164 I965_RCC_CLOCK_GATE_DISABLE |
8165 I965_RCPB_CLOCK_GATE_DISABLE |
8166 I965_ISC_CLOCK_GATE_DISABLE |
8167 I965_FBC_CLOCK_GATE_DISABLE);
8168 I915_WRITE(RENCLK_GATE_D2, 0);
8169}
8170
8171static void gen3_init_clock_gating(struct drm_device *dev)
8172{
8173 struct drm_i915_private *dev_priv = dev->dev_private;
8174 u32 dstate = I915_READ(D_STATE);
8175
8176 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
8177 DSTATE_DOT_CLOCK_GATING;
8178 I915_WRITE(D_STATE, dstate);
8179}
8180
8181static void i85x_init_clock_gating(struct drm_device *dev)
8182{
8183 struct drm_i915_private *dev_priv = dev->dev_private;
8184
8185 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
8186}
8187
8188static void i830_init_clock_gating(struct drm_device *dev)
8189{
8190 struct drm_i915_private *dev_priv = dev->dev_private;
8191
8192 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
652c393a
JB		 8193}
8194
645c62a5
JB		 8195static void ibx_init_clock_gating(struct drm_device *dev)
8196{
8197 struct drm_i915_private *dev_priv = dev->dev_private;
8198
8199 /*
8200 * On Ibex Peak and Cougar Point, we need to disable clock
8201 * gating for the panel power sequencer or it will fail to
8202 * start up when no ports are active.
8203 */
8204 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8205}
8206
8207static void cpt_init_clock_gating(struct drm_device *dev)
8208{
8209 struct drm_i915_private *dev_priv = dev->dev_private;
3bcf603f 8210 int pipe;
645c62a5
JB		 8211
8212 /*
8213 * On Ibex Peak and Cougar Point, we need to disable clock
8214 * gating for the panel power sequencer or it will fail to
8215 * start up when no ports are active.
8216 */
8217 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8218 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
8219 DPLS_EDP_PPS_FIX_DIS);
3bcf603f
JB		 8220 /* Without this, mode sets may fail silently on FDI */
8221 for_each_pipe(pipe)
8222 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
652c393a
JB		 8223}
8224
ac668088 8225static void ironlake_teardown_rc6(struct drm_device *dev)
0cdab21f
CW		 8226{
8227 struct drm_i915_private *dev_priv = dev->dev_private;
8228
8229 if (dev_priv->renderctx) {
ac668088
CW		 8230 i915_gem_object_unpin(dev_priv->renderctx);
8231 drm_gem_object_unreference(&dev_priv->renderctx->base);
0cdab21f
CW		 8232 dev_priv->renderctx = NULL;
8233 }
8234
8235 if (dev_priv->pwrctx) {
ac668088
CW		 8236 i915_gem_object_unpin(dev_priv->pwrctx);
8237 drm_gem_object_unreference(&dev_priv->pwrctx->base);
8238 dev_priv->pwrctx = NULL;
8239 }
8240}
8241
8242static void ironlake_disable_rc6(struct drm_device *dev)
8243{
8244 struct drm_i915_private *dev_priv = dev->dev_private;
8245
8246 if (I915_READ(PWRCTXA)) {
8247 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
8248 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
8249 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
8250 50);
0cdab21f
CW		 8251
8252 I915_WRITE(PWRCTXA, 0);
8253 POSTING_READ(PWRCTXA);
8254
ac668088
CW		 8255 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8256 POSTING_READ(RSTDBYCTL);
0cdab21f 8257 }
ac668088 8258
99507307 8259 ironlake_teardown_rc6(dev);
0cdab21f
CW		 8260}
8261
ac668088 8262static int ironlake_setup_rc6(struct drm_device *dev)
d5bb081b
JB		 8263{
8264 struct drm_i915_private *dev_priv = dev->dev_private;
8265
ac668088
CW		 8266 if (dev_priv->renderctx == NULL)
8267 dev_priv->renderctx = intel_alloc_context_page(dev);
8268 if (!dev_priv->renderctx)
8269 return -ENOMEM;
8270
8271 if (dev_priv->pwrctx == NULL)
8272 dev_priv->pwrctx = intel_alloc_context_page(dev);
8273 if (!dev_priv->pwrctx) {
8274 ironlake_teardown_rc6(dev);
8275 return -ENOMEM;
8276 }
8277
8278 return 0;
d5bb081b
JB		 8279}
8280
8281void ironlake_enable_rc6(struct drm_device *dev)
8282{
8283 struct drm_i915_private *dev_priv = dev->dev_private;
8284 int ret;
8285
ac668088
CW		 8286 /* rc6 disabled by default due to repeated reports of hanging during
8287 * boot and resume.
8288 */
8289 if (!i915_enable_rc6)
8290 return;
8291
2c34b850 8292 mutex_lock(&dev->struct_mutex);
ac668088 8293 ret = ironlake_setup_rc6(dev);
2c34b850
BW		 8294 if (ret) {
8295 mutex_unlock(&dev->struct_mutex);
ac668088 8296 return;
2c34b850 8297 }
ac668088 8298
d5bb081b
JB		 8299 /*
8300 * GPU can automatically power down the render unit if given a page
8301 * to save state.
8302 */
8303 ret = BEGIN_LP_RING(6);
8304 if (ret) {
ac668088 8305 ironlake_teardown_rc6(dev);
2c34b850 8306 mutex_unlock(&dev->struct_mutex);
d5bb081b
JB		 8307 return;
8308 }
ac668088 8309
d5bb081b
JB		 8310 OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
8311 OUT_RING(MI_SET_CONTEXT);
8312 OUT_RING(dev_priv->renderctx->gtt_offset |
8313 MI_MM_SPACE_GTT |
8314 MI_SAVE_EXT_STATE_EN |
8315 MI_RESTORE_EXT_STATE_EN |
8316 MI_RESTORE_INHIBIT);
8317 OUT_RING(MI_SUSPEND_FLUSH);
8318 OUT_RING(MI_NOOP);
8319 OUT_RING(MI_FLUSH);
8320 ADVANCE_LP_RING();
8321
4a246cfc
BW		 8322 /*
8323 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
8324 * does an implicit flush, combined with MI_FLUSH above, it should be
8325 * safe to assume that renderctx is valid
8326 */
8327 ret = intel_wait_ring_idle(LP_RING(dev_priv));
8328 if (ret) {
8329 DRM_ERROR("failed to enable ironlake power power savings\n");
8330 ironlake_teardown_rc6(dev);
8331 mutex_unlock(&dev->struct_mutex);
8332 return;
8333 }
8334
d5bb081b
JB		 8335 I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
8336 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2c34b850 8337 mutex_unlock(&dev->struct_mutex);
d5bb081b
JB		 8338}
8339
645c62a5
JB		 8340void intel_init_clock_gating(struct drm_device *dev)
8341{
8342 struct drm_i915_private *dev_priv = dev->dev_private;
8343
8344 dev_priv->display.init_clock_gating(dev);
8345
8346 if (dev_priv->display.init_pch_clock_gating)
8347 dev_priv->display.init_pch_clock_gating(dev);
8348}
ac668088 8349
e70236a8
JB		 8350/* Set up chip specific display functions */
8351static void intel_init_display(struct drm_device *dev)
8352{
8353 struct drm_i915_private *dev_priv = dev->dev_private;
8354
8355 /* We always want a DPMS function */
f564048e 8356 if (HAS_PCH_SPLIT(dev)) {
f2b115e6 8357 dev_priv->display.dpms = ironlake_crtc_dpms;
f564048e 8358 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
17638cd6 8359 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 8360 } else {
e70236a8 8361 dev_priv->display.dpms = i9xx_crtc_dpms;
f564048e 8362 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
17638cd6 8363 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8364 }
e70236a8 8365
ee5382ae 8366 if (I915_HAS_FBC(dev)) {
9c04f015 8367 if (HAS_PCH_SPLIT(dev)) {
b52eb4dc
ZY		 8368 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
8369 dev_priv->display.enable_fbc = ironlake_enable_fbc;
8370 dev_priv->display.disable_fbc = ironlake_disable_fbc;
8371 } else if (IS_GM45(dev)) {
74dff282
JB		 8372 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
8373 dev_priv->display.enable_fbc = g4x_enable_fbc;
8374 dev_priv->display.disable_fbc = g4x_disable_fbc;
a6c45cf0 8375 } else if (IS_CRESTLINE(dev)) {
e70236a8
JB		 8376 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
8377 dev_priv->display.enable_fbc = i8xx_enable_fbc;
8378 dev_priv->display.disable_fbc = i8xx_disable_fbc;
8379 }
74dff282 8380 /* 855GM needs testing */
e70236a8
JB		 8381 }
8382
8383 /* Returns the core display clock speed */
0206e353 8384 if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 8385 dev_priv->display.get_display_clock_speed =
8386 i945_get_display_clock_speed;
8387 else if (IS_I915G(dev))
8388 dev_priv->display.get_display_clock_speed =
8389 i915_get_display_clock_speed;
f2b115e6 8390 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 8391 dev_priv->display.get_display_clock_speed =
8392 i9xx_misc_get_display_clock_speed;
8393 else if (IS_I915GM(dev))
8394 dev_priv->display.get_display_clock_speed =
8395 i915gm_get_display_clock_speed;
8396 else if (IS_I865G(dev))
8397 dev_priv->display.get_display_clock_speed =
8398 i865_get_display_clock_speed;
f0f8a9ce 8399 else if (IS_I85X(dev))
e70236a8
JB		 8400 dev_priv->display.get_display_clock_speed =
8401 i855_get_display_clock_speed;
8402 else /* 852, 830 */
8403 dev_priv->display.get_display_clock_speed =
8404 i830_get_display_clock_speed;
8405
8406 /* For FIFO watermark updates */
7f8a8569 8407 if (HAS_PCH_SPLIT(dev)) {
645c62a5
JB		 8408 if (HAS_PCH_IBX(dev))
8409 dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
8410 else if (HAS_PCH_CPT(dev))
8411 dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
8412
f00a3ddf 8413 if (IS_GEN5(dev)) {
7f8a8569
ZW		 8414 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
8415 dev_priv->display.update_wm = ironlake_update_wm;
8416 else {
8417 DRM_DEBUG_KMS("Failed to get proper latency. "
8418 "Disable CxSR\n");
8419 dev_priv->display.update_wm = NULL;
1398261a 8420 }
674cf967 8421 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
6067aaea 8422 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
e0dac65e 8423 dev_priv->display.write_eld = ironlake_write_eld;
1398261a
YL		 8424 } else if (IS_GEN6(dev)) {
8425 if (SNB_READ_WM0_LATENCY()) {
8426 dev_priv->display.update_wm = sandybridge_update_wm;
8427 } else {
8428 DRM_DEBUG_KMS("Failed to read display plane latency. "
8429 "Disable CxSR\n");
8430 dev_priv->display.update_wm = NULL;
7f8a8569 8431 }
674cf967 8432 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
6067aaea 8433 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
e0dac65e 8434 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 8435 } else if (IS_IVYBRIDGE(dev)) {
8436 /* FIXME: detect B0+ stepping and use auto training */
8437 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
fe100d4d
JB		 8438 if (SNB_READ_WM0_LATENCY()) {
8439 dev_priv->display.update_wm = sandybridge_update_wm;
8440 } else {
8441 DRM_DEBUG_KMS("Failed to read display plane latency. "
8442 "Disable CxSR\n");
8443 dev_priv->display.update_wm = NULL;
8444 }
28963a3e 8445 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
e0dac65e 8446 dev_priv->display.write_eld = ironlake_write_eld;
7f8a8569
ZW		 8447 } else
8448 dev_priv->display.update_wm = NULL;
8449 } else if (IS_PINEVIEW(dev)) {
d4294342 8450 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
95534263 8451 dev_priv->is_ddr3,
d4294342
ZY		 8452 dev_priv->fsb_freq,
8453 dev_priv->mem_freq)) {
8454 DRM_INFO("failed to find known CxSR latency "
95534263 8455 "(found ddr%s fsb freq %d, mem freq %d), "
d4294342 8456 "disabling CxSR\n",
0206e353 8457 (dev_priv->is_ddr3 == 1) ? "3" : "2",
d4294342
ZY		 8458 dev_priv->fsb_freq, dev_priv->mem_freq);
8459 /* Disable CxSR and never update its watermark again */
8460 pineview_disable_cxsr(dev);
8461 dev_priv->display.update_wm = NULL;
8462 } else
8463 dev_priv->display.update_wm = pineview_update_wm;
95e0ee92 8464 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6067aaea 8465 } else if (IS_G4X(dev)) {
e0dac65e 8466 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 8467 dev_priv->display.update_wm = g4x_update_wm;
6067aaea
JB		 8468 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
8469 } else if (IS_GEN4(dev)) {
e70236a8 8470 dev_priv->display.update_wm = i965_update_wm;
6067aaea
JB		 8471 if (IS_CRESTLINE(dev))
8472 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
8473 else if (IS_BROADWATER(dev))
8474 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
8475 } else if (IS_GEN3(dev)) {
e70236a8
JB		 8476 dev_priv->display.update_wm = i9xx_update_wm;
8477 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6067aaea
JB		 8478 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8479 } else if (IS_I865G(dev)) {
8480 dev_priv->display.update_wm = i830_update_wm;
8481 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8482 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8f4695ed
AJ		 8483 } else if (IS_I85X(dev)) {
8484 dev_priv->display.update_wm = i9xx_update_wm;
8485 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
6067aaea 8486 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
e70236a8 8487 } else {
8f4695ed 8488 dev_priv->display.update_wm = i830_update_wm;
6067aaea 8489 dev_priv->display.init_clock_gating = i830_init_clock_gating;
8f4695ed 8490 if (IS_845G(dev))
e70236a8
JB		 8491 dev_priv->display.get_fifo_size = i845_get_fifo_size;
8492 else
8493 dev_priv->display.get_fifo_size = i830_get_fifo_size;
e70236a8 8494 }
8c9f3aaf
JB		 8495
8496 /* Default just returns -ENODEV to indicate unsupported */
8497 dev_priv->display.queue_flip = intel_default_queue_flip;
8498
8499 switch (INTEL_INFO(dev)->gen) {
8500 case 2:
8501 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8502 break;
8503
8504 case 3:
8505 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8506 break;
8507
8508 case 4:
8509 case 5:
8510 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8511 break;
8512
8513 case 6:
8514 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8515 break;
7c9017e5
JB		 8516 case 7:
8517 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8518 break;
8c9f3aaf 8519 }
e70236a8
JB		 8520}
8521
b690e96c
JB		 8522/*
8523 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8524 * resume, or other times. This quirk makes sure that's the case for
8525 * affected systems.
8526 */
0206e353 8527static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 8528{
8529 struct drm_i915_private *dev_priv = dev->dev_private;
8530
8531 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8532 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
8533}
8534
435793df
KP		 8535/*
8536 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8537 */
8538static void quirk_ssc_force_disable(struct drm_device *dev)
8539{
8540 struct drm_i915_private *dev_priv = dev->dev_private;
8541 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8542}
8543
b690e96c
JB		 8544struct intel_quirk {
8545 int device;
8546 int subsystem_vendor;
8547 int subsystem_device;
8548 void (*hook)(struct drm_device *dev);
8549};
8550
8551struct intel_quirk intel_quirks[] = {
8552 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
8553 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
8554 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 8555 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c
JB		 8556
8557 /* Thinkpad R31 needs pipe A force quirk */
8558 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
8559 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8560 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8561
8562 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
8563 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
8564 /* ThinkPad X40 needs pipe A force quirk */
8565
8566 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8567 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8568
8569 /* 855 & before need to leave pipe A & dpll A up */
8570 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8571 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 8572
8573 /* Lenovo U160 cannot use SSC on LVDS */
8574 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 8575
8576 /* Sony Vaio Y cannot use SSC on LVDS */
8577 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
b690e96c
JB		 8578};
8579
8580static void intel_init_quirks(struct drm_device *dev)
8581{
8582 struct pci_dev *d = dev->pdev;
8583 int i;
8584
8585 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8586 struct intel_quirk *q = &intel_quirks[i];
8587
8588 if (d->device == q->device &&
8589 (d->subsystem_vendor == q->subsystem_vendor ||
8590 q->subsystem_vendor == PCI_ANY_ID) &&
8591 (d->subsystem_device == q->subsystem_device ||
8592 q->subsystem_device == PCI_ANY_ID))
8593 q->hook(dev);
8594 }
8595}
8596
9cce37f4
JB		 8597/* Disable the VGA plane that we never use */
8598static void i915_disable_vga(struct drm_device *dev)
8599{
8600 struct drm_i915_private *dev_priv = dev->dev_private;
8601 u8 sr1;
8602 u32 vga_reg;
8603
8604 if (HAS_PCH_SPLIT(dev))
8605 vga_reg = CPU_VGACNTRL;
8606 else
8607 vga_reg = VGACNTRL;
8608
8609 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8610 outb(1, VGA_SR_INDEX);
8611 sr1 = inb(VGA_SR_DATA);
8612 outb(sr1 | 1<<5, VGA_SR_DATA);
8613 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8614 udelay(300);
8615
8616 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8617 POSTING_READ(vga_reg);
8618}
8619
79e53945
JB		 8620void intel_modeset_init(struct drm_device *dev)
8621{
652c393a 8622 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 8623 int i;
8624
8625 drm_mode_config_init(dev);
8626
8627 dev->mode_config.min_width = 0;
8628 dev->mode_config.min_height = 0;
8629
8630 dev->mode_config.funcs = (void *)&intel_mode_funcs;
8631
b690e96c
JB		 8632 intel_init_quirks(dev);
8633
e70236a8
JB		 8634 intel_init_display(dev);
8635
a6c45cf0
CW		 8636 if (IS_GEN2(dev)) {
8637 dev->mode_config.max_width = 2048;
8638 dev->mode_config.max_height = 2048;
8639 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 8640 dev->mode_config.max_width = 4096;
8641 dev->mode_config.max_height = 4096;
79e53945 8642 } else {
a6c45cf0
CW		 8643 dev->mode_config.max_width = 8192;
8644 dev->mode_config.max_height = 8192;
79e53945 8645 }
35c3047a 8646 dev->mode_config.fb_base = dev->agp->base;
79e53945 8647
28c97730 8648 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 8649 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 8650
a3524f1b 8651 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945
JB		 8652 intel_crtc_init(dev, i);
8653 }
8654
9cce37f4
JB		 8655 /* Just disable it once at startup */
8656 i915_disable_vga(dev);
79e53945 8657 intel_setup_outputs(dev);
652c393a 8658
645c62a5 8659 intel_init_clock_gating(dev);
9cce37f4 8660
7648fa99 8661 if (IS_IRONLAKE_M(dev)) {
f97108d1 8662 ironlake_enable_drps(dev);
7648fa99
JB		 8663 intel_init_emon(dev);
8664 }
f97108d1 8665
1c70c0ce 8666 if (IS_GEN6(dev) || IS_GEN7(dev)) {
3b8d8d91 8667 gen6_enable_rps(dev_priv);
23b2f8bb
JB		 8668 gen6_update_ring_freq(dev_priv);
8669 }
3b8d8d91 8670
652c393a
JB		 8671 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
8672 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
8673 (unsigned long)dev);
2c7111db
CW		 8674}
8675
8676void intel_modeset_gem_init(struct drm_device *dev)
8677{
8678 if (IS_IRONLAKE_M(dev))
8679 ironlake_enable_rc6(dev);
02e792fb
DV		 8680
8681 intel_setup_overlay(dev);
79e53945
JB		 8682}
8683
8684void intel_modeset_cleanup(struct drm_device *dev)
8685{
652c393a
JB		 8686 struct drm_i915_private *dev_priv = dev->dev_private;
8687 struct drm_crtc *crtc;
8688 struct intel_crtc *intel_crtc;
8689
f87ea761 8690 drm_kms_helper_poll_fini(dev);
652c393a
JB		 8691 mutex_lock(&dev->struct_mutex);
8692
723bfd70
JB		 8693 intel_unregister_dsm_handler();
8694
8695
652c393a
JB		 8696 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8697 /* Skip inactive CRTCs */
8698 if (!crtc->fb)
8699 continue;
8700
8701 intel_crtc = to_intel_crtc(crtc);
3dec0095 8702 intel_increase_pllclock(crtc);
652c393a
JB		 8703 }
8704
973d04f9 8705 intel_disable_fbc(dev);
e70236a8 8706
f97108d1
JB		 8707 if (IS_IRONLAKE_M(dev))
8708 ironlake_disable_drps(dev);
1c70c0ce 8709 if (IS_GEN6(dev) || IS_GEN7(dev))
3b8d8d91 8710 gen6_disable_rps(dev);
f97108d1 8711
d5bb081b
JB		 8712 if (IS_IRONLAKE_M(dev))
8713 ironlake_disable_rc6(dev);
0cdab21f 8714
69341a5e
KH		 8715 mutex_unlock(&dev->struct_mutex);
8716
6c0d9350
DV		 8717 /* Disable the irq before mode object teardown, for the irq might
8718 * enqueue unpin/hotplug work. */
8719 drm_irq_uninstall(dev);
8720 cancel_work_sync(&dev_priv->hotplug_work);
6fdd4d98 8721 cancel_work_sync(&dev_priv->rps_work);
6c0d9350 8722
1630fe75
CW		 8723 /* flush any delayed tasks or pending work */
8724 flush_scheduled_work();
8725
3dec0095
DV		 8726 /* Shut off idle work before the crtcs get freed. */
8727 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8728 intel_crtc = to_intel_crtc(crtc);
8729 del_timer_sync(&intel_crtc->idle_timer);
8730 }
8731 del_timer_sync(&dev_priv->idle_timer);
8732 cancel_work_sync(&dev_priv->idle_work);
8733
79e53945
JB		 8734 drm_mode_config_cleanup(dev);
8735}
8736
f1c79df3
ZW		 8737/*
8738 * Return which encoder is currently attached for connector.
8739 */
df0e9248 8740struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 8741{
df0e9248
CW		 8742 return &intel_attached_encoder(connector)->base;
8743}
f1c79df3 8744
df0e9248
CW		 8745void intel_connector_attach_encoder(struct intel_connector *connector,
8746 struct intel_encoder *encoder)
8747{
8748 connector->encoder = encoder;
8749 drm_mode_connector_attach_encoder(&connector->base,
8750 &encoder->base);
79e53945 8751}
28d52043
DA		 8752
8753/*
8754 * set vga decode state - true == enable VGA decode
8755 */
8756int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
8757{
8758 struct drm_i915_private *dev_priv = dev->dev_private;
8759 u16 gmch_ctrl;
8760
8761 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
8762 if (state)
8763 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
8764 else
8765 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
8766 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
8767 return 0;
8768}
c4a1d9e4
CW		 8769
8770#ifdef CONFIG_DEBUG_FS
8771#include <linux/seq_file.h>
8772
8773struct intel_display_error_state {
8774 struct intel_cursor_error_state {
8775 u32 control;
8776 u32 position;
8777 u32 base;
8778 u32 size;
8779 } cursor[2];
8780
8781 struct intel_pipe_error_state {
8782 u32 conf;
8783 u32 source;
8784
8785 u32 htotal;
8786 u32 hblank;
8787 u32 hsync;
8788 u32 vtotal;
8789 u32 vblank;
8790 u32 vsync;
8791 } pipe[2];
8792
8793 struct intel_plane_error_state {
8794 u32 control;
8795 u32 stride;
8796 u32 size;
8797 u32 pos;
8798 u32 addr;
8799 u32 surface;
8800 u32 tile_offset;
8801 } plane[2];
8802};
8803
8804struct intel_display_error_state *
8805intel_display_capture_error_state(struct drm_device *dev)
8806{
0206e353 8807 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 8808 struct intel_display_error_state *error;
8809 int i;
8810
8811 error = kmalloc(sizeof(*error), GFP_ATOMIC);
8812 if (error == NULL)
8813 return NULL;
8814
8815 for (i = 0; i < 2; i++) {
8816 error->cursor[i].control = I915_READ(CURCNTR(i));
8817 error->cursor[i].position = I915_READ(CURPOS(i));
8818 error->cursor[i].base = I915_READ(CURBASE(i));
8819
8820 error->plane[i].control = I915_READ(DSPCNTR(i));
8821 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
8822 error->plane[i].size = I915_READ(DSPSIZE(i));
0206e353 8823 error->plane[i].pos = I915_READ(DSPPOS(i));
c4a1d9e4
CW		 8824 error->plane[i].addr = I915_READ(DSPADDR(i));
8825 if (INTEL_INFO(dev)->gen >= 4) {
8826 error->plane[i].surface = I915_READ(DSPSURF(i));
8827 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
8828 }
8829
8830 error->pipe[i].conf = I915_READ(PIPECONF(i));
8831 error->pipe[i].source = I915_READ(PIPESRC(i));
8832 error->pipe[i].htotal = I915_READ(HTOTAL(i));
8833 error->pipe[i].hblank = I915_READ(HBLANK(i));
8834 error->pipe[i].hsync = I915_READ(HSYNC(i));
8835 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
8836 error->pipe[i].vblank = I915_READ(VBLANK(i));
8837 error->pipe[i].vsync = I915_READ(VSYNC(i));
8838 }
8839
8840 return error;
8841}
8842
8843void
8844intel_display_print_error_state(struct seq_file *m,
8845 struct drm_device *dev,
8846 struct intel_display_error_state *error)
8847{
8848 int i;
8849
8850 for (i = 0; i < 2; i++) {
8851 seq_printf(m, "Pipe [%d]:\n", i);
8852 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
8853 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
8854 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
8855 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
8856 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
8857 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
8858 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
8859 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
8860
8861 seq_printf(m, "Plane [%d]:\n", i);
8862 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
8863 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
8864 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
8865 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
8866 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
8867 if (INTEL_INFO(dev)->gen >= 4) {
8868 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
8869 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
8870 }
8871
8872 seq_printf(m, "Cursor [%d]:\n", i);
8873 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
8874 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
8875 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
8876 }
8877}
8878#endif
Linux 6.x block layer and io_uring tree(s)