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drm/i915: Move toggling planes out of crtc enable/disable.
[linux-block.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
319c1d42 40#include <drm/drm_atomic.h>
c196e1d6 41#include <drm/drm_atomic_helper.h>
760285e7
DH		 42#include <drm/drm_dp_helper.h>
43#include <drm/drm_crtc_helper.h>
465c120c
MR		 44#include <drm/drm_plane_helper.h>
45#include <drm/drm_rect.h>
c0f372b3 46#include <linux/dma_remapping.h>
79e53945 47
465c120c
MR		 48/* Primary plane formats supported by all gen */
49#define COMMON_PRIMARY_FORMATS \
50 DRM_FORMAT_C8, \
51 DRM_FORMAT_RGB565, \
52 DRM_FORMAT_XRGB8888, \
53 DRM_FORMAT_ARGB8888
54
55/* Primary plane formats for gen <= 3 */
56static const uint32_t intel_primary_formats_gen2[] = {
57 COMMON_PRIMARY_FORMATS,
58 DRM_FORMAT_XRGB1555,
59 DRM_FORMAT_ARGB1555,
60};
61
62/* Primary plane formats for gen >= 4 */
63static const uint32_t intel_primary_formats_gen4[] = {
64 COMMON_PRIMARY_FORMATS, \
65 DRM_FORMAT_XBGR8888,
66 DRM_FORMAT_ABGR8888,
67 DRM_FORMAT_XRGB2101010,
68 DRM_FORMAT_ARGB2101010,
69 DRM_FORMAT_XBGR2101010,
70 DRM_FORMAT_ABGR2101010,
71};
72
3d7d6510
MR		 73/* Cursor formats */
74static const uint32_t intel_cursor_formats[] = {
75 DRM_FORMAT_ARGB8888,
76};
77
6b383a7f 78static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 79
f1f644dc 80static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 81 struct intel_crtc_state *pipe_config);
18442d08 82static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 83 struct intel_crtc_state *pipe_config);
f1f644dc 84
e7457a9a 85static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
83a57153
ACO		 86 int x, int y, struct drm_framebuffer *old_fb,
87 struct drm_atomic_state *state);
eb1bfe80
JB		 88static int intel_framebuffer_init(struct drm_device *dev,
89 struct intel_framebuffer *ifb,
90 struct drm_mode_fb_cmd2 *mode_cmd,
91 struct drm_i915_gem_object *obj);
5b18e57c
DV		 92static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
93static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
29407aab 94static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 95 struct intel_link_m_n *m_n,
96 struct intel_link_m_n *m2_n2);
29407aab 97static void ironlake_set_pipeconf(struct drm_crtc *crtc);
229fca97
DV		 98static void haswell_set_pipeconf(struct drm_crtc *crtc);
99static void intel_set_pipe_csc(struct drm_crtc *crtc);
d288f65f 100static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 101 const struct intel_crtc_state *pipe_config);
d288f65f 102static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 103 const struct intel_crtc_state *pipe_config);
ea2c67bb
MR		 104static void intel_begin_crtc_commit(struct drm_crtc *crtc);
105static void intel_finish_crtc_commit(struct drm_crtc *crtc);
549e2bfb
CK		 106static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
107 struct intel_crtc_state *crtc_state);
5ab7b0b7
ID		 108static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
109 int num_connectors);
ce22dba9
ML		 110static void intel_crtc_enable_planes(struct drm_crtc *crtc);
111static void intel_crtc_disable_planes(struct drm_crtc *crtc);
e7457a9a 112
0e32b39c
DA		 113static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
114{
115 if (!connector->mst_port)
116 return connector->encoder;
117 else
118 return &connector->mst_port->mst_encoders[pipe]->base;
119}
120
79e53945 121typedef struct {
0206e353 122 int min, max;
79e53945
JB		 123} intel_range_t;
124
125typedef struct {
0206e353
AJ		 126 int dot_limit;
127 int p2_slow, p2_fast;
79e53945
JB		 128} intel_p2_t;
129
d4906093
ML		 130typedef struct intel_limit intel_limit_t;
131struct intel_limit {
0206e353
AJ		 132 intel_range_t dot, vco, n, m, m1, m2, p, p1;
133 intel_p2_t p2;
d4906093 134};
79e53945 135
d2acd215
DV		 136int
137intel_pch_rawclk(struct drm_device *dev)
138{
139 struct drm_i915_private *dev_priv = dev->dev_private;
140
141 WARN_ON(!HAS_PCH_SPLIT(dev));
142
143 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
144}
145
021357ac
CW		 146static inline u32 /* units of 100MHz */
147intel_fdi_link_freq(struct drm_device *dev)
148{
8b99e68c
CW		 149 if (IS_GEN5(dev)) {
150 struct drm_i915_private *dev_priv = dev->dev_private;
151 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
152 } else
153 return 27;
021357ac
CW		 154}
155
5d536e28 156static const intel_limit_t intel_limits_i8xx_dac = {
0206e353 157 .dot = { .min = 25000, .max = 350000 },
9c333719 158 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 159 .n = { .min = 2, .max = 16 },
0206e353
AJ		 160 .m = { .min = 96, .max = 140 },
161 .m1 = { .min = 18, .max = 26 },
162 .m2 = { .min = 6, .max = 16 },
163 .p = { .min = 4, .max = 128 },
164 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 165 .p2 = { .dot_limit = 165000,
166 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 167};
168
5d536e28
DV		 169static const intel_limit_t intel_limits_i8xx_dvo = {
170 .dot = { .min = 25000, .max = 350000 },
9c333719 171 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 172 .n = { .min = 2, .max = 16 },
5d536e28
DV		 173 .m = { .min = 96, .max = 140 },
174 .m1 = { .min = 18, .max = 26 },
175 .m2 = { .min = 6, .max = 16 },
176 .p = { .min = 4, .max = 128 },
177 .p1 = { .min = 2, .max = 33 },
178 .p2 = { .dot_limit = 165000,
179 .p2_slow = 4, .p2_fast = 4 },
180};
181
e4b36699 182static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353 183 .dot = { .min = 25000, .max = 350000 },
9c333719 184 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 185 .n = { .min = 2, .max = 16 },
0206e353
AJ		 186 .m = { .min = 96, .max = 140 },
187 .m1 = { .min = 18, .max = 26 },
188 .m2 = { .min = 6, .max = 16 },
189 .p = { .min = 4, .max = 128 },
190 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 191 .p2 = { .dot_limit = 165000,
192 .p2_slow = 14, .p2_fast = 7 },
e4b36699 193};
273e27ca 194
e4b36699 195static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 196 .dot = { .min = 20000, .max = 400000 },
197 .vco = { .min = 1400000, .max = 2800000 },
198 .n = { .min = 1, .max = 6 },
199 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 200 .m1 = { .min = 8, .max = 18 },
201 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 202 .p = { .min = 5, .max = 80 },
203 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 204 .p2 = { .dot_limit = 200000,
205 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 206};
207
208static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 209 .dot = { .min = 20000, .max = 400000 },
210 .vco = { .min = 1400000, .max = 2800000 },
211 .n = { .min = 1, .max = 6 },
212 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 213 .m1 = { .min = 8, .max = 18 },
214 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 215 .p = { .min = 7, .max = 98 },
216 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 217 .p2 = { .dot_limit = 112000,
218 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 219};
220
273e27ca 221
e4b36699 222static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 223 .dot = { .min = 25000, .max = 270000 },
224 .vco = { .min = 1750000, .max = 3500000},
225 .n = { .min = 1, .max = 4 },
226 .m = { .min = 104, .max = 138 },
227 .m1 = { .min = 17, .max = 23 },
228 .m2 = { .min = 5, .max = 11 },
229 .p = { .min = 10, .max = 30 },
230 .p1 = { .min = 1, .max = 3},
231 .p2 = { .dot_limit = 270000,
232 .p2_slow = 10,
233 .p2_fast = 10
044c7c41 234 },
e4b36699
KP		 235};
236
237static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 238 .dot = { .min = 22000, .max = 400000 },
239 .vco = { .min = 1750000, .max = 3500000},
240 .n = { .min = 1, .max = 4 },
241 .m = { .min = 104, .max = 138 },
242 .m1 = { .min = 16, .max = 23 },
243 .m2 = { .min = 5, .max = 11 },
244 .p = { .min = 5, .max = 80 },
245 .p1 = { .min = 1, .max = 8},
246 .p2 = { .dot_limit = 165000,
247 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 248};
249
250static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 251 .dot = { .min = 20000, .max = 115000 },
252 .vco = { .min = 1750000, .max = 3500000 },
253 .n = { .min = 1, .max = 3 },
254 .m = { .min = 104, .max = 138 },
255 .m1 = { .min = 17, .max = 23 },
256 .m2 = { .min = 5, .max = 11 },
257 .p = { .min = 28, .max = 112 },
258 .p1 = { .min = 2, .max = 8 },
259 .p2 = { .dot_limit = 0,
260 .p2_slow = 14, .p2_fast = 14
044c7c41 261 },
e4b36699
KP		 262};
263
264static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 265 .dot = { .min = 80000, .max = 224000 },
266 .vco = { .min = 1750000, .max = 3500000 },
267 .n = { .min = 1, .max = 3 },
268 .m = { .min = 104, .max = 138 },
269 .m1 = { .min = 17, .max = 23 },
270 .m2 = { .min = 5, .max = 11 },
271 .p = { .min = 14, .max = 42 },
272 .p1 = { .min = 2, .max = 6 },
273 .p2 = { .dot_limit = 0,
274 .p2_slow = 7, .p2_fast = 7
044c7c41 275 },
e4b36699
KP		 276};
277
f2b115e6 278static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 279 .dot = { .min = 20000, .max = 400000},
280 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 281 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 282 .n = { .min = 3, .max = 6 },
283 .m = { .min = 2, .max = 256 },
273e27ca 284 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 285 .m1 = { .min = 0, .max = 0 },
286 .m2 = { .min = 0, .max = 254 },
287 .p = { .min = 5, .max = 80 },
288 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 289 .p2 = { .dot_limit = 200000,
290 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 291};
292
f2b115e6 293static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 294 .dot = { .min = 20000, .max = 400000 },
295 .vco = { .min = 1700000, .max = 3500000 },
296 .n = { .min = 3, .max = 6 },
297 .m = { .min = 2, .max = 256 },
298 .m1 = { .min = 0, .max = 0 },
299 .m2 = { .min = 0, .max = 254 },
300 .p = { .min = 7, .max = 112 },
301 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 302 .p2 = { .dot_limit = 112000,
303 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 304};
305
273e27ca
EA		 306/* Ironlake / Sandybridge
307 *
308 * We calculate clock using (register_value + 2) for N/M1/M2, so here
309 * the range value for them is (actual_value - 2).
310 */
b91ad0ec 311static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 312 .dot = { .min = 25000, .max = 350000 },
313 .vco = { .min = 1760000, .max = 3510000 },
314 .n = { .min = 1, .max = 5 },
315 .m = { .min = 79, .max = 127 },
316 .m1 = { .min = 12, .max = 22 },
317 .m2 = { .min = 5, .max = 9 },
318 .p = { .min = 5, .max = 80 },
319 .p1 = { .min = 1, .max = 8 },
320 .p2 = { .dot_limit = 225000,
321 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 322};
323
b91ad0ec 324static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 325 .dot = { .min = 25000, .max = 350000 },
326 .vco = { .min = 1760000, .max = 3510000 },
327 .n = { .min = 1, .max = 3 },
328 .m = { .min = 79, .max = 118 },
329 .m1 = { .min = 12, .max = 22 },
330 .m2 = { .min = 5, .max = 9 },
331 .p = { .min = 28, .max = 112 },
332 .p1 = { .min = 2, .max = 8 },
333 .p2 = { .dot_limit = 225000,
334 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 335};
336
337static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 338 .dot = { .min = 25000, .max = 350000 },
339 .vco = { .min = 1760000, .max = 3510000 },
340 .n = { .min = 1, .max = 3 },
341 .m = { .min = 79, .max = 127 },
342 .m1 = { .min = 12, .max = 22 },
343 .m2 = { .min = 5, .max = 9 },
344 .p = { .min = 14, .max = 56 },
345 .p1 = { .min = 2, .max = 8 },
346 .p2 = { .dot_limit = 225000,
347 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 348};
349
273e27ca 350/* LVDS 100mhz refclk limits. */
b91ad0ec 351static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 352 .dot = { .min = 25000, .max = 350000 },
353 .vco = { .min = 1760000, .max = 3510000 },
354 .n = { .min = 1, .max = 2 },
355 .m = { .min = 79, .max = 126 },
356 .m1 = { .min = 12, .max = 22 },
357 .m2 = { .min = 5, .max = 9 },
358 .p = { .min = 28, .max = 112 },
0206e353 359 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 360 .p2 = { .dot_limit = 225000,
361 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 362};
363
364static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 365 .dot = { .min = 25000, .max = 350000 },
366 .vco = { .min = 1760000, .max = 3510000 },
367 .n = { .min = 1, .max = 3 },
368 .m = { .min = 79, .max = 126 },
369 .m1 = { .min = 12, .max = 22 },
370 .m2 = { .min = 5, .max = 9 },
371 .p = { .min = 14, .max = 42 },
0206e353 372 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 373 .p2 = { .dot_limit = 225000,
374 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 375};
376
dc730512 377static const intel_limit_t intel_limits_vlv = {
f01b7962
VS		 378 /*
379 * These are the data rate limits (measured in fast clocks)
380 * since those are the strictest limits we have. The fast
381 * clock and actual rate limits are more relaxed, so checking
382 * them would make no difference.
383 */
384 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
75e53986 385 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 386 .n = { .min = 1, .max = 7 },
a0c4da24
JB		 387 .m1 = { .min = 2, .max = 3 },
388 .m2 = { .min = 11, .max = 156 },
b99ab663 389 .p1 = { .min = 2, .max = 3 },
5fdc9c49 390 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
a0c4da24
JB		 391};
392
ef9348c8
CML		 393static const intel_limit_t intel_limits_chv = {
394 /*
395 * These are the data rate limits (measured in fast clocks)
396 * since those are the strictest limits we have. The fast
397 * clock and actual rate limits are more relaxed, so checking
398 * them would make no difference.
399 */
400 .dot = { .min = 25000 * 5, .max = 540000 * 5},
17fe1021 401 .vco = { .min = 4800000, .max = 6480000 },
ef9348c8
CML		 402 .n = { .min = 1, .max = 1 },
403 .m1 = { .min = 2, .max = 2 },
404 .m2 = { .min = 24 << 22, .max = 175 << 22 },
405 .p1 = { .min = 2, .max = 4 },
406 .p2 = { .p2_slow = 1, .p2_fast = 14 },
407};
408
5ab7b0b7
ID		 409static const intel_limit_t intel_limits_bxt = {
410 /* FIXME: find real dot limits */
411 .dot = { .min = 0, .max = INT_MAX },
412 .vco = { .min = 4800000, .max = 6480000 },
413 .n = { .min = 1, .max = 1 },
414 .m1 = { .min = 2, .max = 2 },
415 /* FIXME: find real m2 limits */
416 .m2 = { .min = 2 << 22, .max = 255 << 22 },
417 .p1 = { .min = 2, .max = 4 },
418 .p2 = { .p2_slow = 1, .p2_fast = 20 },
419};
420
6b4bf1c4
VS		 421static void vlv_clock(int refclk, intel_clock_t *clock)
422{
423 clock->m = clock->m1 * clock->m2;
424 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 425 if (WARN_ON(clock->n == 0 || clock->p == 0))
426 return;
fb03ac01
VS		 427 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
428 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
6b4bf1c4
VS		 429}
430
e0638cdf
PZ		 431/**
432 * Returns whether any output on the specified pipe is of the specified type
433 */
4093561b 434bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
e0638cdf 435{
409ee761 436 struct drm_device *dev = crtc->base.dev;
e0638cdf
PZ		 437 struct intel_encoder *encoder;
438
409ee761 439 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
e0638cdf
PZ		 440 if (encoder->type == type)
441 return true;
442
443 return false;
444}
445
d0737e1d
ACO		 446/**
447 * Returns whether any output on the specified pipe will have the specified
448 * type after a staged modeset is complete, i.e., the same as
449 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
450 * encoder->crtc.
451 */
a93e255f
ACO		 452static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
453 int type)
d0737e1d 454{
a93e255f
ACO		 455 struct drm_atomic_state *state = crtc_state->base.state;
456 struct drm_connector_state *connector_state;
d0737e1d 457 struct intel_encoder *encoder;
a93e255f
ACO		 458 int i, num_connectors = 0;
459
460 for (i = 0; i < state->num_connector; i++) {
461 if (!state->connectors[i])
462 continue;
463
464 connector_state = state->connector_states[i];
465 if (connector_state->crtc != crtc_state->base.crtc)
466 continue;
467
468 num_connectors++;
d0737e1d 469
a93e255f
ACO		 470 encoder = to_intel_encoder(connector_state->best_encoder);
471 if (encoder->type == type)
d0737e1d 472 return true;
a93e255f
ACO		 473 }
474
475 WARN_ON(num_connectors == 0);
d0737e1d
ACO		 476
477 return false;
478}
479
a93e255f
ACO		 480static const intel_limit_t *
481intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
2c07245f 482{
a93e255f 483 struct drm_device *dev = crtc_state->base.crtc->dev;
2c07245f 484 const intel_limit_t *limit;
b91ad0ec 485
a93e255f 486 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 487 if (intel_is_dual_link_lvds(dev)) {
1b894b59 488 if (refclk == 100000)
b91ad0ec
ZW		 489 limit = &intel_limits_ironlake_dual_lvds_100m;
490 else
491 limit = &intel_limits_ironlake_dual_lvds;
492 } else {
1b894b59 493 if (refclk == 100000)
b91ad0ec
ZW		 494 limit = &intel_limits_ironlake_single_lvds_100m;
495 else
496 limit = &intel_limits_ironlake_single_lvds;
497 }
c6bb3538 498 } else
b91ad0ec 499 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 500
501 return limit;
502}
503
a93e255f
ACO		 504static const intel_limit_t *
505intel_g4x_limit(struct intel_crtc_state *crtc_state)
044c7c41 506{
a93e255f 507 struct drm_device *dev = crtc_state->base.crtc->dev;
044c7c41
ML		 508 const intel_limit_t *limit;
509
a93e255f 510 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 511 if (intel_is_dual_link_lvds(dev))
e4b36699 512 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 513 else
e4b36699 514 limit = &intel_limits_g4x_single_channel_lvds;
a93e255f
ACO		 515 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
516 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
e4b36699 517 limit = &intel_limits_g4x_hdmi;
a93e255f 518 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
e4b36699 519 limit = &intel_limits_g4x_sdvo;
044c7c41 520 } else /* The option is for other outputs */
e4b36699 521 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 522
523 return limit;
524}
525
a93e255f
ACO		 526static const intel_limit_t *
527intel_limit(struct intel_crtc_state *crtc_state, int refclk)
79e53945 528{
a93e255f 529 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945
JB		 530 const intel_limit_t *limit;
531
5ab7b0b7
ID		 532 if (IS_BROXTON(dev))
533 limit = &intel_limits_bxt;
534 else if (HAS_PCH_SPLIT(dev))
a93e255f 535 limit = intel_ironlake_limit(crtc_state, refclk);
2c07245f 536 else if (IS_G4X(dev)) {
a93e255f 537 limit = intel_g4x_limit(crtc_state);
f2b115e6 538 } else if (IS_PINEVIEW(dev)) {
a93e255f 539 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
f2b115e6 540 limit = &intel_limits_pineview_lvds;
2177832f 541 else
f2b115e6 542 limit = &intel_limits_pineview_sdvo;
ef9348c8
CML		 543 } else if (IS_CHERRYVIEW(dev)) {
544 limit = &intel_limits_chv;
a0c4da24 545 } else if (IS_VALLEYVIEW(dev)) {
dc730512 546 limit = &intel_limits_vlv;
a6c45cf0 547 } else if (!IS_GEN2(dev)) {
a93e255f 548 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
a6c45cf0
CW		 549 limit = &intel_limits_i9xx_lvds;
550 else
551 limit = &intel_limits_i9xx_sdvo;
79e53945 552 } else {
a93e255f 553 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
e4b36699 554 limit = &intel_limits_i8xx_lvds;
a93e255f 555 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
e4b36699 556 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 557 else
558 limit = &intel_limits_i8xx_dac;
79e53945
JB		 559 }
560 return limit;
561}
562
f2b115e6
AJ		 563/* m1 is reserved as 0 in Pineview, n is a ring counter */
564static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 565{
2177832f
SL		 566 clock->m = clock->m2 + 2;
567 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 568 if (WARN_ON(clock->n == 0 || clock->p == 0))
569 return;
fb03ac01
VS		 570 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
571 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
2177832f
SL		 572}
573
7429e9d4
DV		 574static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
575{
576 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
577}
578
ac58c3f0 579static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 580{
7429e9d4 581 clock->m = i9xx_dpll_compute_m(clock);
79e53945 582 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 583 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
584 return;
fb03ac01
VS		 585 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
586 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
79e53945
JB		 587}
588
ef9348c8
CML		 589static void chv_clock(int refclk, intel_clock_t *clock)
590{
591 clock->m = clock->m1 * clock->m2;
592 clock->p = clock->p1 * clock->p2;
593 if (WARN_ON(clock->n == 0 || clock->p == 0))
594 return;
595 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
596 clock->n << 22);
597 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
598}
599
7c04d1d9 600#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 601/**
602 * Returns whether the given set of divisors are valid for a given refclk with
603 * the given connectors.
604 */
605
1b894b59
CW		 606static bool intel_PLL_is_valid(struct drm_device *dev,
607 const intel_limit_t *limit,
608 const intel_clock_t *clock)
79e53945 609{
f01b7962
VS		 610 if (clock->n < limit->n.min || limit->n.max < clock->n)
611 INTELPllInvalid("n out of range\n");
79e53945 612 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 613 INTELPllInvalid("p1 out of range\n");
79e53945 614 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 615 INTELPllInvalid("m2 out of range\n");
79e53945 616 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 617 INTELPllInvalid("m1 out of range\n");
f01b7962 618
5ab7b0b7 619 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
f01b7962
VS		 620 if (clock->m1 <= clock->m2)
621 INTELPllInvalid("m1 <= m2\n");
622
5ab7b0b7 623 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
f01b7962
VS		 624 if (clock->p < limit->p.min || limit->p.max < clock->p)
625 INTELPllInvalid("p out of range\n");
626 if (clock->m < limit->m.min || limit->m.max < clock->m)
627 INTELPllInvalid("m out of range\n");
628 }
629
79e53945 630 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 631 INTELPllInvalid("vco out of range\n");
79e53945
JB		 632 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
633 * connector, etc., rather than just a single range.
634 */
635 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 636 INTELPllInvalid("dot out of range\n");
79e53945
JB		 637
638 return true;
639}
640
d4906093 641static bool
a93e255f
ACO		 642i9xx_find_best_dpll(const intel_limit_t *limit,
643 struct intel_crtc_state *crtc_state,
cec2f356
SP		 644 int target, int refclk, intel_clock_t *match_clock,
645 intel_clock_t *best_clock)
79e53945 646{
a93e255f 647 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 648 struct drm_device *dev = crtc->base.dev;
79e53945 649 intel_clock_t clock;
79e53945
JB		 650 int err = target;
651
a93e255f 652 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 653 /*
a210b028
DV		 654 * For LVDS just rely on its current settings for dual-channel.
655 * We haven't figured out how to reliably set up different
656 * single/dual channel state, if we even can.
79e53945 657 */
1974cad0 658 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 659 clock.p2 = limit->p2.p2_fast;
660 else
661 clock.p2 = limit->p2.p2_slow;
662 } else {
663 if (target < limit->p2.dot_limit)
664 clock.p2 = limit->p2.p2_slow;
665 else
666 clock.p2 = limit->p2.p2_fast;
667 }
668
0206e353 669 memset(best_clock, 0, sizeof(*best_clock));
79e53945 670
42158660
ZY		 671 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
672 clock.m1++) {
673 for (clock.m2 = limit->m2.min;
674 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 675 if (clock.m2 >= clock.m1)
42158660
ZY		 676 break;
677 for (clock.n = limit->n.min;
678 clock.n <= limit->n.max; clock.n++) {
679 for (clock.p1 = limit->p1.min;
680 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 681 int this_err;
682
ac58c3f0
DV		 683 i9xx_clock(refclk, &clock);
684 if (!intel_PLL_is_valid(dev, limit,
685 &clock))
686 continue;
687 if (match_clock &&
688 clock.p != match_clock->p)
689 continue;
690
691 this_err = abs(clock.dot - target);
692 if (this_err < err) {
693 *best_clock = clock;
694 err = this_err;
695 }
696 }
697 }
698 }
699 }
700
701 return (err != target);
702}
703
704static bool
a93e255f
ACO		 705pnv_find_best_dpll(const intel_limit_t *limit,
706 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 707 int target, int refclk, intel_clock_t *match_clock,
708 intel_clock_t *best_clock)
79e53945 709{
a93e255f 710 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 711 struct drm_device *dev = crtc->base.dev;
79e53945 712 intel_clock_t clock;
79e53945
JB		 713 int err = target;
714
a93e255f 715 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 716 /*
a210b028
DV		 717 * For LVDS just rely on its current settings for dual-channel.
718 * We haven't figured out how to reliably set up different
719 * single/dual channel state, if we even can.
79e53945 720 */
1974cad0 721 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 722 clock.p2 = limit->p2.p2_fast;
723 else
724 clock.p2 = limit->p2.p2_slow;
725 } else {
726 if (target < limit->p2.dot_limit)
727 clock.p2 = limit->p2.p2_slow;
728 else
729 clock.p2 = limit->p2.p2_fast;
730 }
731
0206e353 732 memset(best_clock, 0, sizeof(*best_clock));
79e53945 733
42158660
ZY		 734 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
735 clock.m1++) {
736 for (clock.m2 = limit->m2.min;
737 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 738 for (clock.n = limit->n.min;
739 clock.n <= limit->n.max; clock.n++) {
740 for (clock.p1 = limit->p1.min;
741 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 742 int this_err;
743
ac58c3f0 744 pineview_clock(refclk, &clock);
1b894b59
CW		 745 if (!intel_PLL_is_valid(dev, limit,
746 &clock))
79e53945 747 continue;
cec2f356
SP		 748 if (match_clock &&
749 clock.p != match_clock->p)
750 continue;
79e53945
JB		 751
752 this_err = abs(clock.dot - target);
753 if (this_err < err) {
754 *best_clock = clock;
755 err = this_err;
756 }
757 }
758 }
759 }
760 }
761
762 return (err != target);
763}
764
d4906093 765static bool
a93e255f
ACO		 766g4x_find_best_dpll(const intel_limit_t *limit,
767 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 768 int target, int refclk, intel_clock_t *match_clock,
769 intel_clock_t *best_clock)
d4906093 770{
a93e255f 771 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 772 struct drm_device *dev = crtc->base.dev;
d4906093
ML		 773 intel_clock_t clock;
774 int max_n;
775 bool found;
6ba770dc
AJ		 776 /* approximately equals target * 0.00585 */
777 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 778 found = false;
779
a93e255f 780 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 781 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 782 clock.p2 = limit->p2.p2_fast;
783 else
784 clock.p2 = limit->p2.p2_slow;
785 } else {
786 if (target < limit->p2.dot_limit)
787 clock.p2 = limit->p2.p2_slow;
788 else
789 clock.p2 = limit->p2.p2_fast;
790 }
791
792 memset(best_clock, 0, sizeof(*best_clock));
793 max_n = limit->n.max;
f77f13e2 794 /* based on hardware requirement, prefer smaller n to precision */
d4906093 795 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 796 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 797 for (clock.m1 = limit->m1.max;
798 clock.m1 >= limit->m1.min; clock.m1--) {
799 for (clock.m2 = limit->m2.max;
800 clock.m2 >= limit->m2.min; clock.m2--) {
801 for (clock.p1 = limit->p1.max;
802 clock.p1 >= limit->p1.min; clock.p1--) {
803 int this_err;
804
ac58c3f0 805 i9xx_clock(refclk, &clock);
1b894b59
CW		 806 if (!intel_PLL_is_valid(dev, limit,
807 &clock))
d4906093 808 continue;
1b894b59
CW		 809
810 this_err = abs(clock.dot - target);
d4906093
ML		 811 if (this_err < err_most) {
812 *best_clock = clock;
813 err_most = this_err;
814 max_n = clock.n;
815 found = true;
816 }
817 }
818 }
819 }
820 }
2c07245f
ZW		 821 return found;
822}
823
d5dd62bd
ID		 824/*
825 * Check if the calculated PLL configuration is more optimal compared to the
826 * best configuration and error found so far. Return the calculated error.
827 */
828static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
829 const intel_clock_t *calculated_clock,
830 const intel_clock_t *best_clock,
831 unsigned int best_error_ppm,
832 unsigned int *error_ppm)
833{
9ca3ba01
ID		 834 /*
835 * For CHV ignore the error and consider only the P value.
836 * Prefer a bigger P value based on HW requirements.
837 */
838 if (IS_CHERRYVIEW(dev)) {
839 *error_ppm = 0;
840
841 return calculated_clock->p > best_clock->p;
842 }
843
24be4e46
ID		 844 if (WARN_ON_ONCE(!target_freq))
845 return false;
846
d5dd62bd
ID		 847 *error_ppm = div_u64(1000000ULL *
848 abs(target_freq - calculated_clock->dot),
849 target_freq);
850 /*
851 * Prefer a better P value over a better (smaller) error if the error
852 * is small. Ensure this preference for future configurations too by
853 * setting the error to 0.
854 */
855 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
856 *error_ppm = 0;
857
858 return true;
859 }
860
861 return *error_ppm + 10 < best_error_ppm;
862}
863
a0c4da24 864static bool
a93e255f
ACO		 865vlv_find_best_dpll(const intel_limit_t *limit,
866 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 867 int target, int refclk, intel_clock_t *match_clock,
868 intel_clock_t *best_clock)
a0c4da24 869{
a93e255f 870 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 871 struct drm_device *dev = crtc->base.dev;
6b4bf1c4 872 intel_clock_t clock;
69e4f900 873 unsigned int bestppm = 1000000;
27e639bf
VS		 874 /* min update 19.2 MHz */
875 int max_n = min(limit->n.max, refclk / 19200);
49e497ef 876 bool found = false;
a0c4da24 877
6b4bf1c4
VS		 878 target *= 5; /* fast clock */
879
880 memset(best_clock, 0, sizeof(*best_clock));
a0c4da24
JB		 881
882 /* based on hardware requirement, prefer smaller n to precision */
27e639bf 883 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
811bbf05 884 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
889059d8 885 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
c1a9ae43 886 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
6b4bf1c4 887 clock.p = clock.p1 * clock.p2;
a0c4da24 888 /* based on hardware requirement, prefer bigger m1,m2 values */
6b4bf1c4 889 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
d5dd62bd 890 unsigned int ppm;
69e4f900 891
6b4bf1c4
VS		 892 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
893 refclk * clock.m1);
894
895 vlv_clock(refclk, &clock);
43b0ac53 896
f01b7962
VS		 897 if (!intel_PLL_is_valid(dev, limit,
898 &clock))
43b0ac53
VS		 899 continue;
900
d5dd62bd
ID		 901 if (!vlv_PLL_is_optimal(dev, target,
902 &clock,
903 best_clock,
904 bestppm, &ppm))
905 continue;
6b4bf1c4 906
d5dd62bd
ID		 907 *best_clock = clock;
908 bestppm = ppm;
909 found = true;
a0c4da24
JB		 910 }
911 }
912 }
913 }
a0c4da24 914
49e497ef 915 return found;
a0c4da24 916}
a4fc5ed6 917
ef9348c8 918static bool
a93e255f
ACO		 919chv_find_best_dpll(const intel_limit_t *limit,
920 struct intel_crtc_state *crtc_state,
ef9348c8
CML		 921 int target, int refclk, intel_clock_t *match_clock,
922 intel_clock_t *best_clock)
923{
a93e255f 924 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 925 struct drm_device *dev = crtc->base.dev;
9ca3ba01 926 unsigned int best_error_ppm;
ef9348c8
CML		 927 intel_clock_t clock;
928 uint64_t m2;
929 int found = false;
930
931 memset(best_clock, 0, sizeof(*best_clock));
9ca3ba01 932 best_error_ppm = 1000000;
ef9348c8
CML		 933
934 /*
935 * Based on hardware doc, the n always set to 1, and m1 always
936 * set to 2. If requires to support 200Mhz refclk, we need to
937 * revisit this because n may not 1 anymore.
938 */
939 clock.n = 1, clock.m1 = 2;
940 target *= 5; /* fast clock */
941
942 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
943 for (clock.p2 = limit->p2.p2_fast;
944 clock.p2 >= limit->p2.p2_slow;
945 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
9ca3ba01 946 unsigned int error_ppm;
ef9348c8
CML		 947
948 clock.p = clock.p1 * clock.p2;
949
950 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
951 clock.n) << 22, refclk * clock.m1);
952
953 if (m2 > INT_MAX/clock.m1)
954 continue;
955
956 clock.m2 = m2;
957
958 chv_clock(refclk, &clock);
959
960 if (!intel_PLL_is_valid(dev, limit, &clock))
961 continue;
962
9ca3ba01
ID		 963 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
964 best_error_ppm, &error_ppm))
965 continue;
966
967 *best_clock = clock;
968 best_error_ppm = error_ppm;
969 found = true;
ef9348c8
CML		 970 }
971 }
972
973 return found;
974}
975
5ab7b0b7
ID		 976bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
977 intel_clock_t *best_clock)
978{
979 int refclk = i9xx_get_refclk(crtc_state, 0);
980
981 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
982 target_clock, refclk, NULL, best_clock);
983}
984
20ddf665
VS		 985bool intel_crtc_active(struct drm_crtc *crtc)
986{
987 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
988
989 /* Be paranoid as we can arrive here with only partial
990 * state retrieved from the hardware during setup.
991 *
241bfc38 992 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS		 993 * as Haswell has gained clock readout/fastboot support.
994 *
66e514c1 995 * We can ditch the crtc->primary->fb check as soon as we can
20ddf665 996 * properly reconstruct framebuffers.
c3d1f436
MR		 997 *
998 * FIXME: The intel_crtc->active here should be switched to
999 * crtc->state->active once we have proper CRTC states wired up
1000 * for atomic.
20ddf665 1001 */
c3d1f436 1002 return intel_crtc->active && crtc->primary->state->fb &&
6e3c9717 1003 intel_crtc->config->base.adjusted_mode.crtc_clock;
20ddf665
VS		 1004}
1005
a5c961d1
PZ		 1006enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1007 enum pipe pipe)
1008{
1009 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1010 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1011
6e3c9717 1012 return intel_crtc->config->cpu_transcoder;
a5c961d1
PZ		 1013}
1014
fbf49ea2
VS		 1015static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1016{
1017 struct drm_i915_private *dev_priv = dev->dev_private;
1018 u32 reg = PIPEDSL(pipe);
1019 u32 line1, line2;
1020 u32 line_mask;
1021
1022 if (IS_GEN2(dev))
1023 line_mask = DSL_LINEMASK_GEN2;
1024 else
1025 line_mask = DSL_LINEMASK_GEN3;
1026
1027 line1 = I915_READ(reg) & line_mask;
1028 mdelay(5);
1029 line2 = I915_READ(reg) & line_mask;
1030
1031 return line1 == line2;
1032}
1033
ab7ad7f6
KP		 1034/*
1035 * intel_wait_for_pipe_off - wait for pipe to turn off
575f7ab7 1036 * @crtc: crtc whose pipe to wait for
9d0498a2
JB		 1037 *
1038 * After disabling a pipe, we can't wait for vblank in the usual way,
1039 * spinning on the vblank interrupt status bit, since we won't actually
1040 * see an interrupt when the pipe is disabled.
1041 *
ab7ad7f6
KP		 1042 * On Gen4 and above:
1043 * wait for the pipe register state bit to turn off
1044 *
1045 * Otherwise:
1046 * wait for the display line value to settle (it usually
1047 * ends up stopping at the start of the next frame).
58e10eb9 1048 *
9d0498a2 1049 */
575f7ab7 1050static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
9d0498a2 1051{
575f7ab7 1052 struct drm_device *dev = crtc->base.dev;
9d0498a2 1053 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1054 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 1055 enum pipe pipe = crtc->pipe;
ab7ad7f6
KP		 1056
1057 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1058 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 1059
1060 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1061 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1062 100))
284637d9 1063 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1064 } else {
ab7ad7f6 1065 /* Wait for the display line to settle */
fbf49ea2 1066 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
284637d9 1067 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1068 }
79e53945
JB		 1069}
1070
b0ea7d37
DL		 1071/*
1072 * ibx_digital_port_connected - is the specified port connected?
1073 * @dev_priv: i915 private structure
1074 * @port: the port to test
1075 *
1076 * Returns true if @port is connected, false otherwise.
1077 */
1078bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1079 struct intel_digital_port *port)
1080{
1081 u32 bit;
1082
c36346e3 1083 if (HAS_PCH_IBX(dev_priv->dev)) {
eba905b2 1084 switch (port->port) {
c36346e3
DL		 1085 case PORT_B:
1086 bit = SDE_PORTB_HOTPLUG;
1087 break;
1088 case PORT_C:
1089 bit = SDE_PORTC_HOTPLUG;
1090 break;
1091 case PORT_D:
1092 bit = SDE_PORTD_HOTPLUG;
1093 break;
1094 default:
1095 return true;
1096 }
1097 } else {
eba905b2 1098 switch (port->port) {
c36346e3
DL		 1099 case PORT_B:
1100 bit = SDE_PORTB_HOTPLUG_CPT;
1101 break;
1102 case PORT_C:
1103 bit = SDE_PORTC_HOTPLUG_CPT;
1104 break;
1105 case PORT_D:
1106 bit = SDE_PORTD_HOTPLUG_CPT;
1107 break;
1108 default:
1109 return true;
1110 }
b0ea7d37
DL		 1111 }
1112
1113 return I915_READ(SDEISR) & bit;
1114}
1115
b24e7179
JB		 1116static const char *state_string(bool enabled)
1117{
1118 return enabled ? "on" : "off";
1119}
1120
1121/* Only for pre-ILK configs */
55607e8a
DV		 1122void assert_pll(struct drm_i915_private *dev_priv,
1123 enum pipe pipe, bool state)
b24e7179
JB		 1124{
1125 int reg;
1126 u32 val;
1127 bool cur_state;
1128
1129 reg = DPLL(pipe);
1130 val = I915_READ(reg);
1131 cur_state = !!(val & DPLL_VCO_ENABLE);
e2c719b7 1132 I915_STATE_WARN(cur_state != state,
b24e7179
JB		 1133 "PLL state assertion failure (expected %s, current %s)\n",
1134 state_string(state), state_string(cur_state));
1135}
b24e7179 1136
23538ef1
JN		 1137/* XXX: the dsi pll is shared between MIPI DSI ports */
1138static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1139{
1140 u32 val;
1141 bool cur_state;
1142
1143 mutex_lock(&dev_priv->dpio_lock);
1144 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1145 mutex_unlock(&dev_priv->dpio_lock);
1146
1147 cur_state = val & DSI_PLL_VCO_EN;
e2c719b7 1148 I915_STATE_WARN(cur_state != state,
23538ef1
JN		 1149 "DSI PLL state assertion failure (expected %s, current %s)\n",
1150 state_string(state), state_string(cur_state));
1151}
1152#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1153#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1154
55607e8a 1155struct intel_shared_dpll *
e2b78267
DV		 1156intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1157{
1158 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1159
6e3c9717 1160 if (crtc->config->shared_dpll < 0)
e2b78267
DV		 1161 return NULL;
1162
6e3c9717 1163 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
e2b78267
DV		 1164}
1165
040484af 1166/* For ILK+ */
55607e8a
DV		 1167void assert_shared_dpll(struct drm_i915_private *dev_priv,
1168 struct intel_shared_dpll *pll,
1169 bool state)
040484af 1170{
040484af 1171 bool cur_state;
5358901f 1172 struct intel_dpll_hw_state hw_state;
040484af 1173
92b27b08 1174 if (WARN (!pll,
46edb027 1175 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 1176 return;
ee7b9f93 1177
5358901f 1178 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
e2c719b7 1179 I915_STATE_WARN(cur_state != state,
5358901f
DV		 1180 "%s assertion failure (expected %s, current %s)\n",
1181 pll->name, state_string(state), state_string(cur_state));
040484af 1182}
040484af
JB		 1183
1184static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1185 enum pipe pipe, bool state)
1186{
1187 int reg;
1188 u32 val;
1189 bool cur_state;
ad80a810
PZ		 1190 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1191 pipe);
040484af 1192
affa9354
PZ		 1193 if (HAS_DDI(dev_priv->dev)) {
1194 /* DDI does not have a specific FDI_TX register */
ad80a810 1195 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1196 val = I915_READ(reg);
ad80a810 1197 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1198 } else {
1199 reg = FDI_TX_CTL(pipe);
1200 val = I915_READ(reg);
1201 cur_state = !!(val & FDI_TX_ENABLE);
1202 }
e2c719b7 1203 I915_STATE_WARN(cur_state != state,
040484af
JB		 1204 "FDI TX state assertion failure (expected %s, current %s)\n",
1205 state_string(state), state_string(cur_state));
1206}
1207#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1208#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1209
1210static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1211 enum pipe pipe, bool state)
1212{
1213 int reg;
1214 u32 val;
1215 bool cur_state;
1216
d63fa0dc
PZ		 1217 reg = FDI_RX_CTL(pipe);
1218 val = I915_READ(reg);
1219 cur_state = !!(val & FDI_RX_ENABLE);
e2c719b7 1220 I915_STATE_WARN(cur_state != state,
040484af
JB		 1221 "FDI RX state assertion failure (expected %s, current %s)\n",
1222 state_string(state), state_string(cur_state));
1223}
1224#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1225#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1226
1227static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1228 enum pipe pipe)
1229{
1230 int reg;
1231 u32 val;
1232
1233 /* ILK FDI PLL is always enabled */
3d13ef2e 1234 if (INTEL_INFO(dev_priv->dev)->gen == 5)
040484af
JB		 1235 return;
1236
bf507ef7 1237 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1238 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1239 return;
1240
040484af
JB		 1241 reg = FDI_TX_CTL(pipe);
1242 val = I915_READ(reg);
e2c719b7 1243 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
040484af
JB		 1244}
1245
55607e8a
DV		 1246void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1247 enum pipe pipe, bool state)
040484af
JB		 1248{
1249 int reg;
1250 u32 val;
55607e8a 1251 bool cur_state;
040484af
JB		 1252
1253 reg = FDI_RX_CTL(pipe);
1254 val = I915_READ(reg);
55607e8a 1255 cur_state = !!(val & FDI_RX_PLL_ENABLE);
e2c719b7 1256 I915_STATE_WARN(cur_state != state,
55607e8a
DV		 1257 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1258 state_string(state), state_string(cur_state));
040484af
JB		 1259}
1260
b680c37a
DV		 1261void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1262 enum pipe pipe)
ea0760cf 1263{
bedd4dba
JN		 1264 struct drm_device *dev = dev_priv->dev;
1265 int pp_reg;
ea0760cf
JB		 1266 u32 val;
1267 enum pipe panel_pipe = PIPE_A;
0de3b485 1268 bool locked = true;
ea0760cf 1269
bedd4dba
JN		 1270 if (WARN_ON(HAS_DDI(dev)))
1271 return;
1272
1273 if (HAS_PCH_SPLIT(dev)) {
1274 u32 port_sel;
1275
ea0760cf 1276 pp_reg = PCH_PP_CONTROL;
bedd4dba
JN		 1277 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1278
1279 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1280 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1281 panel_pipe = PIPE_B;
1282 /* XXX: else fix for eDP */
1283 } else if (IS_VALLEYVIEW(dev)) {
1284 /* presumably write lock depends on pipe, not port select */
1285 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1286 panel_pipe = pipe;
ea0760cf
JB		 1287 } else {
1288 pp_reg = PP_CONTROL;
bedd4dba
JN		 1289 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1290 panel_pipe = PIPE_B;
ea0760cf
JB		 1291 }
1292
1293 val = I915_READ(pp_reg);
1294 if (!(val & PANEL_POWER_ON) ||
ec49ba2d 1295 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
ea0760cf
JB		 1296 locked = false;
1297
e2c719b7 1298 I915_STATE_WARN(panel_pipe == pipe && locked,
ea0760cf 1299 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1300 pipe_name(pipe));
ea0760cf
JB		 1301}
1302
93ce0ba6
JN		 1303static void assert_cursor(struct drm_i915_private *dev_priv,
1304 enum pipe pipe, bool state)
1305{
1306 struct drm_device *dev = dev_priv->dev;
1307 bool cur_state;
1308
d9d82081 1309 if (IS_845G(dev) || IS_I865G(dev))
93ce0ba6 1310 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
d9d82081 1311 else
5efb3e28 1312 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
93ce0ba6 1313
e2c719b7 1314 I915_STATE_WARN(cur_state != state,
93ce0ba6
JN		 1315 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1316 pipe_name(pipe), state_string(state), state_string(cur_state));
1317}
1318#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1319#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1320
b840d907
JB		 1321void assert_pipe(struct drm_i915_private *dev_priv,
1322 enum pipe pipe, bool state)
b24e7179
JB		 1323{
1324 int reg;
1325 u32 val;
63d7bbe9 1326 bool cur_state;
702e7a56
PZ		 1327 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1328 pipe);
b24e7179 1329
b6b5d049
VS		 1330 /* if we need the pipe quirk it must be always on */
1331 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1332 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8e636784
DV		 1333 state = true;
1334
f458ebbc 1335 if (!intel_display_power_is_enabled(dev_priv,
b97186f0 1336 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1337 cur_state = false;
1338 } else {
1339 reg = PIPECONF(cpu_transcoder);
1340 val = I915_READ(reg);
1341 cur_state = !!(val & PIPECONF_ENABLE);
1342 }
1343
e2c719b7 1344 I915_STATE_WARN(cur_state != state,
63d7bbe9 1345 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1346 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1347}
1348
931872fc
CW		 1349static void assert_plane(struct drm_i915_private *dev_priv,
1350 enum plane plane, bool state)
b24e7179
JB		 1351{
1352 int reg;
1353 u32 val;
931872fc 1354 bool cur_state;
b24e7179
JB		 1355
1356 reg = DSPCNTR(plane);
1357 val = I915_READ(reg);
931872fc 1358 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
e2c719b7 1359 I915_STATE_WARN(cur_state != state,
931872fc
CW		 1360 "plane %c assertion failure (expected %s, current %s)\n",
1361 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1362}
1363
931872fc
CW		 1364#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1365#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1366
b24e7179
JB		 1367static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1368 enum pipe pipe)
1369{
653e1026 1370 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1371 int reg, i;
1372 u32 val;
1373 int cur_pipe;
1374
653e1026
VS		 1375 /* Primary planes are fixed to pipes on gen4+ */
1376 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1377 reg = DSPCNTR(pipe);
1378 val = I915_READ(reg);
e2c719b7 1379 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
28c05794
AJ		 1380 "plane %c assertion failure, should be disabled but not\n",
1381 plane_name(pipe));
19ec1358 1382 return;
28c05794 1383 }
19ec1358 1384
b24e7179 1385 /* Need to check both planes against the pipe */
055e393f 1386 for_each_pipe(dev_priv, i) {
b24e7179
JB		 1387 reg = DSPCNTR(i);
1388 val = I915_READ(reg);
1389 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1390 DISPPLANE_SEL_PIPE_SHIFT;
e2c719b7 1391 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1392 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1393 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1394 }
1395}
1396
19332d7a
JB		 1397static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1398 enum pipe pipe)
1399{
20674eef 1400 struct drm_device *dev = dev_priv->dev;
1fe47785 1401 int reg, sprite;
19332d7a
JB		 1402 u32 val;
1403
7feb8b88 1404 if (INTEL_INFO(dev)->gen >= 9) {
3bdcfc0c 1405 for_each_sprite(dev_priv, pipe, sprite) {
7feb8b88 1406 val = I915_READ(PLANE_CTL(pipe, sprite));
e2c719b7 1407 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
7feb8b88
DL		 1408 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1409 sprite, pipe_name(pipe));
1410 }
1411 } else if (IS_VALLEYVIEW(dev)) {
3bdcfc0c 1412 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 1413 reg = SPCNTR(pipe, sprite);
20674eef 1414 val = I915_READ(reg);
e2c719b7 1415 I915_STATE_WARN(val & SP_ENABLE,
20674eef 1416 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1fe47785 1417 sprite_name(pipe, sprite), pipe_name(pipe));
20674eef
VS		 1418 }
1419 } else if (INTEL_INFO(dev)->gen >= 7) {
1420 reg = SPRCTL(pipe);
19332d7a 1421 val = I915_READ(reg);
e2c719b7 1422 I915_STATE_WARN(val & SPRITE_ENABLE,
06da8da2 1423 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1424 plane_name(pipe), pipe_name(pipe));
1425 } else if (INTEL_INFO(dev)->gen >= 5) {
1426 reg = DVSCNTR(pipe);
19332d7a 1427 val = I915_READ(reg);
e2c719b7 1428 I915_STATE_WARN(val & DVS_ENABLE,
06da8da2 1429 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1430 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1431 }
1432}
1433
08c71e5e
VS		 1434static void assert_vblank_disabled(struct drm_crtc *crtc)
1435{
e2c719b7 1436 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
08c71e5e
VS		 1437 drm_crtc_vblank_put(crtc);
1438}
1439
89eff4be 1440static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
92f2584a
JB		 1441{
1442 u32 val;
1443 bool enabled;
1444
e2c719b7 1445 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
9d82aa17 1446
92f2584a
JB		 1447 val = I915_READ(PCH_DREF_CONTROL);
1448 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1449 DREF_SUPERSPREAD_SOURCE_MASK));
e2c719b7 1450 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
92f2584a
JB		 1451}
1452
ab9412ba
DV		 1453static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1454 enum pipe pipe)
92f2584a
JB		 1455{
1456 int reg;
1457 u32 val;
1458 bool enabled;
1459
ab9412ba 1460 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1461 val = I915_READ(reg);
1462 enabled = !!(val & TRANS_ENABLE);
e2c719b7 1463 I915_STATE_WARN(enabled,
9db4a9c7
JB		 1464 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1465 pipe_name(pipe));
92f2584a
JB		 1466}
1467
4e634389
KP		 1468static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1469 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1470{
1471 if ((val & DP_PORT_EN) == 0)
1472 return false;
1473
1474 if (HAS_PCH_CPT(dev_priv->dev)) {
1475 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1476 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1477 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1478 return false;
44f37d1f
CML		 1479 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1480 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1481 return false;
f0575e92
KP		 1482 } else {
1483 if ((val & DP_PIPE_MASK) != (pipe << 30))
1484 return false;
1485 }
1486 return true;
1487}
1488
1519b995
KP		 1489static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1490 enum pipe pipe, u32 val)
1491{
dc0fa718 1492 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1493 return false;
1494
1495 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1496 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995 1497 return false;
44f37d1f
CML		 1498 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1499 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1500 return false;
1519b995 1501 } else {
dc0fa718 1502 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1503 return false;
1504 }
1505 return true;
1506}
1507
1508static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1509 enum pipe pipe, u32 val)
1510{
1511 if ((val & LVDS_PORT_EN) == 0)
1512 return false;
1513
1514 if (HAS_PCH_CPT(dev_priv->dev)) {
1515 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1516 return false;
1517 } else {
1518 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1519 return false;
1520 }
1521 return true;
1522}
1523
1524static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1525 enum pipe pipe, u32 val)
1526{
1527 if ((val & ADPA_DAC_ENABLE) == 0)
1528 return false;
1529 if (HAS_PCH_CPT(dev_priv->dev)) {
1530 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1531 return false;
1532 } else {
1533 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1534 return false;
1535 }
1536 return true;
1537}
1538
291906f1 1539static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1540 enum pipe pipe, int reg, u32 port_sel)
291906f1 1541{
47a05eca 1542 u32 val = I915_READ(reg);
e2c719b7 1543 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1544 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1545 reg, pipe_name(pipe));
de9a35ab 1546
e2c719b7 1547 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
75c5da27 1548 && (val & DP_PIPEB_SELECT),
de9a35ab 1549 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1550}
1551
1552static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1553 enum pipe pipe, int reg)
1554{
47a05eca 1555 u32 val = I915_READ(reg);
e2c719b7 1556 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1557 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1558 reg, pipe_name(pipe));
de9a35ab 1559
e2c719b7 1560 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1561 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1562 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1563}
1564
1565static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1566 enum pipe pipe)
1567{
1568 int reg;
1569 u32 val;
291906f1 1570
f0575e92
KP		 1571 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1572 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1573 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1574
1575 reg = PCH_ADPA;
1576 val = I915_READ(reg);
e2c719b7 1577 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1578 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1579 pipe_name(pipe));
291906f1
JB		 1580
1581 reg = PCH_LVDS;
1582 val = I915_READ(reg);
e2c719b7 1583 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1584 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1585 pipe_name(pipe));
291906f1 1586
e2debe91
PZ		 1587 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1588 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1589 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1590}
1591
40e9cf64
JB		 1592static void intel_init_dpio(struct drm_device *dev)
1593{
1594 struct drm_i915_private *dev_priv = dev->dev_private;
1595
1596 if (!IS_VALLEYVIEW(dev))
1597 return;
1598
a09caddd
CML		 1599 /*
1600 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1601 * CHV x1 PHY (DP/HDMI D)
1602 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1603 */
1604 if (IS_CHERRYVIEW(dev)) {
1605 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1606 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1607 } else {
1608 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1609 }
5382f5f3
JB		 1610}
1611
d288f65f 1612static void vlv_enable_pll(struct intel_crtc *crtc,
5cec258b 1613 const struct intel_crtc_state *pipe_config)
87442f73 1614{
426115cf
DV		 1615 struct drm_device *dev = crtc->base.dev;
1616 struct drm_i915_private *dev_priv = dev->dev_private;
1617 int reg = DPLL(crtc->pipe);
d288f65f 1618 u32 dpll = pipe_config->dpll_hw_state.dpll;
87442f73 1619
426115cf 1620 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1621
1622 /* No really, not for ILK+ */
1623 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1624
1625 /* PLL is protected by panel, make sure we can write it */
6a9e7363 1626 if (IS_MOBILE(dev_priv->dev))
426115cf 1627 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1628
426115cf
DV		 1629 I915_WRITE(reg, dpll);
1630 POSTING_READ(reg);
1631 udelay(150);
1632
1633 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1634 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1635
d288f65f 1636 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
426115cf 1637 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1638
1639 /* We do this three times for luck */
426115cf 1640 I915_WRITE(reg, dpll);
87442f73
DV		 1641 POSTING_READ(reg);
1642 udelay(150); /* wait for warmup */
426115cf 1643 I915_WRITE(reg, dpll);
87442f73
DV		 1644 POSTING_READ(reg);
1645 udelay(150); /* wait for warmup */
426115cf 1646 I915_WRITE(reg, dpll);
87442f73
DV		 1647 POSTING_READ(reg);
1648 udelay(150); /* wait for warmup */
1649}
1650
d288f65f 1651static void chv_enable_pll(struct intel_crtc *crtc,
5cec258b 1652 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 1653{
1654 struct drm_device *dev = crtc->base.dev;
1655 struct drm_i915_private *dev_priv = dev->dev_private;
1656 int pipe = crtc->pipe;
1657 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9d556c99
CML		 1658 u32 tmp;
1659
1660 assert_pipe_disabled(dev_priv, crtc->pipe);
1661
1662 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1663
1664 mutex_lock(&dev_priv->dpio_lock);
1665
1666 /* Enable back the 10bit clock to display controller */
1667 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1668 tmp |= DPIO_DCLKP_EN;
1669 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1670
1671 /*
1672 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1673 */
1674 udelay(1);
1675
1676 /* Enable PLL */
d288f65f 1677 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
9d556c99
CML		 1678
1679 /* Check PLL is locked */
a11b0703 1680 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
9d556c99
CML		 1681 DRM_ERROR("PLL %d failed to lock\n", pipe);
1682
a11b0703 1683 /* not sure when this should be written */
d288f65f 1684 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
a11b0703
VS		 1685 POSTING_READ(DPLL_MD(pipe));
1686
9d556c99
CML		 1687 mutex_unlock(&dev_priv->dpio_lock);
1688}
1689
1c4e0274
VS		 1690static int intel_num_dvo_pipes(struct drm_device *dev)
1691{
1692 struct intel_crtc *crtc;
1693 int count = 0;
1694
1695 for_each_intel_crtc(dev, crtc)
1696 count += crtc->active &&
409ee761 1697 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1c4e0274
VS		 1698
1699 return count;
1700}
1701
66e3d5c0 1702static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1703{
66e3d5c0
DV		 1704 struct drm_device *dev = crtc->base.dev;
1705 struct drm_i915_private *dev_priv = dev->dev_private;
1706 int reg = DPLL(crtc->pipe);
6e3c9717 1707 u32 dpll = crtc->config->dpll_hw_state.dpll;
63d7bbe9 1708
66e3d5c0 1709 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1710
63d7bbe9 1711 /* No really, not for ILK+ */
3d13ef2e 1712 BUG_ON(INTEL_INFO(dev)->gen >= 5);
63d7bbe9
JB		 1713
1714 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1715 if (IS_MOBILE(dev) && !IS_I830(dev))
1716 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1717
1c4e0274
VS		 1718 /* Enable DVO 2x clock on both PLLs if necessary */
1719 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1720 /*
1721 * It appears to be important that we don't enable this
1722 * for the current pipe before otherwise configuring the
1723 * PLL. No idea how this should be handled if multiple
1724 * DVO outputs are enabled simultaneosly.
1725 */
1726 dpll |= DPLL_DVO_2X_MODE;
1727 I915_WRITE(DPLL(!crtc->pipe),
1728 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1729 }
66e3d5c0
DV		 1730
1731 /* Wait for the clocks to stabilize. */
1732 POSTING_READ(reg);
1733 udelay(150);
1734
1735 if (INTEL_INFO(dev)->gen >= 4) {
1736 I915_WRITE(DPLL_MD(crtc->pipe),
6e3c9717 1737 crtc->config->dpll_hw_state.dpll_md);
66e3d5c0
DV		 1738 } else {
1739 /* The pixel multiplier can only be updated once the
1740 * DPLL is enabled and the clocks are stable.
1741 *
1742 * So write it again.
1743 */
1744 I915_WRITE(reg, dpll);
1745 }
63d7bbe9
JB		 1746
1747 /* We do this three times for luck */
66e3d5c0 1748 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1749 POSTING_READ(reg);
1750 udelay(150); /* wait for warmup */
66e3d5c0 1751 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1752 POSTING_READ(reg);
1753 udelay(150); /* wait for warmup */
66e3d5c0 1754 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1755 POSTING_READ(reg);
1756 udelay(150); /* wait for warmup */
1757}
1758
1759/**
50b44a44 1760 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1761 * @dev_priv: i915 private structure
1762 * @pipe: pipe PLL to disable
1763 *
1764 * Disable the PLL for @pipe, making sure the pipe is off first.
1765 *
1766 * Note! This is for pre-ILK only.
1767 */
1c4e0274 1768static void i9xx_disable_pll(struct intel_crtc *crtc)
63d7bbe9 1769{
1c4e0274
VS		 1770 struct drm_device *dev = crtc->base.dev;
1771 struct drm_i915_private *dev_priv = dev->dev_private;
1772 enum pipe pipe = crtc->pipe;
1773
1774 /* Disable DVO 2x clock on both PLLs if necessary */
1775 if (IS_I830(dev) &&
409ee761 1776 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1c4e0274
VS		 1777 intel_num_dvo_pipes(dev) == 1) {
1778 I915_WRITE(DPLL(PIPE_B),
1779 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1780 I915_WRITE(DPLL(PIPE_A),
1781 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1782 }
1783
b6b5d049
VS		 1784 /* Don't disable pipe or pipe PLLs if needed */
1785 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1786 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
63d7bbe9
JB		 1787 return;
1788
1789 /* Make sure the pipe isn't still relying on us */
1790 assert_pipe_disabled(dev_priv, pipe);
1791
50b44a44
DV		 1792 I915_WRITE(DPLL(pipe), 0);
1793 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1794}
1795
f6071166
JB		 1796static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1797{
1798 u32 val = 0;
1799
1800 /* Make sure the pipe isn't still relying on us */
1801 assert_pipe_disabled(dev_priv, pipe);
1802
e5cbfbfb
ID		 1803 /*
1804 * Leave integrated clock source and reference clock enabled for pipe B.
1805 * The latter is needed for VGA hotplug / manual detection.
1806 */
f6071166 1807 if (pipe == PIPE_B)
e5cbfbfb 1808 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
f6071166
JB		 1809 I915_WRITE(DPLL(pipe), val);
1810 POSTING_READ(DPLL(pipe));
076ed3b2
CML		 1811
1812}
1813
1814static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1815{
d752048d 1816 enum dpio_channel port = vlv_pipe_to_channel(pipe);
076ed3b2
CML		 1817 u32 val;
1818
a11b0703
VS		 1819 /* Make sure the pipe isn't still relying on us */
1820 assert_pipe_disabled(dev_priv, pipe);
076ed3b2 1821
a11b0703 1822 /* Set PLL en = 0 */
d17ec4ce 1823 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
a11b0703
VS		 1824 if (pipe != PIPE_A)
1825 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1826 I915_WRITE(DPLL(pipe), val);
1827 POSTING_READ(DPLL(pipe));
d752048d
VS		 1828
1829 mutex_lock(&dev_priv->dpio_lock);
1830
1831 /* Disable 10bit clock to display controller */
1832 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1833 val &= ~DPIO_DCLKP_EN;
1834 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1835
61407f6d
VS		 1836 /* disable left/right clock distribution */
1837 if (pipe != PIPE_B) {
1838 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1839 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1840 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1841 } else {
1842 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1843 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1844 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1845 }
1846
d752048d 1847 mutex_unlock(&dev_priv->dpio_lock);
f6071166
JB		 1848}
1849
e4607fcf
CML		 1850void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1851 struct intel_digital_port *dport)
89b667f8
JB		 1852{
1853 u32 port_mask;
00fc31b7 1854 int dpll_reg;
89b667f8 1855
e4607fcf
CML		 1856 switch (dport->port) {
1857 case PORT_B:
89b667f8 1858 port_mask = DPLL_PORTB_READY_MASK;
00fc31b7 1859 dpll_reg = DPLL(0);
e4607fcf
CML		 1860 break;
1861 case PORT_C:
89b667f8 1862 port_mask = DPLL_PORTC_READY_MASK;
00fc31b7
CML		 1863 dpll_reg = DPLL(0);
1864 break;
1865 case PORT_D:
1866 port_mask = DPLL_PORTD_READY_MASK;
1867 dpll_reg = DPIO_PHY_STATUS;
e4607fcf
CML		 1868 break;
1869 default:
1870 BUG();
1871 }
89b667f8 1872
00fc31b7 1873 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
89b667f8 1874 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
00fc31b7 1875 port_name(dport->port), I915_READ(dpll_reg));
89b667f8
JB		 1876}
1877
b14b1055
DV		 1878static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1879{
1880 struct drm_device *dev = crtc->base.dev;
1881 struct drm_i915_private *dev_priv = dev->dev_private;
1882 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1883
be19f0ff
CW		 1884 if (WARN_ON(pll == NULL))
1885 return;
1886
3e369b76 1887 WARN_ON(!pll->config.crtc_mask);
b14b1055
DV		 1888 if (pll->active == 0) {
1889 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1890 WARN_ON(pll->on);
1891 assert_shared_dpll_disabled(dev_priv, pll);
1892
1893 pll->mode_set(dev_priv, pll);
1894 }
1895}
1896
92f2584a 1897/**
85b3894f 1898 * intel_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1899 * @dev_priv: i915 private structure
1900 * @pipe: pipe PLL to enable
1901 *
1902 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1903 * drives the transcoder clock.
1904 */
85b3894f 1905static void intel_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1906{
3d13ef2e
DL		 1907 struct drm_device *dev = crtc->base.dev;
1908 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1909 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1910
87a875bb 1911 if (WARN_ON(pll == NULL))
48da64a8
CW		 1912 return;
1913
3e369b76 1914 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1915 return;
ee7b9f93 1916
74dd6928 1917 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
46edb027 1918 pll->name, pll->active, pll->on,
e2b78267 1919 crtc->base.base.id);
92f2584a 1920
cdbd2316
DV		 1921 if (pll->active++) {
1922 WARN_ON(!pll->on);
e9d6944e 1923 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1924 return;
1925 }
f4a091c7 1926 WARN_ON(pll->on);
ee7b9f93 1927
bd2bb1b9
PZ		 1928 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1929
46edb027 1930 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1931 pll->enable(dev_priv, pll);
ee7b9f93 1932 pll->on = true;
92f2584a
JB		 1933}
1934
f6daaec2 1935static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1936{
3d13ef2e
DL		 1937 struct drm_device *dev = crtc->base.dev;
1938 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1939 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1940
92f2584a 1941 /* PCH only available on ILK+ */
3d13ef2e 1942 BUG_ON(INTEL_INFO(dev)->gen < 5);
87a875bb 1943 if (WARN_ON(pll == NULL))
ee7b9f93 1944 return;
92f2584a 1945
3e369b76 1946 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1947 return;
7a419866 1948
46edb027
DV		 1949 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1950 pll->name, pll->active, pll->on,
e2b78267 1951 crtc->base.base.id);
7a419866 1952
48da64a8 1953 if (WARN_ON(pll->active == 0)) {
e9d6944e 1954 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1955 return;
1956 }
1957
e9d6944e 1958 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1959 WARN_ON(!pll->on);
cdbd2316 1960 if (--pll->active)
7a419866 1961 return;
ee7b9f93 1962
46edb027 1963 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1964 pll->disable(dev_priv, pll);
ee7b9f93 1965 pll->on = false;
bd2bb1b9
PZ		 1966
1967 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
92f2584a
JB		 1968}
1969
b8a4f404
PZ		 1970static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1971 enum pipe pipe)
040484af 1972{
23670b32 1973 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1974 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1975 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1976 uint32_t reg, val, pipeconf_val;
040484af
JB		 1977
1978 /* PCH only available on ILK+ */
55522f37 1979 BUG_ON(!HAS_PCH_SPLIT(dev));
040484af
JB		 1980
1981 /* Make sure PCH DPLL is enabled */
e72f9fbf 1982 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1983 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1984
1985 /* FDI must be feeding us bits for PCH ports */
1986 assert_fdi_tx_enabled(dev_priv, pipe);
1987 assert_fdi_rx_enabled(dev_priv, pipe);
1988
23670b32
DV		 1989 if (HAS_PCH_CPT(dev)) {
1990 /* Workaround: Set the timing override bit before enabling the
1991 * pch transcoder. */
1992 reg = TRANS_CHICKEN2(pipe);
1993 val = I915_READ(reg);
1994 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1995 I915_WRITE(reg, val);
59c859d6 1996 }
23670b32 1997
ab9412ba 1998 reg = PCH_TRANSCONF(pipe);
040484af 1999 val = I915_READ(reg);
5f7f726d 2000 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 2001
2002 if (HAS_PCH_IBX(dev_priv->dev)) {
2003 /*
2004 * make the BPC in transcoder be consistent with
2005 * that in pipeconf reg.
2006 */
dfd07d72
DV		 2007 val &= ~PIPECONF_BPC_MASK;
2008 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 2009 }
5f7f726d
PZ		 2010
2011 val &= ~TRANS_INTERLACE_MASK;
2012 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6 2013 if (HAS_PCH_IBX(dev_priv->dev) &&
409ee761 2014 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7c26e5c6
PZ		 2015 val |= TRANS_LEGACY_INTERLACED_ILK;
2016 else
2017 val |= TRANS_INTERLACED;
5f7f726d
PZ		 2018 else
2019 val |= TRANS_PROGRESSIVE;
2020
040484af
JB		 2021 I915_WRITE(reg, val | TRANS_ENABLE);
2022 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 2023 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 2024}
2025
8fb033d7 2026static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 2027 enum transcoder cpu_transcoder)
040484af 2028{
8fb033d7 2029 u32 val, pipeconf_val;
8fb033d7
PZ		 2030
2031 /* PCH only available on ILK+ */
55522f37 2032 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
8fb033d7 2033
8fb033d7 2034 /* FDI must be feeding us bits for PCH ports */
1a240d4d 2035 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 2036 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 2037
223a6fdf
PZ		 2038 /* Workaround: set timing override bit. */
2039 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2040 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 2041 I915_WRITE(_TRANSA_CHICKEN2, val);
2042
25f3ef11 2043 val = TRANS_ENABLE;
937bb610 2044 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 2045
9a76b1c6
PZ		 2046 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2047 PIPECONF_INTERLACED_ILK)
a35f2679 2048 val |= TRANS_INTERLACED;
8fb033d7
PZ		 2049 else
2050 val |= TRANS_PROGRESSIVE;
2051
ab9412ba
DV		 2052 I915_WRITE(LPT_TRANSCONF, val);
2053 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 2054 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 2055}
2056
b8a4f404
PZ		 2057static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2058 enum pipe pipe)
040484af 2059{
23670b32
DV		 2060 struct drm_device *dev = dev_priv->dev;
2061 uint32_t reg, val;
040484af
JB		 2062
2063 /* FDI relies on the transcoder */
2064 assert_fdi_tx_disabled(dev_priv, pipe);
2065 assert_fdi_rx_disabled(dev_priv, pipe);
2066
291906f1
JB		 2067 /* Ports must be off as well */
2068 assert_pch_ports_disabled(dev_priv, pipe);
2069
ab9412ba 2070 reg = PCH_TRANSCONF(pipe);
040484af
JB		 2071 val = I915_READ(reg);
2072 val &= ~TRANS_ENABLE;
2073 I915_WRITE(reg, val);
2074 /* wait for PCH transcoder off, transcoder state */
2075 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 2076 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 2077
2078 if (!HAS_PCH_IBX(dev)) {
2079 /* Workaround: Clear the timing override chicken bit again. */
2080 reg = TRANS_CHICKEN2(pipe);
2081 val = I915_READ(reg);
2082 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2083 I915_WRITE(reg, val);
2084 }
040484af
JB		 2085}
2086
ab4d966c 2087static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 2088{
8fb033d7
PZ		 2089 u32 val;
2090
ab9412ba 2091 val = I915_READ(LPT_TRANSCONF);
8fb033d7 2092 val &= ~TRANS_ENABLE;
ab9412ba 2093 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 2094 /* wait for PCH transcoder off, transcoder state */
ab9412ba 2095 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 2096 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 2097
2098 /* Workaround: clear timing override bit. */
2099 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2100 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 2101 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 2102}
2103
b24e7179 2104/**
309cfea8 2105 * intel_enable_pipe - enable a pipe, asserting requirements
0372264a 2106 * @crtc: crtc responsible for the pipe
b24e7179 2107 *
0372264a 2108 * Enable @crtc's pipe, making sure that various hardware specific requirements
b24e7179 2109 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
b24e7179 2110 */
e1fdc473 2111static void intel_enable_pipe(struct intel_crtc *crtc)
b24e7179 2112{
0372264a
PZ		 2113 struct drm_device *dev = crtc->base.dev;
2114 struct drm_i915_private *dev_priv = dev->dev_private;
2115 enum pipe pipe = crtc->pipe;
702e7a56
PZ		 2116 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2117 pipe);
1a240d4d 2118 enum pipe pch_transcoder;
b24e7179
JB		 2119 int reg;
2120 u32 val;
2121
58c6eaa2 2122 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2123 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 2124 assert_sprites_disabled(dev_priv, pipe);
2125
681e5811 2126 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 2127 pch_transcoder = TRANSCODER_A;
2128 else
2129 pch_transcoder = pipe;
2130
b24e7179
JB		 2131 /*
2132 * A pipe without a PLL won't actually be able to drive bits from
2133 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2134 * need the check.
2135 */
50360403 2136 if (HAS_GMCH_DISPLAY(dev_priv->dev))
409ee761 2137 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
23538ef1
JN		 2138 assert_dsi_pll_enabled(dev_priv);
2139 else
2140 assert_pll_enabled(dev_priv, pipe);
040484af 2141 else {
6e3c9717 2142 if (crtc->config->has_pch_encoder) {
040484af 2143 /* if driving the PCH, we need FDI enabled */
cc391bbb 2144 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 2145 assert_fdi_tx_pll_enabled(dev_priv,
2146 (enum pipe) cpu_transcoder);
040484af
JB		 2147 }
2148 /* FIXME: assert CPU port conditions for SNB+ */
2149 }
b24e7179 2150
702e7a56 2151 reg = PIPECONF(cpu_transcoder);
b24e7179 2152 val = I915_READ(reg);
7ad25d48 2153 if (val & PIPECONF_ENABLE) {
b6b5d049
VS		 2154 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2155 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
00d70b15 2156 return;
7ad25d48 2157 }
00d70b15
CW		 2158
2159 I915_WRITE(reg, val | PIPECONF_ENABLE);
851855d8 2160 POSTING_READ(reg);
b24e7179
JB		 2161}
2162
2163/**
309cfea8 2164 * intel_disable_pipe - disable a pipe, asserting requirements
575f7ab7 2165 * @crtc: crtc whose pipes is to be disabled
b24e7179 2166 *
575f7ab7
VS		 2167 * Disable the pipe of @crtc, making sure that various hardware
2168 * specific requirements are met, if applicable, e.g. plane
2169 * disabled, panel fitter off, etc.
b24e7179
JB		 2170 *
2171 * Will wait until the pipe has shut down before returning.
2172 */
575f7ab7 2173static void intel_disable_pipe(struct intel_crtc *crtc)
b24e7179 2174{
575f7ab7 2175 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
6e3c9717 2176 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 2177 enum pipe pipe = crtc->pipe;
b24e7179
JB		 2178 int reg;
2179 u32 val;
2180
2181 /*
2182 * Make sure planes won't keep trying to pump pixels to us,
2183 * or we might hang the display.
2184 */
2185 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2186 assert_cursor_disabled(dev_priv, pipe);
19332d7a 2187 assert_sprites_disabled(dev_priv, pipe);
b24e7179 2188
702e7a56 2189 reg = PIPECONF(cpu_transcoder);
b24e7179 2190 val = I915_READ(reg);
00d70b15
CW		 2191 if ((val & PIPECONF_ENABLE) == 0)
2192 return;
2193
67adc644
VS		 2194 /*
2195 * Double wide has implications for planes
2196 * so best keep it disabled when not needed.
2197 */
6e3c9717 2198 if (crtc->config->double_wide)
67adc644
VS		 2199 val &= ~PIPECONF_DOUBLE_WIDE;
2200
2201 /* Don't disable pipe or pipe PLLs if needed */
b6b5d049
VS		 2202 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2203 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
67adc644
VS		 2204 val &= ~PIPECONF_ENABLE;
2205
2206 I915_WRITE(reg, val);
2207 if ((val & PIPECONF_ENABLE) == 0)
2208 intel_wait_for_pipe_off(crtc);
b24e7179
JB		 2209}
2210
d74362c9
KP		 2211/*
2212 * Plane regs are double buffered, going from enabled->disabled needs a
2213 * trigger in order to latch. The display address reg provides this.
2214 */
1dba99f4
VS		 2215void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2216 enum plane plane)
d74362c9 2217{
3d13ef2e
DL		 2218 struct drm_device *dev = dev_priv->dev;
2219 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
1dba99f4
VS		 2220
2221 I915_WRITE(reg, I915_READ(reg));
2222 POSTING_READ(reg);
d74362c9
KP		 2223}
2224
b24e7179 2225/**
262ca2b0 2226 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
fdd508a6
VS		 2227 * @plane: plane to be enabled
2228 * @crtc: crtc for the plane
b24e7179 2229 *
fdd508a6 2230 * Enable @plane on @crtc, making sure that the pipe is running first.
b24e7179 2231 */
fdd508a6
VS		 2232static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2233 struct drm_crtc *crtc)
b24e7179 2234{
fdd508a6
VS		 2235 struct drm_device *dev = plane->dev;
2236 struct drm_i915_private *dev_priv = dev->dev_private;
2237 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b24e7179
JB		 2238
2239 /* If the pipe isn't enabled, we can't pump pixels and may hang */
fdd508a6 2240 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
b70709a6 2241 to_intel_plane_state(plane->state)->visible = true;
939c2fe8 2242
fdd508a6
VS		 2243 dev_priv->display.update_primary_plane(crtc, plane->fb,
2244 crtc->x, crtc->y);
b24e7179
JB		 2245}
2246
693db184
CW		 2247static bool need_vtd_wa(struct drm_device *dev)
2248{
2249#ifdef CONFIG_INTEL_IOMMU
2250 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2251 return true;
2252#endif
2253 return false;
2254}
2255
50470bb0 2256unsigned int
6761dd31
TU		 2257intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2258 uint64_t fb_format_modifier)
a57ce0b2 2259{
6761dd31
TU		 2260 unsigned int tile_height;
2261 uint32_t pixel_bytes;
a57ce0b2 2262
b5d0e9bf
DL		 2263 switch (fb_format_modifier) {
2264 case DRM_FORMAT_MOD_NONE:
2265 tile_height = 1;
2266 break;
2267 case I915_FORMAT_MOD_X_TILED:
2268 tile_height = IS_GEN2(dev) ? 16 : 8;
2269 break;
2270 case I915_FORMAT_MOD_Y_TILED:
2271 tile_height = 32;
2272 break;
2273 case I915_FORMAT_MOD_Yf_TILED:
6761dd31
TU		 2274 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2275 switch (pixel_bytes) {
b5d0e9bf 2276 default:
6761dd31 2277 case 1:
b5d0e9bf
DL		 2278 tile_height = 64;
2279 break;
6761dd31
TU		 2280 case 2:
2281 case 4:
b5d0e9bf
DL		 2282 tile_height = 32;
2283 break;
6761dd31 2284 case 8:
b5d0e9bf
DL		 2285 tile_height = 16;
2286 break;
6761dd31 2287 case 16:
b5d0e9bf
DL		 2288 WARN_ONCE(1,
2289 "128-bit pixels are not supported for display!");
2290 tile_height = 16;
2291 break;
2292 }
2293 break;
2294 default:
2295 MISSING_CASE(fb_format_modifier);
2296 tile_height = 1;
2297 break;
2298 }
091df6cb 2299
6761dd31
TU		 2300 return tile_height;
2301}
2302
2303unsigned int
2304intel_fb_align_height(struct drm_device *dev, unsigned int height,
2305 uint32_t pixel_format, uint64_t fb_format_modifier)
2306{
2307 return ALIGN(height, intel_tile_height(dev, pixel_format,
2308 fb_format_modifier));
a57ce0b2
JB		 2309}
2310
f64b98cd
TU		 2311static int
2312intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2313 const struct drm_plane_state *plane_state)
2314{
50470bb0 2315 struct intel_rotation_info *info = &view->rotation_info;
50470bb0 2316
f64b98cd
TU		 2317 *view = i915_ggtt_view_normal;
2318
50470bb0
TU		 2319 if (!plane_state)
2320 return 0;
2321
121920fa 2322 if (!intel_rotation_90_or_270(plane_state->rotation))
50470bb0
TU		 2323 return 0;
2324
9abc4648 2325 *view = i915_ggtt_view_rotated;
50470bb0
TU		 2326
2327 info->height = fb->height;
2328 info->pixel_format = fb->pixel_format;
2329 info->pitch = fb->pitches[0];
2330 info->fb_modifier = fb->modifier[0];
2331
f64b98cd
TU		 2332 return 0;
2333}
2334
127bd2ac 2335int
850c4cdc
TU		 2336intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2337 struct drm_framebuffer *fb,
82bc3b2d 2338 const struct drm_plane_state *plane_state,
a4872ba6 2339 struct intel_engine_cs *pipelined)
6b95a207 2340{
850c4cdc 2341 struct drm_device *dev = fb->dev;
ce453d81 2342 struct drm_i915_private *dev_priv = dev->dev_private;
850c4cdc 2343 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd 2344 struct i915_ggtt_view view;
6b95a207
KH		 2345 u32 alignment;
2346 int ret;
2347
ebcdd39e
MR		 2348 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2349
7b911adc
TU		 2350 switch (fb->modifier[0]) {
2351 case DRM_FORMAT_MOD_NONE:
1fada4cc
DL		 2352 if (INTEL_INFO(dev)->gen >= 9)
2353 alignment = 256 * 1024;
2354 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
534843da 2355 alignment = 128 * 1024;
a6c45cf0 2356 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 2357 alignment = 4 * 1024;
2358 else
2359 alignment = 64 * 1024;
6b95a207 2360 break;
7b911adc 2361 case I915_FORMAT_MOD_X_TILED:
1fada4cc
DL		 2362 if (INTEL_INFO(dev)->gen >= 9)
2363 alignment = 256 * 1024;
2364 else {
2365 /* pin() will align the object as required by fence */
2366 alignment = 0;
2367 }
6b95a207 2368 break;
7b911adc 2369 case I915_FORMAT_MOD_Y_TILED:
1327b9a1
DL		 2370 case I915_FORMAT_MOD_Yf_TILED:
2371 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2372 "Y tiling bo slipped through, driver bug!\n"))
2373 return -EINVAL;
2374 alignment = 1 * 1024 * 1024;
2375 break;
6b95a207 2376 default:
7b911adc
TU		 2377 MISSING_CASE(fb->modifier[0]);
2378 return -EINVAL;
6b95a207
KH		 2379 }
2380
f64b98cd
TU		 2381 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2382 if (ret)
2383 return ret;
2384
693db184
CW		 2385 /* Note that the w/a also requires 64 PTE of padding following the
2386 * bo. We currently fill all unused PTE with the shadow page and so
2387 * we should always have valid PTE following the scanout preventing
2388 * the VT-d warning.
2389 */
2390 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2391 alignment = 256 * 1024;
2392
d6dd6843
PZ		 2393 /*
2394 * Global gtt pte registers are special registers which actually forward
2395 * writes to a chunk of system memory. Which means that there is no risk
2396 * that the register values disappear as soon as we call
2397 * intel_runtime_pm_put(), so it is correct to wrap only the
2398 * pin/unpin/fence and not more.
2399 */
2400 intel_runtime_pm_get(dev_priv);
2401
ce453d81 2402 dev_priv->mm.interruptible = false;
e6617330 2403 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
f64b98cd 2404 &view);
48b956c5 2405 if (ret)
ce453d81 2406 goto err_interruptible;
6b95a207
KH		 2407
2408 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2409 * fence, whereas 965+ only requires a fence if using
2410 * framebuffer compression. For simplicity, we always install
2411 * a fence as the cost is not that onerous.
2412 */
06d98131 2413 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 2414 if (ret)
2415 goto err_unpin;
1690e1eb 2416
9a5a53b3 2417 i915_gem_object_pin_fence(obj);
6b95a207 2418
ce453d81 2419 dev_priv->mm.interruptible = true;
d6dd6843 2420 intel_runtime_pm_put(dev_priv);
6b95a207 2421 return 0;
48b956c5
CW		 2422
2423err_unpin:
f64b98cd 2424 i915_gem_object_unpin_from_display_plane(obj, &view);
ce453d81
CW		 2425err_interruptible:
2426 dev_priv->mm.interruptible = true;
d6dd6843 2427 intel_runtime_pm_put(dev_priv);
48b956c5 2428 return ret;
6b95a207
KH		 2429}
2430
82bc3b2d
TU		 2431static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2432 const struct drm_plane_state *plane_state)
1690e1eb 2433{
82bc3b2d 2434 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd
TU		 2435 struct i915_ggtt_view view;
2436 int ret;
82bc3b2d 2437
ebcdd39e
MR		 2438 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2439
f64b98cd
TU		 2440 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2441 WARN_ONCE(ret, "Couldn't get view from plane state!");
2442
1690e1eb 2443 i915_gem_object_unpin_fence(obj);
f64b98cd 2444 i915_gem_object_unpin_from_display_plane(obj, &view);
1690e1eb
CW		 2445}
2446
c2c75131
DV		 2447/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2448 * is assumed to be a power-of-two. */
bc752862
CW		 2449unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2450 unsigned int tiling_mode,
2451 unsigned int cpp,
2452 unsigned int pitch)
c2c75131 2453{
bc752862
CW		 2454 if (tiling_mode != I915_TILING_NONE) {
2455 unsigned int tile_rows, tiles;
c2c75131 2456
bc752862
CW		 2457 tile_rows = *y / 8;
2458 *y %= 8;
c2c75131 2459
bc752862
CW		 2460 tiles = *x / (512/cpp);
2461 *x %= 512/cpp;
2462
2463 return tile_rows * pitch * 8 + tiles * 4096;
2464 } else {
2465 unsigned int offset;
2466
2467 offset = *y * pitch + *x * cpp;
2468 *y = 0;
2469 *x = (offset & 4095) / cpp;
2470 return offset & -4096;
2471 }
c2c75131
DV		 2472}
2473
b35d63fa 2474static int i9xx_format_to_fourcc(int format)
46f297fb
JB		 2475{
2476 switch (format) {
2477 case DISPPLANE_8BPP:
2478 return DRM_FORMAT_C8;
2479 case DISPPLANE_BGRX555:
2480 return DRM_FORMAT_XRGB1555;
2481 case DISPPLANE_BGRX565:
2482 return DRM_FORMAT_RGB565;
2483 default:
2484 case DISPPLANE_BGRX888:
2485 return DRM_FORMAT_XRGB8888;
2486 case DISPPLANE_RGBX888:
2487 return DRM_FORMAT_XBGR8888;
2488 case DISPPLANE_BGRX101010:
2489 return DRM_FORMAT_XRGB2101010;
2490 case DISPPLANE_RGBX101010:
2491 return DRM_FORMAT_XBGR2101010;
2492 }
2493}
2494
bc8d7dff
DL		 2495static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2496{
2497 switch (format) {
2498 case PLANE_CTL_FORMAT_RGB_565:
2499 return DRM_FORMAT_RGB565;
2500 default:
2501 case PLANE_CTL_FORMAT_XRGB_8888:
2502 if (rgb_order) {
2503 if (alpha)
2504 return DRM_FORMAT_ABGR8888;
2505 else
2506 return DRM_FORMAT_XBGR8888;
2507 } else {
2508 if (alpha)
2509 return DRM_FORMAT_ARGB8888;
2510 else
2511 return DRM_FORMAT_XRGB8888;
2512 }
2513 case PLANE_CTL_FORMAT_XRGB_2101010:
2514 if (rgb_order)
2515 return DRM_FORMAT_XBGR2101010;
2516 else
2517 return DRM_FORMAT_XRGB2101010;
2518 }
2519}
2520
5724dbd1 2521static bool
f6936e29
DV		 2522intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2523 struct intel_initial_plane_config *plane_config)
46f297fb
JB		 2524{
2525 struct drm_device *dev = crtc->base.dev;
2526 struct drm_i915_gem_object *obj = NULL;
2527 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2d14030b 2528 struct drm_framebuffer *fb = &plane_config->fb->base;
f37b5c2b
DV		 2529 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2530 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2531 PAGE_SIZE);
2532
2533 size_aligned -= base_aligned;
46f297fb 2534
ff2652ea
CW		 2535 if (plane_config->size == 0)
2536 return false;
2537
f37b5c2b
DV		 2538 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2539 base_aligned,
2540 base_aligned,
2541 size_aligned);
46f297fb 2542 if (!obj)
484b41dd 2543 return false;
46f297fb 2544
49af449b
DL		 2545 obj->tiling_mode = plane_config->tiling;
2546 if (obj->tiling_mode == I915_TILING_X)
6bf129df 2547 obj->stride = fb->pitches[0];
46f297fb 2548
6bf129df
DL		 2549 mode_cmd.pixel_format = fb->pixel_format;
2550 mode_cmd.width = fb->width;
2551 mode_cmd.height = fb->height;
2552 mode_cmd.pitches[0] = fb->pitches[0];
18c5247e
DV		 2553 mode_cmd.modifier[0] = fb->modifier[0];
2554 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
46f297fb
JB		 2555
2556 mutex_lock(&dev->struct_mutex);
6bf129df 2557 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
484b41dd 2558 &mode_cmd, obj)) {
46f297fb
JB		 2559 DRM_DEBUG_KMS("intel fb init failed\n");
2560 goto out_unref_obj;
2561 }
46f297fb 2562 mutex_unlock(&dev->struct_mutex);
484b41dd 2563
f6936e29 2564 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
484b41dd 2565 return true;
46f297fb
JB		 2566
2567out_unref_obj:
2568 drm_gem_object_unreference(&obj->base);
2569 mutex_unlock(&dev->struct_mutex);
484b41dd
JB		 2570 return false;
2571}
2572
afd65eb4
MR		 2573/* Update plane->state->fb to match plane->fb after driver-internal updates */
2574static void
2575update_state_fb(struct drm_plane *plane)
2576{
2577 if (plane->fb == plane->state->fb)
2578 return;
2579
2580 if (plane->state->fb)
2581 drm_framebuffer_unreference(plane->state->fb);
2582 plane->state->fb = plane->fb;
2583 if (plane->state->fb)
2584 drm_framebuffer_reference(plane->state->fb);
2585}
2586
5724dbd1 2587static void
f6936e29
DV		 2588intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2589 struct intel_initial_plane_config *plane_config)
484b41dd
JB		 2590{
2591 struct drm_device *dev = intel_crtc->base.dev;
d9ceb816 2592 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd
JB		 2593 struct drm_crtc *c;
2594 struct intel_crtc *i;
2ff8fde1 2595 struct drm_i915_gem_object *obj;
88595ac9
DV		 2596 struct drm_plane *primary = intel_crtc->base.primary;
2597 struct drm_framebuffer *fb;
484b41dd 2598
2d14030b 2599 if (!plane_config->fb)
484b41dd
JB		 2600 return;
2601
f6936e29 2602 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
88595ac9
DV		 2603 fb = &plane_config->fb->base;
2604 goto valid_fb;
f55548b5 2605 }
484b41dd 2606
2d14030b 2607 kfree(plane_config->fb);
484b41dd
JB		 2608
2609 /*
2610 * Failed to alloc the obj, check to see if we should share
2611 * an fb with another CRTC instead
2612 */
70e1e0ec 2613 for_each_crtc(dev, c) {
484b41dd
JB		 2614 i = to_intel_crtc(c);
2615
2616 if (c == &intel_crtc->base)
2617 continue;
2618
2ff8fde1
MR		 2619 if (!i->active)
2620 continue;
2621
88595ac9
DV		 2622 fb = c->primary->fb;
2623 if (!fb)
484b41dd
JB		 2624 continue;
2625
88595ac9 2626 obj = intel_fb_obj(fb);
2ff8fde1 2627 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
88595ac9
DV		 2628 drm_framebuffer_reference(fb);
2629 goto valid_fb;
484b41dd
JB		 2630 }
2631 }
88595ac9
DV		 2632
2633 return;
2634
2635valid_fb:
2636 obj = intel_fb_obj(fb);
2637 if (obj->tiling_mode != I915_TILING_NONE)
2638 dev_priv->preserve_bios_swizzle = true;
2639
2640 primary->fb = fb;
2641 primary->state->crtc = &intel_crtc->base;
2642 primary->crtc = &intel_crtc->base;
2643 update_state_fb(primary);
2644 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
46f297fb
JB		 2645}
2646
29b9bde6
DV		 2647static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2648 struct drm_framebuffer *fb,
2649 int x, int y)
81255565
JB		 2650{
2651 struct drm_device *dev = crtc->dev;
2652 struct drm_i915_private *dev_priv = dev->dev_private;
2653 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2654 struct drm_plane *primary = crtc->primary;
2655 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2656 struct drm_i915_gem_object *obj;
81255565 2657 int plane = intel_crtc->plane;
e506a0c6 2658 unsigned long linear_offset;
81255565 2659 u32 dspcntr;
f45651ba 2660 u32 reg = DSPCNTR(plane);
48404c1e 2661 int pixel_size;
f45651ba 2662
b70709a6 2663 if (!visible || !fb) {
fdd508a6
VS		 2664 I915_WRITE(reg, 0);
2665 if (INTEL_INFO(dev)->gen >= 4)
2666 I915_WRITE(DSPSURF(plane), 0);
2667 else
2668 I915_WRITE(DSPADDR(plane), 0);
2669 POSTING_READ(reg);
2670 return;
2671 }
2672
c9ba6fad
VS		 2673 obj = intel_fb_obj(fb);
2674 if (WARN_ON(obj == NULL))
2675 return;
2676
2677 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2678
f45651ba
VS		 2679 dspcntr = DISPPLANE_GAMMA_ENABLE;
2680
fdd508a6 2681 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2682
2683 if (INTEL_INFO(dev)->gen < 4) {
2684 if (intel_crtc->pipe == PIPE_B)
2685 dspcntr |= DISPPLANE_SEL_PIPE_B;
2686
2687 /* pipesrc and dspsize control the size that is scaled from,
2688 * which should always be the user's requested size.
2689 */
2690 I915_WRITE(DSPSIZE(plane),
6e3c9717
ACO		 2691 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2692 (intel_crtc->config->pipe_src_w - 1));
f45651ba 2693 I915_WRITE(DSPPOS(plane), 0);
c14b0485
VS		 2694 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2695 I915_WRITE(PRIMSIZE(plane),
6e3c9717
ACO		 2696 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2697 (intel_crtc->config->pipe_src_w - 1));
c14b0485
VS		 2698 I915_WRITE(PRIMPOS(plane), 0);
2699 I915_WRITE(PRIMCNSTALPHA(plane), 0);
f45651ba 2700 }
81255565 2701
57779d06
VS		 2702 switch (fb->pixel_format) {
2703 case DRM_FORMAT_C8:
81255565
JB		 2704 dspcntr |= DISPPLANE_8BPP;
2705 break;
57779d06
VS		 2706 case DRM_FORMAT_XRGB1555:
2707 case DRM_FORMAT_ARGB1555:
2708 dspcntr |= DISPPLANE_BGRX555;
81255565 2709 break;
57779d06
VS		 2710 case DRM_FORMAT_RGB565:
2711 dspcntr |= DISPPLANE_BGRX565;
2712 break;
2713 case DRM_FORMAT_XRGB8888:
2714 case DRM_FORMAT_ARGB8888:
2715 dspcntr |= DISPPLANE_BGRX888;
2716 break;
2717 case DRM_FORMAT_XBGR8888:
2718 case DRM_FORMAT_ABGR8888:
2719 dspcntr |= DISPPLANE_RGBX888;
2720 break;
2721 case DRM_FORMAT_XRGB2101010:
2722 case DRM_FORMAT_ARGB2101010:
2723 dspcntr |= DISPPLANE_BGRX101010;
2724 break;
2725 case DRM_FORMAT_XBGR2101010:
2726 case DRM_FORMAT_ABGR2101010:
2727 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2728 break;
2729 default:
baba133a 2730 BUG();
81255565 2731 }
57779d06 2732
f45651ba
VS		 2733 if (INTEL_INFO(dev)->gen >= 4 &&
2734 obj->tiling_mode != I915_TILING_NONE)
2735 dspcntr |= DISPPLANE_TILED;
81255565 2736
de1aa629
VS		 2737 if (IS_G4X(dev))
2738 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2739
b9897127 2740 linear_offset = y * fb->pitches[0] + x * pixel_size;
81255565 2741
c2c75131
DV		 2742 if (INTEL_INFO(dev)->gen >= 4) {
2743 intel_crtc->dspaddr_offset =
bc752862 2744 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
b9897127 2745 pixel_size,
bc752862 2746 fb->pitches[0]);
c2c75131
DV		 2747 linear_offset -= intel_crtc->dspaddr_offset;
2748 } else {
e506a0c6 2749 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2750 }
e506a0c6 2751
8e7d688b 2752 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2753 dspcntr |= DISPPLANE_ROTATE_180;
2754
6e3c9717
ACO		 2755 x += (intel_crtc->config->pipe_src_w - 1);
2756 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2757
2758 /* Finding the last pixel of the last line of the display
2759 data and adding to linear_offset*/
2760 linear_offset +=
6e3c9717
ACO		 2761 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2762 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2763 }
2764
2765 I915_WRITE(reg, dspcntr);
2766
01f2c773 2767 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2768 if (INTEL_INFO(dev)->gen >= 4) {
85ba7b7d
DV		 2769 I915_WRITE(DSPSURF(plane),
2770 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2771 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2772 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2773 } else
f343c5f6 2774 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2775 POSTING_READ(reg);
17638cd6
JB		 2776}
2777
29b9bde6
DV		 2778static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2779 struct drm_framebuffer *fb,
2780 int x, int y)
17638cd6
JB		 2781{
2782 struct drm_device *dev = crtc->dev;
2783 struct drm_i915_private *dev_priv = dev->dev_private;
2784 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2785 struct drm_plane *primary = crtc->primary;
2786 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2787 struct drm_i915_gem_object *obj;
17638cd6 2788 int plane = intel_crtc->plane;
e506a0c6 2789 unsigned long linear_offset;
17638cd6 2790 u32 dspcntr;
f45651ba 2791 u32 reg = DSPCNTR(plane);
48404c1e 2792 int pixel_size;
f45651ba 2793
b70709a6 2794 if (!visible || !fb) {
fdd508a6
VS		 2795 I915_WRITE(reg, 0);
2796 I915_WRITE(DSPSURF(plane), 0);
2797 POSTING_READ(reg);
2798 return;
2799 }
2800
c9ba6fad
VS		 2801 obj = intel_fb_obj(fb);
2802 if (WARN_ON(obj == NULL))
2803 return;
2804
2805 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2806
f45651ba
VS		 2807 dspcntr = DISPPLANE_GAMMA_ENABLE;
2808
fdd508a6 2809 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2810
2811 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2812 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
17638cd6 2813
57779d06
VS		 2814 switch (fb->pixel_format) {
2815 case DRM_FORMAT_C8:
17638cd6
JB		 2816 dspcntr |= DISPPLANE_8BPP;
2817 break;
57779d06
VS		 2818 case DRM_FORMAT_RGB565:
2819 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2820 break;
57779d06
VS		 2821 case DRM_FORMAT_XRGB8888:
2822 case DRM_FORMAT_ARGB8888:
2823 dspcntr |= DISPPLANE_BGRX888;
2824 break;
2825 case DRM_FORMAT_XBGR8888:
2826 case DRM_FORMAT_ABGR8888:
2827 dspcntr |= DISPPLANE_RGBX888;
2828 break;
2829 case DRM_FORMAT_XRGB2101010:
2830 case DRM_FORMAT_ARGB2101010:
2831 dspcntr |= DISPPLANE_BGRX101010;
2832 break;
2833 case DRM_FORMAT_XBGR2101010:
2834 case DRM_FORMAT_ABGR2101010:
2835 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2836 break;
2837 default:
baba133a 2838 BUG();
17638cd6
JB		 2839 }
2840
2841 if (obj->tiling_mode != I915_TILING_NONE)
2842 dspcntr |= DISPPLANE_TILED;
17638cd6 2843
f45651ba 2844 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
1f5d76db 2845 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6 2846
b9897127 2847 linear_offset = y * fb->pitches[0] + x * pixel_size;
c2c75131 2848 intel_crtc->dspaddr_offset =
bc752862 2849 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
b9897127 2850 pixel_size,
bc752862 2851 fb->pitches[0]);
c2c75131 2852 linear_offset -= intel_crtc->dspaddr_offset;
8e7d688b 2853 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2854 dspcntr |= DISPPLANE_ROTATE_180;
2855
2856 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
6e3c9717
ACO		 2857 x += (intel_crtc->config->pipe_src_w - 1);
2858 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2859
2860 /* Finding the last pixel of the last line of the display
2861 data and adding to linear_offset*/
2862 linear_offset +=
6e3c9717
ACO		 2863 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2864 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2865 }
2866 }
2867
2868 I915_WRITE(reg, dspcntr);
17638cd6 2869
01f2c773 2870 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
85ba7b7d
DV		 2871 I915_WRITE(DSPSURF(plane),
2872 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
b3dc685e 2873 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
bc1c91eb
DL		 2874 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2875 } else {
2876 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2877 I915_WRITE(DSPLINOFF(plane), linear_offset);
2878 }
17638cd6 2879 POSTING_READ(reg);
17638cd6
JB		 2880}
2881
b321803d
DL		 2882u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2883 uint32_t pixel_format)
2884{
2885 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2886
2887 /*
2888 * The stride is either expressed as a multiple of 64 bytes
2889 * chunks for linear buffers or in number of tiles for tiled
2890 * buffers.
2891 */
2892 switch (fb_modifier) {
2893 case DRM_FORMAT_MOD_NONE:
2894 return 64;
2895 case I915_FORMAT_MOD_X_TILED:
2896 if (INTEL_INFO(dev)->gen == 2)
2897 return 128;
2898 return 512;
2899 case I915_FORMAT_MOD_Y_TILED:
2900 /* No need to check for old gens and Y tiling since this is
2901 * about the display engine and those will be blocked before
2902 * we get here.
2903 */
2904 return 128;
2905 case I915_FORMAT_MOD_Yf_TILED:
2906 if (bits_per_pixel == 8)
2907 return 64;
2908 else
2909 return 128;
2910 default:
2911 MISSING_CASE(fb_modifier);
2912 return 64;
2913 }
2914}
2915
121920fa
TU		 2916unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2917 struct drm_i915_gem_object *obj)
2918{
9abc4648 2919 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
121920fa
TU		 2920
2921 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
9abc4648 2922 view = &i915_ggtt_view_rotated;
121920fa
TU		 2923
2924 return i915_gem_obj_ggtt_offset_view(obj, view);
2925}
2926
a1b2278e
CK		 2927/*
2928 * This function detaches (aka. unbinds) unused scalers in hardware
2929 */
2930void skl_detach_scalers(struct intel_crtc *intel_crtc)
2931{
2932 struct drm_device *dev;
2933 struct drm_i915_private *dev_priv;
2934 struct intel_crtc_scaler_state *scaler_state;
2935 int i;
2936
2937 if (!intel_crtc || !intel_crtc->config)
2938 return;
2939
2940 dev = intel_crtc->base.dev;
2941 dev_priv = dev->dev_private;
2942 scaler_state = &intel_crtc->config->scaler_state;
2943
2944 /* loop through and disable scalers that aren't in use */
2945 for (i = 0; i < intel_crtc->num_scalers; i++) {
2946 if (!scaler_state->scalers[i].in_use) {
2947 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0);
2948 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0);
2949 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0);
2950 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2951 intel_crtc->base.base.id, intel_crtc->pipe, i);
2952 }
2953 }
2954}
2955
6156a456 2956u32 skl_plane_ctl_format(uint32_t pixel_format)
70d21f0e 2957{
6156a456
CK		 2958 u32 plane_ctl_format = 0;
2959 switch (pixel_format) {
70d21f0e 2960 case DRM_FORMAT_RGB565:
6156a456 2961 plane_ctl_format = PLANE_CTL_FORMAT_RGB_565;
f75fb42a 2962 break;
70d21f0e 2963 case DRM_FORMAT_XBGR8888:
6156a456
CK		 2964 plane_ctl_format = PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2965 break;
2966 case DRM_FORMAT_XRGB8888:
2967 plane_ctl_format = PLANE_CTL_FORMAT_XRGB_8888;
70d21f0e 2968 break;
6156a456
CK		 2969 /*
2970 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2971 * to be already pre-multiplied. We need to add a knob (or a different
2972 * DRM_FORMAT) for user-space to configure that.
2973 */
f75fb42a 2974 case DRM_FORMAT_ABGR8888:
6156a456
CK		 2975 plane_ctl_format = PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2976 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2977 break;
2978 case DRM_FORMAT_ARGB8888:
2979 plane_ctl_format = PLANE_CTL_FORMAT_XRGB_8888 |
2980 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
f75fb42a 2981 break;
70d21f0e 2982 case DRM_FORMAT_XRGB2101010:
6156a456 2983 plane_ctl_format = PLANE_CTL_FORMAT_XRGB_2101010;
70d21f0e
DL		 2984 break;
2985 case DRM_FORMAT_XBGR2101010:
6156a456
CK		 2986 plane_ctl_format = PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2987 break;
2988 case DRM_FORMAT_YUYV:
2989 plane_ctl_format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2990 break;
2991 case DRM_FORMAT_YVYU:
2992 plane_ctl_format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2993 break;
2994 case DRM_FORMAT_UYVY:
2995 plane_ctl_format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2996 break;
2997 case DRM_FORMAT_VYUY:
2998 plane_ctl_format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
70d21f0e
DL		 2999 break;
3000 default:
3001 BUG();
3002 }
6156a456
CK		 3003 return plane_ctl_format;
3004}
70d21f0e 3005
6156a456
CK		 3006u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3007{
3008 u32 plane_ctl_tiling = 0;
3009 switch (fb_modifier) {
30af77c4 3010 case DRM_FORMAT_MOD_NONE:
70d21f0e 3011 break;
30af77c4 3012 case I915_FORMAT_MOD_X_TILED:
6156a456 3013 plane_ctl_tiling = PLANE_CTL_TILED_X;
b321803d
DL		 3014 break;
3015 case I915_FORMAT_MOD_Y_TILED:
6156a456 3016 plane_ctl_tiling = PLANE_CTL_TILED_Y;
b321803d
DL		 3017 break;
3018 case I915_FORMAT_MOD_Yf_TILED:
6156a456 3019 plane_ctl_tiling = PLANE_CTL_TILED_YF;
70d21f0e
DL		 3020 break;
3021 default:
6156a456 3022 MISSING_CASE(fb_modifier);
70d21f0e 3023 }
6156a456
CK		 3024 return plane_ctl_tiling;
3025}
70d21f0e 3026
6156a456
CK		 3027u32 skl_plane_ctl_rotation(unsigned int rotation)
3028{
3029 u32 plane_ctl_rotation = 0;
3b7a5119 3030 switch (rotation) {
6156a456
CK		 3031 case BIT(DRM_ROTATE_0):
3032 break;
3b7a5119 3033 case BIT(DRM_ROTATE_90):
6156a456 3034 plane_ctl_rotation = PLANE_CTL_ROTATE_90;
3b7a5119 3035 break;
3b7a5119 3036 case BIT(DRM_ROTATE_180):
6156a456 3037 plane_ctl_rotation = PLANE_CTL_ROTATE_180;
3b7a5119 3038 break;
3b7a5119 3039 case BIT(DRM_ROTATE_270):
6156a456 3040 plane_ctl_rotation = PLANE_CTL_ROTATE_270;
3b7a5119 3041 break;
6156a456
CK		 3042 default:
3043 MISSING_CASE(rotation);
3044 }
3045
3046 return plane_ctl_rotation;
3047}
3048
3049static void skylake_update_primary_plane(struct drm_crtc *crtc,
3050 struct drm_framebuffer *fb,
3051 int x, int y)
3052{
3053 struct drm_device *dev = crtc->dev;
3054 struct drm_i915_private *dev_priv = dev->dev_private;
3055 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 3056 struct drm_plane *plane = crtc->primary;
3057 bool visible = to_intel_plane_state(plane->state)->visible;
6156a456
CK		 3058 struct drm_i915_gem_object *obj;
3059 int pipe = intel_crtc->pipe;
3060 u32 plane_ctl, stride_div, stride;
3061 u32 tile_height, plane_offset, plane_size;
3062 unsigned int rotation;
3063 int x_offset, y_offset;
3064 unsigned long surf_addr;
6156a456
CK		 3065 struct intel_crtc_state *crtc_state = intel_crtc->config;
3066 struct intel_plane_state *plane_state;
3067 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3068 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3069 int scaler_id = -1;
3070
6156a456
CK		 3071 plane_state = to_intel_plane_state(plane->state);
3072
b70709a6 3073 if (!visible || !fb) {
6156a456
CK		 3074 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3075 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3076 POSTING_READ(PLANE_CTL(pipe, 0));
3077 return;
3b7a5119 3078 }
70d21f0e 3079
6156a456
CK		 3080 plane_ctl = PLANE_CTL_ENABLE |
3081 PLANE_CTL_PIPE_GAMMA_ENABLE |
3082 PLANE_CTL_PIPE_CSC_ENABLE;
3083
3084 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3085 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3086 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3087
3088 rotation = plane->state->rotation;
3089 plane_ctl |= skl_plane_ctl_rotation(rotation);
3090
b321803d
DL		 3091 obj = intel_fb_obj(fb);
3092 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3093 fb->pixel_format);
3b7a5119
SJ		 3094 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3095
6156a456
CK		 3096 /*
3097 * FIXME: intel_plane_state->src, dst aren't set when transitional
3098 * update_plane helpers are called from legacy paths.
3099 * Once full atomic crtc is available, below check can be avoided.
3100 */
3101 if (drm_rect_width(&plane_state->src)) {
3102 scaler_id = plane_state->scaler_id;
3103 src_x = plane_state->src.x1 >> 16;
3104 src_y = plane_state->src.y1 >> 16;
3105 src_w = drm_rect_width(&plane_state->src) >> 16;
3106 src_h = drm_rect_height(&plane_state->src) >> 16;
3107 dst_x = plane_state->dst.x1;
3108 dst_y = plane_state->dst.y1;
3109 dst_w = drm_rect_width(&plane_state->dst);
3110 dst_h = drm_rect_height(&plane_state->dst);
3111
3112 WARN_ON(x != src_x || y != src_y);
3113 } else {
3114 src_w = intel_crtc->config->pipe_src_w;
3115 src_h = intel_crtc->config->pipe_src_h;
3116 }
3117
3b7a5119
SJ		 3118 if (intel_rotation_90_or_270(rotation)) {
3119 /* stride = Surface height in tiles */
3120 tile_height = intel_tile_height(dev, fb->bits_per_pixel,
3121 fb->modifier[0]);
3122 stride = DIV_ROUND_UP(fb->height, tile_height);
6156a456 3123 x_offset = stride * tile_height - y - src_h;
3b7a5119 3124 y_offset = x;
6156a456 3125 plane_size = (src_w - 1) << 16 | (src_h - 1);
3b7a5119
SJ		 3126 } else {
3127 stride = fb->pitches[0] / stride_div;
3128 x_offset = x;
3129 y_offset = y;
6156a456 3130 plane_size = (src_h - 1) << 16 | (src_w - 1);
3b7a5119
SJ		 3131 }
3132 plane_offset = y_offset << 16 | x_offset;
b321803d 3133
70d21f0e 3134 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3b7a5119
SJ		 3135 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3136 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3137 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
6156a456
CK		 3138
3139 if (scaler_id >= 0) {
3140 uint32_t ps_ctrl = 0;
3141
3142 WARN_ON(!dst_w || !dst_h);
3143 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3144 crtc_state->scaler_state.scalers[scaler_id].mode;
3145 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3146 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3147 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3148 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3149 I915_WRITE(PLANE_POS(pipe, 0), 0);
3150 } else {
3151 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3152 }
3153
121920fa 3154 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
70d21f0e
DL		 3155
3156 POSTING_READ(PLANE_SURF(pipe, 0));
3157}
3158
17638cd6
JB		 3159/* Assume fb object is pinned & idle & fenced and just update base pointers */
3160static int
3161intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3162 int x, int y, enum mode_set_atomic state)
3163{
3164 struct drm_device *dev = crtc->dev;
3165 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 3166
6b8e6ed0
CW		 3167 if (dev_priv->display.disable_fbc)
3168 dev_priv->display.disable_fbc(dev);
81255565 3169
29b9bde6
DV		 3170 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3171
3172 return 0;
81255565
JB		 3173}
3174
7514747d 3175static void intel_complete_page_flips(struct drm_device *dev)
96a02917 3176{
96a02917
VS		 3177 struct drm_crtc *crtc;
3178
70e1e0ec 3179 for_each_crtc(dev, crtc) {
96a02917
VS		 3180 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3181 enum plane plane = intel_crtc->plane;
3182
3183 intel_prepare_page_flip(dev, plane);
3184 intel_finish_page_flip_plane(dev, plane);
3185 }
7514747d
VS		 3186}
3187
3188static void intel_update_primary_planes(struct drm_device *dev)
3189{
3190 struct drm_i915_private *dev_priv = dev->dev_private;
3191 struct drm_crtc *crtc;
96a02917 3192
70e1e0ec 3193 for_each_crtc(dev, crtc) {
96a02917
VS		 3194 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3195
51fd371b 3196 drm_modeset_lock(&crtc->mutex, NULL);
947fdaad
CW		 3197 /*
3198 * FIXME: Once we have proper support for primary planes (and
3199 * disabling them without disabling the entire crtc) allow again
66e514c1 3200 * a NULL crtc->primary->fb.
947fdaad 3201 */
f4510a27 3202 if (intel_crtc->active && crtc->primary->fb)
262ca2b0 3203 dev_priv->display.update_primary_plane(crtc,
66e514c1 3204 crtc->primary->fb,
262ca2b0
MR		 3205 crtc->x,
3206 crtc->y);
51fd371b 3207 drm_modeset_unlock(&crtc->mutex);
96a02917
VS		 3208 }
3209}
3210
ce22dba9
ML		 3211void intel_crtc_reset(struct intel_crtc *crtc)
3212{
3213 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3214
3215 if (!crtc->active)
3216 return;
3217
3218 intel_crtc_disable_planes(&crtc->base);
3219 dev_priv->display.crtc_disable(&crtc->base);
3220 dev_priv->display.crtc_enable(&crtc->base);
3221 intel_crtc_enable_planes(&crtc->base);
3222}
3223
7514747d
VS		 3224void intel_prepare_reset(struct drm_device *dev)
3225{
f98ce92f
VS		 3226 struct drm_i915_private *dev_priv = to_i915(dev);
3227 struct intel_crtc *crtc;
3228
7514747d
VS		 3229 /* no reset support for gen2 */
3230 if (IS_GEN2(dev))
3231 return;
3232
3233 /* reset doesn't touch the display */
3234 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3235 return;
3236
3237 drm_modeset_lock_all(dev);
f98ce92f
VS		 3238
3239 /*
3240 * Disabling the crtcs gracefully seems nicer. Also the
3241 * g33 docs say we should at least disable all the planes.
3242 */
3243 for_each_intel_crtc(dev, crtc) {
ce22dba9
ML		 3244 if (!crtc->active)
3245 continue;
3246
3247 intel_crtc_disable_planes(&crtc->base);
3248 dev_priv->display.crtc_disable(&crtc->base);
f98ce92f 3249 }
7514747d
VS		 3250}
3251
3252void intel_finish_reset(struct drm_device *dev)
3253{
3254 struct drm_i915_private *dev_priv = to_i915(dev);
3255
3256 /*
3257 * Flips in the rings will be nuked by the reset,
3258 * so complete all pending flips so that user space
3259 * will get its events and not get stuck.
3260 */
3261 intel_complete_page_flips(dev);
3262
3263 /* no reset support for gen2 */
3264 if (IS_GEN2(dev))
3265 return;
3266
3267 /* reset doesn't touch the display */
3268 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3269 /*
3270 * Flips in the rings have been nuked by the reset,
3271 * so update the base address of all primary
3272 * planes to the the last fb to make sure we're
3273 * showing the correct fb after a reset.
3274 */
3275 intel_update_primary_planes(dev);
3276 return;
3277 }
3278
3279 /*
3280 * The display has been reset as well,
3281 * so need a full re-initialization.
3282 */
3283 intel_runtime_pm_disable_interrupts(dev_priv);
3284 intel_runtime_pm_enable_interrupts(dev_priv);
3285
3286 intel_modeset_init_hw(dev);
3287
3288 spin_lock_irq(&dev_priv->irq_lock);
3289 if (dev_priv->display.hpd_irq_setup)
3290 dev_priv->display.hpd_irq_setup(dev);
3291 spin_unlock_irq(&dev_priv->irq_lock);
3292
3293 intel_modeset_setup_hw_state(dev, true);
3294
3295 intel_hpd_init(dev_priv);
3296
3297 drm_modeset_unlock_all(dev);
3298}
3299
14667a4b
CW		 3300static int
3301intel_finish_fb(struct drm_framebuffer *old_fb)
3302{
2ff8fde1 3303 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
14667a4b
CW		 3304 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3305 bool was_interruptible = dev_priv->mm.interruptible;
3306 int ret;
3307
14667a4b
CW		 3308 /* Big Hammer, we also need to ensure that any pending
3309 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3310 * current scanout is retired before unpinning the old
3311 * framebuffer.
3312 *
3313 * This should only fail upon a hung GPU, in which case we
3314 * can safely continue.
3315 */
3316 dev_priv->mm.interruptible = false;
3317 ret = i915_gem_object_finish_gpu(obj);
3318 dev_priv->mm.interruptible = was_interruptible;
3319
3320 return ret;
3321}
3322
7d5e3799
CW		 3323static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3324{
3325 struct drm_device *dev = crtc->dev;
3326 struct drm_i915_private *dev_priv = dev->dev_private;
3327 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7d5e3799
CW		 3328 bool pending;
3329
3330 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3331 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3332 return false;
3333
5e2d7afc 3334 spin_lock_irq(&dev->event_lock);
7d5e3799 3335 pending = to_intel_crtc(crtc)->unpin_work != NULL;
5e2d7afc 3336 spin_unlock_irq(&dev->event_lock);
7d5e3799
CW		 3337
3338 return pending;
3339}
3340
e30e8f75
GP		 3341static void intel_update_pipe_size(struct intel_crtc *crtc)
3342{
3343 struct drm_device *dev = crtc->base.dev;
3344 struct drm_i915_private *dev_priv = dev->dev_private;
3345 const struct drm_display_mode *adjusted_mode;
3346
3347 if (!i915.fastboot)
3348 return;
3349
3350 /*
3351 * Update pipe size and adjust fitter if needed: the reason for this is
3352 * that in compute_mode_changes we check the native mode (not the pfit
3353 * mode) to see if we can flip rather than do a full mode set. In the
3354 * fastboot case, we'll flip, but if we don't update the pipesrc and
3355 * pfit state, we'll end up with a big fb scanned out into the wrong
3356 * sized surface.
3357 *
3358 * To fix this properly, we need to hoist the checks up into
3359 * compute_mode_changes (or above), check the actual pfit state and
3360 * whether the platform allows pfit disable with pipe active, and only
3361 * then update the pipesrc and pfit state, even on the flip path.
3362 */
3363
6e3c9717 3364 adjusted_mode = &crtc->config->base.adjusted_mode;
e30e8f75
GP		 3365
3366 I915_WRITE(PIPESRC(crtc->pipe),
3367 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3368 (adjusted_mode->crtc_vdisplay - 1));
6e3c9717 3369 if (!crtc->config->pch_pfit.enabled &&
409ee761
ACO		 3370 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3371 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
e30e8f75
GP		 3372 I915_WRITE(PF_CTL(crtc->pipe), 0);
3373 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3374 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3375 }
6e3c9717
ACO		 3376 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3377 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
e30e8f75
GP		 3378}
3379
5e84e1a4
ZW		 3380static void intel_fdi_normal_train(struct drm_crtc *crtc)
3381{
3382 struct drm_device *dev = crtc->dev;
3383 struct drm_i915_private *dev_priv = dev->dev_private;
3384 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3385 int pipe = intel_crtc->pipe;
3386 u32 reg, temp;
3387
3388 /* enable normal train */
3389 reg = FDI_TX_CTL(pipe);
3390 temp = I915_READ(reg);
61e499bf 3391 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 3392 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3393 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 3394 } else {
3395 temp &= ~FDI_LINK_TRAIN_NONE;
3396 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 3397 }
5e84e1a4
ZW		 3398 I915_WRITE(reg, temp);
3399
3400 reg = FDI_RX_CTL(pipe);
3401 temp = I915_READ(reg);
3402 if (HAS_PCH_CPT(dev)) {
3403 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3404 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3405 } else {
3406 temp &= ~FDI_LINK_TRAIN_NONE;
3407 temp |= FDI_LINK_TRAIN_NONE;
3408 }
3409 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3410
3411 /* wait one idle pattern time */
3412 POSTING_READ(reg);
3413 udelay(1000);
357555c0
JB		 3414
3415 /* IVB wants error correction enabled */
3416 if (IS_IVYBRIDGE(dev))
3417 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3418 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 3419}
3420
8db9d77b
ZW		 3421/* The FDI link training functions for ILK/Ibexpeak. */
3422static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3423{
3424 struct drm_device *dev = crtc->dev;
3425 struct drm_i915_private *dev_priv = dev->dev_private;
3426 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3427 int pipe = intel_crtc->pipe;
5eddb70b 3428 u32 reg, temp, tries;
8db9d77b 3429
1c8562f6 3430 /* FDI needs bits from pipe first */
0fc932b8 3431 assert_pipe_enabled(dev_priv, pipe);
0fc932b8 3432
e1a44743
AJ		 3433 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3434 for train result */
5eddb70b
CW		 3435 reg = FDI_RX_IMR(pipe);
3436 temp = I915_READ(reg);
e1a44743
AJ		 3437 temp &= ~FDI_RX_SYMBOL_LOCK;
3438 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3439 I915_WRITE(reg, temp);
3440 I915_READ(reg);
e1a44743
AJ		 3441 udelay(150);
3442
8db9d77b 3443 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3444 reg = FDI_TX_CTL(pipe);
3445 temp = I915_READ(reg);
627eb5a3 3446 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3447 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3448 temp &= ~FDI_LINK_TRAIN_NONE;
3449 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 3450 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3451
5eddb70b
CW		 3452 reg = FDI_RX_CTL(pipe);
3453 temp = I915_READ(reg);
8db9d77b
ZW		 3454 temp &= ~FDI_LINK_TRAIN_NONE;
3455 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 3456 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3457
3458 POSTING_READ(reg);
8db9d77b
ZW		 3459 udelay(150);
3460
5b2adf89 3461 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 3462 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3463 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3464 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 3465
5eddb70b 3466 reg = FDI_RX_IIR(pipe);
e1a44743 3467 for (tries = 0; tries < 5; tries++) {
5eddb70b 3468 temp = I915_READ(reg);
8db9d77b
ZW		 3469 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3470
3471 if ((temp & FDI_RX_BIT_LOCK)) {
3472 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 3473 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 3474 break;
3475 }
8db9d77b 3476 }
e1a44743 3477 if (tries == 5)
5eddb70b 3478 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3479
3480 /* Train 2 */
5eddb70b
CW		 3481 reg = FDI_TX_CTL(pipe);
3482 temp = I915_READ(reg);
8db9d77b
ZW		 3483 temp &= ~FDI_LINK_TRAIN_NONE;
3484 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3485 I915_WRITE(reg, temp);
8db9d77b 3486
5eddb70b
CW		 3487 reg = FDI_RX_CTL(pipe);
3488 temp = I915_READ(reg);
8db9d77b
ZW		 3489 temp &= ~FDI_LINK_TRAIN_NONE;
3490 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3491 I915_WRITE(reg, temp);
8db9d77b 3492
5eddb70b
CW		 3493 POSTING_READ(reg);
3494 udelay(150);
8db9d77b 3495
5eddb70b 3496 reg = FDI_RX_IIR(pipe);
e1a44743 3497 for (tries = 0; tries < 5; tries++) {
5eddb70b 3498 temp = I915_READ(reg);
8db9d77b
ZW		 3499 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3500
3501 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 3502 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 3503 DRM_DEBUG_KMS("FDI train 2 done.\n");
3504 break;
3505 }
8db9d77b 3506 }
e1a44743 3507 if (tries == 5)
5eddb70b 3508 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3509
3510 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 3511
8db9d77b
ZW		 3512}
3513
0206e353 3514static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 3515 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3516 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3517 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3518 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3519};
3520
3521/* The FDI link training functions for SNB/Cougarpoint. */
3522static void gen6_fdi_link_train(struct drm_crtc *crtc)
3523{
3524 struct drm_device *dev = crtc->dev;
3525 struct drm_i915_private *dev_priv = dev->dev_private;
3526 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3527 int pipe = intel_crtc->pipe;
fa37d39e 3528 u32 reg, temp, i, retry;
8db9d77b 3529
e1a44743
AJ		 3530 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3531 for train result */
5eddb70b
CW		 3532 reg = FDI_RX_IMR(pipe);
3533 temp = I915_READ(reg);
e1a44743
AJ		 3534 temp &= ~FDI_RX_SYMBOL_LOCK;
3535 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3536 I915_WRITE(reg, temp);
3537
3538 POSTING_READ(reg);
e1a44743
AJ		 3539 udelay(150);
3540
8db9d77b 3541 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3542 reg = FDI_TX_CTL(pipe);
3543 temp = I915_READ(reg);
627eb5a3 3544 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3545 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3546 temp &= ~FDI_LINK_TRAIN_NONE;
3547 temp |= FDI_LINK_TRAIN_PATTERN_1;
3548 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3549 /* SNB-B */
3550 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 3551 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3552
d74cf324
DV		 3553 I915_WRITE(FDI_RX_MISC(pipe),
3554 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3555
5eddb70b
CW		 3556 reg = FDI_RX_CTL(pipe);
3557 temp = I915_READ(reg);
8db9d77b
ZW		 3558 if (HAS_PCH_CPT(dev)) {
3559 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3560 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3561 } else {
3562 temp &= ~FDI_LINK_TRAIN_NONE;
3563 temp |= FDI_LINK_TRAIN_PATTERN_1;
3564 }
5eddb70b
CW		 3565 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3566
3567 POSTING_READ(reg);
8db9d77b
ZW		 3568 udelay(150);
3569
0206e353 3570 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3571 reg = FDI_TX_CTL(pipe);
3572 temp = I915_READ(reg);
8db9d77b
ZW		 3573 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3574 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3575 I915_WRITE(reg, temp);
3576
3577 POSTING_READ(reg);
8db9d77b
ZW		 3578 udelay(500);
3579
fa37d39e
SP		 3580 for (retry = 0; retry < 5; retry++) {
3581 reg = FDI_RX_IIR(pipe);
3582 temp = I915_READ(reg);
3583 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3584 if (temp & FDI_RX_BIT_LOCK) {
3585 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3586 DRM_DEBUG_KMS("FDI train 1 done.\n");
3587 break;
3588 }
3589 udelay(50);
8db9d77b 3590 }
fa37d39e
SP		 3591 if (retry < 5)
3592 break;
8db9d77b
ZW		 3593 }
3594 if (i == 4)
5eddb70b 3595 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3596
3597 /* Train 2 */
5eddb70b
CW		 3598 reg = FDI_TX_CTL(pipe);
3599 temp = I915_READ(reg);
8db9d77b
ZW		 3600 temp &= ~FDI_LINK_TRAIN_NONE;
3601 temp |= FDI_LINK_TRAIN_PATTERN_2;
3602 if (IS_GEN6(dev)) {
3603 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3604 /* SNB-B */
3605 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3606 }
5eddb70b 3607 I915_WRITE(reg, temp);
8db9d77b 3608
5eddb70b
CW		 3609 reg = FDI_RX_CTL(pipe);
3610 temp = I915_READ(reg);
8db9d77b
ZW		 3611 if (HAS_PCH_CPT(dev)) {
3612 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3613 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3614 } else {
3615 temp &= ~FDI_LINK_TRAIN_NONE;
3616 temp |= FDI_LINK_TRAIN_PATTERN_2;
3617 }
5eddb70b
CW		 3618 I915_WRITE(reg, temp);
3619
3620 POSTING_READ(reg);
8db9d77b
ZW		 3621 udelay(150);
3622
0206e353 3623 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3624 reg = FDI_TX_CTL(pipe);
3625 temp = I915_READ(reg);
8db9d77b
ZW		 3626 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3627 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3628 I915_WRITE(reg, temp);
3629
3630 POSTING_READ(reg);
8db9d77b
ZW		 3631 udelay(500);
3632
fa37d39e
SP		 3633 for (retry = 0; retry < 5; retry++) {
3634 reg = FDI_RX_IIR(pipe);
3635 temp = I915_READ(reg);
3636 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3637 if (temp & FDI_RX_SYMBOL_LOCK) {
3638 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3639 DRM_DEBUG_KMS("FDI train 2 done.\n");
3640 break;
3641 }
3642 udelay(50);
8db9d77b 3643 }
fa37d39e
SP		 3644 if (retry < 5)
3645 break;
8db9d77b
ZW		 3646 }
3647 if (i == 4)
5eddb70b 3648 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3649
3650 DRM_DEBUG_KMS("FDI train done.\n");
3651}
3652
357555c0
JB		 3653/* Manual link training for Ivy Bridge A0 parts */
3654static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3655{
3656 struct drm_device *dev = crtc->dev;
3657 struct drm_i915_private *dev_priv = dev->dev_private;
3658 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3659 int pipe = intel_crtc->pipe;
139ccd3f 3660 u32 reg, temp, i, j;
357555c0
JB		 3661
3662 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3663 for train result */
3664 reg = FDI_RX_IMR(pipe);
3665 temp = I915_READ(reg);
3666 temp &= ~FDI_RX_SYMBOL_LOCK;
3667 temp &= ~FDI_RX_BIT_LOCK;
3668 I915_WRITE(reg, temp);
3669
3670 POSTING_READ(reg);
3671 udelay(150);
3672
01a415fd
DV		 3673 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3674 I915_READ(FDI_RX_IIR(pipe)));
3675
139ccd3f
JB		 3676 /* Try each vswing and preemphasis setting twice before moving on */
3677 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3678 /* disable first in case we need to retry */
3679 reg = FDI_TX_CTL(pipe);
3680 temp = I915_READ(reg);
3681 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3682 temp &= ~FDI_TX_ENABLE;
3683 I915_WRITE(reg, temp);
357555c0 3684
139ccd3f
JB		 3685 reg = FDI_RX_CTL(pipe);
3686 temp = I915_READ(reg);
3687 temp &= ~FDI_LINK_TRAIN_AUTO;
3688 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3689 temp &= ~FDI_RX_ENABLE;
3690 I915_WRITE(reg, temp);
357555c0 3691
139ccd3f 3692 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 3693 reg = FDI_TX_CTL(pipe);
3694 temp = I915_READ(reg);
139ccd3f 3695 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3696 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
139ccd3f 3697 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 3698 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 3699 temp |= snb_b_fdi_train_param[j/2];
3700 temp |= FDI_COMPOSITE_SYNC;
3701 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 3702
139ccd3f
JB		 3703 I915_WRITE(FDI_RX_MISC(pipe),
3704 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 3705
139ccd3f 3706 reg = FDI_RX_CTL(pipe);
357555c0 3707 temp = I915_READ(reg);
139ccd3f
JB		 3708 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3709 temp |= FDI_COMPOSITE_SYNC;
3710 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 3711
139ccd3f
JB		 3712 POSTING_READ(reg);
3713 udelay(1); /* should be 0.5us */
357555c0 3714
139ccd3f
JB		 3715 for (i = 0; i < 4; i++) {
3716 reg = FDI_RX_IIR(pipe);
3717 temp = I915_READ(reg);
3718 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3719
139ccd3f
JB		 3720 if (temp & FDI_RX_BIT_LOCK ||
3721 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3722 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3723 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3724 i);
3725 break;
3726 }
3727 udelay(1); /* should be 0.5us */
3728 }
3729 if (i == 4) {
3730 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3731 continue;
3732 }
357555c0 3733
139ccd3f 3734 /* Train 2 */
357555c0
JB		 3735 reg = FDI_TX_CTL(pipe);
3736 temp = I915_READ(reg);
139ccd3f
JB		 3737 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3738 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3739 I915_WRITE(reg, temp);
3740
3741 reg = FDI_RX_CTL(pipe);
3742 temp = I915_READ(reg);
3743 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3744 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 3745 I915_WRITE(reg, temp);
3746
3747 POSTING_READ(reg);
139ccd3f 3748 udelay(2); /* should be 1.5us */
357555c0 3749
139ccd3f
JB		 3750 for (i = 0; i < 4; i++) {
3751 reg = FDI_RX_IIR(pipe);
3752 temp = I915_READ(reg);
3753 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3754
139ccd3f
JB		 3755 if (temp & FDI_RX_SYMBOL_LOCK ||
3756 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3757 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3758 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3759 i);
3760 goto train_done;
3761 }
3762 udelay(2); /* should be 1.5us */
357555c0 3763 }
139ccd3f
JB		 3764 if (i == 4)
3765 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 3766 }
357555c0 3767
139ccd3f 3768train_done:
357555c0
JB		 3769 DRM_DEBUG_KMS("FDI train done.\n");
3770}
3771
88cefb6c 3772static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 3773{
88cefb6c 3774 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 3775 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 3776 int pipe = intel_crtc->pipe;
5eddb70b 3777 u32 reg, temp;
79e53945 3778
c64e311e 3779
c98e9dcf 3780 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 3781 reg = FDI_RX_CTL(pipe);
3782 temp = I915_READ(reg);
627eb5a3 3783 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
6e3c9717 3784 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
dfd07d72 3785 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 3786 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3787
3788 POSTING_READ(reg);
c98e9dcf
JB		 3789 udelay(200);
3790
3791 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 3792 temp = I915_READ(reg);
3793 I915_WRITE(reg, temp | FDI_PCDCLK);
3794
3795 POSTING_READ(reg);
c98e9dcf
JB		 3796 udelay(200);
3797
20749730
PZ		 3798 /* Enable CPU FDI TX PLL, always on for Ironlake */
3799 reg = FDI_TX_CTL(pipe);
3800 temp = I915_READ(reg);
3801 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3802 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 3803
20749730
PZ		 3804 POSTING_READ(reg);
3805 udelay(100);
6be4a607 3806 }
0e23b99d
JB		 3807}
3808
88cefb6c
DV		 3809static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3810{
3811 struct drm_device *dev = intel_crtc->base.dev;
3812 struct drm_i915_private *dev_priv = dev->dev_private;
3813 int pipe = intel_crtc->pipe;
3814 u32 reg, temp;
3815
3816 /* Switch from PCDclk to Rawclk */
3817 reg = FDI_RX_CTL(pipe);
3818 temp = I915_READ(reg);
3819 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3820
3821 /* Disable CPU FDI TX PLL */
3822 reg = FDI_TX_CTL(pipe);
3823 temp = I915_READ(reg);
3824 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3825
3826 POSTING_READ(reg);
3827 udelay(100);
3828
3829 reg = FDI_RX_CTL(pipe);
3830 temp = I915_READ(reg);
3831 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3832
3833 /* Wait for the clocks to turn off. */
3834 POSTING_READ(reg);
3835 udelay(100);
3836}
3837
0fc932b8
JB		 3838static void ironlake_fdi_disable(struct drm_crtc *crtc)
3839{
3840 struct drm_device *dev = crtc->dev;
3841 struct drm_i915_private *dev_priv = dev->dev_private;
3842 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3843 int pipe = intel_crtc->pipe;
3844 u32 reg, temp;
3845
3846 /* disable CPU FDI tx and PCH FDI rx */
3847 reg = FDI_TX_CTL(pipe);
3848 temp = I915_READ(reg);
3849 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3850 POSTING_READ(reg);
3851
3852 reg = FDI_RX_CTL(pipe);
3853 temp = I915_READ(reg);
3854 temp &= ~(0x7 << 16);
dfd07d72 3855 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3856 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3857
3858 POSTING_READ(reg);
3859 udelay(100);
3860
3861 /* Ironlake workaround, disable clock pointer after downing FDI */
eba905b2 3862 if (HAS_PCH_IBX(dev))
6f06ce18 3863 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 3864
3865 /* still set train pattern 1 */
3866 reg = FDI_TX_CTL(pipe);
3867 temp = I915_READ(reg);
3868 temp &= ~FDI_LINK_TRAIN_NONE;
3869 temp |= FDI_LINK_TRAIN_PATTERN_1;
3870 I915_WRITE(reg, temp);
3871
3872 reg = FDI_RX_CTL(pipe);
3873 temp = I915_READ(reg);
3874 if (HAS_PCH_CPT(dev)) {
3875 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3876 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3877 } else {
3878 temp &= ~FDI_LINK_TRAIN_NONE;
3879 temp |= FDI_LINK_TRAIN_PATTERN_1;
3880 }
3881 /* BPC in FDI rx is consistent with that in PIPECONF */
3882 temp &= ~(0x07 << 16);
dfd07d72 3883 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3884 I915_WRITE(reg, temp);
3885
3886 POSTING_READ(reg);
3887 udelay(100);
3888}
3889
5dce5b93
CW		 3890bool intel_has_pending_fb_unpin(struct drm_device *dev)
3891{
3892 struct intel_crtc *crtc;
3893
3894 /* Note that we don't need to be called with mode_config.lock here
3895 * as our list of CRTC objects is static for the lifetime of the
3896 * device and so cannot disappear as we iterate. Similarly, we can
3897 * happily treat the predicates as racy, atomic checks as userspace
3898 * cannot claim and pin a new fb without at least acquring the
3899 * struct_mutex and so serialising with us.
3900 */
d3fcc808 3901 for_each_intel_crtc(dev, crtc) {
5dce5b93
CW		 3902 if (atomic_read(&crtc->unpin_work_count) == 0)
3903 continue;
3904
3905 if (crtc->unpin_work)
3906 intel_wait_for_vblank(dev, crtc->pipe);
3907
3908 return true;
3909 }
3910
3911 return false;
3912}
3913
d6bbafa1
CW		 3914static void page_flip_completed(struct intel_crtc *intel_crtc)
3915{
3916 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3917 struct intel_unpin_work *work = intel_crtc->unpin_work;
3918
3919 /* ensure that the unpin work is consistent wrt ->pending. */
3920 smp_rmb();
3921 intel_crtc->unpin_work = NULL;
3922
3923 if (work->event)
3924 drm_send_vblank_event(intel_crtc->base.dev,
3925 intel_crtc->pipe,
3926 work->event);
3927
3928 drm_crtc_vblank_put(&intel_crtc->base);
3929
3930 wake_up_all(&dev_priv->pending_flip_queue);
3931 queue_work(dev_priv->wq, &work->work);
3932
3933 trace_i915_flip_complete(intel_crtc->plane,
3934 work->pending_flip_obj);
3935}
3936
46a55d30 3937void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
e6c3a2a6 3938{
0f91128d 3939 struct drm_device *dev = crtc->dev;
5bb61643 3940 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6 3941
2c10d571 3942 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
9c787942
CW		 3943 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3944 !intel_crtc_has_pending_flip(crtc),
3945 60*HZ) == 0)) {
3946 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2c10d571 3947
5e2d7afc 3948 spin_lock_irq(&dev->event_lock);
9c787942
CW		 3949 if (intel_crtc->unpin_work) {
3950 WARN_ONCE(1, "Removing stuck page flip\n");
3951 page_flip_completed(intel_crtc);
3952 }
5e2d7afc 3953 spin_unlock_irq(&dev->event_lock);
9c787942 3954 }
5bb61643 3955
975d568a
CW		 3956 if (crtc->primary->fb) {
3957 mutex_lock(&dev->struct_mutex);
3958 intel_finish_fb(crtc->primary->fb);
3959 mutex_unlock(&dev->struct_mutex);
3960 }
e6c3a2a6
CW		 3961}
3962
e615efe4
ED		 3963/* Program iCLKIP clock to the desired frequency */
3964static void lpt_program_iclkip(struct drm_crtc *crtc)
3965{
3966 struct drm_device *dev = crtc->dev;
3967 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3968 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
e615efe4
ED		 3969 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3970 u32 temp;
3971
09153000
DV		 3972 mutex_lock(&dev_priv->dpio_lock);
3973
e615efe4
ED		 3974 /* It is necessary to ungate the pixclk gate prior to programming
3975 * the divisors, and gate it back when it is done.
3976 */
3977 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3978
3979 /* Disable SSCCTL */
3980 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 3981 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3982 SBI_SSCCTL_DISABLE,
3983 SBI_ICLK);
e615efe4
ED		 3984
3985 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 3986 if (clock == 20000) {
e615efe4
ED		 3987 auxdiv = 1;
3988 divsel = 0x41;
3989 phaseinc = 0x20;
3990 } else {
3991 /* The iCLK virtual clock root frequency is in MHz,
241bfc38
DL		 3992 * but the adjusted_mode->crtc_clock in in KHz. To get the
3993 * divisors, it is necessary to divide one by another, so we
e615efe4
ED		 3994 * convert the virtual clock precision to KHz here for higher
3995 * precision.
3996 */
3997 u32 iclk_virtual_root_freq = 172800 * 1000;
3998 u32 iclk_pi_range = 64;
3999 u32 desired_divisor, msb_divisor_value, pi_value;
4000
12d7ceed 4001 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 4002 msb_divisor_value = desired_divisor / iclk_pi_range;
4003 pi_value = desired_divisor % iclk_pi_range;
4004
4005 auxdiv = 0;
4006 divsel = msb_divisor_value - 2;
4007 phaseinc = pi_value;
4008 }
4009
4010 /* This should not happen with any sane values */
4011 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4012 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4013 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4014 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4015
4016 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 4017 clock,
e615efe4
ED		 4018 auxdiv,
4019 divsel,
4020 phasedir,
4021 phaseinc);
4022
4023 /* Program SSCDIVINTPHASE6 */
988d6ee8 4024 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 4025 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4026 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4027 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4028 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4029 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4030 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 4031 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 4032
4033 /* Program SSCAUXDIV */
988d6ee8 4034 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 4035 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4036 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 4037 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 4038
4039 /* Enable modulator and associated divider */
988d6ee8 4040 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 4041 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 4042 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 4043
4044 /* Wait for initialization time */
4045 udelay(24);
4046
4047 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 4048
4049 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 4050}
4051
275f01b2
DV		 4052static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4053 enum pipe pch_transcoder)
4054{
4055 struct drm_device *dev = crtc->base.dev;
4056 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 4057 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
275f01b2
DV		 4058
4059 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4060 I915_READ(HTOTAL(cpu_transcoder)));
4061 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4062 I915_READ(HBLANK(cpu_transcoder)));
4063 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4064 I915_READ(HSYNC(cpu_transcoder)));
4065
4066 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4067 I915_READ(VTOTAL(cpu_transcoder)));
4068 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4069 I915_READ(VBLANK(cpu_transcoder)));
4070 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4071 I915_READ(VSYNC(cpu_transcoder)));
4072 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4073 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4074}
4075
003632d9 4076static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
1fbc0d78
DV		 4077{
4078 struct drm_i915_private *dev_priv = dev->dev_private;
4079 uint32_t temp;
4080
4081 temp = I915_READ(SOUTH_CHICKEN1);
003632d9 4082 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
1fbc0d78
DV		 4083 return;
4084
4085 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4086 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4087
003632d9
ACO		 4088 temp &= ~FDI_BC_BIFURCATION_SELECT;
4089 if (enable)
4090 temp |= FDI_BC_BIFURCATION_SELECT;
4091
4092 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
1fbc0d78
DV		 4093 I915_WRITE(SOUTH_CHICKEN1, temp);
4094 POSTING_READ(SOUTH_CHICKEN1);
4095}
4096
4097static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4098{
4099 struct drm_device *dev = intel_crtc->base.dev;
1fbc0d78
DV		 4100
4101 switch (intel_crtc->pipe) {
4102 case PIPE_A:
4103 break;
4104 case PIPE_B:
6e3c9717 4105 if (intel_crtc->config->fdi_lanes > 2)
003632d9 4106 cpt_set_fdi_bc_bifurcation(dev, false);
1fbc0d78 4107 else
003632d9 4108 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4109
4110 break;
4111 case PIPE_C:
003632d9 4112 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4113
4114 break;
4115 default:
4116 BUG();
4117 }
4118}
4119
f67a559d
JB		 4120/*
4121 * Enable PCH resources required for PCH ports:
4122 * - PCH PLLs
4123 * - FDI training & RX/TX
4124 * - update transcoder timings
4125 * - DP transcoding bits
4126 * - transcoder
4127 */
4128static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 4129{
4130 struct drm_device *dev = crtc->dev;
4131 struct drm_i915_private *dev_priv = dev->dev_private;
4132 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4133 int pipe = intel_crtc->pipe;
ee7b9f93 4134 u32 reg, temp;
2c07245f 4135
ab9412ba 4136 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 4137
1fbc0d78
DV		 4138 if (IS_IVYBRIDGE(dev))
4139 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4140
cd986abb
DV		 4141 /* Write the TU size bits before fdi link training, so that error
4142 * detection works. */
4143 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4144 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4145
c98e9dcf 4146 /* For PCH output, training FDI link */
674cf967 4147 dev_priv->display.fdi_link_train(crtc);
2c07245f 4148
3ad8a208
DV		 4149 /* We need to program the right clock selection before writing the pixel
4150 * mutliplier into the DPLL. */
303b81e0 4151 if (HAS_PCH_CPT(dev)) {
ee7b9f93 4152 u32 sel;
4b645f14 4153
c98e9dcf 4154 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 4155 temp |= TRANS_DPLL_ENABLE(pipe);
4156 sel = TRANS_DPLLB_SEL(pipe);
6e3c9717 4157 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 4158 temp |= sel;
4159 else
4160 temp &= ~sel;
c98e9dcf 4161 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 4162 }
5eddb70b 4163
3ad8a208
DV		 4164 /* XXX: pch pll's can be enabled any time before we enable the PCH
4165 * transcoder, and we actually should do this to not upset any PCH
4166 * transcoder that already use the clock when we share it.
4167 *
4168 * Note that enable_shared_dpll tries to do the right thing, but
4169 * get_shared_dpll unconditionally resets the pll - we need that to have
4170 * the right LVDS enable sequence. */
85b3894f 4171 intel_enable_shared_dpll(intel_crtc);
3ad8a208 4172
d9b6cb56
JB		 4173 /* set transcoder timing, panel must allow it */
4174 assert_panel_unlocked(dev_priv, pipe);
275f01b2 4175 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 4176
303b81e0 4177 intel_fdi_normal_train(crtc);
5e84e1a4 4178
c98e9dcf 4179 /* For PCH DP, enable TRANS_DP_CTL */
6e3c9717 4180 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
dfd07d72 4181 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 4182 reg = TRANS_DP_CTL(pipe);
4183 temp = I915_READ(reg);
4184 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 4185 TRANS_DP_SYNC_MASK |
4186 TRANS_DP_BPC_MASK);
5eddb70b
CW		 4187 temp |= (TRANS_DP_OUTPUT_ENABLE |
4188 TRANS_DP_ENH_FRAMING);
9325c9f0 4189 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 4190
4191 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 4192 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 4193 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 4194 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 4195
4196 switch (intel_trans_dp_port_sel(crtc)) {
4197 case PCH_DP_B:
5eddb70b 4198 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 4199 break;
4200 case PCH_DP_C:
5eddb70b 4201 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 4202 break;
4203 case PCH_DP_D:
5eddb70b 4204 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 4205 break;
4206 default:
e95d41e1 4207 BUG();
32f9d658 4208 }
2c07245f 4209
5eddb70b 4210 I915_WRITE(reg, temp);
6be4a607 4211 }
b52eb4dc 4212
b8a4f404 4213 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 4214}
4215
1507e5bd
PZ		 4216static void lpt_pch_enable(struct drm_crtc *crtc)
4217{
4218 struct drm_device *dev = crtc->dev;
4219 struct drm_i915_private *dev_priv = dev->dev_private;
4220 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 4221 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1507e5bd 4222
ab9412ba 4223 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 4224
8c52b5e8 4225 lpt_program_iclkip(crtc);
1507e5bd 4226
0540e488 4227 /* Set transcoder timing. */
275f01b2 4228 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 4229
937bb610 4230 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 4231}
4232
716c2e55 4233void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 4234{
e2b78267 4235 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 4236
4237 if (pll == NULL)
4238 return;
4239
3e369b76 4240 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
1e6f2ddc 4241 WARN(1, "bad %s crtc mask\n", pll->name);
ee7b9f93
JB		 4242 return;
4243 }
4244
3e369b76
ACO		 4245 pll->config.crtc_mask &= ~(1 << crtc->pipe);
4246 if (pll->config.crtc_mask == 0) {
f4a091c7
DV		 4247 WARN_ON(pll->on);
4248 WARN_ON(pll->active);
4249 }
4250
6e3c9717 4251 crtc->config->shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 4252}
4253
190f68c5
ACO		 4254struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4255 struct intel_crtc_state *crtc_state)
ee7b9f93 4256{
e2b78267 4257 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8bd31e67 4258 struct intel_shared_dpll *pll;
e2b78267 4259 enum intel_dpll_id i;
ee7b9f93 4260
98b6bd99
DV		 4261 if (HAS_PCH_IBX(dev_priv->dev)) {
4262 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 4263 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 4264 pll = &dev_priv->shared_dplls[i];
98b6bd99 4265
46edb027
DV		 4266 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4267 crtc->base.base.id, pll->name);
98b6bd99 4268
8bd31e67 4269 WARN_ON(pll->new_config->crtc_mask);
f2a69f44 4270
98b6bd99
DV		 4271 goto found;
4272 }
4273
bcddf610
S		 4274 if (IS_BROXTON(dev_priv->dev)) {
4275 /* PLL is attached to port in bxt */
4276 struct intel_encoder *encoder;
4277 struct intel_digital_port *intel_dig_port;
4278
4279 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4280 if (WARN_ON(!encoder))
4281 return NULL;
4282
4283 intel_dig_port = enc_to_dig_port(&encoder->base);
4284 /* 1:1 mapping between ports and PLLs */
4285 i = (enum intel_dpll_id)intel_dig_port->port;
4286 pll = &dev_priv->shared_dplls[i];
4287 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4288 crtc->base.base.id, pll->name);
4289 WARN_ON(pll->new_config->crtc_mask);
4290
4291 goto found;
4292 }
4293
e72f9fbf
DV		 4294 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4295 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 4296
4297 /* Only want to check enabled timings first */
8bd31e67 4298 if (pll->new_config->crtc_mask == 0)
ee7b9f93
JB		 4299 continue;
4300
190f68c5 4301 if (memcmp(&crtc_state->dpll_hw_state,
8bd31e67
ACO		 4302 &pll->new_config->hw_state,
4303 sizeof(pll->new_config->hw_state)) == 0) {
4304 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
1e6f2ddc 4305 crtc->base.base.id, pll->name,
8bd31e67
ACO		 4306 pll->new_config->crtc_mask,
4307 pll->active);
ee7b9f93
JB		 4308 goto found;
4309 }
4310 }
4311
4312 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 4313 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4314 pll = &dev_priv->shared_dplls[i];
8bd31e67 4315 if (pll->new_config->crtc_mask == 0) {
46edb027
DV		 4316 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4317 crtc->base.base.id, pll->name);
ee7b9f93
JB		 4318 goto found;
4319 }
4320 }
4321
4322 return NULL;
4323
4324found:
8bd31e67 4325 if (pll->new_config->crtc_mask == 0)
190f68c5 4326 pll->new_config->hw_state = crtc_state->dpll_hw_state;
f2a69f44 4327
190f68c5 4328 crtc_state->shared_dpll = i;
46edb027
DV		 4329 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4330 pipe_name(crtc->pipe));
ee7b9f93 4331
8bd31e67 4332 pll->new_config->crtc_mask |= 1 << crtc->pipe;
e04c7350 4333
ee7b9f93
JB		 4334 return pll;
4335}
4336
8bd31e67
ACO		 4337/**
4338 * intel_shared_dpll_start_config - start a new PLL staged config
4339 * @dev_priv: DRM device
4340 * @clear_pipes: mask of pipes that will have their PLLs freed
4341 *
4342 * Starts a new PLL staged config, copying the current config but
4343 * releasing the references of pipes specified in clear_pipes.
4344 */
4345static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4346 unsigned clear_pipes)
4347{
4348 struct intel_shared_dpll *pll;
4349 enum intel_dpll_id i;
4350
4351 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4352 pll = &dev_priv->shared_dplls[i];
4353
4354 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4355 GFP_KERNEL);
4356 if (!pll->new_config)
4357 goto cleanup;
4358
4359 pll->new_config->crtc_mask &= ~clear_pipes;
4360 }
4361
4362 return 0;
4363
4364cleanup:
4365 while (--i >= 0) {
4366 pll = &dev_priv->shared_dplls[i];
f354d733 4367 kfree(pll->new_config);
8bd31e67
ACO		 4368 pll->new_config = NULL;
4369 }
4370
4371 return -ENOMEM;
4372}
4373
4374static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4375{
4376 struct intel_shared_dpll *pll;
4377 enum intel_dpll_id i;
4378
4379 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4380 pll = &dev_priv->shared_dplls[i];
4381
4382 WARN_ON(pll->new_config == &pll->config);
4383
4384 pll->config = *pll->new_config;
4385 kfree(pll->new_config);
4386 pll->new_config = NULL;
4387 }
4388}
4389
4390static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4391{
4392 struct intel_shared_dpll *pll;
4393 enum intel_dpll_id i;
4394
4395 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4396 pll = &dev_priv->shared_dplls[i];
4397
4398 WARN_ON(pll->new_config == &pll->config);
4399
4400 kfree(pll->new_config);
4401 pll->new_config = NULL;
4402 }
4403}
4404
a1520318 4405static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 4406{
4407 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 4408 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 4409 u32 temp;
4410
4411 temp = I915_READ(dslreg);
4412 udelay(500);
4413 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 4414 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 4415 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 4416 }
4417}
4418
a1b2278e
CK		 4419/**
4420 * skl_update_scaler_users - Stages update to crtc's scaler state
4421 * @intel_crtc: crtc
4422 * @crtc_state: crtc_state
4423 * @plane: plane (NULL indicates crtc is requesting update)
4424 * @plane_state: plane's state
4425 * @force_detach: request unconditional detachment of scaler
4426 *
4427 * This function updates scaler state for requested plane or crtc.
4428 * To request scaler usage update for a plane, caller shall pass plane pointer.
4429 * To request scaler usage update for crtc, caller shall pass plane pointer
4430 * as NULL.
4431 *
4432 * Return
4433 * 0 - scaler_usage updated successfully
4434 * error - requested scaling cannot be supported or other error condition
4435 */
4436int
4437skl_update_scaler_users(
4438 struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state,
4439 struct intel_plane *intel_plane, struct intel_plane_state *plane_state,
4440 int force_detach)
4441{
4442 int need_scaling;
4443 int idx;
4444 int src_w, src_h, dst_w, dst_h;
4445 int *scaler_id;
4446 struct drm_framebuffer *fb;
4447 struct intel_crtc_scaler_state *scaler_state;
6156a456 4448 unsigned int rotation;
a1b2278e
CK		 4449
4450 if (!intel_crtc || !crtc_state)
4451 return 0;
4452
4453 scaler_state = &crtc_state->scaler_state;
4454
4455 idx = intel_plane ? drm_plane_index(&intel_plane->base) : SKL_CRTC_INDEX;
4456 fb = intel_plane ? plane_state->base.fb : NULL;
4457
4458 if (intel_plane) {
4459 src_w = drm_rect_width(&plane_state->src) >> 16;
4460 src_h = drm_rect_height(&plane_state->src) >> 16;
4461 dst_w = drm_rect_width(&plane_state->dst);
4462 dst_h = drm_rect_height(&plane_state->dst);
4463 scaler_id = &plane_state->scaler_id;
6156a456 4464 rotation = plane_state->base.rotation;
a1b2278e
CK		 4465 } else {
4466 struct drm_display_mode *adjusted_mode =
4467 &crtc_state->base.adjusted_mode;
4468 src_w = crtc_state->pipe_src_w;
4469 src_h = crtc_state->pipe_src_h;
4470 dst_w = adjusted_mode->hdisplay;
4471 dst_h = adjusted_mode->vdisplay;
4472 scaler_id = &scaler_state->scaler_id;
6156a456 4473 rotation = DRM_ROTATE_0;
a1b2278e 4474 }
6156a456
CK		 4475
4476 need_scaling = intel_rotation_90_or_270(rotation) ?
4477 (src_h != dst_w || src_w != dst_h):
4478 (src_w != dst_w || src_h != dst_h);
a1b2278e
CK		 4479
4480 /*
4481 * if plane is being disabled or scaler is no more required or force detach
4482 * - free scaler binded to this plane/crtc
4483 * - in order to do this, update crtc->scaler_usage
4484 *
4485 * Here scaler state in crtc_state is set free so that
4486 * scaler can be assigned to other user. Actual register
4487 * update to free the scaler is done in plane/panel-fit programming.
4488 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4489 */
4490 if (force_detach || !need_scaling || (intel_plane &&
4491 (!fb || !plane_state->visible))) {
4492 if (*scaler_id >= 0) {
4493 scaler_state->scaler_users &= ~(1 << idx);
4494 scaler_state->scalers[*scaler_id].in_use = 0;
4495
4496 DRM_DEBUG_KMS("Staged freeing scaler id %d.%d from %s:%d "
4497 "crtc_state = %p scaler_users = 0x%x\n",
4498 intel_crtc->pipe, *scaler_id, intel_plane ? "PLANE" : "CRTC",
4499 intel_plane ? intel_plane->base.base.id :
4500 intel_crtc->base.base.id, crtc_state,
4501 scaler_state->scaler_users);
4502 *scaler_id = -1;
4503 }
4504 return 0;
4505 }
4506
4507 /* range checks */
4508 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4509 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4510
4511 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4512 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4513 DRM_DEBUG_KMS("%s:%d scaler_user index %u.%u: src %ux%u dst %ux%u "
4514 "size is out of scaler range\n",
4515 intel_plane ? "PLANE" : "CRTC",
4516 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4517 intel_crtc->pipe, idx, src_w, src_h, dst_w, dst_h);
4518 return -EINVAL;
4519 }
4520
4521 /* check colorkey */
4522 if (intel_plane && intel_plane->ckey.flags != I915_SET_COLORKEY_NONE) {
4523 DRM_DEBUG_KMS("PLANE:%d scaling with color key not allowed",
4524 intel_plane->base.base.id);
4525 return -EINVAL;
4526 }
4527
4528 /* Check src format */
4529 if (intel_plane) {
4530 switch (fb->pixel_format) {
4531 case DRM_FORMAT_RGB565:
4532 case DRM_FORMAT_XBGR8888:
4533 case DRM_FORMAT_XRGB8888:
4534 case DRM_FORMAT_ABGR8888:
4535 case DRM_FORMAT_ARGB8888:
4536 case DRM_FORMAT_XRGB2101010:
4537 case DRM_FORMAT_ARGB2101010:
4538 case DRM_FORMAT_XBGR2101010:
4539 case DRM_FORMAT_ABGR2101010:
4540 case DRM_FORMAT_YUYV:
4541 case DRM_FORMAT_YVYU:
4542 case DRM_FORMAT_UYVY:
4543 case DRM_FORMAT_VYUY:
4544 break;
4545 default:
4546 DRM_DEBUG_KMS("PLANE:%d FB:%d unsupported scaling format 0x%x\n",
4547 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4548 return -EINVAL;
4549 }
4550 }
4551
4552 /* mark this plane as a scaler user in crtc_state */
4553 scaler_state->scaler_users |= (1 << idx);
4554 DRM_DEBUG_KMS("%s:%d staged scaling request for %ux%u->%ux%u "
4555 "crtc_state = %p scaler_users = 0x%x\n",
4556 intel_plane ? "PLANE" : "CRTC",
4557 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4558 src_w, src_h, dst_w, dst_h, crtc_state, scaler_state->scaler_users);
4559 return 0;
4560}
4561
4562static void skylake_pfit_update(struct intel_crtc *crtc, int enable)
bd2e244f
JB		 4563{
4564 struct drm_device *dev = crtc->base.dev;
4565 struct drm_i915_private *dev_priv = dev->dev_private;
4566 int pipe = crtc->pipe;
a1b2278e
CK		 4567 struct intel_crtc_scaler_state *scaler_state =
4568 &crtc->config->scaler_state;
4569
4570 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4571
4572 /* To update pfit, first update scaler state */
4573 skl_update_scaler_users(crtc, crtc->config, NULL, NULL, !enable);
4574 intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config);
4575 skl_detach_scalers(crtc);
4576 if (!enable)
4577 return;
bd2e244f 4578
6e3c9717 4579 if (crtc->config->pch_pfit.enabled) {
a1b2278e
CK		 4580 int id;
4581
4582 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4583 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4584 return;
4585 }
4586
4587 id = scaler_state->scaler_id;
4588 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4589 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4590 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4591 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4592
4593 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
bd2e244f
JB		 4594 }
4595}
4596
b074cec8
JB		 4597static void ironlake_pfit_enable(struct intel_crtc *crtc)
4598{
4599 struct drm_device *dev = crtc->base.dev;
4600 struct drm_i915_private *dev_priv = dev->dev_private;
4601 int pipe = crtc->pipe;
4602
6e3c9717 4603 if (crtc->config->pch_pfit.enabled) {
b074cec8
JB		 4604 /* Force use of hard-coded filter coefficients
4605 * as some pre-programmed values are broken,
4606 * e.g. x201.
4607 */
4608 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4609 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4610 PF_PIPE_SEL_IVB(pipe));
4611 else
4612 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
6e3c9717
ACO		 4613 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4614 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
d4270e57
JB		 4615 }
4616}
4617
4a3b8769 4618static void intel_enable_sprite_planes(struct drm_crtc *crtc)
bb53d4ae
VS		 4619{
4620 struct drm_device *dev = crtc->dev;
4621 enum pipe pipe = to_intel_crtc(crtc)->pipe;
af2b653b 4622 struct drm_plane *plane;
bb53d4ae
VS		 4623 struct intel_plane *intel_plane;
4624
af2b653b
MR		 4625 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4626 intel_plane = to_intel_plane(plane);
bb53d4ae
VS		 4627 if (intel_plane->pipe == pipe)
4628 intel_plane_restore(&intel_plane->base);
af2b653b 4629 }
bb53d4ae
VS		 4630}
4631
20bc8673 4632void hsw_enable_ips(struct intel_crtc *crtc)
d77e4531 4633{
cea165c3
VS		 4634 struct drm_device *dev = crtc->base.dev;
4635 struct drm_i915_private *dev_priv = dev->dev_private;
d77e4531 4636
6e3c9717 4637 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4638 return;
4639
cea165c3
VS		 4640 /* We can only enable IPS after we enable a plane and wait for a vblank */
4641 intel_wait_for_vblank(dev, crtc->pipe);
4642
d77e4531 4643 assert_plane_enabled(dev_priv, crtc->plane);
cea165c3 4644 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4645 mutex_lock(&dev_priv->rps.hw_lock);
4646 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4647 mutex_unlock(&dev_priv->rps.hw_lock);
4648 /* Quoting Art Runyan: "its not safe to expect any particular
4649 * value in IPS_CTL bit 31 after enabling IPS through the
e59150dc
JB		 4650 * mailbox." Moreover, the mailbox may return a bogus state,
4651 * so we need to just enable it and continue on.
2a114cc1
BW		 4652 */
4653 } else {
4654 I915_WRITE(IPS_CTL, IPS_ENABLE);
4655 /* The bit only becomes 1 in the next vblank, so this wait here
4656 * is essentially intel_wait_for_vblank. If we don't have this
4657 * and don't wait for vblanks until the end of crtc_enable, then
4658 * the HW state readout code will complain that the expected
4659 * IPS_CTL value is not the one we read. */
4660 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4661 DRM_ERROR("Timed out waiting for IPS enable\n");
4662 }
d77e4531
PZ		 4663}
4664
20bc8673 4665void hsw_disable_ips(struct intel_crtc *crtc)
d77e4531
PZ		 4666{
4667 struct drm_device *dev = crtc->base.dev;
4668 struct drm_i915_private *dev_priv = dev->dev_private;
4669
6e3c9717 4670 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4671 return;
4672
4673 assert_plane_enabled(dev_priv, crtc->plane);
23d0b130 4674 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4675 mutex_lock(&dev_priv->rps.hw_lock);
4676 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4677 mutex_unlock(&dev_priv->rps.hw_lock);
23d0b130
BW		 4678 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4679 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4680 DRM_ERROR("Timed out waiting for IPS disable\n");
e59150dc 4681 } else {
2a114cc1 4682 I915_WRITE(IPS_CTL, 0);
e59150dc
JB		 4683 POSTING_READ(IPS_CTL);
4684 }
d77e4531
PZ		 4685
4686 /* We need to wait for a vblank before we can disable the plane. */
4687 intel_wait_for_vblank(dev, crtc->pipe);
4688}
4689
4690/** Loads the palette/gamma unit for the CRTC with the prepared values */
4691static void intel_crtc_load_lut(struct drm_crtc *crtc)
4692{
4693 struct drm_device *dev = crtc->dev;
4694 struct drm_i915_private *dev_priv = dev->dev_private;
4695 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4696 enum pipe pipe = intel_crtc->pipe;
4697 int palreg = PALETTE(pipe);
4698 int i;
4699 bool reenable_ips = false;
4700
4701 /* The clocks have to be on to load the palette. */
83d65738 4702 if (!crtc->state->enable || !intel_crtc->active)
d77e4531
PZ		 4703 return;
4704
50360403 4705 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
409ee761 4706 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
d77e4531
PZ		 4707 assert_dsi_pll_enabled(dev_priv);
4708 else
4709 assert_pll_enabled(dev_priv, pipe);
4710 }
4711
4712 /* use legacy palette for Ironlake */
7a1db49a 4713 if (!HAS_GMCH_DISPLAY(dev))
d77e4531
PZ		 4714 palreg = LGC_PALETTE(pipe);
4715
4716 /* Workaround : Do not read or write the pipe palette/gamma data while
4717 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4718 */
6e3c9717 4719 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
d77e4531
PZ		 4720 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4721 GAMMA_MODE_MODE_SPLIT)) {
4722 hsw_disable_ips(intel_crtc);
4723 reenable_ips = true;
4724 }
4725
4726 for (i = 0; i < 256; i++) {
4727 I915_WRITE(palreg + 4 * i,
4728 (intel_crtc->lut_r[i] << 16) |
4729 (intel_crtc->lut_g[i] << 8) |
4730 intel_crtc->lut_b[i]);
4731 }
4732
4733 if (reenable_ips)
4734 hsw_enable_ips(intel_crtc);
4735}
4736
7cac945f 4737static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
d3eedb1a 4738{
7cac945f 4739 if (intel_crtc->overlay) {
d3eedb1a
VS		 4740 struct drm_device *dev = intel_crtc->base.dev;
4741 struct drm_i915_private *dev_priv = dev->dev_private;
4742
4743 mutex_lock(&dev->struct_mutex);
4744 dev_priv->mm.interruptible = false;
4745 (void) intel_overlay_switch_off(intel_crtc->overlay);
4746 dev_priv->mm.interruptible = true;
4747 mutex_unlock(&dev->struct_mutex);
4748 }
4749
4750 /* Let userspace switch the overlay on again. In most cases userspace
4751 * has to recompute where to put it anyway.
4752 */
4753}
4754
87d4300a
ML		 4755/**
4756 * intel_post_enable_primary - Perform operations after enabling primary plane
4757 * @crtc: the CRTC whose primary plane was just enabled
4758 *
4759 * Performs potentially sleeping operations that must be done after the primary
4760 * plane is enabled, such as updating FBC and IPS. Note that this may be
4761 * called due to an explicit primary plane update, or due to an implicit
4762 * re-enable that is caused when a sprite plane is updated to no longer
4763 * completely hide the primary plane.
4764 */
4765static void
4766intel_post_enable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4767{
4768 struct drm_device *dev = crtc->dev;
87d4300a 4769 struct drm_i915_private *dev_priv = dev->dev_private;
a5c4d7bc
VS		 4770 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4771 int pipe = intel_crtc->pipe;
a5c4d7bc 4772
87d4300a
ML		 4773 /*
4774 * BDW signals flip done immediately if the plane
4775 * is disabled, even if the plane enable is already
4776 * armed to occur at the next vblank :(
4777 */
4778 if (IS_BROADWELL(dev))
4779 intel_wait_for_vblank(dev, pipe);
a5c4d7bc 4780
87d4300a
ML		 4781 /*
4782 * FIXME IPS should be fine as long as one plane is
4783 * enabled, but in practice it seems to have problems
4784 * when going from primary only to sprite only and vice
4785 * versa.
4786 */
a5c4d7bc
VS		 4787 hsw_enable_ips(intel_crtc);
4788
4789 mutex_lock(&dev->struct_mutex);
7ff0ebcc 4790 intel_fbc_update(dev);
a5c4d7bc 4791 mutex_unlock(&dev->struct_mutex);
f99d7069
DV		 4792
4793 /*
87d4300a
ML		 4794 * Gen2 reports pipe underruns whenever all planes are disabled.
4795 * So don't enable underrun reporting before at least some planes
4796 * are enabled.
4797 * FIXME: Need to fix the logic to work when we turn off all planes
4798 * but leave the pipe running.
f99d7069 4799 */
87d4300a
ML		 4800 if (IS_GEN2(dev))
4801 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4802
4803 /* Underruns don't raise interrupts, so check manually. */
4804 if (HAS_GMCH_DISPLAY(dev))
4805 i9xx_check_fifo_underruns(dev_priv);
a5c4d7bc
VS		 4806}
4807
87d4300a
ML		 4808/**
4809 * intel_pre_disable_primary - Perform operations before disabling primary plane
4810 * @crtc: the CRTC whose primary plane is to be disabled
4811 *
4812 * Performs potentially sleeping operations that must be done before the
4813 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4814 * be called due to an explicit primary plane update, or due to an implicit
4815 * disable that is caused when a sprite plane completely hides the primary
4816 * plane.
4817 */
4818static void
4819intel_pre_disable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4820{
4821 struct drm_device *dev = crtc->dev;
4822 struct drm_i915_private *dev_priv = dev->dev_private;
4823 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4824 int pipe = intel_crtc->pipe;
a5c4d7bc 4825
87d4300a
ML		 4826 /*
4827 * Gen2 reports pipe underruns whenever all planes are disabled.
4828 * So diasble underrun reporting before all the planes get disabled.
4829 * FIXME: Need to fix the logic to work when we turn off all planes
4830 * but leave the pipe running.
4831 */
4832 if (IS_GEN2(dev))
4833 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
a5c4d7bc 4834
87d4300a
ML		 4835 /*
4836 * Vblank time updates from the shadow to live plane control register
4837 * are blocked if the memory self-refresh mode is active at that
4838 * moment. So to make sure the plane gets truly disabled, disable
4839 * first the self-refresh mode. The self-refresh enable bit in turn
4840 * will be checked/applied by the HW only at the next frame start
4841 * event which is after the vblank start event, so we need to have a
4842 * wait-for-vblank between disabling the plane and the pipe.
4843 */
4844 if (HAS_GMCH_DISPLAY(dev))
4845 intel_set_memory_cxsr(dev_priv, false);
4846
4847 mutex_lock(&dev->struct_mutex);
e35fef21 4848 if (dev_priv->fbc.crtc == intel_crtc)
7ff0ebcc 4849 intel_fbc_disable(dev);
87d4300a 4850 mutex_unlock(&dev->struct_mutex);
a5c4d7bc 4851
87d4300a
ML		 4852 /*
4853 * FIXME IPS should be fine as long as one plane is
4854 * enabled, but in practice it seems to have problems
4855 * when going from primary only to sprite only and vice
4856 * versa.
4857 */
a5c4d7bc 4858 hsw_disable_ips(intel_crtc);
87d4300a
ML		 4859}
4860
4861static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4862{
87d4300a
ML		 4863 intel_enable_primary_hw_plane(crtc->primary, crtc);
4864 intel_enable_sprite_planes(crtc);
4865 intel_crtc_update_cursor(crtc, true);
87d4300a
ML		 4866
4867 intel_post_enable_primary(crtc);
4868}
4869
4870static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4871{
4872 struct drm_device *dev = crtc->dev;
4873 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4874 struct intel_plane *intel_plane;
4875 int pipe = intel_crtc->pipe;
4876
4877 intel_crtc_wait_for_pending_flips(crtc);
4878
4879 intel_pre_disable_primary(crtc);
a5c4d7bc 4880
7cac945f 4881 intel_crtc_dpms_overlay_disable(intel_crtc);
27321ae8
ML		 4882 for_each_intel_plane(dev, intel_plane) {
4883 if (intel_plane->pipe == pipe) {
4884 struct drm_crtc *from = intel_plane->base.crtc;
4885
4886 intel_plane->disable_plane(&intel_plane->base,
4887 from ?: crtc, true);
4888 }
4889 }
f98551ae 4890
f99d7069
DV		 4891 /*
4892 * FIXME: Once we grow proper nuclear flip support out of this we need
4893 * to compute the mask of flip planes precisely. For the time being
4894 * consider this a flip to a NULL plane.
4895 */
4896 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
a5c4d7bc
VS		 4897}
4898
f67a559d
JB		 4899static void ironlake_crtc_enable(struct drm_crtc *crtc)
4900{
4901 struct drm_device *dev = crtc->dev;
4902 struct drm_i915_private *dev_priv = dev->dev_private;
4903 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4904 struct intel_encoder *encoder;
f67a559d 4905 int pipe = intel_crtc->pipe;
f67a559d 4906
83d65738 4907 WARN_ON(!crtc->state->enable);
08a48469 4908
f67a559d
JB		 4909 if (intel_crtc->active)
4910 return;
4911
6e3c9717 4912 if (intel_crtc->config->has_pch_encoder)
b14b1055
DV		 4913 intel_prepare_shared_dpll(intel_crtc);
4914
6e3c9717 4915 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4916 intel_dp_set_m_n(intel_crtc, M1_N1);
29407aab
DV		 4917
4918 intel_set_pipe_timings(intel_crtc);
4919
6e3c9717 4920 if (intel_crtc->config->has_pch_encoder) {
29407aab 4921 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4922 &intel_crtc->config->fdi_m_n, NULL);
29407aab
DV		 4923 }
4924
4925 ironlake_set_pipeconf(crtc);
4926
f67a559d 4927 intel_crtc->active = true;
8664281b 4928
a72e4c9f
DV		 4929 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4930 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
8664281b 4931
f6736a1a 4932 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 4933 if (encoder->pre_enable)
4934 encoder->pre_enable(encoder);
f67a559d 4935
6e3c9717 4936 if (intel_crtc->config->has_pch_encoder) {
fff367c7
DV		 4937 /* Note: FDI PLL enabling _must_ be done before we enable the
4938 * cpu pipes, hence this is separate from all the other fdi/pch
4939 * enabling. */
88cefb6c 4940 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 4941 } else {
4942 assert_fdi_tx_disabled(dev_priv, pipe);
4943 assert_fdi_rx_disabled(dev_priv, pipe);
4944 }
f67a559d 4945
b074cec8 4946 ironlake_pfit_enable(intel_crtc);
f67a559d 4947
9c54c0dd
JB		 4948 /*
4949 * On ILK+ LUT must be loaded before the pipe is running but with
4950 * clocks enabled
4951 */
4952 intel_crtc_load_lut(crtc);
4953
f37fcc2a 4954 intel_update_watermarks(crtc);
e1fdc473 4955 intel_enable_pipe(intel_crtc);
f67a559d 4956
6e3c9717 4957 if (intel_crtc->config->has_pch_encoder)
f67a559d 4958 ironlake_pch_enable(crtc);
c98e9dcf 4959
f9b61ff6
DV		 4960 assert_vblank_disabled(crtc);
4961 drm_crtc_vblank_on(crtc);
4962
fa5c73b1
DV		 4963 for_each_encoder_on_crtc(dev, crtc, encoder)
4964 encoder->enable(encoder);
61b77ddd
DV		 4965
4966 if (HAS_PCH_CPT(dev))
a1520318 4967 cpt_verify_modeset(dev, intel_crtc->pipe);
6be4a607
JB		 4968}
4969
42db64ef
PZ		 4970/* IPS only exists on ULT machines and is tied to pipe A. */
4971static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4972{
f5adf94e 4973 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 4974}
4975
e4916946
PZ		 4976/*
4977 * This implements the workaround described in the "notes" section of the mode
4978 * set sequence documentation. When going from no pipes or single pipe to
4979 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4980 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4981 */
4982static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4983{
4984 struct drm_device *dev = crtc->base.dev;
4985 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4986
4987 /* We want to get the other_active_crtc only if there's only 1 other
4988 * active crtc. */
d3fcc808 4989 for_each_intel_crtc(dev, crtc_it) {
e4916946
PZ		 4990 if (!crtc_it->active || crtc_it == crtc)
4991 continue;
4992
4993 if (other_active_crtc)
4994 return;
4995
4996 other_active_crtc = crtc_it;
4997 }
4998 if (!other_active_crtc)
4999 return;
5000
5001 intel_wait_for_vblank(dev, other_active_crtc->pipe);
5002 intel_wait_for_vblank(dev, other_active_crtc->pipe);
5003}
5004
4f771f10
PZ		 5005static void haswell_crtc_enable(struct drm_crtc *crtc)
5006{
5007 struct drm_device *dev = crtc->dev;
5008 struct drm_i915_private *dev_priv = dev->dev_private;
5009 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5010 struct intel_encoder *encoder;
5011 int pipe = intel_crtc->pipe;
4f771f10 5012
83d65738 5013 WARN_ON(!crtc->state->enable);
4f771f10
PZ		 5014
5015 if (intel_crtc->active)
5016 return;
5017
df8ad70c
DV		 5018 if (intel_crtc_to_shared_dpll(intel_crtc))
5019 intel_enable_shared_dpll(intel_crtc);
5020
6e3c9717 5021 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 5022 intel_dp_set_m_n(intel_crtc, M1_N1);
229fca97
DV		 5023
5024 intel_set_pipe_timings(intel_crtc);
5025
6e3c9717
ACO		 5026 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
5027 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
5028 intel_crtc->config->pixel_multiplier - 1);
ebb69c95
CT		 5029 }
5030
6e3c9717 5031 if (intel_crtc->config->has_pch_encoder) {
229fca97 5032 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 5033 &intel_crtc->config->fdi_m_n, NULL);
229fca97
DV		 5034 }
5035
5036 haswell_set_pipeconf(crtc);
5037
5038 intel_set_pipe_csc(crtc);
5039
4f771f10 5040 intel_crtc->active = true;
8664281b 5041
a72e4c9f 5042 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4f771f10
PZ		 5043 for_each_encoder_on_crtc(dev, crtc, encoder)
5044 if (encoder->pre_enable)
5045 encoder->pre_enable(encoder);
5046
6e3c9717 5047 if (intel_crtc->config->has_pch_encoder) {
a72e4c9f
DV		 5048 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5049 true);
4fe9467d
ID		 5050 dev_priv->display.fdi_link_train(crtc);
5051 }
5052
1f544388 5053 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 5054
ff6d9f55 5055 if (INTEL_INFO(dev)->gen == 9)
a1b2278e 5056 skylake_pfit_update(intel_crtc, 1);
ff6d9f55 5057 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 5058 ironlake_pfit_enable(intel_crtc);
ff6d9f55
JB		 5059 else
5060 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10
PZ		 5061
5062 /*
5063 * On ILK+ LUT must be loaded before the pipe is running but with
5064 * clocks enabled
5065 */
5066 intel_crtc_load_lut(crtc);
5067
1f544388 5068 intel_ddi_set_pipe_settings(crtc);
8228c251 5069 intel_ddi_enable_transcoder_func(crtc);
4f771f10 5070
f37fcc2a 5071 intel_update_watermarks(crtc);
e1fdc473 5072 intel_enable_pipe(intel_crtc);
42db64ef 5073
6e3c9717 5074 if (intel_crtc->config->has_pch_encoder)
1507e5bd 5075 lpt_pch_enable(crtc);
4f771f10 5076
6e3c9717 5077 if (intel_crtc->config->dp_encoder_is_mst)
0e32b39c
DA		 5078 intel_ddi_set_vc_payload_alloc(crtc, true);
5079
f9b61ff6
DV		 5080 assert_vblank_disabled(crtc);
5081 drm_crtc_vblank_on(crtc);
5082
8807e55b 5083 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 5084 encoder->enable(encoder);
8807e55b
JN		 5085 intel_opregion_notify_encoder(encoder, true);
5086 }
4f771f10 5087
e4916946
PZ		 5088 /* If we change the relative order between pipe/planes enabling, we need
5089 * to change the workaround. */
5090 haswell_mode_set_planes_workaround(intel_crtc);
4f771f10
PZ		 5091}
5092
3f8dce3a
DV		 5093static void ironlake_pfit_disable(struct intel_crtc *crtc)
5094{
5095 struct drm_device *dev = crtc->base.dev;
5096 struct drm_i915_private *dev_priv = dev->dev_private;
5097 int pipe = crtc->pipe;
5098
5099 /* To avoid upsetting the power well on haswell only disable the pfit if
5100 * it's in use. The hw state code will make sure we get this right. */
6e3c9717 5101 if (crtc->config->pch_pfit.enabled) {
3f8dce3a
DV		 5102 I915_WRITE(PF_CTL(pipe), 0);
5103 I915_WRITE(PF_WIN_POS(pipe), 0);
5104 I915_WRITE(PF_WIN_SZ(pipe), 0);
5105 }
5106}
5107
6be4a607
JB		 5108static void ironlake_crtc_disable(struct drm_crtc *crtc)
5109{
5110 struct drm_device *dev = crtc->dev;
5111 struct drm_i915_private *dev_priv = dev->dev_private;
5112 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 5113 struct intel_encoder *encoder;
6be4a607 5114 int pipe = intel_crtc->pipe;
5eddb70b 5115 u32 reg, temp;
b52eb4dc 5116
f7abfe8b
CW		 5117 if (!intel_crtc->active)
5118 return;
5119
ea9d758d
DV		 5120 for_each_encoder_on_crtc(dev, crtc, encoder)
5121 encoder->disable(encoder);
5122
f9b61ff6
DV		 5123 drm_crtc_vblank_off(crtc);
5124 assert_vblank_disabled(crtc);
5125
6e3c9717 5126 if (intel_crtc->config->has_pch_encoder)
a72e4c9f 5127 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
d925c59a 5128
575f7ab7 5129 intel_disable_pipe(intel_crtc);
32f9d658 5130
3f8dce3a 5131 ironlake_pfit_disable(intel_crtc);
2c07245f 5132
bf49ec8c
DV		 5133 for_each_encoder_on_crtc(dev, crtc, encoder)
5134 if (encoder->post_disable)
5135 encoder->post_disable(encoder);
2c07245f 5136
6e3c9717 5137 if (intel_crtc->config->has_pch_encoder) {
d925c59a 5138 ironlake_fdi_disable(crtc);
913d8d11 5139
d925c59a 5140 ironlake_disable_pch_transcoder(dev_priv, pipe);
6be4a607 5141
d925c59a
DV		 5142 if (HAS_PCH_CPT(dev)) {
5143 /* disable TRANS_DP_CTL */
5144 reg = TRANS_DP_CTL(pipe);
5145 temp = I915_READ(reg);
5146 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5147 TRANS_DP_PORT_SEL_MASK);
5148 temp |= TRANS_DP_PORT_SEL_NONE;
5149 I915_WRITE(reg, temp);
5150
5151 /* disable DPLL_SEL */
5152 temp = I915_READ(PCH_DPLL_SEL);
11887397 5153 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 5154 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 5155 }
e3421a18 5156
d925c59a 5157 /* disable PCH DPLL */
e72f9fbf 5158 intel_disable_shared_dpll(intel_crtc);
8db9d77b 5159
d925c59a
DV		 5160 ironlake_fdi_pll_disable(intel_crtc);
5161 }
6b383a7f 5162
f7abfe8b 5163 intel_crtc->active = false;
46ba614c 5164 intel_update_watermarks(crtc);
d1ebd816
BW		 5165
5166 mutex_lock(&dev->struct_mutex);
7ff0ebcc 5167 intel_fbc_update(dev);
d1ebd816 5168 mutex_unlock(&dev->struct_mutex);
6be4a607 5169}
1b3c7a47 5170
4f771f10 5171static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 5172{
4f771f10
PZ		 5173 struct drm_device *dev = crtc->dev;
5174 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 5175 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10 5176 struct intel_encoder *encoder;
6e3c9717 5177 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee7b9f93 5178
4f771f10
PZ		 5179 if (!intel_crtc->active)
5180 return;
5181
8807e55b
JN		 5182 for_each_encoder_on_crtc(dev, crtc, encoder) {
5183 intel_opregion_notify_encoder(encoder, false);
4f771f10 5184 encoder->disable(encoder);
8807e55b 5185 }
4f771f10 5186
f9b61ff6
DV		 5187 drm_crtc_vblank_off(crtc);
5188 assert_vblank_disabled(crtc);
5189
6e3c9717 5190 if (intel_crtc->config->has_pch_encoder)
a72e4c9f
DV		 5191 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5192 false);
575f7ab7 5193 intel_disable_pipe(intel_crtc);
4f771f10 5194
6e3c9717 5195 if (intel_crtc->config->dp_encoder_is_mst)
a4bf214f
VS		 5196 intel_ddi_set_vc_payload_alloc(crtc, false);
5197
ad80a810 5198 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 5199
ff6d9f55 5200 if (INTEL_INFO(dev)->gen == 9)
a1b2278e 5201 skylake_pfit_update(intel_crtc, 0);
ff6d9f55 5202 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 5203 ironlake_pfit_disable(intel_crtc);
ff6d9f55
JB		 5204 else
5205 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10 5206
1f544388 5207 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10 5208
6e3c9717 5209 if (intel_crtc->config->has_pch_encoder) {
ab4d966c 5210 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 5211 intel_ddi_fdi_disable(crtc);
83616634 5212 }
4f771f10 5213
97b040aa
ID		 5214 for_each_encoder_on_crtc(dev, crtc, encoder)
5215 if (encoder->post_disable)
5216 encoder->post_disable(encoder);
5217
4f771f10 5218 intel_crtc->active = false;
46ba614c 5219 intel_update_watermarks(crtc);
4f771f10
PZ		 5220
5221 mutex_lock(&dev->struct_mutex);
7ff0ebcc 5222 intel_fbc_update(dev);
4f771f10 5223 mutex_unlock(&dev->struct_mutex);
df8ad70c
DV		 5224
5225 if (intel_crtc_to_shared_dpll(intel_crtc))
5226 intel_disable_shared_dpll(intel_crtc);
4f771f10
PZ		 5227}
5228
ee7b9f93
JB		 5229static void ironlake_crtc_off(struct drm_crtc *crtc)
5230{
5231 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 5232 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 5233}
5234
6441ab5f 5235
2dd24552
JB		 5236static void i9xx_pfit_enable(struct intel_crtc *crtc)
5237{
5238 struct drm_device *dev = crtc->base.dev;
5239 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 5240 struct intel_crtc_state *pipe_config = crtc->config;
2dd24552 5241
681a8504 5242 if (!pipe_config->gmch_pfit.control)
2dd24552
JB		 5243 return;
5244
2dd24552 5245 /*
c0b03411
DV		 5246 * The panel fitter should only be adjusted whilst the pipe is disabled,
5247 * according to register description and PRM.
2dd24552 5248 */
c0b03411
DV		 5249 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5250 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 5251
b074cec8
JB		 5252 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5253 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 5254
5255 /* Border color in case we don't scale up to the full screen. Black by
5256 * default, change to something else for debugging. */
5257 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 5258}
5259
d05410f9
DA		 5260static enum intel_display_power_domain port_to_power_domain(enum port port)
5261{
5262 switch (port) {
5263 case PORT_A:
5264 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5265 case PORT_B:
5266 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5267 case PORT_C:
5268 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5269 case PORT_D:
5270 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5271 default:
5272 WARN_ON_ONCE(1);
5273 return POWER_DOMAIN_PORT_OTHER;
5274 }
5275}
5276
77d22dca
ID		 5277#define for_each_power_domain(domain, mask) \
5278 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5279 if ((1 << (domain)) & (mask))
5280
319be8ae
ID		 5281enum intel_display_power_domain
5282intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5283{
5284 struct drm_device *dev = intel_encoder->base.dev;
5285 struct intel_digital_port *intel_dig_port;
5286
5287 switch (intel_encoder->type) {
5288 case INTEL_OUTPUT_UNKNOWN:
5289 /* Only DDI platforms should ever use this output type */
5290 WARN_ON_ONCE(!HAS_DDI(dev));
5291 case INTEL_OUTPUT_DISPLAYPORT:
5292 case INTEL_OUTPUT_HDMI:
5293 case INTEL_OUTPUT_EDP:
5294 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
d05410f9 5295 return port_to_power_domain(intel_dig_port->port);
0e32b39c
DA		 5296 case INTEL_OUTPUT_DP_MST:
5297 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5298 return port_to_power_domain(intel_dig_port->port);
319be8ae
ID		 5299 case INTEL_OUTPUT_ANALOG:
5300 return POWER_DOMAIN_PORT_CRT;
5301 case INTEL_OUTPUT_DSI:
5302 return POWER_DOMAIN_PORT_DSI;
5303 default:
5304 return POWER_DOMAIN_PORT_OTHER;
5305 }
5306}
5307
5308static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 5309{
319be8ae
ID		 5310 struct drm_device *dev = crtc->dev;
5311 struct intel_encoder *intel_encoder;
5312 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5313 enum pipe pipe = intel_crtc->pipe;
77d22dca
ID		 5314 unsigned long mask;
5315 enum transcoder transcoder;
5316
5317 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5318
5319 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5320 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6e3c9717
ACO		 5321 if (intel_crtc->config->pch_pfit.enabled ||
5322 intel_crtc->config->pch_pfit.force_thru)
77d22dca
ID		 5323 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5324
319be8ae
ID		 5325 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5326 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5327
77d22dca
ID		 5328 return mask;
5329}
5330
679dacd4 5331static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
77d22dca 5332{
679dacd4 5333 struct drm_device *dev = state->dev;
77d22dca
ID		 5334 struct drm_i915_private *dev_priv = dev->dev_private;
5335 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
5336 struct intel_crtc *crtc;
5337
5338 /*
5339 * First get all needed power domains, then put all unneeded, to avoid
5340 * any unnecessary toggling of the power wells.
5341 */
d3fcc808 5342 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 5343 enum intel_display_power_domain domain;
5344
83d65738 5345 if (!crtc->base.state->enable)
77d22dca
ID		 5346 continue;
5347
319be8ae 5348 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
77d22dca
ID		 5349
5350 for_each_power_domain(domain, pipe_domains[crtc->pipe])
5351 intel_display_power_get(dev_priv, domain);
5352 }
5353
50f6e502 5354 if (dev_priv->display.modeset_global_resources)
679dacd4 5355 dev_priv->display.modeset_global_resources(state);
50f6e502 5356
d3fcc808 5357 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 5358 enum intel_display_power_domain domain;
5359
5360 for_each_power_domain(domain, crtc->enabled_power_domains)
5361 intel_display_power_put(dev_priv, domain);
5362
5363 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
5364 }
5365
5366 intel_display_set_init_power(dev_priv, false);
5367}
5368
f8437dd1
VK		 5369void broxton_set_cdclk(struct drm_device *dev, int frequency)
5370{
5371 struct drm_i915_private *dev_priv = dev->dev_private;
5372 uint32_t divider;
5373 uint32_t ratio;
5374 uint32_t current_freq;
5375 int ret;
5376
5377 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5378 switch (frequency) {
5379 case 144000:
5380 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5381 ratio = BXT_DE_PLL_RATIO(60);
5382 break;
5383 case 288000:
5384 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5385 ratio = BXT_DE_PLL_RATIO(60);
5386 break;
5387 case 384000:
5388 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5389 ratio = BXT_DE_PLL_RATIO(60);
5390 break;
5391 case 576000:
5392 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5393 ratio = BXT_DE_PLL_RATIO(60);
5394 break;
5395 case 624000:
5396 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5397 ratio = BXT_DE_PLL_RATIO(65);
5398 break;
5399 case 19200:
5400 /*
5401 * Bypass frequency with DE PLL disabled. Init ratio, divider
5402 * to suppress GCC warning.
5403 */
5404 ratio = 0;
5405 divider = 0;
5406 break;
5407 default:
5408 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5409
5410 return;
5411 }
5412
5413 mutex_lock(&dev_priv->rps.hw_lock);
5414 /* Inform power controller of upcoming frequency change */
5415 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5416 0x80000000);
5417 mutex_unlock(&dev_priv->rps.hw_lock);
5418
5419 if (ret) {
5420 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5421 ret, frequency);
5422 return;
5423 }
5424
5425 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5426 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5427 current_freq = current_freq * 500 + 1000;
5428
5429 /*
5430 * DE PLL has to be disabled when
5431 * - setting to 19.2MHz (bypass, PLL isn't used)
5432 * - before setting to 624MHz (PLL needs toggling)
5433 * - before setting to any frequency from 624MHz (PLL needs toggling)
5434 */
5435 if (frequency == 19200 || frequency == 624000 ||
5436 current_freq == 624000) {
5437 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5438 /* Timeout 200us */
5439 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5440 1))
5441 DRM_ERROR("timout waiting for DE PLL unlock\n");
5442 }
5443
5444 if (frequency != 19200) {
5445 uint32_t val;
5446
5447 val = I915_READ(BXT_DE_PLL_CTL);
5448 val &= ~BXT_DE_PLL_RATIO_MASK;
5449 val |= ratio;
5450 I915_WRITE(BXT_DE_PLL_CTL, val);
5451
5452 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5453 /* Timeout 200us */
5454 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5455 DRM_ERROR("timeout waiting for DE PLL lock\n");
5456
5457 val = I915_READ(CDCLK_CTL);
5458 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5459 val |= divider;
5460 /*
5461 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5462 * enable otherwise.
5463 */
5464 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5465 if (frequency >= 500000)
5466 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5467
5468 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5469 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5470 val |= (frequency - 1000) / 500;
5471 I915_WRITE(CDCLK_CTL, val);
5472 }
5473
5474 mutex_lock(&dev_priv->rps.hw_lock);
5475 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5476 DIV_ROUND_UP(frequency, 25000));
5477 mutex_unlock(&dev_priv->rps.hw_lock);
5478
5479 if (ret) {
5480 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5481 ret, frequency);
5482 return;
5483 }
5484
5485 dev_priv->cdclk_freq = frequency;
5486}
5487
5488void broxton_init_cdclk(struct drm_device *dev)
5489{
5490 struct drm_i915_private *dev_priv = dev->dev_private;
5491 uint32_t val;
5492
5493 /*
5494 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5495 * or else the reset will hang because there is no PCH to respond.
5496 * Move the handshake programming to initialization sequence.
5497 * Previously was left up to BIOS.
5498 */
5499 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5500 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5501 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5502
5503 /* Enable PG1 for cdclk */
5504 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5505
5506 /* check if cd clock is enabled */
5507 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5508 DRM_DEBUG_KMS("Display already initialized\n");
5509 return;
5510 }
5511
5512 /*
5513 * FIXME:
5514 * - The initial CDCLK needs to be read from VBT.
5515 * Need to make this change after VBT has changes for BXT.
5516 * - check if setting the max (or any) cdclk freq is really necessary
5517 * here, it belongs to modeset time
5518 */
5519 broxton_set_cdclk(dev, 624000);
5520
5521 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
22e02c0b
VS		 5522 POSTING_READ(DBUF_CTL);
5523
f8437dd1
VK		 5524 udelay(10);
5525
5526 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5527 DRM_ERROR("DBuf power enable timeout!\n");
5528}
5529
5530void broxton_uninit_cdclk(struct drm_device *dev)
5531{
5532 struct drm_i915_private *dev_priv = dev->dev_private;
5533
5534 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
22e02c0b
VS		 5535 POSTING_READ(DBUF_CTL);
5536
f8437dd1
VK		 5537 udelay(10);
5538
5539 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5540 DRM_ERROR("DBuf power disable timeout!\n");
5541
5542 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5543 broxton_set_cdclk(dev, 19200);
5544
5545 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5546}
5547
dfcab17e 5548/* returns HPLL frequency in kHz */
f8bf63fd 5549static int valleyview_get_vco(struct drm_i915_private *dev_priv)
30a970c6 5550{
586f49dc 5551 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
30a970c6 5552
586f49dc
JB		 5553 /* Obtain SKU information */
5554 mutex_lock(&dev_priv->dpio_lock);
5555 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5556 CCK_FUSE_HPLL_FREQ_MASK;
5557 mutex_unlock(&dev_priv->dpio_lock);
30a970c6 5558
dfcab17e 5559 return vco_freq[hpll_freq] * 1000;
30a970c6
JB		 5560}
5561
f8bf63fd
VS		 5562static void vlv_update_cdclk(struct drm_device *dev)
5563{
5564 struct drm_i915_private *dev_priv = dev->dev_private;
5565
164dfd28 5566 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
43dc52c3 5567 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
164dfd28 5568 dev_priv->cdclk_freq);
f8bf63fd
VS		 5569
5570 /*
5571 * Program the gmbus_freq based on the cdclk frequency.
5572 * BSpec erroneously claims we should aim for 4MHz, but
5573 * in fact 1MHz is the correct frequency.
5574 */
164dfd28 5575 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
f8bf63fd
VS		 5576}
5577
30a970c6
JB		 5578/* Adjust CDclk dividers to allow high res or save power if possible */
5579static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5580{
5581 struct drm_i915_private *dev_priv = dev->dev_private;
5582 u32 val, cmd;
5583
164dfd28
VK		 5584 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5585 != dev_priv->cdclk_freq);
d60c4473 5586
dfcab17e 5587 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
30a970c6 5588 cmd = 2;
dfcab17e 5589 else if (cdclk == 266667)
30a970c6
JB		 5590 cmd = 1;
5591 else
5592 cmd = 0;
5593
5594 mutex_lock(&dev_priv->rps.hw_lock);
5595 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5596 val &= ~DSPFREQGUAR_MASK;
5597 val |= (cmd << DSPFREQGUAR_SHIFT);
5598 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5599 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5600 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5601 50)) {
5602 DRM_ERROR("timed out waiting for CDclk change\n");
5603 }
5604 mutex_unlock(&dev_priv->rps.hw_lock);
5605
dfcab17e 5606 if (cdclk == 400000) {
6bcda4f0 5607 u32 divider;
30a970c6 5608
6bcda4f0 5609 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
30a970c6
JB		 5610
5611 mutex_lock(&dev_priv->dpio_lock);
5612 /* adjust cdclk divider */
5613 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
9cf33db5 5614 val &= ~DISPLAY_FREQUENCY_VALUES;
30a970c6
JB		 5615 val |= divider;
5616 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
a877e801
VS		 5617
5618 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5619 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5620 50))
5621 DRM_ERROR("timed out waiting for CDclk change\n");
30a970c6
JB		 5622 mutex_unlock(&dev_priv->dpio_lock);
5623 }
5624
5625 mutex_lock(&dev_priv->dpio_lock);
5626 /* adjust self-refresh exit latency value */
5627 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5628 val &= ~0x7f;
5629
5630 /*
5631 * For high bandwidth configs, we set a higher latency in the bunit
5632 * so that the core display fetch happens in time to avoid underruns.
5633 */
dfcab17e 5634 if (cdclk == 400000)
30a970c6
JB		 5635 val |= 4500 / 250; /* 4.5 usec */
5636 else
5637 val |= 3000 / 250; /* 3.0 usec */
5638 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5639 mutex_unlock(&dev_priv->dpio_lock);
5640
f8bf63fd 5641 vlv_update_cdclk(dev);
30a970c6
JB		 5642}
5643
383c5a6a
VS		 5644static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5645{
5646 struct drm_i915_private *dev_priv = dev->dev_private;
5647 u32 val, cmd;
5648
164dfd28
VK		 5649 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5650 != dev_priv->cdclk_freq);
383c5a6a
VS		 5651
5652 switch (cdclk) {
383c5a6a
VS		 5653 case 333333:
5654 case 320000:
383c5a6a 5655 case 266667:
383c5a6a 5656 case 200000:
383c5a6a
VS		 5657 break;
5658 default:
5f77eeb0 5659 MISSING_CASE(cdclk);
383c5a6a
VS		 5660 return;
5661 }
5662
9d0d3fda
VS		 5663 /*
5664 * Specs are full of misinformation, but testing on actual
5665 * hardware has shown that we just need to write the desired
5666 * CCK divider into the Punit register.
5667 */
5668 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5669
383c5a6a
VS		 5670 mutex_lock(&dev_priv->rps.hw_lock);
5671 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5672 val &= ~DSPFREQGUAR_MASK_CHV;
5673 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5674 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5675 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5676 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5677 50)) {
5678 DRM_ERROR("timed out waiting for CDclk change\n");
5679 }
5680 mutex_unlock(&dev_priv->rps.hw_lock);
5681
5682 vlv_update_cdclk(dev);
5683}
5684
30a970c6
JB		 5685static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5686 int max_pixclk)
5687{
6bcda4f0 5688 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6cca3195 5689 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
29dc7ef3 5690
30a970c6
JB		 5691 /*
5692 * Really only a few cases to deal with, as only 4 CDclks are supported:
5693 * 200MHz
5694 * 267MHz
29dc7ef3 5695 * 320/333MHz (depends on HPLL freq)
6cca3195
VS		 5696 * 400MHz (VLV only)
5697 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5698 * of the lower bin and adjust if needed.
e37c67a1
VS		 5699 *
5700 * We seem to get an unstable or solid color picture at 200MHz.
5701 * Not sure what's wrong. For now use 200MHz only when all pipes
5702 * are off.
30a970c6 5703 */
6cca3195
VS		 5704 if (!IS_CHERRYVIEW(dev_priv) &&
5705 max_pixclk > freq_320*limit/100)
dfcab17e 5706 return 400000;
6cca3195 5707 else if (max_pixclk > 266667*limit/100)
29dc7ef3 5708 return freq_320;
e37c67a1 5709 else if (max_pixclk > 0)
dfcab17e 5710 return 266667;
e37c67a1
VS		 5711 else
5712 return 200000;
30a970c6
JB		 5713}
5714
f8437dd1
VK		 5715static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5716 int max_pixclk)
5717{
5718 /*
5719 * FIXME:
5720 * - remove the guardband, it's not needed on BXT
5721 * - set 19.2MHz bypass frequency if there are no active pipes
5722 */
5723 if (max_pixclk > 576000*9/10)
5724 return 624000;
5725 else if (max_pixclk > 384000*9/10)
5726 return 576000;
5727 else if (max_pixclk > 288000*9/10)
5728 return 384000;
5729 else if (max_pixclk > 144000*9/10)
5730 return 288000;
5731 else
5732 return 144000;
5733}
5734
2f2d7aa1 5735/* compute the max pixel clock for new configuration */
304603f4 5736static int intel_mode_max_pixclk(struct drm_atomic_state *state)
30a970c6 5737{
304603f4 5738 struct drm_device *dev = state->dev;
30a970c6 5739 struct intel_crtc *intel_crtc;
304603f4 5740 struct intel_crtc_state *crtc_state;
30a970c6
JB		 5741 int max_pixclk = 0;
5742
d3fcc808 5743 for_each_intel_crtc(dev, intel_crtc) {
304603f4
ACO		 5744 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5745 if (IS_ERR(crtc_state))
5746 return PTR_ERR(crtc_state);
5747
5748 if (!crtc_state->base.enable)
5749 continue;
5750
5751 max_pixclk = max(max_pixclk,
5752 crtc_state->base.adjusted_mode.crtc_clock);
30a970c6
JB		 5753 }
5754
5755 return max_pixclk;
5756}
5757
304603f4 5758static int valleyview_modeset_global_pipes(struct drm_atomic_state *state,
2f2d7aa1 5759 unsigned *prepare_pipes)
30a970c6 5760{
304603f4 5761 struct drm_i915_private *dev_priv = to_i915(state->dev);
30a970c6 5762 struct intel_crtc *intel_crtc;
304603f4 5763 int max_pixclk = intel_mode_max_pixclk(state);
f8437dd1 5764 int cdclk;
30a970c6 5765
304603f4
ACO		 5766 if (max_pixclk < 0)
5767 return max_pixclk;
30a970c6 5768
f8437dd1
VK		 5769 if (IS_VALLEYVIEW(dev_priv))
5770 cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5771 else
5772 cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
5773
5774 if (cdclk == dev_priv->cdclk_freq)
304603f4 5775 return 0;
30a970c6 5776
2f2d7aa1 5777 /* disable/enable all currently active pipes while we change cdclk */
304603f4 5778 for_each_intel_crtc(state->dev, intel_crtc)
83d65738 5779 if (intel_crtc->base.state->enable)
30a970c6 5780 *prepare_pipes |= (1 << intel_crtc->pipe);
304603f4
ACO		 5781
5782 return 0;
30a970c6
JB		 5783}
5784
1e69cd74
VS		 5785static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5786{
5787 unsigned int credits, default_credits;
5788
5789 if (IS_CHERRYVIEW(dev_priv))
5790 default_credits = PFI_CREDIT(12);
5791 else
5792 default_credits = PFI_CREDIT(8);
5793
164dfd28 5794 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
1e69cd74
VS		 5795 /* CHV suggested value is 31 or 63 */
5796 if (IS_CHERRYVIEW(dev_priv))
5797 credits = PFI_CREDIT_31;
5798 else
5799 credits = PFI_CREDIT(15);
5800 } else {
5801 credits = default_credits;
5802 }
5803
5804 /*
5805 * WA - write default credits before re-programming
5806 * FIXME: should we also set the resend bit here?
5807 */
5808 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5809 default_credits);
5810
5811 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5812 credits | PFI_CREDIT_RESEND);
5813
5814 /*
5815 * FIXME is this guaranteed to clear
5816 * immediately or should we poll for it?
5817 */
5818 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5819}
5820
679dacd4 5821static void valleyview_modeset_global_resources(struct drm_atomic_state *state)
30a970c6 5822{
679dacd4 5823 struct drm_device *dev = state->dev;
30a970c6 5824 struct drm_i915_private *dev_priv = dev->dev_private;
304603f4
ACO		 5825 int max_pixclk = intel_mode_max_pixclk(state);
5826 int req_cdclk;
5827
5828 /* The only reason this can fail is if we fail to add the crtc_state
5829 * to the atomic state. But that can't happen since the call to
5830 * intel_mode_max_pixclk() in valleyview_modeset_global_pipes() (which
5831 * can't have failed otherwise the mode set would be aborted) added all
5832 * the states already. */
5833 if (WARN_ON(max_pixclk < 0))
5834 return;
30a970c6 5835
304603f4 5836 req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
30a970c6 5837
164dfd28 5838 if (req_cdclk != dev_priv->cdclk_freq) {
738c05c0
ID		 5839 /*
5840 * FIXME: We can end up here with all power domains off, yet
5841 * with a CDCLK frequency other than the minimum. To account
5842 * for this take the PIPE-A power domain, which covers the HW
5843 * blocks needed for the following programming. This can be
5844 * removed once it's guaranteed that we get here either with
5845 * the minimum CDCLK set, or the required power domains
5846 * enabled.
5847 */
5848 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5849
383c5a6a
VS		 5850 if (IS_CHERRYVIEW(dev))
5851 cherryview_set_cdclk(dev, req_cdclk);
5852 else
5853 valleyview_set_cdclk(dev, req_cdclk);
738c05c0 5854
1e69cd74
VS		 5855 vlv_program_pfi_credits(dev_priv);
5856
738c05c0 5857 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
383c5a6a 5858 }
30a970c6
JB		 5859}
5860
89b667f8
JB		 5861static void valleyview_crtc_enable(struct drm_crtc *crtc)
5862{
5863 struct drm_device *dev = crtc->dev;
a72e4c9f 5864 struct drm_i915_private *dev_priv = to_i915(dev);
89b667f8
JB		 5865 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5866 struct intel_encoder *encoder;
5867 int pipe = intel_crtc->pipe;
23538ef1 5868 bool is_dsi;
89b667f8 5869
83d65738 5870 WARN_ON(!crtc->state->enable);
89b667f8
JB		 5871
5872 if (intel_crtc->active)
5873 return;
5874
409ee761 5875 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
8525a235 5876
1ae0d137
VS		 5877 if (!is_dsi) {
5878 if (IS_CHERRYVIEW(dev))
6e3c9717 5879 chv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 5880 else
6e3c9717 5881 vlv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 5882 }
5b18e57c 5883
6e3c9717 5884 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 5885 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 5886
5887 intel_set_pipe_timings(intel_crtc);
5888
c14b0485
VS		 5889 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5890 struct drm_i915_private *dev_priv = dev->dev_private;
5891
5892 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5893 I915_WRITE(CHV_CANVAS(pipe), 0);
5894 }
5895
5b18e57c
DV		 5896 i9xx_set_pipeconf(intel_crtc);
5897
89b667f8 5898 intel_crtc->active = true;
89b667f8 5899
a72e4c9f 5900 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 5901
89b667f8
JB		 5902 for_each_encoder_on_crtc(dev, crtc, encoder)
5903 if (encoder->pre_pll_enable)
5904 encoder->pre_pll_enable(encoder);
5905
9d556c99
CML		 5906 if (!is_dsi) {
5907 if (IS_CHERRYVIEW(dev))
6e3c9717 5908 chv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 5909 else
6e3c9717 5910 vlv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 5911 }
89b667f8
JB		 5912
5913 for_each_encoder_on_crtc(dev, crtc, encoder)
5914 if (encoder->pre_enable)
5915 encoder->pre_enable(encoder);
5916
2dd24552
JB		 5917 i9xx_pfit_enable(intel_crtc);
5918
63cbb074
VS		 5919 intel_crtc_load_lut(crtc);
5920
f37fcc2a 5921 intel_update_watermarks(crtc);
e1fdc473 5922 intel_enable_pipe(intel_crtc);
be6a6f8e 5923
4b3a9526
VS		 5924 assert_vblank_disabled(crtc);
5925 drm_crtc_vblank_on(crtc);
5926
f9b61ff6
DV		 5927 for_each_encoder_on_crtc(dev, crtc, encoder)
5928 encoder->enable(encoder);
89b667f8
JB		 5929}
5930
f13c2ef3
DV		 5931static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5932{
5933 struct drm_device *dev = crtc->base.dev;
5934 struct drm_i915_private *dev_priv = dev->dev_private;
5935
6e3c9717
ACO		 5936 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5937 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
f13c2ef3
DV		 5938}
5939
0b8765c6 5940static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 5941{
5942 struct drm_device *dev = crtc->dev;
a72e4c9f 5943 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945 5944 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 5945 struct intel_encoder *encoder;
79e53945 5946 int pipe = intel_crtc->pipe;
79e53945 5947
83d65738 5948 WARN_ON(!crtc->state->enable);
08a48469 5949
f7abfe8b
CW		 5950 if (intel_crtc->active)
5951 return;
5952
f13c2ef3
DV		 5953 i9xx_set_pll_dividers(intel_crtc);
5954
6e3c9717 5955 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 5956 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 5957
5958 intel_set_pipe_timings(intel_crtc);
5959
5b18e57c
DV		 5960 i9xx_set_pipeconf(intel_crtc);
5961
f7abfe8b 5962 intel_crtc->active = true;
6b383a7f 5963
4a3436e8 5964 if (!IS_GEN2(dev))
a72e4c9f 5965 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 5966
9d6d9f19
MK		 5967 for_each_encoder_on_crtc(dev, crtc, encoder)
5968 if (encoder->pre_enable)
5969 encoder->pre_enable(encoder);
5970
f6736a1a
DV		 5971 i9xx_enable_pll(intel_crtc);
5972
2dd24552
JB		 5973 i9xx_pfit_enable(intel_crtc);
5974
63cbb074
VS		 5975 intel_crtc_load_lut(crtc);
5976
f37fcc2a 5977 intel_update_watermarks(crtc);
e1fdc473 5978 intel_enable_pipe(intel_crtc);
be6a6f8e 5979
4b3a9526
VS		 5980 assert_vblank_disabled(crtc);
5981 drm_crtc_vblank_on(crtc);
5982
f9b61ff6
DV		 5983 for_each_encoder_on_crtc(dev, crtc, encoder)
5984 encoder->enable(encoder);
0b8765c6 5985}
79e53945 5986
87476d63
DV		 5987static void i9xx_pfit_disable(struct intel_crtc *crtc)
5988{
5989 struct drm_device *dev = crtc->base.dev;
5990 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 5991
6e3c9717 5992 if (!crtc->config->gmch_pfit.control)
328d8e82 5993 return;
87476d63 5994
328d8e82 5995 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 5996
328d8e82
DV		 5997 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5998 I915_READ(PFIT_CONTROL));
5999 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 6000}
6001
0b8765c6
JB		 6002static void i9xx_crtc_disable(struct drm_crtc *crtc)
6003{
6004 struct drm_device *dev = crtc->dev;
6005 struct drm_i915_private *dev_priv = dev->dev_private;
6006 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6007 struct intel_encoder *encoder;
0b8765c6 6008 int pipe = intel_crtc->pipe;
ef9c3aee 6009
f7abfe8b
CW		 6010 if (!intel_crtc->active)
6011 return;
6012
6304cd91
VS		 6013 /*
6014 * On gen2 planes are double buffered but the pipe isn't, so we must
6015 * wait for planes to fully turn off before disabling the pipe.
564ed191
ID		 6016 * We also need to wait on all gmch platforms because of the
6017 * self-refresh mode constraint explained above.
6304cd91 6018 */
564ed191 6019 intel_wait_for_vblank(dev, pipe);
6304cd91 6020
4b3a9526
VS		 6021 for_each_encoder_on_crtc(dev, crtc, encoder)
6022 encoder->disable(encoder);
6023
f9b61ff6
DV		 6024 drm_crtc_vblank_off(crtc);
6025 assert_vblank_disabled(crtc);
6026
575f7ab7 6027 intel_disable_pipe(intel_crtc);
24a1f16d 6028
87476d63 6029 i9xx_pfit_disable(intel_crtc);
24a1f16d 6030
89b667f8
JB		 6031 for_each_encoder_on_crtc(dev, crtc, encoder)
6032 if (encoder->post_disable)
6033 encoder->post_disable(encoder);
6034
409ee761 6035 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
076ed3b2
CML		 6036 if (IS_CHERRYVIEW(dev))
6037 chv_disable_pll(dev_priv, pipe);
6038 else if (IS_VALLEYVIEW(dev))
6039 vlv_disable_pll(dev_priv, pipe);
6040 else
1c4e0274 6041 i9xx_disable_pll(intel_crtc);
076ed3b2 6042 }
0b8765c6 6043
4a3436e8 6044 if (!IS_GEN2(dev))
a72e4c9f 6045 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4a3436e8 6046
f7abfe8b 6047 intel_crtc->active = false;
46ba614c 6048 intel_update_watermarks(crtc);
f37fcc2a 6049
efa9624e 6050 mutex_lock(&dev->struct_mutex);
7ff0ebcc 6051 intel_fbc_update(dev);
efa9624e 6052 mutex_unlock(&dev->struct_mutex);
0b8765c6
JB		 6053}
6054
ee7b9f93
JB		 6055static void i9xx_crtc_off(struct drm_crtc *crtc)
6056{
6057}
6058
b04c5bd6
BF		 6059/* Master function to enable/disable CRTC and corresponding power wells */
6060void intel_crtc_control(struct drm_crtc *crtc, bool enable)
976f8a20
DV		 6061{
6062 struct drm_device *dev = crtc->dev;
6063 struct drm_i915_private *dev_priv = dev->dev_private;
0e572fe7 6064 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
0e572fe7
DV		 6065 enum intel_display_power_domain domain;
6066 unsigned long domains;
976f8a20 6067
0e572fe7
DV		 6068 if (enable) {
6069 if (!intel_crtc->active) {
e1e9fb84
DV		 6070 domains = get_crtc_power_domains(crtc);
6071 for_each_power_domain(domain, domains)
6072 intel_display_power_get(dev_priv, domain);
6073 intel_crtc->enabled_power_domains = domains;
0e572fe7
DV		 6074
6075 dev_priv->display.crtc_enable(crtc);
ce22dba9 6076 intel_crtc_enable_planes(crtc);
0e572fe7
DV		 6077 }
6078 } else {
6079 if (intel_crtc->active) {
ce22dba9 6080 intel_crtc_disable_planes(crtc);
0e572fe7
DV		 6081 dev_priv->display.crtc_disable(crtc);
6082
e1e9fb84
DV		 6083 domains = intel_crtc->enabled_power_domains;
6084 for_each_power_domain(domain, domains)
6085 intel_display_power_put(dev_priv, domain);
6086 intel_crtc->enabled_power_domains = 0;
0e572fe7
DV		 6087 }
6088 }
b04c5bd6
BF		 6089}
6090
6091/**
6092 * Sets the power management mode of the pipe and plane.
6093 */
6094void intel_crtc_update_dpms(struct drm_crtc *crtc)
6095{
6096 struct drm_device *dev = crtc->dev;
6097 struct intel_encoder *intel_encoder;
6098 bool enable = false;
6099
6100 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
6101 enable |= intel_encoder->connectors_active;
6102
6103 intel_crtc_control(crtc, enable);
976f8a20
DV		 6104}
6105
cdd59983
CW		 6106static void intel_crtc_disable(struct drm_crtc *crtc)
6107{
cdd59983 6108 struct drm_device *dev = crtc->dev;
976f8a20 6109 struct drm_connector *connector;
ee7b9f93 6110 struct drm_i915_private *dev_priv = dev->dev_private;
cdd59983 6111
976f8a20 6112 /* crtc should still be enabled when we disable it. */
83d65738 6113 WARN_ON(!crtc->state->enable);
976f8a20 6114
ce22dba9 6115 intel_crtc_disable_planes(crtc);
976f8a20 6116 dev_priv->display.crtc_disable(crtc);
ee7b9f93
JB		 6117 dev_priv->display.off(crtc);
6118
70a101f8 6119 drm_plane_helper_disable(crtc->primary);
976f8a20
DV		 6120
6121 /* Update computed state. */
6122 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6123 if (!connector->encoder || !connector->encoder->crtc)
6124 continue;
6125
6126 if (connector->encoder->crtc != crtc)
6127 continue;
6128
6129 connector->dpms = DRM_MODE_DPMS_OFF;
6130 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 6131 }
6132}
6133
ea5b213a 6134void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 6135{
4ef69c7a 6136 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 6137
ea5b213a
CW		 6138 drm_encoder_cleanup(encoder);
6139 kfree(intel_encoder);
7e7d76c3
JB		 6140}
6141
9237329d 6142/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
DV		 6143 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6144 * state of the entire output pipe. */
9237329d 6145static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 6146{
5ab432ef
DV		 6147 if (mode == DRM_MODE_DPMS_ON) {
6148 encoder->connectors_active = true;
6149
b2cabb0e 6150 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 6151 } else {
6152 encoder->connectors_active = false;
6153
b2cabb0e 6154 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 6155 }
79e53945
JB		 6156}
6157
0a91ca29
DV		 6158/* Cross check the actual hw state with our own modeset state tracking (and it's
6159 * internal consistency). */
b980514c 6160static void intel_connector_check_state(struct intel_connector *connector)
79e53945 6161{
0a91ca29
DV		 6162 if (connector->get_hw_state(connector)) {
6163 struct intel_encoder *encoder = connector->encoder;
6164 struct drm_crtc *crtc;
6165 bool encoder_enabled;
6166 enum pipe pipe;
6167
6168 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6169 connector->base.base.id,
c23cc417 6170 connector->base.name);
0a91ca29 6171
0e32b39c
DA		 6172 /* there is no real hw state for MST connectors */
6173 if (connector->mst_port)
6174 return;
6175
e2c719b7 6176 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
0a91ca29 6177 "wrong connector dpms state\n");
e2c719b7 6178 I915_STATE_WARN(connector->base.encoder != &encoder->base,
0a91ca29 6179 "active connector not linked to encoder\n");
0a91ca29 6180
36cd7444 6181 if (encoder) {
e2c719b7 6182 I915_STATE_WARN(!encoder->connectors_active,
36cd7444
DA		 6183 "encoder->connectors_active not set\n");
6184
6185 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
e2c719b7
RC		 6186 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6187 if (I915_STATE_WARN_ON(!encoder->base.crtc))
36cd7444 6188 return;
0a91ca29 6189
36cd7444 6190 crtc = encoder->base.crtc;
0a91ca29 6191
83d65738
MR		 6192 I915_STATE_WARN(!crtc->state->enable,
6193 "crtc not enabled\n");
e2c719b7
RC		 6194 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6195 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
36cd7444
DA		 6196 "encoder active on the wrong pipe\n");
6197 }
0a91ca29 6198 }
79e53945
JB		 6199}
6200
08d9bc92
ACO		 6201int intel_connector_init(struct intel_connector *connector)
6202{
6203 struct drm_connector_state *connector_state;
6204
6205 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6206 if (!connector_state)
6207 return -ENOMEM;
6208
6209 connector->base.state = connector_state;
6210 return 0;
6211}
6212
6213struct intel_connector *intel_connector_alloc(void)
6214{
6215 struct intel_connector *connector;
6216
6217 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6218 if (!connector)
6219 return NULL;
6220
6221 if (intel_connector_init(connector) < 0) {
6222 kfree(connector);
6223 return NULL;
6224 }
6225
6226 return connector;
6227}
6228
5ab432ef
DV		 6229/* Even simpler default implementation, if there's really no special case to
6230 * consider. */
6231void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 6232{
5ab432ef
DV		 6233 /* All the simple cases only support two dpms states. */
6234 if (mode != DRM_MODE_DPMS_ON)
6235 mode = DRM_MODE_DPMS_OFF;
d4270e57 6236
5ab432ef
DV		 6237 if (mode == connector->dpms)
6238 return;
6239
6240 connector->dpms = mode;
6241
6242 /* Only need to change hw state when actually enabled */
c9976dcf
CW		 6243 if (connector->encoder)
6244 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
0a91ca29 6245
b980514c 6246 intel_modeset_check_state(connector->dev);
79e53945
JB		 6247}
6248
f0947c37
DV		 6249/* Simple connector->get_hw_state implementation for encoders that support only
6250 * one connector and no cloning and hence the encoder state determines the state
6251 * of the connector. */
6252bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 6253{
24929352 6254 enum pipe pipe = 0;
f0947c37 6255 struct intel_encoder *encoder = connector->encoder;
ea5b213a 6256
f0947c37 6257 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 6258}
6259
6d293983 6260static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
d272ddfa 6261{
6d293983
ACO		 6262 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6263 return crtc_state->fdi_lanes;
d272ddfa
VS		 6264
6265 return 0;
6266}
6267
6d293983 6268static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5cec258b 6269 struct intel_crtc_state *pipe_config)
1857e1da 6270{
6d293983
ACO		 6271 struct drm_atomic_state *state = pipe_config->base.state;
6272 struct intel_crtc *other_crtc;
6273 struct intel_crtc_state *other_crtc_state;
6274
1857e1da
DV		 6275 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6276 pipe_name(pipe), pipe_config->fdi_lanes);
6277 if (pipe_config->fdi_lanes > 4) {
6278 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6279 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6280 return -EINVAL;
1857e1da
DV		 6281 }
6282
bafb6553 6283 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1857e1da
DV		 6284 if (pipe_config->fdi_lanes > 2) {
6285 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6286 pipe_config->fdi_lanes);
6d293983 6287 return -EINVAL;
1857e1da 6288 } else {
6d293983 6289 return 0;
1857e1da
DV		 6290 }
6291 }
6292
6293 if (INTEL_INFO(dev)->num_pipes == 2)
6d293983 6294 return 0;
1857e1da
DV		 6295
6296 /* Ivybridge 3 pipe is really complicated */
6297 switch (pipe) {
6298 case PIPE_A:
6d293983 6299 return 0;
1857e1da 6300 case PIPE_B:
6d293983
ACO		 6301 if (pipe_config->fdi_lanes <= 2)
6302 return 0;
6303
6304 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6305 other_crtc_state =
6306 intel_atomic_get_crtc_state(state, other_crtc);
6307 if (IS_ERR(other_crtc_state))
6308 return PTR_ERR(other_crtc_state);
6309
6310 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
1857e1da
DV		 6311 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6312 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6313 return -EINVAL;
1857e1da 6314 }
6d293983 6315 return 0;
1857e1da 6316 case PIPE_C:
251cc67c
VS		 6317 if (pipe_config->fdi_lanes > 2) {
6318 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6319 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6320 return -EINVAL;
251cc67c 6321 }
6d293983
ACO		 6322
6323 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6324 other_crtc_state =
6325 intel_atomic_get_crtc_state(state, other_crtc);
6326 if (IS_ERR(other_crtc_state))
6327 return PTR_ERR(other_crtc_state);
6328
6329 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
1857e1da 6330 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6d293983 6331 return -EINVAL;
1857e1da 6332 }
6d293983 6333 return 0;
1857e1da
DV		 6334 default:
6335 BUG();
6336 }
6337}
6338
e29c22c0
DV		 6339#define RETRY 1
6340static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5cec258b 6341 struct intel_crtc_state *pipe_config)
877d48d5 6342{
1857e1da 6343 struct drm_device *dev = intel_crtc->base.dev;
2d112de7 6344 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6d293983
ACO		 6345 int lane, link_bw, fdi_dotclock, ret;
6346 bool needs_recompute = false;
877d48d5 6347
e29c22c0 6348retry:
877d48d5
DV		 6349 /* FDI is a binary signal running at ~2.7GHz, encoding
6350 * each output octet as 10 bits. The actual frequency
6351 * is stored as a divider into a 100MHz clock, and the
6352 * mode pixel clock is stored in units of 1KHz.
6353 * Hence the bw of each lane in terms of the mode signal
6354 * is:
6355 */
6356 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6357
241bfc38 6358 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 6359
2bd89a07 6360 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 6361 pipe_config->pipe_bpp);
6362
6363 pipe_config->fdi_lanes = lane;
6364
2bd89a07 6365 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 6366 link_bw, &pipe_config->fdi_m_n);
1857e1da 6367
6d293983
ACO		 6368 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6369 intel_crtc->pipe, pipe_config);
6370 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
e29c22c0
DV		 6371 pipe_config->pipe_bpp -= 2*3;
6372 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6373 pipe_config->pipe_bpp);
6374 needs_recompute = true;
6375 pipe_config->bw_constrained = true;
6376
6377 goto retry;
6378 }
6379
6380 if (needs_recompute)
6381 return RETRY;
6382
6d293983 6383 return ret;
877d48d5
DV		 6384}
6385
42db64ef 6386static void hsw_compute_ips_config(struct intel_crtc *crtc,
5cec258b 6387 struct intel_crtc_state *pipe_config)
42db64ef 6388{
d330a953 6389 pipe_config->ips_enabled = i915.enable_ips &&
3c4ca58c 6390 hsw_crtc_supports_ips(crtc) &&
b6dfdc9b 6391 pipe_config->pipe_bpp <= 24;
42db64ef
PZ		 6392}
6393
a43f6e0f 6394static int intel_crtc_compute_config(struct intel_crtc *crtc,
5cec258b 6395 struct intel_crtc_state *pipe_config)
79e53945 6396{
a43f6e0f 6397 struct drm_device *dev = crtc->base.dev;
8bd31e67 6398 struct drm_i915_private *dev_priv = dev->dev_private;
2d112de7 6399 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
d03c93d4 6400 int ret;
89749350 6401
ad3a4479 6402 /* FIXME should check pixel clock limits on all platforms */
cf532bb2 6403 if (INTEL_INFO(dev)->gen < 4) {
cf532bb2
VS		 6404 int clock_limit =
6405 dev_priv->display.get_display_clock_speed(dev);
6406
6407 /*
6408 * Enable pixel doubling when the dot clock
6409 * is > 90% of the (display) core speed.
6410 *
b397c96b
VS		 6411 * GDG double wide on either pipe,
6412 * otherwise pipe A only.
cf532bb2 6413 */
b397c96b 6414 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
241bfc38 6415 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
ad3a4479 6416 clock_limit *= 2;
cf532bb2 6417 pipe_config->double_wide = true;
ad3a4479
VS		 6418 }
6419
241bfc38 6420 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
e29c22c0 6421 return -EINVAL;
2c07245f 6422 }
89749350 6423
1d1d0e27
VS		 6424 /*
6425 * Pipe horizontal size must be even in:
6426 * - DVO ganged mode
6427 * - LVDS dual channel mode
6428 * - Double wide pipe
6429 */
a93e255f 6430 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
1d1d0e27
VS		 6431 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6432 pipe_config->pipe_src_w &= ~1;
6433
8693a824
DL		 6434 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6435 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 6436 */
6437 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6438 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 6439 return -EINVAL;
44f46b42 6440
f5adf94e 6441 if (HAS_IPS(dev))
a43f6e0f
DV		 6442 hsw_compute_ips_config(crtc, pipe_config);
6443
877d48d5 6444 if (pipe_config->has_pch_encoder)
a43f6e0f 6445 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 6446
d03c93d4
CK		 6447 /* FIXME: remove below call once atomic mode set is place and all crtc
6448 * related checks called from atomic_crtc_check function */
6449 ret = 0;
6450 DRM_DEBUG_KMS("intel_crtc = %p drm_state (pipe_config->base.state) = %p\n",
6451 crtc, pipe_config->base.state);
6452 ret = intel_atomic_setup_scalers(dev, crtc, pipe_config);
6453
6454 return ret;
79e53945
JB		 6455}
6456
1652d19e
VS		 6457static int skylake_get_display_clock_speed(struct drm_device *dev)
6458{
6459 struct drm_i915_private *dev_priv = to_i915(dev);
6460 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6461 uint32_t cdctl = I915_READ(CDCLK_CTL);
6462 uint32_t linkrate;
6463
6464 if (!(lcpll1 & LCPLL_PLL_ENABLE)) {
6465 WARN(1, "LCPLL1 not enabled\n");
6466 return 24000; /* 24MHz is the cd freq with NSSC ref */
6467 }
6468
6469 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6470 return 540000;
6471
6472 linkrate = (I915_READ(DPLL_CTRL1) &
71cd8423 6473 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
1652d19e 6474
71cd8423
DL		 6475 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6476 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
1652d19e
VS		 6477 /* vco 8640 */
6478 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6479 case CDCLK_FREQ_450_432:
6480 return 432000;
6481 case CDCLK_FREQ_337_308:
6482 return 308570;
6483 case CDCLK_FREQ_675_617:
6484 return 617140;
6485 default:
6486 WARN(1, "Unknown cd freq selection\n");
6487 }
6488 } else {
6489 /* vco 8100 */
6490 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6491 case CDCLK_FREQ_450_432:
6492 return 450000;
6493 case CDCLK_FREQ_337_308:
6494 return 337500;
6495 case CDCLK_FREQ_675_617:
6496 return 675000;
6497 default:
6498 WARN(1, "Unknown cd freq selection\n");
6499 }
6500 }
6501
6502 /* error case, do as if DPLL0 isn't enabled */
6503 return 24000;
6504}
6505
6506static int broadwell_get_display_clock_speed(struct drm_device *dev)
6507{
6508 struct drm_i915_private *dev_priv = dev->dev_private;
6509 uint32_t lcpll = I915_READ(LCPLL_CTL);
6510 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6511
6512 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6513 return 800000;
6514 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6515 return 450000;
6516 else if (freq == LCPLL_CLK_FREQ_450)
6517 return 450000;
6518 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6519 return 540000;
6520 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6521 return 337500;
6522 else
6523 return 675000;
6524}
6525
6526static int haswell_get_display_clock_speed(struct drm_device *dev)
6527{
6528 struct drm_i915_private *dev_priv = dev->dev_private;
6529 uint32_t lcpll = I915_READ(LCPLL_CTL);
6530 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6531
6532 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6533 return 800000;
6534 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6535 return 450000;
6536 else if (freq == LCPLL_CLK_FREQ_450)
6537 return 450000;
6538 else if (IS_HSW_ULT(dev))
6539 return 337500;
6540 else
6541 return 540000;
79e53945
JB		 6542}
6543
25eb05fc
JB		 6544static int valleyview_get_display_clock_speed(struct drm_device *dev)
6545{
d197b7d3 6546 struct drm_i915_private *dev_priv = dev->dev_private;
d197b7d3
VS		 6547 u32 val;
6548 int divider;
6549
6bcda4f0
VS		 6550 if (dev_priv->hpll_freq == 0)
6551 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6552
d197b7d3
VS		 6553 mutex_lock(&dev_priv->dpio_lock);
6554 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6555 mutex_unlock(&dev_priv->dpio_lock);
6556
6557 divider = val & DISPLAY_FREQUENCY_VALUES;
6558
7d007f40
VS		 6559 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6560 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6561 "cdclk change in progress\n");
6562
6bcda4f0 6563 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
25eb05fc
JB		 6564}
6565
b37a6434
VS		 6566static int ilk_get_display_clock_speed(struct drm_device *dev)
6567{
6568 return 450000;
6569}
6570
e70236a8
JB		 6571static int i945_get_display_clock_speed(struct drm_device *dev)
6572{
6573 return 400000;
6574}
79e53945 6575
e70236a8 6576static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 6577{
e907f170 6578 return 333333;
e70236a8 6579}
79e53945 6580
e70236a8
JB		 6581static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6582{
6583 return 200000;
6584}
79e53945 6585
257a7ffc
DV		 6586static int pnv_get_display_clock_speed(struct drm_device *dev)
6587{
6588 u16 gcfgc = 0;
6589
6590 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6591
6592 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6593 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
e907f170 6594 return 266667;
257a7ffc 6595 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
e907f170 6596 return 333333;
257a7ffc 6597 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
e907f170 6598 return 444444;
257a7ffc
DV		 6599 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6600 return 200000;
6601 default:
6602 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6603 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
e907f170 6604 return 133333;
257a7ffc 6605 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
e907f170 6606 return 166667;
257a7ffc
DV		 6607 }
6608}
6609
e70236a8
JB		 6610static int i915gm_get_display_clock_speed(struct drm_device *dev)
6611{
6612 u16 gcfgc = 0;
79e53945 6613
e70236a8
JB		 6614 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6615
6616 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
e907f170 6617 return 133333;
e70236a8
JB		 6618 else {
6619 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6620 case GC_DISPLAY_CLOCK_333_MHZ:
e907f170 6621 return 333333;
e70236a8
JB		 6622 default:
6623 case GC_DISPLAY_CLOCK_190_200_MHZ:
6624 return 190000;
79e53945 6625 }
e70236a8
JB		 6626 }
6627}
6628
6629static int i865_get_display_clock_speed(struct drm_device *dev)
6630{
e907f170 6631 return 266667;
e70236a8
JB		 6632}
6633
6634static int i855_get_display_clock_speed(struct drm_device *dev)
6635{
6636 u16 hpllcc = 0;
6637 /* Assume that the hardware is in the high speed state. This
6638 * should be the default.
6639 */
6640 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6641 case GC_CLOCK_133_200:
6642 case GC_CLOCK_100_200:
6643 return 200000;
6644 case GC_CLOCK_166_250:
6645 return 250000;
6646 case GC_CLOCK_100_133:
e907f170 6647 return 133333;
e70236a8 6648 }
79e53945 6649
e70236a8
JB		 6650 /* Shouldn't happen */
6651 return 0;
6652}
79e53945 6653
e70236a8
JB		 6654static int i830_get_display_clock_speed(struct drm_device *dev)
6655{
e907f170 6656 return 133333;
79e53945
JB		 6657}
6658
2c07245f 6659static void
a65851af 6660intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 6661{
a65851af
VS		 6662 while (*num > DATA_LINK_M_N_MASK ||
6663 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 6664 *num >>= 1;
6665 *den >>= 1;
6666 }
6667}
6668
a65851af
VS		 6669static void compute_m_n(unsigned int m, unsigned int n,
6670 uint32_t *ret_m, uint32_t *ret_n)
6671{
6672 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6673 *ret_m = div_u64((uint64_t) m * *ret_n, n);
6674 intel_reduce_m_n_ratio(ret_m, ret_n);
6675}
6676
e69d0bc1
DV		 6677void
6678intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6679 int pixel_clock, int link_clock,
6680 struct intel_link_m_n *m_n)
2c07245f 6681{
e69d0bc1 6682 m_n->tu = 64;
a65851af
VS		 6683
6684 compute_m_n(bits_per_pixel * pixel_clock,
6685 link_clock * nlanes * 8,
6686 &m_n->gmch_m, &m_n->gmch_n);
6687
6688 compute_m_n(pixel_clock, link_clock,
6689 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 6690}
6691
a7615030
CW		 6692static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6693{
d330a953
JN		 6694 if (i915.panel_use_ssc >= 0)
6695 return i915.panel_use_ssc != 0;
41aa3448 6696 return dev_priv->vbt.lvds_use_ssc
435793df 6697 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 6698}
6699
a93e255f
ACO		 6700static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
6701 int num_connectors)
c65d77d8 6702{
a93e255f 6703 struct drm_device *dev = crtc_state->base.crtc->dev;
c65d77d8
JB		 6704 struct drm_i915_private *dev_priv = dev->dev_private;
6705 int refclk;
6706
a93e255f
ACO		 6707 WARN_ON(!crtc_state->base.state);
6708
5ab7b0b7 6709 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
9a0ea498 6710 refclk = 100000;
a93e255f 6711 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
c65d77d8 6712 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b
VS		 6713 refclk = dev_priv->vbt.lvds_ssc_freq;
6714 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
c65d77d8
JB		 6715 } else if (!IS_GEN2(dev)) {
6716 refclk = 96000;
6717 } else {
6718 refclk = 48000;
6719 }
6720
6721 return refclk;
6722}
6723
7429e9d4 6724static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 6725{
7df00d7a 6726 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 6727}
f47709a9 6728
7429e9d4
DV		 6729static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6730{
6731 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 6732}
6733
f47709a9 6734static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
190f68c5 6735 struct intel_crtc_state *crtc_state,
a7516a05
JB		 6736 intel_clock_t *reduced_clock)
6737{
f47709a9 6738 struct drm_device *dev = crtc->base.dev;
a7516a05
JB		 6739 u32 fp, fp2 = 0;
6740
6741 if (IS_PINEVIEW(dev)) {
190f68c5 6742 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
a7516a05 6743 if (reduced_clock)
7429e9d4 6744 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 6745 } else {
190f68c5 6746 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
a7516a05 6747 if (reduced_clock)
7429e9d4 6748 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 6749 }
6750
190f68c5 6751 crtc_state->dpll_hw_state.fp0 = fp;
a7516a05 6752
f47709a9 6753 crtc->lowfreq_avail = false;
a93e255f 6754 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
ab585dea 6755 reduced_clock) {
190f68c5 6756 crtc_state->dpll_hw_state.fp1 = fp2;
f47709a9 6757 crtc->lowfreq_avail = true;
a7516a05 6758 } else {
190f68c5 6759 crtc_state->dpll_hw_state.fp1 = fp;
a7516a05
JB		 6760 }
6761}
6762
5e69f97f
CML		 6763static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6764 pipe)
89b667f8
JB		 6765{
6766 u32 reg_val;
6767
6768 /*
6769 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6770 * and set it to a reasonable value instead.
6771 */
ab3c759a 6772 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8
JB		 6773 reg_val &= 0xffffff00;
6774 reg_val |= 0x00000030;
ab3c759a 6775 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 6776
ab3c759a 6777 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 6778 reg_val &= 0x8cffffff;
6779 reg_val = 0x8c000000;
ab3c759a 6780 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8 6781
ab3c759a 6782 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8 6783 reg_val &= 0xffffff00;
ab3c759a 6784 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 6785
ab3c759a 6786 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 6787 reg_val &= 0x00ffffff;
6788 reg_val |= 0xb0000000;
ab3c759a 6789 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8
JB		 6790}
6791
b551842d
DV		 6792static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6793 struct intel_link_m_n *m_n)
6794{
6795 struct drm_device *dev = crtc->base.dev;
6796 struct drm_i915_private *dev_priv = dev->dev_private;
6797 int pipe = crtc->pipe;
6798
e3b95f1e
DV		 6799 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6800 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6801 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6802 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 6803}
6804
6805static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 6806 struct intel_link_m_n *m_n,
6807 struct intel_link_m_n *m2_n2)
b551842d
DV		 6808{
6809 struct drm_device *dev = crtc->base.dev;
6810 struct drm_i915_private *dev_priv = dev->dev_private;
6811 int pipe = crtc->pipe;
6e3c9717 6812 enum transcoder transcoder = crtc->config->cpu_transcoder;
b551842d
DV		 6813
6814 if (INTEL_INFO(dev)->gen >= 5) {
6815 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6816 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6817 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6818 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
f769cd24
VK		 6819 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6820 * for gen < 8) and if DRRS is supported (to make sure the
6821 * registers are not unnecessarily accessed).
6822 */
44395bfe 6823 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6e3c9717 6824 crtc->config->has_drrs) {
f769cd24
VK		 6825 I915_WRITE(PIPE_DATA_M2(transcoder),
6826 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6827 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6828 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6829 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6830 }
b551842d 6831 } else {
e3b95f1e
DV		 6832 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6833 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6834 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6835 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 6836 }
6837}
6838
fe3cd48d 6839void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
03afc4a2 6840{
fe3cd48d
R		 6841 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6842
6843 if (m_n == M1_N1) {
6844 dp_m_n = &crtc->config->dp_m_n;
6845 dp_m2_n2 = &crtc->config->dp_m2_n2;
6846 } else if (m_n == M2_N2) {
6847
6848 /*
6849 * M2_N2 registers are not supported. Hence m2_n2 divider value
6850 * needs to be programmed into M1_N1.
6851 */
6852 dp_m_n = &crtc->config->dp_m2_n2;
6853 } else {
6854 DRM_ERROR("Unsupported divider value\n");
6855 return;
6856 }
6857
6e3c9717
ACO		 6858 if (crtc->config->has_pch_encoder)
6859 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
03afc4a2 6860 else
fe3cd48d 6861 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
03afc4a2
DV		 6862}
6863
d288f65f 6864static void vlv_update_pll(struct intel_crtc *crtc,
5cec258b 6865 struct intel_crtc_state *pipe_config)
bdd4b6a6
DV		 6866{
6867 u32 dpll, dpll_md;
6868
6869 /*
6870 * Enable DPIO clock input. We should never disable the reference
6871 * clock for pipe B, since VGA hotplug / manual detection depends
6872 * on it.
6873 */
6874 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
6875 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
6876 /* We should never disable this, set it here for state tracking */
6877 if (crtc->pipe == PIPE_B)
6878 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6879 dpll |= DPLL_VCO_ENABLE;
d288f65f 6880 pipe_config->dpll_hw_state.dpll = dpll;
bdd4b6a6 6881
d288f65f 6882 dpll_md = (pipe_config->pixel_multiplier - 1)
bdd4b6a6 6883 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
d288f65f 6884 pipe_config->dpll_hw_state.dpll_md = dpll_md;
bdd4b6a6
DV		 6885}
6886
d288f65f 6887static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 6888 const struct intel_crtc_state *pipe_config)
a0c4da24 6889{
f47709a9 6890 struct drm_device *dev = crtc->base.dev;
a0c4da24 6891 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 6892 int pipe = crtc->pipe;
bdd4b6a6 6893 u32 mdiv;
a0c4da24 6894 u32 bestn, bestm1, bestm2, bestp1, bestp2;
bdd4b6a6 6895 u32 coreclk, reg_val;
a0c4da24 6896
09153000
DV		 6897 mutex_lock(&dev_priv->dpio_lock);
6898
d288f65f
VS		 6899 bestn = pipe_config->dpll.n;
6900 bestm1 = pipe_config->dpll.m1;
6901 bestm2 = pipe_config->dpll.m2;
6902 bestp1 = pipe_config->dpll.p1;
6903 bestp2 = pipe_config->dpll.p2;
a0c4da24 6904
89b667f8
JB		 6905 /* See eDP HDMI DPIO driver vbios notes doc */
6906
6907 /* PLL B needs special handling */
bdd4b6a6 6908 if (pipe == PIPE_B)
5e69f97f 6909 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 6910
6911 /* Set up Tx target for periodic Rcomp update */
ab3c759a 6912 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
89b667f8
JB		 6913
6914 /* Disable target IRef on PLL */
ab3c759a 6915 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
89b667f8 6916 reg_val &= 0x00ffffff;
ab3c759a 6917 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
89b667f8
JB		 6918
6919 /* Disable fast lock */
ab3c759a 6920 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
89b667f8
JB		 6921
6922 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 6923 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6924 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6925 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 6926 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 6927
6928 /*
6929 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6930 * but we don't support that).
6931 * Note: don't use the DAC post divider as it seems unstable.
6932 */
6933 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ab3c759a 6934 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 6935
a0c4da24 6936 mdiv |= DPIO_ENABLE_CALIBRATION;
ab3c759a 6937 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 6938
89b667f8 6939 /* Set HBR and RBR LPF coefficients */
d288f65f 6940 if (pipe_config->port_clock == 162000 ||
409ee761
ACO		 6941 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
6942 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
ab3c759a 6943 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
885b0120 6944 0x009f0003);
89b667f8 6945 else
ab3c759a 6946 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
89b667f8
JB		 6947 0x00d0000f);
6948
681a8504 6949 if (pipe_config->has_dp_encoder) {
89b667f8 6950 /* Use SSC source */
bdd4b6a6 6951 if (pipe == PIPE_A)
ab3c759a 6952 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6953 0x0df40000);
6954 else
ab3c759a 6955 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6956 0x0df70000);
6957 } else { /* HDMI or VGA */
6958 /* Use bend source */
bdd4b6a6 6959 if (pipe == PIPE_A)
ab3c759a 6960 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6961 0x0df70000);
6962 else
ab3c759a 6963 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6964 0x0df40000);
6965 }
a0c4da24 6966
ab3c759a 6967 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
89b667f8 6968 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
409ee761
ACO		 6969 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
6970 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
89b667f8 6971 coreclk |= 0x01000000;
ab3c759a 6972 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
a0c4da24 6973
ab3c759a 6974 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
09153000 6975 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 6976}
6977
d288f65f 6978static void chv_update_pll(struct intel_crtc *crtc,
5cec258b 6979 struct intel_crtc_state *pipe_config)
1ae0d137 6980{
d288f65f 6981 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
1ae0d137
VS		 6982 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
6983 DPLL_VCO_ENABLE;
6984 if (crtc->pipe != PIPE_A)
d288f65f 6985 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
1ae0d137 6986
d288f65f
VS		 6987 pipe_config->dpll_hw_state.dpll_md =
6988 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
1ae0d137
VS		 6989}
6990
d288f65f 6991static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 6992 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 6993{
6994 struct drm_device *dev = crtc->base.dev;
6995 struct drm_i915_private *dev_priv = dev->dev_private;
6996 int pipe = crtc->pipe;
6997 int dpll_reg = DPLL(crtc->pipe);
6998 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9cbe40c1 6999 u32 loopfilter, tribuf_calcntr;
9d556c99 7000 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
a945ce7e 7001 u32 dpio_val;
9cbe40c1 7002 int vco;
9d556c99 7003
d288f65f
VS		 7004 bestn = pipe_config->dpll.n;
7005 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7006 bestm1 = pipe_config->dpll.m1;
7007 bestm2 = pipe_config->dpll.m2 >> 22;
7008 bestp1 = pipe_config->dpll.p1;
7009 bestp2 = pipe_config->dpll.p2;
9cbe40c1 7010 vco = pipe_config->dpll.vco;
a945ce7e 7011 dpio_val = 0;
9cbe40c1 7012 loopfilter = 0;
9d556c99
CML		 7013
7014 /*
7015 * Enable Refclk and SSC
7016 */
a11b0703 7017 I915_WRITE(dpll_reg,
d288f65f 7018 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
a11b0703
VS		 7019
7020 mutex_lock(&dev_priv->dpio_lock);
9d556c99 7021
9d556c99
CML		 7022 /* p1 and p2 divider */
7023 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7024 5 << DPIO_CHV_S1_DIV_SHIFT |
7025 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7026 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7027 1 << DPIO_CHV_K_DIV_SHIFT);
7028
7029 /* Feedback post-divider - m2 */
7030 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7031
7032 /* Feedback refclk divider - n and m1 */
7033 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7034 DPIO_CHV_M1_DIV_BY_2 |
7035 1 << DPIO_CHV_N_DIV_SHIFT);
7036
7037 /* M2 fraction division */
a945ce7e
VP		 7038 if (bestm2_frac)
7039 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
9d556c99
CML		 7040
7041 /* M2 fraction division enable */
a945ce7e
VP		 7042 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7043 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7044 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7045 if (bestm2_frac)
7046 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7047 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
9d556c99 7048
de3a0fde
VP		 7049 /* Program digital lock detect threshold */
7050 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7051 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7052 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7053 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7054 if (!bestm2_frac)
7055 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7056 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7057
9d556c99 7058 /* Loop filter */
9cbe40c1
VP		 7059 if (vco == 5400000) {
7060 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7061 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7062 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7063 tribuf_calcntr = 0x9;
7064 } else if (vco <= 6200000) {
7065 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7066 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7067 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7068 tribuf_calcntr = 0x9;
7069 } else if (vco <= 6480000) {
7070 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7071 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7072 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7073 tribuf_calcntr = 0x8;
7074 } else {
7075 /* Not supported. Apply the same limits as in the max case */
7076 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7077 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7078 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7079 tribuf_calcntr = 0;
7080 }
9d556c99
CML		 7081 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7082
968040b2 7083 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
9cbe40c1
VP		 7084 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7085 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7086 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7087
9d556c99
CML		 7088 /* AFC Recal */
7089 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7090 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7091 DPIO_AFC_RECAL);
7092
7093 mutex_unlock(&dev_priv->dpio_lock);
7094}
7095
d288f65f
VS		 7096/**
7097 * vlv_force_pll_on - forcibly enable just the PLL
7098 * @dev_priv: i915 private structure
7099 * @pipe: pipe PLL to enable
7100 * @dpll: PLL configuration
7101 *
7102 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7103 * in cases where we need the PLL enabled even when @pipe is not going to
7104 * be enabled.
7105 */
7106void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7107 const struct dpll *dpll)
7108{
7109 struct intel_crtc *crtc =
7110 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5cec258b 7111 struct intel_crtc_state pipe_config = {
a93e255f 7112 .base.crtc = &crtc->base,
d288f65f
VS		 7113 .pixel_multiplier = 1,
7114 .dpll = *dpll,
7115 };
7116
7117 if (IS_CHERRYVIEW(dev)) {
7118 chv_update_pll(crtc, &pipe_config);
7119 chv_prepare_pll(crtc, &pipe_config);
7120 chv_enable_pll(crtc, &pipe_config);
7121 } else {
7122 vlv_update_pll(crtc, &pipe_config);
7123 vlv_prepare_pll(crtc, &pipe_config);
7124 vlv_enable_pll(crtc, &pipe_config);
7125 }
7126}
7127
7128/**
7129 * vlv_force_pll_off - forcibly disable just the PLL
7130 * @dev_priv: i915 private structure
7131 * @pipe: pipe PLL to disable
7132 *
7133 * Disable the PLL for @pipe. To be used in cases where we need
7134 * the PLL enabled even when @pipe is not going to be enabled.
7135 */
7136void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7137{
7138 if (IS_CHERRYVIEW(dev))
7139 chv_disable_pll(to_i915(dev), pipe);
7140 else
7141 vlv_disable_pll(to_i915(dev), pipe);
7142}
7143
f47709a9 7144static void i9xx_update_pll(struct intel_crtc *crtc,
190f68c5 7145 struct intel_crtc_state *crtc_state,
f47709a9 7146 intel_clock_t *reduced_clock,
eb1cbe48
DV		 7147 int num_connectors)
7148{
f47709a9 7149 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7150 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 7151 u32 dpll;
7152 bool is_sdvo;
190f68c5 7153 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7154
190f68c5 7155 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7156
a93e255f
ACO		 7157 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7158 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 7159
7160 dpll = DPLL_VGA_MODE_DIS;
7161
a93e255f 7162 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 7163 dpll |= DPLLB_MODE_LVDS;
7164 else
7165 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 7166
ef1b460d 7167 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
190f68c5 7168 dpll |= (crtc_state->pixel_multiplier - 1)
198a037f 7169 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 7170 }
198a037f
DV		 7171
7172 if (is_sdvo)
4a33e48d 7173 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 7174
190f68c5 7175 if (crtc_state->has_dp_encoder)
4a33e48d 7176 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 7177
7178 /* compute bitmask from p1 value */
7179 if (IS_PINEVIEW(dev))
7180 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7181 else {
7182 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7183 if (IS_G4X(dev) && reduced_clock)
7184 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7185 }
7186 switch (clock->p2) {
7187 case 5:
7188 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7189 break;
7190 case 7:
7191 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7192 break;
7193 case 10:
7194 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7195 break;
7196 case 14:
7197 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7198 break;
7199 }
7200 if (INTEL_INFO(dev)->gen >= 4)
7201 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7202
190f68c5 7203 if (crtc_state->sdvo_tv_clock)
eb1cbe48 7204 dpll |= PLL_REF_INPUT_TVCLKINBC;
a93e255f 7205 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7206 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7207 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7208 else
7209 dpll |= PLL_REF_INPUT_DREFCLK;
7210
7211 dpll |= DPLL_VCO_ENABLE;
190f68c5 7212 crtc_state->dpll_hw_state.dpll = dpll;
8bcc2795 7213
eb1cbe48 7214 if (INTEL_INFO(dev)->gen >= 4) {
190f68c5 7215 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
ef1b460d 7216 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
190f68c5 7217 crtc_state->dpll_hw_state.dpll_md = dpll_md;
eb1cbe48
DV		 7218 }
7219}
7220
f47709a9 7221static void i8xx_update_pll(struct intel_crtc *crtc,
190f68c5 7222 struct intel_crtc_state *crtc_state,
f47709a9 7223 intel_clock_t *reduced_clock,
eb1cbe48
DV		 7224 int num_connectors)
7225{
f47709a9 7226 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7227 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 7228 u32 dpll;
190f68c5 7229 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7230
190f68c5 7231 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7232
eb1cbe48
DV		 7233 dpll = DPLL_VGA_MODE_DIS;
7234
a93e255f 7235 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 7236 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7237 } else {
7238 if (clock->p1 == 2)
7239 dpll |= PLL_P1_DIVIDE_BY_TWO;
7240 else
7241 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7242 if (clock->p2 == 4)
7243 dpll |= PLL_P2_DIVIDE_BY_4;
7244 }
7245
a93e255f 7246 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
4a33e48d
DV		 7247 dpll |= DPLL_DVO_2X_MODE;
7248
a93e255f 7249 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7250 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7251 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7252 else
7253 dpll |= PLL_REF_INPUT_DREFCLK;
7254
7255 dpll |= DPLL_VCO_ENABLE;
190f68c5 7256 crtc_state->dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 7257}
7258
8a654f3b 7259static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 7260{
7261 struct drm_device *dev = intel_crtc->base.dev;
7262 struct drm_i915_private *dev_priv = dev->dev_private;
7263 enum pipe pipe = intel_crtc->pipe;
6e3c9717 7264 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8a654f3b 7265 struct drm_display_mode *adjusted_mode =
6e3c9717 7266 &intel_crtc->config->base.adjusted_mode;
1caea6e9
VS		 7267 uint32_t crtc_vtotal, crtc_vblank_end;
7268 int vsyncshift = 0;
4d8a62ea
DV		 7269
7270 /* We need to be careful not to changed the adjusted mode, for otherwise
7271 * the hw state checker will get angry at the mismatch. */
7272 crtc_vtotal = adjusted_mode->crtc_vtotal;
7273 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c 7274
609aeaca 7275 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
b0e77b9c 7276 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 7277 crtc_vtotal -= 1;
7278 crtc_vblank_end -= 1;
609aeaca 7279
409ee761 7280 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
609aeaca
VS		 7281 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7282 else
7283 vsyncshift = adjusted_mode->crtc_hsync_start -
7284 adjusted_mode->crtc_htotal / 2;
1caea6e9
VS		 7285 if (vsyncshift < 0)
7286 vsyncshift += adjusted_mode->crtc_htotal;
b0e77b9c
PZ		 7287 }
7288
7289 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 7290 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 7291
fe2b8f9d 7292 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 7293 (adjusted_mode->crtc_hdisplay - 1) |
7294 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 7295 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 7296 (adjusted_mode->crtc_hblank_start - 1) |
7297 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 7298 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 7299 (adjusted_mode->crtc_hsync_start - 1) |
7300 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7301
fe2b8f9d 7302 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 7303 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 7304 ((crtc_vtotal - 1) << 16));
fe2b8f9d 7305 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 7306 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 7307 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 7308 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 7309 (adjusted_mode->crtc_vsync_start - 1) |
7310 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7311
b5e508d4
PZ		 7312 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7313 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7314 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7315 * bits. */
7316 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7317 (pipe == PIPE_B || pipe == PIPE_C))
7318 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7319
b0e77b9c
PZ		 7320 /* pipesrc controls the size that is scaled from, which should
7321 * always be the user's requested size.
7322 */
7323 I915_WRITE(PIPESRC(pipe),
6e3c9717
ACO		 7324 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7325 (intel_crtc->config->pipe_src_h - 1));
b0e77b9c
PZ		 7326}
7327
1bd1bd80 7328static void intel_get_pipe_timings(struct intel_crtc *crtc,
5cec258b 7329 struct intel_crtc_state *pipe_config)
1bd1bd80
DV		 7330{
7331 struct drm_device *dev = crtc->base.dev;
7332 struct drm_i915_private *dev_priv = dev->dev_private;
7333 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7334 uint32_t tmp;
7335
7336 tmp = I915_READ(HTOTAL(cpu_transcoder));
2d112de7
ACO		 7337 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7338 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7339 tmp = I915_READ(HBLANK(cpu_transcoder));
2d112de7
ACO		 7340 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7341 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7342 tmp = I915_READ(HSYNC(cpu_transcoder));
2d112de7
ACO		 7343 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7344 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7345
7346 tmp = I915_READ(VTOTAL(cpu_transcoder));
2d112de7
ACO		 7347 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7348 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7349 tmp = I915_READ(VBLANK(cpu_transcoder));
2d112de7
ACO		 7350 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7351 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7352 tmp = I915_READ(VSYNC(cpu_transcoder));
2d112de7
ACO		 7353 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7354 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7355
7356 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
2d112de7
ACO		 7357 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7358 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7359 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
1bd1bd80
DV		 7360 }
7361
7362 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 7363 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7364 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7365
2d112de7
ACO		 7366 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7367 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 7368}
7369
f6a83288 7370void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5cec258b 7371 struct intel_crtc_state *pipe_config)
babea61d 7372{
2d112de7
ACO		 7373 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7374 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7375 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7376 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
babea61d 7377
2d112de7
ACO		 7378 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7379 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7380 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7381 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
babea61d 7382
2d112de7 7383 mode->flags = pipe_config->base.adjusted_mode.flags;
babea61d 7384
2d112de7
ACO		 7385 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7386 mode->flags |= pipe_config->base.adjusted_mode.flags;
babea61d
JB		 7387}
7388
84b046f3
DV		 7389static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7390{
7391 struct drm_device *dev = intel_crtc->base.dev;
7392 struct drm_i915_private *dev_priv = dev->dev_private;
7393 uint32_t pipeconf;
7394
9f11a9e4 7395 pipeconf = 0;
84b046f3 7396
b6b5d049
VS		 7397 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7398 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7399 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
67c72a12 7400
6e3c9717 7401 if (intel_crtc->config->double_wide)
cf532bb2 7402 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 7403
ff9ce46e
DV		 7404 /* only g4x and later have fancy bpc/dither controls */
7405 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e 7406 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6e3c9717 7407 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
ff9ce46e 7408 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 7409 PIPECONF_DITHER_TYPE_SP;
84b046f3 7410
6e3c9717 7411 switch (intel_crtc->config->pipe_bpp) {
ff9ce46e
DV		 7412 case 18:
7413 pipeconf |= PIPECONF_6BPC;
7414 break;
7415 case 24:
7416 pipeconf |= PIPECONF_8BPC;
7417 break;
7418 case 30:
7419 pipeconf |= PIPECONF_10BPC;
7420 break;
7421 default:
7422 /* Case prevented by intel_choose_pipe_bpp_dither. */
7423 BUG();
84b046f3
DV		 7424 }
7425 }
7426
7427 if (HAS_PIPE_CXSR(dev)) {
7428 if (intel_crtc->lowfreq_avail) {
7429 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7430 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7431 } else {
7432 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 7433 }
7434 }
7435
6e3c9717 7436 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
efc2cfff 7437 if (INTEL_INFO(dev)->gen < 4 ||
409ee761 7438 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
efc2cfff
VS		 7439 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7440 else
7441 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7442 } else
84b046f3
DV		 7443 pipeconf |= PIPECONF_PROGRESSIVE;
7444
6e3c9717 7445 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
9f11a9e4 7446 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 7447
84b046f3
DV		 7448 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7449 POSTING_READ(PIPECONF(intel_crtc->pipe));
7450}
7451
190f68c5
ACO		 7452static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7453 struct intel_crtc_state *crtc_state)
79e53945 7454{
c7653199 7455 struct drm_device *dev = crtc->base.dev;
79e53945 7456 struct drm_i915_private *dev_priv = dev->dev_private;
c751ce4f 7457 int refclk, num_connectors = 0;
652c393a 7458 intel_clock_t clock, reduced_clock;
a16af721 7459 bool ok, has_reduced_clock = false;
e9fd1c02 7460 bool is_lvds = false, is_dsi = false;
5eddb70b 7461 struct intel_encoder *encoder;
d4906093 7462 const intel_limit_t *limit;
55bb9992
ACO		 7463 struct drm_atomic_state *state = crtc_state->base.state;
7464 struct drm_connector_state *connector_state;
7465 int i;
79e53945 7466
55bb9992
ACO		 7467 for (i = 0; i < state->num_connector; i++) {
7468 if (!state->connectors[i])
d0737e1d
ACO		 7469 continue;
7470
55bb9992
ACO		 7471 connector_state = state->connector_states[i];
7472 if (connector_state->crtc != &crtc->base)
7473 continue;
7474
7475 encoder = to_intel_encoder(connector_state->best_encoder);
7476
5eddb70b 7477 switch (encoder->type) {
79e53945
JB		 7478 case INTEL_OUTPUT_LVDS:
7479 is_lvds = true;
7480 break;
e9fd1c02
JN		 7481 case INTEL_OUTPUT_DSI:
7482 is_dsi = true;
7483 break;
6847d71b
PZ		 7484 default:
7485 break;
79e53945 7486 }
43565a06 7487
c751ce4f 7488 num_connectors++;
79e53945
JB		 7489 }
7490
f2335330 7491 if (is_dsi)
5b18e57c 7492 return 0;
f2335330 7493
190f68c5 7494 if (!crtc_state->clock_set) {
a93e255f 7495 refclk = i9xx_get_refclk(crtc_state, num_connectors);
79e53945 7496
e9fd1c02
JN		 7497 /*
7498 * Returns a set of divisors for the desired target clock with
7499 * the given refclk, or FALSE. The returned values represent
7500 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7501 * 2) / p1 / p2.
7502 */
a93e255f
ACO		 7503 limit = intel_limit(crtc_state, refclk);
7504 ok = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 7505 crtc_state->port_clock,
e9fd1c02 7506 refclk, NULL, &clock);
f2335330 7507 if (!ok) {
e9fd1c02
JN		 7508 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7509 return -EINVAL;
7510 }
79e53945 7511
f2335330
JN		 7512 if (is_lvds && dev_priv->lvds_downclock_avail) {
7513 /*
7514 * Ensure we match the reduced clock's P to the target
7515 * clock. If the clocks don't match, we can't switch
7516 * the display clock by using the FP0/FP1. In such case
7517 * we will disable the LVDS downclock feature.
7518 */
7519 has_reduced_clock =
a93e255f 7520 dev_priv->display.find_dpll(limit, crtc_state,
f2335330
JN		 7521 dev_priv->lvds_downclock,
7522 refclk, &clock,
7523 &reduced_clock);
7524 }
7525 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 7526 crtc_state->dpll.n = clock.n;
7527 crtc_state->dpll.m1 = clock.m1;
7528 crtc_state->dpll.m2 = clock.m2;
7529 crtc_state->dpll.p1 = clock.p1;
7530 crtc_state->dpll.p2 = clock.p2;
f47709a9 7531 }
7026d4ac 7532
e9fd1c02 7533 if (IS_GEN2(dev)) {
190f68c5 7534 i8xx_update_pll(crtc, crtc_state,
2a8f64ca
VP		 7535 has_reduced_clock ? &reduced_clock : NULL,
7536 num_connectors);
9d556c99 7537 } else if (IS_CHERRYVIEW(dev)) {
190f68c5 7538 chv_update_pll(crtc, crtc_state);
e9fd1c02 7539 } else if (IS_VALLEYVIEW(dev)) {
190f68c5 7540 vlv_update_pll(crtc, crtc_state);
e9fd1c02 7541 } else {
190f68c5 7542 i9xx_update_pll(crtc, crtc_state,
eb1cbe48 7543 has_reduced_clock ? &reduced_clock : NULL,
eba905b2 7544 num_connectors);
e9fd1c02 7545 }
79e53945 7546
c8f7a0db 7547 return 0;
f564048e
EA		 7548}
7549
2fa2fe9a 7550static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5cec258b 7551 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 7552{
7553 struct drm_device *dev = crtc->base.dev;
7554 struct drm_i915_private *dev_priv = dev->dev_private;
7555 uint32_t tmp;
7556
dc9e7dec
VS		 7557 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7558 return;
7559
2fa2fe9a 7560 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 7561 if (!(tmp & PFIT_ENABLE))
7562 return;
2fa2fe9a 7563
06922821 7564 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 7565 if (INTEL_INFO(dev)->gen < 4) {
7566 if (crtc->pipe != PIPE_B)
7567 return;
2fa2fe9a
DV		 7568 } else {
7569 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7570 return;
7571 }
7572
06922821 7573 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 7574 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7575 if (INTEL_INFO(dev)->gen < 5)
7576 pipe_config->gmch_pfit.lvds_border_bits =
7577 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7578}
7579
acbec814 7580static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7581 struct intel_crtc_state *pipe_config)
acbec814
JB		 7582{
7583 struct drm_device *dev = crtc->base.dev;
7584 struct drm_i915_private *dev_priv = dev->dev_private;
7585 int pipe = pipe_config->cpu_transcoder;
7586 intel_clock_t clock;
7587 u32 mdiv;
662c6ecb 7588 int refclk = 100000;
acbec814 7589
f573de5a
SK		 7590 /* In case of MIPI DPLL will not even be used */
7591 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7592 return;
7593
acbec814 7594 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 7595 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
acbec814
JB		 7596 mutex_unlock(&dev_priv->dpio_lock);
7597
7598 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7599 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7600 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7601 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7602 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7603
f646628b 7604 vlv_clock(refclk, &clock);
acbec814 7605
f646628b
VS		 7606 /* clock.dot is the fast clock */
7607 pipe_config->port_clock = clock.dot / 5;
acbec814
JB		 7608}
7609
5724dbd1
DL		 7610static void
7611i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7612 struct intel_initial_plane_config *plane_config)
1ad292b5
JB		 7613{
7614 struct drm_device *dev = crtc->base.dev;
7615 struct drm_i915_private *dev_priv = dev->dev_private;
7616 u32 val, base, offset;
7617 int pipe = crtc->pipe, plane = crtc->plane;
7618 int fourcc, pixel_format;
6761dd31 7619 unsigned int aligned_height;
b113d5ee 7620 struct drm_framebuffer *fb;
1b842c89 7621 struct intel_framebuffer *intel_fb;
1ad292b5 7622
42a7b088
DL		 7623 val = I915_READ(DSPCNTR(plane));
7624 if (!(val & DISPLAY_PLANE_ENABLE))
7625 return;
7626
d9806c9f 7627 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 7628 if (!intel_fb) {
1ad292b5
JB		 7629 DRM_DEBUG_KMS("failed to alloc fb\n");
7630 return;
7631 }
7632
1b842c89
DL		 7633 fb = &intel_fb->base;
7634
18c5247e
DV		 7635 if (INTEL_INFO(dev)->gen >= 4) {
7636 if (val & DISPPLANE_TILED) {
49af449b 7637 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 7638 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7639 }
7640 }
1ad292b5
JB		 7641
7642 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 7643 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 7644 fb->pixel_format = fourcc;
7645 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
1ad292b5
JB		 7646
7647 if (INTEL_INFO(dev)->gen >= 4) {
49af449b 7648 if (plane_config->tiling)
1ad292b5
JB		 7649 offset = I915_READ(DSPTILEOFF(plane));
7650 else
7651 offset = I915_READ(DSPLINOFF(plane));
7652 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7653 } else {
7654 base = I915_READ(DSPADDR(plane));
7655 }
7656 plane_config->base = base;
7657
7658 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 7659 fb->width = ((val >> 16) & 0xfff) + 1;
7660 fb->height = ((val >> 0) & 0xfff) + 1;
1ad292b5
JB		 7661
7662 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 7663 fb->pitches[0] = val & 0xffffffc0;
1ad292b5 7664
b113d5ee 7665 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 7666 fb->pixel_format,
7667 fb->modifier[0]);
1ad292b5 7668
f37b5c2b 7669 plane_config->size = fb->pitches[0] * aligned_height;
1ad292b5 7670
2844a921
DL		 7671 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7672 pipe_name(pipe), plane, fb->width, fb->height,
7673 fb->bits_per_pixel, base, fb->pitches[0],
7674 plane_config->size);
1ad292b5 7675
2d14030b 7676 plane_config->fb = intel_fb;
1ad292b5
JB		 7677}
7678
70b23a98 7679static void chv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7680 struct intel_crtc_state *pipe_config)
70b23a98
VS		 7681{
7682 struct drm_device *dev = crtc->base.dev;
7683 struct drm_i915_private *dev_priv = dev->dev_private;
7684 int pipe = pipe_config->cpu_transcoder;
7685 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7686 intel_clock_t clock;
7687 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
7688 int refclk = 100000;
7689
7690 mutex_lock(&dev_priv->dpio_lock);
7691 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7692 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7693 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7694 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7695 mutex_unlock(&dev_priv->dpio_lock);
7696
7697 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7698 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
7699 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7700 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7701 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7702
7703 chv_clock(refclk, &clock);
7704
7705 /* clock.dot is the fast clock */
7706 pipe_config->port_clock = clock.dot / 5;
7707}
7708
0e8ffe1b 7709static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5cec258b 7710 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 7711{
7712 struct drm_device *dev = crtc->base.dev;
7713 struct drm_i915_private *dev_priv = dev->dev_private;
7714 uint32_t tmp;
7715
f458ebbc
DV		 7716 if (!intel_display_power_is_enabled(dev_priv,
7717 POWER_DOMAIN_PIPE(crtc->pipe)))
b5482bd0
ID		 7718 return false;
7719
e143a21c 7720 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 7721 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 7722
0e8ffe1b
DV		 7723 tmp = I915_READ(PIPECONF(crtc->pipe));
7724 if (!(tmp & PIPECONF_ENABLE))
7725 return false;
7726
42571aef
VS		 7727 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7728 switch (tmp & PIPECONF_BPC_MASK) {
7729 case PIPECONF_6BPC:
7730 pipe_config->pipe_bpp = 18;
7731 break;
7732 case PIPECONF_8BPC:
7733 pipe_config->pipe_bpp = 24;
7734 break;
7735 case PIPECONF_10BPC:
7736 pipe_config->pipe_bpp = 30;
7737 break;
7738 default:
7739 break;
7740 }
7741 }
7742
b5a9fa09
DV		 7743 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
7744 pipe_config->limited_color_range = true;
7745
282740f7
VS		 7746 if (INTEL_INFO(dev)->gen < 4)
7747 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7748
1bd1bd80
DV		 7749 intel_get_pipe_timings(crtc, pipe_config);
7750
2fa2fe9a
DV		 7751 i9xx_get_pfit_config(crtc, pipe_config);
7752
6c49f241
DV		 7753 if (INTEL_INFO(dev)->gen >= 4) {
7754 tmp = I915_READ(DPLL_MD(crtc->pipe));
7755 pipe_config->pixel_multiplier =
7756 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7757 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 7758 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 7759 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7760 tmp = I915_READ(DPLL(crtc->pipe));
7761 pipe_config->pixel_multiplier =
7762 ((tmp & SDVO_MULTIPLIER_MASK)
7763 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7764 } else {
7765 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7766 * port and will be fixed up in the encoder->get_config
7767 * function. */
7768 pipe_config->pixel_multiplier = 1;
7769 }
8bcc2795
DV		 7770 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7771 if (!IS_VALLEYVIEW(dev)) {
1c4e0274
VS		 7772 /*
7773 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7774 * on 830. Filter it out here so that we don't
7775 * report errors due to that.
7776 */
7777 if (IS_I830(dev))
7778 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7779
8bcc2795
DV		 7780 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7781 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 7782 } else {
7783 /* Mask out read-only status bits. */
7784 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7785 DPLL_PORTC_READY_MASK |
7786 DPLL_PORTB_READY_MASK);
8bcc2795 7787 }
6c49f241 7788
70b23a98
VS		 7789 if (IS_CHERRYVIEW(dev))
7790 chv_crtc_clock_get(crtc, pipe_config);
7791 else if (IS_VALLEYVIEW(dev))
acbec814
JB		 7792 vlv_crtc_clock_get(crtc, pipe_config);
7793 else
7794 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 7795
0e8ffe1b
DV		 7796 return true;
7797}
7798
dde86e2d 7799static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 7800{
7801 struct drm_i915_private *dev_priv = dev->dev_private;
13d83a67 7802 struct intel_encoder *encoder;
74cfd7ac 7803 u32 val, final;
13d83a67 7804 bool has_lvds = false;
199e5d79 7805 bool has_cpu_edp = false;
199e5d79 7806 bool has_panel = false;
99eb6a01
KP		 7807 bool has_ck505 = false;
7808 bool can_ssc = false;
13d83a67
JB		 7809
7810 /* We need to take the global config into account */
b2784e15 7811 for_each_intel_encoder(dev, encoder) {
199e5d79
KP		 7812 switch (encoder->type) {
7813 case INTEL_OUTPUT_LVDS:
7814 has_panel = true;
7815 has_lvds = true;
7816 break;
7817 case INTEL_OUTPUT_EDP:
7818 has_panel = true;
2de6905f 7819 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 7820 has_cpu_edp = true;
7821 break;
6847d71b
PZ		 7822 default:
7823 break;
13d83a67
JB		 7824 }
7825 }
7826
99eb6a01 7827 if (HAS_PCH_IBX(dev)) {
41aa3448 7828 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 7829 can_ssc = has_ck505;
7830 } else {
7831 has_ck505 = false;
7832 can_ssc = true;
7833 }
7834
2de6905f
ID		 7835 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
7836 has_panel, has_lvds, has_ck505);
13d83a67
JB		 7837
7838 /* Ironlake: try to setup display ref clock before DPLL
7839 * enabling. This is only under driver's control after
7840 * PCH B stepping, previous chipset stepping should be
7841 * ignoring this setting.
7842 */
74cfd7ac
CW		 7843 val = I915_READ(PCH_DREF_CONTROL);
7844
7845 /* As we must carefully and slowly disable/enable each source in turn,
7846 * compute the final state we want first and check if we need to
7847 * make any changes at all.
7848 */
7849 final = val;
7850 final &= ~DREF_NONSPREAD_SOURCE_MASK;
7851 if (has_ck505)
7852 final |= DREF_NONSPREAD_CK505_ENABLE;
7853 else
7854 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7855
7856 final &= ~DREF_SSC_SOURCE_MASK;
7857 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7858 final &= ~DREF_SSC1_ENABLE;
7859
7860 if (has_panel) {
7861 final |= DREF_SSC_SOURCE_ENABLE;
7862
7863 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7864 final |= DREF_SSC1_ENABLE;
7865
7866 if (has_cpu_edp) {
7867 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7868 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7869 else
7870 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7871 } else
7872 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7873 } else {
7874 final |= DREF_SSC_SOURCE_DISABLE;
7875 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7876 }
7877
7878 if (final == val)
7879 return;
7880
13d83a67 7881 /* Always enable nonspread source */
74cfd7ac 7882 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 7883
99eb6a01 7884 if (has_ck505)
74cfd7ac 7885 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 7886 else
74cfd7ac 7887 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 7888
199e5d79 7889 if (has_panel) {
74cfd7ac
CW		 7890 val &= ~DREF_SSC_SOURCE_MASK;
7891 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 7892
199e5d79 7893 /* SSC must be turned on before enabling the CPU output */
99eb6a01 7894 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 7895 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 7896 val |= DREF_SSC1_ENABLE;
e77166b5 7897 } else
74cfd7ac 7898 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 7899
7900 /* Get SSC going before enabling the outputs */
74cfd7ac 7901 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 7902 POSTING_READ(PCH_DREF_CONTROL);
7903 udelay(200);
7904
74cfd7ac 7905 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 7906
7907 /* Enable CPU source on CPU attached eDP */
199e5d79 7908 if (has_cpu_edp) {
99eb6a01 7909 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 7910 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 7911 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
eba905b2 7912 } else
74cfd7ac 7913 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 7914 } else
74cfd7ac 7915 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 7916
74cfd7ac 7917 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 7918 POSTING_READ(PCH_DREF_CONTROL);
7919 udelay(200);
7920 } else {
7921 DRM_DEBUG_KMS("Disabling SSC entirely\n");
7922
74cfd7ac 7923 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 7924
7925 /* Turn off CPU output */
74cfd7ac 7926 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 7927
74cfd7ac 7928 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 7929 POSTING_READ(PCH_DREF_CONTROL);
7930 udelay(200);
7931
7932 /* Turn off the SSC source */
74cfd7ac
CW		 7933 val &= ~DREF_SSC_SOURCE_MASK;
7934 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 7935
7936 /* Turn off SSC1 */
74cfd7ac 7937 val &= ~DREF_SSC1_ENABLE;
199e5d79 7938
74cfd7ac 7939 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 7940 POSTING_READ(PCH_DREF_CONTROL);
7941 udelay(200);
7942 }
74cfd7ac
CW		 7943
7944 BUG_ON(val != final);
13d83a67
JB		 7945}
7946
f31f2d55 7947static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 7948{
f31f2d55 7949 uint32_t tmp;
dde86e2d 7950
0ff066a9
PZ		 7951 tmp = I915_READ(SOUTH_CHICKEN2);
7952 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7953 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 7954
0ff066a9
PZ		 7955 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
7956 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7957 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 7958
0ff066a9
PZ		 7959 tmp = I915_READ(SOUTH_CHICKEN2);
7960 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7961 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 7962
0ff066a9
PZ		 7963 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
7964 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7965 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 7966}
7967
7968/* WaMPhyProgramming:hsw */
7969static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7970{
7971 uint32_t tmp;
dde86e2d
PZ		 7972
7973 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7974 tmp &= ~(0xFF << 24);
7975 tmp |= (0x12 << 24);
7976 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7977
dde86e2d
PZ		 7978 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7979 tmp |= (1 << 11);
7980 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7981
7982 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7983 tmp |= (1 << 11);
7984 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7985
dde86e2d
PZ		 7986 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7987 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7988 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7989
7990 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7991 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7992 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7993
0ff066a9
PZ		 7994 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7995 tmp &= ~(7 << 13);
7996 tmp |= (5 << 13);
7997 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 7998
0ff066a9
PZ		 7999 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8000 tmp &= ~(7 << 13);
8001 tmp |= (5 << 13);
8002 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 8003
8004 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8005 tmp &= ~0xFF;
8006 tmp |= 0x1C;
8007 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8008
8009 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8010 tmp &= ~0xFF;
8011 tmp |= 0x1C;
8012 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8013
8014 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8015 tmp &= ~(0xFF << 16);
8016 tmp |= (0x1C << 16);
8017 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8018
8019 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8020 tmp &= ~(0xFF << 16);
8021 tmp |= (0x1C << 16);
8022 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8023
0ff066a9
PZ		 8024 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8025 tmp |= (1 << 27);
8026 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 8027
0ff066a9
PZ		 8028 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8029 tmp |= (1 << 27);
8030 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 8031
0ff066a9
PZ		 8032 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8033 tmp &= ~(0xF << 28);
8034 tmp |= (4 << 28);
8035 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 8036
0ff066a9
PZ		 8037 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8038 tmp &= ~(0xF << 28);
8039 tmp |= (4 << 28);
8040 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 8041}
8042
2fa86a1f
PZ		 8043/* Implements 3 different sequences from BSpec chapter "Display iCLK
8044 * Programming" based on the parameters passed:
8045 * - Sequence to enable CLKOUT_DP
8046 * - Sequence to enable CLKOUT_DP without spread
8047 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8048 */
8049static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8050 bool with_fdi)
f31f2d55
PZ		 8051{
8052 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 8053 uint32_t reg, tmp;
8054
8055 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8056 with_spread = true;
8057 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8058 with_fdi, "LP PCH doesn't have FDI\n"))
8059 with_fdi = false;
f31f2d55
PZ		 8060
8061 mutex_lock(&dev_priv->dpio_lock);
8062
8063 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8064 tmp &= ~SBI_SSCCTL_DISABLE;
8065 tmp |= SBI_SSCCTL_PATHALT;
8066 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8067
8068 udelay(24);
8069
2fa86a1f
PZ		 8070 if (with_spread) {
8071 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8072 tmp &= ~SBI_SSCCTL_PATHALT;
8073 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 8074
2fa86a1f
PZ		 8075 if (with_fdi) {
8076 lpt_reset_fdi_mphy(dev_priv);
8077 lpt_program_fdi_mphy(dev_priv);
8078 }
8079 }
dde86e2d 8080
2fa86a1f
PZ		 8081 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8082 SBI_GEN0 : SBI_DBUFF0;
8083 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8084 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8085 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246
DV		 8086
8087 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 8088}
8089
47701c3b
PZ		 8090/* Sequence to disable CLKOUT_DP */
8091static void lpt_disable_clkout_dp(struct drm_device *dev)
8092{
8093 struct drm_i915_private *dev_priv = dev->dev_private;
8094 uint32_t reg, tmp;
8095
8096 mutex_lock(&dev_priv->dpio_lock);
8097
8098 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8099 SBI_GEN0 : SBI_DBUFF0;
8100 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8101 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8102 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8103
8104 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8105 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8106 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8107 tmp |= SBI_SSCCTL_PATHALT;
8108 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8109 udelay(32);
8110 }
8111 tmp |= SBI_SSCCTL_DISABLE;
8112 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8113 }
8114
8115 mutex_unlock(&dev_priv->dpio_lock);
8116}
8117
bf8fa3d3
PZ		 8118static void lpt_init_pch_refclk(struct drm_device *dev)
8119{
bf8fa3d3
PZ		 8120 struct intel_encoder *encoder;
8121 bool has_vga = false;
8122
b2784e15 8123 for_each_intel_encoder(dev, encoder) {
bf8fa3d3
PZ		 8124 switch (encoder->type) {
8125 case INTEL_OUTPUT_ANALOG:
8126 has_vga = true;
8127 break;
6847d71b
PZ		 8128 default:
8129 break;
bf8fa3d3
PZ		 8130 }
8131 }
8132
47701c3b
PZ		 8133 if (has_vga)
8134 lpt_enable_clkout_dp(dev, true, true);
8135 else
8136 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 8137}
8138
dde86e2d
PZ		 8139/*
8140 * Initialize reference clocks when the driver loads
8141 */
8142void intel_init_pch_refclk(struct drm_device *dev)
8143{
8144 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8145 ironlake_init_pch_refclk(dev);
8146 else if (HAS_PCH_LPT(dev))
8147 lpt_init_pch_refclk(dev);
8148}
8149
55bb9992 8150static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
d9d444cb 8151{
55bb9992 8152 struct drm_device *dev = crtc_state->base.crtc->dev;
d9d444cb 8153 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992
ACO		 8154 struct drm_atomic_state *state = crtc_state->base.state;
8155 struct drm_connector_state *connector_state;
d9d444cb 8156 struct intel_encoder *encoder;
55bb9992 8157 int num_connectors = 0, i;
d9d444cb
JB		 8158 bool is_lvds = false;
8159
55bb9992
ACO		 8160 for (i = 0; i < state->num_connector; i++) {
8161 if (!state->connectors[i])
d0737e1d
ACO		 8162 continue;
8163
55bb9992
ACO		 8164 connector_state = state->connector_states[i];
8165 if (connector_state->crtc != crtc_state->base.crtc)
8166 continue;
8167
8168 encoder = to_intel_encoder(connector_state->best_encoder);
8169
d9d444cb
JB		 8170 switch (encoder->type) {
8171 case INTEL_OUTPUT_LVDS:
8172 is_lvds = true;
8173 break;
6847d71b
PZ		 8174 default:
8175 break;
d9d444cb
JB		 8176 }
8177 num_connectors++;
8178 }
8179
8180 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b 8181 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
41aa3448 8182 dev_priv->vbt.lvds_ssc_freq);
e91e941b 8183 return dev_priv->vbt.lvds_ssc_freq;
d9d444cb
JB		 8184 }
8185
8186 return 120000;
8187}
8188
6ff93609 8189static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 8190{
c8203565 8191 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 8192 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8193 int pipe = intel_crtc->pipe;
c8203565
PZ		 8194 uint32_t val;
8195
78114071 8196 val = 0;
c8203565 8197
6e3c9717 8198 switch (intel_crtc->config->pipe_bpp) {
c8203565 8199 case 18:
dfd07d72 8200 val |= PIPECONF_6BPC;
c8203565
PZ		 8201 break;
8202 case 24:
dfd07d72 8203 val |= PIPECONF_8BPC;
c8203565
PZ		 8204 break;
8205 case 30:
dfd07d72 8206 val |= PIPECONF_10BPC;
c8203565
PZ		 8207 break;
8208 case 36:
dfd07d72 8209 val |= PIPECONF_12BPC;
c8203565
PZ		 8210 break;
8211 default:
cc769b62
PZ		 8212 /* Case prevented by intel_choose_pipe_bpp_dither. */
8213 BUG();
c8203565
PZ		 8214 }
8215
6e3c9717 8216 if (intel_crtc->config->dither)
c8203565
PZ		 8217 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8218
6e3c9717 8219 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 8220 val |= PIPECONF_INTERLACED_ILK;
8221 else
8222 val |= PIPECONF_PROGRESSIVE;
8223
6e3c9717 8224 if (intel_crtc->config->limited_color_range)
3685a8f3 8225 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 8226
c8203565
PZ		 8227 I915_WRITE(PIPECONF(pipe), val);
8228 POSTING_READ(PIPECONF(pipe));
8229}
8230
86d3efce
VS		 8231/*
8232 * Set up the pipe CSC unit.
8233 *
8234 * Currently only full range RGB to limited range RGB conversion
8235 * is supported, but eventually this should handle various
8236 * RGB<->YCbCr scenarios as well.
8237 */
50f3b016 8238static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 8239{
8240 struct drm_device *dev = crtc->dev;
8241 struct drm_i915_private *dev_priv = dev->dev_private;
8242 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8243 int pipe = intel_crtc->pipe;
8244 uint16_t coeff = 0x7800; /* 1.0 */
8245
8246 /*
8247 * TODO: Check what kind of values actually come out of the pipe
8248 * with these coeff/postoff values and adjust to get the best
8249 * accuracy. Perhaps we even need to take the bpc value into
8250 * consideration.
8251 */
8252
6e3c9717 8253 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8254 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8255
8256 /*
8257 * GY/GU and RY/RU should be the other way around according
8258 * to BSpec, but reality doesn't agree. Just set them up in
8259 * a way that results in the correct picture.
8260 */
8261 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8262 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8263
8264 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8265 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8266
8267 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8268 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8269
8270 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8271 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8272 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8273
8274 if (INTEL_INFO(dev)->gen > 6) {
8275 uint16_t postoff = 0;
8276
6e3c9717 8277 if (intel_crtc->config->limited_color_range)
32cf0cb0 8278 postoff = (16 * (1 << 12) / 255) & 0x1fff;
86d3efce
VS		 8279
8280 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8281 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8282 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8283
8284 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8285 } else {
8286 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8287
6e3c9717 8288 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8289 mode |= CSC_BLACK_SCREEN_OFFSET;
8290
8291 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8292 }
8293}
8294
6ff93609 8295static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38 8296{
756f85cf
PZ		 8297 struct drm_device *dev = crtc->dev;
8298 struct drm_i915_private *dev_priv = dev->dev_private;
ee2b0b38 8299 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
756f85cf 8300 enum pipe pipe = intel_crtc->pipe;
6e3c9717 8301 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee2b0b38
PZ		 8302 uint32_t val;
8303
3eff4faa 8304 val = 0;
ee2b0b38 8305
6e3c9717 8306 if (IS_HASWELL(dev) && intel_crtc->config->dither)
ee2b0b38
PZ		 8307 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8308
6e3c9717 8309 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 8310 val |= PIPECONF_INTERLACED_ILK;
8311 else
8312 val |= PIPECONF_PROGRESSIVE;
8313
702e7a56
PZ		 8314 I915_WRITE(PIPECONF(cpu_transcoder), val);
8315 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 8316
8317 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8318 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
756f85cf 8319
3cdf122c 8320 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
756f85cf
PZ		 8321 val = 0;
8322
6e3c9717 8323 switch (intel_crtc->config->pipe_bpp) {
756f85cf
PZ		 8324 case 18:
8325 val |= PIPEMISC_DITHER_6_BPC;
8326 break;
8327 case 24:
8328 val |= PIPEMISC_DITHER_8_BPC;
8329 break;
8330 case 30:
8331 val |= PIPEMISC_DITHER_10_BPC;
8332 break;
8333 case 36:
8334 val |= PIPEMISC_DITHER_12_BPC;
8335 break;
8336 default:
8337 /* Case prevented by pipe_config_set_bpp. */
8338 BUG();
8339 }
8340
6e3c9717 8341 if (intel_crtc->config->dither)
756f85cf
PZ		 8342 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8343
8344 I915_WRITE(PIPEMISC(pipe), val);
8345 }
ee2b0b38
PZ		 8346}
8347
6591c6e4 8348static bool ironlake_compute_clocks(struct drm_crtc *crtc,
190f68c5 8349 struct intel_crtc_state *crtc_state,
6591c6e4
PZ		 8350 intel_clock_t *clock,
8351 bool *has_reduced_clock,
8352 intel_clock_t *reduced_clock)
8353{
8354 struct drm_device *dev = crtc->dev;
8355 struct drm_i915_private *dev_priv = dev->dev_private;
6591c6e4 8356 int refclk;
d4906093 8357 const intel_limit_t *limit;
a16af721 8358 bool ret, is_lvds = false;
79e53945 8359
a93e255f 8360 is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
79e53945 8361
55bb9992 8362 refclk = ironlake_get_refclk(crtc_state);
79e53945 8363
d4906093
ML		 8364 /*
8365 * Returns a set of divisors for the desired target clock with the given
8366 * refclk, or FALSE. The returned values represent the clock equation:
8367 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8368 */
a93e255f
ACO		 8369 limit = intel_limit(crtc_state, refclk);
8370 ret = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 8371 crtc_state->port_clock,
ee9300bb 8372 refclk, NULL, clock);
6591c6e4
PZ		 8373 if (!ret)
8374 return false;
cda4b7d3 8375
ddc9003c 8376 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 8377 /*
8378 * Ensure we match the reduced clock's P to the target clock.
8379 * If the clocks don't match, we can't switch the display clock
8380 * by using the FP0/FP1. In such case we will disable the LVDS
8381 * downclock feature.
8382 */
ee9300bb 8383 *has_reduced_clock =
a93e255f 8384 dev_priv->display.find_dpll(limit, crtc_state,
ee9300bb
DV		 8385 dev_priv->lvds_downclock,
8386 refclk, clock,
8387 reduced_clock);
652c393a 8388 }
61e9653f 8389
6591c6e4
PZ		 8390 return true;
8391}
8392
d4b1931c
PZ		 8393int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8394{
8395 /*
8396 * Account for spread spectrum to avoid
8397 * oversubscribing the link. Max center spread
8398 * is 2.5%; use 5% for safety's sake.
8399 */
8400 u32 bps = target_clock * bpp * 21 / 20;
619d4d04 8401 return DIV_ROUND_UP(bps, link_bw * 8);
d4b1931c
PZ		 8402}
8403
7429e9d4 8404static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 8405{
7429e9d4 8406 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 8407}
8408
de13a2e3 8409static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
190f68c5 8410 struct intel_crtc_state *crtc_state,
7429e9d4 8411 u32 *fp,
9a7c7890 8412 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 8413{
de13a2e3 8414 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 8415 struct drm_device *dev = crtc->dev;
8416 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992
ACO		 8417 struct drm_atomic_state *state = crtc_state->base.state;
8418 struct drm_connector_state *connector_state;
8419 struct intel_encoder *encoder;
de13a2e3 8420 uint32_t dpll;
55bb9992 8421 int factor, num_connectors = 0, i;
09ede541 8422 bool is_lvds = false, is_sdvo = false;
79e53945 8423
55bb9992
ACO		 8424 for (i = 0; i < state->num_connector; i++) {
8425 if (!state->connectors[i])
d0737e1d
ACO		 8426 continue;
8427
55bb9992
ACO		 8428 connector_state = state->connector_states[i];
8429 if (connector_state->crtc != crtc_state->base.crtc)
8430 continue;
8431
8432 encoder = to_intel_encoder(connector_state->best_encoder);
8433
8434 switch (encoder->type) {
79e53945
JB		 8435 case INTEL_OUTPUT_LVDS:
8436 is_lvds = true;
8437 break;
8438 case INTEL_OUTPUT_SDVO:
7d57382e 8439 case INTEL_OUTPUT_HDMI:
79e53945 8440 is_sdvo = true;
79e53945 8441 break;
6847d71b
PZ		 8442 default:
8443 break;
79e53945 8444 }
43565a06 8445
c751ce4f 8446 num_connectors++;
79e53945 8447 }
79e53945 8448
c1858123 8449 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 8450 factor = 21;
8451 if (is_lvds) {
8452 if ((intel_panel_use_ssc(dev_priv) &&
e91e941b 8453 dev_priv->vbt.lvds_ssc_freq == 100000) ||
f0b44056 8454 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 8455 factor = 25;
190f68c5 8456 } else if (crtc_state->sdvo_tv_clock)
8febb297 8457 factor = 20;
c1858123 8458
190f68c5 8459 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7d0ac5b7 8460 *fp |= FP_CB_TUNE;
2c07245f 8461
9a7c7890
DV		 8462 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8463 *fp2 |= FP_CB_TUNE;
8464
5eddb70b 8465 dpll = 0;
2c07245f 8466
a07d6787
EA		 8467 if (is_lvds)
8468 dpll |= DPLLB_MODE_LVDS;
8469 else
8470 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 8471
190f68c5 8472 dpll |= (crtc_state->pixel_multiplier - 1)
ef1b460d 8473 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 8474
8475 if (is_sdvo)
4a33e48d 8476 dpll |= DPLL_SDVO_HIGH_SPEED;
190f68c5 8477 if (crtc_state->has_dp_encoder)
4a33e48d 8478 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 8479
a07d6787 8480 /* compute bitmask from p1 value */
190f68c5 8481 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 8482 /* also FPA1 */
190f68c5 8483 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 8484
190f68c5 8485 switch (crtc_state->dpll.p2) {
a07d6787
EA		 8486 case 5:
8487 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8488 break;
8489 case 7:
8490 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8491 break;
8492 case 10:
8493 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8494 break;
8495 case 14:
8496 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8497 break;
79e53945
JB		 8498 }
8499
b4c09f3b 8500 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 8501 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 8502 else
8503 dpll |= PLL_REF_INPUT_DREFCLK;
8504
959e16d6 8505 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 8506}
8507
190f68c5
ACO		 8508static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8509 struct intel_crtc_state *crtc_state)
de13a2e3 8510{
c7653199 8511 struct drm_device *dev = crtc->base.dev;
de13a2e3 8512 intel_clock_t clock, reduced_clock;
cbbab5bd 8513 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 8514 bool ok, has_reduced_clock = false;
8b47047b 8515 bool is_lvds = false;
e2b78267 8516 struct intel_shared_dpll *pll;
de13a2e3 8517
409ee761 8518 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
79e53945 8519
5dc5298b
PZ		 8520 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8521 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 8522
190f68c5 8523 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
de13a2e3 8524 &has_reduced_clock, &reduced_clock);
190f68c5 8525 if (!ok && !crtc_state->clock_set) {
de13a2e3
PZ		 8526 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8527 return -EINVAL;
79e53945 8528 }
f47709a9 8529 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 8530 if (!crtc_state->clock_set) {
8531 crtc_state->dpll.n = clock.n;
8532 crtc_state->dpll.m1 = clock.m1;
8533 crtc_state->dpll.m2 = clock.m2;
8534 crtc_state->dpll.p1 = clock.p1;
8535 crtc_state->dpll.p2 = clock.p2;
f47709a9 8536 }
79e53945 8537
5dc5298b 8538 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
190f68c5
ACO		 8539 if (crtc_state->has_pch_encoder) {
8540 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
cbbab5bd 8541 if (has_reduced_clock)
7429e9d4 8542 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 8543
190f68c5 8544 dpll = ironlake_compute_dpll(crtc, crtc_state,
cbbab5bd
DV		 8545 &fp, &reduced_clock,
8546 has_reduced_clock ? &fp2 : NULL);
8547
190f68c5
ACO		 8548 crtc_state->dpll_hw_state.dpll = dpll;
8549 crtc_state->dpll_hw_state.fp0 = fp;
66e985c0 8550 if (has_reduced_clock)
190f68c5 8551 crtc_state->dpll_hw_state.fp1 = fp2;
66e985c0 8552 else
190f68c5 8553 crtc_state->dpll_hw_state.fp1 = fp;
66e985c0 8554
190f68c5 8555 pll = intel_get_shared_dpll(crtc, crtc_state);
ee7b9f93 8556 if (pll == NULL) {
84f44ce7 8557 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
c7653199 8558 pipe_name(crtc->pipe));
4b645f14
JB		 8559 return -EINVAL;
8560 }
3fb37703 8561 }
79e53945 8562
ab585dea 8563 if (is_lvds && has_reduced_clock)
c7653199 8564 crtc->lowfreq_avail = true;
bcd644e0 8565 else
c7653199 8566 crtc->lowfreq_avail = false;
e2b78267 8567
c8f7a0db 8568 return 0;
79e53945
JB		 8569}
8570
eb14cb74
VS		 8571static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8572 struct intel_link_m_n *m_n)
8573{
8574 struct drm_device *dev = crtc->base.dev;
8575 struct drm_i915_private *dev_priv = dev->dev_private;
8576 enum pipe pipe = crtc->pipe;
8577
8578 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8579 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8580 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8581 & ~TU_SIZE_MASK;
8582 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8583 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8584 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8585}
8586
8587static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8588 enum transcoder transcoder,
b95af8be
VK		 8589 struct intel_link_m_n *m_n,
8590 struct intel_link_m_n *m2_n2)
72419203
DV		 8591{
8592 struct drm_device *dev = crtc->base.dev;
8593 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 8594 enum pipe pipe = crtc->pipe;
72419203 8595
eb14cb74
VS		 8596 if (INTEL_INFO(dev)->gen >= 5) {
8597 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8598 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8599 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8600 & ~TU_SIZE_MASK;
8601 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8602 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8603 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
b95af8be
VK		 8604 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8605 * gen < 8) and if DRRS is supported (to make sure the
8606 * registers are not unnecessarily read).
8607 */
8608 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
6e3c9717 8609 crtc->config->has_drrs) {
b95af8be
VK		 8610 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8611 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8612 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8613 & ~TU_SIZE_MASK;
8614 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8615 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8616 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8617 }
eb14cb74
VS		 8618 } else {
8619 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8620 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8621 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8622 & ~TU_SIZE_MASK;
8623 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8624 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8625 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8626 }
8627}
8628
8629void intel_dp_get_m_n(struct intel_crtc *crtc,
5cec258b 8630 struct intel_crtc_state *pipe_config)
eb14cb74 8631{
681a8504 8632 if (pipe_config->has_pch_encoder)
eb14cb74
VS		 8633 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8634 else
8635 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be
VK		 8636 &pipe_config->dp_m_n,
8637 &pipe_config->dp_m2_n2);
eb14cb74 8638}
72419203 8639
eb14cb74 8640static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5cec258b 8641 struct intel_crtc_state *pipe_config)
eb14cb74
VS		 8642{
8643 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be 8644 &pipe_config->fdi_m_n, NULL);
72419203
DV		 8645}
8646
bd2e244f 8647static void skylake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 8648 struct intel_crtc_state *pipe_config)
bd2e244f
JB		 8649{
8650 struct drm_device *dev = crtc->base.dev;
8651 struct drm_i915_private *dev_priv = dev->dev_private;
a1b2278e
CK		 8652 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8653 uint32_t ps_ctrl = 0;
8654 int id = -1;
8655 int i;
bd2e244f 8656
a1b2278e
CK		 8657 /* find scaler attached to this pipe */
8658 for (i = 0; i < crtc->num_scalers; i++) {
8659 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8660 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8661 id = i;
8662 pipe_config->pch_pfit.enabled = true;
8663 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8664 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8665 break;
8666 }
8667 }
bd2e244f 8668
a1b2278e
CK		 8669 scaler_state->scaler_id = id;
8670 if (id >= 0) {
8671 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8672 } else {
8673 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
bd2e244f
JB		 8674 }
8675}
8676
5724dbd1
DL		 8677static void
8678skylake_get_initial_plane_config(struct intel_crtc *crtc,
8679 struct intel_initial_plane_config *plane_config)
bc8d7dff
DL		 8680{
8681 struct drm_device *dev = crtc->base.dev;
8682 struct drm_i915_private *dev_priv = dev->dev_private;
40f46283 8683 u32 val, base, offset, stride_mult, tiling;
bc8d7dff
DL		 8684 int pipe = crtc->pipe;
8685 int fourcc, pixel_format;
6761dd31 8686 unsigned int aligned_height;
bc8d7dff 8687 struct drm_framebuffer *fb;
1b842c89 8688 struct intel_framebuffer *intel_fb;
bc8d7dff 8689
d9806c9f 8690 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 8691 if (!intel_fb) {
bc8d7dff
DL		 8692 DRM_DEBUG_KMS("failed to alloc fb\n");
8693 return;
8694 }
8695
1b842c89
DL		 8696 fb = &intel_fb->base;
8697
bc8d7dff 8698 val = I915_READ(PLANE_CTL(pipe, 0));
42a7b088
DL		 8699 if (!(val & PLANE_CTL_ENABLE))
8700 goto error;
8701
bc8d7dff
DL		 8702 pixel_format = val & PLANE_CTL_FORMAT_MASK;
8703 fourcc = skl_format_to_fourcc(pixel_format,
8704 val & PLANE_CTL_ORDER_RGBX,
8705 val & PLANE_CTL_ALPHA_MASK);
8706 fb->pixel_format = fourcc;
8707 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8708
40f46283
DL		 8709 tiling = val & PLANE_CTL_TILED_MASK;
8710 switch (tiling) {
8711 case PLANE_CTL_TILED_LINEAR:
8712 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
8713 break;
8714 case PLANE_CTL_TILED_X:
8715 plane_config->tiling = I915_TILING_X;
8716 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8717 break;
8718 case PLANE_CTL_TILED_Y:
8719 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
8720 break;
8721 case PLANE_CTL_TILED_YF:
8722 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
8723 break;
8724 default:
8725 MISSING_CASE(tiling);
8726 goto error;
8727 }
8728
bc8d7dff
DL		 8729 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8730 plane_config->base = base;
8731
8732 offset = I915_READ(PLANE_OFFSET(pipe, 0));
8733
8734 val = I915_READ(PLANE_SIZE(pipe, 0));
8735 fb->height = ((val >> 16) & 0xfff) + 1;
8736 fb->width = ((val >> 0) & 0x1fff) + 1;
8737
8738 val = I915_READ(PLANE_STRIDE(pipe, 0));
40f46283
DL		 8739 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
8740 fb->pixel_format);
bc8d7dff
DL		 8741 fb->pitches[0] = (val & 0x3ff) * stride_mult;
8742
8743 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 8744 fb->pixel_format,
8745 fb->modifier[0]);
bc8d7dff 8746
f37b5c2b 8747 plane_config->size = fb->pitches[0] * aligned_height;
bc8d7dff
DL		 8748
8749 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8750 pipe_name(pipe), fb->width, fb->height,
8751 fb->bits_per_pixel, base, fb->pitches[0],
8752 plane_config->size);
8753
2d14030b 8754 plane_config->fb = intel_fb;
bc8d7dff
DL		 8755 return;
8756
8757error:
8758 kfree(fb);
8759}
8760
2fa2fe9a 8761static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 8762 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 8763{
8764 struct drm_device *dev = crtc->base.dev;
8765 struct drm_i915_private *dev_priv = dev->dev_private;
8766 uint32_t tmp;
8767
8768 tmp = I915_READ(PF_CTL(crtc->pipe));
8769
8770 if (tmp & PF_ENABLE) {
fd4daa9c 8771 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV		 8772 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8773 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 8774
8775 /* We currently do not free assignements of panel fitters on
8776 * ivb/hsw (since we don't use the higher upscaling modes which
8777 * differentiates them) so just WARN about this case for now. */
8778 if (IS_GEN7(dev)) {
8779 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8780 PF_PIPE_SEL_IVB(crtc->pipe));
8781 }
2fa2fe9a 8782 }
79e53945
JB		 8783}
8784
5724dbd1
DL		 8785static void
8786ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8787 struct intel_initial_plane_config *plane_config)
4c6baa59
JB		 8788{
8789 struct drm_device *dev = crtc->base.dev;
8790 struct drm_i915_private *dev_priv = dev->dev_private;
8791 u32 val, base, offset;
aeee5a49 8792 int pipe = crtc->pipe;
4c6baa59 8793 int fourcc, pixel_format;
6761dd31 8794 unsigned int aligned_height;
b113d5ee 8795 struct drm_framebuffer *fb;
1b842c89 8796 struct intel_framebuffer *intel_fb;
4c6baa59 8797
42a7b088
DL		 8798 val = I915_READ(DSPCNTR(pipe));
8799 if (!(val & DISPLAY_PLANE_ENABLE))
8800 return;
8801
d9806c9f 8802 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 8803 if (!intel_fb) {
4c6baa59
JB		 8804 DRM_DEBUG_KMS("failed to alloc fb\n");
8805 return;
8806 }
8807
1b842c89
DL		 8808 fb = &intel_fb->base;
8809
18c5247e
DV		 8810 if (INTEL_INFO(dev)->gen >= 4) {
8811 if (val & DISPPLANE_TILED) {
49af449b 8812 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 8813 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8814 }
8815 }
4c6baa59
JB		 8816
8817 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 8818 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 8819 fb->pixel_format = fourcc;
8820 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
4c6baa59 8821
aeee5a49 8822 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
4c6baa59 8823 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
aeee5a49 8824 offset = I915_READ(DSPOFFSET(pipe));
4c6baa59 8825 } else {
49af449b 8826 if (plane_config->tiling)
aeee5a49 8827 offset = I915_READ(DSPTILEOFF(pipe));
4c6baa59 8828 else
aeee5a49 8829 offset = I915_READ(DSPLINOFF(pipe));
4c6baa59
JB		 8830 }
8831 plane_config->base = base;
8832
8833 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 8834 fb->width = ((val >> 16) & 0xfff) + 1;
8835 fb->height = ((val >> 0) & 0xfff) + 1;
4c6baa59
JB		 8836
8837 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 8838 fb->pitches[0] = val & 0xffffffc0;
4c6baa59 8839
b113d5ee 8840 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 8841 fb->pixel_format,
8842 fb->modifier[0]);
4c6baa59 8843
f37b5c2b 8844 plane_config->size = fb->pitches[0] * aligned_height;
4c6baa59 8845
2844a921
DL		 8846 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8847 pipe_name(pipe), fb->width, fb->height,
8848 fb->bits_per_pixel, base, fb->pitches[0],
8849 plane_config->size);
b113d5ee 8850
2d14030b 8851 plane_config->fb = intel_fb;
4c6baa59
JB		 8852}
8853
0e8ffe1b 8854static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5cec258b 8855 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 8856{
8857 struct drm_device *dev = crtc->base.dev;
8858 struct drm_i915_private *dev_priv = dev->dev_private;
8859 uint32_t tmp;
8860
f458ebbc
DV		 8861 if (!intel_display_power_is_enabled(dev_priv,
8862 POWER_DOMAIN_PIPE(crtc->pipe)))
930e8c9e
PZ		 8863 return false;
8864
e143a21c 8865 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 8866 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 8867
0e8ffe1b
DV		 8868 tmp = I915_READ(PIPECONF(crtc->pipe));
8869 if (!(tmp & PIPECONF_ENABLE))
8870 return false;
8871
42571aef
VS		 8872 switch (tmp & PIPECONF_BPC_MASK) {
8873 case PIPECONF_6BPC:
8874 pipe_config->pipe_bpp = 18;
8875 break;
8876 case PIPECONF_8BPC:
8877 pipe_config->pipe_bpp = 24;
8878 break;
8879 case PIPECONF_10BPC:
8880 pipe_config->pipe_bpp = 30;
8881 break;
8882 case PIPECONF_12BPC:
8883 pipe_config->pipe_bpp = 36;
8884 break;
8885 default:
8886 break;
8887 }
8888
b5a9fa09
DV		 8889 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8890 pipe_config->limited_color_range = true;
8891
ab9412ba 8892 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 8893 struct intel_shared_dpll *pll;
8894
88adfff1
DV		 8895 pipe_config->has_pch_encoder = true;
8896
627eb5a3
DV		 8897 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8898 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8899 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 8900
8901 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 8902
c0d43d62 8903 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 8904 pipe_config->shared_dpll =
8905 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 8906 } else {
8907 tmp = I915_READ(PCH_DPLL_SEL);
8908 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8909 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
8910 else
8911 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
8912 }
66e985c0
DV		 8913
8914 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8915
8916 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8917 &pipe_config->dpll_hw_state));
c93f54cf
DV		 8918
8919 tmp = pipe_config->dpll_hw_state.dpll;
8920 pipe_config->pixel_multiplier =
8921 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8922 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 8923
8924 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 8925 } else {
8926 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 8927 }
8928
1bd1bd80
DV		 8929 intel_get_pipe_timings(crtc, pipe_config);
8930
2fa2fe9a
DV		 8931 ironlake_get_pfit_config(crtc, pipe_config);
8932
0e8ffe1b
DV		 8933 return true;
8934}
8935
be256dc7
PZ		 8936static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8937{
8938 struct drm_device *dev = dev_priv->dev;
be256dc7 8939 struct intel_crtc *crtc;
be256dc7 8940
d3fcc808 8941 for_each_intel_crtc(dev, crtc)
e2c719b7 8942 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
be256dc7
PZ		 8943 pipe_name(crtc->pipe));
8944
e2c719b7
RC		 8945 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8946 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8947 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8948 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8949 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
8950 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
be256dc7 8951 "CPU PWM1 enabled\n");
c5107b87 8952 if (IS_HASWELL(dev))
e2c719b7 8953 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
c5107b87 8954 "CPU PWM2 enabled\n");
e2c719b7 8955 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
be256dc7 8956 "PCH PWM1 enabled\n");
e2c719b7 8957 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
be256dc7 8958 "Utility pin enabled\n");
e2c719b7 8959 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
be256dc7 8960
9926ada1
PZ		 8961 /*
8962 * In theory we can still leave IRQs enabled, as long as only the HPD
8963 * interrupts remain enabled. We used to check for that, but since it's
8964 * gen-specific and since we only disable LCPLL after we fully disable
8965 * the interrupts, the check below should be enough.
8966 */
e2c719b7 8967 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
be256dc7
PZ		 8968}
8969
9ccd5aeb
PZ		 8970static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8971{
8972 struct drm_device *dev = dev_priv->dev;
8973
8974 if (IS_HASWELL(dev))
8975 return I915_READ(D_COMP_HSW);
8976 else
8977 return I915_READ(D_COMP_BDW);
8978}
8979
3c4c9b81
PZ		 8980static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8981{
8982 struct drm_device *dev = dev_priv->dev;
8983
8984 if (IS_HASWELL(dev)) {
8985 mutex_lock(&dev_priv->rps.hw_lock);
8986 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8987 val))
f475dadf 8988 DRM_ERROR("Failed to write to D_COMP\n");
3c4c9b81
PZ		 8989 mutex_unlock(&dev_priv->rps.hw_lock);
8990 } else {
9ccd5aeb
PZ		 8991 I915_WRITE(D_COMP_BDW, val);
8992 POSTING_READ(D_COMP_BDW);
3c4c9b81 8993 }
be256dc7
PZ		 8994}
8995
8996/*
8997 * This function implements pieces of two sequences from BSpec:
8998 * - Sequence for display software to disable LCPLL
8999 * - Sequence for display software to allow package C8+
9000 * The steps implemented here are just the steps that actually touch the LCPLL
9001 * register. Callers should take care of disabling all the display engine
9002 * functions, doing the mode unset, fixing interrupts, etc.
9003 */
6ff58d53
PZ		 9004static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9005 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ		 9006{
9007 uint32_t val;
9008
9009 assert_can_disable_lcpll(dev_priv);
9010
9011 val = I915_READ(LCPLL_CTL);
9012
9013 if (switch_to_fclk) {
9014 val |= LCPLL_CD_SOURCE_FCLK;
9015 I915_WRITE(LCPLL_CTL, val);
9016
9017 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9018 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9019 DRM_ERROR("Switching to FCLK failed\n");
9020
9021 val = I915_READ(LCPLL_CTL);
9022 }
9023
9024 val |= LCPLL_PLL_DISABLE;
9025 I915_WRITE(LCPLL_CTL, val);
9026 POSTING_READ(LCPLL_CTL);
9027
9028 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9029 DRM_ERROR("LCPLL still locked\n");
9030
9ccd5aeb 9031 val = hsw_read_dcomp(dev_priv);
be256dc7 9032 val |= D_COMP_COMP_DISABLE;
3c4c9b81 9033 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9034 ndelay(100);
9035
9ccd5aeb
PZ		 9036 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9037 1))
be256dc7
PZ		 9038 DRM_ERROR("D_COMP RCOMP still in progress\n");
9039
9040 if (allow_power_down) {
9041 val = I915_READ(LCPLL_CTL);
9042 val |= LCPLL_POWER_DOWN_ALLOW;
9043 I915_WRITE(LCPLL_CTL, val);
9044 POSTING_READ(LCPLL_CTL);
9045 }
9046}
9047
9048/*
9049 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9050 * source.
9051 */
6ff58d53 9052static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ		 9053{
9054 uint32_t val;
9055
9056 val = I915_READ(LCPLL_CTL);
9057
9058 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9059 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9060 return;
9061
a8a8bd54
PZ		 9062 /*
9063 * Make sure we're not on PC8 state before disabling PC8, otherwise
9064 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
a8a8bd54 9065 */
59bad947 9066 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
215733fa 9067
be256dc7
PZ		 9068 if (val & LCPLL_POWER_DOWN_ALLOW) {
9069 val &= ~LCPLL_POWER_DOWN_ALLOW;
9070 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 9071 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 9072 }
9073
9ccd5aeb 9074 val = hsw_read_dcomp(dev_priv);
be256dc7
PZ		 9075 val |= D_COMP_COMP_FORCE;
9076 val &= ~D_COMP_COMP_DISABLE;
3c4c9b81 9077 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9078
9079 val = I915_READ(LCPLL_CTL);
9080 val &= ~LCPLL_PLL_DISABLE;
9081 I915_WRITE(LCPLL_CTL, val);
9082
9083 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9084 DRM_ERROR("LCPLL not locked yet\n");
9085
9086 if (val & LCPLL_CD_SOURCE_FCLK) {
9087 val = I915_READ(LCPLL_CTL);
9088 val &= ~LCPLL_CD_SOURCE_FCLK;
9089 I915_WRITE(LCPLL_CTL, val);
9090
9091 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9092 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9093 DRM_ERROR("Switching back to LCPLL failed\n");
9094 }
215733fa 9095
59bad947 9096 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
be256dc7
PZ		 9097}
9098
765dab67
PZ		 9099/*
9100 * Package states C8 and deeper are really deep PC states that can only be
9101 * reached when all the devices on the system allow it, so even if the graphics
9102 * device allows PC8+, it doesn't mean the system will actually get to these
9103 * states. Our driver only allows PC8+ when going into runtime PM.
9104 *
9105 * The requirements for PC8+ are that all the outputs are disabled, the power
9106 * well is disabled and most interrupts are disabled, and these are also
9107 * requirements for runtime PM. When these conditions are met, we manually do
9108 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9109 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9110 * hang the machine.
9111 *
9112 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9113 * the state of some registers, so when we come back from PC8+ we need to
9114 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9115 * need to take care of the registers kept by RC6. Notice that this happens even
9116 * if we don't put the device in PCI D3 state (which is what currently happens
9117 * because of the runtime PM support).
9118 *
9119 * For more, read "Display Sequences for Package C8" on the hardware
9120 * documentation.
9121 */
a14cb6fc 9122void hsw_enable_pc8(struct drm_i915_private *dev_priv)
c67a470b 9123{
c67a470b
PZ		 9124 struct drm_device *dev = dev_priv->dev;
9125 uint32_t val;
9126
c67a470b
PZ		 9127 DRM_DEBUG_KMS("Enabling package C8+\n");
9128
c67a470b
PZ		 9129 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9130 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9131 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9132 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9133 }
9134
9135 lpt_disable_clkout_dp(dev);
c67a470b
PZ		 9136 hsw_disable_lcpll(dev_priv, true, true);
9137}
9138
a14cb6fc 9139void hsw_disable_pc8(struct drm_i915_private *dev_priv)
c67a470b
PZ		 9140{
9141 struct drm_device *dev = dev_priv->dev;
9142 uint32_t val;
9143
c67a470b
PZ		 9144 DRM_DEBUG_KMS("Disabling package C8+\n");
9145
9146 hsw_restore_lcpll(dev_priv);
c67a470b
PZ		 9147 lpt_init_pch_refclk(dev);
9148
9149 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9150 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9151 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9152 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9153 }
9154
9155 intel_prepare_ddi(dev);
c67a470b
PZ		 9156}
9157
f8437dd1
VK		 9158static void broxton_modeset_global_resources(struct drm_atomic_state *state)
9159{
9160 struct drm_device *dev = state->dev;
9161 struct drm_i915_private *dev_priv = dev->dev_private;
9162 int max_pixclk = intel_mode_max_pixclk(state);
9163 int req_cdclk;
9164
9165 /* see the comment in valleyview_modeset_global_resources */
9166 if (WARN_ON(max_pixclk < 0))
9167 return;
9168
9169 req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
9170
9171 if (req_cdclk != dev_priv->cdclk_freq)
9172 broxton_set_cdclk(dev, req_cdclk);
9173}
9174
190f68c5
ACO		 9175static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9176 struct intel_crtc_state *crtc_state)
09b4ddf9 9177{
190f68c5 9178 if (!intel_ddi_pll_select(crtc, crtc_state))
6441ab5f 9179 return -EINVAL;
716c2e55 9180
c7653199 9181 crtc->lowfreq_avail = false;
644cef34 9182
c8f7a0db 9183 return 0;
79e53945
JB		 9184}
9185
3760b59c
S		 9186static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9187 enum port port,
9188 struct intel_crtc_state *pipe_config)
9189{
9190 switch (port) {
9191 case PORT_A:
9192 pipe_config->ddi_pll_sel = SKL_DPLL0;
9193 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9194 break;
9195 case PORT_B:
9196 pipe_config->ddi_pll_sel = SKL_DPLL1;
9197 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9198 break;
9199 case PORT_C:
9200 pipe_config->ddi_pll_sel = SKL_DPLL2;
9201 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9202 break;
9203 default:
9204 DRM_ERROR("Incorrect port type\n");
9205 }
9206}
9207
96b7dfb7
S		 9208static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9209 enum port port,
5cec258b 9210 struct intel_crtc_state *pipe_config)
96b7dfb7 9211{
3148ade7 9212 u32 temp, dpll_ctl1;
96b7dfb7
S		 9213
9214 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9215 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9216
9217 switch (pipe_config->ddi_pll_sel) {
3148ade7
DL		 9218 case SKL_DPLL0:
9219 /*
9220 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9221 * of the shared DPLL framework and thus needs to be read out
9222 * separately
9223 */
9224 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9225 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9226 break;
96b7dfb7
S		 9227 case SKL_DPLL1:
9228 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9229 break;
9230 case SKL_DPLL2:
9231 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9232 break;
9233 case SKL_DPLL3:
9234 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9235 break;
96b7dfb7
S		 9236 }
9237}
9238
7d2c8175
DL		 9239static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9240 enum port port,
5cec258b 9241 struct intel_crtc_state *pipe_config)
7d2c8175
DL		 9242{
9243 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9244
9245 switch (pipe_config->ddi_pll_sel) {
9246 case PORT_CLK_SEL_WRPLL1:
9247 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9248 break;
9249 case PORT_CLK_SEL_WRPLL2:
9250 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9251 break;
9252 }
9253}
9254
26804afd 9255static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
5cec258b 9256 struct intel_crtc_state *pipe_config)
26804afd
DV		 9257{
9258 struct drm_device *dev = crtc->base.dev;
9259 struct drm_i915_private *dev_priv = dev->dev_private;
d452c5b6 9260 struct intel_shared_dpll *pll;
26804afd
DV		 9261 enum port port;
9262 uint32_t tmp;
9263
9264 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9265
9266 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9267
96b7dfb7
S		 9268 if (IS_SKYLAKE(dev))
9269 skylake_get_ddi_pll(dev_priv, port, pipe_config);
3760b59c
S		 9270 else if (IS_BROXTON(dev))
9271 bxt_get_ddi_pll(dev_priv, port, pipe_config);
96b7dfb7
S		 9272 else
9273 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9cd86933 9274
d452c5b6
DV		 9275 if (pipe_config->shared_dpll >= 0) {
9276 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9277
9278 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9279 &pipe_config->dpll_hw_state));
9280 }
9281
26804afd
DV		 9282 /*
9283 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9284 * DDI E. So just check whether this pipe is wired to DDI E and whether
9285 * the PCH transcoder is on.
9286 */
ca370455
DL		 9287 if (INTEL_INFO(dev)->gen < 9 &&
9288 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
26804afd
DV		 9289 pipe_config->has_pch_encoder = true;
9290
9291 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9292 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9293 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9294
9295 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9296 }
9297}
9298
0e8ffe1b 9299static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9300 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9301{
9302 struct drm_device *dev = crtc->base.dev;
9303 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 9304 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 9305 uint32_t tmp;
9306
f458ebbc 9307 if (!intel_display_power_is_enabled(dev_priv,
b5482bd0
ID		 9308 POWER_DOMAIN_PIPE(crtc->pipe)))
9309 return false;
9310
e143a21c 9311 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 9312 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9313
eccb140b
DV		 9314 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9315 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9316 enum pipe trans_edp_pipe;
9317 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9318 default:
9319 WARN(1, "unknown pipe linked to edp transcoder\n");
9320 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9321 case TRANS_DDI_EDP_INPUT_A_ON:
9322 trans_edp_pipe = PIPE_A;
9323 break;
9324 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9325 trans_edp_pipe = PIPE_B;
9326 break;
9327 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9328 trans_edp_pipe = PIPE_C;
9329 break;
9330 }
9331
9332 if (trans_edp_pipe == crtc->pipe)
9333 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9334 }
9335
f458ebbc 9336 if (!intel_display_power_is_enabled(dev_priv,
eccb140b 9337 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 9338 return false;
9339
eccb140b 9340 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 9341 if (!(tmp & PIPECONF_ENABLE))
9342 return false;
9343
26804afd 9344 haswell_get_ddi_port_state(crtc, pipe_config);
627eb5a3 9345
1bd1bd80
DV		 9346 intel_get_pipe_timings(crtc, pipe_config);
9347
a1b2278e
CK		 9348 if (INTEL_INFO(dev)->gen >= 9) {
9349 skl_init_scalers(dev, crtc, pipe_config);
9350 }
9351
2fa2fe9a 9352 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
bd2e244f 9353 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
ff6d9f55 9354 if (INTEL_INFO(dev)->gen == 9)
bd2e244f 9355 skylake_get_pfit_config(crtc, pipe_config);
ff6d9f55 9356 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 9357 ironlake_get_pfit_config(crtc, pipe_config);
ff6d9f55
JB		 9358 else
9359 MISSING_CASE(INTEL_INFO(dev)->gen);
9360
a1b2278e
CK		 9361 } else {
9362 pipe_config->scaler_state.scaler_id = -1;
9363 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
bd2e244f 9364 }
88adfff1 9365
e59150dc
JB		 9366 if (IS_HASWELL(dev))
9367 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9368 (I915_READ(IPS_CTL) & IPS_ENABLE);
42db64ef 9369
ebb69c95
CT		 9370 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9371 pipe_config->pixel_multiplier =
9372 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9373 } else {
9374 pipe_config->pixel_multiplier = 1;
9375 }
6c49f241 9376
0e8ffe1b
DV		 9377 return true;
9378}
9379
560b85bb
CW		 9380static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9381{
9382 struct drm_device *dev = crtc->dev;
9383 struct drm_i915_private *dev_priv = dev->dev_private;
9384 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dc41c154 9385 uint32_t cntl = 0, size = 0;
560b85bb 9386
dc41c154 9387 if (base) {
3dd512fb
MR		 9388 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9389 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
dc41c154
VS		 9390 unsigned int stride = roundup_pow_of_two(width) * 4;
9391
9392 switch (stride) {
9393 default:
9394 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9395 width, stride);
9396 stride = 256;
9397 /* fallthrough */
9398 case 256:
9399 case 512:
9400 case 1024:
9401 case 2048:
9402 break;
4b0e333e
CW		 9403 }
9404
dc41c154
VS		 9405 cntl |= CURSOR_ENABLE |
9406 CURSOR_GAMMA_ENABLE |
9407 CURSOR_FORMAT_ARGB |
9408 CURSOR_STRIDE(stride);
9409
9410 size = (height << 12) | width;
4b0e333e 9411 }
560b85bb 9412
dc41c154
VS		 9413 if (intel_crtc->cursor_cntl != 0 &&
9414 (intel_crtc->cursor_base != base ||
9415 intel_crtc->cursor_size != size ||
9416 intel_crtc->cursor_cntl != cntl)) {
9417 /* On these chipsets we can only modify the base/size/stride
9418 * whilst the cursor is disabled.
9419 */
9420 I915_WRITE(_CURACNTR, 0);
4b0e333e 9421 POSTING_READ(_CURACNTR);
dc41c154 9422 intel_crtc->cursor_cntl = 0;
4b0e333e 9423 }
560b85bb 9424
99d1f387 9425 if (intel_crtc->cursor_base != base) {
9db4a9c7 9426 I915_WRITE(_CURABASE, base);
99d1f387
VS		 9427 intel_crtc->cursor_base = base;
9428 }
4726e0b0 9429
dc41c154
VS		 9430 if (intel_crtc->cursor_size != size) {
9431 I915_WRITE(CURSIZE, size);
9432 intel_crtc->cursor_size = size;
4b0e333e 9433 }
560b85bb 9434
4b0e333e 9435 if (intel_crtc->cursor_cntl != cntl) {
4b0e333e
CW		 9436 I915_WRITE(_CURACNTR, cntl);
9437 POSTING_READ(_CURACNTR);
4b0e333e 9438 intel_crtc->cursor_cntl = cntl;
560b85bb 9439 }
560b85bb
CW		 9440}
9441
560b85bb 9442static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
65a21cd6
JB		 9443{
9444 struct drm_device *dev = crtc->dev;
9445 struct drm_i915_private *dev_priv = dev->dev_private;
9446 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9447 int pipe = intel_crtc->pipe;
4b0e333e
CW		 9448 uint32_t cntl;
9449
9450 cntl = 0;
9451 if (base) {
9452 cntl = MCURSOR_GAMMA_ENABLE;
3dd512fb 9453 switch (intel_crtc->base.cursor->state->crtc_w) {
4726e0b0
SK		 9454 case 64:
9455 cntl |= CURSOR_MODE_64_ARGB_AX;
9456 break;
9457 case 128:
9458 cntl |= CURSOR_MODE_128_ARGB_AX;
9459 break;
9460 case 256:
9461 cntl |= CURSOR_MODE_256_ARGB_AX;
9462 break;
9463 default:
3dd512fb 9464 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
4726e0b0 9465 return;
65a21cd6 9466 }
4b0e333e 9467 cntl |= pipe << 28; /* Connect to correct pipe */
47bf17a7
VS		 9468
9469 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9470 cntl |= CURSOR_PIPE_CSC_ENABLE;
4b0e333e 9471 }
65a21cd6 9472
8e7d688b 9473 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
4398ad45
VS		 9474 cntl |= CURSOR_ROTATE_180;
9475
4b0e333e
CW		 9476 if (intel_crtc->cursor_cntl != cntl) {
9477 I915_WRITE(CURCNTR(pipe), cntl);
9478 POSTING_READ(CURCNTR(pipe));
9479 intel_crtc->cursor_cntl = cntl;
65a21cd6 9480 }
4b0e333e 9481
65a21cd6 9482 /* and commit changes on next vblank */
5efb3e28
VS		 9483 I915_WRITE(CURBASE(pipe), base);
9484 POSTING_READ(CURBASE(pipe));
99d1f387
VS		 9485
9486 intel_crtc->cursor_base = base;
65a21cd6
JB		 9487}
9488
cda4b7d3 9489/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 9490static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9491 bool on)
cda4b7d3
CW		 9492{
9493 struct drm_device *dev = crtc->dev;
9494 struct drm_i915_private *dev_priv = dev->dev_private;
9495 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9496 int pipe = intel_crtc->pipe;
3d7d6510
MR		 9497 int x = crtc->cursor_x;
9498 int y = crtc->cursor_y;
d6e4db15 9499 u32 base = 0, pos = 0;
cda4b7d3 9500
d6e4db15 9501 if (on)
cda4b7d3 9502 base = intel_crtc->cursor_addr;
cda4b7d3 9503
6e3c9717 9504 if (x >= intel_crtc->config->pipe_src_w)
d6e4db15
VS		 9505 base = 0;
9506
6e3c9717 9507 if (y >= intel_crtc->config->pipe_src_h)
cda4b7d3
CW		 9508 base = 0;
9509
9510 if (x < 0) {
3dd512fb 9511 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
cda4b7d3
CW		 9512 base = 0;
9513
9514 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9515 x = -x;
9516 }
9517 pos |= x << CURSOR_X_SHIFT;
9518
9519 if (y < 0) {
3dd512fb 9520 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
cda4b7d3
CW		 9521 base = 0;
9522
9523 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9524 y = -y;
9525 }
9526 pos |= y << CURSOR_Y_SHIFT;
9527
4b0e333e 9528 if (base == 0 && intel_crtc->cursor_base == 0)
cda4b7d3
CW		 9529 return;
9530
5efb3e28
VS		 9531 I915_WRITE(CURPOS(pipe), pos);
9532
4398ad45
VS		 9533 /* ILK+ do this automagically */
9534 if (HAS_GMCH_DISPLAY(dev) &&
8e7d688b 9535 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
3dd512fb
MR		 9536 base += (intel_crtc->base.cursor->state->crtc_h *
9537 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
4398ad45
VS		 9538 }
9539
8ac54669 9540 if (IS_845G(dev) || IS_I865G(dev))
5efb3e28
VS		 9541 i845_update_cursor(crtc, base);
9542 else
9543 i9xx_update_cursor(crtc, base);
cda4b7d3
CW		 9544}
9545
dc41c154
VS		 9546static bool cursor_size_ok(struct drm_device *dev,
9547 uint32_t width, uint32_t height)
9548{
9549 if (width == 0 || height == 0)
9550 return false;
9551
9552 /*
9553 * 845g/865g are special in that they are only limited by
9554 * the width of their cursors, the height is arbitrary up to
9555 * the precision of the register. Everything else requires
9556 * square cursors, limited to a few power-of-two sizes.
9557 */
9558 if (IS_845G(dev) || IS_I865G(dev)) {
9559 if ((width & 63) != 0)
9560 return false;
9561
9562 if (width > (IS_845G(dev) ? 64 : 512))
9563 return false;
9564
9565 if (height > 1023)
9566 return false;
9567 } else {
9568 switch (width | height) {
9569 case 256:
9570 case 128:
9571 if (IS_GEN2(dev))
9572 return false;
9573 case 64:
9574 break;
9575 default:
9576 return false;
9577 }
9578 }
9579
9580 return true;
9581}
9582
79e53945 9583static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 9584 u16 *blue, uint32_t start, uint32_t size)
79e53945 9585{
7203425a 9586 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 9587 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 9588
7203425a 9589 for (i = start; i < end; i++) {
79e53945
JB		 9590 intel_crtc->lut_r[i] = red[i] >> 8;
9591 intel_crtc->lut_g[i] = green[i] >> 8;
9592 intel_crtc->lut_b[i] = blue[i] >> 8;
9593 }
9594
9595 intel_crtc_load_lut(crtc);
9596}
9597
79e53945
JB		 9598/* VESA 640x480x72Hz mode to set on the pipe */
9599static struct drm_display_mode load_detect_mode = {
9600 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9601 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9602};
9603
a8bb6818
DV		 9604struct drm_framebuffer *
9605__intel_framebuffer_create(struct drm_device *dev,
9606 struct drm_mode_fb_cmd2 *mode_cmd,
9607 struct drm_i915_gem_object *obj)
d2dff872
CW		 9608{
9609 struct intel_framebuffer *intel_fb;
9610 int ret;
9611
9612 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9613 if (!intel_fb) {
6ccb81f2 9614 drm_gem_object_unreference(&obj->base);
d2dff872
CW		 9615 return ERR_PTR(-ENOMEM);
9616 }
9617
9618 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
dd4916c5
DV		 9619 if (ret)
9620 goto err;
d2dff872
CW		 9621
9622 return &intel_fb->base;
dd4916c5 9623err:
6ccb81f2 9624 drm_gem_object_unreference(&obj->base);
dd4916c5
DV		 9625 kfree(intel_fb);
9626
9627 return ERR_PTR(ret);
d2dff872
CW		 9628}
9629
b5ea642a 9630static struct drm_framebuffer *
a8bb6818
DV		 9631intel_framebuffer_create(struct drm_device *dev,
9632 struct drm_mode_fb_cmd2 *mode_cmd,
9633 struct drm_i915_gem_object *obj)
9634{
9635 struct drm_framebuffer *fb;
9636 int ret;
9637
9638 ret = i915_mutex_lock_interruptible(dev);
9639 if (ret)
9640 return ERR_PTR(ret);
9641 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
9642 mutex_unlock(&dev->struct_mutex);
9643
9644 return fb;
9645}
9646
d2dff872
CW		 9647static u32
9648intel_framebuffer_pitch_for_width(int width, int bpp)
9649{
9650 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
9651 return ALIGN(pitch, 64);
9652}
9653
9654static u32
9655intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
9656{
9657 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
1267a26b 9658 return PAGE_ALIGN(pitch * mode->vdisplay);
d2dff872
CW		 9659}
9660
9661static struct drm_framebuffer *
9662intel_framebuffer_create_for_mode(struct drm_device *dev,
9663 struct drm_display_mode *mode,
9664 int depth, int bpp)
9665{
9666 struct drm_i915_gem_object *obj;
0fed39bd 9667 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 9668
9669 obj = i915_gem_alloc_object(dev,
9670 intel_framebuffer_size_for_mode(mode, bpp));
9671 if (obj == NULL)
9672 return ERR_PTR(-ENOMEM);
9673
9674 mode_cmd.width = mode->hdisplay;
9675 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 9676 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
9677 bpp);
5ca0c34a 9678 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 9679
9680 return intel_framebuffer_create(dev, &mode_cmd, obj);
9681}
9682
9683static struct drm_framebuffer *
9684mode_fits_in_fbdev(struct drm_device *dev,
9685 struct drm_display_mode *mode)
9686{
4520f53a 9687#ifdef CONFIG_DRM_I915_FBDEV
d2dff872
CW		 9688 struct drm_i915_private *dev_priv = dev->dev_private;
9689 struct drm_i915_gem_object *obj;
9690 struct drm_framebuffer *fb;
9691
4c0e5528 9692 if (!dev_priv->fbdev)
d2dff872
CW		 9693 return NULL;
9694
4c0e5528 9695 if (!dev_priv->fbdev->fb)
d2dff872
CW		 9696 return NULL;
9697
4c0e5528
DV		 9698 obj = dev_priv->fbdev->fb->obj;
9699 BUG_ON(!obj);
9700
8bcd4553 9701 fb = &dev_priv->fbdev->fb->base;
01f2c773
VS		 9702 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
9703 fb->bits_per_pixel))
d2dff872
CW		 9704 return NULL;
9705
01f2c773 9706 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 9707 return NULL;
9708
9709 return fb;
4520f53a
DV		 9710#else
9711 return NULL;
9712#endif
d2dff872
CW		 9713}
9714
d2434ab7 9715bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 9716 struct drm_display_mode *mode,
51fd371b
RC		 9717 struct intel_load_detect_pipe *old,
9718 struct drm_modeset_acquire_ctx *ctx)
79e53945
JB		 9719{
9720 struct intel_crtc *intel_crtc;
d2434ab7
DV		 9721 struct intel_encoder *intel_encoder =
9722 intel_attached_encoder(connector);
79e53945 9723 struct drm_crtc *possible_crtc;
4ef69c7a 9724 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 9725 struct drm_crtc *crtc = NULL;
9726 struct drm_device *dev = encoder->dev;
94352cf9 9727 struct drm_framebuffer *fb;
51fd371b 9728 struct drm_mode_config *config = &dev->mode_config;
83a57153 9729 struct drm_atomic_state *state = NULL;
944b0c76 9730 struct drm_connector_state *connector_state;
51fd371b 9731 int ret, i = -1;
79e53945 9732
d2dff872 9733 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 9734 connector->base.id, connector->name,
8e329a03 9735 encoder->base.id, encoder->name);
d2dff872 9736
51fd371b
RC		 9737retry:
9738 ret = drm_modeset_lock(&config->connection_mutex, ctx);
9739 if (ret)
9740 goto fail_unlock;
6e9f798d 9741
79e53945
JB		 9742 /*
9743 * Algorithm gets a little messy:
7a5e4805 9744 *
79e53945
JB		 9745 * - if the connector already has an assigned crtc, use it (but make
9746 * sure it's on first)
7a5e4805 9747 *
79e53945
JB		 9748 * - try to find the first unused crtc that can drive this connector,
9749 * and use that if we find one
79e53945
JB		 9750 */
9751
9752 /* See if we already have a CRTC for this connector */
9753 if (encoder->crtc) {
9754 crtc = encoder->crtc;
8261b191 9755
51fd371b 9756 ret = drm_modeset_lock(&crtc->mutex, ctx);
4d02e2de
DV		 9757 if (ret)
9758 goto fail_unlock;
9759 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
51fd371b
RC		 9760 if (ret)
9761 goto fail_unlock;
7b24056b 9762
24218aac 9763 old->dpms_mode = connector->dpms;
8261b191
CW		 9764 old->load_detect_temp = false;
9765
9766 /* Make sure the crtc and connector are running */
24218aac
DV		 9767 if (connector->dpms != DRM_MODE_DPMS_ON)
9768 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 9769
7173188d 9770 return true;
79e53945
JB		 9771 }
9772
9773 /* Find an unused one (if possible) */
70e1e0ec 9774 for_each_crtc(dev, possible_crtc) {
79e53945
JB		 9775 i++;
9776 if (!(encoder->possible_crtcs & (1 << i)))
9777 continue;
83d65738 9778 if (possible_crtc->state->enable)
a459249c
VS		 9779 continue;
9780 /* This can occur when applying the pipe A quirk on resume. */
9781 if (to_intel_crtc(possible_crtc)->new_enabled)
9782 continue;
9783
9784 crtc = possible_crtc;
9785 break;
79e53945
JB		 9786 }
9787
9788 /*
9789 * If we didn't find an unused CRTC, don't use any.
9790 */
9791 if (!crtc) {
7173188d 9792 DRM_DEBUG_KMS("no pipe available for load-detect\n");
51fd371b 9793 goto fail_unlock;
79e53945
JB		 9794 }
9795
51fd371b
RC		 9796 ret = drm_modeset_lock(&crtc->mutex, ctx);
9797 if (ret)
4d02e2de
DV		 9798 goto fail_unlock;
9799 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9800 if (ret)
51fd371b 9801 goto fail_unlock;
fc303101
DV		 9802 intel_encoder->new_crtc = to_intel_crtc(crtc);
9803 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 9804
9805 intel_crtc = to_intel_crtc(crtc);
412b61d8 9806 intel_crtc->new_enabled = true;
24218aac 9807 old->dpms_mode = connector->dpms;
8261b191 9808 old->load_detect_temp = true;
d2dff872 9809 old->release_fb = NULL;
79e53945 9810
83a57153
ACO		 9811 state = drm_atomic_state_alloc(dev);
9812 if (!state)
9813 return false;
9814
9815 state->acquire_ctx = ctx;
9816
944b0c76
ACO		 9817 connector_state = drm_atomic_get_connector_state(state, connector);
9818 if (IS_ERR(connector_state)) {
9819 ret = PTR_ERR(connector_state);
9820 goto fail;
9821 }
9822
9823 connector_state->crtc = crtc;
9824 connector_state->best_encoder = &intel_encoder->base;
9825
6492711d
CW		 9826 if (!mode)
9827 mode = &load_detect_mode;
79e53945 9828
d2dff872
CW		 9829 /* We need a framebuffer large enough to accommodate all accesses
9830 * that the plane may generate whilst we perform load detection.
9831 * We can not rely on the fbcon either being present (we get called
9832 * during its initialisation to detect all boot displays, or it may
9833 * not even exist) or that it is large enough to satisfy the
9834 * requested mode.
9835 */
94352cf9
DV		 9836 fb = mode_fits_in_fbdev(dev, mode);
9837 if (fb == NULL) {
d2dff872 9838 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 9839 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
9840 old->release_fb = fb;
d2dff872
CW		 9841 } else
9842 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 9843 if (IS_ERR(fb)) {
d2dff872 9844 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
412b61d8 9845 goto fail;
79e53945 9846 }
79e53945 9847
83a57153 9848 if (intel_set_mode(crtc, mode, 0, 0, fb, state)) {
6492711d 9849 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 9850 if (old->release_fb)
9851 old->release_fb->funcs->destroy(old->release_fb);
412b61d8 9852 goto fail;
79e53945 9853 }
9128b040 9854 crtc->primary->crtc = crtc;
7173188d 9855
79e53945 9856 /* let the connector get through one full cycle before testing */
9d0498a2 9857 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 9858 return true;
412b61d8
VS		 9859
9860 fail:
83d65738 9861 intel_crtc->new_enabled = crtc->state->enable;
51fd371b 9862fail_unlock:
83a57153
ACO		 9863 if (state) {
9864 drm_atomic_state_free(state);
9865 state = NULL;
9866 }
9867
51fd371b
RC		 9868 if (ret == -EDEADLK) {
9869 drm_modeset_backoff(ctx);
9870 goto retry;
9871 }
9872
412b61d8 9873 return false;
79e53945
JB		 9874}
9875
d2434ab7 9876void intel_release_load_detect_pipe(struct drm_connector *connector,
49172fee
ACO		 9877 struct intel_load_detect_pipe *old,
9878 struct drm_modeset_acquire_ctx *ctx)
79e53945 9879{
83a57153 9880 struct drm_device *dev = connector->dev;
d2434ab7
DV		 9881 struct intel_encoder *intel_encoder =
9882 intel_attached_encoder(connector);
4ef69c7a 9883 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 9884 struct drm_crtc *crtc = encoder->crtc;
412b61d8 9885 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83a57153 9886 struct drm_atomic_state *state;
944b0c76 9887 struct drm_connector_state *connector_state;
79e53945 9888
d2dff872 9889 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 9890 connector->base.id, connector->name,
8e329a03 9891 encoder->base.id, encoder->name);
d2dff872 9892
8261b191 9893 if (old->load_detect_temp) {
83a57153 9894 state = drm_atomic_state_alloc(dev);
944b0c76
ACO		 9895 if (!state)
9896 goto fail;
83a57153
ACO		 9897
9898 state->acquire_ctx = ctx;
9899
944b0c76
ACO		 9900 connector_state = drm_atomic_get_connector_state(state, connector);
9901 if (IS_ERR(connector_state))
9902 goto fail;
9903
fc303101
DV		 9904 to_intel_connector(connector)->new_encoder = NULL;
9905 intel_encoder->new_crtc = NULL;
412b61d8 9906 intel_crtc->new_enabled = false;
944b0c76
ACO		 9907
9908 connector_state->best_encoder = NULL;
9909 connector_state->crtc = NULL;
9910
83a57153
ACO		 9911 intel_set_mode(crtc, NULL, 0, 0, NULL, state);
9912
9913 drm_atomic_state_free(state);
d2dff872 9914
36206361
DV		 9915 if (old->release_fb) {
9916 drm_framebuffer_unregister_private(old->release_fb);
9917 drm_framebuffer_unreference(old->release_fb);
9918 }
d2dff872 9919
0622a53c 9920 return;
79e53945
JB		 9921 }
9922
c751ce4f 9923 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 9924 if (old->dpms_mode != DRM_MODE_DPMS_ON)
9925 connector->funcs->dpms(connector, old->dpms_mode);
944b0c76
ACO		 9926
9927 return;
9928fail:
9929 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
9930 drm_atomic_state_free(state);
79e53945
JB		 9931}
9932
da4a1efa 9933static int i9xx_pll_refclk(struct drm_device *dev,
5cec258b 9934 const struct intel_crtc_state *pipe_config)
da4a1efa
VS		 9935{
9936 struct drm_i915_private *dev_priv = dev->dev_private;
9937 u32 dpll = pipe_config->dpll_hw_state.dpll;
9938
9939 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
e91e941b 9940 return dev_priv->vbt.lvds_ssc_freq;
da4a1efa
VS		 9941 else if (HAS_PCH_SPLIT(dev))
9942 return 120000;
9943 else if (!IS_GEN2(dev))
9944 return 96000;
9945 else
9946 return 48000;
9947}
9948
79e53945 9949/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc 9950static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 9951 struct intel_crtc_state *pipe_config)
79e53945 9952{
f1f644dc 9953 struct drm_device *dev = crtc->base.dev;
79e53945 9954 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 9955 int pipe = pipe_config->cpu_transcoder;
293623f7 9956 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 9957 u32 fp;
9958 intel_clock_t clock;
da4a1efa 9959 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 9960
9961 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 9962 fp = pipe_config->dpll_hw_state.fp0;
79e53945 9963 else
293623f7 9964 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 9965
9966 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 9967 if (IS_PINEVIEW(dev)) {
9968 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
9969 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 9970 } else {
9971 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
9972 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
9973 }
9974
a6c45cf0 9975 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 9976 if (IS_PINEVIEW(dev))
9977 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
9978 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 9979 else
9980 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 9981 DPLL_FPA01_P1_POST_DIV_SHIFT);
9982
9983 switch (dpll & DPLL_MODE_MASK) {
9984 case DPLLB_MODE_DAC_SERIAL:
9985 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
9986 5 : 10;
9987 break;
9988 case DPLLB_MODE_LVDS:
9989 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
9990 7 : 14;
9991 break;
9992 default:
28c97730 9993 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 9994 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 9995 return;
79e53945
JB		 9996 }
9997
ac58c3f0 9998 if (IS_PINEVIEW(dev))
da4a1efa 9999 pineview_clock(refclk, &clock);
ac58c3f0 10000 else
da4a1efa 10001 i9xx_clock(refclk, &clock);
79e53945 10002 } else {
0fb58223 10003 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
b1c560d1 10004 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
79e53945
JB		 10005
10006 if (is_lvds) {
10007 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10008 DPLL_FPA01_P1_POST_DIV_SHIFT);
b1c560d1
VS		 10009
10010 if (lvds & LVDS_CLKB_POWER_UP)
10011 clock.p2 = 7;
10012 else
10013 clock.p2 = 14;
79e53945
JB		 10014 } else {
10015 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10016 clock.p1 = 2;
10017 else {
10018 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10019 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10020 }
10021 if (dpll & PLL_P2_DIVIDE_BY_4)
10022 clock.p2 = 4;
10023 else
10024 clock.p2 = 2;
79e53945 10025 }
da4a1efa
VS		 10026
10027 i9xx_clock(refclk, &clock);
79e53945
JB		 10028 }
10029
18442d08
VS		 10030 /*
10031 * This value includes pixel_multiplier. We will use
241bfc38 10032 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS		 10033 * encoder's get_config() function.
10034 */
10035 pipe_config->port_clock = clock.dot;
f1f644dc
JB		 10036}
10037
6878da05
VS		 10038int intel_dotclock_calculate(int link_freq,
10039 const struct intel_link_m_n *m_n)
f1f644dc 10040{
f1f644dc
JB		 10041 /*
10042 * The calculation for the data clock is:
1041a02f 10043 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 10044 * But we want to avoid losing precison if possible, so:
1041a02f 10045 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 10046 *
10047 * and the link clock is simpler:
1041a02f 10048 * link_clock = (m * link_clock) / n
f1f644dc
JB		 10049 */
10050
6878da05
VS		 10051 if (!m_n->link_n)
10052 return 0;
f1f644dc 10053
6878da05
VS		 10054 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10055}
f1f644dc 10056
18442d08 10057static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 10058 struct intel_crtc_state *pipe_config)
6878da05
VS		 10059{
10060 struct drm_device *dev = crtc->base.dev;
79e53945 10061
18442d08
VS		 10062 /* read out port_clock from the DPLL */
10063 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 10064
f1f644dc 10065 /*
18442d08 10066 * This value does not include pixel_multiplier.
241bfc38 10067 * We will check that port_clock and adjusted_mode.crtc_clock
18442d08
VS		 10068 * agree once we know their relationship in the encoder's
10069 * get_config() function.
79e53945 10070 */
2d112de7 10071 pipe_config->base.adjusted_mode.crtc_clock =
18442d08
VS		 10072 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10073 &pipe_config->fdi_m_n);
79e53945
JB		 10074}
10075
10076/** Returns the currently programmed mode of the given pipe. */
10077struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10078 struct drm_crtc *crtc)
10079{
548f245b 10080 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 10081 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 10082 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
79e53945 10083 struct drm_display_mode *mode;
5cec258b 10084 struct intel_crtc_state pipe_config;
fe2b8f9d
PZ		 10085 int htot = I915_READ(HTOTAL(cpu_transcoder));
10086 int hsync = I915_READ(HSYNC(cpu_transcoder));
10087 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10088 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 10089 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 10090
10091 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10092 if (!mode)
10093 return NULL;
10094
f1f644dc
JB		 10095 /*
10096 * Construct a pipe_config sufficient for getting the clock info
10097 * back out of crtc_clock_get.
10098 *
10099 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10100 * to use a real value here instead.
10101 */
293623f7 10102 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 10103 pipe_config.pixel_multiplier = 1;
293623f7
VS		 10104 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10105 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10106 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 10107 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10108
773ae034 10109 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB		 10110 mode->hdisplay = (htot & 0xffff) + 1;
10111 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10112 mode->hsync_start = (hsync & 0xffff) + 1;
10113 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10114 mode->vdisplay = (vtot & 0xffff) + 1;
10115 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10116 mode->vsync_start = (vsync & 0xffff) + 1;
10117 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10118
10119 drm_mode_set_name(mode);
79e53945
JB		 10120
10121 return mode;
10122}
10123
652c393a
JB		 10124static void intel_decrease_pllclock(struct drm_crtc *crtc)
10125{
10126 struct drm_device *dev = crtc->dev;
fbee40df 10127 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 10128 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 10129
baff296c 10130 if (!HAS_GMCH_DISPLAY(dev))
652c393a
JB		 10131 return;
10132
10133 if (!dev_priv->lvds_downclock_avail)
10134 return;
10135
10136 /*
10137 * Since this is called by a timer, we should never get here in
10138 * the manual case.
10139 */
10140 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 10141 int pipe = intel_crtc->pipe;
10142 int dpll_reg = DPLL(pipe);
10143 int dpll;
f6e5b160 10144
44d98a61 10145 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 10146
8ac5a6d5 10147 assert_panel_unlocked(dev_priv, pipe);
652c393a 10148
dc257cf1 10149 dpll = I915_READ(dpll_reg);
652c393a
JB		 10150 dpll |= DISPLAY_RATE_SELECT_FPA1;
10151 I915_WRITE(dpll_reg, dpll);
9d0498a2 10152 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 10153 dpll = I915_READ(dpll_reg);
10154 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 10155 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 10156 }
10157
10158}
10159
f047e395
CW		 10160void intel_mark_busy(struct drm_device *dev)
10161{
c67a470b
PZ		 10162 struct drm_i915_private *dev_priv = dev->dev_private;
10163
f62a0076
CW		 10164 if (dev_priv->mm.busy)
10165 return;
10166
43694d69 10167 intel_runtime_pm_get(dev_priv);
c67a470b 10168 i915_update_gfx_val(dev_priv);
43cf3bf0
CW		 10169 if (INTEL_INFO(dev)->gen >= 6)
10170 gen6_rps_busy(dev_priv);
f62a0076 10171 dev_priv->mm.busy = true;
f047e395
CW		 10172}
10173
10174void intel_mark_idle(struct drm_device *dev)
652c393a 10175{
c67a470b 10176 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 10177 struct drm_crtc *crtc;
652c393a 10178
f62a0076
CW		 10179 if (!dev_priv->mm.busy)
10180 return;
10181
10182 dev_priv->mm.busy = false;
10183
70e1e0ec 10184 for_each_crtc(dev, crtc) {
f4510a27 10185 if (!crtc->primary->fb)
652c393a
JB		 10186 continue;
10187
725a5b54 10188 intel_decrease_pllclock(crtc);
652c393a 10189 }
b29c19b6 10190
3d13ef2e 10191 if (INTEL_INFO(dev)->gen >= 6)
b29c19b6 10192 gen6_rps_idle(dev->dev_private);
bb4cdd53 10193
43694d69 10194 intel_runtime_pm_put(dev_priv);
652c393a
JB		 10195}
10196
f5de6e07
ACO		 10197static void intel_crtc_set_state(struct intel_crtc *crtc,
10198 struct intel_crtc_state *crtc_state)
10199{
10200 kfree(crtc->config);
10201 crtc->config = crtc_state;
16f3f658 10202 crtc->base.state = &crtc_state->base;
f5de6e07
ACO		 10203}
10204
79e53945
JB		 10205static void intel_crtc_destroy(struct drm_crtc *crtc)
10206{
10207 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 10208 struct drm_device *dev = crtc->dev;
10209 struct intel_unpin_work *work;
67e77c5a 10210
5e2d7afc 10211 spin_lock_irq(&dev->event_lock);
67e77c5a
DV		 10212 work = intel_crtc->unpin_work;
10213 intel_crtc->unpin_work = NULL;
5e2d7afc 10214 spin_unlock_irq(&dev->event_lock);
67e77c5a
DV		 10215
10216 if (work) {
10217 cancel_work_sync(&work->work);
10218 kfree(work);
10219 }
79e53945 10220
f5de6e07 10221 intel_crtc_set_state(intel_crtc, NULL);
79e53945 10222 drm_crtc_cleanup(crtc);
67e77c5a 10223
79e53945
JB		 10224 kfree(intel_crtc);
10225}
10226
6b95a207
KH		 10227static void intel_unpin_work_fn(struct work_struct *__work)
10228{
10229 struct intel_unpin_work *work =
10230 container_of(__work, struct intel_unpin_work, work);
b4a98e57 10231 struct drm_device *dev = work->crtc->dev;
f99d7069 10232 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
6b95a207 10233
b4a98e57 10234 mutex_lock(&dev->struct_mutex);
82bc3b2d 10235 intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state);
05394f39 10236 drm_gem_object_unreference(&work->pending_flip_obj->base);
d9e86c0e 10237
7ff0ebcc 10238 intel_fbc_update(dev);
f06cc1b9
JH		 10239
10240 if (work->flip_queued_req)
146d84f0 10241 i915_gem_request_assign(&work->flip_queued_req, NULL);
b4a98e57
CW		 10242 mutex_unlock(&dev->struct_mutex);
10243
f99d7069 10244 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
89ed88ba 10245 drm_framebuffer_unreference(work->old_fb);
f99d7069 10246
b4a98e57
CW		 10247 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
10248 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
10249
6b95a207
KH		 10250 kfree(work);
10251}
10252
1afe3e9d 10253static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 10254 struct drm_crtc *crtc)
6b95a207 10255{
6b95a207
KH		 10256 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10257 struct intel_unpin_work *work;
6b95a207
KH		 10258 unsigned long flags;
10259
10260 /* Ignore early vblank irqs */
10261 if (intel_crtc == NULL)
10262 return;
10263
f326038a
DV		 10264 /*
10265 * This is called both by irq handlers and the reset code (to complete
10266 * lost pageflips) so needs the full irqsave spinlocks.
10267 */
6b95a207
KH		 10268 spin_lock_irqsave(&dev->event_lock, flags);
10269 work = intel_crtc->unpin_work;
e7d841ca
CW		 10270
10271 /* Ensure we don't miss a work->pending update ... */
10272 smp_rmb();
10273
10274 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 10275 spin_unlock_irqrestore(&dev->event_lock, flags);
10276 return;
10277 }
10278
d6bbafa1 10279 page_flip_completed(intel_crtc);
0af7e4df 10280
6b95a207 10281 spin_unlock_irqrestore(&dev->event_lock, flags);
6b95a207
KH		 10282}
10283
1afe3e9d
JB		 10284void intel_finish_page_flip(struct drm_device *dev, int pipe)
10285{
fbee40df 10286 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10287 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10288
49b14a5c 10289 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10290}
10291
10292void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10293{
fbee40df 10294 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10295 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10296
49b14a5c 10297 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10298}
10299
75f7f3ec
VS		 10300/* Is 'a' after or equal to 'b'? */
10301static bool g4x_flip_count_after_eq(u32 a, u32 b)
10302{
10303 return !((a - b) & 0x80000000);
10304}
10305
10306static bool page_flip_finished(struct intel_crtc *crtc)
10307{
10308 struct drm_device *dev = crtc->base.dev;
10309 struct drm_i915_private *dev_priv = dev->dev_private;
10310
bdfa7542
VS		 10311 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10312 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10313 return true;
10314
75f7f3ec
VS		 10315 /*
10316 * The relevant registers doen't exist on pre-ctg.
10317 * As the flip done interrupt doesn't trigger for mmio
10318 * flips on gmch platforms, a flip count check isn't
10319 * really needed there. But since ctg has the registers,
10320 * include it in the check anyway.
10321 */
10322 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10323 return true;
10324
10325 /*
10326 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10327 * used the same base address. In that case the mmio flip might
10328 * have completed, but the CS hasn't even executed the flip yet.
10329 *
10330 * A flip count check isn't enough as the CS might have updated
10331 * the base address just after start of vblank, but before we
10332 * managed to process the interrupt. This means we'd complete the
10333 * CS flip too soon.
10334 *
10335 * Combining both checks should get us a good enough result. It may
10336 * still happen that the CS flip has been executed, but has not
10337 * yet actually completed. But in case the base address is the same
10338 * anyway, we don't really care.
10339 */
10340 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10341 crtc->unpin_work->gtt_offset &&
10342 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10343 crtc->unpin_work->flip_count);
10344}
10345
6b95a207
KH		 10346void intel_prepare_page_flip(struct drm_device *dev, int plane)
10347{
fbee40df 10348 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 10349 struct intel_crtc *intel_crtc =
10350 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10351 unsigned long flags;
10352
f326038a
DV		 10353
10354 /*
10355 * This is called both by irq handlers and the reset code (to complete
10356 * lost pageflips) so needs the full irqsave spinlocks.
10357 *
10358 * NB: An MMIO update of the plane base pointer will also
e7d841ca
CW		 10359 * generate a page-flip completion irq, i.e. every modeset
10360 * is also accompanied by a spurious intel_prepare_page_flip().
10361 */
6b95a207 10362 spin_lock_irqsave(&dev->event_lock, flags);
75f7f3ec 10363 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
e7d841ca 10364 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 10365 spin_unlock_irqrestore(&dev->event_lock, flags);
10366}
10367
eba905b2 10368static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
e7d841ca
CW		 10369{
10370 /* Ensure that the work item is consistent when activating it ... */
10371 smp_wmb();
10372 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10373 /* and that it is marked active as soon as the irq could fire. */
10374 smp_wmb();
10375}
10376
8c9f3aaf
JB		 10377static int intel_gen2_queue_flip(struct drm_device *dev,
10378 struct drm_crtc *crtc,
10379 struct drm_framebuffer *fb,
ed8d1975 10380 struct drm_i915_gem_object *obj,
a4872ba6 10381 struct intel_engine_cs *ring,
ed8d1975 10382 uint32_t flags)
8c9f3aaf 10383{
8c9f3aaf 10384 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10385 u32 flip_mask;
10386 int ret;
10387
6d90c952 10388 ret = intel_ring_begin(ring, 6);
8c9f3aaf 10389 if (ret)
4fa62c89 10390 return ret;
8c9f3aaf
JB		 10391
10392 /* Can't queue multiple flips, so wait for the previous
10393 * one to finish before executing the next.
10394 */
10395 if (intel_crtc->plane)
10396 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10397 else
10398 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10399 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10400 intel_ring_emit(ring, MI_NOOP);
10401 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10402 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10403 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10404 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952 10405 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 10406
10407 intel_mark_page_flip_active(intel_crtc);
09246732 10408 __intel_ring_advance(ring);
83d4092b 10409 return 0;
8c9f3aaf
JB		 10410}
10411
10412static int intel_gen3_queue_flip(struct drm_device *dev,
10413 struct drm_crtc *crtc,
10414 struct drm_framebuffer *fb,
ed8d1975 10415 struct drm_i915_gem_object *obj,
a4872ba6 10416 struct intel_engine_cs *ring,
ed8d1975 10417 uint32_t flags)
8c9f3aaf 10418{
8c9f3aaf 10419 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10420 u32 flip_mask;
10421 int ret;
10422
6d90c952 10423 ret = intel_ring_begin(ring, 6);
8c9f3aaf 10424 if (ret)
4fa62c89 10425 return ret;
8c9f3aaf
JB		 10426
10427 if (intel_crtc->plane)
10428 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10429 else
10430 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10431 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10432 intel_ring_emit(ring, MI_NOOP);
10433 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10434 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10435 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10436 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952
DV		 10437 intel_ring_emit(ring, MI_NOOP);
10438
e7d841ca 10439 intel_mark_page_flip_active(intel_crtc);
09246732 10440 __intel_ring_advance(ring);
83d4092b 10441 return 0;
8c9f3aaf
JB		 10442}
10443
10444static int intel_gen4_queue_flip(struct drm_device *dev,
10445 struct drm_crtc *crtc,
10446 struct drm_framebuffer *fb,
ed8d1975 10447 struct drm_i915_gem_object *obj,
a4872ba6 10448 struct intel_engine_cs *ring,
ed8d1975 10449 uint32_t flags)
8c9f3aaf
JB		 10450{
10451 struct drm_i915_private *dev_priv = dev->dev_private;
10452 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10453 uint32_t pf, pipesrc;
10454 int ret;
10455
6d90c952 10456 ret = intel_ring_begin(ring, 4);
8c9f3aaf 10457 if (ret)
4fa62c89 10458 return ret;
8c9f3aaf
JB		 10459
10460 /* i965+ uses the linear or tiled offsets from the
10461 * Display Registers (which do not change across a page-flip)
10462 * so we need only reprogram the base address.
10463 */
6d90c952
DV		 10464 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10465 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10466 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10467 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
c2c75131 10468 obj->tiling_mode);
8c9f3aaf
JB		 10469
10470 /* XXX Enabling the panel-fitter across page-flip is so far
10471 * untested on non-native modes, so ignore it for now.
10472 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10473 */
10474 pf = 0;
10475 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10476 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 10477
10478 intel_mark_page_flip_active(intel_crtc);
09246732 10479 __intel_ring_advance(ring);
83d4092b 10480 return 0;
8c9f3aaf
JB		 10481}
10482
10483static int intel_gen6_queue_flip(struct drm_device *dev,
10484 struct drm_crtc *crtc,
10485 struct drm_framebuffer *fb,
ed8d1975 10486 struct drm_i915_gem_object *obj,
a4872ba6 10487 struct intel_engine_cs *ring,
ed8d1975 10488 uint32_t flags)
8c9f3aaf
JB		 10489{
10490 struct drm_i915_private *dev_priv = dev->dev_private;
10491 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10492 uint32_t pf, pipesrc;
10493 int ret;
10494
6d90c952 10495 ret = intel_ring_begin(ring, 4);
8c9f3aaf 10496 if (ret)
4fa62c89 10497 return ret;
8c9f3aaf 10498
6d90c952
DV		 10499 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10500 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10501 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
75f7f3ec 10502 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
8c9f3aaf 10503
dc257cf1
DV		 10504 /* Contrary to the suggestions in the documentation,
10505 * "Enable Panel Fitter" does not seem to be required when page
10506 * flipping with a non-native mode, and worse causes a normal
10507 * modeset to fail.
10508 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10509 */
10510 pf = 0;
8c9f3aaf 10511 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10512 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 10513
10514 intel_mark_page_flip_active(intel_crtc);
09246732 10515 __intel_ring_advance(ring);
83d4092b 10516 return 0;
8c9f3aaf
JB		 10517}
10518
7c9017e5
JB		 10519static int intel_gen7_queue_flip(struct drm_device *dev,
10520 struct drm_crtc *crtc,
10521 struct drm_framebuffer *fb,
ed8d1975 10522 struct drm_i915_gem_object *obj,
a4872ba6 10523 struct intel_engine_cs *ring,
ed8d1975 10524 uint32_t flags)
7c9017e5 10525{
7c9017e5 10526 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cb05d8de 10527 uint32_t plane_bit = 0;
ffe74d75
CW		 10528 int len, ret;
10529
eba905b2 10530 switch (intel_crtc->plane) {
cb05d8de
DV		 10531 case PLANE_A:
10532 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10533 break;
10534 case PLANE_B:
10535 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10536 break;
10537 case PLANE_C:
10538 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10539 break;
10540 default:
10541 WARN_ONCE(1, "unknown plane in flip command\n");
4fa62c89 10542 return -ENODEV;
cb05d8de
DV		 10543 }
10544
ffe74d75 10545 len = 4;
f476828a 10546 if (ring->id == RCS) {
ffe74d75 10547 len += 6;
f476828a
DL		 10548 /*
10549 * On Gen 8, SRM is now taking an extra dword to accommodate
10550 * 48bits addresses, and we need a NOOP for the batch size to
10551 * stay even.
10552 */
10553 if (IS_GEN8(dev))
10554 len += 2;
10555 }
ffe74d75 10556
f66fab8e
VS		 10557 /*
10558 * BSpec MI_DISPLAY_FLIP for IVB:
10559 * "The full packet must be contained within the same cache line."
10560 *
10561 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
10562 * cacheline, if we ever start emitting more commands before
10563 * the MI_DISPLAY_FLIP we may need to first emit everything else,
10564 * then do the cacheline alignment, and finally emit the
10565 * MI_DISPLAY_FLIP.
10566 */
10567 ret = intel_ring_cacheline_align(ring);
10568 if (ret)
4fa62c89 10569 return ret;
f66fab8e 10570
ffe74d75 10571 ret = intel_ring_begin(ring, len);
7c9017e5 10572 if (ret)
4fa62c89 10573 return ret;
7c9017e5 10574
ffe74d75
CW		 10575 /* Unmask the flip-done completion message. Note that the bspec says that
10576 * we should do this for both the BCS and RCS, and that we must not unmask
10577 * more than one flip event at any time (or ensure that one flip message
10578 * can be sent by waiting for flip-done prior to queueing new flips).
10579 * Experimentation says that BCS works despite DERRMR masking all
10580 * flip-done completion events and that unmasking all planes at once
10581 * for the RCS also doesn't appear to drop events. Setting the DERRMR
10582 * to zero does lead to lockups within MI_DISPLAY_FLIP.
10583 */
10584 if (ring->id == RCS) {
10585 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
10586 intel_ring_emit(ring, DERRMR);
10587 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
10588 DERRMR_PIPEB_PRI_FLIP_DONE |
10589 DERRMR_PIPEC_PRI_FLIP_DONE));
f476828a
DL		 10590 if (IS_GEN8(dev))
10591 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
10592 MI_SRM_LRM_GLOBAL_GTT);
10593 else
10594 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
10595 MI_SRM_LRM_GLOBAL_GTT);
ffe74d75
CW		 10596 intel_ring_emit(ring, DERRMR);
10597 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
f476828a
DL		 10598 if (IS_GEN8(dev)) {
10599 intel_ring_emit(ring, 0);
10600 intel_ring_emit(ring, MI_NOOP);
10601 }
ffe74d75
CW		 10602 }
10603
cb05d8de 10604 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 10605 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
75f7f3ec 10606 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
7c9017e5 10607 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 10608
10609 intel_mark_page_flip_active(intel_crtc);
09246732 10610 __intel_ring_advance(ring);
83d4092b 10611 return 0;
7c9017e5
JB		 10612}
10613
84c33a64
SG		 10614static bool use_mmio_flip(struct intel_engine_cs *ring,
10615 struct drm_i915_gem_object *obj)
10616{
10617 /*
10618 * This is not being used for older platforms, because
10619 * non-availability of flip done interrupt forces us to use
10620 * CS flips. Older platforms derive flip done using some clever
10621 * tricks involving the flip_pending status bits and vblank irqs.
10622 * So using MMIO flips there would disrupt this mechanism.
10623 */
10624
8e09bf83
CW		 10625 if (ring == NULL)
10626 return true;
10627
84c33a64
SG		 10628 if (INTEL_INFO(ring->dev)->gen < 5)
10629 return false;
10630
10631 if (i915.use_mmio_flip < 0)
10632 return false;
10633 else if (i915.use_mmio_flip > 0)
10634 return true;
14bf993e
OM		 10635 else if (i915.enable_execlists)
10636 return true;
84c33a64 10637 else
41c52415 10638 return ring != i915_gem_request_get_ring(obj->last_read_req);
84c33a64
SG		 10639}
10640
ff944564
DL		 10641static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
10642{
10643 struct drm_device *dev = intel_crtc->base.dev;
10644 struct drm_i915_private *dev_priv = dev->dev_private;
10645 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
ff944564
DL		 10646 const enum pipe pipe = intel_crtc->pipe;
10647 u32 ctl, stride;
10648
10649 ctl = I915_READ(PLANE_CTL(pipe, 0));
10650 ctl &= ~PLANE_CTL_TILED_MASK;
2ebef630
TU		 10651 switch (fb->modifier[0]) {
10652 case DRM_FORMAT_MOD_NONE:
10653 break;
10654 case I915_FORMAT_MOD_X_TILED:
ff944564 10655 ctl |= PLANE_CTL_TILED_X;
2ebef630
TU		 10656 break;
10657 case I915_FORMAT_MOD_Y_TILED:
10658 ctl |= PLANE_CTL_TILED_Y;
10659 break;
10660 case I915_FORMAT_MOD_Yf_TILED:
10661 ctl |= PLANE_CTL_TILED_YF;
10662 break;
10663 default:
10664 MISSING_CASE(fb->modifier[0]);
10665 }
ff944564
DL		 10666
10667 /*
10668 * The stride is either expressed as a multiple of 64 bytes chunks for
10669 * linear buffers or in number of tiles for tiled buffers.
10670 */
2ebef630
TU		 10671 stride = fb->pitches[0] /
10672 intel_fb_stride_alignment(dev, fb->modifier[0],
10673 fb->pixel_format);
ff944564
DL		 10674
10675 /*
10676 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
10677 * PLANE_SURF updates, the update is then guaranteed to be atomic.
10678 */
10679 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
10680 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
10681
10682 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
10683 POSTING_READ(PLANE_SURF(pipe, 0));
10684}
10685
10686static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
84c33a64
SG		 10687{
10688 struct drm_device *dev = intel_crtc->base.dev;
10689 struct drm_i915_private *dev_priv = dev->dev_private;
10690 struct intel_framebuffer *intel_fb =
10691 to_intel_framebuffer(intel_crtc->base.primary->fb);
10692 struct drm_i915_gem_object *obj = intel_fb->obj;
10693 u32 dspcntr;
10694 u32 reg;
10695
84c33a64
SG		 10696 reg = DSPCNTR(intel_crtc->plane);
10697 dspcntr = I915_READ(reg);
10698
c5d97472
DL		 10699 if (obj->tiling_mode != I915_TILING_NONE)
10700 dspcntr |= DISPPLANE_TILED;
10701 else
10702 dspcntr &= ~DISPPLANE_TILED;
10703
84c33a64
SG		 10704 I915_WRITE(reg, dspcntr);
10705
10706 I915_WRITE(DSPSURF(intel_crtc->plane),
10707 intel_crtc->unpin_work->gtt_offset);
10708 POSTING_READ(DSPSURF(intel_crtc->plane));
84c33a64 10709
ff944564
DL		 10710}
10711
10712/*
10713 * XXX: This is the temporary way to update the plane registers until we get
10714 * around to using the usual plane update functions for MMIO flips
10715 */
10716static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
10717{
10718 struct drm_device *dev = intel_crtc->base.dev;
10719 bool atomic_update;
10720 u32 start_vbl_count;
10721
10722 intel_mark_page_flip_active(intel_crtc);
10723
10724 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
10725
10726 if (INTEL_INFO(dev)->gen >= 9)
10727 skl_do_mmio_flip(intel_crtc);
10728 else
10729 /* use_mmio_flip() retricts MMIO flips to ilk+ */
10730 ilk_do_mmio_flip(intel_crtc);
10731
9362c7c5
ACO		 10732 if (atomic_update)
10733 intel_pipe_update_end(intel_crtc, start_vbl_count);
84c33a64
SG		 10734}
10735
9362c7c5 10736static void intel_mmio_flip_work_func(struct work_struct *work)
84c33a64 10737{
cc8c4cc2 10738 struct intel_crtc *crtc =
9362c7c5 10739 container_of(work, struct intel_crtc, mmio_flip.work);
cc8c4cc2 10740 struct intel_mmio_flip *mmio_flip;
84c33a64 10741
cc8c4cc2
JH		 10742 mmio_flip = &crtc->mmio_flip;
10743 if (mmio_flip->req)
9c654818
JH		 10744 WARN_ON(__i915_wait_request(mmio_flip->req,
10745 crtc->reset_counter,
10746 false, NULL, NULL) != 0);
84c33a64 10747
cc8c4cc2
JH		 10748 intel_do_mmio_flip(crtc);
10749 if (mmio_flip->req) {
10750 mutex_lock(&crtc->base.dev->struct_mutex);
146d84f0 10751 i915_gem_request_assign(&mmio_flip->req, NULL);
cc8c4cc2
JH		 10752 mutex_unlock(&crtc->base.dev->struct_mutex);
10753 }
84c33a64
SG		 10754}
10755
10756static int intel_queue_mmio_flip(struct drm_device *dev,
10757 struct drm_crtc *crtc,
10758 struct drm_framebuffer *fb,
10759 struct drm_i915_gem_object *obj,
10760 struct intel_engine_cs *ring,
10761 uint32_t flags)
10762{
84c33a64 10763 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
84c33a64 10764
cc8c4cc2
JH		 10765 i915_gem_request_assign(&intel_crtc->mmio_flip.req,
10766 obj->last_write_req);
536f5b5e
ACO		 10767
10768 schedule_work(&intel_crtc->mmio_flip.work);
84c33a64 10769
84c33a64
SG		 10770 return 0;
10771}
10772
8c9f3aaf
JB		 10773static int intel_default_queue_flip(struct drm_device *dev,
10774 struct drm_crtc *crtc,
10775 struct drm_framebuffer *fb,
ed8d1975 10776 struct drm_i915_gem_object *obj,
a4872ba6 10777 struct intel_engine_cs *ring,
ed8d1975 10778 uint32_t flags)
8c9f3aaf
JB		 10779{
10780 return -ENODEV;
10781}
10782
d6bbafa1
CW		 10783static bool __intel_pageflip_stall_check(struct drm_device *dev,
10784 struct drm_crtc *crtc)
10785{
10786 struct drm_i915_private *dev_priv = dev->dev_private;
10787 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10788 struct intel_unpin_work *work = intel_crtc->unpin_work;
10789 u32 addr;
10790
10791 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
10792 return true;
10793
10794 if (!work->enable_stall_check)
10795 return false;
10796
10797 if (work->flip_ready_vblank == 0) {
3a8a946e
DV		 10798 if (work->flip_queued_req &&
10799 !i915_gem_request_completed(work->flip_queued_req, true))
d6bbafa1
CW		 10800 return false;
10801
1e3feefd 10802 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1
CW		 10803 }
10804
1e3feefd 10805 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
d6bbafa1
CW		 10806 return false;
10807
10808 /* Potential stall - if we see that the flip has happened,
10809 * assume a missed interrupt. */
10810 if (INTEL_INFO(dev)->gen >= 4)
10811 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
10812 else
10813 addr = I915_READ(DSPADDR(intel_crtc->plane));
10814
10815 /* There is a potential issue here with a false positive after a flip
10816 * to the same address. We could address this by checking for a
10817 * non-incrementing frame counter.
10818 */
10819 return addr == work->gtt_offset;
10820}
10821
10822void intel_check_page_flip(struct drm_device *dev, int pipe)
10823{
10824 struct drm_i915_private *dev_priv = dev->dev_private;
10825 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10826 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6ad790c0 10827 struct intel_unpin_work *work;
f326038a 10828
6c51d46f 10829 WARN_ON(!in_interrupt());
d6bbafa1
CW		 10830
10831 if (crtc == NULL)
10832 return;
10833
f326038a 10834 spin_lock(&dev->event_lock);
6ad790c0
CW		 10835 work = intel_crtc->unpin_work;
10836 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
d6bbafa1 10837 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
6ad790c0 10838 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
d6bbafa1 10839 page_flip_completed(intel_crtc);
6ad790c0 10840 work = NULL;
d6bbafa1 10841 }
6ad790c0
CW		 10842 if (work != NULL &&
10843 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
10844 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
f326038a 10845 spin_unlock(&dev->event_lock);
d6bbafa1
CW		 10846}
10847
6b95a207
KH		 10848static int intel_crtc_page_flip(struct drm_crtc *crtc,
10849 struct drm_framebuffer *fb,
ed8d1975
KP		 10850 struct drm_pending_vblank_event *event,
10851 uint32_t page_flip_flags)
6b95a207
KH		 10852{
10853 struct drm_device *dev = crtc->dev;
10854 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 10855 struct drm_framebuffer *old_fb = crtc->primary->fb;
2ff8fde1 10856 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
6b95a207 10857 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
455a6808 10858 struct drm_plane *primary = crtc->primary;
a071fa00 10859 enum pipe pipe = intel_crtc->pipe;
6b95a207 10860 struct intel_unpin_work *work;
a4872ba6 10861 struct intel_engine_cs *ring;
cf5d8a46 10862 bool mmio_flip;
52e68630 10863 int ret;
6b95a207 10864
2ff8fde1
MR		 10865 /*
10866 * drm_mode_page_flip_ioctl() should already catch this, but double
10867 * check to be safe. In the future we may enable pageflipping from
10868 * a disabled primary plane.
10869 */
10870 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
10871 return -EBUSY;
10872
e6a595d2 10873 /* Can't change pixel format via MI display flips. */
f4510a27 10874 if (fb->pixel_format != crtc->primary->fb->pixel_format)
e6a595d2
VS		 10875 return -EINVAL;
10876
10877 /*
10878 * TILEOFF/LINOFF registers can't be changed via MI display flips.
10879 * Note that pitch changes could also affect these register.
10880 */
10881 if (INTEL_INFO(dev)->gen > 3 &&
f4510a27
MR		 10882 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
10883 fb->pitches[0] != crtc->primary->fb->pitches[0]))
e6a595d2
VS		 10884 return -EINVAL;
10885
f900db47
CW		 10886 if (i915_terminally_wedged(&dev_priv->gpu_error))
10887 goto out_hang;
10888
b14c5679 10889 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH		 10890 if (work == NULL)
10891 return -ENOMEM;
10892
6b95a207 10893 work->event = event;
b4a98e57 10894 work->crtc = crtc;
ab8d6675 10895 work->old_fb = old_fb;
6b95a207
KH		 10896 INIT_WORK(&work->work, intel_unpin_work_fn);
10897
87b6b101 10898 ret = drm_crtc_vblank_get(crtc);
7317c75e
JB		 10899 if (ret)
10900 goto free_work;
10901
6b95a207 10902 /* We borrow the event spin lock for protecting unpin_work */
5e2d7afc 10903 spin_lock_irq(&dev->event_lock);
6b95a207 10904 if (intel_crtc->unpin_work) {
d6bbafa1
CW		 10905 /* Before declaring the flip queue wedged, check if
10906 * the hardware completed the operation behind our backs.
10907 */
10908 if (__intel_pageflip_stall_check(dev, crtc)) {
10909 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
10910 page_flip_completed(intel_crtc);
10911 } else {
10912 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5e2d7afc 10913 spin_unlock_irq(&dev->event_lock);
468f0b44 10914
d6bbafa1
CW		 10915 drm_crtc_vblank_put(crtc);
10916 kfree(work);
10917 return -EBUSY;
10918 }
6b95a207
KH		 10919 }
10920 intel_crtc->unpin_work = work;
5e2d7afc 10921 spin_unlock_irq(&dev->event_lock);
6b95a207 10922
b4a98e57
CW		 10923 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
10924 flush_workqueue(dev_priv->wq);
10925
75dfca80 10926 /* Reference the objects for the scheduled work. */
ab8d6675 10927 drm_framebuffer_reference(work->old_fb);
05394f39 10928 drm_gem_object_reference(&obj->base);
6b95a207 10929
f4510a27 10930 crtc->primary->fb = fb;
afd65eb4 10931 update_state_fb(crtc->primary);
1ed1f968 10932
e1f99ce6 10933 work->pending_flip_obj = obj;
e1f99ce6 10934
89ed88ba
CW		 10935 ret = i915_mutex_lock_interruptible(dev);
10936 if (ret)
10937 goto cleanup;
10938
b4a98e57 10939 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 10940 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 10941
75f7f3ec 10942 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
a071fa00 10943 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
75f7f3ec 10944
4fa62c89
VS		 10945 if (IS_VALLEYVIEW(dev)) {
10946 ring = &dev_priv->ring[BCS];
ab8d6675 10947 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
8e09bf83
CW		 10948 /* vlv: DISPLAY_FLIP fails to change tiling */
10949 ring = NULL;
48bf5b2d 10950 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
2a92d5bc 10951 ring = &dev_priv->ring[BCS];
4fa62c89 10952 } else if (INTEL_INFO(dev)->gen >= 7) {
41c52415 10953 ring = i915_gem_request_get_ring(obj->last_read_req);
4fa62c89
VS		 10954 if (ring == NULL || ring->id != RCS)
10955 ring = &dev_priv->ring[BCS];
10956 } else {
10957 ring = &dev_priv->ring[RCS];
10958 }
10959
cf5d8a46
CW		 10960 mmio_flip = use_mmio_flip(ring, obj);
10961
10962 /* When using CS flips, we want to emit semaphores between rings.
10963 * However, when using mmio flips we will create a task to do the
10964 * synchronisation, so all we want here is to pin the framebuffer
10965 * into the display plane and skip any waits.
10966 */
82bc3b2d 10967 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
cf5d8a46
CW		 10968 crtc->primary->state,
10969 mmio_flip ? i915_gem_request_get_ring(obj->last_read_req) : ring);
8c9f3aaf
JB		 10970 if (ret)
10971 goto cleanup_pending;
6b95a207 10972
121920fa
TU		 10973 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
10974 + intel_crtc->dspaddr_offset;
4fa62c89 10975
cf5d8a46 10976 if (mmio_flip) {
84c33a64
SG		 10977 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
10978 page_flip_flags);
d6bbafa1
CW		 10979 if (ret)
10980 goto cleanup_unpin;
10981
f06cc1b9
JH		 10982 i915_gem_request_assign(&work->flip_queued_req,
10983 obj->last_write_req);
d6bbafa1 10984 } else {
84c33a64 10985 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
d6bbafa1
CW		 10986 page_flip_flags);
10987 if (ret)
10988 goto cleanup_unpin;
10989
f06cc1b9
JH		 10990 i915_gem_request_assign(&work->flip_queued_req,
10991 intel_ring_get_request(ring));
d6bbafa1
CW		 10992 }
10993
1e3feefd 10994 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1 10995 work->enable_stall_check = true;
4fa62c89 10996
ab8d6675 10997 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
a071fa00
DV		 10998 INTEL_FRONTBUFFER_PRIMARY(pipe));
10999
7ff0ebcc 11000 intel_fbc_disable(dev);
f99d7069 11001 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
6b95a207
KH		 11002 mutex_unlock(&dev->struct_mutex);
11003
e5510fac
JB		 11004 trace_i915_flip_request(intel_crtc->plane, obj);
11005
6b95a207 11006 return 0;
96b099fd 11007
4fa62c89 11008cleanup_unpin:
82bc3b2d 11009 intel_unpin_fb_obj(fb, crtc->primary->state);
8c9f3aaf 11010cleanup_pending:
b4a98e57 11011 atomic_dec(&intel_crtc->unpin_work_count);
89ed88ba
CW		 11012 mutex_unlock(&dev->struct_mutex);
11013cleanup:
f4510a27 11014 crtc->primary->fb = old_fb;
afd65eb4 11015 update_state_fb(crtc->primary);
89ed88ba
CW		 11016
11017 drm_gem_object_unreference_unlocked(&obj->base);
ab8d6675 11018 drm_framebuffer_unreference(work->old_fb);
96b099fd 11019
5e2d7afc 11020 spin_lock_irq(&dev->event_lock);
96b099fd 11021 intel_crtc->unpin_work = NULL;
5e2d7afc 11022 spin_unlock_irq(&dev->event_lock);
96b099fd 11023
87b6b101 11024 drm_crtc_vblank_put(crtc);
7317c75e 11025free_work:
96b099fd
CW		 11026 kfree(work);
11027
f900db47
CW		 11028 if (ret == -EIO) {
11029out_hang:
53a366b9 11030 ret = intel_plane_restore(primary);
f0d3dad3 11031 if (ret == 0 && event) {
5e2d7afc 11032 spin_lock_irq(&dev->event_lock);
a071fa00 11033 drm_send_vblank_event(dev, pipe, event);
5e2d7afc 11034 spin_unlock_irq(&dev->event_lock);
f0d3dad3 11035 }
f900db47 11036 }
96b099fd 11037 return ret;
6b95a207
KH		 11038}
11039
65b38e0d 11040static const struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 11041 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11042 .load_lut = intel_crtc_load_lut,
ea2c67bb
MR		 11043 .atomic_begin = intel_begin_crtc_commit,
11044 .atomic_flush = intel_finish_crtc_commit,
f6e5b160
CW		 11045};
11046
9a935856
DV		 11047/**
11048 * intel_modeset_update_staged_output_state
11049 *
11050 * Updates the staged output configuration state, e.g. after we've read out the
11051 * current hw state.
11052 */
11053static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 11054{
7668851f 11055 struct intel_crtc *crtc;
9a935856
DV		 11056 struct intel_encoder *encoder;
11057 struct intel_connector *connector;
f6e5b160 11058
3a3371ff 11059 for_each_intel_connector(dev, connector) {
9a935856
DV		 11060 connector->new_encoder =
11061 to_intel_encoder(connector->base.encoder);
11062 }
f6e5b160 11063
b2784e15 11064 for_each_intel_encoder(dev, encoder) {
9a935856
DV		 11065 encoder->new_crtc =
11066 to_intel_crtc(encoder->base.crtc);
11067 }
7668851f 11068
d3fcc808 11069 for_each_intel_crtc(dev, crtc) {
83d65738 11070 crtc->new_enabled = crtc->base.state->enable;
7668851f 11071 }
f6e5b160
CW		 11072}
11073
d29b2f9d
ACO		 11074/* Transitional helper to copy current connector/encoder state to
11075 * connector->state. This is needed so that code that is partially
11076 * converted to atomic does the right thing.
11077 */
11078static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11079{
11080 struct intel_connector *connector;
11081
11082 for_each_intel_connector(dev, connector) {
11083 if (connector->base.encoder) {
11084 connector->base.state->best_encoder =
11085 connector->base.encoder;
11086 connector->base.state->crtc =
11087 connector->base.encoder->crtc;
11088 } else {
11089 connector->base.state->best_encoder = NULL;
11090 connector->base.state->crtc = NULL;
11091 }
11092 }
11093}
11094
9a935856
DV		 11095/**
11096 * intel_modeset_commit_output_state
11097 *
11098 * This function copies the stage display pipe configuration to the real one.
11099 */
11100static void intel_modeset_commit_output_state(struct drm_device *dev)
11101{
7668851f 11102 struct intel_crtc *crtc;
9a935856
DV		 11103 struct intel_encoder *encoder;
11104 struct intel_connector *connector;
f6e5b160 11105
3a3371ff 11106 for_each_intel_connector(dev, connector) {
9a935856
DV		 11107 connector->base.encoder = &connector->new_encoder->base;
11108 }
f6e5b160 11109
b2784e15 11110 for_each_intel_encoder(dev, encoder) {
9a935856
DV		 11111 encoder->base.crtc = &encoder->new_crtc->base;
11112 }
7668851f 11113
d3fcc808 11114 for_each_intel_crtc(dev, crtc) {
83d65738 11115 crtc->base.state->enable = crtc->new_enabled;
7668851f
VS		 11116 crtc->base.enabled = crtc->new_enabled;
11117 }
d29b2f9d
ACO		 11118
11119 intel_modeset_update_connector_atomic_state(dev);
9a935856
DV		 11120}
11121
050f7aeb 11122static void
eba905b2 11123connected_sink_compute_bpp(struct intel_connector *connector,
5cec258b 11124 struct intel_crtc_state *pipe_config)
050f7aeb
DV		 11125{
11126 int bpp = pipe_config->pipe_bpp;
11127
11128 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11129 connector->base.base.id,
c23cc417 11130 connector->base.name);
050f7aeb
DV		 11131
11132 /* Don't use an invalid EDID bpc value */
11133 if (connector->base.display_info.bpc &&
11134 connector->base.display_info.bpc * 3 < bpp) {
11135 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11136 bpp, connector->base.display_info.bpc*3);
11137 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11138 }
11139
11140 /* Clamp bpp to 8 on screens without EDID 1.4 */
11141 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11142 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11143 bpp);
11144 pipe_config->pipe_bpp = 24;
11145 }
11146}
11147
4e53c2e0 11148static int
050f7aeb 11149compute_baseline_pipe_bpp(struct intel_crtc *crtc,
5cec258b 11150 struct intel_crtc_state *pipe_config)
4e53c2e0 11151{
050f7aeb 11152 struct drm_device *dev = crtc->base.dev;
1486017f 11153 struct drm_atomic_state *state;
050f7aeb 11154 struct intel_connector *connector;
1486017f 11155 int bpp, i;
4e53c2e0 11156
d328c9d7 11157 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
4e53c2e0 11158 bpp = 10*3;
d328c9d7
DV		 11159 else if (INTEL_INFO(dev)->gen >= 5)
11160 bpp = 12*3;
11161 else
11162 bpp = 8*3;
11163
4e53c2e0 11164
4e53c2e0
DV		 11165 pipe_config->pipe_bpp = bpp;
11166
1486017f
ACO		 11167 state = pipe_config->base.state;
11168
4e53c2e0 11169 /* Clamp display bpp to EDID value */
1486017f
ACO		 11170 for (i = 0; i < state->num_connector; i++) {
11171 if (!state->connectors[i])
11172 continue;
11173
11174 connector = to_intel_connector(state->connectors[i]);
11175 if (state->connector_states[i]->crtc != &crtc->base)
4e53c2e0
DV		 11176 continue;
11177
050f7aeb 11178 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV		 11179 }
11180
11181 return bpp;
11182}
11183
644db711
DV		 11184static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11185{
11186 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11187 "type: 0x%x flags: 0x%x\n",
1342830c 11188 mode->crtc_clock,
644db711
DV		 11189 mode->crtc_hdisplay, mode->crtc_hsync_start,
11190 mode->crtc_hsync_end, mode->crtc_htotal,
11191 mode->crtc_vdisplay, mode->crtc_vsync_start,
11192 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11193}
11194
c0b03411 11195static void intel_dump_pipe_config(struct intel_crtc *crtc,
5cec258b 11196 struct intel_crtc_state *pipe_config,
c0b03411
DV		 11197 const char *context)
11198{
6a60cd87
CK		 11199 struct drm_device *dev = crtc->base.dev;
11200 struct drm_plane *plane;
11201 struct intel_plane *intel_plane;
11202 struct intel_plane_state *state;
11203 struct drm_framebuffer *fb;
11204
11205 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11206 context, pipe_config, pipe_name(crtc->pipe));
c0b03411
DV		 11207
11208 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11209 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11210 pipe_config->pipe_bpp, pipe_config->dither);
11211 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11212 pipe_config->has_pch_encoder,
11213 pipe_config->fdi_lanes,
11214 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11215 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11216 pipe_config->fdi_m_n.tu);
eb14cb74
VS		 11217 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11218 pipe_config->has_dp_encoder,
11219 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11220 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11221 pipe_config->dp_m_n.tu);
b95af8be
VK		 11222
11223 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11224 pipe_config->has_dp_encoder,
11225 pipe_config->dp_m2_n2.gmch_m,
11226 pipe_config->dp_m2_n2.gmch_n,
11227 pipe_config->dp_m2_n2.link_m,
11228 pipe_config->dp_m2_n2.link_n,
11229 pipe_config->dp_m2_n2.tu);
11230
55072d19
DV		 11231 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11232 pipe_config->has_audio,
11233 pipe_config->has_infoframe);
11234
c0b03411 11235 DRM_DEBUG_KMS("requested mode:\n");
2d112de7 11236 drm_mode_debug_printmodeline(&pipe_config->base.mode);
c0b03411 11237 DRM_DEBUG_KMS("adjusted mode:\n");
2d112de7
ACO		 11238 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11239 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
d71b8d4a 11240 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 11241 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11242 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
6a60cd87
CK		 11243 DRM_DEBUG_KMS("num_scalers: %d\n", crtc->num_scalers);
11244 DRM_DEBUG_KMS("scaler_users: 0x%x\n", pipe_config->scaler_state.scaler_users);
11245 DRM_DEBUG_KMS("scaler id: %d\n", pipe_config->scaler_state.scaler_id);
c0b03411
DV		 11246 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11247 pipe_config->gmch_pfit.control,
11248 pipe_config->gmch_pfit.pgm_ratios,
11249 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 11250 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 11251 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 11252 pipe_config->pch_pfit.size,
11253 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 11254 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 11255 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
6a60cd87
CK		 11256
11257 DRM_DEBUG_KMS("planes on this crtc\n");
11258 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11259 intel_plane = to_intel_plane(plane);
11260 if (intel_plane->pipe != crtc->pipe)
11261 continue;
11262
11263 state = to_intel_plane_state(plane->state);
11264 fb = state->base.fb;
11265 if (!fb) {
11266 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11267 "disabled, scaler_id = %d\n",
11268 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11269 plane->base.id, intel_plane->pipe,
11270 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
11271 drm_plane_index(plane), state->scaler_id);
11272 continue;
11273 }
11274
11275 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
11276 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11277 plane->base.id, intel_plane->pipe,
11278 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
11279 drm_plane_index(plane));
11280 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
11281 fb->base.id, fb->width, fb->height, fb->pixel_format);
11282 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
11283 state->scaler_id,
11284 state->src.x1 >> 16, state->src.y1 >> 16,
11285 drm_rect_width(&state->src) >> 16,
11286 drm_rect_height(&state->src) >> 16,
11287 state->dst.x1, state->dst.y1,
11288 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
11289 }
c0b03411
DV		 11290}
11291
bc079e8b
VS		 11292static bool encoders_cloneable(const struct intel_encoder *a,
11293 const struct intel_encoder *b)
accfc0c5 11294{
bc079e8b
VS		 11295 /* masks could be asymmetric, so check both ways */
11296 return a == b || (a->cloneable & (1 << b->type) &&
11297 b->cloneable & (1 << a->type));
11298}
11299
98a221da
ACO		 11300static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11301 struct intel_crtc *crtc,
bc079e8b
VS		 11302 struct intel_encoder *encoder)
11303{
bc079e8b 11304 struct intel_encoder *source_encoder;
98a221da
ACO		 11305 struct drm_connector_state *connector_state;
11306 int i;
bc079e8b 11307
98a221da
ACO		 11308 for (i = 0; i < state->num_connector; i++) {
11309 if (!state->connectors[i])
11310 continue;
bc079e8b 11311
98a221da
ACO		 11312 connector_state = state->connector_states[i];
11313 if (connector_state->crtc != &crtc->base)
bc079e8b
VS		 11314 continue;
11315
98a221da
ACO		 11316 source_encoder =
11317 to_intel_encoder(connector_state->best_encoder);
bc079e8b
VS		 11318 if (!encoders_cloneable(encoder, source_encoder))
11319 return false;
11320 }
11321
11322 return true;
11323}
11324
98a221da
ACO		 11325static bool check_encoder_cloning(struct drm_atomic_state *state,
11326 struct intel_crtc *crtc)
bc079e8b 11327{
accfc0c5 11328 struct intel_encoder *encoder;
98a221da
ACO		 11329 struct drm_connector_state *connector_state;
11330 int i;
accfc0c5 11331
98a221da
ACO		 11332 for (i = 0; i < state->num_connector; i++) {
11333 if (!state->connectors[i])
accfc0c5
DV		 11334 continue;
11335
98a221da
ACO		 11336 connector_state = state->connector_states[i];
11337 if (connector_state->crtc != &crtc->base)
11338 continue;
11339
11340 encoder = to_intel_encoder(connector_state->best_encoder);
11341 if (!check_single_encoder_cloning(state, crtc, encoder))
bc079e8b 11342 return false;
accfc0c5
DV		 11343 }
11344
bc079e8b 11345 return true;
accfc0c5
DV		 11346}
11347
5448a00d 11348static bool check_digital_port_conflicts(struct drm_atomic_state *state)
00f0b378 11349{
5448a00d
ACO		 11350 struct drm_device *dev = state->dev;
11351 struct intel_encoder *encoder;
11352 struct drm_connector_state *connector_state;
00f0b378 11353 unsigned int used_ports = 0;
5448a00d 11354 int i;
00f0b378
VS		 11355
11356 /*
11357 * Walk the connector list instead of the encoder
11358 * list to detect the problem on ddi platforms
11359 * where there's just one encoder per digital port.
11360 */
5448a00d
ACO		 11361 for (i = 0; i < state->num_connector; i++) {
11362 if (!state->connectors[i])
11363 continue;
00f0b378 11364
5448a00d
ACO		 11365 connector_state = state->connector_states[i];
11366 if (!connector_state->best_encoder)
00f0b378
VS		 11367 continue;
11368
5448a00d
ACO		 11369 encoder = to_intel_encoder(connector_state->best_encoder);
11370
11371 WARN_ON(!connector_state->crtc);
00f0b378
VS		 11372
11373 switch (encoder->type) {
11374 unsigned int port_mask;
11375 case INTEL_OUTPUT_UNKNOWN:
11376 if (WARN_ON(!HAS_DDI(dev)))
11377 break;
11378 case INTEL_OUTPUT_DISPLAYPORT:
11379 case INTEL_OUTPUT_HDMI:
11380 case INTEL_OUTPUT_EDP:
11381 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
11382
11383 /* the same port mustn't appear more than once */
11384 if (used_ports & port_mask)
11385 return false;
11386
11387 used_ports |= port_mask;
11388 default:
11389 break;
11390 }
11391 }
11392
11393 return true;
11394}
11395
83a57153
ACO		 11396static void
11397clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
11398{
11399 struct drm_crtc_state tmp_state;
663a3640 11400 struct intel_crtc_scaler_state scaler_state;
83a57153 11401
663a3640 11402 /* Clear only the intel specific part of the crtc state excluding scalers */
83a57153 11403 tmp_state = crtc_state->base;
663a3640 11404 scaler_state = crtc_state->scaler_state;
83a57153
ACO		 11405 memset(crtc_state, 0, sizeof *crtc_state);
11406 crtc_state->base = tmp_state;
663a3640 11407 crtc_state->scaler_state = scaler_state;
83a57153
ACO		 11408}
11409
5cec258b 11410static struct intel_crtc_state *
b8cecdf5 11411intel_modeset_pipe_config(struct drm_crtc *crtc,
83a57153
ACO		 11412 struct drm_display_mode *mode,
11413 struct drm_atomic_state *state)
ee7b9f93 11414{
7758a113 11415 struct intel_encoder *encoder;
0b901879
ACO		 11416 struct intel_connector *connector;
11417 struct drm_connector_state *connector_state;
5cec258b 11418 struct intel_crtc_state *pipe_config;
d328c9d7 11419 int base_bpp, ret = -EINVAL;
0b901879 11420 int i;
e29c22c0 11421 bool retry = true;
ee7b9f93 11422
98a221da 11423 if (!check_encoder_cloning(state, to_intel_crtc(crtc))) {
accfc0c5
DV		 11424 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11425 return ERR_PTR(-EINVAL);
11426 }
11427
5448a00d 11428 if (!check_digital_port_conflicts(state)) {
00f0b378
VS		 11429 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
11430 return ERR_PTR(-EINVAL);
11431 }
11432
83a57153
ACO		 11433 pipe_config = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
11434 if (IS_ERR(pipe_config))
11435 return pipe_config;
11436
11437 clear_intel_crtc_state(pipe_config);
7758a113 11438
07878248 11439 pipe_config->base.crtc = crtc;
2d112de7
ACO		 11440 drm_mode_copy(&pipe_config->base.adjusted_mode, mode);
11441 drm_mode_copy(&pipe_config->base.mode, mode);
37327abd 11442
e143a21c
DV		 11443 pipe_config->cpu_transcoder =
11444 (enum transcoder) to_intel_crtc(crtc)->pipe;
c0d43d62 11445 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
b8cecdf5 11446
2960bc9c
ID		 11447 /*
11448 * Sanitize sync polarity flags based on requested ones. If neither
11449 * positive or negative polarity is requested, treat this as meaning
11450 * negative polarity.
11451 */
2d112de7 11452 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 11453 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
2d112de7 11454 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
2960bc9c 11455
2d112de7 11456 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 11457 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
2d112de7 11458 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
2960bc9c 11459
050f7aeb
DV		 11460 /* Compute a starting value for pipe_config->pipe_bpp taking the source
11461 * plane pixel format and any sink constraints into account. Returns the
11462 * source plane bpp so that dithering can be selected on mismatches
11463 * after encoders and crtc also have had their say. */
d328c9d7
DV		 11464 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
11465 pipe_config);
11466 if (base_bpp < 0)
4e53c2e0
DV		 11467 goto fail;
11468
e41a56be
VS		 11469 /*
11470 * Determine the real pipe dimensions. Note that stereo modes can
11471 * increase the actual pipe size due to the frame doubling and
11472 * insertion of additional space for blanks between the frame. This
11473 * is stored in the crtc timings. We use the requested mode to do this
11474 * computation to clearly distinguish it from the adjusted mode, which
11475 * can be changed by the connectors in the below retry loop.
11476 */
2d112de7 11477 drm_crtc_get_hv_timing(&pipe_config->base.mode,
ecb7e16b
GP		 11478 &pipe_config->pipe_src_w,
11479 &pipe_config->pipe_src_h);
e41a56be 11480
e29c22c0 11481encoder_retry:
ef1b460d 11482 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 11483 pipe_config->port_clock = 0;
ef1b460d 11484 pipe_config->pixel_multiplier = 1;
ff9a6750 11485
135c81b8 11486 /* Fill in default crtc timings, allow encoders to overwrite them. */
2d112de7
ACO		 11487 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
11488 CRTC_STEREO_DOUBLE);
135c81b8 11489
7758a113
DV		 11490 /* Pass our mode to the connectors and the CRTC to give them a chance to
11491 * adjust it according to limitations or connector properties, and also
11492 * a chance to reject the mode entirely.
47f1c6c9 11493 */
0b901879
ACO		 11494 for (i = 0; i < state->num_connector; i++) {
11495 connector = to_intel_connector(state->connectors[i]);
11496 if (!connector)
11497 continue;
47f1c6c9 11498
0b901879
ACO		 11499 connector_state = state->connector_states[i];
11500 if (connector_state->crtc != crtc)
7758a113 11501 continue;
7ae89233 11502
0b901879
ACO		 11503 encoder = to_intel_encoder(connector_state->best_encoder);
11504
efea6e8e
DV		 11505 if (!(encoder->compute_config(encoder, pipe_config))) {
11506 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 11507 goto fail;
11508 }
ee7b9f93 11509 }
47f1c6c9 11510
ff9a6750
DV		 11511 /* Set default port clock if not overwritten by the encoder. Needs to be
11512 * done afterwards in case the encoder adjusts the mode. */
11513 if (!pipe_config->port_clock)
2d112de7 11514 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
241bfc38 11515 * pipe_config->pixel_multiplier;
ff9a6750 11516
a43f6e0f 11517 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 11518 if (ret < 0) {
7758a113
DV		 11519 DRM_DEBUG_KMS("CRTC fixup failed\n");
11520 goto fail;
ee7b9f93 11521 }
e29c22c0
DV		 11522
11523 if (ret == RETRY) {
11524 if (WARN(!retry, "loop in pipe configuration computation\n")) {
11525 ret = -EINVAL;
11526 goto fail;
11527 }
11528
11529 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11530 retry = false;
11531 goto encoder_retry;
11532 }
11533
d328c9d7 11534 pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
4e53c2e0 11535 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
d328c9d7 11536 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
4e53c2e0 11537
b8cecdf5 11538 return pipe_config;
7758a113 11539fail:
e29c22c0 11540 return ERR_PTR(ret);
ee7b9f93 11541}
47f1c6c9 11542
e2e1ed41
DV		 11543/* Computes which crtcs are affected and sets the relevant bits in the mask. For
11544 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
11545static void
11546intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
11547 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 11548{
11549 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 11550 struct drm_device *dev = crtc->dev;
11551 struct intel_encoder *encoder;
11552 struct intel_connector *connector;
11553 struct drm_crtc *tmp_crtc;
79e53945 11554
e2e1ed41 11555 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 11556
e2e1ed41
DV		 11557 /* Check which crtcs have changed outputs connected to them, these need
11558 * to be part of the prepare_pipes mask. We don't (yet) support global
11559 * modeset across multiple crtcs, so modeset_pipes will only have one
11560 * bit set at most. */
3a3371ff 11561 for_each_intel_connector(dev, connector) {
e2e1ed41
DV		 11562 if (connector->base.encoder == &connector->new_encoder->base)
11563 continue;
79e53945 11564
e2e1ed41
DV		 11565 if (connector->base.encoder) {
11566 tmp_crtc = connector->base.encoder->crtc;
11567
11568 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
11569 }
11570
11571 if (connector->new_encoder)
11572 *prepare_pipes |=
11573 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 11574 }
11575
b2784e15 11576 for_each_intel_encoder(dev, encoder) {
e2e1ed41
DV		 11577 if (encoder->base.crtc == &encoder->new_crtc->base)
11578 continue;
11579
11580 if (encoder->base.crtc) {
11581 tmp_crtc = encoder->base.crtc;
11582
11583 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
11584 }
11585
11586 if (encoder->new_crtc)
11587 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 11588 }
11589
7668851f 11590 /* Check for pipes that will be enabled/disabled ... */
d3fcc808 11591 for_each_intel_crtc(dev, intel_crtc) {
83d65738 11592 if (intel_crtc->base.state->enable == intel_crtc->new_enabled)
e2e1ed41 11593 continue;
7e7d76c3 11594
7668851f 11595 if (!intel_crtc->new_enabled)
e2e1ed41 11596 *disable_pipes |= 1 << intel_crtc->pipe;
7668851f
VS		 11597 else
11598 *prepare_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 11599 }
11600
e2e1ed41
DV		 11601
11602 /* set_mode is also used to update properties on life display pipes. */
11603 intel_crtc = to_intel_crtc(crtc);
7668851f 11604 if (intel_crtc->new_enabled)
e2e1ed41
DV		 11605 *prepare_pipes |= 1 << intel_crtc->pipe;
11606
b6c5164d
DV		 11607 /*
11608 * For simplicity do a full modeset on any pipe where the output routing
11609 * changed. We could be more clever, but that would require us to be
11610 * more careful with calling the relevant encoder->mode_set functions.
11611 */
e2e1ed41
DV		 11612 if (*prepare_pipes)
11613 *modeset_pipes = *prepare_pipes;
11614
11615 /* ... and mask these out. */
11616 *modeset_pipes &= ~(*disable_pipes);
11617 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 11618
11619 /*
11620 * HACK: We don't (yet) fully support global modesets. intel_set_config
11621 * obies this rule, but the modeset restore mode of
11622 * intel_modeset_setup_hw_state does not.
11623 */
11624 *modeset_pipes &= 1 << intel_crtc->pipe;
11625 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 11626
11627 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
11628 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 11629}
79e53945 11630
ea9d758d 11631static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 11632{
ea9d758d 11633 struct drm_encoder *encoder;
f6e5b160 11634 struct drm_device *dev = crtc->dev;
f6e5b160 11635
ea9d758d
DV		 11636 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
11637 if (encoder->crtc == crtc)
11638 return true;
11639
11640 return false;
11641}
11642
11643static void
11644intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
11645{
ba41c0de 11646 struct drm_i915_private *dev_priv = dev->dev_private;
ea9d758d
DV		 11647 struct intel_encoder *intel_encoder;
11648 struct intel_crtc *intel_crtc;
11649 struct drm_connector *connector;
11650
ba41c0de
DV		 11651 intel_shared_dpll_commit(dev_priv);
11652
b2784e15 11653 for_each_intel_encoder(dev, intel_encoder) {
ea9d758d
DV		 11654 if (!intel_encoder->base.crtc)
11655 continue;
11656
11657 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
11658
11659 if (prepare_pipes & (1 << intel_crtc->pipe))
11660 intel_encoder->connectors_active = false;
11661 }
11662
11663 intel_modeset_commit_output_state(dev);
11664
7668851f 11665 /* Double check state. */
d3fcc808 11666 for_each_intel_crtc(dev, intel_crtc) {
83d65738 11667 WARN_ON(intel_crtc->base.state->enable != intel_crtc_in_use(&intel_crtc->base));
ea9d758d
DV		 11668 }
11669
11670 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11671 if (!connector->encoder || !connector->encoder->crtc)
11672 continue;
11673
11674 intel_crtc = to_intel_crtc(connector->encoder->crtc);
11675
11676 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 11677 struct drm_property *dpms_property =
11678 dev->mode_config.dpms_property;
11679
ea9d758d 11680 connector->dpms = DRM_MODE_DPMS_ON;
662595df 11681 drm_object_property_set_value(&connector->base,
68d34720
DV		 11682 dpms_property,
11683 DRM_MODE_DPMS_ON);
ea9d758d
DV		 11684
11685 intel_encoder = to_intel_encoder(connector->encoder);
11686 intel_encoder->connectors_active = true;
11687 }
11688 }
11689
11690}
11691
3bd26263 11692static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 11693{
3bd26263 11694 int diff;
f1f644dc
JB		 11695
11696 if (clock1 == clock2)
11697 return true;
11698
11699 if (!clock1 || !clock2)
11700 return false;
11701
11702 diff = abs(clock1 - clock2);
11703
11704 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11705 return true;
11706
11707 return false;
11708}
11709
25c5b266
DV		 11710#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
11711 list_for_each_entry((intel_crtc), \
11712 &(dev)->mode_config.crtc_list, \
11713 base.head) \
0973f18f 11714 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 11715
0e8ffe1b 11716static bool
2fa2fe9a 11717intel_pipe_config_compare(struct drm_device *dev,
5cec258b
ACO		 11718 struct intel_crtc_state *current_config,
11719 struct intel_crtc_state *pipe_config)
0e8ffe1b 11720{
66e985c0
DV		 11721#define PIPE_CONF_CHECK_X(name) \
11722 if (current_config->name != pipe_config->name) { \
11723 DRM_ERROR("mismatch in " #name " " \
11724 "(expected 0x%08x, found 0x%08x)\n", \
11725 current_config->name, \
11726 pipe_config->name); \
11727 return false; \
11728 }
11729
08a24034
DV		 11730#define PIPE_CONF_CHECK_I(name) \
11731 if (current_config->name != pipe_config->name) { \
11732 DRM_ERROR("mismatch in " #name " " \
11733 "(expected %i, found %i)\n", \
11734 current_config->name, \
11735 pipe_config->name); \
11736 return false; \
88adfff1
DV		 11737 }
11738
b95af8be
VK		 11739/* This is required for BDW+ where there is only one set of registers for
11740 * switching between high and low RR.
11741 * This macro can be used whenever a comparison has to be made between one
11742 * hw state and multiple sw state variables.
11743 */
11744#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
11745 if ((current_config->name != pipe_config->name) && \
11746 (current_config->alt_name != pipe_config->name)) { \
11747 DRM_ERROR("mismatch in " #name " " \
11748 "(expected %i or %i, found %i)\n", \
11749 current_config->name, \
11750 current_config->alt_name, \
11751 pipe_config->name); \
11752 return false; \
11753 }
11754
1bd1bd80
DV		 11755#define PIPE_CONF_CHECK_FLAGS(name, mask) \
11756 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 11757 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 11758 "(expected %i, found %i)\n", \
11759 current_config->name & (mask), \
11760 pipe_config->name & (mask)); \
11761 return false; \
11762 }
11763
5e550656
VS		 11764#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11765 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11766 DRM_ERROR("mismatch in " #name " " \
11767 "(expected %i, found %i)\n", \
11768 current_config->name, \
11769 pipe_config->name); \
11770 return false; \
11771 }
11772
bb760063
DV		 11773#define PIPE_CONF_QUIRK(quirk) \
11774 ((current_config->quirks | pipe_config->quirks) & (quirk))
11775
eccb140b
DV		 11776 PIPE_CONF_CHECK_I(cpu_transcoder);
11777
08a24034
DV		 11778 PIPE_CONF_CHECK_I(has_pch_encoder);
11779 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 11780 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
11781 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
11782 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
11783 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
11784 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 11785
eb14cb74 11786 PIPE_CONF_CHECK_I(has_dp_encoder);
b95af8be
VK		 11787
11788 if (INTEL_INFO(dev)->gen < 8) {
11789 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
11790 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
11791 PIPE_CONF_CHECK_I(dp_m_n.link_m);
11792 PIPE_CONF_CHECK_I(dp_m_n.link_n);
11793 PIPE_CONF_CHECK_I(dp_m_n.tu);
11794
11795 if (current_config->has_drrs) {
11796 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
11797 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
11798 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
11799 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
11800 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
11801 }
11802 } else {
11803 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
11804 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
11805 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
11806 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
11807 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
11808 }
eb14cb74 11809
2d112de7
ACO		 11810 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11811 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11812 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11813 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11814 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11815 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
1bd1bd80 11816
2d112de7
ACO		 11817 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11818 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11819 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11820 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11821 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11822 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
1bd1bd80 11823
c93f54cf 11824 PIPE_CONF_CHECK_I(pixel_multiplier);
6897b4b5 11825 PIPE_CONF_CHECK_I(has_hdmi_sink);
b5a9fa09
DV		 11826 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
11827 IS_VALLEYVIEW(dev))
11828 PIPE_CONF_CHECK_I(limited_color_range);
e43823ec 11829 PIPE_CONF_CHECK_I(has_infoframe);
6c49f241 11830
9ed109a7
DV		 11831 PIPE_CONF_CHECK_I(has_audio);
11832
2d112de7 11833 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
1bd1bd80
DV		 11834 DRM_MODE_FLAG_INTERLACE);
11835
bb760063 11836 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
2d112de7 11837 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 11838 DRM_MODE_FLAG_PHSYNC);
2d112de7 11839 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 11840 DRM_MODE_FLAG_NHSYNC);
2d112de7 11841 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 11842 DRM_MODE_FLAG_PVSYNC);
2d112de7 11843 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063
DV		 11844 DRM_MODE_FLAG_NVSYNC);
11845 }
045ac3b5 11846
37327abd
VS		 11847 PIPE_CONF_CHECK_I(pipe_src_w);
11848 PIPE_CONF_CHECK_I(pipe_src_h);
1bd1bd80 11849
9953599b
DV		 11850 /*
11851 * FIXME: BIOS likes to set up a cloned config with lvds+external
11852 * screen. Since we don't yet re-compute the pipe config when moving
11853 * just the lvds port away to another pipe the sw tracking won't match.
11854 *
11855 * Proper atomic modesets with recomputed global state will fix this.
11856 * Until then just don't check gmch state for inherited modes.
11857 */
11858 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
11859 PIPE_CONF_CHECK_I(gmch_pfit.control);
11860 /* pfit ratios are autocomputed by the hw on gen4+ */
11861 if (INTEL_INFO(dev)->gen < 4)
11862 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
11863 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
11864 }
11865
fd4daa9c
CW		 11866 PIPE_CONF_CHECK_I(pch_pfit.enabled);
11867 if (current_config->pch_pfit.enabled) {
11868 PIPE_CONF_CHECK_I(pch_pfit.pos);
11869 PIPE_CONF_CHECK_I(pch_pfit.size);
11870 }
2fa2fe9a 11871
a1b2278e
CK		 11872 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
11873
e59150dc
JB		 11874 /* BDW+ don't expose a synchronous way to read the state */
11875 if (IS_HASWELL(dev))
11876 PIPE_CONF_CHECK_I(ips_enabled);
42db64ef 11877
282740f7
VS		 11878 PIPE_CONF_CHECK_I(double_wide);
11879
26804afd
DV		 11880 PIPE_CONF_CHECK_X(ddi_pll_sel);
11881
c0d43d62 11882 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 11883 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 11884 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 11885 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11886 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
d452c5b6 11887 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
3f4cd19f
DL		 11888 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11889 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11890 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
c0d43d62 11891
42571aef
VS		 11892 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
11893 PIPE_CONF_CHECK_I(pipe_bpp);
11894
2d112de7 11895 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
a9a7e98a 11896 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
5e550656 11897
66e985c0 11898#undef PIPE_CONF_CHECK_X
08a24034 11899#undef PIPE_CONF_CHECK_I
b95af8be 11900#undef PIPE_CONF_CHECK_I_ALT
1bd1bd80 11901#undef PIPE_CONF_CHECK_FLAGS
5e550656 11902#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 11903#undef PIPE_CONF_QUIRK
88adfff1 11904
0e8ffe1b
DV		 11905 return true;
11906}
11907
08db6652
DL		 11908static void check_wm_state(struct drm_device *dev)
11909{
11910 struct drm_i915_private *dev_priv = dev->dev_private;
11911 struct skl_ddb_allocation hw_ddb, *sw_ddb;
11912 struct intel_crtc *intel_crtc;
11913 int plane;
11914
11915 if (INTEL_INFO(dev)->gen < 9)
11916 return;
11917
11918 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
11919 sw_ddb = &dev_priv->wm.skl_hw.ddb;
11920
11921 for_each_intel_crtc(dev, intel_crtc) {
11922 struct skl_ddb_entry *hw_entry, *sw_entry;
11923 const enum pipe pipe = intel_crtc->pipe;
11924
11925 if (!intel_crtc->active)
11926 continue;
11927
11928 /* planes */
dd740780 11929 for_each_plane(dev_priv, pipe, plane) {
08db6652
DL		 11930 hw_entry = &hw_ddb.plane[pipe][plane];
11931 sw_entry = &sw_ddb->plane[pipe][plane];
11932
11933 if (skl_ddb_entry_equal(hw_entry, sw_entry))
11934 continue;
11935
11936 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
11937 "(expected (%u,%u), found (%u,%u))\n",
11938 pipe_name(pipe), plane + 1,
11939 sw_entry->start, sw_entry->end,
11940 hw_entry->start, hw_entry->end);
11941 }
11942
11943 /* cursor */
11944 hw_entry = &hw_ddb.cursor[pipe];
11945 sw_entry = &sw_ddb->cursor[pipe];
11946
11947 if (skl_ddb_entry_equal(hw_entry, sw_entry))
11948 continue;
11949
11950 DRM_ERROR("mismatch in DDB state pipe %c cursor "
11951 "(expected (%u,%u), found (%u,%u))\n",
11952 pipe_name(pipe),
11953 sw_entry->start, sw_entry->end,
11954 hw_entry->start, hw_entry->end);
11955 }
11956}
11957
91d1b4bd
DV		 11958static void
11959check_connector_state(struct drm_device *dev)
8af6cf88 11960{
8af6cf88
DV		 11961 struct intel_connector *connector;
11962
3a3371ff 11963 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 11964 /* This also checks the encoder/connector hw state with the
11965 * ->get_hw_state callbacks. */
11966 intel_connector_check_state(connector);
11967
e2c719b7 11968 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
8af6cf88
DV		 11969 "connector's staged encoder doesn't match current encoder\n");
11970 }
91d1b4bd
DV		 11971}
11972
11973static void
11974check_encoder_state(struct drm_device *dev)
11975{
11976 struct intel_encoder *encoder;
11977 struct intel_connector *connector;
8af6cf88 11978
b2784e15 11979 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 11980 bool enabled = false;
11981 bool active = false;
11982 enum pipe pipe, tracked_pipe;
11983
11984 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11985 encoder->base.base.id,
8e329a03 11986 encoder->base.name);
8af6cf88 11987
e2c719b7 11988 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
8af6cf88 11989 "encoder's stage crtc doesn't match current crtc\n");
e2c719b7 11990 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
8af6cf88
DV		 11991 "encoder's active_connectors set, but no crtc\n");
11992
3a3371ff 11993 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 11994 if (connector->base.encoder != &encoder->base)
11995 continue;
11996 enabled = true;
11997 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
11998 active = true;
11999 }
0e32b39c
DA		 12000 /*
12001 * for MST connectors if we unplug the connector is gone
12002 * away but the encoder is still connected to a crtc
12003 * until a modeset happens in response to the hotplug.
12004 */
12005 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
12006 continue;
12007
e2c719b7 12008 I915_STATE_WARN(!!encoder->base.crtc != enabled,
8af6cf88
DV		 12009 "encoder's enabled state mismatch "
12010 "(expected %i, found %i)\n",
12011 !!encoder->base.crtc, enabled);
e2c719b7 12012 I915_STATE_WARN(active && !encoder->base.crtc,
8af6cf88
DV		 12013 "active encoder with no crtc\n");
12014
e2c719b7 12015 I915_STATE_WARN(encoder->connectors_active != active,
8af6cf88
DV		 12016 "encoder's computed active state doesn't match tracked active state "
12017 "(expected %i, found %i)\n", active, encoder->connectors_active);
12018
12019 active = encoder->get_hw_state(encoder, &pipe);
e2c719b7 12020 I915_STATE_WARN(active != encoder->connectors_active,
8af6cf88
DV		 12021 "encoder's hw state doesn't match sw tracking "
12022 "(expected %i, found %i)\n",
12023 encoder->connectors_active, active);
12024
12025 if (!encoder->base.crtc)
12026 continue;
12027
12028 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
e2c719b7 12029 I915_STATE_WARN(active && pipe != tracked_pipe,
8af6cf88
DV		 12030 "active encoder's pipe doesn't match"
12031 "(expected %i, found %i)\n",
12032 tracked_pipe, pipe);
12033
12034 }
91d1b4bd
DV		 12035}
12036
12037static void
12038check_crtc_state(struct drm_device *dev)
12039{
fbee40df 12040 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 12041 struct intel_crtc *crtc;
12042 struct intel_encoder *encoder;
5cec258b 12043 struct intel_crtc_state pipe_config;
8af6cf88 12044
d3fcc808 12045 for_each_intel_crtc(dev, crtc) {
8af6cf88
DV		 12046 bool enabled = false;
12047 bool active = false;
12048
045ac3b5
JB		 12049 memset(&pipe_config, 0, sizeof(pipe_config));
12050
8af6cf88
DV		 12051 DRM_DEBUG_KMS("[CRTC:%d]\n",
12052 crtc->base.base.id);
12053
83d65738 12054 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
8af6cf88
DV		 12055 "active crtc, but not enabled in sw tracking\n");
12056
b2784e15 12057 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 12058 if (encoder->base.crtc != &crtc->base)
12059 continue;
12060 enabled = true;
12061 if (encoder->connectors_active)
12062 active = true;
12063 }
6c49f241 12064
e2c719b7 12065 I915_STATE_WARN(active != crtc->active,
8af6cf88
DV		 12066 "crtc's computed active state doesn't match tracked active state "
12067 "(expected %i, found %i)\n", active, crtc->active);
83d65738 12068 I915_STATE_WARN(enabled != crtc->base.state->enable,
8af6cf88 12069 "crtc's computed enabled state doesn't match tracked enabled state "
83d65738
MR		 12070 "(expected %i, found %i)\n", enabled,
12071 crtc->base.state->enable);
8af6cf88 12072
0e8ffe1b
DV		 12073 active = dev_priv->display.get_pipe_config(crtc,
12074 &pipe_config);
d62cf62a 12075
b6b5d049
VS		 12076 /* hw state is inconsistent with the pipe quirk */
12077 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12078 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
d62cf62a
DV		 12079 active = crtc->active;
12080
b2784e15 12081 for_each_intel_encoder(dev, encoder) {
3eaba51c 12082 enum pipe pipe;
6c49f241
DV		 12083 if (encoder->base.crtc != &crtc->base)
12084 continue;
1d37b689 12085 if (encoder->get_hw_state(encoder, &pipe))
6c49f241
DV		 12086 encoder->get_config(encoder, &pipe_config);
12087 }
12088
e2c719b7 12089 I915_STATE_WARN(crtc->active != active,
0e8ffe1b
DV		 12090 "crtc active state doesn't match with hw state "
12091 "(expected %i, found %i)\n", crtc->active, active);
12092
c0b03411 12093 if (active &&
6e3c9717 12094 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
e2c719b7 12095 I915_STATE_WARN(1, "pipe state doesn't match!\n");
c0b03411
DV		 12096 intel_dump_pipe_config(crtc, &pipe_config,
12097 "[hw state]");
6e3c9717 12098 intel_dump_pipe_config(crtc, crtc->config,
c0b03411
DV		 12099 "[sw state]");
12100 }
8af6cf88
DV		 12101 }
12102}
12103
91d1b4bd
DV		 12104static void
12105check_shared_dpll_state(struct drm_device *dev)
12106{
fbee40df 12107 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 12108 struct intel_crtc *crtc;
12109 struct intel_dpll_hw_state dpll_hw_state;
12110 int i;
5358901f
DV		 12111
12112 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12113 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12114 int enabled_crtcs = 0, active_crtcs = 0;
12115 bool active;
12116
12117 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12118
12119 DRM_DEBUG_KMS("%s\n", pll->name);
12120
12121 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12122
e2c719b7 12123 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
5358901f 12124 "more active pll users than references: %i vs %i\n",
3e369b76 12125 pll->active, hweight32(pll->config.crtc_mask));
e2c719b7 12126 I915_STATE_WARN(pll->active && !pll->on,
5358901f 12127 "pll in active use but not on in sw tracking\n");
e2c719b7 12128 I915_STATE_WARN(pll->on && !pll->active,
35c95375 12129 "pll in on but not on in use in sw tracking\n");
e2c719b7 12130 I915_STATE_WARN(pll->on != active,
5358901f
DV		 12131 "pll on state mismatch (expected %i, found %i)\n",
12132 pll->on, active);
12133
d3fcc808 12134 for_each_intel_crtc(dev, crtc) {
83d65738 12135 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
5358901f
DV		 12136 enabled_crtcs++;
12137 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12138 active_crtcs++;
12139 }
e2c719b7 12140 I915_STATE_WARN(pll->active != active_crtcs,
5358901f
DV		 12141 "pll active crtcs mismatch (expected %i, found %i)\n",
12142 pll->active, active_crtcs);
e2c719b7 12143 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
5358901f 12144 "pll enabled crtcs mismatch (expected %i, found %i)\n",
3e369b76 12145 hweight32(pll->config.crtc_mask), enabled_crtcs);
66e985c0 12146
e2c719b7 12147 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
66e985c0
DV		 12148 sizeof(dpll_hw_state)),
12149 "pll hw state mismatch\n");
5358901f 12150 }
8af6cf88
DV		 12151}
12152
91d1b4bd
DV		 12153void
12154intel_modeset_check_state(struct drm_device *dev)
12155{
08db6652 12156 check_wm_state(dev);
91d1b4bd
DV		 12157 check_connector_state(dev);
12158 check_encoder_state(dev);
12159 check_crtc_state(dev);
12160 check_shared_dpll_state(dev);
12161}
12162
5cec258b 12163void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
18442d08
VS		 12164 int dotclock)
12165{
12166 /*
12167 * FDI already provided one idea for the dotclock.
12168 * Yell if the encoder disagrees.
12169 */
2d112de7 12170 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
18442d08 12171 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
2d112de7 12172 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
18442d08
VS		 12173}
12174
80715b2f
VS		 12175static void update_scanline_offset(struct intel_crtc *crtc)
12176{
12177 struct drm_device *dev = crtc->base.dev;
12178
12179 /*
12180 * The scanline counter increments at the leading edge of hsync.
12181 *
12182 * On most platforms it starts counting from vtotal-1 on the
12183 * first active line. That means the scanline counter value is
12184 * always one less than what we would expect. Ie. just after
12185 * start of vblank, which also occurs at start of hsync (on the
12186 * last active line), the scanline counter will read vblank_start-1.
12187 *
12188 * On gen2 the scanline counter starts counting from 1 instead
12189 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12190 * to keep the value positive), instead of adding one.
12191 *
12192 * On HSW+ the behaviour of the scanline counter depends on the output
12193 * type. For DP ports it behaves like most other platforms, but on HDMI
12194 * there's an extra 1 line difference. So we need to add two instead of
12195 * one to the value.
12196 */
12197 if (IS_GEN2(dev)) {
6e3c9717 12198 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
80715b2f
VS		 12199 int vtotal;
12200
12201 vtotal = mode->crtc_vtotal;
12202 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12203 vtotal /= 2;
12204
12205 crtc->scanline_offset = vtotal - 1;
12206 } else if (HAS_DDI(dev) &&
409ee761 12207 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
80715b2f
VS		 12208 crtc->scanline_offset = 2;
12209 } else
12210 crtc->scanline_offset = 1;
12211}
12212
5cec258b 12213static struct intel_crtc_state *
7f27126e
JB		 12214intel_modeset_compute_config(struct drm_crtc *crtc,
12215 struct drm_display_mode *mode,
83a57153 12216 struct drm_atomic_state *state,
7f27126e
JB		 12217 unsigned *modeset_pipes,
12218 unsigned *prepare_pipes,
12219 unsigned *disable_pipes)
12220{
db7542dd 12221 struct drm_device *dev = crtc->dev;
5cec258b 12222 struct intel_crtc_state *pipe_config = NULL;
db7542dd 12223 struct intel_crtc *intel_crtc;
0b901879
ACO		 12224 int ret = 0;
12225
12226 ret = drm_atomic_add_affected_connectors(state, crtc);
12227 if (ret)
12228 return ERR_PTR(ret);
7f27126e
JB		 12229
12230 intel_modeset_affected_pipes(crtc, modeset_pipes,
12231 prepare_pipes, disable_pipes);
12232
db7542dd
ACO		 12233 for_each_intel_crtc_masked(dev, *disable_pipes, intel_crtc) {
12234 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12235 if (IS_ERR(pipe_config))
12236 return pipe_config;
12237
12238 pipe_config->base.enable = false;
12239 }
7f27126e
JB		 12240
12241 /*
12242 * Note this needs changes when we start tracking multiple modes
12243 * and crtcs. At that point we'll need to compute the whole config
12244 * (i.e. one pipe_config for each crtc) rather than just the one
12245 * for this crtc.
12246 */
db7542dd
ACO		 12247 for_each_intel_crtc_masked(dev, *modeset_pipes, intel_crtc) {
12248 /* FIXME: For now we still expect modeset_pipes has at most
12249 * one bit set. */
12250 if (WARN_ON(&intel_crtc->base != crtc))
12251 continue;
83a57153 12252
8805aa71 12253 pipe_config = intel_modeset_pipe_config(crtc, mode, state);
db7542dd
ACO		 12254 if (IS_ERR(pipe_config))
12255 return pipe_config;
7f27126e 12256
304603f4
ACO		 12257 pipe_config->base.enable = true;
12258
db7542dd
ACO		 12259 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
12260 "[modeset]");
12261 }
12262
12263 return intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));;
7f27126e
JB		 12264}
12265
225da59b 12266static int __intel_set_mode_setup_plls(struct drm_atomic_state *state,
ed6739ef
ACO		 12267 unsigned modeset_pipes,
12268 unsigned disable_pipes)
12269{
225da59b 12270 struct drm_device *dev = state->dev;
ed6739ef
ACO		 12271 struct drm_i915_private *dev_priv = to_i915(dev);
12272 unsigned clear_pipes = modeset_pipes | disable_pipes;
12273 struct intel_crtc *intel_crtc;
12274 int ret = 0;
12275
12276 if (!dev_priv->display.crtc_compute_clock)
12277 return 0;
12278
12279 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
12280 if (ret)
12281 goto done;
12282
12283 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
225da59b
ACO		 12284 struct intel_crtc_state *crtc_state =
12285 intel_atomic_get_crtc_state(state, intel_crtc);
12286
12287 /* Modeset pipes should have a new state by now */
12288 if (WARN_ON(IS_ERR(crtc_state)))
12289 continue;
12290
ed6739ef 12291 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
225da59b 12292 crtc_state);
ed6739ef
ACO		 12293 if (ret) {
12294 intel_shared_dpll_abort_config(dev_priv);
12295 goto done;
12296 }
12297 }
12298
12299done:
12300 return ret;
12301}
12302
f30da187
DV		 12303static int __intel_set_mode(struct drm_crtc *crtc,
12304 struct drm_display_mode *mode,
7f27126e 12305 int x, int y, struct drm_framebuffer *fb,
5cec258b 12306 struct intel_crtc_state *pipe_config,
7f27126e
JB		 12307 unsigned modeset_pipes,
12308 unsigned prepare_pipes,
12309 unsigned disable_pipes)
a6778b3c
DV		 12310{
12311 struct drm_device *dev = crtc->dev;
fbee40df 12312 struct drm_i915_private *dev_priv = dev->dev_private;
4b4b9238 12313 struct drm_display_mode *saved_mode;
304603f4 12314 struct drm_atomic_state *state = pipe_config->base.state;
83a57153 12315 struct intel_crtc_state *crtc_state_copy = NULL;
25c5b266 12316 struct intel_crtc *intel_crtc;
c0c36b94 12317 int ret = 0;
a6778b3c 12318
4b4b9238 12319 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 12320 if (!saved_mode)
12321 return -ENOMEM;
a6778b3c 12322
83a57153
ACO		 12323 crtc_state_copy = kmalloc(sizeof(*crtc_state_copy), GFP_KERNEL);
12324 if (!crtc_state_copy) {
12325 ret = -ENOMEM;
12326 goto done;
12327 }
12328
3ac18232 12329 *saved_mode = crtc->mode;
a6778b3c 12330
30a970c6
JB		 12331 /*
12332 * See if the config requires any additional preparation, e.g.
12333 * to adjust global state with pipes off. We need to do this
12334 * here so we can get the modeset_pipe updated config for the new
12335 * mode set on this crtc. For other crtcs we need to use the
12336 * adjusted_mode bits in the crtc directly.
12337 */
f8437dd1 12338 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
304603f4
ACO		 12339 ret = valleyview_modeset_global_pipes(state, &prepare_pipes);
12340 if (ret)
12341 goto done;
30a970c6 12342
c164f833
VS		 12343 /* may have added more to prepare_pipes than we should */
12344 prepare_pipes &= ~disable_pipes;
12345 }
12346
225da59b 12347 ret = __intel_set_mode_setup_plls(state, modeset_pipes, disable_pipes);
ed6739ef
ACO		 12348 if (ret)
12349 goto done;
8bd31e67 12350
460da916
DV		 12351 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
12352 intel_crtc_disable(&intel_crtc->base);
12353
ea9d758d 12354 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
ce22dba9
ML		 12355 if (intel_crtc->base.state->enable) {
12356 intel_crtc_disable_planes(&intel_crtc->base);
ea9d758d 12357 dev_priv->display.crtc_disable(&intel_crtc->base);
ce22dba9 12358 }
ea9d758d 12359 }
a6778b3c 12360
6c4c86f5
DV		 12361 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
12362 * to set it here already despite that we pass it down the callchain.
7f27126e
JB		 12363 *
12364 * Note we'll need to fix this up when we start tracking multiple
12365 * pipes; here we assume a single modeset_pipe and only track the
12366 * single crtc and mode.
f6e5b160 12367 */
b8cecdf5 12368 if (modeset_pipes) {
25c5b266 12369 crtc->mode = *mode;
b8cecdf5
DV		 12370 /* mode_set/enable/disable functions rely on a correct pipe
12371 * config. */
f5de6e07 12372 intel_crtc_set_state(to_intel_crtc(crtc), pipe_config);
c326c0a9
VS		 12373
12374 /*
12375 * Calculate and store various constants which
12376 * are later needed by vblank and swap-completion
12377 * timestamping. They are derived from true hwmode.
12378 */
12379 drm_calc_timestamping_constants(crtc,
2d112de7 12380 &pipe_config->base.adjusted_mode);
b8cecdf5 12381 }
7758a113 12382
ea9d758d
DV		 12383 /* Only after disabling all output pipelines that will be changed can we
12384 * update the the output configuration. */
12385 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 12386
304603f4 12387 modeset_update_crtc_power_domains(state);
47fab737 12388
25c5b266 12389 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
455a6808
GP		 12390 struct drm_plane *primary = intel_crtc->base.primary;
12391 int vdisplay, hdisplay;
4c10794f 12392
455a6808 12393 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
70a101f8
MR		 12394 ret = drm_plane_helper_update(primary, &intel_crtc->base,
12395 fb, 0, 0,
12396 hdisplay, vdisplay,
12397 x << 16, y << 16,
12398 hdisplay << 16, vdisplay << 16);
a6778b3c
DV		 12399 }
12400
12401 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
80715b2f
VS		 12402 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
12403 update_scanline_offset(intel_crtc);
12404
25c5b266 12405 dev_priv->display.crtc_enable(&intel_crtc->base);
ce22dba9 12406 intel_crtc_enable_planes(&intel_crtc->base);
80715b2f 12407 }
a6778b3c 12408
a6778b3c
DV		 12409 /* FIXME: add subpixel order */
12410done:
83d65738 12411 if (ret && crtc->state->enable)
3ac18232 12412 crtc->mode = *saved_mode;
a6778b3c 12413
83a57153
ACO		 12414 if (ret == 0 && pipe_config) {
12415 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12416
12417 /* The pipe_config will be freed with the atomic state, so
12418 * make a copy. */
12419 memcpy(crtc_state_copy, intel_crtc->config,
12420 sizeof *crtc_state_copy);
12421 intel_crtc->config = crtc_state_copy;
12422 intel_crtc->base.state = &crtc_state_copy->base;
83a57153
ACO		 12423 } else {
12424 kfree(crtc_state_copy);
12425 }
12426
3ac18232 12427 kfree(saved_mode);
a6778b3c 12428 return ret;
f6e5b160
CW		 12429}
12430
7f27126e
JB		 12431static int intel_set_mode_pipes(struct drm_crtc *crtc,
12432 struct drm_display_mode *mode,
12433 int x, int y, struct drm_framebuffer *fb,
5cec258b 12434 struct intel_crtc_state *pipe_config,
7f27126e
JB		 12435 unsigned modeset_pipes,
12436 unsigned prepare_pipes,
12437 unsigned disable_pipes)
f30da187
DV		 12438{
12439 int ret;
12440
7f27126e
JB		 12441 ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes,
12442 prepare_pipes, disable_pipes);
f30da187
DV		 12443
12444 if (ret == 0)
12445 intel_modeset_check_state(crtc->dev);
12446
12447 return ret;
12448}
12449
7f27126e
JB		 12450static int intel_set_mode(struct drm_crtc *crtc,
12451 struct drm_display_mode *mode,
83a57153
ACO		 12452 int x, int y, struct drm_framebuffer *fb,
12453 struct drm_atomic_state *state)
7f27126e 12454{
5cec258b 12455 struct intel_crtc_state *pipe_config;
7f27126e 12456 unsigned modeset_pipes, prepare_pipes, disable_pipes;
83a57153 12457 int ret = 0;
7f27126e 12458
8805aa71 12459 pipe_config = intel_modeset_compute_config(crtc, mode, state,
7f27126e
JB		 12460 &modeset_pipes,
12461 &prepare_pipes,
12462 &disable_pipes);
12463
83a57153
ACO		 12464 if (IS_ERR(pipe_config)) {
12465 ret = PTR_ERR(pipe_config);
12466 goto out;
12467 }
12468
12469 ret = intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config,
12470 modeset_pipes, prepare_pipes,
12471 disable_pipes);
12472 if (ret)
12473 goto out;
7f27126e 12474
83a57153
ACO		 12475out:
12476 return ret;
7f27126e
JB		 12477}
12478
c0c36b94
CW		 12479void intel_crtc_restore_mode(struct drm_crtc *crtc)
12480{
83a57153
ACO		 12481 struct drm_device *dev = crtc->dev;
12482 struct drm_atomic_state *state;
12483 struct intel_encoder *encoder;
12484 struct intel_connector *connector;
12485 struct drm_connector_state *connector_state;
12486
12487 state = drm_atomic_state_alloc(dev);
12488 if (!state) {
12489 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
12490 crtc->base.id);
12491 return;
12492 }
12493
12494 state->acquire_ctx = dev->mode_config.acquire_ctx;
12495
12496 /* The force restore path in the HW readout code relies on the staged
12497 * config still keeping the user requested config while the actual
12498 * state has been overwritten by the configuration read from HW. We
12499 * need to copy the staged config to the atomic state, otherwise the
12500 * mode set will just reapply the state the HW is already in. */
12501 for_each_intel_encoder(dev, encoder) {
12502 if (&encoder->new_crtc->base != crtc)
12503 continue;
12504
12505 for_each_intel_connector(dev, connector) {
12506 if (connector->new_encoder != encoder)
12507 continue;
12508
12509 connector_state = drm_atomic_get_connector_state(state, &connector->base);
12510 if (IS_ERR(connector_state)) {
12511 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
12512 connector->base.base.id,
12513 connector->base.name,
12514 PTR_ERR(connector_state));
12515 continue;
12516 }
12517
12518 connector_state->crtc = crtc;
12519 connector_state->best_encoder = &encoder->base;
12520 }
12521 }
12522
12523 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb,
12524 state);
12525
12526 drm_atomic_state_free(state);
c0c36b94
CW		 12527}
12528
25c5b266
DV		 12529#undef for_each_intel_crtc_masked
12530
d9e55608
DV		 12531static void intel_set_config_free(struct intel_set_config *config)
12532{
12533 if (!config)
12534 return;
12535
1aa4b628
DV		 12536 kfree(config->save_connector_encoders);
12537 kfree(config->save_encoder_crtcs);
7668851f 12538 kfree(config->save_crtc_enabled);
d9e55608
DV		 12539 kfree(config);
12540}
12541
85f9eb71
DV		 12542static int intel_set_config_save_state(struct drm_device *dev,
12543 struct intel_set_config *config)
12544{
7668851f 12545 struct drm_crtc *crtc;
85f9eb71
DV		 12546 struct drm_encoder *encoder;
12547 struct drm_connector *connector;
12548 int count;
12549
7668851f
VS		 12550 config->save_crtc_enabled =
12551 kcalloc(dev->mode_config.num_crtc,
12552 sizeof(bool), GFP_KERNEL);
12553 if (!config->save_crtc_enabled)
12554 return -ENOMEM;
12555
1aa4b628
DV		 12556 config->save_encoder_crtcs =
12557 kcalloc(dev->mode_config.num_encoder,
12558 sizeof(struct drm_crtc *), GFP_KERNEL);
12559 if (!config->save_encoder_crtcs)
85f9eb71
DV		 12560 return -ENOMEM;
12561
1aa4b628
DV		 12562 config->save_connector_encoders =
12563 kcalloc(dev->mode_config.num_connector,
12564 sizeof(struct drm_encoder *), GFP_KERNEL);
12565 if (!config->save_connector_encoders)
85f9eb71
DV		 12566 return -ENOMEM;
12567
12568 /* Copy data. Note that driver private data is not affected.
12569 * Should anything bad happen only the expected state is
12570 * restored, not the drivers personal bookkeeping.
12571 */
7668851f 12572 count = 0;
70e1e0ec 12573 for_each_crtc(dev, crtc) {
83d65738 12574 config->save_crtc_enabled[count++] = crtc->state->enable;
7668851f
VS		 12575 }
12576
85f9eb71
DV		 12577 count = 0;
12578 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 12579 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 12580 }
12581
12582 count = 0;
12583 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 12584 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 12585 }
12586
12587 return 0;
12588}
12589
12590static void intel_set_config_restore_state(struct drm_device *dev,
12591 struct intel_set_config *config)
12592{
7668851f 12593 struct intel_crtc *crtc;
9a935856
DV		 12594 struct intel_encoder *encoder;
12595 struct intel_connector *connector;
85f9eb71
DV		 12596 int count;
12597
7668851f 12598 count = 0;
d3fcc808 12599 for_each_intel_crtc(dev, crtc) {
7668851f
VS		 12600 crtc->new_enabled = config->save_crtc_enabled[count++];
12601 }
12602
85f9eb71 12603 count = 0;
b2784e15 12604 for_each_intel_encoder(dev, encoder) {
9a935856
DV		 12605 encoder->new_crtc =
12606 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 12607 }
12608
12609 count = 0;
3a3371ff 12610 for_each_intel_connector(dev, connector) {
9a935856
DV		 12611 connector->new_encoder =
12612 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 12613 }
12614}
12615
e3de42b6 12616static bool
2e57f47d 12617is_crtc_connector_off(struct drm_mode_set *set)
e3de42b6
ID		 12618{
12619 int i;
12620
2e57f47d
CW		 12621 if (set->num_connectors == 0)
12622 return false;
12623
12624 if (WARN_ON(set->connectors == NULL))
12625 return false;
12626
12627 for (i = 0; i < set->num_connectors; i++)
12628 if (set->connectors[i]->encoder &&
12629 set->connectors[i]->encoder->crtc == set->crtc &&
12630 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
e3de42b6
ID		 12631 return true;
12632
12633 return false;
12634}
12635
5e2b584e
DV		 12636static void
12637intel_set_config_compute_mode_changes(struct drm_mode_set *set,
12638 struct intel_set_config *config)
12639{
12640
12641 /* We should be able to check here if the fb has the same properties
12642 * and then just flip_or_move it */
2e57f47d
CW		 12643 if (is_crtc_connector_off(set)) {
12644 config->mode_changed = true;
f4510a27 12645 } else if (set->crtc->primary->fb != set->fb) {
3b150f08
MR		 12646 /*
12647 * If we have no fb, we can only flip as long as the crtc is
12648 * active, otherwise we need a full mode set. The crtc may
12649 * be active if we've only disabled the primary plane, or
12650 * in fastboot situations.
12651 */
f4510a27 12652 if (set->crtc->primary->fb == NULL) {
319d9827
JB		 12653 struct intel_crtc *intel_crtc =
12654 to_intel_crtc(set->crtc);
12655
3b150f08 12656 if (intel_crtc->active) {
319d9827
JB		 12657 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
12658 config->fb_changed = true;
12659 } else {
12660 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
12661 config->mode_changed = true;
12662 }
5e2b584e
DV		 12663 } else if (set->fb == NULL) {
12664 config->mode_changed = true;
72f4901e 12665 } else if (set->fb->pixel_format !=
f4510a27 12666 set->crtc->primary->fb->pixel_format) {
5e2b584e 12667 config->mode_changed = true;
e3de42b6 12668 } else {
5e2b584e 12669 config->fb_changed = true;
e3de42b6 12670 }
5e2b584e
DV		 12671 }
12672
835c5873 12673 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 12674 config->fb_changed = true;
12675
12676 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
12677 DRM_DEBUG_KMS("modes are different, full mode set\n");
12678 drm_mode_debug_printmodeline(&set->crtc->mode);
12679 drm_mode_debug_printmodeline(set->mode);
12680 config->mode_changed = true;
12681 }
a1d95703
CW		 12682
12683 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
12684 set->crtc->base.id, config->mode_changed, config->fb_changed);
5e2b584e
DV		 12685}
12686
2e431051 12687static int
9a935856
DV		 12688intel_modeset_stage_output_state(struct drm_device *dev,
12689 struct drm_mode_set *set,
944b0c76
ACO		 12690 struct intel_set_config *config,
12691 struct drm_atomic_state *state)
50f56119 12692{
9a935856 12693 struct intel_connector *connector;
944b0c76 12694 struct drm_connector_state *connector_state;
9a935856 12695 struct intel_encoder *encoder;
7668851f 12696 struct intel_crtc *crtc;
f3f08572 12697 int ro;
50f56119 12698
9abdda74 12699 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 12700 * of connectors. For paranoia, double-check this. */
12701 WARN_ON(!set->fb && (set->num_connectors != 0));
12702 WARN_ON(set->fb && (set->num_connectors == 0));
12703
3a3371ff 12704 for_each_intel_connector(dev, connector) {
9a935856
DV		 12705 /* Otherwise traverse passed in connector list and get encoders
12706 * for them. */
50f56119 12707 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 12708 if (set->connectors[ro] == &connector->base) {
0e32b39c 12709 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
50f56119
DV		 12710 break;
12711 }
12712 }
12713
9a935856
DV		 12714 /* If we disable the crtc, disable all its connectors. Also, if
12715 * the connector is on the changing crtc but not on the new
12716 * connector list, disable it. */
12717 if ((!set->fb || ro == set->num_connectors) &&
12718 connector->base.encoder &&
12719 connector->base.encoder->crtc == set->crtc) {
12720 connector->new_encoder = NULL;
12721
12722 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
12723 connector->base.base.id,
c23cc417 12724 connector->base.name);
9a935856
DV		 12725 }
12726
12727
12728 if (&connector->new_encoder->base != connector->base.encoder) {
10634189
ACO		 12729 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] encoder changed, full mode switch\n",
12730 connector->base.base.id,
12731 connector->base.name);
5e2b584e 12732 config->mode_changed = true;
50f56119
DV		 12733 }
12734 }
9a935856 12735 /* connector->new_encoder is now updated for all connectors. */
50f56119 12736
9a935856 12737 /* Update crtc of enabled connectors. */
3a3371ff 12738 for_each_intel_connector(dev, connector) {
7668851f
VS		 12739 struct drm_crtc *new_crtc;
12740
9a935856 12741 if (!connector->new_encoder)
50f56119
DV		 12742 continue;
12743
9a935856 12744 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 12745
12746 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 12747 if (set->connectors[ro] == &connector->base)
50f56119
DV		 12748 new_crtc = set->crtc;
12749 }
12750
12751 /* Make sure the new CRTC will work with the encoder */
14509916
TR		 12752 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
12753 new_crtc)) {
5e2b584e 12754 return -EINVAL;
50f56119 12755 }
0e32b39c 12756 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
9a935856 12757
944b0c76
ACO		 12758 connector_state =
12759 drm_atomic_get_connector_state(state, &connector->base);
12760 if (IS_ERR(connector_state))
12761 return PTR_ERR(connector_state);
12762
12763 connector_state->crtc = new_crtc;
12764 connector_state->best_encoder = &connector->new_encoder->base;
12765
9a935856
DV		 12766 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
12767 connector->base.base.id,
c23cc417 12768 connector->base.name,
9a935856
DV		 12769 new_crtc->base.id);
12770 }
12771
12772 /* Check for any encoders that needs to be disabled. */
b2784e15 12773 for_each_intel_encoder(dev, encoder) {
5a65f358 12774 int num_connectors = 0;
3a3371ff 12775 for_each_intel_connector(dev, connector) {
9a935856
DV		 12776 if (connector->new_encoder == encoder) {
12777 WARN_ON(!connector->new_encoder->new_crtc);
5a65f358 12778 num_connectors++;
9a935856
DV		 12779 }
12780 }
5a65f358
PZ		 12781
12782 if (num_connectors == 0)
12783 encoder->new_crtc = NULL;
12784 else if (num_connectors > 1)
12785 return -EINVAL;
12786
9a935856
DV		 12787 /* Only now check for crtc changes so we don't miss encoders
12788 * that will be disabled. */
12789 if (&encoder->new_crtc->base != encoder->base.crtc) {
10634189
ACO		 12790 DRM_DEBUG_KMS("[ENCODER:%d:%s] crtc changed, full mode switch\n",
12791 encoder->base.base.id,
12792 encoder->base.name);
5e2b584e 12793 config->mode_changed = true;
50f56119
DV		 12794 }
12795 }
9a935856 12796 /* Now we've also updated encoder->new_crtc for all encoders. */
3a3371ff 12797 for_each_intel_connector(dev, connector) {
944b0c76
ACO		 12798 connector_state =
12799 drm_atomic_get_connector_state(state, &connector->base);
9d918c15
ACO		 12800 if (IS_ERR(connector_state))
12801 return PTR_ERR(connector_state);
944b0c76
ACO		 12802
12803 if (connector->new_encoder) {
0e32b39c
DA		 12804 if (connector->new_encoder != connector->encoder)
12805 connector->encoder = connector->new_encoder;
944b0c76
ACO		 12806 } else {
12807 connector_state->crtc = NULL;
f61cccf3 12808 connector_state->best_encoder = NULL;
944b0c76 12809 }
0e32b39c 12810 }
d3fcc808 12811 for_each_intel_crtc(dev, crtc) {
7668851f
VS		 12812 crtc->new_enabled = false;
12813
b2784e15 12814 for_each_intel_encoder(dev, encoder) {
7668851f
VS		 12815 if (encoder->new_crtc == crtc) {
12816 crtc->new_enabled = true;
12817 break;
12818 }
12819 }
12820
83d65738 12821 if (crtc->new_enabled != crtc->base.state->enable) {
10634189
ACO		 12822 DRM_DEBUG_KMS("[CRTC:%d] %sabled, full mode switch\n",
12823 crtc->base.base.id,
7668851f
VS		 12824 crtc->new_enabled ? "en" : "dis");
12825 config->mode_changed = true;
12826 }
12827 }
12828
2e431051
DV		 12829 return 0;
12830}
12831
7d00a1f5
VS		 12832static void disable_crtc_nofb(struct intel_crtc *crtc)
12833{
12834 struct drm_device *dev = crtc->base.dev;
12835 struct intel_encoder *encoder;
12836 struct intel_connector *connector;
12837
12838 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
12839 pipe_name(crtc->pipe));
12840
3a3371ff 12841 for_each_intel_connector(dev, connector) {
7d00a1f5
VS		 12842 if (connector->new_encoder &&
12843 connector->new_encoder->new_crtc == crtc)
12844 connector->new_encoder = NULL;
12845 }
12846
b2784e15 12847 for_each_intel_encoder(dev, encoder) {
7d00a1f5
VS		 12848 if (encoder->new_crtc == crtc)
12849 encoder->new_crtc = NULL;
12850 }
12851
12852 crtc->new_enabled = false;
12853}
12854
2e431051
DV		 12855static int intel_crtc_set_config(struct drm_mode_set *set)
12856{
12857 struct drm_device *dev;
2e431051 12858 struct drm_mode_set save_set;
83a57153 12859 struct drm_atomic_state *state = NULL;
2e431051 12860 struct intel_set_config *config;
5cec258b 12861 struct intel_crtc_state *pipe_config;
50f52756 12862 unsigned modeset_pipes, prepare_pipes, disable_pipes;
2e431051 12863 int ret;
2e431051 12864
8d3e375e
DV		 12865 BUG_ON(!set);
12866 BUG_ON(!set->crtc);
12867 BUG_ON(!set->crtc->helper_private);
2e431051 12868
7e53f3a4
DV		 12869 /* Enforce sane interface api - has been abused by the fb helper. */
12870 BUG_ON(!set->mode && set->fb);
12871 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 12872
2e431051
DV		 12873 if (set->fb) {
12874 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
12875 set->crtc->base.id, set->fb->base.id,
12876 (int)set->num_connectors, set->x, set->y);
12877 } else {
12878 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 12879 }
12880
12881 dev = set->crtc->dev;
12882
12883 ret = -ENOMEM;
12884 config = kzalloc(sizeof(*config), GFP_KERNEL);
12885 if (!config)
12886 goto out_config;
12887
12888 ret = intel_set_config_save_state(dev, config);
12889 if (ret)
12890 goto out_config;
12891
12892 save_set.crtc = set->crtc;
12893 save_set.mode = &set->crtc->mode;
12894 save_set.x = set->crtc->x;
12895 save_set.y = set->crtc->y;
f4510a27 12896 save_set.fb = set->crtc->primary->fb;
2e431051
DV		 12897
12898 /* Compute whether we need a full modeset, only an fb base update or no
12899 * change at all. In the future we might also check whether only the
12900 * mode changed, e.g. for LVDS where we only change the panel fitter in
12901 * such cases. */
12902 intel_set_config_compute_mode_changes(set, config);
12903
83a57153
ACO		 12904 state = drm_atomic_state_alloc(dev);
12905 if (!state) {
12906 ret = -ENOMEM;
12907 goto out_config;
12908 }
12909
12910 state->acquire_ctx = dev->mode_config.acquire_ctx;
12911
944b0c76 12912 ret = intel_modeset_stage_output_state(dev, set, config, state);
2e431051
DV		 12913 if (ret)
12914 goto fail;
12915
50f52756 12916 pipe_config = intel_modeset_compute_config(set->crtc, set->mode,
8805aa71 12917 state,
50f52756
JB		 12918 &modeset_pipes,
12919 &prepare_pipes,
12920 &disable_pipes);
20664591 12921 if (IS_ERR(pipe_config)) {
6ac0483b 12922 ret = PTR_ERR(pipe_config);
50f52756 12923 goto fail;
20664591 12924 } else if (pipe_config) {
b9950a13 12925 if (pipe_config->has_audio !=
6e3c9717 12926 to_intel_crtc(set->crtc)->config->has_audio)
20664591
JB		 12927 config->mode_changed = true;
12928
af15d2ce
JB		 12929 /*
12930 * Note we have an issue here with infoframes: current code
12931 * only updates them on the full mode set path per hw
12932 * requirements. So here we should be checking for any
12933 * required changes and forcing a mode set.
12934 */
20664591 12935 }
50f52756 12936
1f9954d0
JB		 12937 intel_update_pipe_size(to_intel_crtc(set->crtc));
12938
5e2b584e 12939 if (config->mode_changed) {
50f52756
JB		 12940 ret = intel_set_mode_pipes(set->crtc, set->mode,
12941 set->x, set->y, set->fb, pipe_config,
12942 modeset_pipes, prepare_pipes,
12943 disable_pipes);
5e2b584e 12944 } else if (config->fb_changed) {
3b150f08 12945 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
455a6808 12946 struct drm_plane *primary = set->crtc->primary;
b70709a6
ML		 12947 struct intel_plane_state *plane_state =
12948 to_intel_plane_state(primary->state);
12949 bool was_visible = plane_state->visible;
455a6808 12950 int vdisplay, hdisplay;
3b150f08 12951
455a6808 12952 drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay);
70a101f8
MR		 12953 ret = drm_plane_helper_update(primary, set->crtc, set->fb,
12954 0, 0, hdisplay, vdisplay,
12955 set->x << 16, set->y << 16,
12956 hdisplay << 16, vdisplay << 16);
3b150f08
MR		 12957
12958 /*
12959 * We need to make sure the primary plane is re-enabled if it
12960 * has previously been turned off.
12961 */
b70709a6
ML		 12962 plane_state = to_intel_plane_state(primary->state);
12963 if (ret == 0 && !was_visible && plane_state->visible) {
3b150f08 12964 WARN_ON(!intel_crtc->active);
87d4300a 12965 intel_post_enable_primary(set->crtc);
3b150f08
MR		 12966 }
12967
7ca51a3a
JB		 12968 /*
12969 * In the fastboot case this may be our only check of the
12970 * state after boot. It would be better to only do it on
12971 * the first update, but we don't have a nice way of doing that
12972 * (and really, set_config isn't used much for high freq page
12973 * flipping, so increasing its cost here shouldn't be a big
12974 * deal).
12975 */
d330a953 12976 if (i915.fastboot && ret == 0)
7ca51a3a 12977 intel_modeset_check_state(set->crtc->dev);
50f56119
DV		 12978 }
12979
2d05eae1 12980 if (ret) {
bf67dfeb
DV		 12981 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
12982 set->crtc->base.id, ret);
50f56119 12983fail:
2d05eae1 12984 intel_set_config_restore_state(dev, config);
50f56119 12985
83a57153
ACO		 12986 drm_atomic_state_clear(state);
12987
7d00a1f5
VS		 12988 /*
12989 * HACK: if the pipe was on, but we didn't have a framebuffer,
12990 * force the pipe off to avoid oopsing in the modeset code
12991 * due to fb==NULL. This should only happen during boot since
12992 * we don't yet reconstruct the FB from the hardware state.
12993 */
12994 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
12995 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
12996
2d05eae1
CW		 12997 /* Try to restore the config */
12998 if (config->mode_changed &&
12999 intel_set_mode(save_set.crtc, save_set.mode,
83a57153
ACO		 13000 save_set.x, save_set.y, save_set.fb,
13001 state))
2d05eae1
CW		 13002 DRM_ERROR("failed to restore config after modeset failure\n");
13003 }
50f56119 13004
d9e55608 13005out_config:
83a57153
ACO		 13006 if (state)
13007 drm_atomic_state_free(state);
13008
d9e55608 13009 intel_set_config_free(config);
50f56119
DV		 13010 return ret;
13011}
f6e5b160
CW		 13012
13013static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160 13014 .gamma_set = intel_crtc_gamma_set,
50f56119 13015 .set_config = intel_crtc_set_config,
f6e5b160
CW		 13016 .destroy = intel_crtc_destroy,
13017 .page_flip = intel_crtc_page_flip,
1356837e
MR		 13018 .atomic_duplicate_state = intel_crtc_duplicate_state,
13019 .atomic_destroy_state = intel_crtc_destroy_state,
f6e5b160
CW		 13020};
13021
5358901f
DV		 13022static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13023 struct intel_shared_dpll *pll,
13024 struct intel_dpll_hw_state *hw_state)
ee7b9f93 13025{
5358901f 13026 uint32_t val;
ee7b9f93 13027
f458ebbc 13028 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
bd2bb1b9
PZ		 13029 return false;
13030
5358901f 13031 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 13032 hw_state->dpll = val;
13033 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13034 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 13035
13036 return val & DPLL_VCO_ENABLE;
13037}
13038
15bdd4cf
DV		 13039static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13040 struct intel_shared_dpll *pll)
13041{
3e369b76
ACO		 13042 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13043 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
15bdd4cf
DV		 13044}
13045
e7b903d2
DV		 13046static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13047 struct intel_shared_dpll *pll)
13048{
e7b903d2 13049 /* PCH refclock must be enabled first */
89eff4be 13050 ibx_assert_pch_refclk_enabled(dev_priv);
e7b903d2 13051
3e369b76 13052 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf
DV		 13053
13054 /* Wait for the clocks to stabilize. */
13055 POSTING_READ(PCH_DPLL(pll->id));
13056 udelay(150);
13057
13058 /* The pixel multiplier can only be updated once the
13059 * DPLL is enabled and the clocks are stable.
13060 *
13061 * So write it again.
13062 */
3e369b76 13063 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf 13064 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13065 udelay(200);
13066}
13067
13068static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13069 struct intel_shared_dpll *pll)
13070{
13071 struct drm_device *dev = dev_priv->dev;
13072 struct intel_crtc *crtc;
e7b903d2
DV		 13073
13074 /* Make sure no transcoder isn't still depending on us. */
d3fcc808 13075 for_each_intel_crtc(dev, crtc) {
e7b903d2
DV		 13076 if (intel_crtc_to_shared_dpll(crtc) == pll)
13077 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 13078 }
13079
15bdd4cf
DV		 13080 I915_WRITE(PCH_DPLL(pll->id), 0);
13081 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13082 udelay(200);
13083}
13084
46edb027
DV		 13085static char *ibx_pch_dpll_names[] = {
13086 "PCH DPLL A",
13087 "PCH DPLL B",
13088};
13089
7c74ade1 13090static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 13091{
e7b903d2 13092 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 13093 int i;
13094
7c74ade1 13095 dev_priv->num_shared_dpll = 2;
ee7b9f93 13096
e72f9fbf 13097 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 13098 dev_priv->shared_dplls[i].id = i;
13099 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 13100 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 13101 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13102 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 13103 dev_priv->shared_dplls[i].get_hw_state =
13104 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 13105 }
13106}
13107
7c74ade1
DV		 13108static void intel_shared_dpll_init(struct drm_device *dev)
13109{
e7b903d2 13110 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1 13111
9cd86933
DV		 13112 if (HAS_DDI(dev))
13113 intel_ddi_pll_init(dev);
13114 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7c74ade1
DV		 13115 ibx_pch_dpll_init(dev);
13116 else
13117 dev_priv->num_shared_dpll = 0;
13118
13119 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
7c74ade1
DV		 13120}
13121
1fc0a8f7
TU		 13122/**
13123 * intel_wm_need_update - Check whether watermarks need updating
13124 * @plane: drm plane
13125 * @state: new plane state
13126 *
13127 * Check current plane state versus the new one to determine whether
13128 * watermarks need to be recalculated.
13129 *
13130 * Returns true or false.
13131 */
13132bool intel_wm_need_update(struct drm_plane *plane,
13133 struct drm_plane_state *state)
13134{
13135 /* Update watermarks on tiling changes. */
13136 if (!plane->state->fb || !state->fb ||
13137 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
13138 plane->state->rotation != state->rotation)
13139 return true;
13140
13141 return false;
13142}
13143
6beb8c23
MR		 13144/**
13145 * intel_prepare_plane_fb - Prepare fb for usage on plane
13146 * @plane: drm plane to prepare for
13147 * @fb: framebuffer to prepare for presentation
13148 *
13149 * Prepares a framebuffer for usage on a display plane. Generally this
13150 * involves pinning the underlying object and updating the frontbuffer tracking
13151 * bits. Some older platforms need special physical address handling for
13152 * cursor planes.
13153 *
13154 * Returns 0 on success, negative error code on failure.
13155 */
13156int
13157intel_prepare_plane_fb(struct drm_plane *plane,
d136dfee
TU		 13158 struct drm_framebuffer *fb,
13159 const struct drm_plane_state *new_state)
465c120c
MR		 13160{
13161 struct drm_device *dev = plane->dev;
6beb8c23
MR		 13162 struct intel_plane *intel_plane = to_intel_plane(plane);
13163 enum pipe pipe = intel_plane->pipe;
13164 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13165 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13166 unsigned frontbuffer_bits = 0;
13167 int ret = 0;
465c120c 13168
ea2c67bb 13169 if (!obj)
465c120c
MR		 13170 return 0;
13171
6beb8c23
MR		 13172 switch (plane->type) {
13173 case DRM_PLANE_TYPE_PRIMARY:
13174 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
13175 break;
13176 case DRM_PLANE_TYPE_CURSOR:
13177 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
13178 break;
13179 case DRM_PLANE_TYPE_OVERLAY:
13180 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
13181 break;
13182 }
465c120c 13183
6beb8c23 13184 mutex_lock(&dev->struct_mutex);
465c120c 13185
6beb8c23
MR		 13186 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13187 INTEL_INFO(dev)->cursor_needs_physical) {
13188 int align = IS_I830(dev) ? 16 * 1024 : 256;
13189 ret = i915_gem_object_attach_phys(obj, align);
13190 if (ret)
13191 DRM_DEBUG_KMS("failed to attach phys object\n");
13192 } else {
82bc3b2d 13193 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL);
6beb8c23 13194 }
465c120c 13195
6beb8c23
MR		 13196 if (ret == 0)
13197 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
fdd508a6 13198
4c34574f 13199 mutex_unlock(&dev->struct_mutex);
465c120c 13200
6beb8c23
MR		 13201 return ret;
13202}
13203
38f3ce3a
MR		 13204/**
13205 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13206 * @plane: drm plane to clean up for
13207 * @fb: old framebuffer that was on plane
13208 *
13209 * Cleans up a framebuffer that has just been removed from a plane.
13210 */
13211void
13212intel_cleanup_plane_fb(struct drm_plane *plane,
d136dfee
TU		 13213 struct drm_framebuffer *fb,
13214 const struct drm_plane_state *old_state)
38f3ce3a
MR		 13215{
13216 struct drm_device *dev = plane->dev;
13217 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13218
13219 if (WARN_ON(!obj))
13220 return;
13221
13222 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13223 !INTEL_INFO(dev)->cursor_needs_physical) {
13224 mutex_lock(&dev->struct_mutex);
82bc3b2d 13225 intel_unpin_fb_obj(fb, old_state);
38f3ce3a
MR		 13226 mutex_unlock(&dev->struct_mutex);
13227 }
465c120c
MR		 13228}
13229
6156a456
CK		 13230int
13231skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13232{
13233 int max_scale;
13234 struct drm_device *dev;
13235 struct drm_i915_private *dev_priv;
13236 int crtc_clock, cdclk;
13237
13238 if (!intel_crtc || !crtc_state)
13239 return DRM_PLANE_HELPER_NO_SCALING;
13240
13241 dev = intel_crtc->base.dev;
13242 dev_priv = dev->dev_private;
13243 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13244 cdclk = dev_priv->display.get_display_clock_speed(dev);
13245
13246 if (!crtc_clock || !cdclk)
13247 return DRM_PLANE_HELPER_NO_SCALING;
13248
13249 /*
13250 * skl max scale is lower of:
13251 * close to 3 but not 3, -1 is for that purpose
13252 * or
13253 * cdclk/crtc_clock
13254 */
13255 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13256
13257 return max_scale;
13258}
13259
465c120c 13260static int
3c692a41
GP		 13261intel_check_primary_plane(struct drm_plane *plane,
13262 struct intel_plane_state *state)
13263{
32b7eeec
MR		 13264 struct drm_device *dev = plane->dev;
13265 struct drm_i915_private *dev_priv = dev->dev_private;
2b875c22 13266 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb 13267 struct intel_crtc *intel_crtc;
6156a456 13268 struct intel_crtc_state *crtc_state;
2b875c22 13269 struct drm_framebuffer *fb = state->base.fb;
3c692a41
GP		 13270 struct drm_rect *dest = &state->dst;
13271 struct drm_rect *src = &state->src;
13272 const struct drm_rect *clip = &state->clip;
d8106366 13273 bool can_position = false;
6156a456
CK		 13274 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13275 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
465c120c
MR		 13276 int ret;
13277
ea2c67bb
MR		 13278 crtc = crtc ? crtc : plane->crtc;
13279 intel_crtc = to_intel_crtc(crtc);
6156a456
CK		 13280 crtc_state = state->base.state ?
13281 intel_atomic_get_crtc_state(state->base.state, intel_crtc) : NULL;
ea2c67bb 13282
6156a456
CK		 13283 if (INTEL_INFO(dev)->gen >= 9) {
13284 min_scale = 1;
13285 max_scale = skl_max_scale(intel_crtc, crtc_state);
d8106366 13286 can_position = true;
6156a456 13287 }
d8106366 13288
c59cb179
MR		 13289 ret = drm_plane_helper_check_update(plane, crtc, fb,
13290 src, dest, clip,
6156a456
CK		 13291 min_scale,
13292 max_scale,
d8106366
SJ		 13293 can_position, true,
13294 &state->visible);
c59cb179
MR		 13295 if (ret)
13296 return ret;
465c120c 13297
32b7eeec 13298 if (intel_crtc->active) {
b70709a6
ML		 13299 struct intel_plane_state *old_state =
13300 to_intel_plane_state(plane->state);
13301
32b7eeec
MR		 13302 intel_crtc->atomic.wait_for_flips = true;
13303
13304 /*
13305 * FBC does not work on some platforms for rotated
13306 * planes, so disable it when rotation is not 0 and
13307 * update it when rotation is set back to 0.
13308 *
13309 * FIXME: This is redundant with the fbc update done in
13310 * the primary plane enable function except that that
13311 * one is done too late. We eventually need to unify
13312 * this.
13313 */
b70709a6 13314 if (state->visible &&
32b7eeec 13315 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
e35fef21 13316 dev_priv->fbc.crtc == intel_crtc &&
8e7d688b 13317 state->base.rotation != BIT(DRM_ROTATE_0)) {
32b7eeec
MR		 13318 intel_crtc->atomic.disable_fbc = true;
13319 }
13320
b70709a6 13321 if (state->visible && !old_state->visible) {
32b7eeec
MR		 13322 /*
13323 * BDW signals flip done immediately if the plane
13324 * is disabled, even if the plane enable is already
13325 * armed to occur at the next vblank :(
13326 */
b70709a6 13327 if (IS_BROADWELL(dev))
32b7eeec
MR		 13328 intel_crtc->atomic.wait_vblank = true;
13329 }
13330
13331 intel_crtc->atomic.fb_bits |=
13332 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
13333
13334 intel_crtc->atomic.update_fbc = true;
0fda6568 13335
1fc0a8f7 13336 if (intel_wm_need_update(plane, &state->base))
0fda6568 13337 intel_crtc->atomic.update_wm = true;
ccc759dc
GP		 13338 }
13339
6156a456
CK		 13340 if (INTEL_INFO(dev)->gen >= 9) {
13341 ret = skl_update_scaler_users(intel_crtc, crtc_state,
13342 to_intel_plane(plane), state, 0);
13343 if (ret)
13344 return ret;
13345 }
13346
14af293f
GP		 13347 return 0;
13348}
13349
13350static void
13351intel_commit_primary_plane(struct drm_plane *plane,
13352 struct intel_plane_state *state)
13353{
2b875c22
MR		 13354 struct drm_crtc *crtc = state->base.crtc;
13355 struct drm_framebuffer *fb = state->base.fb;
13356 struct drm_device *dev = plane->dev;
14af293f 13357 struct drm_i915_private *dev_priv = dev->dev_private;
ea2c67bb 13358 struct intel_crtc *intel_crtc;
14af293f
GP		 13359 struct drm_rect *src = &state->src;
13360
ea2c67bb
MR		 13361 crtc = crtc ? crtc : plane->crtc;
13362 intel_crtc = to_intel_crtc(crtc);
cf4c7c12
MR		 13363
13364 plane->fb = fb;
9dc806fc
MR		 13365 crtc->x = src->x1 >> 16;
13366 crtc->y = src->y1 >> 16;
ccc759dc 13367
ccc759dc 13368 if (intel_crtc->active) {
27321ae8 13369 if (state->visible)
ccc759dc
GP		 13370 /* FIXME: kill this fastboot hack */
13371 intel_update_pipe_size(intel_crtc);
465c120c 13372
27321ae8
ML		 13373 dev_priv->display.update_primary_plane(crtc, plane->fb,
13374 crtc->x, crtc->y);
ccc759dc 13375 }
465c120c
MR		 13376}
13377
a8ad0d8e
ML		 13378static void
13379intel_disable_primary_plane(struct drm_plane *plane,
13380 struct drm_crtc *crtc,
13381 bool force)
13382{
13383 struct drm_device *dev = plane->dev;
13384 struct drm_i915_private *dev_priv = dev->dev_private;
13385
a8ad0d8e
ML		 13386 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13387}
13388
32b7eeec 13389static void intel_begin_crtc_commit(struct drm_crtc *crtc)
3c692a41 13390{
32b7eeec 13391 struct drm_device *dev = crtc->dev;
140fd38d 13392 struct drm_i915_private *dev_priv = dev->dev_private;
3c692a41 13393 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ea2c67bb
MR		 13394 struct intel_plane *intel_plane;
13395 struct drm_plane *p;
13396 unsigned fb_bits = 0;
13397
13398 /* Track fb's for any planes being disabled */
13399 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
13400 intel_plane = to_intel_plane(p);
13401
13402 if (intel_crtc->atomic.disabled_planes &
13403 (1 << drm_plane_index(p))) {
13404 switch (p->type) {
13405 case DRM_PLANE_TYPE_PRIMARY:
13406 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
13407 break;
13408 case DRM_PLANE_TYPE_CURSOR:
13409 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
13410 break;
13411 case DRM_PLANE_TYPE_OVERLAY:
13412 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
13413 break;
13414 }
3c692a41 13415
ea2c67bb
MR		 13416 mutex_lock(&dev->struct_mutex);
13417 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
13418 mutex_unlock(&dev->struct_mutex);
13419 }
13420 }
3c692a41 13421
32b7eeec
MR		 13422 if (intel_crtc->atomic.wait_for_flips)
13423 intel_crtc_wait_for_pending_flips(crtc);
3c692a41 13424
32b7eeec
MR		 13425 if (intel_crtc->atomic.disable_fbc)
13426 intel_fbc_disable(dev);
3c692a41 13427
32b7eeec
MR		 13428 if (intel_crtc->atomic.pre_disable_primary)
13429 intel_pre_disable_primary(crtc);
3c692a41 13430
32b7eeec
MR		 13431 if (intel_crtc->atomic.update_wm)
13432 intel_update_watermarks(crtc);
3c692a41 13433
32b7eeec 13434 intel_runtime_pm_get(dev_priv);
3c692a41 13435
c34c9ee4
MR		 13436 /* Perform vblank evasion around commit operation */
13437 if (intel_crtc->active)
13438 intel_crtc->atomic.evade =
13439 intel_pipe_update_start(intel_crtc,
13440 &intel_crtc->atomic.start_vbl_count);
32b7eeec
MR		 13441}
13442
13443static void intel_finish_crtc_commit(struct drm_crtc *crtc)
13444{
13445 struct drm_device *dev = crtc->dev;
13446 struct drm_i915_private *dev_priv = dev->dev_private;
13447 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13448 struct drm_plane *p;
13449
c34c9ee4
MR		 13450 if (intel_crtc->atomic.evade)
13451 intel_pipe_update_end(intel_crtc,
13452 intel_crtc->atomic.start_vbl_count);
3c692a41 13453
140fd38d 13454 intel_runtime_pm_put(dev_priv);
3c692a41 13455
32b7eeec
MR		 13456 if (intel_crtc->atomic.wait_vblank)
13457 intel_wait_for_vblank(dev, intel_crtc->pipe);
13458
13459 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
13460
13461 if (intel_crtc->atomic.update_fbc) {
ccc759dc 13462 mutex_lock(&dev->struct_mutex);
7ff0ebcc 13463 intel_fbc_update(dev);
ccc759dc 13464 mutex_unlock(&dev->struct_mutex);
38f3ce3a 13465 }
3c692a41 13466
32b7eeec
MR		 13467 if (intel_crtc->atomic.post_enable_primary)
13468 intel_post_enable_primary(crtc);
3c692a41 13469
32b7eeec
MR		 13470 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
13471 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
13472 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
13473 false, false);
13474
13475 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
3c692a41
GP		 13476}
13477
cf4c7c12 13478/**
4a3b8769
MR		 13479 * intel_plane_destroy - destroy a plane
13480 * @plane: plane to destroy
cf4c7c12 13481 *
4a3b8769
MR		 13482 * Common destruction function for all types of planes (primary, cursor,
13483 * sprite).
cf4c7c12 13484 */
4a3b8769 13485void intel_plane_destroy(struct drm_plane *plane)
465c120c
MR		 13486{
13487 struct intel_plane *intel_plane = to_intel_plane(plane);
13488 drm_plane_cleanup(plane);
13489 kfree(intel_plane);
13490}
13491
65a3fea0 13492const struct drm_plane_funcs intel_plane_funcs = {
70a101f8
MR		 13493 .update_plane = drm_atomic_helper_update_plane,
13494 .disable_plane = drm_atomic_helper_disable_plane,
3d7d6510 13495 .destroy = intel_plane_destroy,
c196e1d6 13496 .set_property = drm_atomic_helper_plane_set_property,
a98b3431
MR		 13497 .atomic_get_property = intel_plane_atomic_get_property,
13498 .atomic_set_property = intel_plane_atomic_set_property,
ea2c67bb
MR		 13499 .atomic_duplicate_state = intel_plane_duplicate_state,
13500 .atomic_destroy_state = intel_plane_destroy_state,
13501
465c120c
MR		 13502};
13503
13504static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13505 int pipe)
13506{
13507 struct intel_plane *primary;
8e7d688b 13508 struct intel_plane_state *state;
465c120c
MR		 13509 const uint32_t *intel_primary_formats;
13510 int num_formats;
13511
13512 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13513 if (primary == NULL)
13514 return NULL;
13515
8e7d688b
MR		 13516 state = intel_create_plane_state(&primary->base);
13517 if (!state) {
ea2c67bb
MR		 13518 kfree(primary);
13519 return NULL;
13520 }
8e7d688b 13521 primary->base.state = &state->base;
ea2c67bb 13522
465c120c
MR		 13523 primary->can_scale = false;
13524 primary->max_downscale = 1;
6156a456
CK		 13525 if (INTEL_INFO(dev)->gen >= 9) {
13526 primary->can_scale = true;
13527 }
549e2bfb 13528 state->scaler_id = -1;
465c120c
MR		 13529 primary->pipe = pipe;
13530 primary->plane = pipe;
c59cb179
MR		 13531 primary->check_plane = intel_check_primary_plane;
13532 primary->commit_plane = intel_commit_primary_plane;
a8ad0d8e 13533 primary->disable_plane = intel_disable_primary_plane;
08e221fb 13534 primary->ckey.flags = I915_SET_COLORKEY_NONE;
465c120c
MR		 13535 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13536 primary->plane = !pipe;
13537
13538 if (INTEL_INFO(dev)->gen <= 3) {
13539 intel_primary_formats = intel_primary_formats_gen2;
13540 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
13541 } else {
13542 intel_primary_formats = intel_primary_formats_gen4;
13543 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
13544 }
13545
13546 drm_universal_plane_init(dev, &primary->base, 0,
65a3fea0 13547 &intel_plane_funcs,
465c120c
MR		 13548 intel_primary_formats, num_formats,
13549 DRM_PLANE_TYPE_PRIMARY);
48404c1e 13550
3b7a5119
SJ		 13551 if (INTEL_INFO(dev)->gen >= 4)
13552 intel_create_rotation_property(dev, primary);
48404c1e 13553
ea2c67bb
MR		 13554 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13555
465c120c
MR		 13556 return &primary->base;
13557}
13558
3b7a5119
SJ		 13559void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13560{
13561 if (!dev->mode_config.rotation_property) {
13562 unsigned long flags = BIT(DRM_ROTATE_0) |
13563 BIT(DRM_ROTATE_180);
13564
13565 if (INTEL_INFO(dev)->gen >= 9)
13566 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13567
13568 dev->mode_config.rotation_property =
13569 drm_mode_create_rotation_property(dev, flags);
13570 }
13571 if (dev->mode_config.rotation_property)
13572 drm_object_attach_property(&plane->base.base,
13573 dev->mode_config.rotation_property,
13574 plane->base.state->rotation);
13575}
13576
3d7d6510 13577static int
852e787c
GP		 13578intel_check_cursor_plane(struct drm_plane *plane,
13579 struct intel_plane_state *state)
3d7d6510 13580{
2b875c22 13581 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb 13582 struct drm_device *dev = plane->dev;
2b875c22 13583 struct drm_framebuffer *fb = state->base.fb;
852e787c
GP		 13584 struct drm_rect *dest = &state->dst;
13585 struct drm_rect *src = &state->src;
13586 const struct drm_rect *clip = &state->clip;
757f9a3e 13587 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
ea2c67bb 13588 struct intel_crtc *intel_crtc;
757f9a3e
GP		 13589 unsigned stride;
13590 int ret;
3d7d6510 13591
ea2c67bb
MR		 13592 crtc = crtc ? crtc : plane->crtc;
13593 intel_crtc = to_intel_crtc(crtc);
13594
757f9a3e 13595 ret = drm_plane_helper_check_update(plane, crtc, fb,
852e787c 13596 src, dest, clip,
3d7d6510
MR		 13597 DRM_PLANE_HELPER_NO_SCALING,
13598 DRM_PLANE_HELPER_NO_SCALING,
852e787c 13599 true, true, &state->visible);
757f9a3e
GP		 13600 if (ret)
13601 return ret;
13602
13603
13604 /* if we want to turn off the cursor ignore width and height */
13605 if (!obj)
32b7eeec 13606 goto finish;
757f9a3e 13607
757f9a3e 13608 /* Check for which cursor types we support */
ea2c67bb
MR		 13609 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
13610 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13611 state->base.crtc_w, state->base.crtc_h);
757f9a3e
GP		 13612 return -EINVAL;
13613 }
13614
ea2c67bb
MR		 13615 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13616 if (obj->base.size < stride * state->base.crtc_h) {
757f9a3e
GP		 13617 DRM_DEBUG_KMS("buffer is too small\n");
13618 return -ENOMEM;
13619 }
13620
3a656b54 13621 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
757f9a3e
GP		 13622 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13623 ret = -EINVAL;
13624 }
757f9a3e 13625
32b7eeec
MR		 13626finish:
13627 if (intel_crtc->active) {
3749f463 13628 if (plane->state->crtc_w != state->base.crtc_w)
32b7eeec
MR		 13629 intel_crtc->atomic.update_wm = true;
13630
13631 intel_crtc->atomic.fb_bits |=
13632 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
13633 }
13634
757f9a3e 13635 return ret;
852e787c 13636}
3d7d6510 13637
a8ad0d8e
ML		 13638static void
13639intel_disable_cursor_plane(struct drm_plane *plane,
13640 struct drm_crtc *crtc,
13641 bool force)
13642{
13643 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13644
13645 if (!force) {
13646 plane->fb = NULL;
13647 intel_crtc->cursor_bo = NULL;
13648 intel_crtc->cursor_addr = 0;
13649 }
13650
13651 intel_crtc_update_cursor(crtc, false);
13652}
13653
f4a2cf29 13654static void
852e787c
GP		 13655intel_commit_cursor_plane(struct drm_plane *plane,
13656 struct intel_plane_state *state)
13657{
2b875c22 13658 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb
MR		 13659 struct drm_device *dev = plane->dev;
13660 struct intel_crtc *intel_crtc;
2b875c22 13661 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
a912f12f 13662 uint32_t addr;
852e787c 13663
ea2c67bb
MR		 13664 crtc = crtc ? crtc : plane->crtc;
13665 intel_crtc = to_intel_crtc(crtc);
13666
2b875c22 13667 plane->fb = state->base.fb;
ea2c67bb
MR		 13668 crtc->cursor_x = state->base.crtc_x;
13669 crtc->cursor_y = state->base.crtc_y;
13670
a912f12f
GP		 13671 if (intel_crtc->cursor_bo == obj)
13672 goto update;
4ed91096 13673
f4a2cf29 13674 if (!obj)
a912f12f 13675 addr = 0;
f4a2cf29 13676 else if (!INTEL_INFO(dev)->cursor_needs_physical)
a912f12f 13677 addr = i915_gem_obj_ggtt_offset(obj);
f4a2cf29 13678 else
a912f12f 13679 addr = obj->phys_handle->busaddr;
852e787c 13680
a912f12f
GP		 13681 intel_crtc->cursor_addr = addr;
13682 intel_crtc->cursor_bo = obj;
13683update:
852e787c 13684
32b7eeec 13685 if (intel_crtc->active)
a912f12f 13686 intel_crtc_update_cursor(crtc, state->visible);
852e787c
GP		 13687}
13688
3d7d6510
MR		 13689static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13690 int pipe)
13691{
13692 struct intel_plane *cursor;
8e7d688b 13693 struct intel_plane_state *state;
3d7d6510
MR		 13694
13695 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13696 if (cursor == NULL)
13697 return NULL;
13698
8e7d688b
MR		 13699 state = intel_create_plane_state(&cursor->base);
13700 if (!state) {
ea2c67bb
MR		 13701 kfree(cursor);
13702 return NULL;
13703 }
8e7d688b 13704 cursor->base.state = &state->base;
ea2c67bb 13705
3d7d6510
MR		 13706 cursor->can_scale = false;
13707 cursor->max_downscale = 1;
13708 cursor->pipe = pipe;
13709 cursor->plane = pipe;
549e2bfb 13710 state->scaler_id = -1;
c59cb179
MR		 13711 cursor->check_plane = intel_check_cursor_plane;
13712 cursor->commit_plane = intel_commit_cursor_plane;
a8ad0d8e 13713 cursor->disable_plane = intel_disable_cursor_plane;
3d7d6510
MR		 13714
13715 drm_universal_plane_init(dev, &cursor->base, 0,
65a3fea0 13716 &intel_plane_funcs,
3d7d6510
MR		 13717 intel_cursor_formats,
13718 ARRAY_SIZE(intel_cursor_formats),
13719 DRM_PLANE_TYPE_CURSOR);
4398ad45
VS		 13720
13721 if (INTEL_INFO(dev)->gen >= 4) {
13722 if (!dev->mode_config.rotation_property)
13723 dev->mode_config.rotation_property =
13724 drm_mode_create_rotation_property(dev,
13725 BIT(DRM_ROTATE_0) |
13726 BIT(DRM_ROTATE_180));
13727 if (dev->mode_config.rotation_property)
13728 drm_object_attach_property(&cursor->base.base,
13729 dev->mode_config.rotation_property,
8e7d688b 13730 state->base.rotation);
4398ad45
VS		 13731 }
13732
ea2c67bb
MR		 13733 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13734
3d7d6510
MR		 13735 return &cursor->base;
13736}
13737
549e2bfb
CK		 13738static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13739 struct intel_crtc_state *crtc_state)
13740{
13741 int i;
13742 struct intel_scaler *intel_scaler;
13743 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13744
13745 for (i = 0; i < intel_crtc->num_scalers; i++) {
13746 intel_scaler = &scaler_state->scalers[i];
13747 intel_scaler->in_use = 0;
13748 intel_scaler->id = i;
13749
13750 intel_scaler->mode = PS_SCALER_MODE_DYN;
13751 }
13752
13753 scaler_state->scaler_id = -1;
13754}
13755
b358d0a6 13756static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 13757{
fbee40df 13758 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 13759 struct intel_crtc *intel_crtc;
f5de6e07 13760 struct intel_crtc_state *crtc_state = NULL;
3d7d6510
MR		 13761 struct drm_plane *primary = NULL;
13762 struct drm_plane *cursor = NULL;
465c120c 13763 int i, ret;
79e53945 13764
955382f3 13765 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB		 13766 if (intel_crtc == NULL)
13767 return;
13768
f5de6e07
ACO		 13769 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13770 if (!crtc_state)
13771 goto fail;
13772 intel_crtc_set_state(intel_crtc, crtc_state);
07878248 13773 crtc_state->base.crtc = &intel_crtc->base;
f5de6e07 13774
549e2bfb
CK		 13775 /* initialize shared scalers */
13776 if (INTEL_INFO(dev)->gen >= 9) {
13777 if (pipe == PIPE_C)
13778 intel_crtc->num_scalers = 1;
13779 else
13780 intel_crtc->num_scalers = SKL_NUM_SCALERS;
13781
13782 skl_init_scalers(dev, intel_crtc, crtc_state);
13783 }
13784
465c120c 13785 primary = intel_primary_plane_create(dev, pipe);
3d7d6510
MR		 13786 if (!primary)
13787 goto fail;
13788
13789 cursor = intel_cursor_plane_create(dev, pipe);
13790 if (!cursor)
13791 goto fail;
13792
465c120c 13793 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
3d7d6510
MR		 13794 cursor, &intel_crtc_funcs);
13795 if (ret)
13796 goto fail;
79e53945
JB		 13797
13798 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 13799 for (i = 0; i < 256; i++) {
13800 intel_crtc->lut_r[i] = i;
13801 intel_crtc->lut_g[i] = i;
13802 intel_crtc->lut_b[i] = i;
13803 }
13804
1f1c2e24
VS		 13805 /*
13806 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
8c0f92e1 13807 * is hooked to pipe B. Hence we want plane A feeding pipe B.
1f1c2e24 13808 */
80824003
JB		 13809 intel_crtc->pipe = pipe;
13810 intel_crtc->plane = pipe;
3a77c4c4 13811 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
28c97730 13812 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 13813 intel_crtc->plane = !pipe;
80824003
JB		 13814 }
13815
4b0e333e
CW		 13816 intel_crtc->cursor_base = ~0;
13817 intel_crtc->cursor_cntl = ~0;
dc41c154 13818 intel_crtc->cursor_size = ~0;
8d7849db 13819
22fd0fab
JB		 13820 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13821 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13822 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13823 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13824
9362c7c5
ACO		 13825 INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
13826
79e53945 13827 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
87b6b101
DV		 13828
13829 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
3d7d6510
MR		 13830 return;
13831
13832fail:
13833 if (primary)
13834 drm_plane_cleanup(primary);
13835 if (cursor)
13836 drm_plane_cleanup(cursor);
f5de6e07 13837 kfree(crtc_state);
3d7d6510 13838 kfree(intel_crtc);
79e53945
JB		 13839}
13840
752aa88a
JB		 13841enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13842{
13843 struct drm_encoder *encoder = connector->base.encoder;
6e9f798d 13844 struct drm_device *dev = connector->base.dev;
752aa88a 13845
51fd371b 13846 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
752aa88a 13847
d3babd3f 13848 if (!encoder || WARN_ON(!encoder->crtc))
752aa88a
JB		 13849 return INVALID_PIPE;
13850
13851 return to_intel_crtc(encoder->crtc)->pipe;
13852}
13853
08d7b3d1 13854int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 13855 struct drm_file *file)
08d7b3d1 13856{
08d7b3d1 13857 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7707e653 13858 struct drm_crtc *drmmode_crtc;
c05422d5 13859 struct intel_crtc *crtc;
08d7b3d1 13860
7707e653 13861 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
08d7b3d1 13862
7707e653 13863 if (!drmmode_crtc) {
08d7b3d1 13864 DRM_ERROR("no such CRTC id\n");
3f2c2057 13865 return -ENOENT;
08d7b3d1
CW		 13866 }
13867
7707e653 13868 crtc = to_intel_crtc(drmmode_crtc);
c05422d5 13869 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 13870
c05422d5 13871 return 0;
08d7b3d1
CW		 13872}
13873
66a9278e 13874static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 13875{
66a9278e
DV		 13876 struct drm_device *dev = encoder->base.dev;
13877 struct intel_encoder *source_encoder;
79e53945 13878 int index_mask = 0;
79e53945
JB		 13879 int entry = 0;
13880
b2784e15 13881 for_each_intel_encoder(dev, source_encoder) {
bc079e8b 13882 if (encoders_cloneable(encoder, source_encoder))
66a9278e
DV		 13883 index_mask |= (1 << entry);
13884
79e53945
JB		 13885 entry++;
13886 }
4ef69c7a 13887
79e53945
JB		 13888 return index_mask;
13889}
13890
4d302442
CW		 13891static bool has_edp_a(struct drm_device *dev)
13892{
13893 struct drm_i915_private *dev_priv = dev->dev_private;
13894
13895 if (!IS_MOBILE(dev))
13896 return false;
13897
13898 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13899 return false;
13900
e3589908 13901 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
4d302442
CW		 13902 return false;
13903
13904 return true;
13905}
13906
84b4e042
JB		 13907static bool intel_crt_present(struct drm_device *dev)
13908{
13909 struct drm_i915_private *dev_priv = dev->dev_private;
13910
884497ed
DL		 13911 if (INTEL_INFO(dev)->gen >= 9)
13912 return false;
13913
cf404ce4 13914 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
84b4e042
JB		 13915 return false;
13916
13917 if (IS_CHERRYVIEW(dev))
13918 return false;
13919
13920 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
13921 return false;
13922
13923 return true;
13924}
13925
79e53945
JB		 13926static void intel_setup_outputs(struct drm_device *dev)
13927{
725e30ad 13928 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 13929 struct intel_encoder *encoder;
cb0953d7 13930 bool dpd_is_edp = false;
79e53945 13931
c9093354 13932 intel_lvds_init(dev);
79e53945 13933
84b4e042 13934 if (intel_crt_present(dev))
79935fca 13935 intel_crt_init(dev);
cb0953d7 13936
c776eb2e
VK		 13937 if (IS_BROXTON(dev)) {
13938 /*
13939 * FIXME: Broxton doesn't support port detection via the
13940 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13941 * detect the ports.
13942 */
13943 intel_ddi_init(dev, PORT_A);
13944 intel_ddi_init(dev, PORT_B);
13945 intel_ddi_init(dev, PORT_C);
13946 } else if (HAS_DDI(dev)) {
0e72a5b5
ED		 13947 int found;
13948
de31facd
JB		 13949 /*
13950 * Haswell uses DDI functions to detect digital outputs.
13951 * On SKL pre-D0 the strap isn't connected, so we assume
13952 * it's there.
13953 */
0e72a5b5 13954 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
de31facd
JB		 13955 /* WaIgnoreDDIAStrap: skl */
13956 if (found ||
13957 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
0e72a5b5
ED		 13958 intel_ddi_init(dev, PORT_A);
13959
13960 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13961 * register */
13962 found = I915_READ(SFUSE_STRAP);
13963
13964 if (found & SFUSE_STRAP_DDIB_DETECTED)
13965 intel_ddi_init(dev, PORT_B);
13966 if (found & SFUSE_STRAP_DDIC_DETECTED)
13967 intel_ddi_init(dev, PORT_C);
13968 if (found & SFUSE_STRAP_DDID_DETECTED)
13969 intel_ddi_init(dev, PORT_D);
13970 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 13971 int found;
5d8a7752 13972 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
270b3042
DV		 13973
13974 if (has_edp_a(dev))
13975 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 13976
dc0fa718 13977 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 13978 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 13979 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 13980 if (!found)
e2debe91 13981 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 13982 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 13983 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 13984 }
13985
dc0fa718 13986 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 13987 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 13988
dc0fa718 13989 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 13990 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 13991
5eb08b69 13992 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 13993 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 13994
270b3042 13995 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 13996 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 13997 } else if (IS_VALLEYVIEW(dev)) {
e17ac6db
VS		 13998 /*
13999 * The DP_DETECTED bit is the latched state of the DDC
14000 * SDA pin at boot. However since eDP doesn't require DDC
14001 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14002 * eDP ports may have been muxed to an alternate function.
14003 * Thus we can't rely on the DP_DETECTED bit alone to detect
14004 * eDP ports. Consult the VBT as well as DP_DETECTED to
14005 * detect eDP ports.
14006 */
d2182a66
VS		 14007 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
14008 !intel_dp_is_edp(dev, PORT_B))
585a94b8
AB		 14009 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
14010 PORT_B);
e17ac6db
VS		 14011 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
14012 intel_dp_is_edp(dev, PORT_B))
14013 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
585a94b8 14014
d2182a66
VS		 14015 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
14016 !intel_dp_is_edp(dev, PORT_C))
6f6005a5
JB		 14017 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
14018 PORT_C);
e17ac6db
VS		 14019 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
14020 intel_dp_is_edp(dev, PORT_C))
14021 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 14022
9418c1f1 14023 if (IS_CHERRYVIEW(dev)) {
e17ac6db 14024 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
9418c1f1
VS		 14025 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
14026 PORT_D);
e17ac6db
VS		 14027 /* eDP not supported on port D, so don't check VBT */
14028 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
14029 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
9418c1f1
VS		 14030 }
14031
3cfca973 14032 intel_dsi_init(dev);
103a196f 14033 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 14034 bool found = false;
7d57382e 14035
e2debe91 14036 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14037 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 14038 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 14039 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
14040 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 14041 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 14042 }
27185ae1 14043
e7281eab 14044 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 14045 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 14046 }
13520b05
KH		 14047
14048 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 14049
e2debe91 14050 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14051 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 14052 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 14053 }
27185ae1 14054
e2debe91 14055 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 14056
b01f2c3a
JB		 14057 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
14058 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 14059 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 14060 }
e7281eab 14061 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 14062 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 14063 }
27185ae1 14064
b01f2c3a 14065 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 14066 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 14067 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 14068 } else if (IS_GEN2(dev))
79e53945
JB		 14069 intel_dvo_init(dev);
14070
103a196f 14071 if (SUPPORTS_TV(dev))
79e53945
JB		 14072 intel_tv_init(dev);
14073
0bc12bcb 14074 intel_psr_init(dev);
7c8f8a70 14075
b2784e15 14076 for_each_intel_encoder(dev, encoder) {
4ef69c7a
CW		 14077 encoder->base.possible_crtcs = encoder->crtc_mask;
14078 encoder->base.possible_clones =
66a9278e 14079 intel_encoder_clones(encoder);
79e53945 14080 }
47356eb6 14081
dde86e2d 14082 intel_init_pch_refclk(dev);
270b3042
DV		 14083
14084 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 14085}
14086
14087static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14088{
60a5ca01 14089 struct drm_device *dev = fb->dev;
79e53945 14090 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 14091
ef2d633e 14092 drm_framebuffer_cleanup(fb);
60a5ca01 14093 mutex_lock(&dev->struct_mutex);
ef2d633e 14094 WARN_ON(!intel_fb->obj->framebuffer_references--);
60a5ca01
VS		 14095 drm_gem_object_unreference(&intel_fb->obj->base);
14096 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 14097 kfree(intel_fb);
14098}
14099
14100static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 14101 struct drm_file *file,
79e53945
JB		 14102 unsigned int *handle)
14103{
14104 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 14105 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 14106
05394f39 14107 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 14108}
14109
14110static const struct drm_framebuffer_funcs intel_fb_funcs = {
14111 .destroy = intel_user_framebuffer_destroy,
14112 .create_handle = intel_user_framebuffer_create_handle,
14113};
14114
b321803d
DL		 14115static
14116u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14117 uint32_t pixel_format)
14118{
14119 u32 gen = INTEL_INFO(dev)->gen;
14120
14121 if (gen >= 9) {
14122 /* "The stride in bytes must not exceed the of the size of 8K
14123 * pixels and 32K bytes."
14124 */
14125 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14126 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14127 return 32*1024;
14128 } else if (gen >= 4) {
14129 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14130 return 16*1024;
14131 else
14132 return 32*1024;
14133 } else if (gen >= 3) {
14134 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14135 return 8*1024;
14136 else
14137 return 16*1024;
14138 } else {
14139 /* XXX DSPC is limited to 4k tiled */
14140 return 8*1024;
14141 }
14142}
14143
b5ea642a
DV		 14144static int intel_framebuffer_init(struct drm_device *dev,
14145 struct intel_framebuffer *intel_fb,
14146 struct drm_mode_fb_cmd2 *mode_cmd,
14147 struct drm_i915_gem_object *obj)
79e53945 14148{
6761dd31 14149 unsigned int aligned_height;
79e53945 14150 int ret;
b321803d 14151 u32 pitch_limit, stride_alignment;
79e53945 14152
dd4916c5
DV		 14153 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14154
2a80eada
DV		 14155 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14156 /* Enforce that fb modifier and tiling mode match, but only for
14157 * X-tiled. This is needed for FBC. */
14158 if (!!(obj->tiling_mode == I915_TILING_X) !=
14159 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14160 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14161 return -EINVAL;
14162 }
14163 } else {
14164 if (obj->tiling_mode == I915_TILING_X)
14165 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14166 else if (obj->tiling_mode == I915_TILING_Y) {
14167 DRM_DEBUG("No Y tiling for legacy addfb\n");
14168 return -EINVAL;
14169 }
14170 }
14171
9a8f0a12
TU		 14172 /* Passed in modifier sanity checking. */
14173 switch (mode_cmd->modifier[0]) {
14174 case I915_FORMAT_MOD_Y_TILED:
14175 case I915_FORMAT_MOD_Yf_TILED:
14176 if (INTEL_INFO(dev)->gen < 9) {
14177 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14178 mode_cmd->modifier[0]);
14179 return -EINVAL;
14180 }
14181 case DRM_FORMAT_MOD_NONE:
14182 case I915_FORMAT_MOD_X_TILED:
14183 break;
14184 default:
c0f40428
JB		 14185 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14186 mode_cmd->modifier[0]);
57cd6508 14187 return -EINVAL;
c16ed4be 14188 }
57cd6508 14189
b321803d
DL		 14190 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14191 mode_cmd->pixel_format);
14192 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14193 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14194 mode_cmd->pitches[0], stride_alignment);
57cd6508 14195 return -EINVAL;
c16ed4be 14196 }
57cd6508 14197
b321803d
DL		 14198 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14199 mode_cmd->pixel_format);
a35cdaa0 14200 if (mode_cmd->pitches[0] > pitch_limit) {
b321803d
DL		 14201 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14202 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
2a80eada 14203 "tiled" : "linear",
a35cdaa0 14204 mode_cmd->pitches[0], pitch_limit);
5d7bd705 14205 return -EINVAL;
c16ed4be 14206 }
5d7bd705 14207
2a80eada 14208 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
c16ed4be
CW		 14209 mode_cmd->pitches[0] != obj->stride) {
14210 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14211 mode_cmd->pitches[0], obj->stride);
5d7bd705 14212 return -EINVAL;
c16ed4be 14213 }
5d7bd705 14214
57779d06 14215 /* Reject formats not supported by any plane early. */
308e5bcb 14216 switch (mode_cmd->pixel_format) {
57779d06 14217 case DRM_FORMAT_C8:
04b3924d
VS		 14218 case DRM_FORMAT_RGB565:
14219 case DRM_FORMAT_XRGB8888:
14220 case DRM_FORMAT_ARGB8888:
57779d06
VS		 14221 break;
14222 case DRM_FORMAT_XRGB1555:
14223 case DRM_FORMAT_ARGB1555:
c16ed4be 14224 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 14225 DRM_DEBUG("unsupported pixel format: %s\n",
14226 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14227 return -EINVAL;
c16ed4be 14228 }
57779d06
VS		 14229 break;
14230 case DRM_FORMAT_XBGR8888:
14231 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 14232 case DRM_FORMAT_XRGB2101010:
14233 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 14234 case DRM_FORMAT_XBGR2101010:
14235 case DRM_FORMAT_ABGR2101010:
c16ed4be 14236 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 14237 DRM_DEBUG("unsupported pixel format: %s\n",
14238 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14239 return -EINVAL;
c16ed4be 14240 }
b5626747 14241 break;
04b3924d
VS		 14242 case DRM_FORMAT_YUYV:
14243 case DRM_FORMAT_UYVY:
14244 case DRM_FORMAT_YVYU:
14245 case DRM_FORMAT_VYUY:
c16ed4be 14246 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 14247 DRM_DEBUG("unsupported pixel format: %s\n",
14248 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14249 return -EINVAL;
c16ed4be 14250 }
57cd6508
CW		 14251 break;
14252 default:
4ee62c76
VS		 14253 DRM_DEBUG("unsupported pixel format: %s\n",
14254 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 14255 return -EINVAL;
14256 }
14257
90f9a336
VS		 14258 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14259 if (mode_cmd->offsets[0] != 0)
14260 return -EINVAL;
14261
ec2c981e 14262 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
091df6cb
DV		 14263 mode_cmd->pixel_format,
14264 mode_cmd->modifier[0]);
53155c0a
DV		 14265 /* FIXME drm helper for size checks (especially planar formats)? */
14266 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14267 return -EINVAL;
14268
c7d73f6a
DV		 14269 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14270 intel_fb->obj = obj;
80075d49 14271 intel_fb->obj->framebuffer_references++;
c7d73f6a 14272
79e53945
JB		 14273 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14274 if (ret) {
14275 DRM_ERROR("framebuffer init failed %d\n", ret);
14276 return ret;
14277 }
14278
79e53945
JB		 14279 return 0;
14280}
14281
79e53945
JB		 14282static struct drm_framebuffer *
14283intel_user_framebuffer_create(struct drm_device *dev,
14284 struct drm_file *filp,
308e5bcb 14285 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 14286{
05394f39 14287 struct drm_i915_gem_object *obj;
79e53945 14288
308e5bcb
JB		 14289 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14290 mode_cmd->handles[0]));
c8725226 14291 if (&obj->base == NULL)
cce13ff7 14292 return ERR_PTR(-ENOENT);
79e53945 14293
d2dff872 14294 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 14295}
14296
4520f53a 14297#ifndef CONFIG_DRM_I915_FBDEV
0632fef6 14298static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
4520f53a
DV		 14299{
14300}
14301#endif
14302
79e53945 14303static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 14304 .fb_create = intel_user_framebuffer_create,
0632fef6 14305 .output_poll_changed = intel_fbdev_output_poll_changed,
5ee67f1c
MR		 14306 .atomic_check = intel_atomic_check,
14307 .atomic_commit = intel_atomic_commit,
79e53945
JB		 14308};
14309
e70236a8
JB		 14310/* Set up chip specific display functions */
14311static void intel_init_display(struct drm_device *dev)
14312{
14313 struct drm_i915_private *dev_priv = dev->dev_private;
14314
ee9300bb
DV		 14315 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14316 dev_priv->display.find_dpll = g4x_find_best_dpll;
ef9348c8
CML		 14317 else if (IS_CHERRYVIEW(dev))
14318 dev_priv->display.find_dpll = chv_find_best_dpll;
ee9300bb
DV		 14319 else if (IS_VALLEYVIEW(dev))
14320 dev_priv->display.find_dpll = vlv_find_best_dpll;
14321 else if (IS_PINEVIEW(dev))
14322 dev_priv->display.find_dpll = pnv_find_best_dpll;
14323 else
14324 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14325
bc8d7dff
DL		 14326 if (INTEL_INFO(dev)->gen >= 9) {
14327 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14328 dev_priv->display.get_initial_plane_config =
14329 skylake_get_initial_plane_config;
bc8d7dff
DL		 14330 dev_priv->display.crtc_compute_clock =
14331 haswell_crtc_compute_clock;
14332 dev_priv->display.crtc_enable = haswell_crtc_enable;
14333 dev_priv->display.crtc_disable = haswell_crtc_disable;
14334 dev_priv->display.off = ironlake_crtc_off;
14335 dev_priv->display.update_primary_plane =
14336 skylake_update_primary_plane;
14337 } else if (HAS_DDI(dev)) {
0e8ffe1b 14338 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14339 dev_priv->display.get_initial_plane_config =
14340 ironlake_get_initial_plane_config;
797d0259
ACO		 14341 dev_priv->display.crtc_compute_clock =
14342 haswell_crtc_compute_clock;
4f771f10
PZ		 14343 dev_priv->display.crtc_enable = haswell_crtc_enable;
14344 dev_priv->display.crtc_disable = haswell_crtc_disable;
df8ad70c 14345 dev_priv->display.off = ironlake_crtc_off;
bc8d7dff
DL		 14346 dev_priv->display.update_primary_plane =
14347 ironlake_update_primary_plane;
09b4ddf9 14348 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 14349 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
5724dbd1
DL		 14350 dev_priv->display.get_initial_plane_config =
14351 ironlake_get_initial_plane_config;
3fb37703
ACO		 14352 dev_priv->display.crtc_compute_clock =
14353 ironlake_crtc_compute_clock;
76e5a89c
DV		 14354 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14355 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 14356 dev_priv->display.off = ironlake_crtc_off;
262ca2b0
MR		 14357 dev_priv->display.update_primary_plane =
14358 ironlake_update_primary_plane;
89b667f8
JB		 14359 } else if (IS_VALLEYVIEW(dev)) {
14360 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14361 dev_priv->display.get_initial_plane_config =
14362 i9xx_get_initial_plane_config;
d6dfee7a 14363 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
89b667f8
JB		 14364 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14365 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14366 dev_priv->display.off = i9xx_crtc_off;
262ca2b0
MR		 14367 dev_priv->display.update_primary_plane =
14368 i9xx_update_primary_plane;
f564048e 14369 } else {
0e8ffe1b 14370 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14371 dev_priv->display.get_initial_plane_config =
14372 i9xx_get_initial_plane_config;
d6dfee7a 14373 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
76e5a89c
DV		 14374 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14375 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 14376 dev_priv->display.off = i9xx_crtc_off;
262ca2b0
MR		 14377 dev_priv->display.update_primary_plane =
14378 i9xx_update_primary_plane;
f564048e 14379 }
e70236a8 14380
e70236a8 14381 /* Returns the core display clock speed */
1652d19e
VS		 14382 if (IS_SKYLAKE(dev))
14383 dev_priv->display.get_display_clock_speed =
14384 skylake_get_display_clock_speed;
14385 else if (IS_BROADWELL(dev))
14386 dev_priv->display.get_display_clock_speed =
14387 broadwell_get_display_clock_speed;
14388 else if (IS_HASWELL(dev))
14389 dev_priv->display.get_display_clock_speed =
14390 haswell_get_display_clock_speed;
14391 else if (IS_VALLEYVIEW(dev))
25eb05fc
JB		 14392 dev_priv->display.get_display_clock_speed =
14393 valleyview_get_display_clock_speed;
b37a6434
VS		 14394 else if (IS_GEN5(dev))
14395 dev_priv->display.get_display_clock_speed =
14396 ilk_get_display_clock_speed;
a7c66cd8
VS		 14397 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14398 IS_GEN6(dev) || IS_IVYBRIDGE(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 14399 dev_priv->display.get_display_clock_speed =
14400 i945_get_display_clock_speed;
14401 else if (IS_I915G(dev))
14402 dev_priv->display.get_display_clock_speed =
14403 i915_get_display_clock_speed;
257a7ffc 14404 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 14405 dev_priv->display.get_display_clock_speed =
14406 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 14407 else if (IS_PINEVIEW(dev))
14408 dev_priv->display.get_display_clock_speed =
14409 pnv_get_display_clock_speed;
e70236a8
JB		 14410 else if (IS_I915GM(dev))
14411 dev_priv->display.get_display_clock_speed =
14412 i915gm_get_display_clock_speed;
14413 else if (IS_I865G(dev))
14414 dev_priv->display.get_display_clock_speed =
14415 i865_get_display_clock_speed;
f0f8a9ce 14416 else if (IS_I85X(dev))
e70236a8
JB		 14417 dev_priv->display.get_display_clock_speed =
14418 i855_get_display_clock_speed;
14419 else /* 852, 830 */
14420 dev_priv->display.get_display_clock_speed =
14421 i830_get_display_clock_speed;
14422
7c10a2b5 14423 if (IS_GEN5(dev)) {
3bb11b53 14424 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
3bb11b53
SJ		 14425 } else if (IS_GEN6(dev)) {
14426 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
3bb11b53
SJ		 14427 } else if (IS_IVYBRIDGE(dev)) {
14428 /* FIXME: detect B0+ stepping and use auto training */
14429 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
059b2fe9 14430 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3bb11b53 14431 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
30a970c6
JB		 14432 } else if (IS_VALLEYVIEW(dev)) {
14433 dev_priv->display.modeset_global_resources =
14434 valleyview_modeset_global_resources;
f8437dd1
VK		 14435 } else if (IS_BROXTON(dev)) {
14436 dev_priv->display.modeset_global_resources =
14437 broxton_modeset_global_resources;
e70236a8 14438 }
8c9f3aaf 14439
8c9f3aaf
JB		 14440 switch (INTEL_INFO(dev)->gen) {
14441 case 2:
14442 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14443 break;
14444
14445 case 3:
14446 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14447 break;
14448
14449 case 4:
14450 case 5:
14451 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14452 break;
14453
14454 case 6:
14455 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14456 break;
7c9017e5 14457 case 7:
4e0bbc31 14458 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
7c9017e5
JB		 14459 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14460 break;
830c81db 14461 case 9:
ba343e02
TU		 14462 /* Drop through - unsupported since execlist only. */
14463 default:
14464 /* Default just returns -ENODEV to indicate unsupported */
14465 dev_priv->display.queue_flip = intel_default_queue_flip;
8c9f3aaf 14466 }
7bd688cd
JN		 14467
14468 intel_panel_init_backlight_funcs(dev);
e39b999a
VS		 14469
14470 mutex_init(&dev_priv->pps_mutex);
e70236a8
JB		 14471}
14472
b690e96c
JB		 14473/*
14474 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14475 * resume, or other times. This quirk makes sure that's the case for
14476 * affected systems.
14477 */
0206e353 14478static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 14479{
14480 struct drm_i915_private *dev_priv = dev->dev_private;
14481
14482 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 14483 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 14484}
14485
b6b5d049
VS		 14486static void quirk_pipeb_force(struct drm_device *dev)
14487{
14488 struct drm_i915_private *dev_priv = dev->dev_private;
14489
14490 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14491 DRM_INFO("applying pipe b force quirk\n");
14492}
14493
435793df
KP		 14494/*
14495 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14496 */
14497static void quirk_ssc_force_disable(struct drm_device *dev)
14498{
14499 struct drm_i915_private *dev_priv = dev->dev_private;
14500 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 14501 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 14502}
14503
4dca20ef 14504/*
5a15ab5b
CE		 14505 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14506 * brightness value
4dca20ef
CE		 14507 */
14508static void quirk_invert_brightness(struct drm_device *dev)
14509{
14510 struct drm_i915_private *dev_priv = dev->dev_private;
14511 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 14512 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 14513}
14514
9c72cc6f
SD		 14515/* Some VBT's incorrectly indicate no backlight is present */
14516static void quirk_backlight_present(struct drm_device *dev)
14517{
14518 struct drm_i915_private *dev_priv = dev->dev_private;
14519 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14520 DRM_INFO("applying backlight present quirk\n");
14521}
14522
b690e96c
JB		 14523struct intel_quirk {
14524 int device;
14525 int subsystem_vendor;
14526 int subsystem_device;
14527 void (*hook)(struct drm_device *dev);
14528};
14529
5f85f176
EE		 14530/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14531struct intel_dmi_quirk {
14532 void (*hook)(struct drm_device *dev);
14533 const struct dmi_system_id (*dmi_id_list)[];
14534};
14535
14536static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14537{
14538 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14539 return 1;
14540}
14541
14542static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14543 {
14544 .dmi_id_list = &(const struct dmi_system_id[]) {
14545 {
14546 .callback = intel_dmi_reverse_brightness,
14547 .ident = "NCR Corporation",
14548 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14549 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14550 },
14551 },
14552 { } /* terminating entry */
14553 },
14554 .hook = quirk_invert_brightness,
14555 },
14556};
14557
c43b5634 14558static struct intel_quirk intel_quirks[] = {
b690e96c 14559 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 14560 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 14561
b690e96c
JB		 14562 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14563 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14564
b690e96c
JB		 14565 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14566 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14567
5f080c0f
VS		 14568 /* 830 needs to leave pipe A & dpll A up */
14569 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14570
b6b5d049
VS		 14571 /* 830 needs to leave pipe B & dpll B up */
14572 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14573
435793df
KP		 14574 /* Lenovo U160 cannot use SSC on LVDS */
14575 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 14576
14577 /* Sony Vaio Y cannot use SSC on LVDS */
14578 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 14579
be505f64
AH		 14580 /* Acer Aspire 5734Z must invert backlight brightness */
14581 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14582
14583 /* Acer/eMachines G725 */
14584 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14585
14586 /* Acer/eMachines e725 */
14587 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14588
14589 /* Acer/Packard Bell NCL20 */
14590 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14591
14592 /* Acer Aspire 4736Z */
14593 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
0f540c3a
JN		 14594
14595 /* Acer Aspire 5336 */
14596 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
2e93a1aa
SD		 14597
14598 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14599 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
d4967d8c 14600
dfb3d47b
SD		 14601 /* Acer C720 Chromebook (Core i3 4005U) */
14602 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14603
b2a9601c 14604 /* Apple Macbook 2,1 (Core 2 T7400) */
14605 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14606
d4967d8c
SD		 14607 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14608 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
724cb06f
SD		 14609
14610 /* HP Chromebook 14 (Celeron 2955U) */
14611 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
cf6f0af9
JN		 14612
14613 /* Dell Chromebook 11 */
14614 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
b690e96c
JB		 14615};
14616
14617static void intel_init_quirks(struct drm_device *dev)
14618{
14619 struct pci_dev *d = dev->pdev;
14620 int i;
14621
14622 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14623 struct intel_quirk *q = &intel_quirks[i];
14624
14625 if (d->device == q->device &&
14626 (d->subsystem_vendor == q->subsystem_vendor ||
14627 q->subsystem_vendor == PCI_ANY_ID) &&
14628 (d->subsystem_device == q->subsystem_device ||
14629 q->subsystem_device == PCI_ANY_ID))
14630 q->hook(dev);
14631 }
5f85f176
EE		 14632 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14633 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14634 intel_dmi_quirks[i].hook(dev);
14635 }
b690e96c
JB		 14636}
14637
9cce37f4
JB		 14638/* Disable the VGA plane that we never use */
14639static void i915_disable_vga(struct drm_device *dev)
14640{
14641 struct drm_i915_private *dev_priv = dev->dev_private;
14642 u8 sr1;
766aa1c4 14643 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4 14644
2b37c616 14645 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
9cce37f4 14646 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 14647 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 14648 sr1 = inb(VGA_SR_DATA);
14649 outb(sr1 | 1<<5, VGA_SR_DATA);
14650 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14651 udelay(300);
14652
01f5a626 14653 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9cce37f4
JB		 14654 POSTING_READ(vga_reg);
14655}
14656
f817586c
DV		 14657void intel_modeset_init_hw(struct drm_device *dev)
14658{
a8f78b58
ED		 14659 intel_prepare_ddi(dev);
14660
f8bf63fd
VS		 14661 if (IS_VALLEYVIEW(dev))
14662 vlv_update_cdclk(dev);
14663
f817586c
DV		 14664 intel_init_clock_gating(dev);
14665
8090c6b9 14666 intel_enable_gt_powersave(dev);
f817586c
DV		 14667}
14668
79e53945
JB		 14669void intel_modeset_init(struct drm_device *dev)
14670{
652c393a 14671 struct drm_i915_private *dev_priv = dev->dev_private;
1fe47785 14672 int sprite, ret;
8cc87b75 14673 enum pipe pipe;
46f297fb 14674 struct intel_crtc *crtc;
79e53945
JB		 14675
14676 drm_mode_config_init(dev);
14677
14678 dev->mode_config.min_width = 0;
14679 dev->mode_config.min_height = 0;
14680
019d96cb
DA		 14681 dev->mode_config.preferred_depth = 24;
14682 dev->mode_config.prefer_shadow = 1;
14683
25bab385
TU		 14684 dev->mode_config.allow_fb_modifiers = true;
14685
e6ecefaa 14686 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 14687
b690e96c
JB		 14688 intel_init_quirks(dev);
14689
1fa61106
ED		 14690 intel_init_pm(dev);
14691
e3c74757
BW		 14692 if (INTEL_INFO(dev)->num_pipes == 0)
14693 return;
14694
e70236a8 14695 intel_init_display(dev);
7c10a2b5 14696 intel_init_audio(dev);
e70236a8 14697
a6c45cf0
CW		 14698 if (IS_GEN2(dev)) {
14699 dev->mode_config.max_width = 2048;
14700 dev->mode_config.max_height = 2048;
14701 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 14702 dev->mode_config.max_width = 4096;
14703 dev->mode_config.max_height = 4096;
79e53945 14704 } else {
a6c45cf0
CW		 14705 dev->mode_config.max_width = 8192;
14706 dev->mode_config.max_height = 8192;
79e53945 14707 }
068be561 14708
dc41c154
VS		 14709 if (IS_845G(dev) || IS_I865G(dev)) {
14710 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14711 dev->mode_config.cursor_height = 1023;
14712 } else if (IS_GEN2(dev)) {
068be561
DL		 14713 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14714 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14715 } else {
14716 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14717 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14718 }
14719
5d4545ae 14720 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 14721
28c97730 14722 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 14723 INTEL_INFO(dev)->num_pipes,
14724 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 14725
055e393f 14726 for_each_pipe(dev_priv, pipe) {
8cc87b75 14727 intel_crtc_init(dev, pipe);
3bdcfc0c 14728 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 14729 ret = intel_plane_init(dev, pipe, sprite);
7f1f3851 14730 if (ret)
06da8da2 14731 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
1fe47785 14732 pipe_name(pipe), sprite_name(pipe, sprite), ret);
7f1f3851 14733 }
79e53945
JB		 14734 }
14735
f42bb70d
JB		 14736 intel_init_dpio(dev);
14737
e72f9fbf 14738 intel_shared_dpll_init(dev);
ee7b9f93 14739
9cce37f4
JB		 14740 /* Just disable it once at startup */
14741 i915_disable_vga(dev);
79e53945 14742 intel_setup_outputs(dev);
11be49eb
CW		 14743
14744 /* Just in case the BIOS is doing something questionable. */
7ff0ebcc 14745 intel_fbc_disable(dev);
fa9fa083 14746
6e9f798d 14747 drm_modeset_lock_all(dev);
fa9fa083 14748 intel_modeset_setup_hw_state(dev, false);
6e9f798d 14749 drm_modeset_unlock_all(dev);
46f297fb 14750
d3fcc808 14751 for_each_intel_crtc(dev, crtc) {
46f297fb
JB		 14752 if (!crtc->active)
14753 continue;
14754
46f297fb 14755 /*
46f297fb
JB		 14756 * Note that reserving the BIOS fb up front prevents us
14757 * from stuffing other stolen allocations like the ring
14758 * on top. This prevents some ugliness at boot time, and
14759 * can even allow for smooth boot transitions if the BIOS
14760 * fb is large enough for the active pipe configuration.
14761 */
5724dbd1
DL		 14762 if (dev_priv->display.get_initial_plane_config) {
14763 dev_priv->display.get_initial_plane_config(crtc,
46f297fb
JB		 14764 &crtc->plane_config);
14765 /*
14766 * If the fb is shared between multiple heads, we'll
14767 * just get the first one.
14768 */
f6936e29 14769 intel_find_initial_plane_obj(crtc, &crtc->plane_config);
46f297fb 14770 }
46f297fb 14771 }
2c7111db
CW		 14772}
14773
7fad798e
DV		 14774static void intel_enable_pipe_a(struct drm_device *dev)
14775{
14776 struct intel_connector *connector;
14777 struct drm_connector *crt = NULL;
14778 struct intel_load_detect_pipe load_detect_temp;
208bf9fd 14779 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
7fad798e
DV		 14780
14781 /* We can't just switch on the pipe A, we need to set things up with a
14782 * proper mode and output configuration. As a gross hack, enable pipe A
14783 * by enabling the load detect pipe once. */
3a3371ff 14784 for_each_intel_connector(dev, connector) {
7fad798e
DV		 14785 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14786 crt = &connector->base;
14787 break;
14788 }
14789 }
14790
14791 if (!crt)
14792 return;
14793
208bf9fd 14794 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
49172fee 14795 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
7fad798e
DV		 14796}
14797
fa555837
DV		 14798static bool
14799intel_check_plane_mapping(struct intel_crtc *crtc)
14800{
7eb552ae
BW		 14801 struct drm_device *dev = crtc->base.dev;
14802 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 14803 u32 reg, val;
14804
7eb552ae 14805 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 14806 return true;
14807
14808 reg = DSPCNTR(!crtc->plane);
14809 val = I915_READ(reg);
14810
14811 if ((val & DISPLAY_PLANE_ENABLE) &&
14812 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14813 return false;
14814
14815 return true;
14816}
14817
24929352
DV		 14818static void intel_sanitize_crtc(struct intel_crtc *crtc)
14819{
14820 struct drm_device *dev = crtc->base.dev;
14821 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 14822 u32 reg;
24929352 14823
24929352 14824 /* Clear any frame start delays used for debugging left by the BIOS */
6e3c9717 14825 reg = PIPECONF(crtc->config->cpu_transcoder);
24929352
DV		 14826 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14827
d3eaf884 14828 /* restore vblank interrupts to correct state */
9625604c 14829 drm_crtc_vblank_reset(&crtc->base);
d297e103
VS		 14830 if (crtc->active) {
14831 update_scanline_offset(crtc);
9625604c
DV		 14832 drm_crtc_vblank_on(&crtc->base);
14833 }
d3eaf884 14834
24929352 14835 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 14836 * disable the crtc (and hence change the state) if it is wrong. Note
14837 * that gen4+ has a fixed plane -> pipe mapping. */
14838 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 14839 struct intel_connector *connector;
14840 bool plane;
14841
24929352
DV		 14842 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14843 crtc->base.base.id);
14844
14845 /* Pipe has the wrong plane attached and the plane is active.
14846 * Temporarily change the plane mapping and disable everything
14847 * ... */
14848 plane = crtc->plane;
b70709a6 14849 to_intel_plane_state(crtc->base.primary->state)->visible = true;
24929352 14850 crtc->plane = !plane;
ce22dba9 14851 intel_crtc_disable_planes(&crtc->base);
24929352
DV		 14852 dev_priv->display.crtc_disable(&crtc->base);
14853 crtc->plane = plane;
14854
14855 /* ... and break all links. */
3a3371ff 14856 for_each_intel_connector(dev, connector) {
24929352
DV		 14857 if (connector->encoder->base.crtc != &crtc->base)
14858 continue;
14859
7f1950fb
EE		 14860 connector->base.dpms = DRM_MODE_DPMS_OFF;
14861 connector->base.encoder = NULL;
24929352 14862 }
7f1950fb
EE		 14863 /* multiple connectors may have the same encoder:
14864 * handle them and break crtc link separately */
3a3371ff 14865 for_each_intel_connector(dev, connector)
7f1950fb
EE		 14866 if (connector->encoder->base.crtc == &crtc->base) {
14867 connector->encoder->base.crtc = NULL;
14868 connector->encoder->connectors_active = false;
14869 }
24929352
DV		 14870
14871 WARN_ON(crtc->active);
83d65738 14872 crtc->base.state->enable = false;
24929352
DV		 14873 crtc->base.enabled = false;
14874 }
24929352 14875
7fad798e
DV		 14876 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
14877 crtc->pipe == PIPE_A && !crtc->active) {
14878 /* BIOS forgot to enable pipe A, this mostly happens after
14879 * resume. Force-enable the pipe to fix this, the update_dpms
14880 * call below we restore the pipe to the right state, but leave
14881 * the required bits on. */
14882 intel_enable_pipe_a(dev);
14883 }
14884
24929352
DV		 14885 /* Adjust the state of the output pipe according to whether we
14886 * have active connectors/encoders. */
14887 intel_crtc_update_dpms(&crtc->base);
14888
83d65738 14889 if (crtc->active != crtc->base.state->enable) {
24929352
DV		 14890 struct intel_encoder *encoder;
14891
14892 /* This can happen either due to bugs in the get_hw_state
14893 * functions or because the pipe is force-enabled due to the
14894 * pipe A quirk. */
14895 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
14896 crtc->base.base.id,
83d65738 14897 crtc->base.state->enable ? "enabled" : "disabled",
24929352
DV		 14898 crtc->active ? "enabled" : "disabled");
14899
83d65738 14900 crtc->base.state->enable = crtc->active;
24929352
DV		 14901 crtc->base.enabled = crtc->active;
14902
14903 /* Because we only establish the connector -> encoder ->
14904 * crtc links if something is active, this means the
14905 * crtc is now deactivated. Break the links. connector
14906 * -> encoder links are only establish when things are
14907 * actually up, hence no need to break them. */
14908 WARN_ON(crtc->active);
14909
14910 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
14911 WARN_ON(encoder->connectors_active);
14912 encoder->base.crtc = NULL;
14913 }
14914 }
c5ab3bc0 14915
a3ed6aad 14916 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
4cc31489
DV		 14917 /*
14918 * We start out with underrun reporting disabled to avoid races.
14919 * For correct bookkeeping mark this on active crtcs.
14920 *
c5ab3bc0
DV		 14921 * Also on gmch platforms we dont have any hardware bits to
14922 * disable the underrun reporting. Which means we need to start
14923 * out with underrun reporting disabled also on inactive pipes,
14924 * since otherwise we'll complain about the garbage we read when
14925 * e.g. coming up after runtime pm.
14926 *
4cc31489
DV		 14927 * No protection against concurrent access is required - at
14928 * worst a fifo underrun happens which also sets this to false.
14929 */
14930 crtc->cpu_fifo_underrun_disabled = true;
14931 crtc->pch_fifo_underrun_disabled = true;
14932 }
24929352
DV		 14933}
14934
14935static void intel_sanitize_encoder(struct intel_encoder *encoder)
14936{
14937 struct intel_connector *connector;
14938 struct drm_device *dev = encoder->base.dev;
14939
14940 /* We need to check both for a crtc link (meaning that the
14941 * encoder is active and trying to read from a pipe) and the
14942 * pipe itself being active. */
14943 bool has_active_crtc = encoder->base.crtc &&
14944 to_intel_crtc(encoder->base.crtc)->active;
14945
14946 if (encoder->connectors_active && !has_active_crtc) {
14947 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14948 encoder->base.base.id,
8e329a03 14949 encoder->base.name);
24929352
DV		 14950
14951 /* Connector is active, but has no active pipe. This is
14952 * fallout from our resume register restoring. Disable
14953 * the encoder manually again. */
14954 if (encoder->base.crtc) {
14955 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14956 encoder->base.base.id,
8e329a03 14957 encoder->base.name);
24929352 14958 encoder->disable(encoder);
a62d1497
VS		 14959 if (encoder->post_disable)
14960 encoder->post_disable(encoder);
24929352 14961 }
7f1950fb
EE		 14962 encoder->base.crtc = NULL;
14963 encoder->connectors_active = false;
24929352
DV		 14964
14965 /* Inconsistent output/port/pipe state happens presumably due to
14966 * a bug in one of the get_hw_state functions. Or someplace else
14967 * in our code, like the register restore mess on resume. Clamp
14968 * things to off as a safer default. */
3a3371ff 14969 for_each_intel_connector(dev, connector) {
24929352
DV		 14970 if (connector->encoder != encoder)
14971 continue;
7f1950fb
EE		 14972 connector->base.dpms = DRM_MODE_DPMS_OFF;
14973 connector->base.encoder = NULL;
24929352
DV		 14974 }
14975 }
14976 /* Enabled encoders without active connectors will be fixed in
14977 * the crtc fixup. */
14978}
14979
04098753 14980void i915_redisable_vga_power_on(struct drm_device *dev)
0fde901f
KM		 14981{
14982 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 14983 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 14984
04098753
ID		 14985 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
14986 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
14987 i915_disable_vga(dev);
14988 }
14989}
14990
14991void i915_redisable_vga(struct drm_device *dev)
14992{
14993 struct drm_i915_private *dev_priv = dev->dev_private;
14994
8dc8a27c
PZ		 14995 /* This function can be called both from intel_modeset_setup_hw_state or
14996 * at a very early point in our resume sequence, where the power well
14997 * structures are not yet restored. Since this function is at a very
14998 * paranoid "someone might have enabled VGA while we were not looking"
14999 * level, just check if the power well is enabled instead of trying to
15000 * follow the "don't touch the power well if we don't need it" policy
15001 * the rest of the driver uses. */
f458ebbc 15002 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
8dc8a27c
PZ		 15003 return;
15004
04098753 15005 i915_redisable_vga_power_on(dev);
0fde901f
KM		 15006}
15007
98ec7739
VS		 15008static bool primary_get_hw_state(struct intel_crtc *crtc)
15009{
15010 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
15011
15012 if (!crtc->active)
15013 return false;
15014
15015 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
15016}
15017
30e984df 15018static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 15019{
15020 struct drm_i915_private *dev_priv = dev->dev_private;
15021 enum pipe pipe;
24929352
DV		 15022 struct intel_crtc *crtc;
15023 struct intel_encoder *encoder;
15024 struct intel_connector *connector;
5358901f 15025 int i;
24929352 15026
d3fcc808 15027 for_each_intel_crtc(dev, crtc) {
b70709a6
ML		 15028 struct drm_plane *primary = crtc->base.primary;
15029 struct intel_plane_state *plane_state;
15030
6e3c9717 15031 memset(crtc->config, 0, sizeof(*crtc->config));
3b117c8f 15032
6e3c9717 15033 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
9953599b 15034
0e8ffe1b 15035 crtc->active = dev_priv->display.get_pipe_config(crtc,
6e3c9717 15036 crtc->config);
24929352 15037
83d65738 15038 crtc->base.state->enable = crtc->active;
24929352 15039 crtc->base.enabled = crtc->active;
b70709a6
ML		 15040
15041 plane_state = to_intel_plane_state(primary->state);
15042 plane_state->visible = primary_get_hw_state(crtc);
24929352
DV		 15043
15044 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15045 crtc->base.base.id,
15046 crtc->active ? "enabled" : "disabled");
15047 }
15048
5358901f
DV		 15049 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15050 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15051
3e369b76
ACO		 15052 pll->on = pll->get_hw_state(dev_priv, pll,
15053 &pll->config.hw_state);
5358901f 15054 pll->active = 0;
3e369b76 15055 pll->config.crtc_mask = 0;
d3fcc808 15056 for_each_intel_crtc(dev, crtc) {
1e6f2ddc 15057 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
5358901f 15058 pll->active++;
3e369b76 15059 pll->config.crtc_mask |= 1 << crtc->pipe;
1e6f2ddc 15060 }
5358901f 15061 }
5358901f 15062
1e6f2ddc 15063 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
3e369b76 15064 pll->name, pll->config.crtc_mask, pll->on);
bd2bb1b9 15065
3e369b76 15066 if (pll->config.crtc_mask)
bd2bb1b9 15067 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5358901f
DV		 15068 }
15069
b2784e15 15070 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15071 pipe = 0;
15072
15073 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 15074 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15075 encoder->base.crtc = &crtc->base;
6e3c9717 15076 encoder->get_config(encoder, crtc->config);
24929352
DV		 15077 } else {
15078 encoder->base.crtc = NULL;
15079 }
15080
15081 encoder->connectors_active = false;
6f2bcceb 15082 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
24929352 15083 encoder->base.base.id,
8e329a03 15084 encoder->base.name,
24929352 15085 encoder->base.crtc ? "enabled" : "disabled",
6f2bcceb 15086 pipe_name(pipe));
24929352
DV		 15087 }
15088
3a3371ff 15089 for_each_intel_connector(dev, connector) {
24929352
DV		 15090 if (connector->get_hw_state(connector)) {
15091 connector->base.dpms = DRM_MODE_DPMS_ON;
15092 connector->encoder->connectors_active = true;
15093 connector->base.encoder = &connector->encoder->base;
15094 } else {
15095 connector->base.dpms = DRM_MODE_DPMS_OFF;
15096 connector->base.encoder = NULL;
15097 }
15098 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15099 connector->base.base.id,
c23cc417 15100 connector->base.name,
24929352
DV		 15101 connector->base.encoder ? "enabled" : "disabled");
15102 }
30e984df
DV		 15103}
15104
15105/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
15106 * and i915 state tracking structures. */
15107void intel_modeset_setup_hw_state(struct drm_device *dev,
15108 bool force_restore)
15109{
15110 struct drm_i915_private *dev_priv = dev->dev_private;
15111 enum pipe pipe;
30e984df
DV		 15112 struct intel_crtc *crtc;
15113 struct intel_encoder *encoder;
35c95375 15114 int i;
30e984df
DV		 15115
15116 intel_modeset_readout_hw_state(dev);
24929352 15117
babea61d
JB		 15118 /*
15119 * Now that we have the config, copy it to each CRTC struct
15120 * Note that this could go away if we move to using crtc_config
15121 * checking everywhere.
15122 */
d3fcc808 15123 for_each_intel_crtc(dev, crtc) {
d330a953 15124 if (crtc->active && i915.fastboot) {
6e3c9717
ACO		 15125 intel_mode_from_pipe_config(&crtc->base.mode,
15126 crtc->config);
babea61d
JB		 15127 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
15128 crtc->base.base.id);
15129 drm_mode_debug_printmodeline(&crtc->base.mode);
15130 }
15131 }
15132
24929352 15133 /* HW state is read out, now we need to sanitize this mess. */
b2784e15 15134 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15135 intel_sanitize_encoder(encoder);
15136 }
15137
055e393f 15138 for_each_pipe(dev_priv, pipe) {
24929352
DV		 15139 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15140 intel_sanitize_crtc(crtc);
6e3c9717
ACO		 15141 intel_dump_pipe_config(crtc, crtc->config,
15142 "[setup_hw_state]");
24929352 15143 }
9a935856 15144
d29b2f9d
ACO		 15145 intel_modeset_update_connector_atomic_state(dev);
15146
35c95375
DV		 15147 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15148 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15149
15150 if (!pll->on || pll->active)
15151 continue;
15152
15153 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15154
15155 pll->disable(dev_priv, pll);
15156 pll->on = false;
15157 }
15158
3078999f
PB		 15159 if (IS_GEN9(dev))
15160 skl_wm_get_hw_state(dev);
15161 else if (HAS_PCH_SPLIT(dev))
243e6a44
VS		 15162 ilk_wm_get_hw_state(dev);
15163
45e2b5f6 15164 if (force_restore) {
7d0bc1ea
VS		 15165 i915_redisable_vga(dev);
15166
f30da187
DV		 15167 /*
15168 * We need to use raw interfaces for restoring state to avoid
15169 * checking (bogus) intermediate states.
15170 */
055e393f 15171 for_each_pipe(dev_priv, pipe) {
b5644d05
JB		 15172 struct drm_crtc *crtc =
15173 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187 15174
83a57153 15175 intel_crtc_restore_mode(crtc);
45e2b5f6
DV		 15176 }
15177 } else {
15178 intel_modeset_update_staged_output_state(dev);
15179 }
8af6cf88
DV		 15180
15181 intel_modeset_check_state(dev);
2c7111db
CW		 15182}
15183
15184void intel_modeset_gem_init(struct drm_device *dev)
15185{
92122789 15186 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd 15187 struct drm_crtc *c;
2ff8fde1 15188 struct drm_i915_gem_object *obj;
e0d6149b 15189 int ret;
484b41dd 15190
ae48434c
ID		 15191 mutex_lock(&dev->struct_mutex);
15192 intel_init_gt_powersave(dev);
15193 mutex_unlock(&dev->struct_mutex);
15194
92122789
JB		 15195 /*
15196 * There may be no VBT; and if the BIOS enabled SSC we can
15197 * just keep using it to avoid unnecessary flicker. Whereas if the
15198 * BIOS isn't using it, don't assume it will work even if the VBT
15199 * indicates as much.
15200 */
15201 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
15202 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15203 DREF_SSC1_ENABLE);
15204
1833b134 15205 intel_modeset_init_hw(dev);
02e792fb
DV		 15206
15207 intel_setup_overlay(dev);
484b41dd
JB		 15208
15209 /*
15210 * Make sure any fbs we allocated at startup are properly
15211 * pinned & fenced. When we do the allocation it's too early
15212 * for this.
15213 */
70e1e0ec 15214 for_each_crtc(dev, c) {
2ff8fde1
MR		 15215 obj = intel_fb_obj(c->primary->fb);
15216 if (obj == NULL)
484b41dd
JB		 15217 continue;
15218
e0d6149b
TU		 15219 mutex_lock(&dev->struct_mutex);
15220 ret = intel_pin_and_fence_fb_obj(c->primary,
15221 c->primary->fb,
15222 c->primary->state,
15223 NULL);
15224 mutex_unlock(&dev->struct_mutex);
15225 if (ret) {
484b41dd
JB		 15226 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15227 to_intel_crtc(c)->pipe);
66e514c1
DA		 15228 drm_framebuffer_unreference(c->primary->fb);
15229 c->primary->fb = NULL;
afd65eb4 15230 update_state_fb(c->primary);
484b41dd
JB		 15231 }
15232 }
0962c3c9
VS		 15233
15234 intel_backlight_register(dev);
79e53945
JB		 15235}
15236
4932e2c3
ID		 15237void intel_connector_unregister(struct intel_connector *intel_connector)
15238{
15239 struct drm_connector *connector = &intel_connector->base;
15240
15241 intel_panel_destroy_backlight(connector);
34ea3d38 15242 drm_connector_unregister(connector);
4932e2c3
ID		 15243}
15244
79e53945
JB		 15245void intel_modeset_cleanup(struct drm_device *dev)
15246{
652c393a 15247 struct drm_i915_private *dev_priv = dev->dev_private;
d9255d57 15248 struct drm_connector *connector;
652c393a 15249
2eb5252e
ID		 15250 intel_disable_gt_powersave(dev);
15251
0962c3c9
VS		 15252 intel_backlight_unregister(dev);
15253
fd0c0642
DV		 15254 /*
15255 * Interrupts and polling as the first thing to avoid creating havoc.
2eb5252e 15256 * Too much stuff here (turning of connectors, ...) would
fd0c0642
DV		 15257 * experience fancy races otherwise.
15258 */
2aeb7d3a 15259 intel_irq_uninstall(dev_priv);
eb21b92b 15260
fd0c0642
DV		 15261 /*
15262 * Due to the hpd irq storm handling the hotplug work can re-arm the
15263 * poll handlers. Hence disable polling after hpd handling is shut down.
15264 */
f87ea761 15265 drm_kms_helper_poll_fini(dev);
fd0c0642 15266
652c393a
JB		 15267 mutex_lock(&dev->struct_mutex);
15268
723bfd70
JB		 15269 intel_unregister_dsm_handler();
15270
7ff0ebcc 15271 intel_fbc_disable(dev);
e70236a8 15272
69341a5e
KH		 15273 mutex_unlock(&dev->struct_mutex);
15274
1630fe75
CW		 15275 /* flush any delayed tasks or pending work */
15276 flush_scheduled_work();
15277
db31af1d
JN		 15278 /* destroy the backlight and sysfs files before encoders/connectors */
15279 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4932e2c3
ID		 15280 struct intel_connector *intel_connector;
15281
15282 intel_connector = to_intel_connector(connector);
15283 intel_connector->unregister(intel_connector);
db31af1d 15284 }
d9255d57 15285
79e53945 15286 drm_mode_config_cleanup(dev);
4d7bb011
DV		 15287
15288 intel_cleanup_overlay(dev);
ae48434c
ID		 15289
15290 mutex_lock(&dev->struct_mutex);
15291 intel_cleanup_gt_powersave(dev);
15292 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 15293}
15294
f1c79df3
ZW		 15295/*
15296 * Return which encoder is currently attached for connector.
15297 */
df0e9248 15298struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 15299{
df0e9248
CW		 15300 return &intel_attached_encoder(connector)->base;
15301}
f1c79df3 15302
df0e9248
CW		 15303void intel_connector_attach_encoder(struct intel_connector *connector,
15304 struct intel_encoder *encoder)
15305{
15306 connector->encoder = encoder;
15307 drm_mode_connector_attach_encoder(&connector->base,
15308 &encoder->base);
79e53945 15309}
28d52043
DA		 15310
15311/*
15312 * set vga decode state - true == enable VGA decode
15313 */
15314int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15315{
15316 struct drm_i915_private *dev_priv = dev->dev_private;
a885b3cc 15317 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
28d52043
DA		 15318 u16 gmch_ctrl;
15319
75fa041d
CW		 15320 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15321 DRM_ERROR("failed to read control word\n");
15322 return -EIO;
15323 }
15324
c0cc8a55
CW		 15325 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15326 return 0;
15327
28d52043
DA		 15328 if (state)
15329 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15330 else
15331 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
75fa041d
CW		 15332
15333 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15334 DRM_ERROR("failed to write control word\n");
15335 return -EIO;
15336 }
15337
28d52043
DA		 15338 return 0;
15339}
c4a1d9e4 15340
c4a1d9e4 15341struct intel_display_error_state {
ff57f1b0
PZ		 15342
15343 u32 power_well_driver;
15344
63b66e5b
CW		 15345 int num_transcoders;
15346
c4a1d9e4
CW		 15347 struct intel_cursor_error_state {
15348 u32 control;
15349 u32 position;
15350 u32 base;
15351 u32 size;
52331309 15352 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 15353
15354 struct intel_pipe_error_state {
ddf9c536 15355 bool power_domain_on;
c4a1d9e4 15356 u32 source;
f301b1e1 15357 u32 stat;
52331309 15358 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 15359
15360 struct intel_plane_error_state {
15361 u32 control;
15362 u32 stride;
15363 u32 size;
15364 u32 pos;
15365 u32 addr;
15366 u32 surface;
15367 u32 tile_offset;
52331309 15368 } plane[I915_MAX_PIPES];
63b66e5b
CW		 15369
15370 struct intel_transcoder_error_state {
ddf9c536 15371 bool power_domain_on;
63b66e5b
CW		 15372 enum transcoder cpu_transcoder;
15373
15374 u32 conf;
15375
15376 u32 htotal;
15377 u32 hblank;
15378 u32 hsync;
15379 u32 vtotal;
15380 u32 vblank;
15381 u32 vsync;
15382 } transcoder[4];
c4a1d9e4
CW		 15383};
15384
15385struct intel_display_error_state *
15386intel_display_capture_error_state(struct drm_device *dev)
15387{
fbee40df 15388 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4 15389 struct intel_display_error_state *error;
63b66e5b
CW		 15390 int transcoders[] = {
15391 TRANSCODER_A,
15392 TRANSCODER_B,
15393 TRANSCODER_C,
15394 TRANSCODER_EDP,
15395 };
c4a1d9e4
CW		 15396 int i;
15397
63b66e5b
CW		 15398 if (INTEL_INFO(dev)->num_pipes == 0)
15399 return NULL;
15400
9d1cb914 15401 error = kzalloc(sizeof(*error), GFP_ATOMIC);
c4a1d9e4
CW		 15402 if (error == NULL)
15403 return NULL;
15404
190be112 15405 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ff57f1b0
PZ		 15406 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15407
055e393f 15408 for_each_pipe(dev_priv, i) {
ddf9c536 15409 error->pipe[i].power_domain_on =
f458ebbc
DV		 15410 __intel_display_power_is_enabled(dev_priv,
15411 POWER_DOMAIN_PIPE(i));
ddf9c536 15412 if (!error->pipe[i].power_domain_on)
9d1cb914
PZ		 15413 continue;
15414
5efb3e28
VS		 15415 error->cursor[i].control = I915_READ(CURCNTR(i));
15416 error->cursor[i].position = I915_READ(CURPOS(i));
15417 error->cursor[i].base = I915_READ(CURBASE(i));
c4a1d9e4
CW		 15418
15419 error->plane[i].control = I915_READ(DSPCNTR(i));
15420 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 15421 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 15422 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 15423 error->plane[i].pos = I915_READ(DSPPOS(i));
15424 }
ca291363
PZ		 15425 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15426 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 15427 if (INTEL_INFO(dev)->gen >= 4) {
15428 error->plane[i].surface = I915_READ(DSPSURF(i));
15429 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15430 }
15431
c4a1d9e4 15432 error->pipe[i].source = I915_READ(PIPESRC(i));
f301b1e1 15433
3abfce77 15434 if (HAS_GMCH_DISPLAY(dev))
f301b1e1 15435 error->pipe[i].stat = I915_READ(PIPESTAT(i));
63b66e5b
CW		 15436 }
15437
15438 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15439 if (HAS_DDI(dev_priv->dev))
15440 error->num_transcoders++; /* Account for eDP. */
15441
15442 for (i = 0; i < error->num_transcoders; i++) {
15443 enum transcoder cpu_transcoder = transcoders[i];
15444
ddf9c536 15445 error->transcoder[i].power_domain_on =
f458ebbc 15446 __intel_display_power_is_enabled(dev_priv,
38cc1daf 15447 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
ddf9c536 15448 if (!error->transcoder[i].power_domain_on)
9d1cb914
PZ		 15449 continue;
15450
63b66e5b
CW		 15451 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15452
15453 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15454 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15455 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15456 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15457 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15458 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15459 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 15460 }
15461
15462 return error;
15463}
15464
edc3d884
MK		 15465#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15466
c4a1d9e4 15467void
edc3d884 15468intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 15469 struct drm_device *dev,
15470 struct intel_display_error_state *error)
15471{
055e393f 15472 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4
CW		 15473 int i;
15474
63b66e5b
CW		 15475 if (!error)
15476 return;
15477
edc3d884 15478 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
190be112 15479 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
edc3d884 15480 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 15481 error->power_well_driver);
055e393f 15482 for_each_pipe(dev_priv, i) {
edc3d884 15483 err_printf(m, "Pipe [%d]:\n", i);
ddf9c536
ID		 15484 err_printf(m, " Power: %s\n",
15485 error->pipe[i].power_domain_on ? "on" : "off");
edc3d884 15486 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
f301b1e1 15487 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
edc3d884
MK		 15488
15489 err_printf(m, "Plane [%d]:\n", i);
15490 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15491 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 15492 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 15493 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15494 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 15495 }
4b71a570 15496 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 15497 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 15498 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 15499 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15500 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 15501 }
15502
edc3d884
MK		 15503 err_printf(m, "Cursor [%d]:\n", i);
15504 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15505 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15506 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 15507 }
63b66e5b
CW		 15508
15509 for (i = 0; i < error->num_transcoders; i++) {
1cf84bb6 15510 err_printf(m, "CPU transcoder: %c\n",
63b66e5b 15511 transcoder_name(error->transcoder[i].cpu_transcoder));
ddf9c536
ID		 15512 err_printf(m, " Power: %s\n",
15513 error->transcoder[i].power_domain_on ? "on" : "off");
63b66e5b
CW		 15514 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15515 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15516 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15517 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15518 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15519 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15520 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15521 }
c4a1d9e4 15522}
e2fcdaa9
VS		 15523
15524void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15525{
15526 struct intel_crtc *crtc;
15527
15528 for_each_intel_crtc(dev, crtc) {
15529 struct intel_unpin_work *work;
e2fcdaa9 15530
5e2d7afc 15531 spin_lock_irq(&dev->event_lock);
e2fcdaa9
VS		 15532
15533 work = crtc->unpin_work;
15534
15535 if (work && work->event &&
15536 work->event->base.file_priv == file) {
15537 kfree(work->event);
15538 work->event = NULL;
15539 }
15540
5e2d7afc 15541 spin_unlock_irq(&dev->event_lock);
e2fcdaa9
VS		 15542 }
15543}
Linux 6.x block layer and io_uring tree(s)