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drm/i915: Implement WaPixelRepeatModeFixForC0:chv
[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
db18b6a6 39#include "intel_dsi.h"
e5510fac 40#include "i915_trace.h"
319c1d42 41#include <drm/drm_atomic.h>
c196e1d6 42#include <drm/drm_atomic_helper.h>
760285e7
DH		 43#include <drm/drm_dp_helper.h>
44#include <drm/drm_crtc_helper.h>
465c120c
MR		 45#include <drm/drm_plane_helper.h>
46#include <drm/drm_rect.h>
c0f372b3 47#include <linux/dma_remapping.h>
fd8e058a
AG		 48#include <linux/reservation.h>
49#include <linux/dma-buf.h>
79e53945 50
465c120c 51/* Primary plane formats for gen <= 3 */
568db4f2 52static const uint32_t i8xx_primary_formats[] = {
67fe7dc5
DL		 53 DRM_FORMAT_C8,
54 DRM_FORMAT_RGB565,
465c120c 55 DRM_FORMAT_XRGB1555,
67fe7dc5 56 DRM_FORMAT_XRGB8888,
465c120c
MR		 57};
58
59/* Primary plane formats for gen >= 4 */
568db4f2 60static const uint32_t i965_primary_formats[] = {
6c0fd451
DL		 61 DRM_FORMAT_C8,
62 DRM_FORMAT_RGB565,
63 DRM_FORMAT_XRGB8888,
64 DRM_FORMAT_XBGR8888,
65 DRM_FORMAT_XRGB2101010,
66 DRM_FORMAT_XBGR2101010,
67};
68
69static const uint32_t skl_primary_formats[] = {
67fe7dc5
DL		 70 DRM_FORMAT_C8,
71 DRM_FORMAT_RGB565,
72 DRM_FORMAT_XRGB8888,
465c120c 73 DRM_FORMAT_XBGR8888,
67fe7dc5 74 DRM_FORMAT_ARGB8888,
465c120c
MR		 75 DRM_FORMAT_ABGR8888,
76 DRM_FORMAT_XRGB2101010,
465c120c 77 DRM_FORMAT_XBGR2101010,
ea916ea0
KM		 78 DRM_FORMAT_YUYV,
79 DRM_FORMAT_YVYU,
80 DRM_FORMAT_UYVY,
81 DRM_FORMAT_VYUY,
465c120c
MR		 82};
83
3d7d6510
MR		 84/* Cursor formats */
85static const uint32_t intel_cursor_formats[] = {
86 DRM_FORMAT_ARGB8888,
87};
88
f1f644dc 89static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 90 struct intel_crtc_state *pipe_config);
18442d08 91static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 92 struct intel_crtc_state *pipe_config);
f1f644dc 93
eb1bfe80
JB		 94static int intel_framebuffer_init(struct drm_device *dev,
95 struct intel_framebuffer *ifb,
96 struct drm_mode_fb_cmd2 *mode_cmd,
97 struct drm_i915_gem_object *obj);
5b18e57c
DV		 98static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
99static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
bc58be60 100static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
29407aab 101static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 102 struct intel_link_m_n *m_n,
103 struct intel_link_m_n *m2_n2);
29407aab 104static void ironlake_set_pipeconf(struct drm_crtc *crtc);
229fca97 105static void haswell_set_pipeconf(struct drm_crtc *crtc);
391bf048 106static void haswell_set_pipemisc(struct drm_crtc *crtc);
d288f65f 107static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 108 const struct intel_crtc_state *pipe_config);
d288f65f 109static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 110 const struct intel_crtc_state *pipe_config);
613d2b27
ML		 111static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
112static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
549e2bfb
CK		 113static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
114 struct intel_crtc_state *crtc_state);
bfd16b2a
ML		 115static void skylake_pfit_enable(struct intel_crtc *crtc);
116static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
117static void ironlake_pfit_enable(struct intel_crtc *crtc);
043e9bda 118static void intel_modeset_setup_hw_state(struct drm_device *dev);
2622a081 119static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
e7457a9a 120
79e53945 121typedef struct {
0206e353 122 int min, max;
79e53945
JB		 123} intel_range_t;
124
125typedef struct {
0206e353
AJ		 126 int dot_limit;
127 int p2_slow, p2_fast;
79e53945
JB		 128} intel_p2_t;
129
d4906093
ML		 130typedef struct intel_limit intel_limit_t;
131struct intel_limit {
0206e353
AJ		 132 intel_range_t dot, vco, n, m, m1, m2, p, p1;
133 intel_p2_t p2;
d4906093 134};
79e53945 135
bfa7df01
VS		 136/* returns HPLL frequency in kHz */
137static int valleyview_get_vco(struct drm_i915_private *dev_priv)
138{
139 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
140
141 /* Obtain SKU information */
142 mutex_lock(&dev_priv->sb_lock);
143 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
144 CCK_FUSE_HPLL_FREQ_MASK;
145 mutex_unlock(&dev_priv->sb_lock);
146
147 return vco_freq[hpll_freq] * 1000;
148}
149
150static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
151 const char *name, u32 reg)
152{
153 u32 val;
154 int divider;
155
156 if (dev_priv->hpll_freq == 0)
157 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
158
159 mutex_lock(&dev_priv->sb_lock);
160 val = vlv_cck_read(dev_priv, reg);
161 mutex_unlock(&dev_priv->sb_lock);
162
163 divider = val & CCK_FREQUENCY_VALUES;
164
165 WARN((val & CCK_FREQUENCY_STATUS) !=
166 (divider << CCK_FREQUENCY_STATUS_SHIFT),
167 "%s change in progress\n", name);
168
169 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
170}
171
e7dc33f3
VS		 172static int
173intel_pch_rawclk(struct drm_i915_private *dev_priv)
d2acd215 174{
e7dc33f3
VS		 175 return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
176}
d2acd215 177
e7dc33f3
VS		 178static int
179intel_vlv_hrawclk(struct drm_i915_private *dev_priv)
180{
35d38d1f
VS		 181 return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
182 CCK_DISPLAY_REF_CLOCK_CONTROL);
d2acd215
DV		 183}
184
e7dc33f3
VS		 185static int
186intel_g4x_hrawclk(struct drm_i915_private *dev_priv)
79e50a4f 187{
79e50a4f
JN		 188 uint32_t clkcfg;
189
e7dc33f3 190 /* hrawclock is 1/4 the FSB frequency */
79e50a4f
JN		 191 clkcfg = I915_READ(CLKCFG);
192 switch (clkcfg & CLKCFG_FSB_MASK) {
193 case CLKCFG_FSB_400:
e7dc33f3 194 return 100000;
79e50a4f 195 case CLKCFG_FSB_533:
e7dc33f3 196 return 133333;
79e50a4f 197 case CLKCFG_FSB_667:
e7dc33f3 198 return 166667;
79e50a4f 199 case CLKCFG_FSB_800:
e7dc33f3 200 return 200000;
79e50a4f 201 case CLKCFG_FSB_1067:
e7dc33f3 202 return 266667;
79e50a4f 203 case CLKCFG_FSB_1333:
e7dc33f3 204 return 333333;
79e50a4f
JN		 205 /* these two are just a guess; one of them might be right */
206 case CLKCFG_FSB_1600:
207 case CLKCFG_FSB_1600_ALT:
e7dc33f3 208 return 400000;
79e50a4f 209 default:
e7dc33f3 210 return 133333;
79e50a4f
JN		 211 }
212}
213
e7dc33f3
VS		 214static void intel_update_rawclk(struct drm_i915_private *dev_priv)
215{
216 if (HAS_PCH_SPLIT(dev_priv))
217 dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv);
218 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
219 dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv);
220 else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
221 dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv);
222 else
223 return; /* no rawclk on other platforms, or no need to know it */
224
225 DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
226}
227
bfa7df01
VS		 228static void intel_update_czclk(struct drm_i915_private *dev_priv)
229{
666a4537 230 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
bfa7df01
VS		 231 return;
232
233 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
234 CCK_CZ_CLOCK_CONTROL);
235
236 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
237}
238
021357ac 239static inline u32 /* units of 100MHz */
21a727b3
VS		 240intel_fdi_link_freq(struct drm_i915_private *dev_priv,
241 const struct intel_crtc_state *pipe_config)
021357ac 242{
21a727b3
VS		 243 if (HAS_DDI(dev_priv))
244 return pipe_config->port_clock; /* SPLL */
245 else if (IS_GEN5(dev_priv))
246 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
e3b247da 247 else
21a727b3 248 return 270000;
021357ac
CW		 249}
250
5d536e28 251static const intel_limit_t intel_limits_i8xx_dac = {
0206e353 252 .dot = { .min = 25000, .max = 350000 },
9c333719 253 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 254 .n = { .min = 2, .max = 16 },
0206e353
AJ		 255 .m = { .min = 96, .max = 140 },
256 .m1 = { .min = 18, .max = 26 },
257 .m2 = { .min = 6, .max = 16 },
258 .p = { .min = 4, .max = 128 },
259 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 260 .p2 = { .dot_limit = 165000,
261 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 262};
263
5d536e28
DV		 264static const intel_limit_t intel_limits_i8xx_dvo = {
265 .dot = { .min = 25000, .max = 350000 },
9c333719 266 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 267 .n = { .min = 2, .max = 16 },
5d536e28
DV		 268 .m = { .min = 96, .max = 140 },
269 .m1 = { .min = 18, .max = 26 },
270 .m2 = { .min = 6, .max = 16 },
271 .p = { .min = 4, .max = 128 },
272 .p1 = { .min = 2, .max = 33 },
273 .p2 = { .dot_limit = 165000,
274 .p2_slow = 4, .p2_fast = 4 },
275};
276
e4b36699 277static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353 278 .dot = { .min = 25000, .max = 350000 },
9c333719 279 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 280 .n = { .min = 2, .max = 16 },
0206e353
AJ		 281 .m = { .min = 96, .max = 140 },
282 .m1 = { .min = 18, .max = 26 },
283 .m2 = { .min = 6, .max = 16 },
284 .p = { .min = 4, .max = 128 },
285 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 286 .p2 = { .dot_limit = 165000,
287 .p2_slow = 14, .p2_fast = 7 },
e4b36699 288};
273e27ca 289
e4b36699 290static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 291 .dot = { .min = 20000, .max = 400000 },
292 .vco = { .min = 1400000, .max = 2800000 },
293 .n = { .min = 1, .max = 6 },
294 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 295 .m1 = { .min = 8, .max = 18 },
296 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 297 .p = { .min = 5, .max = 80 },
298 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 299 .p2 = { .dot_limit = 200000,
300 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 301};
302
303static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 304 .dot = { .min = 20000, .max = 400000 },
305 .vco = { .min = 1400000, .max = 2800000 },
306 .n = { .min = 1, .max = 6 },
307 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 308 .m1 = { .min = 8, .max = 18 },
309 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 310 .p = { .min = 7, .max = 98 },
311 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 312 .p2 = { .dot_limit = 112000,
313 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 314};
315
273e27ca 316
e4b36699 317static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 318 .dot = { .min = 25000, .max = 270000 },
319 .vco = { .min = 1750000, .max = 3500000},
320 .n = { .min = 1, .max = 4 },
321 .m = { .min = 104, .max = 138 },
322 .m1 = { .min = 17, .max = 23 },
323 .m2 = { .min = 5, .max = 11 },
324 .p = { .min = 10, .max = 30 },
325 .p1 = { .min = 1, .max = 3},
326 .p2 = { .dot_limit = 270000,
327 .p2_slow = 10,
328 .p2_fast = 10
044c7c41 329 },
e4b36699
KP		 330};
331
332static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 333 .dot = { .min = 22000, .max = 400000 },
334 .vco = { .min = 1750000, .max = 3500000},
335 .n = { .min = 1, .max = 4 },
336 .m = { .min = 104, .max = 138 },
337 .m1 = { .min = 16, .max = 23 },
338 .m2 = { .min = 5, .max = 11 },
339 .p = { .min = 5, .max = 80 },
340 .p1 = { .min = 1, .max = 8},
341 .p2 = { .dot_limit = 165000,
342 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 343};
344
345static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 346 .dot = { .min = 20000, .max = 115000 },
347 .vco = { .min = 1750000, .max = 3500000 },
348 .n = { .min = 1, .max = 3 },
349 .m = { .min = 104, .max = 138 },
350 .m1 = { .min = 17, .max = 23 },
351 .m2 = { .min = 5, .max = 11 },
352 .p = { .min = 28, .max = 112 },
353 .p1 = { .min = 2, .max = 8 },
354 .p2 = { .dot_limit = 0,
355 .p2_slow = 14, .p2_fast = 14
044c7c41 356 },
e4b36699
KP		 357};
358
359static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 360 .dot = { .min = 80000, .max = 224000 },
361 .vco = { .min = 1750000, .max = 3500000 },
362 .n = { .min = 1, .max = 3 },
363 .m = { .min = 104, .max = 138 },
364 .m1 = { .min = 17, .max = 23 },
365 .m2 = { .min = 5, .max = 11 },
366 .p = { .min = 14, .max = 42 },
367 .p1 = { .min = 2, .max = 6 },
368 .p2 = { .dot_limit = 0,
369 .p2_slow = 7, .p2_fast = 7
044c7c41 370 },
e4b36699
KP		 371};
372
f2b115e6 373static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 374 .dot = { .min = 20000, .max = 400000},
375 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 376 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 377 .n = { .min = 3, .max = 6 },
378 .m = { .min = 2, .max = 256 },
273e27ca 379 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 380 .m1 = { .min = 0, .max = 0 },
381 .m2 = { .min = 0, .max = 254 },
382 .p = { .min = 5, .max = 80 },
383 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 384 .p2 = { .dot_limit = 200000,
385 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 386};
387
f2b115e6 388static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 389 .dot = { .min = 20000, .max = 400000 },
390 .vco = { .min = 1700000, .max = 3500000 },
391 .n = { .min = 3, .max = 6 },
392 .m = { .min = 2, .max = 256 },
393 .m1 = { .min = 0, .max = 0 },
394 .m2 = { .min = 0, .max = 254 },
395 .p = { .min = 7, .max = 112 },
396 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 397 .p2 = { .dot_limit = 112000,
398 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 399};
400
273e27ca
EA		 401/* Ironlake / Sandybridge
402 *
403 * We calculate clock using (register_value + 2) for N/M1/M2, so here
404 * the range value for them is (actual_value - 2).
405 */
b91ad0ec 406static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 407 .dot = { .min = 25000, .max = 350000 },
408 .vco = { .min = 1760000, .max = 3510000 },
409 .n = { .min = 1, .max = 5 },
410 .m = { .min = 79, .max = 127 },
411 .m1 = { .min = 12, .max = 22 },
412 .m2 = { .min = 5, .max = 9 },
413 .p = { .min = 5, .max = 80 },
414 .p1 = { .min = 1, .max = 8 },
415 .p2 = { .dot_limit = 225000,
416 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 417};
418
b91ad0ec 419static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 420 .dot = { .min = 25000, .max = 350000 },
421 .vco = { .min = 1760000, .max = 3510000 },
422 .n = { .min = 1, .max = 3 },
423 .m = { .min = 79, .max = 118 },
424 .m1 = { .min = 12, .max = 22 },
425 .m2 = { .min = 5, .max = 9 },
426 .p = { .min = 28, .max = 112 },
427 .p1 = { .min = 2, .max = 8 },
428 .p2 = { .dot_limit = 225000,
429 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 430};
431
432static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 433 .dot = { .min = 25000, .max = 350000 },
434 .vco = { .min = 1760000, .max = 3510000 },
435 .n = { .min = 1, .max = 3 },
436 .m = { .min = 79, .max = 127 },
437 .m1 = { .min = 12, .max = 22 },
438 .m2 = { .min = 5, .max = 9 },
439 .p = { .min = 14, .max = 56 },
440 .p1 = { .min = 2, .max = 8 },
441 .p2 = { .dot_limit = 225000,
442 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 443};
444
273e27ca 445/* LVDS 100mhz refclk limits. */
b91ad0ec 446static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 447 .dot = { .min = 25000, .max = 350000 },
448 .vco = { .min = 1760000, .max = 3510000 },
449 .n = { .min = 1, .max = 2 },
450 .m = { .min = 79, .max = 126 },
451 .m1 = { .min = 12, .max = 22 },
452 .m2 = { .min = 5, .max = 9 },
453 .p = { .min = 28, .max = 112 },
0206e353 454 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 455 .p2 = { .dot_limit = 225000,
456 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 457};
458
459static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 460 .dot = { .min = 25000, .max = 350000 },
461 .vco = { .min = 1760000, .max = 3510000 },
462 .n = { .min = 1, .max = 3 },
463 .m = { .min = 79, .max = 126 },
464 .m1 = { .min = 12, .max = 22 },
465 .m2 = { .min = 5, .max = 9 },
466 .p = { .min = 14, .max = 42 },
0206e353 467 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 468 .p2 = { .dot_limit = 225000,
469 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 470};
471
dc730512 472static const intel_limit_t intel_limits_vlv = {
f01b7962
VS		 473 /*
474 * These are the data rate limits (measured in fast clocks)
475 * since those are the strictest limits we have. The fast
476 * clock and actual rate limits are more relaxed, so checking
477 * them would make no difference.
478 */
479 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
75e53986 480 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 481 .n = { .min = 1, .max = 7 },
a0c4da24
JB		 482 .m1 = { .min = 2, .max = 3 },
483 .m2 = { .min = 11, .max = 156 },
b99ab663 484 .p1 = { .min = 2, .max = 3 },
5fdc9c49 485 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
a0c4da24
JB		 486};
487
ef9348c8
CML		 488static const intel_limit_t intel_limits_chv = {
489 /*
490 * These are the data rate limits (measured in fast clocks)
491 * since those are the strictest limits we have. The fast
492 * clock and actual rate limits are more relaxed, so checking
493 * them would make no difference.
494 */
495 .dot = { .min = 25000 * 5, .max = 540000 * 5},
17fe1021 496 .vco = { .min = 4800000, .max = 6480000 },
ef9348c8
CML		 497 .n = { .min = 1, .max = 1 },
498 .m1 = { .min = 2, .max = 2 },
499 .m2 = { .min = 24 << 22, .max = 175 << 22 },
500 .p1 = { .min = 2, .max = 4 },
501 .p2 = { .p2_slow = 1, .p2_fast = 14 },
502};
503
5ab7b0b7
ID		 504static const intel_limit_t intel_limits_bxt = {
505 /* FIXME: find real dot limits */
506 .dot = { .min = 0, .max = INT_MAX },
e6292556 507 .vco = { .min = 4800000, .max = 6700000 },
5ab7b0b7
ID		 508 .n = { .min = 1, .max = 1 },
509 .m1 = { .min = 2, .max = 2 },
510 /* FIXME: find real m2 limits */
511 .m2 = { .min = 2 << 22, .max = 255 << 22 },
512 .p1 = { .min = 2, .max = 4 },
513 .p2 = { .p2_slow = 1, .p2_fast = 20 },
514};
515
cdba954e
ACO		 516static bool
517needs_modeset(struct drm_crtc_state *state)
518{
fc596660 519 return drm_atomic_crtc_needs_modeset(state);
cdba954e
ACO		 520}
521
e0638cdf
PZ		 522/**
523 * Returns whether any output on the specified pipe is of the specified type
524 */
4093561b 525bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
e0638cdf 526{
409ee761 527 struct drm_device *dev = crtc->base.dev;
e0638cdf
PZ		 528 struct intel_encoder *encoder;
529
409ee761 530 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
e0638cdf
PZ		 531 if (encoder->type == type)
532 return true;
533
534 return false;
535}
536
d0737e1d
ACO		 537/**
538 * Returns whether any output on the specified pipe will have the specified
539 * type after a staged modeset is complete, i.e., the same as
540 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
541 * encoder->crtc.
542 */
a93e255f
ACO		 543static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
544 int type)
d0737e1d 545{
a93e255f 546 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 547 struct drm_connector *connector;
a93e255f 548 struct drm_connector_state *connector_state;
d0737e1d 549 struct intel_encoder *encoder;
a93e255f
ACO		 550 int i, num_connectors = 0;
551
da3ced29 552 for_each_connector_in_state(state, connector, connector_state, i) {
a93e255f
ACO		 553 if (connector_state->crtc != crtc_state->base.crtc)
554 continue;
555
556 num_connectors++;
d0737e1d 557
a93e255f
ACO		 558 encoder = to_intel_encoder(connector_state->best_encoder);
559 if (encoder->type == type)
d0737e1d 560 return true;
a93e255f
ACO		 561 }
562
563 WARN_ON(num_connectors == 0);
d0737e1d
ACO		 564
565 return false;
566}
567
dccbea3b
ID		 568/*
569 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
570 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
571 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
572 * The helpers' return value is the rate of the clock that is fed to the
573 * display engine's pipe which can be the above fast dot clock rate or a
574 * divided-down version of it.
575 */
f2b115e6 576/* m1 is reserved as 0 in Pineview, n is a ring counter */
dccbea3b 577static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
79e53945 578{
2177832f
SL		 579 clock->m = clock->m2 + 2;
580 clock->p = clock->p1 * clock->p2;
ed5ca77e 581 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 582 return 0;
fb03ac01
VS		 583 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
584 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 585
586 return clock->dot;
2177832f
SL		 587}
588
7429e9d4
DV		 589static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
590{
591 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
592}
593
dccbea3b 594static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
2177832f 595{
7429e9d4 596 clock->m = i9xx_dpll_compute_m(clock);
79e53945 597 clock->p = clock->p1 * clock->p2;
ed5ca77e 598 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
dccbea3b 599 return 0;
fb03ac01
VS		 600 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
601 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 602
603 return clock->dot;
79e53945
JB		 604}
605
dccbea3b 606static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
589eca67
ID		 607{
608 clock->m = clock->m1 * clock->m2;
609 clock->p = clock->p1 * clock->p2;
610 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 611 return 0;
589eca67
ID		 612 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
613 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 614
615 return clock->dot / 5;
589eca67
ID		 616}
617
dccbea3b 618int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
ef9348c8
CML		 619{
620 clock->m = clock->m1 * clock->m2;
621 clock->p = clock->p1 * clock->p2;
622 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 623 return 0;
ef9348c8
CML		 624 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
625 clock->n << 22);
626 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 627
628 return clock->dot / 5;
ef9348c8
CML		 629}
630
7c04d1d9 631#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 632/**
633 * Returns whether the given set of divisors are valid for a given refclk with
634 * the given connectors.
635 */
636
1b894b59
CW		 637static bool intel_PLL_is_valid(struct drm_device *dev,
638 const intel_limit_t *limit,
639 const intel_clock_t *clock)
79e53945 640{
f01b7962
VS		 641 if (clock->n < limit->n.min || limit->n.max < clock->n)
642 INTELPllInvalid("n out of range\n");
79e53945 643 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 644 INTELPllInvalid("p1 out of range\n");
79e53945 645 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 646 INTELPllInvalid("m2 out of range\n");
79e53945 647 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 648 INTELPllInvalid("m1 out of range\n");
f01b7962 649
666a4537
WB		 650 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
651 !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
f01b7962
VS		 652 if (clock->m1 <= clock->m2)
653 INTELPllInvalid("m1 <= m2\n");
654
666a4537 655 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
f01b7962
VS		 656 if (clock->p < limit->p.min || limit->p.max < clock->p)
657 INTELPllInvalid("p out of range\n");
658 if (clock->m < limit->m.min || limit->m.max < clock->m)
659 INTELPllInvalid("m out of range\n");
660 }
661
79e53945 662 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 663 INTELPllInvalid("vco out of range\n");
79e53945
JB		 664 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
665 * connector, etc., rather than just a single range.
666 */
667 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 668 INTELPllInvalid("dot out of range\n");
79e53945
JB		 669
670 return true;
671}
672
3b1429d9
VS		 673static int
674i9xx_select_p2_div(const intel_limit_t *limit,
675 const struct intel_crtc_state *crtc_state,
676 int target)
79e53945 677{
3b1429d9 678 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945 679
a93e255f 680 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 681 /*
a210b028
DV		 682 * For LVDS just rely on its current settings for dual-channel.
683 * We haven't figured out how to reliably set up different
684 * single/dual channel state, if we even can.
79e53945 685 */
1974cad0 686 if (intel_is_dual_link_lvds(dev))
3b1429d9 687 return limit->p2.p2_fast;
79e53945 688 else
3b1429d9 689 return limit->p2.p2_slow;
79e53945
JB		 690 } else {
691 if (target < limit->p2.dot_limit)
3b1429d9 692 return limit->p2.p2_slow;
79e53945 693 else
3b1429d9 694 return limit->p2.p2_fast;
79e53945 695 }
3b1429d9
VS		 696}
697
70e8aa21
ACO		 698/*
699 * Returns a set of divisors for the desired target clock with the given
700 * refclk, or FALSE. The returned values represent the clock equation:
701 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
702 *
703 * Target and reference clocks are specified in kHz.
704 *
705 * If match_clock is provided, then best_clock P divider must match the P
706 * divider from @match_clock used for LVDS downclocking.
707 */
3b1429d9
VS		 708static bool
709i9xx_find_best_dpll(const intel_limit_t *limit,
710 struct intel_crtc_state *crtc_state,
711 int target, int refclk, intel_clock_t *match_clock,
712 intel_clock_t *best_clock)
713{
714 struct drm_device *dev = crtc_state->base.crtc->dev;
715 intel_clock_t clock;
716 int err = target;
79e53945 717
0206e353 718 memset(best_clock, 0, sizeof(*best_clock));
79e53945 719
3b1429d9
VS		 720 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
721
42158660
ZY		 722 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
723 clock.m1++) {
724 for (clock.m2 = limit->m2.min;
725 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 726 if (clock.m2 >= clock.m1)
42158660
ZY		 727 break;
728 for (clock.n = limit->n.min;
729 clock.n <= limit->n.max; clock.n++) {
730 for (clock.p1 = limit->p1.min;
731 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 732 int this_err;
733
dccbea3b 734 i9xx_calc_dpll_params(refclk, &clock);
ac58c3f0
DV		 735 if (!intel_PLL_is_valid(dev, limit,
736 &clock))
737 continue;
738 if (match_clock &&
739 clock.p != match_clock->p)
740 continue;
741
742 this_err = abs(clock.dot - target);
743 if (this_err < err) {
744 *best_clock = clock;
745 err = this_err;
746 }
747 }
748 }
749 }
750 }
751
752 return (err != target);
753}
754
70e8aa21
ACO		 755/*
756 * Returns a set of divisors for the desired target clock with the given
757 * refclk, or FALSE. The returned values represent the clock equation:
758 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
759 *
760 * Target and reference clocks are specified in kHz.
761 *
762 * If match_clock is provided, then best_clock P divider must match the P
763 * divider from @match_clock used for LVDS downclocking.
764 */
ac58c3f0 765static bool
a93e255f
ACO		 766pnv_find_best_dpll(const intel_limit_t *limit,
767 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 768 int target, int refclk, intel_clock_t *match_clock,
769 intel_clock_t *best_clock)
79e53945 770{
3b1429d9 771 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945 772 intel_clock_t clock;
79e53945
JB		 773 int err = target;
774
0206e353 775 memset(best_clock, 0, sizeof(*best_clock));
79e53945 776
3b1429d9
VS		 777 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
778
42158660
ZY		 779 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
780 clock.m1++) {
781 for (clock.m2 = limit->m2.min;
782 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 783 for (clock.n = limit->n.min;
784 clock.n <= limit->n.max; clock.n++) {
785 for (clock.p1 = limit->p1.min;
786 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 787 int this_err;
788
dccbea3b 789 pnv_calc_dpll_params(refclk, &clock);
1b894b59
CW		 790 if (!intel_PLL_is_valid(dev, limit,
791 &clock))
79e53945 792 continue;
cec2f356
SP		 793 if (match_clock &&
794 clock.p != match_clock->p)
795 continue;
79e53945
JB		 796
797 this_err = abs(clock.dot - target);
798 if (this_err < err) {
799 *best_clock = clock;
800 err = this_err;
801 }
802 }
803 }
804 }
805 }
806
807 return (err != target);
808}
809
997c030c
ACO		 810/*
811 * Returns a set of divisors for the desired target clock with the given
812 * refclk, or FALSE. The returned values represent the clock equation:
813 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
70e8aa21
ACO		 814 *
815 * Target and reference clocks are specified in kHz.
816 *
817 * If match_clock is provided, then best_clock P divider must match the P
818 * divider from @match_clock used for LVDS downclocking.
997c030c 819 */
d4906093 820static bool
a93e255f
ACO		 821g4x_find_best_dpll(const intel_limit_t *limit,
822 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 823 int target, int refclk, intel_clock_t *match_clock,
824 intel_clock_t *best_clock)
d4906093 825{
3b1429d9 826 struct drm_device *dev = crtc_state->base.crtc->dev;
d4906093
ML		 827 intel_clock_t clock;
828 int max_n;
3b1429d9 829 bool found = false;
6ba770dc
AJ		 830 /* approximately equals target * 0.00585 */
831 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 832
833 memset(best_clock, 0, sizeof(*best_clock));
3b1429d9
VS		 834
835 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
836
d4906093 837 max_n = limit->n.max;
f77f13e2 838 /* based on hardware requirement, prefer smaller n to precision */
d4906093 839 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 840 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 841 for (clock.m1 = limit->m1.max;
842 clock.m1 >= limit->m1.min; clock.m1--) {
843 for (clock.m2 = limit->m2.max;
844 clock.m2 >= limit->m2.min; clock.m2--) {
845 for (clock.p1 = limit->p1.max;
846 clock.p1 >= limit->p1.min; clock.p1--) {
847 int this_err;
848
dccbea3b 849 i9xx_calc_dpll_params(refclk, &clock);
1b894b59
CW		 850 if (!intel_PLL_is_valid(dev, limit,
851 &clock))
d4906093 852 continue;
1b894b59
CW		 853
854 this_err = abs(clock.dot - target);
d4906093
ML		 855 if (this_err < err_most) {
856 *best_clock = clock;
857 err_most = this_err;
858 max_n = clock.n;
859 found = true;
860 }
861 }
862 }
863 }
864 }
2c07245f
ZW		 865 return found;
866}
867
d5dd62bd
ID		 868/*
869 * Check if the calculated PLL configuration is more optimal compared to the
870 * best configuration and error found so far. Return the calculated error.
871 */
872static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
873 const intel_clock_t *calculated_clock,
874 const intel_clock_t *best_clock,
875 unsigned int best_error_ppm,
876 unsigned int *error_ppm)
877{
9ca3ba01
ID		 878 /*
879 * For CHV ignore the error and consider only the P value.
880 * Prefer a bigger P value based on HW requirements.
881 */
882 if (IS_CHERRYVIEW(dev)) {
883 *error_ppm = 0;
884
885 return calculated_clock->p > best_clock->p;
886 }
887
24be4e46
ID		 888 if (WARN_ON_ONCE(!target_freq))
889 return false;
890
d5dd62bd
ID		 891 *error_ppm = div_u64(1000000ULL *
892 abs(target_freq - calculated_clock->dot),
893 target_freq);
894 /*
895 * Prefer a better P value over a better (smaller) error if the error
896 * is small. Ensure this preference for future configurations too by
897 * setting the error to 0.
898 */
899 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
900 *error_ppm = 0;
901
902 return true;
903 }
904
905 return *error_ppm + 10 < best_error_ppm;
906}
907
65b3d6a9
ACO		 908/*
909 * Returns a set of divisors for the desired target clock with the given
910 * refclk, or FALSE. The returned values represent the clock equation:
911 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
912 */
a0c4da24 913static bool
a93e255f
ACO		 914vlv_find_best_dpll(const intel_limit_t *limit,
915 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 916 int target, int refclk, intel_clock_t *match_clock,
917 intel_clock_t *best_clock)
a0c4da24 918{
a93e255f 919 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 920 struct drm_device *dev = crtc->base.dev;
6b4bf1c4 921 intel_clock_t clock;
69e4f900 922 unsigned int bestppm = 1000000;
27e639bf
VS		 923 /* min update 19.2 MHz */
924 int max_n = min(limit->n.max, refclk / 19200);
49e497ef 925 bool found = false;
a0c4da24 926
6b4bf1c4
VS		 927 target *= 5; /* fast clock */
928
929 memset(best_clock, 0, sizeof(*best_clock));
a0c4da24
JB		 930
931 /* based on hardware requirement, prefer smaller n to precision */
27e639bf 932 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
811bbf05 933 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
889059d8 934 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
c1a9ae43 935 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
6b4bf1c4 936 clock.p = clock.p1 * clock.p2;
a0c4da24 937 /* based on hardware requirement, prefer bigger m1,m2 values */
6b4bf1c4 938 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
d5dd62bd 939 unsigned int ppm;
69e4f900 940
6b4bf1c4
VS		 941 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
942 refclk * clock.m1);
943
dccbea3b 944 vlv_calc_dpll_params(refclk, &clock);
43b0ac53 945
f01b7962
VS		 946 if (!intel_PLL_is_valid(dev, limit,
947 &clock))
43b0ac53
VS		 948 continue;
949
d5dd62bd
ID		 950 if (!vlv_PLL_is_optimal(dev, target,
951 &clock,
952 best_clock,
953 bestppm, &ppm))
954 continue;
6b4bf1c4 955
d5dd62bd
ID		 956 *best_clock = clock;
957 bestppm = ppm;
958 found = true;
a0c4da24
JB		 959 }
960 }
961 }
962 }
a0c4da24 963
49e497ef 964 return found;
a0c4da24 965}
a4fc5ed6 966
65b3d6a9
ACO		 967/*
968 * Returns a set of divisors for the desired target clock with the given
969 * refclk, or FALSE. The returned values represent the clock equation:
970 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
971 */
ef9348c8 972static bool
a93e255f
ACO		 973chv_find_best_dpll(const intel_limit_t *limit,
974 struct intel_crtc_state *crtc_state,
ef9348c8
CML		 975 int target, int refclk, intel_clock_t *match_clock,
976 intel_clock_t *best_clock)
977{
a93e255f 978 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 979 struct drm_device *dev = crtc->base.dev;
9ca3ba01 980 unsigned int best_error_ppm;
ef9348c8
CML		 981 intel_clock_t clock;
982 uint64_t m2;
983 int found = false;
984
985 memset(best_clock, 0, sizeof(*best_clock));
9ca3ba01 986 best_error_ppm = 1000000;
ef9348c8
CML		 987
988 /*
989 * Based on hardware doc, the n always set to 1, and m1 always
990 * set to 2. If requires to support 200Mhz refclk, we need to
991 * revisit this because n may not 1 anymore.
992 */
993 clock.n = 1, clock.m1 = 2;
994 target *= 5; /* fast clock */
995
996 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
997 for (clock.p2 = limit->p2.p2_fast;
998 clock.p2 >= limit->p2.p2_slow;
999 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
9ca3ba01 1000 unsigned int error_ppm;
ef9348c8
CML		 1001
1002 clock.p = clock.p1 * clock.p2;
1003
1004 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1005 clock.n) << 22, refclk * clock.m1);
1006
1007 if (m2 > INT_MAX/clock.m1)
1008 continue;
1009
1010 clock.m2 = m2;
1011
dccbea3b 1012 chv_calc_dpll_params(refclk, &clock);
ef9348c8
CML		 1013
1014 if (!intel_PLL_is_valid(dev, limit, &clock))
1015 continue;
1016
9ca3ba01
ID		 1017 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1018 best_error_ppm, &error_ppm))
1019 continue;
1020
1021 *best_clock = clock;
1022 best_error_ppm = error_ppm;
1023 found = true;
ef9348c8
CML		 1024 }
1025 }
1026
1027 return found;
1028}
1029
5ab7b0b7
ID		 1030bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1031 intel_clock_t *best_clock)
1032{
65b3d6a9
ACO		 1033 int refclk = 100000;
1034 const intel_limit_t *limit = &intel_limits_bxt;
5ab7b0b7 1035
65b3d6a9 1036 return chv_find_best_dpll(limit, crtc_state,
5ab7b0b7
ID		 1037 target_clock, refclk, NULL, best_clock);
1038}
1039
20ddf665
VS		 1040bool intel_crtc_active(struct drm_crtc *crtc)
1041{
1042 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1043
1044 /* Be paranoid as we can arrive here with only partial
1045 * state retrieved from the hardware during setup.
1046 *
241bfc38 1047 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS		 1048 * as Haswell has gained clock readout/fastboot support.
1049 *
66e514c1 1050 * We can ditch the crtc->primary->fb check as soon as we can
20ddf665 1051 * properly reconstruct framebuffers.
c3d1f436
MR		 1052 *
1053 * FIXME: The intel_crtc->active here should be switched to
1054 * crtc->state->active once we have proper CRTC states wired up
1055 * for atomic.
20ddf665 1056 */
c3d1f436 1057 return intel_crtc->active && crtc->primary->state->fb &&
6e3c9717 1058 intel_crtc->config->base.adjusted_mode.crtc_clock;
20ddf665
VS		 1059}
1060
a5c961d1
PZ		 1061enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1062 enum pipe pipe)
1063{
1064 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1065 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1066
6e3c9717 1067 return intel_crtc->config->cpu_transcoder;
a5c961d1
PZ		 1068}
1069
fbf49ea2
VS		 1070static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1071{
1072 struct drm_i915_private *dev_priv = dev->dev_private;
f0f59a00 1073 i915_reg_t reg = PIPEDSL(pipe);
fbf49ea2
VS		 1074 u32 line1, line2;
1075 u32 line_mask;
1076
1077 if (IS_GEN2(dev))
1078 line_mask = DSL_LINEMASK_GEN2;
1079 else
1080 line_mask = DSL_LINEMASK_GEN3;
1081
1082 line1 = I915_READ(reg) & line_mask;
6adfb1ef 1083 msleep(5);
fbf49ea2
VS		 1084 line2 = I915_READ(reg) & line_mask;
1085
1086 return line1 == line2;
1087}
1088
ab7ad7f6
KP		 1089/*
1090 * intel_wait_for_pipe_off - wait for pipe to turn off
575f7ab7 1091 * @crtc: crtc whose pipe to wait for
9d0498a2
JB		 1092 *
1093 * After disabling a pipe, we can't wait for vblank in the usual way,
1094 * spinning on the vblank interrupt status bit, since we won't actually
1095 * see an interrupt when the pipe is disabled.
1096 *
ab7ad7f6
KP		 1097 * On Gen4 and above:
1098 * wait for the pipe register state bit to turn off
1099 *
1100 * Otherwise:
1101 * wait for the display line value to settle (it usually
1102 * ends up stopping at the start of the next frame).
58e10eb9 1103 *
9d0498a2 1104 */
575f7ab7 1105static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
9d0498a2 1106{
575f7ab7 1107 struct drm_device *dev = crtc->base.dev;
9d0498a2 1108 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1109 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 1110 enum pipe pipe = crtc->pipe;
ab7ad7f6
KP		 1111
1112 if (INTEL_INFO(dev)->gen >= 4) {
f0f59a00 1113 i915_reg_t reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 1114
1115 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1116 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1117 100))
284637d9 1118 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1119 } else {
ab7ad7f6 1120 /* Wait for the display line to settle */
fbf49ea2 1121 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
284637d9 1122 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1123 }
79e53945
JB		 1124}
1125
b24e7179 1126/* Only for pre-ILK configs */
55607e8a
DV		 1127void assert_pll(struct drm_i915_private *dev_priv,
1128 enum pipe pipe, bool state)
b24e7179 1129{
b24e7179
JB		 1130 u32 val;
1131 bool cur_state;
1132
649636ef 1133 val = I915_READ(DPLL(pipe));
b24e7179 1134 cur_state = !!(val & DPLL_VCO_ENABLE);
e2c719b7 1135 I915_STATE_WARN(cur_state != state,
b24e7179 1136 "PLL state assertion failure (expected %s, current %s)\n",
87ad3212 1137 onoff(state), onoff(cur_state));
b24e7179 1138}
b24e7179 1139
23538ef1 1140/* XXX: the dsi pll is shared between MIPI DSI ports */
8563b1e8 1141void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
23538ef1
JN		 1142{
1143 u32 val;
1144 bool cur_state;
1145
a580516d 1146 mutex_lock(&dev_priv->sb_lock);
23538ef1 1147 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
a580516d 1148 mutex_unlock(&dev_priv->sb_lock);
23538ef1
JN		 1149
1150 cur_state = val & DSI_PLL_VCO_EN;
e2c719b7 1151 I915_STATE_WARN(cur_state != state,
23538ef1 1152 "DSI PLL state assertion failure (expected %s, current %s)\n",
87ad3212 1153 onoff(state), onoff(cur_state));
23538ef1 1154}
23538ef1 1155
040484af
JB		 1156static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1157 enum pipe pipe, bool state)
1158{
040484af 1159 bool cur_state;
ad80a810
PZ		 1160 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1161 pipe);
040484af 1162
affa9354
PZ		 1163 if (HAS_DDI(dev_priv->dev)) {
1164 /* DDI does not have a specific FDI_TX register */
649636ef 1165 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
ad80a810 1166 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7 1167 } else {
649636ef 1168 u32 val = I915_READ(FDI_TX_CTL(pipe));
bf507ef7
ED		 1169 cur_state = !!(val & FDI_TX_ENABLE);
1170 }
e2c719b7 1171 I915_STATE_WARN(cur_state != state,
040484af 1172 "FDI TX state assertion failure (expected %s, current %s)\n",
87ad3212 1173 onoff(state), onoff(cur_state));
040484af
JB		 1174}
1175#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1176#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1177
1178static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1179 enum pipe pipe, bool state)
1180{
040484af
JB		 1181 u32 val;
1182 bool cur_state;
1183
649636ef 1184 val = I915_READ(FDI_RX_CTL(pipe));
d63fa0dc 1185 cur_state = !!(val & FDI_RX_ENABLE);
e2c719b7 1186 I915_STATE_WARN(cur_state != state,
040484af 1187 "FDI RX state assertion failure (expected %s, current %s)\n",
87ad3212 1188 onoff(state), onoff(cur_state));
040484af
JB		 1189}
1190#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1191#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1192
1193static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1194 enum pipe pipe)
1195{
040484af
JB		 1196 u32 val;
1197
1198 /* ILK FDI PLL is always enabled */
3d13ef2e 1199 if (INTEL_INFO(dev_priv->dev)->gen == 5)
040484af
JB		 1200 return;
1201
bf507ef7 1202 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1203 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1204 return;
1205
649636ef 1206 val = I915_READ(FDI_TX_CTL(pipe));
e2c719b7 1207 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
040484af
JB		 1208}
1209
55607e8a
DV		 1210void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1211 enum pipe pipe, bool state)
040484af 1212{
040484af 1213 u32 val;
55607e8a 1214 bool cur_state;
040484af 1215
649636ef 1216 val = I915_READ(FDI_RX_CTL(pipe));
55607e8a 1217 cur_state = !!(val & FDI_RX_PLL_ENABLE);
e2c719b7 1218 I915_STATE_WARN(cur_state != state,
55607e8a 1219 "FDI RX PLL assertion failure (expected %s, current %s)\n",
87ad3212 1220 onoff(state), onoff(cur_state));
040484af
JB		 1221}
1222
b680c37a
DV		 1223void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1224 enum pipe pipe)
ea0760cf 1225{
bedd4dba 1226 struct drm_device *dev = dev_priv->dev;
f0f59a00 1227 i915_reg_t pp_reg;
ea0760cf
JB		 1228 u32 val;
1229 enum pipe panel_pipe = PIPE_A;
0de3b485 1230 bool locked = true;
ea0760cf 1231
bedd4dba
JN		 1232 if (WARN_ON(HAS_DDI(dev)))
1233 return;
1234
1235 if (HAS_PCH_SPLIT(dev)) {
1236 u32 port_sel;
1237
ea0760cf 1238 pp_reg = PCH_PP_CONTROL;
bedd4dba
JN		 1239 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1240
1241 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1242 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1243 panel_pipe = PIPE_B;
1244 /* XXX: else fix for eDP */
666a4537 1245 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
bedd4dba
JN		 1246 /* presumably write lock depends on pipe, not port select */
1247 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1248 panel_pipe = pipe;
ea0760cf
JB		 1249 } else {
1250 pp_reg = PP_CONTROL;
bedd4dba
JN		 1251 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1252 panel_pipe = PIPE_B;
ea0760cf
JB		 1253 }
1254
1255 val = I915_READ(pp_reg);
1256 if (!(val & PANEL_POWER_ON) ||
ec49ba2d 1257 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
ea0760cf
JB		 1258 locked = false;
1259
e2c719b7 1260 I915_STATE_WARN(panel_pipe == pipe && locked,
ea0760cf 1261 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1262 pipe_name(pipe));
ea0760cf
JB		 1263}
1264
93ce0ba6
JN		 1265static void assert_cursor(struct drm_i915_private *dev_priv,
1266 enum pipe pipe, bool state)
1267{
1268 struct drm_device *dev = dev_priv->dev;
1269 bool cur_state;
1270
d9d82081 1271 if (IS_845G(dev) || IS_I865G(dev))
0b87c24e 1272 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
d9d82081 1273 else
5efb3e28 1274 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
93ce0ba6 1275
e2c719b7 1276 I915_STATE_WARN(cur_state != state,
93ce0ba6 1277 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
87ad3212 1278 pipe_name(pipe), onoff(state), onoff(cur_state));
93ce0ba6
JN		 1279}
1280#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1281#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1282
b840d907
JB		 1283void assert_pipe(struct drm_i915_private *dev_priv,
1284 enum pipe pipe, bool state)
b24e7179 1285{
63d7bbe9 1286 bool cur_state;
702e7a56
PZ		 1287 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1288 pipe);
4feed0eb 1289 enum intel_display_power_domain power_domain;
b24e7179 1290
b6b5d049
VS		 1291 /* if we need the pipe quirk it must be always on */
1292 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1293 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8e636784
DV		 1294 state = true;
1295
4feed0eb
ID		 1296 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1297 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
649636ef 1298 u32 val = I915_READ(PIPECONF(cpu_transcoder));
69310161 1299 cur_state = !!(val & PIPECONF_ENABLE);
4feed0eb
ID		 1300
1301 intel_display_power_put(dev_priv, power_domain);
1302 } else {
1303 cur_state = false;
69310161
PZ		 1304 }
1305
e2c719b7 1306 I915_STATE_WARN(cur_state != state,
63d7bbe9 1307 "pipe %c assertion failure (expected %s, current %s)\n",
87ad3212 1308 pipe_name(pipe), onoff(state), onoff(cur_state));
b24e7179
JB		 1309}
1310
931872fc
CW		 1311static void assert_plane(struct drm_i915_private *dev_priv,
1312 enum plane plane, bool state)
b24e7179 1313{
b24e7179 1314 u32 val;
931872fc 1315 bool cur_state;
b24e7179 1316
649636ef 1317 val = I915_READ(DSPCNTR(plane));
931872fc 1318 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
e2c719b7 1319 I915_STATE_WARN(cur_state != state,
931872fc 1320 "plane %c assertion failure (expected %s, current %s)\n",
87ad3212 1321 plane_name(plane), onoff(state), onoff(cur_state));
b24e7179
JB		 1322}
1323
931872fc
CW		 1324#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1325#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1326
b24e7179
JB		 1327static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1328 enum pipe pipe)
1329{
653e1026 1330 struct drm_device *dev = dev_priv->dev;
649636ef 1331 int i;
b24e7179 1332
653e1026
VS		 1333 /* Primary planes are fixed to pipes on gen4+ */
1334 if (INTEL_INFO(dev)->gen >= 4) {
649636ef 1335 u32 val = I915_READ(DSPCNTR(pipe));
e2c719b7 1336 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
28c05794
AJ		 1337 "plane %c assertion failure, should be disabled but not\n",
1338 plane_name(pipe));
19ec1358 1339 return;
28c05794 1340 }
19ec1358 1341
b24e7179 1342 /* Need to check both planes against the pipe */
055e393f 1343 for_each_pipe(dev_priv, i) {
649636ef
VS		 1344 u32 val = I915_READ(DSPCNTR(i));
1345 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
b24e7179 1346 DISPPLANE_SEL_PIPE_SHIFT;
e2c719b7 1347 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1348 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1349 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1350 }
1351}
1352
19332d7a
JB		 1353static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1354 enum pipe pipe)
1355{
20674eef 1356 struct drm_device *dev = dev_priv->dev;
649636ef 1357 int sprite;
19332d7a 1358
7feb8b88 1359 if (INTEL_INFO(dev)->gen >= 9) {
3bdcfc0c 1360 for_each_sprite(dev_priv, pipe, sprite) {
649636ef 1361 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
e2c719b7 1362 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
7feb8b88
DL		 1363 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1364 sprite, pipe_name(pipe));
1365 }
666a4537 1366 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
3bdcfc0c 1367 for_each_sprite(dev_priv, pipe, sprite) {
649636ef 1368 u32 val = I915_READ(SPCNTR(pipe, sprite));
e2c719b7 1369 I915_STATE_WARN(val & SP_ENABLE,
20674eef 1370 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1fe47785 1371 sprite_name(pipe, sprite), pipe_name(pipe));
20674eef
VS		 1372 }
1373 } else if (INTEL_INFO(dev)->gen >= 7) {
649636ef 1374 u32 val = I915_READ(SPRCTL(pipe));
e2c719b7 1375 I915_STATE_WARN(val & SPRITE_ENABLE,
06da8da2 1376 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1377 plane_name(pipe), pipe_name(pipe));
1378 } else if (INTEL_INFO(dev)->gen >= 5) {
649636ef 1379 u32 val = I915_READ(DVSCNTR(pipe));
e2c719b7 1380 I915_STATE_WARN(val & DVS_ENABLE,
06da8da2 1381 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1382 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1383 }
1384}
1385
08c71e5e
VS		 1386static void assert_vblank_disabled(struct drm_crtc *crtc)
1387{
e2c719b7 1388 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
08c71e5e
VS		 1389 drm_crtc_vblank_put(crtc);
1390}
1391
7abd4b35
ACO		 1392void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1393 enum pipe pipe)
92f2584a 1394{
92f2584a
JB		 1395 u32 val;
1396 bool enabled;
1397
649636ef 1398 val = I915_READ(PCH_TRANSCONF(pipe));
92f2584a 1399 enabled = !!(val & TRANS_ENABLE);
e2c719b7 1400 I915_STATE_WARN(enabled,
9db4a9c7
JB		 1401 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1402 pipe_name(pipe));
92f2584a
JB		 1403}
1404
4e634389
KP		 1405static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1406 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1407{
1408 if ((val & DP_PORT_EN) == 0)
1409 return false;
1410
1411 if (HAS_PCH_CPT(dev_priv->dev)) {
f0f59a00 1412 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
f0575e92
KP		 1413 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1414 return false;
44f37d1f
CML		 1415 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1416 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1417 return false;
f0575e92
KP		 1418 } else {
1419 if ((val & DP_PIPE_MASK) != (pipe << 30))
1420 return false;
1421 }
1422 return true;
1423}
1424
1519b995
KP		 1425static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1426 enum pipe pipe, u32 val)
1427{
dc0fa718 1428 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1429 return false;
1430
1431 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1432 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995 1433 return false;
44f37d1f
CML		 1434 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1435 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1436 return false;
1519b995 1437 } else {
dc0fa718 1438 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1439 return false;
1440 }
1441 return true;
1442}
1443
1444static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1445 enum pipe pipe, u32 val)
1446{
1447 if ((val & LVDS_PORT_EN) == 0)
1448 return false;
1449
1450 if (HAS_PCH_CPT(dev_priv->dev)) {
1451 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1452 return false;
1453 } else {
1454 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1455 return false;
1456 }
1457 return true;
1458}
1459
1460static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1461 enum pipe pipe, u32 val)
1462{
1463 if ((val & ADPA_DAC_ENABLE) == 0)
1464 return false;
1465 if (HAS_PCH_CPT(dev_priv->dev)) {
1466 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1467 return false;
1468 } else {
1469 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1470 return false;
1471 }
1472 return true;
1473}
1474
291906f1 1475static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0f59a00
VS		 1476 enum pipe pipe, i915_reg_t reg,
1477 u32 port_sel)
291906f1 1478{
47a05eca 1479 u32 val = I915_READ(reg);
e2c719b7 1480 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1481 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
f0f59a00 1482 i915_mmio_reg_offset(reg), pipe_name(pipe));
de9a35ab 1483
e2c719b7 1484 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
75c5da27 1485 && (val & DP_PIPEB_SELECT),
de9a35ab 1486 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1487}
1488
1489static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
f0f59a00 1490 enum pipe pipe, i915_reg_t reg)
291906f1 1491{
47a05eca 1492 u32 val = I915_READ(reg);
e2c719b7 1493 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1494 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
f0f59a00 1495 i915_mmio_reg_offset(reg), pipe_name(pipe));
de9a35ab 1496
e2c719b7 1497 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1498 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1499 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1500}
1501
1502static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1503 enum pipe pipe)
1504{
291906f1 1505 u32 val;
291906f1 1506
f0575e92
KP		 1507 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1508 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1509 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1 1510
649636ef 1511 val = I915_READ(PCH_ADPA);
e2c719b7 1512 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1513 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1514 pipe_name(pipe));
291906f1 1515
649636ef 1516 val = I915_READ(PCH_LVDS);
e2c719b7 1517 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1518 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1519 pipe_name(pipe));
291906f1 1520
e2debe91
PZ		 1521 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1522 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1523 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1524}
1525
d288f65f 1526static void vlv_enable_pll(struct intel_crtc *crtc,
5cec258b 1527 const struct intel_crtc_state *pipe_config)
87442f73 1528{
426115cf
DV		 1529 struct drm_device *dev = crtc->base.dev;
1530 struct drm_i915_private *dev_priv = dev->dev_private;
f0f59a00 1531 i915_reg_t reg = DPLL(crtc->pipe);
d288f65f 1532 u32 dpll = pipe_config->dpll_hw_state.dpll;
87442f73 1533
426115cf 1534 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73 1535
87442f73 1536 /* PLL is protected by panel, make sure we can write it */
6a9e7363 1537 if (IS_MOBILE(dev_priv->dev))
426115cf 1538 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1539
426115cf
DV		 1540 I915_WRITE(reg, dpll);
1541 POSTING_READ(reg);
1542 udelay(150);
1543
1544 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1545 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1546
d288f65f 1547 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
426115cf 1548 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1549
1550 /* We do this three times for luck */
426115cf 1551 I915_WRITE(reg, dpll);
87442f73
DV		 1552 POSTING_READ(reg);
1553 udelay(150); /* wait for warmup */
426115cf 1554 I915_WRITE(reg, dpll);
87442f73
DV		 1555 POSTING_READ(reg);
1556 udelay(150); /* wait for warmup */
426115cf 1557 I915_WRITE(reg, dpll);
87442f73
DV		 1558 POSTING_READ(reg);
1559 udelay(150); /* wait for warmup */
1560}
1561
d288f65f 1562static void chv_enable_pll(struct intel_crtc *crtc,
5cec258b 1563 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 1564{
1565 struct drm_device *dev = crtc->base.dev;
1566 struct drm_i915_private *dev_priv = dev->dev_private;
1567 int pipe = crtc->pipe;
1568 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9d556c99
CML		 1569 u32 tmp;
1570
1571 assert_pipe_disabled(dev_priv, crtc->pipe);
1572
a580516d 1573 mutex_lock(&dev_priv->sb_lock);
9d556c99
CML		 1574
1575 /* Enable back the 10bit clock to display controller */
1576 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1577 tmp |= DPIO_DCLKP_EN;
1578 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1579
54433e91
VS		 1580 mutex_unlock(&dev_priv->sb_lock);
1581
9d556c99
CML		 1582 /*
1583 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1584 */
1585 udelay(1);
1586
1587 /* Enable PLL */
d288f65f 1588 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
9d556c99
CML		 1589
1590 /* Check PLL is locked */
a11b0703 1591 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
9d556c99
CML		 1592 DRM_ERROR("PLL %d failed to lock\n", pipe);
1593
c231775c
VS		 1594 if (pipe != PIPE_A) {
1595 /*
1596 * WaPixelRepeatModeFixForC0:chv
1597 *
1598 * DPLLCMD is AWOL. Use chicken bits to propagate
1599 * the value from DPLLBMD to either pipe B or C.
1600 */
1601 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1602 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1603 I915_WRITE(CBR4_VLV, 0);
1604 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1605
1606 /*
1607 * DPLLB VGA mode also seems to cause problems.
1608 * We should always have it disabled.
1609 */
1610 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1611 } else {
1612 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1613 POSTING_READ(DPLL_MD(pipe));
1614 }
9d556c99
CML		 1615}
1616
1c4e0274
VS		 1617static int intel_num_dvo_pipes(struct drm_device *dev)
1618{
1619 struct intel_crtc *crtc;
1620 int count = 0;
1621
1622 for_each_intel_crtc(dev, crtc)
3538b9df 1623 count += crtc->base.state->active &&
409ee761 1624 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1c4e0274
VS		 1625
1626 return count;
1627}
1628
66e3d5c0 1629static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1630{
66e3d5c0
DV		 1631 struct drm_device *dev = crtc->base.dev;
1632 struct drm_i915_private *dev_priv = dev->dev_private;
f0f59a00 1633 i915_reg_t reg = DPLL(crtc->pipe);
6e3c9717 1634 u32 dpll = crtc->config->dpll_hw_state.dpll;
63d7bbe9 1635
66e3d5c0 1636 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1637
63d7bbe9 1638 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1639 if (IS_MOBILE(dev) && !IS_I830(dev))
1640 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1641
1c4e0274
VS		 1642 /* Enable DVO 2x clock on both PLLs if necessary */
1643 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1644 /*
1645 * It appears to be important that we don't enable this
1646 * for the current pipe before otherwise configuring the
1647 * PLL. No idea how this should be handled if multiple
1648 * DVO outputs are enabled simultaneosly.
1649 */
1650 dpll |= DPLL_DVO_2X_MODE;
1651 I915_WRITE(DPLL(!crtc->pipe),
1652 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1653 }
66e3d5c0 1654
c2b63374
VS		 1655 /*
1656 * Apparently we need to have VGA mode enabled prior to changing
1657 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1658 * dividers, even though the register value does change.
1659 */
1660 I915_WRITE(reg, 0);
1661
8e7a65aa
VS		 1662 I915_WRITE(reg, dpll);
1663
66e3d5c0
DV		 1664 /* Wait for the clocks to stabilize. */
1665 POSTING_READ(reg);
1666 udelay(150);
1667
1668 if (INTEL_INFO(dev)->gen >= 4) {
1669 I915_WRITE(DPLL_MD(crtc->pipe),
6e3c9717 1670 crtc->config->dpll_hw_state.dpll_md);
66e3d5c0
DV		 1671 } else {
1672 /* The pixel multiplier can only be updated once the
1673 * DPLL is enabled and the clocks are stable.
1674 *
1675 * So write it again.
1676 */
1677 I915_WRITE(reg, dpll);
1678 }
63d7bbe9
JB		 1679
1680 /* We do this three times for luck */
66e3d5c0 1681 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1682 POSTING_READ(reg);
1683 udelay(150); /* wait for warmup */
66e3d5c0 1684 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1685 POSTING_READ(reg);
1686 udelay(150); /* wait for warmup */
66e3d5c0 1687 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1688 POSTING_READ(reg);
1689 udelay(150); /* wait for warmup */
1690}
1691
1692/**
50b44a44 1693 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1694 * @dev_priv: i915 private structure
1695 * @pipe: pipe PLL to disable
1696 *
1697 * Disable the PLL for @pipe, making sure the pipe is off first.
1698 *
1699 * Note! This is for pre-ILK only.
1700 */
1c4e0274 1701static void i9xx_disable_pll(struct intel_crtc *crtc)
63d7bbe9 1702{
1c4e0274
VS		 1703 struct drm_device *dev = crtc->base.dev;
1704 struct drm_i915_private *dev_priv = dev->dev_private;
1705 enum pipe pipe = crtc->pipe;
1706
1707 /* Disable DVO 2x clock on both PLLs if necessary */
1708 if (IS_I830(dev) &&
409ee761 1709 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
3538b9df 1710 !intel_num_dvo_pipes(dev)) {
1c4e0274
VS		 1711 I915_WRITE(DPLL(PIPE_B),
1712 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1713 I915_WRITE(DPLL(PIPE_A),
1714 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1715 }
1716
b6b5d049
VS		 1717 /* Don't disable pipe or pipe PLLs if needed */
1718 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1719 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
63d7bbe9
JB		 1720 return;
1721
1722 /* Make sure the pipe isn't still relying on us */
1723 assert_pipe_disabled(dev_priv, pipe);
1724
b8afb911 1725 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
50b44a44 1726 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1727}
1728
f6071166
JB		 1729static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1730{
b8afb911 1731 u32 val;
f6071166
JB		 1732
1733 /* Make sure the pipe isn't still relying on us */
1734 assert_pipe_disabled(dev_priv, pipe);
1735
03ed5cbf
VS		 1736 val = DPLL_INTEGRATED_REF_CLK_VLV |
1737 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1738 if (pipe != PIPE_A)
1739 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1740
f6071166
JB		 1741 I915_WRITE(DPLL(pipe), val);
1742 POSTING_READ(DPLL(pipe));
076ed3b2
CML		 1743}
1744
1745static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1746{
d752048d 1747 enum dpio_channel port = vlv_pipe_to_channel(pipe);
076ed3b2
CML		 1748 u32 val;
1749
a11b0703
VS		 1750 /* Make sure the pipe isn't still relying on us */
1751 assert_pipe_disabled(dev_priv, pipe);
076ed3b2 1752
60bfe44f
VS		 1753 val = DPLL_SSC_REF_CLK_CHV |
1754 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
a11b0703
VS		 1755 if (pipe != PIPE_A)
1756 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
03ed5cbf 1757
a11b0703
VS		 1758 I915_WRITE(DPLL(pipe), val);
1759 POSTING_READ(DPLL(pipe));
d752048d 1760
a580516d 1761 mutex_lock(&dev_priv->sb_lock);
d752048d
VS		 1762
1763 /* Disable 10bit clock to display controller */
1764 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1765 val &= ~DPIO_DCLKP_EN;
1766 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1767
a580516d 1768 mutex_unlock(&dev_priv->sb_lock);
f6071166
JB		 1769}
1770
e4607fcf 1771void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
9b6de0a1
VS		 1772 struct intel_digital_port *dport,
1773 unsigned int expected_mask)
89b667f8
JB		 1774{
1775 u32 port_mask;
f0f59a00 1776 i915_reg_t dpll_reg;
89b667f8 1777
e4607fcf
CML		 1778 switch (dport->port) {
1779 case PORT_B:
89b667f8 1780 port_mask = DPLL_PORTB_READY_MASK;
00fc31b7 1781 dpll_reg = DPLL(0);
e4607fcf
CML		 1782 break;
1783 case PORT_C:
89b667f8 1784 port_mask = DPLL_PORTC_READY_MASK;
00fc31b7 1785 dpll_reg = DPLL(0);
9b6de0a1 1786 expected_mask <<= 4;
00fc31b7
CML		 1787 break;
1788 case PORT_D:
1789 port_mask = DPLL_PORTD_READY_MASK;
1790 dpll_reg = DPIO_PHY_STATUS;
e4607fcf
CML		 1791 break;
1792 default:
1793 BUG();
1794 }
89b667f8 1795
9b6de0a1
VS		 1796 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1797 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1798 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
89b667f8
JB		 1799}
1800
b8a4f404
PZ		 1801static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1802 enum pipe pipe)
040484af 1803{
23670b32 1804 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1805 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1806 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
f0f59a00
VS		 1807 i915_reg_t reg;
1808 uint32_t val, pipeconf_val;
040484af 1809
040484af 1810 /* Make sure PCH DPLL is enabled */
8106ddbd 1811 assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
040484af
JB		 1812
1813 /* FDI must be feeding us bits for PCH ports */
1814 assert_fdi_tx_enabled(dev_priv, pipe);
1815 assert_fdi_rx_enabled(dev_priv, pipe);
1816
23670b32
DV		 1817 if (HAS_PCH_CPT(dev)) {
1818 /* Workaround: Set the timing override bit before enabling the
1819 * pch transcoder. */
1820 reg = TRANS_CHICKEN2(pipe);
1821 val = I915_READ(reg);
1822 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1823 I915_WRITE(reg, val);
59c859d6 1824 }
23670b32 1825
ab9412ba 1826 reg = PCH_TRANSCONF(pipe);
040484af 1827 val = I915_READ(reg);
5f7f726d 1828 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1829
1830 if (HAS_PCH_IBX(dev_priv->dev)) {
1831 /*
c5de7c6f
VS		 1832 * Make the BPC in transcoder be consistent with
1833 * that in pipeconf reg. For HDMI we must use 8bpc
1834 * here for both 8bpc and 12bpc.
e9bcff5c 1835 */
dfd07d72 1836 val &= ~PIPECONF_BPC_MASK;
c5de7c6f
VS		 1837 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1838 val |= PIPECONF_8BPC;
1839 else
1840 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1841 }
5f7f726d
PZ		 1842
1843 val &= ~TRANS_INTERLACE_MASK;
1844 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6 1845 if (HAS_PCH_IBX(dev_priv->dev) &&
409ee761 1846 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7c26e5c6
PZ		 1847 val |= TRANS_LEGACY_INTERLACED_ILK;
1848 else
1849 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1850 else
1851 val |= TRANS_PROGRESSIVE;
1852
040484af
JB		 1853 I915_WRITE(reg, val | TRANS_ENABLE);
1854 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1855 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1856}
1857
8fb033d7 1858static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1859 enum transcoder cpu_transcoder)
040484af 1860{
8fb033d7 1861 u32 val, pipeconf_val;
8fb033d7 1862
8fb033d7 1863 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1864 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1865 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1866
223a6fdf 1867 /* Workaround: set timing override bit. */
36c0d0cf 1868 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
23670b32 1869 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
36c0d0cf 1870 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
223a6fdf 1871
25f3ef11 1872 val = TRANS_ENABLE;
937bb610 1873 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1874
9a76b1c6
PZ		 1875 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1876 PIPECONF_INTERLACED_ILK)
a35f2679 1877 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1878 else
1879 val |= TRANS_PROGRESSIVE;
1880
ab9412ba
DV		 1881 I915_WRITE(LPT_TRANSCONF, val);
1882 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 1883 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1884}
1885
b8a4f404
PZ		 1886static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1887 enum pipe pipe)
040484af 1888{
23670b32 1889 struct drm_device *dev = dev_priv->dev;
f0f59a00
VS		 1890 i915_reg_t reg;
1891 uint32_t val;
040484af
JB		 1892
1893 /* FDI relies on the transcoder */
1894 assert_fdi_tx_disabled(dev_priv, pipe);
1895 assert_fdi_rx_disabled(dev_priv, pipe);
1896
291906f1
JB		 1897 /* Ports must be off as well */
1898 assert_pch_ports_disabled(dev_priv, pipe);
1899
ab9412ba 1900 reg = PCH_TRANSCONF(pipe);
040484af
JB		 1901 val = I915_READ(reg);
1902 val &= ~TRANS_ENABLE;
1903 I915_WRITE(reg, val);
1904 /* wait for PCH transcoder off, transcoder state */
1905 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1906 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32 1907
c465613b 1908 if (HAS_PCH_CPT(dev)) {
23670b32
DV		 1909 /* Workaround: Clear the timing override chicken bit again. */
1910 reg = TRANS_CHICKEN2(pipe);
1911 val = I915_READ(reg);
1912 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1913 I915_WRITE(reg, val);
1914 }
040484af
JB		 1915}
1916
ab4d966c 1917static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1918{
8fb033d7
PZ		 1919 u32 val;
1920
ab9412ba 1921 val = I915_READ(LPT_TRANSCONF);
8fb033d7 1922 val &= ~TRANS_ENABLE;
ab9412ba 1923 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 1924 /* wait for PCH transcoder off, transcoder state */
ab9412ba 1925 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 1926 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1927
1928 /* Workaround: clear timing override bit. */
36c0d0cf 1929 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
23670b32 1930 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
36c0d0cf 1931 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
040484af
JB		 1932}
1933
b24e7179 1934/**
309cfea8 1935 * intel_enable_pipe - enable a pipe, asserting requirements
0372264a 1936 * @crtc: crtc responsible for the pipe
b24e7179 1937 *
0372264a 1938 * Enable @crtc's pipe, making sure that various hardware specific requirements
b24e7179 1939 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
b24e7179 1940 */
e1fdc473 1941static void intel_enable_pipe(struct intel_crtc *crtc)
b24e7179 1942{
0372264a
PZ		 1943 struct drm_device *dev = crtc->base.dev;
1944 struct drm_i915_private *dev_priv = dev->dev_private;
1945 enum pipe pipe = crtc->pipe;
1a70a728 1946 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1a240d4d 1947 enum pipe pch_transcoder;
f0f59a00 1948 i915_reg_t reg;
b24e7179
JB		 1949 u32 val;
1950
9e2ee2dd
VS		 1951 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1952
58c6eaa2 1953 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 1954 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 1955 assert_sprites_disabled(dev_priv, pipe);
1956
681e5811 1957 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1958 pch_transcoder = TRANSCODER_A;
1959 else
1960 pch_transcoder = pipe;
1961
b24e7179
JB		 1962 /*
1963 * A pipe without a PLL won't actually be able to drive bits from
1964 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1965 * need the check.
1966 */
50360403 1967 if (HAS_GMCH_DISPLAY(dev_priv->dev))
a65347ba 1968 if (crtc->config->has_dsi_encoder)
23538ef1
JN		 1969 assert_dsi_pll_enabled(dev_priv);
1970 else
1971 assert_pll_enabled(dev_priv, pipe);
040484af 1972 else {
6e3c9717 1973 if (crtc->config->has_pch_encoder) {
040484af 1974 /* if driving the PCH, we need FDI enabled */
cc391bbb 1975 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1976 assert_fdi_tx_pll_enabled(dev_priv,
1977 (enum pipe) cpu_transcoder);
040484af
JB		 1978 }
1979 /* FIXME: assert CPU port conditions for SNB+ */
1980 }
b24e7179 1981
702e7a56 1982 reg = PIPECONF(cpu_transcoder);
b24e7179 1983 val = I915_READ(reg);
7ad25d48 1984 if (val & PIPECONF_ENABLE) {
b6b5d049
VS		 1985 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1986 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
00d70b15 1987 return;
7ad25d48 1988 }
00d70b15
CW		 1989
1990 I915_WRITE(reg, val | PIPECONF_ENABLE);
851855d8 1991 POSTING_READ(reg);
b7792d8b
VS		 1992
1993 /*
1994 * Until the pipe starts DSL will read as 0, which would cause
1995 * an apparent vblank timestamp jump, which messes up also the
1996 * frame count when it's derived from the timestamps. So let's
1997 * wait for the pipe to start properly before we call
1998 * drm_crtc_vblank_on()
1999 */
2000 if (dev->max_vblank_count == 0 &&
2001 wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
2002 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
b24e7179
JB		 2003}
2004
2005/**
309cfea8 2006 * intel_disable_pipe - disable a pipe, asserting requirements
575f7ab7 2007 * @crtc: crtc whose pipes is to be disabled
b24e7179 2008 *
575f7ab7
VS		 2009 * Disable the pipe of @crtc, making sure that various hardware
2010 * specific requirements are met, if applicable, e.g. plane
2011 * disabled, panel fitter off, etc.
b24e7179
JB		 2012 *
2013 * Will wait until the pipe has shut down before returning.
2014 */
575f7ab7 2015static void intel_disable_pipe(struct intel_crtc *crtc)
b24e7179 2016{
575f7ab7 2017 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
6e3c9717 2018 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 2019 enum pipe pipe = crtc->pipe;
f0f59a00 2020 i915_reg_t reg;
b24e7179
JB		 2021 u32 val;
2022
9e2ee2dd
VS		 2023 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2024
b24e7179
JB		 2025 /*
2026 * Make sure planes won't keep trying to pump pixels to us,
2027 * or we might hang the display.
2028 */
2029 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2030 assert_cursor_disabled(dev_priv, pipe);
19332d7a 2031 assert_sprites_disabled(dev_priv, pipe);
b24e7179 2032
702e7a56 2033 reg = PIPECONF(cpu_transcoder);
b24e7179 2034 val = I915_READ(reg);
00d70b15
CW		 2035 if ((val & PIPECONF_ENABLE) == 0)
2036 return;
2037
67adc644
VS		 2038 /*
2039 * Double wide has implications for planes
2040 * so best keep it disabled when not needed.
2041 */
6e3c9717 2042 if (crtc->config->double_wide)
67adc644
VS		 2043 val &= ~PIPECONF_DOUBLE_WIDE;
2044
2045 /* Don't disable pipe or pipe PLLs if needed */
b6b5d049
VS		 2046 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2047 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
67adc644
VS		 2048 val &= ~PIPECONF_ENABLE;
2049
2050 I915_WRITE(reg, val);
2051 if ((val & PIPECONF_ENABLE) == 0)
2052 intel_wait_for_pipe_off(crtc);
b24e7179
JB		 2053}
2054
693db184
CW		 2055static bool need_vtd_wa(struct drm_device *dev)
2056{
2057#ifdef CONFIG_INTEL_IOMMU
2058 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2059 return true;
2060#endif
2061 return false;
2062}
2063
832be82f
VS		 2064static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2065{
2066 return IS_GEN2(dev_priv) ? 2048 : 4096;
2067}
2068
27ba3910
VS		 2069static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv,
2070 uint64_t fb_modifier, unsigned int cpp)
7b49f948
VS		 2071{
2072 switch (fb_modifier) {
2073 case DRM_FORMAT_MOD_NONE:
2074 return cpp;
2075 case I915_FORMAT_MOD_X_TILED:
2076 if (IS_GEN2(dev_priv))
2077 return 128;
2078 else
2079 return 512;
2080 case I915_FORMAT_MOD_Y_TILED:
2081 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2082 return 128;
2083 else
2084 return 512;
2085 case I915_FORMAT_MOD_Yf_TILED:
2086 switch (cpp) {
2087 case 1:
2088 return 64;
2089 case 2:
2090 case 4:
2091 return 128;
2092 case 8:
2093 case 16:
2094 return 256;
2095 default:
2096 MISSING_CASE(cpp);
2097 return cpp;
2098 }
2099 break;
2100 default:
2101 MISSING_CASE(fb_modifier);
2102 return cpp;
2103 }
2104}
2105
832be82f
VS		 2106unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2107 uint64_t fb_modifier, unsigned int cpp)
a57ce0b2 2108{
832be82f
VS		 2109 if (fb_modifier == DRM_FORMAT_MOD_NONE)
2110 return 1;
2111 else
2112 return intel_tile_size(dev_priv) /
27ba3910 2113 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
6761dd31
TU		 2114}
2115
8d0deca8
VS		 2116/* Return the tile dimensions in pixel units */
2117static void intel_tile_dims(const struct drm_i915_private *dev_priv,
2118 unsigned int *tile_width,
2119 unsigned int *tile_height,
2120 uint64_t fb_modifier,
2121 unsigned int cpp)
2122{
2123 unsigned int tile_width_bytes =
2124 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2125
2126 *tile_width = tile_width_bytes / cpp;
2127 *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
2128}
2129
6761dd31
TU		 2130unsigned int
2131intel_fb_align_height(struct drm_device *dev, unsigned int height,
832be82f 2132 uint32_t pixel_format, uint64_t fb_modifier)
6761dd31 2133{
832be82f
VS		 2134 unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2135 unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2136
2137 return ALIGN(height, tile_height);
a57ce0b2
JB		 2138}
2139
1663b9d6
VS		 2140unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2141{
2142 unsigned int size = 0;
2143 int i;
2144
2145 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2146 size += rot_info->plane[i].width * rot_info->plane[i].height;
2147
2148 return size;
2149}
2150
75c82a53 2151static void
3465c580
VS		 2152intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2153 const struct drm_framebuffer *fb,
2154 unsigned int rotation)
f64b98cd 2155{
2d7a215f
VS		 2156 if (intel_rotation_90_or_270(rotation)) {
2157 *view = i915_ggtt_view_rotated;
2158 view->params.rotated = to_intel_framebuffer(fb)->rot_info;
2159 } else {
2160 *view = i915_ggtt_view_normal;
2161 }
2162}
50470bb0 2163
2d7a215f
VS		 2164static void
2165intel_fill_fb_info(struct drm_i915_private *dev_priv,
2166 struct drm_framebuffer *fb)
2167{
2168 struct intel_rotation_info *info = &to_intel_framebuffer(fb)->rot_info;
2169 unsigned int tile_size, tile_width, tile_height, cpp;
50470bb0 2170
d9b3288e
VS		 2171 tile_size = intel_tile_size(dev_priv);
2172
2173 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
8d0deca8
VS		 2174 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2175 fb->modifier[0], cpp);
d9b3288e 2176
1663b9d6
VS		 2177 info->plane[0].width = DIV_ROUND_UP(fb->pitches[0], tile_width * cpp);
2178 info->plane[0].height = DIV_ROUND_UP(fb->height, tile_height);
84fe03f7 2179
89e3e142 2180 if (info->pixel_format == DRM_FORMAT_NV12) {
832be82f 2181 cpp = drm_format_plane_cpp(fb->pixel_format, 1);
8d0deca8
VS		 2182 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2183 fb->modifier[1], cpp);
d9b3288e 2184
2d7a215f 2185 info->uv_offset = fb->offsets[1];
1663b9d6
VS		 2186 info->plane[1].width = DIV_ROUND_UP(fb->pitches[1], tile_width * cpp);
2187 info->plane[1].height = DIV_ROUND_UP(fb->height / 2, tile_height);
89e3e142 2188 }
f64b98cd
TU		 2189}
2190
603525d7 2191static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
4e9a86b6
VS		 2192{
2193 if (INTEL_INFO(dev_priv)->gen >= 9)
2194 return 256 * 1024;
985b8bb4 2195 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
666a4537 2196 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4e9a86b6
VS		 2197 return 128 * 1024;
2198 else if (INTEL_INFO(dev_priv)->gen >= 4)
2199 return 4 * 1024;
2200 else
44c5905e 2201 return 0;
4e9a86b6
VS		 2202}
2203
603525d7
VS		 2204static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2205 uint64_t fb_modifier)
2206{
2207 switch (fb_modifier) {
2208 case DRM_FORMAT_MOD_NONE:
2209 return intel_linear_alignment(dev_priv);
2210 case I915_FORMAT_MOD_X_TILED:
2211 if (INTEL_INFO(dev_priv)->gen >= 9)
2212 return 256 * 1024;
2213 return 0;
2214 case I915_FORMAT_MOD_Y_TILED:
2215 case I915_FORMAT_MOD_Yf_TILED:
2216 return 1 * 1024 * 1024;
2217 default:
2218 MISSING_CASE(fb_modifier);
2219 return 0;
2220 }
2221}
2222
127bd2ac 2223int
3465c580
VS		 2224intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2225 unsigned int rotation)
6b95a207 2226{
850c4cdc 2227 struct drm_device *dev = fb->dev;
ce453d81 2228 struct drm_i915_private *dev_priv = dev->dev_private;
850c4cdc 2229 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd 2230 struct i915_ggtt_view view;
6b95a207
KH		 2231 u32 alignment;
2232 int ret;
2233
ebcdd39e
MR		 2234 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2235
603525d7 2236 alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
6b95a207 2237
3465c580 2238 intel_fill_fb_ggtt_view(&view, fb, rotation);
f64b98cd 2239
693db184
CW		 2240 /* Note that the w/a also requires 64 PTE of padding following the
2241 * bo. We currently fill all unused PTE with the shadow page and so
2242 * we should always have valid PTE following the scanout preventing
2243 * the VT-d warning.
2244 */
2245 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2246 alignment = 256 * 1024;
2247
d6dd6843
PZ		 2248 /*
2249 * Global gtt pte registers are special registers which actually forward
2250 * writes to a chunk of system memory. Which means that there is no risk
2251 * that the register values disappear as soon as we call
2252 * intel_runtime_pm_put(), so it is correct to wrap only the
2253 * pin/unpin/fence and not more.
2254 */
2255 intel_runtime_pm_get(dev_priv);
2256
7580d774
ML		 2257 ret = i915_gem_object_pin_to_display_plane(obj, alignment,
2258 &view);
48b956c5 2259 if (ret)
b26a6b35 2260 goto err_pm;
6b95a207
KH		 2261
2262 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2263 * fence, whereas 965+ only requires a fence if using
2264 * framebuffer compression. For simplicity, we always install
2265 * a fence as the cost is not that onerous.
2266 */
9807216f
VK		 2267 if (view.type == I915_GGTT_VIEW_NORMAL) {
2268 ret = i915_gem_object_get_fence(obj);
2269 if (ret == -EDEADLK) {
2270 /*
2271 * -EDEADLK means there are no free fences
2272 * no pending flips.
2273 *
2274 * This is propagated to atomic, but it uses
2275 * -EDEADLK to force a locking recovery, so
2276 * change the returned error to -EBUSY.
2277 */
2278 ret = -EBUSY;
2279 goto err_unpin;
2280 } else if (ret)
2281 goto err_unpin;
1690e1eb 2282
9807216f
VK		 2283 i915_gem_object_pin_fence(obj);
2284 }
6b95a207 2285
d6dd6843 2286 intel_runtime_pm_put(dev_priv);
6b95a207 2287 return 0;
48b956c5
CW		 2288
2289err_unpin:
f64b98cd 2290 i915_gem_object_unpin_from_display_plane(obj, &view);
b26a6b35 2291err_pm:
d6dd6843 2292 intel_runtime_pm_put(dev_priv);
48b956c5 2293 return ret;
6b95a207
KH		 2294}
2295
3465c580 2296static void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
1690e1eb 2297{
82bc3b2d 2298 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd 2299 struct i915_ggtt_view view;
82bc3b2d 2300
ebcdd39e
MR		 2301 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2302
3465c580 2303 intel_fill_fb_ggtt_view(&view, fb, rotation);
f64b98cd 2304
9807216f
VK		 2305 if (view.type == I915_GGTT_VIEW_NORMAL)
2306 i915_gem_object_unpin_fence(obj);
2307
f64b98cd 2308 i915_gem_object_unpin_from_display_plane(obj, &view);
1690e1eb
CW		 2309}
2310
29cf9491
VS		 2311/*
2312 * Adjust the tile offset by moving the difference into
2313 * the x/y offsets.
2314 *
2315 * Input tile dimensions and pitch must already be
2316 * rotated to match x and y, and in pixel units.
2317 */
2318static u32 intel_adjust_tile_offset(int *x, int *y,
2319 unsigned int tile_width,
2320 unsigned int tile_height,
2321 unsigned int tile_size,
2322 unsigned int pitch_tiles,
2323 u32 old_offset,
2324 u32 new_offset)
2325{
2326 unsigned int tiles;
2327
2328 WARN_ON(old_offset & (tile_size - 1));
2329 WARN_ON(new_offset & (tile_size - 1));
2330 WARN_ON(new_offset > old_offset);
2331
2332 tiles = (old_offset - new_offset) / tile_size;
2333
2334 *y += tiles / pitch_tiles * tile_height;
2335 *x += tiles % pitch_tiles * tile_width;
2336
2337 return new_offset;
2338}
2339
8d0deca8
VS		 2340/*
2341 * Computes the linear offset to the base tile and adjusts
2342 * x, y. bytes per pixel is assumed to be a power-of-two.
2343 *
2344 * In the 90/270 rotated case, x and y are assumed
2345 * to be already rotated to match the rotated GTT view, and
2346 * pitch is the tile_height aligned framebuffer height.
2347 */
4f2d9934
VS		 2348u32 intel_compute_tile_offset(int *x, int *y,
2349 const struct drm_framebuffer *fb, int plane,
8d0deca8
VS		 2350 unsigned int pitch,
2351 unsigned int rotation)
c2c75131 2352{
4f2d9934
VS		 2353 const struct drm_i915_private *dev_priv = to_i915(fb->dev);
2354 uint64_t fb_modifier = fb->modifier[plane];
2355 unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
29cf9491
VS		 2356 u32 offset, offset_aligned, alignment;
2357
2358 alignment = intel_surf_alignment(dev_priv, fb_modifier);
2359 if (alignment)
2360 alignment--;
2361
b5c65338 2362 if (fb_modifier != DRM_FORMAT_MOD_NONE) {
8d0deca8
VS		 2363 unsigned int tile_size, tile_width, tile_height;
2364 unsigned int tile_rows, tiles, pitch_tiles;
c2c75131 2365
d843310d 2366 tile_size = intel_tile_size(dev_priv);
8d0deca8
VS		 2367 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2368 fb_modifier, cpp);
2369
2370 if (intel_rotation_90_or_270(rotation)) {
2371 pitch_tiles = pitch / tile_height;
2372 swap(tile_width, tile_height);
2373 } else {
2374 pitch_tiles = pitch / (tile_width * cpp);
2375 }
d843310d
VS		 2376
2377 tile_rows = *y / tile_height;
2378 *y %= tile_height;
c2c75131 2379
8d0deca8
VS		 2380 tiles = *x / tile_width;
2381 *x %= tile_width;
bc752862 2382
29cf9491
VS		 2383 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2384 offset_aligned = offset & ~alignment;
bc752862 2385
29cf9491
VS		 2386 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2387 tile_size, pitch_tiles,
2388 offset, offset_aligned);
2389 } else {
bc752862 2390 offset = *y * pitch + *x * cpp;
29cf9491
VS		 2391 offset_aligned = offset & ~alignment;
2392
4e9a86b6
VS		 2393 *y = (offset & alignment) / pitch;
2394 *x = ((offset & alignment) - *y * pitch) / cpp;
bc752862 2395 }
29cf9491
VS		 2396
2397 return offset_aligned;
c2c75131
DV		 2398}
2399
b35d63fa 2400static int i9xx_format_to_fourcc(int format)
46f297fb
JB		 2401{
2402 switch (format) {
2403 case DISPPLANE_8BPP:
2404 return DRM_FORMAT_C8;
2405 case DISPPLANE_BGRX555:
2406 return DRM_FORMAT_XRGB1555;
2407 case DISPPLANE_BGRX565:
2408 return DRM_FORMAT_RGB565;
2409 default:
2410 case DISPPLANE_BGRX888:
2411 return DRM_FORMAT_XRGB8888;
2412 case DISPPLANE_RGBX888:
2413 return DRM_FORMAT_XBGR8888;
2414 case DISPPLANE_BGRX101010:
2415 return DRM_FORMAT_XRGB2101010;
2416 case DISPPLANE_RGBX101010:
2417 return DRM_FORMAT_XBGR2101010;
2418 }
2419}
2420
bc8d7dff
DL		 2421static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2422{
2423 switch (format) {
2424 case PLANE_CTL_FORMAT_RGB_565:
2425 return DRM_FORMAT_RGB565;
2426 default:
2427 case PLANE_CTL_FORMAT_XRGB_8888:
2428 if (rgb_order) {
2429 if (alpha)
2430 return DRM_FORMAT_ABGR8888;
2431 else
2432 return DRM_FORMAT_XBGR8888;
2433 } else {
2434 if (alpha)
2435 return DRM_FORMAT_ARGB8888;
2436 else
2437 return DRM_FORMAT_XRGB8888;
2438 }
2439 case PLANE_CTL_FORMAT_XRGB_2101010:
2440 if (rgb_order)
2441 return DRM_FORMAT_XBGR2101010;
2442 else
2443 return DRM_FORMAT_XRGB2101010;
2444 }
2445}
2446
5724dbd1 2447static bool
f6936e29
DV		 2448intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2449 struct intel_initial_plane_config *plane_config)
46f297fb
JB		 2450{
2451 struct drm_device *dev = crtc->base.dev;
3badb49f 2452 struct drm_i915_private *dev_priv = to_i915(dev);
72e96d64 2453 struct i915_ggtt *ggtt = &dev_priv->ggtt;
46f297fb
JB		 2454 struct drm_i915_gem_object *obj = NULL;
2455 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2d14030b 2456 struct drm_framebuffer *fb = &plane_config->fb->base;
f37b5c2b
DV		 2457 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2458 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2459 PAGE_SIZE);
2460
2461 size_aligned -= base_aligned;
46f297fb 2462
ff2652ea
CW		 2463 if (plane_config->size == 0)
2464 return false;
2465
3badb49f
PZ		 2466 /* If the FB is too big, just don't use it since fbdev is not very
2467 * important and we should probably use that space with FBC or other
2468 * features. */
72e96d64 2469 if (size_aligned * 2 > ggtt->stolen_usable_size)
3badb49f
PZ		 2470 return false;
2471
12c83d99
TU		 2472 mutex_lock(&dev->struct_mutex);
2473
f37b5c2b
DV		 2474 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2475 base_aligned,
2476 base_aligned,
2477 size_aligned);
12c83d99
TU		 2478 if (!obj) {
2479 mutex_unlock(&dev->struct_mutex);
484b41dd 2480 return false;
12c83d99 2481 }
46f297fb 2482
49af449b
DL		 2483 obj->tiling_mode = plane_config->tiling;
2484 if (obj->tiling_mode == I915_TILING_X)
6bf129df 2485 obj->stride = fb->pitches[0];
46f297fb 2486
6bf129df
DL		 2487 mode_cmd.pixel_format = fb->pixel_format;
2488 mode_cmd.width = fb->width;
2489 mode_cmd.height = fb->height;
2490 mode_cmd.pitches[0] = fb->pitches[0];
18c5247e
DV		 2491 mode_cmd.modifier[0] = fb->modifier[0];
2492 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
46f297fb 2493
6bf129df 2494 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
484b41dd 2495 &mode_cmd, obj)) {
46f297fb
JB		 2496 DRM_DEBUG_KMS("intel fb init failed\n");
2497 goto out_unref_obj;
2498 }
12c83d99 2499
46f297fb 2500 mutex_unlock(&dev->struct_mutex);
484b41dd 2501
f6936e29 2502 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
484b41dd 2503 return true;
46f297fb
JB		 2504
2505out_unref_obj:
2506 drm_gem_object_unreference(&obj->base);
2507 mutex_unlock(&dev->struct_mutex);
484b41dd
JB		 2508 return false;
2509}
2510
afd65eb4
MR		 2511/* Update plane->state->fb to match plane->fb after driver-internal updates */
2512static void
2513update_state_fb(struct drm_plane *plane)
2514{
2515 if (plane->fb == plane->state->fb)
2516 return;
2517
2518 if (plane->state->fb)
2519 drm_framebuffer_unreference(plane->state->fb);
2520 plane->state->fb = plane->fb;
2521 if (plane->state->fb)
2522 drm_framebuffer_reference(plane->state->fb);
2523}
2524
5724dbd1 2525static void
f6936e29
DV		 2526intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2527 struct intel_initial_plane_config *plane_config)
484b41dd
JB		 2528{
2529 struct drm_device *dev = intel_crtc->base.dev;
d9ceb816 2530 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd
JB		 2531 struct drm_crtc *c;
2532 struct intel_crtc *i;
2ff8fde1 2533 struct drm_i915_gem_object *obj;
88595ac9 2534 struct drm_plane *primary = intel_crtc->base.primary;
be5651f2 2535 struct drm_plane_state *plane_state = primary->state;
200757f5
MR		 2536 struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2537 struct intel_plane *intel_plane = to_intel_plane(primary);
0a8d8a86
MR		 2538 struct intel_plane_state *intel_state =
2539 to_intel_plane_state(plane_state);
88595ac9 2540 struct drm_framebuffer *fb;
484b41dd 2541
2d14030b 2542 if (!plane_config->fb)
484b41dd
JB		 2543 return;
2544
f6936e29 2545 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
88595ac9
DV		 2546 fb = &plane_config->fb->base;
2547 goto valid_fb;
f55548b5 2548 }
484b41dd 2549
2d14030b 2550 kfree(plane_config->fb);
484b41dd
JB		 2551
2552 /*
2553 * Failed to alloc the obj, check to see if we should share
2554 * an fb with another CRTC instead
2555 */
70e1e0ec 2556 for_each_crtc(dev, c) {
484b41dd
JB		 2557 i = to_intel_crtc(c);
2558
2559 if (c == &intel_crtc->base)
2560 continue;
2561
2ff8fde1
MR		 2562 if (!i->active)
2563 continue;
2564
88595ac9
DV		 2565 fb = c->primary->fb;
2566 if (!fb)
484b41dd
JB		 2567 continue;
2568
88595ac9 2569 obj = intel_fb_obj(fb);
2ff8fde1 2570 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
88595ac9
DV		 2571 drm_framebuffer_reference(fb);
2572 goto valid_fb;
484b41dd
JB		 2573 }
2574 }
88595ac9 2575
200757f5
MR		 2576 /*
2577 * We've failed to reconstruct the BIOS FB. Current display state
2578 * indicates that the primary plane is visible, but has a NULL FB,
2579 * which will lead to problems later if we don't fix it up. The
2580 * simplest solution is to just disable the primary plane now and
2581 * pretend the BIOS never had it enabled.
2582 */
2583 to_intel_plane_state(plane_state)->visible = false;
2584 crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2622a081 2585 intel_pre_disable_primary_noatomic(&intel_crtc->base);
200757f5
MR		 2586 intel_plane->disable_plane(primary, &intel_crtc->base);
2587
88595ac9
DV		 2588 return;
2589
2590valid_fb:
f44e2659
VS		 2591 plane_state->src_x = 0;
2592 plane_state->src_y = 0;
be5651f2
ML		 2593 plane_state->src_w = fb->width << 16;
2594 plane_state->src_h = fb->height << 16;
2595
f44e2659
VS		 2596 plane_state->crtc_x = 0;
2597 plane_state->crtc_y = 0;
be5651f2
ML		 2598 plane_state->crtc_w = fb->width;
2599 plane_state->crtc_h = fb->height;
2600
0a8d8a86
MR		 2601 intel_state->src.x1 = plane_state->src_x;
2602 intel_state->src.y1 = plane_state->src_y;
2603 intel_state->src.x2 = plane_state->src_x + plane_state->src_w;
2604 intel_state->src.y2 = plane_state->src_y + plane_state->src_h;
2605 intel_state->dst.x1 = plane_state->crtc_x;
2606 intel_state->dst.y1 = plane_state->crtc_y;
2607 intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w;
2608 intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h;
2609
88595ac9
DV		 2610 obj = intel_fb_obj(fb);
2611 if (obj->tiling_mode != I915_TILING_NONE)
2612 dev_priv->preserve_bios_swizzle = true;
2613
be5651f2
ML		 2614 drm_framebuffer_reference(fb);
2615 primary->fb = primary->state->fb = fb;
36750f28 2616 primary->crtc = primary->state->crtc = &intel_crtc->base;
36750f28 2617 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
a9ff8714 2618 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
46f297fb
JB		 2619}
2620
a8d201af
ML		 2621static void i9xx_update_primary_plane(struct drm_plane *primary,
2622 const struct intel_crtc_state *crtc_state,
2623 const struct intel_plane_state *plane_state)
81255565 2624{
a8d201af 2625 struct drm_device *dev = primary->dev;
81255565 2626 struct drm_i915_private *dev_priv = dev->dev_private;
a8d201af
ML		 2627 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2628 struct drm_framebuffer *fb = plane_state->base.fb;
2629 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
81255565 2630 int plane = intel_crtc->plane;
54ea9da8 2631 u32 linear_offset;
81255565 2632 u32 dspcntr;
f0f59a00 2633 i915_reg_t reg = DSPCNTR(plane);
8d0deca8 2634 unsigned int rotation = plane_state->base.rotation;
ac484963 2635 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
54ea9da8
VS		 2636 int x = plane_state->src.x1 >> 16;
2637 int y = plane_state->src.y1 >> 16;
c9ba6fad 2638
f45651ba
VS		 2639 dspcntr = DISPPLANE_GAMMA_ENABLE;
2640
fdd508a6 2641 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2642
2643 if (INTEL_INFO(dev)->gen < 4) {
2644 if (intel_crtc->pipe == PIPE_B)
2645 dspcntr |= DISPPLANE_SEL_PIPE_B;
2646
2647 /* pipesrc and dspsize control the size that is scaled from,
2648 * which should always be the user's requested size.
2649 */
2650 I915_WRITE(DSPSIZE(plane),
a8d201af
ML		 2651 ((crtc_state->pipe_src_h - 1) << 16) |
2652 (crtc_state->pipe_src_w - 1));
f45651ba 2653 I915_WRITE(DSPPOS(plane), 0);
c14b0485
VS		 2654 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2655 I915_WRITE(PRIMSIZE(plane),
a8d201af
ML		 2656 ((crtc_state->pipe_src_h - 1) << 16) |
2657 (crtc_state->pipe_src_w - 1));
c14b0485
VS		 2658 I915_WRITE(PRIMPOS(plane), 0);
2659 I915_WRITE(PRIMCNSTALPHA(plane), 0);
f45651ba 2660 }
81255565 2661
57779d06
VS		 2662 switch (fb->pixel_format) {
2663 case DRM_FORMAT_C8:
81255565
JB		 2664 dspcntr |= DISPPLANE_8BPP;
2665 break;
57779d06 2666 case DRM_FORMAT_XRGB1555:
57779d06 2667 dspcntr |= DISPPLANE_BGRX555;
81255565 2668 break;
57779d06
VS		 2669 case DRM_FORMAT_RGB565:
2670 dspcntr |= DISPPLANE_BGRX565;
2671 break;
2672 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2673 dspcntr |= DISPPLANE_BGRX888;
2674 break;
2675 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2676 dspcntr |= DISPPLANE_RGBX888;
2677 break;
2678 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2679 dspcntr |= DISPPLANE_BGRX101010;
2680 break;
2681 case DRM_FORMAT_XBGR2101010:
57779d06 2682 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2683 break;
2684 default:
baba133a 2685 BUG();
81255565 2686 }
57779d06 2687
f45651ba
VS		 2688 if (INTEL_INFO(dev)->gen >= 4 &&
2689 obj->tiling_mode != I915_TILING_NONE)
2690 dspcntr |= DISPPLANE_TILED;
81255565 2691
de1aa629
VS		 2692 if (IS_G4X(dev))
2693 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2694
ac484963 2695 linear_offset = y * fb->pitches[0] + x * cpp;
81255565 2696
c2c75131
DV		 2697 if (INTEL_INFO(dev)->gen >= 4) {
2698 intel_crtc->dspaddr_offset =
4f2d9934 2699 intel_compute_tile_offset(&x, &y, fb, 0,
8d0deca8 2700 fb->pitches[0], rotation);
c2c75131
DV		 2701 linear_offset -= intel_crtc->dspaddr_offset;
2702 } else {
e506a0c6 2703 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2704 }
e506a0c6 2705
8d0deca8 2706 if (rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2707 dspcntr |= DISPPLANE_ROTATE_180;
2708
a8d201af
ML		 2709 x += (crtc_state->pipe_src_w - 1);
2710 y += (crtc_state->pipe_src_h - 1);
48404c1e
SJ		 2711
2712 /* Finding the last pixel of the last line of the display
2713 data and adding to linear_offset*/
2714 linear_offset +=
a8d201af 2715 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
ac484963 2716 (crtc_state->pipe_src_w - 1) * cpp;
48404c1e
SJ		 2717 }
2718
2db3366b
PZ		 2719 intel_crtc->adjusted_x = x;
2720 intel_crtc->adjusted_y = y;
2721
48404c1e
SJ		 2722 I915_WRITE(reg, dspcntr);
2723
01f2c773 2724 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2725 if (INTEL_INFO(dev)->gen >= 4) {
85ba7b7d
DV		 2726 I915_WRITE(DSPSURF(plane),
2727 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2728 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2729 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2730 } else
f343c5f6 2731 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2732 POSTING_READ(reg);
17638cd6
JB		 2733}
2734
a8d201af
ML		 2735static void i9xx_disable_primary_plane(struct drm_plane *primary,
2736 struct drm_crtc *crtc)
17638cd6
JB		 2737{
2738 struct drm_device *dev = crtc->dev;
2739 struct drm_i915_private *dev_priv = dev->dev_private;
2740 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
17638cd6 2741 int plane = intel_crtc->plane;
f45651ba 2742
a8d201af
ML		 2743 I915_WRITE(DSPCNTR(plane), 0);
2744 if (INTEL_INFO(dev_priv)->gen >= 4)
fdd508a6 2745 I915_WRITE(DSPSURF(plane), 0);
a8d201af
ML		 2746 else
2747 I915_WRITE(DSPADDR(plane), 0);
2748 POSTING_READ(DSPCNTR(plane));
2749}
c9ba6fad 2750
a8d201af
ML		 2751static void ironlake_update_primary_plane(struct drm_plane *primary,
2752 const struct intel_crtc_state *crtc_state,
2753 const struct intel_plane_state *plane_state)
2754{
2755 struct drm_device *dev = primary->dev;
2756 struct drm_i915_private *dev_priv = dev->dev_private;
2757 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2758 struct drm_framebuffer *fb = plane_state->base.fb;
2759 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2760 int plane = intel_crtc->plane;
54ea9da8 2761 u32 linear_offset;
a8d201af
ML		 2762 u32 dspcntr;
2763 i915_reg_t reg = DSPCNTR(plane);
8d0deca8 2764 unsigned int rotation = plane_state->base.rotation;
ac484963 2765 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
a8d201af
ML		 2766 int x = plane_state->src.x1 >> 16;
2767 int y = plane_state->src.y1 >> 16;
c9ba6fad 2768
f45651ba 2769 dspcntr = DISPPLANE_GAMMA_ENABLE;
fdd508a6 2770 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2771
2772 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2773 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
17638cd6 2774
57779d06
VS		 2775 switch (fb->pixel_format) {
2776 case DRM_FORMAT_C8:
17638cd6
JB		 2777 dspcntr |= DISPPLANE_8BPP;
2778 break;
57779d06
VS		 2779 case DRM_FORMAT_RGB565:
2780 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2781 break;
57779d06 2782 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2783 dspcntr |= DISPPLANE_BGRX888;
2784 break;
2785 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2786 dspcntr |= DISPPLANE_RGBX888;
2787 break;
2788 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2789 dspcntr |= DISPPLANE_BGRX101010;
2790 break;
2791 case DRM_FORMAT_XBGR2101010:
57779d06 2792 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2793 break;
2794 default:
baba133a 2795 BUG();
17638cd6
JB		 2796 }
2797
2798 if (obj->tiling_mode != I915_TILING_NONE)
2799 dspcntr |= DISPPLANE_TILED;
17638cd6 2800
f45651ba 2801 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
1f5d76db 2802 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6 2803
ac484963 2804 linear_offset = y * fb->pitches[0] + x * cpp;
c2c75131 2805 intel_crtc->dspaddr_offset =
4f2d9934 2806 intel_compute_tile_offset(&x, &y, fb, 0,
8d0deca8 2807 fb->pitches[0], rotation);
c2c75131 2808 linear_offset -= intel_crtc->dspaddr_offset;
8d0deca8 2809 if (rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2810 dspcntr |= DISPPLANE_ROTATE_180;
2811
2812 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
a8d201af
ML		 2813 x += (crtc_state->pipe_src_w - 1);
2814 y += (crtc_state->pipe_src_h - 1);
48404c1e
SJ		 2815
2816 /* Finding the last pixel of the last line of the display
2817 data and adding to linear_offset*/
2818 linear_offset +=
a8d201af 2819 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
ac484963 2820 (crtc_state->pipe_src_w - 1) * cpp;
48404c1e
SJ		 2821 }
2822 }
2823
2db3366b
PZ		 2824 intel_crtc->adjusted_x = x;
2825 intel_crtc->adjusted_y = y;
2826
48404c1e 2827 I915_WRITE(reg, dspcntr);
17638cd6 2828
01f2c773 2829 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
85ba7b7d
DV		 2830 I915_WRITE(DSPSURF(plane),
2831 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
b3dc685e 2832 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
bc1c91eb
DL		 2833 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2834 } else {
2835 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2836 I915_WRITE(DSPLINOFF(plane), linear_offset);
2837 }
17638cd6 2838 POSTING_READ(reg);
17638cd6
JB		 2839}
2840
7b49f948
VS		 2841u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
2842 uint64_t fb_modifier, uint32_t pixel_format)
b321803d 2843{
7b49f948 2844 if (fb_modifier == DRM_FORMAT_MOD_NONE) {
b321803d 2845 return 64;
7b49f948
VS		 2846 } else {
2847 int cpp = drm_format_plane_cpp(pixel_format, 0);
2848
27ba3910 2849 return intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
b321803d
DL		 2850 }
2851}
2852
44eb0cb9
MK		 2853u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
2854 struct drm_i915_gem_object *obj,
2855 unsigned int plane)
121920fa 2856{
ce7f1728 2857 struct i915_ggtt_view view;
dedf278c 2858 struct i915_vma *vma;
44eb0cb9 2859 u64 offset;
121920fa 2860
e7941294 2861 intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb,
3465c580 2862 intel_plane->base.state->rotation);
121920fa 2863
ce7f1728 2864 vma = i915_gem_obj_to_ggtt_view(obj, &view);
dedf278c 2865 if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
ce7f1728 2866 view.type))
dedf278c
TU		 2867 return -1;
2868
44eb0cb9 2869 offset = vma->node.start;
dedf278c
TU		 2870
2871 if (plane == 1) {
7723f47d 2872 offset += vma->ggtt_view.params.rotated.uv_start_page *
dedf278c
TU		 2873 PAGE_SIZE;
2874 }
2875
44eb0cb9
MK		 2876 WARN_ON(upper_32_bits(offset));
2877
2878 return lower_32_bits(offset);
121920fa
TU		 2879}
2880
e435d6e5
ML		 2881static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2882{
2883 struct drm_device *dev = intel_crtc->base.dev;
2884 struct drm_i915_private *dev_priv = dev->dev_private;
2885
2886 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2887 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2888 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
e435d6e5
ML		 2889}
2890
a1b2278e
CK		 2891/*
2892 * This function detaches (aka. unbinds) unused scalers in hardware
2893 */
0583236e 2894static void skl_detach_scalers(struct intel_crtc *intel_crtc)
a1b2278e 2895{
a1b2278e
CK		 2896 struct intel_crtc_scaler_state *scaler_state;
2897 int i;
2898
a1b2278e
CK		 2899 scaler_state = &intel_crtc->config->scaler_state;
2900
2901 /* loop through and disable scalers that aren't in use */
2902 for (i = 0; i < intel_crtc->num_scalers; i++) {
e435d6e5
ML		 2903 if (!scaler_state->scalers[i].in_use)
2904 skl_detach_scaler(intel_crtc, i);
a1b2278e
CK		 2905 }
2906}
2907
6156a456 2908u32 skl_plane_ctl_format(uint32_t pixel_format)
70d21f0e 2909{
6156a456 2910 switch (pixel_format) {
d161cf7a 2911 case DRM_FORMAT_C8:
c34ce3d1 2912 return PLANE_CTL_FORMAT_INDEXED;
70d21f0e 2913 case DRM_FORMAT_RGB565:
c34ce3d1 2914 return PLANE_CTL_FORMAT_RGB_565;
70d21f0e 2915 case DRM_FORMAT_XBGR8888:
c34ce3d1 2916 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
6156a456 2917 case DRM_FORMAT_XRGB8888:
c34ce3d1 2918 return PLANE_CTL_FORMAT_XRGB_8888;
6156a456
CK		 2919 /*
2920 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2921 * to be already pre-multiplied. We need to add a knob (or a different
2922 * DRM_FORMAT) for user-space to configure that.
2923 */
f75fb42a 2924 case DRM_FORMAT_ABGR8888:
c34ce3d1 2925 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
6156a456 2926 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
6156a456 2927 case DRM_FORMAT_ARGB8888:
c34ce3d1 2928 return PLANE_CTL_FORMAT_XRGB_8888 |
6156a456 2929 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
70d21f0e 2930 case DRM_FORMAT_XRGB2101010:
c34ce3d1 2931 return PLANE_CTL_FORMAT_XRGB_2101010;
70d21f0e 2932 case DRM_FORMAT_XBGR2101010:
c34ce3d1 2933 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
6156a456 2934 case DRM_FORMAT_YUYV:
c34ce3d1 2935 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
6156a456 2936 case DRM_FORMAT_YVYU:
c34ce3d1 2937 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
6156a456 2938 case DRM_FORMAT_UYVY:
c34ce3d1 2939 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
6156a456 2940 case DRM_FORMAT_VYUY:
c34ce3d1 2941 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
70d21f0e 2942 default:
4249eeef 2943 MISSING_CASE(pixel_format);
70d21f0e 2944 }
8cfcba41 2945
c34ce3d1 2946 return 0;
6156a456 2947}
70d21f0e 2948
6156a456
CK		 2949u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2950{
6156a456 2951 switch (fb_modifier) {
30af77c4 2952 case DRM_FORMAT_MOD_NONE:
70d21f0e 2953 break;
30af77c4 2954 case I915_FORMAT_MOD_X_TILED:
c34ce3d1 2955 return PLANE_CTL_TILED_X;
b321803d 2956 case I915_FORMAT_MOD_Y_TILED:
c34ce3d1 2957 return PLANE_CTL_TILED_Y;
b321803d 2958 case I915_FORMAT_MOD_Yf_TILED:
c34ce3d1 2959 return PLANE_CTL_TILED_YF;
70d21f0e 2960 default:
6156a456 2961 MISSING_CASE(fb_modifier);
70d21f0e 2962 }
8cfcba41 2963
c34ce3d1 2964 return 0;
6156a456 2965}
70d21f0e 2966
6156a456
CK		 2967u32 skl_plane_ctl_rotation(unsigned int rotation)
2968{
3b7a5119 2969 switch (rotation) {
6156a456
CK		 2970 case BIT(DRM_ROTATE_0):
2971 break;
1e8df167
SJ		 2972 /*
2973 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
2974 * while i915 HW rotation is clockwise, thats why this swapping.
2975 */
3b7a5119 2976 case BIT(DRM_ROTATE_90):
1e8df167 2977 return PLANE_CTL_ROTATE_270;
3b7a5119 2978 case BIT(DRM_ROTATE_180):
c34ce3d1 2979 return PLANE_CTL_ROTATE_180;
3b7a5119 2980 case BIT(DRM_ROTATE_270):
1e8df167 2981 return PLANE_CTL_ROTATE_90;
6156a456
CK		 2982 default:
2983 MISSING_CASE(rotation);
2984 }
2985
c34ce3d1 2986 return 0;
6156a456
CK		 2987}
2988
a8d201af
ML		 2989static void skylake_update_primary_plane(struct drm_plane *plane,
2990 const struct intel_crtc_state *crtc_state,
2991 const struct intel_plane_state *plane_state)
6156a456 2992{
a8d201af 2993 struct drm_device *dev = plane->dev;
6156a456 2994 struct drm_i915_private *dev_priv = dev->dev_private;
a8d201af
ML		 2995 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2996 struct drm_framebuffer *fb = plane_state->base.fb;
2997 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
6156a456
CK		 2998 int pipe = intel_crtc->pipe;
2999 u32 plane_ctl, stride_div, stride;
3000 u32 tile_height, plane_offset, plane_size;
a8d201af 3001 unsigned int rotation = plane_state->base.rotation;
6156a456 3002 int x_offset, y_offset;
44eb0cb9 3003 u32 surf_addr;
a8d201af
ML		 3004 int scaler_id = plane_state->scaler_id;
3005 int src_x = plane_state->src.x1 >> 16;
3006 int src_y = plane_state->src.y1 >> 16;
3007 int src_w = drm_rect_width(&plane_state->src) >> 16;
3008 int src_h = drm_rect_height(&plane_state->src) >> 16;
3009 int dst_x = plane_state->dst.x1;
3010 int dst_y = plane_state->dst.y1;
3011 int dst_w = drm_rect_width(&plane_state->dst);
3012 int dst_h = drm_rect_height(&plane_state->dst);
70d21f0e 3013
6156a456
CK		 3014 plane_ctl = PLANE_CTL_ENABLE |
3015 PLANE_CTL_PIPE_GAMMA_ENABLE |
3016 PLANE_CTL_PIPE_CSC_ENABLE;
3017
3018 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3019 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3020 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
6156a456
CK		 3021 plane_ctl |= skl_plane_ctl_rotation(rotation);
3022
7b49f948 3023 stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
b321803d 3024 fb->pixel_format);
dedf278c 3025 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3b7a5119 3026
a42e5a23
PZ		 3027 WARN_ON(drm_rect_width(&plane_state->src) == 0);
3028
3b7a5119 3029 if (intel_rotation_90_or_270(rotation)) {
832be82f
VS		 3030 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3031
3b7a5119 3032 /* stride = Surface height in tiles */
832be82f 3033 tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp);
3b7a5119 3034 stride = DIV_ROUND_UP(fb->height, tile_height);
a8d201af
ML		 3035 x_offset = stride * tile_height - src_y - src_h;
3036 y_offset = src_x;
6156a456 3037 plane_size = (src_w - 1) << 16 | (src_h - 1);
3b7a5119
SJ		 3038 } else {
3039 stride = fb->pitches[0] / stride_div;
a8d201af
ML		 3040 x_offset = src_x;
3041 y_offset = src_y;
6156a456 3042 plane_size = (src_h - 1) << 16 | (src_w - 1);
3b7a5119
SJ		 3043 }
3044 plane_offset = y_offset << 16 | x_offset;
b321803d 3045
2db3366b
PZ		 3046 intel_crtc->adjusted_x = x_offset;
3047 intel_crtc->adjusted_y = y_offset;
3048
70d21f0e 3049 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3b7a5119
SJ		 3050 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3051 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3052 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
6156a456
CK		 3053
3054 if (scaler_id >= 0) {
3055 uint32_t ps_ctrl = 0;
3056
3057 WARN_ON(!dst_w || !dst_h);
3058 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3059 crtc_state->scaler_state.scalers[scaler_id].mode;
3060 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3061 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3062 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3063 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3064 I915_WRITE(PLANE_POS(pipe, 0), 0);
3065 } else {
3066 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3067 }
3068
121920fa 3069 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
70d21f0e
DL		 3070
3071 POSTING_READ(PLANE_SURF(pipe, 0));
3072}
3073
a8d201af
ML		 3074static void skylake_disable_primary_plane(struct drm_plane *primary,
3075 struct drm_crtc *crtc)
17638cd6
JB		 3076{
3077 struct drm_device *dev = crtc->dev;
3078 struct drm_i915_private *dev_priv = dev->dev_private;
a8d201af 3079 int pipe = to_intel_crtc(crtc)->pipe;
17638cd6 3080
a8d201af
ML		 3081 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3082 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3083 POSTING_READ(PLANE_SURF(pipe, 0));
3084}
29b9bde6 3085
a8d201af
ML		 3086/* Assume fb object is pinned & idle & fenced and just update base pointers */
3087static int
3088intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3089 int x, int y, enum mode_set_atomic state)
3090{
3091 /* Support for kgdboc is disabled, this needs a major rework. */
3092 DRM_ERROR("legacy panic handler not supported any more.\n");
3093
3094 return -ENODEV;
81255565
JB		 3095}
3096
7514747d 3097static void intel_complete_page_flips(struct drm_device *dev)
96a02917 3098{
96a02917
VS		 3099 struct drm_crtc *crtc;
3100
70e1e0ec 3101 for_each_crtc(dev, crtc) {
96a02917
VS		 3102 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3103 enum plane plane = intel_crtc->plane;
3104
3105 intel_prepare_page_flip(dev, plane);
3106 intel_finish_page_flip_plane(dev, plane);
3107 }
7514747d
VS		 3108}
3109
3110static void intel_update_primary_planes(struct drm_device *dev)
3111{
7514747d 3112 struct drm_crtc *crtc;
96a02917 3113
70e1e0ec 3114 for_each_crtc(dev, crtc) {
11c22da6
ML		 3115 struct intel_plane *plane = to_intel_plane(crtc->primary);
3116 struct intel_plane_state *plane_state;
96a02917 3117
11c22da6 3118 drm_modeset_lock_crtc(crtc, &plane->base);
11c22da6
ML		 3119 plane_state = to_intel_plane_state(plane->base.state);
3120
a8d201af
ML		 3121 if (plane_state->visible)
3122 plane->update_plane(&plane->base,
3123 to_intel_crtc_state(crtc->state),
3124 plane_state);
11c22da6
ML		 3125
3126 drm_modeset_unlock_crtc(crtc);
96a02917
VS		 3127 }
3128}
3129
7514747d
VS		 3130void intel_prepare_reset(struct drm_device *dev)
3131{
3132 /* no reset support for gen2 */
3133 if (IS_GEN2(dev))
3134 return;
3135
3136 /* reset doesn't touch the display */
3137 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3138 return;
3139
3140 drm_modeset_lock_all(dev);
f98ce92f
VS		 3141 /*
3142 * Disabling the crtcs gracefully seems nicer. Also the
3143 * g33 docs say we should at least disable all the planes.
3144 */
6b72d486 3145 intel_display_suspend(dev);
7514747d
VS		 3146}
3147
3148void intel_finish_reset(struct drm_device *dev)
3149{
3150 struct drm_i915_private *dev_priv = to_i915(dev);
3151
3152 /*
3153 * Flips in the rings will be nuked by the reset,
3154 * so complete all pending flips so that user space
3155 * will get its events and not get stuck.
3156 */
3157 intel_complete_page_flips(dev);
3158
3159 /* no reset support for gen2 */
3160 if (IS_GEN2(dev))
3161 return;
3162
3163 /* reset doesn't touch the display */
3164 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3165 /*
3166 * Flips in the rings have been nuked by the reset,
3167 * so update the base address of all primary
3168 * planes to the the last fb to make sure we're
3169 * showing the correct fb after a reset.
11c22da6
ML		 3170 *
3171 * FIXME: Atomic will make this obsolete since we won't schedule
3172 * CS-based flips (which might get lost in gpu resets) any more.
7514747d
VS		 3173 */
3174 intel_update_primary_planes(dev);
3175 return;
3176 }
3177
3178 /*
3179 * The display has been reset as well,
3180 * so need a full re-initialization.
3181 */
3182 intel_runtime_pm_disable_interrupts(dev_priv);
3183 intel_runtime_pm_enable_interrupts(dev_priv);
3184
3185 intel_modeset_init_hw(dev);
3186
3187 spin_lock_irq(&dev_priv->irq_lock);
3188 if (dev_priv->display.hpd_irq_setup)
3189 dev_priv->display.hpd_irq_setup(dev);
3190 spin_unlock_irq(&dev_priv->irq_lock);
3191
043e9bda 3192 intel_display_resume(dev);
7514747d
VS		 3193
3194 intel_hpd_init(dev_priv);
3195
3196 drm_modeset_unlock_all(dev);
3197}
3198
7d5e3799
CW		 3199static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3200{
3201 struct drm_device *dev = crtc->dev;
3202 struct drm_i915_private *dev_priv = dev->dev_private;
3203 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7d5e3799
CW		 3204 bool pending;
3205
3206 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3207 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3208 return false;
3209
5e2d7afc 3210 spin_lock_irq(&dev->event_lock);
7d5e3799 3211 pending = to_intel_crtc(crtc)->unpin_work != NULL;
5e2d7afc 3212 spin_unlock_irq(&dev->event_lock);
7d5e3799
CW		 3213
3214 return pending;
3215}
3216
bfd16b2a
ML		 3217static void intel_update_pipe_config(struct intel_crtc *crtc,
3218 struct intel_crtc_state *old_crtc_state)
e30e8f75
GP		 3219{
3220 struct drm_device *dev = crtc->base.dev;
3221 struct drm_i915_private *dev_priv = dev->dev_private;
bfd16b2a
ML		 3222 struct intel_crtc_state *pipe_config =
3223 to_intel_crtc_state(crtc->base.state);
e30e8f75 3224
bfd16b2a
ML		 3225 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3226 crtc->base.mode = crtc->base.state->mode;
3227
3228 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3229 old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3230 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
e30e8f75
GP		 3231
3232 /*
3233 * Update pipe size and adjust fitter if needed: the reason for this is
3234 * that in compute_mode_changes we check the native mode (not the pfit
3235 * mode) to see if we can flip rather than do a full mode set. In the
3236 * fastboot case, we'll flip, but if we don't update the pipesrc and
3237 * pfit state, we'll end up with a big fb scanned out into the wrong
3238 * sized surface.
e30e8f75
GP		 3239 */
3240
e30e8f75 3241 I915_WRITE(PIPESRC(crtc->pipe),
bfd16b2a
ML		 3242 ((pipe_config->pipe_src_w - 1) << 16) |
3243 (pipe_config->pipe_src_h - 1));
3244
3245 /* on skylake this is done by detaching scalers */
3246 if (INTEL_INFO(dev)->gen >= 9) {
3247 skl_detach_scalers(crtc);
3248
3249 if (pipe_config->pch_pfit.enabled)
3250 skylake_pfit_enable(crtc);
3251 } else if (HAS_PCH_SPLIT(dev)) {
3252 if (pipe_config->pch_pfit.enabled)
3253 ironlake_pfit_enable(crtc);
3254 else if (old_crtc_state->pch_pfit.enabled)
3255 ironlake_pfit_disable(crtc, true);
e30e8f75 3256 }
e30e8f75
GP		 3257}
3258
5e84e1a4
ZW		 3259static void intel_fdi_normal_train(struct drm_crtc *crtc)
3260{
3261 struct drm_device *dev = crtc->dev;
3262 struct drm_i915_private *dev_priv = dev->dev_private;
3263 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3264 int pipe = intel_crtc->pipe;
f0f59a00
VS		 3265 i915_reg_t reg;
3266 u32 temp;
5e84e1a4
ZW		 3267
3268 /* enable normal train */
3269 reg = FDI_TX_CTL(pipe);
3270 temp = I915_READ(reg);
61e499bf 3271 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 3272 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3273 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 3274 } else {
3275 temp &= ~FDI_LINK_TRAIN_NONE;
3276 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 3277 }
5e84e1a4
ZW		 3278 I915_WRITE(reg, temp);
3279
3280 reg = FDI_RX_CTL(pipe);
3281 temp = I915_READ(reg);
3282 if (HAS_PCH_CPT(dev)) {
3283 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3284 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3285 } else {
3286 temp &= ~FDI_LINK_TRAIN_NONE;
3287 temp |= FDI_LINK_TRAIN_NONE;
3288 }
3289 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3290
3291 /* wait one idle pattern time */
3292 POSTING_READ(reg);
3293 udelay(1000);
357555c0
JB		 3294
3295 /* IVB wants error correction enabled */
3296 if (IS_IVYBRIDGE(dev))
3297 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3298 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 3299}
3300
8db9d77b
ZW		 3301/* The FDI link training functions for ILK/Ibexpeak. */
3302static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3303{
3304 struct drm_device *dev = crtc->dev;
3305 struct drm_i915_private *dev_priv = dev->dev_private;
3306 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3307 int pipe = intel_crtc->pipe;
f0f59a00
VS		 3308 i915_reg_t reg;
3309 u32 temp, tries;
8db9d77b 3310
1c8562f6 3311 /* FDI needs bits from pipe first */
0fc932b8 3312 assert_pipe_enabled(dev_priv, pipe);
0fc932b8 3313
e1a44743
AJ		 3314 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3315 for train result */
5eddb70b
CW		 3316 reg = FDI_RX_IMR(pipe);
3317 temp = I915_READ(reg);
e1a44743
AJ		 3318 temp &= ~FDI_RX_SYMBOL_LOCK;
3319 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3320 I915_WRITE(reg, temp);
3321 I915_READ(reg);
e1a44743
AJ		 3322 udelay(150);
3323
8db9d77b 3324 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3325 reg = FDI_TX_CTL(pipe);
3326 temp = I915_READ(reg);
627eb5a3 3327 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3328 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3329 temp &= ~FDI_LINK_TRAIN_NONE;
3330 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 3331 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3332
5eddb70b
CW		 3333 reg = FDI_RX_CTL(pipe);
3334 temp = I915_READ(reg);
8db9d77b
ZW		 3335 temp &= ~FDI_LINK_TRAIN_NONE;
3336 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 3337 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3338
3339 POSTING_READ(reg);
8db9d77b
ZW		 3340 udelay(150);
3341
5b2adf89 3342 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 3343 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3344 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3345 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 3346
5eddb70b 3347 reg = FDI_RX_IIR(pipe);
e1a44743 3348 for (tries = 0; tries < 5; tries++) {
5eddb70b 3349 temp = I915_READ(reg);
8db9d77b
ZW		 3350 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3351
3352 if ((temp & FDI_RX_BIT_LOCK)) {
3353 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 3354 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 3355 break;
3356 }
8db9d77b 3357 }
e1a44743 3358 if (tries == 5)
5eddb70b 3359 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3360
3361 /* Train 2 */
5eddb70b
CW		 3362 reg = FDI_TX_CTL(pipe);
3363 temp = I915_READ(reg);
8db9d77b
ZW		 3364 temp &= ~FDI_LINK_TRAIN_NONE;
3365 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3366 I915_WRITE(reg, temp);
8db9d77b 3367
5eddb70b
CW		 3368 reg = FDI_RX_CTL(pipe);
3369 temp = I915_READ(reg);
8db9d77b
ZW		 3370 temp &= ~FDI_LINK_TRAIN_NONE;
3371 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3372 I915_WRITE(reg, temp);
8db9d77b 3373
5eddb70b
CW		 3374 POSTING_READ(reg);
3375 udelay(150);
8db9d77b 3376
5eddb70b 3377 reg = FDI_RX_IIR(pipe);
e1a44743 3378 for (tries = 0; tries < 5; tries++) {
5eddb70b 3379 temp = I915_READ(reg);
8db9d77b
ZW		 3380 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3381
3382 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 3383 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 3384 DRM_DEBUG_KMS("FDI train 2 done.\n");
3385 break;
3386 }
8db9d77b 3387 }
e1a44743 3388 if (tries == 5)
5eddb70b 3389 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3390
3391 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 3392
8db9d77b
ZW		 3393}
3394
0206e353 3395static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 3396 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3397 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3398 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3399 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3400};
3401
3402/* The FDI link training functions for SNB/Cougarpoint. */
3403static void gen6_fdi_link_train(struct drm_crtc *crtc)
3404{
3405 struct drm_device *dev = crtc->dev;
3406 struct drm_i915_private *dev_priv = dev->dev_private;
3407 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3408 int pipe = intel_crtc->pipe;
f0f59a00
VS		 3409 i915_reg_t reg;
3410 u32 temp, i, retry;
8db9d77b 3411
e1a44743
AJ		 3412 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3413 for train result */
5eddb70b
CW		 3414 reg = FDI_RX_IMR(pipe);
3415 temp = I915_READ(reg);
e1a44743
AJ		 3416 temp &= ~FDI_RX_SYMBOL_LOCK;
3417 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3418 I915_WRITE(reg, temp);
3419
3420 POSTING_READ(reg);
e1a44743
AJ		 3421 udelay(150);
3422
8db9d77b 3423 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3424 reg = FDI_TX_CTL(pipe);
3425 temp = I915_READ(reg);
627eb5a3 3426 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3427 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3428 temp &= ~FDI_LINK_TRAIN_NONE;
3429 temp |= FDI_LINK_TRAIN_PATTERN_1;
3430 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3431 /* SNB-B */
3432 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 3433 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3434
d74cf324
DV		 3435 I915_WRITE(FDI_RX_MISC(pipe),
3436 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3437
5eddb70b
CW		 3438 reg = FDI_RX_CTL(pipe);
3439 temp = I915_READ(reg);
8db9d77b
ZW		 3440 if (HAS_PCH_CPT(dev)) {
3441 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3442 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3443 } else {
3444 temp &= ~FDI_LINK_TRAIN_NONE;
3445 temp |= FDI_LINK_TRAIN_PATTERN_1;
3446 }
5eddb70b
CW		 3447 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3448
3449 POSTING_READ(reg);
8db9d77b
ZW		 3450 udelay(150);
3451
0206e353 3452 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3453 reg = FDI_TX_CTL(pipe);
3454 temp = I915_READ(reg);
8db9d77b
ZW		 3455 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3456 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3457 I915_WRITE(reg, temp);
3458
3459 POSTING_READ(reg);
8db9d77b
ZW		 3460 udelay(500);
3461
fa37d39e
SP		 3462 for (retry = 0; retry < 5; retry++) {
3463 reg = FDI_RX_IIR(pipe);
3464 temp = I915_READ(reg);
3465 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3466 if (temp & FDI_RX_BIT_LOCK) {
3467 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3468 DRM_DEBUG_KMS("FDI train 1 done.\n");
3469 break;
3470 }
3471 udelay(50);
8db9d77b 3472 }
fa37d39e
SP		 3473 if (retry < 5)
3474 break;
8db9d77b
ZW		 3475 }
3476 if (i == 4)
5eddb70b 3477 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3478
3479 /* Train 2 */
5eddb70b
CW		 3480 reg = FDI_TX_CTL(pipe);
3481 temp = I915_READ(reg);
8db9d77b
ZW		 3482 temp &= ~FDI_LINK_TRAIN_NONE;
3483 temp |= FDI_LINK_TRAIN_PATTERN_2;
3484 if (IS_GEN6(dev)) {
3485 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3486 /* SNB-B */
3487 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3488 }
5eddb70b 3489 I915_WRITE(reg, temp);
8db9d77b 3490
5eddb70b
CW		 3491 reg = FDI_RX_CTL(pipe);
3492 temp = I915_READ(reg);
8db9d77b
ZW		 3493 if (HAS_PCH_CPT(dev)) {
3494 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3495 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3496 } else {
3497 temp &= ~FDI_LINK_TRAIN_NONE;
3498 temp |= FDI_LINK_TRAIN_PATTERN_2;
3499 }
5eddb70b
CW		 3500 I915_WRITE(reg, temp);
3501
3502 POSTING_READ(reg);
8db9d77b
ZW		 3503 udelay(150);
3504
0206e353 3505 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3506 reg = FDI_TX_CTL(pipe);
3507 temp = I915_READ(reg);
8db9d77b
ZW		 3508 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3509 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3510 I915_WRITE(reg, temp);
3511
3512 POSTING_READ(reg);
8db9d77b
ZW		 3513 udelay(500);
3514
fa37d39e
SP		 3515 for (retry = 0; retry < 5; retry++) {
3516 reg = FDI_RX_IIR(pipe);
3517 temp = I915_READ(reg);
3518 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3519 if (temp & FDI_RX_SYMBOL_LOCK) {
3520 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3521 DRM_DEBUG_KMS("FDI train 2 done.\n");
3522 break;
3523 }
3524 udelay(50);
8db9d77b 3525 }
fa37d39e
SP		 3526 if (retry < 5)
3527 break;
8db9d77b
ZW		 3528 }
3529 if (i == 4)
5eddb70b 3530 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3531
3532 DRM_DEBUG_KMS("FDI train done.\n");
3533}
3534
357555c0
JB		 3535/* Manual link training for Ivy Bridge A0 parts */
3536static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3537{
3538 struct drm_device *dev = crtc->dev;
3539 struct drm_i915_private *dev_priv = dev->dev_private;
3540 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3541 int pipe = intel_crtc->pipe;
f0f59a00
VS		 3542 i915_reg_t reg;
3543 u32 temp, i, j;
357555c0
JB		 3544
3545 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3546 for train result */
3547 reg = FDI_RX_IMR(pipe);
3548 temp = I915_READ(reg);
3549 temp &= ~FDI_RX_SYMBOL_LOCK;
3550 temp &= ~FDI_RX_BIT_LOCK;
3551 I915_WRITE(reg, temp);
3552
3553 POSTING_READ(reg);
3554 udelay(150);
3555
01a415fd
DV		 3556 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3557 I915_READ(FDI_RX_IIR(pipe)));
3558
139ccd3f
JB		 3559 /* Try each vswing and preemphasis setting twice before moving on */
3560 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3561 /* disable first in case we need to retry */
3562 reg = FDI_TX_CTL(pipe);
3563 temp = I915_READ(reg);
3564 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3565 temp &= ~FDI_TX_ENABLE;
3566 I915_WRITE(reg, temp);
357555c0 3567
139ccd3f
JB		 3568 reg = FDI_RX_CTL(pipe);
3569 temp = I915_READ(reg);
3570 temp &= ~FDI_LINK_TRAIN_AUTO;
3571 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3572 temp &= ~FDI_RX_ENABLE;
3573 I915_WRITE(reg, temp);
357555c0 3574
139ccd3f 3575 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 3576 reg = FDI_TX_CTL(pipe);
3577 temp = I915_READ(reg);
139ccd3f 3578 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3579 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
139ccd3f 3580 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 3581 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 3582 temp |= snb_b_fdi_train_param[j/2];
3583 temp |= FDI_COMPOSITE_SYNC;
3584 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 3585
139ccd3f
JB		 3586 I915_WRITE(FDI_RX_MISC(pipe),
3587 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 3588
139ccd3f 3589 reg = FDI_RX_CTL(pipe);
357555c0 3590 temp = I915_READ(reg);
139ccd3f
JB		 3591 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3592 temp |= FDI_COMPOSITE_SYNC;
3593 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 3594
139ccd3f
JB		 3595 POSTING_READ(reg);
3596 udelay(1); /* should be 0.5us */
357555c0 3597
139ccd3f
JB		 3598 for (i = 0; i < 4; i++) {
3599 reg = FDI_RX_IIR(pipe);
3600 temp = I915_READ(reg);
3601 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3602
139ccd3f
JB		 3603 if (temp & FDI_RX_BIT_LOCK ||
3604 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3605 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3606 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3607 i);
3608 break;
3609 }
3610 udelay(1); /* should be 0.5us */
3611 }
3612 if (i == 4) {
3613 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3614 continue;
3615 }
357555c0 3616
139ccd3f 3617 /* Train 2 */
357555c0
JB		 3618 reg = FDI_TX_CTL(pipe);
3619 temp = I915_READ(reg);
139ccd3f
JB		 3620 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3621 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3622 I915_WRITE(reg, temp);
3623
3624 reg = FDI_RX_CTL(pipe);
3625 temp = I915_READ(reg);
3626 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3627 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 3628 I915_WRITE(reg, temp);
3629
3630 POSTING_READ(reg);
139ccd3f 3631 udelay(2); /* should be 1.5us */
357555c0 3632
139ccd3f
JB		 3633 for (i = 0; i < 4; i++) {
3634 reg = FDI_RX_IIR(pipe);
3635 temp = I915_READ(reg);
3636 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3637
139ccd3f
JB		 3638 if (temp & FDI_RX_SYMBOL_LOCK ||
3639 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3640 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3641 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3642 i);
3643 goto train_done;
3644 }
3645 udelay(2); /* should be 1.5us */
357555c0 3646 }
139ccd3f
JB		 3647 if (i == 4)
3648 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 3649 }
357555c0 3650
139ccd3f 3651train_done:
357555c0
JB		 3652 DRM_DEBUG_KMS("FDI train done.\n");
3653}
3654
88cefb6c 3655static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 3656{
88cefb6c 3657 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 3658 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 3659 int pipe = intel_crtc->pipe;
f0f59a00
VS		 3660 i915_reg_t reg;
3661 u32 temp;
c64e311e 3662
c98e9dcf 3663 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 3664 reg = FDI_RX_CTL(pipe);
3665 temp = I915_READ(reg);
627eb5a3 3666 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
6e3c9717 3667 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
dfd07d72 3668 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 3669 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3670
3671 POSTING_READ(reg);
c98e9dcf
JB		 3672 udelay(200);
3673
3674 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 3675 temp = I915_READ(reg);
3676 I915_WRITE(reg, temp | FDI_PCDCLK);
3677
3678 POSTING_READ(reg);
c98e9dcf
JB		 3679 udelay(200);
3680
20749730
PZ		 3681 /* Enable CPU FDI TX PLL, always on for Ironlake */
3682 reg = FDI_TX_CTL(pipe);
3683 temp = I915_READ(reg);
3684 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3685 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 3686
20749730
PZ		 3687 POSTING_READ(reg);
3688 udelay(100);
6be4a607 3689 }
0e23b99d
JB		 3690}
3691
88cefb6c
DV		 3692static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3693{
3694 struct drm_device *dev = intel_crtc->base.dev;
3695 struct drm_i915_private *dev_priv = dev->dev_private;
3696 int pipe = intel_crtc->pipe;
f0f59a00
VS		 3697 i915_reg_t reg;
3698 u32 temp;
88cefb6c
DV		 3699
3700 /* Switch from PCDclk to Rawclk */
3701 reg = FDI_RX_CTL(pipe);
3702 temp = I915_READ(reg);
3703 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3704
3705 /* Disable CPU FDI TX PLL */
3706 reg = FDI_TX_CTL(pipe);
3707 temp = I915_READ(reg);
3708 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3709
3710 POSTING_READ(reg);
3711 udelay(100);
3712
3713 reg = FDI_RX_CTL(pipe);
3714 temp = I915_READ(reg);
3715 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3716
3717 /* Wait for the clocks to turn off. */
3718 POSTING_READ(reg);
3719 udelay(100);
3720}
3721
0fc932b8
JB		 3722static void ironlake_fdi_disable(struct drm_crtc *crtc)
3723{
3724 struct drm_device *dev = crtc->dev;
3725 struct drm_i915_private *dev_priv = dev->dev_private;
3726 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3727 int pipe = intel_crtc->pipe;
f0f59a00
VS		 3728 i915_reg_t reg;
3729 u32 temp;
0fc932b8
JB		 3730
3731 /* disable CPU FDI tx and PCH FDI rx */
3732 reg = FDI_TX_CTL(pipe);
3733 temp = I915_READ(reg);
3734 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3735 POSTING_READ(reg);
3736
3737 reg = FDI_RX_CTL(pipe);
3738 temp = I915_READ(reg);
3739 temp &= ~(0x7 << 16);
dfd07d72 3740 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3741 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3742
3743 POSTING_READ(reg);
3744 udelay(100);
3745
3746 /* Ironlake workaround, disable clock pointer after downing FDI */
eba905b2 3747 if (HAS_PCH_IBX(dev))
6f06ce18 3748 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 3749
3750 /* still set train pattern 1 */
3751 reg = FDI_TX_CTL(pipe);
3752 temp = I915_READ(reg);
3753 temp &= ~FDI_LINK_TRAIN_NONE;
3754 temp |= FDI_LINK_TRAIN_PATTERN_1;
3755 I915_WRITE(reg, temp);
3756
3757 reg = FDI_RX_CTL(pipe);
3758 temp = I915_READ(reg);
3759 if (HAS_PCH_CPT(dev)) {
3760 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3761 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3762 } else {
3763 temp &= ~FDI_LINK_TRAIN_NONE;
3764 temp |= FDI_LINK_TRAIN_PATTERN_1;
3765 }
3766 /* BPC in FDI rx is consistent with that in PIPECONF */
3767 temp &= ~(0x07 << 16);
dfd07d72 3768 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3769 I915_WRITE(reg, temp);
3770
3771 POSTING_READ(reg);
3772 udelay(100);
3773}
3774
5dce5b93
CW		 3775bool intel_has_pending_fb_unpin(struct drm_device *dev)
3776{
3777 struct intel_crtc *crtc;
3778
3779 /* Note that we don't need to be called with mode_config.lock here
3780 * as our list of CRTC objects is static for the lifetime of the
3781 * device and so cannot disappear as we iterate. Similarly, we can
3782 * happily treat the predicates as racy, atomic checks as userspace
3783 * cannot claim and pin a new fb without at least acquring the
3784 * struct_mutex and so serialising with us.
3785 */
d3fcc808 3786 for_each_intel_crtc(dev, crtc) {
5dce5b93
CW		 3787 if (atomic_read(&crtc->unpin_work_count) == 0)
3788 continue;
3789
3790 if (crtc->unpin_work)
3791 intel_wait_for_vblank(dev, crtc->pipe);
3792
3793 return true;
3794 }
3795
3796 return false;
3797}
3798
d6bbafa1
CW		 3799static void page_flip_completed(struct intel_crtc *intel_crtc)
3800{
3801 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3802 struct intel_unpin_work *work = intel_crtc->unpin_work;
3803
3804 /* ensure that the unpin work is consistent wrt ->pending. */
3805 smp_rmb();
3806 intel_crtc->unpin_work = NULL;
3807
3808 if (work->event)
3809 drm_send_vblank_event(intel_crtc->base.dev,
3810 intel_crtc->pipe,
3811 work->event);
3812
3813 drm_crtc_vblank_put(&intel_crtc->base);
3814
3815 wake_up_all(&dev_priv->pending_flip_queue);
3816 queue_work(dev_priv->wq, &work->work);
3817
3818 trace_i915_flip_complete(intel_crtc->plane,
3819 work->pending_flip_obj);
3820}
3821
5008e874 3822static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
e6c3a2a6 3823{
0f91128d 3824 struct drm_device *dev = crtc->dev;
5bb61643 3825 struct drm_i915_private *dev_priv = dev->dev_private;
5008e874 3826 long ret;
e6c3a2a6 3827
2c10d571 3828 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
5008e874
ML		 3829
3830 ret = wait_event_interruptible_timeout(
3831 dev_priv->pending_flip_queue,
3832 !intel_crtc_has_pending_flip(crtc),
3833 60*HZ);
3834
3835 if (ret < 0)
3836 return ret;
3837
3838 if (ret == 0) {
9c787942 3839 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2c10d571 3840
5e2d7afc 3841 spin_lock_irq(&dev->event_lock);
9c787942
CW		 3842 if (intel_crtc->unpin_work) {
3843 WARN_ONCE(1, "Removing stuck page flip\n");
3844 page_flip_completed(intel_crtc);
3845 }
5e2d7afc 3846 spin_unlock_irq(&dev->event_lock);
9c787942 3847 }
5bb61643 3848
5008e874 3849 return 0;
e6c3a2a6
CW		 3850}
3851
060f02d8
VS		 3852static void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
3853{
3854 u32 temp;
3855
3856 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3857
3858 mutex_lock(&dev_priv->sb_lock);
3859
3860 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3861 temp |= SBI_SSCCTL_DISABLE;
3862 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3863
3864 mutex_unlock(&dev_priv->sb_lock);
3865}
3866
e615efe4
ED		 3867/* Program iCLKIP clock to the desired frequency */
3868static void lpt_program_iclkip(struct drm_crtc *crtc)
3869{
64b46a06 3870 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6e3c9717 3871 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
e615efe4
ED		 3872 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3873 u32 temp;
3874
060f02d8 3875 lpt_disable_iclkip(dev_priv);
e615efe4 3876
64b46a06
VS		 3877 /* The iCLK virtual clock root frequency is in MHz,
3878 * but the adjusted_mode->crtc_clock in in KHz. To get the
3879 * divisors, it is necessary to divide one by another, so we
3880 * convert the virtual clock precision to KHz here for higher
3881 * precision.
3882 */
3883 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
e615efe4
ED		 3884 u32 iclk_virtual_root_freq = 172800 * 1000;
3885 u32 iclk_pi_range = 64;
64b46a06 3886 u32 desired_divisor;
e615efe4 3887
64b46a06
VS		 3888 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
3889 clock << auxdiv);
3890 divsel = (desired_divisor / iclk_pi_range) - 2;
3891 phaseinc = desired_divisor % iclk_pi_range;
e615efe4 3892
64b46a06
VS		 3893 /*
3894 * Near 20MHz is a corner case which is
3895 * out of range for the 7-bit divisor
3896 */
3897 if (divsel <= 0x7f)
3898 break;
e615efe4
ED		 3899 }
3900
3901 /* This should not happen with any sane values */
3902 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3903 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3904 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3905 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3906
3907 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 3908 clock,
e615efe4
ED		 3909 auxdiv,
3910 divsel,
3911 phasedir,
3912 phaseinc);
3913
060f02d8
VS		 3914 mutex_lock(&dev_priv->sb_lock);
3915
e615efe4 3916 /* Program SSCDIVINTPHASE6 */
988d6ee8 3917 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3918 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3919 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3920 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3921 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3922 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3923 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 3924 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 3925
3926 /* Program SSCAUXDIV */
988d6ee8 3927 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 3928 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3929 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 3930 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 3931
3932 /* Enable modulator and associated divider */
988d6ee8 3933 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 3934 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 3935 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4 3936
060f02d8
VS		 3937 mutex_unlock(&dev_priv->sb_lock);
3938
e615efe4
ED		 3939 /* Wait for initialization time */
3940 udelay(24);
3941
3942 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3943}
3944
8802e5b6
VS		 3945int lpt_get_iclkip(struct drm_i915_private *dev_priv)
3946{
3947 u32 divsel, phaseinc, auxdiv;
3948 u32 iclk_virtual_root_freq = 172800 * 1000;
3949 u32 iclk_pi_range = 64;
3950 u32 desired_divisor;
3951 u32 temp;
3952
3953 if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
3954 return 0;
3955
3956 mutex_lock(&dev_priv->sb_lock);
3957
3958 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3959 if (temp & SBI_SSCCTL_DISABLE) {
3960 mutex_unlock(&dev_priv->sb_lock);
3961 return 0;
3962 }
3963
3964 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3965 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
3966 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
3967 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
3968 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
3969
3970 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3971 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
3972 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
3973
3974 mutex_unlock(&dev_priv->sb_lock);
3975
3976 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
3977
3978 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
3979 desired_divisor << auxdiv);
3980}
3981
275f01b2
DV		 3982static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3983 enum pipe pch_transcoder)
3984{
3985 struct drm_device *dev = crtc->base.dev;
3986 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3987 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
275f01b2
DV		 3988
3989 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3990 I915_READ(HTOTAL(cpu_transcoder)));
3991 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3992 I915_READ(HBLANK(cpu_transcoder)));
3993 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3994 I915_READ(HSYNC(cpu_transcoder)));
3995
3996 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3997 I915_READ(VTOTAL(cpu_transcoder)));
3998 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3999 I915_READ(VBLANK(cpu_transcoder)));
4000 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4001 I915_READ(VSYNC(cpu_transcoder)));
4002 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4003 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4004}
4005
003632d9 4006static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
1fbc0d78
DV		 4007{
4008 struct drm_i915_private *dev_priv = dev->dev_private;
4009 uint32_t temp;
4010
4011 temp = I915_READ(SOUTH_CHICKEN1);
003632d9 4012 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
1fbc0d78
DV		 4013 return;
4014
4015 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4016 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4017
003632d9
ACO		 4018 temp &= ~FDI_BC_BIFURCATION_SELECT;
4019 if (enable)
4020 temp |= FDI_BC_BIFURCATION_SELECT;
4021
4022 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
1fbc0d78
DV		 4023 I915_WRITE(SOUTH_CHICKEN1, temp);
4024 POSTING_READ(SOUTH_CHICKEN1);
4025}
4026
4027static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4028{
4029 struct drm_device *dev = intel_crtc->base.dev;
1fbc0d78
DV		 4030
4031 switch (intel_crtc->pipe) {
4032 case PIPE_A:
4033 break;
4034 case PIPE_B:
6e3c9717 4035 if (intel_crtc->config->fdi_lanes > 2)
003632d9 4036 cpt_set_fdi_bc_bifurcation(dev, false);
1fbc0d78 4037 else
003632d9 4038 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4039
4040 break;
4041 case PIPE_C:
003632d9 4042 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4043
4044 break;
4045 default:
4046 BUG();
4047 }
4048}
4049
c48b5305
VS		 4050/* Return which DP Port should be selected for Transcoder DP control */
4051static enum port
4052intel_trans_dp_port_sel(struct drm_crtc *crtc)
4053{
4054 struct drm_device *dev = crtc->dev;
4055 struct intel_encoder *encoder;
4056
4057 for_each_encoder_on_crtc(dev, crtc, encoder) {
4058 if (encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4059 encoder->type == INTEL_OUTPUT_EDP)
4060 return enc_to_dig_port(&encoder->base)->port;
4061 }
4062
4063 return -1;
4064}
4065
f67a559d
JB		 4066/*
4067 * Enable PCH resources required for PCH ports:
4068 * - PCH PLLs
4069 * - FDI training & RX/TX
4070 * - update transcoder timings
4071 * - DP transcoding bits
4072 * - transcoder
4073 */
4074static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 4075{
4076 struct drm_device *dev = crtc->dev;
4077 struct drm_i915_private *dev_priv = dev->dev_private;
4078 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4079 int pipe = intel_crtc->pipe;
f0f59a00 4080 u32 temp;
2c07245f 4081
ab9412ba 4082 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 4083
1fbc0d78
DV		 4084 if (IS_IVYBRIDGE(dev))
4085 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4086
cd986abb
DV		 4087 /* Write the TU size bits before fdi link training, so that error
4088 * detection works. */
4089 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4090 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4091
3860b2ec
VS		 4092 /*
4093 * Sometimes spurious CPU pipe underruns happen during FDI
4094 * training, at least with VGA+HDMI cloning. Suppress them.
4095 */
4096 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4097
c98e9dcf 4098 /* For PCH output, training FDI link */
674cf967 4099 dev_priv->display.fdi_link_train(crtc);
2c07245f 4100
3ad8a208
DV		 4101 /* We need to program the right clock selection before writing the pixel
4102 * mutliplier into the DPLL. */
303b81e0 4103 if (HAS_PCH_CPT(dev)) {
ee7b9f93 4104 u32 sel;
4b645f14 4105
c98e9dcf 4106 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 4107 temp |= TRANS_DPLL_ENABLE(pipe);
4108 sel = TRANS_DPLLB_SEL(pipe);
8106ddbd
ACO		 4109 if (intel_crtc->config->shared_dpll ==
4110 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
ee7b9f93
JB		 4111 temp |= sel;
4112 else
4113 temp &= ~sel;
c98e9dcf 4114 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 4115 }
5eddb70b 4116
3ad8a208
DV		 4117 /* XXX: pch pll's can be enabled any time before we enable the PCH
4118 * transcoder, and we actually should do this to not upset any PCH
4119 * transcoder that already use the clock when we share it.
4120 *
4121 * Note that enable_shared_dpll tries to do the right thing, but
4122 * get_shared_dpll unconditionally resets the pll - we need that to have
4123 * the right LVDS enable sequence. */
85b3894f 4124 intel_enable_shared_dpll(intel_crtc);
3ad8a208 4125
d9b6cb56
JB		 4126 /* set transcoder timing, panel must allow it */
4127 assert_panel_unlocked(dev_priv, pipe);
275f01b2 4128 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 4129
303b81e0 4130 intel_fdi_normal_train(crtc);
5e84e1a4 4131
3860b2ec
VS		 4132 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4133
c98e9dcf 4134 /* For PCH DP, enable TRANS_DP_CTL */
6e3c9717 4135 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
9c4edaee
VS		 4136 const struct drm_display_mode *adjusted_mode =
4137 &intel_crtc->config->base.adjusted_mode;
dfd07d72 4138 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
f0f59a00 4139 i915_reg_t reg = TRANS_DP_CTL(pipe);
5eddb70b
CW		 4140 temp = I915_READ(reg);
4141 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 4142 TRANS_DP_SYNC_MASK |
4143 TRANS_DP_BPC_MASK);
e3ef4479 4144 temp |= TRANS_DP_OUTPUT_ENABLE;
9325c9f0 4145 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf 4146
9c4edaee 4147 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 4148 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
9c4edaee 4149 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 4150 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 4151
4152 switch (intel_trans_dp_port_sel(crtc)) {
c48b5305 4153 case PORT_B:
5eddb70b 4154 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf 4155 break;
c48b5305 4156 case PORT_C:
5eddb70b 4157 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf 4158 break;
c48b5305 4159 case PORT_D:
5eddb70b 4160 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 4161 break;
4162 default:
e95d41e1 4163 BUG();
32f9d658 4164 }
2c07245f 4165
5eddb70b 4166 I915_WRITE(reg, temp);
6be4a607 4167 }
b52eb4dc 4168
b8a4f404 4169 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 4170}
4171
1507e5bd
PZ		 4172static void lpt_pch_enable(struct drm_crtc *crtc)
4173{
4174 struct drm_device *dev = crtc->dev;
4175 struct drm_i915_private *dev_priv = dev->dev_private;
4176 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 4177 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1507e5bd 4178
ab9412ba 4179 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 4180
8c52b5e8 4181 lpt_program_iclkip(crtc);
1507e5bd 4182
0540e488 4183 /* Set transcoder timing. */
275f01b2 4184 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 4185
937bb610 4186 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 4187}
4188
a1520318 4189static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 4190{
4191 struct drm_i915_private *dev_priv = dev->dev_private;
f0f59a00 4192 i915_reg_t dslreg = PIPEDSL(pipe);
d4270e57
JB		 4193 u32 temp;
4194
4195 temp = I915_READ(dslreg);
4196 udelay(500);
4197 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 4198 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 4199 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 4200 }
4201}
4202
86adf9d7
ML		 4203static int
4204skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4205 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4206 int src_w, int src_h, int dst_w, int dst_h)
a1b2278e 4207{
86adf9d7
ML		 4208 struct intel_crtc_scaler_state *scaler_state =
4209 &crtc_state->scaler_state;
4210 struct intel_crtc *intel_crtc =
4211 to_intel_crtc(crtc_state->base.crtc);
a1b2278e 4212 int need_scaling;
6156a456
CK		 4213
4214 need_scaling = intel_rotation_90_or_270(rotation) ?
4215 (src_h != dst_w || src_w != dst_h):
4216 (src_w != dst_w || src_h != dst_h);
a1b2278e
CK		 4217
4218 /*
4219 * if plane is being disabled or scaler is no more required or force detach
4220 * - free scaler binded to this plane/crtc
4221 * - in order to do this, update crtc->scaler_usage
4222 *
4223 * Here scaler state in crtc_state is set free so that
4224 * scaler can be assigned to other user. Actual register
4225 * update to free the scaler is done in plane/panel-fit programming.
4226 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4227 */
86adf9d7 4228 if (force_detach || !need_scaling) {
a1b2278e 4229 if (*scaler_id >= 0) {
86adf9d7 4230 scaler_state->scaler_users &= ~(1 << scaler_user);
a1b2278e
CK		 4231 scaler_state->scalers[*scaler_id].in_use = 0;
4232
86adf9d7
ML		 4233 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4234 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4235 intel_crtc->pipe, scaler_user, *scaler_id,
a1b2278e
CK		 4236 scaler_state->scaler_users);
4237 *scaler_id = -1;
4238 }
4239 return 0;
4240 }
4241
4242 /* range checks */
4243 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4244 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4245
4246 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4247 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
86adf9d7 4248 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
a1b2278e 4249 "size is out of scaler range\n",
86adf9d7 4250 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
a1b2278e
CK		 4251 return -EINVAL;
4252 }
4253
86adf9d7
ML		 4254 /* mark this plane as a scaler user in crtc_state */
4255 scaler_state->scaler_users |= (1 << scaler_user);
4256 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4257 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4258 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4259 scaler_state->scaler_users);
4260
4261 return 0;
4262}
4263
4264/**
4265 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4266 *
4267 * @state: crtc's scaler state
86adf9d7
ML		 4268 *
4269 * Return
4270 * 0 - scaler_usage updated successfully
4271 * error - requested scaling cannot be supported or other error condition
4272 */
e435d6e5 4273int skl_update_scaler_crtc(struct intel_crtc_state *state)
86adf9d7
ML		 4274{
4275 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
7c5f93b0 4276 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
86adf9d7
ML		 4277
4278 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4279 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4280
e435d6e5 4281 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
fa5a7970 4282 &state->scaler_state.scaler_id, BIT(DRM_ROTATE_0),
86adf9d7 4283 state->pipe_src_w, state->pipe_src_h,
aad941d5 4284 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
86adf9d7
ML		 4285}
4286
4287/**
4288 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4289 *
4290 * @state: crtc's scaler state
86adf9d7
ML		 4291 * @plane_state: atomic plane state to update
4292 *
4293 * Return
4294 * 0 - scaler_usage updated successfully
4295 * error - requested scaling cannot be supported or other error condition
4296 */
da20eabd
ML		 4297static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4298 struct intel_plane_state *plane_state)
86adf9d7
ML		 4299{
4300
4301 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
da20eabd
ML		 4302 struct intel_plane *intel_plane =
4303 to_intel_plane(plane_state->base.plane);
86adf9d7
ML		 4304 struct drm_framebuffer *fb = plane_state->base.fb;
4305 int ret;
4306
4307 bool force_detach = !fb || !plane_state->visible;
4308
4309 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4310 intel_plane->base.base.id, intel_crtc->pipe,
4311 drm_plane_index(&intel_plane->base));
4312
4313 ret = skl_update_scaler(crtc_state, force_detach,
4314 drm_plane_index(&intel_plane->base),
4315 &plane_state->scaler_id,
4316 plane_state->base.rotation,
4317 drm_rect_width(&plane_state->src) >> 16,
4318 drm_rect_height(&plane_state->src) >> 16,
4319 drm_rect_width(&plane_state->dst),
4320 drm_rect_height(&plane_state->dst));
4321
4322 if (ret || plane_state->scaler_id < 0)
4323 return ret;
4324
a1b2278e 4325 /* check colorkey */
818ed961 4326 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
86adf9d7 4327 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
818ed961 4328 intel_plane->base.base.id);
a1b2278e
CK		 4329 return -EINVAL;
4330 }
4331
4332 /* Check src format */
86adf9d7
ML		 4333 switch (fb->pixel_format) {
4334 case DRM_FORMAT_RGB565:
4335 case DRM_FORMAT_XBGR8888:
4336 case DRM_FORMAT_XRGB8888:
4337 case DRM_FORMAT_ABGR8888:
4338 case DRM_FORMAT_ARGB8888:
4339 case DRM_FORMAT_XRGB2101010:
4340 case DRM_FORMAT_XBGR2101010:
4341 case DRM_FORMAT_YUYV:
4342 case DRM_FORMAT_YVYU:
4343 case DRM_FORMAT_UYVY:
4344 case DRM_FORMAT_VYUY:
4345 break;
4346 default:
4347 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4348 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4349 return -EINVAL;
a1b2278e
CK		 4350 }
4351
a1b2278e
CK		 4352 return 0;
4353}
4354
e435d6e5
ML		 4355static void skylake_scaler_disable(struct intel_crtc *crtc)
4356{
4357 int i;
4358
4359 for (i = 0; i < crtc->num_scalers; i++)
4360 skl_detach_scaler(crtc, i);
4361}
4362
4363static void skylake_pfit_enable(struct intel_crtc *crtc)
bd2e244f
JB		 4364{
4365 struct drm_device *dev = crtc->base.dev;
4366 struct drm_i915_private *dev_priv = dev->dev_private;
4367 int pipe = crtc->pipe;
a1b2278e
CK		 4368 struct intel_crtc_scaler_state *scaler_state =
4369 &crtc->config->scaler_state;
4370
4371 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4372
6e3c9717 4373 if (crtc->config->pch_pfit.enabled) {
a1b2278e
CK		 4374 int id;
4375
4376 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4377 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4378 return;
4379 }
4380
4381 id = scaler_state->scaler_id;
4382 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4383 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4384 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4385 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4386
4387 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
bd2e244f
JB		 4388 }
4389}
4390
b074cec8
JB		 4391static void ironlake_pfit_enable(struct intel_crtc *crtc)
4392{
4393 struct drm_device *dev = crtc->base.dev;
4394 struct drm_i915_private *dev_priv = dev->dev_private;
4395 int pipe = crtc->pipe;
4396
6e3c9717 4397 if (crtc->config->pch_pfit.enabled) {
b074cec8
JB		 4398 /* Force use of hard-coded filter coefficients
4399 * as some pre-programmed values are broken,
4400 * e.g. x201.
4401 */
4402 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4403 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4404 PF_PIPE_SEL_IVB(pipe));
4405 else
4406 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
6e3c9717
ACO		 4407 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4408 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
d4270e57
JB		 4409 }
4410}
4411
20bc8673 4412void hsw_enable_ips(struct intel_crtc *crtc)
d77e4531 4413{
cea165c3
VS		 4414 struct drm_device *dev = crtc->base.dev;
4415 struct drm_i915_private *dev_priv = dev->dev_private;
d77e4531 4416
6e3c9717 4417 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4418 return;
4419
307e4498
ML		 4420 /*
4421 * We can only enable IPS after we enable a plane and wait for a vblank
4422 * This function is called from post_plane_update, which is run after
4423 * a vblank wait.
4424 */
cea165c3 4425
d77e4531 4426 assert_plane_enabled(dev_priv, crtc->plane);
cea165c3 4427 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4428 mutex_lock(&dev_priv->rps.hw_lock);
4429 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4430 mutex_unlock(&dev_priv->rps.hw_lock);
4431 /* Quoting Art Runyan: "its not safe to expect any particular
4432 * value in IPS_CTL bit 31 after enabling IPS through the
e59150dc
JB		 4433 * mailbox." Moreover, the mailbox may return a bogus state,
4434 * so we need to just enable it and continue on.
2a114cc1
BW		 4435 */
4436 } else {
4437 I915_WRITE(IPS_CTL, IPS_ENABLE);
4438 /* The bit only becomes 1 in the next vblank, so this wait here
4439 * is essentially intel_wait_for_vblank. If we don't have this
4440 * and don't wait for vblanks until the end of crtc_enable, then
4441 * the HW state readout code will complain that the expected
4442 * IPS_CTL value is not the one we read. */
4443 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4444 DRM_ERROR("Timed out waiting for IPS enable\n");
4445 }
d77e4531
PZ		 4446}
4447
20bc8673 4448void hsw_disable_ips(struct intel_crtc *crtc)
d77e4531
PZ		 4449{
4450 struct drm_device *dev = crtc->base.dev;
4451 struct drm_i915_private *dev_priv = dev->dev_private;
4452
6e3c9717 4453 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4454 return;
4455
4456 assert_plane_enabled(dev_priv, crtc->plane);
23d0b130 4457 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4458 mutex_lock(&dev_priv->rps.hw_lock);
4459 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4460 mutex_unlock(&dev_priv->rps.hw_lock);
23d0b130
BW		 4461 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4462 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4463 DRM_ERROR("Timed out waiting for IPS disable\n");
e59150dc 4464 } else {
2a114cc1 4465 I915_WRITE(IPS_CTL, 0);
e59150dc
JB		 4466 POSTING_READ(IPS_CTL);
4467 }
d77e4531
PZ		 4468
4469 /* We need to wait for a vblank before we can disable the plane. */
4470 intel_wait_for_vblank(dev, crtc->pipe);
4471}
4472
7cac945f 4473static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
d3eedb1a 4474{
7cac945f 4475 if (intel_crtc->overlay) {
d3eedb1a
VS		 4476 struct drm_device *dev = intel_crtc->base.dev;
4477 struct drm_i915_private *dev_priv = dev->dev_private;
4478
4479 mutex_lock(&dev->struct_mutex);
4480 dev_priv->mm.interruptible = false;
4481 (void) intel_overlay_switch_off(intel_crtc->overlay);
4482 dev_priv->mm.interruptible = true;
4483 mutex_unlock(&dev->struct_mutex);
4484 }
4485
4486 /* Let userspace switch the overlay on again. In most cases userspace
4487 * has to recompute where to put it anyway.
4488 */
4489}
4490
87d4300a
ML		 4491/**
4492 * intel_post_enable_primary - Perform operations after enabling primary plane
4493 * @crtc: the CRTC whose primary plane was just enabled
4494 *
4495 * Performs potentially sleeping operations that must be done after the primary
4496 * plane is enabled, such as updating FBC and IPS. Note that this may be
4497 * called due to an explicit primary plane update, or due to an implicit
4498 * re-enable that is caused when a sprite plane is updated to no longer
4499 * completely hide the primary plane.
4500 */
4501static void
4502intel_post_enable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4503{
4504 struct drm_device *dev = crtc->dev;
87d4300a 4505 struct drm_i915_private *dev_priv = dev->dev_private;
a5c4d7bc
VS		 4506 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4507 int pipe = intel_crtc->pipe;
a5c4d7bc 4508
87d4300a
ML		 4509 /*
4510 * FIXME IPS should be fine as long as one plane is
4511 * enabled, but in practice it seems to have problems
4512 * when going from primary only to sprite only and vice
4513 * versa.
4514 */
a5c4d7bc
VS		 4515 hsw_enable_ips(intel_crtc);
4516
f99d7069 4517 /*
87d4300a
ML		 4518 * Gen2 reports pipe underruns whenever all planes are disabled.
4519 * So don't enable underrun reporting before at least some planes
4520 * are enabled.
4521 * FIXME: Need to fix the logic to work when we turn off all planes
4522 * but leave the pipe running.
f99d7069 4523 */
87d4300a
ML		 4524 if (IS_GEN2(dev))
4525 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4526
aca7b684
VS		 4527 /* Underruns don't always raise interrupts, so check manually. */
4528 intel_check_cpu_fifo_underruns(dev_priv);
4529 intel_check_pch_fifo_underruns(dev_priv);
a5c4d7bc
VS		 4530}
4531
2622a081 4532/* FIXME move all this to pre_plane_update() with proper state tracking */
87d4300a
ML		 4533static void
4534intel_pre_disable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4535{
4536 struct drm_device *dev = crtc->dev;
4537 struct drm_i915_private *dev_priv = dev->dev_private;
4538 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4539 int pipe = intel_crtc->pipe;
a5c4d7bc 4540
87d4300a
ML		 4541 /*
4542 * Gen2 reports pipe underruns whenever all planes are disabled.
4543 * So diasble underrun reporting before all the planes get disabled.
4544 * FIXME: Need to fix the logic to work when we turn off all planes
4545 * but leave the pipe running.
4546 */
4547 if (IS_GEN2(dev))
4548 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
a5c4d7bc 4549
2622a081
VS		 4550 /*
4551 * FIXME IPS should be fine as long as one plane is
4552 * enabled, but in practice it seems to have problems
4553 * when going from primary only to sprite only and vice
4554 * versa.
4555 */
4556 hsw_disable_ips(intel_crtc);
4557}
4558
4559/* FIXME get rid of this and use pre_plane_update */
4560static void
4561intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
4562{
4563 struct drm_device *dev = crtc->dev;
4564 struct drm_i915_private *dev_priv = dev->dev_private;
4565 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4566 int pipe = intel_crtc->pipe;
4567
4568 intel_pre_disable_primary(crtc);
4569
87d4300a
ML		 4570 /*
4571 * Vblank time updates from the shadow to live plane control register
4572 * are blocked if the memory self-refresh mode is active at that
4573 * moment. So to make sure the plane gets truly disabled, disable
4574 * first the self-refresh mode. The self-refresh enable bit in turn
4575 * will be checked/applied by the HW only at the next frame start
4576 * event which is after the vblank start event, so we need to have a
4577 * wait-for-vblank between disabling the plane and the pipe.
4578 */
262cd2e1 4579 if (HAS_GMCH_DISPLAY(dev)) {
87d4300a 4580 intel_set_memory_cxsr(dev_priv, false);
262cd2e1
VS		 4581 dev_priv->wm.vlv.cxsr = false;
4582 intel_wait_for_vblank(dev, pipe);
4583 }
87d4300a
ML		 4584}
4585
cd202f69 4586static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
ac21b225 4587{
cd202f69
ML		 4588 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4589 struct drm_atomic_state *old_state = old_crtc_state->base.state;
92826fcd
ML		 4590 struct intel_crtc_state *pipe_config =
4591 to_intel_crtc_state(crtc->base.state);
ac21b225 4592 struct drm_device *dev = crtc->base.dev;
cd202f69
ML		 4593 struct drm_plane *primary = crtc->base.primary;
4594 struct drm_plane_state *old_pri_state =
4595 drm_atomic_get_existing_plane_state(old_state, primary);
ac21b225 4596
cd202f69 4597 intel_frontbuffer_flip(dev, pipe_config->fb_bits);
ac21b225 4598
ab1d3a0e 4599 crtc->wm.cxsr_allowed = true;
852eb00d 4600
caed361d 4601 if (pipe_config->update_wm_post && pipe_config->base.active)
f015c551
VS		 4602 intel_update_watermarks(&crtc->base);
4603
cd202f69
ML		 4604 if (old_pri_state) {
4605 struct intel_plane_state *primary_state =
4606 to_intel_plane_state(primary->state);
4607 struct intel_plane_state *old_primary_state =
4608 to_intel_plane_state(old_pri_state);
4609
31ae71fc
ML		 4610 intel_fbc_post_update(crtc);
4611
cd202f69
ML		 4612 if (primary_state->visible &&
4613 (needs_modeset(&pipe_config->base) ||
4614 !old_primary_state->visible))
4615 intel_post_enable_primary(&crtc->base);
4616 }
ac21b225
ML		 4617}
4618
5c74cd73 4619static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
ac21b225 4620{
5c74cd73 4621 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
ac21b225 4622 struct drm_device *dev = crtc->base.dev;
eddfcbcd 4623 struct drm_i915_private *dev_priv = dev->dev_private;
ab1d3a0e
ML		 4624 struct intel_crtc_state *pipe_config =
4625 to_intel_crtc_state(crtc->base.state);
5c74cd73
ML		 4626 struct drm_atomic_state *old_state = old_crtc_state->base.state;
4627 struct drm_plane *primary = crtc->base.primary;
4628 struct drm_plane_state *old_pri_state =
4629 drm_atomic_get_existing_plane_state(old_state, primary);
4630 bool modeset = needs_modeset(&pipe_config->base);
ac21b225 4631
5c74cd73
ML		 4632 if (old_pri_state) {
4633 struct intel_plane_state *primary_state =
4634 to_intel_plane_state(primary->state);
4635 struct intel_plane_state *old_primary_state =
4636 to_intel_plane_state(old_pri_state);
4637
31ae71fc
ML		 4638 intel_fbc_pre_update(crtc);
4639
5c74cd73
ML		 4640 if (old_primary_state->visible &&
4641 (modeset || !primary_state->visible))
4642 intel_pre_disable_primary(&crtc->base);
4643 }
852eb00d 4644
ab1d3a0e 4645 if (pipe_config->disable_cxsr) {
852eb00d 4646 crtc->wm.cxsr_allowed = false;
2dfd178d 4647
2622a081
VS		 4648 /*
4649 * Vblank time updates from the shadow to live plane control register
4650 * are blocked if the memory self-refresh mode is active at that
4651 * moment. So to make sure the plane gets truly disabled, disable
4652 * first the self-refresh mode. The self-refresh enable bit in turn
4653 * will be checked/applied by the HW only at the next frame start
4654 * event which is after the vblank start event, so we need to have a
4655 * wait-for-vblank between disabling the plane and the pipe.
4656 */
4657 if (old_crtc_state->base.active) {
2dfd178d 4658 intel_set_memory_cxsr(dev_priv, false);
2622a081
VS		 4659 dev_priv->wm.vlv.cxsr = false;
4660 intel_wait_for_vblank(dev, crtc->pipe);
4661 }
852eb00d 4662 }
92826fcd 4663
ed4a6a7c
MR		 4664 /*
4665 * IVB workaround: must disable low power watermarks for at least
4666 * one frame before enabling scaling. LP watermarks can be re-enabled
4667 * when scaling is disabled.
4668 *
4669 * WaCxSRDisabledForSpriteScaling:ivb
4670 */
4671 if (pipe_config->disable_lp_wm) {
4672 ilk_disable_lp_wm(dev);
4673 intel_wait_for_vblank(dev, crtc->pipe);
4674 }
4675
4676 /*
4677 * If we're doing a modeset, we're done. No need to do any pre-vblank
4678 * watermark programming here.
4679 */
4680 if (needs_modeset(&pipe_config->base))
4681 return;
4682
4683 /*
4684 * For platforms that support atomic watermarks, program the
4685 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
4686 * will be the intermediate values that are safe for both pre- and
4687 * post- vblank; when vblank happens, the 'active' values will be set
4688 * to the final 'target' values and we'll do this again to get the
4689 * optimal watermarks. For gen9+ platforms, the values we program here
4690 * will be the final target values which will get automatically latched
4691 * at vblank time; no further programming will be necessary.
4692 *
4693 * If a platform hasn't been transitioned to atomic watermarks yet,
4694 * we'll continue to update watermarks the old way, if flags tell
4695 * us to.
4696 */
4697 if (dev_priv->display.initial_watermarks != NULL)
4698 dev_priv->display.initial_watermarks(pipe_config);
caed361d 4699 else if (pipe_config->update_wm_pre)
92826fcd 4700 intel_update_watermarks(&crtc->base);
ac21b225
ML		 4701}
4702
d032ffa0 4703static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
87d4300a
ML		 4704{
4705 struct drm_device *dev = crtc->dev;
4706 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
d032ffa0 4707 struct drm_plane *p;
87d4300a
ML		 4708 int pipe = intel_crtc->pipe;
4709
7cac945f 4710 intel_crtc_dpms_overlay_disable(intel_crtc);
27321ae8 4711
d032ffa0
ML		 4712 drm_for_each_plane_mask(p, dev, plane_mask)
4713 to_intel_plane(p)->disable_plane(p, crtc);
f98551ae 4714
f99d7069
DV		 4715 /*
4716 * FIXME: Once we grow proper nuclear flip support out of this we need
4717 * to compute the mask of flip planes precisely. For the time being
4718 * consider this a flip to a NULL plane.
4719 */
4720 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
a5c4d7bc
VS		 4721}
4722
f67a559d
JB		 4723static void ironlake_crtc_enable(struct drm_crtc *crtc)
4724{
4725 struct drm_device *dev = crtc->dev;
4726 struct drm_i915_private *dev_priv = dev->dev_private;
4727 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4728 struct intel_encoder *encoder;
f67a559d 4729 int pipe = intel_crtc->pipe;
b95c5321
ML		 4730 struct intel_crtc_state *pipe_config =
4731 to_intel_crtc_state(crtc->state);
f67a559d 4732
53d9f4e9 4733 if (WARN_ON(intel_crtc->active))
f67a559d
JB		 4734 return;
4735
81b088ca
VS		 4736 if (intel_crtc->config->has_pch_encoder)
4737 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4738
6e3c9717 4739 if (intel_crtc->config->has_pch_encoder)
b14b1055
DV		 4740 intel_prepare_shared_dpll(intel_crtc);
4741
6e3c9717 4742 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4743 intel_dp_set_m_n(intel_crtc, M1_N1);
29407aab
DV		 4744
4745 intel_set_pipe_timings(intel_crtc);
bc58be60 4746 intel_set_pipe_src_size(intel_crtc);
29407aab 4747
6e3c9717 4748 if (intel_crtc->config->has_pch_encoder) {
29407aab 4749 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4750 &intel_crtc->config->fdi_m_n, NULL);
29407aab
DV		 4751 }
4752
4753 ironlake_set_pipeconf(crtc);
4754
f67a559d 4755 intel_crtc->active = true;
8664281b 4756
a72e4c9f 4757 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
8664281b 4758
f6736a1a 4759 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 4760 if (encoder->pre_enable)
4761 encoder->pre_enable(encoder);
f67a559d 4762
6e3c9717 4763 if (intel_crtc->config->has_pch_encoder) {
fff367c7
DV		 4764 /* Note: FDI PLL enabling _must_ be done before we enable the
4765 * cpu pipes, hence this is separate from all the other fdi/pch
4766 * enabling. */
88cefb6c 4767 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 4768 } else {
4769 assert_fdi_tx_disabled(dev_priv, pipe);
4770 assert_fdi_rx_disabled(dev_priv, pipe);
4771 }
f67a559d 4772
b074cec8 4773 ironlake_pfit_enable(intel_crtc);
f67a559d 4774
9c54c0dd
JB		 4775 /*
4776 * On ILK+ LUT must be loaded before the pipe is running but with
4777 * clocks enabled
4778 */
b95c5321 4779 intel_color_load_luts(&pipe_config->base);
9c54c0dd 4780
1d5bf5d9
ID		 4781 if (dev_priv->display.initial_watermarks != NULL)
4782 dev_priv->display.initial_watermarks(intel_crtc->config);
e1fdc473 4783 intel_enable_pipe(intel_crtc);
f67a559d 4784
6e3c9717 4785 if (intel_crtc->config->has_pch_encoder)
f67a559d 4786 ironlake_pch_enable(crtc);
c98e9dcf 4787
f9b61ff6
DV		 4788 assert_vblank_disabled(crtc);
4789 drm_crtc_vblank_on(crtc);
4790
fa5c73b1
DV		 4791 for_each_encoder_on_crtc(dev, crtc, encoder)
4792 encoder->enable(encoder);
61b77ddd
DV		 4793
4794 if (HAS_PCH_CPT(dev))
a1520318 4795 cpt_verify_modeset(dev, intel_crtc->pipe);
37ca8d4c
VS		 4796
4797 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
4798 if (intel_crtc->config->has_pch_encoder)
4799 intel_wait_for_vblank(dev, pipe);
4800 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
6be4a607
JB		 4801}
4802
42db64ef
PZ		 4803/* IPS only exists on ULT machines and is tied to pipe A. */
4804static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4805{
f5adf94e 4806 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 4807}
4808
4f771f10
PZ		 4809static void haswell_crtc_enable(struct drm_crtc *crtc)
4810{
4811 struct drm_device *dev = crtc->dev;
4812 struct drm_i915_private *dev_priv = dev->dev_private;
4813 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4814 struct intel_encoder *encoder;
99d736a2 4815 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4d1de975 4816 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
99d736a2
ML		 4817 struct intel_crtc_state *pipe_config =
4818 to_intel_crtc_state(crtc->state);
4f771f10 4819
53d9f4e9 4820 if (WARN_ON(intel_crtc->active))
4f771f10
PZ		 4821 return;
4822
81b088ca
VS		 4823 if (intel_crtc->config->has_pch_encoder)
4824 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4825 false);
4826
8106ddbd 4827 if (intel_crtc->config->shared_dpll)
df8ad70c
DV		 4828 intel_enable_shared_dpll(intel_crtc);
4829
6e3c9717 4830 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4831 intel_dp_set_m_n(intel_crtc, M1_N1);
229fca97 4832
4d1de975
JN		 4833 if (!intel_crtc->config->has_dsi_encoder)
4834 intel_set_pipe_timings(intel_crtc);
4835
bc58be60 4836 intel_set_pipe_src_size(intel_crtc);
229fca97 4837
4d1de975
JN		 4838 if (cpu_transcoder != TRANSCODER_EDP &&
4839 !transcoder_is_dsi(cpu_transcoder)) {
4840 I915_WRITE(PIPE_MULT(cpu_transcoder),
6e3c9717 4841 intel_crtc->config->pixel_multiplier - 1);
ebb69c95
CT		 4842 }
4843
6e3c9717 4844 if (intel_crtc->config->has_pch_encoder) {
229fca97 4845 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4846 &intel_crtc->config->fdi_m_n, NULL);
229fca97
DV		 4847 }
4848
4d1de975
JN		 4849 if (!intel_crtc->config->has_dsi_encoder)
4850 haswell_set_pipeconf(crtc);
4851
391bf048 4852 haswell_set_pipemisc(crtc);
229fca97 4853
b95c5321 4854 intel_color_set_csc(&pipe_config->base);
229fca97 4855
4f771f10 4856 intel_crtc->active = true;
8664281b 4857
6b698516
DV		 4858 if (intel_crtc->config->has_pch_encoder)
4859 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4860 else
4861 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4862
7d4aefd0 4863 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10
PZ		 4864 if (encoder->pre_enable)
4865 encoder->pre_enable(encoder);
7d4aefd0 4866 }
4f771f10 4867
d2d65408 4868 if (intel_crtc->config->has_pch_encoder)
4fe9467d 4869 dev_priv->display.fdi_link_train(crtc);
4fe9467d 4870
a65347ba 4871 if (!intel_crtc->config->has_dsi_encoder)
7d4aefd0 4872 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 4873
1c132b44 4874 if (INTEL_INFO(dev)->gen >= 9)
e435d6e5 4875 skylake_pfit_enable(intel_crtc);
ff6d9f55 4876 else
1c132b44 4877 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 4878
4879 /*
4880 * On ILK+ LUT must be loaded before the pipe is running but with
4881 * clocks enabled
4882 */
b95c5321 4883 intel_color_load_luts(&pipe_config->base);
4f771f10 4884
1f544388 4885 intel_ddi_set_pipe_settings(crtc);
a65347ba 4886 if (!intel_crtc->config->has_dsi_encoder)
7d4aefd0 4887 intel_ddi_enable_transcoder_func(crtc);
4f771f10 4888
1d5bf5d9
ID		 4889 if (dev_priv->display.initial_watermarks != NULL)
4890 dev_priv->display.initial_watermarks(pipe_config);
4891 else
4892 intel_update_watermarks(crtc);
4d1de975
JN		 4893
4894 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
4895 if (!intel_crtc->config->has_dsi_encoder)
4896 intel_enable_pipe(intel_crtc);
42db64ef 4897
6e3c9717 4898 if (intel_crtc->config->has_pch_encoder)
1507e5bd 4899 lpt_pch_enable(crtc);
4f771f10 4900
a65347ba 4901 if (intel_crtc->config->dp_encoder_is_mst)
0e32b39c
DA		 4902 intel_ddi_set_vc_payload_alloc(crtc, true);
4903
f9b61ff6
DV		 4904 assert_vblank_disabled(crtc);
4905 drm_crtc_vblank_on(crtc);
4906
8807e55b 4907 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 4908 encoder->enable(encoder);
8807e55b
JN		 4909 intel_opregion_notify_encoder(encoder, true);
4910 }
4f771f10 4911
6b698516
DV		 4912 if (intel_crtc->config->has_pch_encoder) {
4913 intel_wait_for_vblank(dev, pipe);
4914 intel_wait_for_vblank(dev, pipe);
4915 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
d2d65408
VS		 4916 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4917 true);
6b698516 4918 }
d2d65408 4919
e4916946
PZ		 4920 /* If we change the relative order between pipe/planes enabling, we need
4921 * to change the workaround. */
99d736a2
ML		 4922 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4923 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4924 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4925 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4926 }
4f771f10
PZ		 4927}
4928
bfd16b2a 4929static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
3f8dce3a
DV		 4930{
4931 struct drm_device *dev = crtc->base.dev;
4932 struct drm_i915_private *dev_priv = dev->dev_private;
4933 int pipe = crtc->pipe;
4934
4935 /* To avoid upsetting the power well on haswell only disable the pfit if
4936 * it's in use. The hw state code will make sure we get this right. */
bfd16b2a 4937 if (force || crtc->config->pch_pfit.enabled) {
3f8dce3a
DV		 4938 I915_WRITE(PF_CTL(pipe), 0);
4939 I915_WRITE(PF_WIN_POS(pipe), 0);
4940 I915_WRITE(PF_WIN_SZ(pipe), 0);
4941 }
4942}
4943
6be4a607
JB		 4944static void ironlake_crtc_disable(struct drm_crtc *crtc)
4945{
4946 struct drm_device *dev = crtc->dev;
4947 struct drm_i915_private *dev_priv = dev->dev_private;
4948 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4949 struct intel_encoder *encoder;
6be4a607 4950 int pipe = intel_crtc->pipe;
b52eb4dc 4951
37ca8d4c
VS		 4952 if (intel_crtc->config->has_pch_encoder)
4953 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4954
ea9d758d
DV		 4955 for_each_encoder_on_crtc(dev, crtc, encoder)
4956 encoder->disable(encoder);
4957
f9b61ff6
DV		 4958 drm_crtc_vblank_off(crtc);
4959 assert_vblank_disabled(crtc);
4960
3860b2ec
VS		 4961 /*
4962 * Sometimes spurious CPU pipe underruns happen when the
4963 * pipe is already disabled, but FDI RX/TX is still enabled.
4964 * Happens at least with VGA+HDMI cloning. Suppress them.
4965 */
4966 if (intel_crtc->config->has_pch_encoder)
4967 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4968
575f7ab7 4969 intel_disable_pipe(intel_crtc);
32f9d658 4970
bfd16b2a 4971 ironlake_pfit_disable(intel_crtc, false);
2c07245f 4972
3860b2ec 4973 if (intel_crtc->config->has_pch_encoder) {
5a74f70a 4974 ironlake_fdi_disable(crtc);
3860b2ec
VS		 4975 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4976 }
5a74f70a 4977
bf49ec8c
DV		 4978 for_each_encoder_on_crtc(dev, crtc, encoder)
4979 if (encoder->post_disable)
4980 encoder->post_disable(encoder);
2c07245f 4981
6e3c9717 4982 if (intel_crtc->config->has_pch_encoder) {
d925c59a 4983 ironlake_disable_pch_transcoder(dev_priv, pipe);
6be4a607 4984
d925c59a 4985 if (HAS_PCH_CPT(dev)) {
f0f59a00
VS		 4986 i915_reg_t reg;
4987 u32 temp;
4988
d925c59a
DV		 4989 /* disable TRANS_DP_CTL */
4990 reg = TRANS_DP_CTL(pipe);
4991 temp = I915_READ(reg);
4992 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4993 TRANS_DP_PORT_SEL_MASK);
4994 temp |= TRANS_DP_PORT_SEL_NONE;
4995 I915_WRITE(reg, temp);
4996
4997 /* disable DPLL_SEL */
4998 temp = I915_READ(PCH_DPLL_SEL);
11887397 4999 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 5000 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 5001 }
e3421a18 5002
d925c59a
DV		 5003 ironlake_fdi_pll_disable(intel_crtc);
5004 }
81b088ca
VS		 5005
5006 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
6be4a607 5007}
1b3c7a47 5008
4f771f10 5009static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 5010{
4f771f10
PZ		 5011 struct drm_device *dev = crtc->dev;
5012 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 5013 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10 5014 struct intel_encoder *encoder;
6e3c9717 5015 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee7b9f93 5016
d2d65408
VS		 5017 if (intel_crtc->config->has_pch_encoder)
5018 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5019 false);
5020
8807e55b
JN		 5021 for_each_encoder_on_crtc(dev, crtc, encoder) {
5022 intel_opregion_notify_encoder(encoder, false);
4f771f10 5023 encoder->disable(encoder);
8807e55b 5024 }
4f771f10 5025
f9b61ff6
DV		 5026 drm_crtc_vblank_off(crtc);
5027 assert_vblank_disabled(crtc);
5028
4d1de975
JN		 5029 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5030 if (!intel_crtc->config->has_dsi_encoder)
5031 intel_disable_pipe(intel_crtc);
4f771f10 5032
6e3c9717 5033 if (intel_crtc->config->dp_encoder_is_mst)
a4bf214f
VS		 5034 intel_ddi_set_vc_payload_alloc(crtc, false);
5035
a65347ba 5036 if (!intel_crtc->config->has_dsi_encoder)
7d4aefd0 5037 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 5038
1c132b44 5039 if (INTEL_INFO(dev)->gen >= 9)
e435d6e5 5040 skylake_scaler_disable(intel_crtc);
ff6d9f55 5041 else
bfd16b2a 5042 ironlake_pfit_disable(intel_crtc, false);
4f771f10 5043
a65347ba 5044 if (!intel_crtc->config->has_dsi_encoder)
7d4aefd0 5045 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10 5046
97b040aa
ID		 5047 for_each_encoder_on_crtc(dev, crtc, encoder)
5048 if (encoder->post_disable)
5049 encoder->post_disable(encoder);
81b088ca 5050
92966a37
VS		 5051 if (intel_crtc->config->has_pch_encoder) {
5052 lpt_disable_pch_transcoder(dev_priv);
503a74e9 5053 lpt_disable_iclkip(dev_priv);
92966a37
VS		 5054 intel_ddi_fdi_disable(crtc);
5055
81b088ca
VS		 5056 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5057 true);
92966a37 5058 }
4f771f10
PZ		 5059}
5060
2dd24552
JB		 5061static void i9xx_pfit_enable(struct intel_crtc *crtc)
5062{
5063 struct drm_device *dev = crtc->base.dev;
5064 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 5065 struct intel_crtc_state *pipe_config = crtc->config;
2dd24552 5066
681a8504 5067 if (!pipe_config->gmch_pfit.control)
2dd24552
JB		 5068 return;
5069
2dd24552 5070 /*
c0b03411
DV		 5071 * The panel fitter should only be adjusted whilst the pipe is disabled,
5072 * according to register description and PRM.
2dd24552 5073 */
c0b03411
DV		 5074 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5075 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 5076
b074cec8
JB		 5077 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5078 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 5079
5080 /* Border color in case we don't scale up to the full screen. Black by
5081 * default, change to something else for debugging. */
5082 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 5083}
5084
d05410f9
DA		 5085static enum intel_display_power_domain port_to_power_domain(enum port port)
5086{
5087 switch (port) {
5088 case PORT_A:
6331a704 5089 return POWER_DOMAIN_PORT_DDI_A_LANES;
d05410f9 5090 case PORT_B:
6331a704 5091 return POWER_DOMAIN_PORT_DDI_B_LANES;
d05410f9 5092 case PORT_C:
6331a704 5093 return POWER_DOMAIN_PORT_DDI_C_LANES;
d05410f9 5094 case PORT_D:
6331a704 5095 return POWER_DOMAIN_PORT_DDI_D_LANES;
d8e19f99 5096 case PORT_E:
6331a704 5097 return POWER_DOMAIN_PORT_DDI_E_LANES;
d05410f9 5098 default:
b9fec167 5099 MISSING_CASE(port);
d05410f9
DA		 5100 return POWER_DOMAIN_PORT_OTHER;
5101 }
5102}
5103
25f78f58
VS		 5104static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5105{
5106 switch (port) {
5107 case PORT_A:
5108 return POWER_DOMAIN_AUX_A;
5109 case PORT_B:
5110 return POWER_DOMAIN_AUX_B;
5111 case PORT_C:
5112 return POWER_DOMAIN_AUX_C;
5113 case PORT_D:
5114 return POWER_DOMAIN_AUX_D;
5115 case PORT_E:
5116 /* FIXME: Check VBT for actual wiring of PORT E */
5117 return POWER_DOMAIN_AUX_D;
5118 default:
b9fec167 5119 MISSING_CASE(port);
25f78f58
VS		 5120 return POWER_DOMAIN_AUX_A;
5121 }
5122}
5123
319be8ae
ID		 5124enum intel_display_power_domain
5125intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5126{
5127 struct drm_device *dev = intel_encoder->base.dev;
5128 struct intel_digital_port *intel_dig_port;
5129
5130 switch (intel_encoder->type) {
5131 case INTEL_OUTPUT_UNKNOWN:
5132 /* Only DDI platforms should ever use this output type */
5133 WARN_ON_ONCE(!HAS_DDI(dev));
5134 case INTEL_OUTPUT_DISPLAYPORT:
5135 case INTEL_OUTPUT_HDMI:
5136 case INTEL_OUTPUT_EDP:
5137 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
d05410f9 5138 return port_to_power_domain(intel_dig_port->port);
0e32b39c
DA		 5139 case INTEL_OUTPUT_DP_MST:
5140 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5141 return port_to_power_domain(intel_dig_port->port);
319be8ae
ID		 5142 case INTEL_OUTPUT_ANALOG:
5143 return POWER_DOMAIN_PORT_CRT;
5144 case INTEL_OUTPUT_DSI:
5145 return POWER_DOMAIN_PORT_DSI;
5146 default:
5147 return POWER_DOMAIN_PORT_OTHER;
5148 }
5149}
5150
25f78f58
VS		 5151enum intel_display_power_domain
5152intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5153{
5154 struct drm_device *dev = intel_encoder->base.dev;
5155 struct intel_digital_port *intel_dig_port;
5156
5157 switch (intel_encoder->type) {
5158 case INTEL_OUTPUT_UNKNOWN:
651174a4
ID		 5159 case INTEL_OUTPUT_HDMI:
5160 /*
5161 * Only DDI platforms should ever use these output types.
5162 * We can get here after the HDMI detect code has already set
5163 * the type of the shared encoder. Since we can't be sure
5164 * what's the status of the given connectors, play safe and
5165 * run the DP detection too.
5166 */
25f78f58
VS		 5167 WARN_ON_ONCE(!HAS_DDI(dev));
5168 case INTEL_OUTPUT_DISPLAYPORT:
5169 case INTEL_OUTPUT_EDP:
5170 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5171 return port_to_aux_power_domain(intel_dig_port->port);
5172 case INTEL_OUTPUT_DP_MST:
5173 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5174 return port_to_aux_power_domain(intel_dig_port->port);
5175 default:
b9fec167 5176 MISSING_CASE(intel_encoder->type);
25f78f58
VS		 5177 return POWER_DOMAIN_AUX_A;
5178 }
5179}
5180
74bff5f9
ML		 5181static unsigned long get_crtc_power_domains(struct drm_crtc *crtc,
5182 struct intel_crtc_state *crtc_state)
77d22dca 5183{
319be8ae 5184 struct drm_device *dev = crtc->dev;
74bff5f9 5185 struct drm_encoder *encoder;
319be8ae
ID		 5186 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5187 enum pipe pipe = intel_crtc->pipe;
77d22dca 5188 unsigned long mask;
74bff5f9 5189 enum transcoder transcoder = crtc_state->cpu_transcoder;
77d22dca 5190
74bff5f9 5191 if (!crtc_state->base.active)
292b990e
ML		 5192 return 0;
5193
77d22dca
ID		 5194 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5195 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
74bff5f9
ML		 5196 if (crtc_state->pch_pfit.enabled ||
5197 crtc_state->pch_pfit.force_thru)
77d22dca
ID		 5198 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5199
74bff5f9
ML		 5200 drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5201 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5202
319be8ae 5203 mask |= BIT(intel_display_port_power_domain(intel_encoder));
74bff5f9 5204 }
319be8ae 5205
15e7ec29
ML		 5206 if (crtc_state->shared_dpll)
5207 mask |= BIT(POWER_DOMAIN_PLLS);
5208
77d22dca
ID		 5209 return mask;
5210}
5211
74bff5f9
ML		 5212static unsigned long
5213modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5214 struct intel_crtc_state *crtc_state)
77d22dca 5215{
292b990e
ML		 5216 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5217 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5218 enum intel_display_power_domain domain;
5219 unsigned long domains, new_domains, old_domains;
77d22dca 5220
292b990e 5221 old_domains = intel_crtc->enabled_power_domains;
74bff5f9
ML		 5222 intel_crtc->enabled_power_domains = new_domains =
5223 get_crtc_power_domains(crtc, crtc_state);
77d22dca 5224
292b990e
ML		 5225 domains = new_domains & ~old_domains;
5226
5227 for_each_power_domain(domain, domains)
5228 intel_display_power_get(dev_priv, domain);
5229
5230 return old_domains & ~new_domains;
5231}
5232
5233static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5234 unsigned long domains)
5235{
5236 enum intel_display_power_domain domain;
5237
5238 for_each_power_domain(domain, domains)
5239 intel_display_power_put(dev_priv, domain);
5240}
77d22dca 5241
adafdc6f
MK		 5242static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5243{
5244 int max_cdclk_freq = dev_priv->max_cdclk_freq;
5245
5246 if (INTEL_INFO(dev_priv)->gen >= 9 ||
5247 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5248 return max_cdclk_freq;
5249 else if (IS_CHERRYVIEW(dev_priv))
5250 return max_cdclk_freq*95/100;
5251 else if (INTEL_INFO(dev_priv)->gen < 4)
5252 return 2*max_cdclk_freq*90/100;
5253 else
5254 return max_cdclk_freq*90/100;
5255}
5256
560a7ae4
DL		 5257static void intel_update_max_cdclk(struct drm_device *dev)
5258{
5259 struct drm_i915_private *dev_priv = dev->dev_private;
5260
ef11bdb3 5261 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
560a7ae4
DL		 5262 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5263
5264 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5265 dev_priv->max_cdclk_freq = 675000;
5266 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5267 dev_priv->max_cdclk_freq = 540000;
5268 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5269 dev_priv->max_cdclk_freq = 450000;
5270 else
5271 dev_priv->max_cdclk_freq = 337500;
5272 } else if (IS_BROADWELL(dev)) {
5273 /*
5274 * FIXME with extra cooling we can allow
5275 * 540 MHz for ULX and 675 Mhz for ULT.
5276 * How can we know if extra cooling is
5277 * available? PCI ID, VTB, something else?
5278 */
5279 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5280 dev_priv->max_cdclk_freq = 450000;
5281 else if (IS_BDW_ULX(dev))
5282 dev_priv->max_cdclk_freq = 450000;
5283 else if (IS_BDW_ULT(dev))
5284 dev_priv->max_cdclk_freq = 540000;
5285 else
5286 dev_priv->max_cdclk_freq = 675000;
0904deaf
MK		 5287 } else if (IS_CHERRYVIEW(dev)) {
5288 dev_priv->max_cdclk_freq = 320000;
560a7ae4
DL		 5289 } else if (IS_VALLEYVIEW(dev)) {
5290 dev_priv->max_cdclk_freq = 400000;
5291 } else {
5292 /* otherwise assume cdclk is fixed */
5293 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5294 }
5295
adafdc6f
MK		 5296 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5297
560a7ae4
DL		 5298 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5299 dev_priv->max_cdclk_freq);
adafdc6f
MK		 5300
5301 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5302 dev_priv->max_dotclk_freq);
560a7ae4
DL		 5303}
5304
5305static void intel_update_cdclk(struct drm_device *dev)
5306{
5307 struct drm_i915_private *dev_priv = dev->dev_private;
5308
5309 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5310 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5311 dev_priv->cdclk_freq);
5312
5313 /*
5314 * Program the gmbus_freq based on the cdclk frequency.
5315 * BSpec erroneously claims we should aim for 4MHz, but
5316 * in fact 1MHz is the correct frequency.
5317 */
666a4537 5318 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
560a7ae4
DL		 5319 /*
5320 * Program the gmbus_freq based on the cdclk frequency.
5321 * BSpec erroneously claims we should aim for 4MHz, but
5322 * in fact 1MHz is the correct frequency.
5323 */
5324 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5325 }
5326
5327 if (dev_priv->max_cdclk_freq == 0)
5328 intel_update_max_cdclk(dev);
5329}
5330
70d0c574 5331static void broxton_set_cdclk(struct drm_device *dev, int frequency)
f8437dd1
VK		 5332{
5333 struct drm_i915_private *dev_priv = dev->dev_private;
5334 uint32_t divider;
5335 uint32_t ratio;
5336 uint32_t current_freq;
5337 int ret;
5338
5339 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5340 switch (frequency) {
5341 case 144000:
5342 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5343 ratio = BXT_DE_PLL_RATIO(60);
5344 break;
5345 case 288000:
5346 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5347 ratio = BXT_DE_PLL_RATIO(60);
5348 break;
5349 case 384000:
5350 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5351 ratio = BXT_DE_PLL_RATIO(60);
5352 break;
5353 case 576000:
5354 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5355 ratio = BXT_DE_PLL_RATIO(60);
5356 break;
5357 case 624000:
5358 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5359 ratio = BXT_DE_PLL_RATIO(65);
5360 break;
5361 case 19200:
5362 /*
5363 * Bypass frequency with DE PLL disabled. Init ratio, divider
5364 * to suppress GCC warning.
5365 */
5366 ratio = 0;
5367 divider = 0;
5368 break;
5369 default:
5370 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5371
5372 return;
5373 }
5374
5375 mutex_lock(&dev_priv->rps.hw_lock);
5376 /* Inform power controller of upcoming frequency change */
5377 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5378 0x80000000);
5379 mutex_unlock(&dev_priv->rps.hw_lock);
5380
5381 if (ret) {
5382 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5383 ret, frequency);
5384 return;
5385 }
5386
5387 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5388 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5389 current_freq = current_freq * 500 + 1000;
5390
5391 /*
5392 * DE PLL has to be disabled when
5393 * - setting to 19.2MHz (bypass, PLL isn't used)
5394 * - before setting to 624MHz (PLL needs toggling)
5395 * - before setting to any frequency from 624MHz (PLL needs toggling)
5396 */
5397 if (frequency == 19200 || frequency == 624000 ||
5398 current_freq == 624000) {
5399 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5400 /* Timeout 200us */
5401 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5402 1))
5403 DRM_ERROR("timout waiting for DE PLL unlock\n");
5404 }
5405
5406 if (frequency != 19200) {
5407 uint32_t val;
5408
5409 val = I915_READ(BXT_DE_PLL_CTL);
5410 val &= ~BXT_DE_PLL_RATIO_MASK;
5411 val |= ratio;
5412 I915_WRITE(BXT_DE_PLL_CTL, val);
5413
5414 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5415 /* Timeout 200us */
5416 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5417 DRM_ERROR("timeout waiting for DE PLL lock\n");
5418
5419 val = I915_READ(CDCLK_CTL);
5420 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5421 val |= divider;
5422 /*
5423 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5424 * enable otherwise.
5425 */
5426 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5427 if (frequency >= 500000)
5428 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5429
5430 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5431 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5432 val |= (frequency - 1000) / 500;
5433 I915_WRITE(CDCLK_CTL, val);
5434 }
5435
5436 mutex_lock(&dev_priv->rps.hw_lock);
5437 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5438 DIV_ROUND_UP(frequency, 25000));
5439 mutex_unlock(&dev_priv->rps.hw_lock);
5440
5441 if (ret) {
5442 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5443 ret, frequency);
5444 return;
5445 }
5446
a47871bd 5447 intel_update_cdclk(dev);
f8437dd1
VK		 5448}
5449
5450void broxton_init_cdclk(struct drm_device *dev)
5451{
5452 struct drm_i915_private *dev_priv = dev->dev_private;
5453 uint32_t val;
5454
5455 /*
5456 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5457 * or else the reset will hang because there is no PCH to respond.
5458 * Move the handshake programming to initialization sequence.
5459 * Previously was left up to BIOS.
5460 */
5461 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5462 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5463 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5464
5465 /* Enable PG1 for cdclk */
5466 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5467
5468 /* check if cd clock is enabled */
5469 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5470 DRM_DEBUG_KMS("Display already initialized\n");
5471 return;
5472 }
5473
5474 /*
5475 * FIXME:
5476 * - The initial CDCLK needs to be read from VBT.
5477 * Need to make this change after VBT has changes for BXT.
5478 * - check if setting the max (or any) cdclk freq is really necessary
5479 * here, it belongs to modeset time
5480 */
5481 broxton_set_cdclk(dev, 624000);
5482
5483 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
22e02c0b
VS		 5484 POSTING_READ(DBUF_CTL);
5485
f8437dd1
VK		 5486 udelay(10);
5487
5488 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5489 DRM_ERROR("DBuf power enable timeout!\n");
5490}
5491
5492void broxton_uninit_cdclk(struct drm_device *dev)
5493{
5494 struct drm_i915_private *dev_priv = dev->dev_private;
5495
5496 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
22e02c0b
VS		 5497 POSTING_READ(DBUF_CTL);
5498
f8437dd1
VK		 5499 udelay(10);
5500
5501 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5502 DRM_ERROR("DBuf power disable timeout!\n");
5503
5504 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5505 broxton_set_cdclk(dev, 19200);
5506
5507 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5508}
5509
5d96d8af
DL		 5510static const struct skl_cdclk_entry {
5511 unsigned int freq;
5512 unsigned int vco;
5513} skl_cdclk_frequencies[] = {
5514 { .freq = 308570, .vco = 8640 },
5515 { .freq = 337500, .vco = 8100 },
5516 { .freq = 432000, .vco = 8640 },
5517 { .freq = 450000, .vco = 8100 },
5518 { .freq = 540000, .vco = 8100 },
5519 { .freq = 617140, .vco = 8640 },
5520 { .freq = 675000, .vco = 8100 },
5521};
5522
5523static unsigned int skl_cdclk_decimal(unsigned int freq)
5524{
5525 return (freq - 1000) / 500;
5526}
5527
5528static unsigned int skl_cdclk_get_vco(unsigned int freq)
5529{
5530 unsigned int i;
5531
5532 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5533 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5534
5535 if (e->freq == freq)
5536 return e->vco;
5537 }
5538
5539 return 8100;
5540}
5541
5542static void
5543skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5544{
5545 unsigned int min_freq;
5546 u32 val;
5547
5548 /* select the minimum CDCLK before enabling DPLL 0 */
5549 val = I915_READ(CDCLK_CTL);
5550 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5551 val |= CDCLK_FREQ_337_308;
5552
5553 if (required_vco == 8640)
5554 min_freq = 308570;
5555 else
5556 min_freq = 337500;
5557
5558 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5559
5560 I915_WRITE(CDCLK_CTL, val);
5561 POSTING_READ(CDCLK_CTL);
5562
5563 /*
5564 * We always enable DPLL0 with the lowest link rate possible, but still
5565 * taking into account the VCO required to operate the eDP panel at the
5566 * desired frequency. The usual DP link rates operate with a VCO of
5567 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5568 * The modeset code is responsible for the selection of the exact link
5569 * rate later on, with the constraint of choosing a frequency that
5570 * works with required_vco.
5571 */
5572 val = I915_READ(DPLL_CTRL1);
5573
5574 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5575 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5576 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5577 if (required_vco == 8640)
5578 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5579 SKL_DPLL0);
5580 else
5581 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5582 SKL_DPLL0);
5583
5584 I915_WRITE(DPLL_CTRL1, val);
5585 POSTING_READ(DPLL_CTRL1);
5586
5587 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5588
5589 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5590 DRM_ERROR("DPLL0 not locked\n");
5591}
5592
5593static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5594{
5595 int ret;
5596 u32 val;
5597
5598 /* inform PCU we want to change CDCLK */
5599 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5600 mutex_lock(&dev_priv->rps.hw_lock);
5601 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5602 mutex_unlock(&dev_priv->rps.hw_lock);
5603
5604 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5605}
5606
5607static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5608{
5609 unsigned int i;
5610
5611 for (i = 0; i < 15; i++) {
5612 if (skl_cdclk_pcu_ready(dev_priv))
5613 return true;
5614 udelay(10);
5615 }
5616
5617 return false;
5618}
5619
5620static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5621{
560a7ae4 5622 struct drm_device *dev = dev_priv->dev;
5d96d8af
DL		 5623 u32 freq_select, pcu_ack;
5624
5625 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5626
5627 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5628 DRM_ERROR("failed to inform PCU about cdclk change\n");
5629 return;
5630 }
5631
5632 /* set CDCLK_CTL */
5633 switch(freq) {
5634 case 450000:
5635 case 432000:
5636 freq_select = CDCLK_FREQ_450_432;
5637 pcu_ack = 1;
5638 break;
5639 case 540000:
5640 freq_select = CDCLK_FREQ_540;
5641 pcu_ack = 2;
5642 break;
5643 case 308570:
5644 case 337500:
5645 default:
5646 freq_select = CDCLK_FREQ_337_308;
5647 pcu_ack = 0;
5648 break;
5649 case 617140:
5650 case 675000:
5651 freq_select = CDCLK_FREQ_675_617;
5652 pcu_ack = 3;
5653 break;
5654 }
5655
5656 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5657 POSTING_READ(CDCLK_CTL);
5658
5659 /* inform PCU of the change */
5660 mutex_lock(&dev_priv->rps.hw_lock);
5661 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5662 mutex_unlock(&dev_priv->rps.hw_lock);
560a7ae4
DL		 5663
5664 intel_update_cdclk(dev);
5d96d8af
DL		 5665}
5666
5667void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5668{
5669 /* disable DBUF power */
5670 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5671 POSTING_READ(DBUF_CTL);
5672
5673 udelay(10);
5674
5675 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5676 DRM_ERROR("DBuf power disable timeout\n");
5677
ab96c1ee
ID		 5678 /* disable DPLL0 */
5679 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5680 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5681 DRM_ERROR("Couldn't disable DPLL0\n");
5d96d8af
DL		 5682}
5683
5684void skl_init_cdclk(struct drm_i915_private *dev_priv)
5685{
5d96d8af
DL		 5686 unsigned int required_vco;
5687
39d9b85a
GW		 5688 /* DPLL0 not enabled (happens on early BIOS versions) */
5689 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5690 /* enable DPLL0 */
5691 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5692 skl_dpll0_enable(dev_priv, required_vco);
5d96d8af
DL		 5693 }
5694
5d96d8af
DL		 5695 /* set CDCLK to the frequency the BIOS chose */
5696 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5697
5698 /* enable DBUF power */
5699 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5700 POSTING_READ(DBUF_CTL);
5701
5702 udelay(10);
5703
5704 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5705 DRM_ERROR("DBuf power enable timeout\n");
5706}
5707
c73666f3
SK		 5708int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
5709{
5710 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
5711 uint32_t cdctl = I915_READ(CDCLK_CTL);
5712 int freq = dev_priv->skl_boot_cdclk;
5713
f1b391a5
SK		 5714 /*
5715 * check if the pre-os intialized the display
5716 * There is SWF18 scratchpad register defined which is set by the
5717 * pre-os which can be used by the OS drivers to check the status
5718 */
5719 if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
5720 goto sanitize;
5721
c73666f3
SK		 5722 /* Is PLL enabled and locked ? */
5723 if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK)))
5724 goto sanitize;
5725
5726 /* DPLL okay; verify the cdclock
5727 *
5728 * Noticed in some instances that the freq selection is correct but
5729 * decimal part is programmed wrong from BIOS where pre-os does not
5730 * enable display. Verify the same as well.
5731 */
5732 if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq)))
5733 /* All well; nothing to sanitize */
5734 return false;
5735sanitize:
5736 /*
5737 * As of now initialize with max cdclk till
5738 * we get dynamic cdclk support
5739 * */
5740 dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
5741 skl_init_cdclk(dev_priv);
5742
5743 /* we did have to sanitize */
5744 return true;
5745}
5746
30a970c6
JB		 5747/* Adjust CDclk dividers to allow high res or save power if possible */
5748static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5749{
5750 struct drm_i915_private *dev_priv = dev->dev_private;
5751 u32 val, cmd;
5752
164dfd28
VK		 5753 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5754 != dev_priv->cdclk_freq);
d60c4473 5755
dfcab17e 5756 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
30a970c6 5757 cmd = 2;
dfcab17e 5758 else if (cdclk == 266667)
30a970c6
JB		 5759 cmd = 1;
5760 else
5761 cmd = 0;
5762
5763 mutex_lock(&dev_priv->rps.hw_lock);
5764 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5765 val &= ~DSPFREQGUAR_MASK;
5766 val |= (cmd << DSPFREQGUAR_SHIFT);
5767 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5768 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5769 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5770 50)) {
5771 DRM_ERROR("timed out waiting for CDclk change\n");
5772 }
5773 mutex_unlock(&dev_priv->rps.hw_lock);
5774
54433e91
VS		 5775 mutex_lock(&dev_priv->sb_lock);
5776
dfcab17e 5777 if (cdclk == 400000) {
6bcda4f0 5778 u32 divider;
30a970c6 5779
6bcda4f0 5780 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
30a970c6 5781
30a970c6
JB		 5782 /* adjust cdclk divider */
5783 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
87d5d259 5784 val &= ~CCK_FREQUENCY_VALUES;
30a970c6
JB		 5785 val |= divider;
5786 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
a877e801
VS		 5787
5788 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
87d5d259 5789 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
a877e801
VS		 5790 50))
5791 DRM_ERROR("timed out waiting for CDclk change\n");
30a970c6
JB		 5792 }
5793
30a970c6
JB		 5794 /* adjust self-refresh exit latency value */
5795 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5796 val &= ~0x7f;
5797
5798 /*
5799 * For high bandwidth configs, we set a higher latency in the bunit
5800 * so that the core display fetch happens in time to avoid underruns.
5801 */
dfcab17e 5802 if (cdclk == 400000)
30a970c6
JB		 5803 val |= 4500 / 250; /* 4.5 usec */
5804 else
5805 val |= 3000 / 250; /* 3.0 usec */
5806 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
54433e91 5807
a580516d 5808 mutex_unlock(&dev_priv->sb_lock);
30a970c6 5809
b6283055 5810 intel_update_cdclk(dev);
30a970c6
JB		 5811}
5812
383c5a6a
VS		 5813static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5814{
5815 struct drm_i915_private *dev_priv = dev->dev_private;
5816 u32 val, cmd;
5817
164dfd28
VK		 5818 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5819 != dev_priv->cdclk_freq);
383c5a6a
VS		 5820
5821 switch (cdclk) {
383c5a6a
VS		 5822 case 333333:
5823 case 320000:
383c5a6a 5824 case 266667:
383c5a6a 5825 case 200000:
383c5a6a
VS		 5826 break;
5827 default:
5f77eeb0 5828 MISSING_CASE(cdclk);
383c5a6a
VS		 5829 return;
5830 }
5831
9d0d3fda
VS		 5832 /*
5833 * Specs are full of misinformation, but testing on actual
5834 * hardware has shown that we just need to write the desired
5835 * CCK divider into the Punit register.
5836 */
5837 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5838
383c5a6a
VS		 5839 mutex_lock(&dev_priv->rps.hw_lock);
5840 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5841 val &= ~DSPFREQGUAR_MASK_CHV;
5842 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5843 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5844 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5845 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5846 50)) {
5847 DRM_ERROR("timed out waiting for CDclk change\n");
5848 }
5849 mutex_unlock(&dev_priv->rps.hw_lock);
5850
b6283055 5851 intel_update_cdclk(dev);
383c5a6a
VS		 5852}
5853
30a970c6
JB		 5854static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5855 int max_pixclk)
5856{
6bcda4f0 5857 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6cca3195 5858 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
29dc7ef3 5859
30a970c6
JB		 5860 /*
5861 * Really only a few cases to deal with, as only 4 CDclks are supported:
5862 * 200MHz
5863 * 267MHz
29dc7ef3 5864 * 320/333MHz (depends on HPLL freq)
6cca3195
VS		 5865 * 400MHz (VLV only)
5866 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5867 * of the lower bin and adjust if needed.
e37c67a1
VS		 5868 *
5869 * We seem to get an unstable or solid color picture at 200MHz.
5870 * Not sure what's wrong. For now use 200MHz only when all pipes
5871 * are off.
30a970c6 5872 */
6cca3195
VS		 5873 if (!IS_CHERRYVIEW(dev_priv) &&
5874 max_pixclk > freq_320*limit/100)
dfcab17e 5875 return 400000;
6cca3195 5876 else if (max_pixclk > 266667*limit/100)
29dc7ef3 5877 return freq_320;
e37c67a1 5878 else if (max_pixclk > 0)
dfcab17e 5879 return 266667;
e37c67a1
VS		 5880 else
5881 return 200000;
30a970c6
JB		 5882}
5883
f8437dd1
VK		 5884static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5885 int max_pixclk)
5886{
5887 /*
5888 * FIXME:
5889 * - remove the guardband, it's not needed on BXT
5890 * - set 19.2MHz bypass frequency if there are no active pipes
5891 */
5892 if (max_pixclk > 576000*9/10)
5893 return 624000;
5894 else if (max_pixclk > 384000*9/10)
5895 return 576000;
5896 else if (max_pixclk > 288000*9/10)
5897 return 384000;
5898 else if (max_pixclk > 144000*9/10)
5899 return 288000;
5900 else
5901 return 144000;
5902}
5903
e8788cbc 5904/* Compute the max pixel clock for new configuration. */
a821fc46
ACO		 5905static int intel_mode_max_pixclk(struct drm_device *dev,
5906 struct drm_atomic_state *state)
30a970c6 5907{
565602d7
ML		 5908 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
5909 struct drm_i915_private *dev_priv = dev->dev_private;
5910 struct drm_crtc *crtc;
5911 struct drm_crtc_state *crtc_state;
5912 unsigned max_pixclk = 0, i;
5913 enum pipe pipe;
30a970c6 5914
565602d7
ML		 5915 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
5916 sizeof(intel_state->min_pixclk));
304603f4 5917
565602d7
ML		 5918 for_each_crtc_in_state(state, crtc, crtc_state, i) {
5919 int pixclk = 0;
5920
5921 if (crtc_state->enable)
5922 pixclk = crtc_state->adjusted_mode.crtc_clock;
304603f4 5923
565602d7 5924 intel_state->min_pixclk[i] = pixclk;
30a970c6
JB		 5925 }
5926
565602d7
ML		 5927 for_each_pipe(dev_priv, pipe)
5928 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
5929
30a970c6
JB		 5930 return max_pixclk;
5931}
5932
27c329ed 5933static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
30a970c6 5934{
27c329ed
ML		 5935 struct drm_device *dev = state->dev;
5936 struct drm_i915_private *dev_priv = dev->dev_private;
5937 int max_pixclk = intel_mode_max_pixclk(dev, state);
1a617b77
ML		 5938 struct intel_atomic_state *intel_state =
5939 to_intel_atomic_state(state);
30a970c6 5940
304603f4
ACO		 5941 if (max_pixclk < 0)
5942 return max_pixclk;
30a970c6 5943
1a617b77 5944 intel_state->cdclk = intel_state->dev_cdclk =
27c329ed 5945 valleyview_calc_cdclk(dev_priv, max_pixclk);
0a9ab303 5946
1a617b77
ML		 5947 if (!intel_state->active_crtcs)
5948 intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
5949
27c329ed
ML		 5950 return 0;
5951}
304603f4 5952
27c329ed
ML		 5953static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5954{
5955 struct drm_device *dev = state->dev;
5956 struct drm_i915_private *dev_priv = dev->dev_private;
5957 int max_pixclk = intel_mode_max_pixclk(dev, state);
1a617b77
ML		 5958 struct intel_atomic_state *intel_state =
5959 to_intel_atomic_state(state);
85a96e7a 5960
27c329ed
ML		 5961 if (max_pixclk < 0)
5962 return max_pixclk;
85a96e7a 5963
1a617b77 5964 intel_state->cdclk = intel_state->dev_cdclk =
27c329ed 5965 broxton_calc_cdclk(dev_priv, max_pixclk);
85a96e7a 5966
1a617b77
ML		 5967 if (!intel_state->active_crtcs)
5968 intel_state->dev_cdclk = broxton_calc_cdclk(dev_priv, 0);
5969
27c329ed 5970 return 0;
30a970c6
JB		 5971}
5972
1e69cd74
VS		 5973static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5974{
5975 unsigned int credits, default_credits;
5976
5977 if (IS_CHERRYVIEW(dev_priv))
5978 default_credits = PFI_CREDIT(12);
5979 else
5980 default_credits = PFI_CREDIT(8);
5981
bfa7df01 5982 if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
1e69cd74
VS		 5983 /* CHV suggested value is 31 or 63 */
5984 if (IS_CHERRYVIEW(dev_priv))
fcc0008f 5985 credits = PFI_CREDIT_63;
1e69cd74
VS		 5986 else
5987 credits = PFI_CREDIT(15);
5988 } else {
5989 credits = default_credits;
5990 }
5991
5992 /*
5993 * WA - write default credits before re-programming
5994 * FIXME: should we also set the resend bit here?
5995 */
5996 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5997 default_credits);
5998
5999 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6000 credits | PFI_CREDIT_RESEND);
6001
6002 /*
6003 * FIXME is this guaranteed to clear
6004 * immediately or should we poll for it?
6005 */
6006 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6007}
6008
27c329ed 6009static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
30a970c6 6010{
a821fc46 6011 struct drm_device *dev = old_state->dev;
30a970c6 6012 struct drm_i915_private *dev_priv = dev->dev_private;
1a617b77
ML		 6013 struct intel_atomic_state *old_intel_state =
6014 to_intel_atomic_state(old_state);
6015 unsigned req_cdclk = old_intel_state->dev_cdclk;
30a970c6 6016
27c329ed
ML		 6017 /*
6018 * FIXME: We can end up here with all power domains off, yet
6019 * with a CDCLK frequency other than the minimum. To account
6020 * for this take the PIPE-A power domain, which covers the HW
6021 * blocks needed for the following programming. This can be
6022 * removed once it's guaranteed that we get here either with
6023 * the minimum CDCLK set, or the required power domains
6024 * enabled.
6025 */
6026 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
738c05c0 6027
27c329ed
ML		 6028 if (IS_CHERRYVIEW(dev))
6029 cherryview_set_cdclk(dev, req_cdclk);
6030 else
6031 valleyview_set_cdclk(dev, req_cdclk);
738c05c0 6032
27c329ed 6033 vlv_program_pfi_credits(dev_priv);
1e69cd74 6034
27c329ed 6035 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
30a970c6
JB		 6036}
6037
89b667f8
JB		 6038static void valleyview_crtc_enable(struct drm_crtc *crtc)
6039{
6040 struct drm_device *dev = crtc->dev;
a72e4c9f 6041 struct drm_i915_private *dev_priv = to_i915(dev);
89b667f8
JB		 6042 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6043 struct intel_encoder *encoder;
b95c5321
ML		 6044 struct intel_crtc_state *pipe_config =
6045 to_intel_crtc_state(crtc->state);
89b667f8 6046 int pipe = intel_crtc->pipe;
89b667f8 6047
53d9f4e9 6048 if (WARN_ON(intel_crtc->active))
89b667f8
JB		 6049 return;
6050
6e3c9717 6051 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6052 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 6053
6054 intel_set_pipe_timings(intel_crtc);
bc58be60 6055 intel_set_pipe_src_size(intel_crtc);
5b18e57c 6056
c14b0485
VS		 6057 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6058 struct drm_i915_private *dev_priv = dev->dev_private;
6059
6060 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6061 I915_WRITE(CHV_CANVAS(pipe), 0);
6062 }
6063
5b18e57c
DV		 6064 i9xx_set_pipeconf(intel_crtc);
6065
89b667f8 6066 intel_crtc->active = true;
89b667f8 6067
a72e4c9f 6068 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6069
89b667f8
JB		 6070 for_each_encoder_on_crtc(dev, crtc, encoder)
6071 if (encoder->pre_pll_enable)
6072 encoder->pre_pll_enable(encoder);
6073
a65347ba 6074 if (!intel_crtc->config->has_dsi_encoder) {
c0b4c660
VS		 6075 if (IS_CHERRYVIEW(dev)) {
6076 chv_prepare_pll(intel_crtc, intel_crtc->config);
6e3c9717 6077 chv_enable_pll(intel_crtc, intel_crtc->config);
c0b4c660
VS		 6078 } else {
6079 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6e3c9717 6080 vlv_enable_pll(intel_crtc, intel_crtc->config);
c0b4c660 6081 }
9d556c99 6082 }
89b667f8
JB		 6083
6084 for_each_encoder_on_crtc(dev, crtc, encoder)
6085 if (encoder->pre_enable)
6086 encoder->pre_enable(encoder);
6087
2dd24552
JB		 6088 i9xx_pfit_enable(intel_crtc);
6089
b95c5321 6090 intel_color_load_luts(&pipe_config->base);
63cbb074 6091
caed361d 6092 intel_update_watermarks(crtc);
e1fdc473 6093 intel_enable_pipe(intel_crtc);
be6a6f8e 6094
4b3a9526
VS		 6095 assert_vblank_disabled(crtc);
6096 drm_crtc_vblank_on(crtc);
6097
f9b61ff6
DV		 6098 for_each_encoder_on_crtc(dev, crtc, encoder)
6099 encoder->enable(encoder);
89b667f8
JB		 6100}
6101
f13c2ef3
DV		 6102static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6103{
6104 struct drm_device *dev = crtc->base.dev;
6105 struct drm_i915_private *dev_priv = dev->dev_private;
6106
6e3c9717
ACO		 6107 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6108 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
f13c2ef3
DV		 6109}
6110
0b8765c6 6111static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 6112{
6113 struct drm_device *dev = crtc->dev;
a72e4c9f 6114 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945 6115 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6116 struct intel_encoder *encoder;
b95c5321
ML		 6117 struct intel_crtc_state *pipe_config =
6118 to_intel_crtc_state(crtc->state);
79e53945 6119 int pipe = intel_crtc->pipe;
79e53945 6120
53d9f4e9 6121 if (WARN_ON(intel_crtc->active))
f7abfe8b
CW		 6122 return;
6123
f13c2ef3
DV		 6124 i9xx_set_pll_dividers(intel_crtc);
6125
6e3c9717 6126 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6127 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 6128
6129 intel_set_pipe_timings(intel_crtc);
bc58be60 6130 intel_set_pipe_src_size(intel_crtc);
5b18e57c 6131
5b18e57c
DV		 6132 i9xx_set_pipeconf(intel_crtc);
6133
f7abfe8b 6134 intel_crtc->active = true;
6b383a7f 6135
4a3436e8 6136 if (!IS_GEN2(dev))
a72e4c9f 6137 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6138
9d6d9f19
MK		 6139 for_each_encoder_on_crtc(dev, crtc, encoder)
6140 if (encoder->pre_enable)
6141 encoder->pre_enable(encoder);
6142
f6736a1a
DV		 6143 i9xx_enable_pll(intel_crtc);
6144
2dd24552
JB		 6145 i9xx_pfit_enable(intel_crtc);
6146
b95c5321 6147 intel_color_load_luts(&pipe_config->base);
63cbb074 6148
f37fcc2a 6149 intel_update_watermarks(crtc);
e1fdc473 6150 intel_enable_pipe(intel_crtc);
be6a6f8e 6151
4b3a9526
VS		 6152 assert_vblank_disabled(crtc);
6153 drm_crtc_vblank_on(crtc);
6154
f9b61ff6
DV		 6155 for_each_encoder_on_crtc(dev, crtc, encoder)
6156 encoder->enable(encoder);
0b8765c6 6157}
79e53945 6158
87476d63
DV		 6159static void i9xx_pfit_disable(struct intel_crtc *crtc)
6160{
6161 struct drm_device *dev = crtc->base.dev;
6162 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 6163
6e3c9717 6164 if (!crtc->config->gmch_pfit.control)
328d8e82 6165 return;
87476d63 6166
328d8e82 6167 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 6168
328d8e82
DV		 6169 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6170 I915_READ(PFIT_CONTROL));
6171 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 6172}
6173
0b8765c6
JB		 6174static void i9xx_crtc_disable(struct drm_crtc *crtc)
6175{
6176 struct drm_device *dev = crtc->dev;
6177 struct drm_i915_private *dev_priv = dev->dev_private;
6178 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6179 struct intel_encoder *encoder;
0b8765c6 6180 int pipe = intel_crtc->pipe;
ef9c3aee 6181
6304cd91
VS		 6182 /*
6183 * On gen2 planes are double buffered but the pipe isn't, so we must
6184 * wait for planes to fully turn off before disabling the pipe.
6185 */
90e83e53
ACO		 6186 if (IS_GEN2(dev))
6187 intel_wait_for_vblank(dev, pipe);
6304cd91 6188
4b3a9526
VS		 6189 for_each_encoder_on_crtc(dev, crtc, encoder)
6190 encoder->disable(encoder);
6191
f9b61ff6
DV		 6192 drm_crtc_vblank_off(crtc);
6193 assert_vblank_disabled(crtc);
6194
575f7ab7 6195 intel_disable_pipe(intel_crtc);
24a1f16d 6196
87476d63 6197 i9xx_pfit_disable(intel_crtc);
24a1f16d 6198
89b667f8
JB		 6199 for_each_encoder_on_crtc(dev, crtc, encoder)
6200 if (encoder->post_disable)
6201 encoder->post_disable(encoder);
6202
a65347ba 6203 if (!intel_crtc->config->has_dsi_encoder) {
076ed3b2
CML		 6204 if (IS_CHERRYVIEW(dev))
6205 chv_disable_pll(dev_priv, pipe);
6206 else if (IS_VALLEYVIEW(dev))
6207 vlv_disable_pll(dev_priv, pipe);
6208 else
1c4e0274 6209 i9xx_disable_pll(intel_crtc);
076ed3b2 6210 }
0b8765c6 6211
d6db995f
VS		 6212 for_each_encoder_on_crtc(dev, crtc, encoder)
6213 if (encoder->post_pll_disable)
6214 encoder->post_pll_disable(encoder);
6215
4a3436e8 6216 if (!IS_GEN2(dev))
a72e4c9f 6217 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
0b8765c6
JB		 6218}
6219
b17d48e2
ML		 6220static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6221{
842e0307 6222 struct intel_encoder *encoder;
b17d48e2
ML		 6223 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6224 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6225 enum intel_display_power_domain domain;
6226 unsigned long domains;
6227
6228 if (!intel_crtc->active)
6229 return;
6230
a539205a 6231 if (to_intel_plane_state(crtc->primary->state)->visible) {
fc32b1fd
ML		 6232 WARN_ON(intel_crtc->unpin_work);
6233
2622a081 6234 intel_pre_disable_primary_noatomic(crtc);
54a41961
ML		 6235
6236 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6237 to_intel_plane_state(crtc->primary->state)->visible = false;
a539205a
ML		 6238 }
6239
b17d48e2 6240 dev_priv->display.crtc_disable(crtc);
842e0307
ML		 6241
6242 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was enabled, now disabled\n",
6243 crtc->base.id);
6244
6245 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6246 crtc->state->active = false;
37d9078b 6247 intel_crtc->active = false;
842e0307
ML		 6248 crtc->enabled = false;
6249 crtc->state->connector_mask = 0;
6250 crtc->state->encoder_mask = 0;
6251
6252 for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6253 encoder->base.crtc = NULL;
6254
58f9c0bc 6255 intel_fbc_disable(intel_crtc);
37d9078b 6256 intel_update_watermarks(crtc);
1f7457b1 6257 intel_disable_shared_dpll(intel_crtc);
b17d48e2
ML		 6258
6259 domains = intel_crtc->enabled_power_domains;
6260 for_each_power_domain(domain, domains)
6261 intel_display_power_put(dev_priv, domain);
6262 intel_crtc->enabled_power_domains = 0;
565602d7
ML		 6263
6264 dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6265 dev_priv->min_pixclk[intel_crtc->pipe] = 0;
b17d48e2
ML		 6266}
6267
6b72d486
ML		 6268/*
6269 * turn all crtc's off, but do not adjust state
6270 * This has to be paired with a call to intel_modeset_setup_hw_state.
6271 */
70e0bd74 6272int intel_display_suspend(struct drm_device *dev)
ee7b9f93 6273{
e2c8b870 6274 struct drm_i915_private *dev_priv = to_i915(dev);
70e0bd74 6275 struct drm_atomic_state *state;
e2c8b870 6276 int ret;
70e0bd74 6277
e2c8b870
ML		 6278 state = drm_atomic_helper_suspend(dev);
6279 ret = PTR_ERR_OR_ZERO(state);
70e0bd74
ML		 6280 if (ret)
6281 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
e2c8b870
ML		 6282 else
6283 dev_priv->modeset_restore_state = state;
70e0bd74 6284 return ret;
ee7b9f93
JB		 6285}
6286
ea5b213a 6287void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 6288{
4ef69c7a 6289 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 6290
ea5b213a
CW		 6291 drm_encoder_cleanup(encoder);
6292 kfree(intel_encoder);
7e7d76c3
JB		 6293}
6294
0a91ca29
DV		 6295/* Cross check the actual hw state with our own modeset state tracking (and it's
6296 * internal consistency). */
b980514c 6297static void intel_connector_check_state(struct intel_connector *connector)
79e53945 6298{
35dd3c64
ML		 6299 struct drm_crtc *crtc = connector->base.state->crtc;
6300
6301 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6302 connector->base.base.id,
6303 connector->base.name);
6304
0a91ca29 6305 if (connector->get_hw_state(connector)) {
e85376cb 6306 struct intel_encoder *encoder = connector->encoder;
35dd3c64 6307 struct drm_connector_state *conn_state = connector->base.state;
0a91ca29 6308
35dd3c64
ML		 6309 I915_STATE_WARN(!crtc,
6310 "connector enabled without attached crtc\n");
0a91ca29 6311
35dd3c64
ML		 6312 if (!crtc)
6313 return;
6314
6315 I915_STATE_WARN(!crtc->state->active,
6316 "connector is active, but attached crtc isn't\n");
6317
e85376cb 6318 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
35dd3c64
ML		 6319 return;
6320
e85376cb 6321 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
35dd3c64
ML		 6322 "atomic encoder doesn't match attached encoder\n");
6323
e85376cb 6324 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
35dd3c64
ML		 6325 "attached encoder crtc differs from connector crtc\n");
6326 } else {
4d688a2a
ML		 6327 I915_STATE_WARN(crtc && crtc->state->active,
6328 "attached crtc is active, but connector isn't\n");
35dd3c64
ML		 6329 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6330 "best encoder set without crtc!\n");
0a91ca29 6331 }
79e53945
JB		 6332}
6333
08d9bc92
ACO		 6334int intel_connector_init(struct intel_connector *connector)
6335{
5350a031 6336 drm_atomic_helper_connector_reset(&connector->base);
08d9bc92 6337
5350a031 6338 if (!connector->base.state)
08d9bc92
ACO		 6339 return -ENOMEM;
6340
08d9bc92
ACO		 6341 return 0;
6342}
6343
6344struct intel_connector *intel_connector_alloc(void)
6345{
6346 struct intel_connector *connector;
6347
6348 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6349 if (!connector)
6350 return NULL;
6351
6352 if (intel_connector_init(connector) < 0) {
6353 kfree(connector);
6354 return NULL;
6355 }
6356
6357 return connector;
6358}
6359
f0947c37
DV		 6360/* Simple connector->get_hw_state implementation for encoders that support only
6361 * one connector and no cloning and hence the encoder state determines the state
6362 * of the connector. */
6363bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 6364{
24929352 6365 enum pipe pipe = 0;
f0947c37 6366 struct intel_encoder *encoder = connector->encoder;
ea5b213a 6367
f0947c37 6368 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 6369}
6370
6d293983 6371static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
d272ddfa 6372{
6d293983
ACO		 6373 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6374 return crtc_state->fdi_lanes;
d272ddfa
VS		 6375
6376 return 0;
6377}
6378
6d293983 6379static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5cec258b 6380 struct intel_crtc_state *pipe_config)
1857e1da 6381{
6d293983
ACO		 6382 struct drm_atomic_state *state = pipe_config->base.state;
6383 struct intel_crtc *other_crtc;
6384 struct intel_crtc_state *other_crtc_state;
6385
1857e1da
DV		 6386 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6387 pipe_name(pipe), pipe_config->fdi_lanes);
6388 if (pipe_config->fdi_lanes > 4) {
6389 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6390 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6391 return -EINVAL;
1857e1da
DV		 6392 }
6393
bafb6553 6394 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1857e1da
DV		 6395 if (pipe_config->fdi_lanes > 2) {
6396 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6397 pipe_config->fdi_lanes);
6d293983 6398 return -EINVAL;
1857e1da 6399 } else {
6d293983 6400 return 0;
1857e1da
DV		 6401 }
6402 }
6403
6404 if (INTEL_INFO(dev)->num_pipes == 2)
6d293983 6405 return 0;
1857e1da
DV		 6406
6407 /* Ivybridge 3 pipe is really complicated */
6408 switch (pipe) {
6409 case PIPE_A:
6d293983 6410 return 0;
1857e1da 6411 case PIPE_B:
6d293983
ACO		 6412 if (pipe_config->fdi_lanes <= 2)
6413 return 0;
6414
6415 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6416 other_crtc_state =
6417 intel_atomic_get_crtc_state(state, other_crtc);
6418 if (IS_ERR(other_crtc_state))
6419 return PTR_ERR(other_crtc_state);
6420
6421 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
1857e1da
DV		 6422 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6423 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6424 return -EINVAL;
1857e1da 6425 }
6d293983 6426 return 0;
1857e1da 6427 case PIPE_C:
251cc67c
VS		 6428 if (pipe_config->fdi_lanes > 2) {
6429 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6430 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6431 return -EINVAL;
251cc67c 6432 }
6d293983
ACO		 6433
6434 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6435 other_crtc_state =
6436 intel_atomic_get_crtc_state(state, other_crtc);
6437 if (IS_ERR(other_crtc_state))
6438 return PTR_ERR(other_crtc_state);
6439
6440 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
1857e1da 6441 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6d293983 6442 return -EINVAL;
1857e1da 6443 }
6d293983 6444 return 0;
1857e1da
DV		 6445 default:
6446 BUG();
6447 }
6448}
6449
e29c22c0
DV		 6450#define RETRY 1
6451static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5cec258b 6452 struct intel_crtc_state *pipe_config)
877d48d5 6453{
1857e1da 6454 struct drm_device *dev = intel_crtc->base.dev;
7c5f93b0 6455 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6d293983
ACO		 6456 int lane, link_bw, fdi_dotclock, ret;
6457 bool needs_recompute = false;
877d48d5 6458
e29c22c0 6459retry:
877d48d5
DV		 6460 /* FDI is a binary signal running at ~2.7GHz, encoding
6461 * each output octet as 10 bits. The actual frequency
6462 * is stored as a divider into a 100MHz clock, and the
6463 * mode pixel clock is stored in units of 1KHz.
6464 * Hence the bw of each lane in terms of the mode signal
6465 * is:
6466 */
21a727b3 6467 link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
877d48d5 6468
241bfc38 6469 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 6470
2bd89a07 6471 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 6472 pipe_config->pipe_bpp);
6473
6474 pipe_config->fdi_lanes = lane;
6475
2bd89a07 6476 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 6477 link_bw, &pipe_config->fdi_m_n);
1857e1da 6478
e3b247da 6479 ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6d293983 6480 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
e29c22c0
DV		 6481 pipe_config->pipe_bpp -= 2*3;
6482 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6483 pipe_config->pipe_bpp);
6484 needs_recompute = true;
6485 pipe_config->bw_constrained = true;
6486
6487 goto retry;
6488 }
6489
6490 if (needs_recompute)
6491 return RETRY;
6492
6d293983 6493 return ret;
877d48d5
DV		 6494}
6495
8cfb3407
VS		 6496static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6497 struct intel_crtc_state *pipe_config)
6498{
6499 if (pipe_config->pipe_bpp > 24)
6500 return false;
6501
6502 /* HSW can handle pixel rate up to cdclk? */
6503 if (IS_HASWELL(dev_priv->dev))
6504 return true;
6505
6506 /*
b432e5cf
VS		 6507 * We compare against max which means we must take
6508 * the increased cdclk requirement into account when
6509 * calculating the new cdclk.
6510 *
6511 * Should measure whether using a lower cdclk w/o IPS
8cfb3407
VS		 6512 */
6513 return ilk_pipe_pixel_rate(pipe_config) <=
6514 dev_priv->max_cdclk_freq * 95 / 100;
6515}
6516
42db64ef 6517static void hsw_compute_ips_config(struct intel_crtc *crtc,
5cec258b 6518 struct intel_crtc_state *pipe_config)
42db64ef 6519{
8cfb3407
VS		 6520 struct drm_device *dev = crtc->base.dev;
6521 struct drm_i915_private *dev_priv = dev->dev_private;
6522
d330a953 6523 pipe_config->ips_enabled = i915.enable_ips &&
8cfb3407
VS		 6524 hsw_crtc_supports_ips(crtc) &&
6525 pipe_config_supports_ips(dev_priv, pipe_config);
42db64ef
PZ		 6526}
6527
39acb4aa
VS		 6528static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6529{
6530 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6531
6532 /* GDG double wide on either pipe, otherwise pipe A only */
6533 return INTEL_INFO(dev_priv)->gen < 4 &&
6534 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6535}
6536
a43f6e0f 6537static int intel_crtc_compute_config(struct intel_crtc *crtc,
5cec258b 6538 struct intel_crtc_state *pipe_config)
79e53945 6539{
a43f6e0f 6540 struct drm_device *dev = crtc->base.dev;
8bd31e67 6541 struct drm_i915_private *dev_priv = dev->dev_private;
7c5f93b0 6542 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
89749350 6543
ad3a4479 6544 /* FIXME should check pixel clock limits on all platforms */
cf532bb2 6545 if (INTEL_INFO(dev)->gen < 4) {
39acb4aa 6546 int clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
cf532bb2
VS		 6547
6548 /*
39acb4aa 6549 * Enable double wide mode when the dot clock
cf532bb2 6550 * is > 90% of the (display) core speed.
cf532bb2 6551 */
39acb4aa
VS		 6552 if (intel_crtc_supports_double_wide(crtc) &&
6553 adjusted_mode->crtc_clock > clock_limit) {
ad3a4479 6554 clock_limit *= 2;
cf532bb2 6555 pipe_config->double_wide = true;
ad3a4479
VS		 6556 }
6557
39acb4aa
VS		 6558 if (adjusted_mode->crtc_clock > clock_limit) {
6559 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6560 adjusted_mode->crtc_clock, clock_limit,
6561 yesno(pipe_config->double_wide));
e29c22c0 6562 return -EINVAL;
39acb4aa 6563 }
2c07245f 6564 }
89749350 6565
1d1d0e27
VS		 6566 /*
6567 * Pipe horizontal size must be even in:
6568 * - DVO ganged mode
6569 * - LVDS dual channel mode
6570 * - Double wide pipe
6571 */
a93e255f 6572 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
1d1d0e27
VS		 6573 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6574 pipe_config->pipe_src_w &= ~1;
6575
8693a824
DL		 6576 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6577 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 6578 */
6579 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
aad941d5 6580 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
e29c22c0 6581 return -EINVAL;
44f46b42 6582
f5adf94e 6583 if (HAS_IPS(dev))
a43f6e0f
DV		 6584 hsw_compute_ips_config(crtc, pipe_config);
6585
877d48d5 6586 if (pipe_config->has_pch_encoder)
a43f6e0f 6587 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 6588
cf5a15be 6589 return 0;
79e53945
JB		 6590}
6591
1652d19e
VS		 6592static int skylake_get_display_clock_speed(struct drm_device *dev)
6593{
6594 struct drm_i915_private *dev_priv = to_i915(dev);
6595 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6596 uint32_t cdctl = I915_READ(CDCLK_CTL);
6597 uint32_t linkrate;
6598
414355a7 6599 if (!(lcpll1 & LCPLL_PLL_ENABLE))
1652d19e 6600 return 24000; /* 24MHz is the cd freq with NSSC ref */
1652d19e
VS		 6601
6602 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6603 return 540000;
6604
6605 linkrate = (I915_READ(DPLL_CTRL1) &
71cd8423 6606 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
1652d19e 6607
71cd8423
DL		 6608 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6609 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
1652d19e
VS		 6610 /* vco 8640 */
6611 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6612 case CDCLK_FREQ_450_432:
6613 return 432000;
6614 case CDCLK_FREQ_337_308:
6615 return 308570;
6616 case CDCLK_FREQ_675_617:
6617 return 617140;
6618 default:
6619 WARN(1, "Unknown cd freq selection\n");
6620 }
6621 } else {
6622 /* vco 8100 */
6623 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6624 case CDCLK_FREQ_450_432:
6625 return 450000;
6626 case CDCLK_FREQ_337_308:
6627 return 337500;
6628 case CDCLK_FREQ_675_617:
6629 return 675000;
6630 default:
6631 WARN(1, "Unknown cd freq selection\n");
6632 }
6633 }
6634
6635 /* error case, do as if DPLL0 isn't enabled */
6636 return 24000;
6637}
6638
acd3f3d3
BP		 6639static int broxton_get_display_clock_speed(struct drm_device *dev)
6640{
6641 struct drm_i915_private *dev_priv = to_i915(dev);
6642 uint32_t cdctl = I915_READ(CDCLK_CTL);
6643 uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6644 uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6645 int cdclk;
6646
6647 if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6648 return 19200;
6649
6650 cdclk = 19200 * pll_ratio / 2;
6651
6652 switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6653 case BXT_CDCLK_CD2X_DIV_SEL_1:
6654 return cdclk; /* 576MHz or 624MHz */
6655 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6656 return cdclk * 2 / 3; /* 384MHz */
6657 case BXT_CDCLK_CD2X_DIV_SEL_2:
6658 return cdclk / 2; /* 288MHz */
6659 case BXT_CDCLK_CD2X_DIV_SEL_4:
6660 return cdclk / 4; /* 144MHz */
6661 }
6662
6663 /* error case, do as if DE PLL isn't enabled */
6664 return 19200;
6665}
6666
1652d19e
VS		 6667static int broadwell_get_display_clock_speed(struct drm_device *dev)
6668{
6669 struct drm_i915_private *dev_priv = dev->dev_private;
6670 uint32_t lcpll = I915_READ(LCPLL_CTL);
6671 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6672
6673 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6674 return 800000;
6675 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6676 return 450000;
6677 else if (freq == LCPLL_CLK_FREQ_450)
6678 return 450000;
6679 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6680 return 540000;
6681 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6682 return 337500;
6683 else
6684 return 675000;
6685}
6686
6687static int haswell_get_display_clock_speed(struct drm_device *dev)
6688{
6689 struct drm_i915_private *dev_priv = dev->dev_private;
6690 uint32_t lcpll = I915_READ(LCPLL_CTL);
6691 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6692
6693 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6694 return 800000;
6695 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6696 return 450000;
6697 else if (freq == LCPLL_CLK_FREQ_450)
6698 return 450000;
6699 else if (IS_HSW_ULT(dev))
6700 return 337500;
6701 else
6702 return 540000;
79e53945
JB		 6703}
6704
25eb05fc
JB		 6705static int valleyview_get_display_clock_speed(struct drm_device *dev)
6706{
bfa7df01
VS		 6707 return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6708 CCK_DISPLAY_CLOCK_CONTROL);
25eb05fc
JB		 6709}
6710
b37a6434
VS		 6711static int ilk_get_display_clock_speed(struct drm_device *dev)
6712{
6713 return 450000;
6714}
6715
e70236a8
JB		 6716static int i945_get_display_clock_speed(struct drm_device *dev)
6717{
6718 return 400000;
6719}
79e53945 6720
e70236a8 6721static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 6722{
e907f170 6723 return 333333;
e70236a8 6724}
79e53945 6725
e70236a8
JB		 6726static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6727{
6728 return 200000;
6729}
79e53945 6730
257a7ffc
DV		 6731static int pnv_get_display_clock_speed(struct drm_device *dev)
6732{
6733 u16 gcfgc = 0;
6734
6735 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6736
6737 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6738 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
e907f170 6739 return 266667;
257a7ffc 6740 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
e907f170 6741 return 333333;
257a7ffc 6742 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
e907f170 6743 return 444444;
257a7ffc
DV		 6744 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6745 return 200000;
6746 default:
6747 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6748 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
e907f170 6749 return 133333;
257a7ffc 6750 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
e907f170 6751 return 166667;
257a7ffc
DV		 6752 }
6753}
6754
e70236a8
JB		 6755static int i915gm_get_display_clock_speed(struct drm_device *dev)
6756{
6757 u16 gcfgc = 0;
79e53945 6758
e70236a8
JB		 6759 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6760
6761 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
e907f170 6762 return 133333;
e70236a8
JB		 6763 else {
6764 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6765 case GC_DISPLAY_CLOCK_333_MHZ:
e907f170 6766 return 333333;
e70236a8
JB		 6767 default:
6768 case GC_DISPLAY_CLOCK_190_200_MHZ:
6769 return 190000;
79e53945 6770 }
e70236a8
JB		 6771 }
6772}
6773
6774static int i865_get_display_clock_speed(struct drm_device *dev)
6775{
e907f170 6776 return 266667;
e70236a8
JB		 6777}
6778
1b1d2716 6779static int i85x_get_display_clock_speed(struct drm_device *dev)
e70236a8
JB		 6780{
6781 u16 hpllcc = 0;
1b1d2716 6782
65cd2b3f
VS		 6783 /*
6784 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6785 * encoding is different :(
6786 * FIXME is this the right way to detect 852GM/852GMV?
6787 */
6788 if (dev->pdev->revision == 0x1)
6789 return 133333;
6790
1b1d2716
VS		 6791 pci_bus_read_config_word(dev->pdev->bus,
6792 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6793
e70236a8
JB		 6794 /* Assume that the hardware is in the high speed state. This
6795 * should be the default.
6796 */
6797 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6798 case GC_CLOCK_133_200:
1b1d2716 6799 case GC_CLOCK_133_200_2:
e70236a8
JB		 6800 case GC_CLOCK_100_200:
6801 return 200000;
6802 case GC_CLOCK_166_250:
6803 return 250000;
6804 case GC_CLOCK_100_133:
e907f170 6805 return 133333;
1b1d2716
VS		 6806 case GC_CLOCK_133_266:
6807 case GC_CLOCK_133_266_2:
6808 case GC_CLOCK_166_266:
6809 return 266667;
e70236a8 6810 }
79e53945 6811
e70236a8
JB		 6812 /* Shouldn't happen */
6813 return 0;
6814}
79e53945 6815
e70236a8
JB		 6816static int i830_get_display_clock_speed(struct drm_device *dev)
6817{
e907f170 6818 return 133333;
79e53945
JB		 6819}
6820
34edce2f
VS		 6821static unsigned int intel_hpll_vco(struct drm_device *dev)
6822{
6823 struct drm_i915_private *dev_priv = dev->dev_private;
6824 static const unsigned int blb_vco[8] = {
6825 [0] = 3200000,
6826 [1] = 4000000,
6827 [2] = 5333333,
6828 [3] = 4800000,
6829 [4] = 6400000,
6830 };
6831 static const unsigned int pnv_vco[8] = {
6832 [0] = 3200000,
6833 [1] = 4000000,
6834 [2] = 5333333,
6835 [3] = 4800000,
6836 [4] = 2666667,
6837 };
6838 static const unsigned int cl_vco[8] = {
6839 [0] = 3200000,
6840 [1] = 4000000,
6841 [2] = 5333333,
6842 [3] = 6400000,
6843 [4] = 3333333,
6844 [5] = 3566667,
6845 [6] = 4266667,
6846 };
6847 static const unsigned int elk_vco[8] = {
6848 [0] = 3200000,
6849 [1] = 4000000,
6850 [2] = 5333333,
6851 [3] = 4800000,
6852 };
6853 static const unsigned int ctg_vco[8] = {
6854 [0] = 3200000,
6855 [1] = 4000000,
6856 [2] = 5333333,
6857 [3] = 6400000,
6858 [4] = 2666667,
6859 [5] = 4266667,
6860 };
6861 const unsigned int *vco_table;
6862 unsigned int vco;
6863 uint8_t tmp = 0;
6864
6865 /* FIXME other chipsets? */
6866 if (IS_GM45(dev))
6867 vco_table = ctg_vco;
6868 else if (IS_G4X(dev))
6869 vco_table = elk_vco;
6870 else if (IS_CRESTLINE(dev))
6871 vco_table = cl_vco;
6872 else if (IS_PINEVIEW(dev))
6873 vco_table = pnv_vco;
6874 else if (IS_G33(dev))
6875 vco_table = blb_vco;
6876 else
6877 return 0;
6878
6879 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6880
6881 vco = vco_table[tmp & 0x7];
6882 if (vco == 0)
6883 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6884 else
6885 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6886
6887 return vco;
6888}
6889
6890static int gm45_get_display_clock_speed(struct drm_device *dev)
6891{
6892 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6893 uint16_t tmp = 0;
6894
6895 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6896
6897 cdclk_sel = (tmp >> 12) & 0x1;
6898
6899 switch (vco) {
6900 case 2666667:
6901 case 4000000:
6902 case 5333333:
6903 return cdclk_sel ? 333333 : 222222;
6904 case 3200000:
6905 return cdclk_sel ? 320000 : 228571;
6906 default:
6907 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6908 return 222222;
6909 }
6910}
6911
6912static int i965gm_get_display_clock_speed(struct drm_device *dev)
6913{
6914 static const uint8_t div_3200[] = { 16, 10, 8 };
6915 static const uint8_t div_4000[] = { 20, 12, 10 };
6916 static const uint8_t div_5333[] = { 24, 16, 14 };
6917 const uint8_t *div_table;
6918 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6919 uint16_t tmp = 0;
6920
6921 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6922
6923 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6924
6925 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6926 goto fail;
6927
6928 switch (vco) {
6929 case 3200000:
6930 div_table = div_3200;
6931 break;
6932 case 4000000:
6933 div_table = div_4000;
6934 break;
6935 case 5333333:
6936 div_table = div_5333;
6937 break;
6938 default:
6939 goto fail;
6940 }
6941
6942 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6943
caf4e252 6944fail:
34edce2f
VS		 6945 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6946 return 200000;
6947}
6948
6949static int g33_get_display_clock_speed(struct drm_device *dev)
6950{
6951 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
6952 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
6953 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6954 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6955 const uint8_t *div_table;
6956 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6957 uint16_t tmp = 0;
6958
6959 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6960
6961 cdclk_sel = (tmp >> 4) & 0x7;
6962
6963 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6964 goto fail;
6965
6966 switch (vco) {
6967 case 3200000:
6968 div_table = div_3200;
6969 break;
6970 case 4000000:
6971 div_table = div_4000;
6972 break;
6973 case 4800000:
6974 div_table = div_4800;
6975 break;
6976 case 5333333:
6977 div_table = div_5333;
6978 break;
6979 default:
6980 goto fail;
6981 }
6982
6983 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6984
caf4e252 6985fail:
34edce2f
VS		 6986 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
6987 return 190476;
6988}
6989
2c07245f 6990static void
a65851af 6991intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 6992{
a65851af
VS		 6993 while (*num > DATA_LINK_M_N_MASK ||
6994 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 6995 *num >>= 1;
6996 *den >>= 1;
6997 }
6998}
6999
a65851af
VS		 7000static void compute_m_n(unsigned int m, unsigned int n,
7001 uint32_t *ret_m, uint32_t *ret_n)
7002{
7003 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7004 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7005 intel_reduce_m_n_ratio(ret_m, ret_n);
7006}
7007
e69d0bc1
DV		 7008void
7009intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7010 int pixel_clock, int link_clock,
7011 struct intel_link_m_n *m_n)
2c07245f 7012{
e69d0bc1 7013 m_n->tu = 64;
a65851af
VS		 7014
7015 compute_m_n(bits_per_pixel * pixel_clock,
7016 link_clock * nlanes * 8,
7017 &m_n->gmch_m, &m_n->gmch_n);
7018
7019 compute_m_n(pixel_clock, link_clock,
7020 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 7021}
7022
a7615030
CW		 7023static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7024{
d330a953
JN		 7025 if (i915.panel_use_ssc >= 0)
7026 return i915.panel_use_ssc != 0;
41aa3448 7027 return dev_priv->vbt.lvds_use_ssc
435793df 7028 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 7029}
7030
7429e9d4 7031static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 7032{
7df00d7a 7033 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 7034}
f47709a9 7035
7429e9d4
DV		 7036static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7037{
7038 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 7039}
7040
f47709a9 7041static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
190f68c5 7042 struct intel_crtc_state *crtc_state,
a7516a05
JB		 7043 intel_clock_t *reduced_clock)
7044{
f47709a9 7045 struct drm_device *dev = crtc->base.dev;
a7516a05
JB		 7046 u32 fp, fp2 = 0;
7047
7048 if (IS_PINEVIEW(dev)) {
190f68c5 7049 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7050 if (reduced_clock)
7429e9d4 7051 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 7052 } else {
190f68c5 7053 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7054 if (reduced_clock)
7429e9d4 7055 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 7056 }
7057
190f68c5 7058 crtc_state->dpll_hw_state.fp0 = fp;
a7516a05 7059
f47709a9 7060 crtc->lowfreq_avail = false;
a93e255f 7061 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
ab585dea 7062 reduced_clock) {
190f68c5 7063 crtc_state->dpll_hw_state.fp1 = fp2;
f47709a9 7064 crtc->lowfreq_avail = true;
a7516a05 7065 } else {
190f68c5 7066 crtc_state->dpll_hw_state.fp1 = fp;
a7516a05
JB		 7067 }
7068}
7069
5e69f97f
CML		 7070static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7071 pipe)
89b667f8
JB		 7072{
7073 u32 reg_val;
7074
7075 /*
7076 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7077 * and set it to a reasonable value instead.
7078 */
ab3c759a 7079 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8
JB		 7080 reg_val &= 0xffffff00;
7081 reg_val |= 0x00000030;
ab3c759a 7082 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7083
ab3c759a 7084 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 7085 reg_val &= 0x8cffffff;
7086 reg_val = 0x8c000000;
ab3c759a 7087 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8 7088
ab3c759a 7089 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8 7090 reg_val &= 0xffffff00;
ab3c759a 7091 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7092
ab3c759a 7093 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 7094 reg_val &= 0x00ffffff;
7095 reg_val |= 0xb0000000;
ab3c759a 7096 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8
JB		 7097}
7098
b551842d
DV		 7099static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7100 struct intel_link_m_n *m_n)
7101{
7102 struct drm_device *dev = crtc->base.dev;
7103 struct drm_i915_private *dev_priv = dev->dev_private;
7104 int pipe = crtc->pipe;
7105
e3b95f1e
DV		 7106 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7107 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7108 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7109 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 7110}
7111
7112static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 7113 struct intel_link_m_n *m_n,
7114 struct intel_link_m_n *m2_n2)
b551842d
DV		 7115{
7116 struct drm_device *dev = crtc->base.dev;
7117 struct drm_i915_private *dev_priv = dev->dev_private;
7118 int pipe = crtc->pipe;
6e3c9717 7119 enum transcoder transcoder = crtc->config->cpu_transcoder;
b551842d
DV		 7120
7121 if (INTEL_INFO(dev)->gen >= 5) {
7122 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7123 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7124 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7125 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
f769cd24
VK		 7126 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7127 * for gen < 8) and if DRRS is supported (to make sure the
7128 * registers are not unnecessarily accessed).
7129 */
44395bfe 7130 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6e3c9717 7131 crtc->config->has_drrs) {
f769cd24
VK		 7132 I915_WRITE(PIPE_DATA_M2(transcoder),
7133 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7134 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7135 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7136 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7137 }
b551842d 7138 } else {
e3b95f1e
DV		 7139 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7140 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7141 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7142 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 7143 }
7144}
7145
fe3cd48d 7146void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
03afc4a2 7147{
fe3cd48d
R		 7148 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7149
7150 if (m_n == M1_N1) {
7151 dp_m_n = &crtc->config->dp_m_n;
7152 dp_m2_n2 = &crtc->config->dp_m2_n2;
7153 } else if (m_n == M2_N2) {
7154
7155 /*
7156 * M2_N2 registers are not supported. Hence m2_n2 divider value
7157 * needs to be programmed into M1_N1.
7158 */
7159 dp_m_n = &crtc->config->dp_m2_n2;
7160 } else {
7161 DRM_ERROR("Unsupported divider value\n");
7162 return;
7163 }
7164
6e3c9717
ACO		 7165 if (crtc->config->has_pch_encoder)
7166 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
03afc4a2 7167 else
fe3cd48d 7168 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
03afc4a2
DV		 7169}
7170
251ac862
DV		 7171static void vlv_compute_dpll(struct intel_crtc *crtc,
7172 struct intel_crtc_state *pipe_config)
bdd4b6a6 7173{
03ed5cbf
VS		 7174 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
7175 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7176 DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV;
7177 if (crtc->pipe != PIPE_A)
7178 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
bdd4b6a6 7179
03ed5cbf
VS		 7180 pipe_config->dpll_hw_state.dpll_md =
7181 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7182}
bdd4b6a6 7183
03ed5cbf
VS		 7184static void chv_compute_dpll(struct intel_crtc *crtc,
7185 struct intel_crtc_state *pipe_config)
7186{
7187 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7188 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7189 DPLL_VCO_ENABLE;
7190 if (crtc->pipe != PIPE_A)
7191 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7192
7193 pipe_config->dpll_hw_state.dpll_md =
7194 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
bdd4b6a6
DV		 7195}
7196
d288f65f 7197static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7198 const struct intel_crtc_state *pipe_config)
a0c4da24 7199{
f47709a9 7200 struct drm_device *dev = crtc->base.dev;
a0c4da24 7201 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 7202 int pipe = crtc->pipe;
bdd4b6a6 7203 u32 mdiv;
a0c4da24 7204 u32 bestn, bestm1, bestm2, bestp1, bestp2;
bdd4b6a6 7205 u32 coreclk, reg_val;
a0c4da24 7206
a580516d 7207 mutex_lock(&dev_priv->sb_lock);
09153000 7208
d288f65f
VS		 7209 bestn = pipe_config->dpll.n;
7210 bestm1 = pipe_config->dpll.m1;
7211 bestm2 = pipe_config->dpll.m2;
7212 bestp1 = pipe_config->dpll.p1;
7213 bestp2 = pipe_config->dpll.p2;
a0c4da24 7214
89b667f8
JB		 7215 /* See eDP HDMI DPIO driver vbios notes doc */
7216
7217 /* PLL B needs special handling */
bdd4b6a6 7218 if (pipe == PIPE_B)
5e69f97f 7219 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 7220
7221 /* Set up Tx target for periodic Rcomp update */
ab3c759a 7222 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
89b667f8
JB		 7223
7224 /* Disable target IRef on PLL */
ab3c759a 7225 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
89b667f8 7226 reg_val &= 0x00ffffff;
ab3c759a 7227 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
89b667f8
JB		 7228
7229 /* Disable fast lock */
ab3c759a 7230 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
89b667f8
JB		 7231
7232 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 7233 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7234 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7235 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 7236 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 7237
7238 /*
7239 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7240 * but we don't support that).
7241 * Note: don't use the DAC post divider as it seems unstable.
7242 */
7243 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ab3c759a 7244 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7245
a0c4da24 7246 mdiv |= DPIO_ENABLE_CALIBRATION;
ab3c759a 7247 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7248
89b667f8 7249 /* Set HBR and RBR LPF coefficients */
d288f65f 7250 if (pipe_config->port_clock == 162000 ||
409ee761
ACO		 7251 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7252 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
ab3c759a 7253 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
885b0120 7254 0x009f0003);
89b667f8 7255 else
ab3c759a 7256 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
89b667f8
JB		 7257 0x00d0000f);
7258
681a8504 7259 if (pipe_config->has_dp_encoder) {
89b667f8 7260 /* Use SSC source */
bdd4b6a6 7261 if (pipe == PIPE_A)
ab3c759a 7262 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7263 0x0df40000);
7264 else
ab3c759a 7265 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7266 0x0df70000);
7267 } else { /* HDMI or VGA */
7268 /* Use bend source */
bdd4b6a6 7269 if (pipe == PIPE_A)
ab3c759a 7270 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7271 0x0df70000);
7272 else
ab3c759a 7273 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7274 0x0df40000);
7275 }
a0c4da24 7276
ab3c759a 7277 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
89b667f8 7278 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
409ee761
ACO		 7279 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7280 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
89b667f8 7281 coreclk |= 0x01000000;
ab3c759a 7282 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
a0c4da24 7283
ab3c759a 7284 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
a580516d 7285 mutex_unlock(&dev_priv->sb_lock);
a0c4da24
JB		 7286}
7287
d288f65f 7288static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7289 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 7290{
7291 struct drm_device *dev = crtc->base.dev;
7292 struct drm_i915_private *dev_priv = dev->dev_private;
7293 int pipe = crtc->pipe;
f0f59a00 7294 i915_reg_t dpll_reg = DPLL(crtc->pipe);
9d556c99 7295 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9cbe40c1 7296 u32 loopfilter, tribuf_calcntr;
9d556c99 7297 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
a945ce7e 7298 u32 dpio_val;
9cbe40c1 7299 int vco;
9d556c99 7300
d288f65f
VS		 7301 bestn = pipe_config->dpll.n;
7302 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7303 bestm1 = pipe_config->dpll.m1;
7304 bestm2 = pipe_config->dpll.m2 >> 22;
7305 bestp1 = pipe_config->dpll.p1;
7306 bestp2 = pipe_config->dpll.p2;
9cbe40c1 7307 vco = pipe_config->dpll.vco;
a945ce7e 7308 dpio_val = 0;
9cbe40c1 7309 loopfilter = 0;
9d556c99
CML		 7310
7311 /*
7312 * Enable Refclk and SSC
7313 */
a11b0703 7314 I915_WRITE(dpll_reg,
d288f65f 7315 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
a11b0703 7316
a580516d 7317 mutex_lock(&dev_priv->sb_lock);
9d556c99 7318
9d556c99
CML		 7319 /* p1 and p2 divider */
7320 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7321 5 << DPIO_CHV_S1_DIV_SHIFT |
7322 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7323 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7324 1 << DPIO_CHV_K_DIV_SHIFT);
7325
7326 /* Feedback post-divider - m2 */
7327 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7328
7329 /* Feedback refclk divider - n and m1 */
7330 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7331 DPIO_CHV_M1_DIV_BY_2 |
7332 1 << DPIO_CHV_N_DIV_SHIFT);
7333
7334 /* M2 fraction division */
25a25dfc 7335 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
9d556c99
CML		 7336
7337 /* M2 fraction division enable */
a945ce7e
VP		 7338 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7339 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7340 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7341 if (bestm2_frac)
7342 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7343 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
9d556c99 7344
de3a0fde
VP		 7345 /* Program digital lock detect threshold */
7346 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7347 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7348 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7349 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7350 if (!bestm2_frac)
7351 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7352 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7353
9d556c99 7354 /* Loop filter */
9cbe40c1
VP		 7355 if (vco == 5400000) {
7356 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7357 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7358 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7359 tribuf_calcntr = 0x9;
7360 } else if (vco <= 6200000) {
7361 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7362 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7363 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7364 tribuf_calcntr = 0x9;
7365 } else if (vco <= 6480000) {
7366 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7367 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7368 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7369 tribuf_calcntr = 0x8;
7370 } else {
7371 /* Not supported. Apply the same limits as in the max case */
7372 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7373 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7374 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7375 tribuf_calcntr = 0;
7376 }
9d556c99
CML		 7377 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7378
968040b2 7379 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
9cbe40c1
VP		 7380 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7381 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7382 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7383
9d556c99
CML		 7384 /* AFC Recal */
7385 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7386 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7387 DPIO_AFC_RECAL);
7388
a580516d 7389 mutex_unlock(&dev_priv->sb_lock);
9d556c99
CML		 7390}
7391
d288f65f
VS		 7392/**
7393 * vlv_force_pll_on - forcibly enable just the PLL
7394 * @dev_priv: i915 private structure
7395 * @pipe: pipe PLL to enable
7396 * @dpll: PLL configuration
7397 *
7398 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7399 * in cases where we need the PLL enabled even when @pipe is not going to
7400 * be enabled.
7401 */
3f36b937
TU		 7402int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7403 const struct dpll *dpll)
d288f65f
VS		 7404{
7405 struct intel_crtc *crtc =
7406 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
3f36b937
TU		 7407 struct intel_crtc_state *pipe_config;
7408
7409 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7410 if (!pipe_config)
7411 return -ENOMEM;
7412
7413 pipe_config->base.crtc = &crtc->base;
7414 pipe_config->pixel_multiplier = 1;
7415 pipe_config->dpll = *dpll;
d288f65f
VS		 7416
7417 if (IS_CHERRYVIEW(dev)) {
3f36b937
TU		 7418 chv_compute_dpll(crtc, pipe_config);
7419 chv_prepare_pll(crtc, pipe_config);
7420 chv_enable_pll(crtc, pipe_config);
d288f65f 7421 } else {
3f36b937
TU		 7422 vlv_compute_dpll(crtc, pipe_config);
7423 vlv_prepare_pll(crtc, pipe_config);
7424 vlv_enable_pll(crtc, pipe_config);
d288f65f 7425 }
3f36b937
TU		 7426
7427 kfree(pipe_config);
7428
7429 return 0;
d288f65f
VS		 7430}
7431
7432/**
7433 * vlv_force_pll_off - forcibly disable just the PLL
7434 * @dev_priv: i915 private structure
7435 * @pipe: pipe PLL to disable
7436 *
7437 * Disable the PLL for @pipe. To be used in cases where we need
7438 * the PLL enabled even when @pipe is not going to be enabled.
7439 */
7440void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7441{
7442 if (IS_CHERRYVIEW(dev))
7443 chv_disable_pll(to_i915(dev), pipe);
7444 else
7445 vlv_disable_pll(to_i915(dev), pipe);
7446}
7447
251ac862
DV		 7448static void i9xx_compute_dpll(struct intel_crtc *crtc,
7449 struct intel_crtc_state *crtc_state,
ceb41007 7450 intel_clock_t *reduced_clock)
eb1cbe48 7451{
f47709a9 7452 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7453 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 7454 u32 dpll;
7455 bool is_sdvo;
190f68c5 7456 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7457
190f68c5 7458 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7459
a93e255f
ACO		 7460 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7461 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 7462
7463 dpll = DPLL_VGA_MODE_DIS;
7464
a93e255f 7465 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 7466 dpll |= DPLLB_MODE_LVDS;
7467 else
7468 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 7469
ef1b460d 7470 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
190f68c5 7471 dpll |= (crtc_state->pixel_multiplier - 1)
198a037f 7472 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 7473 }
198a037f
DV		 7474
7475 if (is_sdvo)
4a33e48d 7476 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 7477
190f68c5 7478 if (crtc_state->has_dp_encoder)
4a33e48d 7479 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 7480
7481 /* compute bitmask from p1 value */
7482 if (IS_PINEVIEW(dev))
7483 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7484 else {
7485 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7486 if (IS_G4X(dev) && reduced_clock)
7487 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7488 }
7489 switch (clock->p2) {
7490 case 5:
7491 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7492 break;
7493 case 7:
7494 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7495 break;
7496 case 10:
7497 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7498 break;
7499 case 14:
7500 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7501 break;
7502 }
7503 if (INTEL_INFO(dev)->gen >= 4)
7504 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7505
190f68c5 7506 if (crtc_state->sdvo_tv_clock)
eb1cbe48 7507 dpll |= PLL_REF_INPUT_TVCLKINBC;
a93e255f 7508 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
ceb41007 7509 intel_panel_use_ssc(dev_priv))
eb1cbe48
DV		 7510 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7511 else
7512 dpll |= PLL_REF_INPUT_DREFCLK;
7513
7514 dpll |= DPLL_VCO_ENABLE;
190f68c5 7515 crtc_state->dpll_hw_state.dpll = dpll;
8bcc2795 7516
eb1cbe48 7517 if (INTEL_INFO(dev)->gen >= 4) {
190f68c5 7518 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
ef1b460d 7519 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
190f68c5 7520 crtc_state->dpll_hw_state.dpll_md = dpll_md;
eb1cbe48
DV		 7521 }
7522}
7523
251ac862
DV		 7524static void i8xx_compute_dpll(struct intel_crtc *crtc,
7525 struct intel_crtc_state *crtc_state,
ceb41007 7526 intel_clock_t *reduced_clock)
eb1cbe48 7527{
f47709a9 7528 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7529 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 7530 u32 dpll;
190f68c5 7531 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7532
190f68c5 7533 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7534
eb1cbe48
DV		 7535 dpll = DPLL_VGA_MODE_DIS;
7536
a93e255f 7537 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 7538 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7539 } else {
7540 if (clock->p1 == 2)
7541 dpll |= PLL_P1_DIVIDE_BY_TWO;
7542 else
7543 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7544 if (clock->p2 == 4)
7545 dpll |= PLL_P2_DIVIDE_BY_4;
7546 }
7547
a93e255f 7548 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
4a33e48d
DV		 7549 dpll |= DPLL_DVO_2X_MODE;
7550
a93e255f 7551 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
ceb41007 7552 intel_panel_use_ssc(dev_priv))
eb1cbe48
DV		 7553 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7554 else
7555 dpll |= PLL_REF_INPUT_DREFCLK;
7556
7557 dpll |= DPLL_VCO_ENABLE;
190f68c5 7558 crtc_state->dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 7559}
7560
8a654f3b 7561static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 7562{
7563 struct drm_device *dev = intel_crtc->base.dev;
7564 struct drm_i915_private *dev_priv = dev->dev_private;
7565 enum pipe pipe = intel_crtc->pipe;
6e3c9717 7566 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7c5f93b0 7567 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
1caea6e9
VS		 7568 uint32_t crtc_vtotal, crtc_vblank_end;
7569 int vsyncshift = 0;
4d8a62ea
DV		 7570
7571 /* We need to be careful not to changed the adjusted mode, for otherwise
7572 * the hw state checker will get angry at the mismatch. */
7573 crtc_vtotal = adjusted_mode->crtc_vtotal;
7574 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c 7575
609aeaca 7576 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
b0e77b9c 7577 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 7578 crtc_vtotal -= 1;
7579 crtc_vblank_end -= 1;
609aeaca 7580
409ee761 7581 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
609aeaca
VS		 7582 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7583 else
7584 vsyncshift = adjusted_mode->crtc_hsync_start -
7585 adjusted_mode->crtc_htotal / 2;
1caea6e9
VS		 7586 if (vsyncshift < 0)
7587 vsyncshift += adjusted_mode->crtc_htotal;
b0e77b9c
PZ		 7588 }
7589
7590 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 7591 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 7592
fe2b8f9d 7593 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 7594 (adjusted_mode->crtc_hdisplay - 1) |
7595 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 7596 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 7597 (adjusted_mode->crtc_hblank_start - 1) |
7598 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 7599 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 7600 (adjusted_mode->crtc_hsync_start - 1) |
7601 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7602
fe2b8f9d 7603 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 7604 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 7605 ((crtc_vtotal - 1) << 16));
fe2b8f9d 7606 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 7607 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 7608 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 7609 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 7610 (adjusted_mode->crtc_vsync_start - 1) |
7611 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7612
b5e508d4
PZ		 7613 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7614 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7615 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7616 * bits. */
7617 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7618 (pipe == PIPE_B || pipe == PIPE_C))
7619 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7620
bc58be60
JN		 7621}
7622
7623static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
7624{
7625 struct drm_device *dev = intel_crtc->base.dev;
7626 struct drm_i915_private *dev_priv = dev->dev_private;
7627 enum pipe pipe = intel_crtc->pipe;
7628
b0e77b9c
PZ		 7629 /* pipesrc controls the size that is scaled from, which should
7630 * always be the user's requested size.
7631 */
7632 I915_WRITE(PIPESRC(pipe),
6e3c9717
ACO		 7633 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7634 (intel_crtc->config->pipe_src_h - 1));
b0e77b9c
PZ		 7635}
7636
1bd1bd80 7637static void intel_get_pipe_timings(struct intel_crtc *crtc,
5cec258b 7638 struct intel_crtc_state *pipe_config)
1bd1bd80
DV		 7639{
7640 struct drm_device *dev = crtc->base.dev;
7641 struct drm_i915_private *dev_priv = dev->dev_private;
7642 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7643 uint32_t tmp;
7644
7645 tmp = I915_READ(HTOTAL(cpu_transcoder));
2d112de7
ACO		 7646 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7647 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7648 tmp = I915_READ(HBLANK(cpu_transcoder));
2d112de7
ACO		 7649 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7650 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7651 tmp = I915_READ(HSYNC(cpu_transcoder));
2d112de7
ACO		 7652 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7653 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7654
7655 tmp = I915_READ(VTOTAL(cpu_transcoder));
2d112de7
ACO		 7656 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7657 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7658 tmp = I915_READ(VBLANK(cpu_transcoder));
2d112de7
ACO		 7659 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7660 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7661 tmp = I915_READ(VSYNC(cpu_transcoder));
2d112de7
ACO		 7662 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7663 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7664
7665 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
2d112de7
ACO		 7666 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7667 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7668 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
1bd1bd80 7669 }
bc58be60
JN		 7670}
7671
7672static void intel_get_pipe_src_size(struct intel_crtc *crtc,
7673 struct intel_crtc_state *pipe_config)
7674{
7675 struct drm_device *dev = crtc->base.dev;
7676 struct drm_i915_private *dev_priv = dev->dev_private;
7677 u32 tmp;
1bd1bd80
DV		 7678
7679 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 7680 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7681 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7682
2d112de7
ACO		 7683 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7684 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 7685}
7686
f6a83288 7687void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5cec258b 7688 struct intel_crtc_state *pipe_config)
babea61d 7689{
2d112de7
ACO		 7690 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7691 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7692 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7693 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
babea61d 7694
2d112de7
ACO		 7695 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7696 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7697 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7698 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
babea61d 7699
2d112de7 7700 mode->flags = pipe_config->base.adjusted_mode.flags;
cd13f5ab 7701 mode->type = DRM_MODE_TYPE_DRIVER;
babea61d 7702
2d112de7
ACO		 7703 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7704 mode->flags |= pipe_config->base.adjusted_mode.flags;
cd13f5ab
ML		 7705
7706 mode->hsync = drm_mode_hsync(mode);
7707 mode->vrefresh = drm_mode_vrefresh(mode);
7708 drm_mode_set_name(mode);
babea61d
JB		 7709}
7710
84b046f3
DV		 7711static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7712{
7713 struct drm_device *dev = intel_crtc->base.dev;
7714 struct drm_i915_private *dev_priv = dev->dev_private;
7715 uint32_t pipeconf;
7716
9f11a9e4 7717 pipeconf = 0;
84b046f3 7718
b6b5d049
VS		 7719 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7720 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7721 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
67c72a12 7722
6e3c9717 7723 if (intel_crtc->config->double_wide)
cf532bb2 7724 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 7725
ff9ce46e 7726 /* only g4x and later have fancy bpc/dither controls */
666a4537 7727 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
ff9ce46e 7728 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6e3c9717 7729 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
ff9ce46e 7730 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 7731 PIPECONF_DITHER_TYPE_SP;
84b046f3 7732
6e3c9717 7733 switch (intel_crtc->config->pipe_bpp) {
ff9ce46e
DV		 7734 case 18:
7735 pipeconf |= PIPECONF_6BPC;
7736 break;
7737 case 24:
7738 pipeconf |= PIPECONF_8BPC;
7739 break;
7740 case 30:
7741 pipeconf |= PIPECONF_10BPC;
7742 break;
7743 default:
7744 /* Case prevented by intel_choose_pipe_bpp_dither. */
7745 BUG();
84b046f3
DV		 7746 }
7747 }
7748
7749 if (HAS_PIPE_CXSR(dev)) {
7750 if (intel_crtc->lowfreq_avail) {
7751 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7752 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7753 } else {
7754 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 7755 }
7756 }
7757
6e3c9717 7758 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
efc2cfff 7759 if (INTEL_INFO(dev)->gen < 4 ||
409ee761 7760 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
efc2cfff
VS		 7761 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7762 else
7763 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7764 } else
84b046f3
DV		 7765 pipeconf |= PIPECONF_PROGRESSIVE;
7766
666a4537
WB		 7767 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
7768 intel_crtc->config->limited_color_range)
9f11a9e4 7769 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 7770
84b046f3
DV		 7771 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7772 POSTING_READ(PIPECONF(intel_crtc->pipe));
7773}
7774
81c97f52
ACO		 7775static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7776 struct intel_crtc_state *crtc_state)
7777{
7778 struct drm_device *dev = crtc->base.dev;
7779 struct drm_i915_private *dev_priv = dev->dev_private;
7780 const intel_limit_t *limit;
7781 int refclk = 48000;
7782
7783 memset(&crtc_state->dpll_hw_state, 0,
7784 sizeof(crtc_state->dpll_hw_state));
7785
7786 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7787 if (intel_panel_use_ssc(dev_priv)) {
7788 refclk = dev_priv->vbt.lvds_ssc_freq;
7789 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7790 }
7791
7792 limit = &intel_limits_i8xx_lvds;
7793 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) {
7794 limit = &intel_limits_i8xx_dvo;
7795 } else {
7796 limit = &intel_limits_i8xx_dac;
7797 }
7798
7799 if (!crtc_state->clock_set &&
7800 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7801 refclk, NULL, &crtc_state->dpll)) {
7802 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7803 return -EINVAL;
7804 }
7805
7806 i8xx_compute_dpll(crtc, crtc_state, NULL);
7807
7808 return 0;
7809}
7810
19ec6693
ACO		 7811static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7812 struct intel_crtc_state *crtc_state)
7813{
7814 struct drm_device *dev = crtc->base.dev;
7815 struct drm_i915_private *dev_priv = dev->dev_private;
7816 const intel_limit_t *limit;
7817 int refclk = 96000;
7818
7819 memset(&crtc_state->dpll_hw_state, 0,
7820 sizeof(crtc_state->dpll_hw_state));
7821
7822 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7823 if (intel_panel_use_ssc(dev_priv)) {
7824 refclk = dev_priv->vbt.lvds_ssc_freq;
7825 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7826 }
7827
7828 if (intel_is_dual_link_lvds(dev))
7829 limit = &intel_limits_g4x_dual_channel_lvds;
7830 else
7831 limit = &intel_limits_g4x_single_channel_lvds;
7832 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7833 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7834 limit = &intel_limits_g4x_hdmi;
7835 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7836 limit = &intel_limits_g4x_sdvo;
7837 } else {
7838 /* The option is for other outputs */
7839 limit = &intel_limits_i9xx_sdvo;
7840 }
7841
7842 if (!crtc_state->clock_set &&
7843 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7844 refclk, NULL, &crtc_state->dpll)) {
7845 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7846 return -EINVAL;
7847 }
7848
7849 i9xx_compute_dpll(crtc, crtc_state, NULL);
7850
7851 return 0;
7852}
7853
70e8aa21
ACO		 7854static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7855 struct intel_crtc_state *crtc_state)
7856{
7857 struct drm_device *dev = crtc->base.dev;
7858 struct drm_i915_private *dev_priv = dev->dev_private;
7859 const intel_limit_t *limit;
7860 int refclk = 96000;
7861
7862 memset(&crtc_state->dpll_hw_state, 0,
7863 sizeof(crtc_state->dpll_hw_state));
7864
7865 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7866 if (intel_panel_use_ssc(dev_priv)) {
7867 refclk = dev_priv->vbt.lvds_ssc_freq;
7868 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7869 }
7870
7871 limit = &intel_limits_pineview_lvds;
7872 } else {
7873 limit = &intel_limits_pineview_sdvo;
7874 }
7875
7876 if (!crtc_state->clock_set &&
7877 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7878 refclk, NULL, &crtc_state->dpll)) {
7879 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7880 return -EINVAL;
7881 }
7882
7883 i9xx_compute_dpll(crtc, crtc_state, NULL);
7884
7885 return 0;
7886}
7887
190f68c5
ACO		 7888static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7889 struct intel_crtc_state *crtc_state)
79e53945 7890{
c7653199 7891 struct drm_device *dev = crtc->base.dev;
79e53945 7892 struct drm_i915_private *dev_priv = dev->dev_private;
d4906093 7893 const intel_limit_t *limit;
81c97f52 7894 int refclk = 96000;
79e53945 7895
dd3cd74a
ACO		 7896 memset(&crtc_state->dpll_hw_state, 0,
7897 sizeof(crtc_state->dpll_hw_state));
7898
70e8aa21
ACO		 7899 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7900 if (intel_panel_use_ssc(dev_priv)) {
7901 refclk = dev_priv->vbt.lvds_ssc_freq;
7902 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7903 }
43565a06 7904
70e8aa21
ACO		 7905 limit = &intel_limits_i9xx_lvds;
7906 } else {
7907 limit = &intel_limits_i9xx_sdvo;
81c97f52 7908 }
79e53945 7909
70e8aa21
ACO		 7910 if (!crtc_state->clock_set &&
7911 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7912 refclk, NULL, &crtc_state->dpll)) {
7913 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7914 return -EINVAL;
f47709a9 7915 }
7026d4ac 7916
81c97f52 7917 i9xx_compute_dpll(crtc, crtc_state, NULL);
79e53945 7918
c8f7a0db 7919 return 0;
f564048e
EA		 7920}
7921
65b3d6a9
ACO		 7922static int chv_crtc_compute_clock(struct intel_crtc *crtc,
7923 struct intel_crtc_state *crtc_state)
7924{
7925 int refclk = 100000;
7926 const intel_limit_t *limit = &intel_limits_chv;
7927
7928 memset(&crtc_state->dpll_hw_state, 0,
7929 sizeof(crtc_state->dpll_hw_state));
7930
7931 if (crtc_state->has_dsi_encoder)
7932 return 0;
7933
7934 if (!crtc_state->clock_set &&
7935 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7936 refclk, NULL, &crtc_state->dpll)) {
7937 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7938 return -EINVAL;
7939 }
7940
7941 chv_compute_dpll(crtc, crtc_state);
7942
7943 return 0;
7944}
7945
7946static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
7947 struct intel_crtc_state *crtc_state)
7948{
7949 int refclk = 100000;
7950 const intel_limit_t *limit = &intel_limits_vlv;
7951
7952 memset(&crtc_state->dpll_hw_state, 0,
7953 sizeof(crtc_state->dpll_hw_state));
7954
7955 if (crtc_state->has_dsi_encoder)
7956 return 0;
7957
7958 if (!crtc_state->clock_set &&
7959 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7960 refclk, NULL, &crtc_state->dpll)) {
7961 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7962 return -EINVAL;
7963 }
7964
7965 vlv_compute_dpll(crtc, crtc_state);
7966
7967 return 0;
7968}
7969
2fa2fe9a 7970static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5cec258b 7971 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 7972{
7973 struct drm_device *dev = crtc->base.dev;
7974 struct drm_i915_private *dev_priv = dev->dev_private;
7975 uint32_t tmp;
7976
dc9e7dec
VS		 7977 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7978 return;
7979
2fa2fe9a 7980 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 7981 if (!(tmp & PFIT_ENABLE))
7982 return;
2fa2fe9a 7983
06922821 7984 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 7985 if (INTEL_INFO(dev)->gen < 4) {
7986 if (crtc->pipe != PIPE_B)
7987 return;
2fa2fe9a
DV		 7988 } else {
7989 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7990 return;
7991 }
7992
06922821 7993 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 7994 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7995 if (INTEL_INFO(dev)->gen < 5)
7996 pipe_config->gmch_pfit.lvds_border_bits =
7997 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7998}
7999
acbec814 8000static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 8001 struct intel_crtc_state *pipe_config)
acbec814
JB		 8002{
8003 struct drm_device *dev = crtc->base.dev;
8004 struct drm_i915_private *dev_priv = dev->dev_private;
8005 int pipe = pipe_config->cpu_transcoder;
8006 intel_clock_t clock;
8007 u32 mdiv;
662c6ecb 8008 int refclk = 100000;
acbec814 8009
f573de5a
SK		 8010 /* In case of MIPI DPLL will not even be used */
8011 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
8012 return;
8013
a580516d 8014 mutex_lock(&dev_priv->sb_lock);
ab3c759a 8015 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
a580516d 8016 mutex_unlock(&dev_priv->sb_lock);
acbec814
JB		 8017
8018 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8019 clock.m2 = mdiv & DPIO_M2DIV_MASK;
8020 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8021 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8022 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8023
dccbea3b 8024 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
acbec814
JB		 8025}
8026
5724dbd1
DL		 8027static void
8028i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8029 struct intel_initial_plane_config *plane_config)
1ad292b5
JB		 8030{
8031 struct drm_device *dev = crtc->base.dev;
8032 struct drm_i915_private *dev_priv = dev->dev_private;
8033 u32 val, base, offset;
8034 int pipe = crtc->pipe, plane = crtc->plane;
8035 int fourcc, pixel_format;
6761dd31 8036 unsigned int aligned_height;
b113d5ee 8037 struct drm_framebuffer *fb;
1b842c89 8038 struct intel_framebuffer *intel_fb;
1ad292b5 8039
42a7b088
DL		 8040 val = I915_READ(DSPCNTR(plane));
8041 if (!(val & DISPLAY_PLANE_ENABLE))
8042 return;
8043
d9806c9f 8044 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 8045 if (!intel_fb) {
1ad292b5
JB		 8046 DRM_DEBUG_KMS("failed to alloc fb\n");
8047 return;
8048 }
8049
1b842c89
DL		 8050 fb = &intel_fb->base;
8051
18c5247e
DV		 8052 if (INTEL_INFO(dev)->gen >= 4) {
8053 if (val & DISPPLANE_TILED) {
49af449b 8054 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 8055 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8056 }
8057 }
1ad292b5
JB		 8058
8059 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 8060 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 8061 fb->pixel_format = fourcc;
8062 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
1ad292b5
JB		 8063
8064 if (INTEL_INFO(dev)->gen >= 4) {
49af449b 8065 if (plane_config->tiling)
1ad292b5
JB		 8066 offset = I915_READ(DSPTILEOFF(plane));
8067 else
8068 offset = I915_READ(DSPLINOFF(plane));
8069 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8070 } else {
8071 base = I915_READ(DSPADDR(plane));
8072 }
8073 plane_config->base = base;
8074
8075 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 8076 fb->width = ((val >> 16) & 0xfff) + 1;
8077 fb->height = ((val >> 0) & 0xfff) + 1;
1ad292b5
JB		 8078
8079 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 8080 fb->pitches[0] = val & 0xffffffc0;
1ad292b5 8081
b113d5ee 8082 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 8083 fb->pixel_format,
8084 fb->modifier[0]);
1ad292b5 8085
f37b5c2b 8086 plane_config->size = fb->pitches[0] * aligned_height;
1ad292b5 8087
2844a921
DL		 8088 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8089 pipe_name(pipe), plane, fb->width, fb->height,
8090 fb->bits_per_pixel, base, fb->pitches[0],
8091 plane_config->size);
1ad292b5 8092
2d14030b 8093 plane_config->fb = intel_fb;
1ad292b5
JB		 8094}
8095
70b23a98 8096static void chv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 8097 struct intel_crtc_state *pipe_config)
70b23a98
VS		 8098{
8099 struct drm_device *dev = crtc->base.dev;
8100 struct drm_i915_private *dev_priv = dev->dev_private;
8101 int pipe = pipe_config->cpu_transcoder;
8102 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8103 intel_clock_t clock;
0d7b6b11 8104 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
70b23a98
VS		 8105 int refclk = 100000;
8106
a580516d 8107 mutex_lock(&dev_priv->sb_lock);
70b23a98
VS		 8108 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8109 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8110 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8111 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
0d7b6b11 8112 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
a580516d 8113 mutex_unlock(&dev_priv->sb_lock);
70b23a98
VS		 8114
8115 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
0d7b6b11
ID		 8116 clock.m2 = (pll_dw0 & 0xff) << 22;
8117 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8118 clock.m2 |= pll_dw2 & 0x3fffff;
70b23a98
VS		 8119 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8120 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8121 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8122
dccbea3b 8123 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
70b23a98
VS		 8124}
8125
0e8ffe1b 8126static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5cec258b 8127 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 8128{
8129 struct drm_device *dev = crtc->base.dev;
8130 struct drm_i915_private *dev_priv = dev->dev_private;
1729050e 8131 enum intel_display_power_domain power_domain;
0e8ffe1b 8132 uint32_t tmp;
1729050e 8133 bool ret;
0e8ffe1b 8134
1729050e
ID		 8135 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8136 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
b5482bd0
ID		 8137 return false;
8138
e143a21c 8139 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8106ddbd 8140 pipe_config->shared_dpll = NULL;
eccb140b 8141
1729050e
ID		 8142 ret = false;
8143
0e8ffe1b
DV		 8144 tmp = I915_READ(PIPECONF(crtc->pipe));
8145 if (!(tmp & PIPECONF_ENABLE))
1729050e 8146 goto out;
0e8ffe1b 8147
666a4537 8148 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
42571aef
VS		 8149 switch (tmp & PIPECONF_BPC_MASK) {
8150 case PIPECONF_6BPC:
8151 pipe_config->pipe_bpp = 18;
8152 break;
8153 case PIPECONF_8BPC:
8154 pipe_config->pipe_bpp = 24;
8155 break;
8156 case PIPECONF_10BPC:
8157 pipe_config->pipe_bpp = 30;
8158 break;
8159 default:
8160 break;
8161 }
8162 }
8163
666a4537
WB		 8164 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8165 (tmp & PIPECONF_COLOR_RANGE_SELECT))
b5a9fa09
DV		 8166 pipe_config->limited_color_range = true;
8167
282740f7
VS		 8168 if (INTEL_INFO(dev)->gen < 4)
8169 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8170
1bd1bd80 8171 intel_get_pipe_timings(crtc, pipe_config);
bc58be60 8172 intel_get_pipe_src_size(crtc, pipe_config);
1bd1bd80 8173
2fa2fe9a
DV		 8174 i9xx_get_pfit_config(crtc, pipe_config);
8175
6c49f241 8176 if (INTEL_INFO(dev)->gen >= 4) {
c231775c
VS		 8177 /* No way to read it out on pipes B and C */
8178 if (IS_CHERRYVIEW(dev) && crtc->pipe != PIPE_A)
8179 tmp = dev_priv->chv_dpll_md[crtc->pipe];
8180 else
8181 tmp = I915_READ(DPLL_MD(crtc->pipe));
6c49f241
DV		 8182 pipe_config->pixel_multiplier =
8183 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8184 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 8185 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 8186 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8187 tmp = I915_READ(DPLL(crtc->pipe));
8188 pipe_config->pixel_multiplier =
8189 ((tmp & SDVO_MULTIPLIER_MASK)
8190 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8191 } else {
8192 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8193 * port and will be fixed up in the encoder->get_config
8194 * function. */
8195 pipe_config->pixel_multiplier = 1;
8196 }
8bcc2795 8197 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
666a4537 8198 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
1c4e0274
VS		 8199 /*
8200 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8201 * on 830. Filter it out here so that we don't
8202 * report errors due to that.
8203 */
8204 if (IS_I830(dev))
8205 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8206
8bcc2795
DV		 8207 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8208 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 8209 } else {
8210 /* Mask out read-only status bits. */
8211 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8212 DPLL_PORTC_READY_MASK |
8213 DPLL_PORTB_READY_MASK);
8bcc2795 8214 }
6c49f241 8215
70b23a98
VS		 8216 if (IS_CHERRYVIEW(dev))
8217 chv_crtc_clock_get(crtc, pipe_config);
8218 else if (IS_VALLEYVIEW(dev))
acbec814
JB		 8219 vlv_crtc_clock_get(crtc, pipe_config);
8220 else
8221 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 8222
0f64614d
VS		 8223 /*
8224 * Normally the dotclock is filled in by the encoder .get_config()
8225 * but in case the pipe is enabled w/o any ports we need a sane
8226 * default.
8227 */
8228 pipe_config->base.adjusted_mode.crtc_clock =
8229 pipe_config->port_clock / pipe_config->pixel_multiplier;
8230
1729050e
ID		 8231 ret = true;
8232
8233out:
8234 intel_display_power_put(dev_priv, power_domain);
8235
8236 return ret;
0e8ffe1b
DV		 8237}
8238
dde86e2d 8239static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 8240{
8241 struct drm_i915_private *dev_priv = dev->dev_private;
13d83a67 8242 struct intel_encoder *encoder;
74cfd7ac 8243 u32 val, final;
13d83a67 8244 bool has_lvds = false;
199e5d79 8245 bool has_cpu_edp = false;
199e5d79 8246 bool has_panel = false;
99eb6a01
KP		 8247 bool has_ck505 = false;
8248 bool can_ssc = false;
13d83a67
JB		 8249
8250 /* We need to take the global config into account */
b2784e15 8251 for_each_intel_encoder(dev, encoder) {
199e5d79
KP		 8252 switch (encoder->type) {
8253 case INTEL_OUTPUT_LVDS:
8254 has_panel = true;
8255 has_lvds = true;
8256 break;
8257 case INTEL_OUTPUT_EDP:
8258 has_panel = true;
2de6905f 8259 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 8260 has_cpu_edp = true;
8261 break;
6847d71b
PZ		 8262 default:
8263 break;
13d83a67
JB		 8264 }
8265 }
8266
99eb6a01 8267 if (HAS_PCH_IBX(dev)) {
41aa3448 8268 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 8269 can_ssc = has_ck505;
8270 } else {
8271 has_ck505 = false;
8272 can_ssc = true;
8273 }
8274
2de6905f
ID		 8275 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8276 has_panel, has_lvds, has_ck505);
13d83a67
JB		 8277
8278 /* Ironlake: try to setup display ref clock before DPLL
8279 * enabling. This is only under driver's control after
8280 * PCH B stepping, previous chipset stepping should be
8281 * ignoring this setting.
8282 */
74cfd7ac
CW		 8283 val = I915_READ(PCH_DREF_CONTROL);
8284
8285 /* As we must carefully and slowly disable/enable each source in turn,
8286 * compute the final state we want first and check if we need to
8287 * make any changes at all.
8288 */
8289 final = val;
8290 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8291 if (has_ck505)
8292 final |= DREF_NONSPREAD_CK505_ENABLE;
8293 else
8294 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8295
8296 final &= ~DREF_SSC_SOURCE_MASK;
8297 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8298 final &= ~DREF_SSC1_ENABLE;
8299
8300 if (has_panel) {
8301 final |= DREF_SSC_SOURCE_ENABLE;
8302
8303 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8304 final |= DREF_SSC1_ENABLE;
8305
8306 if (has_cpu_edp) {
8307 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8308 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8309 else
8310 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8311 } else
8312 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8313 } else {
8314 final |= DREF_SSC_SOURCE_DISABLE;
8315 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8316 }
8317
8318 if (final == val)
8319 return;
8320
13d83a67 8321 /* Always enable nonspread source */
74cfd7ac 8322 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 8323
99eb6a01 8324 if (has_ck505)
74cfd7ac 8325 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 8326 else
74cfd7ac 8327 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 8328
199e5d79 8329 if (has_panel) {
74cfd7ac
CW		 8330 val &= ~DREF_SSC_SOURCE_MASK;
8331 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 8332
199e5d79 8333 /* SSC must be turned on before enabling the CPU output */
99eb6a01 8334 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8335 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 8336 val |= DREF_SSC1_ENABLE;
e77166b5 8337 } else
74cfd7ac 8338 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 8339
8340 /* Get SSC going before enabling the outputs */
74cfd7ac 8341 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8342 POSTING_READ(PCH_DREF_CONTROL);
8343 udelay(200);
8344
74cfd7ac 8345 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 8346
8347 /* Enable CPU source on CPU attached eDP */
199e5d79 8348 if (has_cpu_edp) {
99eb6a01 8349 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8350 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 8351 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
eba905b2 8352 } else
74cfd7ac 8353 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 8354 } else
74cfd7ac 8355 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8356
74cfd7ac 8357 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8358 POSTING_READ(PCH_DREF_CONTROL);
8359 udelay(200);
8360 } else {
8361 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8362
74cfd7ac 8363 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 8364
8365 /* Turn off CPU output */
74cfd7ac 8366 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8367
74cfd7ac 8368 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8369 POSTING_READ(PCH_DREF_CONTROL);
8370 udelay(200);
8371
8372 /* Turn off the SSC source */
74cfd7ac
CW		 8373 val &= ~DREF_SSC_SOURCE_MASK;
8374 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 8375
8376 /* Turn off SSC1 */
74cfd7ac 8377 val &= ~DREF_SSC1_ENABLE;
199e5d79 8378
74cfd7ac 8379 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 8380 POSTING_READ(PCH_DREF_CONTROL);
8381 udelay(200);
8382 }
74cfd7ac
CW		 8383
8384 BUG_ON(val != final);
13d83a67
JB		 8385}
8386
f31f2d55 8387static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 8388{
f31f2d55 8389 uint32_t tmp;
dde86e2d 8390
0ff066a9
PZ		 8391 tmp = I915_READ(SOUTH_CHICKEN2);
8392 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8393 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8394
0ff066a9
PZ		 8395 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8396 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8397 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 8398
0ff066a9
PZ		 8399 tmp = I915_READ(SOUTH_CHICKEN2);
8400 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8401 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8402
0ff066a9
PZ		 8403 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8404 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8405 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 8406}
8407
8408/* WaMPhyProgramming:hsw */
8409static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8410{
8411 uint32_t tmp;
dde86e2d
PZ		 8412
8413 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8414 tmp &= ~(0xFF << 24);
8415 tmp |= (0x12 << 24);
8416 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8417
dde86e2d
PZ		 8418 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8419 tmp |= (1 << 11);
8420 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8421
8422 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8423 tmp |= (1 << 11);
8424 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8425
dde86e2d
PZ		 8426 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8427 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8428 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8429
8430 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8431 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8432 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8433
0ff066a9
PZ		 8434 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8435 tmp &= ~(7 << 13);
8436 tmp |= (5 << 13);
8437 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 8438
0ff066a9
PZ		 8439 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8440 tmp &= ~(7 << 13);
8441 tmp |= (5 << 13);
8442 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 8443
8444 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8445 tmp &= ~0xFF;
8446 tmp |= 0x1C;
8447 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8448
8449 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8450 tmp &= ~0xFF;
8451 tmp |= 0x1C;
8452 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8453
8454 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8455 tmp &= ~(0xFF << 16);
8456 tmp |= (0x1C << 16);
8457 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8458
8459 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8460 tmp &= ~(0xFF << 16);
8461 tmp |= (0x1C << 16);
8462 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8463
0ff066a9
PZ		 8464 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8465 tmp |= (1 << 27);
8466 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 8467
0ff066a9
PZ		 8468 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8469 tmp |= (1 << 27);
8470 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 8471
0ff066a9
PZ		 8472 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8473 tmp &= ~(0xF << 28);
8474 tmp |= (4 << 28);
8475 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 8476
0ff066a9
PZ		 8477 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8478 tmp &= ~(0xF << 28);
8479 tmp |= (4 << 28);
8480 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 8481}
8482
2fa86a1f
PZ		 8483/* Implements 3 different sequences from BSpec chapter "Display iCLK
8484 * Programming" based on the parameters passed:
8485 * - Sequence to enable CLKOUT_DP
8486 * - Sequence to enable CLKOUT_DP without spread
8487 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8488 */
8489static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8490 bool with_fdi)
f31f2d55
PZ		 8491{
8492 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 8493 uint32_t reg, tmp;
8494
8495 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8496 with_spread = true;
c2699524 8497 if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
2fa86a1f 8498 with_fdi = false;
f31f2d55 8499
a580516d 8500 mutex_lock(&dev_priv->sb_lock);
f31f2d55
PZ		 8501
8502 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8503 tmp &= ~SBI_SSCCTL_DISABLE;
8504 tmp |= SBI_SSCCTL_PATHALT;
8505 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8506
8507 udelay(24);
8508
2fa86a1f
PZ		 8509 if (with_spread) {
8510 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8511 tmp &= ~SBI_SSCCTL_PATHALT;
8512 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 8513
2fa86a1f
PZ		 8514 if (with_fdi) {
8515 lpt_reset_fdi_mphy(dev_priv);
8516 lpt_program_fdi_mphy(dev_priv);
8517 }
8518 }
dde86e2d 8519
c2699524 8520 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
2fa86a1f
PZ		 8521 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8522 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8523 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246 8524
a580516d 8525 mutex_unlock(&dev_priv->sb_lock);
dde86e2d
PZ		 8526}
8527
47701c3b
PZ		 8528/* Sequence to disable CLKOUT_DP */
8529static void lpt_disable_clkout_dp(struct drm_device *dev)
8530{
8531 struct drm_i915_private *dev_priv = dev->dev_private;
8532 uint32_t reg, tmp;
8533
a580516d 8534 mutex_lock(&dev_priv->sb_lock);
47701c3b 8535
c2699524 8536 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
47701c3b
PZ		 8537 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8538 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8539 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8540
8541 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8542 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8543 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8544 tmp |= SBI_SSCCTL_PATHALT;
8545 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8546 udelay(32);
8547 }
8548 tmp |= SBI_SSCCTL_DISABLE;
8549 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8550 }
8551
a580516d 8552 mutex_unlock(&dev_priv->sb_lock);
47701c3b
PZ		 8553}
8554
f7be2c21
VS		 8555#define BEND_IDX(steps) ((50 + (steps)) / 5)
8556
8557static const uint16_t sscdivintphase[] = {
8558 [BEND_IDX( 50)] = 0x3B23,
8559 [BEND_IDX( 45)] = 0x3B23,
8560 [BEND_IDX( 40)] = 0x3C23,
8561 [BEND_IDX( 35)] = 0x3C23,
8562 [BEND_IDX( 30)] = 0x3D23,
8563 [BEND_IDX( 25)] = 0x3D23,
8564 [BEND_IDX( 20)] = 0x3E23,
8565 [BEND_IDX( 15)] = 0x3E23,
8566 [BEND_IDX( 10)] = 0x3F23,
8567 [BEND_IDX( 5)] = 0x3F23,
8568 [BEND_IDX( 0)] = 0x0025,
8569 [BEND_IDX( -5)] = 0x0025,
8570 [BEND_IDX(-10)] = 0x0125,
8571 [BEND_IDX(-15)] = 0x0125,
8572 [BEND_IDX(-20)] = 0x0225,
8573 [BEND_IDX(-25)] = 0x0225,
8574 [BEND_IDX(-30)] = 0x0325,
8575 [BEND_IDX(-35)] = 0x0325,
8576 [BEND_IDX(-40)] = 0x0425,
8577 [BEND_IDX(-45)] = 0x0425,
8578 [BEND_IDX(-50)] = 0x0525,
8579};
8580
8581/*
8582 * Bend CLKOUT_DP
8583 * steps -50 to 50 inclusive, in steps of 5
8584 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8585 * change in clock period = -(steps / 10) * 5.787 ps
8586 */
8587static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
8588{
8589 uint32_t tmp;
8590 int idx = BEND_IDX(steps);
8591
8592 if (WARN_ON(steps % 5 != 0))
8593 return;
8594
8595 if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
8596 return;
8597
8598 mutex_lock(&dev_priv->sb_lock);
8599
8600 if (steps % 10 != 0)
8601 tmp = 0xAAAAAAAB;
8602 else
8603 tmp = 0x00000000;
8604 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
8605
8606 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8607 tmp &= 0xffff0000;
8608 tmp |= sscdivintphase[idx];
8609 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8610
8611 mutex_unlock(&dev_priv->sb_lock);
8612}
8613
8614#undef BEND_IDX
8615
bf8fa3d3
PZ		 8616static void lpt_init_pch_refclk(struct drm_device *dev)
8617{
bf8fa3d3
PZ		 8618 struct intel_encoder *encoder;
8619 bool has_vga = false;
8620
b2784e15 8621 for_each_intel_encoder(dev, encoder) {
bf8fa3d3
PZ		 8622 switch (encoder->type) {
8623 case INTEL_OUTPUT_ANALOG:
8624 has_vga = true;
8625 break;
6847d71b
PZ		 8626 default:
8627 break;
bf8fa3d3
PZ		 8628 }
8629 }
8630
f7be2c21
VS		 8631 if (has_vga) {
8632 lpt_bend_clkout_dp(to_i915(dev), 0);
47701c3b 8633 lpt_enable_clkout_dp(dev, true, true);
f7be2c21 8634 } else {
47701c3b 8635 lpt_disable_clkout_dp(dev);
f7be2c21 8636 }
bf8fa3d3
PZ		 8637}
8638
dde86e2d
PZ		 8639/*
8640 * Initialize reference clocks when the driver loads
8641 */
8642void intel_init_pch_refclk(struct drm_device *dev)
8643{
8644 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8645 ironlake_init_pch_refclk(dev);
8646 else if (HAS_PCH_LPT(dev))
8647 lpt_init_pch_refclk(dev);
8648}
8649
6ff93609 8650static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 8651{
c8203565 8652 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 8653 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8654 int pipe = intel_crtc->pipe;
c8203565
PZ		 8655 uint32_t val;
8656
78114071 8657 val = 0;
c8203565 8658
6e3c9717 8659 switch (intel_crtc->config->pipe_bpp) {
c8203565 8660 case 18:
dfd07d72 8661 val |= PIPECONF_6BPC;
c8203565
PZ		 8662 break;
8663 case 24:
dfd07d72 8664 val |= PIPECONF_8BPC;
c8203565
PZ		 8665 break;
8666 case 30:
dfd07d72 8667 val |= PIPECONF_10BPC;
c8203565
PZ		 8668 break;
8669 case 36:
dfd07d72 8670 val |= PIPECONF_12BPC;
c8203565
PZ		 8671 break;
8672 default:
cc769b62
PZ		 8673 /* Case prevented by intel_choose_pipe_bpp_dither. */
8674 BUG();
c8203565
PZ		 8675 }
8676
6e3c9717 8677 if (intel_crtc->config->dither)
c8203565
PZ		 8678 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8679
6e3c9717 8680 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 8681 val |= PIPECONF_INTERLACED_ILK;
8682 else
8683 val |= PIPECONF_PROGRESSIVE;
8684
6e3c9717 8685 if (intel_crtc->config->limited_color_range)
3685a8f3 8686 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 8687
c8203565
PZ		 8688 I915_WRITE(PIPECONF(pipe), val);
8689 POSTING_READ(PIPECONF(pipe));
8690}
8691
6ff93609 8692static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38 8693{
391bf048 8694 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
ee2b0b38 8695 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 8696 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
391bf048 8697 u32 val = 0;
ee2b0b38 8698
391bf048 8699 if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
ee2b0b38
PZ		 8700 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8701
6e3c9717 8702 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 8703 val |= PIPECONF_INTERLACED_ILK;
8704 else
8705 val |= PIPECONF_PROGRESSIVE;
8706
702e7a56
PZ		 8707 I915_WRITE(PIPECONF(cpu_transcoder), val);
8708 POSTING_READ(PIPECONF(cpu_transcoder));
391bf048
JN		 8709}
8710
391bf048
JN		 8711static void haswell_set_pipemisc(struct drm_crtc *crtc)
8712{
8713 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8714 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
756f85cf 8715
391bf048
JN		 8716 if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
8717 u32 val = 0;
756f85cf 8718
6e3c9717 8719 switch (intel_crtc->config->pipe_bpp) {
756f85cf
PZ		 8720 case 18:
8721 val |= PIPEMISC_DITHER_6_BPC;
8722 break;
8723 case 24:
8724 val |= PIPEMISC_DITHER_8_BPC;
8725 break;
8726 case 30:
8727 val |= PIPEMISC_DITHER_10_BPC;
8728 break;
8729 case 36:
8730 val |= PIPEMISC_DITHER_12_BPC;
8731 break;
8732 default:
8733 /* Case prevented by pipe_config_set_bpp. */
8734 BUG();
8735 }
8736
6e3c9717 8737 if (intel_crtc->config->dither)
756f85cf
PZ		 8738 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8739
391bf048 8740 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
756f85cf 8741 }
ee2b0b38
PZ		 8742}
8743
d4b1931c
PZ		 8744int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8745{
8746 /*
8747 * Account for spread spectrum to avoid
8748 * oversubscribing the link. Max center spread
8749 * is 2.5%; use 5% for safety's sake.
8750 */
8751 u32 bps = target_clock * bpp * 21 / 20;
619d4d04 8752 return DIV_ROUND_UP(bps, link_bw * 8);
d4b1931c
PZ		 8753}
8754
7429e9d4 8755static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 8756{
7429e9d4 8757 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 8758}
8759
b75ca6f6
ACO		 8760static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8761 struct intel_crtc_state *crtc_state,
8762 intel_clock_t *reduced_clock)
79e53945 8763{
de13a2e3 8764 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 8765 struct drm_device *dev = crtc->dev;
8766 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8767 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8768 struct drm_connector *connector;
55bb9992
ACO		 8769 struct drm_connector_state *connector_state;
8770 struct intel_encoder *encoder;
b75ca6f6 8771 u32 dpll, fp, fp2;
ceb41007 8772 int factor, i;
09ede541 8773 bool is_lvds = false, is_sdvo = false;
79e53945 8774
da3ced29 8775 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8776 if (connector_state->crtc != crtc_state->base.crtc)
8777 continue;
8778
8779 encoder = to_intel_encoder(connector_state->best_encoder);
8780
8781 switch (encoder->type) {
79e53945
JB		 8782 case INTEL_OUTPUT_LVDS:
8783 is_lvds = true;
8784 break;
8785 case INTEL_OUTPUT_SDVO:
7d57382e 8786 case INTEL_OUTPUT_HDMI:
79e53945 8787 is_sdvo = true;
79e53945 8788 break;
6847d71b
PZ		 8789 default:
8790 break;
79e53945
JB		 8791 }
8792 }
79e53945 8793
c1858123 8794 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 8795 factor = 21;
8796 if (is_lvds) {
8797 if ((intel_panel_use_ssc(dev_priv) &&
e91e941b 8798 dev_priv->vbt.lvds_ssc_freq == 100000) ||
f0b44056 8799 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 8800 factor = 25;
190f68c5 8801 } else if (crtc_state->sdvo_tv_clock)
8febb297 8802 factor = 20;
c1858123 8803
b75ca6f6
ACO		 8804 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8805
190f68c5 8806 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
b75ca6f6
ACO		 8807 fp |= FP_CB_TUNE;
8808
8809 if (reduced_clock) {
8810 fp2 = i9xx_dpll_compute_fp(reduced_clock);
2c07245f 8811
b75ca6f6
ACO		 8812 if (reduced_clock->m < factor * reduced_clock->n)
8813 fp2 |= FP_CB_TUNE;
8814 } else {
8815 fp2 = fp;
8816 }
9a7c7890 8817
5eddb70b 8818 dpll = 0;
2c07245f 8819
a07d6787
EA		 8820 if (is_lvds)
8821 dpll |= DPLLB_MODE_LVDS;
8822 else
8823 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 8824
190f68c5 8825 dpll |= (crtc_state->pixel_multiplier - 1)
ef1b460d 8826 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 8827
8828 if (is_sdvo)
4a33e48d 8829 dpll |= DPLL_SDVO_HIGH_SPEED;
190f68c5 8830 if (crtc_state->has_dp_encoder)
4a33e48d 8831 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 8832
a07d6787 8833 /* compute bitmask from p1 value */
190f68c5 8834 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 8835 /* also FPA1 */
190f68c5 8836 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 8837
190f68c5 8838 switch (crtc_state->dpll.p2) {
a07d6787
EA		 8839 case 5:
8840 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8841 break;
8842 case 7:
8843 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8844 break;
8845 case 10:
8846 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8847 break;
8848 case 14:
8849 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8850 break;
79e53945
JB		 8851 }
8852
ceb41007 8853 if (is_lvds && intel_panel_use_ssc(dev_priv))
43565a06 8854 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 8855 else
8856 dpll |= PLL_REF_INPUT_DREFCLK;
8857
b75ca6f6
ACO		 8858 dpll |= DPLL_VCO_ENABLE;
8859
8860 crtc_state->dpll_hw_state.dpll = dpll;
8861 crtc_state->dpll_hw_state.fp0 = fp;
8862 crtc_state->dpll_hw_state.fp1 = fp2;
de13a2e3
PZ		 8863}
8864
190f68c5
ACO		 8865static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8866 struct intel_crtc_state *crtc_state)
de13a2e3 8867{
997c030c
ACO		 8868 struct drm_device *dev = crtc->base.dev;
8869 struct drm_i915_private *dev_priv = dev->dev_private;
364ee29d 8870 intel_clock_t reduced_clock;
7ed9f894 8871 bool has_reduced_clock = false;
e2b78267 8872 struct intel_shared_dpll *pll;
997c030c
ACO		 8873 const intel_limit_t *limit;
8874 int refclk = 120000;
de13a2e3 8875
dd3cd74a
ACO		 8876 memset(&crtc_state->dpll_hw_state, 0,
8877 sizeof(crtc_state->dpll_hw_state));
8878
ded220e2
ACO		 8879 crtc->lowfreq_avail = false;
8880
8881 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8882 if (!crtc_state->has_pch_encoder)
8883 return 0;
79e53945 8884
997c030c
ACO		 8885 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8886 if (intel_panel_use_ssc(dev_priv)) {
8887 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8888 dev_priv->vbt.lvds_ssc_freq);
8889 refclk = dev_priv->vbt.lvds_ssc_freq;
8890 }
8891
8892 if (intel_is_dual_link_lvds(dev)) {
8893 if (refclk == 100000)
8894 limit = &intel_limits_ironlake_dual_lvds_100m;
8895 else
8896 limit = &intel_limits_ironlake_dual_lvds;
8897 } else {
8898 if (refclk == 100000)
8899 limit = &intel_limits_ironlake_single_lvds_100m;
8900 else
8901 limit = &intel_limits_ironlake_single_lvds;
8902 }
8903 } else {
8904 limit = &intel_limits_ironlake_dac;
8905 }
8906
364ee29d 8907 if (!crtc_state->clock_set &&
997c030c
ACO		 8908 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8909 refclk, NULL, &crtc_state->dpll)) {
364ee29d
ACO		 8910 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8911 return -EINVAL;
f47709a9 8912 }
79e53945 8913
b75ca6f6
ACO		 8914 ironlake_compute_dpll(crtc, crtc_state,
8915 has_reduced_clock ? &reduced_clock : NULL);
66e985c0 8916
ded220e2
ACO		 8917 pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
8918 if (pll == NULL) {
8919 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8920 pipe_name(crtc->pipe));
8921 return -EINVAL;
3fb37703 8922 }
79e53945 8923
ded220e2
ACO		 8924 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8925 has_reduced_clock)
c7653199 8926 crtc->lowfreq_avail = true;
e2b78267 8927
c8f7a0db 8928 return 0;
79e53945
JB		 8929}
8930
eb14cb74
VS		 8931static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8932 struct intel_link_m_n *m_n)
8933{
8934 struct drm_device *dev = crtc->base.dev;
8935 struct drm_i915_private *dev_priv = dev->dev_private;
8936 enum pipe pipe = crtc->pipe;
8937
8938 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8939 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8940 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8941 & ~TU_SIZE_MASK;
8942 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8943 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8944 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8945}
8946
8947static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8948 enum transcoder transcoder,
b95af8be
VK		 8949 struct intel_link_m_n *m_n,
8950 struct intel_link_m_n *m2_n2)
72419203
DV		 8951{
8952 struct drm_device *dev = crtc->base.dev;
8953 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 8954 enum pipe pipe = crtc->pipe;
72419203 8955
eb14cb74
VS		 8956 if (INTEL_INFO(dev)->gen >= 5) {
8957 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8958 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8959 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8960 & ~TU_SIZE_MASK;
8961 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8962 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8963 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
b95af8be
VK		 8964 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8965 * gen < 8) and if DRRS is supported (to make sure the
8966 * registers are not unnecessarily read).
8967 */
8968 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
6e3c9717 8969 crtc->config->has_drrs) {
b95af8be
VK		 8970 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8971 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8972 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8973 & ~TU_SIZE_MASK;
8974 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8975 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8976 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8977 }
eb14cb74
VS		 8978 } else {
8979 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8980 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8981 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8982 & ~TU_SIZE_MASK;
8983 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8984 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8985 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8986 }
8987}
8988
8989void intel_dp_get_m_n(struct intel_crtc *crtc,
5cec258b 8990 struct intel_crtc_state *pipe_config)
eb14cb74 8991{
681a8504 8992 if (pipe_config->has_pch_encoder)
eb14cb74
VS		 8993 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8994 else
8995 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be
VK		 8996 &pipe_config->dp_m_n,
8997 &pipe_config->dp_m2_n2);
eb14cb74 8998}
72419203 8999
eb14cb74 9000static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5cec258b 9001 struct intel_crtc_state *pipe_config)
eb14cb74
VS		 9002{
9003 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be 9004 &pipe_config->fdi_m_n, NULL);
72419203
DV		 9005}
9006
bd2e244f 9007static void skylake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 9008 struct intel_crtc_state *pipe_config)
bd2e244f
JB		 9009{
9010 struct drm_device *dev = crtc->base.dev;
9011 struct drm_i915_private *dev_priv = dev->dev_private;
a1b2278e
CK		 9012 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9013 uint32_t ps_ctrl = 0;
9014 int id = -1;
9015 int i;
bd2e244f 9016
a1b2278e
CK		 9017 /* find scaler attached to this pipe */
9018 for (i = 0; i < crtc->num_scalers; i++) {
9019 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9020 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9021 id = i;
9022 pipe_config->pch_pfit.enabled = true;
9023 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9024 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9025 break;
9026 }
9027 }
bd2e244f 9028
a1b2278e
CK		 9029 scaler_state->scaler_id = id;
9030 if (id >= 0) {
9031 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9032 } else {
9033 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
bd2e244f
JB		 9034 }
9035}
9036
5724dbd1
DL		 9037static void
9038skylake_get_initial_plane_config(struct intel_crtc *crtc,
9039 struct intel_initial_plane_config *plane_config)
bc8d7dff
DL		 9040{
9041 struct drm_device *dev = crtc->base.dev;
9042 struct drm_i915_private *dev_priv = dev->dev_private;
40f46283 9043 u32 val, base, offset, stride_mult, tiling;
bc8d7dff
DL		 9044 int pipe = crtc->pipe;
9045 int fourcc, pixel_format;
6761dd31 9046 unsigned int aligned_height;
bc8d7dff 9047 struct drm_framebuffer *fb;
1b842c89 9048 struct intel_framebuffer *intel_fb;
bc8d7dff 9049
d9806c9f 9050 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 9051 if (!intel_fb) {
bc8d7dff
DL		 9052 DRM_DEBUG_KMS("failed to alloc fb\n");
9053 return;
9054 }
9055
1b842c89
DL		 9056 fb = &intel_fb->base;
9057
bc8d7dff 9058 val = I915_READ(PLANE_CTL(pipe, 0));
42a7b088
DL		 9059 if (!(val & PLANE_CTL_ENABLE))
9060 goto error;
9061
bc8d7dff
DL		 9062 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9063 fourcc = skl_format_to_fourcc(pixel_format,
9064 val & PLANE_CTL_ORDER_RGBX,
9065 val & PLANE_CTL_ALPHA_MASK);
9066 fb->pixel_format = fourcc;
9067 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9068
40f46283
DL		 9069 tiling = val & PLANE_CTL_TILED_MASK;
9070 switch (tiling) {
9071 case PLANE_CTL_TILED_LINEAR:
9072 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9073 break;
9074 case PLANE_CTL_TILED_X:
9075 plane_config->tiling = I915_TILING_X;
9076 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9077 break;
9078 case PLANE_CTL_TILED_Y:
9079 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9080 break;
9081 case PLANE_CTL_TILED_YF:
9082 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9083 break;
9084 default:
9085 MISSING_CASE(tiling);
9086 goto error;
9087 }
9088
bc8d7dff
DL		 9089 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9090 plane_config->base = base;
9091
9092 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9093
9094 val = I915_READ(PLANE_SIZE(pipe, 0));
9095 fb->height = ((val >> 16) & 0xfff) + 1;
9096 fb->width = ((val >> 0) & 0x1fff) + 1;
9097
9098 val = I915_READ(PLANE_STRIDE(pipe, 0));
7b49f948 9099 stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
40f46283 9100 fb->pixel_format);
bc8d7dff
DL		 9101 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9102
9103 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 9104 fb->pixel_format,
9105 fb->modifier[0]);
bc8d7dff 9106
f37b5c2b 9107 plane_config->size = fb->pitches[0] * aligned_height;
bc8d7dff
DL		 9108
9109 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9110 pipe_name(pipe), fb->width, fb->height,
9111 fb->bits_per_pixel, base, fb->pitches[0],
9112 plane_config->size);
9113
2d14030b 9114 plane_config->fb = intel_fb;
bc8d7dff
DL		 9115 return;
9116
9117error:
9118 kfree(fb);
9119}
9120
2fa2fe9a 9121static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 9122 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 9123{
9124 struct drm_device *dev = crtc->base.dev;
9125 struct drm_i915_private *dev_priv = dev->dev_private;
9126 uint32_t tmp;
9127
9128 tmp = I915_READ(PF_CTL(crtc->pipe));
9129
9130 if (tmp & PF_ENABLE) {
fd4daa9c 9131 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV		 9132 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9133 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 9134
9135 /* We currently do not free assignements of panel fitters on
9136 * ivb/hsw (since we don't use the higher upscaling modes which
9137 * differentiates them) so just WARN about this case for now. */
9138 if (IS_GEN7(dev)) {
9139 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9140 PF_PIPE_SEL_IVB(crtc->pipe));
9141 }
2fa2fe9a 9142 }
79e53945
JB		 9143}
9144
5724dbd1
DL		 9145static void
9146ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9147 struct intel_initial_plane_config *plane_config)
4c6baa59
JB		 9148{
9149 struct drm_device *dev = crtc->base.dev;
9150 struct drm_i915_private *dev_priv = dev->dev_private;
9151 u32 val, base, offset;
aeee5a49 9152 int pipe = crtc->pipe;
4c6baa59 9153 int fourcc, pixel_format;
6761dd31 9154 unsigned int aligned_height;
b113d5ee 9155 struct drm_framebuffer *fb;
1b842c89 9156 struct intel_framebuffer *intel_fb;
4c6baa59 9157
42a7b088
DL		 9158 val = I915_READ(DSPCNTR(pipe));
9159 if (!(val & DISPLAY_PLANE_ENABLE))
9160 return;
9161
d9806c9f 9162 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 9163 if (!intel_fb) {
4c6baa59
JB		 9164 DRM_DEBUG_KMS("failed to alloc fb\n");
9165 return;
9166 }
9167
1b842c89
DL		 9168 fb = &intel_fb->base;
9169
18c5247e
DV		 9170 if (INTEL_INFO(dev)->gen >= 4) {
9171 if (val & DISPPLANE_TILED) {
49af449b 9172 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 9173 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9174 }
9175 }
4c6baa59
JB		 9176
9177 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 9178 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 9179 fb->pixel_format = fourcc;
9180 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
4c6baa59 9181
aeee5a49 9182 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
4c6baa59 9183 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
aeee5a49 9184 offset = I915_READ(DSPOFFSET(pipe));
4c6baa59 9185 } else {
49af449b 9186 if (plane_config->tiling)
aeee5a49 9187 offset = I915_READ(DSPTILEOFF(pipe));
4c6baa59 9188 else
aeee5a49 9189 offset = I915_READ(DSPLINOFF(pipe));
4c6baa59
JB		 9190 }
9191 plane_config->base = base;
9192
9193 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 9194 fb->width = ((val >> 16) & 0xfff) + 1;
9195 fb->height = ((val >> 0) & 0xfff) + 1;
4c6baa59
JB		 9196
9197 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 9198 fb->pitches[0] = val & 0xffffffc0;
4c6baa59 9199
b113d5ee 9200 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 9201 fb->pixel_format,
9202 fb->modifier[0]);
4c6baa59 9203
f37b5c2b 9204 plane_config->size = fb->pitches[0] * aligned_height;
4c6baa59 9205
2844a921
DL		 9206 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9207 pipe_name(pipe), fb->width, fb->height,
9208 fb->bits_per_pixel, base, fb->pitches[0],
9209 plane_config->size);
b113d5ee 9210
2d14030b 9211 plane_config->fb = intel_fb;
4c6baa59
JB		 9212}
9213
0e8ffe1b 9214static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9215 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9216{
9217 struct drm_device *dev = crtc->base.dev;
9218 struct drm_i915_private *dev_priv = dev->dev_private;
1729050e 9219 enum intel_display_power_domain power_domain;
0e8ffe1b 9220 uint32_t tmp;
1729050e 9221 bool ret;
0e8ffe1b 9222
1729050e
ID		 9223 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9224 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
930e8c9e
PZ		 9225 return false;
9226
e143a21c 9227 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8106ddbd 9228 pipe_config->shared_dpll = NULL;
eccb140b 9229
1729050e 9230 ret = false;
0e8ffe1b
DV		 9231 tmp = I915_READ(PIPECONF(crtc->pipe));
9232 if (!(tmp & PIPECONF_ENABLE))
1729050e 9233 goto out;
0e8ffe1b 9234
42571aef
VS		 9235 switch (tmp & PIPECONF_BPC_MASK) {
9236 case PIPECONF_6BPC:
9237 pipe_config->pipe_bpp = 18;
9238 break;
9239 case PIPECONF_8BPC:
9240 pipe_config->pipe_bpp = 24;
9241 break;
9242 case PIPECONF_10BPC:
9243 pipe_config->pipe_bpp = 30;
9244 break;
9245 case PIPECONF_12BPC:
9246 pipe_config->pipe_bpp = 36;
9247 break;
9248 default:
9249 break;
9250 }
9251
b5a9fa09
DV		 9252 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9253 pipe_config->limited_color_range = true;
9254
ab9412ba 9255 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0 9256 struct intel_shared_dpll *pll;
8106ddbd 9257 enum intel_dpll_id pll_id;
66e985c0 9258
88adfff1
DV		 9259 pipe_config->has_pch_encoder = true;
9260
627eb5a3
DV		 9261 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9262 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9263 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 9264
9265 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 9266
c0d43d62 9267 if (HAS_PCH_IBX(dev_priv->dev)) {
8106ddbd 9268 pll_id = (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 9269 } else {
9270 tmp = I915_READ(PCH_DPLL_SEL);
9271 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8106ddbd 9272 pll_id = DPLL_ID_PCH_PLL_B;
c0d43d62 9273 else
8106ddbd 9274 pll_id= DPLL_ID_PCH_PLL_A;
c0d43d62 9275 }
66e985c0 9276
8106ddbd
ACO		 9277 pipe_config->shared_dpll =
9278 intel_get_shared_dpll_by_id(dev_priv, pll_id);
9279 pll = pipe_config->shared_dpll;
66e985c0 9280
2edd6443
ACO		 9281 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9282 &pipe_config->dpll_hw_state));
c93f54cf
DV		 9283
9284 tmp = pipe_config->dpll_hw_state.dpll;
9285 pipe_config->pixel_multiplier =
9286 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9287 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 9288
9289 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 9290 } else {
9291 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 9292 }
9293
1bd1bd80 9294 intel_get_pipe_timings(crtc, pipe_config);
bc58be60 9295 intel_get_pipe_src_size(crtc, pipe_config);
1bd1bd80 9296
2fa2fe9a
DV		 9297 ironlake_get_pfit_config(crtc, pipe_config);
9298
1729050e
ID		 9299 ret = true;
9300
9301out:
9302 intel_display_power_put(dev_priv, power_domain);
9303
9304 return ret;
0e8ffe1b
DV		 9305}
9306
be256dc7
PZ		 9307static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9308{
9309 struct drm_device *dev = dev_priv->dev;
be256dc7 9310 struct intel_crtc *crtc;
be256dc7 9311
d3fcc808 9312 for_each_intel_crtc(dev, crtc)
e2c719b7 9313 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
be256dc7
PZ		 9314 pipe_name(crtc->pipe));
9315
e2c719b7
RC		 9316 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9317 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
01403de3
VS		 9318 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9319 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
e2c719b7
RC		 9320 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9321 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
be256dc7 9322 "CPU PWM1 enabled\n");
c5107b87 9323 if (IS_HASWELL(dev))
e2c719b7 9324 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
c5107b87 9325 "CPU PWM2 enabled\n");
e2c719b7 9326 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
be256dc7 9327 "PCH PWM1 enabled\n");
e2c719b7 9328 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
be256dc7 9329 "Utility pin enabled\n");
e2c719b7 9330 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
be256dc7 9331
9926ada1
PZ		 9332 /*
9333 * In theory we can still leave IRQs enabled, as long as only the HPD
9334 * interrupts remain enabled. We used to check for that, but since it's
9335 * gen-specific and since we only disable LCPLL after we fully disable
9336 * the interrupts, the check below should be enough.
9337 */
e2c719b7 9338 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
be256dc7
PZ		 9339}
9340
9ccd5aeb
PZ		 9341static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9342{
9343 struct drm_device *dev = dev_priv->dev;
9344
9345 if (IS_HASWELL(dev))
9346 return I915_READ(D_COMP_HSW);
9347 else
9348 return I915_READ(D_COMP_BDW);
9349}
9350
3c4c9b81
PZ		 9351static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9352{
9353 struct drm_device *dev = dev_priv->dev;
9354
9355 if (IS_HASWELL(dev)) {
9356 mutex_lock(&dev_priv->rps.hw_lock);
9357 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9358 val))
f475dadf 9359 DRM_ERROR("Failed to write to D_COMP\n");
3c4c9b81
PZ		 9360 mutex_unlock(&dev_priv->rps.hw_lock);
9361 } else {
9ccd5aeb
PZ		 9362 I915_WRITE(D_COMP_BDW, val);
9363 POSTING_READ(D_COMP_BDW);
3c4c9b81 9364 }
be256dc7
PZ		 9365}
9366
9367/*
9368 * This function implements pieces of two sequences from BSpec:
9369 * - Sequence for display software to disable LCPLL
9370 * - Sequence for display software to allow package C8+
9371 * The steps implemented here are just the steps that actually touch the LCPLL
9372 * register. Callers should take care of disabling all the display engine
9373 * functions, doing the mode unset, fixing interrupts, etc.
9374 */
6ff58d53
PZ		 9375static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9376 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ		 9377{
9378 uint32_t val;
9379
9380 assert_can_disable_lcpll(dev_priv);
9381
9382 val = I915_READ(LCPLL_CTL);
9383
9384 if (switch_to_fclk) {
9385 val |= LCPLL_CD_SOURCE_FCLK;
9386 I915_WRITE(LCPLL_CTL, val);
9387
9388 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9389 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9390 DRM_ERROR("Switching to FCLK failed\n");
9391
9392 val = I915_READ(LCPLL_CTL);
9393 }
9394
9395 val |= LCPLL_PLL_DISABLE;
9396 I915_WRITE(LCPLL_CTL, val);
9397 POSTING_READ(LCPLL_CTL);
9398
9399 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9400 DRM_ERROR("LCPLL still locked\n");
9401
9ccd5aeb 9402 val = hsw_read_dcomp(dev_priv);
be256dc7 9403 val |= D_COMP_COMP_DISABLE;
3c4c9b81 9404 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9405 ndelay(100);
9406
9ccd5aeb
PZ		 9407 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9408 1))
be256dc7
PZ		 9409 DRM_ERROR("D_COMP RCOMP still in progress\n");
9410
9411 if (allow_power_down) {
9412 val = I915_READ(LCPLL_CTL);
9413 val |= LCPLL_POWER_DOWN_ALLOW;
9414 I915_WRITE(LCPLL_CTL, val);
9415 POSTING_READ(LCPLL_CTL);
9416 }
9417}
9418
9419/*
9420 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9421 * source.
9422 */
6ff58d53 9423static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ		 9424{
9425 uint32_t val;
9426
9427 val = I915_READ(LCPLL_CTL);
9428
9429 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9430 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9431 return;
9432
a8a8bd54
PZ		 9433 /*
9434 * Make sure we're not on PC8 state before disabling PC8, otherwise
9435 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
a8a8bd54 9436 */
59bad947 9437 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
215733fa 9438
be256dc7
PZ		 9439 if (val & LCPLL_POWER_DOWN_ALLOW) {
9440 val &= ~LCPLL_POWER_DOWN_ALLOW;
9441 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 9442 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 9443 }
9444
9ccd5aeb 9445 val = hsw_read_dcomp(dev_priv);
be256dc7
PZ		 9446 val |= D_COMP_COMP_FORCE;
9447 val &= ~D_COMP_COMP_DISABLE;
3c4c9b81 9448 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9449
9450 val = I915_READ(LCPLL_CTL);
9451 val &= ~LCPLL_PLL_DISABLE;
9452 I915_WRITE(LCPLL_CTL, val);
9453
9454 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9455 DRM_ERROR("LCPLL not locked yet\n");
9456
9457 if (val & LCPLL_CD_SOURCE_FCLK) {
9458 val = I915_READ(LCPLL_CTL);
9459 val &= ~LCPLL_CD_SOURCE_FCLK;
9460 I915_WRITE(LCPLL_CTL, val);
9461
9462 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9463 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9464 DRM_ERROR("Switching back to LCPLL failed\n");
9465 }
215733fa 9466
59bad947 9467 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
b6283055 9468 intel_update_cdclk(dev_priv->dev);
be256dc7
PZ		 9469}
9470
765dab67
PZ		 9471/*
9472 * Package states C8 and deeper are really deep PC states that can only be
9473 * reached when all the devices on the system allow it, so even if the graphics
9474 * device allows PC8+, it doesn't mean the system will actually get to these
9475 * states. Our driver only allows PC8+ when going into runtime PM.
9476 *
9477 * The requirements for PC8+ are that all the outputs are disabled, the power
9478 * well is disabled and most interrupts are disabled, and these are also
9479 * requirements for runtime PM. When these conditions are met, we manually do
9480 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9481 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9482 * hang the machine.
9483 *
9484 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9485 * the state of some registers, so when we come back from PC8+ we need to
9486 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9487 * need to take care of the registers kept by RC6. Notice that this happens even
9488 * if we don't put the device in PCI D3 state (which is what currently happens
9489 * because of the runtime PM support).
9490 *
9491 * For more, read "Display Sequences for Package C8" on the hardware
9492 * documentation.
9493 */
a14cb6fc 9494void hsw_enable_pc8(struct drm_i915_private *dev_priv)
c67a470b 9495{
c67a470b
PZ		 9496 struct drm_device *dev = dev_priv->dev;
9497 uint32_t val;
9498
c67a470b
PZ		 9499 DRM_DEBUG_KMS("Enabling package C8+\n");
9500
c2699524 9501 if (HAS_PCH_LPT_LP(dev)) {
c67a470b
PZ		 9502 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9503 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9504 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9505 }
9506
9507 lpt_disable_clkout_dp(dev);
c67a470b
PZ		 9508 hsw_disable_lcpll(dev_priv, true, true);
9509}
9510
a14cb6fc 9511void hsw_disable_pc8(struct drm_i915_private *dev_priv)
c67a470b
PZ		 9512{
9513 struct drm_device *dev = dev_priv->dev;
9514 uint32_t val;
9515
c67a470b
PZ		 9516 DRM_DEBUG_KMS("Disabling package C8+\n");
9517
9518 hsw_restore_lcpll(dev_priv);
c67a470b
PZ		 9519 lpt_init_pch_refclk(dev);
9520
c2699524 9521 if (HAS_PCH_LPT_LP(dev)) {
c67a470b
PZ		 9522 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9523 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9524 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9525 }
c67a470b
PZ		 9526}
9527
27c329ed 9528static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
f8437dd1 9529{
a821fc46 9530 struct drm_device *dev = old_state->dev;
1a617b77
ML		 9531 struct intel_atomic_state *old_intel_state =
9532 to_intel_atomic_state(old_state);
9533 unsigned int req_cdclk = old_intel_state->dev_cdclk;
f8437dd1 9534
27c329ed 9535 broxton_set_cdclk(dev, req_cdclk);
f8437dd1
VK		 9536}
9537
b432e5cf 9538/* compute the max rate for new configuration */
27c329ed 9539static int ilk_max_pixel_rate(struct drm_atomic_state *state)
b432e5cf 9540{
565602d7
ML		 9541 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9542 struct drm_i915_private *dev_priv = state->dev->dev_private;
9543 struct drm_crtc *crtc;
9544 struct drm_crtc_state *cstate;
27c329ed 9545 struct intel_crtc_state *crtc_state;
565602d7
ML		 9546 unsigned max_pixel_rate = 0, i;
9547 enum pipe pipe;
b432e5cf 9548
565602d7
ML		 9549 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
9550 sizeof(intel_state->min_pixclk));
27c329ed 9551
565602d7
ML		 9552 for_each_crtc_in_state(state, crtc, cstate, i) {
9553 int pixel_rate;
27c329ed 9554
565602d7
ML		 9555 crtc_state = to_intel_crtc_state(cstate);
9556 if (!crtc_state->base.enable) {
9557 intel_state->min_pixclk[i] = 0;
b432e5cf 9558 continue;
565602d7 9559 }
b432e5cf 9560
27c329ed 9561 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
b432e5cf
VS		 9562
9563 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
565602d7 9564 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
b432e5cf
VS		 9565 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9566
565602d7 9567 intel_state->min_pixclk[i] = pixel_rate;
b432e5cf
VS		 9568 }
9569
565602d7
ML		 9570 for_each_pipe(dev_priv, pipe)
9571 max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
9572
b432e5cf
VS		 9573 return max_pixel_rate;
9574}
9575
9576static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9577{
9578 struct drm_i915_private *dev_priv = dev->dev_private;
9579 uint32_t val, data;
9580 int ret;
9581
9582 if (WARN((I915_READ(LCPLL_CTL) &
9583 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9584 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9585 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9586 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9587 "trying to change cdclk frequency with cdclk not enabled\n"))
9588 return;
9589
9590 mutex_lock(&dev_priv->rps.hw_lock);
9591 ret = sandybridge_pcode_write(dev_priv,
9592 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9593 mutex_unlock(&dev_priv->rps.hw_lock);
9594 if (ret) {
9595 DRM_ERROR("failed to inform pcode about cdclk change\n");
9596 return;
9597 }
9598
9599 val = I915_READ(LCPLL_CTL);
9600 val |= LCPLL_CD_SOURCE_FCLK;
9601 I915_WRITE(LCPLL_CTL, val);
9602
5ba00178
TU		 9603 if (wait_for_us(I915_READ(LCPLL_CTL) &
9604 LCPLL_CD_SOURCE_FCLK_DONE, 1))
b432e5cf
VS		 9605 DRM_ERROR("Switching to FCLK failed\n");
9606
9607 val = I915_READ(LCPLL_CTL);
9608 val &= ~LCPLL_CLK_FREQ_MASK;
9609
9610 switch (cdclk) {
9611 case 450000:
9612 val |= LCPLL_CLK_FREQ_450;
9613 data = 0;
9614 break;
9615 case 540000:
9616 val |= LCPLL_CLK_FREQ_54O_BDW;
9617 data = 1;
9618 break;
9619 case 337500:
9620 val |= LCPLL_CLK_FREQ_337_5_BDW;
9621 data = 2;
9622 break;
9623 case 675000:
9624 val |= LCPLL_CLK_FREQ_675_BDW;
9625 data = 3;
9626 break;
9627 default:
9628 WARN(1, "invalid cdclk frequency\n");
9629 return;
9630 }
9631
9632 I915_WRITE(LCPLL_CTL, val);
9633
9634 val = I915_READ(LCPLL_CTL);
9635 val &= ~LCPLL_CD_SOURCE_FCLK;
9636 I915_WRITE(LCPLL_CTL, val);
9637
5ba00178
TU		 9638 if (wait_for_us((I915_READ(LCPLL_CTL) &
9639 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
b432e5cf
VS		 9640 DRM_ERROR("Switching back to LCPLL failed\n");
9641
9642 mutex_lock(&dev_priv->rps.hw_lock);
9643 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9644 mutex_unlock(&dev_priv->rps.hw_lock);
9645
9646 intel_update_cdclk(dev);
9647
9648 WARN(cdclk != dev_priv->cdclk_freq,
9649 "cdclk requested %d kHz but got %d kHz\n",
9650 cdclk, dev_priv->cdclk_freq);
9651}
9652
27c329ed 9653static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
b432e5cf 9654{
27c329ed 9655 struct drm_i915_private *dev_priv = to_i915(state->dev);
1a617b77 9656 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
27c329ed 9657 int max_pixclk = ilk_max_pixel_rate(state);
b432e5cf
VS		 9658 int cdclk;
9659
9660 /*
9661 * FIXME should also account for plane ratio
9662 * once 64bpp pixel formats are supported.
9663 */
27c329ed 9664 if (max_pixclk > 540000)
b432e5cf 9665 cdclk = 675000;
27c329ed 9666 else if (max_pixclk > 450000)
b432e5cf 9667 cdclk = 540000;
27c329ed 9668 else if (max_pixclk > 337500)
b432e5cf
VS		 9669 cdclk = 450000;
9670 else
9671 cdclk = 337500;
9672
b432e5cf 9673 if (cdclk > dev_priv->max_cdclk_freq) {
63ba534e
ML		 9674 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9675 cdclk, dev_priv->max_cdclk_freq);
9676 return -EINVAL;
b432e5cf
VS		 9677 }
9678
1a617b77
ML		 9679 intel_state->cdclk = intel_state->dev_cdclk = cdclk;
9680 if (!intel_state->active_crtcs)
9681 intel_state->dev_cdclk = 337500;
b432e5cf
VS		 9682
9683 return 0;
9684}
9685
27c329ed 9686static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
b432e5cf 9687{
27c329ed 9688 struct drm_device *dev = old_state->dev;
1a617b77
ML		 9689 struct intel_atomic_state *old_intel_state =
9690 to_intel_atomic_state(old_state);
9691 unsigned req_cdclk = old_intel_state->dev_cdclk;
b432e5cf 9692
27c329ed 9693 broadwell_set_cdclk(dev, req_cdclk);
b432e5cf
VS		 9694}
9695
190f68c5
ACO		 9696static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9697 struct intel_crtc_state *crtc_state)
09b4ddf9 9698{
af3997b5
MK		 9699 struct intel_encoder *intel_encoder =
9700 intel_ddi_get_crtc_new_encoder(crtc_state);
9701
9702 if (intel_encoder->type != INTEL_OUTPUT_DSI) {
9703 if (!intel_ddi_pll_select(crtc, crtc_state))
9704 return -EINVAL;
9705 }
716c2e55 9706
c7653199 9707 crtc->lowfreq_avail = false;
644cef34 9708
c8f7a0db 9709 return 0;
79e53945
JB		 9710}
9711
3760b59c
S		 9712static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9713 enum port port,
9714 struct intel_crtc_state *pipe_config)
9715{
8106ddbd
ACO		 9716 enum intel_dpll_id id;
9717
3760b59c
S		 9718 switch (port) {
9719 case PORT_A:
9720 pipe_config->ddi_pll_sel = SKL_DPLL0;
08250c4b 9721 id = DPLL_ID_SKL_DPLL0;
3760b59c
S		 9722 break;
9723 case PORT_B:
9724 pipe_config->ddi_pll_sel = SKL_DPLL1;
08250c4b 9725 id = DPLL_ID_SKL_DPLL1;
3760b59c
S		 9726 break;
9727 case PORT_C:
9728 pipe_config->ddi_pll_sel = SKL_DPLL2;
08250c4b 9729 id = DPLL_ID_SKL_DPLL2;
3760b59c
S		 9730 break;
9731 default:
9732 DRM_ERROR("Incorrect port type\n");
8106ddbd 9733 return;
3760b59c 9734 }
8106ddbd
ACO		 9735
9736 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
3760b59c
S		 9737}
9738
96b7dfb7
S		 9739static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9740 enum port port,
5cec258b 9741 struct intel_crtc_state *pipe_config)
96b7dfb7 9742{
8106ddbd 9743 enum intel_dpll_id id;
a3c988ea 9744 u32 temp;
96b7dfb7
S		 9745
9746 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9747 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9748
9749 switch (pipe_config->ddi_pll_sel) {
3148ade7 9750 case SKL_DPLL0:
a3c988ea
ACO		 9751 id = DPLL_ID_SKL_DPLL0;
9752 break;
96b7dfb7 9753 case SKL_DPLL1:
8106ddbd 9754 id = DPLL_ID_SKL_DPLL1;
96b7dfb7
S		 9755 break;
9756 case SKL_DPLL2:
8106ddbd 9757 id = DPLL_ID_SKL_DPLL2;
96b7dfb7
S		 9758 break;
9759 case SKL_DPLL3:
8106ddbd 9760 id = DPLL_ID_SKL_DPLL3;
96b7dfb7 9761 break;
8106ddbd
ACO		 9762 default:
9763 MISSING_CASE(pipe_config->ddi_pll_sel);
9764 return;
96b7dfb7 9765 }
8106ddbd
ACO		 9766
9767 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
96b7dfb7
S		 9768}
9769
7d2c8175
DL		 9770static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9771 enum port port,
5cec258b 9772 struct intel_crtc_state *pipe_config)
7d2c8175 9773{
8106ddbd
ACO		 9774 enum intel_dpll_id id;
9775
7d2c8175
DL		 9776 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9777
9778 switch (pipe_config->ddi_pll_sel) {
9779 case PORT_CLK_SEL_WRPLL1:
8106ddbd 9780 id = DPLL_ID_WRPLL1;
7d2c8175
DL		 9781 break;
9782 case PORT_CLK_SEL_WRPLL2:
8106ddbd 9783 id = DPLL_ID_WRPLL2;
7d2c8175 9784 break;
00490c22 9785 case PORT_CLK_SEL_SPLL:
8106ddbd 9786 id = DPLL_ID_SPLL;
79bd23da 9787 break;
9d16da65
ACO		 9788 case PORT_CLK_SEL_LCPLL_810:
9789 id = DPLL_ID_LCPLL_810;
9790 break;
9791 case PORT_CLK_SEL_LCPLL_1350:
9792 id = DPLL_ID_LCPLL_1350;
9793 break;
9794 case PORT_CLK_SEL_LCPLL_2700:
9795 id = DPLL_ID_LCPLL_2700;
9796 break;
8106ddbd
ACO		 9797 default:
9798 MISSING_CASE(pipe_config->ddi_pll_sel);
9799 /* fall through */
9800 case PORT_CLK_SEL_NONE:
8106ddbd 9801 return;
7d2c8175 9802 }
8106ddbd
ACO		 9803
9804 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
7d2c8175
DL		 9805}
9806
cf30429e
JN		 9807static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
9808 struct intel_crtc_state *pipe_config,
9809 unsigned long *power_domain_mask)
9810{
9811 struct drm_device *dev = crtc->base.dev;
9812 struct drm_i915_private *dev_priv = dev->dev_private;
9813 enum intel_display_power_domain power_domain;
9814 u32 tmp;
9815
9816 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9817
9818 /*
9819 * XXX: Do intel_display_power_get_if_enabled before reading this (for
9820 * consistency and less surprising code; it's in always on power).
9821 */
9822 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9823 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9824 enum pipe trans_edp_pipe;
9825 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9826 default:
9827 WARN(1, "unknown pipe linked to edp transcoder\n");
9828 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9829 case TRANS_DDI_EDP_INPUT_A_ON:
9830 trans_edp_pipe = PIPE_A;
9831 break;
9832 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9833 trans_edp_pipe = PIPE_B;
9834 break;
9835 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9836 trans_edp_pipe = PIPE_C;
9837 break;
9838 }
9839
9840 if (trans_edp_pipe == crtc->pipe)
9841 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9842 }
9843
9844 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
9845 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9846 return false;
9847 *power_domain_mask |= BIT(power_domain);
9848
9849 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9850
9851 return tmp & PIPECONF_ENABLE;
9852}
9853
4d1de975
JN		 9854static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
9855 struct intel_crtc_state *pipe_config,
9856 unsigned long *power_domain_mask)
9857{
9858 struct drm_device *dev = crtc->base.dev;
9859 struct drm_i915_private *dev_priv = dev->dev_private;
9860 enum intel_display_power_domain power_domain;
9861 enum port port;
9862 enum transcoder cpu_transcoder;
9863 u32 tmp;
9864
9865 pipe_config->has_dsi_encoder = false;
9866
9867 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
9868 if (port == PORT_A)
9869 cpu_transcoder = TRANSCODER_DSI_A;
9870 else
9871 cpu_transcoder = TRANSCODER_DSI_C;
9872
9873 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
9874 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9875 continue;
9876 *power_domain_mask |= BIT(power_domain);
9877
db18b6a6
ID		 9878 /*
9879 * The PLL needs to be enabled with a valid divider
9880 * configuration, otherwise accessing DSI registers will hang
9881 * the machine. See BSpec North Display Engine
9882 * registers/MIPI[BXT]. We can break out here early, since we
9883 * need the same DSI PLL to be enabled for both DSI ports.
9884 */
9885 if (!intel_dsi_pll_is_enabled(dev_priv))
9886 break;
9887
4d1de975
JN		 9888 /* XXX: this works for video mode only */
9889 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
9890 if (!(tmp & DPI_ENABLE))
9891 continue;
9892
9893 tmp = I915_READ(MIPI_CTRL(port));
9894 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
9895 continue;
9896
9897 pipe_config->cpu_transcoder = cpu_transcoder;
9898 pipe_config->has_dsi_encoder = true;
9899 break;
9900 }
9901
9902 return pipe_config->has_dsi_encoder;
9903}
9904
26804afd 9905static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
5cec258b 9906 struct intel_crtc_state *pipe_config)
26804afd
DV		 9907{
9908 struct drm_device *dev = crtc->base.dev;
9909 struct drm_i915_private *dev_priv = dev->dev_private;
d452c5b6 9910 struct intel_shared_dpll *pll;
26804afd
DV		 9911 enum port port;
9912 uint32_t tmp;
9913
9914 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9915
9916 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9917
ef11bdb3 9918 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
96b7dfb7 9919 skylake_get_ddi_pll(dev_priv, port, pipe_config);
3760b59c
S		 9920 else if (IS_BROXTON(dev))
9921 bxt_get_ddi_pll(dev_priv, port, pipe_config);
96b7dfb7
S		 9922 else
9923 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9cd86933 9924
8106ddbd
ACO		 9925 pll = pipe_config->shared_dpll;
9926 if (pll) {
2edd6443
ACO		 9927 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9928 &pipe_config->dpll_hw_state));
d452c5b6
DV		 9929 }
9930
26804afd
DV		 9931 /*
9932 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9933 * DDI E. So just check whether this pipe is wired to DDI E and whether
9934 * the PCH transcoder is on.
9935 */
ca370455
DL		 9936 if (INTEL_INFO(dev)->gen < 9 &&
9937 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
26804afd
DV		 9938 pipe_config->has_pch_encoder = true;
9939
9940 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9941 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9942 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9943
9944 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9945 }
9946}
9947
0e8ffe1b 9948static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9949 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9950{
9951 struct drm_device *dev = crtc->base.dev;
9952 struct drm_i915_private *dev_priv = dev->dev_private;
1729050e
ID		 9953 enum intel_display_power_domain power_domain;
9954 unsigned long power_domain_mask;
cf30429e 9955 bool active;
0e8ffe1b 9956
1729050e
ID		 9957 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9958 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
b5482bd0 9959 return false;
1729050e
ID		 9960 power_domain_mask = BIT(power_domain);
9961
8106ddbd 9962 pipe_config->shared_dpll = NULL;
c0d43d62 9963
cf30429e 9964 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
eccb140b 9965
4d1de975
JN		 9966 if (IS_BROXTON(dev_priv)) {
9967 bxt_get_dsi_transcoder_state(crtc, pipe_config,
9968 &power_domain_mask);
9969 WARN_ON(active && pipe_config->has_dsi_encoder);
9970 if (pipe_config->has_dsi_encoder)
9971 active = true;
9972 }
9973
cf30429e 9974 if (!active)
1729050e 9975 goto out;
0e8ffe1b 9976
4d1de975
JN		 9977 if (!pipe_config->has_dsi_encoder) {
9978 haswell_get_ddi_port_state(crtc, pipe_config);
9979 intel_get_pipe_timings(crtc, pipe_config);
9980 }
627eb5a3 9981
bc58be60 9982 intel_get_pipe_src_size(crtc, pipe_config);
1bd1bd80 9983
05dc698c
LL		 9984 pipe_config->gamma_mode =
9985 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
9986
a1b2278e
CK		 9987 if (INTEL_INFO(dev)->gen >= 9) {
9988 skl_init_scalers(dev, crtc, pipe_config);
9989 }
9990
af99ceda
CK		 9991 if (INTEL_INFO(dev)->gen >= 9) {
9992 pipe_config->scaler_state.scaler_id = -1;
9993 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9994 }
9995
1729050e
ID		 9996 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9997 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
9998 power_domain_mask |= BIT(power_domain);
1c132b44 9999 if (INTEL_INFO(dev)->gen >= 9)
bd2e244f 10000 skylake_get_pfit_config(crtc, pipe_config);
ff6d9f55 10001 else
1c132b44 10002 ironlake_get_pfit_config(crtc, pipe_config);
bd2e244f 10003 }
88adfff1 10004
e59150dc
JB		 10005 if (IS_HASWELL(dev))
10006 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
10007 (I915_READ(IPS_CTL) & IPS_ENABLE);
42db64ef 10008
4d1de975
JN		 10009 if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
10010 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
ebb69c95
CT		 10011 pipe_config->pixel_multiplier =
10012 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10013 } else {
10014 pipe_config->pixel_multiplier = 1;
10015 }
6c49f241 10016
1729050e
ID		 10017out:
10018 for_each_power_domain(power_domain, power_domain_mask)
10019 intel_display_power_put(dev_priv, power_domain);
10020
cf30429e 10021 return active;
0e8ffe1b
DV		 10022}
10023
55a08b3f
ML		 10024static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
10025 const struct intel_plane_state *plane_state)
560b85bb
CW		 10026{
10027 struct drm_device *dev = crtc->dev;
10028 struct drm_i915_private *dev_priv = dev->dev_private;
10029 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dc41c154 10030 uint32_t cntl = 0, size = 0;
560b85bb 10031
55a08b3f
ML		 10032 if (plane_state && plane_state->visible) {
10033 unsigned int width = plane_state->base.crtc_w;
10034 unsigned int height = plane_state->base.crtc_h;
dc41c154
VS		 10035 unsigned int stride = roundup_pow_of_two(width) * 4;
10036
10037 switch (stride) {
10038 default:
10039 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10040 width, stride);
10041 stride = 256;
10042 /* fallthrough */
10043 case 256:
10044 case 512:
10045 case 1024:
10046 case 2048:
10047 break;
4b0e333e
CW		 10048 }
10049
dc41c154
VS		 10050 cntl |= CURSOR_ENABLE |
10051 CURSOR_GAMMA_ENABLE |
10052 CURSOR_FORMAT_ARGB |
10053 CURSOR_STRIDE(stride);
10054
10055 size = (height << 12) | width;
4b0e333e 10056 }
560b85bb 10057
dc41c154
VS		 10058 if (intel_crtc->cursor_cntl != 0 &&
10059 (intel_crtc->cursor_base != base ||
10060 intel_crtc->cursor_size != size ||
10061 intel_crtc->cursor_cntl != cntl)) {
10062 /* On these chipsets we can only modify the base/size/stride
10063 * whilst the cursor is disabled.
10064 */
0b87c24e
VS		 10065 I915_WRITE(CURCNTR(PIPE_A), 0);
10066 POSTING_READ(CURCNTR(PIPE_A));
dc41c154 10067 intel_crtc->cursor_cntl = 0;
4b0e333e 10068 }
560b85bb 10069
99d1f387 10070 if (intel_crtc->cursor_base != base) {
0b87c24e 10071 I915_WRITE(CURBASE(PIPE_A), base);
99d1f387
VS		 10072 intel_crtc->cursor_base = base;
10073 }
4726e0b0 10074
dc41c154
VS		 10075 if (intel_crtc->cursor_size != size) {
10076 I915_WRITE(CURSIZE, size);
10077 intel_crtc->cursor_size = size;
4b0e333e 10078 }
560b85bb 10079
4b0e333e 10080 if (intel_crtc->cursor_cntl != cntl) {
0b87c24e
VS		 10081 I915_WRITE(CURCNTR(PIPE_A), cntl);
10082 POSTING_READ(CURCNTR(PIPE_A));
4b0e333e 10083 intel_crtc->cursor_cntl = cntl;
560b85bb 10084 }
560b85bb
CW		 10085}
10086
55a08b3f
ML		 10087static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
10088 const struct intel_plane_state *plane_state)
65a21cd6
JB		 10089{
10090 struct drm_device *dev = crtc->dev;
10091 struct drm_i915_private *dev_priv = dev->dev_private;
10092 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10093 int pipe = intel_crtc->pipe;
663f3122 10094 uint32_t cntl = 0;
4b0e333e 10095
55a08b3f 10096 if (plane_state && plane_state->visible) {
4b0e333e 10097 cntl = MCURSOR_GAMMA_ENABLE;
55a08b3f 10098 switch (plane_state->base.crtc_w) {
4726e0b0
SK		 10099 case 64:
10100 cntl |= CURSOR_MODE_64_ARGB_AX;
10101 break;
10102 case 128:
10103 cntl |= CURSOR_MODE_128_ARGB_AX;
10104 break;
10105 case 256:
10106 cntl |= CURSOR_MODE_256_ARGB_AX;
10107 break;
10108 default:
55a08b3f 10109 MISSING_CASE(plane_state->base.crtc_w);
4726e0b0 10110 return;
65a21cd6 10111 }
4b0e333e 10112 cntl |= pipe << 28; /* Connect to correct pipe */
47bf17a7 10113
fc6f93bc 10114 if (HAS_DDI(dev))
47bf17a7 10115 cntl |= CURSOR_PIPE_CSC_ENABLE;
65a21cd6 10116
55a08b3f
ML		 10117 if (plane_state->base.rotation == BIT(DRM_ROTATE_180))
10118 cntl |= CURSOR_ROTATE_180;
10119 }
4398ad45 10120
4b0e333e
CW		 10121 if (intel_crtc->cursor_cntl != cntl) {
10122 I915_WRITE(CURCNTR(pipe), cntl);
10123 POSTING_READ(CURCNTR(pipe));
10124 intel_crtc->cursor_cntl = cntl;
65a21cd6 10125 }
4b0e333e 10126
65a21cd6 10127 /* and commit changes on next vblank */
5efb3e28
VS		 10128 I915_WRITE(CURBASE(pipe), base);
10129 POSTING_READ(CURBASE(pipe));
99d1f387
VS		 10130
10131 intel_crtc->cursor_base = base;
65a21cd6
JB		 10132}
10133
cda4b7d3 10134/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f 10135static void intel_crtc_update_cursor(struct drm_crtc *crtc,
55a08b3f 10136 const struct intel_plane_state *plane_state)
cda4b7d3
CW		 10137{
10138 struct drm_device *dev = crtc->dev;
10139 struct drm_i915_private *dev_priv = dev->dev_private;
10140 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10141 int pipe = intel_crtc->pipe;
55a08b3f
ML		 10142 u32 base = intel_crtc->cursor_addr;
10143 u32 pos = 0;
cda4b7d3 10144
55a08b3f
ML		 10145 if (plane_state) {
10146 int x = plane_state->base.crtc_x;
10147 int y = plane_state->base.crtc_y;
cda4b7d3 10148
55a08b3f
ML		 10149 if (x < 0) {
10150 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10151 x = -x;
10152 }
10153 pos |= x << CURSOR_X_SHIFT;
cda4b7d3 10154
55a08b3f
ML		 10155 if (y < 0) {
10156 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10157 y = -y;
10158 }
10159 pos |= y << CURSOR_Y_SHIFT;
10160
10161 /* ILK+ do this automagically */
10162 if (HAS_GMCH_DISPLAY(dev) &&
10163 plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
10164 base += (plane_state->base.crtc_h *
10165 plane_state->base.crtc_w - 1) * 4;
10166 }
cda4b7d3 10167 }
cda4b7d3 10168
5efb3e28
VS		 10169 I915_WRITE(CURPOS(pipe), pos);
10170
8ac54669 10171 if (IS_845G(dev) || IS_I865G(dev))
55a08b3f 10172 i845_update_cursor(crtc, base, plane_state);
5efb3e28 10173 else
55a08b3f 10174 i9xx_update_cursor(crtc, base, plane_state);
cda4b7d3
CW		 10175}
10176
dc41c154
VS		 10177static bool cursor_size_ok(struct drm_device *dev,
10178 uint32_t width, uint32_t height)
10179{
10180 if (width == 0 || height == 0)
10181 return false;
10182
10183 /*
10184 * 845g/865g are special in that they are only limited by
10185 * the width of their cursors, the height is arbitrary up to
10186 * the precision of the register. Everything else requires
10187 * square cursors, limited to a few power-of-two sizes.
10188 */
10189 if (IS_845G(dev) || IS_I865G(dev)) {
10190 if ((width & 63) != 0)
10191 return false;
10192
10193 if (width > (IS_845G(dev) ? 64 : 512))
10194 return false;
10195
10196 if (height > 1023)
10197 return false;
10198 } else {
10199 switch (width | height) {
10200 case 256:
10201 case 128:
10202 if (IS_GEN2(dev))
10203 return false;
10204 case 64:
10205 break;
10206 default:
10207 return false;
10208 }
10209 }
10210
10211 return true;
10212}
10213
79e53945
JB		 10214/* VESA 640x480x72Hz mode to set on the pipe */
10215static struct drm_display_mode load_detect_mode = {
10216 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10217 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10218};
10219
a8bb6818
DV		 10220struct drm_framebuffer *
10221__intel_framebuffer_create(struct drm_device *dev,
10222 struct drm_mode_fb_cmd2 *mode_cmd,
10223 struct drm_i915_gem_object *obj)
d2dff872
CW		 10224{
10225 struct intel_framebuffer *intel_fb;
10226 int ret;
10227
10228 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
dcb1394e 10229 if (!intel_fb)
d2dff872 10230 return ERR_PTR(-ENOMEM);
d2dff872
CW		 10231
10232 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
dd4916c5
DV		 10233 if (ret)
10234 goto err;
d2dff872
CW		 10235
10236 return &intel_fb->base;
dcb1394e 10237
dd4916c5 10238err:
dd4916c5 10239 kfree(intel_fb);
dd4916c5 10240 return ERR_PTR(ret);
d2dff872
CW		 10241}
10242
b5ea642a 10243static struct drm_framebuffer *
a8bb6818
DV		 10244intel_framebuffer_create(struct drm_device *dev,
10245 struct drm_mode_fb_cmd2 *mode_cmd,
10246 struct drm_i915_gem_object *obj)
10247{
10248 struct drm_framebuffer *fb;
10249 int ret;
10250
10251 ret = i915_mutex_lock_interruptible(dev);
10252 if (ret)
10253 return ERR_PTR(ret);
10254 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10255 mutex_unlock(&dev->struct_mutex);
10256
10257 return fb;
10258}
10259
d2dff872
CW		 10260static u32
10261intel_framebuffer_pitch_for_width(int width, int bpp)
10262{
10263 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10264 return ALIGN(pitch, 64);
10265}
10266
10267static u32
10268intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10269{
10270 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
1267a26b 10271 return PAGE_ALIGN(pitch * mode->vdisplay);
d2dff872
CW		 10272}
10273
10274static struct drm_framebuffer *
10275intel_framebuffer_create_for_mode(struct drm_device *dev,
10276 struct drm_display_mode *mode,
10277 int depth, int bpp)
10278{
dcb1394e 10279 struct drm_framebuffer *fb;
d2dff872 10280 struct drm_i915_gem_object *obj;
0fed39bd 10281 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 10282
10283 obj = i915_gem_alloc_object(dev,
10284 intel_framebuffer_size_for_mode(mode, bpp));
10285 if (obj == NULL)
10286 return ERR_PTR(-ENOMEM);
10287
10288 mode_cmd.width = mode->hdisplay;
10289 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 10290 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10291 bpp);
5ca0c34a 10292 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872 10293
dcb1394e
LW		 10294 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
10295 if (IS_ERR(fb))
10296 drm_gem_object_unreference_unlocked(&obj->base);
10297
10298 return fb;
d2dff872
CW		 10299}
10300
10301static struct drm_framebuffer *
10302mode_fits_in_fbdev(struct drm_device *dev,
10303 struct drm_display_mode *mode)
10304{
0695726e 10305#ifdef CONFIG_DRM_FBDEV_EMULATION
d2dff872
CW		 10306 struct drm_i915_private *dev_priv = dev->dev_private;
10307 struct drm_i915_gem_object *obj;
10308 struct drm_framebuffer *fb;
10309
4c0e5528 10310 if (!dev_priv->fbdev)
d2dff872
CW		 10311 return NULL;
10312
4c0e5528 10313 if (!dev_priv->fbdev->fb)
d2dff872
CW		 10314 return NULL;
10315
4c0e5528
DV		 10316 obj = dev_priv->fbdev->fb->obj;
10317 BUG_ON(!obj);
10318
8bcd4553 10319 fb = &dev_priv->fbdev->fb->base;
01f2c773
VS		 10320 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10321 fb->bits_per_pixel))
d2dff872
CW		 10322 return NULL;
10323
01f2c773 10324 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 10325 return NULL;
10326
edde3617 10327 drm_framebuffer_reference(fb);
d2dff872 10328 return fb;
4520f53a
DV		 10329#else
10330 return NULL;
10331#endif
d2dff872
CW		 10332}
10333
d3a40d1b
ACO		 10334static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10335 struct drm_crtc *crtc,
10336 struct drm_display_mode *mode,
10337 struct drm_framebuffer *fb,
10338 int x, int y)
10339{
10340 struct drm_plane_state *plane_state;
10341 int hdisplay, vdisplay;
10342 int ret;
10343
10344 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10345 if (IS_ERR(plane_state))
10346 return PTR_ERR(plane_state);
10347
10348 if (mode)
10349 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10350 else
10351 hdisplay = vdisplay = 0;
10352
10353 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10354 if (ret)
10355 return ret;
10356 drm_atomic_set_fb_for_plane(plane_state, fb);
10357 plane_state->crtc_x = 0;
10358 plane_state->crtc_y = 0;
10359 plane_state->crtc_w = hdisplay;
10360 plane_state->crtc_h = vdisplay;
10361 plane_state->src_x = x << 16;
10362 plane_state->src_y = y << 16;
10363 plane_state->src_w = hdisplay << 16;
10364 plane_state->src_h = vdisplay << 16;
10365
10366 return 0;
10367}
10368
d2434ab7 10369bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 10370 struct drm_display_mode *mode,
51fd371b
RC		 10371 struct intel_load_detect_pipe *old,
10372 struct drm_modeset_acquire_ctx *ctx)
79e53945
JB		 10373{
10374 struct intel_crtc *intel_crtc;
d2434ab7
DV		 10375 struct intel_encoder *intel_encoder =
10376 intel_attached_encoder(connector);
79e53945 10377 struct drm_crtc *possible_crtc;
4ef69c7a 10378 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 10379 struct drm_crtc *crtc = NULL;
10380 struct drm_device *dev = encoder->dev;
94352cf9 10381 struct drm_framebuffer *fb;
51fd371b 10382 struct drm_mode_config *config = &dev->mode_config;
edde3617 10383 struct drm_atomic_state *state = NULL, *restore_state = NULL;
944b0c76 10384 struct drm_connector_state *connector_state;
4be07317 10385 struct intel_crtc_state *crtc_state;
51fd371b 10386 int ret, i = -1;
79e53945 10387
d2dff872 10388 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10389 connector->base.id, connector->name,
8e329a03 10390 encoder->base.id, encoder->name);
d2dff872 10391
edde3617
ML		 10392 old->restore_state = NULL;
10393
51fd371b
RC		 10394retry:
10395 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10396 if (ret)
ad3c558f 10397 goto fail;
6e9f798d 10398
79e53945
JB		 10399 /*
10400 * Algorithm gets a little messy:
7a5e4805 10401 *
79e53945
JB		 10402 * - if the connector already has an assigned crtc, use it (but make
10403 * sure it's on first)
7a5e4805 10404 *
79e53945
JB		 10405 * - try to find the first unused crtc that can drive this connector,
10406 * and use that if we find one
79e53945
JB		 10407 */
10408
10409 /* See if we already have a CRTC for this connector */
edde3617
ML		 10410 if (connector->state->crtc) {
10411 crtc = connector->state->crtc;
8261b191 10412
51fd371b 10413 ret = drm_modeset_lock(&crtc->mutex, ctx);
4d02e2de 10414 if (ret)
ad3c558f 10415 goto fail;
8261b191
CW		 10416
10417 /* Make sure the crtc and connector are running */
edde3617 10418 goto found;
79e53945
JB		 10419 }
10420
10421 /* Find an unused one (if possible) */
70e1e0ec 10422 for_each_crtc(dev, possible_crtc) {
79e53945
JB		 10423 i++;
10424 if (!(encoder->possible_crtcs & (1 << i)))
10425 continue;
edde3617
ML		 10426
10427 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
10428 if (ret)
10429 goto fail;
10430
10431 if (possible_crtc->state->enable) {
10432 drm_modeset_unlock(&possible_crtc->mutex);
a459249c 10433 continue;
edde3617 10434 }
a459249c
VS		 10435
10436 crtc = possible_crtc;
10437 break;
79e53945
JB		 10438 }
10439
10440 /*
10441 * If we didn't find an unused CRTC, don't use any.
10442 */
10443 if (!crtc) {
7173188d 10444 DRM_DEBUG_KMS("no pipe available for load-detect\n");
ad3c558f 10445 goto fail;
79e53945
JB		 10446 }
10447
edde3617
ML		 10448found:
10449 intel_crtc = to_intel_crtc(crtc);
10450
4d02e2de
DV		 10451 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10452 if (ret)
ad3c558f 10453 goto fail;
79e53945 10454
83a57153 10455 state = drm_atomic_state_alloc(dev);
edde3617
ML		 10456 restore_state = drm_atomic_state_alloc(dev);
10457 if (!state || !restore_state) {
10458 ret = -ENOMEM;
10459 goto fail;
10460 }
83a57153
ACO		 10461
10462 state->acquire_ctx = ctx;
edde3617 10463 restore_state->acquire_ctx = ctx;
83a57153 10464
944b0c76
ACO		 10465 connector_state = drm_atomic_get_connector_state(state, connector);
10466 if (IS_ERR(connector_state)) {
10467 ret = PTR_ERR(connector_state);
10468 goto fail;
10469 }
10470
edde3617
ML		 10471 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
10472 if (ret)
10473 goto fail;
944b0c76 10474
4be07317
ACO		 10475 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10476 if (IS_ERR(crtc_state)) {
10477 ret = PTR_ERR(crtc_state);
10478 goto fail;
10479 }
10480
49d6fa21 10481 crtc_state->base.active = crtc_state->base.enable = true;
4be07317 10482
6492711d
CW		 10483 if (!mode)
10484 mode = &load_detect_mode;
79e53945 10485
d2dff872
CW		 10486 /* We need a framebuffer large enough to accommodate all accesses
10487 * that the plane may generate whilst we perform load detection.
10488 * We can not rely on the fbcon either being present (we get called
10489 * during its initialisation to detect all boot displays, or it may
10490 * not even exist) or that it is large enough to satisfy the
10491 * requested mode.
10492 */
94352cf9
DV		 10493 fb = mode_fits_in_fbdev(dev, mode);
10494 if (fb == NULL) {
d2dff872 10495 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9 10496 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
d2dff872
CW		 10497 } else
10498 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 10499 if (IS_ERR(fb)) {
d2dff872 10500 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
412b61d8 10501 goto fail;
79e53945 10502 }
79e53945 10503
d3a40d1b
ACO		 10504 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10505 if (ret)
10506 goto fail;
10507
edde3617
ML		 10508 drm_framebuffer_unreference(fb);
10509
10510 ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
10511 if (ret)
10512 goto fail;
10513
10514 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
10515 if (!ret)
10516 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
10517 if (!ret)
10518 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
10519 if (ret) {
10520 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
10521 goto fail;
10522 }
8c7b5ccb 10523
3ba86073
ML		 10524 ret = drm_atomic_commit(state);
10525 if (ret) {
6492711d 10526 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
412b61d8 10527 goto fail;
79e53945 10528 }
edde3617
ML		 10529
10530 old->restore_state = restore_state;
7173188d 10531
79e53945 10532 /* let the connector get through one full cycle before testing */
9d0498a2 10533 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 10534 return true;
412b61d8 10535
ad3c558f 10536fail:
e5d958ef 10537 drm_atomic_state_free(state);
edde3617
ML		 10538 drm_atomic_state_free(restore_state);
10539 restore_state = state = NULL;
83a57153 10540
51fd371b
RC		 10541 if (ret == -EDEADLK) {
10542 drm_modeset_backoff(ctx);
10543 goto retry;
10544 }
10545
412b61d8 10546 return false;
79e53945
JB		 10547}
10548
d2434ab7 10549void intel_release_load_detect_pipe(struct drm_connector *connector,
49172fee
ACO		 10550 struct intel_load_detect_pipe *old,
10551 struct drm_modeset_acquire_ctx *ctx)
79e53945 10552{
d2434ab7
DV		 10553 struct intel_encoder *intel_encoder =
10554 intel_attached_encoder(connector);
4ef69c7a 10555 struct drm_encoder *encoder = &intel_encoder->base;
edde3617 10556 struct drm_atomic_state *state = old->restore_state;
d3a40d1b 10557 int ret;
79e53945 10558
d2dff872 10559 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10560 connector->base.id, connector->name,
8e329a03 10561 encoder->base.id, encoder->name);
d2dff872 10562
edde3617 10563 if (!state)
0622a53c 10564 return;
79e53945 10565
edde3617
ML		 10566 ret = drm_atomic_commit(state);
10567 if (ret) {
10568 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
10569 drm_atomic_state_free(state);
10570 }
79e53945
JB		 10571}
10572
da4a1efa 10573static int i9xx_pll_refclk(struct drm_device *dev,
5cec258b 10574 const struct intel_crtc_state *pipe_config)
da4a1efa
VS		 10575{
10576 struct drm_i915_private *dev_priv = dev->dev_private;
10577 u32 dpll = pipe_config->dpll_hw_state.dpll;
10578
10579 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
e91e941b 10580 return dev_priv->vbt.lvds_ssc_freq;
da4a1efa
VS		 10581 else if (HAS_PCH_SPLIT(dev))
10582 return 120000;
10583 else if (!IS_GEN2(dev))
10584 return 96000;
10585 else
10586 return 48000;
10587}
10588
79e53945 10589/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc 10590static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 10591 struct intel_crtc_state *pipe_config)
79e53945 10592{
f1f644dc 10593 struct drm_device *dev = crtc->base.dev;
79e53945 10594 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 10595 int pipe = pipe_config->cpu_transcoder;
293623f7 10596 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 10597 u32 fp;
10598 intel_clock_t clock;
dccbea3b 10599 int port_clock;
da4a1efa 10600 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 10601
10602 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 10603 fp = pipe_config->dpll_hw_state.fp0;
79e53945 10604 else
293623f7 10605 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 10606
10607 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 10608 if (IS_PINEVIEW(dev)) {
10609 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10610 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 10611 } else {
10612 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10613 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10614 }
10615
a6c45cf0 10616 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 10617 if (IS_PINEVIEW(dev))
10618 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10619 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 10620 else
10621 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 10622 DPLL_FPA01_P1_POST_DIV_SHIFT);
10623
10624 switch (dpll & DPLL_MODE_MASK) {
10625 case DPLLB_MODE_DAC_SERIAL:
10626 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10627 5 : 10;
10628 break;
10629 case DPLLB_MODE_LVDS:
10630 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10631 7 : 14;
10632 break;
10633 default:
28c97730 10634 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 10635 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 10636 return;
79e53945
JB		 10637 }
10638
ac58c3f0 10639 if (IS_PINEVIEW(dev))
dccbea3b 10640 port_clock = pnv_calc_dpll_params(refclk, &clock);
ac58c3f0 10641 else
dccbea3b 10642 port_clock = i9xx_calc_dpll_params(refclk, &clock);
79e53945 10643 } else {
0fb58223 10644 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
b1c560d1 10645 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
79e53945
JB		 10646
10647 if (is_lvds) {
10648 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10649 DPLL_FPA01_P1_POST_DIV_SHIFT);
b1c560d1
VS		 10650
10651 if (lvds & LVDS_CLKB_POWER_UP)
10652 clock.p2 = 7;
10653 else
10654 clock.p2 = 14;
79e53945
JB		 10655 } else {
10656 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10657 clock.p1 = 2;
10658 else {
10659 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10660 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10661 }
10662 if (dpll & PLL_P2_DIVIDE_BY_4)
10663 clock.p2 = 4;
10664 else
10665 clock.p2 = 2;
79e53945 10666 }
da4a1efa 10667
dccbea3b 10668 port_clock = i9xx_calc_dpll_params(refclk, &clock);
79e53945
JB		 10669 }
10670
18442d08
VS		 10671 /*
10672 * This value includes pixel_multiplier. We will use
241bfc38 10673 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS		 10674 * encoder's get_config() function.
10675 */
dccbea3b 10676 pipe_config->port_clock = port_clock;
f1f644dc
JB		 10677}
10678
6878da05
VS		 10679int intel_dotclock_calculate(int link_freq,
10680 const struct intel_link_m_n *m_n)
f1f644dc 10681{
f1f644dc
JB		 10682 /*
10683 * The calculation for the data clock is:
1041a02f 10684 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 10685 * But we want to avoid losing precison if possible, so:
1041a02f 10686 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 10687 *
10688 * and the link clock is simpler:
1041a02f 10689 * link_clock = (m * link_clock) / n
f1f644dc
JB		 10690 */
10691
6878da05
VS		 10692 if (!m_n->link_n)
10693 return 0;
f1f644dc 10694
6878da05
VS		 10695 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10696}
f1f644dc 10697
18442d08 10698static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 10699 struct intel_crtc_state *pipe_config)
6878da05 10700{
e3b247da 10701 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
79e53945 10702
18442d08
VS		 10703 /* read out port_clock from the DPLL */
10704 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 10705
f1f644dc 10706 /*
e3b247da
VS		 10707 * In case there is an active pipe without active ports,
10708 * we may need some idea for the dotclock anyway.
10709 * Calculate one based on the FDI configuration.
79e53945 10710 */
2d112de7 10711 pipe_config->base.adjusted_mode.crtc_clock =
21a727b3 10712 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
18442d08 10713 &pipe_config->fdi_m_n);
79e53945
JB		 10714}
10715
10716/** Returns the currently programmed mode of the given pipe. */
10717struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10718 struct drm_crtc *crtc)
10719{
548f245b 10720 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 10721 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 10722 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
79e53945 10723 struct drm_display_mode *mode;
3f36b937 10724 struct intel_crtc_state *pipe_config;
fe2b8f9d
PZ		 10725 int htot = I915_READ(HTOTAL(cpu_transcoder));
10726 int hsync = I915_READ(HSYNC(cpu_transcoder));
10727 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10728 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 10729 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 10730
10731 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10732 if (!mode)
10733 return NULL;
10734
3f36b937
TU		 10735 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10736 if (!pipe_config) {
10737 kfree(mode);
10738 return NULL;
10739 }
10740
f1f644dc
JB		 10741 /*
10742 * Construct a pipe_config sufficient for getting the clock info
10743 * back out of crtc_clock_get.
10744 *
10745 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10746 * to use a real value here instead.
10747 */
3f36b937
TU		 10748 pipe_config->cpu_transcoder = (enum transcoder) pipe;
10749 pipe_config->pixel_multiplier = 1;
10750 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10751 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10752 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10753 i9xx_crtc_clock_get(intel_crtc, pipe_config);
10754
10755 mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
79e53945
JB		 10756 mode->hdisplay = (htot & 0xffff) + 1;
10757 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10758 mode->hsync_start = (hsync & 0xffff) + 1;
10759 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10760 mode->vdisplay = (vtot & 0xffff) + 1;
10761 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10762 mode->vsync_start = (vsync & 0xffff) + 1;
10763 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10764
10765 drm_mode_set_name(mode);
79e53945 10766
3f36b937
TU		 10767 kfree(pipe_config);
10768
79e53945
JB		 10769 return mode;
10770}
10771
f047e395
CW		 10772void intel_mark_busy(struct drm_device *dev)
10773{
c67a470b
PZ		 10774 struct drm_i915_private *dev_priv = dev->dev_private;
10775
f62a0076
CW		 10776 if (dev_priv->mm.busy)
10777 return;
10778
43694d69 10779 intel_runtime_pm_get(dev_priv);
c67a470b 10780 i915_update_gfx_val(dev_priv);
43cf3bf0
CW		 10781 if (INTEL_INFO(dev)->gen >= 6)
10782 gen6_rps_busy(dev_priv);
f62a0076 10783 dev_priv->mm.busy = true;
f047e395
CW		 10784}
10785
10786void intel_mark_idle(struct drm_device *dev)
652c393a 10787{
c67a470b 10788 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 10789
f62a0076
CW		 10790 if (!dev_priv->mm.busy)
10791 return;
10792
10793 dev_priv->mm.busy = false;
10794
3d13ef2e 10795 if (INTEL_INFO(dev)->gen >= 6)
b29c19b6 10796 gen6_rps_idle(dev->dev_private);
bb4cdd53 10797
43694d69 10798 intel_runtime_pm_put(dev_priv);
652c393a
JB		 10799}
10800
79e53945
JB		 10801static void intel_crtc_destroy(struct drm_crtc *crtc)
10802{
10803 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 10804 struct drm_device *dev = crtc->dev;
10805 struct intel_unpin_work *work;
67e77c5a 10806
5e2d7afc 10807 spin_lock_irq(&dev->event_lock);
67e77c5a
DV		 10808 work = intel_crtc->unpin_work;
10809 intel_crtc->unpin_work = NULL;
5e2d7afc 10810 spin_unlock_irq(&dev->event_lock);
67e77c5a
DV		 10811
10812 if (work) {
10813 cancel_work_sync(&work->work);
10814 kfree(work);
10815 }
79e53945
JB		 10816
10817 drm_crtc_cleanup(crtc);
67e77c5a 10818
79e53945
JB		 10819 kfree(intel_crtc);
10820}
10821
6b95a207
KH		 10822static void intel_unpin_work_fn(struct work_struct *__work)
10823{
10824 struct intel_unpin_work *work =
10825 container_of(__work, struct intel_unpin_work, work);
a9ff8714
VS		 10826 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10827 struct drm_device *dev = crtc->base.dev;
10828 struct drm_plane *primary = crtc->base.primary;
6b95a207 10829
b4a98e57 10830 mutex_lock(&dev->struct_mutex);
3465c580 10831 intel_unpin_fb_obj(work->old_fb, primary->state->rotation);
05394f39 10832 drm_gem_object_unreference(&work->pending_flip_obj->base);
d9e86c0e 10833
f06cc1b9 10834 if (work->flip_queued_req)
146d84f0 10835 i915_gem_request_assign(&work->flip_queued_req, NULL);
b4a98e57
CW		 10836 mutex_unlock(&dev->struct_mutex);
10837
a9ff8714 10838 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
1eb52238 10839 intel_fbc_post_update(crtc);
89ed88ba 10840 drm_framebuffer_unreference(work->old_fb);
f99d7069 10841
a9ff8714
VS		 10842 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10843 atomic_dec(&crtc->unpin_work_count);
b4a98e57 10844
6b95a207
KH		 10845 kfree(work);
10846}
10847
1afe3e9d 10848static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 10849 struct drm_crtc *crtc)
6b95a207 10850{
6b95a207
KH		 10851 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10852 struct intel_unpin_work *work;
6b95a207
KH		 10853 unsigned long flags;
10854
10855 /* Ignore early vblank irqs */
10856 if (intel_crtc == NULL)
10857 return;
10858
f326038a
DV		 10859 /*
10860 * This is called both by irq handlers and the reset code (to complete
10861 * lost pageflips) so needs the full irqsave spinlocks.
10862 */
6b95a207
KH		 10863 spin_lock_irqsave(&dev->event_lock, flags);
10864 work = intel_crtc->unpin_work;
e7d841ca
CW		 10865
10866 /* Ensure we don't miss a work->pending update ... */
10867 smp_rmb();
10868
10869 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 10870 spin_unlock_irqrestore(&dev->event_lock, flags);
10871 return;
10872 }
10873
d6bbafa1 10874 page_flip_completed(intel_crtc);
0af7e4df 10875
6b95a207 10876 spin_unlock_irqrestore(&dev->event_lock, flags);
6b95a207
KH		 10877}
10878
1afe3e9d
JB		 10879void intel_finish_page_flip(struct drm_device *dev, int pipe)
10880{
fbee40df 10881 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10882 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10883
49b14a5c 10884 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10885}
10886
10887void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10888{
fbee40df 10889 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10890 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10891
49b14a5c 10892 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10893}
10894
75f7f3ec
VS		 10895/* Is 'a' after or equal to 'b'? */
10896static bool g4x_flip_count_after_eq(u32 a, u32 b)
10897{
10898 return !((a - b) & 0x80000000);
10899}
10900
10901static bool page_flip_finished(struct intel_crtc *crtc)
10902{
10903 struct drm_device *dev = crtc->base.dev;
10904 struct drm_i915_private *dev_priv = dev->dev_private;
10905
bdfa7542
VS		 10906 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10907 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10908 return true;
10909
75f7f3ec
VS		 10910 /*
10911 * The relevant registers doen't exist on pre-ctg.
10912 * As the flip done interrupt doesn't trigger for mmio
10913 * flips on gmch platforms, a flip count check isn't
10914 * really needed there. But since ctg has the registers,
10915 * include it in the check anyway.
10916 */
10917 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10918 return true;
10919
e8861675
ML		 10920 /*
10921 * BDW signals flip done immediately if the plane
10922 * is disabled, even if the plane enable is already
10923 * armed to occur at the next vblank :(
10924 */
10925
75f7f3ec
VS		 10926 /*
10927 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10928 * used the same base address. In that case the mmio flip might
10929 * have completed, but the CS hasn't even executed the flip yet.
10930 *
10931 * A flip count check isn't enough as the CS might have updated
10932 * the base address just after start of vblank, but before we
10933 * managed to process the interrupt. This means we'd complete the
10934 * CS flip too soon.
10935 *
10936 * Combining both checks should get us a good enough result. It may
10937 * still happen that the CS flip has been executed, but has not
10938 * yet actually completed. But in case the base address is the same
10939 * anyway, we don't really care.
10940 */
10941 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10942 crtc->unpin_work->gtt_offset &&
fd8f507c 10943 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
75f7f3ec
VS		 10944 crtc->unpin_work->flip_count);
10945}
10946
6b95a207
KH		 10947void intel_prepare_page_flip(struct drm_device *dev, int plane)
10948{
fbee40df 10949 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 10950 struct intel_crtc *intel_crtc =
10951 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10952 unsigned long flags;
10953
f326038a
DV		 10954
10955 /*
10956 * This is called both by irq handlers and the reset code (to complete
10957 * lost pageflips) so needs the full irqsave spinlocks.
10958 *
10959 * NB: An MMIO update of the plane base pointer will also
e7d841ca
CW		 10960 * generate a page-flip completion irq, i.e. every modeset
10961 * is also accompanied by a spurious intel_prepare_page_flip().
10962 */
6b95a207 10963 spin_lock_irqsave(&dev->event_lock, flags);
75f7f3ec 10964 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
e7d841ca 10965 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 10966 spin_unlock_irqrestore(&dev->event_lock, flags);
10967}
10968
6042639c 10969static inline void intel_mark_page_flip_active(struct intel_unpin_work *work)
e7d841ca
CW		 10970{
10971 /* Ensure that the work item is consistent when activating it ... */
10972 smp_wmb();
6042639c 10973 atomic_set(&work->pending, INTEL_FLIP_PENDING);
e7d841ca
CW		 10974 /* and that it is marked active as soon as the irq could fire. */
10975 smp_wmb();
10976}
10977
8c9f3aaf
JB		 10978static int intel_gen2_queue_flip(struct drm_device *dev,
10979 struct drm_crtc *crtc,
10980 struct drm_framebuffer *fb,
ed8d1975 10981 struct drm_i915_gem_object *obj,
6258fbe2 10982 struct drm_i915_gem_request *req,
ed8d1975 10983 uint32_t flags)
8c9f3aaf 10984{
4a570db5 10985 struct intel_engine_cs *engine = req->engine;
8c9f3aaf 10986 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10987 u32 flip_mask;
10988 int ret;
10989
5fb9de1a 10990 ret = intel_ring_begin(req, 6);
8c9f3aaf 10991 if (ret)
4fa62c89 10992 return ret;
8c9f3aaf
JB		 10993
10994 /* Can't queue multiple flips, so wait for the previous
10995 * one to finish before executing the next.
10996 */
10997 if (intel_crtc->plane)
10998 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10999 else
11000 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
e2f80391
TU		 11001 intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask);
11002 intel_ring_emit(engine, MI_NOOP);
11003 intel_ring_emit(engine, MI_DISPLAY_FLIP |
6d90c952 11004 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
e2f80391
TU		 11005 intel_ring_emit(engine, fb->pitches[0]);
11006 intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset);
11007 intel_ring_emit(engine, 0); /* aux display base address, unused */
e7d841ca 11008
6042639c 11009 intel_mark_page_flip_active(intel_crtc->unpin_work);
83d4092b 11010 return 0;
8c9f3aaf
JB		 11011}
11012
11013static int intel_gen3_queue_flip(struct drm_device *dev,
11014 struct drm_crtc *crtc,
11015 struct drm_framebuffer *fb,
ed8d1975 11016 struct drm_i915_gem_object *obj,
6258fbe2 11017 struct drm_i915_gem_request *req,
ed8d1975 11018 uint32_t flags)
8c9f3aaf 11019{
4a570db5 11020 struct intel_engine_cs *engine = req->engine;
8c9f3aaf 11021 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 11022 u32 flip_mask;
11023 int ret;
11024
5fb9de1a 11025 ret = intel_ring_begin(req, 6);
8c9f3aaf 11026 if (ret)
4fa62c89 11027 return ret;
8c9f3aaf
JB		 11028
11029 if (intel_crtc->plane)
11030 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11031 else
11032 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
e2f80391
TU		 11033 intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask);
11034 intel_ring_emit(engine, MI_NOOP);
11035 intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 |
6d90c952 11036 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
e2f80391
TU		 11037 intel_ring_emit(engine, fb->pitches[0]);
11038 intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset);
11039 intel_ring_emit(engine, MI_NOOP);
6d90c952 11040
6042639c 11041 intel_mark_page_flip_active(intel_crtc->unpin_work);
83d4092b 11042 return 0;
8c9f3aaf
JB		 11043}
11044
11045static int intel_gen4_queue_flip(struct drm_device *dev,
11046 struct drm_crtc *crtc,
11047 struct drm_framebuffer *fb,
ed8d1975 11048 struct drm_i915_gem_object *obj,
6258fbe2 11049 struct drm_i915_gem_request *req,
ed8d1975 11050 uint32_t flags)
8c9f3aaf 11051{
4a570db5 11052 struct intel_engine_cs *engine = req->engine;
8c9f3aaf
JB		 11053 struct drm_i915_private *dev_priv = dev->dev_private;
11054 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11055 uint32_t pf, pipesrc;
11056 int ret;
11057
5fb9de1a 11058 ret = intel_ring_begin(req, 4);
8c9f3aaf 11059 if (ret)
4fa62c89 11060 return ret;
8c9f3aaf
JB		 11061
11062 /* i965+ uses the linear or tiled offsets from the
11063 * Display Registers (which do not change across a page-flip)
11064 * so we need only reprogram the base address.
11065 */
e2f80391 11066 intel_ring_emit(engine, MI_DISPLAY_FLIP |
6d90c952 11067 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
e2f80391
TU		 11068 intel_ring_emit(engine, fb->pitches[0]);
11069 intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset |
c2c75131 11070 obj->tiling_mode);
8c9f3aaf
JB		 11071
11072 /* XXX Enabling the panel-fitter across page-flip is so far
11073 * untested on non-native modes, so ignore it for now.
11074 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11075 */
11076 pf = 0;
11077 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
e2f80391 11078 intel_ring_emit(engine, pf | pipesrc);
e7d841ca 11079
6042639c 11080 intel_mark_page_flip_active(intel_crtc->unpin_work);
83d4092b 11081 return 0;
8c9f3aaf
JB		 11082}
11083
11084static int intel_gen6_queue_flip(struct drm_device *dev,
11085 struct drm_crtc *crtc,
11086 struct drm_framebuffer *fb,
ed8d1975 11087 struct drm_i915_gem_object *obj,
6258fbe2 11088 struct drm_i915_gem_request *req,
ed8d1975 11089 uint32_t flags)
8c9f3aaf 11090{
4a570db5 11091 struct intel_engine_cs *engine = req->engine;
8c9f3aaf
JB		 11092 struct drm_i915_private *dev_priv = dev->dev_private;
11093 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11094 uint32_t pf, pipesrc;
11095 int ret;
11096
5fb9de1a 11097 ret = intel_ring_begin(req, 4);
8c9f3aaf 11098 if (ret)
4fa62c89 11099 return ret;
8c9f3aaf 11100
e2f80391 11101 intel_ring_emit(engine, MI_DISPLAY_FLIP |
6d90c952 11102 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
e2f80391
TU		 11103 intel_ring_emit(engine, fb->pitches[0] | obj->tiling_mode);
11104 intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset);
8c9f3aaf 11105
dc257cf1
DV		 11106 /* Contrary to the suggestions in the documentation,
11107 * "Enable Panel Fitter" does not seem to be required when page
11108 * flipping with a non-native mode, and worse causes a normal
11109 * modeset to fail.
11110 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11111 */
11112 pf = 0;
8c9f3aaf 11113 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
e2f80391 11114 intel_ring_emit(engine, pf | pipesrc);
e7d841ca 11115
6042639c 11116 intel_mark_page_flip_active(intel_crtc->unpin_work);
83d4092b 11117 return 0;
8c9f3aaf
JB		 11118}
11119
7c9017e5
JB		 11120static int intel_gen7_queue_flip(struct drm_device *dev,
11121 struct drm_crtc *crtc,
11122 struct drm_framebuffer *fb,
ed8d1975 11123 struct drm_i915_gem_object *obj,
6258fbe2 11124 struct drm_i915_gem_request *req,
ed8d1975 11125 uint32_t flags)
7c9017e5 11126{
4a570db5 11127 struct intel_engine_cs *engine = req->engine;
7c9017e5 11128 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cb05d8de 11129 uint32_t plane_bit = 0;
ffe74d75
CW		 11130 int len, ret;
11131
eba905b2 11132 switch (intel_crtc->plane) {
cb05d8de
DV		 11133 case PLANE_A:
11134 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11135 break;
11136 case PLANE_B:
11137 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11138 break;
11139 case PLANE_C:
11140 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11141 break;
11142 default:
11143 WARN_ONCE(1, "unknown plane in flip command\n");
4fa62c89 11144 return -ENODEV;
cb05d8de
DV		 11145 }
11146
ffe74d75 11147 len = 4;
e2f80391 11148 if (engine->id == RCS) {
ffe74d75 11149 len += 6;
f476828a
DL		 11150 /*
11151 * On Gen 8, SRM is now taking an extra dword to accommodate
11152 * 48bits addresses, and we need a NOOP for the batch size to
11153 * stay even.
11154 */
11155 if (IS_GEN8(dev))
11156 len += 2;
11157 }
ffe74d75 11158
f66fab8e
VS		 11159 /*
11160 * BSpec MI_DISPLAY_FLIP for IVB:
11161 * "The full packet must be contained within the same cache line."
11162 *
11163 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11164 * cacheline, if we ever start emitting more commands before
11165 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11166 * then do the cacheline alignment, and finally emit the
11167 * MI_DISPLAY_FLIP.
11168 */
bba09b12 11169 ret = intel_ring_cacheline_align(req);
f66fab8e 11170 if (ret)
4fa62c89 11171 return ret;
f66fab8e 11172
5fb9de1a 11173 ret = intel_ring_begin(req, len);
7c9017e5 11174 if (ret)
4fa62c89 11175 return ret;
7c9017e5 11176
ffe74d75
CW		 11177 /* Unmask the flip-done completion message. Note that the bspec says that
11178 * we should do this for both the BCS and RCS, and that we must not unmask
11179 * more than one flip event at any time (or ensure that one flip message
11180 * can be sent by waiting for flip-done prior to queueing new flips).
11181 * Experimentation says that BCS works despite DERRMR masking all
11182 * flip-done completion events and that unmasking all planes at once
11183 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11184 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11185 */
e2f80391
TU		 11186 if (engine->id == RCS) {
11187 intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1));
11188 intel_ring_emit_reg(engine, DERRMR);
11189 intel_ring_emit(engine, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11190 DERRMR_PIPEB_PRI_FLIP_DONE |
11191 DERRMR_PIPEC_PRI_FLIP_DONE));
f476828a 11192 if (IS_GEN8(dev))
e2f80391 11193 intel_ring_emit(engine, MI_STORE_REGISTER_MEM_GEN8 |
f476828a
DL		 11194 MI_SRM_LRM_GLOBAL_GTT);
11195 else
e2f80391 11196 intel_ring_emit(engine, MI_STORE_REGISTER_MEM |
f476828a 11197 MI_SRM_LRM_GLOBAL_GTT);
e2f80391
TU		 11198 intel_ring_emit_reg(engine, DERRMR);
11199 intel_ring_emit(engine, engine->scratch.gtt_offset + 256);
f476828a 11200 if (IS_GEN8(dev)) {
e2f80391
TU		 11201 intel_ring_emit(engine, 0);
11202 intel_ring_emit(engine, MI_NOOP);
f476828a 11203 }
ffe74d75
CW		 11204 }
11205
e2f80391
TU		 11206 intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 | plane_bit);
11207 intel_ring_emit(engine, (fb->pitches[0] | obj->tiling_mode));
11208 intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset);
11209 intel_ring_emit(engine, (MI_NOOP));
e7d841ca 11210
6042639c 11211 intel_mark_page_flip_active(intel_crtc->unpin_work);
83d4092b 11212 return 0;
7c9017e5
JB		 11213}
11214
0bc40be8 11215static bool use_mmio_flip(struct intel_engine_cs *engine,
84c33a64
SG		 11216 struct drm_i915_gem_object *obj)
11217{
11218 /*
11219 * This is not being used for older platforms, because
11220 * non-availability of flip done interrupt forces us to use
11221 * CS flips. Older platforms derive flip done using some clever
11222 * tricks involving the flip_pending status bits and vblank irqs.
11223 * So using MMIO flips there would disrupt this mechanism.
11224 */
11225
0bc40be8 11226 if (engine == NULL)
8e09bf83
CW		 11227 return true;
11228
0bc40be8 11229 if (INTEL_INFO(engine->dev)->gen < 5)
84c33a64
SG		 11230 return false;
11231
11232 if (i915.use_mmio_flip < 0)
11233 return false;
11234 else if (i915.use_mmio_flip > 0)
11235 return true;
14bf993e
OM		 11236 else if (i915.enable_execlists)
11237 return true;
fd8e058a
AG		 11238 else if (obj->base.dma_buf &&
11239 !reservation_object_test_signaled_rcu(obj->base.dma_buf->resv,
11240 false))
11241 return true;
84c33a64 11242 else
666796da 11243 return engine != i915_gem_request_get_engine(obj->last_write_req);
84c33a64
SG		 11244}
11245
6042639c 11246static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
86efe24a 11247 unsigned int rotation,
6042639c 11248 struct intel_unpin_work *work)
ff944564
DL		 11249{
11250 struct drm_device *dev = intel_crtc->base.dev;
11251 struct drm_i915_private *dev_priv = dev->dev_private;
11252 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
ff944564 11253 const enum pipe pipe = intel_crtc->pipe;
86efe24a 11254 u32 ctl, stride, tile_height;
ff944564
DL		 11255
11256 ctl = I915_READ(PLANE_CTL(pipe, 0));
11257 ctl &= ~PLANE_CTL_TILED_MASK;
2ebef630
TU		 11258 switch (fb->modifier[0]) {
11259 case DRM_FORMAT_MOD_NONE:
11260 break;
11261 case I915_FORMAT_MOD_X_TILED:
ff944564 11262 ctl |= PLANE_CTL_TILED_X;
2ebef630
TU		 11263 break;
11264 case I915_FORMAT_MOD_Y_TILED:
11265 ctl |= PLANE_CTL_TILED_Y;
11266 break;
11267 case I915_FORMAT_MOD_Yf_TILED:
11268 ctl |= PLANE_CTL_TILED_YF;
11269 break;
11270 default:
11271 MISSING_CASE(fb->modifier[0]);
11272 }
ff944564
DL		 11273
11274 /*
11275 * The stride is either expressed as a multiple of 64 bytes chunks for
11276 * linear buffers or in number of tiles for tiled buffers.
11277 */
86efe24a
TU		 11278 if (intel_rotation_90_or_270(rotation)) {
11279 /* stride = Surface height in tiles */
832be82f 11280 tile_height = intel_tile_height(dev_priv, fb->modifier[0], 0);
86efe24a
TU		 11281 stride = DIV_ROUND_UP(fb->height, tile_height);
11282 } else {
11283 stride = fb->pitches[0] /
7b49f948
VS		 11284 intel_fb_stride_alignment(dev_priv, fb->modifier[0],
11285 fb->pixel_format);
86efe24a 11286 }
ff944564
DL		 11287
11288 /*
11289 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11290 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11291 */
11292 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11293 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11294
6042639c 11295 I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
ff944564
DL		 11296 POSTING_READ(PLANE_SURF(pipe, 0));
11297}
11298
6042639c
CW		 11299static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11300 struct intel_unpin_work *work)
84c33a64
SG		 11301{
11302 struct drm_device *dev = intel_crtc->base.dev;
11303 struct drm_i915_private *dev_priv = dev->dev_private;
11304 struct intel_framebuffer *intel_fb =
11305 to_intel_framebuffer(intel_crtc->base.primary->fb);
11306 struct drm_i915_gem_object *obj = intel_fb->obj;
f0f59a00 11307 i915_reg_t reg = DSPCNTR(intel_crtc->plane);
84c33a64 11308 u32 dspcntr;
84c33a64 11309
84c33a64
SG		 11310 dspcntr = I915_READ(reg);
11311
c5d97472
DL		 11312 if (obj->tiling_mode != I915_TILING_NONE)
11313 dspcntr |= DISPPLANE_TILED;
11314 else
11315 dspcntr &= ~DISPPLANE_TILED;
11316
84c33a64
SG		 11317 I915_WRITE(reg, dspcntr);
11318
6042639c 11319 I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
84c33a64 11320 POSTING_READ(DSPSURF(intel_crtc->plane));
ff944564
DL		 11321}
11322
11323/*
11324 * XXX: This is the temporary way to update the plane registers until we get
11325 * around to using the usual plane update functions for MMIO flips
11326 */
6042639c 11327static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip)
ff944564 11328{
6042639c
CW		 11329 struct intel_crtc *crtc = mmio_flip->crtc;
11330 struct intel_unpin_work *work;
11331
11332 spin_lock_irq(&crtc->base.dev->event_lock);
11333 work = crtc->unpin_work;
11334 spin_unlock_irq(&crtc->base.dev->event_lock);
11335 if (work == NULL)
11336 return;
ff944564 11337
6042639c 11338 intel_mark_page_flip_active(work);
ff944564 11339
6042639c 11340 intel_pipe_update_start(crtc);
ff944564 11341
6042639c 11342 if (INTEL_INFO(mmio_flip->i915)->gen >= 9)
86efe24a 11343 skl_do_mmio_flip(crtc, mmio_flip->rotation, work);
ff944564
DL		 11344 else
11345 /* use_mmio_flip() retricts MMIO flips to ilk+ */
6042639c 11346 ilk_do_mmio_flip(crtc, work);
ff944564 11347
6042639c 11348 intel_pipe_update_end(crtc);
84c33a64
SG		 11349}
11350
9362c7c5 11351static void intel_mmio_flip_work_func(struct work_struct *work)
84c33a64 11352{
b2cfe0ab
CW		 11353 struct intel_mmio_flip *mmio_flip =
11354 container_of(work, struct intel_mmio_flip, work);
fd8e058a
AG		 11355 struct intel_framebuffer *intel_fb =
11356 to_intel_framebuffer(mmio_flip->crtc->base.primary->fb);
11357 struct drm_i915_gem_object *obj = intel_fb->obj;
84c33a64 11358
6042639c 11359 if (mmio_flip->req) {
eed29a5b 11360 WARN_ON(__i915_wait_request(mmio_flip->req,
b2cfe0ab 11361 mmio_flip->crtc->reset_counter,
bcafc4e3
CW		 11362 false, NULL,
11363 &mmio_flip->i915->rps.mmioflips));
6042639c
CW		 11364 i915_gem_request_unreference__unlocked(mmio_flip->req);
11365 }
84c33a64 11366
fd8e058a
AG		 11367 /* For framebuffer backed by dmabuf, wait for fence */
11368 if (obj->base.dma_buf)
11369 WARN_ON(reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
11370 false, false,
11371 MAX_SCHEDULE_TIMEOUT) < 0);
11372
6042639c 11373 intel_do_mmio_flip(mmio_flip);
b2cfe0ab 11374 kfree(mmio_flip);
84c33a64
SG		 11375}
11376
11377static int intel_queue_mmio_flip(struct drm_device *dev,
11378 struct drm_crtc *crtc,
86efe24a 11379 struct drm_i915_gem_object *obj)
84c33a64 11380{
b2cfe0ab
CW		 11381 struct intel_mmio_flip *mmio_flip;
11382
11383 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11384 if (mmio_flip == NULL)
11385 return -ENOMEM;
84c33a64 11386
bcafc4e3 11387 mmio_flip->i915 = to_i915(dev);
eed29a5b 11388 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
b2cfe0ab 11389 mmio_flip->crtc = to_intel_crtc(crtc);
86efe24a 11390 mmio_flip->rotation = crtc->primary->state->rotation;
536f5b5e 11391
b2cfe0ab
CW		 11392 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11393 schedule_work(&mmio_flip->work);
84c33a64 11394
84c33a64
SG		 11395 return 0;
11396}
11397
8c9f3aaf
JB		 11398static int intel_default_queue_flip(struct drm_device *dev,
11399 struct drm_crtc *crtc,
11400 struct drm_framebuffer *fb,
ed8d1975 11401 struct drm_i915_gem_object *obj,
6258fbe2 11402 struct drm_i915_gem_request *req,
ed8d1975 11403 uint32_t flags)
8c9f3aaf
JB		 11404{
11405 return -ENODEV;
11406}
11407
d6bbafa1
CW		 11408static bool __intel_pageflip_stall_check(struct drm_device *dev,
11409 struct drm_crtc *crtc)
11410{
11411 struct drm_i915_private *dev_priv = dev->dev_private;
11412 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11413 struct intel_unpin_work *work = intel_crtc->unpin_work;
11414 u32 addr;
11415
11416 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11417 return true;
11418
908565c2
CW		 11419 if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11420 return false;
11421
d6bbafa1
CW		 11422 if (!work->enable_stall_check)
11423 return false;
11424
11425 if (work->flip_ready_vblank == 0) {
3a8a946e
DV		 11426 if (work->flip_queued_req &&
11427 !i915_gem_request_completed(work->flip_queued_req, true))
d6bbafa1
CW		 11428 return false;
11429
1e3feefd 11430 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1
CW		 11431 }
11432
1e3feefd 11433 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
d6bbafa1
CW		 11434 return false;
11435
11436 /* Potential stall - if we see that the flip has happened,
11437 * assume a missed interrupt. */
11438 if (INTEL_INFO(dev)->gen >= 4)
11439 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11440 else
11441 addr = I915_READ(DSPADDR(intel_crtc->plane));
11442
11443 /* There is a potential issue here with a false positive after a flip
11444 * to the same address. We could address this by checking for a
11445 * non-incrementing frame counter.
11446 */
11447 return addr == work->gtt_offset;
11448}
11449
11450void intel_check_page_flip(struct drm_device *dev, int pipe)
11451{
11452 struct drm_i915_private *dev_priv = dev->dev_private;
11453 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11454 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6ad790c0 11455 struct intel_unpin_work *work;
f326038a 11456
6c51d46f 11457 WARN_ON(!in_interrupt());
d6bbafa1
CW		 11458
11459 if (crtc == NULL)
11460 return;
11461
f326038a 11462 spin_lock(&dev->event_lock);
6ad790c0
CW		 11463 work = intel_crtc->unpin_work;
11464 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
d6bbafa1 11465 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
6ad790c0 11466 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
d6bbafa1 11467 page_flip_completed(intel_crtc);
6ad790c0 11468 work = NULL;
d6bbafa1 11469 }
6ad790c0
CW		 11470 if (work != NULL &&
11471 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11472 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
f326038a 11473 spin_unlock(&dev->event_lock);
d6bbafa1
CW		 11474}
11475
6b95a207
KH		 11476static int intel_crtc_page_flip(struct drm_crtc *crtc,
11477 struct drm_framebuffer *fb,
ed8d1975
KP		 11478 struct drm_pending_vblank_event *event,
11479 uint32_t page_flip_flags)
6b95a207
KH		 11480{
11481 struct drm_device *dev = crtc->dev;
11482 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 11483 struct drm_framebuffer *old_fb = crtc->primary->fb;
2ff8fde1 11484 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
6b95a207 11485 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
455a6808 11486 struct drm_plane *primary = crtc->primary;
a071fa00 11487 enum pipe pipe = intel_crtc->pipe;
6b95a207 11488 struct intel_unpin_work *work;
e2f80391 11489 struct intel_engine_cs *engine;
cf5d8a46 11490 bool mmio_flip;
91af127f 11491 struct drm_i915_gem_request *request = NULL;
52e68630 11492 int ret;
6b95a207 11493
2ff8fde1
MR		 11494 /*
11495 * drm_mode_page_flip_ioctl() should already catch this, but double
11496 * check to be safe. In the future we may enable pageflipping from
11497 * a disabled primary plane.
11498 */
11499 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11500 return -EBUSY;
11501
e6a595d2 11502 /* Can't change pixel format via MI display flips. */
f4510a27 11503 if (fb->pixel_format != crtc->primary->fb->pixel_format)
e6a595d2
VS		 11504 return -EINVAL;
11505
11506 /*
11507 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11508 * Note that pitch changes could also affect these register.
11509 */
11510 if (INTEL_INFO(dev)->gen > 3 &&
f4510a27
MR		 11511 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11512 fb->pitches[0] != crtc->primary->fb->pitches[0]))
e6a595d2
VS		 11513 return -EINVAL;
11514
f900db47
CW		 11515 if (i915_terminally_wedged(&dev_priv->gpu_error))
11516 goto out_hang;
11517
b14c5679 11518 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH		 11519 if (work == NULL)
11520 return -ENOMEM;
11521
6b95a207 11522 work->event = event;
b4a98e57 11523 work->crtc = crtc;
ab8d6675 11524 work->old_fb = old_fb;
6b95a207
KH		 11525 INIT_WORK(&work->work, intel_unpin_work_fn);
11526
87b6b101 11527 ret = drm_crtc_vblank_get(crtc);
7317c75e
JB		 11528 if (ret)
11529 goto free_work;
11530
6b95a207 11531 /* We borrow the event spin lock for protecting unpin_work */
5e2d7afc 11532 spin_lock_irq(&dev->event_lock);
6b95a207 11533 if (intel_crtc->unpin_work) {
d6bbafa1
CW		 11534 /* Before declaring the flip queue wedged, check if
11535 * the hardware completed the operation behind our backs.
11536 */
11537 if (__intel_pageflip_stall_check(dev, crtc)) {
11538 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11539 page_flip_completed(intel_crtc);
11540 } else {
11541 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5e2d7afc 11542 spin_unlock_irq(&dev->event_lock);
468f0b44 11543
d6bbafa1
CW		 11544 drm_crtc_vblank_put(crtc);
11545 kfree(work);
11546 return -EBUSY;
11547 }
6b95a207
KH		 11548 }
11549 intel_crtc->unpin_work = work;
5e2d7afc 11550 spin_unlock_irq(&dev->event_lock);
6b95a207 11551
b4a98e57
CW		 11552 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11553 flush_workqueue(dev_priv->wq);
11554
75dfca80 11555 /* Reference the objects for the scheduled work. */
ab8d6675 11556 drm_framebuffer_reference(work->old_fb);
05394f39 11557 drm_gem_object_reference(&obj->base);
6b95a207 11558
f4510a27 11559 crtc->primary->fb = fb;
afd65eb4 11560 update_state_fb(crtc->primary);
e8216e50 11561 intel_fbc_pre_update(intel_crtc);
1ed1f968 11562
e1f99ce6 11563 work->pending_flip_obj = obj;
e1f99ce6 11564
89ed88ba
CW		 11565 ret = i915_mutex_lock_interruptible(dev);
11566 if (ret)
11567 goto cleanup;
11568
b4a98e57 11569 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 11570 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 11571
75f7f3ec 11572 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
fd8f507c 11573 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
75f7f3ec 11574
666a4537 11575 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
4a570db5 11576 engine = &dev_priv->engine[BCS];
ab8d6675 11577 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
8e09bf83 11578 /* vlv: DISPLAY_FLIP fails to change tiling */
e2f80391 11579 engine = NULL;
48bf5b2d 11580 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
4a570db5 11581 engine = &dev_priv->engine[BCS];
4fa62c89 11582 } else if (INTEL_INFO(dev)->gen >= 7) {
666796da 11583 engine = i915_gem_request_get_engine(obj->last_write_req);
e2f80391 11584 if (engine == NULL || engine->id != RCS)
4a570db5 11585 engine = &dev_priv->engine[BCS];
4fa62c89 11586 } else {
4a570db5 11587 engine = &dev_priv->engine[RCS];
4fa62c89
VS		 11588 }
11589
e2f80391 11590 mmio_flip = use_mmio_flip(engine, obj);
cf5d8a46
CW		 11591
11592 /* When using CS flips, we want to emit semaphores between rings.
11593 * However, when using mmio flips we will create a task to do the
11594 * synchronisation, so all we want here is to pin the framebuffer
11595 * into the display plane and skip any waits.
11596 */
7580d774 11597 if (!mmio_flip) {
e2f80391 11598 ret = i915_gem_object_sync(obj, engine, &request);
7580d774
ML		 11599 if (ret)
11600 goto cleanup_pending;
11601 }
11602
3465c580 11603 ret = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
8c9f3aaf
JB		 11604 if (ret)
11605 goto cleanup_pending;
6b95a207 11606
dedf278c
TU		 11607 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11608 obj, 0);
11609 work->gtt_offset += intel_crtc->dspaddr_offset;
4fa62c89 11610
cf5d8a46 11611 if (mmio_flip) {
86efe24a 11612 ret = intel_queue_mmio_flip(dev, crtc, obj);
d6bbafa1
CW		 11613 if (ret)
11614 goto cleanup_unpin;
11615
f06cc1b9
JH		 11616 i915_gem_request_assign(&work->flip_queued_req,
11617 obj->last_write_req);
d6bbafa1 11618 } else {
6258fbe2 11619 if (!request) {
e2f80391 11620 request = i915_gem_request_alloc(engine, NULL);
26827088
DG		 11621 if (IS_ERR(request)) {
11622 ret = PTR_ERR(request);
6258fbe2 11623 goto cleanup_unpin;
26827088 11624 }
6258fbe2
JH		 11625 }
11626
11627 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
d6bbafa1
CW		 11628 page_flip_flags);
11629 if (ret)
11630 goto cleanup_unpin;
11631
6258fbe2 11632 i915_gem_request_assign(&work->flip_queued_req, request);
d6bbafa1
CW		 11633 }
11634
91af127f 11635 if (request)
75289874 11636 i915_add_request_no_flush(request);
91af127f 11637
1e3feefd 11638 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1 11639 work->enable_stall_check = true;
4fa62c89 11640
ab8d6675 11641 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
a9ff8714 11642 to_intel_plane(primary)->frontbuffer_bit);
c80ac854 11643 mutex_unlock(&dev->struct_mutex);
a071fa00 11644
a9ff8714
VS		 11645 intel_frontbuffer_flip_prepare(dev,
11646 to_intel_plane(primary)->frontbuffer_bit);
6b95a207 11647
e5510fac
JB		 11648 trace_i915_flip_request(intel_crtc->plane, obj);
11649
6b95a207 11650 return 0;
96b099fd 11651
4fa62c89 11652cleanup_unpin:
3465c580 11653 intel_unpin_fb_obj(fb, crtc->primary->state->rotation);
8c9f3aaf 11654cleanup_pending:
0aa498d5 11655 if (!IS_ERR_OR_NULL(request))
91af127f 11656 i915_gem_request_cancel(request);
b4a98e57 11657 atomic_dec(&intel_crtc->unpin_work_count);
89ed88ba
CW		 11658 mutex_unlock(&dev->struct_mutex);
11659cleanup:
f4510a27 11660 crtc->primary->fb = old_fb;
afd65eb4 11661 update_state_fb(crtc->primary);
89ed88ba
CW		 11662
11663 drm_gem_object_unreference_unlocked(&obj->base);
ab8d6675 11664 drm_framebuffer_unreference(work->old_fb);
96b099fd 11665
5e2d7afc 11666 spin_lock_irq(&dev->event_lock);
96b099fd 11667 intel_crtc->unpin_work = NULL;
5e2d7afc 11668 spin_unlock_irq(&dev->event_lock);
96b099fd 11669
87b6b101 11670 drm_crtc_vblank_put(crtc);
7317c75e 11671free_work:
96b099fd
CW		 11672 kfree(work);
11673
f900db47 11674 if (ret == -EIO) {
02e0efb5
ML		 11675 struct drm_atomic_state *state;
11676 struct drm_plane_state *plane_state;
11677
f900db47 11678out_hang:
02e0efb5
ML		 11679 state = drm_atomic_state_alloc(dev);
11680 if (!state)
11681 return -ENOMEM;
11682 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11683
11684retry:
11685 plane_state = drm_atomic_get_plane_state(state, primary);
11686 ret = PTR_ERR_OR_ZERO(plane_state);
11687 if (!ret) {
11688 drm_atomic_set_fb_for_plane(plane_state, fb);
11689
11690 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11691 if (!ret)
11692 ret = drm_atomic_commit(state);
11693 }
11694
11695 if (ret == -EDEADLK) {
11696 drm_modeset_backoff(state->acquire_ctx);
11697 drm_atomic_state_clear(state);
11698 goto retry;
11699 }
11700
11701 if (ret)
11702 drm_atomic_state_free(state);
11703
f0d3dad3 11704 if (ret == 0 && event) {
5e2d7afc 11705 spin_lock_irq(&dev->event_lock);
a071fa00 11706 drm_send_vblank_event(dev, pipe, event);
5e2d7afc 11707 spin_unlock_irq(&dev->event_lock);
f0d3dad3 11708 }
f900db47 11709 }
96b099fd 11710 return ret;
6b95a207
KH		 11711}
11712
da20eabd
ML		 11713
11714/**
11715 * intel_wm_need_update - Check whether watermarks need updating
11716 * @plane: drm plane
11717 * @state: new plane state
11718 *
11719 * Check current plane state versus the new one to determine whether
11720 * watermarks need to be recalculated.
11721 *
11722 * Returns true or false.
11723 */
11724static bool intel_wm_need_update(struct drm_plane *plane,
11725 struct drm_plane_state *state)
11726{
d21fbe87
MR		 11727 struct intel_plane_state *new = to_intel_plane_state(state);
11728 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
11729
11730 /* Update watermarks on tiling or size changes. */
92826fcd
ML		 11731 if (new->visible != cur->visible)
11732 return true;
11733
11734 if (!cur->base.fb || !new->base.fb)
11735 return false;
11736
11737 if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] ||
11738 cur->base.rotation != new->base.rotation ||
d21fbe87
MR		 11739 drm_rect_width(&new->src) != drm_rect_width(&cur->src) ||
11740 drm_rect_height(&new->src) != drm_rect_height(&cur->src) ||
11741 drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) ||
11742 drm_rect_height(&new->dst) != drm_rect_height(&cur->dst))
2791a16c 11743 return true;
7809e5ae 11744
2791a16c 11745 return false;
7809e5ae
MR		 11746}
11747
d21fbe87
MR		 11748static bool needs_scaling(struct intel_plane_state *state)
11749{
11750 int src_w = drm_rect_width(&state->src) >> 16;
11751 int src_h = drm_rect_height(&state->src) >> 16;
11752 int dst_w = drm_rect_width(&state->dst);
11753 int dst_h = drm_rect_height(&state->dst);
11754
11755 return (src_w != dst_w || src_h != dst_h);
11756}
11757
da20eabd
ML		 11758int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11759 struct drm_plane_state *plane_state)
11760{
ab1d3a0e 11761 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
da20eabd
ML		 11762 struct drm_crtc *crtc = crtc_state->crtc;
11763 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11764 struct drm_plane *plane = plane_state->plane;
11765 struct drm_device *dev = crtc->dev;
ed4a6a7c 11766 struct drm_i915_private *dev_priv = to_i915(dev);
da20eabd
ML		 11767 struct intel_plane_state *old_plane_state =
11768 to_intel_plane_state(plane->state);
11769 int idx = intel_crtc->base.base.id, ret;
da20eabd
ML		 11770 bool mode_changed = needs_modeset(crtc_state);
11771 bool was_crtc_enabled = crtc->state->active;
11772 bool is_crtc_enabled = crtc_state->active;
da20eabd
ML		 11773 bool turn_off, turn_on, visible, was_visible;
11774 struct drm_framebuffer *fb = plane_state->fb;
11775
11776 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11777 plane->type != DRM_PLANE_TYPE_CURSOR) {
11778 ret = skl_update_scaler_plane(
11779 to_intel_crtc_state(crtc_state),
11780 to_intel_plane_state(plane_state));
11781 if (ret)
11782 return ret;
11783 }
11784
da20eabd
ML		 11785 was_visible = old_plane_state->visible;
11786 visible = to_intel_plane_state(plane_state)->visible;
11787
11788 if (!was_crtc_enabled && WARN_ON(was_visible))
11789 was_visible = false;
11790
35c08f43
ML		 11791 /*
11792 * Visibility is calculated as if the crtc was on, but
11793 * after scaler setup everything depends on it being off
11794 * when the crtc isn't active.
11795 */
11796 if (!is_crtc_enabled)
11797 to_intel_plane_state(plane_state)->visible = visible = false;
da20eabd
ML		 11798
11799 if (!was_visible && !visible)
11800 return 0;
11801
e8861675
ML		 11802 if (fb != old_plane_state->base.fb)
11803 pipe_config->fb_changed = true;
11804
da20eabd
ML		 11805 turn_off = was_visible && (!visible || mode_changed);
11806 turn_on = visible && (!was_visible || mode_changed);
11807
11808 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11809 plane->base.id, fb ? fb->base.id : -1);
11810
11811 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11812 plane->base.id, was_visible, visible,
11813 turn_off, turn_on, mode_changed);
11814
caed361d
VS		 11815 if (turn_on) {
11816 pipe_config->update_wm_pre = true;
11817
11818 /* must disable cxsr around plane enable/disable */
11819 if (plane->type != DRM_PLANE_TYPE_CURSOR)
11820 pipe_config->disable_cxsr = true;
11821 } else if (turn_off) {
11822 pipe_config->update_wm_post = true;
92826fcd 11823
852eb00d 11824 /* must disable cxsr around plane enable/disable */
e8861675 11825 if (plane->type != DRM_PLANE_TYPE_CURSOR)
ab1d3a0e 11826 pipe_config->disable_cxsr = true;
852eb00d 11827 } else if (intel_wm_need_update(plane, plane_state)) {
caed361d
VS		 11828 /* FIXME bollocks */
11829 pipe_config->update_wm_pre = true;
11830 pipe_config->update_wm_post = true;
852eb00d 11831 }
da20eabd 11832
ed4a6a7c 11833 /* Pre-gen9 platforms need two-step watermark updates */
caed361d
VS		 11834 if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) &&
11835 INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks)
ed4a6a7c
MR		 11836 to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true;
11837
8be6ca85 11838 if (visible || was_visible)
cd202f69 11839 pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit;
a9ff8714 11840
31ae71fc
ML		 11841 /*
11842 * WaCxSRDisabledForSpriteScaling:ivb
11843 *
11844 * cstate->update_wm was already set above, so this flag will
11845 * take effect when we commit and program watermarks.
11846 */
11847 if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev) &&
11848 needs_scaling(to_intel_plane_state(plane_state)) &&
11849 !needs_scaling(old_plane_state))
11850 pipe_config->disable_lp_wm = true;
d21fbe87 11851
da20eabd
ML		 11852 return 0;
11853}
11854
6d3a1ce7
ML		 11855static bool encoders_cloneable(const struct intel_encoder *a,
11856 const struct intel_encoder *b)
11857{
11858 /* masks could be asymmetric, so check both ways */
11859 return a == b || (a->cloneable & (1 << b->type) &&
11860 b->cloneable & (1 << a->type));
11861}
11862
11863static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11864 struct intel_crtc *crtc,
11865 struct intel_encoder *encoder)
11866{
11867 struct intel_encoder *source_encoder;
11868 struct drm_connector *connector;
11869 struct drm_connector_state *connector_state;
11870 int i;
11871
11872 for_each_connector_in_state(state, connector, connector_state, i) {
11873 if (connector_state->crtc != &crtc->base)
11874 continue;
11875
11876 source_encoder =
11877 to_intel_encoder(connector_state->best_encoder);
11878 if (!encoders_cloneable(encoder, source_encoder))
11879 return false;
11880 }
11881
11882 return true;
11883}
11884
11885static bool check_encoder_cloning(struct drm_atomic_state *state,
11886 struct intel_crtc *crtc)
11887{
11888 struct intel_encoder *encoder;
11889 struct drm_connector *connector;
11890 struct drm_connector_state *connector_state;
11891 int i;
11892
11893 for_each_connector_in_state(state, connector, connector_state, i) {
11894 if (connector_state->crtc != &crtc->base)
11895 continue;
11896
11897 encoder = to_intel_encoder(connector_state->best_encoder);
11898 if (!check_single_encoder_cloning(state, crtc, encoder))
11899 return false;
11900 }
11901
11902 return true;
11903}
11904
11905static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11906 struct drm_crtc_state *crtc_state)
11907{
cf5a15be 11908 struct drm_device *dev = crtc->dev;
ad421372 11909 struct drm_i915_private *dev_priv = dev->dev_private;
6d3a1ce7 11910 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cf5a15be
ML		 11911 struct intel_crtc_state *pipe_config =
11912 to_intel_crtc_state(crtc_state);
6d3a1ce7 11913 struct drm_atomic_state *state = crtc_state->state;
4d20cd86 11914 int ret;
6d3a1ce7
ML		 11915 bool mode_changed = needs_modeset(crtc_state);
11916
11917 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11918 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11919 return -EINVAL;
11920 }
11921
852eb00d 11922 if (mode_changed && !crtc_state->active)
caed361d 11923 pipe_config->update_wm_post = true;
eddfcbcd 11924
ad421372
ML		 11925 if (mode_changed && crtc_state->enable &&
11926 dev_priv->display.crtc_compute_clock &&
8106ddbd 11927 !WARN_ON(pipe_config->shared_dpll)) {
ad421372
ML		 11928 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11929 pipe_config);
11930 if (ret)
11931 return ret;
11932 }
11933
82cf435b
LL		 11934 if (crtc_state->color_mgmt_changed) {
11935 ret = intel_color_check(crtc, crtc_state);
11936 if (ret)
11937 return ret;
11938 }
11939
e435d6e5 11940 ret = 0;
86c8bbbe 11941 if (dev_priv->display.compute_pipe_wm) {
e3bddded 11942 ret = dev_priv->display.compute_pipe_wm(pipe_config);
ed4a6a7c
MR		 11943 if (ret) {
11944 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
11945 return ret;
11946 }
11947 }
11948
11949 if (dev_priv->display.compute_intermediate_wm &&
11950 !to_intel_atomic_state(state)->skip_intermediate_wm) {
11951 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
11952 return 0;
11953
11954 /*
11955 * Calculate 'intermediate' watermarks that satisfy both the
11956 * old state and the new state. We can program these
11957 * immediately.
11958 */
11959 ret = dev_priv->display.compute_intermediate_wm(crtc->dev,
11960 intel_crtc,
11961 pipe_config);
11962 if (ret) {
11963 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
86c8bbbe 11964 return ret;
ed4a6a7c 11965 }
86c8bbbe
MR		 11966 }
11967
e435d6e5
ML		 11968 if (INTEL_INFO(dev)->gen >= 9) {
11969 if (mode_changed)
11970 ret = skl_update_scaler_crtc(pipe_config);
11971
11972 if (!ret)
11973 ret = intel_atomic_setup_scalers(dev, intel_crtc,
11974 pipe_config);
11975 }
11976
11977 return ret;
6d3a1ce7
ML		 11978}
11979
65b38e0d 11980static const struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160 11981 .mode_set_base_atomic = intel_pipe_set_base_atomic,
ea2c67bb
MR		 11982 .atomic_begin = intel_begin_crtc_commit,
11983 .atomic_flush = intel_finish_crtc_commit,
6d3a1ce7 11984 .atomic_check = intel_crtc_atomic_check,
f6e5b160
CW		 11985};
11986
d29b2f9d
ACO		 11987static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11988{
11989 struct intel_connector *connector;
11990
11991 for_each_intel_connector(dev, connector) {
11992 if (connector->base.encoder) {
11993 connector->base.state->best_encoder =
11994 connector->base.encoder;
11995 connector->base.state->crtc =
11996 connector->base.encoder->crtc;
11997 } else {
11998 connector->base.state->best_encoder = NULL;
11999 connector->base.state->crtc = NULL;
12000 }
12001 }
12002}
12003
050f7aeb 12004static void
eba905b2 12005connected_sink_compute_bpp(struct intel_connector *connector,
5cec258b 12006 struct intel_crtc_state *pipe_config)
050f7aeb
DV		 12007{
12008 int bpp = pipe_config->pipe_bpp;
12009
12010 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12011 connector->base.base.id,
c23cc417 12012 connector->base.name);
050f7aeb
DV		 12013
12014 /* Don't use an invalid EDID bpc value */
12015 if (connector->base.display_info.bpc &&
12016 connector->base.display_info.bpc * 3 < bpp) {
12017 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12018 bpp, connector->base.display_info.bpc*3);
12019 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
12020 }
12021
013dd9e0
JN		 12022 /* Clamp bpp to default limit on screens without EDID 1.4 */
12023 if (connector->base.display_info.bpc == 0) {
12024 int type = connector->base.connector_type;
12025 int clamp_bpp = 24;
12026
12027 /* Fall back to 18 bpp when DP sink capability is unknown. */
12028 if (type == DRM_MODE_CONNECTOR_DisplayPort ||
12029 type == DRM_MODE_CONNECTOR_eDP)
12030 clamp_bpp = 18;
12031
12032 if (bpp > clamp_bpp) {
12033 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n",
12034 bpp, clamp_bpp);
12035 pipe_config->pipe_bpp = clamp_bpp;
12036 }
050f7aeb
DV		 12037 }
12038}
12039
4e53c2e0 12040static int
050f7aeb 12041compute_baseline_pipe_bpp(struct intel_crtc *crtc,
5cec258b 12042 struct intel_crtc_state *pipe_config)
4e53c2e0 12043{
050f7aeb 12044 struct drm_device *dev = crtc->base.dev;
1486017f 12045 struct drm_atomic_state *state;
da3ced29
ACO		 12046 struct drm_connector *connector;
12047 struct drm_connector_state *connector_state;
1486017f 12048 int bpp, i;
4e53c2e0 12049
666a4537 12050 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
4e53c2e0 12051 bpp = 10*3;
d328c9d7
DV		 12052 else if (INTEL_INFO(dev)->gen >= 5)
12053 bpp = 12*3;
12054 else
12055 bpp = 8*3;
12056
4e53c2e0 12057
4e53c2e0
DV		 12058 pipe_config->pipe_bpp = bpp;
12059
1486017f
ACO		 12060 state = pipe_config->base.state;
12061
4e53c2e0 12062 /* Clamp display bpp to EDID value */
da3ced29
ACO		 12063 for_each_connector_in_state(state, connector, connector_state, i) {
12064 if (connector_state->crtc != &crtc->base)
4e53c2e0
DV		 12065 continue;
12066
da3ced29
ACO		 12067 connected_sink_compute_bpp(to_intel_connector(connector),
12068 pipe_config);
4e53c2e0
DV		 12069 }
12070
12071 return bpp;
12072}
12073
644db711
DV		 12074static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12075{
12076 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12077 "type: 0x%x flags: 0x%x\n",
1342830c 12078 mode->crtc_clock,
644db711
DV		 12079 mode->crtc_hdisplay, mode->crtc_hsync_start,
12080 mode->crtc_hsync_end, mode->crtc_htotal,
12081 mode->crtc_vdisplay, mode->crtc_vsync_start,
12082 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12083}
12084
c0b03411 12085static void intel_dump_pipe_config(struct intel_crtc *crtc,
5cec258b 12086 struct intel_crtc_state *pipe_config,
c0b03411
DV		 12087 const char *context)
12088{
6a60cd87
CK		 12089 struct drm_device *dev = crtc->base.dev;
12090 struct drm_plane *plane;
12091 struct intel_plane *intel_plane;
12092 struct intel_plane_state *state;
12093 struct drm_framebuffer *fb;
12094
12095 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
12096 context, pipe_config, pipe_name(crtc->pipe));
c0b03411 12097
da205630 12098 DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config->cpu_transcoder));
c0b03411
DV		 12099 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12100 pipe_config->pipe_bpp, pipe_config->dither);
12101 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12102 pipe_config->has_pch_encoder,
12103 pipe_config->fdi_lanes,
12104 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12105 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12106 pipe_config->fdi_m_n.tu);
90a6b7b0 12107 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
eb14cb74 12108 pipe_config->has_dp_encoder,
90a6b7b0 12109 pipe_config->lane_count,
eb14cb74
VS		 12110 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12111 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12112 pipe_config->dp_m_n.tu);
b95af8be 12113
90a6b7b0 12114 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
b95af8be 12115 pipe_config->has_dp_encoder,
90a6b7b0 12116 pipe_config->lane_count,
b95af8be
VK		 12117 pipe_config->dp_m2_n2.gmch_m,
12118 pipe_config->dp_m2_n2.gmch_n,
12119 pipe_config->dp_m2_n2.link_m,
12120 pipe_config->dp_m2_n2.link_n,
12121 pipe_config->dp_m2_n2.tu);
12122
55072d19
DV		 12123 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12124 pipe_config->has_audio,
12125 pipe_config->has_infoframe);
12126
c0b03411 12127 DRM_DEBUG_KMS("requested mode:\n");
2d112de7 12128 drm_mode_debug_printmodeline(&pipe_config->base.mode);
c0b03411 12129 DRM_DEBUG_KMS("adjusted mode:\n");
2d112de7
ACO		 12130 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12131 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
d71b8d4a 12132 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 12133 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12134 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
0ec463d3
TU		 12135 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12136 crtc->num_scalers,
12137 pipe_config->scaler_state.scaler_users,
12138 pipe_config->scaler_state.scaler_id);
c0b03411
DV		 12139 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12140 pipe_config->gmch_pfit.control,
12141 pipe_config->gmch_pfit.pgm_ratios,
12142 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 12143 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 12144 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 12145 pipe_config->pch_pfit.size,
12146 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 12147 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 12148 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
6a60cd87 12149
415ff0f6 12150 if (IS_BROXTON(dev)) {
05712c15 12151 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
415ff0f6 12152 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
c8453338 12153 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
415ff0f6
TU		 12154 pipe_config->ddi_pll_sel,
12155 pipe_config->dpll_hw_state.ebb0,
05712c15 12156 pipe_config->dpll_hw_state.ebb4,
415ff0f6
TU		 12157 pipe_config->dpll_hw_state.pll0,
12158 pipe_config->dpll_hw_state.pll1,
12159 pipe_config->dpll_hw_state.pll2,
12160 pipe_config->dpll_hw_state.pll3,
12161 pipe_config->dpll_hw_state.pll6,
12162 pipe_config->dpll_hw_state.pll8,
05712c15 12163 pipe_config->dpll_hw_state.pll9,
c8453338 12164 pipe_config->dpll_hw_state.pll10,
415ff0f6 12165 pipe_config->dpll_hw_state.pcsdw12);
ef11bdb3 12166 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
415ff0f6
TU		 12167 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12168 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12169 pipe_config->ddi_pll_sel,
12170 pipe_config->dpll_hw_state.ctrl1,
12171 pipe_config->dpll_hw_state.cfgcr1,
12172 pipe_config->dpll_hw_state.cfgcr2);
12173 } else if (HAS_DDI(dev)) {
1260f07e 12174 DRM_DEBUG_KMS("ddi_pll_sel: 0x%x; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
415ff0f6 12175 pipe_config->ddi_pll_sel,
00490c22
ML		 12176 pipe_config->dpll_hw_state.wrpll,
12177 pipe_config->dpll_hw_state.spll);
415ff0f6
TU		 12178 } else {
12179 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12180 "fp0: 0x%x, fp1: 0x%x\n",
12181 pipe_config->dpll_hw_state.dpll,
12182 pipe_config->dpll_hw_state.dpll_md,
12183 pipe_config->dpll_hw_state.fp0,
12184 pipe_config->dpll_hw_state.fp1);
12185 }
12186
6a60cd87
CK		 12187 DRM_DEBUG_KMS("planes on this crtc\n");
12188 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12189 intel_plane = to_intel_plane(plane);
12190 if (intel_plane->pipe != crtc->pipe)
12191 continue;
12192
12193 state = to_intel_plane_state(plane->state);
12194 fb = state->base.fb;
12195 if (!fb) {
12196 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12197 "disabled, scaler_id = %d\n",
12198 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12199 plane->base.id, intel_plane->pipe,
12200 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12201 drm_plane_index(plane), state->scaler_id);
12202 continue;
12203 }
12204
12205 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12206 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12207 plane->base.id, intel_plane->pipe,
12208 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12209 drm_plane_index(plane));
12210 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12211 fb->base.id, fb->width, fb->height, fb->pixel_format);
12212 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12213 state->scaler_id,
12214 state->src.x1 >> 16, state->src.y1 >> 16,
12215 drm_rect_width(&state->src) >> 16,
12216 drm_rect_height(&state->src) >> 16,
12217 state->dst.x1, state->dst.y1,
12218 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12219 }
c0b03411
DV		 12220}
12221
5448a00d 12222static bool check_digital_port_conflicts(struct drm_atomic_state *state)
00f0b378 12223{
5448a00d 12224 struct drm_device *dev = state->dev;
da3ced29 12225 struct drm_connector *connector;
00f0b378
VS		 12226 unsigned int used_ports = 0;
12227
12228 /*
12229 * Walk the connector list instead of the encoder
12230 * list to detect the problem on ddi platforms
12231 * where there's just one encoder per digital port.
12232 */
0bff4858
VS		 12233 drm_for_each_connector(connector, dev) {
12234 struct drm_connector_state *connector_state;
12235 struct intel_encoder *encoder;
12236
12237 connector_state = drm_atomic_get_existing_connector_state(state, connector);
12238 if (!connector_state)
12239 connector_state = connector->state;
12240
5448a00d 12241 if (!connector_state->best_encoder)
00f0b378
VS		 12242 continue;
12243
5448a00d
ACO		 12244 encoder = to_intel_encoder(connector_state->best_encoder);
12245
12246 WARN_ON(!connector_state->crtc);
00f0b378
VS		 12247
12248 switch (encoder->type) {
12249 unsigned int port_mask;
12250 case INTEL_OUTPUT_UNKNOWN:
12251 if (WARN_ON(!HAS_DDI(dev)))
12252 break;
12253 case INTEL_OUTPUT_DISPLAYPORT:
12254 case INTEL_OUTPUT_HDMI:
12255 case INTEL_OUTPUT_EDP:
12256 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12257
12258 /* the same port mustn't appear more than once */
12259 if (used_ports & port_mask)
12260 return false;
12261
12262 used_ports |= port_mask;
12263 default:
12264 break;
12265 }
12266 }
12267
12268 return true;
12269}
12270
83a57153
ACO		 12271static void
12272clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12273{
12274 struct drm_crtc_state tmp_state;
663a3640 12275 struct intel_crtc_scaler_state scaler_state;
4978cc93 12276 struct intel_dpll_hw_state dpll_hw_state;
8106ddbd 12277 struct intel_shared_dpll *shared_dpll;
8504c74c 12278 uint32_t ddi_pll_sel;
c4e2d043 12279 bool force_thru;
83a57153 12280
7546a384
ACO		 12281 /* FIXME: before the switch to atomic started, a new pipe_config was
12282 * kzalloc'd. Code that depends on any field being zero should be
12283 * fixed, so that the crtc_state can be safely duplicated. For now,
12284 * only fields that are know to not cause problems are preserved. */
12285
83a57153 12286 tmp_state = crtc_state->base;
663a3640 12287 scaler_state = crtc_state->scaler_state;
4978cc93
ACO		 12288 shared_dpll = crtc_state->shared_dpll;
12289 dpll_hw_state = crtc_state->dpll_hw_state;
8504c74c 12290 ddi_pll_sel = crtc_state->ddi_pll_sel;
c4e2d043 12291 force_thru = crtc_state->pch_pfit.force_thru;
4978cc93 12292
83a57153 12293 memset(crtc_state, 0, sizeof *crtc_state);
4978cc93 12294
83a57153 12295 crtc_state->base = tmp_state;
663a3640 12296 crtc_state->scaler_state = scaler_state;
4978cc93
ACO		 12297 crtc_state->shared_dpll = shared_dpll;
12298 crtc_state->dpll_hw_state = dpll_hw_state;
8504c74c 12299 crtc_state->ddi_pll_sel = ddi_pll_sel;
c4e2d043 12300 crtc_state->pch_pfit.force_thru = force_thru;
83a57153
ACO		 12301}
12302
548ee15b 12303static int
b8cecdf5 12304intel_modeset_pipe_config(struct drm_crtc *crtc,
b359283a 12305 struct intel_crtc_state *pipe_config)
ee7b9f93 12306{
b359283a 12307 struct drm_atomic_state *state = pipe_config->base.state;
7758a113 12308 struct intel_encoder *encoder;
da3ced29 12309 struct drm_connector *connector;
0b901879 12310 struct drm_connector_state *connector_state;
d328c9d7 12311 int base_bpp, ret = -EINVAL;
0b901879 12312 int i;
e29c22c0 12313 bool retry = true;
ee7b9f93 12314
83a57153 12315 clear_intel_crtc_state(pipe_config);
7758a113 12316
e143a21c
DV		 12317 pipe_config->cpu_transcoder =
12318 (enum transcoder) to_intel_crtc(crtc)->pipe;
b8cecdf5 12319
2960bc9c
ID		 12320 /*
12321 * Sanitize sync polarity flags based on requested ones. If neither
12322 * positive or negative polarity is requested, treat this as meaning
12323 * negative polarity.
12324 */
2d112de7 12325 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 12326 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
2d112de7 12327 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
2960bc9c 12328
2d112de7 12329 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 12330 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
2d112de7 12331 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
2960bc9c 12332
d328c9d7
DV		 12333 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12334 pipe_config);
12335 if (base_bpp < 0)
4e53c2e0
DV		 12336 goto fail;
12337
e41a56be
VS		 12338 /*
12339 * Determine the real pipe dimensions. Note that stereo modes can
12340 * increase the actual pipe size due to the frame doubling and
12341 * insertion of additional space for blanks between the frame. This
12342 * is stored in the crtc timings. We use the requested mode to do this
12343 * computation to clearly distinguish it from the adjusted mode, which
12344 * can be changed by the connectors in the below retry loop.
12345 */
2d112de7 12346 drm_crtc_get_hv_timing(&pipe_config->base.mode,
ecb7e16b
GP		 12347 &pipe_config->pipe_src_w,
12348 &pipe_config->pipe_src_h);
e41a56be 12349
e29c22c0 12350encoder_retry:
ef1b460d 12351 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 12352 pipe_config->port_clock = 0;
ef1b460d 12353 pipe_config->pixel_multiplier = 1;
ff9a6750 12354
135c81b8 12355 /* Fill in default crtc timings, allow encoders to overwrite them. */
2d112de7
ACO		 12356 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12357 CRTC_STEREO_DOUBLE);
135c81b8 12358
7758a113
DV		 12359 /* Pass our mode to the connectors and the CRTC to give them a chance to
12360 * adjust it according to limitations or connector properties, and also
12361 * a chance to reject the mode entirely.
47f1c6c9 12362 */
da3ced29 12363 for_each_connector_in_state(state, connector, connector_state, i) {
0b901879 12364 if (connector_state->crtc != crtc)
7758a113 12365 continue;
7ae89233 12366
0b901879
ACO		 12367 encoder = to_intel_encoder(connector_state->best_encoder);
12368
efea6e8e
DV		 12369 if (!(encoder->compute_config(encoder, pipe_config))) {
12370 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 12371 goto fail;
12372 }
ee7b9f93 12373 }
47f1c6c9 12374
ff9a6750
DV		 12375 /* Set default port clock if not overwritten by the encoder. Needs to be
12376 * done afterwards in case the encoder adjusts the mode. */
12377 if (!pipe_config->port_clock)
2d112de7 12378 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
241bfc38 12379 * pipe_config->pixel_multiplier;
ff9a6750 12380
a43f6e0f 12381 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 12382 if (ret < 0) {
7758a113
DV		 12383 DRM_DEBUG_KMS("CRTC fixup failed\n");
12384 goto fail;
ee7b9f93 12385 }
e29c22c0
DV		 12386
12387 if (ret == RETRY) {
12388 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12389 ret = -EINVAL;
12390 goto fail;
12391 }
12392
12393 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12394 retry = false;
12395 goto encoder_retry;
12396 }
12397
e8fa4270
DV		 12398 /* Dithering seems to not pass-through bits correctly when it should, so
12399 * only enable it on 6bpc panels. */
12400 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
62f0ace5 12401 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
d328c9d7 12402 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
4e53c2e0 12403
7758a113 12404fail:
548ee15b 12405 return ret;
ee7b9f93 12406}
47f1c6c9 12407
ea9d758d 12408static void
4740b0f2 12409intel_modeset_update_crtc_state(struct drm_atomic_state *state)
ea9d758d 12410{
0a9ab303
ACO		 12411 struct drm_crtc *crtc;
12412 struct drm_crtc_state *crtc_state;
8a75d157 12413 int i;
ea9d758d 12414
7668851f 12415 /* Double check state. */
8a75d157 12416 for_each_crtc_in_state(state, crtc, crtc_state, i) {
3cb480bc 12417 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
fc467a22
ML		 12418
12419 /* Update hwmode for vblank functions */
12420 if (crtc->state->active)
12421 crtc->hwmode = crtc->state->adjusted_mode;
12422 else
12423 crtc->hwmode.crtc_clock = 0;
61067a5e
ML		 12424
12425 /*
12426 * Update legacy state to satisfy fbc code. This can
12427 * be removed when fbc uses the atomic state.
12428 */
12429 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12430 struct drm_plane_state *plane_state = crtc->primary->state;
12431
12432 crtc->primary->fb = plane_state->fb;
12433 crtc->x = plane_state->src_x >> 16;
12434 crtc->y = plane_state->src_y >> 16;
12435 }
ea9d758d 12436 }
ea9d758d
DV		 12437}
12438
3bd26263 12439static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 12440{
3bd26263 12441 int diff;
f1f644dc
JB		 12442
12443 if (clock1 == clock2)
12444 return true;
12445
12446 if (!clock1 || !clock2)
12447 return false;
12448
12449 diff = abs(clock1 - clock2);
12450
12451 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12452 return true;
12453
12454 return false;
12455}
12456
25c5b266
DV		 12457#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12458 list_for_each_entry((intel_crtc), \
12459 &(dev)->mode_config.crtc_list, \
12460 base.head) \
95150bdf 12461 for_each_if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 12462
cfb23ed6
ML		 12463static bool
12464intel_compare_m_n(unsigned int m, unsigned int n,
12465 unsigned int m2, unsigned int n2,
12466 bool exact)
12467{
12468 if (m == m2 && n == n2)
12469 return true;
12470
12471 if (exact || !m || !n || !m2 || !n2)
12472 return false;
12473
12474 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12475
31d10b57
ML		 12476 if (n > n2) {
12477 while (n > n2) {
cfb23ed6
ML		 12478 m2 <<= 1;
12479 n2 <<= 1;
12480 }
31d10b57
ML		 12481 } else if (n < n2) {
12482 while (n < n2) {
cfb23ed6
ML		 12483 m <<= 1;
12484 n <<= 1;
12485 }
12486 }
12487
31d10b57
ML		 12488 if (n != n2)
12489 return false;
12490
12491 return intel_fuzzy_clock_check(m, m2);
cfb23ed6
ML		 12492}
12493
12494static bool
12495intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12496 struct intel_link_m_n *m2_n2,
12497 bool adjust)
12498{
12499 if (m_n->tu == m2_n2->tu &&
12500 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12501 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12502 intel_compare_m_n(m_n->link_m, m_n->link_n,
12503 m2_n2->link_m, m2_n2->link_n, !adjust)) {
12504 if (adjust)
12505 *m2_n2 = *m_n;
12506
12507 return true;
12508 }
12509
12510 return false;
12511}
12512
0e8ffe1b 12513static bool
2fa2fe9a 12514intel_pipe_config_compare(struct drm_device *dev,
5cec258b 12515 struct intel_crtc_state *current_config,
cfb23ed6
ML		 12516 struct intel_crtc_state *pipe_config,
12517 bool adjust)
0e8ffe1b 12518{
cfb23ed6
ML		 12519 bool ret = true;
12520
12521#define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12522 do { \
12523 if (!adjust) \
12524 DRM_ERROR(fmt, ##__VA_ARGS__); \
12525 else \
12526 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12527 } while (0)
12528
66e985c0
DV		 12529#define PIPE_CONF_CHECK_X(name) \
12530 if (current_config->name != pipe_config->name) { \
cfb23ed6 12531 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
66e985c0
DV		 12532 "(expected 0x%08x, found 0x%08x)\n", \
12533 current_config->name, \
12534 pipe_config->name); \
cfb23ed6 12535 ret = false; \
66e985c0
DV		 12536 }
12537
08a24034
DV		 12538#define PIPE_CONF_CHECK_I(name) \
12539 if (current_config->name != pipe_config->name) { \
cfb23ed6 12540 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
08a24034
DV		 12541 "(expected %i, found %i)\n", \
12542 current_config->name, \
12543 pipe_config->name); \
cfb23ed6
ML		 12544 ret = false; \
12545 }
12546
8106ddbd
ACO		 12547#define PIPE_CONF_CHECK_P(name) \
12548 if (current_config->name != pipe_config->name) { \
12549 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12550 "(expected %p, found %p)\n", \
12551 current_config->name, \
12552 pipe_config->name); \
12553 ret = false; \
12554 }
12555
cfb23ed6
ML		 12556#define PIPE_CONF_CHECK_M_N(name) \
12557 if (!intel_compare_link_m_n(&current_config->name, \
12558 &pipe_config->name,\
12559 adjust)) { \
12560 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12561 "(expected tu %i gmch %i/%i link %i/%i, " \
12562 "found tu %i, gmch %i/%i link %i/%i)\n", \
12563 current_config->name.tu, \
12564 current_config->name.gmch_m, \
12565 current_config->name.gmch_n, \
12566 current_config->name.link_m, \
12567 current_config->name.link_n, \
12568 pipe_config->name.tu, \
12569 pipe_config->name.gmch_m, \
12570 pipe_config->name.gmch_n, \
12571 pipe_config->name.link_m, \
12572 pipe_config->name.link_n); \
12573 ret = false; \
12574 }
12575
55c561a7
DV		 12576/* This is required for BDW+ where there is only one set of registers for
12577 * switching between high and low RR.
12578 * This macro can be used whenever a comparison has to be made between one
12579 * hw state and multiple sw state variables.
12580 */
cfb23ed6
ML		 12581#define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12582 if (!intel_compare_link_m_n(&current_config->name, \
12583 &pipe_config->name, adjust) && \
12584 !intel_compare_link_m_n(&current_config->alt_name, \
12585 &pipe_config->name, adjust)) { \
12586 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12587 "(expected tu %i gmch %i/%i link %i/%i, " \
12588 "or tu %i gmch %i/%i link %i/%i, " \
12589 "found tu %i, gmch %i/%i link %i/%i)\n", \
12590 current_config->name.tu, \
12591 current_config->name.gmch_m, \
12592 current_config->name.gmch_n, \
12593 current_config->name.link_m, \
12594 current_config->name.link_n, \
12595 current_config->alt_name.tu, \
12596 current_config->alt_name.gmch_m, \
12597 current_config->alt_name.gmch_n, \
12598 current_config->alt_name.link_m, \
12599 current_config->alt_name.link_n, \
12600 pipe_config->name.tu, \
12601 pipe_config->name.gmch_m, \
12602 pipe_config->name.gmch_n, \
12603 pipe_config->name.link_m, \
12604 pipe_config->name.link_n); \
12605 ret = false; \
88adfff1
DV		 12606 }
12607
1bd1bd80
DV		 12608#define PIPE_CONF_CHECK_FLAGS(name, mask) \
12609 if ((current_config->name ^ pipe_config->name) & (mask)) { \
cfb23ed6 12610 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 12611 "(expected %i, found %i)\n", \
12612 current_config->name & (mask), \
12613 pipe_config->name & (mask)); \
cfb23ed6 12614 ret = false; \
1bd1bd80
DV		 12615 }
12616
5e550656
VS		 12617#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12618 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
cfb23ed6 12619 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
5e550656
VS		 12620 "(expected %i, found %i)\n", \
12621 current_config->name, \
12622 pipe_config->name); \
cfb23ed6 12623 ret = false; \
5e550656
VS		 12624 }
12625
bb760063
DV		 12626#define PIPE_CONF_QUIRK(quirk) \
12627 ((current_config->quirks | pipe_config->quirks) & (quirk))
12628
eccb140b
DV		 12629 PIPE_CONF_CHECK_I(cpu_transcoder);
12630
08a24034
DV		 12631 PIPE_CONF_CHECK_I(has_pch_encoder);
12632 PIPE_CONF_CHECK_I(fdi_lanes);
cfb23ed6 12633 PIPE_CONF_CHECK_M_N(fdi_m_n);
08a24034 12634
eb14cb74 12635 PIPE_CONF_CHECK_I(has_dp_encoder);
90a6b7b0 12636 PIPE_CONF_CHECK_I(lane_count);
b95af8be
VK		 12637
12638 if (INTEL_INFO(dev)->gen < 8) {
cfb23ed6
ML		 12639 PIPE_CONF_CHECK_M_N(dp_m_n);
12640
cfb23ed6
ML		 12641 if (current_config->has_drrs)
12642 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12643 } else
12644 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
eb14cb74 12645
a65347ba
JN		 12646 PIPE_CONF_CHECK_I(has_dsi_encoder);
12647
2d112de7
ACO		 12648 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12649 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12650 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12651 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12652 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12653 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
1bd1bd80 12654
2d112de7
ACO		 12655 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12656 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12657 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12658 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12659 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12660 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
1bd1bd80 12661
c93f54cf 12662 PIPE_CONF_CHECK_I(pixel_multiplier);
6897b4b5 12663 PIPE_CONF_CHECK_I(has_hdmi_sink);
b5a9fa09 12664 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
666a4537 12665 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
b5a9fa09 12666 PIPE_CONF_CHECK_I(limited_color_range);
e43823ec 12667 PIPE_CONF_CHECK_I(has_infoframe);
6c49f241 12668
9ed109a7
DV		 12669 PIPE_CONF_CHECK_I(has_audio);
12670
2d112de7 12671 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
1bd1bd80
DV		 12672 DRM_MODE_FLAG_INTERLACE);
12673
bb760063 12674 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
2d112de7 12675 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12676 DRM_MODE_FLAG_PHSYNC);
2d112de7 12677 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12678 DRM_MODE_FLAG_NHSYNC);
2d112de7 12679 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12680 DRM_MODE_FLAG_PVSYNC);
2d112de7 12681 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063
DV		 12682 DRM_MODE_FLAG_NVSYNC);
12683 }
045ac3b5 12684
333b8ca8 12685 PIPE_CONF_CHECK_X(gmch_pfit.control);
e2ff2d4a
DV		 12686 /* pfit ratios are autocomputed by the hw on gen4+ */
12687 if (INTEL_INFO(dev)->gen < 4)
12688 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
333b8ca8 12689 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
9953599b 12690
bfd16b2a
ML		 12691 if (!adjust) {
12692 PIPE_CONF_CHECK_I(pipe_src_w);
12693 PIPE_CONF_CHECK_I(pipe_src_h);
12694
12695 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12696 if (current_config->pch_pfit.enabled) {
12697 PIPE_CONF_CHECK_X(pch_pfit.pos);
12698 PIPE_CONF_CHECK_X(pch_pfit.size);
12699 }
2fa2fe9a 12700
7aefe2b5
ML		 12701 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12702 }
a1b2278e 12703
e59150dc
JB		 12704 /* BDW+ don't expose a synchronous way to read the state */
12705 if (IS_HASWELL(dev))
12706 PIPE_CONF_CHECK_I(ips_enabled);
42db64ef 12707
282740f7
VS		 12708 PIPE_CONF_CHECK_I(double_wide);
12709
26804afd
DV		 12710 PIPE_CONF_CHECK_X(ddi_pll_sel);
12711
8106ddbd 12712 PIPE_CONF_CHECK_P(shared_dpll);
66e985c0 12713 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 12714 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 12715 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12716 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
d452c5b6 12717 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
00490c22 12718 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
3f4cd19f
DL		 12719 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12720 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12721 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
c0d43d62 12722
42571aef
VS		 12723 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12724 PIPE_CONF_CHECK_I(pipe_bpp);
12725
2d112de7 12726 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
a9a7e98a 12727 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
5e550656 12728
66e985c0 12729#undef PIPE_CONF_CHECK_X
08a24034 12730#undef PIPE_CONF_CHECK_I
8106ddbd 12731#undef PIPE_CONF_CHECK_P
1bd1bd80 12732#undef PIPE_CONF_CHECK_FLAGS
5e550656 12733#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 12734#undef PIPE_CONF_QUIRK
cfb23ed6 12735#undef INTEL_ERR_OR_DBG_KMS
88adfff1 12736
cfb23ed6 12737 return ret;
0e8ffe1b
DV		 12738}
12739
e3b247da
VS		 12740static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
12741 const struct intel_crtc_state *pipe_config)
12742{
12743 if (pipe_config->has_pch_encoder) {
21a727b3 12744 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
e3b247da
VS		 12745 &pipe_config->fdi_m_n);
12746 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
12747
12748 /*
12749 * FDI already provided one idea for the dotclock.
12750 * Yell if the encoder disagrees.
12751 */
12752 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
12753 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12754 fdi_dotclock, dotclock);
12755 }
12756}
12757
08db6652
DL		 12758static void check_wm_state(struct drm_device *dev)
12759{
12760 struct drm_i915_private *dev_priv = dev->dev_private;
12761 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12762 struct intel_crtc *intel_crtc;
12763 int plane;
12764
12765 if (INTEL_INFO(dev)->gen < 9)
12766 return;
12767
12768 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12769 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12770
12771 for_each_intel_crtc(dev, intel_crtc) {
12772 struct skl_ddb_entry *hw_entry, *sw_entry;
12773 const enum pipe pipe = intel_crtc->pipe;
12774
12775 if (!intel_crtc->active)
12776 continue;
12777
12778 /* planes */
dd740780 12779 for_each_plane(dev_priv, pipe, plane) {
08db6652
DL		 12780 hw_entry = &hw_ddb.plane[pipe][plane];
12781 sw_entry = &sw_ddb->plane[pipe][plane];
12782
12783 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12784 continue;
12785
12786 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12787 "(expected (%u,%u), found (%u,%u))\n",
12788 pipe_name(pipe), plane + 1,
12789 sw_entry->start, sw_entry->end,
12790 hw_entry->start, hw_entry->end);
12791 }
12792
12793 /* cursor */
4969d33e
MR		 12794 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12795 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
08db6652
DL		 12796
12797 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12798 continue;
12799
12800 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12801 "(expected (%u,%u), found (%u,%u))\n",
12802 pipe_name(pipe),
12803 sw_entry->start, sw_entry->end,
12804 hw_entry->start, hw_entry->end);
12805 }
12806}
12807
91d1b4bd 12808static void
35dd3c64
ML		 12809check_connector_state(struct drm_device *dev,
12810 struct drm_atomic_state *old_state)
8af6cf88 12811{
35dd3c64
ML		 12812 struct drm_connector_state *old_conn_state;
12813 struct drm_connector *connector;
12814 int i;
8af6cf88 12815
35dd3c64
ML		 12816 for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12817 struct drm_encoder *encoder = connector->encoder;
12818 struct drm_connector_state *state = connector->state;
ad3c558f 12819
8af6cf88
DV		 12820 /* This also checks the encoder/connector hw state with the
12821 * ->get_hw_state callbacks. */
35dd3c64 12822 intel_connector_check_state(to_intel_connector(connector));
8af6cf88 12823
ad3c558f 12824 I915_STATE_WARN(state->best_encoder != encoder,
35dd3c64 12825 "connector's atomic encoder doesn't match legacy encoder\n");
8af6cf88 12826 }
91d1b4bd
DV		 12827}
12828
12829static void
12830check_encoder_state(struct drm_device *dev)
12831{
12832 struct intel_encoder *encoder;
12833 struct intel_connector *connector;
8af6cf88 12834
b2784e15 12835 for_each_intel_encoder(dev, encoder) {
8af6cf88 12836 bool enabled = false;
4d20cd86 12837 enum pipe pipe;
8af6cf88
DV		 12838
12839 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12840 encoder->base.base.id,
8e329a03 12841 encoder->base.name);
8af6cf88 12842
3a3371ff 12843 for_each_intel_connector(dev, connector) {
4d20cd86 12844 if (connector->base.state->best_encoder != &encoder->base)
8af6cf88
DV		 12845 continue;
12846 enabled = true;
ad3c558f
ML		 12847
12848 I915_STATE_WARN(connector->base.state->crtc !=
12849 encoder->base.crtc,
12850 "connector's crtc doesn't match encoder crtc\n");
8af6cf88 12851 }
0e32b39c 12852
e2c719b7 12853 I915_STATE_WARN(!!encoder->base.crtc != enabled,
8af6cf88
DV		 12854 "encoder's enabled state mismatch "
12855 "(expected %i, found %i)\n",
12856 !!encoder->base.crtc, enabled);
7c60d198
ML		 12857
12858 if (!encoder->base.crtc) {
4d20cd86 12859 bool active;
7c60d198 12860
4d20cd86
ML		 12861 active = encoder->get_hw_state(encoder, &pipe);
12862 I915_STATE_WARN(active,
12863 "encoder detached but still enabled on pipe %c.\n",
12864 pipe_name(pipe));
7c60d198 12865 }
8af6cf88 12866 }
91d1b4bd
DV		 12867}
12868
12869static void
4d20cd86 12870check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
91d1b4bd 12871{
fbee40df 12872 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd 12873 struct intel_encoder *encoder;
4d20cd86
ML		 12874 struct drm_crtc_state *old_crtc_state;
12875 struct drm_crtc *crtc;
12876 int i;
8af6cf88 12877
4d20cd86
ML		 12878 for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
12879 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12880 struct intel_crtc_state *pipe_config, *sw_config;
7b89b8de 12881 bool active;
8af6cf88 12882
bfd16b2a
ML		 12883 if (!needs_modeset(crtc->state) &&
12884 !to_intel_crtc_state(crtc->state)->update_pipe)
4d20cd86 12885 continue;
045ac3b5 12886
4d20cd86
ML		 12887 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12888 pipe_config = to_intel_crtc_state(old_crtc_state);
12889 memset(pipe_config, 0, sizeof(*pipe_config));
12890 pipe_config->base.crtc = crtc;
12891 pipe_config->base.state = old_state;
8af6cf88 12892
4d20cd86
ML		 12893 DRM_DEBUG_KMS("[CRTC:%d]\n",
12894 crtc->base.id);
8af6cf88 12895
4d20cd86
ML		 12896 active = dev_priv->display.get_pipe_config(intel_crtc,
12897 pipe_config);
d62cf62a 12898
b6b5d049 12899 /* hw state is inconsistent with the pipe quirk */
4d20cd86
ML		 12900 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12901 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12902 active = crtc->state->active;
6c49f241 12903
4d20cd86 12904 I915_STATE_WARN(crtc->state->active != active,
0e8ffe1b 12905 "crtc active state doesn't match with hw state "
4d20cd86 12906 "(expected %i, found %i)\n", crtc->state->active, active);
0e8ffe1b 12907
4d20cd86 12908 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
53d9f4e9 12909 "transitional active state does not match atomic hw state "
4d20cd86
ML		 12910 "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
12911
12912 for_each_encoder_on_crtc(dev, crtc, encoder) {
12913 enum pipe pipe;
12914
12915 active = encoder->get_hw_state(encoder, &pipe);
12916 I915_STATE_WARN(active != crtc->state->active,
12917 "[ENCODER:%i] active %i with crtc active %i\n",
12918 encoder->base.base.id, active, crtc->state->active);
12919
12920 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12921 "Encoder connected to wrong pipe %c\n",
12922 pipe_name(pipe));
12923
12924 if (active)
12925 encoder->get_config(encoder, pipe_config);
12926 }
53d9f4e9 12927
4d20cd86 12928 if (!crtc->state->active)
cfb23ed6
ML		 12929 continue;
12930
e3b247da
VS		 12931 intel_pipe_config_sanity_check(dev_priv, pipe_config);
12932
4d20cd86
ML		 12933 sw_config = to_intel_crtc_state(crtc->state);
12934 if (!intel_pipe_config_compare(dev, sw_config,
12935 pipe_config, false)) {
e2c719b7 12936 I915_STATE_WARN(1, "pipe state doesn't match!\n");
4d20cd86 12937 intel_dump_pipe_config(intel_crtc, pipe_config,
c0b03411 12938 "[hw state]");
4d20cd86 12939 intel_dump_pipe_config(intel_crtc, sw_config,
c0b03411
DV		 12940 "[sw state]");
12941 }
8af6cf88
DV		 12942 }
12943}
12944
91d1b4bd
DV		 12945static void
12946check_shared_dpll_state(struct drm_device *dev)
12947{
fbee40df 12948 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 12949 struct intel_crtc *crtc;
12950 struct intel_dpll_hw_state dpll_hw_state;
12951 int i;
5358901f
DV		 12952
12953 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8106ddbd
ACO		 12954 struct intel_shared_dpll *pll =
12955 intel_get_shared_dpll_by_id(dev_priv, i);
2dd66ebd 12956 unsigned enabled_crtcs = 0, active_crtcs = 0;
5358901f
DV		 12957 bool active;
12958
12959 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12960
12961 DRM_DEBUG_KMS("%s\n", pll->name);
12962
2edd6443 12963 active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
5358901f 12964
2dd66ebd
ML		 12965 I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask,
12966 "more active pll users than references: %x vs %x\n",
12967 pll->active_mask, pll->config.crtc_mask);
9d16da65
ACO		 12968
12969 if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
2dd66ebd
ML		 12970 I915_STATE_WARN(!pll->on && pll->active_mask,
12971 "pll in active use but not on in sw tracking\n");
12972 I915_STATE_WARN(pll->on && !pll->active_mask,
12973 "pll is on but not used by any active crtc\n");
9d16da65
ACO		 12974 I915_STATE_WARN(pll->on != active,
12975 "pll on state mismatch (expected %i, found %i)\n",
12976 pll->on, active);
12977 }
5358901f 12978
d3fcc808 12979 for_each_intel_crtc(dev, crtc) {
8106ddbd 12980 if (crtc->base.state->enable && crtc->config->shared_dpll == pll)
2dd66ebd
ML		 12981 enabled_crtcs |= 1 << drm_crtc_index(&crtc->base);
12982 if (crtc->base.state->active && crtc->config->shared_dpll == pll)
12983 active_crtcs |= 1 << drm_crtc_index(&crtc->base);
5358901f 12984 }
2dd66ebd
ML		 12985
12986 I915_STATE_WARN(pll->active_mask != active_crtcs,
12987 "pll active crtcs mismatch (expected %x, found %x)\n",
12988 pll->active_mask, active_crtcs);
12989 I915_STATE_WARN(pll->config.crtc_mask != enabled_crtcs,
12990 "pll enabled crtcs mismatch (expected %x, found %x)\n",
12991 pll->config.crtc_mask, enabled_crtcs);
66e985c0 12992
e2c719b7 12993 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
66e985c0
DV		 12994 sizeof(dpll_hw_state)),
12995 "pll hw state mismatch\n");
5358901f 12996 }
8af6cf88
DV		 12997}
12998
ee165b1a
ML		 12999static void
13000intel_modeset_check_state(struct drm_device *dev,
13001 struct drm_atomic_state *old_state)
91d1b4bd 13002{
08db6652 13003 check_wm_state(dev);
35dd3c64 13004 check_connector_state(dev, old_state);
91d1b4bd 13005 check_encoder_state(dev);
4d20cd86 13006 check_crtc_state(dev, old_state);
91d1b4bd
DV		 13007 check_shared_dpll_state(dev);
13008}
13009
80715b2f
VS		 13010static void update_scanline_offset(struct intel_crtc *crtc)
13011{
13012 struct drm_device *dev = crtc->base.dev;
13013
13014 /*
13015 * The scanline counter increments at the leading edge of hsync.
13016 *
13017 * On most platforms it starts counting from vtotal-1 on the
13018 * first active line. That means the scanline counter value is
13019 * always one less than what we would expect. Ie. just after
13020 * start of vblank, which also occurs at start of hsync (on the
13021 * last active line), the scanline counter will read vblank_start-1.
13022 *
13023 * On gen2 the scanline counter starts counting from 1 instead
13024 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13025 * to keep the value positive), instead of adding one.
13026 *
13027 * On HSW+ the behaviour of the scanline counter depends on the output
13028 * type. For DP ports it behaves like most other platforms, but on HDMI
13029 * there's an extra 1 line difference. So we need to add two instead of
13030 * one to the value.
13031 */
13032 if (IS_GEN2(dev)) {
124abe07 13033 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
80715b2f
VS		 13034 int vtotal;
13035
124abe07
VS		 13036 vtotal = adjusted_mode->crtc_vtotal;
13037 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
80715b2f
VS		 13038 vtotal /= 2;
13039
13040 crtc->scanline_offset = vtotal - 1;
13041 } else if (HAS_DDI(dev) &&
409ee761 13042 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
80715b2f
VS		 13043 crtc->scanline_offset = 2;
13044 } else
13045 crtc->scanline_offset = 1;
13046}
13047
ad421372 13048static void intel_modeset_clear_plls(struct drm_atomic_state *state)
ed6739ef 13049{
225da59b 13050 struct drm_device *dev = state->dev;
ed6739ef 13051 struct drm_i915_private *dev_priv = to_i915(dev);
ad421372 13052 struct intel_shared_dpll_config *shared_dpll = NULL;
0a9ab303
ACO		 13053 struct drm_crtc *crtc;
13054 struct drm_crtc_state *crtc_state;
0a9ab303 13055 int i;
ed6739ef
ACO		 13056
13057 if (!dev_priv->display.crtc_compute_clock)
ad421372 13058 return;
ed6739ef 13059
0a9ab303 13060 for_each_crtc_in_state(state, crtc, crtc_state, i) {
fb1a38a9 13061 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8106ddbd
ACO		 13062 struct intel_shared_dpll *old_dpll =
13063 to_intel_crtc_state(crtc->state)->shared_dpll;
0a9ab303 13064
fb1a38a9 13065 if (!needs_modeset(crtc_state))
225da59b
ACO		 13066 continue;
13067
8106ddbd 13068 to_intel_crtc_state(crtc_state)->shared_dpll = NULL;
fb1a38a9 13069
8106ddbd 13070 if (!old_dpll)
fb1a38a9 13071 continue;
0a9ab303 13072
ad421372
ML		 13073 if (!shared_dpll)
13074 shared_dpll = intel_atomic_get_shared_dpll_state(state);
ed6739ef 13075
8106ddbd 13076 intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc);
ad421372 13077 }
ed6739ef
ACO		 13078}
13079
99d736a2
ML		 13080/*
13081 * This implements the workaround described in the "notes" section of the mode
13082 * set sequence documentation. When going from no pipes or single pipe to
13083 * multiple pipes, and planes are enabled after the pipe, we need to wait at
13084 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13085 */
13086static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13087{
13088 struct drm_crtc_state *crtc_state;
13089 struct intel_crtc *intel_crtc;
13090 struct drm_crtc *crtc;
13091 struct intel_crtc_state *first_crtc_state = NULL;
13092 struct intel_crtc_state *other_crtc_state = NULL;
13093 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13094 int i;
13095
13096 /* look at all crtc's that are going to be enabled in during modeset */
13097 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13098 intel_crtc = to_intel_crtc(crtc);
13099
13100 if (!crtc_state->active || !needs_modeset(crtc_state))
13101 continue;
13102
13103 if (first_crtc_state) {
13104 other_crtc_state = to_intel_crtc_state(crtc_state);
13105 break;
13106 } else {
13107 first_crtc_state = to_intel_crtc_state(crtc_state);
13108 first_pipe = intel_crtc->pipe;
13109 }
13110 }
13111
13112 /* No workaround needed? */
13113 if (!first_crtc_state)
13114 return 0;
13115
13116 /* w/a possibly needed, check how many crtc's are already enabled. */
13117 for_each_intel_crtc(state->dev, intel_crtc) {
13118 struct intel_crtc_state *pipe_config;
13119
13120 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13121 if (IS_ERR(pipe_config))
13122 return PTR_ERR(pipe_config);
13123
13124 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13125
13126 if (!pipe_config->base.active ||
13127 needs_modeset(&pipe_config->base))
13128 continue;
13129
13130 /* 2 or more enabled crtcs means no need for w/a */
13131 if (enabled_pipe != INVALID_PIPE)
13132 return 0;
13133
13134 enabled_pipe = intel_crtc->pipe;
13135 }
13136
13137 if (enabled_pipe != INVALID_PIPE)
13138 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13139 else if (other_crtc_state)
13140 other_crtc_state->hsw_workaround_pipe = first_pipe;
13141
13142 return 0;
13143}
13144
27c329ed
ML		 13145static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13146{
13147 struct drm_crtc *crtc;
13148 struct drm_crtc_state *crtc_state;
13149 int ret = 0;
13150
13151 /* add all active pipes to the state */
13152 for_each_crtc(state->dev, crtc) {
13153 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13154 if (IS_ERR(crtc_state))
13155 return PTR_ERR(crtc_state);
13156
13157 if (!crtc_state->active || needs_modeset(crtc_state))
13158 continue;
13159
13160 crtc_state->mode_changed = true;
13161
13162 ret = drm_atomic_add_affected_connectors(state, crtc);
13163 if (ret)
13164 break;
13165
13166 ret = drm_atomic_add_affected_planes(state, crtc);
13167 if (ret)
13168 break;
13169 }
13170
13171 return ret;
13172}
13173
c347a676 13174static int intel_modeset_checks(struct drm_atomic_state *state)
054518dd 13175{
565602d7
ML		 13176 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13177 struct drm_i915_private *dev_priv = state->dev->dev_private;
13178 struct drm_crtc *crtc;
13179 struct drm_crtc_state *crtc_state;
13180 int ret = 0, i;
054518dd 13181
b359283a
ML		 13182 if (!check_digital_port_conflicts(state)) {
13183 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13184 return -EINVAL;
13185 }
13186
565602d7
ML		 13187 intel_state->modeset = true;
13188 intel_state->active_crtcs = dev_priv->active_crtcs;
13189
13190 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13191 if (crtc_state->active)
13192 intel_state->active_crtcs |= 1 << i;
13193 else
13194 intel_state->active_crtcs &= ~(1 << i);
13195 }
13196
054518dd
ACO		 13197 /*
13198 * See if the config requires any additional preparation, e.g.
13199 * to adjust global state with pipes off. We need to do this
13200 * here so we can get the modeset_pipe updated config for the new
13201 * mode set on this crtc. For other crtcs we need to use the
13202 * adjusted_mode bits in the crtc directly.
13203 */
27c329ed 13204 if (dev_priv->display.modeset_calc_cdclk) {
27c329ed
ML		 13205 ret = dev_priv->display.modeset_calc_cdclk(state);
13206
1a617b77 13207 if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq)
27c329ed
ML		 13208 ret = intel_modeset_all_pipes(state);
13209
13210 if (ret < 0)
054518dd 13211 return ret;
e8788cbc
ML		 13212
13213 DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
13214 intel_state->cdclk, intel_state->dev_cdclk);
27c329ed 13215 } else
1a617b77 13216 to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
054518dd 13217
ad421372 13218 intel_modeset_clear_plls(state);
054518dd 13219
565602d7 13220 if (IS_HASWELL(dev_priv))
ad421372 13221 return haswell_mode_set_planes_workaround(state);
99d736a2 13222
ad421372 13223 return 0;
c347a676
ACO		 13224}
13225
aa363136
MR		 13226/*
13227 * Handle calculation of various watermark data at the end of the atomic check
13228 * phase. The code here should be run after the per-crtc and per-plane 'check'
13229 * handlers to ensure that all derived state has been updated.
13230 */
13231static void calc_watermark_data(struct drm_atomic_state *state)
13232{
13233 struct drm_device *dev = state->dev;
13234 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13235 struct drm_crtc *crtc;
13236 struct drm_crtc_state *cstate;
13237 struct drm_plane *plane;
13238 struct drm_plane_state *pstate;
13239
13240 /*
13241 * Calculate watermark configuration details now that derived
13242 * plane/crtc state is all properly updated.
13243 */
13244 drm_for_each_crtc(crtc, dev) {
13245 cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?:
13246 crtc->state;
13247
13248 if (cstate->active)
13249 intel_state->wm_config.num_pipes_active++;
13250 }
13251 drm_for_each_legacy_plane(plane, dev) {
13252 pstate = drm_atomic_get_existing_plane_state(state, plane) ?:
13253 plane->state;
13254
13255 if (!to_intel_plane_state(pstate)->visible)
13256 continue;
13257
13258 intel_state->wm_config.sprites_enabled = true;
13259 if (pstate->crtc_w != pstate->src_w >> 16 ||
13260 pstate->crtc_h != pstate->src_h >> 16)
13261 intel_state->wm_config.sprites_scaled = true;
13262 }
13263}
13264
74c090b1
ML		 13265/**
13266 * intel_atomic_check - validate state object
13267 * @dev: drm device
13268 * @state: state to validate
13269 */
13270static int intel_atomic_check(struct drm_device *dev,
13271 struct drm_atomic_state *state)
c347a676 13272{
dd8b3bdb 13273 struct drm_i915_private *dev_priv = to_i915(dev);
aa363136 13274 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
c347a676
ACO		 13275 struct drm_crtc *crtc;
13276 struct drm_crtc_state *crtc_state;
13277 int ret, i;
61333b60 13278 bool any_ms = false;
c347a676 13279
74c090b1 13280 ret = drm_atomic_helper_check_modeset(dev, state);
054518dd
ACO		 13281 if (ret)
13282 return ret;
13283
c347a676 13284 for_each_crtc_in_state(state, crtc, crtc_state, i) {
cfb23ed6
ML		 13285 struct intel_crtc_state *pipe_config =
13286 to_intel_crtc_state(crtc_state);
1ed51de9
DV		 13287
13288 /* Catch I915_MODE_FLAG_INHERITED */
13289 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13290 crtc_state->mode_changed = true;
cfb23ed6 13291
61333b60
ML		 13292 if (!crtc_state->enable) {
13293 if (needs_modeset(crtc_state))
13294 any_ms = true;
c347a676 13295 continue;
61333b60 13296 }
c347a676 13297
26495481 13298 if (!needs_modeset(crtc_state))
cfb23ed6
ML		 13299 continue;
13300
26495481
DV		 13301 /* FIXME: For only active_changed we shouldn't need to do any
13302 * state recomputation at all. */
13303
1ed51de9
DV		 13304 ret = drm_atomic_add_affected_connectors(state, crtc);
13305 if (ret)
13306 return ret;
b359283a 13307
cfb23ed6 13308 ret = intel_modeset_pipe_config(crtc, pipe_config);
c347a676
ACO		 13309 if (ret)
13310 return ret;
13311
73831236 13312 if (i915.fastboot &&
dd8b3bdb 13313 intel_pipe_config_compare(dev,
cfb23ed6 13314 to_intel_crtc_state(crtc->state),
1ed51de9 13315 pipe_config, true)) {
26495481 13316 crtc_state->mode_changed = false;
bfd16b2a 13317 to_intel_crtc_state(crtc_state)->update_pipe = true;
26495481
DV		 13318 }
13319
13320 if (needs_modeset(crtc_state)) {
13321 any_ms = true;
cfb23ed6
ML		 13322
13323 ret = drm_atomic_add_affected_planes(state, crtc);
13324 if (ret)
13325 return ret;
13326 }
61333b60 13327
26495481
DV		 13328 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13329 needs_modeset(crtc_state) ?
13330 "[modeset]" : "[fastset]");
c347a676
ACO		 13331 }
13332
61333b60
ML		 13333 if (any_ms) {
13334 ret = intel_modeset_checks(state);
13335
13336 if (ret)
13337 return ret;
27c329ed 13338 } else
dd8b3bdb 13339 intel_state->cdclk = dev_priv->cdclk_freq;
76305b1a 13340
dd8b3bdb 13341 ret = drm_atomic_helper_check_planes(dev, state);
aa363136
MR		 13342 if (ret)
13343 return ret;
13344
f51be2e0 13345 intel_fbc_choose_crtc(dev_priv, state);
aa363136
MR		 13346 calc_watermark_data(state);
13347
13348 return 0;
054518dd
ACO		 13349}
13350
5008e874
ML		 13351static int intel_atomic_prepare_commit(struct drm_device *dev,
13352 struct drm_atomic_state *state,
13353 bool async)
13354{
7580d774
ML		 13355 struct drm_i915_private *dev_priv = dev->dev_private;
13356 struct drm_plane_state *plane_state;
5008e874 13357 struct drm_crtc_state *crtc_state;
7580d774 13358 struct drm_plane *plane;
5008e874
ML		 13359 struct drm_crtc *crtc;
13360 int i, ret;
13361
13362 if (async) {
13363 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13364 return -EINVAL;
13365 }
13366
13367 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13368 ret = intel_crtc_wait_for_pending_flips(crtc);
13369 if (ret)
13370 return ret;
7580d774
ML		 13371
13372 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
13373 flush_workqueue(dev_priv->wq);
5008e874
ML		 13374 }
13375
f935675f
ML		 13376 ret = mutex_lock_interruptible(&dev->struct_mutex);
13377 if (ret)
13378 return ret;
13379
5008e874 13380 ret = drm_atomic_helper_prepare_planes(dev, state);
7580d774
ML		 13381 if (!ret && !async && !i915_reset_in_progress(&dev_priv->gpu_error)) {
13382 u32 reset_counter;
13383
13384 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
13385 mutex_unlock(&dev->struct_mutex);
13386
13387 for_each_plane_in_state(state, plane, plane_state, i) {
13388 struct intel_plane_state *intel_plane_state =
13389 to_intel_plane_state(plane_state);
13390
13391 if (!intel_plane_state->wait_req)
13392 continue;
13393
13394 ret = __i915_wait_request(intel_plane_state->wait_req,
13395 reset_counter, true,
13396 NULL, NULL);
13397
13398 /* Swallow -EIO errors to allow updates during hw lockup. */
13399 if (ret == -EIO)
13400 ret = 0;
13401
13402 if (ret)
13403 break;
13404 }
13405
13406 if (!ret)
13407 return 0;
13408
13409 mutex_lock(&dev->struct_mutex);
13410 drm_atomic_helper_cleanup_planes(dev, state);
13411 }
5008e874 13412
f935675f 13413 mutex_unlock(&dev->struct_mutex);
5008e874
ML		 13414 return ret;
13415}
13416
e8861675
ML		 13417static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
13418 struct drm_i915_private *dev_priv,
13419 unsigned crtc_mask)
13420{
13421 unsigned last_vblank_count[I915_MAX_PIPES];
13422 enum pipe pipe;
13423 int ret;
13424
13425 if (!crtc_mask)
13426 return;
13427
13428 for_each_pipe(dev_priv, pipe) {
13429 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
13430
13431 if (!((1 << pipe) & crtc_mask))
13432 continue;
13433
13434 ret = drm_crtc_vblank_get(crtc);
13435 if (WARN_ON(ret != 0)) {
13436 crtc_mask &= ~(1 << pipe);
13437 continue;
13438 }
13439
13440 last_vblank_count[pipe] = drm_crtc_vblank_count(crtc);
13441 }
13442
13443 for_each_pipe(dev_priv, pipe) {
13444 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
13445 long lret;
13446
13447 if (!((1 << pipe) & crtc_mask))
13448 continue;
13449
13450 lret = wait_event_timeout(dev->vblank[pipe].queue,
13451 last_vblank_count[pipe] !=
13452 drm_crtc_vblank_count(crtc),
13453 msecs_to_jiffies(50));
13454
13455 WARN_ON(!lret);
13456
13457 drm_crtc_vblank_put(crtc);
13458 }
13459}
13460
13461static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
13462{
13463 /* fb updated, need to unpin old fb */
13464 if (crtc_state->fb_changed)
13465 return true;
13466
13467 /* wm changes, need vblank before final wm's */
caed361d 13468 if (crtc_state->update_wm_post)
e8861675
ML		 13469 return true;
13470
13471 /*
13472 * cxsr is re-enabled after vblank.
caed361d 13473 * This is already handled by crtc_state->update_wm_post,
e8861675
ML		 13474 * but added for clarity.
13475 */
13476 if (crtc_state->disable_cxsr)
13477 return true;
13478
13479 return false;
13480}
13481
74c090b1
ML		 13482/**
13483 * intel_atomic_commit - commit validated state object
13484 * @dev: DRM device
13485 * @state: the top-level driver state object
13486 * @async: asynchronous commit
13487 *
13488 * This function commits a top-level state object that has been validated
13489 * with drm_atomic_helper_check().
13490 *
13491 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13492 * we can only handle plane-related operations and do not yet support
13493 * asynchronous commit.
13494 *
13495 * RETURNS
13496 * Zero for success or -errno.
13497 */
13498static int intel_atomic_commit(struct drm_device *dev,
13499 struct drm_atomic_state *state,
13500 bool async)
a6778b3c 13501{
565602d7 13502 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
fbee40df 13503 struct drm_i915_private *dev_priv = dev->dev_private;
29ceb0e6 13504 struct drm_crtc_state *old_crtc_state;
7580d774 13505 struct drm_crtc *crtc;
ed4a6a7c 13506 struct intel_crtc_state *intel_cstate;
565602d7
ML		 13507 int ret = 0, i;
13508 bool hw_check = intel_state->modeset;
33c8df89 13509 unsigned long put_domains[I915_MAX_PIPES] = {};
e8861675 13510 unsigned crtc_vblank_mask = 0;
a6778b3c 13511
5008e874 13512 ret = intel_atomic_prepare_commit(dev, state, async);
7580d774
ML		 13513 if (ret) {
13514 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
d4afb8cc 13515 return ret;
7580d774 13516 }
d4afb8cc 13517
1c5e19f8 13518 drm_atomic_helper_swap_state(dev, state);
a1475e77
ML		 13519 dev_priv->wm.config = intel_state->wm_config;
13520 intel_shared_dpll_commit(state);
1c5e19f8 13521
565602d7
ML		 13522 if (intel_state->modeset) {
13523 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
13524 sizeof(intel_state->min_pixclk));
13525 dev_priv->active_crtcs = intel_state->active_crtcs;
1a617b77 13526 dev_priv->atomic_cdclk_freq = intel_state->cdclk;
33c8df89
ML		 13527
13528 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
565602d7
ML		 13529 }
13530
29ceb0e6 13531 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
a539205a
ML		 13532 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13533
33c8df89
ML		 13534 if (needs_modeset(crtc->state) ||
13535 to_intel_crtc_state(crtc->state)->update_pipe) {
13536 hw_check = true;
13537
13538 put_domains[to_intel_crtc(crtc)->pipe] =
13539 modeset_get_crtc_power_domains(crtc,
13540 to_intel_crtc_state(crtc->state));
13541 }
13542
61333b60
ML		 13543 if (!needs_modeset(crtc->state))
13544 continue;
13545
29ceb0e6 13546 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
460da916 13547
29ceb0e6
VS		 13548 if (old_crtc_state->active) {
13549 intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
a539205a 13550 dev_priv->display.crtc_disable(crtc);
eddfcbcd 13551 intel_crtc->active = false;
58f9c0bc 13552 intel_fbc_disable(intel_crtc);
eddfcbcd 13553 intel_disable_shared_dpll(intel_crtc);
9bbc8258
VS		 13554
13555 /*
13556 * Underruns don't always raise
13557 * interrupts, so check manually.
13558 */
13559 intel_check_cpu_fifo_underruns(dev_priv);
13560 intel_check_pch_fifo_underruns(dev_priv);
b9001114
ML		 13561
13562 if (!crtc->state->active)
13563 intel_update_watermarks(crtc);
a539205a 13564 }
b8cecdf5 13565 }
7758a113 13566
ea9d758d
DV		 13567 /* Only after disabling all output pipelines that will be changed can we
13568 * update the the output configuration. */
4740b0f2 13569 intel_modeset_update_crtc_state(state);
f6e5b160 13570
565602d7 13571 if (intel_state->modeset) {
4740b0f2 13572 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
33c8df89
ML		 13573
13574 if (dev_priv->display.modeset_commit_cdclk &&
13575 intel_state->dev_cdclk != dev_priv->cdclk_freq)
13576 dev_priv->display.modeset_commit_cdclk(state);
4740b0f2 13577 }
47fab737 13578
a6778b3c 13579 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
29ceb0e6 13580 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
f6ac4b2a
ML		 13581 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13582 bool modeset = needs_modeset(crtc->state);
e8861675
ML		 13583 struct intel_crtc_state *pipe_config =
13584 to_intel_crtc_state(crtc->state);
13585 bool update_pipe = !modeset && pipe_config->update_pipe;
9f836f90 13586
f6ac4b2a 13587 if (modeset && crtc->state->active) {
a539205a
ML		 13588 update_scanline_offset(to_intel_crtc(crtc));
13589 dev_priv->display.crtc_enable(crtc);
13590 }
80715b2f 13591
f6ac4b2a 13592 if (!modeset)
29ceb0e6 13593 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
f6ac4b2a 13594
31ae71fc
ML		 13595 if (crtc->state->active &&
13596 drm_atomic_get_existing_plane_state(state, crtc->primary))
49227c4a
PZ		 13597 intel_fbc_enable(intel_crtc);
13598
6173ee28
ML		 13599 if (crtc->state->active &&
13600 (crtc->state->planes_changed || update_pipe))
29ceb0e6 13601 drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
bfd16b2a 13602
e8861675
ML		 13603 if (pipe_config->base.active && needs_vblank_wait(pipe_config))
13604 crtc_vblank_mask |= 1 << i;
80715b2f 13605 }
a6778b3c 13606
a6778b3c 13607 /* FIXME: add subpixel order */
83a57153 13608
e8861675
ML		 13609 if (!state->legacy_cursor_update)
13610 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
f935675f 13611
ed4a6a7c
MR		 13612 /*
13613 * Now that the vblank has passed, we can go ahead and program the
13614 * optimal watermarks on platforms that need two-step watermark
13615 * programming.
13616 *
13617 * TODO: Move this (and other cleanup) to an async worker eventually.
13618 */
29ceb0e6 13619 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
ed4a6a7c
MR		 13620 intel_cstate = to_intel_crtc_state(crtc->state);
13621
13622 if (dev_priv->display.optimize_watermarks)
13623 dev_priv->display.optimize_watermarks(intel_cstate);
13624 }
13625
177246a8
MR		 13626 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13627 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
13628
13629 if (put_domains[i])
13630 modeset_put_power_domains(dev_priv, put_domains[i]);
13631 }
13632
13633 if (intel_state->modeset)
13634 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
13635
f935675f 13636 mutex_lock(&dev->struct_mutex);
d4afb8cc 13637 drm_atomic_helper_cleanup_planes(dev, state);
f935675f 13638 mutex_unlock(&dev->struct_mutex);
2bfb4627 13639
565602d7 13640 if (hw_check)
ee165b1a
ML		 13641 intel_modeset_check_state(dev, state);
13642
13643 drm_atomic_state_free(state);
f30da187 13644
75714940
MK		 13645 /* As one of the primary mmio accessors, KMS has a high likelihood
13646 * of triggering bugs in unclaimed access. After we finish
13647 * modesetting, see if an error has been flagged, and if so
13648 * enable debugging for the next modeset - and hope we catch
13649 * the culprit.
13650 *
13651 * XXX note that we assume display power is on at this point.
13652 * This might hold true now but we need to add pm helper to check
13653 * unclaimed only when the hardware is on, as atomic commits
13654 * can happen also when the device is completely off.
13655 */
13656 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
13657
74c090b1 13658 return 0;
7f27126e
JB		 13659}
13660
c0c36b94
CW		 13661void intel_crtc_restore_mode(struct drm_crtc *crtc)
13662{
83a57153
ACO		 13663 struct drm_device *dev = crtc->dev;
13664 struct drm_atomic_state *state;
e694eb02 13665 struct drm_crtc_state *crtc_state;
2bfb4627 13666 int ret;
83a57153
ACO		 13667
13668 state = drm_atomic_state_alloc(dev);
13669 if (!state) {
e694eb02 13670 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
83a57153
ACO		 13671 crtc->base.id);
13672 return;
13673 }
13674
e694eb02 13675 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
83a57153 13676
e694eb02
ML		 13677retry:
13678 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13679 ret = PTR_ERR_OR_ZERO(crtc_state);
13680 if (!ret) {
13681 if (!crtc_state->active)
13682 goto out;
83a57153 13683
e694eb02 13684 crtc_state->mode_changed = true;
74c090b1 13685 ret = drm_atomic_commit(state);
83a57153
ACO		 13686 }
13687
e694eb02
ML		 13688 if (ret == -EDEADLK) {
13689 drm_atomic_state_clear(state);
13690 drm_modeset_backoff(state->acquire_ctx);
13691 goto retry;
4ed9fb37 13692 }
4be07317 13693
2bfb4627 13694 if (ret)
e694eb02 13695out:
2bfb4627 13696 drm_atomic_state_free(state);
c0c36b94
CW		 13697}
13698
25c5b266
DV		 13699#undef for_each_intel_crtc_masked
13700
f6e5b160 13701static const struct drm_crtc_funcs intel_crtc_funcs = {
82cf435b 13702 .gamma_set = drm_atomic_helper_legacy_gamma_set,
74c090b1 13703 .set_config = drm_atomic_helper_set_config,
82cf435b 13704 .set_property = drm_atomic_helper_crtc_set_property,
f6e5b160
CW		 13705 .destroy = intel_crtc_destroy,
13706 .page_flip = intel_crtc_page_flip,
1356837e
MR		 13707 .atomic_duplicate_state = intel_crtc_duplicate_state,
13708 .atomic_destroy_state = intel_crtc_destroy_state,
f6e5b160
CW		 13709};
13710
6beb8c23
MR		 13711/**
13712 * intel_prepare_plane_fb - Prepare fb for usage on plane
13713 * @plane: drm plane to prepare for
13714 * @fb: framebuffer to prepare for presentation
13715 *
13716 * Prepares a framebuffer for usage on a display plane. Generally this
13717 * involves pinning the underlying object and updating the frontbuffer tracking
13718 * bits. Some older platforms need special physical address handling for
13719 * cursor planes.
13720 *
f935675f
ML		 13721 * Must be called with struct_mutex held.
13722 *
6beb8c23
MR		 13723 * Returns 0 on success, negative error code on failure.
13724 */
13725int
13726intel_prepare_plane_fb(struct drm_plane *plane,
d136dfee 13727 const struct drm_plane_state *new_state)
465c120c
MR		 13728{
13729 struct drm_device *dev = plane->dev;
844f9111 13730 struct drm_framebuffer *fb = new_state->fb;
6beb8c23 13731 struct intel_plane *intel_plane = to_intel_plane(plane);
6beb8c23 13732 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
1ee49399 13733 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
6beb8c23 13734 int ret = 0;
465c120c 13735
1ee49399 13736 if (!obj && !old_obj)
465c120c
MR		 13737 return 0;
13738
5008e874
ML		 13739 if (old_obj) {
13740 struct drm_crtc_state *crtc_state =
13741 drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
13742
13743 /* Big Hammer, we also need to ensure that any pending
13744 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13745 * current scanout is retired before unpinning the old
13746 * framebuffer. Note that we rely on userspace rendering
13747 * into the buffer attached to the pipe they are waiting
13748 * on. If not, userspace generates a GPU hang with IPEHR
13749 * point to the MI_WAIT_FOR_EVENT.
13750 *
13751 * This should only fail upon a hung GPU, in which case we
13752 * can safely continue.
13753 */
13754 if (needs_modeset(crtc_state))
13755 ret = i915_gem_object_wait_rendering(old_obj, true);
13756
13757 /* Swallow -EIO errors to allow updates during hw lockup. */
13758 if (ret && ret != -EIO)
f935675f 13759 return ret;
5008e874
ML		 13760 }
13761
3c28ff22
AG		 13762 /* For framebuffer backed by dmabuf, wait for fence */
13763 if (obj && obj->base.dma_buf) {
bcf8be27
ML		 13764 long lret;
13765
13766 lret = reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
13767 false, true,
13768 MAX_SCHEDULE_TIMEOUT);
13769 if (lret == -ERESTARTSYS)
13770 return lret;
3c28ff22 13771
bcf8be27 13772 WARN(lret < 0, "waiting returns %li\n", lret);
3c28ff22
AG		 13773 }
13774
1ee49399
ML		 13775 if (!obj) {
13776 ret = 0;
13777 } else if (plane->type == DRM_PLANE_TYPE_CURSOR &&
6beb8c23
MR		 13778 INTEL_INFO(dev)->cursor_needs_physical) {
13779 int align = IS_I830(dev) ? 16 * 1024 : 256;
13780 ret = i915_gem_object_attach_phys(obj, align);
13781 if (ret)
13782 DRM_DEBUG_KMS("failed to attach phys object\n");
13783 } else {
3465c580 13784 ret = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
6beb8c23 13785 }
465c120c 13786
7580d774
ML		 13787 if (ret == 0) {
13788 if (obj) {
13789 struct intel_plane_state *plane_state =
13790 to_intel_plane_state(new_state);
13791
13792 i915_gem_request_assign(&plane_state->wait_req,
13793 obj->last_write_req);
13794 }
13795
a9ff8714 13796 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
7580d774 13797 }
fdd508a6 13798
6beb8c23
MR		 13799 return ret;
13800}
13801
38f3ce3a
MR		 13802/**
13803 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13804 * @plane: drm plane to clean up for
13805 * @fb: old framebuffer that was on plane
13806 *
13807 * Cleans up a framebuffer that has just been removed from a plane.
f935675f
ML		 13808 *
13809 * Must be called with struct_mutex held.
38f3ce3a
MR		 13810 */
13811void
13812intel_cleanup_plane_fb(struct drm_plane *plane,
d136dfee 13813 const struct drm_plane_state *old_state)
38f3ce3a
MR		 13814{
13815 struct drm_device *dev = plane->dev;
1ee49399 13816 struct intel_plane *intel_plane = to_intel_plane(plane);
7580d774 13817 struct intel_plane_state *old_intel_state;
1ee49399
ML		 13818 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
13819 struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
38f3ce3a 13820
7580d774
ML		 13821 old_intel_state = to_intel_plane_state(old_state);
13822
1ee49399 13823 if (!obj && !old_obj)
38f3ce3a
MR		 13824 return;
13825
1ee49399
ML		 13826 if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
13827 !INTEL_INFO(dev)->cursor_needs_physical))
3465c580 13828 intel_unpin_fb_obj(old_state->fb, old_state->rotation);
1ee49399
ML		 13829
13830 /* prepare_fb aborted? */
13831 if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) ||
13832 (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit)))
13833 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
7580d774
ML		 13834
13835 i915_gem_request_assign(&old_intel_state->wait_req, NULL);
465c120c
MR		 13836}
13837
6156a456
CK		 13838int
13839skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13840{
13841 int max_scale;
13842 struct drm_device *dev;
13843 struct drm_i915_private *dev_priv;
13844 int crtc_clock, cdclk;
13845
bf8a0af0 13846 if (!intel_crtc || !crtc_state->base.enable)
6156a456
CK		 13847 return DRM_PLANE_HELPER_NO_SCALING;
13848
13849 dev = intel_crtc->base.dev;
13850 dev_priv = dev->dev_private;
13851 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
27c329ed 13852 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
6156a456 13853
54bf1ce6 13854 if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
6156a456
CK		 13855 return DRM_PLANE_HELPER_NO_SCALING;
13856
13857 /*
13858 * skl max scale is lower of:
13859 * close to 3 but not 3, -1 is for that purpose
13860 * or
13861 * cdclk/crtc_clock
13862 */
13863 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13864
13865 return max_scale;
13866}
13867
465c120c 13868static int
3c692a41 13869intel_check_primary_plane(struct drm_plane *plane,
061e4b8d 13870 struct intel_crtc_state *crtc_state,
3c692a41
GP		 13871 struct intel_plane_state *state)
13872{
2b875c22
MR		 13873 struct drm_crtc *crtc = state->base.crtc;
13874 struct drm_framebuffer *fb = state->base.fb;
6156a456 13875 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
061e4b8d
ML		 13876 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13877 bool can_position = false;
465c120c 13878
693bdc28
VS		 13879 if (INTEL_INFO(plane->dev)->gen >= 9) {
13880 /* use scaler when colorkey is not required */
13881 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
13882 min_scale = 1;
13883 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13884 }
d8106366 13885 can_position = true;
6156a456 13886 }
d8106366 13887
061e4b8d
ML		 13888 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13889 &state->dst, &state->clip,
da20eabd
ML		 13890 min_scale, max_scale,
13891 can_position, true,
13892 &state->visible);
14af293f
GP		 13893}
13894
613d2b27
ML		 13895static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13896 struct drm_crtc_state *old_crtc_state)
3c692a41 13897{
32b7eeec 13898 struct drm_device *dev = crtc->dev;
3c692a41 13899 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
bfd16b2a
ML		 13900 struct intel_crtc_state *old_intel_state =
13901 to_intel_crtc_state(old_crtc_state);
13902 bool modeset = needs_modeset(crtc->state);
3c692a41 13903
c34c9ee4 13904 /* Perform vblank evasion around commit operation */
62852622 13905 intel_pipe_update_start(intel_crtc);
0583236e 13906
bfd16b2a
ML		 13907 if (modeset)
13908 return;
13909
20a34e78
ML		 13910 if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) {
13911 intel_color_set_csc(crtc->state);
13912 intel_color_load_luts(crtc->state);
13913 }
13914
bfd16b2a
ML		 13915 if (to_intel_crtc_state(crtc->state)->update_pipe)
13916 intel_update_pipe_config(intel_crtc, old_intel_state);
13917 else if (INTEL_INFO(dev)->gen >= 9)
0583236e 13918 skl_detach_scalers(intel_crtc);
32b7eeec
MR		 13919}
13920
613d2b27
ML		 13921static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13922 struct drm_crtc_state *old_crtc_state)
32b7eeec 13923{
32b7eeec 13924 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
32b7eeec 13925
62852622 13926 intel_pipe_update_end(intel_crtc);
3c692a41
GP		 13927}
13928
cf4c7c12 13929/**
4a3b8769
MR		 13930 * intel_plane_destroy - destroy a plane
13931 * @plane: plane to destroy
cf4c7c12 13932 *
4a3b8769
MR		 13933 * Common destruction function for all types of planes (primary, cursor,
13934 * sprite).
cf4c7c12 13935 */
4a3b8769 13936void intel_plane_destroy(struct drm_plane *plane)
465c120c
MR		 13937{
13938 struct intel_plane *intel_plane = to_intel_plane(plane);
13939 drm_plane_cleanup(plane);
13940 kfree(intel_plane);
13941}
13942
65a3fea0 13943const struct drm_plane_funcs intel_plane_funcs = {
70a101f8
MR		 13944 .update_plane = drm_atomic_helper_update_plane,
13945 .disable_plane = drm_atomic_helper_disable_plane,
3d7d6510 13946 .destroy = intel_plane_destroy,
c196e1d6 13947 .set_property = drm_atomic_helper_plane_set_property,
a98b3431
MR		 13948 .atomic_get_property = intel_plane_atomic_get_property,
13949 .atomic_set_property = intel_plane_atomic_set_property,
ea2c67bb
MR		 13950 .atomic_duplicate_state = intel_plane_duplicate_state,
13951 .atomic_destroy_state = intel_plane_destroy_state,
13952
465c120c
MR		 13953};
13954
13955static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13956 int pipe)
13957{
13958 struct intel_plane *primary;
8e7d688b 13959 struct intel_plane_state *state;
465c120c 13960 const uint32_t *intel_primary_formats;
45e3743a 13961 unsigned int num_formats;
465c120c
MR		 13962
13963 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13964 if (primary == NULL)
13965 return NULL;
13966
8e7d688b
MR		 13967 state = intel_create_plane_state(&primary->base);
13968 if (!state) {
ea2c67bb
MR		 13969 kfree(primary);
13970 return NULL;
13971 }
8e7d688b 13972 primary->base.state = &state->base;
ea2c67bb 13973
465c120c
MR		 13974 primary->can_scale = false;
13975 primary->max_downscale = 1;
6156a456
CK		 13976 if (INTEL_INFO(dev)->gen >= 9) {
13977 primary->can_scale = true;
af99ceda 13978 state->scaler_id = -1;
6156a456 13979 }
465c120c
MR		 13980 primary->pipe = pipe;
13981 primary->plane = pipe;
a9ff8714 13982 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
c59cb179 13983 primary->check_plane = intel_check_primary_plane;
465c120c
MR		 13984 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13985 primary->plane = !pipe;
13986
6c0fd451
DL		 13987 if (INTEL_INFO(dev)->gen >= 9) {
13988 intel_primary_formats = skl_primary_formats;
13989 num_formats = ARRAY_SIZE(skl_primary_formats);
a8d201af
ML		 13990
13991 primary->update_plane = skylake_update_primary_plane;
13992 primary->disable_plane = skylake_disable_primary_plane;
13993 } else if (HAS_PCH_SPLIT(dev)) {
13994 intel_primary_formats = i965_primary_formats;
13995 num_formats = ARRAY_SIZE(i965_primary_formats);
13996
13997 primary->update_plane = ironlake_update_primary_plane;
13998 primary->disable_plane = i9xx_disable_primary_plane;
6c0fd451 13999 } else if (INTEL_INFO(dev)->gen >= 4) {
568db4f2
DL		 14000 intel_primary_formats = i965_primary_formats;
14001 num_formats = ARRAY_SIZE(i965_primary_formats);
a8d201af
ML		 14002
14003 primary->update_plane = i9xx_update_primary_plane;
14004 primary->disable_plane = i9xx_disable_primary_plane;
6c0fd451
DL		 14005 } else {
14006 intel_primary_formats = i8xx_primary_formats;
14007 num_formats = ARRAY_SIZE(i8xx_primary_formats);
a8d201af
ML		 14008
14009 primary->update_plane = i9xx_update_primary_plane;
14010 primary->disable_plane = i9xx_disable_primary_plane;
465c120c
MR		 14011 }
14012
14013 drm_universal_plane_init(dev, &primary->base, 0,
65a3fea0 14014 &intel_plane_funcs,
465c120c 14015 intel_primary_formats, num_formats,
b0b3b795 14016 DRM_PLANE_TYPE_PRIMARY, NULL);
48404c1e 14017
3b7a5119
SJ		 14018 if (INTEL_INFO(dev)->gen >= 4)
14019 intel_create_rotation_property(dev, primary);
48404c1e 14020
ea2c67bb
MR		 14021 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
14022
465c120c
MR		 14023 return &primary->base;
14024}
14025
3b7a5119
SJ		 14026void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
14027{
14028 if (!dev->mode_config.rotation_property) {
14029 unsigned long flags = BIT(DRM_ROTATE_0) |
14030 BIT(DRM_ROTATE_180);
14031
14032 if (INTEL_INFO(dev)->gen >= 9)
14033 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
14034
14035 dev->mode_config.rotation_property =
14036 drm_mode_create_rotation_property(dev, flags);
14037 }
14038 if (dev->mode_config.rotation_property)
14039 drm_object_attach_property(&plane->base.base,
14040 dev->mode_config.rotation_property,
14041 plane->base.state->rotation);
14042}
14043
3d7d6510 14044static int
852e787c 14045intel_check_cursor_plane(struct drm_plane *plane,
061e4b8d 14046 struct intel_crtc_state *crtc_state,
852e787c 14047 struct intel_plane_state *state)
3d7d6510 14048{
061e4b8d 14049 struct drm_crtc *crtc = crtc_state->base.crtc;
2b875c22 14050 struct drm_framebuffer *fb = state->base.fb;
757f9a3e 14051 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
b29ec92c 14052 enum pipe pipe = to_intel_plane(plane)->pipe;
757f9a3e
GP		 14053 unsigned stride;
14054 int ret;
3d7d6510 14055
061e4b8d
ML		 14056 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
14057 &state->dst, &state->clip,
3d7d6510
MR		 14058 DRM_PLANE_HELPER_NO_SCALING,
14059 DRM_PLANE_HELPER_NO_SCALING,
852e787c 14060 true, true, &state->visible);
757f9a3e
GP		 14061 if (ret)
14062 return ret;
14063
757f9a3e
GP		 14064 /* if we want to turn off the cursor ignore width and height */
14065 if (!obj)
da20eabd 14066 return 0;
757f9a3e 14067
757f9a3e 14068 /* Check for which cursor types we support */
061e4b8d 14069 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
ea2c67bb
MR		 14070 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
14071 state->base.crtc_w, state->base.crtc_h);
757f9a3e
GP		 14072 return -EINVAL;
14073 }
14074
ea2c67bb
MR		 14075 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
14076 if (obj->base.size < stride * state->base.crtc_h) {
757f9a3e
GP		 14077 DRM_DEBUG_KMS("buffer is too small\n");
14078 return -ENOMEM;
14079 }
14080
3a656b54 14081 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
757f9a3e 14082 DRM_DEBUG_KMS("cursor cannot be tiled\n");
da20eabd 14083 return -EINVAL;
32b7eeec
MR		 14084 }
14085
b29ec92c
VS		 14086 /*
14087 * There's something wrong with the cursor on CHV pipe C.
14088 * If it straddles the left edge of the screen then
14089 * moving it away from the edge or disabling it often
14090 * results in a pipe underrun, and often that can lead to
14091 * dead pipe (constant underrun reported, and it scans
14092 * out just a solid color). To recover from that, the
14093 * display power well must be turned off and on again.
14094 * Refuse the put the cursor into that compromised position.
14095 */
14096 if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
14097 state->visible && state->base.crtc_x < 0) {
14098 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
14099 return -EINVAL;
14100 }
14101
da20eabd 14102 return 0;
852e787c 14103}
3d7d6510 14104
a8ad0d8e
ML		 14105static void
14106intel_disable_cursor_plane(struct drm_plane *plane,
7fabf5ef 14107 struct drm_crtc *crtc)
a8ad0d8e 14108{
f2858021
ML		 14109 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14110
14111 intel_crtc->cursor_addr = 0;
55a08b3f 14112 intel_crtc_update_cursor(crtc, NULL);
a8ad0d8e
ML		 14113}
14114
f4a2cf29 14115static void
55a08b3f
ML		 14116intel_update_cursor_plane(struct drm_plane *plane,
14117 const struct intel_crtc_state *crtc_state,
14118 const struct intel_plane_state *state)
852e787c 14119{
55a08b3f
ML		 14120 struct drm_crtc *crtc = crtc_state->base.crtc;
14121 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ea2c67bb 14122 struct drm_device *dev = plane->dev;
2b875c22 14123 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
a912f12f 14124 uint32_t addr;
852e787c 14125
f4a2cf29 14126 if (!obj)
a912f12f 14127 addr = 0;
f4a2cf29 14128 else if (!INTEL_INFO(dev)->cursor_needs_physical)
a912f12f 14129 addr = i915_gem_obj_ggtt_offset(obj);
f4a2cf29 14130 else
a912f12f 14131 addr = obj->phys_handle->busaddr;
852e787c 14132
a912f12f 14133 intel_crtc->cursor_addr = addr;
55a08b3f 14134 intel_crtc_update_cursor(crtc, state);
852e787c
GP		 14135}
14136
3d7d6510
MR		 14137static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14138 int pipe)
14139{
14140 struct intel_plane *cursor;
8e7d688b 14141 struct intel_plane_state *state;
3d7d6510
MR		 14142
14143 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14144 if (cursor == NULL)
14145 return NULL;
14146
8e7d688b
MR		 14147 state = intel_create_plane_state(&cursor->base);
14148 if (!state) {
ea2c67bb
MR		 14149 kfree(cursor);
14150 return NULL;
14151 }
8e7d688b 14152 cursor->base.state = &state->base;
ea2c67bb 14153
3d7d6510
MR		 14154 cursor->can_scale = false;
14155 cursor->max_downscale = 1;
14156 cursor->pipe = pipe;
14157 cursor->plane = pipe;
a9ff8714 14158 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
c59cb179 14159 cursor->check_plane = intel_check_cursor_plane;
55a08b3f 14160 cursor->update_plane = intel_update_cursor_plane;
a8ad0d8e 14161 cursor->disable_plane = intel_disable_cursor_plane;
3d7d6510
MR		 14162
14163 drm_universal_plane_init(dev, &cursor->base, 0,
65a3fea0 14164 &intel_plane_funcs,
3d7d6510
MR		 14165 intel_cursor_formats,
14166 ARRAY_SIZE(intel_cursor_formats),
b0b3b795 14167 DRM_PLANE_TYPE_CURSOR, NULL);
4398ad45
VS		 14168
14169 if (INTEL_INFO(dev)->gen >= 4) {
14170 if (!dev->mode_config.rotation_property)
14171 dev->mode_config.rotation_property =
14172 drm_mode_create_rotation_property(dev,
14173 BIT(DRM_ROTATE_0) |
14174 BIT(DRM_ROTATE_180));
14175 if (dev->mode_config.rotation_property)
14176 drm_object_attach_property(&cursor->base.base,
14177 dev->mode_config.rotation_property,
8e7d688b 14178 state->base.rotation);
4398ad45
VS		 14179 }
14180
af99ceda
CK		 14181 if (INTEL_INFO(dev)->gen >=9)
14182 state->scaler_id = -1;
14183
ea2c67bb
MR		 14184 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14185
3d7d6510
MR		 14186 return &cursor->base;
14187}
14188
549e2bfb
CK		 14189static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14190 struct intel_crtc_state *crtc_state)
14191{
14192 int i;
14193 struct intel_scaler *intel_scaler;
14194 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14195
14196 for (i = 0; i < intel_crtc->num_scalers; i++) {
14197 intel_scaler = &scaler_state->scalers[i];
14198 intel_scaler->in_use = 0;
549e2bfb
CK		 14199 intel_scaler->mode = PS_SCALER_MODE_DYN;
14200 }
14201
14202 scaler_state->scaler_id = -1;
14203}
14204
b358d0a6 14205static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 14206{
fbee40df 14207 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 14208 struct intel_crtc *intel_crtc;
f5de6e07 14209 struct intel_crtc_state *crtc_state = NULL;
3d7d6510
MR		 14210 struct drm_plane *primary = NULL;
14211 struct drm_plane *cursor = NULL;
8563b1e8 14212 int ret;
79e53945 14213
955382f3 14214 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB		 14215 if (intel_crtc == NULL)
14216 return;
14217
f5de6e07
ACO		 14218 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14219 if (!crtc_state)
14220 goto fail;
550acefd
ACO		 14221 intel_crtc->config = crtc_state;
14222 intel_crtc->base.state = &crtc_state->base;
07878248 14223 crtc_state->base.crtc = &intel_crtc->base;
f5de6e07 14224
549e2bfb
CK		 14225 /* initialize shared scalers */
14226 if (INTEL_INFO(dev)->gen >= 9) {
14227 if (pipe == PIPE_C)
14228 intel_crtc->num_scalers = 1;
14229 else
14230 intel_crtc->num_scalers = SKL_NUM_SCALERS;
14231
14232 skl_init_scalers(dev, intel_crtc, crtc_state);
14233 }
14234
465c120c 14235 primary = intel_primary_plane_create(dev, pipe);
3d7d6510
MR		 14236 if (!primary)
14237 goto fail;
14238
14239 cursor = intel_cursor_plane_create(dev, pipe);
14240 if (!cursor)
14241 goto fail;
14242
465c120c 14243 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
f9882876 14244 cursor, &intel_crtc_funcs, NULL);
3d7d6510
MR		 14245 if (ret)
14246 goto fail;
79e53945 14247
1f1c2e24
VS		 14248 /*
14249 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
8c0f92e1 14250 * is hooked to pipe B. Hence we want plane A feeding pipe B.
1f1c2e24 14251 */
80824003
JB		 14252 intel_crtc->pipe = pipe;
14253 intel_crtc->plane = pipe;
3a77c4c4 14254 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
28c97730 14255 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 14256 intel_crtc->plane = !pipe;
80824003
JB		 14257 }
14258
4b0e333e
CW		 14259 intel_crtc->cursor_base = ~0;
14260 intel_crtc->cursor_cntl = ~0;
dc41c154 14261 intel_crtc->cursor_size = ~0;
8d7849db 14262
852eb00d
VS		 14263 intel_crtc->wm.cxsr_allowed = true;
14264
22fd0fab
JB		 14265 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14266 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14267 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14268 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14269
79e53945 14270 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
87b6b101 14271
8563b1e8
LL		 14272 intel_color_init(&intel_crtc->base);
14273
87b6b101 14274 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
3d7d6510
MR		 14275 return;
14276
14277fail:
14278 if (primary)
14279 drm_plane_cleanup(primary);
14280 if (cursor)
14281 drm_plane_cleanup(cursor);
f5de6e07 14282 kfree(crtc_state);
3d7d6510 14283 kfree(intel_crtc);
79e53945
JB		 14284}
14285
752aa88a
JB		 14286enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14287{
14288 struct drm_encoder *encoder = connector->base.encoder;
6e9f798d 14289 struct drm_device *dev = connector->base.dev;
752aa88a 14290
51fd371b 14291 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
752aa88a 14292
d3babd3f 14293 if (!encoder || WARN_ON(!encoder->crtc))
752aa88a
JB		 14294 return INVALID_PIPE;
14295
14296 return to_intel_crtc(encoder->crtc)->pipe;
14297}
14298
08d7b3d1 14299int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 14300 struct drm_file *file)
08d7b3d1 14301{
08d7b3d1 14302 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7707e653 14303 struct drm_crtc *drmmode_crtc;
c05422d5 14304 struct intel_crtc *crtc;
08d7b3d1 14305
7707e653 14306 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
08d7b3d1 14307
7707e653 14308 if (!drmmode_crtc) {
08d7b3d1 14309 DRM_ERROR("no such CRTC id\n");
3f2c2057 14310 return -ENOENT;
08d7b3d1
CW		 14311 }
14312
7707e653 14313 crtc = to_intel_crtc(drmmode_crtc);
c05422d5 14314 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 14315
c05422d5 14316 return 0;
08d7b3d1
CW		 14317}
14318
66a9278e 14319static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 14320{
66a9278e
DV		 14321 struct drm_device *dev = encoder->base.dev;
14322 struct intel_encoder *source_encoder;
79e53945 14323 int index_mask = 0;
79e53945
JB		 14324 int entry = 0;
14325
b2784e15 14326 for_each_intel_encoder(dev, source_encoder) {
bc079e8b 14327 if (encoders_cloneable(encoder, source_encoder))
66a9278e
DV		 14328 index_mask |= (1 << entry);
14329
79e53945
JB		 14330 entry++;
14331 }
4ef69c7a 14332
79e53945
JB		 14333 return index_mask;
14334}
14335
4d302442
CW		 14336static bool has_edp_a(struct drm_device *dev)
14337{
14338 struct drm_i915_private *dev_priv = dev->dev_private;
14339
14340 if (!IS_MOBILE(dev))
14341 return false;
14342
14343 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14344 return false;
14345
e3589908 14346 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
4d302442
CW		 14347 return false;
14348
14349 return true;
14350}
14351
84b4e042
JB		 14352static bool intel_crt_present(struct drm_device *dev)
14353{
14354 struct drm_i915_private *dev_priv = dev->dev_private;
14355
884497ed
DL		 14356 if (INTEL_INFO(dev)->gen >= 9)
14357 return false;
14358
cf404ce4 14359 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
84b4e042
JB		 14360 return false;
14361
14362 if (IS_CHERRYVIEW(dev))
14363 return false;
14364
65e472e4
VS		 14365 if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
14366 return false;
14367
70ac54d0
VS		 14368 /* DDI E can't be used if DDI A requires 4 lanes */
14369 if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
14370 return false;
14371
e4abb733 14372 if (!dev_priv->vbt.int_crt_support)
84b4e042
JB		 14373 return false;
14374
14375 return true;
14376}
14377
79e53945
JB		 14378static void intel_setup_outputs(struct drm_device *dev)
14379{
725e30ad 14380 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 14381 struct intel_encoder *encoder;
cb0953d7 14382 bool dpd_is_edp = false;
79e53945 14383
c9093354 14384 intel_lvds_init(dev);
79e53945 14385
84b4e042 14386 if (intel_crt_present(dev))
79935fca 14387 intel_crt_init(dev);
cb0953d7 14388
c776eb2e
VK		 14389 if (IS_BROXTON(dev)) {
14390 /*
14391 * FIXME: Broxton doesn't support port detection via the
14392 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14393 * detect the ports.
14394 */
14395 intel_ddi_init(dev, PORT_A);
14396 intel_ddi_init(dev, PORT_B);
14397 intel_ddi_init(dev, PORT_C);
c6c794a2
SS		 14398
14399 intel_dsi_init(dev);
c776eb2e 14400 } else if (HAS_DDI(dev)) {
0e72a5b5
ED		 14401 int found;
14402
de31facd
JB		 14403 /*
14404 * Haswell uses DDI functions to detect digital outputs.
14405 * On SKL pre-D0 the strap isn't connected, so we assume
14406 * it's there.
14407 */
77179400 14408 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
de31facd 14409 /* WaIgnoreDDIAStrap: skl */
ef11bdb3 14410 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
0e72a5b5
ED		 14411 intel_ddi_init(dev, PORT_A);
14412
14413 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14414 * register */
14415 found = I915_READ(SFUSE_STRAP);
14416
14417 if (found & SFUSE_STRAP_DDIB_DETECTED)
14418 intel_ddi_init(dev, PORT_B);
14419 if (found & SFUSE_STRAP_DDIC_DETECTED)
14420 intel_ddi_init(dev, PORT_C);
14421 if (found & SFUSE_STRAP_DDID_DETECTED)
14422 intel_ddi_init(dev, PORT_D);
2800e4c2
RV		 14423 /*
14424 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14425 */
ef11bdb3 14426 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
2800e4c2
RV		 14427 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14428 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14429 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14430 intel_ddi_init(dev, PORT_E);
14431
0e72a5b5 14432 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 14433 int found;
5d8a7752 14434 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
270b3042
DV		 14435
14436 if (has_edp_a(dev))
14437 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 14438
dc0fa718 14439 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 14440 /* PCH SDVOB multiplex with HDMIB */
2a5c0832 14441 found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
30ad48b7 14442 if (!found)
e2debe91 14443 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 14444 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 14445 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 14446 }
14447
dc0fa718 14448 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 14449 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 14450
dc0fa718 14451 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 14452 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 14453
5eb08b69 14454 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 14455 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 14456
270b3042 14457 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 14458 intel_dp_init(dev, PCH_DP_D, PORT_D);
666a4537 14459 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
e17ac6db
VS		 14460 /*
14461 * The DP_DETECTED bit is the latched state of the DDC
14462 * SDA pin at boot. However since eDP doesn't require DDC
14463 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14464 * eDP ports may have been muxed to an alternate function.
14465 * Thus we can't rely on the DP_DETECTED bit alone to detect
14466 * eDP ports. Consult the VBT as well as DP_DETECTED to
14467 * detect eDP ports.
14468 */
e66eb81d 14469 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
d2182a66 14470 !intel_dp_is_edp(dev, PORT_B))
e66eb81d
VS		 14471 intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14472 if (I915_READ(VLV_DP_B) & DP_DETECTED ||
e17ac6db 14473 intel_dp_is_edp(dev, PORT_B))
e66eb81d 14474 intel_dp_init(dev, VLV_DP_B, PORT_B);
585a94b8 14475
e66eb81d 14476 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
d2182a66 14477 !intel_dp_is_edp(dev, PORT_C))
e66eb81d
VS		 14478 intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14479 if (I915_READ(VLV_DP_C) & DP_DETECTED ||
e17ac6db 14480 intel_dp_is_edp(dev, PORT_C))
e66eb81d 14481 intel_dp_init(dev, VLV_DP_C, PORT_C);
19c03924 14482
9418c1f1 14483 if (IS_CHERRYVIEW(dev)) {
e17ac6db 14484 /* eDP not supported on port D, so don't check VBT */
e66eb81d
VS		 14485 if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
14486 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14487 if (I915_READ(CHV_DP_D) & DP_DETECTED)
14488 intel_dp_init(dev, CHV_DP_D, PORT_D);
9418c1f1
VS		 14489 }
14490
3cfca973 14491 intel_dsi_init(dev);
09da55dc 14492 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
27185ae1 14493 bool found = false;
7d57382e 14494
e2debe91 14495 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14496 DRM_DEBUG_KMS("probing SDVOB\n");
2a5c0832 14497 found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
3fec3d2f 14498 if (!found && IS_G4X(dev)) {
b01f2c3a 14499 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 14500 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 14501 }
27185ae1 14502
3fec3d2f 14503 if (!found && IS_G4X(dev))
ab9d7c30 14504 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 14505 }
13520b05
KH		 14506
14507 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 14508
e2debe91 14509 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14510 DRM_DEBUG_KMS("probing SDVOC\n");
2a5c0832 14511 found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
b01f2c3a 14512 }
27185ae1 14513
e2debe91 14514 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 14515
3fec3d2f 14516 if (IS_G4X(dev)) {
b01f2c3a 14517 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 14518 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 14519 }
3fec3d2f 14520 if (IS_G4X(dev))
ab9d7c30 14521 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 14522 }
27185ae1 14523
3fec3d2f 14524 if (IS_G4X(dev) &&
e7281eab 14525 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 14526 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 14527 } else if (IS_GEN2(dev))
79e53945
JB		 14528 intel_dvo_init(dev);
14529
103a196f 14530 if (SUPPORTS_TV(dev))
79e53945
JB		 14531 intel_tv_init(dev);
14532
0bc12bcb 14533 intel_psr_init(dev);
7c8f8a70 14534
b2784e15 14535 for_each_intel_encoder(dev, encoder) {
4ef69c7a
CW		 14536 encoder->base.possible_crtcs = encoder->crtc_mask;
14537 encoder->base.possible_clones =
66a9278e 14538 intel_encoder_clones(encoder);
79e53945 14539 }
47356eb6 14540
dde86e2d 14541 intel_init_pch_refclk(dev);
270b3042
DV		 14542
14543 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 14544}
14545
14546static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14547{
60a5ca01 14548 struct drm_device *dev = fb->dev;
79e53945 14549 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 14550
ef2d633e 14551 drm_framebuffer_cleanup(fb);
60a5ca01 14552 mutex_lock(&dev->struct_mutex);
ef2d633e 14553 WARN_ON(!intel_fb->obj->framebuffer_references--);
60a5ca01
VS		 14554 drm_gem_object_unreference(&intel_fb->obj->base);
14555 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 14556 kfree(intel_fb);
14557}
14558
14559static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 14560 struct drm_file *file,
79e53945
JB		 14561 unsigned int *handle)
14562{
14563 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 14564 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 14565
cc917ab4
CW		 14566 if (obj->userptr.mm) {
14567 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14568 return -EINVAL;
14569 }
14570
05394f39 14571 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 14572}
14573
86c98588
RV		 14574static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14575 struct drm_file *file,
14576 unsigned flags, unsigned color,
14577 struct drm_clip_rect *clips,
14578 unsigned num_clips)
14579{
14580 struct drm_device *dev = fb->dev;
14581 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14582 struct drm_i915_gem_object *obj = intel_fb->obj;
14583
14584 mutex_lock(&dev->struct_mutex);
74b4ea1e 14585 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
86c98588
RV		 14586 mutex_unlock(&dev->struct_mutex);
14587
14588 return 0;
14589}
14590
79e53945
JB		 14591static const struct drm_framebuffer_funcs intel_fb_funcs = {
14592 .destroy = intel_user_framebuffer_destroy,
14593 .create_handle = intel_user_framebuffer_create_handle,
86c98588 14594 .dirty = intel_user_framebuffer_dirty,
79e53945
JB		 14595};
14596
b321803d
DL		 14597static
14598u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14599 uint32_t pixel_format)
14600{
14601 u32 gen = INTEL_INFO(dev)->gen;
14602
14603 if (gen >= 9) {
ac484963
VS		 14604 int cpp = drm_format_plane_cpp(pixel_format, 0);
14605
b321803d
DL		 14606 /* "The stride in bytes must not exceed the of the size of 8K
14607 * pixels and 32K bytes."
14608 */
ac484963 14609 return min(8192 * cpp, 32768);
666a4537 14610 } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
b321803d
DL		 14611 return 32*1024;
14612 } else if (gen >= 4) {
14613 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14614 return 16*1024;
14615 else
14616 return 32*1024;
14617 } else if (gen >= 3) {
14618 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14619 return 8*1024;
14620 else
14621 return 16*1024;
14622 } else {
14623 /* XXX DSPC is limited to 4k tiled */
14624 return 8*1024;
14625 }
14626}
14627
b5ea642a
DV		 14628static int intel_framebuffer_init(struct drm_device *dev,
14629 struct intel_framebuffer *intel_fb,
14630 struct drm_mode_fb_cmd2 *mode_cmd,
14631 struct drm_i915_gem_object *obj)
79e53945 14632{
7b49f948 14633 struct drm_i915_private *dev_priv = to_i915(dev);
6761dd31 14634 unsigned int aligned_height;
79e53945 14635 int ret;
b321803d 14636 u32 pitch_limit, stride_alignment;
79e53945 14637
dd4916c5
DV		 14638 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14639
2a80eada
DV		 14640 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14641 /* Enforce that fb modifier and tiling mode match, but only for
14642 * X-tiled. This is needed for FBC. */
14643 if (!!(obj->tiling_mode == I915_TILING_X) !=
14644 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14645 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14646 return -EINVAL;
14647 }
14648 } else {
14649 if (obj->tiling_mode == I915_TILING_X)
14650 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14651 else if (obj->tiling_mode == I915_TILING_Y) {
14652 DRM_DEBUG("No Y tiling for legacy addfb\n");
14653 return -EINVAL;
14654 }
14655 }
14656
9a8f0a12
TU		 14657 /* Passed in modifier sanity checking. */
14658 switch (mode_cmd->modifier[0]) {
14659 case I915_FORMAT_MOD_Y_TILED:
14660 case I915_FORMAT_MOD_Yf_TILED:
14661 if (INTEL_INFO(dev)->gen < 9) {
14662 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14663 mode_cmd->modifier[0]);
14664 return -EINVAL;
14665 }
14666 case DRM_FORMAT_MOD_NONE:
14667 case I915_FORMAT_MOD_X_TILED:
14668 break;
14669 default:
c0f40428
JB		 14670 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14671 mode_cmd->modifier[0]);
57cd6508 14672 return -EINVAL;
c16ed4be 14673 }
57cd6508 14674
7b49f948
VS		 14675 stride_alignment = intel_fb_stride_alignment(dev_priv,
14676 mode_cmd->modifier[0],
b321803d
DL		 14677 mode_cmd->pixel_format);
14678 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14679 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14680 mode_cmd->pitches[0], stride_alignment);
57cd6508 14681 return -EINVAL;
c16ed4be 14682 }
57cd6508 14683
b321803d
DL		 14684 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14685 mode_cmd->pixel_format);
a35cdaa0 14686 if (mode_cmd->pitches[0] > pitch_limit) {
b321803d
DL		 14687 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14688 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
2a80eada 14689 "tiled" : "linear",
a35cdaa0 14690 mode_cmd->pitches[0], pitch_limit);
5d7bd705 14691 return -EINVAL;
c16ed4be 14692 }
5d7bd705 14693
2a80eada 14694 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
c16ed4be
CW		 14695 mode_cmd->pitches[0] != obj->stride) {
14696 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14697 mode_cmd->pitches[0], obj->stride);
5d7bd705 14698 return -EINVAL;
c16ed4be 14699 }
5d7bd705 14700
57779d06 14701 /* Reject formats not supported by any plane early. */
308e5bcb 14702 switch (mode_cmd->pixel_format) {
57779d06 14703 case DRM_FORMAT_C8:
04b3924d
VS		 14704 case DRM_FORMAT_RGB565:
14705 case DRM_FORMAT_XRGB8888:
14706 case DRM_FORMAT_ARGB8888:
57779d06
VS		 14707 break;
14708 case DRM_FORMAT_XRGB1555:
c16ed4be 14709 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 14710 DRM_DEBUG("unsupported pixel format: %s\n",
14711 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14712 return -EINVAL;
c16ed4be 14713 }
57779d06 14714 break;
57779d06 14715 case DRM_FORMAT_ABGR8888:
666a4537
WB		 14716 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
14717 INTEL_INFO(dev)->gen < 9) {
6c0fd451
DL		 14718 DRM_DEBUG("unsupported pixel format: %s\n",
14719 drm_get_format_name(mode_cmd->pixel_format));
14720 return -EINVAL;
14721 }
14722 break;
14723 case DRM_FORMAT_XBGR8888:
04b3924d 14724 case DRM_FORMAT_XRGB2101010:
57779d06 14725 case DRM_FORMAT_XBGR2101010:
c16ed4be 14726 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 14727 DRM_DEBUG("unsupported pixel format: %s\n",
14728 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14729 return -EINVAL;
c16ed4be 14730 }
b5626747 14731 break;
7531208b 14732 case DRM_FORMAT_ABGR2101010:
666a4537 14733 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
7531208b
DL		 14734 DRM_DEBUG("unsupported pixel format: %s\n",
14735 drm_get_format_name(mode_cmd->pixel_format));
14736 return -EINVAL;
14737 }
14738 break;
04b3924d
VS		 14739 case DRM_FORMAT_YUYV:
14740 case DRM_FORMAT_UYVY:
14741 case DRM_FORMAT_YVYU:
14742 case DRM_FORMAT_VYUY:
c16ed4be 14743 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 14744 DRM_DEBUG("unsupported pixel format: %s\n",
14745 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14746 return -EINVAL;
c16ed4be 14747 }
57cd6508
CW		 14748 break;
14749 default:
4ee62c76
VS		 14750 DRM_DEBUG("unsupported pixel format: %s\n",
14751 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 14752 return -EINVAL;
14753 }
14754
90f9a336
VS		 14755 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14756 if (mode_cmd->offsets[0] != 0)
14757 return -EINVAL;
14758
ec2c981e 14759 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
091df6cb
DV		 14760 mode_cmd->pixel_format,
14761 mode_cmd->modifier[0]);
53155c0a
DV		 14762 /* FIXME drm helper for size checks (especially planar formats)? */
14763 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14764 return -EINVAL;
14765
c7d73f6a
DV		 14766 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14767 intel_fb->obj = obj;
14768
2d7a215f
VS		 14769 intel_fill_fb_info(dev_priv, &intel_fb->base);
14770
79e53945
JB		 14771 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14772 if (ret) {
14773 DRM_ERROR("framebuffer init failed %d\n", ret);
14774 return ret;
14775 }
14776
0b05e1e0
VS		 14777 intel_fb->obj->framebuffer_references++;
14778
79e53945
JB		 14779 return 0;
14780}
14781
79e53945
JB		 14782static struct drm_framebuffer *
14783intel_user_framebuffer_create(struct drm_device *dev,
14784 struct drm_file *filp,
1eb83451 14785 const struct drm_mode_fb_cmd2 *user_mode_cmd)
79e53945 14786{
dcb1394e 14787 struct drm_framebuffer *fb;
05394f39 14788 struct drm_i915_gem_object *obj;
76dc3769 14789 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
79e53945 14790
308e5bcb 14791 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
76dc3769 14792 mode_cmd.handles[0]));
c8725226 14793 if (&obj->base == NULL)
cce13ff7 14794 return ERR_PTR(-ENOENT);
79e53945 14795
92907cbb 14796 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
dcb1394e
LW		 14797 if (IS_ERR(fb))
14798 drm_gem_object_unreference_unlocked(&obj->base);
14799
14800 return fb;
79e53945
JB		 14801}
14802
0695726e 14803#ifndef CONFIG_DRM_FBDEV_EMULATION
0632fef6 14804static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
4520f53a
DV		 14805{
14806}
14807#endif
14808
79e53945 14809static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 14810 .fb_create = intel_user_framebuffer_create,
0632fef6 14811 .output_poll_changed = intel_fbdev_output_poll_changed,
5ee67f1c
MR		 14812 .atomic_check = intel_atomic_check,
14813 .atomic_commit = intel_atomic_commit,
de419ab6
ML		 14814 .atomic_state_alloc = intel_atomic_state_alloc,
14815 .atomic_state_clear = intel_atomic_state_clear,
79e53945
JB		 14816};
14817
88212941
ID		 14818/**
14819 * intel_init_display_hooks - initialize the display modesetting hooks
14820 * @dev_priv: device private
14821 */
14822void intel_init_display_hooks(struct drm_i915_private *dev_priv)
e70236a8 14823{
88212941 14824 if (INTEL_INFO(dev_priv)->gen >= 9) {
bc8d7dff 14825 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14826 dev_priv->display.get_initial_plane_config =
14827 skylake_get_initial_plane_config;
bc8d7dff
DL		 14828 dev_priv->display.crtc_compute_clock =
14829 haswell_crtc_compute_clock;
14830 dev_priv->display.crtc_enable = haswell_crtc_enable;
14831 dev_priv->display.crtc_disable = haswell_crtc_disable;
88212941 14832 } else if (HAS_DDI(dev_priv)) {
0e8ffe1b 14833 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14834 dev_priv->display.get_initial_plane_config =
14835 ironlake_get_initial_plane_config;
797d0259
ACO		 14836 dev_priv->display.crtc_compute_clock =
14837 haswell_crtc_compute_clock;
4f771f10
PZ		 14838 dev_priv->display.crtc_enable = haswell_crtc_enable;
14839 dev_priv->display.crtc_disable = haswell_crtc_disable;
88212941 14840 } else if (HAS_PCH_SPLIT(dev_priv)) {
0e8ffe1b 14841 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
5724dbd1
DL		 14842 dev_priv->display.get_initial_plane_config =
14843 ironlake_get_initial_plane_config;
3fb37703
ACO		 14844 dev_priv->display.crtc_compute_clock =
14845 ironlake_crtc_compute_clock;
76e5a89c
DV		 14846 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14847 dev_priv->display.crtc_disable = ironlake_crtc_disable;
65b3d6a9 14848 } else if (IS_CHERRYVIEW(dev_priv)) {
89b667f8 14849 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14850 dev_priv->display.get_initial_plane_config =
14851 i9xx_get_initial_plane_config;
65b3d6a9
ACO		 14852 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
14853 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14854 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14855 } else if (IS_VALLEYVIEW(dev_priv)) {
14856 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14857 dev_priv->display.get_initial_plane_config =
14858 i9xx_get_initial_plane_config;
14859 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
89b667f8
JB		 14860 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14861 dev_priv->display.crtc_disable = i9xx_crtc_disable;
19ec6693
ACO		 14862 } else if (IS_G4X(dev_priv)) {
14863 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14864 dev_priv->display.get_initial_plane_config =
14865 i9xx_get_initial_plane_config;
14866 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
14867 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14868 dev_priv->display.crtc_disable = i9xx_crtc_disable;
70e8aa21
ACO		 14869 } else if (IS_PINEVIEW(dev_priv)) {
14870 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14871 dev_priv->display.get_initial_plane_config =
14872 i9xx_get_initial_plane_config;
14873 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
14874 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14875 dev_priv->display.crtc_disable = i9xx_crtc_disable;
81c97f52 14876 } else if (!IS_GEN2(dev_priv)) {
0e8ffe1b 14877 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14878 dev_priv->display.get_initial_plane_config =
14879 i9xx_get_initial_plane_config;
d6dfee7a 14880 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
76e5a89c
DV		 14881 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14882 dev_priv->display.crtc_disable = i9xx_crtc_disable;
81c97f52
ACO		 14883 } else {
14884 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14885 dev_priv->display.get_initial_plane_config =
14886 i9xx_get_initial_plane_config;
14887 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
14888 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14889 dev_priv->display.crtc_disable = i9xx_crtc_disable;
f564048e 14890 }
e70236a8 14891
e70236a8 14892 /* Returns the core display clock speed */
88212941 14893 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
1652d19e
VS		 14894 dev_priv->display.get_display_clock_speed =
14895 skylake_get_display_clock_speed;
88212941 14896 else if (IS_BROXTON(dev_priv))
acd3f3d3
BP		 14897 dev_priv->display.get_display_clock_speed =
14898 broxton_get_display_clock_speed;
88212941 14899 else if (IS_BROADWELL(dev_priv))
1652d19e
VS		 14900 dev_priv->display.get_display_clock_speed =
14901 broadwell_get_display_clock_speed;
88212941 14902 else if (IS_HASWELL(dev_priv))
1652d19e
VS		 14903 dev_priv->display.get_display_clock_speed =
14904 haswell_get_display_clock_speed;
88212941 14905 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
25eb05fc
JB		 14906 dev_priv->display.get_display_clock_speed =
14907 valleyview_get_display_clock_speed;
88212941 14908 else if (IS_GEN5(dev_priv))
b37a6434
VS		 14909 dev_priv->display.get_display_clock_speed =
14910 ilk_get_display_clock_speed;
88212941
ID		 14911 else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) ||
14912 IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
e70236a8
JB		 14913 dev_priv->display.get_display_clock_speed =
14914 i945_get_display_clock_speed;
88212941 14915 else if (IS_GM45(dev_priv))
34edce2f
VS		 14916 dev_priv->display.get_display_clock_speed =
14917 gm45_get_display_clock_speed;
88212941 14918 else if (IS_CRESTLINE(dev_priv))
34edce2f
VS		 14919 dev_priv->display.get_display_clock_speed =
14920 i965gm_get_display_clock_speed;
88212941 14921 else if (IS_PINEVIEW(dev_priv))
34edce2f
VS		 14922 dev_priv->display.get_display_clock_speed =
14923 pnv_get_display_clock_speed;
88212941 14924 else if (IS_G33(dev_priv) || IS_G4X(dev_priv))
34edce2f
VS		 14925 dev_priv->display.get_display_clock_speed =
14926 g33_get_display_clock_speed;
88212941 14927 else if (IS_I915G(dev_priv))
e70236a8
JB		 14928 dev_priv->display.get_display_clock_speed =
14929 i915_get_display_clock_speed;
88212941 14930 else if (IS_I945GM(dev_priv) || IS_845G(dev_priv))
e70236a8
JB		 14931 dev_priv->display.get_display_clock_speed =
14932 i9xx_misc_get_display_clock_speed;
88212941 14933 else if (IS_I915GM(dev_priv))
e70236a8
JB		 14934 dev_priv->display.get_display_clock_speed =
14935 i915gm_get_display_clock_speed;
88212941 14936 else if (IS_I865G(dev_priv))
e70236a8
JB		 14937 dev_priv->display.get_display_clock_speed =
14938 i865_get_display_clock_speed;
88212941 14939 else if (IS_I85X(dev_priv))
e70236a8 14940 dev_priv->display.get_display_clock_speed =
1b1d2716 14941 i85x_get_display_clock_speed;
623e01e5 14942 else { /* 830 */
88212941 14943 WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n");
e70236a8
JB		 14944 dev_priv->display.get_display_clock_speed =
14945 i830_get_display_clock_speed;
623e01e5 14946 }
e70236a8 14947
88212941 14948 if (IS_GEN5(dev_priv)) {
3bb11b53 14949 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
88212941 14950 } else if (IS_GEN6(dev_priv)) {
3bb11b53 14951 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
88212941 14952 } else if (IS_IVYBRIDGE(dev_priv)) {
3bb11b53
SJ		 14953 /* FIXME: detect B0+ stepping and use auto training */
14954 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
88212941 14955 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3bb11b53 14956 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
88212941 14957 if (IS_BROADWELL(dev_priv)) {
27c329ed
ML		 14958 dev_priv->display.modeset_commit_cdclk =
14959 broadwell_modeset_commit_cdclk;
14960 dev_priv->display.modeset_calc_cdclk =
14961 broadwell_modeset_calc_cdclk;
14962 }
88212941 14963 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
27c329ed
ML		 14964 dev_priv->display.modeset_commit_cdclk =
14965 valleyview_modeset_commit_cdclk;
14966 dev_priv->display.modeset_calc_cdclk =
14967 valleyview_modeset_calc_cdclk;
88212941 14968 } else if (IS_BROXTON(dev_priv)) {
27c329ed
ML		 14969 dev_priv->display.modeset_commit_cdclk =
14970 broxton_modeset_commit_cdclk;
14971 dev_priv->display.modeset_calc_cdclk =
14972 broxton_modeset_calc_cdclk;
e70236a8 14973 }
8c9f3aaf 14974
88212941 14975 switch (INTEL_INFO(dev_priv)->gen) {
8c9f3aaf
JB		 14976 case 2:
14977 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14978 break;
14979
14980 case 3:
14981 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14982 break;
14983
14984 case 4:
14985 case 5:
14986 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14987 break;
14988
14989 case 6:
14990 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14991 break;
7c9017e5 14992 case 7:
4e0bbc31 14993 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
7c9017e5
JB		 14994 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14995 break;
830c81db 14996 case 9:
ba343e02
TU		 14997 /* Drop through - unsupported since execlist only. */
14998 default:
14999 /* Default just returns -ENODEV to indicate unsupported */
15000 dev_priv->display.queue_flip = intel_default_queue_flip;
8c9f3aaf 15001 }
e70236a8
JB		 15002}
15003
b690e96c
JB		 15004/*
15005 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
15006 * resume, or other times. This quirk makes sure that's the case for
15007 * affected systems.
15008 */
0206e353 15009static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 15010{
15011 struct drm_i915_private *dev_priv = dev->dev_private;
15012
15013 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 15014 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 15015}
15016
b6b5d049
VS		 15017static void quirk_pipeb_force(struct drm_device *dev)
15018{
15019 struct drm_i915_private *dev_priv = dev->dev_private;
15020
15021 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
15022 DRM_INFO("applying pipe b force quirk\n");
15023}
15024
435793df
KP		 15025/*
15026 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
15027 */
15028static void quirk_ssc_force_disable(struct drm_device *dev)
15029{
15030 struct drm_i915_private *dev_priv = dev->dev_private;
15031 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 15032 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 15033}
15034
4dca20ef 15035/*
5a15ab5b
CE		 15036 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
15037 * brightness value
4dca20ef
CE		 15038 */
15039static void quirk_invert_brightness(struct drm_device *dev)
15040{
15041 struct drm_i915_private *dev_priv = dev->dev_private;
15042 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 15043 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 15044}
15045
9c72cc6f
SD		 15046/* Some VBT's incorrectly indicate no backlight is present */
15047static void quirk_backlight_present(struct drm_device *dev)
15048{
15049 struct drm_i915_private *dev_priv = dev->dev_private;
15050 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
15051 DRM_INFO("applying backlight present quirk\n");
15052}
15053
b690e96c
JB		 15054struct intel_quirk {
15055 int device;
15056 int subsystem_vendor;
15057 int subsystem_device;
15058 void (*hook)(struct drm_device *dev);
15059};
15060
5f85f176
EE		 15061/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
15062struct intel_dmi_quirk {
15063 void (*hook)(struct drm_device *dev);
15064 const struct dmi_system_id (*dmi_id_list)[];
15065};
15066
15067static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
15068{
15069 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
15070 return 1;
15071}
15072
15073static const struct intel_dmi_quirk intel_dmi_quirks[] = {
15074 {
15075 .dmi_id_list = &(const struct dmi_system_id[]) {
15076 {
15077 .callback = intel_dmi_reverse_brightness,
15078 .ident = "NCR Corporation",
15079 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
15080 DMI_MATCH(DMI_PRODUCT_NAME, ""),
15081 },
15082 },
15083 { } /* terminating entry */
15084 },
15085 .hook = quirk_invert_brightness,
15086 },
15087};
15088
c43b5634 15089static struct intel_quirk intel_quirks[] = {
b690e96c
JB		 15090 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
15091 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
15092
b690e96c
JB		 15093 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
15094 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
15095
5f080c0f
VS		 15096 /* 830 needs to leave pipe A & dpll A up */
15097 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
15098
b6b5d049
VS		 15099 /* 830 needs to leave pipe B & dpll B up */
15100 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
15101
435793df
KP		 15102 /* Lenovo U160 cannot use SSC on LVDS */
15103 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 15104
15105 /* Sony Vaio Y cannot use SSC on LVDS */
15106 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 15107
be505f64
AH		 15108 /* Acer Aspire 5734Z must invert backlight brightness */
15109 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
15110
15111 /* Acer/eMachines G725 */
15112 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
15113
15114 /* Acer/eMachines e725 */
15115 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
15116
15117 /* Acer/Packard Bell NCL20 */
15118 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
15119
15120 /* Acer Aspire 4736Z */
15121 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
0f540c3a
JN		 15122
15123 /* Acer Aspire 5336 */
15124 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
2e93a1aa
SD		 15125
15126 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
15127 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
d4967d8c 15128
dfb3d47b
SD		 15129 /* Acer C720 Chromebook (Core i3 4005U) */
15130 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
15131
b2a9601c 15132 /* Apple Macbook 2,1 (Core 2 T7400) */
15133 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
15134
1b9448b0
JN		 15135 /* Apple Macbook 4,1 */
15136 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
15137
d4967d8c
SD		 15138 /* Toshiba CB35 Chromebook (Celeron 2955U) */
15139 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
724cb06f
SD		 15140
15141 /* HP Chromebook 14 (Celeron 2955U) */
15142 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
cf6f0af9
JN		 15143
15144 /* Dell Chromebook 11 */
15145 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
9be64eee
JN		 15146
15147 /* Dell Chromebook 11 (2015 version) */
15148 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
b690e96c
JB		 15149};
15150
15151static void intel_init_quirks(struct drm_device *dev)
15152{
15153 struct pci_dev *d = dev->pdev;
15154 int i;
15155
15156 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
15157 struct intel_quirk *q = &intel_quirks[i];
15158
15159 if (d->device == q->device &&
15160 (d->subsystem_vendor == q->subsystem_vendor ||
15161 q->subsystem_vendor == PCI_ANY_ID) &&
15162 (d->subsystem_device == q->subsystem_device ||
15163 q->subsystem_device == PCI_ANY_ID))
15164 q->hook(dev);
15165 }
5f85f176
EE		 15166 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
15167 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
15168 intel_dmi_quirks[i].hook(dev);
15169 }
b690e96c
JB		 15170}
15171
9cce37f4
JB		 15172/* Disable the VGA plane that we never use */
15173static void i915_disable_vga(struct drm_device *dev)
15174{
15175 struct drm_i915_private *dev_priv = dev->dev_private;
15176 u8 sr1;
f0f59a00 15177 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
9cce37f4 15178
2b37c616 15179 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
9cce37f4 15180 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 15181 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 15182 sr1 = inb(VGA_SR_DATA);
15183 outb(sr1 | 1<<5, VGA_SR_DATA);
15184 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
15185 udelay(300);
15186
01f5a626 15187 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9cce37f4
JB		 15188 POSTING_READ(vga_reg);
15189}
15190
f817586c
DV		 15191void intel_modeset_init_hw(struct drm_device *dev)
15192{
1a617b77
ML		 15193 struct drm_i915_private *dev_priv = dev->dev_private;
15194
b6283055 15195 intel_update_cdclk(dev);
1a617b77
ML		 15196
15197 dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
15198
f817586c 15199 intel_init_clock_gating(dev);
8090c6b9 15200 intel_enable_gt_powersave(dev);
f817586c
DV		 15201}
15202
d93c0372
MR		 15203/*
15204 * Calculate what we think the watermarks should be for the state we've read
15205 * out of the hardware and then immediately program those watermarks so that
15206 * we ensure the hardware settings match our internal state.
15207 *
15208 * We can calculate what we think WM's should be by creating a duplicate of the
15209 * current state (which was constructed during hardware readout) and running it
15210 * through the atomic check code to calculate new watermark values in the
15211 * state object.
15212 */
15213static void sanitize_watermarks(struct drm_device *dev)
15214{
15215 struct drm_i915_private *dev_priv = to_i915(dev);
15216 struct drm_atomic_state *state;
15217 struct drm_crtc *crtc;
15218 struct drm_crtc_state *cstate;
15219 struct drm_modeset_acquire_ctx ctx;
15220 int ret;
15221 int i;
15222
15223 /* Only supported on platforms that use atomic watermark design */
ed4a6a7c 15224 if (!dev_priv->display.optimize_watermarks)
d93c0372
MR		 15225 return;
15226
15227 /*
15228 * We need to hold connection_mutex before calling duplicate_state so
15229 * that the connector loop is protected.
15230 */
15231 drm_modeset_acquire_init(&ctx, 0);
15232retry:
0cd1262d 15233 ret = drm_modeset_lock_all_ctx(dev, &ctx);
d93c0372
MR		 15234 if (ret == -EDEADLK) {
15235 drm_modeset_backoff(&ctx);
15236 goto retry;
15237 } else if (WARN_ON(ret)) {
0cd1262d 15238 goto fail;
d93c0372
MR		 15239 }
15240
15241 state = drm_atomic_helper_duplicate_state(dev, &ctx);
15242 if (WARN_ON(IS_ERR(state)))
0cd1262d 15243 goto fail;
d93c0372 15244
ed4a6a7c
MR		 15245 /*
15246 * Hardware readout is the only time we don't want to calculate
15247 * intermediate watermarks (since we don't trust the current
15248 * watermarks).
15249 */
15250 to_intel_atomic_state(state)->skip_intermediate_wm = true;
15251
d93c0372
MR		 15252 ret = intel_atomic_check(dev, state);
15253 if (ret) {
15254 /*
15255 * If we fail here, it means that the hardware appears to be
15256 * programmed in a way that shouldn't be possible, given our
15257 * understanding of watermark requirements. This might mean a
15258 * mistake in the hardware readout code or a mistake in the
15259 * watermark calculations for a given platform. Raise a WARN
15260 * so that this is noticeable.
15261 *
15262 * If this actually happens, we'll have to just leave the
15263 * BIOS-programmed watermarks untouched and hope for the best.
15264 */
15265 WARN(true, "Could not determine valid watermarks for inherited state\n");
0cd1262d 15266 goto fail;
d93c0372
MR		 15267 }
15268
15269 /* Write calculated watermark values back */
15270 to_i915(dev)->wm.config = to_intel_atomic_state(state)->wm_config;
15271 for_each_crtc_in_state(state, crtc, cstate, i) {
15272 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
15273
ed4a6a7c
MR		 15274 cs->wm.need_postvbl_update = true;
15275 dev_priv->display.optimize_watermarks(cs);
d93c0372
MR		 15276 }
15277
15278 drm_atomic_state_free(state);
0cd1262d 15279fail:
d93c0372
MR		 15280 drm_modeset_drop_locks(&ctx);
15281 drm_modeset_acquire_fini(&ctx);
15282}
15283
79e53945
JB		 15284void intel_modeset_init(struct drm_device *dev)
15285{
72e96d64
JL		 15286 struct drm_i915_private *dev_priv = to_i915(dev);
15287 struct i915_ggtt *ggtt = &dev_priv->ggtt;
1fe47785 15288 int sprite, ret;
8cc87b75 15289 enum pipe pipe;
46f297fb 15290 struct intel_crtc *crtc;
79e53945
JB		 15291
15292 drm_mode_config_init(dev);
15293
15294 dev->mode_config.min_width = 0;
15295 dev->mode_config.min_height = 0;
15296
019d96cb
DA		 15297 dev->mode_config.preferred_depth = 24;
15298 dev->mode_config.prefer_shadow = 1;
15299
25bab385
TU		 15300 dev->mode_config.allow_fb_modifiers = true;
15301
e6ecefaa 15302 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 15303
b690e96c
JB		 15304 intel_init_quirks(dev);
15305
1fa61106
ED		 15306 intel_init_pm(dev);
15307
e3c74757
BW		 15308 if (INTEL_INFO(dev)->num_pipes == 0)
15309 return;
15310
69f92f67
LW		 15311 /*
15312 * There may be no VBT; and if the BIOS enabled SSC we can
15313 * just keep using it to avoid unnecessary flicker. Whereas if the
15314 * BIOS isn't using it, don't assume it will work even if the VBT
15315 * indicates as much.
15316 */
15317 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
15318 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15319 DREF_SSC1_ENABLE);
15320
15321 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15322 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15323 bios_lvds_use_ssc ? "en" : "dis",
15324 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15325 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15326 }
15327 }
15328
a6c45cf0
CW		 15329 if (IS_GEN2(dev)) {
15330 dev->mode_config.max_width = 2048;
15331 dev->mode_config.max_height = 2048;
15332 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 15333 dev->mode_config.max_width = 4096;
15334 dev->mode_config.max_height = 4096;
79e53945 15335 } else {
a6c45cf0
CW		 15336 dev->mode_config.max_width = 8192;
15337 dev->mode_config.max_height = 8192;
79e53945 15338 }
068be561 15339
dc41c154
VS		 15340 if (IS_845G(dev) || IS_I865G(dev)) {
15341 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15342 dev->mode_config.cursor_height = 1023;
15343 } else if (IS_GEN2(dev)) {
068be561
DL		 15344 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15345 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15346 } else {
15347 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15348 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15349 }
15350
72e96d64 15351 dev->mode_config.fb_base = ggtt->mappable_base;
79e53945 15352
28c97730 15353 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 15354 INTEL_INFO(dev)->num_pipes,
15355 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 15356
055e393f 15357 for_each_pipe(dev_priv, pipe) {
8cc87b75 15358 intel_crtc_init(dev, pipe);
3bdcfc0c 15359 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 15360 ret = intel_plane_init(dev, pipe, sprite);
7f1f3851 15361 if (ret)
06da8da2 15362 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
1fe47785 15363 pipe_name(pipe), sprite_name(pipe, sprite), ret);
7f1f3851 15364 }
79e53945
JB		 15365 }
15366
bfa7df01 15367 intel_update_czclk(dev_priv);
e7dc33f3 15368 intel_update_rawclk(dev_priv);
bfa7df01
VS		 15369 intel_update_cdclk(dev);
15370
e72f9fbf 15371 intel_shared_dpll_init(dev);
ee7b9f93 15372
9cce37f4
JB		 15373 /* Just disable it once at startup */
15374 i915_disable_vga(dev);
79e53945 15375 intel_setup_outputs(dev);
11be49eb 15376
6e9f798d 15377 drm_modeset_lock_all(dev);
043e9bda 15378 intel_modeset_setup_hw_state(dev);
6e9f798d 15379 drm_modeset_unlock_all(dev);
46f297fb 15380
d3fcc808 15381 for_each_intel_crtc(dev, crtc) {
eeebeac5
ML		 15382 struct intel_initial_plane_config plane_config = {};
15383
46f297fb
JB		 15384 if (!crtc->active)
15385 continue;
15386
46f297fb 15387 /*
46f297fb
JB		 15388 * Note that reserving the BIOS fb up front prevents us
15389 * from stuffing other stolen allocations like the ring
15390 * on top. This prevents some ugliness at boot time, and
15391 * can even allow for smooth boot transitions if the BIOS
15392 * fb is large enough for the active pipe configuration.
15393 */
eeebeac5
ML		 15394 dev_priv->display.get_initial_plane_config(crtc,
15395 &plane_config);
15396
15397 /*
15398 * If the fb is shared between multiple heads, we'll
15399 * just get the first one.
15400 */
15401 intel_find_initial_plane_obj(crtc, &plane_config);
46f297fb 15402 }
d93c0372
MR		 15403
15404 /*
15405 * Make sure hardware watermarks really match the state we read out.
15406 * Note that we need to do this after reconstructing the BIOS fb's
15407 * since the watermark calculation done here will use pstate->fb.
15408 */
15409 sanitize_watermarks(dev);
2c7111db
CW		 15410}
15411
7fad798e
DV		 15412static void intel_enable_pipe_a(struct drm_device *dev)
15413{
15414 struct intel_connector *connector;
15415 struct drm_connector *crt = NULL;
15416 struct intel_load_detect_pipe load_detect_temp;
208bf9fd 15417 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
7fad798e
DV		 15418
15419 /* We can't just switch on the pipe A, we need to set things up with a
15420 * proper mode and output configuration. As a gross hack, enable pipe A
15421 * by enabling the load detect pipe once. */
3a3371ff 15422 for_each_intel_connector(dev, connector) {
7fad798e
DV		 15423 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15424 crt = &connector->base;
15425 break;
15426 }
15427 }
15428
15429 if (!crt)
15430 return;
15431
208bf9fd 15432 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
49172fee 15433 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
7fad798e
DV		 15434}
15435
fa555837
DV		 15436static bool
15437intel_check_plane_mapping(struct intel_crtc *crtc)
15438{
7eb552ae
BW		 15439 struct drm_device *dev = crtc->base.dev;
15440 struct drm_i915_private *dev_priv = dev->dev_private;
649636ef 15441 u32 val;
fa555837 15442
7eb552ae 15443 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 15444 return true;
15445
649636ef 15446 val = I915_READ(DSPCNTR(!crtc->plane));
fa555837
DV		 15447
15448 if ((val & DISPLAY_PLANE_ENABLE) &&
15449 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15450 return false;
15451
15452 return true;
15453}
15454
02e93c35
VS		 15455static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15456{
15457 struct drm_device *dev = crtc->base.dev;
15458 struct intel_encoder *encoder;
15459
15460 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15461 return true;
15462
15463 return false;
15464}
15465
dd756198
VS		 15466static bool intel_encoder_has_connectors(struct intel_encoder *encoder)
15467{
15468 struct drm_device *dev = encoder->base.dev;
15469 struct intel_connector *connector;
15470
15471 for_each_connector_on_encoder(dev, &encoder->base, connector)
15472 return true;
15473
15474 return false;
15475}
15476
24929352
DV		 15477static void intel_sanitize_crtc(struct intel_crtc *crtc)
15478{
15479 struct drm_device *dev = crtc->base.dev;
15480 struct drm_i915_private *dev_priv = dev->dev_private;
4d1de975 15481 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
24929352 15482
24929352 15483 /* Clear any frame start delays used for debugging left by the BIOS */
4d1de975
JN		 15484 if (!transcoder_is_dsi(cpu_transcoder)) {
15485 i915_reg_t reg = PIPECONF(cpu_transcoder);
15486
15487 I915_WRITE(reg,
15488 I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15489 }
24929352 15490
d3eaf884 15491 /* restore vblank interrupts to correct state */
9625604c 15492 drm_crtc_vblank_reset(&crtc->base);
d297e103 15493 if (crtc->active) {
f9cd7b88
VS		 15494 struct intel_plane *plane;
15495
9625604c 15496 drm_crtc_vblank_on(&crtc->base);
f9cd7b88
VS		 15497
15498 /* Disable everything but the primary plane */
15499 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15500 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15501 continue;
15502
15503 plane->disable_plane(&plane->base, &crtc->base);
15504 }
9625604c 15505 }
d3eaf884 15506
24929352 15507 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 15508 * disable the crtc (and hence change the state) if it is wrong. Note
15509 * that gen4+ has a fixed plane -> pipe mapping. */
15510 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 15511 bool plane;
15512
24929352
DV		 15513 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15514 crtc->base.base.id);
15515
15516 /* Pipe has the wrong plane attached and the plane is active.
15517 * Temporarily change the plane mapping and disable everything
15518 * ... */
15519 plane = crtc->plane;
b70709a6 15520 to_intel_plane_state(crtc->base.primary->state)->visible = true;
24929352 15521 crtc->plane = !plane;
b17d48e2 15522 intel_crtc_disable_noatomic(&crtc->base);
24929352 15523 crtc->plane = plane;
24929352 15524 }
24929352 15525
7fad798e
DV		 15526 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15527 crtc->pipe == PIPE_A && !crtc->active) {
15528 /* BIOS forgot to enable pipe A, this mostly happens after
15529 * resume. Force-enable the pipe to fix this, the update_dpms
15530 * call below we restore the pipe to the right state, but leave
15531 * the required bits on. */
15532 intel_enable_pipe_a(dev);
15533 }
15534
24929352
DV		 15535 /* Adjust the state of the output pipe according to whether we
15536 * have active connectors/encoders. */
842e0307 15537 if (crtc->active && !intel_crtc_has_encoders(crtc))
b17d48e2 15538 intel_crtc_disable_noatomic(&crtc->base);
24929352 15539
a3ed6aad 15540 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
4cc31489
DV		 15541 /*
15542 * We start out with underrun reporting disabled to avoid races.
15543 * For correct bookkeeping mark this on active crtcs.
15544 *
c5ab3bc0
DV		 15545 * Also on gmch platforms we dont have any hardware bits to
15546 * disable the underrun reporting. Which means we need to start
15547 * out with underrun reporting disabled also on inactive pipes,
15548 * since otherwise we'll complain about the garbage we read when
15549 * e.g. coming up after runtime pm.
15550 *
4cc31489
DV		 15551 * No protection against concurrent access is required - at
15552 * worst a fifo underrun happens which also sets this to false.
15553 */
15554 crtc->cpu_fifo_underrun_disabled = true;
15555 crtc->pch_fifo_underrun_disabled = true;
15556 }
24929352
DV		 15557}
15558
15559static void intel_sanitize_encoder(struct intel_encoder *encoder)
15560{
15561 struct intel_connector *connector;
15562 struct drm_device *dev = encoder->base.dev;
15563
15564 /* We need to check both for a crtc link (meaning that the
15565 * encoder is active and trying to read from a pipe) and the
15566 * pipe itself being active. */
15567 bool has_active_crtc = encoder->base.crtc &&
15568 to_intel_crtc(encoder->base.crtc)->active;
15569
dd756198 15570 if (intel_encoder_has_connectors(encoder) && !has_active_crtc) {
24929352
DV		 15571 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15572 encoder->base.base.id,
8e329a03 15573 encoder->base.name);
24929352
DV		 15574
15575 /* Connector is active, but has no active pipe. This is
15576 * fallout from our resume register restoring. Disable
15577 * the encoder manually again. */
15578 if (encoder->base.crtc) {
15579 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15580 encoder->base.base.id,
8e329a03 15581 encoder->base.name);
24929352 15582 encoder->disable(encoder);
a62d1497
VS		 15583 if (encoder->post_disable)
15584 encoder->post_disable(encoder);
24929352 15585 }
7f1950fb 15586 encoder->base.crtc = NULL;
24929352
DV		 15587
15588 /* Inconsistent output/port/pipe state happens presumably due to
15589 * a bug in one of the get_hw_state functions. Or someplace else
15590 * in our code, like the register restore mess on resume. Clamp
15591 * things to off as a safer default. */
3a3371ff 15592 for_each_intel_connector(dev, connector) {
24929352
DV		 15593 if (connector->encoder != encoder)
15594 continue;
7f1950fb
EE		 15595 connector->base.dpms = DRM_MODE_DPMS_OFF;
15596 connector->base.encoder = NULL;
24929352
DV		 15597 }
15598 }
15599 /* Enabled encoders without active connectors will be fixed in
15600 * the crtc fixup. */
15601}
15602
04098753 15603void i915_redisable_vga_power_on(struct drm_device *dev)
0fde901f
KM		 15604{
15605 struct drm_i915_private *dev_priv = dev->dev_private;
f0f59a00 15606 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
0fde901f 15607
04098753
ID		 15608 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15609 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15610 i915_disable_vga(dev);
15611 }
15612}
15613
15614void i915_redisable_vga(struct drm_device *dev)
15615{
15616 struct drm_i915_private *dev_priv = dev->dev_private;
15617
8dc8a27c
PZ		 15618 /* This function can be called both from intel_modeset_setup_hw_state or
15619 * at a very early point in our resume sequence, where the power well
15620 * structures are not yet restored. Since this function is at a very
15621 * paranoid "someone might have enabled VGA while we were not looking"
15622 * level, just check if the power well is enabled instead of trying to
15623 * follow the "don't touch the power well if we don't need it" policy
15624 * the rest of the driver uses. */
6392f847 15625 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
8dc8a27c
PZ		 15626 return;
15627
04098753 15628 i915_redisable_vga_power_on(dev);
6392f847
ID		 15629
15630 intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
0fde901f
KM		 15631}
15632
f9cd7b88 15633static bool primary_get_hw_state(struct intel_plane *plane)
98ec7739 15634{
f9cd7b88 15635 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
98ec7739 15636
f9cd7b88 15637 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
d032ffa0
ML		 15638}
15639
f9cd7b88
VS		 15640/* FIXME read out full plane state for all planes */
15641static void readout_plane_state(struct intel_crtc *crtc)
d032ffa0 15642{
b26d3ea3 15643 struct drm_plane *primary = crtc->base.primary;
f9cd7b88 15644 struct intel_plane_state *plane_state =
b26d3ea3 15645 to_intel_plane_state(primary->state);
d032ffa0 15646
19b8d387 15647 plane_state->visible = crtc->active &&
b26d3ea3
ML		 15648 primary_get_hw_state(to_intel_plane(primary));
15649
15650 if (plane_state->visible)
15651 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
98ec7739
VS		 15652}
15653
30e984df 15654static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 15655{
15656 struct drm_i915_private *dev_priv = dev->dev_private;
15657 enum pipe pipe;
24929352
DV		 15658 struct intel_crtc *crtc;
15659 struct intel_encoder *encoder;
15660 struct intel_connector *connector;
5358901f 15661 int i;
24929352 15662
565602d7
ML		 15663 dev_priv->active_crtcs = 0;
15664
d3fcc808 15665 for_each_intel_crtc(dev, crtc) {
565602d7
ML		 15666 struct intel_crtc_state *crtc_state = crtc->config;
15667 int pixclk = 0;
3b117c8f 15668
565602d7
ML		 15669 __drm_atomic_helper_crtc_destroy_state(&crtc->base, &crtc_state->base);
15670 memset(crtc_state, 0, sizeof(*crtc_state));
15671 crtc_state->base.crtc = &crtc->base;
24929352 15672
565602d7
ML		 15673 crtc_state->base.active = crtc_state->base.enable =
15674 dev_priv->display.get_pipe_config(crtc, crtc_state);
15675
15676 crtc->base.enabled = crtc_state->base.enable;
15677 crtc->active = crtc_state->base.active;
15678
15679 if (crtc_state->base.active) {
15680 dev_priv->active_crtcs |= 1 << crtc->pipe;
15681
15682 if (IS_BROADWELL(dev_priv)) {
15683 pixclk = ilk_pipe_pixel_rate(crtc_state);
15684
15685 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
15686 if (crtc_state->ips_enabled)
15687 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
15688 } else if (IS_VALLEYVIEW(dev_priv) ||
15689 IS_CHERRYVIEW(dev_priv) ||
15690 IS_BROXTON(dev_priv))
15691 pixclk = crtc_state->base.adjusted_mode.crtc_clock;
15692 else
15693 WARN_ON(dev_priv->display.modeset_calc_cdclk);
15694 }
15695
15696 dev_priv->min_pixclk[crtc->pipe] = pixclk;
b70709a6 15697
f9cd7b88 15698 readout_plane_state(crtc);
24929352
DV		 15699
15700 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15701 crtc->base.base.id,
15702 crtc->active ? "enabled" : "disabled");
15703 }
15704
5358901f
DV		 15705 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15706 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15707
2edd6443
ACO		 15708 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
15709 &pll->config.hw_state);
3e369b76 15710 pll->config.crtc_mask = 0;
d3fcc808 15711 for_each_intel_crtc(dev, crtc) {
2dd66ebd 15712 if (crtc->active && crtc->config->shared_dpll == pll)
3e369b76 15713 pll->config.crtc_mask |= 1 << crtc->pipe;
5358901f 15714 }
2dd66ebd 15715 pll->active_mask = pll->config.crtc_mask;
5358901f 15716
1e6f2ddc 15717 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
3e369b76 15718 pll->name, pll->config.crtc_mask, pll->on);
5358901f
DV		 15719 }
15720
b2784e15 15721 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15722 pipe = 0;
15723
15724 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 15725 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15726 encoder->base.crtc = &crtc->base;
6e3c9717 15727 encoder->get_config(encoder, crtc->config);
24929352
DV		 15728 } else {
15729 encoder->base.crtc = NULL;
15730 }
15731
6f2bcceb 15732 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
24929352 15733 encoder->base.base.id,
8e329a03 15734 encoder->base.name,
24929352 15735 encoder->base.crtc ? "enabled" : "disabled",
6f2bcceb 15736 pipe_name(pipe));
24929352
DV		 15737 }
15738
3a3371ff 15739 for_each_intel_connector(dev, connector) {
24929352
DV		 15740 if (connector->get_hw_state(connector)) {
15741 connector->base.dpms = DRM_MODE_DPMS_ON;
2aa974c9
ML		 15742
15743 encoder = connector->encoder;
15744 connector->base.encoder = &encoder->base;
15745
15746 if (encoder->base.crtc &&
15747 encoder->base.crtc->state->active) {
15748 /*
15749 * This has to be done during hardware readout
15750 * because anything calling .crtc_disable may
15751 * rely on the connector_mask being accurate.
15752 */
15753 encoder->base.crtc->state->connector_mask |=
15754 1 << drm_connector_index(&connector->base);
e87a52b3
ML		 15755 encoder->base.crtc->state->encoder_mask |=
15756 1 << drm_encoder_index(&encoder->base);
2aa974c9
ML		 15757 }
15758
24929352
DV		 15759 } else {
15760 connector->base.dpms = DRM_MODE_DPMS_OFF;
15761 connector->base.encoder = NULL;
15762 }
15763 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15764 connector->base.base.id,
c23cc417 15765 connector->base.name,
24929352
DV		 15766 connector->base.encoder ? "enabled" : "disabled");
15767 }
7f4c6284
VS		 15768
15769 for_each_intel_crtc(dev, crtc) {
15770 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15771
15772 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15773 if (crtc->base.state->active) {
15774 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15775 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15776 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15777
15778 /*
15779 * The initial mode needs to be set in order to keep
15780 * the atomic core happy. It wants a valid mode if the
15781 * crtc's enabled, so we do the above call.
15782 *
15783 * At this point some state updated by the connectors
15784 * in their ->detect() callback has not run yet, so
15785 * no recalculation can be done yet.
15786 *
15787 * Even if we could do a recalculation and modeset
15788 * right now it would cause a double modeset if
15789 * fbdev or userspace chooses a different initial mode.
15790 *
15791 * If that happens, someone indicated they wanted a
15792 * mode change, which means it's safe to do a full
15793 * recalculation.
15794 */
15795 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
9eca6832
VS		 15796
15797 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15798 update_scanline_offset(crtc);
7f4c6284 15799 }
e3b247da
VS		 15800
15801 intel_pipe_config_sanity_check(dev_priv, crtc->config);
7f4c6284 15802 }
30e984df
DV		 15803}
15804
043e9bda
ML		 15805/* Scan out the current hw modeset state,
15806 * and sanitizes it to the current state
15807 */
15808static void
15809intel_modeset_setup_hw_state(struct drm_device *dev)
30e984df
DV		 15810{
15811 struct drm_i915_private *dev_priv = dev->dev_private;
15812 enum pipe pipe;
30e984df
DV		 15813 struct intel_crtc *crtc;
15814 struct intel_encoder *encoder;
35c95375 15815 int i;
30e984df
DV		 15816
15817 intel_modeset_readout_hw_state(dev);
24929352
DV		 15818
15819 /* HW state is read out, now we need to sanitize this mess. */
b2784e15 15820 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15821 intel_sanitize_encoder(encoder);
15822 }
15823
055e393f 15824 for_each_pipe(dev_priv, pipe) {
24929352
DV		 15825 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15826 intel_sanitize_crtc(crtc);
6e3c9717
ACO		 15827 intel_dump_pipe_config(crtc, crtc->config,
15828 "[setup_hw_state]");
24929352 15829 }
9a935856 15830
d29b2f9d
ACO		 15831 intel_modeset_update_connector_atomic_state(dev);
15832
35c95375
DV		 15833 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15834 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15835
2dd66ebd 15836 if (!pll->on || pll->active_mask)
35c95375
DV		 15837 continue;
15838
15839 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15840
2edd6443 15841 pll->funcs.disable(dev_priv, pll);
35c95375
DV		 15842 pll->on = false;
15843 }
15844
666a4537 15845 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
6eb1a681
VS		 15846 vlv_wm_get_hw_state(dev);
15847 else if (IS_GEN9(dev))
3078999f
PB		 15848 skl_wm_get_hw_state(dev);
15849 else if (HAS_PCH_SPLIT(dev))
243e6a44 15850 ilk_wm_get_hw_state(dev);
292b990e
ML		 15851
15852 for_each_intel_crtc(dev, crtc) {
15853 unsigned long put_domains;
15854
74bff5f9 15855 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
292b990e
ML		 15856 if (WARN_ON(put_domains))
15857 modeset_put_power_domains(dev_priv, put_domains);
15858 }
15859 intel_display_set_init_power(dev_priv, false);
010cf73d
PZ		 15860
15861 intel_fbc_init_pipe_state(dev_priv);
043e9bda 15862}
7d0bc1ea 15863
043e9bda
ML		 15864void intel_display_resume(struct drm_device *dev)
15865{
e2c8b870
ML		 15866 struct drm_i915_private *dev_priv = to_i915(dev);
15867 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
15868 struct drm_modeset_acquire_ctx ctx;
043e9bda 15869 int ret;
e2c8b870 15870 bool setup = false;
f30da187 15871
e2c8b870 15872 dev_priv->modeset_restore_state = NULL;
043e9bda 15873
ea49c9ac
ML		 15874 /*
15875 * This is a cludge because with real atomic modeset mode_config.mutex
15876 * won't be taken. Unfortunately some probed state like
15877 * audio_codec_enable is still protected by mode_config.mutex, so lock
15878 * it here for now.
15879 */
15880 mutex_lock(&dev->mode_config.mutex);
e2c8b870 15881 drm_modeset_acquire_init(&ctx, 0);
043e9bda 15882
e2c8b870
ML		 15883retry:
15884 ret = drm_modeset_lock_all_ctx(dev, &ctx);
043e9bda 15885
e2c8b870
ML		 15886 if (ret == 0 && !setup) {
15887 setup = true;
043e9bda 15888
e2c8b870
ML		 15889 intel_modeset_setup_hw_state(dev);
15890 i915_redisable_vga(dev);
45e2b5f6 15891 }
8af6cf88 15892
e2c8b870
ML		 15893 if (ret == 0 && state) {
15894 struct drm_crtc_state *crtc_state;
15895 struct drm_crtc *crtc;
15896 int i;
043e9bda 15897
e2c8b870
ML		 15898 state->acquire_ctx = &ctx;
15899
15900 for_each_crtc_in_state(state, crtc, crtc_state, i) {
15901 /*
15902 * Force recalculation even if we restore
15903 * current state. With fast modeset this may not result
15904 * in a modeset when the state is compatible.
15905 */
15906 crtc_state->mode_changed = true;
15907 }
15908
15909 ret = drm_atomic_commit(state);
043e9bda
ML		 15910 }
15911
e2c8b870
ML		 15912 if (ret == -EDEADLK) {
15913 drm_modeset_backoff(&ctx);
15914 goto retry;
15915 }
043e9bda 15916
e2c8b870
ML		 15917 drm_modeset_drop_locks(&ctx);
15918 drm_modeset_acquire_fini(&ctx);
ea49c9ac 15919 mutex_unlock(&dev->mode_config.mutex);
043e9bda 15920
e2c8b870
ML		 15921 if (ret) {
15922 DRM_ERROR("Restoring old state failed with %i\n", ret);
15923 drm_atomic_state_free(state);
15924 }
2c7111db
CW		 15925}
15926
15927void intel_modeset_gem_init(struct drm_device *dev)
15928{
484b41dd 15929 struct drm_crtc *c;
2ff8fde1 15930 struct drm_i915_gem_object *obj;
e0d6149b 15931 int ret;
484b41dd 15932
ae48434c 15933 intel_init_gt_powersave(dev);
ae48434c 15934
1833b134 15935 intel_modeset_init_hw(dev);
02e792fb
DV		 15936
15937 intel_setup_overlay(dev);
484b41dd
JB		 15938
15939 /*
15940 * Make sure any fbs we allocated at startup are properly
15941 * pinned & fenced. When we do the allocation it's too early
15942 * for this.
15943 */
70e1e0ec 15944 for_each_crtc(dev, c) {
2ff8fde1
MR		 15945 obj = intel_fb_obj(c->primary->fb);
15946 if (obj == NULL)
484b41dd
JB		 15947 continue;
15948
e0d6149b 15949 mutex_lock(&dev->struct_mutex);
3465c580
VS		 15950 ret = intel_pin_and_fence_fb_obj(c->primary->fb,
15951 c->primary->state->rotation);
e0d6149b
TU		 15952 mutex_unlock(&dev->struct_mutex);
15953 if (ret) {
484b41dd
JB		 15954 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15955 to_intel_crtc(c)->pipe);
66e514c1
DA		 15956 drm_framebuffer_unreference(c->primary->fb);
15957 c->primary->fb = NULL;
36750f28 15958 c->primary->crtc = c->primary->state->crtc = NULL;
afd65eb4 15959 update_state_fb(c->primary);
36750f28 15960 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
484b41dd
JB		 15961 }
15962 }
0962c3c9
VS		 15963
15964 intel_backlight_register(dev);
79e53945
JB		 15965}
15966
4932e2c3
ID		 15967void intel_connector_unregister(struct intel_connector *intel_connector)
15968{
15969 struct drm_connector *connector = &intel_connector->base;
15970
15971 intel_panel_destroy_backlight(connector);
34ea3d38 15972 drm_connector_unregister(connector);
4932e2c3
ID		 15973}
15974
79e53945
JB		 15975void intel_modeset_cleanup(struct drm_device *dev)
15976{
652c393a 15977 struct drm_i915_private *dev_priv = dev->dev_private;
19c8054c 15978 struct intel_connector *connector;
652c393a 15979
2eb5252e
ID		 15980 intel_disable_gt_powersave(dev);
15981
0962c3c9
VS		 15982 intel_backlight_unregister(dev);
15983
fd0c0642
DV		 15984 /*
15985 * Interrupts and polling as the first thing to avoid creating havoc.
2eb5252e 15986 * Too much stuff here (turning of connectors, ...) would
fd0c0642
DV		 15987 * experience fancy races otherwise.
15988 */
2aeb7d3a 15989 intel_irq_uninstall(dev_priv);
eb21b92b 15990
fd0c0642
DV		 15991 /*
15992 * Due to the hpd irq storm handling the hotplug work can re-arm the
15993 * poll handlers. Hence disable polling after hpd handling is shut down.
15994 */
f87ea761 15995 drm_kms_helper_poll_fini(dev);
fd0c0642 15996
723bfd70
JB		 15997 intel_unregister_dsm_handler();
15998
c937ab3e 15999 intel_fbc_global_disable(dev_priv);
69341a5e 16000
1630fe75
CW		 16001 /* flush any delayed tasks or pending work */
16002 flush_scheduled_work();
16003
db31af1d 16004 /* destroy the backlight and sysfs files before encoders/connectors */
19c8054c
JN		 16005 for_each_intel_connector(dev, connector)
16006 connector->unregister(connector);
d9255d57 16007
79e53945 16008 drm_mode_config_cleanup(dev);
4d7bb011
DV		 16009
16010 intel_cleanup_overlay(dev);
ae48434c 16011
ae48434c 16012 intel_cleanup_gt_powersave(dev);
f5949141
DV		 16013
16014 intel_teardown_gmbus(dev);
79e53945
JB		 16015}
16016
f1c79df3
ZW		 16017/*
16018 * Return which encoder is currently attached for connector.
16019 */
df0e9248 16020struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 16021{
df0e9248
CW		 16022 return &intel_attached_encoder(connector)->base;
16023}
f1c79df3 16024
df0e9248
CW		 16025void intel_connector_attach_encoder(struct intel_connector *connector,
16026 struct intel_encoder *encoder)
16027{
16028 connector->encoder = encoder;
16029 drm_mode_connector_attach_encoder(&connector->base,
16030 &encoder->base);
79e53945 16031}
28d52043
DA		 16032
16033/*
16034 * set vga decode state - true == enable VGA decode
16035 */
16036int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
16037{
16038 struct drm_i915_private *dev_priv = dev->dev_private;
a885b3cc 16039 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
28d52043
DA		 16040 u16 gmch_ctrl;
16041
75fa041d
CW		 16042 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
16043 DRM_ERROR("failed to read control word\n");
16044 return -EIO;
16045 }
16046
c0cc8a55
CW		 16047 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
16048 return 0;
16049
28d52043
DA		 16050 if (state)
16051 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
16052 else
16053 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
75fa041d
CW		 16054
16055 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
16056 DRM_ERROR("failed to write control word\n");
16057 return -EIO;
16058 }
16059
28d52043
DA		 16060 return 0;
16061}
c4a1d9e4 16062
c4a1d9e4 16063struct intel_display_error_state {
ff57f1b0
PZ		 16064
16065 u32 power_well_driver;
16066
63b66e5b
CW		 16067 int num_transcoders;
16068
c4a1d9e4
CW		 16069 struct intel_cursor_error_state {
16070 u32 control;
16071 u32 position;
16072 u32 base;
16073 u32 size;
52331309 16074 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 16075
16076 struct intel_pipe_error_state {
ddf9c536 16077 bool power_domain_on;
c4a1d9e4 16078 u32 source;
f301b1e1 16079 u32 stat;
52331309 16080 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 16081
16082 struct intel_plane_error_state {
16083 u32 control;
16084 u32 stride;
16085 u32 size;
16086 u32 pos;
16087 u32 addr;
16088 u32 surface;
16089 u32 tile_offset;
52331309 16090 } plane[I915_MAX_PIPES];
63b66e5b
CW		 16091
16092 struct intel_transcoder_error_state {
ddf9c536 16093 bool power_domain_on;
63b66e5b
CW		 16094 enum transcoder cpu_transcoder;
16095
16096 u32 conf;
16097
16098 u32 htotal;
16099 u32 hblank;
16100 u32 hsync;
16101 u32 vtotal;
16102 u32 vblank;
16103 u32 vsync;
16104 } transcoder[4];
c4a1d9e4
CW		 16105};
16106
16107struct intel_display_error_state *
16108intel_display_capture_error_state(struct drm_device *dev)
16109{
fbee40df 16110 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4 16111 struct intel_display_error_state *error;
63b66e5b
CW		 16112 int transcoders[] = {
16113 TRANSCODER_A,
16114 TRANSCODER_B,
16115 TRANSCODER_C,
16116 TRANSCODER_EDP,
16117 };
c4a1d9e4
CW		 16118 int i;
16119
63b66e5b
CW		 16120 if (INTEL_INFO(dev)->num_pipes == 0)
16121 return NULL;
16122
9d1cb914 16123 error = kzalloc(sizeof(*error), GFP_ATOMIC);
c4a1d9e4
CW		 16124 if (error == NULL)
16125 return NULL;
16126
190be112 16127 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ff57f1b0
PZ		 16128 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
16129
055e393f 16130 for_each_pipe(dev_priv, i) {
ddf9c536 16131 error->pipe[i].power_domain_on =
f458ebbc
DV		 16132 __intel_display_power_is_enabled(dev_priv,
16133 POWER_DOMAIN_PIPE(i));
ddf9c536 16134 if (!error->pipe[i].power_domain_on)
9d1cb914
PZ		 16135 continue;
16136
5efb3e28
VS		 16137 error->cursor[i].control = I915_READ(CURCNTR(i));
16138 error->cursor[i].position = I915_READ(CURPOS(i));
16139 error->cursor[i].base = I915_READ(CURBASE(i));
c4a1d9e4
CW		 16140
16141 error->plane[i].control = I915_READ(DSPCNTR(i));
16142 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 16143 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 16144 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 16145 error->plane[i].pos = I915_READ(DSPPOS(i));
16146 }
ca291363
PZ		 16147 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16148 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 16149 if (INTEL_INFO(dev)->gen >= 4) {
16150 error->plane[i].surface = I915_READ(DSPSURF(i));
16151 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
16152 }
16153
c4a1d9e4 16154 error->pipe[i].source = I915_READ(PIPESRC(i));
f301b1e1 16155
3abfce77 16156 if (HAS_GMCH_DISPLAY(dev))
f301b1e1 16157 error->pipe[i].stat = I915_READ(PIPESTAT(i));
63b66e5b
CW		 16158 }
16159
4d1de975 16160 /* Note: this does not include DSI transcoders. */
63b66e5b
CW		 16161 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
16162 if (HAS_DDI(dev_priv->dev))
16163 error->num_transcoders++; /* Account for eDP. */
16164
16165 for (i = 0; i < error->num_transcoders; i++) {
16166 enum transcoder cpu_transcoder = transcoders[i];
16167
ddf9c536 16168 error->transcoder[i].power_domain_on =
f458ebbc 16169 __intel_display_power_is_enabled(dev_priv,
38cc1daf 16170 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
ddf9c536 16171 if (!error->transcoder[i].power_domain_on)
9d1cb914
PZ		 16172 continue;
16173
63b66e5b
CW		 16174 error->transcoder[i].cpu_transcoder = cpu_transcoder;
16175
16176 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
16177 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
16178 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
16179 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
16180 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
16181 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
16182 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 16183 }
16184
16185 return error;
16186}
16187
edc3d884
MK		 16188#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
16189
c4a1d9e4 16190void
edc3d884 16191intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 16192 struct drm_device *dev,
16193 struct intel_display_error_state *error)
16194{
055e393f 16195 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4
CW		 16196 int i;
16197
63b66e5b
CW		 16198 if (!error)
16199 return;
16200
edc3d884 16201 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
190be112 16202 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
edc3d884 16203 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 16204 error->power_well_driver);
055e393f 16205 for_each_pipe(dev_priv, i) {
edc3d884 16206 err_printf(m, "Pipe [%d]:\n", i);
ddf9c536 16207 err_printf(m, " Power: %s\n",
87ad3212 16208 onoff(error->pipe[i].power_domain_on));
edc3d884 16209 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
f301b1e1 16210 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
edc3d884
MK		 16211
16212 err_printf(m, "Plane [%d]:\n", i);
16213 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
16214 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 16215 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 16216 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
16217 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 16218 }
4b71a570 16219 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 16220 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 16221 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 16222 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
16223 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 16224 }
16225
edc3d884
MK		 16226 err_printf(m, "Cursor [%d]:\n", i);
16227 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
16228 err_printf(m, " POS: %08x\n", error->cursor[i].position);
16229 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 16230 }
63b66e5b
CW		 16231
16232 for (i = 0; i < error->num_transcoders; i++) {
da205630 16233 err_printf(m, "CPU transcoder: %s\n",
63b66e5b 16234 transcoder_name(error->transcoder[i].cpu_transcoder));
ddf9c536 16235 err_printf(m, " Power: %s\n",
87ad3212 16236 onoff(error->transcoder[i].power_domain_on));
63b66e5b
CW		 16237 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
16238 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
16239 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
16240 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
16241 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
16242 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
16243 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
16244 }
c4a1d9e4 16245}
Linux 6.x block layer and io_uring tree(s)