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drm/i915: Use adjusted_mode in DSI PLL calculations
[linux-block.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 47
f1f644dc
JB		 48static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
49 struct intel_crtc_config *pipe_config);
18442d08
VS		 50static void ironlake_pch_clock_get(struct intel_crtc *crtc,
51 struct intel_crtc_config *pipe_config);
f1f644dc 52
e7457a9a
DL		 53static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
54 int x, int y, struct drm_framebuffer *old_fb);
55
56
79e53945 57typedef struct {
0206e353 58 int min, max;
79e53945
JB		 59} intel_range_t;
60
61typedef struct {
0206e353
AJ		 62 int dot_limit;
63 int p2_slow, p2_fast;
79e53945
JB		 64} intel_p2_t;
65
d4906093
ML		 66typedef struct intel_limit intel_limit_t;
67struct intel_limit {
0206e353
AJ		 68 intel_range_t dot, vco, n, m, m1, m2, p, p1;
69 intel_p2_t p2;
d4906093 70};
79e53945 71
d2acd215
DV		 72int
73intel_pch_rawclk(struct drm_device *dev)
74{
75 struct drm_i915_private *dev_priv = dev->dev_private;
76
77 WARN_ON(!HAS_PCH_SPLIT(dev));
78
79 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
80}
81
021357ac
CW		 82static inline u32 /* units of 100MHz */
83intel_fdi_link_freq(struct drm_device *dev)
84{
8b99e68c
CW		 85 if (IS_GEN5(dev)) {
86 struct drm_i915_private *dev_priv = dev->dev_private;
87 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
88 } else
89 return 27;
021357ac
CW		 90}
91
5d536e28 92static const intel_limit_t intel_limits_i8xx_dac = {
0206e353
AJ		 93 .dot = { .min = 25000, .max = 350000 },
94 .vco = { .min = 930000, .max = 1400000 },
95 .n = { .min = 3, .max = 16 },
96 .m = { .min = 96, .max = 140 },
97 .m1 = { .min = 18, .max = 26 },
98 .m2 = { .min = 6, .max = 16 },
99 .p = { .min = 4, .max = 128 },
100 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 101 .p2 = { .dot_limit = 165000,
102 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 103};
104
5d536e28
DV		 105static const intel_limit_t intel_limits_i8xx_dvo = {
106 .dot = { .min = 25000, .max = 350000 },
107 .vco = { .min = 930000, .max = 1400000 },
108 .n = { .min = 3, .max = 16 },
109 .m = { .min = 96, .max = 140 },
110 .m1 = { .min = 18, .max = 26 },
111 .m2 = { .min = 6, .max = 16 },
112 .p = { .min = 4, .max = 128 },
113 .p1 = { .min = 2, .max = 33 },
114 .p2 = { .dot_limit = 165000,
115 .p2_slow = 4, .p2_fast = 4 },
116};
117
e4b36699 118static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 119 .dot = { .min = 25000, .max = 350000 },
120 .vco = { .min = 930000, .max = 1400000 },
121 .n = { .min = 3, .max = 16 },
122 .m = { .min = 96, .max = 140 },
123 .m1 = { .min = 18, .max = 26 },
124 .m2 = { .min = 6, .max = 16 },
125 .p = { .min = 4, .max = 128 },
126 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 127 .p2 = { .dot_limit = 165000,
128 .p2_slow = 14, .p2_fast = 7 },
e4b36699 129};
273e27ca 130
e4b36699 131static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 132 .dot = { .min = 20000, .max = 400000 },
133 .vco = { .min = 1400000, .max = 2800000 },
134 .n = { .min = 1, .max = 6 },
135 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 136 .m1 = { .min = 8, .max = 18 },
137 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 138 .p = { .min = 5, .max = 80 },
139 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 140 .p2 = { .dot_limit = 200000,
141 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 142};
143
144static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 145 .dot = { .min = 20000, .max = 400000 },
146 .vco = { .min = 1400000, .max = 2800000 },
147 .n = { .min = 1, .max = 6 },
148 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 149 .m1 = { .min = 8, .max = 18 },
150 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 151 .p = { .min = 7, .max = 98 },
152 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 153 .p2 = { .dot_limit = 112000,
154 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 155};
156
273e27ca 157
e4b36699 158static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 159 .dot = { .min = 25000, .max = 270000 },
160 .vco = { .min = 1750000, .max = 3500000},
161 .n = { .min = 1, .max = 4 },
162 .m = { .min = 104, .max = 138 },
163 .m1 = { .min = 17, .max = 23 },
164 .m2 = { .min = 5, .max = 11 },
165 .p = { .min = 10, .max = 30 },
166 .p1 = { .min = 1, .max = 3},
167 .p2 = { .dot_limit = 270000,
168 .p2_slow = 10,
169 .p2_fast = 10
044c7c41 170 },
e4b36699
KP		 171};
172
173static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 174 .dot = { .min = 22000, .max = 400000 },
175 .vco = { .min = 1750000, .max = 3500000},
176 .n = { .min = 1, .max = 4 },
177 .m = { .min = 104, .max = 138 },
178 .m1 = { .min = 16, .max = 23 },
179 .m2 = { .min = 5, .max = 11 },
180 .p = { .min = 5, .max = 80 },
181 .p1 = { .min = 1, .max = 8},
182 .p2 = { .dot_limit = 165000,
183 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 184};
185
186static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 187 .dot = { .min = 20000, .max = 115000 },
188 .vco = { .min = 1750000, .max = 3500000 },
189 .n = { .min = 1, .max = 3 },
190 .m = { .min = 104, .max = 138 },
191 .m1 = { .min = 17, .max = 23 },
192 .m2 = { .min = 5, .max = 11 },
193 .p = { .min = 28, .max = 112 },
194 .p1 = { .min = 2, .max = 8 },
195 .p2 = { .dot_limit = 0,
196 .p2_slow = 14, .p2_fast = 14
044c7c41 197 },
e4b36699
KP		 198};
199
200static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 201 .dot = { .min = 80000, .max = 224000 },
202 .vco = { .min = 1750000, .max = 3500000 },
203 .n = { .min = 1, .max = 3 },
204 .m = { .min = 104, .max = 138 },
205 .m1 = { .min = 17, .max = 23 },
206 .m2 = { .min = 5, .max = 11 },
207 .p = { .min = 14, .max = 42 },
208 .p1 = { .min = 2, .max = 6 },
209 .p2 = { .dot_limit = 0,
210 .p2_slow = 7, .p2_fast = 7
044c7c41 211 },
e4b36699
KP		 212};
213
f2b115e6 214static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 215 .dot = { .min = 20000, .max = 400000},
216 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 217 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 218 .n = { .min = 3, .max = 6 },
219 .m = { .min = 2, .max = 256 },
273e27ca 220 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 221 .m1 = { .min = 0, .max = 0 },
222 .m2 = { .min = 0, .max = 254 },
223 .p = { .min = 5, .max = 80 },
224 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 225 .p2 = { .dot_limit = 200000,
226 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 227};
228
f2b115e6 229static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 230 .dot = { .min = 20000, .max = 400000 },
231 .vco = { .min = 1700000, .max = 3500000 },
232 .n = { .min = 3, .max = 6 },
233 .m = { .min = 2, .max = 256 },
234 .m1 = { .min = 0, .max = 0 },
235 .m2 = { .min = 0, .max = 254 },
236 .p = { .min = 7, .max = 112 },
237 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 238 .p2 = { .dot_limit = 112000,
239 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 240};
241
273e27ca
EA		 242/* Ironlake / Sandybridge
243 *
244 * We calculate clock using (register_value + 2) for N/M1/M2, so here
245 * the range value for them is (actual_value - 2).
246 */
b91ad0ec 247static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 248 .dot = { .min = 25000, .max = 350000 },
249 .vco = { .min = 1760000, .max = 3510000 },
250 .n = { .min = 1, .max = 5 },
251 .m = { .min = 79, .max = 127 },
252 .m1 = { .min = 12, .max = 22 },
253 .m2 = { .min = 5, .max = 9 },
254 .p = { .min = 5, .max = 80 },
255 .p1 = { .min = 1, .max = 8 },
256 .p2 = { .dot_limit = 225000,
257 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 258};
259
b91ad0ec 260static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 261 .dot = { .min = 25000, .max = 350000 },
262 .vco = { .min = 1760000, .max = 3510000 },
263 .n = { .min = 1, .max = 3 },
264 .m = { .min = 79, .max = 118 },
265 .m1 = { .min = 12, .max = 22 },
266 .m2 = { .min = 5, .max = 9 },
267 .p = { .min = 28, .max = 112 },
268 .p1 = { .min = 2, .max = 8 },
269 .p2 = { .dot_limit = 225000,
270 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 271};
272
273static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 274 .dot = { .min = 25000, .max = 350000 },
275 .vco = { .min = 1760000, .max = 3510000 },
276 .n = { .min = 1, .max = 3 },
277 .m = { .min = 79, .max = 127 },
278 .m1 = { .min = 12, .max = 22 },
279 .m2 = { .min = 5, .max = 9 },
280 .p = { .min = 14, .max = 56 },
281 .p1 = { .min = 2, .max = 8 },
282 .p2 = { .dot_limit = 225000,
283 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 284};
285
273e27ca 286/* LVDS 100mhz refclk limits. */
b91ad0ec 287static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 288 .dot = { .min = 25000, .max = 350000 },
289 .vco = { .min = 1760000, .max = 3510000 },
290 .n = { .min = 1, .max = 2 },
291 .m = { .min = 79, .max = 126 },
292 .m1 = { .min = 12, .max = 22 },
293 .m2 = { .min = 5, .max = 9 },
294 .p = { .min = 28, .max = 112 },
0206e353 295 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 296 .p2 = { .dot_limit = 225000,
297 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 298};
299
300static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 301 .dot = { .min = 25000, .max = 350000 },
302 .vco = { .min = 1760000, .max = 3510000 },
303 .n = { .min = 1, .max = 3 },
304 .m = { .min = 79, .max = 126 },
305 .m1 = { .min = 12, .max = 22 },
306 .m2 = { .min = 5, .max = 9 },
307 .p = { .min = 14, .max = 42 },
0206e353 308 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 309 .p2 = { .dot_limit = 225000,
310 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 311};
312
a0c4da24
JB		 313static const intel_limit_t intel_limits_vlv_dac = {
314 .dot = { .min = 25000, .max = 270000 },
315 .vco = { .min = 4000000, .max = 6000000 },
316 .n = { .min = 1, .max = 7 },
317 .m = { .min = 22, .max = 450 }, /* guess */
318 .m1 = { .min = 2, .max = 3 },
319 .m2 = { .min = 11, .max = 156 },
320 .p = { .min = 10, .max = 30 },
75e53986 321 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 322 .p2 = { .dot_limit = 270000,
323 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 324};
325
326static const intel_limit_t intel_limits_vlv_hdmi = {
75e53986
DV		 327 .dot = { .min = 25000, .max = 270000 },
328 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24
JB		 329 .n = { .min = 1, .max = 7 },
330 .m = { .min = 60, .max = 300 }, /* guess */
331 .m1 = { .min = 2, .max = 3 },
332 .m2 = { .min = 11, .max = 156 },
333 .p = { .min = 10, .max = 30 },
334 .p1 = { .min = 2, .max = 3 },
335 .p2 = { .dot_limit = 270000,
336 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 337};
338
1b894b59
CW		 339static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
340 int refclk)
2c07245f 341{
b91ad0ec 342 struct drm_device *dev = crtc->dev;
2c07245f 343 const intel_limit_t *limit;
b91ad0ec
ZW		 344
345 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 346 if (intel_is_dual_link_lvds(dev)) {
1b894b59 347 if (refclk == 100000)
b91ad0ec
ZW		 348 limit = &intel_limits_ironlake_dual_lvds_100m;
349 else
350 limit = &intel_limits_ironlake_dual_lvds;
351 } else {
1b894b59 352 if (refclk == 100000)
b91ad0ec
ZW		 353 limit = &intel_limits_ironlake_single_lvds_100m;
354 else
355 limit = &intel_limits_ironlake_single_lvds;
356 }
c6bb3538 357 } else
b91ad0ec 358 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 359
360 return limit;
361}
362
044c7c41
ML		 363static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
364{
365 struct drm_device *dev = crtc->dev;
044c7c41
ML		 366 const intel_limit_t *limit;
367
368 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 369 if (intel_is_dual_link_lvds(dev))
e4b36699 370 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 371 else
e4b36699 372 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 373 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
374 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 375 limit = &intel_limits_g4x_hdmi;
044c7c41 376 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 377 limit = &intel_limits_g4x_sdvo;
044c7c41 378 } else /* The option is for other outputs */
e4b36699 379 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 380
381 return limit;
382}
383
1b894b59 384static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 385{
386 struct drm_device *dev = crtc->dev;
387 const intel_limit_t *limit;
388
bad720ff 389 if (HAS_PCH_SPLIT(dev))
1b894b59 390 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 391 else if (IS_G4X(dev)) {
044c7c41 392 limit = intel_g4x_limit(crtc);
f2b115e6 393 } else if (IS_PINEVIEW(dev)) {
2177832f 394 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 395 limit = &intel_limits_pineview_lvds;
2177832f 396 else
f2b115e6 397 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 398 } else if (IS_VALLEYVIEW(dev)) {
399 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
400 limit = &intel_limits_vlv_dac;
a0c4da24 401 else
65ce4bf5 402 limit = &intel_limits_vlv_hdmi;
a6c45cf0
CW		 403 } else if (!IS_GEN2(dev)) {
404 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
405 limit = &intel_limits_i9xx_lvds;
406 else
407 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 408 } else {
409 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 410 limit = &intel_limits_i8xx_lvds;
5d536e28 411 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
e4b36699 412 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 413 else
414 limit = &intel_limits_i8xx_dac;
79e53945
JB		 415 }
416 return limit;
417}
418
f2b115e6
AJ		 419/* m1 is reserved as 0 in Pineview, n is a ring counter */
420static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 421{
2177832f
SL		 422 clock->m = clock->m2 + 2;
423 clock->p = clock->p1 * clock->p2;
424 clock->vco = refclk * clock->m / clock->n;
425 clock->dot = clock->vco / clock->p;
426}
427
7429e9d4
DV		 428static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
429{
430 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
431}
432
ac58c3f0 433static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 434{
7429e9d4 435 clock->m = i9xx_dpll_compute_m(clock);
79e53945
JB		 436 clock->p = clock->p1 * clock->p2;
437 clock->vco = refclk * clock->m / (clock->n + 2);
438 clock->dot = clock->vco / clock->p;
439}
440
79e53945
JB		 441/**
442 * Returns whether any output on the specified pipe is of the specified type
443 */
4ef69c7a 444bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 445{
4ef69c7a 446 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 447 struct intel_encoder *encoder;
448
6c2b7c12
DV		 449 for_each_encoder_on_crtc(dev, crtc, encoder)
450 if (encoder->type == type)
4ef69c7a
CW		 451 return true;
452
453 return false;
79e53945
JB		 454}
455
7c04d1d9 456#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 457/**
458 * Returns whether the given set of divisors are valid for a given refclk with
459 * the given connectors.
460 */
461
1b894b59
CW		 462static bool intel_PLL_is_valid(struct drm_device *dev,
463 const intel_limit_t *limit,
464 const intel_clock_t *clock)
79e53945 465{
79e53945 466 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 467 INTELPllInvalid("p1 out of range\n");
79e53945 468 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 469 INTELPllInvalid("p out of range\n");
79e53945 470 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 471 INTELPllInvalid("m2 out of range\n");
79e53945 472 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 473 INTELPllInvalid("m1 out of range\n");
f2b115e6 474 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 475 INTELPllInvalid("m1 <= m2\n");
79e53945 476 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 477 INTELPllInvalid("m out of range\n");
79e53945 478 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 479 INTELPllInvalid("n out of range\n");
79e53945 480 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 481 INTELPllInvalid("vco out of range\n");
79e53945
JB		 482 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
483 * connector, etc., rather than just a single range.
484 */
485 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 486 INTELPllInvalid("dot out of range\n");
79e53945
JB		 487
488 return true;
489}
490
d4906093 491static bool
ee9300bb 492i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 493 int target, int refclk, intel_clock_t *match_clock,
494 intel_clock_t *best_clock)
79e53945
JB		 495{
496 struct drm_device *dev = crtc->dev;
79e53945 497 intel_clock_t clock;
79e53945
JB		 498 int err = target;
499
a210b028 500 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 501 /*
a210b028
DV		 502 * For LVDS just rely on its current settings for dual-channel.
503 * We haven't figured out how to reliably set up different
504 * single/dual channel state, if we even can.
79e53945 505 */
1974cad0 506 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 507 clock.p2 = limit->p2.p2_fast;
508 else
509 clock.p2 = limit->p2.p2_slow;
510 } else {
511 if (target < limit->p2.dot_limit)
512 clock.p2 = limit->p2.p2_slow;
513 else
514 clock.p2 = limit->p2.p2_fast;
515 }
516
0206e353 517 memset(best_clock, 0, sizeof(*best_clock));
79e53945 518
42158660
ZY		 519 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
520 clock.m1++) {
521 for (clock.m2 = limit->m2.min;
522 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 523 if (clock.m2 >= clock.m1)
42158660
ZY		 524 break;
525 for (clock.n = limit->n.min;
526 clock.n <= limit->n.max; clock.n++) {
527 for (clock.p1 = limit->p1.min;
528 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 529 int this_err;
530
ac58c3f0
DV		 531 i9xx_clock(refclk, &clock);
532 if (!intel_PLL_is_valid(dev, limit,
533 &clock))
534 continue;
535 if (match_clock &&
536 clock.p != match_clock->p)
537 continue;
538
539 this_err = abs(clock.dot - target);
540 if (this_err < err) {
541 *best_clock = clock;
542 err = this_err;
543 }
544 }
545 }
546 }
547 }
548
549 return (err != target);
550}
551
552static bool
ee9300bb
DV		 553pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
554 int target, int refclk, intel_clock_t *match_clock,
555 intel_clock_t *best_clock)
79e53945
JB		 556{
557 struct drm_device *dev = crtc->dev;
79e53945 558 intel_clock_t clock;
79e53945
JB		 559 int err = target;
560
a210b028 561 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 562 /*
a210b028
DV		 563 * For LVDS just rely on its current settings for dual-channel.
564 * We haven't figured out how to reliably set up different
565 * single/dual channel state, if we even can.
79e53945 566 */
1974cad0 567 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 568 clock.p2 = limit->p2.p2_fast;
569 else
570 clock.p2 = limit->p2.p2_slow;
571 } else {
572 if (target < limit->p2.dot_limit)
573 clock.p2 = limit->p2.p2_slow;
574 else
575 clock.p2 = limit->p2.p2_fast;
576 }
577
0206e353 578 memset(best_clock, 0, sizeof(*best_clock));
79e53945 579
42158660
ZY		 580 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
581 clock.m1++) {
582 for (clock.m2 = limit->m2.min;
583 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 584 for (clock.n = limit->n.min;
585 clock.n <= limit->n.max; clock.n++) {
586 for (clock.p1 = limit->p1.min;
587 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 588 int this_err;
589
ac58c3f0 590 pineview_clock(refclk, &clock);
1b894b59
CW		 591 if (!intel_PLL_is_valid(dev, limit,
592 &clock))
79e53945 593 continue;
cec2f356
SP		 594 if (match_clock &&
595 clock.p != match_clock->p)
596 continue;
79e53945
JB		 597
598 this_err = abs(clock.dot - target);
599 if (this_err < err) {
600 *best_clock = clock;
601 err = this_err;
602 }
603 }
604 }
605 }
606 }
607
608 return (err != target);
609}
610
d4906093 611static bool
ee9300bb
DV		 612g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
613 int target, int refclk, intel_clock_t *match_clock,
614 intel_clock_t *best_clock)
d4906093
ML		 615{
616 struct drm_device *dev = crtc->dev;
d4906093
ML		 617 intel_clock_t clock;
618 int max_n;
619 bool found;
6ba770dc
AJ		 620 /* approximately equals target * 0.00585 */
621 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 622 found = false;
623
624 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 625 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 626 clock.p2 = limit->p2.p2_fast;
627 else
628 clock.p2 = limit->p2.p2_slow;
629 } else {
630 if (target < limit->p2.dot_limit)
631 clock.p2 = limit->p2.p2_slow;
632 else
633 clock.p2 = limit->p2.p2_fast;
634 }
635
636 memset(best_clock, 0, sizeof(*best_clock));
637 max_n = limit->n.max;
f77f13e2 638 /* based on hardware requirement, prefer smaller n to precision */
d4906093 639 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 640 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 641 for (clock.m1 = limit->m1.max;
642 clock.m1 >= limit->m1.min; clock.m1--) {
643 for (clock.m2 = limit->m2.max;
644 clock.m2 >= limit->m2.min; clock.m2--) {
645 for (clock.p1 = limit->p1.max;
646 clock.p1 >= limit->p1.min; clock.p1--) {
647 int this_err;
648
ac58c3f0 649 i9xx_clock(refclk, &clock);
1b894b59
CW		 650 if (!intel_PLL_is_valid(dev, limit,
651 &clock))
d4906093 652 continue;
1b894b59
CW		 653
654 this_err = abs(clock.dot - target);
d4906093
ML		 655 if (this_err < err_most) {
656 *best_clock = clock;
657 err_most = this_err;
658 max_n = clock.n;
659 found = true;
660 }
661 }
662 }
663 }
664 }
2c07245f
ZW		 665 return found;
666}
667
a0c4da24 668static bool
ee9300bb
DV		 669vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
670 int target, int refclk, intel_clock_t *match_clock,
671 intel_clock_t *best_clock)
a0c4da24
JB		 672{
673 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
674 u32 m, n, fastclk;
f3f08572 675 u32 updrate, minupdate, p;
a0c4da24
JB		 676 unsigned long bestppm, ppm, absppm;
677 int dotclk, flag;
678
af447bd3 679 flag = 0;
a0c4da24
JB		 680 dotclk = target * 1000;
681 bestppm = 1000000;
682 ppm = absppm = 0;
683 fastclk = dotclk / (2*100);
684 updrate = 0;
685 minupdate = 19200;
a0c4da24
JB		 686 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
687 bestm1 = bestm2 = bestp1 = bestp2 = 0;
688
689 /* based on hardware requirement, prefer smaller n to precision */
690 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
691 updrate = refclk / n;
692 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
693 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
694 if (p2 > 10)
695 p2 = p2 - 1;
696 p = p1 * p2;
697 /* based on hardware requirement, prefer bigger m1,m2 values */
698 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
699 m2 = (((2*(fastclk * p * n / m1 )) +
700 refclk) / (2*refclk));
701 m = m1 * m2;
702 vco = updrate * m;
703 if (vco >= limit->vco.min && vco < limit->vco.max) {
704 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
705 absppm = (ppm > 0) ? ppm : (-ppm);
706 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
707 bestppm = 0;
708 flag = 1;
709 }
710 if (absppm < bestppm - 10) {
711 bestppm = absppm;
712 flag = 1;
713 }
714 if (flag) {
715 bestn = n;
716 bestm1 = m1;
717 bestm2 = m2;
718 bestp1 = p1;
719 bestp2 = p2;
720 flag = 0;
721 }
722 }
723 }
724 }
725 }
726 }
727 best_clock->n = bestn;
728 best_clock->m1 = bestm1;
729 best_clock->m2 = bestm2;
730 best_clock->p1 = bestp1;
731 best_clock->p2 = bestp2;
732
733 return true;
734}
a4fc5ed6 735
20ddf665
VS		 736bool intel_crtc_active(struct drm_crtc *crtc)
737{
738 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
739
740 /* Be paranoid as we can arrive here with only partial
741 * state retrieved from the hardware during setup.
742 *
743 * We can ditch the adjusted_mode.clock check as soon
744 * as Haswell has gained clock readout/fastboot support.
745 *
746 * We can ditch the crtc->fb check as soon as we can
747 * properly reconstruct framebuffers.
748 */
749 return intel_crtc->active && crtc->fb &&
750 intel_crtc->config.adjusted_mode.clock;
751}
752
a5c961d1
PZ		 753enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
754 enum pipe pipe)
755{
756 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
757 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
758
3b117c8f 759 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 760}
761
a928d536
PZ		 762static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
763{
764 struct drm_i915_private *dev_priv = dev->dev_private;
765 u32 frame, frame_reg = PIPEFRAME(pipe);
766
767 frame = I915_READ(frame_reg);
768
769 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
770 DRM_DEBUG_KMS("vblank wait timed out\n");
771}
772
9d0498a2
JB		 773/**
774 * intel_wait_for_vblank - wait for vblank on a given pipe
775 * @dev: drm device
776 * @pipe: pipe to wait for
777 *
778 * Wait for vblank to occur on a given pipe. Needed for various bits of
779 * mode setting code.
780 */
781void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 782{
9d0498a2 783 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 784 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 785
a928d536
PZ		 786 if (INTEL_INFO(dev)->gen >= 5) {
787 ironlake_wait_for_vblank(dev, pipe);
788 return;
789 }
790
300387c0
CW		 791 /* Clear existing vblank status. Note this will clear any other
792 * sticky status fields as well.
793 *
794 * This races with i915_driver_irq_handler() with the result
795 * that either function could miss a vblank event. Here it is not
796 * fatal, as we will either wait upon the next vblank interrupt or
797 * timeout. Generally speaking intel_wait_for_vblank() is only
798 * called during modeset at which time the GPU should be idle and
799 * should *not* be performing page flips and thus not waiting on
800 * vblanks...
801 * Currently, the result of us stealing a vblank from the irq
802 * handler is that a single frame will be skipped during swapbuffers.
803 */
804 I915_WRITE(pipestat_reg,
805 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
806
9d0498a2 807 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 808 if (wait_for(I915_READ(pipestat_reg) &
809 PIPE_VBLANK_INTERRUPT_STATUS,
810 50))
9d0498a2
JB		 811 DRM_DEBUG_KMS("vblank wait timed out\n");
812}
813
ab7ad7f6
KP		 814/*
815 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 816 * @dev: drm device
817 * @pipe: pipe to wait for
818 *
819 * After disabling a pipe, we can't wait for vblank in the usual way,
820 * spinning on the vblank interrupt status bit, since we won't actually
821 * see an interrupt when the pipe is disabled.
822 *
ab7ad7f6
KP		 823 * On Gen4 and above:
824 * wait for the pipe register state bit to turn off
825 *
826 * Otherwise:
827 * wait for the display line value to settle (it usually
828 * ends up stopping at the start of the next frame).
58e10eb9 829 *
9d0498a2 830 */
58e10eb9 831void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 832{
833 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 834 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
835 pipe);
ab7ad7f6
KP		 836
837 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 838 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 839
840 /* Wait for the Pipe State to go off */
58e10eb9
CW		 841 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
842 100))
284637d9 843 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 844 } else {
837ba00f 845 u32 last_line, line_mask;
58e10eb9 846 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 847 unsigned long timeout = jiffies + msecs_to_jiffies(100);
848
837ba00f
PZ		 849 if (IS_GEN2(dev))
850 line_mask = DSL_LINEMASK_GEN2;
851 else
852 line_mask = DSL_LINEMASK_GEN3;
853
ab7ad7f6
KP		 854 /* Wait for the display line to settle */
855 do {
837ba00f 856 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 857 mdelay(5);
837ba00f 858 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 859 time_after(timeout, jiffies));
860 if (time_after(jiffies, timeout))
284637d9 861 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 862 }
79e53945
JB		 863}
864
b0ea7d37
DL		 865/*
866 * ibx_digital_port_connected - is the specified port connected?
867 * @dev_priv: i915 private structure
868 * @port: the port to test
869 *
870 * Returns true if @port is connected, false otherwise.
871 */
872bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
873 struct intel_digital_port *port)
874{
875 u32 bit;
876
c36346e3
DL		 877 if (HAS_PCH_IBX(dev_priv->dev)) {
878 switch(port->port) {
879 case PORT_B:
880 bit = SDE_PORTB_HOTPLUG;
881 break;
882 case PORT_C:
883 bit = SDE_PORTC_HOTPLUG;
884 break;
885 case PORT_D:
886 bit = SDE_PORTD_HOTPLUG;
887 break;
888 default:
889 return true;
890 }
891 } else {
892 switch(port->port) {
893 case PORT_B:
894 bit = SDE_PORTB_HOTPLUG_CPT;
895 break;
896 case PORT_C:
897 bit = SDE_PORTC_HOTPLUG_CPT;
898 break;
899 case PORT_D:
900 bit = SDE_PORTD_HOTPLUG_CPT;
901 break;
902 default:
903 return true;
904 }
b0ea7d37
DL		 905 }
906
907 return I915_READ(SDEISR) & bit;
908}
909
b24e7179
JB		 910static const char *state_string(bool enabled)
911{
912 return enabled ? "on" : "off";
913}
914
915/* Only for pre-ILK configs */
55607e8a
DV		 916void assert_pll(struct drm_i915_private *dev_priv,
917 enum pipe pipe, bool state)
b24e7179
JB		 918{
919 int reg;
920 u32 val;
921 bool cur_state;
922
923 reg = DPLL(pipe);
924 val = I915_READ(reg);
925 cur_state = !!(val & DPLL_VCO_ENABLE);
926 WARN(cur_state != state,
927 "PLL state assertion failure (expected %s, current %s)\n",
928 state_string(state), state_string(cur_state));
929}
b24e7179 930
23538ef1
JN		 931/* XXX: the dsi pll is shared between MIPI DSI ports */
932static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
933{
934 u32 val;
935 bool cur_state;
936
937 mutex_lock(&dev_priv->dpio_lock);
938 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
939 mutex_unlock(&dev_priv->dpio_lock);
940
941 cur_state = val & DSI_PLL_VCO_EN;
942 WARN(cur_state != state,
943 "DSI PLL state assertion failure (expected %s, current %s)\n",
944 state_string(state), state_string(cur_state));
945}
946#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
947#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
948
55607e8a 949struct intel_shared_dpll *
e2b78267
DV		 950intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
951{
952 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
953
a43f6e0f 954 if (crtc->config.shared_dpll < 0)
e2b78267
DV		 955 return NULL;
956
a43f6e0f 957 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
e2b78267
DV		 958}
959
040484af 960/* For ILK+ */
55607e8a
DV		 961void assert_shared_dpll(struct drm_i915_private *dev_priv,
962 struct intel_shared_dpll *pll,
963 bool state)
040484af 964{
040484af 965 bool cur_state;
5358901f 966 struct intel_dpll_hw_state hw_state;
040484af 967
9d82aa17
ED		 968 if (HAS_PCH_LPT(dev_priv->dev)) {
969 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
970 return;
971 }
972
92b27b08 973 if (WARN (!pll,
46edb027 974 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 975 return;
ee7b9f93 976
5358901f 977 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
92b27b08 978 WARN(cur_state != state,
5358901f
DV		 979 "%s assertion failure (expected %s, current %s)\n",
980 pll->name, state_string(state), state_string(cur_state));
040484af 981}
040484af
JB		 982
983static void assert_fdi_tx(struct drm_i915_private *dev_priv,
984 enum pipe pipe, bool state)
985{
986 int reg;
987 u32 val;
988 bool cur_state;
ad80a810
PZ		 989 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
990 pipe);
040484af 991
affa9354
PZ		 992 if (HAS_DDI(dev_priv->dev)) {
993 /* DDI does not have a specific FDI_TX register */
ad80a810 994 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 995 val = I915_READ(reg);
ad80a810 996 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 997 } else {
998 reg = FDI_TX_CTL(pipe);
999 val = I915_READ(reg);
1000 cur_state = !!(val & FDI_TX_ENABLE);
1001 }
040484af
JB		 1002 WARN(cur_state != state,
1003 "FDI TX state assertion failure (expected %s, current %s)\n",
1004 state_string(state), state_string(cur_state));
1005}
1006#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1007#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1008
1009static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1010 enum pipe pipe, bool state)
1011{
1012 int reg;
1013 u32 val;
1014 bool cur_state;
1015
d63fa0dc
PZ		 1016 reg = FDI_RX_CTL(pipe);
1017 val = I915_READ(reg);
1018 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1019 WARN(cur_state != state,
1020 "FDI RX state assertion failure (expected %s, current %s)\n",
1021 state_string(state), state_string(cur_state));
1022}
1023#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1024#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1025
1026static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1027 enum pipe pipe)
1028{
1029 int reg;
1030 u32 val;
1031
1032 /* ILK FDI PLL is always enabled */
1033 if (dev_priv->info->gen == 5)
1034 return;
1035
bf507ef7 1036 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1037 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1038 return;
1039
040484af
JB		 1040 reg = FDI_TX_CTL(pipe);
1041 val = I915_READ(reg);
1042 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1043}
1044
55607e8a
DV		 1045void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1046 enum pipe pipe, bool state)
040484af
JB		 1047{
1048 int reg;
1049 u32 val;
55607e8a 1050 bool cur_state;
040484af
JB		 1051
1052 reg = FDI_RX_CTL(pipe);
1053 val = I915_READ(reg);
55607e8a
DV		 1054 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1055 WARN(cur_state != state,
1056 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1057 state_string(state), state_string(cur_state));
040484af
JB		 1058}
1059
ea0760cf
JB		 1060static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1061 enum pipe pipe)
1062{
1063 int pp_reg, lvds_reg;
1064 u32 val;
1065 enum pipe panel_pipe = PIPE_A;
0de3b485 1066 bool locked = true;
ea0760cf
JB		 1067
1068 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1069 pp_reg = PCH_PP_CONTROL;
1070 lvds_reg = PCH_LVDS;
1071 } else {
1072 pp_reg = PP_CONTROL;
1073 lvds_reg = LVDS;
1074 }
1075
1076 val = I915_READ(pp_reg);
1077 if (!(val & PANEL_POWER_ON) ||
1078 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1079 locked = false;
1080
1081 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1082 panel_pipe = PIPE_B;
1083
1084 WARN(panel_pipe == pipe && locked,
1085 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1086 pipe_name(pipe));
ea0760cf
JB		 1087}
1088
93ce0ba6
JN		 1089static void assert_cursor(struct drm_i915_private *dev_priv,
1090 enum pipe pipe, bool state)
1091{
1092 struct drm_device *dev = dev_priv->dev;
1093 bool cur_state;
1094
1095 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1096 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1097 else if (IS_845G(dev) || IS_I865G(dev))
1098 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1099 else
1100 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1101
1102 WARN(cur_state != state,
1103 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1104 pipe_name(pipe), state_string(state), state_string(cur_state));
1105}
1106#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1107#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1108
b840d907
JB		 1109void assert_pipe(struct drm_i915_private *dev_priv,
1110 enum pipe pipe, bool state)
b24e7179
JB		 1111{
1112 int reg;
1113 u32 val;
63d7bbe9 1114 bool cur_state;
702e7a56
PZ		 1115 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1116 pipe);
b24e7179 1117
8e636784
DV		 1118 /* if we need the pipe A quirk it must be always on */
1119 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1120 state = true;
1121
b97186f0
PZ		 1122 if (!intel_display_power_enabled(dev_priv->dev,
1123 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1124 cur_state = false;
1125 } else {
1126 reg = PIPECONF(cpu_transcoder);
1127 val = I915_READ(reg);
1128 cur_state = !!(val & PIPECONF_ENABLE);
1129 }
1130
63d7bbe9
JB		 1131 WARN(cur_state != state,
1132 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1133 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1134}
1135
931872fc
CW		 1136static void assert_plane(struct drm_i915_private *dev_priv,
1137 enum plane plane, bool state)
b24e7179
JB		 1138{
1139 int reg;
1140 u32 val;
931872fc 1141 bool cur_state;
b24e7179
JB		 1142
1143 reg = DSPCNTR(plane);
1144 val = I915_READ(reg);
931872fc
CW		 1145 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1146 WARN(cur_state != state,
1147 "plane %c assertion failure (expected %s, current %s)\n",
1148 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1149}
1150
931872fc
CW		 1151#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1152#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1153
b24e7179
JB		 1154static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1155 enum pipe pipe)
1156{
653e1026 1157 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1158 int reg, i;
1159 u32 val;
1160 int cur_pipe;
1161
653e1026
VS		 1162 /* Primary planes are fixed to pipes on gen4+ */
1163 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1164 reg = DSPCNTR(pipe);
1165 val = I915_READ(reg);
1166 WARN((val & DISPLAY_PLANE_ENABLE),
1167 "plane %c assertion failure, should be disabled but not\n",
1168 plane_name(pipe));
19ec1358 1169 return;
28c05794 1170 }
19ec1358 1171
b24e7179 1172 /* Need to check both planes against the pipe */
08e2a7de 1173 for_each_pipe(i) {
b24e7179
JB		 1174 reg = DSPCNTR(i);
1175 val = I915_READ(reg);
1176 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1177 DISPPLANE_SEL_PIPE_SHIFT;
1178 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1179 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1180 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1181 }
1182}
1183
19332d7a
JB		 1184static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1185 enum pipe pipe)
1186{
20674eef 1187 struct drm_device *dev = dev_priv->dev;
19332d7a
JB		 1188 int reg, i;
1189 u32 val;
1190
20674eef
VS		 1191 if (IS_VALLEYVIEW(dev)) {
1192 for (i = 0; i < dev_priv->num_plane; i++) {
1193 reg = SPCNTR(pipe, i);
1194 val = I915_READ(reg);
1195 WARN((val & SP_ENABLE),
1196 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1197 sprite_name(pipe, i), pipe_name(pipe));
1198 }
1199 } else if (INTEL_INFO(dev)->gen >= 7) {
1200 reg = SPRCTL(pipe);
19332d7a 1201 val = I915_READ(reg);
20674eef 1202 WARN((val & SPRITE_ENABLE),
06da8da2 1203 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1204 plane_name(pipe), pipe_name(pipe));
1205 } else if (INTEL_INFO(dev)->gen >= 5) {
1206 reg = DVSCNTR(pipe);
19332d7a 1207 val = I915_READ(reg);
20674eef 1208 WARN((val & DVS_ENABLE),
06da8da2 1209 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1210 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1211 }
1212}
1213
92f2584a
JB		 1214static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1215{
1216 u32 val;
1217 bool enabled;
1218
9d82aa17
ED		 1219 if (HAS_PCH_LPT(dev_priv->dev)) {
1220 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1221 return;
1222 }
1223
92f2584a
JB		 1224 val = I915_READ(PCH_DREF_CONTROL);
1225 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1226 DREF_SUPERSPREAD_SOURCE_MASK));
1227 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1228}
1229
ab9412ba
DV		 1230static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1231 enum pipe pipe)
92f2584a
JB		 1232{
1233 int reg;
1234 u32 val;
1235 bool enabled;
1236
ab9412ba 1237 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1238 val = I915_READ(reg);
1239 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1240 WARN(enabled,
1241 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1242 pipe_name(pipe));
92f2584a
JB		 1243}
1244
4e634389
KP		 1245static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1246 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1247{
1248 if ((val & DP_PORT_EN) == 0)
1249 return false;
1250
1251 if (HAS_PCH_CPT(dev_priv->dev)) {
1252 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1253 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1254 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1255 return false;
1256 } else {
1257 if ((val & DP_PIPE_MASK) != (pipe << 30))
1258 return false;
1259 }
1260 return true;
1261}
1262
1519b995
KP		 1263static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1264 enum pipe pipe, u32 val)
1265{
dc0fa718 1266 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1267 return false;
1268
1269 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1270 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1271 return false;
1272 } else {
dc0fa718 1273 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1274 return false;
1275 }
1276 return true;
1277}
1278
1279static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1280 enum pipe pipe, u32 val)
1281{
1282 if ((val & LVDS_PORT_EN) == 0)
1283 return false;
1284
1285 if (HAS_PCH_CPT(dev_priv->dev)) {
1286 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1287 return false;
1288 } else {
1289 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1290 return false;
1291 }
1292 return true;
1293}
1294
1295static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1296 enum pipe pipe, u32 val)
1297{
1298 if ((val & ADPA_DAC_ENABLE) == 0)
1299 return false;
1300 if (HAS_PCH_CPT(dev_priv->dev)) {
1301 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1302 return false;
1303 } else {
1304 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1305 return false;
1306 }
1307 return true;
1308}
1309
291906f1 1310static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1311 enum pipe pipe, int reg, u32 port_sel)
291906f1 1312{
47a05eca 1313 u32 val = I915_READ(reg);
4e634389 1314 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1315 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1316 reg, pipe_name(pipe));
de9a35ab 1317
75c5da27
DV		 1318 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1319 && (val & DP_PIPEB_SELECT),
de9a35ab 1320 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1321}
1322
1323static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1324 enum pipe pipe, int reg)
1325{
47a05eca 1326 u32 val = I915_READ(reg);
b70ad586 1327 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1328 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1329 reg, pipe_name(pipe));
de9a35ab 1330
dc0fa718 1331 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1332 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1333 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1334}
1335
1336static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1337 enum pipe pipe)
1338{
1339 int reg;
1340 u32 val;
291906f1 1341
f0575e92
KP		 1342 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1343 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1344 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1345
1346 reg = PCH_ADPA;
1347 val = I915_READ(reg);
b70ad586 1348 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1349 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1350 pipe_name(pipe));
291906f1
JB		 1351
1352 reg = PCH_LVDS;
1353 val = I915_READ(reg);
b70ad586 1354 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1355 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1356 pipe_name(pipe));
291906f1 1357
e2debe91
PZ		 1358 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1359 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1360 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1361}
1362
426115cf 1363static void vlv_enable_pll(struct intel_crtc *crtc)
87442f73 1364{
426115cf
DV		 1365 struct drm_device *dev = crtc->base.dev;
1366 struct drm_i915_private *dev_priv = dev->dev_private;
1367 int reg = DPLL(crtc->pipe);
1368 u32 dpll = crtc->config.dpll_hw_state.dpll;
87442f73 1369
426115cf 1370 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1371
1372 /* No really, not for ILK+ */
1373 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1374
1375 /* PLL is protected by panel, make sure we can write it */
1376 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
426115cf 1377 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1378
426115cf
DV		 1379 I915_WRITE(reg, dpll);
1380 POSTING_READ(reg);
1381 udelay(150);
1382
1383 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1384 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1385
1386 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1387 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1388
1389 /* We do this three times for luck */
426115cf 1390 I915_WRITE(reg, dpll);
87442f73
DV		 1391 POSTING_READ(reg);
1392 udelay(150); /* wait for warmup */
426115cf 1393 I915_WRITE(reg, dpll);
87442f73
DV		 1394 POSTING_READ(reg);
1395 udelay(150); /* wait for warmup */
426115cf 1396 I915_WRITE(reg, dpll);
87442f73
DV		 1397 POSTING_READ(reg);
1398 udelay(150); /* wait for warmup */
1399}
1400
66e3d5c0 1401static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1402{
66e3d5c0
DV		 1403 struct drm_device *dev = crtc->base.dev;
1404 struct drm_i915_private *dev_priv = dev->dev_private;
1405 int reg = DPLL(crtc->pipe);
1406 u32 dpll = crtc->config.dpll_hw_state.dpll;
63d7bbe9 1407
66e3d5c0 1408 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1409
63d7bbe9 1410 /* No really, not for ILK+ */
87442f73 1411 BUG_ON(dev_priv->info->gen >= 5);
63d7bbe9
JB		 1412
1413 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1414 if (IS_MOBILE(dev) && !IS_I830(dev))
1415 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1416
66e3d5c0
DV		 1417 I915_WRITE(reg, dpll);
1418
1419 /* Wait for the clocks to stabilize. */
1420 POSTING_READ(reg);
1421 udelay(150);
1422
1423 if (INTEL_INFO(dev)->gen >= 4) {
1424 I915_WRITE(DPLL_MD(crtc->pipe),
1425 crtc->config.dpll_hw_state.dpll_md);
1426 } else {
1427 /* The pixel multiplier can only be updated once the
1428 * DPLL is enabled and the clocks are stable.
1429 *
1430 * So write it again.
1431 */
1432 I915_WRITE(reg, dpll);
1433 }
63d7bbe9
JB		 1434
1435 /* We do this three times for luck */
66e3d5c0 1436 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1437 POSTING_READ(reg);
1438 udelay(150); /* wait for warmup */
66e3d5c0 1439 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1440 POSTING_READ(reg);
1441 udelay(150); /* wait for warmup */
66e3d5c0 1442 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1443 POSTING_READ(reg);
1444 udelay(150); /* wait for warmup */
1445}
1446
1447/**
50b44a44 1448 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1449 * @dev_priv: i915 private structure
1450 * @pipe: pipe PLL to disable
1451 *
1452 * Disable the PLL for @pipe, making sure the pipe is off first.
1453 *
1454 * Note! This is for pre-ILK only.
1455 */
50b44a44 1456static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
63d7bbe9 1457{
63d7bbe9
JB		 1458 /* Don't disable pipe A or pipe A PLLs if needed */
1459 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1460 return;
1461
1462 /* Make sure the pipe isn't still relying on us */
1463 assert_pipe_disabled(dev_priv, pipe);
1464
50b44a44
DV		 1465 I915_WRITE(DPLL(pipe), 0);
1466 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1467}
1468
89b667f8
JB		 1469void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1470{
1471 u32 port_mask;
1472
1473 if (!port)
1474 port_mask = DPLL_PORTB_READY_MASK;
1475 else
1476 port_mask = DPLL_PORTC_READY_MASK;
1477
1478 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1479 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1480 'B' + port, I915_READ(DPLL(0)));
1481}
1482
92f2584a 1483/**
e72f9fbf 1484 * ironlake_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1485 * @dev_priv: i915 private structure
1486 * @pipe: pipe PLL to enable
1487 *
1488 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1489 * drives the transcoder clock.
1490 */
e2b78267 1491static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1492{
e2b78267
DV		 1493 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1494 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1495
48da64a8 1496 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1497 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1498 if (WARN_ON(pll == NULL))
48da64a8
CW		 1499 return;
1500
1501 if (WARN_ON(pll->refcount == 0))
1502 return;
ee7b9f93 1503
46edb027
DV		 1504 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1505 pll->name, pll->active, pll->on,
e2b78267 1506 crtc->base.base.id);
92f2584a 1507
cdbd2316
DV		 1508 if (pll->active++) {
1509 WARN_ON(!pll->on);
e9d6944e 1510 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1511 return;
1512 }
f4a091c7 1513 WARN_ON(pll->on);
ee7b9f93 1514
46edb027 1515 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1516 pll->enable(dev_priv, pll);
ee7b9f93 1517 pll->on = true;
92f2584a
JB		 1518}
1519
e2b78267 1520static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1521{
e2b78267
DV		 1522 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1523 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1524
92f2584a
JB		 1525 /* PCH only available on ILK+ */
1526 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1527 if (WARN_ON(pll == NULL))
ee7b9f93 1528 return;
92f2584a 1529
48da64a8
CW		 1530 if (WARN_ON(pll->refcount == 0))
1531 return;
7a419866 1532
46edb027
DV		 1533 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1534 pll->name, pll->active, pll->on,
e2b78267 1535 crtc->base.base.id);
7a419866 1536
48da64a8 1537 if (WARN_ON(pll->active == 0)) {
e9d6944e 1538 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1539 return;
1540 }
1541
e9d6944e 1542 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1543 WARN_ON(!pll->on);
cdbd2316 1544 if (--pll->active)
7a419866 1545 return;
ee7b9f93 1546
46edb027 1547 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1548 pll->disable(dev_priv, pll);
ee7b9f93 1549 pll->on = false;
92f2584a
JB		 1550}
1551
b8a4f404
PZ		 1552static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1553 enum pipe pipe)
040484af 1554{
23670b32 1555 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1556 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1557 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1558 uint32_t reg, val, pipeconf_val;
040484af
JB		 1559
1560 /* PCH only available on ILK+ */
1561 BUG_ON(dev_priv->info->gen < 5);
1562
1563 /* Make sure PCH DPLL is enabled */
e72f9fbf 1564 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1565 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1566
1567 /* FDI must be feeding us bits for PCH ports */
1568 assert_fdi_tx_enabled(dev_priv, pipe);
1569 assert_fdi_rx_enabled(dev_priv, pipe);
1570
23670b32
DV		 1571 if (HAS_PCH_CPT(dev)) {
1572 /* Workaround: Set the timing override bit before enabling the
1573 * pch transcoder. */
1574 reg = TRANS_CHICKEN2(pipe);
1575 val = I915_READ(reg);
1576 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1577 I915_WRITE(reg, val);
59c859d6 1578 }
23670b32 1579
ab9412ba 1580 reg = PCH_TRANSCONF(pipe);
040484af 1581 val = I915_READ(reg);
5f7f726d 1582 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1583
1584 if (HAS_PCH_IBX(dev_priv->dev)) {
1585 /*
1586 * make the BPC in transcoder be consistent with
1587 * that in pipeconf reg.
1588 */
dfd07d72
DV		 1589 val &= ~PIPECONF_BPC_MASK;
1590 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1591 }
5f7f726d
PZ		 1592
1593 val &= ~TRANS_INTERLACE_MASK;
1594 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1595 if (HAS_PCH_IBX(dev_priv->dev) &&
1596 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1597 val |= TRANS_LEGACY_INTERLACED_ILK;
1598 else
1599 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1600 else
1601 val |= TRANS_PROGRESSIVE;
1602
040484af
JB		 1603 I915_WRITE(reg, val | TRANS_ENABLE);
1604 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1605 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1606}
1607
8fb033d7 1608static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1609 enum transcoder cpu_transcoder)
040484af 1610{
8fb033d7 1611 u32 val, pipeconf_val;
8fb033d7
PZ		 1612
1613 /* PCH only available on ILK+ */
1614 BUG_ON(dev_priv->info->gen < 5);
1615
8fb033d7 1616 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1617 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1618 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1619
223a6fdf
PZ		 1620 /* Workaround: set timing override bit. */
1621 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1622 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1623 I915_WRITE(_TRANSA_CHICKEN2, val);
1624
25f3ef11 1625 val = TRANS_ENABLE;
937bb610 1626 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1627
9a76b1c6
PZ		 1628 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1629 PIPECONF_INTERLACED_ILK)
a35f2679 1630 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1631 else
1632 val |= TRANS_PROGRESSIVE;
1633
ab9412ba
DV		 1634 I915_WRITE(LPT_TRANSCONF, val);
1635 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 1636 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1637}
1638
b8a4f404
PZ		 1639static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1640 enum pipe pipe)
040484af 1641{
23670b32
DV		 1642 struct drm_device *dev = dev_priv->dev;
1643 uint32_t reg, val;
040484af
JB		 1644
1645 /* FDI relies on the transcoder */
1646 assert_fdi_tx_disabled(dev_priv, pipe);
1647 assert_fdi_rx_disabled(dev_priv, pipe);
1648
291906f1
JB		 1649 /* Ports must be off as well */
1650 assert_pch_ports_disabled(dev_priv, pipe);
1651
ab9412ba 1652 reg = PCH_TRANSCONF(pipe);
040484af
JB		 1653 val = I915_READ(reg);
1654 val &= ~TRANS_ENABLE;
1655 I915_WRITE(reg, val);
1656 /* wait for PCH transcoder off, transcoder state */
1657 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1658 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1659
1660 if (!HAS_PCH_IBX(dev)) {
1661 /* Workaround: Clear the timing override chicken bit again. */
1662 reg = TRANS_CHICKEN2(pipe);
1663 val = I915_READ(reg);
1664 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1665 I915_WRITE(reg, val);
1666 }
040484af
JB		 1667}
1668
ab4d966c 1669static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1670{
8fb033d7
PZ		 1671 u32 val;
1672
ab9412ba 1673 val = I915_READ(LPT_TRANSCONF);
8fb033d7 1674 val &= ~TRANS_ENABLE;
ab9412ba 1675 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 1676 /* wait for PCH transcoder off, transcoder state */
ab9412ba 1677 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 1678 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1679
1680 /* Workaround: clear timing override bit. */
1681 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1682 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1683 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1684}
1685
b24e7179 1686/**
309cfea8 1687 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1688 * @dev_priv: i915 private structure
1689 * @pipe: pipe to enable
040484af 1690 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1691 *
1692 * Enable @pipe, making sure that various hardware specific requirements
1693 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1694 *
1695 * @pipe should be %PIPE_A or %PIPE_B.
1696 *
1697 * Will wait until the pipe is actually running (i.e. first vblank) before
1698 * returning.
1699 */
040484af 1700static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
23538ef1 1701 bool pch_port, bool dsi)
b24e7179 1702{
702e7a56
PZ		 1703 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1704 pipe);
1a240d4d 1705 enum pipe pch_transcoder;
b24e7179
JB		 1706 int reg;
1707 u32 val;
1708
58c6eaa2 1709 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 1710 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 1711 assert_sprites_disabled(dev_priv, pipe);
1712
681e5811 1713 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1714 pch_transcoder = TRANSCODER_A;
1715 else
1716 pch_transcoder = pipe;
1717
b24e7179
JB		 1718 /*
1719 * A pipe without a PLL won't actually be able to drive bits from
1720 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1721 * need the check.
1722 */
1723 if (!HAS_PCH_SPLIT(dev_priv->dev))
23538ef1
JN		 1724 if (dsi)
1725 assert_dsi_pll_enabled(dev_priv);
1726 else
1727 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1728 else {
1729 if (pch_port) {
1730 /* if driving the PCH, we need FDI enabled */
cc391bbb 1731 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1732 assert_fdi_tx_pll_enabled(dev_priv,
1733 (enum pipe) cpu_transcoder);
040484af
JB		 1734 }
1735 /* FIXME: assert CPU port conditions for SNB+ */
1736 }
b24e7179 1737
702e7a56 1738 reg = PIPECONF(cpu_transcoder);
b24e7179 1739 val = I915_READ(reg);
00d70b15
CW		 1740 if (val & PIPECONF_ENABLE)
1741 return;
1742
1743 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1744 intel_wait_for_vblank(dev_priv->dev, pipe);
1745}
1746
1747/**
309cfea8 1748 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1749 * @dev_priv: i915 private structure
1750 * @pipe: pipe to disable
1751 *
1752 * Disable @pipe, making sure that various hardware specific requirements
1753 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1754 *
1755 * @pipe should be %PIPE_A or %PIPE_B.
1756 *
1757 * Will wait until the pipe has shut down before returning.
1758 */
1759static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1760 enum pipe pipe)
1761{
702e7a56
PZ		 1762 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1763 pipe);
b24e7179
JB		 1764 int reg;
1765 u32 val;
1766
1767 /*
1768 * Make sure planes won't keep trying to pump pixels to us,
1769 * or we might hang the display.
1770 */
1771 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 1772 assert_cursor_disabled(dev_priv, pipe);
19332d7a 1773 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1774
1775 /* Don't disable pipe A or pipe A PLLs if needed */
1776 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1777 return;
1778
702e7a56 1779 reg = PIPECONF(cpu_transcoder);
b24e7179 1780 val = I915_READ(reg);
00d70b15
CW		 1781 if ((val & PIPECONF_ENABLE) == 0)
1782 return;
1783
1784 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1785 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1786}
1787
d74362c9
KP		 1788/*
1789 * Plane regs are double buffered, going from enabled->disabled needs a
1790 * trigger in order to latch. The display address reg provides this.
1791 */
6f1d69b0 1792void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1793 enum plane plane)
1794{
14f86147
DL		 1795 if (dev_priv->info->gen >= 4)
1796 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1797 else
1798 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1799}
1800
b24e7179
JB		 1801/**
1802 * intel_enable_plane - enable a display plane on a given pipe
1803 * @dev_priv: i915 private structure
1804 * @plane: plane to enable
1805 * @pipe: pipe being fed
1806 *
1807 * Enable @plane on @pipe, making sure that @pipe is running first.
1808 */
1809static void intel_enable_plane(struct drm_i915_private *dev_priv,
1810 enum plane plane, enum pipe pipe)
1811{
1812 int reg;
1813 u32 val;
1814
1815 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1816 assert_pipe_enabled(dev_priv, pipe);
1817
1818 reg = DSPCNTR(plane);
1819 val = I915_READ(reg);
00d70b15
CW		 1820 if (val & DISPLAY_PLANE_ENABLE)
1821 return;
1822
1823 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1824 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1825 intel_wait_for_vblank(dev_priv->dev, pipe);
1826}
1827
b24e7179
JB		 1828/**
1829 * intel_disable_plane - disable a display plane
1830 * @dev_priv: i915 private structure
1831 * @plane: plane to disable
1832 * @pipe: pipe consuming the data
1833 *
1834 * Disable @plane; should be an independent operation.
1835 */
1836static void intel_disable_plane(struct drm_i915_private *dev_priv,
1837 enum plane plane, enum pipe pipe)
1838{
1839 int reg;
1840 u32 val;
1841
1842 reg = DSPCNTR(plane);
1843 val = I915_READ(reg);
00d70b15
CW		 1844 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1845 return;
1846
1847 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1848 intel_flush_display_plane(dev_priv, plane);
1849 intel_wait_for_vblank(dev_priv->dev, pipe);
1850}
1851
693db184
CW		 1852static bool need_vtd_wa(struct drm_device *dev)
1853{
1854#ifdef CONFIG_INTEL_IOMMU
1855 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1856 return true;
1857#endif
1858 return false;
1859}
1860
127bd2ac 1861int
48b956c5 1862intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1863 struct drm_i915_gem_object *obj,
919926ae 1864 struct intel_ring_buffer *pipelined)
6b95a207 1865{
ce453d81 1866 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1867 u32 alignment;
1868 int ret;
1869
05394f39 1870 switch (obj->tiling_mode) {
6b95a207 1871 case I915_TILING_NONE:
534843da
CW		 1872 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1873 alignment = 128 * 1024;
a6c45cf0 1874 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1875 alignment = 4 * 1024;
1876 else
1877 alignment = 64 * 1024;
6b95a207
KH		 1878 break;
1879 case I915_TILING_X:
1880 /* pin() will align the object as required by fence */
1881 alignment = 0;
1882 break;
1883 case I915_TILING_Y:
8bb6e959
DV		 1884 /* Despite that we check this in framebuffer_init userspace can
1885 * screw us over and change the tiling after the fact. Only
1886 * pinned buffers can't change their tiling. */
1887 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH		 1888 return -EINVAL;
1889 default:
1890 BUG();
1891 }
1892
693db184
CW		 1893 /* Note that the w/a also requires 64 PTE of padding following the
1894 * bo. We currently fill all unused PTE with the shadow page and so
1895 * we should always have valid PTE following the scanout preventing
1896 * the VT-d warning.
1897 */
1898 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1899 alignment = 256 * 1024;
1900
ce453d81 1901 dev_priv->mm.interruptible = false;
2da3b9b9 1902 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1903 if (ret)
ce453d81 1904 goto err_interruptible;
6b95a207
KH		 1905
1906 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1907 * fence, whereas 965+ only requires a fence if using
1908 * framebuffer compression. For simplicity, we always install
1909 * a fence as the cost is not that onerous.
1910 */
06d98131 1911 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1912 if (ret)
1913 goto err_unpin;
1690e1eb 1914
9a5a53b3 1915 i915_gem_object_pin_fence(obj);
6b95a207 1916
ce453d81 1917 dev_priv->mm.interruptible = true;
6b95a207 1918 return 0;
48b956c5
CW		 1919
1920err_unpin:
cc98b413 1921 i915_gem_object_unpin_from_display_plane(obj);
ce453d81
CW		 1922err_interruptible:
1923 dev_priv->mm.interruptible = true;
48b956c5 1924 return ret;
6b95a207
KH		 1925}
1926
1690e1eb
CW		 1927void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1928{
1929 i915_gem_object_unpin_fence(obj);
cc98b413 1930 i915_gem_object_unpin_from_display_plane(obj);
1690e1eb
CW		 1931}
1932
c2c75131
DV		 1933/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1934 * is assumed to be a power-of-two. */
bc752862
CW		 1935unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1936 unsigned int tiling_mode,
1937 unsigned int cpp,
1938 unsigned int pitch)
c2c75131 1939{
bc752862
CW		 1940 if (tiling_mode != I915_TILING_NONE) {
1941 unsigned int tile_rows, tiles;
c2c75131 1942
bc752862
CW		 1943 tile_rows = *y / 8;
1944 *y %= 8;
c2c75131 1945
bc752862
CW		 1946 tiles = *x / (512/cpp);
1947 *x %= 512/cpp;
1948
1949 return tile_rows * pitch * 8 + tiles * 4096;
1950 } else {
1951 unsigned int offset;
1952
1953 offset = *y * pitch + *x * cpp;
1954 *y = 0;
1955 *x = (offset & 4095) / cpp;
1956 return offset & -4096;
1957 }
c2c75131
DV		 1958}
1959
17638cd6
JB		 1960static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1961 int x, int y)
81255565
JB		 1962{
1963 struct drm_device *dev = crtc->dev;
1964 struct drm_i915_private *dev_priv = dev->dev_private;
1965 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1966 struct intel_framebuffer *intel_fb;
05394f39 1967 struct drm_i915_gem_object *obj;
81255565 1968 int plane = intel_crtc->plane;
e506a0c6 1969 unsigned long linear_offset;
81255565 1970 u32 dspcntr;
5eddb70b 1971 u32 reg;
81255565
JB		 1972
1973 switch (plane) {
1974 case 0:
1975 case 1:
1976 break;
1977 default:
84f44ce7 1978 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 1979 return -EINVAL;
1980 }
1981
1982 intel_fb = to_intel_framebuffer(fb);
1983 obj = intel_fb->obj;
81255565 1984
5eddb70b
CW		 1985 reg = DSPCNTR(plane);
1986 dspcntr = I915_READ(reg);
81255565
JB		 1987 /* Mask out pixel format bits in case we change it */
1988 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 1989 switch (fb->pixel_format) {
1990 case DRM_FORMAT_C8:
81255565
JB		 1991 dspcntr |= DISPPLANE_8BPP;
1992 break;
57779d06
VS		 1993 case DRM_FORMAT_XRGB1555:
1994 case DRM_FORMAT_ARGB1555:
1995 dspcntr |= DISPPLANE_BGRX555;
81255565 1996 break;
57779d06
VS		 1997 case DRM_FORMAT_RGB565:
1998 dspcntr |= DISPPLANE_BGRX565;
1999 break;
2000 case DRM_FORMAT_XRGB8888:
2001 case DRM_FORMAT_ARGB8888:
2002 dspcntr |= DISPPLANE_BGRX888;
2003 break;
2004 case DRM_FORMAT_XBGR8888:
2005 case DRM_FORMAT_ABGR8888:
2006 dspcntr |= DISPPLANE_RGBX888;
2007 break;
2008 case DRM_FORMAT_XRGB2101010:
2009 case DRM_FORMAT_ARGB2101010:
2010 dspcntr |= DISPPLANE_BGRX101010;
2011 break;
2012 case DRM_FORMAT_XBGR2101010:
2013 case DRM_FORMAT_ABGR2101010:
2014 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2015 break;
2016 default:
baba133a 2017 BUG();
81255565 2018 }
57779d06 2019
a6c45cf0 2020 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2021 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2022 dspcntr |= DISPPLANE_TILED;
2023 else
2024 dspcntr &= ~DISPPLANE_TILED;
2025 }
2026
de1aa629
VS		 2027 if (IS_G4X(dev))
2028 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2029
5eddb70b 2030 I915_WRITE(reg, dspcntr);
81255565 2031
e506a0c6 2032 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2033
c2c75131
DV		 2034 if (INTEL_INFO(dev)->gen >= 4) {
2035 intel_crtc->dspaddr_offset =
bc752862
CW		 2036 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2037 fb->bits_per_pixel / 8,
2038 fb->pitches[0]);
c2c75131
DV		 2039 linear_offset -= intel_crtc->dspaddr_offset;
2040 } else {
e506a0c6 2041 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2042 }
e506a0c6 2043
f343c5f6
BW		 2044 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2045 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2046 fb->pitches[0]);
01f2c773 2047 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2048 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131 2049 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 2050 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2051 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2052 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2053 } else
f343c5f6 2054 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2055 POSTING_READ(reg);
81255565 2056
17638cd6
JB		 2057 return 0;
2058}
2059
2060static int ironlake_update_plane(struct drm_crtc *crtc,
2061 struct drm_framebuffer *fb, int x, int y)
2062{
2063 struct drm_device *dev = crtc->dev;
2064 struct drm_i915_private *dev_priv = dev->dev_private;
2065 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2066 struct intel_framebuffer *intel_fb;
2067 struct drm_i915_gem_object *obj;
2068 int plane = intel_crtc->plane;
e506a0c6 2069 unsigned long linear_offset;
17638cd6
JB		 2070 u32 dspcntr;
2071 u32 reg;
2072
2073 switch (plane) {
2074 case 0:
2075 case 1:
27f8227b 2076 case 2:
17638cd6
JB		 2077 break;
2078 default:
84f44ce7 2079 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 2080 return -EINVAL;
2081 }
2082
2083 intel_fb = to_intel_framebuffer(fb);
2084 obj = intel_fb->obj;
2085
2086 reg = DSPCNTR(plane);
2087 dspcntr = I915_READ(reg);
2088 /* Mask out pixel format bits in case we change it */
2089 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2090 switch (fb->pixel_format) {
2091 case DRM_FORMAT_C8:
17638cd6
JB		 2092 dspcntr |= DISPPLANE_8BPP;
2093 break;
57779d06
VS		 2094 case DRM_FORMAT_RGB565:
2095 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2096 break;
57779d06
VS		 2097 case DRM_FORMAT_XRGB8888:
2098 case DRM_FORMAT_ARGB8888:
2099 dspcntr |= DISPPLANE_BGRX888;
2100 break;
2101 case DRM_FORMAT_XBGR8888:
2102 case DRM_FORMAT_ABGR8888:
2103 dspcntr |= DISPPLANE_RGBX888;
2104 break;
2105 case DRM_FORMAT_XRGB2101010:
2106 case DRM_FORMAT_ARGB2101010:
2107 dspcntr |= DISPPLANE_BGRX101010;
2108 break;
2109 case DRM_FORMAT_XBGR2101010:
2110 case DRM_FORMAT_ABGR2101010:
2111 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2112 break;
2113 default:
baba133a 2114 BUG();
17638cd6
JB		 2115 }
2116
2117 if (obj->tiling_mode != I915_TILING_NONE)
2118 dspcntr |= DISPPLANE_TILED;
2119 else
2120 dspcntr &= ~DISPPLANE_TILED;
2121
1f5d76db
PZ		 2122 if (IS_HASWELL(dev))
2123 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2124 else
2125 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6
JB		 2126
2127 I915_WRITE(reg, dspcntr);
2128
e506a0c6 2129 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2130 intel_crtc->dspaddr_offset =
bc752862
CW		 2131 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2132 fb->bits_per_pixel / 8,
2133 fb->pitches[0]);
c2c75131 2134 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2135
f343c5f6
BW		 2136 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2137 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2138 fb->pitches[0]);
01f2c773 2139 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131 2140 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 2141 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2142 if (IS_HASWELL(dev)) {
2143 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2144 } else {
2145 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2146 I915_WRITE(DSPLINOFF(plane), linear_offset);
2147 }
17638cd6
JB		 2148 POSTING_READ(reg);
2149
2150 return 0;
2151}
2152
2153/* Assume fb object is pinned & idle & fenced and just update base pointers */
2154static int
2155intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2156 int x, int y, enum mode_set_atomic state)
2157{
2158 struct drm_device *dev = crtc->dev;
2159 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2160
6b8e6ed0
CW		 2161 if (dev_priv->display.disable_fbc)
2162 dev_priv->display.disable_fbc(dev);
3dec0095 2163 intel_increase_pllclock(crtc);
81255565 2164
6b8e6ed0 2165 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2166}
2167
96a02917
VS		 2168void intel_display_handle_reset(struct drm_device *dev)
2169{
2170 struct drm_i915_private *dev_priv = dev->dev_private;
2171 struct drm_crtc *crtc;
2172
2173 /*
2174 * Flips in the rings have been nuked by the reset,
2175 * so complete all pending flips so that user space
2176 * will get its events and not get stuck.
2177 *
2178 * Also update the base address of all primary
2179 * planes to the the last fb to make sure we're
2180 * showing the correct fb after a reset.
2181 *
2182 * Need to make two loops over the crtcs so that we
2183 * don't try to grab a crtc mutex before the
2184 * pending_flip_queue really got woken up.
2185 */
2186
2187 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2188 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2189 enum plane plane = intel_crtc->plane;
2190
2191 intel_prepare_page_flip(dev, plane);
2192 intel_finish_page_flip_plane(dev, plane);
2193 }
2194
2195 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2196 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2197
2198 mutex_lock(&crtc->mutex);
2199 if (intel_crtc->active)
2200 dev_priv->display.update_plane(crtc, crtc->fb,
2201 crtc->x, crtc->y);
2202 mutex_unlock(&crtc->mutex);
2203 }
2204}
2205
14667a4b
CW		 2206static int
2207intel_finish_fb(struct drm_framebuffer *old_fb)
2208{
2209 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2210 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2211 bool was_interruptible = dev_priv->mm.interruptible;
2212 int ret;
2213
14667a4b
CW		 2214 /* Big Hammer, we also need to ensure that any pending
2215 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2216 * current scanout is retired before unpinning the old
2217 * framebuffer.
2218 *
2219 * This should only fail upon a hung GPU, in which case we
2220 * can safely continue.
2221 */
2222 dev_priv->mm.interruptible = false;
2223 ret = i915_gem_object_finish_gpu(obj);
2224 dev_priv->mm.interruptible = was_interruptible;
2225
2226 return ret;
2227}
2228
198598d0
VS		 2229static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2230{
2231 struct drm_device *dev = crtc->dev;
2232 struct drm_i915_master_private *master_priv;
2233 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2234
2235 if (!dev->primary->master)
2236 return;
2237
2238 master_priv = dev->primary->master->driver_priv;
2239 if (!master_priv->sarea_priv)
2240 return;
2241
2242 switch (intel_crtc->pipe) {
2243 case 0:
2244 master_priv->sarea_priv->pipeA_x = x;
2245 master_priv->sarea_priv->pipeA_y = y;
2246 break;
2247 case 1:
2248 master_priv->sarea_priv->pipeB_x = x;
2249 master_priv->sarea_priv->pipeB_y = y;
2250 break;
2251 default:
2252 break;
2253 }
2254}
2255
5c3b82e2 2256static int
3c4fdcfb 2257intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2258 struct drm_framebuffer *fb)
79e53945
JB		 2259{
2260 struct drm_device *dev = crtc->dev;
6b8e6ed0 2261 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2262 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2263 struct drm_framebuffer *old_fb;
5c3b82e2 2264 int ret;
79e53945
JB		 2265
2266 /* no fb bound */
94352cf9 2267 if (!fb) {
a5071c2f 2268 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2269 return 0;
2270 }
2271
7eb552ae 2272 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2273 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2274 plane_name(intel_crtc->plane),
2275 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2276 return -EINVAL;
79e53945
JB		 2277 }
2278
5c3b82e2 2279 mutex_lock(&dev->struct_mutex);
265db958 2280 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2281 to_intel_framebuffer(fb)->obj,
919926ae 2282 NULL);
5c3b82e2
CW		 2283 if (ret != 0) {
2284 mutex_unlock(&dev->struct_mutex);
a5071c2f 2285 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2286 return ret;
2287 }
79e53945 2288
4d6a3e63
JB		 2289 /* Update pipe size and adjust fitter if needed */
2290 if (i915_fastboot) {
2291 I915_WRITE(PIPESRC(intel_crtc->pipe),
2292 ((crtc->mode.hdisplay - 1) << 16) |
2293 (crtc->mode.vdisplay - 1));
2294 if (!intel_crtc->config.pch_pfit.size &&
2295 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2296 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2297 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2298 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2299 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2300 }
2301 }
2302
94352cf9 2303 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2304 if (ret) {
94352cf9 2305 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2306 mutex_unlock(&dev->struct_mutex);
a5071c2f 2307 DRM_ERROR("failed to update base address\n");
4e6cfefc 2308 return ret;
79e53945 2309 }
3c4fdcfb 2310
94352cf9
DV		 2311 old_fb = crtc->fb;
2312 crtc->fb = fb;
6c4c86f5
DV		 2313 crtc->x = x;
2314 crtc->y = y;
94352cf9 2315
b7f1de28 2316 if (old_fb) {
d7697eea
DV		 2317 if (intel_crtc->active && old_fb != fb)
2318 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2319 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2320 }
652c393a 2321
6b8e6ed0 2322 intel_update_fbc(dev);
4906557e 2323 intel_edp_psr_update(dev);
5c3b82e2 2324 mutex_unlock(&dev->struct_mutex);
79e53945 2325
198598d0 2326 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2327
2328 return 0;
79e53945
JB		 2329}
2330
5e84e1a4
ZW		 2331static void intel_fdi_normal_train(struct drm_crtc *crtc)
2332{
2333 struct drm_device *dev = crtc->dev;
2334 struct drm_i915_private *dev_priv = dev->dev_private;
2335 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2336 int pipe = intel_crtc->pipe;
2337 u32 reg, temp;
2338
2339 /* enable normal train */
2340 reg = FDI_TX_CTL(pipe);
2341 temp = I915_READ(reg);
61e499bf 2342 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2343 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2344 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2345 } else {
2346 temp &= ~FDI_LINK_TRAIN_NONE;
2347 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2348 }
5e84e1a4
ZW		 2349 I915_WRITE(reg, temp);
2350
2351 reg = FDI_RX_CTL(pipe);
2352 temp = I915_READ(reg);
2353 if (HAS_PCH_CPT(dev)) {
2354 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2355 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2356 } else {
2357 temp &= ~FDI_LINK_TRAIN_NONE;
2358 temp |= FDI_LINK_TRAIN_NONE;
2359 }
2360 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2361
2362 /* wait one idle pattern time */
2363 POSTING_READ(reg);
2364 udelay(1000);
357555c0
JB		 2365
2366 /* IVB wants error correction enabled */
2367 if (IS_IVYBRIDGE(dev))
2368 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2369 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2370}
2371
1e833f40
DV		 2372static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2373{
2374 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2375}
2376
01a415fd
DV		 2377static void ivb_modeset_global_resources(struct drm_device *dev)
2378{
2379 struct drm_i915_private *dev_priv = dev->dev_private;
2380 struct intel_crtc *pipe_B_crtc =
2381 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2382 struct intel_crtc *pipe_C_crtc =
2383 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2384 uint32_t temp;
2385
1e833f40
DV		 2386 /*
2387 * When everything is off disable fdi C so that we could enable fdi B
2388 * with all lanes. Note that we don't care about enabled pipes without
2389 * an enabled pch encoder.
2390 */
2391 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2392 !pipe_has_enabled_pch(pipe_C_crtc)) {
01a415fd
DV		 2393 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2394 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2395
2396 temp = I915_READ(SOUTH_CHICKEN1);
2397 temp &= ~FDI_BC_BIFURCATION_SELECT;
2398 DRM_DEBUG_KMS("disabling fdi C rx\n");
2399 I915_WRITE(SOUTH_CHICKEN1, temp);
2400 }
2401}
2402
8db9d77b
ZW		 2403/* The FDI link training functions for ILK/Ibexpeak. */
2404static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2405{
2406 struct drm_device *dev = crtc->dev;
2407 struct drm_i915_private *dev_priv = dev->dev_private;
2408 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2409 int pipe = intel_crtc->pipe;
0fc932b8 2410 int plane = intel_crtc->plane;
5eddb70b 2411 u32 reg, temp, tries;
8db9d77b 2412
0fc932b8
JB		 2413 /* FDI needs bits from pipe & plane first */
2414 assert_pipe_enabled(dev_priv, pipe);
2415 assert_plane_enabled(dev_priv, plane);
2416
e1a44743
AJ		 2417 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2418 for train result */
5eddb70b
CW		 2419 reg = FDI_RX_IMR(pipe);
2420 temp = I915_READ(reg);
e1a44743
AJ		 2421 temp &= ~FDI_RX_SYMBOL_LOCK;
2422 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2423 I915_WRITE(reg, temp);
2424 I915_READ(reg);
e1a44743
AJ		 2425 udelay(150);
2426
8db9d77b 2427 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2428 reg = FDI_TX_CTL(pipe);
2429 temp = I915_READ(reg);
627eb5a3
DV		 2430 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2431 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2432 temp &= ~FDI_LINK_TRAIN_NONE;
2433 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2434 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2435
5eddb70b
CW		 2436 reg = FDI_RX_CTL(pipe);
2437 temp = I915_READ(reg);
8db9d77b
ZW		 2438 temp &= ~FDI_LINK_TRAIN_NONE;
2439 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2440 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2441
2442 POSTING_READ(reg);
8db9d77b
ZW		 2443 udelay(150);
2444
5b2adf89 2445 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2446 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2447 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2448 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2449
5eddb70b 2450 reg = FDI_RX_IIR(pipe);
e1a44743 2451 for (tries = 0; tries < 5; tries++) {
5eddb70b 2452 temp = I915_READ(reg);
8db9d77b
ZW		 2453 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2454
2455 if ((temp & FDI_RX_BIT_LOCK)) {
2456 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2457 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2458 break;
2459 }
8db9d77b 2460 }
e1a44743 2461 if (tries == 5)
5eddb70b 2462 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2463
2464 /* Train 2 */
5eddb70b
CW		 2465 reg = FDI_TX_CTL(pipe);
2466 temp = I915_READ(reg);
8db9d77b
ZW		 2467 temp &= ~FDI_LINK_TRAIN_NONE;
2468 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2469 I915_WRITE(reg, temp);
8db9d77b 2470
5eddb70b
CW		 2471 reg = FDI_RX_CTL(pipe);
2472 temp = I915_READ(reg);
8db9d77b
ZW		 2473 temp &= ~FDI_LINK_TRAIN_NONE;
2474 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2475 I915_WRITE(reg, temp);
8db9d77b 2476
5eddb70b
CW		 2477 POSTING_READ(reg);
2478 udelay(150);
8db9d77b 2479
5eddb70b 2480 reg = FDI_RX_IIR(pipe);
e1a44743 2481 for (tries = 0; tries < 5; tries++) {
5eddb70b 2482 temp = I915_READ(reg);
8db9d77b
ZW		 2483 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2484
2485 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2486 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2487 DRM_DEBUG_KMS("FDI train 2 done.\n");
2488 break;
2489 }
8db9d77b 2490 }
e1a44743 2491 if (tries == 5)
5eddb70b 2492 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2493
2494 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2495
8db9d77b
ZW		 2496}
2497
0206e353 2498static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2499 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2500 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2501 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2502 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2503};
2504
2505/* The FDI link training functions for SNB/Cougarpoint. */
2506static void gen6_fdi_link_train(struct drm_crtc *crtc)
2507{
2508 struct drm_device *dev = crtc->dev;
2509 struct drm_i915_private *dev_priv = dev->dev_private;
2510 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2511 int pipe = intel_crtc->pipe;
fa37d39e 2512 u32 reg, temp, i, retry;
8db9d77b 2513
e1a44743
AJ		 2514 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2515 for train result */
5eddb70b
CW		 2516 reg = FDI_RX_IMR(pipe);
2517 temp = I915_READ(reg);
e1a44743
AJ		 2518 temp &= ~FDI_RX_SYMBOL_LOCK;
2519 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2520 I915_WRITE(reg, temp);
2521
2522 POSTING_READ(reg);
e1a44743
AJ		 2523 udelay(150);
2524
8db9d77b 2525 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2526 reg = FDI_TX_CTL(pipe);
2527 temp = I915_READ(reg);
627eb5a3
DV		 2528 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2529 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2530 temp &= ~FDI_LINK_TRAIN_NONE;
2531 temp |= FDI_LINK_TRAIN_PATTERN_1;
2532 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2533 /* SNB-B */
2534 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2535 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2536
d74cf324
DV		 2537 I915_WRITE(FDI_RX_MISC(pipe),
2538 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2539
5eddb70b
CW		 2540 reg = FDI_RX_CTL(pipe);
2541 temp = I915_READ(reg);
8db9d77b
ZW		 2542 if (HAS_PCH_CPT(dev)) {
2543 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2544 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2545 } else {
2546 temp &= ~FDI_LINK_TRAIN_NONE;
2547 temp |= FDI_LINK_TRAIN_PATTERN_1;
2548 }
5eddb70b
CW		 2549 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2550
2551 POSTING_READ(reg);
8db9d77b
ZW		 2552 udelay(150);
2553
0206e353 2554 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2555 reg = FDI_TX_CTL(pipe);
2556 temp = I915_READ(reg);
8db9d77b
ZW		 2557 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2558 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2559 I915_WRITE(reg, temp);
2560
2561 POSTING_READ(reg);
8db9d77b
ZW		 2562 udelay(500);
2563
fa37d39e
SP		 2564 for (retry = 0; retry < 5; retry++) {
2565 reg = FDI_RX_IIR(pipe);
2566 temp = I915_READ(reg);
2567 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2568 if (temp & FDI_RX_BIT_LOCK) {
2569 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2570 DRM_DEBUG_KMS("FDI train 1 done.\n");
2571 break;
2572 }
2573 udelay(50);
8db9d77b 2574 }
fa37d39e
SP		 2575 if (retry < 5)
2576 break;
8db9d77b
ZW		 2577 }
2578 if (i == 4)
5eddb70b 2579 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2580
2581 /* Train 2 */
5eddb70b
CW		 2582 reg = FDI_TX_CTL(pipe);
2583 temp = I915_READ(reg);
8db9d77b
ZW		 2584 temp &= ~FDI_LINK_TRAIN_NONE;
2585 temp |= FDI_LINK_TRAIN_PATTERN_2;
2586 if (IS_GEN6(dev)) {
2587 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2588 /* SNB-B */
2589 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2590 }
5eddb70b 2591 I915_WRITE(reg, temp);
8db9d77b 2592
5eddb70b
CW		 2593 reg = FDI_RX_CTL(pipe);
2594 temp = I915_READ(reg);
8db9d77b
ZW		 2595 if (HAS_PCH_CPT(dev)) {
2596 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2597 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2598 } else {
2599 temp &= ~FDI_LINK_TRAIN_NONE;
2600 temp |= FDI_LINK_TRAIN_PATTERN_2;
2601 }
5eddb70b
CW		 2602 I915_WRITE(reg, temp);
2603
2604 POSTING_READ(reg);
8db9d77b
ZW		 2605 udelay(150);
2606
0206e353 2607 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2608 reg = FDI_TX_CTL(pipe);
2609 temp = I915_READ(reg);
8db9d77b
ZW		 2610 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2611 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2612 I915_WRITE(reg, temp);
2613
2614 POSTING_READ(reg);
8db9d77b
ZW		 2615 udelay(500);
2616
fa37d39e
SP		 2617 for (retry = 0; retry < 5; retry++) {
2618 reg = FDI_RX_IIR(pipe);
2619 temp = I915_READ(reg);
2620 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2621 if (temp & FDI_RX_SYMBOL_LOCK) {
2622 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2623 DRM_DEBUG_KMS("FDI train 2 done.\n");
2624 break;
2625 }
2626 udelay(50);
8db9d77b 2627 }
fa37d39e
SP		 2628 if (retry < 5)
2629 break;
8db9d77b
ZW		 2630 }
2631 if (i == 4)
5eddb70b 2632 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2633
2634 DRM_DEBUG_KMS("FDI train done.\n");
2635}
2636
357555c0
JB		 2637/* Manual link training for Ivy Bridge A0 parts */
2638static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2639{
2640 struct drm_device *dev = crtc->dev;
2641 struct drm_i915_private *dev_priv = dev->dev_private;
2642 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2643 int pipe = intel_crtc->pipe;
139ccd3f 2644 u32 reg, temp, i, j;
357555c0
JB		 2645
2646 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2647 for train result */
2648 reg = FDI_RX_IMR(pipe);
2649 temp = I915_READ(reg);
2650 temp &= ~FDI_RX_SYMBOL_LOCK;
2651 temp &= ~FDI_RX_BIT_LOCK;
2652 I915_WRITE(reg, temp);
2653
2654 POSTING_READ(reg);
2655 udelay(150);
2656
01a415fd
DV		 2657 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2658 I915_READ(FDI_RX_IIR(pipe)));
2659
139ccd3f
JB		 2660 /* Try each vswing and preemphasis setting twice before moving on */
2661 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2662 /* disable first in case we need to retry */
2663 reg = FDI_TX_CTL(pipe);
2664 temp = I915_READ(reg);
2665 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2666 temp &= ~FDI_TX_ENABLE;
2667 I915_WRITE(reg, temp);
357555c0 2668
139ccd3f
JB		 2669 reg = FDI_RX_CTL(pipe);
2670 temp = I915_READ(reg);
2671 temp &= ~FDI_LINK_TRAIN_AUTO;
2672 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2673 temp &= ~FDI_RX_ENABLE;
2674 I915_WRITE(reg, temp);
357555c0 2675
139ccd3f 2676 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 2677 reg = FDI_TX_CTL(pipe);
2678 temp = I915_READ(reg);
139ccd3f
JB		 2679 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2680 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2681 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 2682 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 2683 temp |= snb_b_fdi_train_param[j/2];
2684 temp |= FDI_COMPOSITE_SYNC;
2685 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 2686
139ccd3f
JB		 2687 I915_WRITE(FDI_RX_MISC(pipe),
2688 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 2689
139ccd3f 2690 reg = FDI_RX_CTL(pipe);
357555c0 2691 temp = I915_READ(reg);
139ccd3f
JB		 2692 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2693 temp |= FDI_COMPOSITE_SYNC;
2694 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 2695
139ccd3f
JB		 2696 POSTING_READ(reg);
2697 udelay(1); /* should be 0.5us */
357555c0 2698
139ccd3f
JB		 2699 for (i = 0; i < 4; i++) {
2700 reg = FDI_RX_IIR(pipe);
2701 temp = I915_READ(reg);
2702 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 2703
139ccd3f
JB		 2704 if (temp & FDI_RX_BIT_LOCK ||
2705 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2706 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2707 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2708 i);
2709 break;
2710 }
2711 udelay(1); /* should be 0.5us */
2712 }
2713 if (i == 4) {
2714 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2715 continue;
2716 }
357555c0 2717
139ccd3f 2718 /* Train 2 */
357555c0
JB		 2719 reg = FDI_TX_CTL(pipe);
2720 temp = I915_READ(reg);
139ccd3f
JB		 2721 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2722 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2723 I915_WRITE(reg, temp);
2724
2725 reg = FDI_RX_CTL(pipe);
2726 temp = I915_READ(reg);
2727 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2728 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 2729 I915_WRITE(reg, temp);
2730
2731 POSTING_READ(reg);
139ccd3f 2732 udelay(2); /* should be 1.5us */
357555c0 2733
139ccd3f
JB		 2734 for (i = 0; i < 4; i++) {
2735 reg = FDI_RX_IIR(pipe);
2736 temp = I915_READ(reg);
2737 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 2738
139ccd3f
JB		 2739 if (temp & FDI_RX_SYMBOL_LOCK ||
2740 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2741 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2742 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2743 i);
2744 goto train_done;
2745 }
2746 udelay(2); /* should be 1.5us */
357555c0 2747 }
139ccd3f
JB		 2748 if (i == 4)
2749 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 2750 }
357555c0 2751
139ccd3f 2752train_done:
357555c0
JB		 2753 DRM_DEBUG_KMS("FDI train done.\n");
2754}
2755
88cefb6c 2756static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2757{
88cefb6c 2758 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2759 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2760 int pipe = intel_crtc->pipe;
5eddb70b 2761 u32 reg, temp;
79e53945 2762
c64e311e 2763
c98e9dcf 2764 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2765 reg = FDI_RX_CTL(pipe);
2766 temp = I915_READ(reg);
627eb5a3
DV		 2767 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2768 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
dfd07d72 2769 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2770 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2771
2772 POSTING_READ(reg);
c98e9dcf
JB		 2773 udelay(200);
2774
2775 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2776 temp = I915_READ(reg);
2777 I915_WRITE(reg, temp | FDI_PCDCLK);
2778
2779 POSTING_READ(reg);
c98e9dcf
JB		 2780 udelay(200);
2781
20749730
PZ		 2782 /* Enable CPU FDI TX PLL, always on for Ironlake */
2783 reg = FDI_TX_CTL(pipe);
2784 temp = I915_READ(reg);
2785 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2786 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2787
20749730
PZ		 2788 POSTING_READ(reg);
2789 udelay(100);
6be4a607 2790 }
0e23b99d
JB		 2791}
2792
88cefb6c
DV		 2793static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2794{
2795 struct drm_device *dev = intel_crtc->base.dev;
2796 struct drm_i915_private *dev_priv = dev->dev_private;
2797 int pipe = intel_crtc->pipe;
2798 u32 reg, temp;
2799
2800 /* Switch from PCDclk to Rawclk */
2801 reg = FDI_RX_CTL(pipe);
2802 temp = I915_READ(reg);
2803 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2804
2805 /* Disable CPU FDI TX PLL */
2806 reg = FDI_TX_CTL(pipe);
2807 temp = I915_READ(reg);
2808 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2809
2810 POSTING_READ(reg);
2811 udelay(100);
2812
2813 reg = FDI_RX_CTL(pipe);
2814 temp = I915_READ(reg);
2815 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2816
2817 /* Wait for the clocks to turn off. */
2818 POSTING_READ(reg);
2819 udelay(100);
2820}
2821
0fc932b8
JB		 2822static void ironlake_fdi_disable(struct drm_crtc *crtc)
2823{
2824 struct drm_device *dev = crtc->dev;
2825 struct drm_i915_private *dev_priv = dev->dev_private;
2826 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2827 int pipe = intel_crtc->pipe;
2828 u32 reg, temp;
2829
2830 /* disable CPU FDI tx and PCH FDI rx */
2831 reg = FDI_TX_CTL(pipe);
2832 temp = I915_READ(reg);
2833 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2834 POSTING_READ(reg);
2835
2836 reg = FDI_RX_CTL(pipe);
2837 temp = I915_READ(reg);
2838 temp &= ~(0x7 << 16);
dfd07d72 2839 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2840 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2841
2842 POSTING_READ(reg);
2843 udelay(100);
2844
2845 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2846 if (HAS_PCH_IBX(dev)) {
2847 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2848 }
0fc932b8
JB		 2849
2850 /* still set train pattern 1 */
2851 reg = FDI_TX_CTL(pipe);
2852 temp = I915_READ(reg);
2853 temp &= ~FDI_LINK_TRAIN_NONE;
2854 temp |= FDI_LINK_TRAIN_PATTERN_1;
2855 I915_WRITE(reg, temp);
2856
2857 reg = FDI_RX_CTL(pipe);
2858 temp = I915_READ(reg);
2859 if (HAS_PCH_CPT(dev)) {
2860 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2861 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2862 } else {
2863 temp &= ~FDI_LINK_TRAIN_NONE;
2864 temp |= FDI_LINK_TRAIN_PATTERN_1;
2865 }
2866 /* BPC in FDI rx is consistent with that in PIPECONF */
2867 temp &= ~(0x07 << 16);
dfd07d72 2868 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2869 I915_WRITE(reg, temp);
2870
2871 POSTING_READ(reg);
2872 udelay(100);
2873}
2874
5bb61643
CW		 2875static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2876{
2877 struct drm_device *dev = crtc->dev;
2878 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2879 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2880 unsigned long flags;
2881 bool pending;
2882
10d83730
VS		 2883 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2884 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2885 return false;
2886
2887 spin_lock_irqsave(&dev->event_lock, flags);
2888 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2889 spin_unlock_irqrestore(&dev->event_lock, flags);
2890
2891 return pending;
2892}
2893
e6c3a2a6
CW		 2894static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2895{
0f91128d 2896 struct drm_device *dev = crtc->dev;
5bb61643 2897 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2898
2899 if (crtc->fb == NULL)
2900 return;
2901
2c10d571
DV		 2902 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2903
5bb61643
CW		 2904 wait_event(dev_priv->pending_flip_queue,
2905 !intel_crtc_has_pending_flip(crtc));
2906
0f91128d
CW		 2907 mutex_lock(&dev->struct_mutex);
2908 intel_finish_fb(crtc->fb);
2909 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2910}
2911
e615efe4
ED		 2912/* Program iCLKIP clock to the desired frequency */
2913static void lpt_program_iclkip(struct drm_crtc *crtc)
2914{
2915 struct drm_device *dev = crtc->dev;
2916 struct drm_i915_private *dev_priv = dev->dev_private;
12d7ceed 2917 int clock = to_intel_crtc(crtc)->config.adjusted_mode.clock;
e615efe4
ED		 2918 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2919 u32 temp;
2920
09153000
DV		 2921 mutex_lock(&dev_priv->dpio_lock);
2922
e615efe4
ED		 2923 /* It is necessary to ungate the pixclk gate prior to programming
2924 * the divisors, and gate it back when it is done.
2925 */
2926 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2927
2928 /* Disable SSCCTL */
2929 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2930 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2931 SBI_SSCCTL_DISABLE,
2932 SBI_ICLK);
e615efe4
ED		 2933
2934 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 2935 if (clock == 20000) {
e615efe4
ED		 2936 auxdiv = 1;
2937 divsel = 0x41;
2938 phaseinc = 0x20;
2939 } else {
2940 /* The iCLK virtual clock root frequency is in MHz,
12d7ceed 2941 * but the adjusted_mode->clock in in KHz. To get the divisors,
e615efe4
ED		 2942 * it is necessary to divide one by another, so we
2943 * convert the virtual clock precision to KHz here for higher
2944 * precision.
2945 */
2946 u32 iclk_virtual_root_freq = 172800 * 1000;
2947 u32 iclk_pi_range = 64;
2948 u32 desired_divisor, msb_divisor_value, pi_value;
2949
12d7ceed 2950 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 2951 msb_divisor_value = desired_divisor / iclk_pi_range;
2952 pi_value = desired_divisor % iclk_pi_range;
2953
2954 auxdiv = 0;
2955 divsel = msb_divisor_value - 2;
2956 phaseinc = pi_value;
2957 }
2958
2959 /* This should not happen with any sane values */
2960 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2961 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2962 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2963 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2964
2965 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 2966 clock,
e615efe4
ED		 2967 auxdiv,
2968 divsel,
2969 phasedir,
2970 phaseinc);
2971
2972 /* Program SSCDIVINTPHASE6 */
988d6ee8 2973 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 2974 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2975 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2976 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2977 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2978 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2979 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 2980 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 2981
2982 /* Program SSCAUXDIV */
988d6ee8 2983 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 2984 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2985 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 2986 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 2987
2988 /* Enable modulator and associated divider */
988d6ee8 2989 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 2990 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 2991 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 2992
2993 /* Wait for initialization time */
2994 udelay(24);
2995
2996 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 2997
2998 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 2999}
3000
275f01b2
DV		 3001static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3002 enum pipe pch_transcoder)
3003{
3004 struct drm_device *dev = crtc->base.dev;
3005 struct drm_i915_private *dev_priv = dev->dev_private;
3006 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3007
3008 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3009 I915_READ(HTOTAL(cpu_transcoder)));
3010 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3011 I915_READ(HBLANK(cpu_transcoder)));
3012 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3013 I915_READ(HSYNC(cpu_transcoder)));
3014
3015 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3016 I915_READ(VTOTAL(cpu_transcoder)));
3017 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3018 I915_READ(VBLANK(cpu_transcoder)));
3019 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3020 I915_READ(VSYNC(cpu_transcoder)));
3021 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3022 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3023}
3024
f67a559d
JB		 3025/*
3026 * Enable PCH resources required for PCH ports:
3027 * - PCH PLLs
3028 * - FDI training & RX/TX
3029 * - update transcoder timings
3030 * - DP transcoding bits
3031 * - transcoder
3032 */
3033static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3034{
3035 struct drm_device *dev = crtc->dev;
3036 struct drm_i915_private *dev_priv = dev->dev_private;
3037 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3038 int pipe = intel_crtc->pipe;
ee7b9f93 3039 u32 reg, temp;
2c07245f 3040
ab9412ba 3041 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 3042
cd986abb
DV		 3043 /* Write the TU size bits before fdi link training, so that error
3044 * detection works. */
3045 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3046 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3047
c98e9dcf 3048 /* For PCH output, training FDI link */
674cf967 3049 dev_priv->display.fdi_link_train(crtc);
2c07245f 3050
3ad8a208
DV		 3051 /* We need to program the right clock selection before writing the pixel
3052 * mutliplier into the DPLL. */
303b81e0 3053 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3054 u32 sel;
4b645f14 3055
c98e9dcf 3056 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 3057 temp |= TRANS_DPLL_ENABLE(pipe);
3058 sel = TRANS_DPLLB_SEL(pipe);
a43f6e0f 3059 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 3060 temp |= sel;
3061 else
3062 temp &= ~sel;
c98e9dcf 3063 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3064 }
5eddb70b 3065
3ad8a208
DV		 3066 /* XXX: pch pll's can be enabled any time before we enable the PCH
3067 * transcoder, and we actually should do this to not upset any PCH
3068 * transcoder that already use the clock when we share it.
3069 *
3070 * Note that enable_shared_dpll tries to do the right thing, but
3071 * get_shared_dpll unconditionally resets the pll - we need that to have
3072 * the right LVDS enable sequence. */
3073 ironlake_enable_shared_dpll(intel_crtc);
3074
d9b6cb56
JB		 3075 /* set transcoder timing, panel must allow it */
3076 assert_panel_unlocked(dev_priv, pipe);
275f01b2 3077 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 3078
303b81e0 3079 intel_fdi_normal_train(crtc);
5e84e1a4 3080
c98e9dcf
JB		 3081 /* For PCH DP, enable TRANS_DP_CTL */
3082 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3083 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3084 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3085 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3086 reg = TRANS_DP_CTL(pipe);
3087 temp = I915_READ(reg);
3088 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3089 TRANS_DP_SYNC_MASK |
3090 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3091 temp |= (TRANS_DP_OUTPUT_ENABLE |
3092 TRANS_DP_ENH_FRAMING);
9325c9f0 3093 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3094
3095 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3096 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3097 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3098 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3099
3100 switch (intel_trans_dp_port_sel(crtc)) {
3101 case PCH_DP_B:
5eddb70b 3102 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3103 break;
3104 case PCH_DP_C:
5eddb70b 3105 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3106 break;
3107 case PCH_DP_D:
5eddb70b 3108 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3109 break;
3110 default:
e95d41e1 3111 BUG();
32f9d658 3112 }
2c07245f 3113
5eddb70b 3114 I915_WRITE(reg, temp);
6be4a607 3115 }
b52eb4dc 3116
b8a4f404 3117 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3118}
3119
1507e5bd
PZ		 3120static void lpt_pch_enable(struct drm_crtc *crtc)
3121{
3122 struct drm_device *dev = crtc->dev;
3123 struct drm_i915_private *dev_priv = dev->dev_private;
3124 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3125 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3126
ab9412ba 3127 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3128
8c52b5e8 3129 lpt_program_iclkip(crtc);
1507e5bd 3130
0540e488 3131 /* Set transcoder timing. */
275f01b2 3132 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 3133
937bb610 3134 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3135}
3136
e2b78267 3137static void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3138{
e2b78267 3139 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 3140
3141 if (pll == NULL)
3142 return;
3143
3144 if (pll->refcount == 0) {
46edb027 3145 WARN(1, "bad %s refcount\n", pll->name);
ee7b9f93
JB		 3146 return;
3147 }
3148
f4a091c7
DV		 3149 if (--pll->refcount == 0) {
3150 WARN_ON(pll->on);
3151 WARN_ON(pll->active);
3152 }
3153
a43f6e0f 3154 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 3155}
3156
b89a1d39 3157static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3158{
e2b78267
DV		 3159 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3160 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3161 enum intel_dpll_id i;
ee7b9f93 3162
ee7b9f93 3163 if (pll) {
46edb027
DV		 3164 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3165 crtc->base.base.id, pll->name);
e2b78267 3166 intel_put_shared_dpll(crtc);
ee7b9f93
JB		 3167 }
3168
98b6bd99
DV		 3169 if (HAS_PCH_IBX(dev_priv->dev)) {
3170 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 3171 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 3172 pll = &dev_priv->shared_dplls[i];
98b6bd99 3173
46edb027
DV		 3174 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3175 crtc->base.base.id, pll->name);
98b6bd99
DV		 3176
3177 goto found;
3178 }
3179
e72f9fbf
DV		 3180 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3181 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 3182
3183 /* Only want to check enabled timings first */
3184 if (pll->refcount == 0)
3185 continue;
3186
b89a1d39
DV		 3187 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3188 sizeof(pll->hw_state)) == 0) {
46edb027 3189 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
e2b78267 3190 crtc->base.base.id,
46edb027 3191 pll->name, pll->refcount, pll->active);
ee7b9f93
JB		 3192
3193 goto found;
3194 }
3195 }
3196
3197 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 3198 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3199 pll = &dev_priv->shared_dplls[i];
ee7b9f93 3200 if (pll->refcount == 0) {
46edb027
DV		 3201 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3202 crtc->base.base.id, pll->name);
ee7b9f93
JB		 3203 goto found;
3204 }
3205 }
3206
3207 return NULL;
3208
3209found:
a43f6e0f 3210 crtc->config.shared_dpll = i;
46edb027
DV		 3211 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3212 pipe_name(crtc->pipe));
ee7b9f93 3213
cdbd2316 3214 if (pll->active == 0) {
66e985c0
DV		 3215 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3216 sizeof(pll->hw_state));
3217
46edb027 3218 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
cdbd2316 3219 WARN_ON(pll->on);
e9d6944e 3220 assert_shared_dpll_disabled(dev_priv, pll);
ee7b9f93 3221
15bdd4cf 3222 pll->mode_set(dev_priv, pll);
cdbd2316
DV		 3223 }
3224 pll->refcount++;
e04c7350 3225
ee7b9f93
JB		 3226 return pll;
3227}
3228
a1520318 3229static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 3230{
3231 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3232 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3233 u32 temp;
3234
3235 temp = I915_READ(dslreg);
3236 udelay(500);
3237 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3238 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3239 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3240 }
3241}
3242
b074cec8
JB		 3243static void ironlake_pfit_enable(struct intel_crtc *crtc)
3244{
3245 struct drm_device *dev = crtc->base.dev;
3246 struct drm_i915_private *dev_priv = dev->dev_private;
3247 int pipe = crtc->pipe;
3248
0ef37f3f 3249 if (crtc->config.pch_pfit.size) {
b074cec8
JB		 3250 /* Force use of hard-coded filter coefficients
3251 * as some pre-programmed values are broken,
3252 * e.g. x201.
3253 */
3254 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3255 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3256 PF_PIPE_SEL_IVB(pipe));
3257 else
3258 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3259 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3260 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
d4270e57
JB		 3261 }
3262}
3263
bb53d4ae
VS		 3264static void intel_enable_planes(struct drm_crtc *crtc)
3265{
3266 struct drm_device *dev = crtc->dev;
3267 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3268 struct intel_plane *intel_plane;
3269
3270 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3271 if (intel_plane->pipe == pipe)
3272 intel_plane_restore(&intel_plane->base);
3273}
3274
3275static void intel_disable_planes(struct drm_crtc *crtc)
3276{
3277 struct drm_device *dev = crtc->dev;
3278 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3279 struct intel_plane *intel_plane;
3280
3281 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3282 if (intel_plane->pipe == pipe)
3283 intel_plane_disable(&intel_plane->base);
3284}
3285
f67a559d
JB		 3286static void ironlake_crtc_enable(struct drm_crtc *crtc)
3287{
3288 struct drm_device *dev = crtc->dev;
3289 struct drm_i915_private *dev_priv = dev->dev_private;
3290 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3291 struct intel_encoder *encoder;
f67a559d
JB		 3292 int pipe = intel_crtc->pipe;
3293 int plane = intel_crtc->plane;
f67a559d 3294
08a48469
DV		 3295 WARN_ON(!crtc->enabled);
3296
f67a559d
JB		 3297 if (intel_crtc->active)
3298 return;
3299
3300 intel_crtc->active = true;
8664281b
PZ		 3301
3302 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3303 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3304
f6736a1a 3305 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 3306 if (encoder->pre_enable)
3307 encoder->pre_enable(encoder);
f67a559d 3308
5bfe2ac0 3309 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3310 /* Note: FDI PLL enabling _must_ be done before we enable the
3311 * cpu pipes, hence this is separate from all the other fdi/pch
3312 * enabling. */
88cefb6c 3313 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3314 } else {
3315 assert_fdi_tx_disabled(dev_priv, pipe);
3316 assert_fdi_rx_disabled(dev_priv, pipe);
3317 }
f67a559d 3318
b074cec8 3319 ironlake_pfit_enable(intel_crtc);
f67a559d 3320
9c54c0dd
JB		 3321 /*
3322 * On ILK+ LUT must be loaded before the pipe is running but with
3323 * clocks enabled
3324 */
3325 intel_crtc_load_lut(crtc);
3326
f37fcc2a 3327 intel_update_watermarks(crtc);
5bfe2ac0 3328 intel_enable_pipe(dev_priv, pipe,
23538ef1 3329 intel_crtc->config.has_pch_encoder, false);
f67a559d 3330 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3331 intel_enable_planes(crtc);
5c38d48c 3332 intel_crtc_update_cursor(crtc, true);
f67a559d 3333
5bfe2ac0 3334 if (intel_crtc->config.has_pch_encoder)
f67a559d 3335 ironlake_pch_enable(crtc);
c98e9dcf 3336
d1ebd816 3337 mutex_lock(&dev->struct_mutex);
bed4a673 3338 intel_update_fbc(dev);
d1ebd816
BW		 3339 mutex_unlock(&dev->struct_mutex);
3340
fa5c73b1
DV		 3341 for_each_encoder_on_crtc(dev, crtc, encoder)
3342 encoder->enable(encoder);
61b77ddd
DV		 3343
3344 if (HAS_PCH_CPT(dev))
a1520318 3345 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3346
3347 /*
3348 * There seems to be a race in PCH platform hw (at least on some
3349 * outputs) where an enabled pipe still completes any pageflip right
3350 * away (as if the pipe is off) instead of waiting for vblank. As soon
3351 * as the first vblank happend, everything works as expected. Hence just
3352 * wait for one vblank before returning to avoid strange things
3353 * happening.
3354 */
3355 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3356}
3357
42db64ef
PZ		 3358/* IPS only exists on ULT machines and is tied to pipe A. */
3359static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3360{
f5adf94e 3361 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 3362}
3363
3364static void hsw_enable_ips(struct intel_crtc *crtc)
3365{
3366 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3367
3368 if (!crtc->config.ips_enabled)
3369 return;
3370
3371 /* We can only enable IPS after we enable a plane and wait for a vblank.
3372 * We guarantee that the plane is enabled by calling intel_enable_ips
3373 * only after intel_enable_plane. And intel_enable_plane already waits
3374 * for a vblank, so all we need to do here is to enable the IPS bit. */
3375 assert_plane_enabled(dev_priv, crtc->plane);
3376 I915_WRITE(IPS_CTL, IPS_ENABLE);
3377}
3378
3379static void hsw_disable_ips(struct intel_crtc *crtc)
3380{
3381 struct drm_device *dev = crtc->base.dev;
3382 struct drm_i915_private *dev_priv = dev->dev_private;
3383
3384 if (!crtc->config.ips_enabled)
3385 return;
3386
3387 assert_plane_enabled(dev_priv, crtc->plane);
3388 I915_WRITE(IPS_CTL, 0);
3389
3390 /* We need to wait for a vblank before we can disable the plane. */
3391 intel_wait_for_vblank(dev, crtc->pipe);
3392}
3393
4f771f10
PZ		 3394static void haswell_crtc_enable(struct drm_crtc *crtc)
3395{
3396 struct drm_device *dev = crtc->dev;
3397 struct drm_i915_private *dev_priv = dev->dev_private;
3398 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3399 struct intel_encoder *encoder;
3400 int pipe = intel_crtc->pipe;
3401 int plane = intel_crtc->plane;
4f771f10
PZ		 3402
3403 WARN_ON(!crtc->enabled);
3404
3405 if (intel_crtc->active)
3406 return;
3407
3408 intel_crtc->active = true;
8664281b
PZ		 3409
3410 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3411 if (intel_crtc->config.has_pch_encoder)
3412 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3413
5bfe2ac0 3414 if (intel_crtc->config.has_pch_encoder)
04945641 3415 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3416
3417 for_each_encoder_on_crtc(dev, crtc, encoder)
3418 if (encoder->pre_enable)
3419 encoder->pre_enable(encoder);
3420
1f544388 3421 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3422
b074cec8 3423 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 3424
3425 /*
3426 * On ILK+ LUT must be loaded before the pipe is running but with
3427 * clocks enabled
3428 */
3429 intel_crtc_load_lut(crtc);
3430
1f544388 3431 intel_ddi_set_pipe_settings(crtc);
8228c251 3432 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3433
f37fcc2a 3434 intel_update_watermarks(crtc);
5bfe2ac0 3435 intel_enable_pipe(dev_priv, pipe,
23538ef1 3436 intel_crtc->config.has_pch_encoder, false);
4f771f10 3437 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3438 intel_enable_planes(crtc);
5c38d48c 3439 intel_crtc_update_cursor(crtc, true);
4f771f10 3440
42db64ef
PZ		 3441 hsw_enable_ips(intel_crtc);
3442
5bfe2ac0 3443 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3444 lpt_pch_enable(crtc);
4f771f10
PZ		 3445
3446 mutex_lock(&dev->struct_mutex);
3447 intel_update_fbc(dev);
3448 mutex_unlock(&dev->struct_mutex);
3449
8807e55b 3450 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 3451 encoder->enable(encoder);
8807e55b
JN		 3452 intel_opregion_notify_encoder(encoder, true);
3453 }
4f771f10 3454
4f771f10
PZ		 3455 /*
3456 * There seems to be a race in PCH platform hw (at least on some
3457 * outputs) where an enabled pipe still completes any pageflip right
3458 * away (as if the pipe is off) instead of waiting for vblank. As soon
3459 * as the first vblank happend, everything works as expected. Hence just
3460 * wait for one vblank before returning to avoid strange things
3461 * happening.
3462 */
3463 intel_wait_for_vblank(dev, intel_crtc->pipe);
3464}
3465
3f8dce3a
DV		 3466static void ironlake_pfit_disable(struct intel_crtc *crtc)
3467{
3468 struct drm_device *dev = crtc->base.dev;
3469 struct drm_i915_private *dev_priv = dev->dev_private;
3470 int pipe = crtc->pipe;
3471
3472 /* To avoid upsetting the power well on haswell only disable the pfit if
3473 * it's in use. The hw state code will make sure we get this right. */
3474 if (crtc->config.pch_pfit.size) {
3475 I915_WRITE(PF_CTL(pipe), 0);
3476 I915_WRITE(PF_WIN_POS(pipe), 0);
3477 I915_WRITE(PF_WIN_SZ(pipe), 0);
3478 }
3479}
3480
6be4a607
JB		 3481static void ironlake_crtc_disable(struct drm_crtc *crtc)
3482{
3483 struct drm_device *dev = crtc->dev;
3484 struct drm_i915_private *dev_priv = dev->dev_private;
3485 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3486 struct intel_encoder *encoder;
6be4a607
JB		 3487 int pipe = intel_crtc->pipe;
3488 int plane = intel_crtc->plane;
5eddb70b 3489 u32 reg, temp;
b52eb4dc 3490
ef9c3aee 3491
f7abfe8b
CW		 3492 if (!intel_crtc->active)
3493 return;
3494
ea9d758d
DV		 3495 for_each_encoder_on_crtc(dev, crtc, encoder)
3496 encoder->disable(encoder);
3497
e6c3a2a6 3498 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3499 drm_vblank_off(dev, pipe);
913d8d11 3500
5c3fe8b0 3501 if (dev_priv->fbc.plane == plane)
973d04f9 3502 intel_disable_fbc(dev);
2c07245f 3503
0d5b8c61 3504 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3505 intel_disable_planes(crtc);
0d5b8c61
VS		 3506 intel_disable_plane(dev_priv, plane, pipe);
3507
d925c59a
DV		 3508 if (intel_crtc->config.has_pch_encoder)
3509 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3510
b24e7179 3511 intel_disable_pipe(dev_priv, pipe);
32f9d658 3512
3f8dce3a 3513 ironlake_pfit_disable(intel_crtc);
2c07245f 3514
bf49ec8c
DV		 3515 for_each_encoder_on_crtc(dev, crtc, encoder)
3516 if (encoder->post_disable)
3517 encoder->post_disable(encoder);
2c07245f 3518
d925c59a
DV		 3519 if (intel_crtc->config.has_pch_encoder) {
3520 ironlake_fdi_disable(crtc);
913d8d11 3521
d925c59a
DV		 3522 ironlake_disable_pch_transcoder(dev_priv, pipe);
3523 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
6be4a607 3524
d925c59a
DV		 3525 if (HAS_PCH_CPT(dev)) {
3526 /* disable TRANS_DP_CTL */
3527 reg = TRANS_DP_CTL(pipe);
3528 temp = I915_READ(reg);
3529 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3530 TRANS_DP_PORT_SEL_MASK);
3531 temp |= TRANS_DP_PORT_SEL_NONE;
3532 I915_WRITE(reg, temp);
3533
3534 /* disable DPLL_SEL */
3535 temp = I915_READ(PCH_DPLL_SEL);
11887397 3536 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 3537 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 3538 }
e3421a18 3539
d925c59a 3540 /* disable PCH DPLL */
e72f9fbf 3541 intel_disable_shared_dpll(intel_crtc);
8db9d77b 3542
d925c59a
DV		 3543 ironlake_fdi_pll_disable(intel_crtc);
3544 }
6b383a7f 3545
f7abfe8b 3546 intel_crtc->active = false;
46ba614c 3547 intel_update_watermarks(crtc);
d1ebd816
BW		 3548
3549 mutex_lock(&dev->struct_mutex);
6b383a7f 3550 intel_update_fbc(dev);
d1ebd816 3551 mutex_unlock(&dev->struct_mutex);
6be4a607 3552}
1b3c7a47 3553
4f771f10 3554static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3555{
4f771f10
PZ		 3556 struct drm_device *dev = crtc->dev;
3557 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3558 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3559 struct intel_encoder *encoder;
3560 int pipe = intel_crtc->pipe;
3561 int plane = intel_crtc->plane;
3b117c8f 3562 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3563
4f771f10
PZ		 3564 if (!intel_crtc->active)
3565 return;
3566
8807e55b
JN		 3567 for_each_encoder_on_crtc(dev, crtc, encoder) {
3568 intel_opregion_notify_encoder(encoder, false);
4f771f10 3569 encoder->disable(encoder);
8807e55b 3570 }
4f771f10
PZ		 3571
3572 intel_crtc_wait_for_pending_flips(crtc);
3573 drm_vblank_off(dev, pipe);
4f771f10 3574
891348b2 3575 /* FBC must be disabled before disabling the plane on HSW. */
5c3fe8b0 3576 if (dev_priv->fbc.plane == plane)
4f771f10
PZ		 3577 intel_disable_fbc(dev);
3578
42db64ef
PZ		 3579 hsw_disable_ips(intel_crtc);
3580
0d5b8c61 3581 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3582 intel_disable_planes(crtc);
891348b2
RV		 3583 intel_disable_plane(dev_priv, plane, pipe);
3584
8664281b
PZ		 3585 if (intel_crtc->config.has_pch_encoder)
3586 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ		 3587 intel_disable_pipe(dev_priv, pipe);
3588
ad80a810 3589 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3590
3f8dce3a 3591 ironlake_pfit_disable(intel_crtc);
4f771f10 3592
1f544388 3593 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3594
3595 for_each_encoder_on_crtc(dev, crtc, encoder)
3596 if (encoder->post_disable)
3597 encoder->post_disable(encoder);
3598
88adfff1 3599 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3600 lpt_disable_pch_transcoder(dev_priv);
8664281b 3601 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3602 intel_ddi_fdi_disable(crtc);
83616634 3603 }
4f771f10
PZ		 3604
3605 intel_crtc->active = false;
46ba614c 3606 intel_update_watermarks(crtc);
4f771f10
PZ		 3607
3608 mutex_lock(&dev->struct_mutex);
3609 intel_update_fbc(dev);
3610 mutex_unlock(&dev->struct_mutex);
3611}
3612
ee7b9f93
JB		 3613static void ironlake_crtc_off(struct drm_crtc *crtc)
3614{
3615 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 3616 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 3617}
3618
6441ab5f
PZ		 3619static void haswell_crtc_off(struct drm_crtc *crtc)
3620{
3621 intel_ddi_put_crtc_pll(crtc);
3622}
3623
02e792fb
DV		 3624static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3625{
02e792fb 3626 if (!enable && intel_crtc->overlay) {
23f09ce3 3627 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3628 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3629
23f09ce3 3630 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3631 dev_priv->mm.interruptible = false;
3632 (void) intel_overlay_switch_off(intel_crtc->overlay);
3633 dev_priv->mm.interruptible = true;
23f09ce3 3634 mutex_unlock(&dev->struct_mutex);
02e792fb 3635 }
02e792fb 3636
5dcdbcb0
CW		 3637 /* Let userspace switch the overlay on again. In most cases userspace
3638 * has to recompute where to put it anyway.
3639 */
02e792fb
DV		 3640}
3641
61bc95c1
EE		 3642/**
3643 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3644 * cursor plane briefly if not already running after enabling the display
3645 * plane.
3646 * This workaround avoids occasional blank screens when self refresh is
3647 * enabled.
3648 */
3649static void
3650g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3651{
3652 u32 cntl = I915_READ(CURCNTR(pipe));
3653
3654 if ((cntl & CURSOR_MODE) == 0) {
3655 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3656
3657 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3658 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3659 intel_wait_for_vblank(dev_priv->dev, pipe);
3660 I915_WRITE(CURCNTR(pipe), cntl);
3661 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3662 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3663 }
3664}
3665
2dd24552
JB		 3666static void i9xx_pfit_enable(struct intel_crtc *crtc)
3667{
3668 struct drm_device *dev = crtc->base.dev;
3669 struct drm_i915_private *dev_priv = dev->dev_private;
3670 struct intel_crtc_config *pipe_config = &crtc->config;
3671
328d8e82 3672 if (!crtc->config.gmch_pfit.control)
2dd24552
JB		 3673 return;
3674
2dd24552 3675 /*
c0b03411
DV		 3676 * The panel fitter should only be adjusted whilst the pipe is disabled,
3677 * according to register description and PRM.
2dd24552 3678 */
c0b03411
DV		 3679 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3680 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 3681
b074cec8
JB		 3682 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3683 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 3684
3685 /* Border color in case we don't scale up to the full screen. Black by
3686 * default, change to something else for debugging. */
3687 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 3688}
3689
89b667f8
JB		 3690static void valleyview_crtc_enable(struct drm_crtc *crtc)
3691{
3692 struct drm_device *dev = crtc->dev;
3693 struct drm_i915_private *dev_priv = dev->dev_private;
3694 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3695 struct intel_encoder *encoder;
3696 int pipe = intel_crtc->pipe;
3697 int plane = intel_crtc->plane;
23538ef1 3698 bool is_dsi;
89b667f8
JB		 3699
3700 WARN_ON(!crtc->enabled);
3701
3702 if (intel_crtc->active)
3703 return;
3704
3705 intel_crtc->active = true;
89b667f8 3706
89b667f8
JB		 3707 for_each_encoder_on_crtc(dev, crtc, encoder)
3708 if (encoder->pre_pll_enable)
3709 encoder->pre_pll_enable(encoder);
3710
23538ef1
JN		 3711 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
3712
e9fd1c02
JN		 3713 if (!is_dsi)
3714 vlv_enable_pll(intel_crtc);
89b667f8
JB		 3715
3716 for_each_encoder_on_crtc(dev, crtc, encoder)
3717 if (encoder->pre_enable)
3718 encoder->pre_enable(encoder);
3719
2dd24552
JB		 3720 i9xx_pfit_enable(intel_crtc);
3721
63cbb074
VS		 3722 intel_crtc_load_lut(crtc);
3723
f37fcc2a 3724 intel_update_watermarks(crtc);
23538ef1 3725 intel_enable_pipe(dev_priv, pipe, false, is_dsi);
89b667f8 3726 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3727 intel_enable_planes(crtc);
5c38d48c 3728 intel_crtc_update_cursor(crtc, true);
89b667f8 3729
89b667f8 3730 intel_update_fbc(dev);
5004945f
JN		 3731
3732 for_each_encoder_on_crtc(dev, crtc, encoder)
3733 encoder->enable(encoder);
89b667f8
JB		 3734}
3735
0b8765c6 3736static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3737{
3738 struct drm_device *dev = crtc->dev;
79e53945
JB		 3739 struct drm_i915_private *dev_priv = dev->dev_private;
3740 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3741 struct intel_encoder *encoder;
79e53945 3742 int pipe = intel_crtc->pipe;
80824003 3743 int plane = intel_crtc->plane;
79e53945 3744
08a48469
DV		 3745 WARN_ON(!crtc->enabled);
3746
f7abfe8b
CW		 3747 if (intel_crtc->active)
3748 return;
3749
3750 intel_crtc->active = true;
6b383a7f 3751
9d6d9f19
MK		 3752 for_each_encoder_on_crtc(dev, crtc, encoder)
3753 if (encoder->pre_enable)
3754 encoder->pre_enable(encoder);
3755
f6736a1a
DV		 3756 i9xx_enable_pll(intel_crtc);
3757
2dd24552
JB		 3758 i9xx_pfit_enable(intel_crtc);
3759
63cbb074
VS		 3760 intel_crtc_load_lut(crtc);
3761
f37fcc2a 3762 intel_update_watermarks(crtc);
23538ef1 3763 intel_enable_pipe(dev_priv, pipe, false, false);
b24e7179 3764 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3765 intel_enable_planes(crtc);
22e407d7 3766 /* The fixup needs to happen before cursor is enabled */
61bc95c1
EE		 3767 if (IS_G4X(dev))
3768 g4x_fixup_plane(dev_priv, pipe);
22e407d7 3769 intel_crtc_update_cursor(crtc, true);
79e53945 3770
0b8765c6
JB		 3771 /* Give the overlay scaler a chance to enable if it's on this pipe */
3772 intel_crtc_dpms_overlay(intel_crtc, true);
ef9c3aee 3773
f440eb13 3774 intel_update_fbc(dev);
ef9c3aee 3775
fa5c73b1
DV		 3776 for_each_encoder_on_crtc(dev, crtc, encoder)
3777 encoder->enable(encoder);
0b8765c6 3778}
79e53945 3779
87476d63
DV		 3780static void i9xx_pfit_disable(struct intel_crtc *crtc)
3781{
3782 struct drm_device *dev = crtc->base.dev;
3783 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 3784
328d8e82
DV		 3785 if (!crtc->config.gmch_pfit.control)
3786 return;
87476d63 3787
328d8e82 3788 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 3789
328d8e82
DV		 3790 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3791 I915_READ(PFIT_CONTROL));
3792 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 3793}
3794
0b8765c6
JB		 3795static void i9xx_crtc_disable(struct drm_crtc *crtc)
3796{
3797 struct drm_device *dev = crtc->dev;
3798 struct drm_i915_private *dev_priv = dev->dev_private;
3799 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3800 struct intel_encoder *encoder;
0b8765c6
JB		 3801 int pipe = intel_crtc->pipe;
3802 int plane = intel_crtc->plane;
ef9c3aee 3803
f7abfe8b
CW		 3804 if (!intel_crtc->active)
3805 return;
3806
ea9d758d
DV		 3807 for_each_encoder_on_crtc(dev, crtc, encoder)
3808 encoder->disable(encoder);
3809
0b8765c6 3810 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3811 intel_crtc_wait_for_pending_flips(crtc);
3812 drm_vblank_off(dev, pipe);
0b8765c6 3813
5c3fe8b0 3814 if (dev_priv->fbc.plane == plane)
973d04f9 3815 intel_disable_fbc(dev);
79e53945 3816
0d5b8c61
VS		 3817 intel_crtc_dpms_overlay(intel_crtc, false);
3818 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3819 intel_disable_planes(crtc);
b24e7179 3820 intel_disable_plane(dev_priv, plane, pipe);
0d5b8c61 3821
b24e7179 3822 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3823
87476d63 3824 i9xx_pfit_disable(intel_crtc);
24a1f16d 3825
89b667f8
JB		 3826 for_each_encoder_on_crtc(dev, crtc, encoder)
3827 if (encoder->post_disable)
3828 encoder->post_disable(encoder);
3829
e9fd1c02
JN		 3830 if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3831 i9xx_disable_pll(dev_priv, pipe);
0b8765c6 3832
f7abfe8b 3833 intel_crtc->active = false;
46ba614c 3834 intel_update_watermarks(crtc);
f37fcc2a
VS		 3835
3836 intel_update_fbc(dev);
0b8765c6
JB		 3837}
3838
ee7b9f93
JB		 3839static void i9xx_crtc_off(struct drm_crtc *crtc)
3840{
3841}
3842
976f8a20
DV		 3843static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3844 bool enabled)
2c07245f
ZW		 3845{
3846 struct drm_device *dev = crtc->dev;
3847 struct drm_i915_master_private *master_priv;
3848 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3849 int pipe = intel_crtc->pipe;
79e53945
JB		 3850
3851 if (!dev->primary->master)
3852 return;
3853
3854 master_priv = dev->primary->master->driver_priv;
3855 if (!master_priv->sarea_priv)
3856 return;
3857
79e53945
JB		 3858 switch (pipe) {
3859 case 0:
3860 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3861 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3862 break;
3863 case 1:
3864 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3865 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3866 break;
3867 default:
9db4a9c7 3868 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3869 break;
3870 }
79e53945
JB		 3871}
3872
976f8a20
DV		 3873/**
3874 * Sets the power management mode of the pipe and plane.
3875 */
3876void intel_crtc_update_dpms(struct drm_crtc *crtc)
3877{
3878 struct drm_device *dev = crtc->dev;
3879 struct drm_i915_private *dev_priv = dev->dev_private;
3880 struct intel_encoder *intel_encoder;
3881 bool enable = false;
3882
3883 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3884 enable |= intel_encoder->connectors_active;
3885
3886 if (enable)
3887 dev_priv->display.crtc_enable(crtc);
3888 else
3889 dev_priv->display.crtc_disable(crtc);
3890
3891 intel_crtc_update_sarea(crtc, enable);
3892}
3893
cdd59983
CW		 3894static void intel_crtc_disable(struct drm_crtc *crtc)
3895{
cdd59983 3896 struct drm_device *dev = crtc->dev;
976f8a20 3897 struct drm_connector *connector;
ee7b9f93 3898 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3899 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3900
976f8a20
DV		 3901 /* crtc should still be enabled when we disable it. */
3902 WARN_ON(!crtc->enabled);
3903
3904 dev_priv->display.crtc_disable(crtc);
c77bf565 3905 intel_crtc->eld_vld = false;
976f8a20 3906 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3907 dev_priv->display.off(crtc);
3908
931872fc 3909 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
93ce0ba6 3910 assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
931872fc 3911 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3912
3913 if (crtc->fb) {
3914 mutex_lock(&dev->struct_mutex);
1690e1eb 3915 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3916 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3917 crtc->fb = NULL;
3918 }
3919
3920 /* Update computed state. */
3921 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3922 if (!connector->encoder || !connector->encoder->crtc)
3923 continue;
3924
3925 if (connector->encoder->crtc != crtc)
3926 continue;
3927
3928 connector->dpms = DRM_MODE_DPMS_OFF;
3929 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3930 }
3931}
3932
ea5b213a 3933void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3934{
4ef69c7a 3935 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3936
ea5b213a
CW		 3937 drm_encoder_cleanup(encoder);
3938 kfree(intel_encoder);
7e7d76c3
JB		 3939}
3940
9237329d 3941/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
DV		 3942 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3943 * state of the entire output pipe. */
9237329d 3944static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3945{
5ab432ef
DV		 3946 if (mode == DRM_MODE_DPMS_ON) {
3947 encoder->connectors_active = true;
3948
b2cabb0e 3949 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3950 } else {
3951 encoder->connectors_active = false;
3952
b2cabb0e 3953 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3954 }
79e53945
JB		 3955}
3956
0a91ca29
DV		 3957/* Cross check the actual hw state with our own modeset state tracking (and it's
3958 * internal consistency). */
b980514c 3959static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3960{
0a91ca29
DV		 3961 if (connector->get_hw_state(connector)) {
3962 struct intel_encoder *encoder = connector->encoder;
3963 struct drm_crtc *crtc;
3964 bool encoder_enabled;
3965 enum pipe pipe;
3966
3967 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3968 connector->base.base.id,
3969 drm_get_connector_name(&connector->base));
3970
3971 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3972 "wrong connector dpms state\n");
3973 WARN(connector->base.encoder != &encoder->base,
3974 "active connector not linked to encoder\n");
3975 WARN(!encoder->connectors_active,
3976 "encoder->connectors_active not set\n");
3977
3978 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3979 WARN(!encoder_enabled, "encoder not enabled\n");
3980 if (WARN_ON(!encoder->base.crtc))
3981 return;
3982
3983 crtc = encoder->base.crtc;
3984
3985 WARN(!crtc->enabled, "crtc not enabled\n");
3986 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3987 WARN(pipe != to_intel_crtc(crtc)->pipe,
3988 "encoder active on the wrong pipe\n");
3989 }
79e53945
JB		 3990}
3991
5ab432ef
DV		 3992/* Even simpler default implementation, if there's really no special case to
3993 * consider. */
3994void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3995{
5ab432ef 3996 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3997
5ab432ef
DV		 3998 /* All the simple cases only support two dpms states. */
3999 if (mode != DRM_MODE_DPMS_ON)
4000 mode = DRM_MODE_DPMS_OFF;
d4270e57 4001
5ab432ef
DV		 4002 if (mode == connector->dpms)
4003 return;
4004
4005 connector->dpms = mode;
4006
4007 /* Only need to change hw state when actually enabled */
4008 if (encoder->base.crtc)
4009 intel_encoder_dpms(encoder, mode);
4010 else
8af6cf88 4011 WARN_ON(encoder->connectors_active != false);
0a91ca29 4012
b980514c 4013 intel_modeset_check_state(connector->dev);
79e53945
JB		 4014}
4015
f0947c37
DV		 4016/* Simple connector->get_hw_state implementation for encoders that support only
4017 * one connector and no cloning and hence the encoder state determines the state
4018 * of the connector. */
4019bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 4020{
24929352 4021 enum pipe pipe = 0;
f0947c37 4022 struct intel_encoder *encoder = connector->encoder;
ea5b213a 4023
f0947c37 4024 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 4025}
4026
1857e1da
DV		 4027static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4028 struct intel_crtc_config *pipe_config)
4029{
4030 struct drm_i915_private *dev_priv = dev->dev_private;
4031 struct intel_crtc *pipe_B_crtc =
4032 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4033
4034 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4035 pipe_name(pipe), pipe_config->fdi_lanes);
4036 if (pipe_config->fdi_lanes > 4) {
4037 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4038 pipe_name(pipe), pipe_config->fdi_lanes);
4039 return false;
4040 }
4041
4042 if (IS_HASWELL(dev)) {
4043 if (pipe_config->fdi_lanes > 2) {
4044 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4045 pipe_config->fdi_lanes);
4046 return false;
4047 } else {
4048 return true;
4049 }
4050 }
4051
4052 if (INTEL_INFO(dev)->num_pipes == 2)
4053 return true;
4054
4055 /* Ivybridge 3 pipe is really complicated */
4056 switch (pipe) {
4057 case PIPE_A:
4058 return true;
4059 case PIPE_B:
4060 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4061 pipe_config->fdi_lanes > 2) {
4062 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4063 pipe_name(pipe), pipe_config->fdi_lanes);
4064 return false;
4065 }
4066 return true;
4067 case PIPE_C:
1e833f40 4068 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
1857e1da
DV		 4069 pipe_B_crtc->config.fdi_lanes <= 2) {
4070 if (pipe_config->fdi_lanes > 2) {
4071 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4072 pipe_name(pipe), pipe_config->fdi_lanes);
4073 return false;
4074 }
4075 } else {
4076 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4077 return false;
4078 }
4079 return true;
4080 default:
4081 BUG();
4082 }
4083}
4084
e29c22c0
DV		 4085#define RETRY 1
4086static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4087 struct intel_crtc_config *pipe_config)
877d48d5 4088{
1857e1da 4089 struct drm_device *dev = intel_crtc->base.dev;
877d48d5 4090 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
ff9a6750 4091 int lane, link_bw, fdi_dotclock;
e29c22c0 4092 bool setup_ok, needs_recompute = false;
877d48d5 4093
e29c22c0 4094retry:
877d48d5
DV		 4095 /* FDI is a binary signal running at ~2.7GHz, encoding
4096 * each output octet as 10 bits. The actual frequency
4097 * is stored as a divider into a 100MHz clock, and the
4098 * mode pixel clock is stored in units of 1KHz.
4099 * Hence the bw of each lane in terms of the mode signal
4100 * is:
4101 */
4102 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4103
ff9a6750 4104 fdi_dotclock = adjusted_mode->clock;
877d48d5 4105
2bd89a07 4106 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 4107 pipe_config->pipe_bpp);
4108
4109 pipe_config->fdi_lanes = lane;
4110
2bd89a07 4111 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 4112 link_bw, &pipe_config->fdi_m_n);
1857e1da 4113
e29c22c0
DV		 4114 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4115 intel_crtc->pipe, pipe_config);
4116 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4117 pipe_config->pipe_bpp -= 2*3;
4118 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4119 pipe_config->pipe_bpp);
4120 needs_recompute = true;
4121 pipe_config->bw_constrained = true;
4122
4123 goto retry;
4124 }
4125
4126 if (needs_recompute)
4127 return RETRY;
4128
4129 return setup_ok ? 0 : -EINVAL;
877d48d5
DV		 4130}
4131
42db64ef
PZ		 4132static void hsw_compute_ips_config(struct intel_crtc *crtc,
4133 struct intel_crtc_config *pipe_config)
4134{
3c4ca58c
PZ		 4135 pipe_config->ips_enabled = i915_enable_ips &&
4136 hsw_crtc_supports_ips(crtc) &&
b6dfdc9b 4137 pipe_config->pipe_bpp <= 24;
42db64ef
PZ		 4138}
4139
a43f6e0f 4140static int intel_crtc_compute_config(struct intel_crtc *crtc,
e29c22c0 4141 struct intel_crtc_config *pipe_config)
79e53945 4142{
a43f6e0f 4143 struct drm_device *dev = crtc->base.dev;
b8cecdf5 4144 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 4145
8693a824
DL		 4146 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4147 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 4148 */
4149 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4150 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 4151 return -EINVAL;
44f46b42 4152
bd080ee5 4153 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4154 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4155 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4156 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4157 * for lvds. */
4158 pipe_config->pipe_bpp = 8*3;
4159 }
4160
f5adf94e 4161 if (HAS_IPS(dev))
a43f6e0f
DV		 4162 hsw_compute_ips_config(crtc, pipe_config);
4163
4164 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4165 * clock survives for now. */
4166 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4167 pipe_config->shared_dpll = crtc->config.shared_dpll;
42db64ef 4168
877d48d5 4169 if (pipe_config->has_pch_encoder)
a43f6e0f 4170 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 4171
e29c22c0 4172 return 0;
79e53945
JB		 4173}
4174
25eb05fc
JB		 4175static int valleyview_get_display_clock_speed(struct drm_device *dev)
4176{
4177 return 400000; /* FIXME */
4178}
4179
e70236a8
JB		 4180static int i945_get_display_clock_speed(struct drm_device *dev)
4181{
4182 return 400000;
4183}
79e53945 4184
e70236a8 4185static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4186{
e70236a8
JB		 4187 return 333000;
4188}
79e53945 4189
e70236a8
JB		 4190static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4191{
4192 return 200000;
4193}
79e53945 4194
257a7ffc
DV		 4195static int pnv_get_display_clock_speed(struct drm_device *dev)
4196{
4197 u16 gcfgc = 0;
4198
4199 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4200
4201 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4202 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4203 return 267000;
4204 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4205 return 333000;
4206 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4207 return 444000;
4208 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4209 return 200000;
4210 default:
4211 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4212 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4213 return 133000;
4214 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4215 return 167000;
4216 }
4217}
4218
e70236a8
JB		 4219static int i915gm_get_display_clock_speed(struct drm_device *dev)
4220{
4221 u16 gcfgc = 0;
79e53945 4222
e70236a8
JB		 4223 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4224
4225 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4226 return 133000;
4227 else {
4228 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4229 case GC_DISPLAY_CLOCK_333_MHZ:
4230 return 333000;
4231 default:
4232 case GC_DISPLAY_CLOCK_190_200_MHZ:
4233 return 190000;
79e53945 4234 }
e70236a8
JB		 4235 }
4236}
4237
4238static int i865_get_display_clock_speed(struct drm_device *dev)
4239{
4240 return 266000;
4241}
4242
4243static int i855_get_display_clock_speed(struct drm_device *dev)
4244{
4245 u16 hpllcc = 0;
4246 /* Assume that the hardware is in the high speed state. This
4247 * should be the default.
4248 */
4249 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4250 case GC_CLOCK_133_200:
4251 case GC_CLOCK_100_200:
4252 return 200000;
4253 case GC_CLOCK_166_250:
4254 return 250000;
4255 case GC_CLOCK_100_133:
79e53945 4256 return 133000;
e70236a8 4257 }
79e53945 4258
e70236a8
JB		 4259 /* Shouldn't happen */
4260 return 0;
4261}
79e53945 4262
e70236a8
JB		 4263static int i830_get_display_clock_speed(struct drm_device *dev)
4264{
4265 return 133000;
79e53945
JB		 4266}
4267
2c07245f 4268static void
a65851af 4269intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 4270{
a65851af
VS		 4271 while (*num > DATA_LINK_M_N_MASK ||
4272 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 4273 *num >>= 1;
4274 *den >>= 1;
4275 }
4276}
4277
a65851af
VS		 4278static void compute_m_n(unsigned int m, unsigned int n,
4279 uint32_t *ret_m, uint32_t *ret_n)
4280{
4281 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4282 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4283 intel_reduce_m_n_ratio(ret_m, ret_n);
4284}
4285
e69d0bc1
DV		 4286void
4287intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4288 int pixel_clock, int link_clock,
4289 struct intel_link_m_n *m_n)
2c07245f 4290{
e69d0bc1 4291 m_n->tu = 64;
a65851af
VS		 4292
4293 compute_m_n(bits_per_pixel * pixel_clock,
4294 link_clock * nlanes * 8,
4295 &m_n->gmch_m, &m_n->gmch_n);
4296
4297 compute_m_n(pixel_clock, link_clock,
4298 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4299}
4300
a7615030
CW		 4301static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4302{
72bbe58c
KP		 4303 if (i915_panel_use_ssc >= 0)
4304 return i915_panel_use_ssc != 0;
41aa3448 4305 return dev_priv->vbt.lvds_use_ssc
435793df 4306 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4307}
4308
a0c4da24
JB		 4309static int vlv_get_refclk(struct drm_crtc *crtc)
4310{
4311 struct drm_device *dev = crtc->dev;
4312 struct drm_i915_private *dev_priv = dev->dev_private;
4313 int refclk = 27000; /* for DP & HDMI */
4314
4315 return 100000; /* only one validated so far */
4316
4317 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4318 refclk = 96000;
4319 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4320 if (intel_panel_use_ssc(dev_priv))
4321 refclk = 100000;
4322 else
4323 refclk = 96000;
4324 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4325 refclk = 100000;
4326 }
4327
4328 return refclk;
4329}
4330
c65d77d8
JB		 4331static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4332{
4333 struct drm_device *dev = crtc->dev;
4334 struct drm_i915_private *dev_priv = dev->dev_private;
4335 int refclk;
4336
a0c4da24
JB		 4337 if (IS_VALLEYVIEW(dev)) {
4338 refclk = vlv_get_refclk(crtc);
4339 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8 4340 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
41aa3448 4341 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
c65d77d8
JB		 4342 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4343 refclk / 1000);
4344 } else if (!IS_GEN2(dev)) {
4345 refclk = 96000;
4346 } else {
4347 refclk = 48000;
4348 }
4349
4350 return refclk;
4351}
4352
7429e9d4 4353static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 4354{
7df00d7a 4355 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 4356}
f47709a9 4357
7429e9d4
DV		 4358static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4359{
4360 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 4361}
4362
f47709a9 4363static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4364 intel_clock_t *reduced_clock)
4365{
f47709a9 4366 struct drm_device *dev = crtc->base.dev;
a7516a05 4367 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4368 int pipe = crtc->pipe;
a7516a05
JB		 4369 u32 fp, fp2 = 0;
4370
4371 if (IS_PINEVIEW(dev)) {
7429e9d4 4372 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4373 if (reduced_clock)
7429e9d4 4374 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 4375 } else {
7429e9d4 4376 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4377 if (reduced_clock)
7429e9d4 4378 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 4379 }
4380
4381 I915_WRITE(FP0(pipe), fp);
8bcc2795 4382 crtc->config.dpll_hw_state.fp0 = fp;
a7516a05 4383
f47709a9
DV		 4384 crtc->lowfreq_avail = false;
4385 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4386 reduced_clock && i915_powersave) {
4387 I915_WRITE(FP1(pipe), fp2);
8bcc2795 4388 crtc->config.dpll_hw_state.fp1 = fp2;
f47709a9 4389 crtc->lowfreq_avail = true;
a7516a05
JB		 4390 } else {
4391 I915_WRITE(FP1(pipe), fp);
8bcc2795 4392 crtc->config.dpll_hw_state.fp1 = fp;
a7516a05
JB		 4393 }
4394}
4395
5e69f97f
CML		 4396static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
4397 pipe)
89b667f8
JB		 4398{
4399 u32 reg_val;
4400
4401 /*
4402 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4403 * and set it to a reasonable value instead.
4404 */
5e69f97f 4405 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
89b667f8
JB		 4406 reg_val &= 0xffffff00;
4407 reg_val |= 0x00000030;
5e69f97f 4408 vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
89b667f8 4409
5e69f97f 4410 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
89b667f8
JB		 4411 reg_val &= 0x8cffffff;
4412 reg_val = 0x8c000000;
5e69f97f 4413 vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
89b667f8 4414
5e69f97f 4415 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
89b667f8 4416 reg_val &= 0xffffff00;
5e69f97f 4417 vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
89b667f8 4418
5e69f97f 4419 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
89b667f8
JB		 4420 reg_val &= 0x00ffffff;
4421 reg_val |= 0xb0000000;
5e69f97f 4422 vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
89b667f8
JB		 4423}
4424
b551842d
DV		 4425static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4426 struct intel_link_m_n *m_n)
4427{
4428 struct drm_device *dev = crtc->base.dev;
4429 struct drm_i915_private *dev_priv = dev->dev_private;
4430 int pipe = crtc->pipe;
4431
e3b95f1e
DV		 4432 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4433 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4434 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4435 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 4436}
4437
4438static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4439 struct intel_link_m_n *m_n)
4440{
4441 struct drm_device *dev = crtc->base.dev;
4442 struct drm_i915_private *dev_priv = dev->dev_private;
4443 int pipe = crtc->pipe;
4444 enum transcoder transcoder = crtc->config.cpu_transcoder;
4445
4446 if (INTEL_INFO(dev)->gen >= 5) {
4447 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4448 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4449 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4450 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4451 } else {
e3b95f1e
DV		 4452 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4453 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4454 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4455 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 4456 }
4457}
4458
03afc4a2
DV		 4459static void intel_dp_set_m_n(struct intel_crtc *crtc)
4460{
4461 if (crtc->config.has_pch_encoder)
4462 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4463 else
4464 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4465}
4466
f47709a9 4467static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4468{
f47709a9 4469 struct drm_device *dev = crtc->base.dev;
a0c4da24 4470 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4471 int pipe = crtc->pipe;
89b667f8 4472 u32 dpll, mdiv;
a0c4da24 4473 u32 bestn, bestm1, bestm2, bestp1, bestp2;
198a037f 4474 u32 coreclk, reg_val, dpll_md;
a0c4da24 4475
09153000
DV		 4476 mutex_lock(&dev_priv->dpio_lock);
4477
f47709a9
DV		 4478 bestn = crtc->config.dpll.n;
4479 bestm1 = crtc->config.dpll.m1;
4480 bestm2 = crtc->config.dpll.m2;
4481 bestp1 = crtc->config.dpll.p1;
4482 bestp2 = crtc->config.dpll.p2;
a0c4da24 4483
89b667f8
JB		 4484 /* See eDP HDMI DPIO driver vbios notes doc */
4485
4486 /* PLL B needs special handling */
4487 if (pipe)
5e69f97f 4488 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 4489
4490 /* Set up Tx target for periodic Rcomp update */
5e69f97f 4491 vlv_dpio_write(dev_priv, pipe, DPIO_IREF_BCAST, 0x0100000f);
89b667f8
JB		 4492
4493 /* Disable target IRef on PLL */
5e69f97f 4494 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF_CTL(pipe));
89b667f8 4495 reg_val &= 0x00ffffff;
5e69f97f 4496 vlv_dpio_write(dev_priv, pipe, DPIO_IREF_CTL(pipe), reg_val);
89b667f8
JB		 4497
4498 /* Disable fast lock */
5e69f97f 4499 vlv_dpio_write(dev_priv, pipe, DPIO_FASTCLK_DISABLE, 0x610);
89b667f8
JB		 4500
4501 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4502 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4503 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4504 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4505 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 4506
4507 /*
4508 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4509 * but we don't support that).
4510 * Note: don't use the DAC post divider as it seems unstable.
4511 */
4512 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5e69f97f 4513 vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
a0c4da24 4514
a0c4da24 4515 mdiv |= DPIO_ENABLE_CALIBRATION;
5e69f97f 4516 vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
a0c4da24 4517
89b667f8 4518 /* Set HBR and RBR LPF coefficients */
ff9a6750 4519 if (crtc->config.port_clock == 162000 ||
99750bd4 4520 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
89b667f8 4521 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5e69f97f 4522 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
885b0120 4523 0x009f0003);
89b667f8 4524 else
5e69f97f 4525 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
89b667f8
JB		 4526 0x00d0000f);
4527
4528 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4529 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4530 /* Use SSC source */
4531 if (!pipe)
5e69f97f 4532 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4533 0x0df40000);
4534 else
5e69f97f 4535 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4536 0x0df70000);
4537 } else { /* HDMI or VGA */
4538 /* Use bend source */
4539 if (!pipe)
5e69f97f 4540 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4541 0x0df70000);
4542 else
5e69f97f 4543 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4544 0x0df40000);
4545 }
a0c4da24 4546
5e69f97f 4547 coreclk = vlv_dpio_read(dev_priv, pipe, DPIO_CORE_CLK(pipe));
89b667f8
JB		 4548 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4549 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4550 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4551 coreclk |= 0x01000000;
5e69f97f 4552 vlv_dpio_write(dev_priv, pipe, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4553
5e69f97f 4554 vlv_dpio_write(dev_priv, pipe, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4555
89b667f8
JB		 4556 /* Enable DPIO clock input */
4557 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4558 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4559 if (pipe)
4560 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
a0c4da24
JB		 4561
4562 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4563 crtc->config.dpll_hw_state.dpll = dpll;
4564
ef1b460d
DV		 4565 dpll_md = (crtc->config.pixel_multiplier - 1)
4566 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795
DV		 4567 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4568
89b667f8
JB		 4569 if (crtc->config.has_dp_encoder)
4570 intel_dp_set_m_n(crtc);
09153000
DV		 4571
4572 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4573}
4574
f47709a9
DV		 4575static void i9xx_update_pll(struct intel_crtc *crtc,
4576 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4577 int num_connectors)
4578{
f47709a9 4579 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4580 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 4581 u32 dpll;
4582 bool is_sdvo;
f47709a9 4583 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4584
f47709a9 4585 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4586
f47709a9
DV		 4587 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4588 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4589
4590 dpll = DPLL_VGA_MODE_DIS;
4591
f47709a9 4592 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4593 dpll |= DPLLB_MODE_LVDS;
4594 else
4595 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4596
ef1b460d 4597 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
198a037f
DV		 4598 dpll |= (crtc->config.pixel_multiplier - 1)
4599 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 4600 }
198a037f
DV		 4601
4602 if (is_sdvo)
4a33e48d 4603 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 4604
f47709a9 4605 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4a33e48d 4606 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 4607
4608 /* compute bitmask from p1 value */
4609 if (IS_PINEVIEW(dev))
4610 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4611 else {
4612 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4613 if (IS_G4X(dev) && reduced_clock)
4614 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4615 }
4616 switch (clock->p2) {
4617 case 5:
4618 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4619 break;
4620 case 7:
4621 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4622 break;
4623 case 10:
4624 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4625 break;
4626 case 14:
4627 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4628 break;
4629 }
4630 if (INTEL_INFO(dev)->gen >= 4)
4631 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4632
09ede541 4633 if (crtc->config.sdvo_tv_clock)
eb1cbe48 4634 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4635 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4636 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4637 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4638 else
4639 dpll |= PLL_REF_INPUT_DREFCLK;
4640
4641 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4642 crtc->config.dpll_hw_state.dpll = dpll;
4643
eb1cbe48 4644 if (INTEL_INFO(dev)->gen >= 4) {
ef1b460d
DV		 4645 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4646 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795 4647 crtc->config.dpll_hw_state.dpll_md = dpll_md;
eb1cbe48 4648 }
66e3d5c0
DV		 4649
4650 if (crtc->config.has_dp_encoder)
4651 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4652}
4653
f47709a9 4654static void i8xx_update_pll(struct intel_crtc *crtc,
f47709a9 4655 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4656 int num_connectors)
4657{
f47709a9 4658 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4659 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 4660 u32 dpll;
f47709a9 4661 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4662
f47709a9 4663 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4664
eb1cbe48
DV		 4665 dpll = DPLL_VGA_MODE_DIS;
4666
f47709a9 4667 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4668 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4669 } else {
4670 if (clock->p1 == 2)
4671 dpll |= PLL_P1_DIVIDE_BY_TWO;
4672 else
4673 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4674 if (clock->p2 == 4)
4675 dpll |= PLL_P2_DIVIDE_BY_4;
4676 }
4677
4a33e48d
DV		 4678 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
4679 dpll |= DPLL_DVO_2X_MODE;
4680
f47709a9 4681 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4682 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4683 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4684 else
4685 dpll |= PLL_REF_INPUT_DREFCLK;
4686
4687 dpll |= DPLL_VCO_ENABLE;
8bcc2795 4688 crtc->config.dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 4689}
4690
8a654f3b 4691static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 4692{
4693 struct drm_device *dev = intel_crtc->base.dev;
4694 struct drm_i915_private *dev_priv = dev->dev_private;
4695 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4696 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8a654f3b
DV		 4697 struct drm_display_mode *adjusted_mode =
4698 &intel_crtc->config.adjusted_mode;
4699 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4d8a62ea
DV		 4700 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4701
4702 /* We need to be careful not to changed the adjusted mode, for otherwise
4703 * the hw state checker will get angry at the mismatch. */
4704 crtc_vtotal = adjusted_mode->crtc_vtotal;
4705 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c
PZ		 4706
4707 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4708 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 4709 crtc_vtotal -= 1;
4710 crtc_vblank_end -= 1;
b0e77b9c
PZ		 4711 vsyncshift = adjusted_mode->crtc_hsync_start
4712 - adjusted_mode->crtc_htotal / 2;
4713 } else {
4714 vsyncshift = 0;
4715 }
4716
4717 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4718 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4719
fe2b8f9d 4720 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4721 (adjusted_mode->crtc_hdisplay - 1) |
4722 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4723 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4724 (adjusted_mode->crtc_hblank_start - 1) |
4725 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4726 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4727 (adjusted_mode->crtc_hsync_start - 1) |
4728 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4729
fe2b8f9d 4730 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 4731 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 4732 ((crtc_vtotal - 1) << 16));
fe2b8f9d 4733 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 4734 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 4735 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 4736 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4737 (adjusted_mode->crtc_vsync_start - 1) |
4738 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4739
b5e508d4
PZ		 4740 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4741 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4742 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4743 * bits. */
4744 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4745 (pipe == PIPE_B || pipe == PIPE_C))
4746 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4747
b0e77b9c
PZ		 4748 /* pipesrc controls the size that is scaled from, which should
4749 * always be the user's requested size.
4750 */
4751 I915_WRITE(PIPESRC(pipe),
4752 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4753}
4754
1bd1bd80
DV		 4755static void intel_get_pipe_timings(struct intel_crtc *crtc,
4756 struct intel_crtc_config *pipe_config)
4757{
4758 struct drm_device *dev = crtc->base.dev;
4759 struct drm_i915_private *dev_priv = dev->dev_private;
4760 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4761 uint32_t tmp;
4762
4763 tmp = I915_READ(HTOTAL(cpu_transcoder));
4764 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4765 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4766 tmp = I915_READ(HBLANK(cpu_transcoder));
4767 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4768 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4769 tmp = I915_READ(HSYNC(cpu_transcoder));
4770 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4771 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4772
4773 tmp = I915_READ(VTOTAL(cpu_transcoder));
4774 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4775 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4776 tmp = I915_READ(VBLANK(cpu_transcoder));
4777 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4778 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4779 tmp = I915_READ(VSYNC(cpu_transcoder));
4780 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4781 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4782
4783 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4784 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4785 pipe_config->adjusted_mode.crtc_vtotal += 1;
4786 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4787 }
4788
4789 tmp = I915_READ(PIPESRC(crtc->pipe));
4790 pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4791 pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4792}
4793
babea61d
JB		 4794static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
4795 struct intel_crtc_config *pipe_config)
4796{
4797 struct drm_crtc *crtc = &intel_crtc->base;
4798
4799 crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
4800 crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
4801 crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
4802 crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
4803
4804 crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
4805 crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
4806 crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
4807 crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
4808
4809 crtc->mode.flags = pipe_config->adjusted_mode.flags;
4810
4811 crtc->mode.clock = pipe_config->adjusted_mode.clock;
4812 crtc->mode.flags |= pipe_config->adjusted_mode.flags;
4813}
4814
84b046f3
DV		 4815static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4816{
4817 struct drm_device *dev = intel_crtc->base.dev;
4818 struct drm_i915_private *dev_priv = dev->dev_private;
4819 uint32_t pipeconf;
4820
9f11a9e4 4821 pipeconf = 0;
84b046f3
DV		 4822
4823 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4824 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4825 * core speed.
4826 *
4827 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4828 * pipe == 0 check?
4829 */
a2b076b6 4830 if (intel_crtc->config.adjusted_mode.clock >
84b046f3
DV		 4831 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4832 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3
DV		 4833 }
4834
ff9ce46e
DV		 4835 /* only g4x and later have fancy bpc/dither controls */
4836 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e
DV		 4837 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4838 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4839 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 4840 PIPECONF_DITHER_TYPE_SP;
84b046f3 4841
ff9ce46e
DV		 4842 switch (intel_crtc->config.pipe_bpp) {
4843 case 18:
4844 pipeconf |= PIPECONF_6BPC;
4845 break;
4846 case 24:
4847 pipeconf |= PIPECONF_8BPC;
4848 break;
4849 case 30:
4850 pipeconf |= PIPECONF_10BPC;
4851 break;
4852 default:
4853 /* Case prevented by intel_choose_pipe_bpp_dither. */
4854 BUG();
84b046f3
DV		 4855 }
4856 }
4857
4858 if (HAS_PIPE_CXSR(dev)) {
4859 if (intel_crtc->lowfreq_avail) {
4860 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4861 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4862 } else {
4863 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 4864 }
4865 }
4866
84b046f3
DV		 4867 if (!IS_GEN2(dev) &&
4868 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4869 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4870 else
4871 pipeconf |= PIPECONF_PROGRESSIVE;
4872
9f11a9e4
DV		 4873 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4874 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 4875
84b046f3
DV		 4876 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4877 POSTING_READ(PIPECONF(intel_crtc->pipe));
4878}
4879
f564048e 4880static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4881 int x, int y,
94352cf9 4882 struct drm_framebuffer *fb)
79e53945
JB		 4883{
4884 struct drm_device *dev = crtc->dev;
4885 struct drm_i915_private *dev_priv = dev->dev_private;
4886 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5 4887 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
79e53945 4888 int pipe = intel_crtc->pipe;
80824003 4889 int plane = intel_crtc->plane;
c751ce4f 4890 int refclk, num_connectors = 0;
652c393a 4891 intel_clock_t clock, reduced_clock;
84b046f3 4892 u32 dspcntr;
a16af721 4893 bool ok, has_reduced_clock = false;
e9fd1c02 4894 bool is_lvds = false, is_dsi = false;
5eddb70b 4895 struct intel_encoder *encoder;
d4906093 4896 const intel_limit_t *limit;
5c3b82e2 4897 int ret;
79e53945 4898
6c2b7c12 4899 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4900 switch (encoder->type) {
79e53945
JB		 4901 case INTEL_OUTPUT_LVDS:
4902 is_lvds = true;
4903 break;
e9fd1c02
JN		 4904 case INTEL_OUTPUT_DSI:
4905 is_dsi = true;
4906 break;
79e53945 4907 }
43565a06 4908
c751ce4f 4909 num_connectors++;
79e53945
JB		 4910 }
4911
c65d77d8 4912 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4913
65ce4bf5 4914 if (!is_dsi && !intel_crtc->config.clock_set) {
e9fd1c02
JN		 4915 /*
4916 * Returns a set of divisors for the desired target clock with
4917 * the given refclk, or FALSE. The returned values represent
4918 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
4919 * 2) / p1 / p2.
4920 */
4921 limit = intel_limit(crtc, refclk);
4922 ok = dev_priv->display.find_dpll(limit, crtc,
4923 intel_crtc->config.port_clock,
4924 refclk, NULL, &clock);
4925 if (!ok && !intel_crtc->config.clock_set) {
4926 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4927 return -EINVAL;
4928 }
79e53945
JB		 4929 }
4930
cda4b7d3 4931 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4932 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4933
e9fd1c02 4934 if (!is_dsi && is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4935 /*
4936 * Ensure we match the reduced clock's P to the target clock.
4937 * If the clocks don't match, we can't switch the display clock
4938 * by using the FP0/FP1. In such case we will disable the LVDS
4939 * downclock feature.
4940 */
65ce4bf5 4941 limit = intel_limit(crtc, refclk);
ee9300bb
DV		 4942 has_reduced_clock =
4943 dev_priv->display.find_dpll(limit, crtc,
5eddb70b 4944 dev_priv->lvds_downclock,
ee9300bb 4945 refclk, &clock,
5eddb70b 4946 &reduced_clock);
7026d4ac 4947 }
f47709a9
DV		 4948 /* Compat-code for transition, will disappear. */
4949 if (!intel_crtc->config.clock_set) {
4950 intel_crtc->config.dpll.n = clock.n;
4951 intel_crtc->config.dpll.m1 = clock.m1;
4952 intel_crtc->config.dpll.m2 = clock.m2;
4953 intel_crtc->config.dpll.p1 = clock.p1;
4954 intel_crtc->config.dpll.p2 = clock.p2;
4955 }
7026d4ac 4956
e9fd1c02 4957 if (IS_GEN2(dev)) {
8a654f3b 4958 i8xx_update_pll(intel_crtc,
2a8f64ca
VP		 4959 has_reduced_clock ? &reduced_clock : NULL,
4960 num_connectors);
e9fd1c02
JN		 4961 } else if (IS_VALLEYVIEW(dev)) {
4962 if (!is_dsi)
4963 vlv_update_pll(intel_crtc);
4964 } else {
f47709a9 4965 i9xx_update_pll(intel_crtc,
eb1cbe48 4966 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 4967 num_connectors);
e9fd1c02 4968 }
79e53945 4969
79e53945
JB		 4970 /* Set up the display plane register */
4971 dspcntr = DISPPLANE_GAMMA_ENABLE;
4972
da6ecc5d
JB		 4973 if (!IS_VALLEYVIEW(dev)) {
4974 if (pipe == 0)
4975 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4976 else
4977 dspcntr |= DISPPLANE_SEL_PIPE_B;
4978 }
79e53945 4979
8a654f3b 4980 intel_set_pipe_timings(intel_crtc);
5eddb70b
CW		 4981
4982 /* pipesrc and dspsize control the size that is scaled from,
4983 * which should always be the user's requested size.
79e53945 4984 */
929c77fb
EA		 4985 I915_WRITE(DSPSIZE(plane),
4986 ((mode->vdisplay - 1) << 16) |
4987 (mode->hdisplay - 1));
4988 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4989
84b046f3
DV		 4990 i9xx_set_pipeconf(intel_crtc);
4991
f564048e
EA		 4992 I915_WRITE(DSPCNTR(plane), dspcntr);
4993 POSTING_READ(DSPCNTR(plane));
4994
94352cf9 4995 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e 4996
f564048e
EA		 4997 return ret;
4998}
4999
2fa2fe9a
DV		 5000static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5001 struct intel_crtc_config *pipe_config)
5002{
5003 struct drm_device *dev = crtc->base.dev;
5004 struct drm_i915_private *dev_priv = dev->dev_private;
5005 uint32_t tmp;
5006
5007 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 5008 if (!(tmp & PFIT_ENABLE))
5009 return;
2fa2fe9a 5010
06922821 5011 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 5012 if (INTEL_INFO(dev)->gen < 4) {
5013 if (crtc->pipe != PIPE_B)
5014 return;
2fa2fe9a
DV		 5015 } else {
5016 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5017 return;
5018 }
5019
06922821 5020 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 5021 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5022 if (INTEL_INFO(dev)->gen < 5)
5023 pipe_config->gmch_pfit.lvds_border_bits =
5024 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5025}
5026
0e8ffe1b
DV		 5027static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5028 struct intel_crtc_config *pipe_config)
5029{
5030 struct drm_device *dev = crtc->base.dev;
5031 struct drm_i915_private *dev_priv = dev->dev_private;
5032 uint32_t tmp;
5033
e143a21c 5034 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 5035 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 5036
0e8ffe1b
DV		 5037 tmp = I915_READ(PIPECONF(crtc->pipe));
5038 if (!(tmp & PIPECONF_ENABLE))
5039 return false;
5040
42571aef
VS		 5041 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5042 switch (tmp & PIPECONF_BPC_MASK) {
5043 case PIPECONF_6BPC:
5044 pipe_config->pipe_bpp = 18;
5045 break;
5046 case PIPECONF_8BPC:
5047 pipe_config->pipe_bpp = 24;
5048 break;
5049 case PIPECONF_10BPC:
5050 pipe_config->pipe_bpp = 30;
5051 break;
5052 default:
5053 break;
5054 }
5055 }
5056
1bd1bd80
DV		 5057 intel_get_pipe_timings(crtc, pipe_config);
5058
2fa2fe9a
DV		 5059 i9xx_get_pfit_config(crtc, pipe_config);
5060
6c49f241
DV		 5061 if (INTEL_INFO(dev)->gen >= 4) {
5062 tmp = I915_READ(DPLL_MD(crtc->pipe));
5063 pipe_config->pixel_multiplier =
5064 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5065 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 5066 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 5067 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5068 tmp = I915_READ(DPLL(crtc->pipe));
5069 pipe_config->pixel_multiplier =
5070 ((tmp & SDVO_MULTIPLIER_MASK)
5071 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5072 } else {
5073 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5074 * port and will be fixed up in the encoder->get_config
5075 * function. */
5076 pipe_config->pixel_multiplier = 1;
5077 }
8bcc2795
DV		 5078 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5079 if (!IS_VALLEYVIEW(dev)) {
5080 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5081 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 5082 } else {
5083 /* Mask out read-only status bits. */
5084 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5085 DPLL_PORTC_READY_MASK |
5086 DPLL_PORTB_READY_MASK);
8bcc2795 5087 }
6c49f241 5088
18442d08
VS		 5089 i9xx_crtc_clock_get(crtc, pipe_config);
5090
0e8ffe1b
DV		 5091 return true;
5092}
5093
dde86e2d 5094static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 5095{
5096 struct drm_i915_private *dev_priv = dev->dev_private;
5097 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 5098 struct intel_encoder *encoder;
74cfd7ac 5099 u32 val, final;
13d83a67 5100 bool has_lvds = false;
199e5d79 5101 bool has_cpu_edp = false;
199e5d79 5102 bool has_panel = false;
99eb6a01
KP		 5103 bool has_ck505 = false;
5104 bool can_ssc = false;
13d83a67
JB		 5105
5106 /* We need to take the global config into account */
199e5d79
KP		 5107 list_for_each_entry(encoder, &mode_config->encoder_list,
5108 base.head) {
5109 switch (encoder->type) {
5110 case INTEL_OUTPUT_LVDS:
5111 has_panel = true;
5112 has_lvds = true;
5113 break;
5114 case INTEL_OUTPUT_EDP:
5115 has_panel = true;
2de6905f 5116 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 5117 has_cpu_edp = true;
5118 break;
13d83a67
JB		 5119 }
5120 }
5121
99eb6a01 5122 if (HAS_PCH_IBX(dev)) {
41aa3448 5123 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 5124 can_ssc = has_ck505;
5125 } else {
5126 has_ck505 = false;
5127 can_ssc = true;
5128 }
5129
2de6905f
ID		 5130 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5131 has_panel, has_lvds, has_ck505);
13d83a67
JB		 5132
5133 /* Ironlake: try to setup display ref clock before DPLL
5134 * enabling. This is only under driver's control after
5135 * PCH B stepping, previous chipset stepping should be
5136 * ignoring this setting.
5137 */
74cfd7ac
CW		 5138 val = I915_READ(PCH_DREF_CONTROL);
5139
5140 /* As we must carefully and slowly disable/enable each source in turn,
5141 * compute the final state we want first and check if we need to
5142 * make any changes at all.
5143 */
5144 final = val;
5145 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5146 if (has_ck505)
5147 final |= DREF_NONSPREAD_CK505_ENABLE;
5148 else
5149 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5150
5151 final &= ~DREF_SSC_SOURCE_MASK;
5152 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5153 final &= ~DREF_SSC1_ENABLE;
5154
5155 if (has_panel) {
5156 final |= DREF_SSC_SOURCE_ENABLE;
5157
5158 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5159 final |= DREF_SSC1_ENABLE;
5160
5161 if (has_cpu_edp) {
5162 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5163 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5164 else
5165 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5166 } else
5167 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5168 } else {
5169 final |= DREF_SSC_SOURCE_DISABLE;
5170 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5171 }
5172
5173 if (final == val)
5174 return;
5175
13d83a67 5176 /* Always enable nonspread source */
74cfd7ac 5177 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5178
99eb6a01 5179 if (has_ck505)
74cfd7ac 5180 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 5181 else
74cfd7ac 5182 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5183
199e5d79 5184 if (has_panel) {
74cfd7ac
CW		 5185 val &= ~DREF_SSC_SOURCE_MASK;
5186 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5187
199e5d79 5188 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5189 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5190 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 5191 val |= DREF_SSC1_ENABLE;
e77166b5 5192 } else
74cfd7ac 5193 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 5194
5195 /* Get SSC going before enabling the outputs */
74cfd7ac 5196 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5197 POSTING_READ(PCH_DREF_CONTROL);
5198 udelay(200);
5199
74cfd7ac 5200 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 5201
5202 /* Enable CPU source on CPU attached eDP */
199e5d79 5203 if (has_cpu_edp) {
99eb6a01 5204 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5205 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 5206 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5207 }
13d83a67 5208 else
74cfd7ac 5209 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 5210 } else
74cfd7ac 5211 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5212
74cfd7ac 5213 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5214 POSTING_READ(PCH_DREF_CONTROL);
5215 udelay(200);
5216 } else {
5217 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5218
74cfd7ac 5219 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 5220
5221 /* Turn off CPU output */
74cfd7ac 5222 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5223
74cfd7ac 5224 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5225 POSTING_READ(PCH_DREF_CONTROL);
5226 udelay(200);
5227
5228 /* Turn off the SSC source */
74cfd7ac
CW		 5229 val &= ~DREF_SSC_SOURCE_MASK;
5230 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 5231
5232 /* Turn off SSC1 */
74cfd7ac 5233 val &= ~DREF_SSC1_ENABLE;
199e5d79 5234
74cfd7ac 5235 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 5236 POSTING_READ(PCH_DREF_CONTROL);
5237 udelay(200);
5238 }
74cfd7ac
CW		 5239
5240 BUG_ON(val != final);
13d83a67
JB		 5241}
5242
f31f2d55 5243static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 5244{
f31f2d55 5245 uint32_t tmp;
dde86e2d 5246
0ff066a9
PZ		 5247 tmp = I915_READ(SOUTH_CHICKEN2);
5248 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5249 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 5250
0ff066a9
PZ		 5251 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5252 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5253 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 5254
0ff066a9
PZ		 5255 tmp = I915_READ(SOUTH_CHICKEN2);
5256 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5257 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 5258
0ff066a9
PZ		 5259 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5260 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5261 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 5262}
5263
5264/* WaMPhyProgramming:hsw */
5265static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5266{
5267 uint32_t tmp;
dde86e2d
PZ		 5268
5269 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5270 tmp &= ~(0xFF << 24);
5271 tmp |= (0x12 << 24);
5272 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5273
dde86e2d
PZ		 5274 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5275 tmp |= (1 << 11);
5276 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5277
5278 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5279 tmp |= (1 << 11);
5280 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5281
dde86e2d
PZ		 5282 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5283 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5284 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5285
5286 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5287 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5288 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5289
0ff066a9
PZ		 5290 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5291 tmp &= ~(7 << 13);
5292 tmp |= (5 << 13);
5293 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 5294
0ff066a9
PZ		 5295 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5296 tmp &= ~(7 << 13);
5297 tmp |= (5 << 13);
5298 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 5299
5300 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5301 tmp &= ~0xFF;
5302 tmp |= 0x1C;
5303 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5304
5305 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5306 tmp &= ~0xFF;
5307 tmp |= 0x1C;
5308 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5309
5310 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5311 tmp &= ~(0xFF << 16);
5312 tmp |= (0x1C << 16);
5313 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5314
5315 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5316 tmp &= ~(0xFF << 16);
5317 tmp |= (0x1C << 16);
5318 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5319
0ff066a9
PZ		 5320 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5321 tmp |= (1 << 27);
5322 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 5323
0ff066a9
PZ		 5324 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5325 tmp |= (1 << 27);
5326 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 5327
0ff066a9
PZ		 5328 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5329 tmp &= ~(0xF << 28);
5330 tmp |= (4 << 28);
5331 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 5332
0ff066a9
PZ		 5333 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5334 tmp &= ~(0xF << 28);
5335 tmp |= (4 << 28);
5336 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 5337}
5338
2fa86a1f
PZ		 5339/* Implements 3 different sequences from BSpec chapter "Display iCLK
5340 * Programming" based on the parameters passed:
5341 * - Sequence to enable CLKOUT_DP
5342 * - Sequence to enable CLKOUT_DP without spread
5343 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5344 */
5345static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5346 bool with_fdi)
f31f2d55
PZ		 5347{
5348 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 5349 uint32_t reg, tmp;
5350
5351 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5352 with_spread = true;
5353 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5354 with_fdi, "LP PCH doesn't have FDI\n"))
5355 with_fdi = false;
f31f2d55
PZ		 5356
5357 mutex_lock(&dev_priv->dpio_lock);
5358
5359 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5360 tmp &= ~SBI_SSCCTL_DISABLE;
5361 tmp |= SBI_SSCCTL_PATHALT;
5362 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5363
5364 udelay(24);
5365
2fa86a1f
PZ		 5366 if (with_spread) {
5367 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5368 tmp &= ~SBI_SSCCTL_PATHALT;
5369 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 5370
2fa86a1f
PZ		 5371 if (with_fdi) {
5372 lpt_reset_fdi_mphy(dev_priv);
5373 lpt_program_fdi_mphy(dev_priv);
5374 }
5375 }
dde86e2d 5376
2fa86a1f
PZ		 5377 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5378 SBI_GEN0 : SBI_DBUFF0;
5379 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5380 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5381 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246
DV		 5382
5383 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5384}
5385
47701c3b
PZ		 5386/* Sequence to disable CLKOUT_DP */
5387static void lpt_disable_clkout_dp(struct drm_device *dev)
5388{
5389 struct drm_i915_private *dev_priv = dev->dev_private;
5390 uint32_t reg, tmp;
5391
5392 mutex_lock(&dev_priv->dpio_lock);
5393
5394 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5395 SBI_GEN0 : SBI_DBUFF0;
5396 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5397 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5398 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5399
5400 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5401 if (!(tmp & SBI_SSCCTL_DISABLE)) {
5402 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5403 tmp |= SBI_SSCCTL_PATHALT;
5404 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5405 udelay(32);
5406 }
5407 tmp |= SBI_SSCCTL_DISABLE;
5408 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5409 }
5410
5411 mutex_unlock(&dev_priv->dpio_lock);
5412}
5413
bf8fa3d3
PZ		 5414static void lpt_init_pch_refclk(struct drm_device *dev)
5415{
5416 struct drm_mode_config *mode_config = &dev->mode_config;
5417 struct intel_encoder *encoder;
5418 bool has_vga = false;
5419
5420 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5421 switch (encoder->type) {
5422 case INTEL_OUTPUT_ANALOG:
5423 has_vga = true;
5424 break;
5425 }
5426 }
5427
47701c3b
PZ		 5428 if (has_vga)
5429 lpt_enable_clkout_dp(dev, true, true);
5430 else
5431 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 5432}
5433
dde86e2d
PZ		 5434/*
5435 * Initialize reference clocks when the driver loads
5436 */
5437void intel_init_pch_refclk(struct drm_device *dev)
5438{
5439 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5440 ironlake_init_pch_refclk(dev);
5441 else if (HAS_PCH_LPT(dev))
5442 lpt_init_pch_refclk(dev);
5443}
5444
d9d444cb
JB		 5445static int ironlake_get_refclk(struct drm_crtc *crtc)
5446{
5447 struct drm_device *dev = crtc->dev;
5448 struct drm_i915_private *dev_priv = dev->dev_private;
5449 struct intel_encoder *encoder;
d9d444cb
JB		 5450 int num_connectors = 0;
5451 bool is_lvds = false;
5452
6c2b7c12 5453 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5454 switch (encoder->type) {
5455 case INTEL_OUTPUT_LVDS:
5456 is_lvds = true;
5457 break;
d9d444cb
JB		 5458 }
5459 num_connectors++;
5460 }
5461
5462 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5463 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
41aa3448
RV		 5464 dev_priv->vbt.lvds_ssc_freq);
5465 return dev_priv->vbt.lvds_ssc_freq * 1000;
d9d444cb
JB		 5466 }
5467
5468 return 120000;
5469}
5470
6ff93609 5471static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 5472{
c8203565 5473 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5474 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5475 int pipe = intel_crtc->pipe;
c8203565
PZ		 5476 uint32_t val;
5477
78114071 5478 val = 0;
c8203565 5479
965e0c48 5480 switch (intel_crtc->config.pipe_bpp) {
c8203565 5481 case 18:
dfd07d72 5482 val |= PIPECONF_6BPC;
c8203565
PZ		 5483 break;
5484 case 24:
dfd07d72 5485 val |= PIPECONF_8BPC;
c8203565
PZ		 5486 break;
5487 case 30:
dfd07d72 5488 val |= PIPECONF_10BPC;
c8203565
PZ		 5489 break;
5490 case 36:
dfd07d72 5491 val |= PIPECONF_12BPC;
c8203565
PZ		 5492 break;
5493 default:
cc769b62
PZ		 5494 /* Case prevented by intel_choose_pipe_bpp_dither. */
5495 BUG();
c8203565
PZ		 5496 }
5497
d8b32247 5498 if (intel_crtc->config.dither)
c8203565
PZ		 5499 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5500
6ff93609 5501 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 5502 val |= PIPECONF_INTERLACED_ILK;
5503 else
5504 val |= PIPECONF_PROGRESSIVE;
5505
50f3b016 5506 if (intel_crtc->config.limited_color_range)
3685a8f3 5507 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 5508
c8203565
PZ		 5509 I915_WRITE(PIPECONF(pipe), val);
5510 POSTING_READ(PIPECONF(pipe));
5511}
5512
86d3efce
VS		 5513/*
5514 * Set up the pipe CSC unit.
5515 *
5516 * Currently only full range RGB to limited range RGB conversion
5517 * is supported, but eventually this should handle various
5518 * RGB<->YCbCr scenarios as well.
5519 */
50f3b016 5520static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5521{
5522 struct drm_device *dev = crtc->dev;
5523 struct drm_i915_private *dev_priv = dev->dev_private;
5524 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5525 int pipe = intel_crtc->pipe;
5526 uint16_t coeff = 0x7800; /* 1.0 */
5527
5528 /*
5529 * TODO: Check what kind of values actually come out of the pipe
5530 * with these coeff/postoff values and adjust to get the best
5531 * accuracy. Perhaps we even need to take the bpc value into
5532 * consideration.
5533 */
5534
50f3b016 5535 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5536 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5537
5538 /*
5539 * GY/GU and RY/RU should be the other way around according
5540 * to BSpec, but reality doesn't agree. Just set them up in
5541 * a way that results in the correct picture.
5542 */
5543 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5544 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5545
5546 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5547 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5548
5549 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5550 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5551
5552 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5553 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5554 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5555
5556 if (INTEL_INFO(dev)->gen > 6) {
5557 uint16_t postoff = 0;
5558
50f3b016 5559 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5560 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5561
5562 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5563 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5564 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5565
5566 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5567 } else {
5568 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5569
50f3b016 5570 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5571 mode |= CSC_BLACK_SCREEN_OFFSET;
5572
5573 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5574 }
5575}
5576
6ff93609 5577static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38
PZ		 5578{
5579 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5580 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5581 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5582 uint32_t val;
5583
3eff4faa 5584 val = 0;
ee2b0b38 5585
d8b32247 5586 if (intel_crtc->config.dither)
ee2b0b38
PZ		 5587 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5588
6ff93609 5589 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 5590 val |= PIPECONF_INTERLACED_ILK;
5591 else
5592 val |= PIPECONF_PROGRESSIVE;
5593
702e7a56
PZ		 5594 I915_WRITE(PIPECONF(cpu_transcoder), val);
5595 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 5596
5597 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5598 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
ee2b0b38
PZ		 5599}
5600
6591c6e4 5601static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6591c6e4
PZ		 5602 intel_clock_t *clock,
5603 bool *has_reduced_clock,
5604 intel_clock_t *reduced_clock)
5605{
5606 struct drm_device *dev = crtc->dev;
5607 struct drm_i915_private *dev_priv = dev->dev_private;
5608 struct intel_encoder *intel_encoder;
5609 int refclk;
d4906093 5610 const intel_limit_t *limit;
a16af721 5611 bool ret, is_lvds = false;
79e53945 5612
6591c6e4
PZ		 5613 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5614 switch (intel_encoder->type) {
79e53945
JB		 5615 case INTEL_OUTPUT_LVDS:
5616 is_lvds = true;
5617 break;
79e53945
JB		 5618 }
5619 }
5620
d9d444cb 5621 refclk = ironlake_get_refclk(crtc);
79e53945 5622
d4906093
ML		 5623 /*
5624 * Returns a set of divisors for the desired target clock with the given
5625 * refclk, or FALSE. The returned values represent the clock equation:
5626 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5627 */
1b894b59 5628 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 5629 ret = dev_priv->display.find_dpll(limit, crtc,
5630 to_intel_crtc(crtc)->config.port_clock,
ee9300bb 5631 refclk, NULL, clock);
6591c6e4
PZ		 5632 if (!ret)
5633 return false;
cda4b7d3 5634
ddc9003c 5635 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5636 /*
5637 * Ensure we match the reduced clock's P to the target clock.
5638 * If the clocks don't match, we can't switch the display clock
5639 * by using the FP0/FP1. In such case we will disable the LVDS
5640 * downclock feature.
5641 */
ee9300bb
DV		 5642 *has_reduced_clock =
5643 dev_priv->display.find_dpll(limit, crtc,
5644 dev_priv->lvds_downclock,
5645 refclk, clock,
5646 reduced_clock);
652c393a 5647 }
61e9653f 5648
6591c6e4
PZ		 5649 return true;
5650}
5651
01a415fd
DV		 5652static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5653{
5654 struct drm_i915_private *dev_priv = dev->dev_private;
5655 uint32_t temp;
5656
5657 temp = I915_READ(SOUTH_CHICKEN1);
5658 if (temp & FDI_BC_BIFURCATION_SELECT)
5659 return;
5660
5661 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5662 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5663
5664 temp |= FDI_BC_BIFURCATION_SELECT;
5665 DRM_DEBUG_KMS("enabling fdi C rx\n");
5666 I915_WRITE(SOUTH_CHICKEN1, temp);
5667 POSTING_READ(SOUTH_CHICKEN1);
5668}
5669
ebfd86fd 5670static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
01a415fd
DV		 5671{
5672 struct drm_device *dev = intel_crtc->base.dev;
5673 struct drm_i915_private *dev_priv = dev->dev_private;
01a415fd
DV		 5674
5675 switch (intel_crtc->pipe) {
5676 case PIPE_A:
ebfd86fd 5677 break;
01a415fd 5678 case PIPE_B:
ebfd86fd 5679 if (intel_crtc->config.fdi_lanes > 2)
01a415fd
DV		 5680 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5681 else
5682 cpt_enable_fdi_bc_bifurcation(dev);
5683
ebfd86fd 5684 break;
01a415fd 5685 case PIPE_C:
01a415fd
DV		 5686 cpt_enable_fdi_bc_bifurcation(dev);
5687
ebfd86fd 5688 break;
01a415fd
DV		 5689 default:
5690 BUG();
5691 }
5692}
5693
d4b1931c
PZ		 5694int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5695{
5696 /*
5697 * Account for spread spectrum to avoid
5698 * oversubscribing the link. Max center spread
5699 * is 2.5%; use 5% for safety's sake.
5700 */
5701 u32 bps = target_clock * bpp * 21 / 20;
5702 return bps / (link_bw * 8) + 1;
5703}
5704
7429e9d4 5705static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 5706{
7429e9d4 5707 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 5708}
5709
de13a2e3 5710static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7429e9d4 5711 u32 *fp,
9a7c7890 5712 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5713{
de13a2e3 5714 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5715 struct drm_device *dev = crtc->dev;
5716 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5717 struct intel_encoder *intel_encoder;
5718 uint32_t dpll;
6cc5f341 5719 int factor, num_connectors = 0;
09ede541 5720 bool is_lvds = false, is_sdvo = false;
79e53945 5721
de13a2e3
PZ		 5722 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5723 switch (intel_encoder->type) {
79e53945
JB		 5724 case INTEL_OUTPUT_LVDS:
5725 is_lvds = true;
5726 break;
5727 case INTEL_OUTPUT_SDVO:
7d57382e 5728 case INTEL_OUTPUT_HDMI:
79e53945 5729 is_sdvo = true;
79e53945 5730 break;
79e53945 5731 }
43565a06 5732
c751ce4f 5733 num_connectors++;
79e53945 5734 }
79e53945 5735
c1858123 5736 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5737 factor = 21;
5738 if (is_lvds) {
5739 if ((intel_panel_use_ssc(dev_priv) &&
41aa3448 5740 dev_priv->vbt.lvds_ssc_freq == 100) ||
f0b44056 5741 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 5742 factor = 25;
09ede541 5743 } else if (intel_crtc->config.sdvo_tv_clock)
8febb297 5744 factor = 20;
c1858123 5745
7429e9d4 5746 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7d0ac5b7 5747 *fp |= FP_CB_TUNE;
2c07245f 5748
9a7c7890
DV		 5749 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5750 *fp2 |= FP_CB_TUNE;
5751
5eddb70b 5752 dpll = 0;
2c07245f 5753
a07d6787
EA		 5754 if (is_lvds)
5755 dpll |= DPLLB_MODE_LVDS;
5756 else
5757 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 5758
ef1b460d
DV		 5759 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5760 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 5761
5762 if (is_sdvo)
4a33e48d 5763 dpll |= DPLL_SDVO_HIGH_SPEED;
9566e9af 5764 if (intel_crtc->config.has_dp_encoder)
4a33e48d 5765 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 5766
a07d6787 5767 /* compute bitmask from p1 value */
7429e9d4 5768 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5769 /* also FPA1 */
7429e9d4 5770 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5771
7429e9d4 5772 switch (intel_crtc->config.dpll.p2) {
a07d6787
EA		 5773 case 5:
5774 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5775 break;
5776 case 7:
5777 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5778 break;
5779 case 10:
5780 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5781 break;
5782 case 14:
5783 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5784 break;
79e53945
JB		 5785 }
5786
b4c09f3b 5787 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5788 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5789 else
5790 dpll |= PLL_REF_INPUT_DREFCLK;
5791
959e16d6 5792 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 5793}
5794
5795static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5796 int x, int y,
5797 struct drm_framebuffer *fb)
5798{
5799 struct drm_device *dev = crtc->dev;
5800 struct drm_i915_private *dev_priv = dev->dev_private;
5801 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5802 int pipe = intel_crtc->pipe;
5803 int plane = intel_crtc->plane;
5804 int num_connectors = 0;
5805 intel_clock_t clock, reduced_clock;
cbbab5bd 5806 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 5807 bool ok, has_reduced_clock = false;
8b47047b 5808 bool is_lvds = false;
de13a2e3 5809 struct intel_encoder *encoder;
e2b78267 5810 struct intel_shared_dpll *pll;
de13a2e3 5811 int ret;
de13a2e3
PZ		 5812
5813 for_each_encoder_on_crtc(dev, crtc, encoder) {
5814 switch (encoder->type) {
5815 case INTEL_OUTPUT_LVDS:
5816 is_lvds = true;
5817 break;
de13a2e3
PZ		 5818 }
5819
5820 num_connectors++;
a07d6787 5821 }
79e53945 5822
5dc5298b
PZ		 5823 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5824 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5825
ff9a6750 5826 ok = ironlake_compute_clocks(crtc, &clock,
de13a2e3 5827 &has_reduced_clock, &reduced_clock);
ee9300bb 5828 if (!ok && !intel_crtc->config.clock_set) {
de13a2e3
PZ		 5829 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5830 return -EINVAL;
79e53945 5831 }
f47709a9
DV		 5832 /* Compat-code for transition, will disappear. */
5833 if (!intel_crtc->config.clock_set) {
5834 intel_crtc->config.dpll.n = clock.n;
5835 intel_crtc->config.dpll.m1 = clock.m1;
5836 intel_crtc->config.dpll.m2 = clock.m2;
5837 intel_crtc->config.dpll.p1 = clock.p1;
5838 intel_crtc->config.dpll.p2 = clock.p2;
5839 }
79e53945 5840
de13a2e3
PZ		 5841 /* Ensure that the cursor is valid for the new mode before changing... */
5842 intel_crtc_update_cursor(crtc, true);
5843
5dc5298b 5844 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 5845 if (intel_crtc->config.has_pch_encoder) {
7429e9d4 5846 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
cbbab5bd 5847 if (has_reduced_clock)
7429e9d4 5848 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 5849
7429e9d4 5850 dpll = ironlake_compute_dpll(intel_crtc,
cbbab5bd
DV		 5851 &fp, &reduced_clock,
5852 has_reduced_clock ? &fp2 : NULL);
5853
959e16d6 5854 intel_crtc->config.dpll_hw_state.dpll = dpll;
66e985c0
DV		 5855 intel_crtc->config.dpll_hw_state.fp0 = fp;
5856 if (has_reduced_clock)
5857 intel_crtc->config.dpll_hw_state.fp1 = fp2;
5858 else
5859 intel_crtc->config.dpll_hw_state.fp1 = fp;
5860
b89a1d39 5861 pll = intel_get_shared_dpll(intel_crtc);
ee7b9f93 5862 if (pll == NULL) {
84f44ce7
VS		 5863 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5864 pipe_name(pipe));
4b645f14
JB		 5865 return -EINVAL;
5866 }
ee7b9f93 5867 } else
e72f9fbf 5868 intel_put_shared_dpll(intel_crtc);
79e53945 5869
03afc4a2
DV		 5870 if (intel_crtc->config.has_dp_encoder)
5871 intel_dp_set_m_n(intel_crtc);
79e53945 5872
bcd644e0
DV		 5873 if (is_lvds && has_reduced_clock && i915_powersave)
5874 intel_crtc->lowfreq_avail = true;
5875 else
5876 intel_crtc->lowfreq_avail = false;
e2b78267
DV		 5877
5878 if (intel_crtc->config.has_pch_encoder) {
5879 pll = intel_crtc_to_shared_dpll(intel_crtc);
5880
652c393a
JB		 5881 }
5882
8a654f3b 5883 intel_set_pipe_timings(intel_crtc);
5eddb70b 5884
ca3a0ff8 5885 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5886 intel_cpu_transcoder_set_m_n(intel_crtc,
5887 &intel_crtc->config.fdi_m_n);
5888 }
2c07245f 5889
ebfd86fd
DV		 5890 if (IS_IVYBRIDGE(dev))
5891 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
79e53945 5892
6ff93609 5893 ironlake_set_pipeconf(crtc);
79e53945 5894
a1f9e77e
PZ		 5895 /* Set up the display plane register */
5896 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5897 POSTING_READ(DSPCNTR(plane));
79e53945 5898
94352cf9 5899 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd 5900
1857e1da 5901 return ret;
79e53945
JB		 5902}
5903
eb14cb74
VS		 5904static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
5905 struct intel_link_m_n *m_n)
5906{
5907 struct drm_device *dev = crtc->base.dev;
5908 struct drm_i915_private *dev_priv = dev->dev_private;
5909 enum pipe pipe = crtc->pipe;
5910
5911 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
5912 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
5913 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
5914 & ~TU_SIZE_MASK;
5915 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
5916 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
5917 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5918}
5919
5920static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
5921 enum transcoder transcoder,
5922 struct intel_link_m_n *m_n)
72419203
DV		 5923{
5924 struct drm_device *dev = crtc->base.dev;
5925 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74
VS		 5926 enum pipe pipe = crtc->pipe;
5927
5928 if (INTEL_INFO(dev)->gen >= 5) {
5929 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
5930 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
5931 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5932 & ~TU_SIZE_MASK;
5933 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5934 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5935 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5936 } else {
5937 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
5938 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
5939 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
5940 & ~TU_SIZE_MASK;
5941 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
5942 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
5943 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5944 }
5945}
5946
5947void intel_dp_get_m_n(struct intel_crtc *crtc,
5948 struct intel_crtc_config *pipe_config)
5949{
5950 if (crtc->config.has_pch_encoder)
5951 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
5952 else
5953 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
5954 &pipe_config->dp_m_n);
5955}
72419203 5956
eb14cb74
VS		 5957static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5958 struct intel_crtc_config *pipe_config)
5959{
5960 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
5961 &pipe_config->fdi_m_n);
72419203
DV		 5962}
5963
2fa2fe9a
DV		 5964static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5965 struct intel_crtc_config *pipe_config)
5966{
5967 struct drm_device *dev = crtc->base.dev;
5968 struct drm_i915_private *dev_priv = dev->dev_private;
5969 uint32_t tmp;
5970
5971 tmp = I915_READ(PF_CTL(crtc->pipe));
5972
5973 if (tmp & PF_ENABLE) {
5974 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5975 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 5976
5977 /* We currently do not free assignements of panel fitters on
5978 * ivb/hsw (since we don't use the higher upscaling modes which
5979 * differentiates them) so just WARN about this case for now. */
5980 if (IS_GEN7(dev)) {
5981 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5982 PF_PIPE_SEL_IVB(crtc->pipe));
5983 }
2fa2fe9a 5984 }
79e53945
JB		 5985}
5986
0e8ffe1b
DV		 5987static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5988 struct intel_crtc_config *pipe_config)
5989{
5990 struct drm_device *dev = crtc->base.dev;
5991 struct drm_i915_private *dev_priv = dev->dev_private;
5992 uint32_t tmp;
5993
e143a21c 5994 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 5995 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 5996
0e8ffe1b
DV		 5997 tmp = I915_READ(PIPECONF(crtc->pipe));
5998 if (!(tmp & PIPECONF_ENABLE))
5999 return false;
6000
42571aef
VS		 6001 switch (tmp & PIPECONF_BPC_MASK) {
6002 case PIPECONF_6BPC:
6003 pipe_config->pipe_bpp = 18;
6004 break;
6005 case PIPECONF_8BPC:
6006 pipe_config->pipe_bpp = 24;
6007 break;
6008 case PIPECONF_10BPC:
6009 pipe_config->pipe_bpp = 30;
6010 break;
6011 case PIPECONF_12BPC:
6012 pipe_config->pipe_bpp = 36;
6013 break;
6014 default:
6015 break;
6016 }
6017
ab9412ba 6018 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 6019 struct intel_shared_dpll *pll;
6020
88adfff1
DV		 6021 pipe_config->has_pch_encoder = true;
6022
627eb5a3
DV		 6023 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6024 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6025 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6026
6027 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 6028
c0d43d62 6029 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 6030 pipe_config->shared_dpll =
6031 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 6032 } else {
6033 tmp = I915_READ(PCH_DPLL_SEL);
6034 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6035 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6036 else
6037 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6038 }
66e985c0
DV		 6039
6040 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6041
6042 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6043 &pipe_config->dpll_hw_state));
c93f54cf
DV		 6044
6045 tmp = pipe_config->dpll_hw_state.dpll;
6046 pipe_config->pixel_multiplier =
6047 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6048 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 6049
6050 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 6051 } else {
6052 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 6053 }
6054
1bd1bd80
DV		 6055 intel_get_pipe_timings(crtc, pipe_config);
6056
2fa2fe9a
DV		 6057 ironlake_get_pfit_config(crtc, pipe_config);
6058
0e8ffe1b
DV		 6059 return true;
6060}
6061
be256dc7
PZ		 6062static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6063{
6064 struct drm_device *dev = dev_priv->dev;
6065 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6066 struct intel_crtc *crtc;
6067 unsigned long irqflags;
bd633a7c 6068 uint32_t val;
be256dc7
PZ		 6069
6070 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6071 WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
6072 pipe_name(crtc->pipe));
6073
6074 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6075 WARN(plls->spll_refcount, "SPLL enabled\n");
6076 WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6077 WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6078 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6079 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6080 "CPU PWM1 enabled\n");
6081 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6082 "CPU PWM2 enabled\n");
6083 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6084 "PCH PWM1 enabled\n");
6085 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6086 "Utility pin enabled\n");
6087 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6088
6089 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
6090 val = I915_READ(DEIMR);
6091 WARN((val & ~DE_PCH_EVENT_IVB) != val,
6092 "Unexpected DEIMR bits enabled: 0x%x\n", val);
6093 val = I915_READ(SDEIMR);
bd633a7c 6094 WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
be256dc7
PZ		 6095 "Unexpected SDEIMR bits enabled: 0x%x\n", val);
6096 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
6097}
6098
6099/*
6100 * This function implements pieces of two sequences from BSpec:
6101 * - Sequence for display software to disable LCPLL
6102 * - Sequence for display software to allow package C8+
6103 * The steps implemented here are just the steps that actually touch the LCPLL
6104 * register. Callers should take care of disabling all the display engine
6105 * functions, doing the mode unset, fixing interrupts, etc.
6106 */
6107void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6108 bool switch_to_fclk, bool allow_power_down)
6109{
6110 uint32_t val;
6111
6112 assert_can_disable_lcpll(dev_priv);
6113
6114 val = I915_READ(LCPLL_CTL);
6115
6116 if (switch_to_fclk) {
6117 val |= LCPLL_CD_SOURCE_FCLK;
6118 I915_WRITE(LCPLL_CTL, val);
6119
6120 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6121 LCPLL_CD_SOURCE_FCLK_DONE, 1))
6122 DRM_ERROR("Switching to FCLK failed\n");
6123
6124 val = I915_READ(LCPLL_CTL);
6125 }
6126
6127 val |= LCPLL_PLL_DISABLE;
6128 I915_WRITE(LCPLL_CTL, val);
6129 POSTING_READ(LCPLL_CTL);
6130
6131 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6132 DRM_ERROR("LCPLL still locked\n");
6133
6134 val = I915_READ(D_COMP);
6135 val |= D_COMP_COMP_DISABLE;
6136 I915_WRITE(D_COMP, val);
6137 POSTING_READ(D_COMP);
6138 ndelay(100);
6139
6140 if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6141 DRM_ERROR("D_COMP RCOMP still in progress\n");
6142
6143 if (allow_power_down) {
6144 val = I915_READ(LCPLL_CTL);
6145 val |= LCPLL_POWER_DOWN_ALLOW;
6146 I915_WRITE(LCPLL_CTL, val);
6147 POSTING_READ(LCPLL_CTL);
6148 }
6149}
6150
6151/*
6152 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6153 * source.
6154 */
6155void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6156{
6157 uint32_t val;
6158
6159 val = I915_READ(LCPLL_CTL);
6160
6161 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6162 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6163 return;
6164
215733fa
PZ		 6165 /* Make sure we're not on PC8 state before disabling PC8, otherwise
6166 * we'll hang the machine! */
6167 dev_priv->uncore.funcs.force_wake_get(dev_priv);
6168
be256dc7
PZ		 6169 if (val & LCPLL_POWER_DOWN_ALLOW) {
6170 val &= ~LCPLL_POWER_DOWN_ALLOW;
6171 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 6172 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 6173 }
6174
6175 val = I915_READ(D_COMP);
6176 val |= D_COMP_COMP_FORCE;
6177 val &= ~D_COMP_COMP_DISABLE;
6178 I915_WRITE(D_COMP, val);
35d8f2eb 6179 POSTING_READ(D_COMP);
be256dc7
PZ		 6180
6181 val = I915_READ(LCPLL_CTL);
6182 val &= ~LCPLL_PLL_DISABLE;
6183 I915_WRITE(LCPLL_CTL, val);
6184
6185 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6186 DRM_ERROR("LCPLL not locked yet\n");
6187
6188 if (val & LCPLL_CD_SOURCE_FCLK) {
6189 val = I915_READ(LCPLL_CTL);
6190 val &= ~LCPLL_CD_SOURCE_FCLK;
6191 I915_WRITE(LCPLL_CTL, val);
6192
6193 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6194 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6195 DRM_ERROR("Switching back to LCPLL failed\n");
6196 }
215733fa
PZ		 6197
6198 dev_priv->uncore.funcs.force_wake_put(dev_priv);
be256dc7
PZ		 6199}
6200
c67a470b
PZ		 6201void hsw_enable_pc8_work(struct work_struct *__work)
6202{
6203 struct drm_i915_private *dev_priv =
6204 container_of(to_delayed_work(__work), struct drm_i915_private,
6205 pc8.enable_work);
6206 struct drm_device *dev = dev_priv->dev;
6207 uint32_t val;
6208
6209 if (dev_priv->pc8.enabled)
6210 return;
6211
6212 DRM_DEBUG_KMS("Enabling package C8+\n");
6213
6214 dev_priv->pc8.enabled = true;
6215
6216 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6217 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6218 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6219 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6220 }
6221
6222 lpt_disable_clkout_dp(dev);
6223 hsw_pc8_disable_interrupts(dev);
6224 hsw_disable_lcpll(dev_priv, true, true);
6225}
6226
6227static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6228{
6229 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6230 WARN(dev_priv->pc8.disable_count < 1,
6231 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6232
6233 dev_priv->pc8.disable_count--;
6234 if (dev_priv->pc8.disable_count != 0)
6235 return;
6236
6237 schedule_delayed_work(&dev_priv->pc8.enable_work,
90058745 6238 msecs_to_jiffies(i915_pc8_timeout));
c67a470b
PZ		 6239}
6240
6241static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6242{
6243 struct drm_device *dev = dev_priv->dev;
6244 uint32_t val;
6245
6246 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6247 WARN(dev_priv->pc8.disable_count < 0,
6248 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6249
6250 dev_priv->pc8.disable_count++;
6251 if (dev_priv->pc8.disable_count != 1)
6252 return;
6253
6254 cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6255 if (!dev_priv->pc8.enabled)
6256 return;
6257
6258 DRM_DEBUG_KMS("Disabling package C8+\n");
6259
6260 hsw_restore_lcpll(dev_priv);
6261 hsw_pc8_restore_interrupts(dev);
6262 lpt_init_pch_refclk(dev);
6263
6264 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6265 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6266 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6267 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6268 }
6269
6270 intel_prepare_ddi(dev);
6271 i915_gem_init_swizzling(dev);
6272 mutex_lock(&dev_priv->rps.hw_lock);
6273 gen6_update_ring_freq(dev);
6274 mutex_unlock(&dev_priv->rps.hw_lock);
6275 dev_priv->pc8.enabled = false;
6276}
6277
6278void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6279{
6280 mutex_lock(&dev_priv->pc8.lock);
6281 __hsw_enable_package_c8(dev_priv);
6282 mutex_unlock(&dev_priv->pc8.lock);
6283}
6284
6285void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6286{
6287 mutex_lock(&dev_priv->pc8.lock);
6288 __hsw_disable_package_c8(dev_priv);
6289 mutex_unlock(&dev_priv->pc8.lock);
6290}
6291
6292static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6293{
6294 struct drm_device *dev = dev_priv->dev;
6295 struct intel_crtc *crtc;
6296 uint32_t val;
6297
6298 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6299 if (crtc->base.enabled)
6300 return false;
6301
6302 /* This case is still possible since we have the i915.disable_power_well
6303 * parameter and also the KVMr or something else might be requesting the
6304 * power well. */
6305 val = I915_READ(HSW_PWR_WELL_DRIVER);
6306 if (val != 0) {
6307 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6308 return false;
6309 }
6310
6311 return true;
6312}
6313
6314/* Since we're called from modeset_global_resources there's no way to
6315 * symmetrically increase and decrease the refcount, so we use
6316 * dev_priv->pc8.requirements_met to track whether we already have the refcount
6317 * or not.
6318 */
6319static void hsw_update_package_c8(struct drm_device *dev)
6320{
6321 struct drm_i915_private *dev_priv = dev->dev_private;
6322 bool allow;
6323
6324 if (!i915_enable_pc8)
6325 return;
6326
6327 mutex_lock(&dev_priv->pc8.lock);
6328
6329 allow = hsw_can_enable_package_c8(dev_priv);
6330
6331 if (allow == dev_priv->pc8.requirements_met)
6332 goto done;
6333
6334 dev_priv->pc8.requirements_met = allow;
6335
6336 if (allow)
6337 __hsw_enable_package_c8(dev_priv);
6338 else
6339 __hsw_disable_package_c8(dev_priv);
6340
6341done:
6342 mutex_unlock(&dev_priv->pc8.lock);
6343}
6344
6345static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6346{
6347 if (!dev_priv->pc8.gpu_idle) {
6348 dev_priv->pc8.gpu_idle = true;
6349 hsw_enable_package_c8(dev_priv);
6350 }
6351}
6352
6353static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6354{
6355 if (dev_priv->pc8.gpu_idle) {
6356 dev_priv->pc8.gpu_idle = false;
6357 hsw_disable_package_c8(dev_priv);
6358 }
be256dc7
PZ		 6359}
6360
d6dd9eb1
DV		 6361static void haswell_modeset_global_resources(struct drm_device *dev)
6362{
d6dd9eb1
DV		 6363 bool enable = false;
6364 struct intel_crtc *crtc;
d6dd9eb1
DV		 6365
6366 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
e7a639c4
DV		 6367 if (!crtc->base.enabled)
6368 continue;
d6dd9eb1 6369
e7a639c4
DV		 6370 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
6371 crtc->config.cpu_transcoder != TRANSCODER_EDP)
d6dd9eb1
DV		 6372 enable = true;
6373 }
6374
d6dd9eb1 6375 intel_set_power_well(dev, enable);
c67a470b
PZ		 6376
6377 hsw_update_package_c8(dev);
d6dd9eb1
DV		 6378}
6379
09b4ddf9 6380static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 6381 int x, int y,
6382 struct drm_framebuffer *fb)
6383{
6384 struct drm_device *dev = crtc->dev;
6385 struct drm_i915_private *dev_priv = dev->dev_private;
6386 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
09b4ddf9 6387 int plane = intel_crtc->plane;
09b4ddf9 6388 int ret;
09b4ddf9 6389
ff9a6750 6390 if (!intel_ddi_pll_mode_set(crtc))
6441ab5f
PZ		 6391 return -EINVAL;
6392
09b4ddf9
PZ		 6393 /* Ensure that the cursor is valid for the new mode before changing... */
6394 intel_crtc_update_cursor(crtc, true);
6395
03afc4a2
DV		 6396 if (intel_crtc->config.has_dp_encoder)
6397 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 6398
6399 intel_crtc->lowfreq_avail = false;
09b4ddf9 6400
8a654f3b 6401 intel_set_pipe_timings(intel_crtc);
09b4ddf9 6402
ca3a0ff8 6403 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 6404 intel_cpu_transcoder_set_m_n(intel_crtc,
6405 &intel_crtc->config.fdi_m_n);
6406 }
09b4ddf9 6407
6ff93609 6408 haswell_set_pipeconf(crtc);
09b4ddf9 6409
50f3b016 6410 intel_set_pipe_csc(crtc);
86d3efce 6411
09b4ddf9 6412 /* Set up the display plane register */
86d3efce 6413 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 6414 POSTING_READ(DSPCNTR(plane));
6415
6416 ret = intel_pipe_set_base(crtc, x, y, fb);
6417
1f803ee5 6418 return ret;
79e53945
JB		 6419}
6420
0e8ffe1b
DV		 6421static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6422 struct intel_crtc_config *pipe_config)
6423{
6424 struct drm_device *dev = crtc->base.dev;
6425 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 6426 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 6427 uint32_t tmp;
6428
e143a21c 6429 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 6430 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6431
eccb140b
DV		 6432 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6433 if (tmp & TRANS_DDI_FUNC_ENABLE) {
6434 enum pipe trans_edp_pipe;
6435 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6436 default:
6437 WARN(1, "unknown pipe linked to edp transcoder\n");
6438 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6439 case TRANS_DDI_EDP_INPUT_A_ON:
6440 trans_edp_pipe = PIPE_A;
6441 break;
6442 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6443 trans_edp_pipe = PIPE_B;
6444 break;
6445 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6446 trans_edp_pipe = PIPE_C;
6447 break;
6448 }
6449
6450 if (trans_edp_pipe == crtc->pipe)
6451 pipe_config->cpu_transcoder = TRANSCODER_EDP;
6452 }
6453
b97186f0 6454 if (!intel_display_power_enabled(dev,
eccb140b 6455 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 6456 return false;
6457
eccb140b 6458 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 6459 if (!(tmp & PIPECONF_ENABLE))
6460 return false;
6461
88adfff1 6462 /*
f196e6be 6463 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV		 6464 * DDI E. So just check whether this pipe is wired to DDI E and whether
6465 * the PCH transcoder is on.
6466 */
eccb140b 6467 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
88adfff1 6468 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
ab9412ba 6469 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
88adfff1
DV		 6470 pipe_config->has_pch_encoder = true;
6471
627eb5a3
DV		 6472 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6473 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6474 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6475
6476 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 6477 }
6478
1bd1bd80
DV		 6479 intel_get_pipe_timings(crtc, pipe_config);
6480
2fa2fe9a
DV		 6481 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6482 if (intel_display_power_enabled(dev, pfit_domain))
6483 ironlake_get_pfit_config(crtc, pipe_config);
88adfff1 6484
42db64ef
PZ		 6485 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6486 (I915_READ(IPS_CTL) & IPS_ENABLE);
6487
6c49f241
DV		 6488 pipe_config->pixel_multiplier = 1;
6489
0e8ffe1b
DV		 6490 return true;
6491}
6492
f564048e 6493static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 6494 int x, int y,
94352cf9 6495 struct drm_framebuffer *fb)
f564048e
EA		 6496{
6497 struct drm_device *dev = crtc->dev;
6498 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19 6499 struct intel_encoder *encoder;
0b701d27 6500 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5 6501 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 6502 int pipe = intel_crtc->pipe;
f564048e
EA		 6503 int ret;
6504
0b701d27 6505 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6506
b8cecdf5
DV		 6507 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6508
79e53945 6509 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6510
9256aa19
DV		 6511 if (ret != 0)
6512 return ret;
6513
6514 for_each_encoder_on_crtc(dev, crtc, encoder) {
6515 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6516 encoder->base.base.id,
6517 drm_get_encoder_name(&encoder->base),
6518 mode->base.id, mode->name);
36f2d1f1 6519 encoder->mode_set(encoder);
9256aa19
DV		 6520 }
6521
6522 return 0;
79e53945
JB		 6523}
6524
3a9627f4
WF		 6525static bool intel_eld_uptodate(struct drm_connector *connector,
6526 int reg_eldv, uint32_t bits_eldv,
6527 int reg_elda, uint32_t bits_elda,
6528 int reg_edid)
6529{
6530 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6531 uint8_t *eld = connector->eld;
6532 uint32_t i;
6533
6534 i = I915_READ(reg_eldv);
6535 i &= bits_eldv;
6536
6537 if (!eld[0])
6538 return !i;
6539
6540 if (!i)
6541 return false;
6542
6543 i = I915_READ(reg_elda);
6544 i &= ~bits_elda;
6545 I915_WRITE(reg_elda, i);
6546
6547 for (i = 0; i < eld[2]; i++)
6548 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6549 return false;
6550
6551 return true;
6552}
6553
e0dac65e
WF		 6554static void g4x_write_eld(struct drm_connector *connector,
6555 struct drm_crtc *crtc)
6556{
6557 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6558 uint8_t *eld = connector->eld;
6559 uint32_t eldv;
6560 uint32_t len;
6561 uint32_t i;
6562
6563 i = I915_READ(G4X_AUD_VID_DID);
6564
6565 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6566 eldv = G4X_ELDV_DEVCL_DEVBLC;
6567 else
6568 eldv = G4X_ELDV_DEVCTG;
6569
3a9627f4
WF		 6570 if (intel_eld_uptodate(connector,
6571 G4X_AUD_CNTL_ST, eldv,
6572 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6573 G4X_HDMIW_HDMIEDID))
6574 return;
6575
e0dac65e
WF		 6576 i = I915_READ(G4X_AUD_CNTL_ST);
6577 i &= ~(eldv | G4X_ELD_ADDR);
6578 len = (i >> 9) & 0x1f; /* ELD buffer size */
6579 I915_WRITE(G4X_AUD_CNTL_ST, i);
6580
6581 if (!eld[0])
6582 return;
6583
6584 len = min_t(uint8_t, eld[2], len);
6585 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6586 for (i = 0; i < len; i++)
6587 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6588
6589 i = I915_READ(G4X_AUD_CNTL_ST);
6590 i |= eldv;
6591 I915_WRITE(G4X_AUD_CNTL_ST, i);
6592}
6593
83358c85
WX		 6594static void haswell_write_eld(struct drm_connector *connector,
6595 struct drm_crtc *crtc)
6596{
6597 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6598 uint8_t *eld = connector->eld;
6599 struct drm_device *dev = crtc->dev;
7b9f35a6 6600 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6601 uint32_t eldv;
6602 uint32_t i;
6603 int len;
6604 int pipe = to_intel_crtc(crtc)->pipe;
6605 int tmp;
6606
6607 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6608 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6609 int aud_config = HSW_AUD_CFG(pipe);
6610 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6611
6612
6613 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6614
6615 /* Audio output enable */
6616 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6617 tmp = I915_READ(aud_cntrl_st2);
6618 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6619 I915_WRITE(aud_cntrl_st2, tmp);
6620
6621 /* Wait for 1 vertical blank */
6622 intel_wait_for_vblank(dev, pipe);
6623
6624 /* Set ELD valid state */
6625 tmp = I915_READ(aud_cntrl_st2);
6626 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6627 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6628 I915_WRITE(aud_cntrl_st2, tmp);
6629 tmp = I915_READ(aud_cntrl_st2);
6630 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6631
6632 /* Enable HDMI mode */
6633 tmp = I915_READ(aud_config);
6634 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6635 /* clear N_programing_enable and N_value_index */
6636 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6637 I915_WRITE(aud_config, tmp);
6638
6639 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6640
6641 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6642 intel_crtc->eld_vld = true;
83358c85
WX		 6643
6644 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6645 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6646 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6647 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6648 } else
6649 I915_WRITE(aud_config, 0);
6650
6651 if (intel_eld_uptodate(connector,
6652 aud_cntrl_st2, eldv,
6653 aud_cntl_st, IBX_ELD_ADDRESS,
6654 hdmiw_hdmiedid))
6655 return;
6656
6657 i = I915_READ(aud_cntrl_st2);
6658 i &= ~eldv;
6659 I915_WRITE(aud_cntrl_st2, i);
6660
6661 if (!eld[0])
6662 return;
6663
6664 i = I915_READ(aud_cntl_st);
6665 i &= ~IBX_ELD_ADDRESS;
6666 I915_WRITE(aud_cntl_st, i);
6667 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6668 DRM_DEBUG_DRIVER("port num:%d\n", i);
6669
6670 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6671 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6672 for (i = 0; i < len; i++)
6673 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6674
6675 i = I915_READ(aud_cntrl_st2);
6676 i |= eldv;
6677 I915_WRITE(aud_cntrl_st2, i);
6678
6679}
6680
e0dac65e
WF		 6681static void ironlake_write_eld(struct drm_connector *connector,
6682 struct drm_crtc *crtc)
6683{
6684 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6685 uint8_t *eld = connector->eld;
6686 uint32_t eldv;
6687 uint32_t i;
6688 int len;
6689 int hdmiw_hdmiedid;
b6daa025 6690 int aud_config;
e0dac65e
WF		 6691 int aud_cntl_st;
6692 int aud_cntrl_st2;
9b138a83 6693 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6694
b3f33cbf 6695 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6696 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6697 aud_config = IBX_AUD_CFG(pipe);
6698 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6699 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6700 } else {
9b138a83
WX		 6701 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6702 aud_config = CPT_AUD_CFG(pipe);
6703 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6704 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6705 }
6706
9b138a83 6707 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6708
6709 i = I915_READ(aud_cntl_st);
9b138a83 6710 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6711 if (!i) {
6712 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6713 /* operate blindly on all ports */
1202b4c6
WF		 6714 eldv = IBX_ELD_VALIDB;
6715 eldv |= IBX_ELD_VALIDB << 4;
6716 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 6717 } else {
2582a850 6718 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 6719 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6720 }
6721
3a9627f4
WF		 6722 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6723 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6724 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6725 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6726 } else
6727 I915_WRITE(aud_config, 0);
e0dac65e 6728
3a9627f4
WF		 6729 if (intel_eld_uptodate(connector,
6730 aud_cntrl_st2, eldv,
6731 aud_cntl_st, IBX_ELD_ADDRESS,
6732 hdmiw_hdmiedid))
6733 return;
6734
e0dac65e
WF		 6735 i = I915_READ(aud_cntrl_st2);
6736 i &= ~eldv;
6737 I915_WRITE(aud_cntrl_st2, i);
6738
6739 if (!eld[0])
6740 return;
6741
e0dac65e 6742 i = I915_READ(aud_cntl_st);
1202b4c6 6743 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6744 I915_WRITE(aud_cntl_st, i);
6745
6746 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6747 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6748 for (i = 0; i < len; i++)
6749 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6750
6751 i = I915_READ(aud_cntrl_st2);
6752 i |= eldv;
6753 I915_WRITE(aud_cntrl_st2, i);
6754}
6755
6756void intel_write_eld(struct drm_encoder *encoder,
6757 struct drm_display_mode *mode)
6758{
6759 struct drm_crtc *crtc = encoder->crtc;
6760 struct drm_connector *connector;
6761 struct drm_device *dev = encoder->dev;
6762 struct drm_i915_private *dev_priv = dev->dev_private;
6763
6764 connector = drm_select_eld(encoder, mode);
6765 if (!connector)
6766 return;
6767
6768 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6769 connector->base.id,
6770 drm_get_connector_name(connector),
6771 connector->encoder->base.id,
6772 drm_get_encoder_name(connector->encoder));
6773
6774 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6775
6776 if (dev_priv->display.write_eld)
6777 dev_priv->display.write_eld(connector, crtc);
6778}
6779
79e53945
JB		 6780/** Loads the palette/gamma unit for the CRTC with the prepared values */
6781void intel_crtc_load_lut(struct drm_crtc *crtc)
6782{
6783 struct drm_device *dev = crtc->dev;
6784 struct drm_i915_private *dev_priv = dev->dev_private;
6785 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
42db64ef
PZ		 6786 enum pipe pipe = intel_crtc->pipe;
6787 int palreg = PALETTE(pipe);
79e53945 6788 int i;
42db64ef 6789 bool reenable_ips = false;
79e53945
JB		 6790
6791 /* The clocks have to be on to load the palette. */
aed3f09d 6792 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6793 return;
6794
23538ef1
JN		 6795 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
6796 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
6797 assert_dsi_pll_enabled(dev_priv);
6798 else
6799 assert_pll_enabled(dev_priv, pipe);
6800 }
14420bd0 6801
f2b115e6 6802 /* use legacy palette for Ironlake */
bad720ff 6803 if (HAS_PCH_SPLIT(dev))
42db64ef
PZ		 6804 palreg = LGC_PALETTE(pipe);
6805
6806 /* Workaround : Do not read or write the pipe palette/gamma data while
6807 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6808 */
6809 if (intel_crtc->config.ips_enabled &&
6810 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6811 GAMMA_MODE_MODE_SPLIT)) {
6812 hsw_disable_ips(intel_crtc);
6813 reenable_ips = true;
6814 }
2c07245f 6815
79e53945
JB		 6816 for (i = 0; i < 256; i++) {
6817 I915_WRITE(palreg + 4 * i,
6818 (intel_crtc->lut_r[i] << 16) |
6819 (intel_crtc->lut_g[i] << 8) |
6820 intel_crtc->lut_b[i]);
6821 }
42db64ef
PZ		 6822
6823 if (reenable_ips)
6824 hsw_enable_ips(intel_crtc);
79e53945
JB		 6825}
6826
560b85bb
CW		 6827static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6828{
6829 struct drm_device *dev = crtc->dev;
6830 struct drm_i915_private *dev_priv = dev->dev_private;
6831 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6832 bool visible = base != 0;
6833 u32 cntl;
6834
6835 if (intel_crtc->cursor_visible == visible)
6836 return;
6837
9db4a9c7 6838 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6839 if (visible) {
6840 /* On these chipsets we can only modify the base whilst
6841 * the cursor is disabled.
6842 */
9db4a9c7 6843 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6844
6845 cntl &= ~(CURSOR_FORMAT_MASK);
6846 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6847 cntl |= CURSOR_ENABLE |
6848 CURSOR_GAMMA_ENABLE |
6849 CURSOR_FORMAT_ARGB;
6850 } else
6851 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6852 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6853
6854 intel_crtc->cursor_visible = visible;
6855}
6856
6857static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6858{
6859 struct drm_device *dev = crtc->dev;
6860 struct drm_i915_private *dev_priv = dev->dev_private;
6861 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6862 int pipe = intel_crtc->pipe;
6863 bool visible = base != 0;
6864
6865 if (intel_crtc->cursor_visible != visible) {
548f245b 6866 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6867 if (base) {
6868 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6869 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6870 cntl |= pipe << 28; /* Connect to correct pipe */
6871 } else {
6872 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6873 cntl |= CURSOR_MODE_DISABLE;
6874 }
9db4a9c7 6875 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6876
6877 intel_crtc->cursor_visible = visible;
6878 }
6879 /* and commit changes on next vblank */
9db4a9c7 6880 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6881}
6882
65a21cd6
JB		 6883static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6884{
6885 struct drm_device *dev = crtc->dev;
6886 struct drm_i915_private *dev_priv = dev->dev_private;
6887 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6888 int pipe = intel_crtc->pipe;
6889 bool visible = base != 0;
6890
6891 if (intel_crtc->cursor_visible != visible) {
6892 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6893 if (base) {
6894 cntl &= ~CURSOR_MODE;
6895 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6896 } else {
6897 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6898 cntl |= CURSOR_MODE_DISABLE;
6899 }
1f5d76db 6900 if (IS_HASWELL(dev)) {
86d3efce 6901 cntl |= CURSOR_PIPE_CSC_ENABLE;
1f5d76db
PZ		 6902 cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
6903 }
65a21cd6
JB		 6904 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6905
6906 intel_crtc->cursor_visible = visible;
6907 }
6908 /* and commit changes on next vblank */
6909 I915_WRITE(CURBASE_IVB(pipe), base);
6910}
6911
cda4b7d3 6912/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6913static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6914 bool on)
cda4b7d3
CW		 6915{
6916 struct drm_device *dev = crtc->dev;
6917 struct drm_i915_private *dev_priv = dev->dev_private;
6918 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6919 int pipe = intel_crtc->pipe;
6920 int x = intel_crtc->cursor_x;
6921 int y = intel_crtc->cursor_y;
560b85bb 6922 u32 base, pos;
cda4b7d3
CW		 6923 bool visible;
6924
6925 pos = 0;
6926
6b383a7f 6927 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6928 base = intel_crtc->cursor_addr;
6929 if (x > (int) crtc->fb->width)
6930 base = 0;
6931
6932 if (y > (int) crtc->fb->height)
6933 base = 0;
6934 } else
6935 base = 0;
6936
6937 if (x < 0) {
6938 if (x + intel_crtc->cursor_width < 0)
6939 base = 0;
6940
6941 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6942 x = -x;
6943 }
6944 pos |= x << CURSOR_X_SHIFT;
6945
6946 if (y < 0) {
6947 if (y + intel_crtc->cursor_height < 0)
6948 base = 0;
6949
6950 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6951 y = -y;
6952 }
6953 pos |= y << CURSOR_Y_SHIFT;
6954
6955 visible = base != 0;
560b85bb 6956 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6957 return;
6958
0cd83aa9 6959 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6960 I915_WRITE(CURPOS_IVB(pipe), pos);
6961 ivb_update_cursor(crtc, base);
6962 } else {
6963 I915_WRITE(CURPOS(pipe), pos);
6964 if (IS_845G(dev) || IS_I865G(dev))
6965 i845_update_cursor(crtc, base);
6966 else
6967 i9xx_update_cursor(crtc, base);
6968 }
cda4b7d3
CW		 6969}
6970
79e53945 6971static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6972 struct drm_file *file,
79e53945
JB		 6973 uint32_t handle,
6974 uint32_t width, uint32_t height)
6975{
6976 struct drm_device *dev = crtc->dev;
6977 struct drm_i915_private *dev_priv = dev->dev_private;
6978 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6979 struct drm_i915_gem_object *obj;
cda4b7d3 6980 uint32_t addr;
3f8bc370 6981 int ret;
79e53945 6982
79e53945
JB		 6983 /* if we want to turn off the cursor ignore width and height */
6984 if (!handle) {
28c97730 6985 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6986 addr = 0;
05394f39 6987 obj = NULL;
5004417d 6988 mutex_lock(&dev->struct_mutex);
3f8bc370 6989 goto finish;
79e53945
JB		 6990 }
6991
6992 /* Currently we only support 64x64 cursors */
6993 if (width != 64 || height != 64) {
6994 DRM_ERROR("we currently only support 64x64 cursors\n");
6995 return -EINVAL;
6996 }
6997
05394f39 6998 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6999 if (&obj->base == NULL)
79e53945
JB		 7000 return -ENOENT;
7001
05394f39 7002 if (obj->base.size < width * height * 4) {
79e53945 7003 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 7004 ret = -ENOMEM;
7005 goto fail;
79e53945
JB		 7006 }
7007
71acb5eb 7008 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 7009 mutex_lock(&dev->struct_mutex);
b295d1b6 7010 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 7011 unsigned alignment;
7012
d9e86c0e
CW		 7013 if (obj->tiling_mode) {
7014 DRM_ERROR("cursor cannot be tiled\n");
7015 ret = -EINVAL;
7016 goto fail_locked;
7017 }
7018
693db184
CW		 7019 /* Note that the w/a also requires 2 PTE of padding following
7020 * the bo. We currently fill all unused PTE with the shadow
7021 * page and so we should always have valid PTE following the
7022 * cursor preventing the VT-d warning.
7023 */
7024 alignment = 0;
7025 if (need_vtd_wa(dev))
7026 alignment = 64*1024;
7027
7028 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 7029 if (ret) {
7030 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 7031 goto fail_locked;
e7b526bb
CW		 7032 }
7033
d9e86c0e
CW		 7034 ret = i915_gem_object_put_fence(obj);
7035 if (ret) {
2da3b9b9 7036 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 7037 goto fail_unpin;
7038 }
7039
f343c5f6 7040 addr = i915_gem_obj_ggtt_offset(obj);
71acb5eb 7041 } else {
6eeefaf3 7042 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 7043 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 7044 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7045 align);
71acb5eb
DA		 7046 if (ret) {
7047 DRM_ERROR("failed to attach phys object\n");
7f9872e0 7048 goto fail_locked;
71acb5eb 7049 }
05394f39 7050 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 7051 }
7052
a6c45cf0 7053 if (IS_GEN2(dev))
14b60391
JB		 7054 I915_WRITE(CURSIZE, (height << 12) | width);
7055
3f8bc370 7056 finish:
3f8bc370 7057 if (intel_crtc->cursor_bo) {
b295d1b6 7058 if (dev_priv->info->cursor_needs_physical) {
05394f39 7059 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 7060 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7061 } else
cc98b413 7062 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
05394f39 7063 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 7064 }
80824003 7065
7f9872e0 7066 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 7067
7068 intel_crtc->cursor_addr = addr;
05394f39 7069 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 7070 intel_crtc->cursor_width = width;
7071 intel_crtc->cursor_height = height;
7072
40ccc72b 7073 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
3f8bc370 7074
79e53945 7075 return 0;
e7b526bb 7076fail_unpin:
cc98b413 7077 i915_gem_object_unpin_from_display_plane(obj);
7f9872e0 7078fail_locked:
34b8686e 7079 mutex_unlock(&dev->struct_mutex);
bc9025bd 7080fail:
05394f39 7081 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 7082 return ret;
79e53945
JB		 7083}
7084
7085static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7086{
79e53945 7087 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 7088
cda4b7d3
CW		 7089 intel_crtc->cursor_x = x;
7090 intel_crtc->cursor_y = y;
652c393a 7091
40ccc72b 7092 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
79e53945
JB		 7093
7094 return 0;
7095}
7096
7097/** Sets the color ramps on behalf of RandR */
7098void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
7099 u16 blue, int regno)
7100{
7101 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7102
7103 intel_crtc->lut_r[regno] = red >> 8;
7104 intel_crtc->lut_g[regno] = green >> 8;
7105 intel_crtc->lut_b[regno] = blue >> 8;
7106}
7107
b8c00ac5
DA		 7108void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
7109 u16 *blue, int regno)
7110{
7111 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7112
7113 *red = intel_crtc->lut_r[regno] << 8;
7114 *green = intel_crtc->lut_g[regno] << 8;
7115 *blue = intel_crtc->lut_b[regno] << 8;
7116}
7117
79e53945 7118static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 7119 u16 *blue, uint32_t start, uint32_t size)
79e53945 7120{
7203425a 7121 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 7122 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 7123
7203425a 7124 for (i = start; i < end; i++) {
79e53945
JB		 7125 intel_crtc->lut_r[i] = red[i] >> 8;
7126 intel_crtc->lut_g[i] = green[i] >> 8;
7127 intel_crtc->lut_b[i] = blue[i] >> 8;
7128 }
7129
7130 intel_crtc_load_lut(crtc);
7131}
7132
79e53945
JB		 7133/* VESA 640x480x72Hz mode to set on the pipe */
7134static struct drm_display_mode load_detect_mode = {
7135 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7136 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7137};
7138
d2dff872
CW		 7139static struct drm_framebuffer *
7140intel_framebuffer_create(struct drm_device *dev,
308e5bcb 7141 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 7142 struct drm_i915_gem_object *obj)
7143{
7144 struct intel_framebuffer *intel_fb;
7145 int ret;
7146
7147 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7148 if (!intel_fb) {
7149 drm_gem_object_unreference_unlocked(&obj->base);
7150 return ERR_PTR(-ENOMEM);
7151 }
7152
7153 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7154 if (ret) {
7155 drm_gem_object_unreference_unlocked(&obj->base);
7156 kfree(intel_fb);
7157 return ERR_PTR(ret);
7158 }
7159
7160 return &intel_fb->base;
7161}
7162
7163static u32
7164intel_framebuffer_pitch_for_width(int width, int bpp)
7165{
7166 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7167 return ALIGN(pitch, 64);
7168}
7169
7170static u32
7171intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7172{
7173 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7174 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7175}
7176
7177static struct drm_framebuffer *
7178intel_framebuffer_create_for_mode(struct drm_device *dev,
7179 struct drm_display_mode *mode,
7180 int depth, int bpp)
7181{
7182 struct drm_i915_gem_object *obj;
0fed39bd 7183 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 7184
7185 obj = i915_gem_alloc_object(dev,
7186 intel_framebuffer_size_for_mode(mode, bpp));
7187 if (obj == NULL)
7188 return ERR_PTR(-ENOMEM);
7189
7190 mode_cmd.width = mode->hdisplay;
7191 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 7192 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7193 bpp);
5ca0c34a 7194 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 7195
7196 return intel_framebuffer_create(dev, &mode_cmd, obj);
7197}
7198
7199static struct drm_framebuffer *
7200mode_fits_in_fbdev(struct drm_device *dev,
7201 struct drm_display_mode *mode)
7202{
7203 struct drm_i915_private *dev_priv = dev->dev_private;
7204 struct drm_i915_gem_object *obj;
7205 struct drm_framebuffer *fb;
7206
7207 if (dev_priv->fbdev == NULL)
7208 return NULL;
7209
7210 obj = dev_priv->fbdev->ifb.obj;
7211 if (obj == NULL)
7212 return NULL;
7213
7214 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 7215 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7216 fb->bits_per_pixel))
d2dff872
CW		 7217 return NULL;
7218
01f2c773 7219 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 7220 return NULL;
7221
7222 return fb;
7223}
7224
d2434ab7 7225bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 7226 struct drm_display_mode *mode,
8261b191 7227 struct intel_load_detect_pipe *old)
79e53945
JB		 7228{
7229 struct intel_crtc *intel_crtc;
d2434ab7
DV		 7230 struct intel_encoder *intel_encoder =
7231 intel_attached_encoder(connector);
79e53945 7232 struct drm_crtc *possible_crtc;
4ef69c7a 7233 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 7234 struct drm_crtc *crtc = NULL;
7235 struct drm_device *dev = encoder->dev;
94352cf9 7236 struct drm_framebuffer *fb;
79e53945
JB		 7237 int i = -1;
7238
d2dff872
CW		 7239 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7240 connector->base.id, drm_get_connector_name(connector),
7241 encoder->base.id, drm_get_encoder_name(encoder));
7242
79e53945
JB		 7243 /*
7244 * Algorithm gets a little messy:
7a5e4805 7245 *
79e53945
JB		 7246 * - if the connector already has an assigned crtc, use it (but make
7247 * sure it's on first)
7a5e4805 7248 *
79e53945
JB		 7249 * - try to find the first unused crtc that can drive this connector,
7250 * and use that if we find one
79e53945
JB		 7251 */
7252
7253 /* See if we already have a CRTC for this connector */
7254 if (encoder->crtc) {
7255 crtc = encoder->crtc;
8261b191 7256
7b24056b
DV		 7257 mutex_lock(&crtc->mutex);
7258
24218aac 7259 old->dpms_mode = connector->dpms;
8261b191
CW		 7260 old->load_detect_temp = false;
7261
7262 /* Make sure the crtc and connector are running */
24218aac
DV		 7263 if (connector->dpms != DRM_MODE_DPMS_ON)
7264 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 7265
7173188d 7266 return true;
79e53945
JB		 7267 }
7268
7269 /* Find an unused one (if possible) */
7270 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7271 i++;
7272 if (!(encoder->possible_crtcs & (1 << i)))
7273 continue;
7274 if (!possible_crtc->enabled) {
7275 crtc = possible_crtc;
7276 break;
7277 }
79e53945
JB		 7278 }
7279
7280 /*
7281 * If we didn't find an unused CRTC, don't use any.
7282 */
7283 if (!crtc) {
7173188d
CW		 7284 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7285 return false;
79e53945
JB		 7286 }
7287
7b24056b 7288 mutex_lock(&crtc->mutex);
fc303101
DV		 7289 intel_encoder->new_crtc = to_intel_crtc(crtc);
7290 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 7291
7292 intel_crtc = to_intel_crtc(crtc);
24218aac 7293 old->dpms_mode = connector->dpms;
8261b191 7294 old->load_detect_temp = true;
d2dff872 7295 old->release_fb = NULL;
79e53945 7296
6492711d
CW		 7297 if (!mode)
7298 mode = &load_detect_mode;
79e53945 7299
d2dff872
CW		 7300 /* We need a framebuffer large enough to accommodate all accesses
7301 * that the plane may generate whilst we perform load detection.
7302 * We can not rely on the fbcon either being present (we get called
7303 * during its initialisation to detect all boot displays, or it may
7304 * not even exist) or that it is large enough to satisfy the
7305 * requested mode.
7306 */
94352cf9
DV		 7307 fb = mode_fits_in_fbdev(dev, mode);
7308 if (fb == NULL) {
d2dff872 7309 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 7310 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7311 old->release_fb = fb;
d2dff872
CW		 7312 } else
7313 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 7314 if (IS_ERR(fb)) {
d2dff872 7315 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 7316 mutex_unlock(&crtc->mutex);
0e8b3d3e 7317 return false;
79e53945 7318 }
79e53945 7319
c0c36b94 7320 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 7321 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 7322 if (old->release_fb)
7323 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 7324 mutex_unlock(&crtc->mutex);
0e8b3d3e 7325 return false;
79e53945 7326 }
7173188d 7327
79e53945 7328 /* let the connector get through one full cycle before testing */
9d0498a2 7329 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 7330 return true;
79e53945
JB		 7331}
7332
d2434ab7 7333void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 7334 struct intel_load_detect_pipe *old)
79e53945 7335{
d2434ab7
DV		 7336 struct intel_encoder *intel_encoder =
7337 intel_attached_encoder(connector);
4ef69c7a 7338 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 7339 struct drm_crtc *crtc = encoder->crtc;
79e53945 7340
d2dff872
CW		 7341 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7342 connector->base.id, drm_get_connector_name(connector),
7343 encoder->base.id, drm_get_encoder_name(encoder));
7344
8261b191 7345 if (old->load_detect_temp) {
fc303101
DV		 7346 to_intel_connector(connector)->new_encoder = NULL;
7347 intel_encoder->new_crtc = NULL;
7348 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 7349
36206361
DV		 7350 if (old->release_fb) {
7351 drm_framebuffer_unregister_private(old->release_fb);
7352 drm_framebuffer_unreference(old->release_fb);
7353 }
d2dff872 7354
67c96400 7355 mutex_unlock(&crtc->mutex);
0622a53c 7356 return;
79e53945
JB		 7357 }
7358
c751ce4f 7359 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 7360 if (old->dpms_mode != DRM_MODE_DPMS_ON)
7361 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 7362
7363 mutex_unlock(&crtc->mutex);
79e53945
JB		 7364}
7365
da4a1efa
VS		 7366static int i9xx_pll_refclk(struct drm_device *dev,
7367 const struct intel_crtc_config *pipe_config)
7368{
7369 struct drm_i915_private *dev_priv = dev->dev_private;
7370 u32 dpll = pipe_config->dpll_hw_state.dpll;
7371
7372 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
7373 return dev_priv->vbt.lvds_ssc_freq * 1000;
7374 else if (HAS_PCH_SPLIT(dev))
7375 return 120000;
7376 else if (!IS_GEN2(dev))
7377 return 96000;
7378 else
7379 return 48000;
7380}
7381
79e53945 7382/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc
JB		 7383static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7384 struct intel_crtc_config *pipe_config)
79e53945 7385{
f1f644dc 7386 struct drm_device *dev = crtc->base.dev;
79e53945 7387 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 7388 int pipe = pipe_config->cpu_transcoder;
293623f7 7389 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 7390 u32 fp;
7391 intel_clock_t clock;
da4a1efa 7392 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 7393
7394 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 7395 fp = pipe_config->dpll_hw_state.fp0;
79e53945 7396 else
293623f7 7397 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 7398
7399 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 7400 if (IS_PINEVIEW(dev)) {
7401 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7402 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 7403 } else {
7404 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7405 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7406 }
7407
a6c45cf0 7408 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 7409 if (IS_PINEVIEW(dev))
7410 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7411 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 7412 else
7413 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 7414 DPLL_FPA01_P1_POST_DIV_SHIFT);
7415
7416 switch (dpll & DPLL_MODE_MASK) {
7417 case DPLLB_MODE_DAC_SERIAL:
7418 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7419 5 : 10;
7420 break;
7421 case DPLLB_MODE_LVDS:
7422 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7423 7 : 14;
7424 break;
7425 default:
28c97730 7426 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 7427 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 7428 return;
79e53945
JB		 7429 }
7430
ac58c3f0 7431 if (IS_PINEVIEW(dev))
da4a1efa 7432 pineview_clock(refclk, &clock);
ac58c3f0 7433 else
da4a1efa 7434 i9xx_clock(refclk, &clock);
79e53945
JB		 7435 } else {
7436 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7437
7438 if (is_lvds) {
7439 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7440 DPLL_FPA01_P1_POST_DIV_SHIFT);
7441 clock.p2 = 14;
79e53945
JB		 7442 } else {
7443 if (dpll & PLL_P1_DIVIDE_BY_TWO)
7444 clock.p1 = 2;
7445 else {
7446 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7447 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7448 }
7449 if (dpll & PLL_P2_DIVIDE_BY_4)
7450 clock.p2 = 4;
7451 else
7452 clock.p2 = 2;
79e53945 7453 }
da4a1efa
VS		 7454
7455 i9xx_clock(refclk, &clock);
79e53945
JB		 7456 }
7457
18442d08
VS		 7458 /*
7459 * This value includes pixel_multiplier. We will use
7460 * port_clock to compute adjusted_mode.clock in the
7461 * encoder's get_config() function.
7462 */
7463 pipe_config->port_clock = clock.dot;
f1f644dc
JB		 7464}
7465
6878da05
VS		 7466int intel_dotclock_calculate(int link_freq,
7467 const struct intel_link_m_n *m_n)
f1f644dc 7468{
f1f644dc
JB		 7469 /*
7470 * The calculation for the data clock is:
1041a02f 7471 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 7472 * But we want to avoid losing precison if possible, so:
1041a02f 7473 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 7474 *
7475 * and the link clock is simpler:
1041a02f 7476 * link_clock = (m * link_clock) / n
f1f644dc
JB		 7477 */
7478
6878da05
VS		 7479 if (!m_n->link_n)
7480 return 0;
7481
7482 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
7483}
7484
18442d08
VS		 7485static void ironlake_pch_clock_get(struct intel_crtc *crtc,
7486 struct intel_crtc_config *pipe_config)
6878da05
VS		 7487{
7488 struct drm_device *dev = crtc->base.dev;
18442d08
VS		 7489
7490 /* read out port_clock from the DPLL */
7491 i9xx_crtc_clock_get(crtc, pipe_config);
6878da05 7492
f1f644dc 7493 /*
18442d08
VS		 7494 * This value does not include pixel_multiplier.
7495 * We will check that port_clock and adjusted_mode.clock
7496 * agree once we know their relationship in the encoder's
7497 * get_config() function.
79e53945 7498 */
18442d08
VS		 7499 pipe_config->adjusted_mode.clock =
7500 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
7501 &pipe_config->fdi_m_n);
79e53945
JB		 7502}
7503
7504/** Returns the currently programmed mode of the given pipe. */
7505struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7506 struct drm_crtc *crtc)
7507{
548f245b 7508 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 7509 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 7510 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 7511 struct drm_display_mode *mode;
f1f644dc 7512 struct intel_crtc_config pipe_config;
fe2b8f9d
PZ		 7513 int htot = I915_READ(HTOTAL(cpu_transcoder));
7514 int hsync = I915_READ(HSYNC(cpu_transcoder));
7515 int vtot = I915_READ(VTOTAL(cpu_transcoder));
7516 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 7517 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 7518
7519 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7520 if (!mode)
7521 return NULL;
7522
f1f644dc
JB		 7523 /*
7524 * Construct a pipe_config sufficient for getting the clock info
7525 * back out of crtc_clock_get.
7526 *
7527 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7528 * to use a real value here instead.
7529 */
293623f7 7530 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 7531 pipe_config.pixel_multiplier = 1;
293623f7
VS		 7532 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
7533 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
7534 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 7535 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7536
7537 mode->clock = pipe_config.adjusted_mode.clock;
79e53945
JB		 7538 mode->hdisplay = (htot & 0xffff) + 1;
7539 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7540 mode->hsync_start = (hsync & 0xffff) + 1;
7541 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7542 mode->vdisplay = (vtot & 0xffff) + 1;
7543 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7544 mode->vsync_start = (vsync & 0xffff) + 1;
7545 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7546
7547 drm_mode_set_name(mode);
79e53945
JB		 7548
7549 return mode;
7550}
7551
3dec0095 7552static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 7553{
7554 struct drm_device *dev = crtc->dev;
7555 drm_i915_private_t *dev_priv = dev->dev_private;
7556 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7557 int pipe = intel_crtc->pipe;
dbdc6479
JB		 7558 int dpll_reg = DPLL(pipe);
7559 int dpll;
652c393a 7560
bad720ff 7561 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7562 return;
7563
7564 if (!dev_priv->lvds_downclock_avail)
7565 return;
7566
dbdc6479 7567 dpll = I915_READ(dpll_reg);
652c393a 7568 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 7569 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 7570
8ac5a6d5 7571 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 7572
7573 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7574 I915_WRITE(dpll_reg, dpll);
9d0498a2 7575 intel_wait_for_vblank(dev, pipe);
dbdc6479 7576
652c393a
JB		 7577 dpll = I915_READ(dpll_reg);
7578 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 7579 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 7580 }
652c393a
JB		 7581}
7582
7583static void intel_decrease_pllclock(struct drm_crtc *crtc)
7584{
7585 struct drm_device *dev = crtc->dev;
7586 drm_i915_private_t *dev_priv = dev->dev_private;
7587 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 7588
bad720ff 7589 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7590 return;
7591
7592 if (!dev_priv->lvds_downclock_avail)
7593 return;
7594
7595 /*
7596 * Since this is called by a timer, we should never get here in
7597 * the manual case.
7598 */
7599 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 7600 int pipe = intel_crtc->pipe;
7601 int dpll_reg = DPLL(pipe);
7602 int dpll;
f6e5b160 7603
44d98a61 7604 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7605
8ac5a6d5 7606 assert_panel_unlocked(dev_priv, pipe);
652c393a 7607
dc257cf1 7608 dpll = I915_READ(dpll_reg);
652c393a
JB		 7609 dpll |= DISPLAY_RATE_SELECT_FPA1;
7610 I915_WRITE(dpll_reg, dpll);
9d0498a2 7611 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7612 dpll = I915_READ(dpll_reg);
7613 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7614 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7615 }
7616
7617}
7618
f047e395
CW		 7619void intel_mark_busy(struct drm_device *dev)
7620{
c67a470b
PZ		 7621 struct drm_i915_private *dev_priv = dev->dev_private;
7622
7623 hsw_package_c8_gpu_busy(dev_priv);
7624 i915_update_gfx_val(dev_priv);
f047e395
CW		 7625}
7626
7627void intel_mark_idle(struct drm_device *dev)
652c393a 7628{
c67a470b 7629 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 7630 struct drm_crtc *crtc;
652c393a 7631
c67a470b
PZ		 7632 hsw_package_c8_gpu_idle(dev_priv);
7633
652c393a
JB		 7634 if (!i915_powersave)
7635 return;
7636
652c393a 7637 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 7638 if (!crtc->fb)
7639 continue;
7640
725a5b54 7641 intel_decrease_pllclock(crtc);
652c393a 7642 }
652c393a
JB		 7643}
7644
c65355bb
CW		 7645void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7646 struct intel_ring_buffer *ring)
652c393a 7647{
f047e395
CW		 7648 struct drm_device *dev = obj->base.dev;
7649 struct drm_crtc *crtc;
652c393a 7650
f047e395 7651 if (!i915_powersave)
acb87dfb
CW		 7652 return;
7653
652c393a
JB		 7654 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7655 if (!crtc->fb)
7656 continue;
7657
c65355bb
CW		 7658 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7659 continue;
7660
7661 intel_increase_pllclock(crtc);
7662 if (ring && intel_fbc_enabled(dev))
7663 ring->fbc_dirty = true;
652c393a
JB		 7664 }
7665}
7666
79e53945
JB		 7667static void intel_crtc_destroy(struct drm_crtc *crtc)
7668{
7669 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7670 struct drm_device *dev = crtc->dev;
7671 struct intel_unpin_work *work;
7672 unsigned long flags;
7673
7674 spin_lock_irqsave(&dev->event_lock, flags);
7675 work = intel_crtc->unpin_work;
7676 intel_crtc->unpin_work = NULL;
7677 spin_unlock_irqrestore(&dev->event_lock, flags);
7678
7679 if (work) {
7680 cancel_work_sync(&work->work);
7681 kfree(work);
7682 }
79e53945 7683
40ccc72b
MK		 7684 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7685
79e53945 7686 drm_crtc_cleanup(crtc);
67e77c5a 7687
79e53945
JB		 7688 kfree(intel_crtc);
7689}
7690
6b95a207
KH		 7691static void intel_unpin_work_fn(struct work_struct *__work)
7692{
7693 struct intel_unpin_work *work =
7694 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7695 struct drm_device *dev = work->crtc->dev;
6b95a207 7696
b4a98e57 7697 mutex_lock(&dev->struct_mutex);
1690e1eb 7698 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7699 drm_gem_object_unreference(&work->pending_flip_obj->base);
7700 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7701
b4a98e57
CW		 7702 intel_update_fbc(dev);
7703 mutex_unlock(&dev->struct_mutex);
7704
7705 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7706 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7707
6b95a207
KH		 7708 kfree(work);
7709}
7710
1afe3e9d 7711static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7712 struct drm_crtc *crtc)
6b95a207
KH		 7713{
7714 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7715 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7716 struct intel_unpin_work *work;
6b95a207
KH		 7717 unsigned long flags;
7718
7719 /* Ignore early vblank irqs */
7720 if (intel_crtc == NULL)
7721 return;
7722
7723 spin_lock_irqsave(&dev->event_lock, flags);
7724 work = intel_crtc->unpin_work;
e7d841ca
CW		 7725
7726 /* Ensure we don't miss a work->pending update ... */
7727 smp_rmb();
7728
7729 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7730 spin_unlock_irqrestore(&dev->event_lock, flags);
7731 return;
7732 }
7733
e7d841ca
CW		 7734 /* and that the unpin work is consistent wrt ->pending. */
7735 smp_rmb();
7736
6b95a207 7737 intel_crtc->unpin_work = NULL;
6b95a207 7738
45a066eb
RC		 7739 if (work->event)
7740 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7741
0af7e4df
MK		 7742 drm_vblank_put(dev, intel_crtc->pipe);
7743
6b95a207
KH		 7744 spin_unlock_irqrestore(&dev->event_lock, flags);
7745
2c10d571 7746 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7747
7748 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7749
7750 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7751}
7752
1afe3e9d
JB		 7753void intel_finish_page_flip(struct drm_device *dev, int pipe)
7754{
7755 drm_i915_private_t *dev_priv = dev->dev_private;
7756 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7757
49b14a5c 7758 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7759}
7760
7761void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7762{
7763 drm_i915_private_t *dev_priv = dev->dev_private;
7764 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7765
49b14a5c 7766 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7767}
7768
6b95a207
KH		 7769void intel_prepare_page_flip(struct drm_device *dev, int plane)
7770{
7771 drm_i915_private_t *dev_priv = dev->dev_private;
7772 struct intel_crtc *intel_crtc =
7773 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7774 unsigned long flags;
7775
e7d841ca
CW		 7776 /* NB: An MMIO update of the plane base pointer will also
7777 * generate a page-flip completion irq, i.e. every modeset
7778 * is also accompanied by a spurious intel_prepare_page_flip().
7779 */
6b95a207 7780 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7781 if (intel_crtc->unpin_work)
7782 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7783 spin_unlock_irqrestore(&dev->event_lock, flags);
7784}
7785
e7d841ca
CW		 7786inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7787{
7788 /* Ensure that the work item is consistent when activating it ... */
7789 smp_wmb();
7790 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7791 /* and that it is marked active as soon as the irq could fire. */
7792 smp_wmb();
7793}
7794
8c9f3aaf
JB		 7795static int intel_gen2_queue_flip(struct drm_device *dev,
7796 struct drm_crtc *crtc,
7797 struct drm_framebuffer *fb,
ed8d1975
KP		 7798 struct drm_i915_gem_object *obj,
7799 uint32_t flags)
8c9f3aaf
JB		 7800{
7801 struct drm_i915_private *dev_priv = dev->dev_private;
7802 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7803 u32 flip_mask;
6d90c952 7804 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7805 int ret;
7806
6d90c952 7807 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7808 if (ret)
83d4092b 7809 goto err;
8c9f3aaf 7810
6d90c952 7811 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7812 if (ret)
83d4092b 7813 goto err_unpin;
8c9f3aaf
JB		 7814
7815 /* Can't queue multiple flips, so wait for the previous
7816 * one to finish before executing the next.
7817 */
7818 if (intel_crtc->plane)
7819 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7820 else
7821 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7822 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7823 intel_ring_emit(ring, MI_NOOP);
7824 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7825 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7826 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 7827 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952 7828 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7829
7830 intel_mark_page_flip_active(intel_crtc);
09246732 7831 __intel_ring_advance(ring);
83d4092b
CW		 7832 return 0;
7833
7834err_unpin:
7835 intel_unpin_fb_obj(obj);
7836err:
8c9f3aaf
JB		 7837 return ret;
7838}
7839
7840static int intel_gen3_queue_flip(struct drm_device *dev,
7841 struct drm_crtc *crtc,
7842 struct drm_framebuffer *fb,
ed8d1975
KP		 7843 struct drm_i915_gem_object *obj,
7844 uint32_t flags)
8c9f3aaf
JB		 7845{
7846 struct drm_i915_private *dev_priv = dev->dev_private;
7847 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7848 u32 flip_mask;
6d90c952 7849 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7850 int ret;
7851
6d90c952 7852 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7853 if (ret)
83d4092b 7854 goto err;
8c9f3aaf 7855
6d90c952 7856 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7857 if (ret)
83d4092b 7858 goto err_unpin;
8c9f3aaf
JB		 7859
7860 if (intel_crtc->plane)
7861 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7862 else
7863 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7864 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7865 intel_ring_emit(ring, MI_NOOP);
7866 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7867 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7868 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 7869 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952
DV		 7870 intel_ring_emit(ring, MI_NOOP);
7871
e7d841ca 7872 intel_mark_page_flip_active(intel_crtc);
09246732 7873 __intel_ring_advance(ring);
83d4092b
CW		 7874 return 0;
7875
7876err_unpin:
7877 intel_unpin_fb_obj(obj);
7878err:
8c9f3aaf
JB		 7879 return ret;
7880}
7881
7882static int intel_gen4_queue_flip(struct drm_device *dev,
7883 struct drm_crtc *crtc,
7884 struct drm_framebuffer *fb,
ed8d1975
KP		 7885 struct drm_i915_gem_object *obj,
7886 uint32_t flags)
8c9f3aaf
JB		 7887{
7888 struct drm_i915_private *dev_priv = dev->dev_private;
7889 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7890 uint32_t pf, pipesrc;
6d90c952 7891 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7892 int ret;
7893
6d90c952 7894 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7895 if (ret)
83d4092b 7896 goto err;
8c9f3aaf 7897
6d90c952 7898 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7899 if (ret)
83d4092b 7900 goto err_unpin;
8c9f3aaf
JB		 7901
7902 /* i965+ uses the linear or tiled offsets from the
7903 * Display Registers (which do not change across a page-flip)
7904 * so we need only reprogram the base address.
7905 */
6d90c952
DV		 7906 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7907 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7908 intel_ring_emit(ring, fb->pitches[0]);
c2c75131 7909 intel_ring_emit(ring,
f343c5f6 7910 (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
c2c75131 7911 obj->tiling_mode);
8c9f3aaf
JB		 7912
7913 /* XXX Enabling the panel-fitter across page-flip is so far
7914 * untested on non-native modes, so ignore it for now.
7915 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7916 */
7917 pf = 0;
7918 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7919 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7920
7921 intel_mark_page_flip_active(intel_crtc);
09246732 7922 __intel_ring_advance(ring);
83d4092b
CW		 7923 return 0;
7924
7925err_unpin:
7926 intel_unpin_fb_obj(obj);
7927err:
8c9f3aaf
JB		 7928 return ret;
7929}
7930
7931static int intel_gen6_queue_flip(struct drm_device *dev,
7932 struct drm_crtc *crtc,
7933 struct drm_framebuffer *fb,
ed8d1975
KP		 7934 struct drm_i915_gem_object *obj,
7935 uint32_t flags)
8c9f3aaf
JB		 7936{
7937 struct drm_i915_private *dev_priv = dev->dev_private;
7938 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7939 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7940 uint32_t pf, pipesrc;
7941 int ret;
7942
6d90c952 7943 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7944 if (ret)
83d4092b 7945 goto err;
8c9f3aaf 7946
6d90c952 7947 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7948 if (ret)
83d4092b 7949 goto err_unpin;
8c9f3aaf 7950
6d90c952
DV		 7951 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7952 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7953 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
f343c5f6 7954 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8c9f3aaf 7955
dc257cf1
DV		 7956 /* Contrary to the suggestions in the documentation,
7957 * "Enable Panel Fitter" does not seem to be required when page
7958 * flipping with a non-native mode, and worse causes a normal
7959 * modeset to fail.
7960 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7961 */
7962 pf = 0;
8c9f3aaf 7963 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7964 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7965
7966 intel_mark_page_flip_active(intel_crtc);
09246732 7967 __intel_ring_advance(ring);
83d4092b
CW		 7968 return 0;
7969
7970err_unpin:
7971 intel_unpin_fb_obj(obj);
7972err:
8c9f3aaf
JB		 7973 return ret;
7974}
7975
7c9017e5
JB		 7976static int intel_gen7_queue_flip(struct drm_device *dev,
7977 struct drm_crtc *crtc,
7978 struct drm_framebuffer *fb,
ed8d1975
KP		 7979 struct drm_i915_gem_object *obj,
7980 uint32_t flags)
7c9017e5
JB		 7981{
7982 struct drm_i915_private *dev_priv = dev->dev_private;
7983 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ffe74d75 7984 struct intel_ring_buffer *ring;
cb05d8de 7985 uint32_t plane_bit = 0;
ffe74d75
CW		 7986 int len, ret;
7987
7988 ring = obj->ring;
7989 if (ring == NULL || ring->id != RCS)
7990 ring = &dev_priv->ring[BCS];
7c9017e5
JB		 7991
7992 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7993 if (ret)
83d4092b 7994 goto err;
7c9017e5 7995
cb05d8de
DV		 7996 switch(intel_crtc->plane) {
7997 case PLANE_A:
7998 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7999 break;
8000 case PLANE_B:
8001 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
8002 break;
8003 case PLANE_C:
8004 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
8005 break;
8006 default:
8007 WARN_ONCE(1, "unknown plane in flip command\n");
8008 ret = -ENODEV;
ab3951eb 8009 goto err_unpin;
cb05d8de
DV		 8010 }
8011
ffe74d75
CW		 8012 len = 4;
8013 if (ring->id == RCS)
8014 len += 6;
8015
8016 ret = intel_ring_begin(ring, len);
7c9017e5 8017 if (ret)
83d4092b 8018 goto err_unpin;
7c9017e5 8019
ffe74d75
CW		 8020 /* Unmask the flip-done completion message. Note that the bspec says that
8021 * we should do this for both the BCS and RCS, and that we must not unmask
8022 * more than one flip event at any time (or ensure that one flip message
8023 * can be sent by waiting for flip-done prior to queueing new flips).
8024 * Experimentation says that BCS works despite DERRMR masking all
8025 * flip-done completion events and that unmasking all planes at once
8026 * for the RCS also doesn't appear to drop events. Setting the DERRMR
8027 * to zero does lead to lockups within MI_DISPLAY_FLIP.
8028 */
8029 if (ring->id == RCS) {
8030 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8031 intel_ring_emit(ring, DERRMR);
8032 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8033 DERRMR_PIPEB_PRI_FLIP_DONE |
8034 DERRMR_PIPEC_PRI_FLIP_DONE));
8035 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
8036 intel_ring_emit(ring, DERRMR);
8037 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8038 }
8039
cb05d8de 8040 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 8041 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
f343c5f6 8042 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7c9017e5 8043 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 8044
8045 intel_mark_page_flip_active(intel_crtc);
09246732 8046 __intel_ring_advance(ring);
83d4092b
CW		 8047 return 0;
8048
8049err_unpin:
8050 intel_unpin_fb_obj(obj);
8051err:
7c9017e5
JB		 8052 return ret;
8053}
8054
8c9f3aaf
JB		 8055static int intel_default_queue_flip(struct drm_device *dev,
8056 struct drm_crtc *crtc,
8057 struct drm_framebuffer *fb,
ed8d1975
KP		 8058 struct drm_i915_gem_object *obj,
8059 uint32_t flags)
8c9f3aaf
JB		 8060{
8061 return -ENODEV;
8062}
8063
6b95a207
KH		 8064static int intel_crtc_page_flip(struct drm_crtc *crtc,
8065 struct drm_framebuffer *fb,
ed8d1975
KP		 8066 struct drm_pending_vblank_event *event,
8067 uint32_t page_flip_flags)
6b95a207
KH		 8068{
8069 struct drm_device *dev = crtc->dev;
8070 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 8071 struct drm_framebuffer *old_fb = crtc->fb;
8072 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 8073 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8074 struct intel_unpin_work *work;
8c9f3aaf 8075 unsigned long flags;
52e68630 8076 int ret;
6b95a207 8077
e6a595d2
VS		 8078 /* Can't change pixel format via MI display flips. */
8079 if (fb->pixel_format != crtc->fb->pixel_format)
8080 return -EINVAL;
8081
8082 /*
8083 * TILEOFF/LINOFF registers can't be changed via MI display flips.
8084 * Note that pitch changes could also affect these register.
8085 */
8086 if (INTEL_INFO(dev)->gen > 3 &&
8087 (fb->offsets[0] != crtc->fb->offsets[0] ||
8088 fb->pitches[0] != crtc->fb->pitches[0]))
8089 return -EINVAL;
8090
6b95a207
KH		 8091 work = kzalloc(sizeof *work, GFP_KERNEL);
8092 if (work == NULL)
8093 return -ENOMEM;
8094
6b95a207 8095 work->event = event;
b4a98e57 8096 work->crtc = crtc;
4a35f83b 8097 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 8098 INIT_WORK(&work->work, intel_unpin_work_fn);
8099
7317c75e
JB		 8100 ret = drm_vblank_get(dev, intel_crtc->pipe);
8101 if (ret)
8102 goto free_work;
8103
6b95a207
KH		 8104 /* We borrow the event spin lock for protecting unpin_work */
8105 spin_lock_irqsave(&dev->event_lock, flags);
8106 if (intel_crtc->unpin_work) {
8107 spin_unlock_irqrestore(&dev->event_lock, flags);
8108 kfree(work);
7317c75e 8109 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 8110
8111 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 8112 return -EBUSY;
8113 }
8114 intel_crtc->unpin_work = work;
8115 spin_unlock_irqrestore(&dev->event_lock, flags);
8116
b4a98e57
CW		 8117 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8118 flush_workqueue(dev_priv->wq);
8119
79158103
CW		 8120 ret = i915_mutex_lock_interruptible(dev);
8121 if (ret)
8122 goto cleanup;
6b95a207 8123
75dfca80 8124 /* Reference the objects for the scheduled work. */
05394f39
CW		 8125 drm_gem_object_reference(&work->old_fb_obj->base);
8126 drm_gem_object_reference(&obj->base);
6b95a207
KH		 8127
8128 crtc->fb = fb;
96b099fd 8129
e1f99ce6 8130 work->pending_flip_obj = obj;
e1f99ce6 8131
4e5359cd
SF		 8132 work->enable_stall_check = true;
8133
b4a98e57 8134 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 8135 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 8136
ed8d1975 8137 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8c9f3aaf
JB		 8138 if (ret)
8139 goto cleanup_pending;
6b95a207 8140
7782de3b 8141 intel_disable_fbc(dev);
c65355bb 8142 intel_mark_fb_busy(obj, NULL);
6b95a207
KH		 8143 mutex_unlock(&dev->struct_mutex);
8144
e5510fac
JB		 8145 trace_i915_flip_request(intel_crtc->plane, obj);
8146
6b95a207 8147 return 0;
96b099fd 8148
8c9f3aaf 8149cleanup_pending:
b4a98e57 8150 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 8151 crtc->fb = old_fb;
05394f39
CW		 8152 drm_gem_object_unreference(&work->old_fb_obj->base);
8153 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 8154 mutex_unlock(&dev->struct_mutex);
8155
79158103 8156cleanup:
96b099fd
CW		 8157 spin_lock_irqsave(&dev->event_lock, flags);
8158 intel_crtc->unpin_work = NULL;
8159 spin_unlock_irqrestore(&dev->event_lock, flags);
8160
7317c75e
JB		 8161 drm_vblank_put(dev, intel_crtc->pipe);
8162free_work:
96b099fd
CW		 8163 kfree(work);
8164
8165 return ret;
6b95a207
KH		 8166}
8167
f6e5b160 8168static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 8169 .mode_set_base_atomic = intel_pipe_set_base_atomic,
8170 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 8171};
8172
50f56119
DV		 8173static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
8174 struct drm_crtc *crtc)
8175{
8176 struct drm_device *dev;
8177 struct drm_crtc *tmp;
8178 int crtc_mask = 1;
47f1c6c9 8179
50f56119 8180 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 8181
50f56119 8182 dev = crtc->dev;
47f1c6c9 8183
50f56119
DV		 8184 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
8185 if (tmp == crtc)
8186 break;
8187 crtc_mask <<= 1;
8188 }
47f1c6c9 8189
50f56119
DV		 8190 if (encoder->possible_crtcs & crtc_mask)
8191 return true;
8192 return false;
47f1c6c9 8193}
79e53945 8194
9a935856
DV		 8195/**
8196 * intel_modeset_update_staged_output_state
8197 *
8198 * Updates the staged output configuration state, e.g. after we've read out the
8199 * current hw state.
8200 */
8201static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 8202{
9a935856
DV		 8203 struct intel_encoder *encoder;
8204 struct intel_connector *connector;
f6e5b160 8205
9a935856
DV		 8206 list_for_each_entry(connector, &dev->mode_config.connector_list,
8207 base.head) {
8208 connector->new_encoder =
8209 to_intel_encoder(connector->base.encoder);
8210 }
f6e5b160 8211
9a935856
DV		 8212 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8213 base.head) {
8214 encoder->new_crtc =
8215 to_intel_crtc(encoder->base.crtc);
8216 }
f6e5b160
CW		 8217}
8218
9a935856
DV		 8219/**
8220 * intel_modeset_commit_output_state
8221 *
8222 * This function copies the stage display pipe configuration to the real one.
8223 */
8224static void intel_modeset_commit_output_state(struct drm_device *dev)
8225{
8226 struct intel_encoder *encoder;
8227 struct intel_connector *connector;
f6e5b160 8228
9a935856
DV		 8229 list_for_each_entry(connector, &dev->mode_config.connector_list,
8230 base.head) {
8231 connector->base.encoder = &connector->new_encoder->base;
8232 }
f6e5b160 8233
9a935856
DV		 8234 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8235 base.head) {
8236 encoder->base.crtc = &encoder->new_crtc->base;
8237 }
8238}
8239
050f7aeb
DV		 8240static void
8241connected_sink_compute_bpp(struct intel_connector * connector,
8242 struct intel_crtc_config *pipe_config)
8243{
8244 int bpp = pipe_config->pipe_bpp;
8245
8246 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8247 connector->base.base.id,
8248 drm_get_connector_name(&connector->base));
8249
8250 /* Don't use an invalid EDID bpc value */
8251 if (connector->base.display_info.bpc &&
8252 connector->base.display_info.bpc * 3 < bpp) {
8253 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8254 bpp, connector->base.display_info.bpc*3);
8255 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8256 }
8257
8258 /* Clamp bpp to 8 on screens without EDID 1.4 */
8259 if (connector->base.display_info.bpc == 0 && bpp > 24) {
8260 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8261 bpp);
8262 pipe_config->pipe_bpp = 24;
8263 }
8264}
8265
4e53c2e0 8266static int
050f7aeb
DV		 8267compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8268 struct drm_framebuffer *fb,
8269 struct intel_crtc_config *pipe_config)
4e53c2e0 8270{
050f7aeb
DV		 8271 struct drm_device *dev = crtc->base.dev;
8272 struct intel_connector *connector;
4e53c2e0
DV		 8273 int bpp;
8274
d42264b1
DV		 8275 switch (fb->pixel_format) {
8276 case DRM_FORMAT_C8:
4e53c2e0
DV		 8277 bpp = 8*3; /* since we go through a colormap */
8278 break;
d42264b1
DV		 8279 case DRM_FORMAT_XRGB1555:
8280 case DRM_FORMAT_ARGB1555:
8281 /* checked in intel_framebuffer_init already */
8282 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8283 return -EINVAL;
8284 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 8285 bpp = 6*3; /* min is 18bpp */
8286 break;
d42264b1
DV		 8287 case DRM_FORMAT_XBGR8888:
8288 case DRM_FORMAT_ABGR8888:
8289 /* checked in intel_framebuffer_init already */
8290 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8291 return -EINVAL;
8292 case DRM_FORMAT_XRGB8888:
8293 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 8294 bpp = 8*3;
8295 break;
d42264b1
DV		 8296 case DRM_FORMAT_XRGB2101010:
8297 case DRM_FORMAT_ARGB2101010:
8298 case DRM_FORMAT_XBGR2101010:
8299 case DRM_FORMAT_ABGR2101010:
8300 /* checked in intel_framebuffer_init already */
8301 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 8302 return -EINVAL;
4e53c2e0
DV		 8303 bpp = 10*3;
8304 break;
baba133a 8305 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 8306 default:
8307 DRM_DEBUG_KMS("unsupported depth\n");
8308 return -EINVAL;
8309 }
8310
4e53c2e0
DV		 8311 pipe_config->pipe_bpp = bpp;
8312
8313 /* Clamp display bpp to EDID value */
8314 list_for_each_entry(connector, &dev->mode_config.connector_list,
050f7aeb 8315 base.head) {
1b829e05
DV		 8316 if (!connector->new_encoder ||
8317 connector->new_encoder->new_crtc != crtc)
4e53c2e0
DV		 8318 continue;
8319
050f7aeb 8320 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV		 8321 }
8322
8323 return bpp;
8324}
8325
c0b03411
DV		 8326static void intel_dump_pipe_config(struct intel_crtc *crtc,
8327 struct intel_crtc_config *pipe_config,
8328 const char *context)
8329{
8330 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8331 context, pipe_name(crtc->pipe));
8332
8333 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8334 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8335 pipe_config->pipe_bpp, pipe_config->dither);
8336 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8337 pipe_config->has_pch_encoder,
8338 pipe_config->fdi_lanes,
8339 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8340 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8341 pipe_config->fdi_m_n.tu);
eb14cb74
VS		 8342 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8343 pipe_config->has_dp_encoder,
8344 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
8345 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
8346 pipe_config->dp_m_n.tu);
c0b03411
DV		 8347 DRM_DEBUG_KMS("requested mode:\n");
8348 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8349 DRM_DEBUG_KMS("adjusted mode:\n");
8350 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
d71b8d4a 8351 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
c0b03411
DV		 8352 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8353 pipe_config->gmch_pfit.control,
8354 pipe_config->gmch_pfit.pgm_ratios,
8355 pipe_config->gmch_pfit.lvds_border_bits);
8356 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
8357 pipe_config->pch_pfit.pos,
8358 pipe_config->pch_pfit.size);
42db64ef 8359 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
c0b03411
DV		 8360}
8361
accfc0c5
DV		 8362static bool check_encoder_cloning(struct drm_crtc *crtc)
8363{
8364 int num_encoders = 0;
8365 bool uncloneable_encoders = false;
8366 struct intel_encoder *encoder;
8367
8368 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8369 base.head) {
8370 if (&encoder->new_crtc->base != crtc)
8371 continue;
8372
8373 num_encoders++;
8374 if (!encoder->cloneable)
8375 uncloneable_encoders = true;
8376 }
8377
8378 return !(num_encoders > 1 && uncloneable_encoders);
8379}
8380
b8cecdf5
DV		 8381static struct intel_crtc_config *
8382intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 8383 struct drm_framebuffer *fb,
b8cecdf5 8384 struct drm_display_mode *mode)
ee7b9f93 8385{
7758a113 8386 struct drm_device *dev = crtc->dev;
7758a113 8387 struct intel_encoder *encoder;
b8cecdf5 8388 struct intel_crtc_config *pipe_config;
e29c22c0
DV		 8389 int plane_bpp, ret = -EINVAL;
8390 bool retry = true;
ee7b9f93 8391
accfc0c5
DV		 8392 if (!check_encoder_cloning(crtc)) {
8393 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8394 return ERR_PTR(-EINVAL);
8395 }
8396
b8cecdf5
DV		 8397 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8398 if (!pipe_config)
7758a113
DV		 8399 return ERR_PTR(-ENOMEM);
8400
b8cecdf5
DV		 8401 drm_mode_copy(&pipe_config->adjusted_mode, mode);
8402 drm_mode_copy(&pipe_config->requested_mode, mode);
e143a21c
DV		 8403 pipe_config->cpu_transcoder =
8404 (enum transcoder) to_intel_crtc(crtc)->pipe;
c0d43d62 8405 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
b8cecdf5 8406
2960bc9c
ID		 8407 /*
8408 * Sanitize sync polarity flags based on requested ones. If neither
8409 * positive or negative polarity is requested, treat this as meaning
8410 * negative polarity.
8411 */
8412 if (!(pipe_config->adjusted_mode.flags &
8413 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8414 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8415
8416 if (!(pipe_config->adjusted_mode.flags &
8417 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8418 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8419
050f7aeb
DV		 8420 /* Compute a starting value for pipe_config->pipe_bpp taking the source
8421 * plane pixel format and any sink constraints into account. Returns the
8422 * source plane bpp so that dithering can be selected on mismatches
8423 * after encoders and crtc also have had their say. */
8424 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8425 fb, pipe_config);
4e53c2e0
DV		 8426 if (plane_bpp < 0)
8427 goto fail;
8428
e29c22c0 8429encoder_retry:
ef1b460d 8430 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 8431 pipe_config->port_clock = 0;
ef1b460d 8432 pipe_config->pixel_multiplier = 1;
ff9a6750 8433
135c81b8
DV		 8434 /* Fill in default crtc timings, allow encoders to overwrite them. */
8435 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, 0);
8436
7758a113
DV		 8437 /* Pass our mode to the connectors and the CRTC to give them a chance to
8438 * adjust it according to limitations or connector properties, and also
8439 * a chance to reject the mode entirely.
47f1c6c9 8440 */
7758a113
DV		 8441 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8442 base.head) {
47f1c6c9 8443
7758a113
DV		 8444 if (&encoder->new_crtc->base != crtc)
8445 continue;
7ae89233 8446
efea6e8e
DV		 8447 if (!(encoder->compute_config(encoder, pipe_config))) {
8448 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 8449 goto fail;
8450 }
ee7b9f93 8451 }
47f1c6c9 8452
ff9a6750
DV		 8453 /* Set default port clock if not overwritten by the encoder. Needs to be
8454 * done afterwards in case the encoder adjusts the mode. */
8455 if (!pipe_config->port_clock)
3c52f4eb
VS		 8456 pipe_config->port_clock = pipe_config->adjusted_mode.clock *
8457 pipe_config->pixel_multiplier;
ff9a6750 8458
a43f6e0f 8459 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 8460 if (ret < 0) {
7758a113
DV		 8461 DRM_DEBUG_KMS("CRTC fixup failed\n");
8462 goto fail;
ee7b9f93 8463 }
e29c22c0
DV		 8464
8465 if (ret == RETRY) {
8466 if (WARN(!retry, "loop in pipe configuration computation\n")) {
8467 ret = -EINVAL;
8468 goto fail;
8469 }
8470
8471 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8472 retry = false;
8473 goto encoder_retry;
8474 }
8475
4e53c2e0
DV		 8476 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
8477 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8478 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
8479
b8cecdf5 8480 return pipe_config;
7758a113 8481fail:
b8cecdf5 8482 kfree(pipe_config);
e29c22c0 8483 return ERR_PTR(ret);
ee7b9f93 8484}
47f1c6c9 8485
e2e1ed41
DV		 8486/* Computes which crtcs are affected and sets the relevant bits in the mask. For
8487 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8488static void
8489intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
8490 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 8491{
8492 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 8493 struct drm_device *dev = crtc->dev;
8494 struct intel_encoder *encoder;
8495 struct intel_connector *connector;
8496 struct drm_crtc *tmp_crtc;
79e53945 8497
e2e1ed41 8498 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 8499
e2e1ed41
DV		 8500 /* Check which crtcs have changed outputs connected to them, these need
8501 * to be part of the prepare_pipes mask. We don't (yet) support global
8502 * modeset across multiple crtcs, so modeset_pipes will only have one
8503 * bit set at most. */
8504 list_for_each_entry(connector, &dev->mode_config.connector_list,
8505 base.head) {
8506 if (connector->base.encoder == &connector->new_encoder->base)
8507 continue;
79e53945 8508
e2e1ed41
DV		 8509 if (connector->base.encoder) {
8510 tmp_crtc = connector->base.encoder->crtc;
8511
8512 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8513 }
8514
8515 if (connector->new_encoder)
8516 *prepare_pipes |=
8517 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 8518 }
8519
e2e1ed41
DV		 8520 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8521 base.head) {
8522 if (encoder->base.crtc == &encoder->new_crtc->base)
8523 continue;
8524
8525 if (encoder->base.crtc) {
8526 tmp_crtc = encoder->base.crtc;
8527
8528 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8529 }
8530
8531 if (encoder->new_crtc)
8532 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 8533 }
8534
e2e1ed41
DV		 8535 /* Check for any pipes that will be fully disabled ... */
8536 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8537 base.head) {
8538 bool used = false;
22fd0fab 8539
e2e1ed41
DV		 8540 /* Don't try to disable disabled crtcs. */
8541 if (!intel_crtc->base.enabled)
8542 continue;
7e7d76c3 8543
e2e1ed41
DV		 8544 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8545 base.head) {
8546 if (encoder->new_crtc == intel_crtc)
8547 used = true;
8548 }
8549
8550 if (!used)
8551 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 8552 }
8553
e2e1ed41
DV		 8554
8555 /* set_mode is also used to update properties on life display pipes. */
8556 intel_crtc = to_intel_crtc(crtc);
8557 if (crtc->enabled)
8558 *prepare_pipes |= 1 << intel_crtc->pipe;
8559
b6c5164d
DV		 8560 /*
8561 * For simplicity do a full modeset on any pipe where the output routing
8562 * changed. We could be more clever, but that would require us to be
8563 * more careful with calling the relevant encoder->mode_set functions.
8564 */
e2e1ed41
DV		 8565 if (*prepare_pipes)
8566 *modeset_pipes = *prepare_pipes;
8567
8568 /* ... and mask these out. */
8569 *modeset_pipes &= ~(*disable_pipes);
8570 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 8571
8572 /*
8573 * HACK: We don't (yet) fully support global modesets. intel_set_config
8574 * obies this rule, but the modeset restore mode of
8575 * intel_modeset_setup_hw_state does not.
8576 */
8577 *modeset_pipes &= 1 << intel_crtc->pipe;
8578 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 8579
8580 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8581 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 8582}
79e53945 8583
ea9d758d 8584static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 8585{
ea9d758d 8586 struct drm_encoder *encoder;
f6e5b160 8587 struct drm_device *dev = crtc->dev;
f6e5b160 8588
ea9d758d
DV		 8589 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8590 if (encoder->crtc == crtc)
8591 return true;
8592
8593 return false;
8594}
8595
8596static void
8597intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8598{
8599 struct intel_encoder *intel_encoder;
8600 struct intel_crtc *intel_crtc;
8601 struct drm_connector *connector;
8602
8603 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8604 base.head) {
8605 if (!intel_encoder->base.crtc)
8606 continue;
8607
8608 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8609
8610 if (prepare_pipes & (1 << intel_crtc->pipe))
8611 intel_encoder->connectors_active = false;
8612 }
8613
8614 intel_modeset_commit_output_state(dev);
8615
8616 /* Update computed state. */
8617 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8618 base.head) {
8619 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8620 }
8621
8622 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8623 if (!connector->encoder || !connector->encoder->crtc)
8624 continue;
8625
8626 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8627
8628 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 8629 struct drm_property *dpms_property =
8630 dev->mode_config.dpms_property;
8631
ea9d758d 8632 connector->dpms = DRM_MODE_DPMS_ON;
662595df 8633 drm_object_property_set_value(&connector->base,
68d34720
DV		 8634 dpms_property,
8635 DRM_MODE_DPMS_ON);
ea9d758d
DV		 8636
8637 intel_encoder = to_intel_encoder(connector->encoder);
8638 intel_encoder->connectors_active = true;
8639 }
8640 }
8641
8642}
8643
3bd26263 8644static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 8645{
3bd26263 8646 int diff;
f1f644dc
JB		 8647
8648 if (clock1 == clock2)
8649 return true;
8650
8651 if (!clock1 || !clock2)
8652 return false;
8653
8654 diff = abs(clock1 - clock2);
8655
8656 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8657 return true;
8658
8659 return false;
8660}
8661
25c5b266
DV		 8662#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8663 list_for_each_entry((intel_crtc), \
8664 &(dev)->mode_config.crtc_list, \
8665 base.head) \
0973f18f 8666 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 8667
0e8ffe1b 8668static bool
2fa2fe9a
DV		 8669intel_pipe_config_compare(struct drm_device *dev,
8670 struct intel_crtc_config *current_config,
0e8ffe1b
DV		 8671 struct intel_crtc_config *pipe_config)
8672{
66e985c0
DV		 8673#define PIPE_CONF_CHECK_X(name) \
8674 if (current_config->name != pipe_config->name) { \
8675 DRM_ERROR("mismatch in " #name " " \
8676 "(expected 0x%08x, found 0x%08x)\n", \
8677 current_config->name, \
8678 pipe_config->name); \
8679 return false; \
8680 }
8681
08a24034
DV		 8682#define PIPE_CONF_CHECK_I(name) \
8683 if (current_config->name != pipe_config->name) { \
8684 DRM_ERROR("mismatch in " #name " " \
8685 "(expected %i, found %i)\n", \
8686 current_config->name, \
8687 pipe_config->name); \
8688 return false; \
88adfff1
DV		 8689 }
8690
1bd1bd80
DV		 8691#define PIPE_CONF_CHECK_FLAGS(name, mask) \
8692 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 8693 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 8694 "(expected %i, found %i)\n", \
8695 current_config->name & (mask), \
8696 pipe_config->name & (mask)); \
8697 return false; \
8698 }
8699
5e550656
VS		 8700#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
8701 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
8702 DRM_ERROR("mismatch in " #name " " \
8703 "(expected %i, found %i)\n", \
8704 current_config->name, \
8705 pipe_config->name); \
8706 return false; \
8707 }
8708
bb760063
DV		 8709#define PIPE_CONF_QUIRK(quirk) \
8710 ((current_config->quirks | pipe_config->quirks) & (quirk))
8711
eccb140b
DV		 8712 PIPE_CONF_CHECK_I(cpu_transcoder);
8713
08a24034
DV		 8714 PIPE_CONF_CHECK_I(has_pch_encoder);
8715 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 8716 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8717 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8718 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8719 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8720 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 8721
eb14cb74
VS		 8722 PIPE_CONF_CHECK_I(has_dp_encoder);
8723 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
8724 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
8725 PIPE_CONF_CHECK_I(dp_m_n.link_m);
8726 PIPE_CONF_CHECK_I(dp_m_n.link_n);
8727 PIPE_CONF_CHECK_I(dp_m_n.tu);
8728
1bd1bd80
DV		 8729 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8730 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8731 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8732 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8733 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8734 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8735
8736 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8737 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8738 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8739 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8740 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8741 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8742
c93f54cf 8743 PIPE_CONF_CHECK_I(pixel_multiplier);
6c49f241 8744
1bd1bd80
DV		 8745 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8746 DRM_MODE_FLAG_INTERLACE);
8747
bb760063
DV		 8748 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8749 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8750 DRM_MODE_FLAG_PHSYNC);
8751 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8752 DRM_MODE_FLAG_NHSYNC);
8753 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8754 DRM_MODE_FLAG_PVSYNC);
8755 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8756 DRM_MODE_FLAG_NVSYNC);
8757 }
045ac3b5 8758
1bd1bd80
DV		 8759 PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8760 PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8761
2fa2fe9a
DV		 8762 PIPE_CONF_CHECK_I(gmch_pfit.control);
8763 /* pfit ratios are autocomputed by the hw on gen4+ */
8764 if (INTEL_INFO(dev)->gen < 4)
8765 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8766 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8767 PIPE_CONF_CHECK_I(pch_pfit.pos);
8768 PIPE_CONF_CHECK_I(pch_pfit.size);
8769
42db64ef
PZ		 8770 PIPE_CONF_CHECK_I(ips_enabled);
8771
c0d43d62 8772 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 8773 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 8774 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 8775 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8776 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
c0d43d62 8777
42571aef
VS		 8778 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
8779 PIPE_CONF_CHECK_I(pipe_bpp);
8780
d71b8d4a 8781 if (!IS_HASWELL(dev)) {
5e550656 8782 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.clock);
d71b8d4a
VS		 8783 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
8784 }
5e550656 8785
66e985c0 8786#undef PIPE_CONF_CHECK_X
08a24034 8787#undef PIPE_CONF_CHECK_I
1bd1bd80 8788#undef PIPE_CONF_CHECK_FLAGS
5e550656 8789#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 8790#undef PIPE_CONF_QUIRK
88adfff1 8791
0e8ffe1b
DV		 8792 return true;
8793}
8794
91d1b4bd
DV		 8795static void
8796check_connector_state(struct drm_device *dev)
8af6cf88 8797{
8af6cf88
DV		 8798 struct intel_connector *connector;
8799
8800 list_for_each_entry(connector, &dev->mode_config.connector_list,
8801 base.head) {
8802 /* This also checks the encoder/connector hw state with the
8803 * ->get_hw_state callbacks. */
8804 intel_connector_check_state(connector);
8805
8806 WARN(&connector->new_encoder->base != connector->base.encoder,
8807 "connector's staged encoder doesn't match current encoder\n");
8808 }
91d1b4bd
DV		 8809}
8810
8811static void
8812check_encoder_state(struct drm_device *dev)
8813{
8814 struct intel_encoder *encoder;
8815 struct intel_connector *connector;
8af6cf88
DV		 8816
8817 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8818 base.head) {
8819 bool enabled = false;
8820 bool active = false;
8821 enum pipe pipe, tracked_pipe;
8822
8823 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8824 encoder->base.base.id,
8825 drm_get_encoder_name(&encoder->base));
8826
8827 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8828 "encoder's stage crtc doesn't match current crtc\n");
8829 WARN(encoder->connectors_active && !encoder->base.crtc,
8830 "encoder's active_connectors set, but no crtc\n");
8831
8832 list_for_each_entry(connector, &dev->mode_config.connector_list,
8833 base.head) {
8834 if (connector->base.encoder != &encoder->base)
8835 continue;
8836 enabled = true;
8837 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8838 active = true;
8839 }
8840 WARN(!!encoder->base.crtc != enabled,
8841 "encoder's enabled state mismatch "
8842 "(expected %i, found %i)\n",
8843 !!encoder->base.crtc, enabled);
8844 WARN(active && !encoder->base.crtc,
8845 "active encoder with no crtc\n");
8846
8847 WARN(encoder->connectors_active != active,
8848 "encoder's computed active state doesn't match tracked active state "
8849 "(expected %i, found %i)\n", active, encoder->connectors_active);
8850
8851 active = encoder->get_hw_state(encoder, &pipe);
8852 WARN(active != encoder->connectors_active,
8853 "encoder's hw state doesn't match sw tracking "
8854 "(expected %i, found %i)\n",
8855 encoder->connectors_active, active);
8856
8857 if (!encoder->base.crtc)
8858 continue;
8859
8860 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8861 WARN(active && pipe != tracked_pipe,
8862 "active encoder's pipe doesn't match"
8863 "(expected %i, found %i)\n",
8864 tracked_pipe, pipe);
8865
8866 }
91d1b4bd
DV		 8867}
8868
8869static void
8870check_crtc_state(struct drm_device *dev)
8871{
8872 drm_i915_private_t *dev_priv = dev->dev_private;
8873 struct intel_crtc *crtc;
8874 struct intel_encoder *encoder;
8875 struct intel_crtc_config pipe_config;
8af6cf88
DV		 8876
8877 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8878 base.head) {
8879 bool enabled = false;
8880 bool active = false;
8881
045ac3b5
JB		 8882 memset(&pipe_config, 0, sizeof(pipe_config));
8883
8af6cf88
DV		 8884 DRM_DEBUG_KMS("[CRTC:%d]\n",
8885 crtc->base.base.id);
8886
8887 WARN(crtc->active && !crtc->base.enabled,
8888 "active crtc, but not enabled in sw tracking\n");
8889
8890 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8891 base.head) {
8892 if (encoder->base.crtc != &crtc->base)
8893 continue;
8894 enabled = true;
8895 if (encoder->connectors_active)
8896 active = true;
8897 }
6c49f241 8898
8af6cf88
DV		 8899 WARN(active != crtc->active,
8900 "crtc's computed active state doesn't match tracked active state "
8901 "(expected %i, found %i)\n", active, crtc->active);
8902 WARN(enabled != crtc->base.enabled,
8903 "crtc's computed enabled state doesn't match tracked enabled state "
8904 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8905
0e8ffe1b
DV		 8906 active = dev_priv->display.get_pipe_config(crtc,
8907 &pipe_config);
d62cf62a
DV		 8908
8909 /* hw state is inconsistent with the pipe A quirk */
8910 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
8911 active = crtc->active;
8912
6c49f241
DV		 8913 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8914 base.head) {
3eaba51c 8915 enum pipe pipe;
6c49f241
DV		 8916 if (encoder->base.crtc != &crtc->base)
8917 continue;
3eaba51c
VS		 8918 if (encoder->get_config &&
8919 encoder->get_hw_state(encoder, &pipe))
6c49f241
DV		 8920 encoder->get_config(encoder, &pipe_config);
8921 }
8922
0e8ffe1b
DV		 8923 WARN(crtc->active != active,
8924 "crtc active state doesn't match with hw state "
8925 "(expected %i, found %i)\n", crtc->active, active);
8926
c0b03411
DV		 8927 if (active &&
8928 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8929 WARN(1, "pipe state doesn't match!\n");
8930 intel_dump_pipe_config(crtc, &pipe_config,
8931 "[hw state]");
8932 intel_dump_pipe_config(crtc, &crtc->config,
8933 "[sw state]");
8934 }
8af6cf88
DV		 8935 }
8936}
8937
91d1b4bd
DV		 8938static void
8939check_shared_dpll_state(struct drm_device *dev)
8940{
8941 drm_i915_private_t *dev_priv = dev->dev_private;
8942 struct intel_crtc *crtc;
8943 struct intel_dpll_hw_state dpll_hw_state;
8944 int i;
5358901f
DV		 8945
8946 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8947 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
8948 int enabled_crtcs = 0, active_crtcs = 0;
8949 bool active;
8950
8951 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
8952
8953 DRM_DEBUG_KMS("%s\n", pll->name);
8954
8955 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
8956
8957 WARN(pll->active > pll->refcount,
8958 "more active pll users than references: %i vs %i\n",
8959 pll->active, pll->refcount);
8960 WARN(pll->active && !pll->on,
8961 "pll in active use but not on in sw tracking\n");
35c95375
DV		 8962 WARN(pll->on && !pll->active,
8963 "pll in on but not on in use in sw tracking\n");
5358901f
DV		 8964 WARN(pll->on != active,
8965 "pll on state mismatch (expected %i, found %i)\n",
8966 pll->on, active);
8967
8968 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8969 base.head) {
8970 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
8971 enabled_crtcs++;
8972 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
8973 active_crtcs++;
8974 }
8975 WARN(pll->active != active_crtcs,
8976 "pll active crtcs mismatch (expected %i, found %i)\n",
8977 pll->active, active_crtcs);
8978 WARN(pll->refcount != enabled_crtcs,
8979 "pll enabled crtcs mismatch (expected %i, found %i)\n",
8980 pll->refcount, enabled_crtcs);
66e985c0
DV		 8981
8982 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
8983 sizeof(dpll_hw_state)),
8984 "pll hw state mismatch\n");
5358901f 8985 }
8af6cf88
DV		 8986}
8987
91d1b4bd
DV		 8988void
8989intel_modeset_check_state(struct drm_device *dev)
8990{
8991 check_connector_state(dev);
8992 check_encoder_state(dev);
8993 check_crtc_state(dev);
8994 check_shared_dpll_state(dev);
8995}
8996
18442d08
VS		 8997void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
8998 int dotclock)
8999{
9000 /*
9001 * FDI already provided one idea for the dotclock.
9002 * Yell if the encoder disagrees.
9003 */
9004 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.clock, dotclock),
9005 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
9006 pipe_config->adjusted_mode.clock, dotclock);
9007}
9008
f30da187
DV		 9009static int __intel_set_mode(struct drm_crtc *crtc,
9010 struct drm_display_mode *mode,
9011 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 9012{
9013 struct drm_device *dev = crtc->dev;
dbf2b54e 9014 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 9015 struct drm_display_mode *saved_mode, *saved_hwmode;
9016 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 9017 struct intel_crtc *intel_crtc;
9018 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 9019 int ret = 0;
a6778b3c 9020
3ac18232 9021 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 9022 if (!saved_mode)
9023 return -ENOMEM;
3ac18232 9024 saved_hwmode = saved_mode + 1;
a6778b3c 9025
e2e1ed41 9026 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 9027 &prepare_pipes, &disable_pipes);
9028
3ac18232
TG		 9029 *saved_hwmode = crtc->hwmode;
9030 *saved_mode = crtc->mode;
a6778b3c 9031
25c5b266
DV		 9032 /* Hack: Because we don't (yet) support global modeset on multiple
9033 * crtcs, we don't keep track of the new mode for more than one crtc.
9034 * Hence simply check whether any bit is set in modeset_pipes in all the
9035 * pieces of code that are not yet converted to deal with mutliple crtcs
9036 * changing their mode at the same time. */
25c5b266 9037 if (modeset_pipes) {
4e53c2e0 9038 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 9039 if (IS_ERR(pipe_config)) {
9040 ret = PTR_ERR(pipe_config);
9041 pipe_config = NULL;
9042
3ac18232 9043 goto out;
25c5b266 9044 }
c0b03411
DV		 9045 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
9046 "[modeset]");
25c5b266 9047 }
a6778b3c 9048
460da916
DV		 9049 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9050 intel_crtc_disable(&intel_crtc->base);
9051
ea9d758d
DV		 9052 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9053 if (intel_crtc->base.enabled)
9054 dev_priv->display.crtc_disable(&intel_crtc->base);
9055 }
a6778b3c 9056
6c4c86f5
DV		 9057 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9058 * to set it here already despite that we pass it down the callchain.
f6e5b160 9059 */
b8cecdf5 9060 if (modeset_pipes) {
25c5b266 9061 crtc->mode = *mode;
b8cecdf5
DV		 9062 /* mode_set/enable/disable functions rely on a correct pipe
9063 * config. */
9064 to_intel_crtc(crtc)->config = *pipe_config;
9065 }
7758a113 9066
ea9d758d
DV		 9067 /* Only after disabling all output pipelines that will be changed can we
9068 * update the the output configuration. */
9069 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 9070
47fab737
DV		 9071 if (dev_priv->display.modeset_global_resources)
9072 dev_priv->display.modeset_global_resources(dev);
9073
a6778b3c
DV		 9074 /* Set up the DPLL and any encoders state that needs to adjust or depend
9075 * on the DPLL.
f6e5b160 9076 */
25c5b266 9077 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 9078 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 9079 x, y, fb);
9080 if (ret)
9081 goto done;
a6778b3c
DV		 9082 }
9083
9084 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 9085 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
9086 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 9087
25c5b266
DV		 9088 if (modeset_pipes) {
9089 /* Store real post-adjustment hardware mode. */
b8cecdf5 9090 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 9091
25c5b266
DV		 9092 /* Calculate and store various constants which
9093 * are later needed by vblank and swap-completion
9094 * timestamping. They are derived from true hwmode.
9095 */
9096 drm_calc_timestamping_constants(crtc);
9097 }
a6778b3c
DV		 9098
9099 /* FIXME: add subpixel order */
9100done:
c0c36b94 9101 if (ret && crtc->enabled) {
3ac18232
TG		 9102 crtc->hwmode = *saved_hwmode;
9103 crtc->mode = *saved_mode;
a6778b3c
DV		 9104 }
9105
3ac18232 9106out:
b8cecdf5 9107 kfree(pipe_config);
3ac18232 9108 kfree(saved_mode);
a6778b3c 9109 return ret;
f6e5b160
CW		 9110}
9111
e7457a9a
DL		 9112static int intel_set_mode(struct drm_crtc *crtc,
9113 struct drm_display_mode *mode,
9114 int x, int y, struct drm_framebuffer *fb)
f30da187
DV		 9115{
9116 int ret;
9117
9118 ret = __intel_set_mode(crtc, mode, x, y, fb);
9119
9120 if (ret == 0)
9121 intel_modeset_check_state(crtc->dev);
9122
9123 return ret;
9124}
9125
c0c36b94
CW		 9126void intel_crtc_restore_mode(struct drm_crtc *crtc)
9127{
9128 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
9129}
9130
25c5b266
DV		 9131#undef for_each_intel_crtc_masked
9132
d9e55608
DV		 9133static void intel_set_config_free(struct intel_set_config *config)
9134{
9135 if (!config)
9136 return;
9137
1aa4b628
DV		 9138 kfree(config->save_connector_encoders);
9139 kfree(config->save_encoder_crtcs);
d9e55608
DV		 9140 kfree(config);
9141}
9142
85f9eb71
DV		 9143static int intel_set_config_save_state(struct drm_device *dev,
9144 struct intel_set_config *config)
9145{
85f9eb71
DV		 9146 struct drm_encoder *encoder;
9147 struct drm_connector *connector;
9148 int count;
9149
1aa4b628
DV		 9150 config->save_encoder_crtcs =
9151 kcalloc(dev->mode_config.num_encoder,
9152 sizeof(struct drm_crtc *), GFP_KERNEL);
9153 if (!config->save_encoder_crtcs)
85f9eb71
DV		 9154 return -ENOMEM;
9155
1aa4b628
DV		 9156 config->save_connector_encoders =
9157 kcalloc(dev->mode_config.num_connector,
9158 sizeof(struct drm_encoder *), GFP_KERNEL);
9159 if (!config->save_connector_encoders)
85f9eb71
DV		 9160 return -ENOMEM;
9161
9162 /* Copy data. Note that driver private data is not affected.
9163 * Should anything bad happen only the expected state is
9164 * restored, not the drivers personal bookkeeping.
9165 */
85f9eb71
DV		 9166 count = 0;
9167 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 9168 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 9169 }
9170
9171 count = 0;
9172 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 9173 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 9174 }
9175
9176 return 0;
9177}
9178
9179static void intel_set_config_restore_state(struct drm_device *dev,
9180 struct intel_set_config *config)
9181{
9a935856
DV		 9182 struct intel_encoder *encoder;
9183 struct intel_connector *connector;
85f9eb71
DV		 9184 int count;
9185
85f9eb71 9186 count = 0;
9a935856
DV		 9187 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9188 encoder->new_crtc =
9189 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 9190 }
9191
9192 count = 0;
9a935856
DV		 9193 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
9194 connector->new_encoder =
9195 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 9196 }
9197}
9198
e3de42b6 9199static bool
2e57f47d 9200is_crtc_connector_off(struct drm_mode_set *set)
e3de42b6
ID		 9201{
9202 int i;
9203
2e57f47d
CW		 9204 if (set->num_connectors == 0)
9205 return false;
9206
9207 if (WARN_ON(set->connectors == NULL))
9208 return false;
9209
9210 for (i = 0; i < set->num_connectors; i++)
9211 if (set->connectors[i]->encoder &&
9212 set->connectors[i]->encoder->crtc == set->crtc &&
9213 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
e3de42b6
ID		 9214 return true;
9215
9216 return false;
9217}
9218
5e2b584e
DV		 9219static void
9220intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9221 struct intel_set_config *config)
9222{
9223
9224 /* We should be able to check here if the fb has the same properties
9225 * and then just flip_or_move it */
2e57f47d
CW		 9226 if (is_crtc_connector_off(set)) {
9227 config->mode_changed = true;
e3de42b6 9228 } else if (set->crtc->fb != set->fb) {
5e2b584e
DV		 9229 /* If we have no fb then treat it as a full mode set */
9230 if (set->crtc->fb == NULL) {
319d9827
JB		 9231 struct intel_crtc *intel_crtc =
9232 to_intel_crtc(set->crtc);
9233
9234 if (intel_crtc->active && i915_fastboot) {
9235 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9236 config->fb_changed = true;
9237 } else {
9238 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9239 config->mode_changed = true;
9240 }
5e2b584e
DV		 9241 } else if (set->fb == NULL) {
9242 config->mode_changed = true;
72f4901e
DV		 9243 } else if (set->fb->pixel_format !=
9244 set->crtc->fb->pixel_format) {
5e2b584e 9245 config->mode_changed = true;
e3de42b6 9246 } else {
5e2b584e 9247 config->fb_changed = true;
e3de42b6 9248 }
5e2b584e
DV		 9249 }
9250
835c5873 9251 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 9252 config->fb_changed = true;
9253
9254 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9255 DRM_DEBUG_KMS("modes are different, full mode set\n");
9256 drm_mode_debug_printmodeline(&set->crtc->mode);
9257 drm_mode_debug_printmodeline(set->mode);
9258 config->mode_changed = true;
9259 }
a1d95703
CW		 9260
9261 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9262 set->crtc->base.id, config->mode_changed, config->fb_changed);
5e2b584e
DV		 9263}
9264
2e431051 9265static int
9a935856
DV		 9266intel_modeset_stage_output_state(struct drm_device *dev,
9267 struct drm_mode_set *set,
9268 struct intel_set_config *config)
50f56119 9269{
85f9eb71 9270 struct drm_crtc *new_crtc;
9a935856
DV		 9271 struct intel_connector *connector;
9272 struct intel_encoder *encoder;
f3f08572 9273 int ro;
50f56119 9274
9abdda74 9275 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 9276 * of connectors. For paranoia, double-check this. */
9277 WARN_ON(!set->fb && (set->num_connectors != 0));
9278 WARN_ON(set->fb && (set->num_connectors == 0));
9279
9a935856
DV		 9280 list_for_each_entry(connector, &dev->mode_config.connector_list,
9281 base.head) {
9282 /* Otherwise traverse passed in connector list and get encoders
9283 * for them. */
50f56119 9284 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 9285 if (set->connectors[ro] == &connector->base) {
9286 connector->new_encoder = connector->encoder;
50f56119
DV		 9287 break;
9288 }
9289 }
9290
9a935856
DV		 9291 /* If we disable the crtc, disable all its connectors. Also, if
9292 * the connector is on the changing crtc but not on the new
9293 * connector list, disable it. */
9294 if ((!set->fb || ro == set->num_connectors) &&
9295 connector->base.encoder &&
9296 connector->base.encoder->crtc == set->crtc) {
9297 connector->new_encoder = NULL;
9298
9299 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9300 connector->base.base.id,
9301 drm_get_connector_name(&connector->base));
9302 }
9303
9304
9305 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 9306 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 9307 config->mode_changed = true;
50f56119
DV		 9308 }
9309 }
9a935856 9310 /* connector->new_encoder is now updated for all connectors. */
50f56119 9311
9a935856 9312 /* Update crtc of enabled connectors. */
9a935856
DV		 9313 list_for_each_entry(connector, &dev->mode_config.connector_list,
9314 base.head) {
9315 if (!connector->new_encoder)
50f56119
DV		 9316 continue;
9317
9a935856 9318 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 9319
9320 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 9321 if (set->connectors[ro] == &connector->base)
50f56119
DV		 9322 new_crtc = set->crtc;
9323 }
9324
9325 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 9326 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
9327 new_crtc)) {
5e2b584e 9328 return -EINVAL;
50f56119 9329 }
9a935856
DV		 9330 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9331
9332 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9333 connector->base.base.id,
9334 drm_get_connector_name(&connector->base),
9335 new_crtc->base.id);
9336 }
9337
9338 /* Check for any encoders that needs to be disabled. */
9339 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9340 base.head) {
9341 list_for_each_entry(connector,
9342 &dev->mode_config.connector_list,
9343 base.head) {
9344 if (connector->new_encoder == encoder) {
9345 WARN_ON(!connector->new_encoder->new_crtc);
9346
9347 goto next_encoder;
9348 }
9349 }
9350 encoder->new_crtc = NULL;
9351next_encoder:
9352 /* Only now check for crtc changes so we don't miss encoders
9353 * that will be disabled. */
9354 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 9355 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 9356 config->mode_changed = true;
50f56119
DV		 9357 }
9358 }
9a935856 9359 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 9360
2e431051
DV		 9361 return 0;
9362}
9363
9364static int intel_crtc_set_config(struct drm_mode_set *set)
9365{
9366 struct drm_device *dev;
2e431051
DV		 9367 struct drm_mode_set save_set;
9368 struct intel_set_config *config;
9369 int ret;
2e431051 9370
8d3e375e
DV		 9371 BUG_ON(!set);
9372 BUG_ON(!set->crtc);
9373 BUG_ON(!set->crtc->helper_private);
2e431051 9374
7e53f3a4
DV		 9375 /* Enforce sane interface api - has been abused by the fb helper. */
9376 BUG_ON(!set->mode && set->fb);
9377 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 9378
2e431051
DV		 9379 if (set->fb) {
9380 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9381 set->crtc->base.id, set->fb->base.id,
9382 (int)set->num_connectors, set->x, set->y);
9383 } else {
9384 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 9385 }
9386
9387 dev = set->crtc->dev;
9388
9389 ret = -ENOMEM;
9390 config = kzalloc(sizeof(*config), GFP_KERNEL);
9391 if (!config)
9392 goto out_config;
9393
9394 ret = intel_set_config_save_state(dev, config);
9395 if (ret)
9396 goto out_config;
9397
9398 save_set.crtc = set->crtc;
9399 save_set.mode = &set->crtc->mode;
9400 save_set.x = set->crtc->x;
9401 save_set.y = set->crtc->y;
9402 save_set.fb = set->crtc->fb;
9403
9404 /* Compute whether we need a full modeset, only an fb base update or no
9405 * change at all. In the future we might also check whether only the
9406 * mode changed, e.g. for LVDS where we only change the panel fitter in
9407 * such cases. */
9408 intel_set_config_compute_mode_changes(set, config);
9409
9a935856 9410 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 9411 if (ret)
9412 goto fail;
9413
5e2b584e 9414 if (config->mode_changed) {
c0c36b94
CW		 9415 ret = intel_set_mode(set->crtc, set->mode,
9416 set->x, set->y, set->fb);
5e2b584e 9417 } else if (config->fb_changed) {
4878cae2
VS		 9418 intel_crtc_wait_for_pending_flips(set->crtc);
9419
4f660f49 9420 ret = intel_pipe_set_base(set->crtc,
94352cf9 9421 set->x, set->y, set->fb);
50f56119
DV		 9422 }
9423
2d05eae1 9424 if (ret) {
bf67dfeb
DV		 9425 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9426 set->crtc->base.id, ret);
50f56119 9427fail:
2d05eae1 9428 intel_set_config_restore_state(dev, config);
50f56119 9429
2d05eae1
CW		 9430 /* Try to restore the config */
9431 if (config->mode_changed &&
9432 intel_set_mode(save_set.crtc, save_set.mode,
9433 save_set.x, save_set.y, save_set.fb))
9434 DRM_ERROR("failed to restore config after modeset failure\n");
9435 }
50f56119 9436
d9e55608
DV		 9437out_config:
9438 intel_set_config_free(config);
50f56119
DV		 9439 return ret;
9440}
f6e5b160
CW		 9441
9442static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 9443 .cursor_set = intel_crtc_cursor_set,
9444 .cursor_move = intel_crtc_cursor_move,
9445 .gamma_set = intel_crtc_gamma_set,
50f56119 9446 .set_config = intel_crtc_set_config,
f6e5b160
CW		 9447 .destroy = intel_crtc_destroy,
9448 .page_flip = intel_crtc_page_flip,
9449};
9450
79f689aa
PZ		 9451static void intel_cpu_pll_init(struct drm_device *dev)
9452{
affa9354 9453 if (HAS_DDI(dev))
79f689aa
PZ		 9454 intel_ddi_pll_init(dev);
9455}
9456
5358901f
DV		 9457static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
9458 struct intel_shared_dpll *pll,
9459 struct intel_dpll_hw_state *hw_state)
ee7b9f93 9460{
5358901f 9461 uint32_t val;
ee7b9f93 9462
5358901f 9463 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 9464 hw_state->dpll = val;
9465 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
9466 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 9467
9468 return val & DPLL_VCO_ENABLE;
9469}
9470
15bdd4cf
DV		 9471static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
9472 struct intel_shared_dpll *pll)
9473{
9474 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
9475 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
9476}
9477
e7b903d2
DV		 9478static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
9479 struct intel_shared_dpll *pll)
9480{
e7b903d2
DV		 9481 /* PCH refclock must be enabled first */
9482 assert_pch_refclk_enabled(dev_priv);
9483
15bdd4cf
DV		 9484 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9485
9486 /* Wait for the clocks to stabilize. */
9487 POSTING_READ(PCH_DPLL(pll->id));
9488 udelay(150);
9489
9490 /* The pixel multiplier can only be updated once the
9491 * DPLL is enabled and the clocks are stable.
9492 *
9493 * So write it again.
9494 */
9495 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9496 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 9497 udelay(200);
9498}
9499
9500static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
9501 struct intel_shared_dpll *pll)
9502{
9503 struct drm_device *dev = dev_priv->dev;
9504 struct intel_crtc *crtc;
e7b903d2
DV		 9505
9506 /* Make sure no transcoder isn't still depending on us. */
9507 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9508 if (intel_crtc_to_shared_dpll(crtc) == pll)
9509 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 9510 }
9511
15bdd4cf
DV		 9512 I915_WRITE(PCH_DPLL(pll->id), 0);
9513 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 9514 udelay(200);
9515}
9516
46edb027
DV		 9517static char *ibx_pch_dpll_names[] = {
9518 "PCH DPLL A",
9519 "PCH DPLL B",
9520};
9521
7c74ade1 9522static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 9523{
e7b903d2 9524 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 9525 int i;
9526
7c74ade1 9527 dev_priv->num_shared_dpll = 2;
ee7b9f93 9528
e72f9fbf 9529 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 9530 dev_priv->shared_dplls[i].id = i;
9531 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 9532 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 9533 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
9534 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 9535 dev_priv->shared_dplls[i].get_hw_state =
9536 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 9537 }
9538}
9539
7c74ade1
DV		 9540static void intel_shared_dpll_init(struct drm_device *dev)
9541{
e7b903d2 9542 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1
DV		 9543
9544 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9545 ibx_pch_dpll_init(dev);
9546 else
9547 dev_priv->num_shared_dpll = 0;
9548
9549 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
9550 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9551 dev_priv->num_shared_dpll);
9552}
9553
b358d0a6 9554static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 9555{
22fd0fab 9556 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 9557 struct intel_crtc *intel_crtc;
9558 int i;
9559
9560 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
9561 if (intel_crtc == NULL)
9562 return;
9563
9564 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9565
9566 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 9567 for (i = 0; i < 256; i++) {
9568 intel_crtc->lut_r[i] = i;
9569 intel_crtc->lut_g[i] = i;
9570 intel_crtc->lut_b[i] = i;
9571 }
9572
80824003
JB		 9573 /* Swap pipes & planes for FBC on pre-965 */
9574 intel_crtc->pipe = pipe;
9575 intel_crtc->plane = pipe;
e2e767ab 9576 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 9577 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 9578 intel_crtc->plane = !pipe;
80824003
JB		 9579 }
9580
22fd0fab
JB		 9581 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9582 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9583 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9584 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9585
79e53945 9586 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 9587}
9588
08d7b3d1 9589int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 9590 struct drm_file *file)
08d7b3d1 9591{
08d7b3d1 9592 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 9593 struct drm_mode_object *drmmode_obj;
9594 struct intel_crtc *crtc;
08d7b3d1 9595
1cff8f6b
DV		 9596 if (!drm_core_check_feature(dev, DRIVER_MODESET))
9597 return -ENODEV;
08d7b3d1 9598
c05422d5
DV		 9599 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9600 DRM_MODE_OBJECT_CRTC);
08d7b3d1 9601
c05422d5 9602 if (!drmmode_obj) {
08d7b3d1
CW		 9603 DRM_ERROR("no such CRTC id\n");
9604 return -EINVAL;
9605 }
9606
c05422d5
DV		 9607 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9608 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 9609
c05422d5 9610 return 0;
08d7b3d1
CW		 9611}
9612
66a9278e 9613static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 9614{
66a9278e
DV		 9615 struct drm_device *dev = encoder->base.dev;
9616 struct intel_encoder *source_encoder;
79e53945 9617 int index_mask = 0;
79e53945
JB		 9618 int entry = 0;
9619
66a9278e
DV		 9620 list_for_each_entry(source_encoder,
9621 &dev->mode_config.encoder_list, base.head) {
9622
9623 if (encoder == source_encoder)
79e53945 9624 index_mask |= (1 << entry);
66a9278e
DV		 9625
9626 /* Intel hw has only one MUX where enocoders could be cloned. */
9627 if (encoder->cloneable && source_encoder->cloneable)
9628 index_mask |= (1 << entry);
9629
79e53945
JB		 9630 entry++;
9631 }
4ef69c7a 9632
79e53945
JB		 9633 return index_mask;
9634}
9635
4d302442
CW		 9636static bool has_edp_a(struct drm_device *dev)
9637{
9638 struct drm_i915_private *dev_priv = dev->dev_private;
9639
9640 if (!IS_MOBILE(dev))
9641 return false;
9642
9643 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9644 return false;
9645
9646 if (IS_GEN5(dev) &&
9647 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9648 return false;
9649
9650 return true;
9651}
9652
79e53945
JB		 9653static void intel_setup_outputs(struct drm_device *dev)
9654{
725e30ad 9655 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 9656 struct intel_encoder *encoder;
cb0953d7 9657 bool dpd_is_edp = false;
79e53945 9658
c9093354 9659 intel_lvds_init(dev);
79e53945 9660
c40c0f5b 9661 if (!IS_ULT(dev))
79935fca 9662 intel_crt_init(dev);
cb0953d7 9663
affa9354 9664 if (HAS_DDI(dev)) {
0e72a5b5
ED		 9665 int found;
9666
9667 /* Haswell uses DDI functions to detect digital outputs */
9668 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9669 /* DDI A only supports eDP */
9670 if (found)
9671 intel_ddi_init(dev, PORT_A);
9672
9673 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9674 * register */
9675 found = I915_READ(SFUSE_STRAP);
9676
9677 if (found & SFUSE_STRAP_DDIB_DETECTED)
9678 intel_ddi_init(dev, PORT_B);
9679 if (found & SFUSE_STRAP_DDIC_DETECTED)
9680 intel_ddi_init(dev, PORT_C);
9681 if (found & SFUSE_STRAP_DDID_DETECTED)
9682 intel_ddi_init(dev, PORT_D);
9683 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 9684 int found;
270b3042
DV		 9685 dpd_is_edp = intel_dpd_is_edp(dev);
9686
9687 if (has_edp_a(dev))
9688 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 9689
dc0fa718 9690 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 9691 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 9692 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 9693 if (!found)
e2debe91 9694 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 9695 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 9696 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 9697 }
9698
dc0fa718 9699 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 9700 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 9701
dc0fa718 9702 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 9703 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 9704
5eb08b69 9705 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 9706 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 9707
270b3042 9708 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 9709 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 9710 } else if (IS_VALLEYVIEW(dev)) {
19c03924 9711 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
6f6005a5
JB		 9712 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
9713 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
9714 PORT_C);
9715 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9716 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
9717 PORT_C);
9718 }
19c03924 9719
dc0fa718 9720 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 9721 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9722 PORT_B);
67cfc203
VS		 9723 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9724 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 9725 }
3cfca973
JN		 9726
9727 intel_dsi_init(dev);
103a196f 9728 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 9729 bool found = false;
7d57382e 9730
e2debe91 9731 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9732 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 9733 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 9734 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9735 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 9736 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 9737 }
27185ae1 9738
e7281eab 9739 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9740 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 9741 }
13520b05
KH		 9742
9743 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 9744
e2debe91 9745 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9746 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 9747 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 9748 }
27185ae1 9749
e2debe91 9750 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 9751
b01f2c3a
JB		 9752 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9753 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 9754 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 9755 }
e7281eab 9756 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9757 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 9758 }
27185ae1 9759
b01f2c3a 9760 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 9761 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 9762 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 9763 } else if (IS_GEN2(dev))
79e53945
JB		 9764 intel_dvo_init(dev);
9765
103a196f 9766 if (SUPPORTS_TV(dev))
79e53945
JB		 9767 intel_tv_init(dev);
9768
4ef69c7a
CW		 9769 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9770 encoder->base.possible_crtcs = encoder->crtc_mask;
9771 encoder->base.possible_clones =
66a9278e 9772 intel_encoder_clones(encoder);
79e53945 9773 }
47356eb6 9774
dde86e2d 9775 intel_init_pch_refclk(dev);
270b3042
DV		 9776
9777 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 9778}
9779
ddfe1567
CW		 9780void intel_framebuffer_fini(struct intel_framebuffer *fb)
9781{
9782 drm_framebuffer_cleanup(&fb->base);
9783 drm_gem_object_unreference_unlocked(&fb->obj->base);
9784}
9785
79e53945
JB		 9786static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9787{
9788 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 9789
ddfe1567 9790 intel_framebuffer_fini(intel_fb);
79e53945
JB		 9791 kfree(intel_fb);
9792}
9793
9794static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 9795 struct drm_file *file,
79e53945
JB		 9796 unsigned int *handle)
9797{
9798 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 9799 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 9800
05394f39 9801 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 9802}
9803
9804static const struct drm_framebuffer_funcs intel_fb_funcs = {
9805 .destroy = intel_user_framebuffer_destroy,
9806 .create_handle = intel_user_framebuffer_create_handle,
9807};
9808
38651674
DA		 9809int intel_framebuffer_init(struct drm_device *dev,
9810 struct intel_framebuffer *intel_fb,
308e5bcb 9811 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 9812 struct drm_i915_gem_object *obj)
79e53945 9813{
a35cdaa0 9814 int pitch_limit;
79e53945
JB		 9815 int ret;
9816
c16ed4be
CW		 9817 if (obj->tiling_mode == I915_TILING_Y) {
9818 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 9819 return -EINVAL;
c16ed4be 9820 }
57cd6508 9821
c16ed4be
CW		 9822 if (mode_cmd->pitches[0] & 63) {
9823 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9824 mode_cmd->pitches[0]);
57cd6508 9825 return -EINVAL;
c16ed4be 9826 }
57cd6508 9827
a35cdaa0
CW		 9828 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9829 pitch_limit = 32*1024;
9830 } else if (INTEL_INFO(dev)->gen >= 4) {
9831 if (obj->tiling_mode)
9832 pitch_limit = 16*1024;
9833 else
9834 pitch_limit = 32*1024;
9835 } else if (INTEL_INFO(dev)->gen >= 3) {
9836 if (obj->tiling_mode)
9837 pitch_limit = 8*1024;
9838 else
9839 pitch_limit = 16*1024;
9840 } else
9841 /* XXX DSPC is limited to 4k tiled */
9842 pitch_limit = 8*1024;
9843
9844 if (mode_cmd->pitches[0] > pitch_limit) {
9845 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9846 obj->tiling_mode ? "tiled" : "linear",
9847 mode_cmd->pitches[0], pitch_limit);
5d7bd705 9848 return -EINVAL;
c16ed4be 9849 }
5d7bd705
VS		 9850
9851 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 9852 mode_cmd->pitches[0] != obj->stride) {
9853 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9854 mode_cmd->pitches[0], obj->stride);
5d7bd705 9855 return -EINVAL;
c16ed4be 9856 }
5d7bd705 9857
57779d06 9858 /* Reject formats not supported by any plane early. */
308e5bcb 9859 switch (mode_cmd->pixel_format) {
57779d06 9860 case DRM_FORMAT_C8:
04b3924d
VS		 9861 case DRM_FORMAT_RGB565:
9862 case DRM_FORMAT_XRGB8888:
9863 case DRM_FORMAT_ARGB8888:
57779d06
VS		 9864 break;
9865 case DRM_FORMAT_XRGB1555:
9866 case DRM_FORMAT_ARGB1555:
c16ed4be 9867 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 9868 DRM_DEBUG("unsupported pixel format: %s\n",
9869 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9870 return -EINVAL;
c16ed4be 9871 }
57779d06
VS		 9872 break;
9873 case DRM_FORMAT_XBGR8888:
9874 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 9875 case DRM_FORMAT_XRGB2101010:
9876 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 9877 case DRM_FORMAT_XBGR2101010:
9878 case DRM_FORMAT_ABGR2101010:
c16ed4be 9879 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 9880 DRM_DEBUG("unsupported pixel format: %s\n",
9881 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9882 return -EINVAL;
c16ed4be 9883 }
b5626747 9884 break;
04b3924d
VS		 9885 case DRM_FORMAT_YUYV:
9886 case DRM_FORMAT_UYVY:
9887 case DRM_FORMAT_YVYU:
9888 case DRM_FORMAT_VYUY:
c16ed4be 9889 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 9890 DRM_DEBUG("unsupported pixel format: %s\n",
9891 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9892 return -EINVAL;
c16ed4be 9893 }
57cd6508
CW		 9894 break;
9895 default:
4ee62c76
VS		 9896 DRM_DEBUG("unsupported pixel format: %s\n",
9897 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 9898 return -EINVAL;
9899 }
9900
90f9a336
VS		 9901 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9902 if (mode_cmd->offsets[0] != 0)
9903 return -EINVAL;
9904
c7d73f6a
DV		 9905 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9906 intel_fb->obj = obj;
9907
79e53945
JB		 9908 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9909 if (ret) {
9910 DRM_ERROR("framebuffer init failed %d\n", ret);
9911 return ret;
9912 }
9913
79e53945
JB		 9914 return 0;
9915}
9916
79e53945
JB		 9917static struct drm_framebuffer *
9918intel_user_framebuffer_create(struct drm_device *dev,
9919 struct drm_file *filp,
308e5bcb 9920 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 9921{
05394f39 9922 struct drm_i915_gem_object *obj;
79e53945 9923
308e5bcb
JB		 9924 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9925 mode_cmd->handles[0]));
c8725226 9926 if (&obj->base == NULL)
cce13ff7 9927 return ERR_PTR(-ENOENT);
79e53945 9928
d2dff872 9929 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 9930}
9931
79e53945 9932static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 9933 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 9934 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 9935};
9936
e70236a8
JB		 9937/* Set up chip specific display functions */
9938static void intel_init_display(struct drm_device *dev)
9939{
9940 struct drm_i915_private *dev_priv = dev->dev_private;
9941
ee9300bb
DV		 9942 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9943 dev_priv->display.find_dpll = g4x_find_best_dpll;
9944 else if (IS_VALLEYVIEW(dev))
9945 dev_priv->display.find_dpll = vlv_find_best_dpll;
9946 else if (IS_PINEVIEW(dev))
9947 dev_priv->display.find_dpll = pnv_find_best_dpll;
9948 else
9949 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9950
affa9354 9951 if (HAS_DDI(dev)) {
0e8ffe1b 9952 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 9953 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 9954 dev_priv->display.crtc_enable = haswell_crtc_enable;
9955 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 9956 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 9957 dev_priv->display.update_plane = ironlake_update_plane;
9958 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 9959 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f564048e 9960 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 9961 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9962 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 9963 dev_priv->display.off = ironlake_crtc_off;
17638cd6 9964 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 9965 } else if (IS_VALLEYVIEW(dev)) {
9966 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9967 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9968 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9969 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9970 dev_priv->display.off = i9xx_crtc_off;
9971 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9972 } else {
0e8ffe1b 9973 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f564048e 9974 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 9975 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9976 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 9977 dev_priv->display.off = i9xx_crtc_off;
17638cd6 9978 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9979 }
e70236a8 9980
e70236a8 9981 /* Returns the core display clock speed */
25eb05fc
JB		 9982 if (IS_VALLEYVIEW(dev))
9983 dev_priv->display.get_display_clock_speed =
9984 valleyview_get_display_clock_speed;
9985 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 9986 dev_priv->display.get_display_clock_speed =
9987 i945_get_display_clock_speed;
9988 else if (IS_I915G(dev))
9989 dev_priv->display.get_display_clock_speed =
9990 i915_get_display_clock_speed;
257a7ffc 9991 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 9992 dev_priv->display.get_display_clock_speed =
9993 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 9994 else if (IS_PINEVIEW(dev))
9995 dev_priv->display.get_display_clock_speed =
9996 pnv_get_display_clock_speed;
e70236a8
JB		 9997 else if (IS_I915GM(dev))
9998 dev_priv->display.get_display_clock_speed =
9999 i915gm_get_display_clock_speed;
10000 else if (IS_I865G(dev))
10001 dev_priv->display.get_display_clock_speed =
10002 i865_get_display_clock_speed;
f0f8a9ce 10003 else if (IS_I85X(dev))
e70236a8
JB		 10004 dev_priv->display.get_display_clock_speed =
10005 i855_get_display_clock_speed;
10006 else /* 852, 830 */
10007 dev_priv->display.get_display_clock_speed =
10008 i830_get_display_clock_speed;
10009
7f8a8569 10010 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 10011 if (IS_GEN5(dev)) {
674cf967 10012 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 10013 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 10014 } else if (IS_GEN6(dev)) {
674cf967 10015 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 10016 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 10017 } else if (IS_IVYBRIDGE(dev)) {
10018 /* FIXME: detect B0+ stepping and use auto training */
10019 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 10020 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 10021 dev_priv->display.modeset_global_resources =
10022 ivb_modeset_global_resources;
c82e4d26
ED		 10023 } else if (IS_HASWELL(dev)) {
10024 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 10025 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 10026 dev_priv->display.modeset_global_resources =
10027 haswell_modeset_global_resources;
a0e63c22 10028 }
6067aaea 10029 } else if (IS_G4X(dev)) {
e0dac65e 10030 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 10031 }
8c9f3aaf
JB		 10032
10033 /* Default just returns -ENODEV to indicate unsupported */
10034 dev_priv->display.queue_flip = intel_default_queue_flip;
10035
10036 switch (INTEL_INFO(dev)->gen) {
10037 case 2:
10038 dev_priv->display.queue_flip = intel_gen2_queue_flip;
10039 break;
10040
10041 case 3:
10042 dev_priv->display.queue_flip = intel_gen3_queue_flip;
10043 break;
10044
10045 case 4:
10046 case 5:
10047 dev_priv->display.queue_flip = intel_gen4_queue_flip;
10048 break;
10049
10050 case 6:
10051 dev_priv->display.queue_flip = intel_gen6_queue_flip;
10052 break;
7c9017e5
JB		 10053 case 7:
10054 dev_priv->display.queue_flip = intel_gen7_queue_flip;
10055 break;
8c9f3aaf 10056 }
e70236a8
JB		 10057}
10058
b690e96c
JB		 10059/*
10060 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
10061 * resume, or other times. This quirk makes sure that's the case for
10062 * affected systems.
10063 */
0206e353 10064static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 10065{
10066 struct drm_i915_private *dev_priv = dev->dev_private;
10067
10068 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 10069 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 10070}
10071
435793df
KP		 10072/*
10073 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
10074 */
10075static void quirk_ssc_force_disable(struct drm_device *dev)
10076{
10077 struct drm_i915_private *dev_priv = dev->dev_private;
10078 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 10079 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 10080}
10081
4dca20ef 10082/*
5a15ab5b
CE		 10083 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
10084 * brightness value
4dca20ef
CE		 10085 */
10086static void quirk_invert_brightness(struct drm_device *dev)
10087{
10088 struct drm_i915_private *dev_priv = dev->dev_private;
10089 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 10090 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 10091}
10092
e85843be
KM		 10093/*
10094 * Some machines (Dell XPS13) suffer broken backlight controls if
10095 * BLM_PCH_PWM_ENABLE is set.
10096 */
10097static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
10098{
10099 struct drm_i915_private *dev_priv = dev->dev_private;
10100 dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
10101 DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
10102}
10103
b690e96c
JB		 10104struct intel_quirk {
10105 int device;
10106 int subsystem_vendor;
10107 int subsystem_device;
10108 void (*hook)(struct drm_device *dev);
10109};
10110
5f85f176
EE		 10111/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
10112struct intel_dmi_quirk {
10113 void (*hook)(struct drm_device *dev);
10114 const struct dmi_system_id (*dmi_id_list)[];
10115};
10116
10117static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
10118{
10119 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
10120 return 1;
10121}
10122
10123static const struct intel_dmi_quirk intel_dmi_quirks[] = {
10124 {
10125 .dmi_id_list = &(const struct dmi_system_id[]) {
10126 {
10127 .callback = intel_dmi_reverse_brightness,
10128 .ident = "NCR Corporation",
10129 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
10130 DMI_MATCH(DMI_PRODUCT_NAME, ""),
10131 },
10132 },
10133 { } /* terminating entry */
10134 },
10135 .hook = quirk_invert_brightness,
10136 },
10137};
10138
c43b5634 10139static struct intel_quirk intel_quirks[] = {
b690e96c 10140 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 10141 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 10142
b690e96c
JB		 10143 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10144 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
10145
b690e96c
JB		 10146 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10147 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
10148
ccd0d36e 10149 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 10150 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 10151 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 10152
10153 /* Lenovo U160 cannot use SSC on LVDS */
10154 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 10155
10156 /* Sony Vaio Y cannot use SSC on LVDS */
10157 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 10158
10159 /* Acer Aspire 5734Z must invert backlight brightness */
10160 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 10161
10162 /* Acer/eMachines G725 */
10163 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 10164
10165 /* Acer/eMachines e725 */
10166 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 10167
10168 /* Acer/Packard Bell NCL20 */
10169 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 10170
10171 /* Acer Aspire 4736Z */
10172 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
e85843be
KM		 10173
10174 /* Dell XPS13 HD Sandy Bridge */
10175 { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
10176 /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
10177 { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
b690e96c
JB		 10178};
10179
10180static void intel_init_quirks(struct drm_device *dev)
10181{
10182 struct pci_dev *d = dev->pdev;
10183 int i;
10184
10185 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
10186 struct intel_quirk *q = &intel_quirks[i];
10187
10188 if (d->device == q->device &&
10189 (d->subsystem_vendor == q->subsystem_vendor ||
10190 q->subsystem_vendor == PCI_ANY_ID) &&
10191 (d->subsystem_device == q->subsystem_device ||
10192 q->subsystem_device == PCI_ANY_ID))
10193 q->hook(dev);
10194 }
5f85f176
EE		 10195 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10196 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10197 intel_dmi_quirks[i].hook(dev);
10198 }
b690e96c
JB		 10199}
10200
9cce37f4
JB		 10201/* Disable the VGA plane that we never use */
10202static void i915_disable_vga(struct drm_device *dev)
10203{
10204 struct drm_i915_private *dev_priv = dev->dev_private;
10205 u8 sr1;
766aa1c4 10206 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 10207
10208 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 10209 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 10210 sr1 = inb(VGA_SR_DATA);
10211 outb(sr1 | 1<<5, VGA_SR_DATA);
81b5c7bc
AW		 10212
10213 /* Disable VGA memory on Intel HD */
10214 if (HAS_PCH_SPLIT(dev)) {
10215 outb(inb(VGA_MSR_READ) & ~VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10216 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10217 VGA_RSRC_NORMAL_IO |
10218 VGA_RSRC_NORMAL_MEM);
10219 }
10220
9cce37f4
JB		 10221 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10222 udelay(300);
10223
10224 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10225 POSTING_READ(vga_reg);
10226}
10227
81b5c7bc
AW		 10228static void i915_enable_vga(struct drm_device *dev)
10229{
10230 /* Enable VGA memory on Intel HD */
10231 if (HAS_PCH_SPLIT(dev)) {
10232 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10233 outb(inb(VGA_MSR_READ) | VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10234 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10235 VGA_RSRC_LEGACY_MEM |
10236 VGA_RSRC_NORMAL_IO |
10237 VGA_RSRC_NORMAL_MEM);
10238 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10239 }
10240}
10241
f817586c
DV		 10242void intel_modeset_init_hw(struct drm_device *dev)
10243{
fa42e23c 10244 intel_init_power_well(dev);
0232e927 10245
a8f78b58
ED		 10246 intel_prepare_ddi(dev);
10247
f817586c
DV		 10248 intel_init_clock_gating(dev);
10249
79f5b2c7 10250 mutex_lock(&dev->struct_mutex);
8090c6b9 10251 intel_enable_gt_powersave(dev);
79f5b2c7 10252 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 10253}
10254
7d708ee4
ID		 10255void intel_modeset_suspend_hw(struct drm_device *dev)
10256{
10257 intel_suspend_hw(dev);
10258}
10259
79e53945
JB		 10260void intel_modeset_init(struct drm_device *dev)
10261{
652c393a 10262 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 10263 int i, j, ret;
79e53945
JB		 10264
10265 drm_mode_config_init(dev);
10266
10267 dev->mode_config.min_width = 0;
10268 dev->mode_config.min_height = 0;
10269
019d96cb
DA		 10270 dev->mode_config.preferred_depth = 24;
10271 dev->mode_config.prefer_shadow = 1;
10272
e6ecefaa 10273 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 10274
b690e96c
JB		 10275 intel_init_quirks(dev);
10276
1fa61106
ED		 10277 intel_init_pm(dev);
10278
e3c74757
BW		 10279 if (INTEL_INFO(dev)->num_pipes == 0)
10280 return;
10281
e70236a8
JB		 10282 intel_init_display(dev);
10283
a6c45cf0
CW		 10284 if (IS_GEN2(dev)) {
10285 dev->mode_config.max_width = 2048;
10286 dev->mode_config.max_height = 2048;
10287 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 10288 dev->mode_config.max_width = 4096;
10289 dev->mode_config.max_height = 4096;
79e53945 10290 } else {
a6c45cf0
CW		 10291 dev->mode_config.max_width = 8192;
10292 dev->mode_config.max_height = 8192;
79e53945 10293 }
5d4545ae 10294 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 10295
28c97730 10296 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 10297 INTEL_INFO(dev)->num_pipes,
10298 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 10299
08e2a7de 10300 for_each_pipe(i) {
79e53945 10301 intel_crtc_init(dev, i);
7f1f3851
JB		 10302 for (j = 0; j < dev_priv->num_plane; j++) {
10303 ret = intel_plane_init(dev, i, j);
10304 if (ret)
06da8da2
VS		 10305 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10306 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 10307 }
79e53945
JB		 10308 }
10309
79f689aa 10310 intel_cpu_pll_init(dev);
e72f9fbf 10311 intel_shared_dpll_init(dev);
ee7b9f93 10312
9cce37f4
JB		 10313 /* Just disable it once at startup */
10314 i915_disable_vga(dev);
79e53945 10315 intel_setup_outputs(dev);
11be49eb
CW		 10316
10317 /* Just in case the BIOS is doing something questionable. */
10318 intel_disable_fbc(dev);
2c7111db
CW		 10319}
10320
24929352
DV		 10321static void
10322intel_connector_break_all_links(struct intel_connector *connector)
10323{
10324 connector->base.dpms = DRM_MODE_DPMS_OFF;
10325 connector->base.encoder = NULL;
10326 connector->encoder->connectors_active = false;
10327 connector->encoder->base.crtc = NULL;
10328}
10329
7fad798e
DV		 10330static void intel_enable_pipe_a(struct drm_device *dev)
10331{
10332 struct intel_connector *connector;
10333 struct drm_connector *crt = NULL;
10334 struct intel_load_detect_pipe load_detect_temp;
10335
10336 /* We can't just switch on the pipe A, we need to set things up with a
10337 * proper mode and output configuration. As a gross hack, enable pipe A
10338 * by enabling the load detect pipe once. */
10339 list_for_each_entry(connector,
10340 &dev->mode_config.connector_list,
10341 base.head) {
10342 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
10343 crt = &connector->base;
10344 break;
10345 }
10346 }
10347
10348 if (!crt)
10349 return;
10350
10351 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
10352 intel_release_load_detect_pipe(crt, &load_detect_temp);
10353
652c393a 10354
7fad798e
DV		 10355}
10356
fa555837
DV		 10357static bool
10358intel_check_plane_mapping(struct intel_crtc *crtc)
10359{
7eb552ae
BW		 10360 struct drm_device *dev = crtc->base.dev;
10361 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 10362 u32 reg, val;
10363
7eb552ae 10364 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 10365 return true;
10366
10367 reg = DSPCNTR(!crtc->plane);
10368 val = I915_READ(reg);
10369
10370 if ((val & DISPLAY_PLANE_ENABLE) &&
10371 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
10372 return false;
10373
10374 return true;
10375}
10376
24929352
DV		 10377static void intel_sanitize_crtc(struct intel_crtc *crtc)
10378{
10379 struct drm_device *dev = crtc->base.dev;
10380 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 10381 u32 reg;
24929352 10382
24929352 10383 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 10384 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 10385 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
10386
10387 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 10388 * disable the crtc (and hence change the state) if it is wrong. Note
10389 * that gen4+ has a fixed plane -> pipe mapping. */
10390 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 10391 struct intel_connector *connector;
10392 bool plane;
10393
24929352
DV		 10394 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10395 crtc->base.base.id);
10396
10397 /* Pipe has the wrong plane attached and the plane is active.
10398 * Temporarily change the plane mapping and disable everything
10399 * ... */
10400 plane = crtc->plane;
10401 crtc->plane = !plane;
10402 dev_priv->display.crtc_disable(&crtc->base);
10403 crtc->plane = plane;
10404
10405 /* ... and break all links. */
10406 list_for_each_entry(connector, &dev->mode_config.connector_list,
10407 base.head) {
10408 if (connector->encoder->base.crtc != &crtc->base)
10409 continue;
10410
10411 intel_connector_break_all_links(connector);
10412 }
10413
10414 WARN_ON(crtc->active);
10415 crtc->base.enabled = false;
10416 }
24929352 10417
7fad798e
DV		 10418 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
10419 crtc->pipe == PIPE_A && !crtc->active) {
10420 /* BIOS forgot to enable pipe A, this mostly happens after
10421 * resume. Force-enable the pipe to fix this, the update_dpms
10422 * call below we restore the pipe to the right state, but leave
10423 * the required bits on. */
10424 intel_enable_pipe_a(dev);
10425 }
10426
24929352
DV		 10427 /* Adjust the state of the output pipe according to whether we
10428 * have active connectors/encoders. */
10429 intel_crtc_update_dpms(&crtc->base);
10430
10431 if (crtc->active != crtc->base.enabled) {
10432 struct intel_encoder *encoder;
10433
10434 /* This can happen either due to bugs in the get_hw_state
10435 * functions or because the pipe is force-enabled due to the
10436 * pipe A quirk. */
10437 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10438 crtc->base.base.id,
10439 crtc->base.enabled ? "enabled" : "disabled",
10440 crtc->active ? "enabled" : "disabled");
10441
10442 crtc->base.enabled = crtc->active;
10443
10444 /* Because we only establish the connector -> encoder ->
10445 * crtc links if something is active, this means the
10446 * crtc is now deactivated. Break the links. connector
10447 * -> encoder links are only establish when things are
10448 * actually up, hence no need to break them. */
10449 WARN_ON(crtc->active);
10450
10451 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
10452 WARN_ON(encoder->connectors_active);
10453 encoder->base.crtc = NULL;
10454 }
10455 }
10456}
10457
10458static void intel_sanitize_encoder(struct intel_encoder *encoder)
10459{
10460 struct intel_connector *connector;
10461 struct drm_device *dev = encoder->base.dev;
10462
10463 /* We need to check both for a crtc link (meaning that the
10464 * encoder is active and trying to read from a pipe) and the
10465 * pipe itself being active. */
10466 bool has_active_crtc = encoder->base.crtc &&
10467 to_intel_crtc(encoder->base.crtc)->active;
10468
10469 if (encoder->connectors_active && !has_active_crtc) {
10470 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10471 encoder->base.base.id,
10472 drm_get_encoder_name(&encoder->base));
10473
10474 /* Connector is active, but has no active pipe. This is
10475 * fallout from our resume register restoring. Disable
10476 * the encoder manually again. */
10477 if (encoder->base.crtc) {
10478 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10479 encoder->base.base.id,
10480 drm_get_encoder_name(&encoder->base));
10481 encoder->disable(encoder);
10482 }
10483
10484 /* Inconsistent output/port/pipe state happens presumably due to
10485 * a bug in one of the get_hw_state functions. Or someplace else
10486 * in our code, like the register restore mess on resume. Clamp
10487 * things to off as a safer default. */
10488 list_for_each_entry(connector,
10489 &dev->mode_config.connector_list,
10490 base.head) {
10491 if (connector->encoder != encoder)
10492 continue;
10493
10494 intel_connector_break_all_links(connector);
10495 }
10496 }
10497 /* Enabled encoders without active connectors will be fixed in
10498 * the crtc fixup. */
10499}
10500
44cec740 10501void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 10502{
10503 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 10504 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 10505
8dc8a27c
PZ		 10506 /* This function can be called both from intel_modeset_setup_hw_state or
10507 * at a very early point in our resume sequence, where the power well
10508 * structures are not yet restored. Since this function is at a very
10509 * paranoid "someone might have enabled VGA while we were not looking"
10510 * level, just check if the power well is enabled instead of trying to
10511 * follow the "don't touch the power well if we don't need it" policy
10512 * the rest of the driver uses. */
10513 if (HAS_POWER_WELL(dev) &&
6aedd1f5 10514 (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
8dc8a27c
PZ		 10515 return;
10516
0fde901f
KM		 10517 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
10518 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 10519 i915_disable_vga(dev);
0fde901f
KM		 10520 }
10521}
10522
30e984df 10523static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 10524{
10525 struct drm_i915_private *dev_priv = dev->dev_private;
10526 enum pipe pipe;
24929352
DV		 10527 struct intel_crtc *crtc;
10528 struct intel_encoder *encoder;
10529 struct intel_connector *connector;
5358901f 10530 int i;
24929352 10531
0e8ffe1b
DV		 10532 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10533 base.head) {
88adfff1 10534 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f 10535
0e8ffe1b
DV		 10536 crtc->active = dev_priv->display.get_pipe_config(crtc,
10537 &crtc->config);
24929352
DV		 10538
10539 crtc->base.enabled = crtc->active;
10540
10541 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10542 crtc->base.base.id,
10543 crtc->active ? "enabled" : "disabled");
10544 }
10545
5358901f 10546 /* FIXME: Smash this into the new shared dpll infrastructure. */
affa9354 10547 if (HAS_DDI(dev))
6441ab5f
PZ		 10548 intel_ddi_setup_hw_pll_state(dev);
10549
5358901f
DV		 10550 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10551 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10552
10553 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
10554 pll->active = 0;
10555 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10556 base.head) {
10557 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10558 pll->active++;
10559 }
10560 pll->refcount = pll->active;
10561
35c95375
DV		 10562 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10563 pll->name, pll->refcount, pll->on);
5358901f
DV		 10564 }
10565
24929352
DV		 10566 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10567 base.head) {
10568 pipe = 0;
10569
10570 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 10571 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10572 encoder->base.crtc = &crtc->base;
510d5f2f 10573 if (encoder->get_config)
045ac3b5 10574 encoder->get_config(encoder, &crtc->config);
24929352
DV		 10575 } else {
10576 encoder->base.crtc = NULL;
10577 }
10578
10579 encoder->connectors_active = false;
10580 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
10581 encoder->base.base.id,
10582 drm_get_encoder_name(&encoder->base),
10583 encoder->base.crtc ? "enabled" : "disabled",
10584 pipe);
10585 }
10586
10587 list_for_each_entry(connector, &dev->mode_config.connector_list,
10588 base.head) {
10589 if (connector->get_hw_state(connector)) {
10590 connector->base.dpms = DRM_MODE_DPMS_ON;
10591 connector->encoder->connectors_active = true;
10592 connector->base.encoder = &connector->encoder->base;
10593 } else {
10594 connector->base.dpms = DRM_MODE_DPMS_OFF;
10595 connector->base.encoder = NULL;
10596 }
10597 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10598 connector->base.base.id,
10599 drm_get_connector_name(&connector->base),
10600 connector->base.encoder ? "enabled" : "disabled");
10601 }
30e984df
DV		 10602}
10603
10604/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10605 * and i915 state tracking structures. */
10606void intel_modeset_setup_hw_state(struct drm_device *dev,
10607 bool force_restore)
10608{
10609 struct drm_i915_private *dev_priv = dev->dev_private;
10610 enum pipe pipe;
10611 struct drm_plane *plane;
10612 struct intel_crtc *crtc;
10613 struct intel_encoder *encoder;
35c95375 10614 int i;
30e984df
DV		 10615
10616 intel_modeset_readout_hw_state(dev);
24929352 10617
babea61d
JB		 10618 /*
10619 * Now that we have the config, copy it to each CRTC struct
10620 * Note that this could go away if we move to using crtc_config
10621 * checking everywhere.
10622 */
10623 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10624 base.head) {
10625 if (crtc->active && i915_fastboot) {
10626 intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10627
10628 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10629 crtc->base.base.id);
10630 drm_mode_debug_printmodeline(&crtc->base.mode);
10631 }
10632 }
10633
24929352
DV		 10634 /* HW state is read out, now we need to sanitize this mess. */
10635 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10636 base.head) {
10637 intel_sanitize_encoder(encoder);
10638 }
10639
10640 for_each_pipe(pipe) {
10641 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10642 intel_sanitize_crtc(crtc);
c0b03411 10643 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
24929352 10644 }
9a935856 10645
35c95375
DV		 10646 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10647 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10648
10649 if (!pll->on || pll->active)
10650 continue;
10651
10652 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
10653
10654 pll->disable(dev_priv, pll);
10655 pll->on = false;
10656 }
10657
45e2b5f6 10658 if (force_restore) {
f30da187
DV		 10659 /*
10660 * We need to use raw interfaces for restoring state to avoid
10661 * checking (bogus) intermediate states.
10662 */
45e2b5f6 10663 for_each_pipe(pipe) {
b5644d05
JB		 10664 struct drm_crtc *crtc =
10665 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 10666
10667 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10668 crtc->fb);
45e2b5f6 10669 }
b5644d05
JB		 10670 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
10671 intel_plane_restore(plane);
0fde901f
KM		 10672
10673 i915_redisable_vga(dev);
45e2b5f6
DV		 10674 } else {
10675 intel_modeset_update_staged_output_state(dev);
10676 }
8af6cf88
DV		 10677
10678 intel_modeset_check_state(dev);
2e938892
DV		 10679
10680 drm_mode_config_reset(dev);
2c7111db
CW		 10681}
10682
10683void intel_modeset_gem_init(struct drm_device *dev)
10684{
1833b134 10685 intel_modeset_init_hw(dev);
02e792fb
DV		 10686
10687 intel_setup_overlay(dev);
24929352 10688
45e2b5f6 10689 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 10690}
10691
10692void intel_modeset_cleanup(struct drm_device *dev)
10693{
652c393a
JB		 10694 struct drm_i915_private *dev_priv = dev->dev_private;
10695 struct drm_crtc *crtc;
652c393a 10696
fd0c0642
DV		 10697 /*
10698 * Interrupts and polling as the first thing to avoid creating havoc.
10699 * Too much stuff here (turning of rps, connectors, ...) would
10700 * experience fancy races otherwise.
10701 */
10702 drm_irq_uninstall(dev);
10703 cancel_work_sync(&dev_priv->hotplug_work);
10704 /*
10705 * Due to the hpd irq storm handling the hotplug work can re-arm the
10706 * poll handlers. Hence disable polling after hpd handling is shut down.
10707 */
f87ea761 10708 drm_kms_helper_poll_fini(dev);
fd0c0642 10709
652c393a
JB		 10710 mutex_lock(&dev->struct_mutex);
10711
723bfd70
JB		 10712 intel_unregister_dsm_handler();
10713
652c393a
JB		 10714 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10715 /* Skip inactive CRTCs */
10716 if (!crtc->fb)
10717 continue;
10718
3dec0095 10719 intel_increase_pllclock(crtc);
652c393a
JB		 10720 }
10721
973d04f9 10722 intel_disable_fbc(dev);
e70236a8 10723
81b5c7bc
AW		 10724 i915_enable_vga(dev);
10725
8090c6b9 10726 intel_disable_gt_powersave(dev);
0cdab21f 10727
930ebb46
DV		 10728 ironlake_teardown_rc6(dev);
10729
69341a5e
KH		 10730 mutex_unlock(&dev->struct_mutex);
10731
1630fe75
CW		 10732 /* flush any delayed tasks or pending work */
10733 flush_scheduled_work();
10734
dc652f90
JN		 10735 /* destroy backlight, if any, before the connectors */
10736 intel_panel_destroy_backlight(dev);
10737
79e53945 10738 drm_mode_config_cleanup(dev);
4d7bb011
DV		 10739
10740 intel_cleanup_overlay(dev);
79e53945
JB		 10741}
10742
f1c79df3
ZW		 10743/*
10744 * Return which encoder is currently attached for connector.
10745 */
df0e9248 10746struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 10747{
df0e9248
CW		 10748 return &intel_attached_encoder(connector)->base;
10749}
f1c79df3 10750
df0e9248
CW		 10751void intel_connector_attach_encoder(struct intel_connector *connector,
10752 struct intel_encoder *encoder)
10753{
10754 connector->encoder = encoder;
10755 drm_mode_connector_attach_encoder(&connector->base,
10756 &encoder->base);
79e53945 10757}
28d52043
DA		 10758
10759/*
10760 * set vga decode state - true == enable VGA decode
10761 */
10762int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10763{
10764 struct drm_i915_private *dev_priv = dev->dev_private;
10765 u16 gmch_ctrl;
10766
10767 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
10768 if (state)
10769 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10770 else
10771 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10772 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10773 return 0;
10774}
c4a1d9e4 10775
c4a1d9e4 10776struct intel_display_error_state {
ff57f1b0
PZ		 10777
10778 u32 power_well_driver;
10779
63b66e5b
CW		 10780 int num_transcoders;
10781
c4a1d9e4
CW		 10782 struct intel_cursor_error_state {
10783 u32 control;
10784 u32 position;
10785 u32 base;
10786 u32 size;
52331309 10787 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 10788
10789 struct intel_pipe_error_state {
c4a1d9e4 10790 u32 source;
52331309 10791 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 10792
10793 struct intel_plane_error_state {
10794 u32 control;
10795 u32 stride;
10796 u32 size;
10797 u32 pos;
10798 u32 addr;
10799 u32 surface;
10800 u32 tile_offset;
52331309 10801 } plane[I915_MAX_PIPES];
63b66e5b
CW		 10802
10803 struct intel_transcoder_error_state {
10804 enum transcoder cpu_transcoder;
10805
10806 u32 conf;
10807
10808 u32 htotal;
10809 u32 hblank;
10810 u32 hsync;
10811 u32 vtotal;
10812 u32 vblank;
10813 u32 vsync;
10814 } transcoder[4];
c4a1d9e4
CW		 10815};
10816
10817struct intel_display_error_state *
10818intel_display_capture_error_state(struct drm_device *dev)
10819{
0206e353 10820 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 10821 struct intel_display_error_state *error;
63b66e5b
CW		 10822 int transcoders[] = {
10823 TRANSCODER_A,
10824 TRANSCODER_B,
10825 TRANSCODER_C,
10826 TRANSCODER_EDP,
10827 };
c4a1d9e4
CW		 10828 int i;
10829
63b66e5b
CW		 10830 if (INTEL_INFO(dev)->num_pipes == 0)
10831 return NULL;
10832
c4a1d9e4
CW		 10833 error = kmalloc(sizeof(*error), GFP_ATOMIC);
10834 if (error == NULL)
10835 return NULL;
10836
ff57f1b0
PZ		 10837 if (HAS_POWER_WELL(dev))
10838 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10839
52331309 10840 for_each_pipe(i) {
a18c4c3d
PZ		 10841 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10842 error->cursor[i].control = I915_READ(CURCNTR(i));
10843 error->cursor[i].position = I915_READ(CURPOS(i));
10844 error->cursor[i].base = I915_READ(CURBASE(i));
10845 } else {
10846 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10847 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10848 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10849 }
c4a1d9e4
CW		 10850
10851 error->plane[i].control = I915_READ(DSPCNTR(i));
10852 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 10853 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 10854 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 10855 error->plane[i].pos = I915_READ(DSPPOS(i));
10856 }
ca291363
PZ		 10857 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10858 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 10859 if (INTEL_INFO(dev)->gen >= 4) {
10860 error->plane[i].surface = I915_READ(DSPSURF(i));
10861 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10862 }
10863
c4a1d9e4 10864 error->pipe[i].source = I915_READ(PIPESRC(i));
63b66e5b
CW		 10865 }
10866
10867 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
10868 if (HAS_DDI(dev_priv->dev))
10869 error->num_transcoders++; /* Account for eDP. */
10870
10871 for (i = 0; i < error->num_transcoders; i++) {
10872 enum transcoder cpu_transcoder = transcoders[i];
10873
10874 error->transcoder[i].cpu_transcoder = cpu_transcoder;
10875
10876 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
10877 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10878 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10879 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10880 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10881 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10882 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 10883 }
10884
12d217c7
PZ		 10885 /* In the code above we read the registers without checking if the power
10886 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10887 * prevent the next I915_WRITE from detecting it and printing an error
10888 * message. */
907b28c5 10889 intel_uncore_clear_errors(dev);
12d217c7 10890
c4a1d9e4
CW		 10891 return error;
10892}
10893
edc3d884
MK		 10894#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10895
c4a1d9e4 10896void
edc3d884 10897intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 10898 struct drm_device *dev,
10899 struct intel_display_error_state *error)
10900{
10901 int i;
10902
63b66e5b
CW		 10903 if (!error)
10904 return;
10905
edc3d884 10906 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
ff57f1b0 10907 if (HAS_POWER_WELL(dev))
edc3d884 10908 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 10909 error->power_well_driver);
52331309 10910 for_each_pipe(i) {
edc3d884 10911 err_printf(m, "Pipe [%d]:\n", i);
edc3d884 10912 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
edc3d884
MK		 10913
10914 err_printf(m, "Plane [%d]:\n", i);
10915 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
10916 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 10917 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 10918 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
10919 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 10920 }
4b71a570 10921 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 10922 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 10923 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 10924 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
10925 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 10926 }
10927
edc3d884
MK		 10928 err_printf(m, "Cursor [%d]:\n", i);
10929 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
10930 err_printf(m, " POS: %08x\n", error->cursor[i].position);
10931 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 10932 }
63b66e5b
CW		 10933
10934 for (i = 0; i < error->num_transcoders; i++) {
10935 err_printf(m, " CPU transcoder: %c\n",
10936 transcoder_name(error->transcoder[i].cpu_transcoder));
10937 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
10938 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
10939 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
10940 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
10941 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
10942 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
10943 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
10944 }
c4a1d9e4 10945}
Linux 6.x block layer and io_uring tree(s)