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drm/i915/skl: enable WaForceContextSaveRestoreNonCoherent
[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
319c1d42 40#include <drm/drm_atomic.h>
c196e1d6 41#include <drm/drm_atomic_helper.h>
760285e7
DH		 42#include <drm/drm_dp_helper.h>
43#include <drm/drm_crtc_helper.h>
465c120c
MR		 44#include <drm/drm_plane_helper.h>
45#include <drm/drm_rect.h>
c0f372b3 46#include <linux/dma_remapping.h>
79e53945 47
465c120c 48/* Primary plane formats for gen <= 3 */
568db4f2 49static const uint32_t i8xx_primary_formats[] = {
67fe7dc5
DL		 50 DRM_FORMAT_C8,
51 DRM_FORMAT_RGB565,
465c120c 52 DRM_FORMAT_XRGB1555,
67fe7dc5 53 DRM_FORMAT_XRGB8888,
465c120c
MR		 54};
55
56/* Primary plane formats for gen >= 4 */
568db4f2 57static const uint32_t i965_primary_formats[] = {
6c0fd451
DL		 58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB8888,
61 DRM_FORMAT_XBGR8888,
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
64};
65
66static const uint32_t skl_primary_formats[] = {
67fe7dc5
DL		 67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
465c120c 70 DRM_FORMAT_XBGR8888,
67fe7dc5 71 DRM_FORMAT_ARGB8888,
465c120c
MR		 72 DRM_FORMAT_ABGR8888,
73 DRM_FORMAT_XRGB2101010,
465c120c 74 DRM_FORMAT_XBGR2101010,
465c120c
MR		 75};
76
3d7d6510
MR		 77/* Cursor formats */
78static const uint32_t intel_cursor_formats[] = {
79 DRM_FORMAT_ARGB8888,
80};
81
6b383a7f 82static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 83
f1f644dc 84static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 85 struct intel_crtc_state *pipe_config);
18442d08 86static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 87 struct intel_crtc_state *pipe_config);
f1f644dc 88
8c7b5ccb 89static int intel_set_mode(struct drm_crtc *crtc,
83a57153 90 struct drm_atomic_state *state);
eb1bfe80
JB		 91static int intel_framebuffer_init(struct drm_device *dev,
92 struct intel_framebuffer *ifb,
93 struct drm_mode_fb_cmd2 *mode_cmd,
94 struct drm_i915_gem_object *obj);
5b18e57c
DV		 95static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
96static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
29407aab 97static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 98 struct intel_link_m_n *m_n,
99 struct intel_link_m_n *m2_n2);
29407aab 100static void ironlake_set_pipeconf(struct drm_crtc *crtc);
229fca97
DV		 101static void haswell_set_pipeconf(struct drm_crtc *crtc);
102static void intel_set_pipe_csc(struct drm_crtc *crtc);
d288f65f 103static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 104 const struct intel_crtc_state *pipe_config);
d288f65f 105static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 106 const struct intel_crtc_state *pipe_config);
ea2c67bb
MR		 107static void intel_begin_crtc_commit(struct drm_crtc *crtc);
108static void intel_finish_crtc_commit(struct drm_crtc *crtc);
549e2bfb
CK		 109static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
110 struct intel_crtc_state *crtc_state);
5ab7b0b7
ID		 111static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
112 int num_connectors);
ce22dba9
ML		 113static void intel_crtc_enable_planes(struct drm_crtc *crtc);
114static void intel_crtc_disable_planes(struct drm_crtc *crtc);
e7457a9a 115
0e32b39c
DA		 116static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
117{
118 if (!connector->mst_port)
119 return connector->encoder;
120 else
121 return &connector->mst_port->mst_encoders[pipe]->base;
122}
123
79e53945 124typedef struct {
0206e353 125 int min, max;
79e53945
JB		 126} intel_range_t;
127
128typedef struct {
0206e353
AJ		 129 int dot_limit;
130 int p2_slow, p2_fast;
79e53945
JB		 131} intel_p2_t;
132
d4906093
ML		 133typedef struct intel_limit intel_limit_t;
134struct intel_limit {
0206e353
AJ		 135 intel_range_t dot, vco, n, m, m1, m2, p, p1;
136 intel_p2_t p2;
d4906093 137};
79e53945 138
d2acd215
DV		 139int
140intel_pch_rawclk(struct drm_device *dev)
141{
142 struct drm_i915_private *dev_priv = dev->dev_private;
143
144 WARN_ON(!HAS_PCH_SPLIT(dev));
145
146 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
147}
148
021357ac
CW		 149static inline u32 /* units of 100MHz */
150intel_fdi_link_freq(struct drm_device *dev)
151{
8b99e68c
CW		 152 if (IS_GEN5(dev)) {
153 struct drm_i915_private *dev_priv = dev->dev_private;
154 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
155 } else
156 return 27;
021357ac
CW		 157}
158
5d536e28 159static const intel_limit_t intel_limits_i8xx_dac = {
0206e353 160 .dot = { .min = 25000, .max = 350000 },
9c333719 161 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 162 .n = { .min = 2, .max = 16 },
0206e353
AJ		 163 .m = { .min = 96, .max = 140 },
164 .m1 = { .min = 18, .max = 26 },
165 .m2 = { .min = 6, .max = 16 },
166 .p = { .min = 4, .max = 128 },
167 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 168 .p2 = { .dot_limit = 165000,
169 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 170};
171
5d536e28
DV		 172static const intel_limit_t intel_limits_i8xx_dvo = {
173 .dot = { .min = 25000, .max = 350000 },
9c333719 174 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 175 .n = { .min = 2, .max = 16 },
5d536e28
DV		 176 .m = { .min = 96, .max = 140 },
177 .m1 = { .min = 18, .max = 26 },
178 .m2 = { .min = 6, .max = 16 },
179 .p = { .min = 4, .max = 128 },
180 .p1 = { .min = 2, .max = 33 },
181 .p2 = { .dot_limit = 165000,
182 .p2_slow = 4, .p2_fast = 4 },
183};
184
e4b36699 185static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353 186 .dot = { .min = 25000, .max = 350000 },
9c333719 187 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 188 .n = { .min = 2, .max = 16 },
0206e353
AJ		 189 .m = { .min = 96, .max = 140 },
190 .m1 = { .min = 18, .max = 26 },
191 .m2 = { .min = 6, .max = 16 },
192 .p = { .min = 4, .max = 128 },
193 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 194 .p2 = { .dot_limit = 165000,
195 .p2_slow = 14, .p2_fast = 7 },
e4b36699 196};
273e27ca 197
e4b36699 198static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 199 .dot = { .min = 20000, .max = 400000 },
200 .vco = { .min = 1400000, .max = 2800000 },
201 .n = { .min = 1, .max = 6 },
202 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 203 .m1 = { .min = 8, .max = 18 },
204 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 205 .p = { .min = 5, .max = 80 },
206 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 207 .p2 = { .dot_limit = 200000,
208 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 209};
210
211static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 212 .dot = { .min = 20000, .max = 400000 },
213 .vco = { .min = 1400000, .max = 2800000 },
214 .n = { .min = 1, .max = 6 },
215 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 216 .m1 = { .min = 8, .max = 18 },
217 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 218 .p = { .min = 7, .max = 98 },
219 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 220 .p2 = { .dot_limit = 112000,
221 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 222};
223
273e27ca 224
e4b36699 225static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 226 .dot = { .min = 25000, .max = 270000 },
227 .vco = { .min = 1750000, .max = 3500000},
228 .n = { .min = 1, .max = 4 },
229 .m = { .min = 104, .max = 138 },
230 .m1 = { .min = 17, .max = 23 },
231 .m2 = { .min = 5, .max = 11 },
232 .p = { .min = 10, .max = 30 },
233 .p1 = { .min = 1, .max = 3},
234 .p2 = { .dot_limit = 270000,
235 .p2_slow = 10,
236 .p2_fast = 10
044c7c41 237 },
e4b36699
KP		 238};
239
240static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 241 .dot = { .min = 22000, .max = 400000 },
242 .vco = { .min = 1750000, .max = 3500000},
243 .n = { .min = 1, .max = 4 },
244 .m = { .min = 104, .max = 138 },
245 .m1 = { .min = 16, .max = 23 },
246 .m2 = { .min = 5, .max = 11 },
247 .p = { .min = 5, .max = 80 },
248 .p1 = { .min = 1, .max = 8},
249 .p2 = { .dot_limit = 165000,
250 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 251};
252
253static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 254 .dot = { .min = 20000, .max = 115000 },
255 .vco = { .min = 1750000, .max = 3500000 },
256 .n = { .min = 1, .max = 3 },
257 .m = { .min = 104, .max = 138 },
258 .m1 = { .min = 17, .max = 23 },
259 .m2 = { .min = 5, .max = 11 },
260 .p = { .min = 28, .max = 112 },
261 .p1 = { .min = 2, .max = 8 },
262 .p2 = { .dot_limit = 0,
263 .p2_slow = 14, .p2_fast = 14
044c7c41 264 },
e4b36699
KP		 265};
266
267static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 268 .dot = { .min = 80000, .max = 224000 },
269 .vco = { .min = 1750000, .max = 3500000 },
270 .n = { .min = 1, .max = 3 },
271 .m = { .min = 104, .max = 138 },
272 .m1 = { .min = 17, .max = 23 },
273 .m2 = { .min = 5, .max = 11 },
274 .p = { .min = 14, .max = 42 },
275 .p1 = { .min = 2, .max = 6 },
276 .p2 = { .dot_limit = 0,
277 .p2_slow = 7, .p2_fast = 7
044c7c41 278 },
e4b36699
KP		 279};
280
f2b115e6 281static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 282 .dot = { .min = 20000, .max = 400000},
283 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 284 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 285 .n = { .min = 3, .max = 6 },
286 .m = { .min = 2, .max = 256 },
273e27ca 287 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 288 .m1 = { .min = 0, .max = 0 },
289 .m2 = { .min = 0, .max = 254 },
290 .p = { .min = 5, .max = 80 },
291 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 292 .p2 = { .dot_limit = 200000,
293 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 294};
295
f2b115e6 296static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 297 .dot = { .min = 20000, .max = 400000 },
298 .vco = { .min = 1700000, .max = 3500000 },
299 .n = { .min = 3, .max = 6 },
300 .m = { .min = 2, .max = 256 },
301 .m1 = { .min = 0, .max = 0 },
302 .m2 = { .min = 0, .max = 254 },
303 .p = { .min = 7, .max = 112 },
304 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 305 .p2 = { .dot_limit = 112000,
306 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 307};
308
273e27ca
EA		 309/* Ironlake / Sandybridge
310 *
311 * We calculate clock using (register_value + 2) for N/M1/M2, so here
312 * the range value for them is (actual_value - 2).
313 */
b91ad0ec 314static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 315 .dot = { .min = 25000, .max = 350000 },
316 .vco = { .min = 1760000, .max = 3510000 },
317 .n = { .min = 1, .max = 5 },
318 .m = { .min = 79, .max = 127 },
319 .m1 = { .min = 12, .max = 22 },
320 .m2 = { .min = 5, .max = 9 },
321 .p = { .min = 5, .max = 80 },
322 .p1 = { .min = 1, .max = 8 },
323 .p2 = { .dot_limit = 225000,
324 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 325};
326
b91ad0ec 327static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 328 .dot = { .min = 25000, .max = 350000 },
329 .vco = { .min = 1760000, .max = 3510000 },
330 .n = { .min = 1, .max = 3 },
331 .m = { .min = 79, .max = 118 },
332 .m1 = { .min = 12, .max = 22 },
333 .m2 = { .min = 5, .max = 9 },
334 .p = { .min = 28, .max = 112 },
335 .p1 = { .min = 2, .max = 8 },
336 .p2 = { .dot_limit = 225000,
337 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 338};
339
340static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 341 .dot = { .min = 25000, .max = 350000 },
342 .vco = { .min = 1760000, .max = 3510000 },
343 .n = { .min = 1, .max = 3 },
344 .m = { .min = 79, .max = 127 },
345 .m1 = { .min = 12, .max = 22 },
346 .m2 = { .min = 5, .max = 9 },
347 .p = { .min = 14, .max = 56 },
348 .p1 = { .min = 2, .max = 8 },
349 .p2 = { .dot_limit = 225000,
350 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 351};
352
273e27ca 353/* LVDS 100mhz refclk limits. */
b91ad0ec 354static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 355 .dot = { .min = 25000, .max = 350000 },
356 .vco = { .min = 1760000, .max = 3510000 },
357 .n = { .min = 1, .max = 2 },
358 .m = { .min = 79, .max = 126 },
359 .m1 = { .min = 12, .max = 22 },
360 .m2 = { .min = 5, .max = 9 },
361 .p = { .min = 28, .max = 112 },
0206e353 362 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 363 .p2 = { .dot_limit = 225000,
364 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 365};
366
367static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 368 .dot = { .min = 25000, .max = 350000 },
369 .vco = { .min = 1760000, .max = 3510000 },
370 .n = { .min = 1, .max = 3 },
371 .m = { .min = 79, .max = 126 },
372 .m1 = { .min = 12, .max = 22 },
373 .m2 = { .min = 5, .max = 9 },
374 .p = { .min = 14, .max = 42 },
0206e353 375 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 376 .p2 = { .dot_limit = 225000,
377 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 378};
379
dc730512 380static const intel_limit_t intel_limits_vlv = {
f01b7962
VS		 381 /*
382 * These are the data rate limits (measured in fast clocks)
383 * since those are the strictest limits we have. The fast
384 * clock and actual rate limits are more relaxed, so checking
385 * them would make no difference.
386 */
387 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
75e53986 388 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 389 .n = { .min = 1, .max = 7 },
a0c4da24
JB		 390 .m1 = { .min = 2, .max = 3 },
391 .m2 = { .min = 11, .max = 156 },
b99ab663 392 .p1 = { .min = 2, .max = 3 },
5fdc9c49 393 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
a0c4da24
JB		 394};
395
ef9348c8
CML		 396static const intel_limit_t intel_limits_chv = {
397 /*
398 * These are the data rate limits (measured in fast clocks)
399 * since those are the strictest limits we have. The fast
400 * clock and actual rate limits are more relaxed, so checking
401 * them would make no difference.
402 */
403 .dot = { .min = 25000 * 5, .max = 540000 * 5},
17fe1021 404 .vco = { .min = 4800000, .max = 6480000 },
ef9348c8
CML		 405 .n = { .min = 1, .max = 1 },
406 .m1 = { .min = 2, .max = 2 },
407 .m2 = { .min = 24 << 22, .max = 175 << 22 },
408 .p1 = { .min = 2, .max = 4 },
409 .p2 = { .p2_slow = 1, .p2_fast = 14 },
410};
411
5ab7b0b7
ID		 412static const intel_limit_t intel_limits_bxt = {
413 /* FIXME: find real dot limits */
414 .dot = { .min = 0, .max = INT_MAX },
415 .vco = { .min = 4800000, .max = 6480000 },
416 .n = { .min = 1, .max = 1 },
417 .m1 = { .min = 2, .max = 2 },
418 /* FIXME: find real m2 limits */
419 .m2 = { .min = 2 << 22, .max = 255 << 22 },
420 .p1 = { .min = 2, .max = 4 },
421 .p2 = { .p2_slow = 1, .p2_fast = 20 },
422};
423
6b4bf1c4
VS		 424static void vlv_clock(int refclk, intel_clock_t *clock)
425{
426 clock->m = clock->m1 * clock->m2;
427 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 428 if (WARN_ON(clock->n == 0 || clock->p == 0))
429 return;
fb03ac01
VS		 430 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
431 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
6b4bf1c4
VS		 432}
433
e0638cdf
PZ		 434/**
435 * Returns whether any output on the specified pipe is of the specified type
436 */
4093561b 437bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
e0638cdf 438{
409ee761 439 struct drm_device *dev = crtc->base.dev;
e0638cdf
PZ		 440 struct intel_encoder *encoder;
441
409ee761 442 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
e0638cdf
PZ		 443 if (encoder->type == type)
444 return true;
445
446 return false;
447}
448
d0737e1d
ACO		 449/**
450 * Returns whether any output on the specified pipe will have the specified
451 * type after a staged modeset is complete, i.e., the same as
452 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
453 * encoder->crtc.
454 */
a93e255f
ACO		 455static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
456 int type)
d0737e1d 457{
a93e255f 458 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 459 struct drm_connector *connector;
a93e255f 460 struct drm_connector_state *connector_state;
d0737e1d 461 struct intel_encoder *encoder;
a93e255f
ACO		 462 int i, num_connectors = 0;
463
da3ced29 464 for_each_connector_in_state(state, connector, connector_state, i) {
a93e255f
ACO		 465 if (connector_state->crtc != crtc_state->base.crtc)
466 continue;
467
468 num_connectors++;
d0737e1d 469
a93e255f
ACO		 470 encoder = to_intel_encoder(connector_state->best_encoder);
471 if (encoder->type == type)
d0737e1d 472 return true;
a93e255f
ACO		 473 }
474
475 WARN_ON(num_connectors == 0);
d0737e1d
ACO		 476
477 return false;
478}
479
a93e255f
ACO		 480static const intel_limit_t *
481intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
2c07245f 482{
a93e255f 483 struct drm_device *dev = crtc_state->base.crtc->dev;
2c07245f 484 const intel_limit_t *limit;
b91ad0ec 485
a93e255f 486 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 487 if (intel_is_dual_link_lvds(dev)) {
1b894b59 488 if (refclk == 100000)
b91ad0ec
ZW		 489 limit = &intel_limits_ironlake_dual_lvds_100m;
490 else
491 limit = &intel_limits_ironlake_dual_lvds;
492 } else {
1b894b59 493 if (refclk == 100000)
b91ad0ec
ZW		 494 limit = &intel_limits_ironlake_single_lvds_100m;
495 else
496 limit = &intel_limits_ironlake_single_lvds;
497 }
c6bb3538 498 } else
b91ad0ec 499 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 500
501 return limit;
502}
503
a93e255f
ACO		 504static const intel_limit_t *
505intel_g4x_limit(struct intel_crtc_state *crtc_state)
044c7c41 506{
a93e255f 507 struct drm_device *dev = crtc_state->base.crtc->dev;
044c7c41
ML		 508 const intel_limit_t *limit;
509
a93e255f 510 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 511 if (intel_is_dual_link_lvds(dev))
e4b36699 512 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 513 else
e4b36699 514 limit = &intel_limits_g4x_single_channel_lvds;
a93e255f
ACO		 515 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
516 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
e4b36699 517 limit = &intel_limits_g4x_hdmi;
a93e255f 518 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
e4b36699 519 limit = &intel_limits_g4x_sdvo;
044c7c41 520 } else /* The option is for other outputs */
e4b36699 521 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 522
523 return limit;
524}
525
a93e255f
ACO		 526static const intel_limit_t *
527intel_limit(struct intel_crtc_state *crtc_state, int refclk)
79e53945 528{
a93e255f 529 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945
JB		 530 const intel_limit_t *limit;
531
5ab7b0b7
ID		 532 if (IS_BROXTON(dev))
533 limit = &intel_limits_bxt;
534 else if (HAS_PCH_SPLIT(dev))
a93e255f 535 limit = intel_ironlake_limit(crtc_state, refclk);
2c07245f 536 else if (IS_G4X(dev)) {
a93e255f 537 limit = intel_g4x_limit(crtc_state);
f2b115e6 538 } else if (IS_PINEVIEW(dev)) {
a93e255f 539 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
f2b115e6 540 limit = &intel_limits_pineview_lvds;
2177832f 541 else
f2b115e6 542 limit = &intel_limits_pineview_sdvo;
ef9348c8
CML		 543 } else if (IS_CHERRYVIEW(dev)) {
544 limit = &intel_limits_chv;
a0c4da24 545 } else if (IS_VALLEYVIEW(dev)) {
dc730512 546 limit = &intel_limits_vlv;
a6c45cf0 547 } else if (!IS_GEN2(dev)) {
a93e255f 548 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
a6c45cf0
CW		 549 limit = &intel_limits_i9xx_lvds;
550 else
551 limit = &intel_limits_i9xx_sdvo;
79e53945 552 } else {
a93e255f 553 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
e4b36699 554 limit = &intel_limits_i8xx_lvds;
a93e255f 555 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
e4b36699 556 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 557 else
558 limit = &intel_limits_i8xx_dac;
79e53945
JB		 559 }
560 return limit;
561}
562
f2b115e6
AJ		 563/* m1 is reserved as 0 in Pineview, n is a ring counter */
564static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 565{
2177832f
SL		 566 clock->m = clock->m2 + 2;
567 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 568 if (WARN_ON(clock->n == 0 || clock->p == 0))
569 return;
fb03ac01
VS		 570 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
571 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
2177832f
SL		 572}
573
7429e9d4
DV		 574static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
575{
576 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
577}
578
ac58c3f0 579static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 580{
7429e9d4 581 clock->m = i9xx_dpll_compute_m(clock);
79e53945 582 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 583 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
584 return;
fb03ac01
VS		 585 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
586 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
79e53945
JB		 587}
588
ef9348c8
CML		 589static void chv_clock(int refclk, intel_clock_t *clock)
590{
591 clock->m = clock->m1 * clock->m2;
592 clock->p = clock->p1 * clock->p2;
593 if (WARN_ON(clock->n == 0 || clock->p == 0))
594 return;
595 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
596 clock->n << 22);
597 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
598}
599
7c04d1d9 600#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 601/**
602 * Returns whether the given set of divisors are valid for a given refclk with
603 * the given connectors.
604 */
605
1b894b59
CW		 606static bool intel_PLL_is_valid(struct drm_device *dev,
607 const intel_limit_t *limit,
608 const intel_clock_t *clock)
79e53945 609{
f01b7962
VS		 610 if (clock->n < limit->n.min || limit->n.max < clock->n)
611 INTELPllInvalid("n out of range\n");
79e53945 612 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 613 INTELPllInvalid("p1 out of range\n");
79e53945 614 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 615 INTELPllInvalid("m2 out of range\n");
79e53945 616 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 617 INTELPllInvalid("m1 out of range\n");
f01b7962 618
5ab7b0b7 619 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
f01b7962
VS		 620 if (clock->m1 <= clock->m2)
621 INTELPllInvalid("m1 <= m2\n");
622
5ab7b0b7 623 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
f01b7962
VS		 624 if (clock->p < limit->p.min || limit->p.max < clock->p)
625 INTELPllInvalid("p out of range\n");
626 if (clock->m < limit->m.min || limit->m.max < clock->m)
627 INTELPllInvalid("m out of range\n");
628 }
629
79e53945 630 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 631 INTELPllInvalid("vco out of range\n");
79e53945
JB		 632 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
633 * connector, etc., rather than just a single range.
634 */
635 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 636 INTELPllInvalid("dot out of range\n");
79e53945
JB		 637
638 return true;
639}
640
d4906093 641static bool
a93e255f
ACO		 642i9xx_find_best_dpll(const intel_limit_t *limit,
643 struct intel_crtc_state *crtc_state,
cec2f356
SP		 644 int target, int refclk, intel_clock_t *match_clock,
645 intel_clock_t *best_clock)
79e53945 646{
a93e255f 647 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 648 struct drm_device *dev = crtc->base.dev;
79e53945 649 intel_clock_t clock;
79e53945
JB		 650 int err = target;
651
a93e255f 652 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 653 /*
a210b028
DV		 654 * For LVDS just rely on its current settings for dual-channel.
655 * We haven't figured out how to reliably set up different
656 * single/dual channel state, if we even can.
79e53945 657 */
1974cad0 658 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 659 clock.p2 = limit->p2.p2_fast;
660 else
661 clock.p2 = limit->p2.p2_slow;
662 } else {
663 if (target < limit->p2.dot_limit)
664 clock.p2 = limit->p2.p2_slow;
665 else
666 clock.p2 = limit->p2.p2_fast;
667 }
668
0206e353 669 memset(best_clock, 0, sizeof(*best_clock));
79e53945 670
42158660
ZY		 671 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
672 clock.m1++) {
673 for (clock.m2 = limit->m2.min;
674 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 675 if (clock.m2 >= clock.m1)
42158660
ZY		 676 break;
677 for (clock.n = limit->n.min;
678 clock.n <= limit->n.max; clock.n++) {
679 for (clock.p1 = limit->p1.min;
680 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 681 int this_err;
682
ac58c3f0
DV		 683 i9xx_clock(refclk, &clock);
684 if (!intel_PLL_is_valid(dev, limit,
685 &clock))
686 continue;
687 if (match_clock &&
688 clock.p != match_clock->p)
689 continue;
690
691 this_err = abs(clock.dot - target);
692 if (this_err < err) {
693 *best_clock = clock;
694 err = this_err;
695 }
696 }
697 }
698 }
699 }
700
701 return (err != target);
702}
703
704static bool
a93e255f
ACO		 705pnv_find_best_dpll(const intel_limit_t *limit,
706 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 707 int target, int refclk, intel_clock_t *match_clock,
708 intel_clock_t *best_clock)
79e53945 709{
a93e255f 710 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 711 struct drm_device *dev = crtc->base.dev;
79e53945 712 intel_clock_t clock;
79e53945
JB		 713 int err = target;
714
a93e255f 715 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 716 /*
a210b028
DV		 717 * For LVDS just rely on its current settings for dual-channel.
718 * We haven't figured out how to reliably set up different
719 * single/dual channel state, if we even can.
79e53945 720 */
1974cad0 721 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 722 clock.p2 = limit->p2.p2_fast;
723 else
724 clock.p2 = limit->p2.p2_slow;
725 } else {
726 if (target < limit->p2.dot_limit)
727 clock.p2 = limit->p2.p2_slow;
728 else
729 clock.p2 = limit->p2.p2_fast;
730 }
731
0206e353 732 memset(best_clock, 0, sizeof(*best_clock));
79e53945 733
42158660
ZY		 734 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
735 clock.m1++) {
736 for (clock.m2 = limit->m2.min;
737 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 738 for (clock.n = limit->n.min;
739 clock.n <= limit->n.max; clock.n++) {
740 for (clock.p1 = limit->p1.min;
741 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 742 int this_err;
743
ac58c3f0 744 pineview_clock(refclk, &clock);
1b894b59
CW		 745 if (!intel_PLL_is_valid(dev, limit,
746 &clock))
79e53945 747 continue;
cec2f356
SP		 748 if (match_clock &&
749 clock.p != match_clock->p)
750 continue;
79e53945
JB		 751
752 this_err = abs(clock.dot - target);
753 if (this_err < err) {
754 *best_clock = clock;
755 err = this_err;
756 }
757 }
758 }
759 }
760 }
761
762 return (err != target);
763}
764
d4906093 765static bool
a93e255f
ACO		 766g4x_find_best_dpll(const intel_limit_t *limit,
767 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 768 int target, int refclk, intel_clock_t *match_clock,
769 intel_clock_t *best_clock)
d4906093 770{
a93e255f 771 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 772 struct drm_device *dev = crtc->base.dev;
d4906093
ML		 773 intel_clock_t clock;
774 int max_n;
775 bool found;
6ba770dc
AJ		 776 /* approximately equals target * 0.00585 */
777 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 778 found = false;
779
a93e255f 780 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 781 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 782 clock.p2 = limit->p2.p2_fast;
783 else
784 clock.p2 = limit->p2.p2_slow;
785 } else {
786 if (target < limit->p2.dot_limit)
787 clock.p2 = limit->p2.p2_slow;
788 else
789 clock.p2 = limit->p2.p2_fast;
790 }
791
792 memset(best_clock, 0, sizeof(*best_clock));
793 max_n = limit->n.max;
f77f13e2 794 /* based on hardware requirement, prefer smaller n to precision */
d4906093 795 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 796 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 797 for (clock.m1 = limit->m1.max;
798 clock.m1 >= limit->m1.min; clock.m1--) {
799 for (clock.m2 = limit->m2.max;
800 clock.m2 >= limit->m2.min; clock.m2--) {
801 for (clock.p1 = limit->p1.max;
802 clock.p1 >= limit->p1.min; clock.p1--) {
803 int this_err;
804
ac58c3f0 805 i9xx_clock(refclk, &clock);
1b894b59
CW		 806 if (!intel_PLL_is_valid(dev, limit,
807 &clock))
d4906093 808 continue;
1b894b59
CW		 809
810 this_err = abs(clock.dot - target);
d4906093
ML		 811 if (this_err < err_most) {
812 *best_clock = clock;
813 err_most = this_err;
814 max_n = clock.n;
815 found = true;
816 }
817 }
818 }
819 }
820 }
2c07245f
ZW		 821 return found;
822}
823
d5dd62bd
ID		 824/*
825 * Check if the calculated PLL configuration is more optimal compared to the
826 * best configuration and error found so far. Return the calculated error.
827 */
828static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
829 const intel_clock_t *calculated_clock,
830 const intel_clock_t *best_clock,
831 unsigned int best_error_ppm,
832 unsigned int *error_ppm)
833{
9ca3ba01
ID		 834 /*
835 * For CHV ignore the error and consider only the P value.
836 * Prefer a bigger P value based on HW requirements.
837 */
838 if (IS_CHERRYVIEW(dev)) {
839 *error_ppm = 0;
840
841 return calculated_clock->p > best_clock->p;
842 }
843
24be4e46
ID		 844 if (WARN_ON_ONCE(!target_freq))
845 return false;
846
d5dd62bd
ID		 847 *error_ppm = div_u64(1000000ULL *
848 abs(target_freq - calculated_clock->dot),
849 target_freq);
850 /*
851 * Prefer a better P value over a better (smaller) error if the error
852 * is small. Ensure this preference for future configurations too by
853 * setting the error to 0.
854 */
855 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
856 *error_ppm = 0;
857
858 return true;
859 }
860
861 return *error_ppm + 10 < best_error_ppm;
862}
863
a0c4da24 864static bool
a93e255f
ACO		 865vlv_find_best_dpll(const intel_limit_t *limit,
866 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 867 int target, int refclk, intel_clock_t *match_clock,
868 intel_clock_t *best_clock)
a0c4da24 869{
a93e255f 870 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 871 struct drm_device *dev = crtc->base.dev;
6b4bf1c4 872 intel_clock_t clock;
69e4f900 873 unsigned int bestppm = 1000000;
27e639bf
VS		 874 /* min update 19.2 MHz */
875 int max_n = min(limit->n.max, refclk / 19200);
49e497ef 876 bool found = false;
a0c4da24 877
6b4bf1c4
VS		 878 target *= 5; /* fast clock */
879
880 memset(best_clock, 0, sizeof(*best_clock));
a0c4da24
JB		 881
882 /* based on hardware requirement, prefer smaller n to precision */
27e639bf 883 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
811bbf05 884 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
889059d8 885 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
c1a9ae43 886 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
6b4bf1c4 887 clock.p = clock.p1 * clock.p2;
a0c4da24 888 /* based on hardware requirement, prefer bigger m1,m2 values */
6b4bf1c4 889 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
d5dd62bd 890 unsigned int ppm;
69e4f900 891
6b4bf1c4
VS		 892 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
893 refclk * clock.m1);
894
895 vlv_clock(refclk, &clock);
43b0ac53 896
f01b7962
VS		 897 if (!intel_PLL_is_valid(dev, limit,
898 &clock))
43b0ac53
VS		 899 continue;
900
d5dd62bd
ID		 901 if (!vlv_PLL_is_optimal(dev, target,
902 &clock,
903 best_clock,
904 bestppm, &ppm))
905 continue;
6b4bf1c4 906
d5dd62bd
ID		 907 *best_clock = clock;
908 bestppm = ppm;
909 found = true;
a0c4da24
JB		 910 }
911 }
912 }
913 }
a0c4da24 914
49e497ef 915 return found;
a0c4da24 916}
a4fc5ed6 917
ef9348c8 918static bool
a93e255f
ACO		 919chv_find_best_dpll(const intel_limit_t *limit,
920 struct intel_crtc_state *crtc_state,
ef9348c8
CML		 921 int target, int refclk, intel_clock_t *match_clock,
922 intel_clock_t *best_clock)
923{
a93e255f 924 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 925 struct drm_device *dev = crtc->base.dev;
9ca3ba01 926 unsigned int best_error_ppm;
ef9348c8
CML		 927 intel_clock_t clock;
928 uint64_t m2;
929 int found = false;
930
931 memset(best_clock, 0, sizeof(*best_clock));
9ca3ba01 932 best_error_ppm = 1000000;
ef9348c8
CML		 933
934 /*
935 * Based on hardware doc, the n always set to 1, and m1 always
936 * set to 2. If requires to support 200Mhz refclk, we need to
937 * revisit this because n may not 1 anymore.
938 */
939 clock.n = 1, clock.m1 = 2;
940 target *= 5; /* fast clock */
941
942 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
943 for (clock.p2 = limit->p2.p2_fast;
944 clock.p2 >= limit->p2.p2_slow;
945 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
9ca3ba01 946 unsigned int error_ppm;
ef9348c8
CML		 947
948 clock.p = clock.p1 * clock.p2;
949
950 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
951 clock.n) << 22, refclk * clock.m1);
952
953 if (m2 > INT_MAX/clock.m1)
954 continue;
955
956 clock.m2 = m2;
957
958 chv_clock(refclk, &clock);
959
960 if (!intel_PLL_is_valid(dev, limit, &clock))
961 continue;
962
9ca3ba01
ID		 963 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
964 best_error_ppm, &error_ppm))
965 continue;
966
967 *best_clock = clock;
968 best_error_ppm = error_ppm;
969 found = true;
ef9348c8
CML		 970 }
971 }
972
973 return found;
974}
975
5ab7b0b7
ID		 976bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
977 intel_clock_t *best_clock)
978{
979 int refclk = i9xx_get_refclk(crtc_state, 0);
980
981 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
982 target_clock, refclk, NULL, best_clock);
983}
984
20ddf665
VS		 985bool intel_crtc_active(struct drm_crtc *crtc)
986{
987 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
988
989 /* Be paranoid as we can arrive here with only partial
990 * state retrieved from the hardware during setup.
991 *
241bfc38 992 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS		 993 * as Haswell has gained clock readout/fastboot support.
994 *
66e514c1 995 * We can ditch the crtc->primary->fb check as soon as we can
20ddf665 996 * properly reconstruct framebuffers.
c3d1f436
MR		 997 *
998 * FIXME: The intel_crtc->active here should be switched to
999 * crtc->state->active once we have proper CRTC states wired up
1000 * for atomic.
20ddf665 1001 */
c3d1f436 1002 return intel_crtc->active && crtc->primary->state->fb &&
6e3c9717 1003 intel_crtc->config->base.adjusted_mode.crtc_clock;
20ddf665
VS		 1004}
1005
a5c961d1
PZ		 1006enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1007 enum pipe pipe)
1008{
1009 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1010 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1011
6e3c9717 1012 return intel_crtc->config->cpu_transcoder;
a5c961d1
PZ		 1013}
1014
fbf49ea2
VS		 1015static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1016{
1017 struct drm_i915_private *dev_priv = dev->dev_private;
1018 u32 reg = PIPEDSL(pipe);
1019 u32 line1, line2;
1020 u32 line_mask;
1021
1022 if (IS_GEN2(dev))
1023 line_mask = DSL_LINEMASK_GEN2;
1024 else
1025 line_mask = DSL_LINEMASK_GEN3;
1026
1027 line1 = I915_READ(reg) & line_mask;
1028 mdelay(5);
1029 line2 = I915_READ(reg) & line_mask;
1030
1031 return line1 == line2;
1032}
1033
ab7ad7f6
KP		 1034/*
1035 * intel_wait_for_pipe_off - wait for pipe to turn off
575f7ab7 1036 * @crtc: crtc whose pipe to wait for
9d0498a2
JB		 1037 *
1038 * After disabling a pipe, we can't wait for vblank in the usual way,
1039 * spinning on the vblank interrupt status bit, since we won't actually
1040 * see an interrupt when the pipe is disabled.
1041 *
ab7ad7f6
KP		 1042 * On Gen4 and above:
1043 * wait for the pipe register state bit to turn off
1044 *
1045 * Otherwise:
1046 * wait for the display line value to settle (it usually
1047 * ends up stopping at the start of the next frame).
58e10eb9 1048 *
9d0498a2 1049 */
575f7ab7 1050static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
9d0498a2 1051{
575f7ab7 1052 struct drm_device *dev = crtc->base.dev;
9d0498a2 1053 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1054 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 1055 enum pipe pipe = crtc->pipe;
ab7ad7f6
KP		 1056
1057 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1058 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 1059
1060 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1061 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1062 100))
284637d9 1063 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1064 } else {
ab7ad7f6 1065 /* Wait for the display line to settle */
fbf49ea2 1066 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
284637d9 1067 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1068 }
79e53945
JB		 1069}
1070
b0ea7d37
DL		 1071/*
1072 * ibx_digital_port_connected - is the specified port connected?
1073 * @dev_priv: i915 private structure
1074 * @port: the port to test
1075 *
1076 * Returns true if @port is connected, false otherwise.
1077 */
1078bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1079 struct intel_digital_port *port)
1080{
1081 u32 bit;
1082
c36346e3 1083 if (HAS_PCH_IBX(dev_priv->dev)) {
eba905b2 1084 switch (port->port) {
c36346e3
DL		 1085 case PORT_B:
1086 bit = SDE_PORTB_HOTPLUG;
1087 break;
1088 case PORT_C:
1089 bit = SDE_PORTC_HOTPLUG;
1090 break;
1091 case PORT_D:
1092 bit = SDE_PORTD_HOTPLUG;
1093 break;
1094 default:
1095 return true;
1096 }
1097 } else {
eba905b2 1098 switch (port->port) {
c36346e3
DL		 1099 case PORT_B:
1100 bit = SDE_PORTB_HOTPLUG_CPT;
1101 break;
1102 case PORT_C:
1103 bit = SDE_PORTC_HOTPLUG_CPT;
1104 break;
1105 case PORT_D:
1106 bit = SDE_PORTD_HOTPLUG_CPT;
1107 break;
1108 default:
1109 return true;
1110 }
b0ea7d37
DL		 1111 }
1112
1113 return I915_READ(SDEISR) & bit;
1114}
1115
b24e7179
JB		 1116static const char *state_string(bool enabled)
1117{
1118 return enabled ? "on" : "off";
1119}
1120
1121/* Only for pre-ILK configs */
55607e8a
DV		 1122void assert_pll(struct drm_i915_private *dev_priv,
1123 enum pipe pipe, bool state)
b24e7179
JB		 1124{
1125 int reg;
1126 u32 val;
1127 bool cur_state;
1128
1129 reg = DPLL(pipe);
1130 val = I915_READ(reg);
1131 cur_state = !!(val & DPLL_VCO_ENABLE);
e2c719b7 1132 I915_STATE_WARN(cur_state != state,
b24e7179
JB		 1133 "PLL state assertion failure (expected %s, current %s)\n",
1134 state_string(state), state_string(cur_state));
1135}
b24e7179 1136
23538ef1
JN		 1137/* XXX: the dsi pll is shared between MIPI DSI ports */
1138static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1139{
1140 u32 val;
1141 bool cur_state;
1142
1143 mutex_lock(&dev_priv->dpio_lock);
1144 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1145 mutex_unlock(&dev_priv->dpio_lock);
1146
1147 cur_state = val & DSI_PLL_VCO_EN;
e2c719b7 1148 I915_STATE_WARN(cur_state != state,
23538ef1
JN		 1149 "DSI PLL state assertion failure (expected %s, current %s)\n",
1150 state_string(state), state_string(cur_state));
1151}
1152#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1153#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1154
55607e8a 1155struct intel_shared_dpll *
e2b78267
DV		 1156intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1157{
1158 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1159
6e3c9717 1160 if (crtc->config->shared_dpll < 0)
e2b78267
DV		 1161 return NULL;
1162
6e3c9717 1163 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
e2b78267
DV		 1164}
1165
040484af 1166/* For ILK+ */
55607e8a
DV		 1167void assert_shared_dpll(struct drm_i915_private *dev_priv,
1168 struct intel_shared_dpll *pll,
1169 bool state)
040484af 1170{
040484af 1171 bool cur_state;
5358901f 1172 struct intel_dpll_hw_state hw_state;
040484af 1173
92b27b08 1174 if (WARN (!pll,
46edb027 1175 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 1176 return;
ee7b9f93 1177
5358901f 1178 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
e2c719b7 1179 I915_STATE_WARN(cur_state != state,
5358901f
DV		 1180 "%s assertion failure (expected %s, current %s)\n",
1181 pll->name, state_string(state), state_string(cur_state));
040484af 1182}
040484af
JB		 1183
1184static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1185 enum pipe pipe, bool state)
1186{
1187 int reg;
1188 u32 val;
1189 bool cur_state;
ad80a810
PZ		 1190 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1191 pipe);
040484af 1192
affa9354
PZ		 1193 if (HAS_DDI(dev_priv->dev)) {
1194 /* DDI does not have a specific FDI_TX register */
ad80a810 1195 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1196 val = I915_READ(reg);
ad80a810 1197 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1198 } else {
1199 reg = FDI_TX_CTL(pipe);
1200 val = I915_READ(reg);
1201 cur_state = !!(val & FDI_TX_ENABLE);
1202 }
e2c719b7 1203 I915_STATE_WARN(cur_state != state,
040484af
JB		 1204 "FDI TX state assertion failure (expected %s, current %s)\n",
1205 state_string(state), state_string(cur_state));
1206}
1207#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1208#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1209
1210static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1211 enum pipe pipe, bool state)
1212{
1213 int reg;
1214 u32 val;
1215 bool cur_state;
1216
d63fa0dc
PZ		 1217 reg = FDI_RX_CTL(pipe);
1218 val = I915_READ(reg);
1219 cur_state = !!(val & FDI_RX_ENABLE);
e2c719b7 1220 I915_STATE_WARN(cur_state != state,
040484af
JB		 1221 "FDI RX state assertion failure (expected %s, current %s)\n",
1222 state_string(state), state_string(cur_state));
1223}
1224#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1225#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1226
1227static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1228 enum pipe pipe)
1229{
1230 int reg;
1231 u32 val;
1232
1233 /* ILK FDI PLL is always enabled */
3d13ef2e 1234 if (INTEL_INFO(dev_priv->dev)->gen == 5)
040484af
JB		 1235 return;
1236
bf507ef7 1237 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1238 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1239 return;
1240
040484af
JB		 1241 reg = FDI_TX_CTL(pipe);
1242 val = I915_READ(reg);
e2c719b7 1243 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
040484af
JB		 1244}
1245
55607e8a
DV		 1246void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1247 enum pipe pipe, bool state)
040484af
JB		 1248{
1249 int reg;
1250 u32 val;
55607e8a 1251 bool cur_state;
040484af
JB		 1252
1253 reg = FDI_RX_CTL(pipe);
1254 val = I915_READ(reg);
55607e8a 1255 cur_state = !!(val & FDI_RX_PLL_ENABLE);
e2c719b7 1256 I915_STATE_WARN(cur_state != state,
55607e8a
DV		 1257 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1258 state_string(state), state_string(cur_state));
040484af
JB		 1259}
1260
b680c37a
DV		 1261void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1262 enum pipe pipe)
ea0760cf 1263{
bedd4dba
JN		 1264 struct drm_device *dev = dev_priv->dev;
1265 int pp_reg;
ea0760cf
JB		 1266 u32 val;
1267 enum pipe panel_pipe = PIPE_A;
0de3b485 1268 bool locked = true;
ea0760cf 1269
bedd4dba
JN		 1270 if (WARN_ON(HAS_DDI(dev)))
1271 return;
1272
1273 if (HAS_PCH_SPLIT(dev)) {
1274 u32 port_sel;
1275
ea0760cf 1276 pp_reg = PCH_PP_CONTROL;
bedd4dba
JN		 1277 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1278
1279 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1280 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1281 panel_pipe = PIPE_B;
1282 /* XXX: else fix for eDP */
1283 } else if (IS_VALLEYVIEW(dev)) {
1284 /* presumably write lock depends on pipe, not port select */
1285 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1286 panel_pipe = pipe;
ea0760cf
JB		 1287 } else {
1288 pp_reg = PP_CONTROL;
bedd4dba
JN		 1289 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1290 panel_pipe = PIPE_B;
ea0760cf
JB		 1291 }
1292
1293 val = I915_READ(pp_reg);
1294 if (!(val & PANEL_POWER_ON) ||
ec49ba2d 1295 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
ea0760cf
JB		 1296 locked = false;
1297
e2c719b7 1298 I915_STATE_WARN(panel_pipe == pipe && locked,
ea0760cf 1299 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1300 pipe_name(pipe));
ea0760cf
JB		 1301}
1302
93ce0ba6
JN		 1303static void assert_cursor(struct drm_i915_private *dev_priv,
1304 enum pipe pipe, bool state)
1305{
1306 struct drm_device *dev = dev_priv->dev;
1307 bool cur_state;
1308
d9d82081 1309 if (IS_845G(dev) || IS_I865G(dev))
93ce0ba6 1310 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
d9d82081 1311 else
5efb3e28 1312 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
93ce0ba6 1313
e2c719b7 1314 I915_STATE_WARN(cur_state != state,
93ce0ba6
JN		 1315 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1316 pipe_name(pipe), state_string(state), state_string(cur_state));
1317}
1318#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1319#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1320
b840d907
JB		 1321void assert_pipe(struct drm_i915_private *dev_priv,
1322 enum pipe pipe, bool state)
b24e7179
JB		 1323{
1324 int reg;
1325 u32 val;
63d7bbe9 1326 bool cur_state;
702e7a56
PZ		 1327 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1328 pipe);
b24e7179 1329
b6b5d049
VS		 1330 /* if we need the pipe quirk it must be always on */
1331 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1332 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8e636784
DV		 1333 state = true;
1334
f458ebbc 1335 if (!intel_display_power_is_enabled(dev_priv,
b97186f0 1336 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1337 cur_state = false;
1338 } else {
1339 reg = PIPECONF(cpu_transcoder);
1340 val = I915_READ(reg);
1341 cur_state = !!(val & PIPECONF_ENABLE);
1342 }
1343
e2c719b7 1344 I915_STATE_WARN(cur_state != state,
63d7bbe9 1345 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1346 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1347}
1348
931872fc
CW		 1349static void assert_plane(struct drm_i915_private *dev_priv,
1350 enum plane plane, bool state)
b24e7179
JB		 1351{
1352 int reg;
1353 u32 val;
931872fc 1354 bool cur_state;
b24e7179
JB		 1355
1356 reg = DSPCNTR(plane);
1357 val = I915_READ(reg);
931872fc 1358 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
e2c719b7 1359 I915_STATE_WARN(cur_state != state,
931872fc
CW		 1360 "plane %c assertion failure (expected %s, current %s)\n",
1361 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1362}
1363
931872fc
CW		 1364#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1365#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1366
b24e7179
JB		 1367static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1368 enum pipe pipe)
1369{
653e1026 1370 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1371 int reg, i;
1372 u32 val;
1373 int cur_pipe;
1374
653e1026
VS		 1375 /* Primary planes are fixed to pipes on gen4+ */
1376 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1377 reg = DSPCNTR(pipe);
1378 val = I915_READ(reg);
e2c719b7 1379 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
28c05794
AJ		 1380 "plane %c assertion failure, should be disabled but not\n",
1381 plane_name(pipe));
19ec1358 1382 return;
28c05794 1383 }
19ec1358 1384
b24e7179 1385 /* Need to check both planes against the pipe */
055e393f 1386 for_each_pipe(dev_priv, i) {
b24e7179
JB		 1387 reg = DSPCNTR(i);
1388 val = I915_READ(reg);
1389 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1390 DISPPLANE_SEL_PIPE_SHIFT;
e2c719b7 1391 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1392 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1393 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1394 }
1395}
1396
19332d7a
JB		 1397static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1398 enum pipe pipe)
1399{
20674eef 1400 struct drm_device *dev = dev_priv->dev;
1fe47785 1401 int reg, sprite;
19332d7a
JB		 1402 u32 val;
1403
7feb8b88 1404 if (INTEL_INFO(dev)->gen >= 9) {
3bdcfc0c 1405 for_each_sprite(dev_priv, pipe, sprite) {
7feb8b88 1406 val = I915_READ(PLANE_CTL(pipe, sprite));
e2c719b7 1407 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
7feb8b88
DL		 1408 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1409 sprite, pipe_name(pipe));
1410 }
1411 } else if (IS_VALLEYVIEW(dev)) {
3bdcfc0c 1412 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 1413 reg = SPCNTR(pipe, sprite);
20674eef 1414 val = I915_READ(reg);
e2c719b7 1415 I915_STATE_WARN(val & SP_ENABLE,
20674eef 1416 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1fe47785 1417 sprite_name(pipe, sprite), pipe_name(pipe));
20674eef
VS		 1418 }
1419 } else if (INTEL_INFO(dev)->gen >= 7) {
1420 reg = SPRCTL(pipe);
19332d7a 1421 val = I915_READ(reg);
e2c719b7 1422 I915_STATE_WARN(val & SPRITE_ENABLE,
06da8da2 1423 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1424 plane_name(pipe), pipe_name(pipe));
1425 } else if (INTEL_INFO(dev)->gen >= 5) {
1426 reg = DVSCNTR(pipe);
19332d7a 1427 val = I915_READ(reg);
e2c719b7 1428 I915_STATE_WARN(val & DVS_ENABLE,
06da8da2 1429 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1430 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1431 }
1432}
1433
08c71e5e
VS		 1434static void assert_vblank_disabled(struct drm_crtc *crtc)
1435{
e2c719b7 1436 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
08c71e5e
VS		 1437 drm_crtc_vblank_put(crtc);
1438}
1439
89eff4be 1440static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
92f2584a
JB		 1441{
1442 u32 val;
1443 bool enabled;
1444
e2c719b7 1445 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
9d82aa17 1446
92f2584a
JB		 1447 val = I915_READ(PCH_DREF_CONTROL);
1448 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1449 DREF_SUPERSPREAD_SOURCE_MASK));
e2c719b7 1450 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
92f2584a
JB		 1451}
1452
ab9412ba
DV		 1453static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1454 enum pipe pipe)
92f2584a
JB		 1455{
1456 int reg;
1457 u32 val;
1458 bool enabled;
1459
ab9412ba 1460 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1461 val = I915_READ(reg);
1462 enabled = !!(val & TRANS_ENABLE);
e2c719b7 1463 I915_STATE_WARN(enabled,
9db4a9c7
JB		 1464 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1465 pipe_name(pipe));
92f2584a
JB		 1466}
1467
4e634389
KP		 1468static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1469 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1470{
1471 if ((val & DP_PORT_EN) == 0)
1472 return false;
1473
1474 if (HAS_PCH_CPT(dev_priv->dev)) {
1475 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1476 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1477 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1478 return false;
44f37d1f
CML		 1479 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1480 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1481 return false;
f0575e92
KP		 1482 } else {
1483 if ((val & DP_PIPE_MASK) != (pipe << 30))
1484 return false;
1485 }
1486 return true;
1487}
1488
1519b995
KP		 1489static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1490 enum pipe pipe, u32 val)
1491{
dc0fa718 1492 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1493 return false;
1494
1495 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1496 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995 1497 return false;
44f37d1f
CML		 1498 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1499 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1500 return false;
1519b995 1501 } else {
dc0fa718 1502 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1503 return false;
1504 }
1505 return true;
1506}
1507
1508static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1509 enum pipe pipe, u32 val)
1510{
1511 if ((val & LVDS_PORT_EN) == 0)
1512 return false;
1513
1514 if (HAS_PCH_CPT(dev_priv->dev)) {
1515 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1516 return false;
1517 } else {
1518 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1519 return false;
1520 }
1521 return true;
1522}
1523
1524static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1525 enum pipe pipe, u32 val)
1526{
1527 if ((val & ADPA_DAC_ENABLE) == 0)
1528 return false;
1529 if (HAS_PCH_CPT(dev_priv->dev)) {
1530 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1531 return false;
1532 } else {
1533 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1534 return false;
1535 }
1536 return true;
1537}
1538
291906f1 1539static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1540 enum pipe pipe, int reg, u32 port_sel)
291906f1 1541{
47a05eca 1542 u32 val = I915_READ(reg);
e2c719b7 1543 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1544 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1545 reg, pipe_name(pipe));
de9a35ab 1546
e2c719b7 1547 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
75c5da27 1548 && (val & DP_PIPEB_SELECT),
de9a35ab 1549 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1550}
1551
1552static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1553 enum pipe pipe, int reg)
1554{
47a05eca 1555 u32 val = I915_READ(reg);
e2c719b7 1556 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1557 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1558 reg, pipe_name(pipe));
de9a35ab 1559
e2c719b7 1560 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1561 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1562 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1563}
1564
1565static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1566 enum pipe pipe)
1567{
1568 int reg;
1569 u32 val;
291906f1 1570
f0575e92
KP		 1571 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1572 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1573 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1574
1575 reg = PCH_ADPA;
1576 val = I915_READ(reg);
e2c719b7 1577 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1578 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1579 pipe_name(pipe));
291906f1
JB		 1580
1581 reg = PCH_LVDS;
1582 val = I915_READ(reg);
e2c719b7 1583 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1584 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1585 pipe_name(pipe));
291906f1 1586
e2debe91
PZ		 1587 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1588 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1589 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1590}
1591
40e9cf64
JB		 1592static void intel_init_dpio(struct drm_device *dev)
1593{
1594 struct drm_i915_private *dev_priv = dev->dev_private;
1595
1596 if (!IS_VALLEYVIEW(dev))
1597 return;
1598
a09caddd
CML		 1599 /*
1600 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1601 * CHV x1 PHY (DP/HDMI D)
1602 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1603 */
1604 if (IS_CHERRYVIEW(dev)) {
1605 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1606 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1607 } else {
1608 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1609 }
5382f5f3
JB		 1610}
1611
d288f65f 1612static void vlv_enable_pll(struct intel_crtc *crtc,
5cec258b 1613 const struct intel_crtc_state *pipe_config)
87442f73 1614{
426115cf
DV		 1615 struct drm_device *dev = crtc->base.dev;
1616 struct drm_i915_private *dev_priv = dev->dev_private;
1617 int reg = DPLL(crtc->pipe);
d288f65f 1618 u32 dpll = pipe_config->dpll_hw_state.dpll;
87442f73 1619
426115cf 1620 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1621
1622 /* No really, not for ILK+ */
1623 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1624
1625 /* PLL is protected by panel, make sure we can write it */
6a9e7363 1626 if (IS_MOBILE(dev_priv->dev))
426115cf 1627 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1628
426115cf
DV		 1629 I915_WRITE(reg, dpll);
1630 POSTING_READ(reg);
1631 udelay(150);
1632
1633 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1634 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1635
d288f65f 1636 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
426115cf 1637 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1638
1639 /* We do this three times for luck */
426115cf 1640 I915_WRITE(reg, dpll);
87442f73
DV		 1641 POSTING_READ(reg);
1642 udelay(150); /* wait for warmup */
426115cf 1643 I915_WRITE(reg, dpll);
87442f73
DV		 1644 POSTING_READ(reg);
1645 udelay(150); /* wait for warmup */
426115cf 1646 I915_WRITE(reg, dpll);
87442f73
DV		 1647 POSTING_READ(reg);
1648 udelay(150); /* wait for warmup */
1649}
1650
d288f65f 1651static void chv_enable_pll(struct intel_crtc *crtc,
5cec258b 1652 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 1653{
1654 struct drm_device *dev = crtc->base.dev;
1655 struct drm_i915_private *dev_priv = dev->dev_private;
1656 int pipe = crtc->pipe;
1657 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9d556c99
CML		 1658 u32 tmp;
1659
1660 assert_pipe_disabled(dev_priv, crtc->pipe);
1661
1662 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1663
1664 mutex_lock(&dev_priv->dpio_lock);
1665
1666 /* Enable back the 10bit clock to display controller */
1667 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1668 tmp |= DPIO_DCLKP_EN;
1669 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1670
1671 /*
1672 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1673 */
1674 udelay(1);
1675
1676 /* Enable PLL */
d288f65f 1677 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
9d556c99
CML		 1678
1679 /* Check PLL is locked */
a11b0703 1680 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
9d556c99
CML		 1681 DRM_ERROR("PLL %d failed to lock\n", pipe);
1682
a11b0703 1683 /* not sure when this should be written */
d288f65f 1684 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
a11b0703
VS		 1685 POSTING_READ(DPLL_MD(pipe));
1686
9d556c99
CML		 1687 mutex_unlock(&dev_priv->dpio_lock);
1688}
1689
1c4e0274
VS		 1690static int intel_num_dvo_pipes(struct drm_device *dev)
1691{
1692 struct intel_crtc *crtc;
1693 int count = 0;
1694
1695 for_each_intel_crtc(dev, crtc)
1696 count += crtc->active &&
409ee761 1697 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1c4e0274
VS		 1698
1699 return count;
1700}
1701
66e3d5c0 1702static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1703{
66e3d5c0
DV		 1704 struct drm_device *dev = crtc->base.dev;
1705 struct drm_i915_private *dev_priv = dev->dev_private;
1706 int reg = DPLL(crtc->pipe);
6e3c9717 1707 u32 dpll = crtc->config->dpll_hw_state.dpll;
63d7bbe9 1708
66e3d5c0 1709 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1710
63d7bbe9 1711 /* No really, not for ILK+ */
3d13ef2e 1712 BUG_ON(INTEL_INFO(dev)->gen >= 5);
63d7bbe9
JB		 1713
1714 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1715 if (IS_MOBILE(dev) && !IS_I830(dev))
1716 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1717
1c4e0274
VS		 1718 /* Enable DVO 2x clock on both PLLs if necessary */
1719 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1720 /*
1721 * It appears to be important that we don't enable this
1722 * for the current pipe before otherwise configuring the
1723 * PLL. No idea how this should be handled if multiple
1724 * DVO outputs are enabled simultaneosly.
1725 */
1726 dpll |= DPLL_DVO_2X_MODE;
1727 I915_WRITE(DPLL(!crtc->pipe),
1728 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1729 }
66e3d5c0
DV		 1730
1731 /* Wait for the clocks to stabilize. */
1732 POSTING_READ(reg);
1733 udelay(150);
1734
1735 if (INTEL_INFO(dev)->gen >= 4) {
1736 I915_WRITE(DPLL_MD(crtc->pipe),
6e3c9717 1737 crtc->config->dpll_hw_state.dpll_md);
66e3d5c0
DV		 1738 } else {
1739 /* The pixel multiplier can only be updated once the
1740 * DPLL is enabled and the clocks are stable.
1741 *
1742 * So write it again.
1743 */
1744 I915_WRITE(reg, dpll);
1745 }
63d7bbe9
JB		 1746
1747 /* We do this three times for luck */
66e3d5c0 1748 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1749 POSTING_READ(reg);
1750 udelay(150); /* wait for warmup */
66e3d5c0 1751 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1752 POSTING_READ(reg);
1753 udelay(150); /* wait for warmup */
66e3d5c0 1754 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1755 POSTING_READ(reg);
1756 udelay(150); /* wait for warmup */
1757}
1758
1759/**
50b44a44 1760 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1761 * @dev_priv: i915 private structure
1762 * @pipe: pipe PLL to disable
1763 *
1764 * Disable the PLL for @pipe, making sure the pipe is off first.
1765 *
1766 * Note! This is for pre-ILK only.
1767 */
1c4e0274 1768static void i9xx_disable_pll(struct intel_crtc *crtc)
63d7bbe9 1769{
1c4e0274
VS		 1770 struct drm_device *dev = crtc->base.dev;
1771 struct drm_i915_private *dev_priv = dev->dev_private;
1772 enum pipe pipe = crtc->pipe;
1773
1774 /* Disable DVO 2x clock on both PLLs if necessary */
1775 if (IS_I830(dev) &&
409ee761 1776 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1c4e0274
VS		 1777 intel_num_dvo_pipes(dev) == 1) {
1778 I915_WRITE(DPLL(PIPE_B),
1779 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1780 I915_WRITE(DPLL(PIPE_A),
1781 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1782 }
1783
b6b5d049
VS		 1784 /* Don't disable pipe or pipe PLLs if needed */
1785 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1786 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
63d7bbe9
JB		 1787 return;
1788
1789 /* Make sure the pipe isn't still relying on us */
1790 assert_pipe_disabled(dev_priv, pipe);
1791
50b44a44
DV		 1792 I915_WRITE(DPLL(pipe), 0);
1793 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1794}
1795
f6071166
JB		 1796static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1797{
1798 u32 val = 0;
1799
1800 /* Make sure the pipe isn't still relying on us */
1801 assert_pipe_disabled(dev_priv, pipe);
1802
e5cbfbfb
ID		 1803 /*
1804 * Leave integrated clock source and reference clock enabled for pipe B.
1805 * The latter is needed for VGA hotplug / manual detection.
1806 */
f6071166 1807 if (pipe == PIPE_B)
e5cbfbfb 1808 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
f6071166
JB		 1809 I915_WRITE(DPLL(pipe), val);
1810 POSTING_READ(DPLL(pipe));
076ed3b2
CML		 1811
1812}
1813
1814static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1815{
d752048d 1816 enum dpio_channel port = vlv_pipe_to_channel(pipe);
076ed3b2
CML		 1817 u32 val;
1818
a11b0703
VS		 1819 /* Make sure the pipe isn't still relying on us */
1820 assert_pipe_disabled(dev_priv, pipe);
076ed3b2 1821
a11b0703 1822 /* Set PLL en = 0 */
d17ec4ce 1823 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
a11b0703
VS		 1824 if (pipe != PIPE_A)
1825 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1826 I915_WRITE(DPLL(pipe), val);
1827 POSTING_READ(DPLL(pipe));
d752048d
VS		 1828
1829 mutex_lock(&dev_priv->dpio_lock);
1830
1831 /* Disable 10bit clock to display controller */
1832 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1833 val &= ~DPIO_DCLKP_EN;
1834 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1835
61407f6d
VS		 1836 /* disable left/right clock distribution */
1837 if (pipe != PIPE_B) {
1838 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1839 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1840 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1841 } else {
1842 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1843 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1844 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1845 }
1846
d752048d 1847 mutex_unlock(&dev_priv->dpio_lock);
f6071166
JB		 1848}
1849
e4607fcf 1850void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
9b6de0a1
VS		 1851 struct intel_digital_port *dport,
1852 unsigned int expected_mask)
89b667f8
JB		 1853{
1854 u32 port_mask;
00fc31b7 1855 int dpll_reg;
89b667f8 1856
e4607fcf
CML		 1857 switch (dport->port) {
1858 case PORT_B:
89b667f8 1859 port_mask = DPLL_PORTB_READY_MASK;
00fc31b7 1860 dpll_reg = DPLL(0);
e4607fcf
CML		 1861 break;
1862 case PORT_C:
89b667f8 1863 port_mask = DPLL_PORTC_READY_MASK;
00fc31b7 1864 dpll_reg = DPLL(0);
9b6de0a1 1865 expected_mask <<= 4;
00fc31b7
CML		 1866 break;
1867 case PORT_D:
1868 port_mask = DPLL_PORTD_READY_MASK;
1869 dpll_reg = DPIO_PHY_STATUS;
e4607fcf
CML		 1870 break;
1871 default:
1872 BUG();
1873 }
89b667f8 1874
9b6de0a1
VS		 1875 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1876 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1877 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
89b667f8
JB		 1878}
1879
b14b1055
DV		 1880static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1881{
1882 struct drm_device *dev = crtc->base.dev;
1883 struct drm_i915_private *dev_priv = dev->dev_private;
1884 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1885
be19f0ff
CW		 1886 if (WARN_ON(pll == NULL))
1887 return;
1888
3e369b76 1889 WARN_ON(!pll->config.crtc_mask);
b14b1055
DV		 1890 if (pll->active == 0) {
1891 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1892 WARN_ON(pll->on);
1893 assert_shared_dpll_disabled(dev_priv, pll);
1894
1895 pll->mode_set(dev_priv, pll);
1896 }
1897}
1898
92f2584a 1899/**
85b3894f 1900 * intel_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1901 * @dev_priv: i915 private structure
1902 * @pipe: pipe PLL to enable
1903 *
1904 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1905 * drives the transcoder clock.
1906 */
85b3894f 1907static void intel_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1908{
3d13ef2e
DL		 1909 struct drm_device *dev = crtc->base.dev;
1910 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1911 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1912
87a875bb 1913 if (WARN_ON(pll == NULL))
48da64a8
CW		 1914 return;
1915
3e369b76 1916 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1917 return;
ee7b9f93 1918
74dd6928 1919 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
46edb027 1920 pll->name, pll->active, pll->on,
e2b78267 1921 crtc->base.base.id);
92f2584a 1922
cdbd2316
DV		 1923 if (pll->active++) {
1924 WARN_ON(!pll->on);
e9d6944e 1925 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1926 return;
1927 }
f4a091c7 1928 WARN_ON(pll->on);
ee7b9f93 1929
bd2bb1b9
PZ		 1930 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1931
46edb027 1932 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1933 pll->enable(dev_priv, pll);
ee7b9f93 1934 pll->on = true;
92f2584a
JB		 1935}
1936
f6daaec2 1937static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1938{
3d13ef2e
DL		 1939 struct drm_device *dev = crtc->base.dev;
1940 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1941 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1942
92f2584a 1943 /* PCH only available on ILK+ */
3d13ef2e 1944 BUG_ON(INTEL_INFO(dev)->gen < 5);
87a875bb 1945 if (WARN_ON(pll == NULL))
ee7b9f93 1946 return;
92f2584a 1947
3e369b76 1948 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1949 return;
7a419866 1950
46edb027
DV		 1951 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1952 pll->name, pll->active, pll->on,
e2b78267 1953 crtc->base.base.id);
7a419866 1954
48da64a8 1955 if (WARN_ON(pll->active == 0)) {
e9d6944e 1956 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1957 return;
1958 }
1959
e9d6944e 1960 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1961 WARN_ON(!pll->on);
cdbd2316 1962 if (--pll->active)
7a419866 1963 return;
ee7b9f93 1964
46edb027 1965 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1966 pll->disable(dev_priv, pll);
ee7b9f93 1967 pll->on = false;
bd2bb1b9
PZ		 1968
1969 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
92f2584a
JB		 1970}
1971
b8a4f404
PZ		 1972static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1973 enum pipe pipe)
040484af 1974{
23670b32 1975 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1976 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1977 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1978 uint32_t reg, val, pipeconf_val;
040484af
JB		 1979
1980 /* PCH only available on ILK+ */
55522f37 1981 BUG_ON(!HAS_PCH_SPLIT(dev));
040484af
JB		 1982
1983 /* Make sure PCH DPLL is enabled */
e72f9fbf 1984 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1985 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1986
1987 /* FDI must be feeding us bits for PCH ports */
1988 assert_fdi_tx_enabled(dev_priv, pipe);
1989 assert_fdi_rx_enabled(dev_priv, pipe);
1990
23670b32
DV		 1991 if (HAS_PCH_CPT(dev)) {
1992 /* Workaround: Set the timing override bit before enabling the
1993 * pch transcoder. */
1994 reg = TRANS_CHICKEN2(pipe);
1995 val = I915_READ(reg);
1996 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1997 I915_WRITE(reg, val);
59c859d6 1998 }
23670b32 1999
ab9412ba 2000 reg = PCH_TRANSCONF(pipe);
040484af 2001 val = I915_READ(reg);
5f7f726d 2002 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 2003
2004 if (HAS_PCH_IBX(dev_priv->dev)) {
2005 /*
2006 * make the BPC in transcoder be consistent with
2007 * that in pipeconf reg.
2008 */
dfd07d72
DV		 2009 val &= ~PIPECONF_BPC_MASK;
2010 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 2011 }
5f7f726d
PZ		 2012
2013 val &= ~TRANS_INTERLACE_MASK;
2014 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6 2015 if (HAS_PCH_IBX(dev_priv->dev) &&
409ee761 2016 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7c26e5c6
PZ		 2017 val |= TRANS_LEGACY_INTERLACED_ILK;
2018 else
2019 val |= TRANS_INTERLACED;
5f7f726d
PZ		 2020 else
2021 val |= TRANS_PROGRESSIVE;
2022
040484af
JB		 2023 I915_WRITE(reg, val | TRANS_ENABLE);
2024 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 2025 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 2026}
2027
8fb033d7 2028static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 2029 enum transcoder cpu_transcoder)
040484af 2030{
8fb033d7 2031 u32 val, pipeconf_val;
8fb033d7
PZ		 2032
2033 /* PCH only available on ILK+ */
55522f37 2034 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
8fb033d7 2035
8fb033d7 2036 /* FDI must be feeding us bits for PCH ports */
1a240d4d 2037 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 2038 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 2039
223a6fdf
PZ		 2040 /* Workaround: set timing override bit. */
2041 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2042 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 2043 I915_WRITE(_TRANSA_CHICKEN2, val);
2044
25f3ef11 2045 val = TRANS_ENABLE;
937bb610 2046 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 2047
9a76b1c6
PZ		 2048 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2049 PIPECONF_INTERLACED_ILK)
a35f2679 2050 val |= TRANS_INTERLACED;
8fb033d7
PZ		 2051 else
2052 val |= TRANS_PROGRESSIVE;
2053
ab9412ba
DV		 2054 I915_WRITE(LPT_TRANSCONF, val);
2055 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 2056 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 2057}
2058
b8a4f404
PZ		 2059static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2060 enum pipe pipe)
040484af 2061{
23670b32
DV		 2062 struct drm_device *dev = dev_priv->dev;
2063 uint32_t reg, val;
040484af
JB		 2064
2065 /* FDI relies on the transcoder */
2066 assert_fdi_tx_disabled(dev_priv, pipe);
2067 assert_fdi_rx_disabled(dev_priv, pipe);
2068
291906f1
JB		 2069 /* Ports must be off as well */
2070 assert_pch_ports_disabled(dev_priv, pipe);
2071
ab9412ba 2072 reg = PCH_TRANSCONF(pipe);
040484af
JB		 2073 val = I915_READ(reg);
2074 val &= ~TRANS_ENABLE;
2075 I915_WRITE(reg, val);
2076 /* wait for PCH transcoder off, transcoder state */
2077 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 2078 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 2079
2080 if (!HAS_PCH_IBX(dev)) {
2081 /* Workaround: Clear the timing override chicken bit again. */
2082 reg = TRANS_CHICKEN2(pipe);
2083 val = I915_READ(reg);
2084 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2085 I915_WRITE(reg, val);
2086 }
040484af
JB		 2087}
2088
ab4d966c 2089static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 2090{
8fb033d7
PZ		 2091 u32 val;
2092
ab9412ba 2093 val = I915_READ(LPT_TRANSCONF);
8fb033d7 2094 val &= ~TRANS_ENABLE;
ab9412ba 2095 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 2096 /* wait for PCH transcoder off, transcoder state */
ab9412ba 2097 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 2098 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 2099
2100 /* Workaround: clear timing override bit. */
2101 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2102 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 2103 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 2104}
2105
b24e7179 2106/**
309cfea8 2107 * intel_enable_pipe - enable a pipe, asserting requirements
0372264a 2108 * @crtc: crtc responsible for the pipe
b24e7179 2109 *
0372264a 2110 * Enable @crtc's pipe, making sure that various hardware specific requirements
b24e7179 2111 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
b24e7179 2112 */
e1fdc473 2113static void intel_enable_pipe(struct intel_crtc *crtc)
b24e7179 2114{
0372264a
PZ		 2115 struct drm_device *dev = crtc->base.dev;
2116 struct drm_i915_private *dev_priv = dev->dev_private;
2117 enum pipe pipe = crtc->pipe;
702e7a56
PZ		 2118 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2119 pipe);
1a240d4d 2120 enum pipe pch_transcoder;
b24e7179
JB		 2121 int reg;
2122 u32 val;
2123
58c6eaa2 2124 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2125 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 2126 assert_sprites_disabled(dev_priv, pipe);
2127
681e5811 2128 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 2129 pch_transcoder = TRANSCODER_A;
2130 else
2131 pch_transcoder = pipe;
2132
b24e7179
JB		 2133 /*
2134 * A pipe without a PLL won't actually be able to drive bits from
2135 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2136 * need the check.
2137 */
50360403 2138 if (HAS_GMCH_DISPLAY(dev_priv->dev))
409ee761 2139 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
23538ef1
JN		 2140 assert_dsi_pll_enabled(dev_priv);
2141 else
2142 assert_pll_enabled(dev_priv, pipe);
040484af 2143 else {
6e3c9717 2144 if (crtc->config->has_pch_encoder) {
040484af 2145 /* if driving the PCH, we need FDI enabled */
cc391bbb 2146 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 2147 assert_fdi_tx_pll_enabled(dev_priv,
2148 (enum pipe) cpu_transcoder);
040484af
JB		 2149 }
2150 /* FIXME: assert CPU port conditions for SNB+ */
2151 }
b24e7179 2152
702e7a56 2153 reg = PIPECONF(cpu_transcoder);
b24e7179 2154 val = I915_READ(reg);
7ad25d48 2155 if (val & PIPECONF_ENABLE) {
b6b5d049
VS		 2156 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2157 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
00d70b15 2158 return;
7ad25d48 2159 }
00d70b15
CW		 2160
2161 I915_WRITE(reg, val | PIPECONF_ENABLE);
851855d8 2162 POSTING_READ(reg);
b24e7179
JB		 2163}
2164
2165/**
309cfea8 2166 * intel_disable_pipe - disable a pipe, asserting requirements
575f7ab7 2167 * @crtc: crtc whose pipes is to be disabled
b24e7179 2168 *
575f7ab7
VS		 2169 * Disable the pipe of @crtc, making sure that various hardware
2170 * specific requirements are met, if applicable, e.g. plane
2171 * disabled, panel fitter off, etc.
b24e7179
JB		 2172 *
2173 * Will wait until the pipe has shut down before returning.
2174 */
575f7ab7 2175static void intel_disable_pipe(struct intel_crtc *crtc)
b24e7179 2176{
575f7ab7 2177 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
6e3c9717 2178 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 2179 enum pipe pipe = crtc->pipe;
b24e7179
JB		 2180 int reg;
2181 u32 val;
2182
2183 /*
2184 * Make sure planes won't keep trying to pump pixels to us,
2185 * or we might hang the display.
2186 */
2187 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2188 assert_cursor_disabled(dev_priv, pipe);
19332d7a 2189 assert_sprites_disabled(dev_priv, pipe);
b24e7179 2190
702e7a56 2191 reg = PIPECONF(cpu_transcoder);
b24e7179 2192 val = I915_READ(reg);
00d70b15
CW		 2193 if ((val & PIPECONF_ENABLE) == 0)
2194 return;
2195
67adc644
VS		 2196 /*
2197 * Double wide has implications for planes
2198 * so best keep it disabled when not needed.
2199 */
6e3c9717 2200 if (crtc->config->double_wide)
67adc644
VS		 2201 val &= ~PIPECONF_DOUBLE_WIDE;
2202
2203 /* Don't disable pipe or pipe PLLs if needed */
b6b5d049
VS		 2204 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2205 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
67adc644
VS		 2206 val &= ~PIPECONF_ENABLE;
2207
2208 I915_WRITE(reg, val);
2209 if ((val & PIPECONF_ENABLE) == 0)
2210 intel_wait_for_pipe_off(crtc);
b24e7179
JB		 2211}
2212
d74362c9
KP		 2213/*
2214 * Plane regs are double buffered, going from enabled->disabled needs a
2215 * trigger in order to latch. The display address reg provides this.
2216 */
1dba99f4
VS		 2217void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2218 enum plane plane)
d74362c9 2219{
3d13ef2e
DL		 2220 struct drm_device *dev = dev_priv->dev;
2221 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
1dba99f4
VS		 2222
2223 I915_WRITE(reg, I915_READ(reg));
2224 POSTING_READ(reg);
d74362c9
KP		 2225}
2226
b24e7179 2227/**
262ca2b0 2228 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
fdd508a6
VS		 2229 * @plane: plane to be enabled
2230 * @crtc: crtc for the plane
b24e7179 2231 *
fdd508a6 2232 * Enable @plane on @crtc, making sure that the pipe is running first.
b24e7179 2233 */
fdd508a6
VS		 2234static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2235 struct drm_crtc *crtc)
b24e7179 2236{
fdd508a6
VS		 2237 struct drm_device *dev = plane->dev;
2238 struct drm_i915_private *dev_priv = dev->dev_private;
2239 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b24e7179
JB		 2240
2241 /* If the pipe isn't enabled, we can't pump pixels and may hang */
fdd508a6 2242 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
b70709a6 2243 to_intel_plane_state(plane->state)->visible = true;
939c2fe8 2244
fdd508a6
VS		 2245 dev_priv->display.update_primary_plane(crtc, plane->fb,
2246 crtc->x, crtc->y);
b24e7179
JB		 2247}
2248
693db184
CW		 2249static bool need_vtd_wa(struct drm_device *dev)
2250{
2251#ifdef CONFIG_INTEL_IOMMU
2252 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2253 return true;
2254#endif
2255 return false;
2256}
2257
50470bb0 2258unsigned int
6761dd31
TU		 2259intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2260 uint64_t fb_format_modifier)
a57ce0b2 2261{
6761dd31
TU		 2262 unsigned int tile_height;
2263 uint32_t pixel_bytes;
a57ce0b2 2264
b5d0e9bf
DL		 2265 switch (fb_format_modifier) {
2266 case DRM_FORMAT_MOD_NONE:
2267 tile_height = 1;
2268 break;
2269 case I915_FORMAT_MOD_X_TILED:
2270 tile_height = IS_GEN2(dev) ? 16 : 8;
2271 break;
2272 case I915_FORMAT_MOD_Y_TILED:
2273 tile_height = 32;
2274 break;
2275 case I915_FORMAT_MOD_Yf_TILED:
6761dd31
TU		 2276 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2277 switch (pixel_bytes) {
b5d0e9bf 2278 default:
6761dd31 2279 case 1:
b5d0e9bf
DL		 2280 tile_height = 64;
2281 break;
6761dd31
TU		 2282 case 2:
2283 case 4:
b5d0e9bf
DL		 2284 tile_height = 32;
2285 break;
6761dd31 2286 case 8:
b5d0e9bf
DL		 2287 tile_height = 16;
2288 break;
6761dd31 2289 case 16:
b5d0e9bf
DL		 2290 WARN_ONCE(1,
2291 "128-bit pixels are not supported for display!");
2292 tile_height = 16;
2293 break;
2294 }
2295 break;
2296 default:
2297 MISSING_CASE(fb_format_modifier);
2298 tile_height = 1;
2299 break;
2300 }
091df6cb 2301
6761dd31
TU		 2302 return tile_height;
2303}
2304
2305unsigned int
2306intel_fb_align_height(struct drm_device *dev, unsigned int height,
2307 uint32_t pixel_format, uint64_t fb_format_modifier)
2308{
2309 return ALIGN(height, intel_tile_height(dev, pixel_format,
2310 fb_format_modifier));
a57ce0b2
JB		 2311}
2312
f64b98cd
TU		 2313static int
2314intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2315 const struct drm_plane_state *plane_state)
2316{
50470bb0 2317 struct intel_rotation_info *info = &view->rotation_info;
50470bb0 2318
f64b98cd
TU		 2319 *view = i915_ggtt_view_normal;
2320
50470bb0
TU		 2321 if (!plane_state)
2322 return 0;
2323
121920fa 2324 if (!intel_rotation_90_or_270(plane_state->rotation))
50470bb0
TU		 2325 return 0;
2326
9abc4648 2327 *view = i915_ggtt_view_rotated;
50470bb0
TU		 2328
2329 info->height = fb->height;
2330 info->pixel_format = fb->pixel_format;
2331 info->pitch = fb->pitches[0];
2332 info->fb_modifier = fb->modifier[0];
2333
f64b98cd
TU		 2334 return 0;
2335}
2336
127bd2ac 2337int
850c4cdc
TU		 2338intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2339 struct drm_framebuffer *fb,
82bc3b2d 2340 const struct drm_plane_state *plane_state,
a4872ba6 2341 struct intel_engine_cs *pipelined)
6b95a207 2342{
850c4cdc 2343 struct drm_device *dev = fb->dev;
ce453d81 2344 struct drm_i915_private *dev_priv = dev->dev_private;
850c4cdc 2345 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd 2346 struct i915_ggtt_view view;
6b95a207
KH		 2347 u32 alignment;
2348 int ret;
2349
ebcdd39e
MR		 2350 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2351
7b911adc
TU		 2352 switch (fb->modifier[0]) {
2353 case DRM_FORMAT_MOD_NONE:
1fada4cc
DL		 2354 if (INTEL_INFO(dev)->gen >= 9)
2355 alignment = 256 * 1024;
2356 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
534843da 2357 alignment = 128 * 1024;
a6c45cf0 2358 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 2359 alignment = 4 * 1024;
2360 else
2361 alignment = 64 * 1024;
6b95a207 2362 break;
7b911adc 2363 case I915_FORMAT_MOD_X_TILED:
1fada4cc
DL		 2364 if (INTEL_INFO(dev)->gen >= 9)
2365 alignment = 256 * 1024;
2366 else {
2367 /* pin() will align the object as required by fence */
2368 alignment = 0;
2369 }
6b95a207 2370 break;
7b911adc 2371 case I915_FORMAT_MOD_Y_TILED:
1327b9a1
DL		 2372 case I915_FORMAT_MOD_Yf_TILED:
2373 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2374 "Y tiling bo slipped through, driver bug!\n"))
2375 return -EINVAL;
2376 alignment = 1 * 1024 * 1024;
2377 break;
6b95a207 2378 default:
7b911adc
TU		 2379 MISSING_CASE(fb->modifier[0]);
2380 return -EINVAL;
6b95a207
KH		 2381 }
2382
f64b98cd
TU		 2383 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2384 if (ret)
2385 return ret;
2386
693db184
CW		 2387 /* Note that the w/a also requires 64 PTE of padding following the
2388 * bo. We currently fill all unused PTE with the shadow page and so
2389 * we should always have valid PTE following the scanout preventing
2390 * the VT-d warning.
2391 */
2392 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2393 alignment = 256 * 1024;
2394
d6dd6843
PZ		 2395 /*
2396 * Global gtt pte registers are special registers which actually forward
2397 * writes to a chunk of system memory. Which means that there is no risk
2398 * that the register values disappear as soon as we call
2399 * intel_runtime_pm_put(), so it is correct to wrap only the
2400 * pin/unpin/fence and not more.
2401 */
2402 intel_runtime_pm_get(dev_priv);
2403
ce453d81 2404 dev_priv->mm.interruptible = false;
e6617330 2405 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
f64b98cd 2406 &view);
48b956c5 2407 if (ret)
ce453d81 2408 goto err_interruptible;
6b95a207
KH		 2409
2410 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2411 * fence, whereas 965+ only requires a fence if using
2412 * framebuffer compression. For simplicity, we always install
2413 * a fence as the cost is not that onerous.
2414 */
06d98131 2415 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 2416 if (ret)
2417 goto err_unpin;
1690e1eb 2418
9a5a53b3 2419 i915_gem_object_pin_fence(obj);
6b95a207 2420
ce453d81 2421 dev_priv->mm.interruptible = true;
d6dd6843 2422 intel_runtime_pm_put(dev_priv);
6b95a207 2423 return 0;
48b956c5
CW		 2424
2425err_unpin:
f64b98cd 2426 i915_gem_object_unpin_from_display_plane(obj, &view);
ce453d81
CW		 2427err_interruptible:
2428 dev_priv->mm.interruptible = true;
d6dd6843 2429 intel_runtime_pm_put(dev_priv);
48b956c5 2430 return ret;
6b95a207
KH		 2431}
2432
82bc3b2d
TU		 2433static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2434 const struct drm_plane_state *plane_state)
1690e1eb 2435{
82bc3b2d 2436 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd
TU		 2437 struct i915_ggtt_view view;
2438 int ret;
82bc3b2d 2439
ebcdd39e
MR		 2440 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2441
f64b98cd
TU		 2442 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2443 WARN_ONCE(ret, "Couldn't get view from plane state!");
2444
1690e1eb 2445 i915_gem_object_unpin_fence(obj);
f64b98cd 2446 i915_gem_object_unpin_from_display_plane(obj, &view);
1690e1eb
CW		 2447}
2448
c2c75131
DV		 2449/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2450 * is assumed to be a power-of-two. */
bc752862
CW		 2451unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2452 unsigned int tiling_mode,
2453 unsigned int cpp,
2454 unsigned int pitch)
c2c75131 2455{
bc752862
CW		 2456 if (tiling_mode != I915_TILING_NONE) {
2457 unsigned int tile_rows, tiles;
c2c75131 2458
bc752862
CW		 2459 tile_rows = *y / 8;
2460 *y %= 8;
c2c75131 2461
bc752862
CW		 2462 tiles = *x / (512/cpp);
2463 *x %= 512/cpp;
2464
2465 return tile_rows * pitch * 8 + tiles * 4096;
2466 } else {
2467 unsigned int offset;
2468
2469 offset = *y * pitch + *x * cpp;
2470 *y = 0;
2471 *x = (offset & 4095) / cpp;
2472 return offset & -4096;
2473 }
c2c75131
DV		 2474}
2475
b35d63fa 2476static int i9xx_format_to_fourcc(int format)
46f297fb
JB		 2477{
2478 switch (format) {
2479 case DISPPLANE_8BPP:
2480 return DRM_FORMAT_C8;
2481 case DISPPLANE_BGRX555:
2482 return DRM_FORMAT_XRGB1555;
2483 case DISPPLANE_BGRX565:
2484 return DRM_FORMAT_RGB565;
2485 default:
2486 case DISPPLANE_BGRX888:
2487 return DRM_FORMAT_XRGB8888;
2488 case DISPPLANE_RGBX888:
2489 return DRM_FORMAT_XBGR8888;
2490 case DISPPLANE_BGRX101010:
2491 return DRM_FORMAT_XRGB2101010;
2492 case DISPPLANE_RGBX101010:
2493 return DRM_FORMAT_XBGR2101010;
2494 }
2495}
2496
bc8d7dff
DL		 2497static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2498{
2499 switch (format) {
2500 case PLANE_CTL_FORMAT_RGB_565:
2501 return DRM_FORMAT_RGB565;
2502 default:
2503 case PLANE_CTL_FORMAT_XRGB_8888:
2504 if (rgb_order) {
2505 if (alpha)
2506 return DRM_FORMAT_ABGR8888;
2507 else
2508 return DRM_FORMAT_XBGR8888;
2509 } else {
2510 if (alpha)
2511 return DRM_FORMAT_ARGB8888;
2512 else
2513 return DRM_FORMAT_XRGB8888;
2514 }
2515 case PLANE_CTL_FORMAT_XRGB_2101010:
2516 if (rgb_order)
2517 return DRM_FORMAT_XBGR2101010;
2518 else
2519 return DRM_FORMAT_XRGB2101010;
2520 }
2521}
2522
5724dbd1 2523static bool
f6936e29
DV		 2524intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2525 struct intel_initial_plane_config *plane_config)
46f297fb
JB		 2526{
2527 struct drm_device *dev = crtc->base.dev;
2528 struct drm_i915_gem_object *obj = NULL;
2529 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2d14030b 2530 struct drm_framebuffer *fb = &plane_config->fb->base;
f37b5c2b
DV		 2531 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2532 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2533 PAGE_SIZE);
2534
2535 size_aligned -= base_aligned;
46f297fb 2536
ff2652ea
CW		 2537 if (plane_config->size == 0)
2538 return false;
2539
f37b5c2b
DV		 2540 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2541 base_aligned,
2542 base_aligned,
2543 size_aligned);
46f297fb 2544 if (!obj)
484b41dd 2545 return false;
46f297fb 2546
49af449b
DL		 2547 obj->tiling_mode = plane_config->tiling;
2548 if (obj->tiling_mode == I915_TILING_X)
6bf129df 2549 obj->stride = fb->pitches[0];
46f297fb 2550
6bf129df
DL		 2551 mode_cmd.pixel_format = fb->pixel_format;
2552 mode_cmd.width = fb->width;
2553 mode_cmd.height = fb->height;
2554 mode_cmd.pitches[0] = fb->pitches[0];
18c5247e
DV		 2555 mode_cmd.modifier[0] = fb->modifier[0];
2556 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
46f297fb
JB		 2557
2558 mutex_lock(&dev->struct_mutex);
6bf129df 2559 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
484b41dd 2560 &mode_cmd, obj)) {
46f297fb
JB		 2561 DRM_DEBUG_KMS("intel fb init failed\n");
2562 goto out_unref_obj;
2563 }
46f297fb 2564 mutex_unlock(&dev->struct_mutex);
484b41dd 2565
f6936e29 2566 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
484b41dd 2567 return true;
46f297fb
JB		 2568
2569out_unref_obj:
2570 drm_gem_object_unreference(&obj->base);
2571 mutex_unlock(&dev->struct_mutex);
484b41dd
JB		 2572 return false;
2573}
2574
afd65eb4
MR		 2575/* Update plane->state->fb to match plane->fb after driver-internal updates */
2576static void
2577update_state_fb(struct drm_plane *plane)
2578{
2579 if (plane->fb == plane->state->fb)
2580 return;
2581
2582 if (plane->state->fb)
2583 drm_framebuffer_unreference(plane->state->fb);
2584 plane->state->fb = plane->fb;
2585 if (plane->state->fb)
2586 drm_framebuffer_reference(plane->state->fb);
2587}
2588
5724dbd1 2589static void
f6936e29
DV		 2590intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2591 struct intel_initial_plane_config *plane_config)
484b41dd
JB		 2592{
2593 struct drm_device *dev = intel_crtc->base.dev;
d9ceb816 2594 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd
JB		 2595 struct drm_crtc *c;
2596 struct intel_crtc *i;
2ff8fde1 2597 struct drm_i915_gem_object *obj;
88595ac9
DV		 2598 struct drm_plane *primary = intel_crtc->base.primary;
2599 struct drm_framebuffer *fb;
484b41dd 2600
2d14030b 2601 if (!plane_config->fb)
484b41dd
JB		 2602 return;
2603
f6936e29 2604 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
88595ac9
DV		 2605 fb = &plane_config->fb->base;
2606 goto valid_fb;
f55548b5 2607 }
484b41dd 2608
2d14030b 2609 kfree(plane_config->fb);
484b41dd
JB		 2610
2611 /*
2612 * Failed to alloc the obj, check to see if we should share
2613 * an fb with another CRTC instead
2614 */
70e1e0ec 2615 for_each_crtc(dev, c) {
484b41dd
JB		 2616 i = to_intel_crtc(c);
2617
2618 if (c == &intel_crtc->base)
2619 continue;
2620
2ff8fde1
MR		 2621 if (!i->active)
2622 continue;
2623
88595ac9
DV		 2624 fb = c->primary->fb;
2625 if (!fb)
484b41dd
JB		 2626 continue;
2627
88595ac9 2628 obj = intel_fb_obj(fb);
2ff8fde1 2629 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
88595ac9
DV		 2630 drm_framebuffer_reference(fb);
2631 goto valid_fb;
484b41dd
JB		 2632 }
2633 }
88595ac9
DV		 2634
2635 return;
2636
2637valid_fb:
2638 obj = intel_fb_obj(fb);
2639 if (obj->tiling_mode != I915_TILING_NONE)
2640 dev_priv->preserve_bios_swizzle = true;
2641
2642 primary->fb = fb;
2643 primary->state->crtc = &intel_crtc->base;
2644 primary->crtc = &intel_crtc->base;
2645 update_state_fb(primary);
2646 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
46f297fb
JB		 2647}
2648
29b9bde6
DV		 2649static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2650 struct drm_framebuffer *fb,
2651 int x, int y)
81255565
JB		 2652{
2653 struct drm_device *dev = crtc->dev;
2654 struct drm_i915_private *dev_priv = dev->dev_private;
2655 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2656 struct drm_plane *primary = crtc->primary;
2657 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2658 struct drm_i915_gem_object *obj;
81255565 2659 int plane = intel_crtc->plane;
e506a0c6 2660 unsigned long linear_offset;
81255565 2661 u32 dspcntr;
f45651ba 2662 u32 reg = DSPCNTR(plane);
48404c1e 2663 int pixel_size;
f45651ba 2664
b70709a6 2665 if (!visible || !fb) {
fdd508a6
VS		 2666 I915_WRITE(reg, 0);
2667 if (INTEL_INFO(dev)->gen >= 4)
2668 I915_WRITE(DSPSURF(plane), 0);
2669 else
2670 I915_WRITE(DSPADDR(plane), 0);
2671 POSTING_READ(reg);
2672 return;
2673 }
2674
c9ba6fad
VS		 2675 obj = intel_fb_obj(fb);
2676 if (WARN_ON(obj == NULL))
2677 return;
2678
2679 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2680
f45651ba
VS		 2681 dspcntr = DISPPLANE_GAMMA_ENABLE;
2682
fdd508a6 2683 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2684
2685 if (INTEL_INFO(dev)->gen < 4) {
2686 if (intel_crtc->pipe == PIPE_B)
2687 dspcntr |= DISPPLANE_SEL_PIPE_B;
2688
2689 /* pipesrc and dspsize control the size that is scaled from,
2690 * which should always be the user's requested size.
2691 */
2692 I915_WRITE(DSPSIZE(plane),
6e3c9717
ACO		 2693 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2694 (intel_crtc->config->pipe_src_w - 1));
f45651ba 2695 I915_WRITE(DSPPOS(plane), 0);
c14b0485
VS		 2696 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2697 I915_WRITE(PRIMSIZE(plane),
6e3c9717
ACO		 2698 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2699 (intel_crtc->config->pipe_src_w - 1));
c14b0485
VS		 2700 I915_WRITE(PRIMPOS(plane), 0);
2701 I915_WRITE(PRIMCNSTALPHA(plane), 0);
f45651ba 2702 }
81255565 2703
57779d06
VS		 2704 switch (fb->pixel_format) {
2705 case DRM_FORMAT_C8:
81255565
JB		 2706 dspcntr |= DISPPLANE_8BPP;
2707 break;
57779d06 2708 case DRM_FORMAT_XRGB1555:
57779d06 2709 dspcntr |= DISPPLANE_BGRX555;
81255565 2710 break;
57779d06
VS		 2711 case DRM_FORMAT_RGB565:
2712 dspcntr |= DISPPLANE_BGRX565;
2713 break;
2714 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2715 dspcntr |= DISPPLANE_BGRX888;
2716 break;
2717 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2718 dspcntr |= DISPPLANE_RGBX888;
2719 break;
2720 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2721 dspcntr |= DISPPLANE_BGRX101010;
2722 break;
2723 case DRM_FORMAT_XBGR2101010:
57779d06 2724 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2725 break;
2726 default:
baba133a 2727 BUG();
81255565 2728 }
57779d06 2729
f45651ba
VS		 2730 if (INTEL_INFO(dev)->gen >= 4 &&
2731 obj->tiling_mode != I915_TILING_NONE)
2732 dspcntr |= DISPPLANE_TILED;
81255565 2733
de1aa629
VS		 2734 if (IS_G4X(dev))
2735 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2736
b9897127 2737 linear_offset = y * fb->pitches[0] + x * pixel_size;
81255565 2738
c2c75131
DV		 2739 if (INTEL_INFO(dev)->gen >= 4) {
2740 intel_crtc->dspaddr_offset =
bc752862 2741 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
b9897127 2742 pixel_size,
bc752862 2743 fb->pitches[0]);
c2c75131
DV		 2744 linear_offset -= intel_crtc->dspaddr_offset;
2745 } else {
e506a0c6 2746 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2747 }
e506a0c6 2748
8e7d688b 2749 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2750 dspcntr |= DISPPLANE_ROTATE_180;
2751
6e3c9717
ACO		 2752 x += (intel_crtc->config->pipe_src_w - 1);
2753 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2754
2755 /* Finding the last pixel of the last line of the display
2756 data and adding to linear_offset*/
2757 linear_offset +=
6e3c9717
ACO		 2758 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2759 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2760 }
2761
2762 I915_WRITE(reg, dspcntr);
2763
01f2c773 2764 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2765 if (INTEL_INFO(dev)->gen >= 4) {
85ba7b7d
DV		 2766 I915_WRITE(DSPSURF(plane),
2767 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2768 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2769 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2770 } else
f343c5f6 2771 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2772 POSTING_READ(reg);
17638cd6
JB		 2773}
2774
29b9bde6
DV		 2775static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2776 struct drm_framebuffer *fb,
2777 int x, int y)
17638cd6
JB		 2778{
2779 struct drm_device *dev = crtc->dev;
2780 struct drm_i915_private *dev_priv = dev->dev_private;
2781 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2782 struct drm_plane *primary = crtc->primary;
2783 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2784 struct drm_i915_gem_object *obj;
17638cd6 2785 int plane = intel_crtc->plane;
e506a0c6 2786 unsigned long linear_offset;
17638cd6 2787 u32 dspcntr;
f45651ba 2788 u32 reg = DSPCNTR(plane);
48404c1e 2789 int pixel_size;
f45651ba 2790
b70709a6 2791 if (!visible || !fb) {
fdd508a6
VS		 2792 I915_WRITE(reg, 0);
2793 I915_WRITE(DSPSURF(plane), 0);
2794 POSTING_READ(reg);
2795 return;
2796 }
2797
c9ba6fad
VS		 2798 obj = intel_fb_obj(fb);
2799 if (WARN_ON(obj == NULL))
2800 return;
2801
2802 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2803
f45651ba
VS		 2804 dspcntr = DISPPLANE_GAMMA_ENABLE;
2805
fdd508a6 2806 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2807
2808 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2809 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
17638cd6 2810
57779d06
VS		 2811 switch (fb->pixel_format) {
2812 case DRM_FORMAT_C8:
17638cd6
JB		 2813 dspcntr |= DISPPLANE_8BPP;
2814 break;
57779d06
VS		 2815 case DRM_FORMAT_RGB565:
2816 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2817 break;
57779d06 2818 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2819 dspcntr |= DISPPLANE_BGRX888;
2820 break;
2821 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2822 dspcntr |= DISPPLANE_RGBX888;
2823 break;
2824 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2825 dspcntr |= DISPPLANE_BGRX101010;
2826 break;
2827 case DRM_FORMAT_XBGR2101010:
57779d06 2828 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2829 break;
2830 default:
baba133a 2831 BUG();
17638cd6
JB		 2832 }
2833
2834 if (obj->tiling_mode != I915_TILING_NONE)
2835 dspcntr |= DISPPLANE_TILED;
17638cd6 2836
f45651ba 2837 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
1f5d76db 2838 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6 2839
b9897127 2840 linear_offset = y * fb->pitches[0] + x * pixel_size;
c2c75131 2841 intel_crtc->dspaddr_offset =
bc752862 2842 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
b9897127 2843 pixel_size,
bc752862 2844 fb->pitches[0]);
c2c75131 2845 linear_offset -= intel_crtc->dspaddr_offset;
8e7d688b 2846 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2847 dspcntr |= DISPPLANE_ROTATE_180;
2848
2849 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
6e3c9717
ACO		 2850 x += (intel_crtc->config->pipe_src_w - 1);
2851 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2852
2853 /* Finding the last pixel of the last line of the display
2854 data and adding to linear_offset*/
2855 linear_offset +=
6e3c9717
ACO		 2856 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2857 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2858 }
2859 }
2860
2861 I915_WRITE(reg, dspcntr);
17638cd6 2862
01f2c773 2863 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
85ba7b7d
DV		 2864 I915_WRITE(DSPSURF(plane),
2865 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
b3dc685e 2866 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
bc1c91eb
DL		 2867 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2868 } else {
2869 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2870 I915_WRITE(DSPLINOFF(plane), linear_offset);
2871 }
17638cd6 2872 POSTING_READ(reg);
17638cd6
JB		 2873}
2874
b321803d
DL		 2875u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2876 uint32_t pixel_format)
2877{
2878 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2879
2880 /*
2881 * The stride is either expressed as a multiple of 64 bytes
2882 * chunks for linear buffers or in number of tiles for tiled
2883 * buffers.
2884 */
2885 switch (fb_modifier) {
2886 case DRM_FORMAT_MOD_NONE:
2887 return 64;
2888 case I915_FORMAT_MOD_X_TILED:
2889 if (INTEL_INFO(dev)->gen == 2)
2890 return 128;
2891 return 512;
2892 case I915_FORMAT_MOD_Y_TILED:
2893 /* No need to check for old gens and Y tiling since this is
2894 * about the display engine and those will be blocked before
2895 * we get here.
2896 */
2897 return 128;
2898 case I915_FORMAT_MOD_Yf_TILED:
2899 if (bits_per_pixel == 8)
2900 return 64;
2901 else
2902 return 128;
2903 default:
2904 MISSING_CASE(fb_modifier);
2905 return 64;
2906 }
2907}
2908
121920fa
TU		 2909unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2910 struct drm_i915_gem_object *obj)
2911{
9abc4648 2912 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
121920fa
TU		 2913
2914 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
9abc4648 2915 view = &i915_ggtt_view_rotated;
121920fa
TU		 2916
2917 return i915_gem_obj_ggtt_offset_view(obj, view);
2918}
2919
a1b2278e
CK		 2920/*
2921 * This function detaches (aka. unbinds) unused scalers in hardware
2922 */
2923void skl_detach_scalers(struct intel_crtc *intel_crtc)
2924{
2925 struct drm_device *dev;
2926 struct drm_i915_private *dev_priv;
2927 struct intel_crtc_scaler_state *scaler_state;
2928 int i;
2929
2930 if (!intel_crtc || !intel_crtc->config)
2931 return;
2932
2933 dev = intel_crtc->base.dev;
2934 dev_priv = dev->dev_private;
2935 scaler_state = &intel_crtc->config->scaler_state;
2936
2937 /* loop through and disable scalers that aren't in use */
2938 for (i = 0; i < intel_crtc->num_scalers; i++) {
2939 if (!scaler_state->scalers[i].in_use) {
2940 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0);
2941 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0);
2942 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0);
2943 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2944 intel_crtc->base.base.id, intel_crtc->pipe, i);
2945 }
2946 }
2947}
2948
6156a456 2949u32 skl_plane_ctl_format(uint32_t pixel_format)
70d21f0e 2950{
6156a456 2951 switch (pixel_format) {
d161cf7a 2952 case DRM_FORMAT_C8:
c34ce3d1 2953 return PLANE_CTL_FORMAT_INDEXED;
70d21f0e 2954 case DRM_FORMAT_RGB565:
c34ce3d1 2955 return PLANE_CTL_FORMAT_RGB_565;
70d21f0e 2956 case DRM_FORMAT_XBGR8888:
c34ce3d1 2957 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
6156a456 2958 case DRM_FORMAT_XRGB8888:
c34ce3d1 2959 return PLANE_CTL_FORMAT_XRGB_8888;
6156a456
CK		 2960 /*
2961 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2962 * to be already pre-multiplied. We need to add a knob (or a different
2963 * DRM_FORMAT) for user-space to configure that.
2964 */
f75fb42a 2965 case DRM_FORMAT_ABGR8888:
c34ce3d1 2966 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
6156a456 2967 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
6156a456 2968 case DRM_FORMAT_ARGB8888:
c34ce3d1 2969 return PLANE_CTL_FORMAT_XRGB_8888 |
6156a456 2970 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
70d21f0e 2971 case DRM_FORMAT_XRGB2101010:
c34ce3d1 2972 return PLANE_CTL_FORMAT_XRGB_2101010;
70d21f0e 2973 case DRM_FORMAT_XBGR2101010:
c34ce3d1 2974 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
6156a456 2975 case DRM_FORMAT_YUYV:
c34ce3d1 2976 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
6156a456 2977 case DRM_FORMAT_YVYU:
c34ce3d1 2978 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
6156a456 2979 case DRM_FORMAT_UYVY:
c34ce3d1 2980 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
6156a456 2981 case DRM_FORMAT_VYUY:
c34ce3d1 2982 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
70d21f0e 2983 default:
4249eeef 2984 MISSING_CASE(pixel_format);
70d21f0e 2985 }
8cfcba41 2986
c34ce3d1 2987 return 0;
6156a456 2988}
70d21f0e 2989
6156a456
CK		 2990u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2991{
6156a456 2992 switch (fb_modifier) {
30af77c4 2993 case DRM_FORMAT_MOD_NONE:
70d21f0e 2994 break;
30af77c4 2995 case I915_FORMAT_MOD_X_TILED:
c34ce3d1 2996 return PLANE_CTL_TILED_X;
b321803d 2997 case I915_FORMAT_MOD_Y_TILED:
c34ce3d1 2998 return PLANE_CTL_TILED_Y;
b321803d 2999 case I915_FORMAT_MOD_Yf_TILED:
c34ce3d1 3000 return PLANE_CTL_TILED_YF;
70d21f0e 3001 default:
6156a456 3002 MISSING_CASE(fb_modifier);
70d21f0e 3003 }
8cfcba41 3004
c34ce3d1 3005 return 0;
6156a456 3006}
70d21f0e 3007
6156a456
CK		 3008u32 skl_plane_ctl_rotation(unsigned int rotation)
3009{
3b7a5119 3010 switch (rotation) {
6156a456
CK		 3011 case BIT(DRM_ROTATE_0):
3012 break;
1e8df167
SJ		 3013 /*
3014 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3015 * while i915 HW rotation is clockwise, thats why this swapping.
3016 */
3b7a5119 3017 case BIT(DRM_ROTATE_90):
1e8df167 3018 return PLANE_CTL_ROTATE_270;
3b7a5119 3019 case BIT(DRM_ROTATE_180):
c34ce3d1 3020 return PLANE_CTL_ROTATE_180;
3b7a5119 3021 case BIT(DRM_ROTATE_270):
1e8df167 3022 return PLANE_CTL_ROTATE_90;
6156a456
CK		 3023 default:
3024 MISSING_CASE(rotation);
3025 }
3026
c34ce3d1 3027 return 0;
6156a456
CK		 3028}
3029
3030static void skylake_update_primary_plane(struct drm_crtc *crtc,
3031 struct drm_framebuffer *fb,
3032 int x, int y)
3033{
3034 struct drm_device *dev = crtc->dev;
3035 struct drm_i915_private *dev_priv = dev->dev_private;
3036 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 3037 struct drm_plane *plane = crtc->primary;
3038 bool visible = to_intel_plane_state(plane->state)->visible;
6156a456
CK		 3039 struct drm_i915_gem_object *obj;
3040 int pipe = intel_crtc->pipe;
3041 u32 plane_ctl, stride_div, stride;
3042 u32 tile_height, plane_offset, plane_size;
3043 unsigned int rotation;
3044 int x_offset, y_offset;
3045 unsigned long surf_addr;
6156a456
CK		 3046 struct intel_crtc_state *crtc_state = intel_crtc->config;
3047 struct intel_plane_state *plane_state;
3048 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3049 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3050 int scaler_id = -1;
3051
6156a456
CK		 3052 plane_state = to_intel_plane_state(plane->state);
3053
b70709a6 3054 if (!visible || !fb) {
6156a456
CK		 3055 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3056 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3057 POSTING_READ(PLANE_CTL(pipe, 0));
3058 return;
3b7a5119 3059 }
70d21f0e 3060
6156a456
CK		 3061 plane_ctl = PLANE_CTL_ENABLE |
3062 PLANE_CTL_PIPE_GAMMA_ENABLE |
3063 PLANE_CTL_PIPE_CSC_ENABLE;
3064
3065 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3066 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3067 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3068
3069 rotation = plane->state->rotation;
3070 plane_ctl |= skl_plane_ctl_rotation(rotation);
3071
b321803d
DL		 3072 obj = intel_fb_obj(fb);
3073 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3074 fb->pixel_format);
3b7a5119
SJ		 3075 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3076
6156a456
CK		 3077 /*
3078 * FIXME: intel_plane_state->src, dst aren't set when transitional
3079 * update_plane helpers are called from legacy paths.
3080 * Once full atomic crtc is available, below check can be avoided.
3081 */
3082 if (drm_rect_width(&plane_state->src)) {
3083 scaler_id = plane_state->scaler_id;
3084 src_x = plane_state->src.x1 >> 16;
3085 src_y = plane_state->src.y1 >> 16;
3086 src_w = drm_rect_width(&plane_state->src) >> 16;
3087 src_h = drm_rect_height(&plane_state->src) >> 16;
3088 dst_x = plane_state->dst.x1;
3089 dst_y = plane_state->dst.y1;
3090 dst_w = drm_rect_width(&plane_state->dst);
3091 dst_h = drm_rect_height(&plane_state->dst);
3092
3093 WARN_ON(x != src_x || y != src_y);
3094 } else {
3095 src_w = intel_crtc->config->pipe_src_w;
3096 src_h = intel_crtc->config->pipe_src_h;
3097 }
3098
3b7a5119
SJ		 3099 if (intel_rotation_90_or_270(rotation)) {
3100 /* stride = Surface height in tiles */
2614f17d 3101 tile_height = intel_tile_height(dev, fb->pixel_format,
3b7a5119
SJ		 3102 fb->modifier[0]);
3103 stride = DIV_ROUND_UP(fb->height, tile_height);
6156a456 3104 x_offset = stride * tile_height - y - src_h;
3b7a5119 3105 y_offset = x;
6156a456 3106 plane_size = (src_w - 1) << 16 | (src_h - 1);
3b7a5119
SJ		 3107 } else {
3108 stride = fb->pitches[0] / stride_div;
3109 x_offset = x;
3110 y_offset = y;
6156a456 3111 plane_size = (src_h - 1) << 16 | (src_w - 1);
3b7a5119
SJ		 3112 }
3113 plane_offset = y_offset << 16 | x_offset;
b321803d 3114
70d21f0e 3115 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3b7a5119
SJ		 3116 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3117 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3118 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
6156a456
CK		 3119
3120 if (scaler_id >= 0) {
3121 uint32_t ps_ctrl = 0;
3122
3123 WARN_ON(!dst_w || !dst_h);
3124 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3125 crtc_state->scaler_state.scalers[scaler_id].mode;
3126 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3127 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3128 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3129 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3130 I915_WRITE(PLANE_POS(pipe, 0), 0);
3131 } else {
3132 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3133 }
3134
121920fa 3135 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
70d21f0e
DL		 3136
3137 POSTING_READ(PLANE_SURF(pipe, 0));
3138}
3139
17638cd6
JB		 3140/* Assume fb object is pinned & idle & fenced and just update base pointers */
3141static int
3142intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3143 int x, int y, enum mode_set_atomic state)
3144{
3145 struct drm_device *dev = crtc->dev;
3146 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 3147
6b8e6ed0
CW		 3148 if (dev_priv->display.disable_fbc)
3149 dev_priv->display.disable_fbc(dev);
81255565 3150
29b9bde6
DV		 3151 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3152
3153 return 0;
81255565
JB		 3154}
3155
7514747d 3156static void intel_complete_page_flips(struct drm_device *dev)
96a02917 3157{
96a02917
VS		 3158 struct drm_crtc *crtc;
3159
70e1e0ec 3160 for_each_crtc(dev, crtc) {
96a02917
VS		 3161 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3162 enum plane plane = intel_crtc->plane;
3163
3164 intel_prepare_page_flip(dev, plane);
3165 intel_finish_page_flip_plane(dev, plane);
3166 }
7514747d
VS		 3167}
3168
3169static void intel_update_primary_planes(struct drm_device *dev)
3170{
3171 struct drm_i915_private *dev_priv = dev->dev_private;
3172 struct drm_crtc *crtc;
96a02917 3173
70e1e0ec 3174 for_each_crtc(dev, crtc) {
96a02917
VS		 3175 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3176
51fd371b 3177 drm_modeset_lock(&crtc->mutex, NULL);
947fdaad
CW		 3178 /*
3179 * FIXME: Once we have proper support for primary planes (and
3180 * disabling them without disabling the entire crtc) allow again
66e514c1 3181 * a NULL crtc->primary->fb.
947fdaad 3182 */
f4510a27 3183 if (intel_crtc->active && crtc->primary->fb)
262ca2b0 3184 dev_priv->display.update_primary_plane(crtc,
66e514c1 3185 crtc->primary->fb,
262ca2b0
MR		 3186 crtc->x,
3187 crtc->y);
51fd371b 3188 drm_modeset_unlock(&crtc->mutex);
96a02917
VS		 3189 }
3190}
3191
ce22dba9
ML		 3192void intel_crtc_reset(struct intel_crtc *crtc)
3193{
3194 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3195
3196 if (!crtc->active)
3197 return;
3198
3199 intel_crtc_disable_planes(&crtc->base);
3200 dev_priv->display.crtc_disable(&crtc->base);
3201 dev_priv->display.crtc_enable(&crtc->base);
3202 intel_crtc_enable_planes(&crtc->base);
3203}
3204
7514747d
VS		 3205void intel_prepare_reset(struct drm_device *dev)
3206{
f98ce92f
VS		 3207 struct drm_i915_private *dev_priv = to_i915(dev);
3208 struct intel_crtc *crtc;
3209
7514747d
VS		 3210 /* no reset support for gen2 */
3211 if (IS_GEN2(dev))
3212 return;
3213
3214 /* reset doesn't touch the display */
3215 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3216 return;
3217
3218 drm_modeset_lock_all(dev);
f98ce92f
VS		 3219
3220 /*
3221 * Disabling the crtcs gracefully seems nicer. Also the
3222 * g33 docs say we should at least disable all the planes.
3223 */
3224 for_each_intel_crtc(dev, crtc) {
ce22dba9
ML		 3225 if (!crtc->active)
3226 continue;
3227
3228 intel_crtc_disable_planes(&crtc->base);
3229 dev_priv->display.crtc_disable(&crtc->base);
f98ce92f 3230 }
7514747d
VS		 3231}
3232
3233void intel_finish_reset(struct drm_device *dev)
3234{
3235 struct drm_i915_private *dev_priv = to_i915(dev);
3236
3237 /*
3238 * Flips in the rings will be nuked by the reset,
3239 * so complete all pending flips so that user space
3240 * will get its events and not get stuck.
3241 */
3242 intel_complete_page_flips(dev);
3243
3244 /* no reset support for gen2 */
3245 if (IS_GEN2(dev))
3246 return;
3247
3248 /* reset doesn't touch the display */
3249 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3250 /*
3251 * Flips in the rings have been nuked by the reset,
3252 * so update the base address of all primary
3253 * planes to the the last fb to make sure we're
3254 * showing the correct fb after a reset.
3255 */
3256 intel_update_primary_planes(dev);
3257 return;
3258 }
3259
3260 /*
3261 * The display has been reset as well,
3262 * so need a full re-initialization.
3263 */
3264 intel_runtime_pm_disable_interrupts(dev_priv);
3265 intel_runtime_pm_enable_interrupts(dev_priv);
3266
3267 intel_modeset_init_hw(dev);
3268
3269 spin_lock_irq(&dev_priv->irq_lock);
3270 if (dev_priv->display.hpd_irq_setup)
3271 dev_priv->display.hpd_irq_setup(dev);
3272 spin_unlock_irq(&dev_priv->irq_lock);
3273
3274 intel_modeset_setup_hw_state(dev, true);
3275
3276 intel_hpd_init(dev_priv);
3277
3278 drm_modeset_unlock_all(dev);
3279}
3280
2e2f351d 3281static void
14667a4b
CW		 3282intel_finish_fb(struct drm_framebuffer *old_fb)
3283{
2ff8fde1 3284 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2e2f351d 3285 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
14667a4b
CW		 3286 bool was_interruptible = dev_priv->mm.interruptible;
3287 int ret;
3288
14667a4b
CW		 3289 /* Big Hammer, we also need to ensure that any pending
3290 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3291 * current scanout is retired before unpinning the old
2e2f351d
CW		 3292 * framebuffer. Note that we rely on userspace rendering
3293 * into the buffer attached to the pipe they are waiting
3294 * on. If not, userspace generates a GPU hang with IPEHR
3295 * point to the MI_WAIT_FOR_EVENT.
14667a4b
CW		 3296 *
3297 * This should only fail upon a hung GPU, in which case we
3298 * can safely continue.
3299 */
3300 dev_priv->mm.interruptible = false;
2e2f351d 3301 ret = i915_gem_object_wait_rendering(obj, true);
14667a4b
CW		 3302 dev_priv->mm.interruptible = was_interruptible;
3303
2e2f351d 3304 WARN_ON(ret);
14667a4b
CW		 3305}
3306
7d5e3799
CW		 3307static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3308{
3309 struct drm_device *dev = crtc->dev;
3310 struct drm_i915_private *dev_priv = dev->dev_private;
3311 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7d5e3799
CW		 3312 bool pending;
3313
3314 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3315 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3316 return false;
3317
5e2d7afc 3318 spin_lock_irq(&dev->event_lock);
7d5e3799 3319 pending = to_intel_crtc(crtc)->unpin_work != NULL;
5e2d7afc 3320 spin_unlock_irq(&dev->event_lock);
7d5e3799
CW		 3321
3322 return pending;
3323}
3324
e30e8f75
GP		 3325static void intel_update_pipe_size(struct intel_crtc *crtc)
3326{
3327 struct drm_device *dev = crtc->base.dev;
3328 struct drm_i915_private *dev_priv = dev->dev_private;
3329 const struct drm_display_mode *adjusted_mode;
3330
3331 if (!i915.fastboot)
3332 return;
3333
3334 /*
3335 * Update pipe size and adjust fitter if needed: the reason for this is
3336 * that in compute_mode_changes we check the native mode (not the pfit
3337 * mode) to see if we can flip rather than do a full mode set. In the
3338 * fastboot case, we'll flip, but if we don't update the pipesrc and
3339 * pfit state, we'll end up with a big fb scanned out into the wrong
3340 * sized surface.
3341 *
3342 * To fix this properly, we need to hoist the checks up into
3343 * compute_mode_changes (or above), check the actual pfit state and
3344 * whether the platform allows pfit disable with pipe active, and only
3345 * then update the pipesrc and pfit state, even on the flip path.
3346 */
3347
6e3c9717 3348 adjusted_mode = &crtc->config->base.adjusted_mode;
e30e8f75
GP		 3349
3350 I915_WRITE(PIPESRC(crtc->pipe),
3351 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3352 (adjusted_mode->crtc_vdisplay - 1));
6e3c9717 3353 if (!crtc->config->pch_pfit.enabled &&
409ee761
ACO		 3354 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3355 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
e30e8f75
GP		 3356 I915_WRITE(PF_CTL(crtc->pipe), 0);
3357 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3358 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3359 }
6e3c9717
ACO		 3360 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3361 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
e30e8f75
GP		 3362}
3363
5e84e1a4
ZW		 3364static void intel_fdi_normal_train(struct drm_crtc *crtc)
3365{
3366 struct drm_device *dev = crtc->dev;
3367 struct drm_i915_private *dev_priv = dev->dev_private;
3368 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3369 int pipe = intel_crtc->pipe;
3370 u32 reg, temp;
3371
3372 /* enable normal train */
3373 reg = FDI_TX_CTL(pipe);
3374 temp = I915_READ(reg);
61e499bf 3375 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 3376 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3377 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 3378 } else {
3379 temp &= ~FDI_LINK_TRAIN_NONE;
3380 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 3381 }
5e84e1a4
ZW		 3382 I915_WRITE(reg, temp);
3383
3384 reg = FDI_RX_CTL(pipe);
3385 temp = I915_READ(reg);
3386 if (HAS_PCH_CPT(dev)) {
3387 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3388 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3389 } else {
3390 temp &= ~FDI_LINK_TRAIN_NONE;
3391 temp |= FDI_LINK_TRAIN_NONE;
3392 }
3393 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3394
3395 /* wait one idle pattern time */
3396 POSTING_READ(reg);
3397 udelay(1000);
357555c0
JB		 3398
3399 /* IVB wants error correction enabled */
3400 if (IS_IVYBRIDGE(dev))
3401 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3402 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 3403}
3404
8db9d77b
ZW		 3405/* The FDI link training functions for ILK/Ibexpeak. */
3406static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3407{
3408 struct drm_device *dev = crtc->dev;
3409 struct drm_i915_private *dev_priv = dev->dev_private;
3410 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3411 int pipe = intel_crtc->pipe;
5eddb70b 3412 u32 reg, temp, tries;
8db9d77b 3413
1c8562f6 3414 /* FDI needs bits from pipe first */
0fc932b8 3415 assert_pipe_enabled(dev_priv, pipe);
0fc932b8 3416
e1a44743
AJ		 3417 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3418 for train result */
5eddb70b
CW		 3419 reg = FDI_RX_IMR(pipe);
3420 temp = I915_READ(reg);
e1a44743
AJ		 3421 temp &= ~FDI_RX_SYMBOL_LOCK;
3422 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3423 I915_WRITE(reg, temp);
3424 I915_READ(reg);
e1a44743
AJ		 3425 udelay(150);
3426
8db9d77b 3427 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3428 reg = FDI_TX_CTL(pipe);
3429 temp = I915_READ(reg);
627eb5a3 3430 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3431 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3432 temp &= ~FDI_LINK_TRAIN_NONE;
3433 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 3434 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3435
5eddb70b
CW		 3436 reg = FDI_RX_CTL(pipe);
3437 temp = I915_READ(reg);
8db9d77b
ZW		 3438 temp &= ~FDI_LINK_TRAIN_NONE;
3439 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 3440 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3441
3442 POSTING_READ(reg);
8db9d77b
ZW		 3443 udelay(150);
3444
5b2adf89 3445 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 3446 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3447 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3448 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 3449
5eddb70b 3450 reg = FDI_RX_IIR(pipe);
e1a44743 3451 for (tries = 0; tries < 5; tries++) {
5eddb70b 3452 temp = I915_READ(reg);
8db9d77b
ZW		 3453 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3454
3455 if ((temp & FDI_RX_BIT_LOCK)) {
3456 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 3457 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 3458 break;
3459 }
8db9d77b 3460 }
e1a44743 3461 if (tries == 5)
5eddb70b 3462 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3463
3464 /* Train 2 */
5eddb70b
CW		 3465 reg = FDI_TX_CTL(pipe);
3466 temp = I915_READ(reg);
8db9d77b
ZW		 3467 temp &= ~FDI_LINK_TRAIN_NONE;
3468 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3469 I915_WRITE(reg, temp);
8db9d77b 3470
5eddb70b
CW		 3471 reg = FDI_RX_CTL(pipe);
3472 temp = I915_READ(reg);
8db9d77b
ZW		 3473 temp &= ~FDI_LINK_TRAIN_NONE;
3474 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3475 I915_WRITE(reg, temp);
8db9d77b 3476
5eddb70b
CW		 3477 POSTING_READ(reg);
3478 udelay(150);
8db9d77b 3479
5eddb70b 3480 reg = FDI_RX_IIR(pipe);
e1a44743 3481 for (tries = 0; tries < 5; tries++) {
5eddb70b 3482 temp = I915_READ(reg);
8db9d77b
ZW		 3483 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3484
3485 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 3486 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 3487 DRM_DEBUG_KMS("FDI train 2 done.\n");
3488 break;
3489 }
8db9d77b 3490 }
e1a44743 3491 if (tries == 5)
5eddb70b 3492 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3493
3494 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 3495
8db9d77b
ZW		 3496}
3497
0206e353 3498static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 3499 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3500 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3501 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3502 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3503};
3504
3505/* The FDI link training functions for SNB/Cougarpoint. */
3506static void gen6_fdi_link_train(struct drm_crtc *crtc)
3507{
3508 struct drm_device *dev = crtc->dev;
3509 struct drm_i915_private *dev_priv = dev->dev_private;
3510 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3511 int pipe = intel_crtc->pipe;
fa37d39e 3512 u32 reg, temp, i, retry;
8db9d77b 3513
e1a44743
AJ		 3514 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3515 for train result */
5eddb70b
CW		 3516 reg = FDI_RX_IMR(pipe);
3517 temp = I915_READ(reg);
e1a44743
AJ		 3518 temp &= ~FDI_RX_SYMBOL_LOCK;
3519 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3520 I915_WRITE(reg, temp);
3521
3522 POSTING_READ(reg);
e1a44743
AJ		 3523 udelay(150);
3524
8db9d77b 3525 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3526 reg = FDI_TX_CTL(pipe);
3527 temp = I915_READ(reg);
627eb5a3 3528 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3529 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3530 temp &= ~FDI_LINK_TRAIN_NONE;
3531 temp |= FDI_LINK_TRAIN_PATTERN_1;
3532 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3533 /* SNB-B */
3534 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 3535 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3536
d74cf324
DV		 3537 I915_WRITE(FDI_RX_MISC(pipe),
3538 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3539
5eddb70b
CW		 3540 reg = FDI_RX_CTL(pipe);
3541 temp = I915_READ(reg);
8db9d77b
ZW		 3542 if (HAS_PCH_CPT(dev)) {
3543 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3544 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3545 } else {
3546 temp &= ~FDI_LINK_TRAIN_NONE;
3547 temp |= FDI_LINK_TRAIN_PATTERN_1;
3548 }
5eddb70b
CW		 3549 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3550
3551 POSTING_READ(reg);
8db9d77b
ZW		 3552 udelay(150);
3553
0206e353 3554 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3555 reg = FDI_TX_CTL(pipe);
3556 temp = I915_READ(reg);
8db9d77b
ZW		 3557 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3558 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3559 I915_WRITE(reg, temp);
3560
3561 POSTING_READ(reg);
8db9d77b
ZW		 3562 udelay(500);
3563
fa37d39e
SP		 3564 for (retry = 0; retry < 5; retry++) {
3565 reg = FDI_RX_IIR(pipe);
3566 temp = I915_READ(reg);
3567 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3568 if (temp & FDI_RX_BIT_LOCK) {
3569 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3570 DRM_DEBUG_KMS("FDI train 1 done.\n");
3571 break;
3572 }
3573 udelay(50);
8db9d77b 3574 }
fa37d39e
SP		 3575 if (retry < 5)
3576 break;
8db9d77b
ZW		 3577 }
3578 if (i == 4)
5eddb70b 3579 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3580
3581 /* Train 2 */
5eddb70b
CW		 3582 reg = FDI_TX_CTL(pipe);
3583 temp = I915_READ(reg);
8db9d77b
ZW		 3584 temp &= ~FDI_LINK_TRAIN_NONE;
3585 temp |= FDI_LINK_TRAIN_PATTERN_2;
3586 if (IS_GEN6(dev)) {
3587 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3588 /* SNB-B */
3589 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3590 }
5eddb70b 3591 I915_WRITE(reg, temp);
8db9d77b 3592
5eddb70b
CW		 3593 reg = FDI_RX_CTL(pipe);
3594 temp = I915_READ(reg);
8db9d77b
ZW		 3595 if (HAS_PCH_CPT(dev)) {
3596 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3597 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3598 } else {
3599 temp &= ~FDI_LINK_TRAIN_NONE;
3600 temp |= FDI_LINK_TRAIN_PATTERN_2;
3601 }
5eddb70b
CW		 3602 I915_WRITE(reg, temp);
3603
3604 POSTING_READ(reg);
8db9d77b
ZW		 3605 udelay(150);
3606
0206e353 3607 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3608 reg = FDI_TX_CTL(pipe);
3609 temp = I915_READ(reg);
8db9d77b
ZW		 3610 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3611 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3612 I915_WRITE(reg, temp);
3613
3614 POSTING_READ(reg);
8db9d77b
ZW		 3615 udelay(500);
3616
fa37d39e
SP		 3617 for (retry = 0; retry < 5; retry++) {
3618 reg = FDI_RX_IIR(pipe);
3619 temp = I915_READ(reg);
3620 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3621 if (temp & FDI_RX_SYMBOL_LOCK) {
3622 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3623 DRM_DEBUG_KMS("FDI train 2 done.\n");
3624 break;
3625 }
3626 udelay(50);
8db9d77b 3627 }
fa37d39e
SP		 3628 if (retry < 5)
3629 break;
8db9d77b
ZW		 3630 }
3631 if (i == 4)
5eddb70b 3632 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3633
3634 DRM_DEBUG_KMS("FDI train done.\n");
3635}
3636
357555c0
JB		 3637/* Manual link training for Ivy Bridge A0 parts */
3638static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3639{
3640 struct drm_device *dev = crtc->dev;
3641 struct drm_i915_private *dev_priv = dev->dev_private;
3642 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3643 int pipe = intel_crtc->pipe;
139ccd3f 3644 u32 reg, temp, i, j;
357555c0
JB		 3645
3646 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3647 for train result */
3648 reg = FDI_RX_IMR(pipe);
3649 temp = I915_READ(reg);
3650 temp &= ~FDI_RX_SYMBOL_LOCK;
3651 temp &= ~FDI_RX_BIT_LOCK;
3652 I915_WRITE(reg, temp);
3653
3654 POSTING_READ(reg);
3655 udelay(150);
3656
01a415fd
DV		 3657 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3658 I915_READ(FDI_RX_IIR(pipe)));
3659
139ccd3f
JB		 3660 /* Try each vswing and preemphasis setting twice before moving on */
3661 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3662 /* disable first in case we need to retry */
3663 reg = FDI_TX_CTL(pipe);
3664 temp = I915_READ(reg);
3665 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3666 temp &= ~FDI_TX_ENABLE;
3667 I915_WRITE(reg, temp);
357555c0 3668
139ccd3f
JB		 3669 reg = FDI_RX_CTL(pipe);
3670 temp = I915_READ(reg);
3671 temp &= ~FDI_LINK_TRAIN_AUTO;
3672 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3673 temp &= ~FDI_RX_ENABLE;
3674 I915_WRITE(reg, temp);
357555c0 3675
139ccd3f 3676 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 3677 reg = FDI_TX_CTL(pipe);
3678 temp = I915_READ(reg);
139ccd3f 3679 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3680 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
139ccd3f 3681 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 3682 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 3683 temp |= snb_b_fdi_train_param[j/2];
3684 temp |= FDI_COMPOSITE_SYNC;
3685 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 3686
139ccd3f
JB		 3687 I915_WRITE(FDI_RX_MISC(pipe),
3688 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 3689
139ccd3f 3690 reg = FDI_RX_CTL(pipe);
357555c0 3691 temp = I915_READ(reg);
139ccd3f
JB		 3692 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3693 temp |= FDI_COMPOSITE_SYNC;
3694 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 3695
139ccd3f
JB		 3696 POSTING_READ(reg);
3697 udelay(1); /* should be 0.5us */
357555c0 3698
139ccd3f
JB		 3699 for (i = 0; i < 4; i++) {
3700 reg = FDI_RX_IIR(pipe);
3701 temp = I915_READ(reg);
3702 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3703
139ccd3f
JB		 3704 if (temp & FDI_RX_BIT_LOCK ||
3705 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3706 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3707 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3708 i);
3709 break;
3710 }
3711 udelay(1); /* should be 0.5us */
3712 }
3713 if (i == 4) {
3714 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3715 continue;
3716 }
357555c0 3717
139ccd3f 3718 /* Train 2 */
357555c0
JB		 3719 reg = FDI_TX_CTL(pipe);
3720 temp = I915_READ(reg);
139ccd3f
JB		 3721 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3722 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3723 I915_WRITE(reg, temp);
3724
3725 reg = FDI_RX_CTL(pipe);
3726 temp = I915_READ(reg);
3727 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3728 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 3729 I915_WRITE(reg, temp);
3730
3731 POSTING_READ(reg);
139ccd3f 3732 udelay(2); /* should be 1.5us */
357555c0 3733
139ccd3f
JB		 3734 for (i = 0; i < 4; i++) {
3735 reg = FDI_RX_IIR(pipe);
3736 temp = I915_READ(reg);
3737 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3738
139ccd3f
JB		 3739 if (temp & FDI_RX_SYMBOL_LOCK ||
3740 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3741 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3742 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3743 i);
3744 goto train_done;
3745 }
3746 udelay(2); /* should be 1.5us */
357555c0 3747 }
139ccd3f
JB		 3748 if (i == 4)
3749 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 3750 }
357555c0 3751
139ccd3f 3752train_done:
357555c0
JB		 3753 DRM_DEBUG_KMS("FDI train done.\n");
3754}
3755
88cefb6c 3756static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 3757{
88cefb6c 3758 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 3759 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 3760 int pipe = intel_crtc->pipe;
5eddb70b 3761 u32 reg, temp;
79e53945 3762
c64e311e 3763
c98e9dcf 3764 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 3765 reg = FDI_RX_CTL(pipe);
3766 temp = I915_READ(reg);
627eb5a3 3767 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
6e3c9717 3768 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
dfd07d72 3769 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 3770 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3771
3772 POSTING_READ(reg);
c98e9dcf
JB		 3773 udelay(200);
3774
3775 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 3776 temp = I915_READ(reg);
3777 I915_WRITE(reg, temp | FDI_PCDCLK);
3778
3779 POSTING_READ(reg);
c98e9dcf
JB		 3780 udelay(200);
3781
20749730
PZ		 3782 /* Enable CPU FDI TX PLL, always on for Ironlake */
3783 reg = FDI_TX_CTL(pipe);
3784 temp = I915_READ(reg);
3785 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3786 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 3787
20749730
PZ		 3788 POSTING_READ(reg);
3789 udelay(100);
6be4a607 3790 }
0e23b99d
JB		 3791}
3792
88cefb6c
DV		 3793static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3794{
3795 struct drm_device *dev = intel_crtc->base.dev;
3796 struct drm_i915_private *dev_priv = dev->dev_private;
3797 int pipe = intel_crtc->pipe;
3798 u32 reg, temp;
3799
3800 /* Switch from PCDclk to Rawclk */
3801 reg = FDI_RX_CTL(pipe);
3802 temp = I915_READ(reg);
3803 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3804
3805 /* Disable CPU FDI TX PLL */
3806 reg = FDI_TX_CTL(pipe);
3807 temp = I915_READ(reg);
3808 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3809
3810 POSTING_READ(reg);
3811 udelay(100);
3812
3813 reg = FDI_RX_CTL(pipe);
3814 temp = I915_READ(reg);
3815 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3816
3817 /* Wait for the clocks to turn off. */
3818 POSTING_READ(reg);
3819 udelay(100);
3820}
3821
0fc932b8
JB		 3822static void ironlake_fdi_disable(struct drm_crtc *crtc)
3823{
3824 struct drm_device *dev = crtc->dev;
3825 struct drm_i915_private *dev_priv = dev->dev_private;
3826 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3827 int pipe = intel_crtc->pipe;
3828 u32 reg, temp;
3829
3830 /* disable CPU FDI tx and PCH FDI rx */
3831 reg = FDI_TX_CTL(pipe);
3832 temp = I915_READ(reg);
3833 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3834 POSTING_READ(reg);
3835
3836 reg = FDI_RX_CTL(pipe);
3837 temp = I915_READ(reg);
3838 temp &= ~(0x7 << 16);
dfd07d72 3839 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3840 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3841
3842 POSTING_READ(reg);
3843 udelay(100);
3844
3845 /* Ironlake workaround, disable clock pointer after downing FDI */
eba905b2 3846 if (HAS_PCH_IBX(dev))
6f06ce18 3847 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 3848
3849 /* still set train pattern 1 */
3850 reg = FDI_TX_CTL(pipe);
3851 temp = I915_READ(reg);
3852 temp &= ~FDI_LINK_TRAIN_NONE;
3853 temp |= FDI_LINK_TRAIN_PATTERN_1;
3854 I915_WRITE(reg, temp);
3855
3856 reg = FDI_RX_CTL(pipe);
3857 temp = I915_READ(reg);
3858 if (HAS_PCH_CPT(dev)) {
3859 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3860 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3861 } else {
3862 temp &= ~FDI_LINK_TRAIN_NONE;
3863 temp |= FDI_LINK_TRAIN_PATTERN_1;
3864 }
3865 /* BPC in FDI rx is consistent with that in PIPECONF */
3866 temp &= ~(0x07 << 16);
dfd07d72 3867 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3868 I915_WRITE(reg, temp);
3869
3870 POSTING_READ(reg);
3871 udelay(100);
3872}
3873
5dce5b93
CW		 3874bool intel_has_pending_fb_unpin(struct drm_device *dev)
3875{
3876 struct intel_crtc *crtc;
3877
3878 /* Note that we don't need to be called with mode_config.lock here
3879 * as our list of CRTC objects is static for the lifetime of the
3880 * device and so cannot disappear as we iterate. Similarly, we can
3881 * happily treat the predicates as racy, atomic checks as userspace
3882 * cannot claim and pin a new fb without at least acquring the
3883 * struct_mutex and so serialising with us.
3884 */
d3fcc808 3885 for_each_intel_crtc(dev, crtc) {
5dce5b93
CW		 3886 if (atomic_read(&crtc->unpin_work_count) == 0)
3887 continue;
3888
3889 if (crtc->unpin_work)
3890 intel_wait_for_vblank(dev, crtc->pipe);
3891
3892 return true;
3893 }
3894
3895 return false;
3896}
3897
d6bbafa1
CW		 3898static void page_flip_completed(struct intel_crtc *intel_crtc)
3899{
3900 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3901 struct intel_unpin_work *work = intel_crtc->unpin_work;
3902
3903 /* ensure that the unpin work is consistent wrt ->pending. */
3904 smp_rmb();
3905 intel_crtc->unpin_work = NULL;
3906
3907 if (work->event)
3908 drm_send_vblank_event(intel_crtc->base.dev,
3909 intel_crtc->pipe,
3910 work->event);
3911
3912 drm_crtc_vblank_put(&intel_crtc->base);
3913
3914 wake_up_all(&dev_priv->pending_flip_queue);
3915 queue_work(dev_priv->wq, &work->work);
3916
3917 trace_i915_flip_complete(intel_crtc->plane,
3918 work->pending_flip_obj);
3919}
3920
46a55d30 3921void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
e6c3a2a6 3922{
0f91128d 3923 struct drm_device *dev = crtc->dev;
5bb61643 3924 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6 3925
2c10d571 3926 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
9c787942
CW		 3927 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3928 !intel_crtc_has_pending_flip(crtc),
3929 60*HZ) == 0)) {
3930 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2c10d571 3931
5e2d7afc 3932 spin_lock_irq(&dev->event_lock);
9c787942
CW		 3933 if (intel_crtc->unpin_work) {
3934 WARN_ONCE(1, "Removing stuck page flip\n");
3935 page_flip_completed(intel_crtc);
3936 }
5e2d7afc 3937 spin_unlock_irq(&dev->event_lock);
9c787942 3938 }
5bb61643 3939
975d568a
CW		 3940 if (crtc->primary->fb) {
3941 mutex_lock(&dev->struct_mutex);
3942 intel_finish_fb(crtc->primary->fb);
3943 mutex_unlock(&dev->struct_mutex);
3944 }
e6c3a2a6
CW		 3945}
3946
e615efe4
ED		 3947/* Program iCLKIP clock to the desired frequency */
3948static void lpt_program_iclkip(struct drm_crtc *crtc)
3949{
3950 struct drm_device *dev = crtc->dev;
3951 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3952 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
e615efe4
ED		 3953 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3954 u32 temp;
3955
09153000
DV		 3956 mutex_lock(&dev_priv->dpio_lock);
3957
e615efe4
ED		 3958 /* It is necessary to ungate the pixclk gate prior to programming
3959 * the divisors, and gate it back when it is done.
3960 */
3961 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3962
3963 /* Disable SSCCTL */
3964 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 3965 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3966 SBI_SSCCTL_DISABLE,
3967 SBI_ICLK);
e615efe4
ED		 3968
3969 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 3970 if (clock == 20000) {
e615efe4
ED		 3971 auxdiv = 1;
3972 divsel = 0x41;
3973 phaseinc = 0x20;
3974 } else {
3975 /* The iCLK virtual clock root frequency is in MHz,
241bfc38
DL		 3976 * but the adjusted_mode->crtc_clock in in KHz. To get the
3977 * divisors, it is necessary to divide one by another, so we
e615efe4
ED		 3978 * convert the virtual clock precision to KHz here for higher
3979 * precision.
3980 */
3981 u32 iclk_virtual_root_freq = 172800 * 1000;
3982 u32 iclk_pi_range = 64;
3983 u32 desired_divisor, msb_divisor_value, pi_value;
3984
12d7ceed 3985 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 3986 msb_divisor_value = desired_divisor / iclk_pi_range;
3987 pi_value = desired_divisor % iclk_pi_range;
3988
3989 auxdiv = 0;
3990 divsel = msb_divisor_value - 2;
3991 phaseinc = pi_value;
3992 }
3993
3994 /* This should not happen with any sane values */
3995 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3996 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3997 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3998 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3999
4000 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 4001 clock,
e615efe4
ED		 4002 auxdiv,
4003 divsel,
4004 phasedir,
4005 phaseinc);
4006
4007 /* Program SSCDIVINTPHASE6 */
988d6ee8 4008 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 4009 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4010 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4011 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4012 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4013 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4014 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 4015 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 4016
4017 /* Program SSCAUXDIV */
988d6ee8 4018 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 4019 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4020 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 4021 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 4022
4023 /* Enable modulator and associated divider */
988d6ee8 4024 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 4025 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 4026 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 4027
4028 /* Wait for initialization time */
4029 udelay(24);
4030
4031 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 4032
4033 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 4034}
4035
275f01b2
DV		 4036static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4037 enum pipe pch_transcoder)
4038{
4039 struct drm_device *dev = crtc->base.dev;
4040 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 4041 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
275f01b2
DV		 4042
4043 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4044 I915_READ(HTOTAL(cpu_transcoder)));
4045 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4046 I915_READ(HBLANK(cpu_transcoder)));
4047 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4048 I915_READ(HSYNC(cpu_transcoder)));
4049
4050 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4051 I915_READ(VTOTAL(cpu_transcoder)));
4052 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4053 I915_READ(VBLANK(cpu_transcoder)));
4054 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4055 I915_READ(VSYNC(cpu_transcoder)));
4056 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4057 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4058}
4059
003632d9 4060static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
1fbc0d78
DV		 4061{
4062 struct drm_i915_private *dev_priv = dev->dev_private;
4063 uint32_t temp;
4064
4065 temp = I915_READ(SOUTH_CHICKEN1);
003632d9 4066 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
1fbc0d78
DV		 4067 return;
4068
4069 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4070 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4071
003632d9
ACO		 4072 temp &= ~FDI_BC_BIFURCATION_SELECT;
4073 if (enable)
4074 temp |= FDI_BC_BIFURCATION_SELECT;
4075
4076 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
1fbc0d78
DV		 4077 I915_WRITE(SOUTH_CHICKEN1, temp);
4078 POSTING_READ(SOUTH_CHICKEN1);
4079}
4080
4081static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4082{
4083 struct drm_device *dev = intel_crtc->base.dev;
1fbc0d78
DV		 4084
4085 switch (intel_crtc->pipe) {
4086 case PIPE_A:
4087 break;
4088 case PIPE_B:
6e3c9717 4089 if (intel_crtc->config->fdi_lanes > 2)
003632d9 4090 cpt_set_fdi_bc_bifurcation(dev, false);
1fbc0d78 4091 else
003632d9 4092 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4093
4094 break;
4095 case PIPE_C:
003632d9 4096 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4097
4098 break;
4099 default:
4100 BUG();
4101 }
4102}
4103
f67a559d
JB		 4104/*
4105 * Enable PCH resources required for PCH ports:
4106 * - PCH PLLs
4107 * - FDI training & RX/TX
4108 * - update transcoder timings
4109 * - DP transcoding bits
4110 * - transcoder
4111 */
4112static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 4113{
4114 struct drm_device *dev = crtc->dev;
4115 struct drm_i915_private *dev_priv = dev->dev_private;
4116 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4117 int pipe = intel_crtc->pipe;
ee7b9f93 4118 u32 reg, temp;
2c07245f 4119
ab9412ba 4120 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 4121
1fbc0d78
DV		 4122 if (IS_IVYBRIDGE(dev))
4123 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4124
cd986abb
DV		 4125 /* Write the TU size bits before fdi link training, so that error
4126 * detection works. */
4127 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4128 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4129
c98e9dcf 4130 /* For PCH output, training FDI link */
674cf967 4131 dev_priv->display.fdi_link_train(crtc);
2c07245f 4132
3ad8a208
DV		 4133 /* We need to program the right clock selection before writing the pixel
4134 * mutliplier into the DPLL. */
303b81e0 4135 if (HAS_PCH_CPT(dev)) {
ee7b9f93 4136 u32 sel;
4b645f14 4137
c98e9dcf 4138 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 4139 temp |= TRANS_DPLL_ENABLE(pipe);
4140 sel = TRANS_DPLLB_SEL(pipe);
6e3c9717 4141 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 4142 temp |= sel;
4143 else
4144 temp &= ~sel;
c98e9dcf 4145 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 4146 }
5eddb70b 4147
3ad8a208
DV		 4148 /* XXX: pch pll's can be enabled any time before we enable the PCH
4149 * transcoder, and we actually should do this to not upset any PCH
4150 * transcoder that already use the clock when we share it.
4151 *
4152 * Note that enable_shared_dpll tries to do the right thing, but
4153 * get_shared_dpll unconditionally resets the pll - we need that to have
4154 * the right LVDS enable sequence. */
85b3894f 4155 intel_enable_shared_dpll(intel_crtc);
3ad8a208 4156
d9b6cb56
JB		 4157 /* set transcoder timing, panel must allow it */
4158 assert_panel_unlocked(dev_priv, pipe);
275f01b2 4159 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 4160
303b81e0 4161 intel_fdi_normal_train(crtc);
5e84e1a4 4162
c98e9dcf 4163 /* For PCH DP, enable TRANS_DP_CTL */
6e3c9717 4164 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
dfd07d72 4165 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 4166 reg = TRANS_DP_CTL(pipe);
4167 temp = I915_READ(reg);
4168 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 4169 TRANS_DP_SYNC_MASK |
4170 TRANS_DP_BPC_MASK);
5eddb70b
CW		 4171 temp |= (TRANS_DP_OUTPUT_ENABLE |
4172 TRANS_DP_ENH_FRAMING);
9325c9f0 4173 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 4174
4175 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 4176 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 4177 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 4178 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 4179
4180 switch (intel_trans_dp_port_sel(crtc)) {
4181 case PCH_DP_B:
5eddb70b 4182 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 4183 break;
4184 case PCH_DP_C:
5eddb70b 4185 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 4186 break;
4187 case PCH_DP_D:
5eddb70b 4188 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 4189 break;
4190 default:
e95d41e1 4191 BUG();
32f9d658 4192 }
2c07245f 4193
5eddb70b 4194 I915_WRITE(reg, temp);
6be4a607 4195 }
b52eb4dc 4196
b8a4f404 4197 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 4198}
4199
1507e5bd
PZ		 4200static void lpt_pch_enable(struct drm_crtc *crtc)
4201{
4202 struct drm_device *dev = crtc->dev;
4203 struct drm_i915_private *dev_priv = dev->dev_private;
4204 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 4205 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1507e5bd 4206
ab9412ba 4207 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 4208
8c52b5e8 4209 lpt_program_iclkip(crtc);
1507e5bd 4210
0540e488 4211 /* Set transcoder timing. */
275f01b2 4212 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 4213
937bb610 4214 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 4215}
4216
716c2e55 4217void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 4218{
e2b78267 4219 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 4220
4221 if (pll == NULL)
4222 return;
4223
3e369b76 4224 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
1e6f2ddc 4225 WARN(1, "bad %s crtc mask\n", pll->name);
ee7b9f93
JB		 4226 return;
4227 }
4228
3e369b76
ACO		 4229 pll->config.crtc_mask &= ~(1 << crtc->pipe);
4230 if (pll->config.crtc_mask == 0) {
f4a091c7
DV		 4231 WARN_ON(pll->on);
4232 WARN_ON(pll->active);
4233 }
4234
6e3c9717 4235 crtc->config->shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 4236}
4237
190f68c5
ACO		 4238struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4239 struct intel_crtc_state *crtc_state)
ee7b9f93 4240{
e2b78267 4241 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8bd31e67 4242 struct intel_shared_dpll *pll;
e2b78267 4243 enum intel_dpll_id i;
ee7b9f93 4244
98b6bd99
DV		 4245 if (HAS_PCH_IBX(dev_priv->dev)) {
4246 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 4247 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 4248 pll = &dev_priv->shared_dplls[i];
98b6bd99 4249
46edb027
DV		 4250 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4251 crtc->base.base.id, pll->name);
98b6bd99 4252
8bd31e67 4253 WARN_ON(pll->new_config->crtc_mask);
f2a69f44 4254
98b6bd99
DV		 4255 goto found;
4256 }
4257
bcddf610
S		 4258 if (IS_BROXTON(dev_priv->dev)) {
4259 /* PLL is attached to port in bxt */
4260 struct intel_encoder *encoder;
4261 struct intel_digital_port *intel_dig_port;
4262
4263 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4264 if (WARN_ON(!encoder))
4265 return NULL;
4266
4267 intel_dig_port = enc_to_dig_port(&encoder->base);
4268 /* 1:1 mapping between ports and PLLs */
4269 i = (enum intel_dpll_id)intel_dig_port->port;
4270 pll = &dev_priv->shared_dplls[i];
4271 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4272 crtc->base.base.id, pll->name);
4273 WARN_ON(pll->new_config->crtc_mask);
4274
4275 goto found;
4276 }
4277
e72f9fbf
DV		 4278 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4279 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 4280
4281 /* Only want to check enabled timings first */
8bd31e67 4282 if (pll->new_config->crtc_mask == 0)
ee7b9f93
JB		 4283 continue;
4284
190f68c5 4285 if (memcmp(&crtc_state->dpll_hw_state,
8bd31e67
ACO		 4286 &pll->new_config->hw_state,
4287 sizeof(pll->new_config->hw_state)) == 0) {
4288 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
1e6f2ddc 4289 crtc->base.base.id, pll->name,
8bd31e67
ACO		 4290 pll->new_config->crtc_mask,
4291 pll->active);
ee7b9f93
JB		 4292 goto found;
4293 }
4294 }
4295
4296 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 4297 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4298 pll = &dev_priv->shared_dplls[i];
8bd31e67 4299 if (pll->new_config->crtc_mask == 0) {
46edb027
DV		 4300 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4301 crtc->base.base.id, pll->name);
ee7b9f93
JB		 4302 goto found;
4303 }
4304 }
4305
4306 return NULL;
4307
4308found:
8bd31e67 4309 if (pll->new_config->crtc_mask == 0)
190f68c5 4310 pll->new_config->hw_state = crtc_state->dpll_hw_state;
f2a69f44 4311
190f68c5 4312 crtc_state->shared_dpll = i;
46edb027
DV		 4313 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4314 pipe_name(crtc->pipe));
ee7b9f93 4315
8bd31e67 4316 pll->new_config->crtc_mask |= 1 << crtc->pipe;
e04c7350 4317
ee7b9f93
JB		 4318 return pll;
4319}
4320
8bd31e67
ACO		 4321/**
4322 * intel_shared_dpll_start_config - start a new PLL staged config
4323 * @dev_priv: DRM device
4324 * @clear_pipes: mask of pipes that will have their PLLs freed
4325 *
4326 * Starts a new PLL staged config, copying the current config but
4327 * releasing the references of pipes specified in clear_pipes.
4328 */
4329static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4330 unsigned clear_pipes)
4331{
4332 struct intel_shared_dpll *pll;
4333 enum intel_dpll_id i;
4334
4335 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4336 pll = &dev_priv->shared_dplls[i];
4337
4338 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4339 GFP_KERNEL);
4340 if (!pll->new_config)
4341 goto cleanup;
4342
4343 pll->new_config->crtc_mask &= ~clear_pipes;
4344 }
4345
4346 return 0;
4347
4348cleanup:
4349 while (--i >= 0) {
4350 pll = &dev_priv->shared_dplls[i];
f354d733 4351 kfree(pll->new_config);
8bd31e67
ACO		 4352 pll->new_config = NULL;
4353 }
4354
4355 return -ENOMEM;
4356}
4357
4358static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4359{
4360 struct intel_shared_dpll *pll;
4361 enum intel_dpll_id i;
4362
4363 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4364 pll = &dev_priv->shared_dplls[i];
4365
4366 WARN_ON(pll->new_config == &pll->config);
4367
4368 pll->config = *pll->new_config;
4369 kfree(pll->new_config);
4370 pll->new_config = NULL;
4371 }
4372}
4373
4374static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4375{
4376 struct intel_shared_dpll *pll;
4377 enum intel_dpll_id i;
4378
4379 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4380 pll = &dev_priv->shared_dplls[i];
4381
4382 WARN_ON(pll->new_config == &pll->config);
4383
4384 kfree(pll->new_config);
4385 pll->new_config = NULL;
4386 }
4387}
4388
a1520318 4389static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 4390{
4391 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 4392 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 4393 u32 temp;
4394
4395 temp = I915_READ(dslreg);
4396 udelay(500);
4397 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 4398 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 4399 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 4400 }
4401}
4402
a1b2278e
CK		 4403/**
4404 * skl_update_scaler_users - Stages update to crtc's scaler state
4405 * @intel_crtc: crtc
4406 * @crtc_state: crtc_state
4407 * @plane: plane (NULL indicates crtc is requesting update)
4408 * @plane_state: plane's state
4409 * @force_detach: request unconditional detachment of scaler
4410 *
4411 * This function updates scaler state for requested plane or crtc.
4412 * To request scaler usage update for a plane, caller shall pass plane pointer.
4413 * To request scaler usage update for crtc, caller shall pass plane pointer
4414 * as NULL.
4415 *
4416 * Return
4417 * 0 - scaler_usage updated successfully
4418 * error - requested scaling cannot be supported or other error condition
4419 */
4420int
4421skl_update_scaler_users(
4422 struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state,
4423 struct intel_plane *intel_plane, struct intel_plane_state *plane_state,
4424 int force_detach)
4425{
4426 int need_scaling;
4427 int idx;
4428 int src_w, src_h, dst_w, dst_h;
4429 int *scaler_id;
4430 struct drm_framebuffer *fb;
4431 struct intel_crtc_scaler_state *scaler_state;
6156a456 4432 unsigned int rotation;
a1b2278e
CK		 4433
4434 if (!intel_crtc || !crtc_state)
4435 return 0;
4436
4437 scaler_state = &crtc_state->scaler_state;
4438
4439 idx = intel_plane ? drm_plane_index(&intel_plane->base) : SKL_CRTC_INDEX;
4440 fb = intel_plane ? plane_state->base.fb : NULL;
4441
4442 if (intel_plane) {
4443 src_w = drm_rect_width(&plane_state->src) >> 16;
4444 src_h = drm_rect_height(&plane_state->src) >> 16;
4445 dst_w = drm_rect_width(&plane_state->dst);
4446 dst_h = drm_rect_height(&plane_state->dst);
4447 scaler_id = &plane_state->scaler_id;
6156a456 4448 rotation = plane_state->base.rotation;
a1b2278e
CK		 4449 } else {
4450 struct drm_display_mode *adjusted_mode =
4451 &crtc_state->base.adjusted_mode;
4452 src_w = crtc_state->pipe_src_w;
4453 src_h = crtc_state->pipe_src_h;
4454 dst_w = adjusted_mode->hdisplay;
4455 dst_h = adjusted_mode->vdisplay;
4456 scaler_id = &scaler_state->scaler_id;
6156a456 4457 rotation = DRM_ROTATE_0;
a1b2278e 4458 }
6156a456
CK		 4459
4460 need_scaling = intel_rotation_90_or_270(rotation) ?
4461 (src_h != dst_w || src_w != dst_h):
4462 (src_w != dst_w || src_h != dst_h);
a1b2278e
CK		 4463
4464 /*
4465 * if plane is being disabled or scaler is no more required or force detach
4466 * - free scaler binded to this plane/crtc
4467 * - in order to do this, update crtc->scaler_usage
4468 *
4469 * Here scaler state in crtc_state is set free so that
4470 * scaler can be assigned to other user. Actual register
4471 * update to free the scaler is done in plane/panel-fit programming.
4472 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4473 */
4474 if (force_detach || !need_scaling || (intel_plane &&
4475 (!fb || !plane_state->visible))) {
4476 if (*scaler_id >= 0) {
4477 scaler_state->scaler_users &= ~(1 << idx);
4478 scaler_state->scalers[*scaler_id].in_use = 0;
4479
4480 DRM_DEBUG_KMS("Staged freeing scaler id %d.%d from %s:%d "
4481 "crtc_state = %p scaler_users = 0x%x\n",
4482 intel_crtc->pipe, *scaler_id, intel_plane ? "PLANE" : "CRTC",
4483 intel_plane ? intel_plane->base.base.id :
4484 intel_crtc->base.base.id, crtc_state,
4485 scaler_state->scaler_users);
4486 *scaler_id = -1;
4487 }
4488 return 0;
4489 }
4490
4491 /* range checks */
4492 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4493 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4494
4495 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4496 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4497 DRM_DEBUG_KMS("%s:%d scaler_user index %u.%u: src %ux%u dst %ux%u "
4498 "size is out of scaler range\n",
4499 intel_plane ? "PLANE" : "CRTC",
4500 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4501 intel_crtc->pipe, idx, src_w, src_h, dst_w, dst_h);
4502 return -EINVAL;
4503 }
4504
4505 /* check colorkey */
4506 if (intel_plane && intel_plane->ckey.flags != I915_SET_COLORKEY_NONE) {
4507 DRM_DEBUG_KMS("PLANE:%d scaling with color key not allowed",
4508 intel_plane->base.base.id);
4509 return -EINVAL;
4510 }
4511
4512 /* Check src format */
4513 if (intel_plane) {
4514 switch (fb->pixel_format) {
4515 case DRM_FORMAT_RGB565:
4516 case DRM_FORMAT_XBGR8888:
4517 case DRM_FORMAT_XRGB8888:
4518 case DRM_FORMAT_ABGR8888:
4519 case DRM_FORMAT_ARGB8888:
4520 case DRM_FORMAT_XRGB2101010:
a1b2278e 4521 case DRM_FORMAT_XBGR2101010:
a1b2278e
CK		 4522 case DRM_FORMAT_YUYV:
4523 case DRM_FORMAT_YVYU:
4524 case DRM_FORMAT_UYVY:
4525 case DRM_FORMAT_VYUY:
4526 break;
4527 default:
4528 DRM_DEBUG_KMS("PLANE:%d FB:%d unsupported scaling format 0x%x\n",
4529 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4530 return -EINVAL;
4531 }
4532 }
4533
4534 /* mark this plane as a scaler user in crtc_state */
4535 scaler_state->scaler_users |= (1 << idx);
4536 DRM_DEBUG_KMS("%s:%d staged scaling request for %ux%u->%ux%u "
4537 "crtc_state = %p scaler_users = 0x%x\n",
4538 intel_plane ? "PLANE" : "CRTC",
4539 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4540 src_w, src_h, dst_w, dst_h, crtc_state, scaler_state->scaler_users);
4541 return 0;
4542}
4543
4544static void skylake_pfit_update(struct intel_crtc *crtc, int enable)
bd2e244f
JB		 4545{
4546 struct drm_device *dev = crtc->base.dev;
4547 struct drm_i915_private *dev_priv = dev->dev_private;
4548 int pipe = crtc->pipe;
a1b2278e
CK		 4549 struct intel_crtc_scaler_state *scaler_state =
4550 &crtc->config->scaler_state;
4551
4552 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4553
4554 /* To update pfit, first update scaler state */
4555 skl_update_scaler_users(crtc, crtc->config, NULL, NULL, !enable);
4556 intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config);
4557 skl_detach_scalers(crtc);
4558 if (!enable)
4559 return;
bd2e244f 4560
6e3c9717 4561 if (crtc->config->pch_pfit.enabled) {
a1b2278e
CK		 4562 int id;
4563
4564 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4565 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4566 return;
4567 }
4568
4569 id = scaler_state->scaler_id;
4570 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4571 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4572 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4573 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4574
4575 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
bd2e244f
JB		 4576 }
4577}
4578
b074cec8
JB		 4579static void ironlake_pfit_enable(struct intel_crtc *crtc)
4580{
4581 struct drm_device *dev = crtc->base.dev;
4582 struct drm_i915_private *dev_priv = dev->dev_private;
4583 int pipe = crtc->pipe;
4584
6e3c9717 4585 if (crtc->config->pch_pfit.enabled) {
b074cec8
JB		 4586 /* Force use of hard-coded filter coefficients
4587 * as some pre-programmed values are broken,
4588 * e.g. x201.
4589 */
4590 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4591 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4592 PF_PIPE_SEL_IVB(pipe));
4593 else
4594 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
6e3c9717
ACO		 4595 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4596 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
d4270e57
JB		 4597 }
4598}
4599
4a3b8769 4600static void intel_enable_sprite_planes(struct drm_crtc *crtc)
bb53d4ae
VS		 4601{
4602 struct drm_device *dev = crtc->dev;
4603 enum pipe pipe = to_intel_crtc(crtc)->pipe;
af2b653b 4604 struct drm_plane *plane;
bb53d4ae
VS		 4605 struct intel_plane *intel_plane;
4606
af2b653b
MR		 4607 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4608 intel_plane = to_intel_plane(plane);
bb53d4ae
VS		 4609 if (intel_plane->pipe == pipe)
4610 intel_plane_restore(&intel_plane->base);
af2b653b 4611 }
bb53d4ae
VS		 4612}
4613
20bc8673 4614void hsw_enable_ips(struct intel_crtc *crtc)
d77e4531 4615{
cea165c3
VS		 4616 struct drm_device *dev = crtc->base.dev;
4617 struct drm_i915_private *dev_priv = dev->dev_private;
d77e4531 4618
6e3c9717 4619 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4620 return;
4621
cea165c3
VS		 4622 /* We can only enable IPS after we enable a plane and wait for a vblank */
4623 intel_wait_for_vblank(dev, crtc->pipe);
4624
d77e4531 4625 assert_plane_enabled(dev_priv, crtc->plane);
cea165c3 4626 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4627 mutex_lock(&dev_priv->rps.hw_lock);
4628 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4629 mutex_unlock(&dev_priv->rps.hw_lock);
4630 /* Quoting Art Runyan: "its not safe to expect any particular
4631 * value in IPS_CTL bit 31 after enabling IPS through the
e59150dc
JB		 4632 * mailbox." Moreover, the mailbox may return a bogus state,
4633 * so we need to just enable it and continue on.
2a114cc1
BW		 4634 */
4635 } else {
4636 I915_WRITE(IPS_CTL, IPS_ENABLE);
4637 /* The bit only becomes 1 in the next vblank, so this wait here
4638 * is essentially intel_wait_for_vblank. If we don't have this
4639 * and don't wait for vblanks until the end of crtc_enable, then
4640 * the HW state readout code will complain that the expected
4641 * IPS_CTL value is not the one we read. */
4642 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4643 DRM_ERROR("Timed out waiting for IPS enable\n");
4644 }
d77e4531
PZ		 4645}
4646
20bc8673 4647void hsw_disable_ips(struct intel_crtc *crtc)
d77e4531
PZ		 4648{
4649 struct drm_device *dev = crtc->base.dev;
4650 struct drm_i915_private *dev_priv = dev->dev_private;
4651
6e3c9717 4652 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4653 return;
4654
4655 assert_plane_enabled(dev_priv, crtc->plane);
23d0b130 4656 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4657 mutex_lock(&dev_priv->rps.hw_lock);
4658 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4659 mutex_unlock(&dev_priv->rps.hw_lock);
23d0b130
BW		 4660 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4661 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4662 DRM_ERROR("Timed out waiting for IPS disable\n");
e59150dc 4663 } else {
2a114cc1 4664 I915_WRITE(IPS_CTL, 0);
e59150dc
JB		 4665 POSTING_READ(IPS_CTL);
4666 }
d77e4531
PZ		 4667
4668 /* We need to wait for a vblank before we can disable the plane. */
4669 intel_wait_for_vblank(dev, crtc->pipe);
4670}
4671
4672/** Loads the palette/gamma unit for the CRTC with the prepared values */
4673static void intel_crtc_load_lut(struct drm_crtc *crtc)
4674{
4675 struct drm_device *dev = crtc->dev;
4676 struct drm_i915_private *dev_priv = dev->dev_private;
4677 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4678 enum pipe pipe = intel_crtc->pipe;
4679 int palreg = PALETTE(pipe);
4680 int i;
4681 bool reenable_ips = false;
4682
4683 /* The clocks have to be on to load the palette. */
83d65738 4684 if (!crtc->state->enable || !intel_crtc->active)
d77e4531
PZ		 4685 return;
4686
50360403 4687 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
409ee761 4688 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
d77e4531
PZ		 4689 assert_dsi_pll_enabled(dev_priv);
4690 else
4691 assert_pll_enabled(dev_priv, pipe);
4692 }
4693
4694 /* use legacy palette for Ironlake */
7a1db49a 4695 if (!HAS_GMCH_DISPLAY(dev))
d77e4531
PZ		 4696 palreg = LGC_PALETTE(pipe);
4697
4698 /* Workaround : Do not read or write the pipe palette/gamma data while
4699 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4700 */
6e3c9717 4701 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
d77e4531
PZ		 4702 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4703 GAMMA_MODE_MODE_SPLIT)) {
4704 hsw_disable_ips(intel_crtc);
4705 reenable_ips = true;
4706 }
4707
4708 for (i = 0; i < 256; i++) {
4709 I915_WRITE(palreg + 4 * i,
4710 (intel_crtc->lut_r[i] << 16) |
4711 (intel_crtc->lut_g[i] << 8) |
4712 intel_crtc->lut_b[i]);
4713 }
4714
4715 if (reenable_ips)
4716 hsw_enable_ips(intel_crtc);
4717}
4718
7cac945f 4719static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
d3eedb1a 4720{
7cac945f 4721 if (intel_crtc->overlay) {
d3eedb1a
VS		 4722 struct drm_device *dev = intel_crtc->base.dev;
4723 struct drm_i915_private *dev_priv = dev->dev_private;
4724
4725 mutex_lock(&dev->struct_mutex);
4726 dev_priv->mm.interruptible = false;
4727 (void) intel_overlay_switch_off(intel_crtc->overlay);
4728 dev_priv->mm.interruptible = true;
4729 mutex_unlock(&dev->struct_mutex);
4730 }
4731
4732 /* Let userspace switch the overlay on again. In most cases userspace
4733 * has to recompute where to put it anyway.
4734 */
4735}
4736
87d4300a
ML		 4737/**
4738 * intel_post_enable_primary - Perform operations after enabling primary plane
4739 * @crtc: the CRTC whose primary plane was just enabled
4740 *
4741 * Performs potentially sleeping operations that must be done after the primary
4742 * plane is enabled, such as updating FBC and IPS. Note that this may be
4743 * called due to an explicit primary plane update, or due to an implicit
4744 * re-enable that is caused when a sprite plane is updated to no longer
4745 * completely hide the primary plane.
4746 */
4747static void
4748intel_post_enable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4749{
4750 struct drm_device *dev = crtc->dev;
87d4300a 4751 struct drm_i915_private *dev_priv = dev->dev_private;
a5c4d7bc
VS		 4752 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4753 int pipe = intel_crtc->pipe;
a5c4d7bc 4754
87d4300a
ML		 4755 /*
4756 * BDW signals flip done immediately if the plane
4757 * is disabled, even if the plane enable is already
4758 * armed to occur at the next vblank :(
4759 */
4760 if (IS_BROADWELL(dev))
4761 intel_wait_for_vblank(dev, pipe);
a5c4d7bc 4762
87d4300a
ML		 4763 /*
4764 * FIXME IPS should be fine as long as one plane is
4765 * enabled, but in practice it seems to have problems
4766 * when going from primary only to sprite only and vice
4767 * versa.
4768 */
a5c4d7bc
VS		 4769 hsw_enable_ips(intel_crtc);
4770
4771 mutex_lock(&dev->struct_mutex);
7ff0ebcc 4772 intel_fbc_update(dev);
a5c4d7bc 4773 mutex_unlock(&dev->struct_mutex);
f99d7069
DV		 4774
4775 /*
87d4300a
ML		 4776 * Gen2 reports pipe underruns whenever all planes are disabled.
4777 * So don't enable underrun reporting before at least some planes
4778 * are enabled.
4779 * FIXME: Need to fix the logic to work when we turn off all planes
4780 * but leave the pipe running.
f99d7069 4781 */
87d4300a
ML		 4782 if (IS_GEN2(dev))
4783 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4784
4785 /* Underruns don't raise interrupts, so check manually. */
4786 if (HAS_GMCH_DISPLAY(dev))
4787 i9xx_check_fifo_underruns(dev_priv);
a5c4d7bc
VS		 4788}
4789
87d4300a
ML		 4790/**
4791 * intel_pre_disable_primary - Perform operations before disabling primary plane
4792 * @crtc: the CRTC whose primary plane is to be disabled
4793 *
4794 * Performs potentially sleeping operations that must be done before the
4795 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4796 * be called due to an explicit primary plane update, or due to an implicit
4797 * disable that is caused when a sprite plane completely hides the primary
4798 * plane.
4799 */
4800static void
4801intel_pre_disable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4802{
4803 struct drm_device *dev = crtc->dev;
4804 struct drm_i915_private *dev_priv = dev->dev_private;
4805 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4806 int pipe = intel_crtc->pipe;
a5c4d7bc 4807
87d4300a
ML		 4808 /*
4809 * Gen2 reports pipe underruns whenever all planes are disabled.
4810 * So diasble underrun reporting before all the planes get disabled.
4811 * FIXME: Need to fix the logic to work when we turn off all planes
4812 * but leave the pipe running.
4813 */
4814 if (IS_GEN2(dev))
4815 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
a5c4d7bc 4816
87d4300a
ML		 4817 /*
4818 * Vblank time updates from the shadow to live plane control register
4819 * are blocked if the memory self-refresh mode is active at that
4820 * moment. So to make sure the plane gets truly disabled, disable
4821 * first the self-refresh mode. The self-refresh enable bit in turn
4822 * will be checked/applied by the HW only at the next frame start
4823 * event which is after the vblank start event, so we need to have a
4824 * wait-for-vblank between disabling the plane and the pipe.
4825 */
4826 if (HAS_GMCH_DISPLAY(dev))
4827 intel_set_memory_cxsr(dev_priv, false);
4828
4829 mutex_lock(&dev->struct_mutex);
e35fef21 4830 if (dev_priv->fbc.crtc == intel_crtc)
7ff0ebcc 4831 intel_fbc_disable(dev);
87d4300a 4832 mutex_unlock(&dev->struct_mutex);
a5c4d7bc 4833
87d4300a
ML		 4834 /*
4835 * FIXME IPS should be fine as long as one plane is
4836 * enabled, but in practice it seems to have problems
4837 * when going from primary only to sprite only and vice
4838 * versa.
4839 */
a5c4d7bc 4840 hsw_disable_ips(intel_crtc);
87d4300a
ML		 4841}
4842
4843static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4844{
87d4300a
ML		 4845 intel_enable_primary_hw_plane(crtc->primary, crtc);
4846 intel_enable_sprite_planes(crtc);
4847 intel_crtc_update_cursor(crtc, true);
87d4300a
ML		 4848
4849 intel_post_enable_primary(crtc);
4850}
4851
4852static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4853{
4854 struct drm_device *dev = crtc->dev;
4855 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4856 struct intel_plane *intel_plane;
4857 int pipe = intel_crtc->pipe;
4858
4859 intel_crtc_wait_for_pending_flips(crtc);
4860
4861 intel_pre_disable_primary(crtc);
a5c4d7bc 4862
7cac945f 4863 intel_crtc_dpms_overlay_disable(intel_crtc);
27321ae8
ML		 4864 for_each_intel_plane(dev, intel_plane) {
4865 if (intel_plane->pipe == pipe) {
4866 struct drm_crtc *from = intel_plane->base.crtc;
4867
4868 intel_plane->disable_plane(&intel_plane->base,
4869 from ?: crtc, true);
4870 }
4871 }
f98551ae 4872
f99d7069
DV		 4873 /*
4874 * FIXME: Once we grow proper nuclear flip support out of this we need
4875 * to compute the mask of flip planes precisely. For the time being
4876 * consider this a flip to a NULL plane.
4877 */
4878 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
a5c4d7bc
VS		 4879}
4880
f67a559d
JB		 4881static void ironlake_crtc_enable(struct drm_crtc *crtc)
4882{
4883 struct drm_device *dev = crtc->dev;
4884 struct drm_i915_private *dev_priv = dev->dev_private;
4885 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4886 struct intel_encoder *encoder;
f67a559d 4887 int pipe = intel_crtc->pipe;
f67a559d 4888
83d65738 4889 WARN_ON(!crtc->state->enable);
08a48469 4890
f67a559d
JB		 4891 if (intel_crtc->active)
4892 return;
4893
6e3c9717 4894 if (intel_crtc->config->has_pch_encoder)
b14b1055
DV		 4895 intel_prepare_shared_dpll(intel_crtc);
4896
6e3c9717 4897 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4898 intel_dp_set_m_n(intel_crtc, M1_N1);
29407aab
DV		 4899
4900 intel_set_pipe_timings(intel_crtc);
4901
6e3c9717 4902 if (intel_crtc->config->has_pch_encoder) {
29407aab 4903 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4904 &intel_crtc->config->fdi_m_n, NULL);
29407aab
DV		 4905 }
4906
4907 ironlake_set_pipeconf(crtc);
4908
f67a559d 4909 intel_crtc->active = true;
8664281b 4910
a72e4c9f
DV		 4911 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4912 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
8664281b 4913
f6736a1a 4914 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 4915 if (encoder->pre_enable)
4916 encoder->pre_enable(encoder);
f67a559d 4917
6e3c9717 4918 if (intel_crtc->config->has_pch_encoder) {
fff367c7
DV		 4919 /* Note: FDI PLL enabling _must_ be done before we enable the
4920 * cpu pipes, hence this is separate from all the other fdi/pch
4921 * enabling. */
88cefb6c 4922 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 4923 } else {
4924 assert_fdi_tx_disabled(dev_priv, pipe);
4925 assert_fdi_rx_disabled(dev_priv, pipe);
4926 }
f67a559d 4927
b074cec8 4928 ironlake_pfit_enable(intel_crtc);
f67a559d 4929
9c54c0dd
JB		 4930 /*
4931 * On ILK+ LUT must be loaded before the pipe is running but with
4932 * clocks enabled
4933 */
4934 intel_crtc_load_lut(crtc);
4935
f37fcc2a 4936 intel_update_watermarks(crtc);
e1fdc473 4937 intel_enable_pipe(intel_crtc);
f67a559d 4938
6e3c9717 4939 if (intel_crtc->config->has_pch_encoder)
f67a559d 4940 ironlake_pch_enable(crtc);
c98e9dcf 4941
f9b61ff6
DV		 4942 assert_vblank_disabled(crtc);
4943 drm_crtc_vblank_on(crtc);
4944
fa5c73b1
DV		 4945 for_each_encoder_on_crtc(dev, crtc, encoder)
4946 encoder->enable(encoder);
61b77ddd
DV		 4947
4948 if (HAS_PCH_CPT(dev))
a1520318 4949 cpt_verify_modeset(dev, intel_crtc->pipe);
6be4a607
JB		 4950}
4951
42db64ef
PZ		 4952/* IPS only exists on ULT machines and is tied to pipe A. */
4953static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4954{
f5adf94e 4955 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 4956}
4957
e4916946
PZ		 4958/*
4959 * This implements the workaround described in the "notes" section of the mode
4960 * set sequence documentation. When going from no pipes or single pipe to
4961 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4962 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4963 */
4964static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4965{
4966 struct drm_device *dev = crtc->base.dev;
4967 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4968
4969 /* We want to get the other_active_crtc only if there's only 1 other
4970 * active crtc. */
d3fcc808 4971 for_each_intel_crtc(dev, crtc_it) {
e4916946
PZ		 4972 if (!crtc_it->active || crtc_it == crtc)
4973 continue;
4974
4975 if (other_active_crtc)
4976 return;
4977
4978 other_active_crtc = crtc_it;
4979 }
4980 if (!other_active_crtc)
4981 return;
4982
4983 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4984 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4985}
4986
4f771f10
PZ		 4987static void haswell_crtc_enable(struct drm_crtc *crtc)
4988{
4989 struct drm_device *dev = crtc->dev;
4990 struct drm_i915_private *dev_priv = dev->dev_private;
4991 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4992 struct intel_encoder *encoder;
4993 int pipe = intel_crtc->pipe;
4f771f10 4994
83d65738 4995 WARN_ON(!crtc->state->enable);
4f771f10
PZ		 4996
4997 if (intel_crtc->active)
4998 return;
4999
df8ad70c
DV		 5000 if (intel_crtc_to_shared_dpll(intel_crtc))
5001 intel_enable_shared_dpll(intel_crtc);
5002
6e3c9717 5003 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 5004 intel_dp_set_m_n(intel_crtc, M1_N1);
229fca97
DV		 5005
5006 intel_set_pipe_timings(intel_crtc);
5007
6e3c9717
ACO		 5008 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
5009 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
5010 intel_crtc->config->pixel_multiplier - 1);
ebb69c95
CT		 5011 }
5012
6e3c9717 5013 if (intel_crtc->config->has_pch_encoder) {
229fca97 5014 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 5015 &intel_crtc->config->fdi_m_n, NULL);
229fca97
DV		 5016 }
5017
5018 haswell_set_pipeconf(crtc);
5019
5020 intel_set_pipe_csc(crtc);
5021
4f771f10 5022 intel_crtc->active = true;
8664281b 5023
a72e4c9f 5024 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4f771f10
PZ		 5025 for_each_encoder_on_crtc(dev, crtc, encoder)
5026 if (encoder->pre_enable)
5027 encoder->pre_enable(encoder);
5028
6e3c9717 5029 if (intel_crtc->config->has_pch_encoder) {
a72e4c9f
DV		 5030 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5031 true);
4fe9467d
ID		 5032 dev_priv->display.fdi_link_train(crtc);
5033 }
5034
1f544388 5035 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 5036
ff6d9f55 5037 if (INTEL_INFO(dev)->gen == 9)
a1b2278e 5038 skylake_pfit_update(intel_crtc, 1);
ff6d9f55 5039 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 5040 ironlake_pfit_enable(intel_crtc);
ff6d9f55
JB		 5041 else
5042 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10
PZ		 5043
5044 /*
5045 * On ILK+ LUT must be loaded before the pipe is running but with
5046 * clocks enabled
5047 */
5048 intel_crtc_load_lut(crtc);
5049
1f544388 5050 intel_ddi_set_pipe_settings(crtc);
8228c251 5051 intel_ddi_enable_transcoder_func(crtc);
4f771f10 5052
f37fcc2a 5053 intel_update_watermarks(crtc);
e1fdc473 5054 intel_enable_pipe(intel_crtc);
42db64ef 5055
6e3c9717 5056 if (intel_crtc->config->has_pch_encoder)
1507e5bd 5057 lpt_pch_enable(crtc);
4f771f10 5058
6e3c9717 5059 if (intel_crtc->config->dp_encoder_is_mst)
0e32b39c
DA		 5060 intel_ddi_set_vc_payload_alloc(crtc, true);
5061
f9b61ff6
DV		 5062 assert_vblank_disabled(crtc);
5063 drm_crtc_vblank_on(crtc);
5064
8807e55b 5065 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 5066 encoder->enable(encoder);
8807e55b
JN		 5067 intel_opregion_notify_encoder(encoder, true);
5068 }
4f771f10 5069
e4916946
PZ		 5070 /* If we change the relative order between pipe/planes enabling, we need
5071 * to change the workaround. */
5072 haswell_mode_set_planes_workaround(intel_crtc);
4f771f10
PZ		 5073}
5074
3f8dce3a
DV		 5075static void ironlake_pfit_disable(struct intel_crtc *crtc)
5076{
5077 struct drm_device *dev = crtc->base.dev;
5078 struct drm_i915_private *dev_priv = dev->dev_private;
5079 int pipe = crtc->pipe;
5080
5081 /* To avoid upsetting the power well on haswell only disable the pfit if
5082 * it's in use. The hw state code will make sure we get this right. */
6e3c9717 5083 if (crtc->config->pch_pfit.enabled) {
3f8dce3a
DV		 5084 I915_WRITE(PF_CTL(pipe), 0);
5085 I915_WRITE(PF_WIN_POS(pipe), 0);
5086 I915_WRITE(PF_WIN_SZ(pipe), 0);
5087 }
5088}
5089
6be4a607
JB		 5090static void ironlake_crtc_disable(struct drm_crtc *crtc)
5091{
5092 struct drm_device *dev = crtc->dev;
5093 struct drm_i915_private *dev_priv = dev->dev_private;
5094 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 5095 struct intel_encoder *encoder;
6be4a607 5096 int pipe = intel_crtc->pipe;
5eddb70b 5097 u32 reg, temp;
b52eb4dc 5098
f7abfe8b
CW		 5099 if (!intel_crtc->active)
5100 return;
5101
ea9d758d
DV		 5102 for_each_encoder_on_crtc(dev, crtc, encoder)
5103 encoder->disable(encoder);
5104
f9b61ff6
DV		 5105 drm_crtc_vblank_off(crtc);
5106 assert_vblank_disabled(crtc);
5107
6e3c9717 5108 if (intel_crtc->config->has_pch_encoder)
a72e4c9f 5109 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
d925c59a 5110
575f7ab7 5111 intel_disable_pipe(intel_crtc);
32f9d658 5112
3f8dce3a 5113 ironlake_pfit_disable(intel_crtc);
2c07245f 5114
bf49ec8c
DV		 5115 for_each_encoder_on_crtc(dev, crtc, encoder)
5116 if (encoder->post_disable)
5117 encoder->post_disable(encoder);
2c07245f 5118
6e3c9717 5119 if (intel_crtc->config->has_pch_encoder) {
d925c59a 5120 ironlake_fdi_disable(crtc);
913d8d11 5121
d925c59a 5122 ironlake_disable_pch_transcoder(dev_priv, pipe);
6be4a607 5123
d925c59a
DV		 5124 if (HAS_PCH_CPT(dev)) {
5125 /* disable TRANS_DP_CTL */
5126 reg = TRANS_DP_CTL(pipe);
5127 temp = I915_READ(reg);
5128 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5129 TRANS_DP_PORT_SEL_MASK);
5130 temp |= TRANS_DP_PORT_SEL_NONE;
5131 I915_WRITE(reg, temp);
5132
5133 /* disable DPLL_SEL */
5134 temp = I915_READ(PCH_DPLL_SEL);
11887397 5135 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 5136 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 5137 }
e3421a18 5138
d925c59a 5139 /* disable PCH DPLL */
e72f9fbf 5140 intel_disable_shared_dpll(intel_crtc);
8db9d77b 5141
d925c59a
DV		 5142 ironlake_fdi_pll_disable(intel_crtc);
5143 }
6b383a7f 5144
f7abfe8b 5145 intel_crtc->active = false;
46ba614c 5146 intel_update_watermarks(crtc);
d1ebd816
BW		 5147
5148 mutex_lock(&dev->struct_mutex);
7ff0ebcc 5149 intel_fbc_update(dev);
d1ebd816 5150 mutex_unlock(&dev->struct_mutex);
6be4a607 5151}
1b3c7a47 5152
4f771f10 5153static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 5154{
4f771f10
PZ		 5155 struct drm_device *dev = crtc->dev;
5156 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 5157 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10 5158 struct intel_encoder *encoder;
6e3c9717 5159 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee7b9f93 5160
4f771f10
PZ		 5161 if (!intel_crtc->active)
5162 return;
5163
8807e55b
JN		 5164 for_each_encoder_on_crtc(dev, crtc, encoder) {
5165 intel_opregion_notify_encoder(encoder, false);
4f771f10 5166 encoder->disable(encoder);
8807e55b 5167 }
4f771f10 5168
f9b61ff6
DV		 5169 drm_crtc_vblank_off(crtc);
5170 assert_vblank_disabled(crtc);
5171
6e3c9717 5172 if (intel_crtc->config->has_pch_encoder)
a72e4c9f
DV		 5173 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5174 false);
575f7ab7 5175 intel_disable_pipe(intel_crtc);
4f771f10 5176
6e3c9717 5177 if (intel_crtc->config->dp_encoder_is_mst)
a4bf214f
VS		 5178 intel_ddi_set_vc_payload_alloc(crtc, false);
5179
ad80a810 5180 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 5181
ff6d9f55 5182 if (INTEL_INFO(dev)->gen == 9)
a1b2278e 5183 skylake_pfit_update(intel_crtc, 0);
ff6d9f55 5184 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 5185 ironlake_pfit_disable(intel_crtc);
ff6d9f55
JB		 5186 else
5187 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10 5188
1f544388 5189 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10 5190
6e3c9717 5191 if (intel_crtc->config->has_pch_encoder) {
ab4d966c 5192 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 5193 intel_ddi_fdi_disable(crtc);
83616634 5194 }
4f771f10 5195
97b040aa
ID		 5196 for_each_encoder_on_crtc(dev, crtc, encoder)
5197 if (encoder->post_disable)
5198 encoder->post_disable(encoder);
5199
4f771f10 5200 intel_crtc->active = false;
46ba614c 5201 intel_update_watermarks(crtc);
4f771f10
PZ		 5202
5203 mutex_lock(&dev->struct_mutex);
7ff0ebcc 5204 intel_fbc_update(dev);
4f771f10 5205 mutex_unlock(&dev->struct_mutex);
df8ad70c
DV		 5206
5207 if (intel_crtc_to_shared_dpll(intel_crtc))
5208 intel_disable_shared_dpll(intel_crtc);
4f771f10
PZ		 5209}
5210
ee7b9f93
JB		 5211static void ironlake_crtc_off(struct drm_crtc *crtc)
5212{
5213 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 5214 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 5215}
5216
6441ab5f 5217
2dd24552
JB		 5218static void i9xx_pfit_enable(struct intel_crtc *crtc)
5219{
5220 struct drm_device *dev = crtc->base.dev;
5221 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 5222 struct intel_crtc_state *pipe_config = crtc->config;
2dd24552 5223
681a8504 5224 if (!pipe_config->gmch_pfit.control)
2dd24552
JB		 5225 return;
5226
2dd24552 5227 /*
c0b03411
DV		 5228 * The panel fitter should only be adjusted whilst the pipe is disabled,
5229 * according to register description and PRM.
2dd24552 5230 */
c0b03411
DV		 5231 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5232 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 5233
b074cec8
JB		 5234 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5235 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 5236
5237 /* Border color in case we don't scale up to the full screen. Black by
5238 * default, change to something else for debugging. */
5239 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 5240}
5241
d05410f9
DA		 5242static enum intel_display_power_domain port_to_power_domain(enum port port)
5243{
5244 switch (port) {
5245 case PORT_A:
5246 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5247 case PORT_B:
5248 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5249 case PORT_C:
5250 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5251 case PORT_D:
5252 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5253 default:
5254 WARN_ON_ONCE(1);
5255 return POWER_DOMAIN_PORT_OTHER;
5256 }
5257}
5258
77d22dca
ID		 5259#define for_each_power_domain(domain, mask) \
5260 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5261 if ((1 << (domain)) & (mask))
5262
319be8ae
ID		 5263enum intel_display_power_domain
5264intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5265{
5266 struct drm_device *dev = intel_encoder->base.dev;
5267 struct intel_digital_port *intel_dig_port;
5268
5269 switch (intel_encoder->type) {
5270 case INTEL_OUTPUT_UNKNOWN:
5271 /* Only DDI platforms should ever use this output type */
5272 WARN_ON_ONCE(!HAS_DDI(dev));
5273 case INTEL_OUTPUT_DISPLAYPORT:
5274 case INTEL_OUTPUT_HDMI:
5275 case INTEL_OUTPUT_EDP:
5276 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
d05410f9 5277 return port_to_power_domain(intel_dig_port->port);
0e32b39c
DA		 5278 case INTEL_OUTPUT_DP_MST:
5279 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5280 return port_to_power_domain(intel_dig_port->port);
319be8ae
ID		 5281 case INTEL_OUTPUT_ANALOG:
5282 return POWER_DOMAIN_PORT_CRT;
5283 case INTEL_OUTPUT_DSI:
5284 return POWER_DOMAIN_PORT_DSI;
5285 default:
5286 return POWER_DOMAIN_PORT_OTHER;
5287 }
5288}
5289
5290static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 5291{
319be8ae
ID		 5292 struct drm_device *dev = crtc->dev;
5293 struct intel_encoder *intel_encoder;
5294 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5295 enum pipe pipe = intel_crtc->pipe;
77d22dca
ID		 5296 unsigned long mask;
5297 enum transcoder transcoder;
5298
5299 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5300
5301 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5302 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6e3c9717
ACO		 5303 if (intel_crtc->config->pch_pfit.enabled ||
5304 intel_crtc->config->pch_pfit.force_thru)
77d22dca
ID		 5305 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5306
319be8ae
ID		 5307 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5308 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5309
77d22dca
ID		 5310 return mask;
5311}
5312
679dacd4 5313static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
77d22dca 5314{
679dacd4 5315 struct drm_device *dev = state->dev;
77d22dca
ID		 5316 struct drm_i915_private *dev_priv = dev->dev_private;
5317 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
5318 struct intel_crtc *crtc;
5319
5320 /*
5321 * First get all needed power domains, then put all unneeded, to avoid
5322 * any unnecessary toggling of the power wells.
5323 */
d3fcc808 5324 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 5325 enum intel_display_power_domain domain;
5326
83d65738 5327 if (!crtc->base.state->enable)
77d22dca
ID		 5328 continue;
5329
319be8ae 5330 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
77d22dca
ID		 5331
5332 for_each_power_domain(domain, pipe_domains[crtc->pipe])
5333 intel_display_power_get(dev_priv, domain);
5334 }
5335
50f6e502 5336 if (dev_priv->display.modeset_global_resources)
679dacd4 5337 dev_priv->display.modeset_global_resources(state);
50f6e502 5338
d3fcc808 5339 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 5340 enum intel_display_power_domain domain;
5341
5342 for_each_power_domain(domain, crtc->enabled_power_domains)
5343 intel_display_power_put(dev_priv, domain);
5344
5345 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
5346 }
5347
5348 intel_display_set_init_power(dev_priv, false);
5349}
5350
f8437dd1
VK		 5351void broxton_set_cdclk(struct drm_device *dev, int frequency)
5352{
5353 struct drm_i915_private *dev_priv = dev->dev_private;
5354 uint32_t divider;
5355 uint32_t ratio;
5356 uint32_t current_freq;
5357 int ret;
5358
5359 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5360 switch (frequency) {
5361 case 144000:
5362 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5363 ratio = BXT_DE_PLL_RATIO(60);
5364 break;
5365 case 288000:
5366 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5367 ratio = BXT_DE_PLL_RATIO(60);
5368 break;
5369 case 384000:
5370 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5371 ratio = BXT_DE_PLL_RATIO(60);
5372 break;
5373 case 576000:
5374 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5375 ratio = BXT_DE_PLL_RATIO(60);
5376 break;
5377 case 624000:
5378 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5379 ratio = BXT_DE_PLL_RATIO(65);
5380 break;
5381 case 19200:
5382 /*
5383 * Bypass frequency with DE PLL disabled. Init ratio, divider
5384 * to suppress GCC warning.
5385 */
5386 ratio = 0;
5387 divider = 0;
5388 break;
5389 default:
5390 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5391
5392 return;
5393 }
5394
5395 mutex_lock(&dev_priv->rps.hw_lock);
5396 /* Inform power controller of upcoming frequency change */
5397 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5398 0x80000000);
5399 mutex_unlock(&dev_priv->rps.hw_lock);
5400
5401 if (ret) {
5402 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5403 ret, frequency);
5404 return;
5405 }
5406
5407 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5408 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5409 current_freq = current_freq * 500 + 1000;
5410
5411 /*
5412 * DE PLL has to be disabled when
5413 * - setting to 19.2MHz (bypass, PLL isn't used)
5414 * - before setting to 624MHz (PLL needs toggling)
5415 * - before setting to any frequency from 624MHz (PLL needs toggling)
5416 */
5417 if (frequency == 19200 || frequency == 624000 ||
5418 current_freq == 624000) {
5419 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5420 /* Timeout 200us */
5421 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5422 1))
5423 DRM_ERROR("timout waiting for DE PLL unlock\n");
5424 }
5425
5426 if (frequency != 19200) {
5427 uint32_t val;
5428
5429 val = I915_READ(BXT_DE_PLL_CTL);
5430 val &= ~BXT_DE_PLL_RATIO_MASK;
5431 val |= ratio;
5432 I915_WRITE(BXT_DE_PLL_CTL, val);
5433
5434 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5435 /* Timeout 200us */
5436 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5437 DRM_ERROR("timeout waiting for DE PLL lock\n");
5438
5439 val = I915_READ(CDCLK_CTL);
5440 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5441 val |= divider;
5442 /*
5443 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5444 * enable otherwise.
5445 */
5446 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5447 if (frequency >= 500000)
5448 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5449
5450 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5451 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5452 val |= (frequency - 1000) / 500;
5453 I915_WRITE(CDCLK_CTL, val);
5454 }
5455
5456 mutex_lock(&dev_priv->rps.hw_lock);
5457 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5458 DIV_ROUND_UP(frequency, 25000));
5459 mutex_unlock(&dev_priv->rps.hw_lock);
5460
5461 if (ret) {
5462 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5463 ret, frequency);
5464 return;
5465 }
5466
5467 dev_priv->cdclk_freq = frequency;
5468}
5469
5470void broxton_init_cdclk(struct drm_device *dev)
5471{
5472 struct drm_i915_private *dev_priv = dev->dev_private;
5473 uint32_t val;
5474
5475 /*
5476 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5477 * or else the reset will hang because there is no PCH to respond.
5478 * Move the handshake programming to initialization sequence.
5479 * Previously was left up to BIOS.
5480 */
5481 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5482 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5483 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5484
5485 /* Enable PG1 for cdclk */
5486 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5487
5488 /* check if cd clock is enabled */
5489 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5490 DRM_DEBUG_KMS("Display already initialized\n");
5491 return;
5492 }
5493
5494 /*
5495 * FIXME:
5496 * - The initial CDCLK needs to be read from VBT.
5497 * Need to make this change after VBT has changes for BXT.
5498 * - check if setting the max (or any) cdclk freq is really necessary
5499 * here, it belongs to modeset time
5500 */
5501 broxton_set_cdclk(dev, 624000);
5502
5503 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
22e02c0b
VS		 5504 POSTING_READ(DBUF_CTL);
5505
f8437dd1
VK		 5506 udelay(10);
5507
5508 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5509 DRM_ERROR("DBuf power enable timeout!\n");
5510}
5511
5512void broxton_uninit_cdclk(struct drm_device *dev)
5513{
5514 struct drm_i915_private *dev_priv = dev->dev_private;
5515
5516 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
22e02c0b
VS		 5517 POSTING_READ(DBUF_CTL);
5518
f8437dd1
VK		 5519 udelay(10);
5520
5521 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5522 DRM_ERROR("DBuf power disable timeout!\n");
5523
5524 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5525 broxton_set_cdclk(dev, 19200);
5526
5527 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5528}
5529
dfcab17e 5530/* returns HPLL frequency in kHz */
f8bf63fd 5531static int valleyview_get_vco(struct drm_i915_private *dev_priv)
30a970c6 5532{
586f49dc 5533 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
30a970c6 5534
586f49dc
JB		 5535 /* Obtain SKU information */
5536 mutex_lock(&dev_priv->dpio_lock);
5537 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5538 CCK_FUSE_HPLL_FREQ_MASK;
5539 mutex_unlock(&dev_priv->dpio_lock);
30a970c6 5540
dfcab17e 5541 return vco_freq[hpll_freq] * 1000;
30a970c6
JB		 5542}
5543
f8bf63fd
VS		 5544static void vlv_update_cdclk(struct drm_device *dev)
5545{
5546 struct drm_i915_private *dev_priv = dev->dev_private;
5547
164dfd28 5548 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
43dc52c3 5549 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
164dfd28 5550 dev_priv->cdclk_freq);
f8bf63fd
VS		 5551
5552 /*
5553 * Program the gmbus_freq based on the cdclk frequency.
5554 * BSpec erroneously claims we should aim for 4MHz, but
5555 * in fact 1MHz is the correct frequency.
5556 */
164dfd28 5557 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
f8bf63fd
VS		 5558}
5559
30a970c6
JB		 5560/* Adjust CDclk dividers to allow high res or save power if possible */
5561static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5562{
5563 struct drm_i915_private *dev_priv = dev->dev_private;
5564 u32 val, cmd;
5565
164dfd28
VK		 5566 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5567 != dev_priv->cdclk_freq);
d60c4473 5568
dfcab17e 5569 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
30a970c6 5570 cmd = 2;
dfcab17e 5571 else if (cdclk == 266667)
30a970c6
JB		 5572 cmd = 1;
5573 else
5574 cmd = 0;
5575
5576 mutex_lock(&dev_priv->rps.hw_lock);
5577 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5578 val &= ~DSPFREQGUAR_MASK;
5579 val |= (cmd << DSPFREQGUAR_SHIFT);
5580 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5581 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5582 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5583 50)) {
5584 DRM_ERROR("timed out waiting for CDclk change\n");
5585 }
5586 mutex_unlock(&dev_priv->rps.hw_lock);
5587
dfcab17e 5588 if (cdclk == 400000) {
6bcda4f0 5589 u32 divider;
30a970c6 5590
6bcda4f0 5591 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
30a970c6
JB		 5592
5593 mutex_lock(&dev_priv->dpio_lock);
5594 /* adjust cdclk divider */
5595 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
9cf33db5 5596 val &= ~DISPLAY_FREQUENCY_VALUES;
30a970c6
JB		 5597 val |= divider;
5598 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
a877e801
VS		 5599
5600 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5601 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5602 50))
5603 DRM_ERROR("timed out waiting for CDclk change\n");
30a970c6
JB		 5604 mutex_unlock(&dev_priv->dpio_lock);
5605 }
5606
5607 mutex_lock(&dev_priv->dpio_lock);
5608 /* adjust self-refresh exit latency value */
5609 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5610 val &= ~0x7f;
5611
5612 /*
5613 * For high bandwidth configs, we set a higher latency in the bunit
5614 * so that the core display fetch happens in time to avoid underruns.
5615 */
dfcab17e 5616 if (cdclk == 400000)
30a970c6
JB		 5617 val |= 4500 / 250; /* 4.5 usec */
5618 else
5619 val |= 3000 / 250; /* 3.0 usec */
5620 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5621 mutex_unlock(&dev_priv->dpio_lock);
5622
f8bf63fd 5623 vlv_update_cdclk(dev);
30a970c6
JB		 5624}
5625
383c5a6a
VS		 5626static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5627{
5628 struct drm_i915_private *dev_priv = dev->dev_private;
5629 u32 val, cmd;
5630
164dfd28
VK		 5631 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5632 != dev_priv->cdclk_freq);
383c5a6a
VS		 5633
5634 switch (cdclk) {
383c5a6a
VS		 5635 case 333333:
5636 case 320000:
383c5a6a 5637 case 266667:
383c5a6a 5638 case 200000:
383c5a6a
VS		 5639 break;
5640 default:
5f77eeb0 5641 MISSING_CASE(cdclk);
383c5a6a
VS		 5642 return;
5643 }
5644
9d0d3fda
VS		 5645 /*
5646 * Specs are full of misinformation, but testing on actual
5647 * hardware has shown that we just need to write the desired
5648 * CCK divider into the Punit register.
5649 */
5650 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5651
383c5a6a
VS		 5652 mutex_lock(&dev_priv->rps.hw_lock);
5653 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5654 val &= ~DSPFREQGUAR_MASK_CHV;
5655 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5656 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5657 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5658 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5659 50)) {
5660 DRM_ERROR("timed out waiting for CDclk change\n");
5661 }
5662 mutex_unlock(&dev_priv->rps.hw_lock);
5663
5664 vlv_update_cdclk(dev);
5665}
5666
30a970c6
JB		 5667static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5668 int max_pixclk)
5669{
6bcda4f0 5670 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6cca3195 5671 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
29dc7ef3 5672
30a970c6
JB		 5673 /*
5674 * Really only a few cases to deal with, as only 4 CDclks are supported:
5675 * 200MHz
5676 * 267MHz
29dc7ef3 5677 * 320/333MHz (depends on HPLL freq)
6cca3195
VS		 5678 * 400MHz (VLV only)
5679 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5680 * of the lower bin and adjust if needed.
e37c67a1
VS		 5681 *
5682 * We seem to get an unstable or solid color picture at 200MHz.
5683 * Not sure what's wrong. For now use 200MHz only when all pipes
5684 * are off.
30a970c6 5685 */
6cca3195
VS		 5686 if (!IS_CHERRYVIEW(dev_priv) &&
5687 max_pixclk > freq_320*limit/100)
dfcab17e 5688 return 400000;
6cca3195 5689 else if (max_pixclk > 266667*limit/100)
29dc7ef3 5690 return freq_320;
e37c67a1 5691 else if (max_pixclk > 0)
dfcab17e 5692 return 266667;
e37c67a1
VS		 5693 else
5694 return 200000;
30a970c6
JB		 5695}
5696
f8437dd1
VK		 5697static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5698 int max_pixclk)
5699{
5700 /*
5701 * FIXME:
5702 * - remove the guardband, it's not needed on BXT
5703 * - set 19.2MHz bypass frequency if there are no active pipes
5704 */
5705 if (max_pixclk > 576000*9/10)
5706 return 624000;
5707 else if (max_pixclk > 384000*9/10)
5708 return 576000;
5709 else if (max_pixclk > 288000*9/10)
5710 return 384000;
5711 else if (max_pixclk > 144000*9/10)
5712 return 288000;
5713 else
5714 return 144000;
5715}
5716
a821fc46
ACO		 5717/* Compute the max pixel clock for new configuration. Uses atomic state if
5718 * that's non-NULL, look at current state otherwise. */
5719static int intel_mode_max_pixclk(struct drm_device *dev,
5720 struct drm_atomic_state *state)
30a970c6 5721{
30a970c6 5722 struct intel_crtc *intel_crtc;
304603f4 5723 struct intel_crtc_state *crtc_state;
30a970c6
JB		 5724 int max_pixclk = 0;
5725
d3fcc808 5726 for_each_intel_crtc(dev, intel_crtc) {
a821fc46
ACO		 5727 if (state)
5728 crtc_state =
5729 intel_atomic_get_crtc_state(state, intel_crtc);
5730 else
5731 crtc_state = intel_crtc->config;
304603f4
ACO		 5732 if (IS_ERR(crtc_state))
5733 return PTR_ERR(crtc_state);
5734
5735 if (!crtc_state->base.enable)
5736 continue;
5737
5738 max_pixclk = max(max_pixclk,
5739 crtc_state->base.adjusted_mode.crtc_clock);
30a970c6
JB		 5740 }
5741
5742 return max_pixclk;
5743}
5744
0a9ab303 5745static int valleyview_modeset_global_pipes(struct drm_atomic_state *state)
30a970c6 5746{
304603f4 5747 struct drm_i915_private *dev_priv = to_i915(state->dev);
0a9ab303
ACO		 5748 struct drm_crtc *crtc;
5749 struct drm_crtc_state *crtc_state;
a821fc46 5750 int max_pixclk = intel_mode_max_pixclk(state->dev, state);
0a9ab303 5751 int cdclk, i;
30a970c6 5752
304603f4
ACO		 5753 if (max_pixclk < 0)
5754 return max_pixclk;
30a970c6 5755
f8437dd1
VK		 5756 if (IS_VALLEYVIEW(dev_priv))
5757 cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5758 else
5759 cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
5760
5761 if (cdclk == dev_priv->cdclk_freq)
304603f4 5762 return 0;
30a970c6 5763
0a9ab303
ACO		 5764 /* add all active pipes to the state */
5765 for_each_crtc(state->dev, crtc) {
5766 if (!crtc->state->enable)
5767 continue;
5768
5769 crtc_state = drm_atomic_get_crtc_state(state, crtc);
5770 if (IS_ERR(crtc_state))
5771 return PTR_ERR(crtc_state);
5772 }
5773
2f2d7aa1 5774 /* disable/enable all currently active pipes while we change cdclk */
0a9ab303
ACO		 5775 for_each_crtc_in_state(state, crtc, crtc_state, i)
5776 if (crtc_state->enable)
5777 crtc_state->mode_changed = true;
304603f4
ACO		 5778
5779 return 0;
30a970c6
JB		 5780}
5781
1e69cd74
VS		 5782static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5783{
5784 unsigned int credits, default_credits;
5785
5786 if (IS_CHERRYVIEW(dev_priv))
5787 default_credits = PFI_CREDIT(12);
5788 else
5789 default_credits = PFI_CREDIT(8);
5790
164dfd28 5791 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
1e69cd74
VS		 5792 /* CHV suggested value is 31 or 63 */
5793 if (IS_CHERRYVIEW(dev_priv))
5794 credits = PFI_CREDIT_31;
5795 else
5796 credits = PFI_CREDIT(15);
5797 } else {
5798 credits = default_credits;
5799 }
5800
5801 /*
5802 * WA - write default credits before re-programming
5803 * FIXME: should we also set the resend bit here?
5804 */
5805 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5806 default_credits);
5807
5808 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5809 credits | PFI_CREDIT_RESEND);
5810
5811 /*
5812 * FIXME is this guaranteed to clear
5813 * immediately or should we poll for it?
5814 */
5815 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5816}
5817
a821fc46 5818static void valleyview_modeset_global_resources(struct drm_atomic_state *old_state)
30a970c6 5819{
a821fc46 5820 struct drm_device *dev = old_state->dev;
30a970c6 5821 struct drm_i915_private *dev_priv = dev->dev_private;
a821fc46 5822 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
304603f4
ACO		 5823 int req_cdclk;
5824
a821fc46
ACO		 5825 /* The path in intel_mode_max_pixclk() with a NULL atomic state should
5826 * never fail. */
304603f4
ACO		 5827 if (WARN_ON(max_pixclk < 0))
5828 return;
30a970c6 5829
304603f4 5830 req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
30a970c6 5831
164dfd28 5832 if (req_cdclk != dev_priv->cdclk_freq) {
738c05c0
ID		 5833 /*
5834 * FIXME: We can end up here with all power domains off, yet
5835 * with a CDCLK frequency other than the minimum. To account
5836 * for this take the PIPE-A power domain, which covers the HW
5837 * blocks needed for the following programming. This can be
5838 * removed once it's guaranteed that we get here either with
5839 * the minimum CDCLK set, or the required power domains
5840 * enabled.
5841 */
5842 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5843
383c5a6a
VS		 5844 if (IS_CHERRYVIEW(dev))
5845 cherryview_set_cdclk(dev, req_cdclk);
5846 else
5847 valleyview_set_cdclk(dev, req_cdclk);
738c05c0 5848
1e69cd74
VS		 5849 vlv_program_pfi_credits(dev_priv);
5850
738c05c0 5851 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
383c5a6a 5852 }
30a970c6
JB		 5853}
5854
89b667f8
JB		 5855static void valleyview_crtc_enable(struct drm_crtc *crtc)
5856{
5857 struct drm_device *dev = crtc->dev;
a72e4c9f 5858 struct drm_i915_private *dev_priv = to_i915(dev);
89b667f8
JB		 5859 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5860 struct intel_encoder *encoder;
5861 int pipe = intel_crtc->pipe;
23538ef1 5862 bool is_dsi;
89b667f8 5863
83d65738 5864 WARN_ON(!crtc->state->enable);
89b667f8
JB		 5865
5866 if (intel_crtc->active)
5867 return;
5868
409ee761 5869 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
8525a235 5870
1ae0d137
VS		 5871 if (!is_dsi) {
5872 if (IS_CHERRYVIEW(dev))
6e3c9717 5873 chv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 5874 else
6e3c9717 5875 vlv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 5876 }
5b18e57c 5877
6e3c9717 5878 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 5879 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 5880
5881 intel_set_pipe_timings(intel_crtc);
5882
c14b0485
VS		 5883 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5884 struct drm_i915_private *dev_priv = dev->dev_private;
5885
5886 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5887 I915_WRITE(CHV_CANVAS(pipe), 0);
5888 }
5889
5b18e57c
DV		 5890 i9xx_set_pipeconf(intel_crtc);
5891
89b667f8 5892 intel_crtc->active = true;
89b667f8 5893
a72e4c9f 5894 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 5895
89b667f8
JB		 5896 for_each_encoder_on_crtc(dev, crtc, encoder)
5897 if (encoder->pre_pll_enable)
5898 encoder->pre_pll_enable(encoder);
5899
9d556c99
CML		 5900 if (!is_dsi) {
5901 if (IS_CHERRYVIEW(dev))
6e3c9717 5902 chv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 5903 else
6e3c9717 5904 vlv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 5905 }
89b667f8
JB		 5906
5907 for_each_encoder_on_crtc(dev, crtc, encoder)
5908 if (encoder->pre_enable)
5909 encoder->pre_enable(encoder);
5910
2dd24552
JB		 5911 i9xx_pfit_enable(intel_crtc);
5912
63cbb074
VS		 5913 intel_crtc_load_lut(crtc);
5914
f37fcc2a 5915 intel_update_watermarks(crtc);
e1fdc473 5916 intel_enable_pipe(intel_crtc);
be6a6f8e 5917
4b3a9526
VS		 5918 assert_vblank_disabled(crtc);
5919 drm_crtc_vblank_on(crtc);
5920
f9b61ff6
DV		 5921 for_each_encoder_on_crtc(dev, crtc, encoder)
5922 encoder->enable(encoder);
89b667f8
JB		 5923}
5924
f13c2ef3
DV		 5925static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5926{
5927 struct drm_device *dev = crtc->base.dev;
5928 struct drm_i915_private *dev_priv = dev->dev_private;
5929
6e3c9717
ACO		 5930 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5931 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
f13c2ef3
DV		 5932}
5933
0b8765c6 5934static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 5935{
5936 struct drm_device *dev = crtc->dev;
a72e4c9f 5937 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945 5938 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 5939 struct intel_encoder *encoder;
79e53945 5940 int pipe = intel_crtc->pipe;
79e53945 5941
83d65738 5942 WARN_ON(!crtc->state->enable);
08a48469 5943
f7abfe8b
CW		 5944 if (intel_crtc->active)
5945 return;
5946
f13c2ef3
DV		 5947 i9xx_set_pll_dividers(intel_crtc);
5948
6e3c9717 5949 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 5950 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 5951
5952 intel_set_pipe_timings(intel_crtc);
5953
5b18e57c
DV		 5954 i9xx_set_pipeconf(intel_crtc);
5955
f7abfe8b 5956 intel_crtc->active = true;
6b383a7f 5957
4a3436e8 5958 if (!IS_GEN2(dev))
a72e4c9f 5959 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 5960
9d6d9f19
MK		 5961 for_each_encoder_on_crtc(dev, crtc, encoder)
5962 if (encoder->pre_enable)
5963 encoder->pre_enable(encoder);
5964
f6736a1a
DV		 5965 i9xx_enable_pll(intel_crtc);
5966
2dd24552
JB		 5967 i9xx_pfit_enable(intel_crtc);
5968
63cbb074
VS		 5969 intel_crtc_load_lut(crtc);
5970
f37fcc2a 5971 intel_update_watermarks(crtc);
e1fdc473 5972 intel_enable_pipe(intel_crtc);
be6a6f8e 5973
4b3a9526
VS		 5974 assert_vblank_disabled(crtc);
5975 drm_crtc_vblank_on(crtc);
5976
f9b61ff6
DV		 5977 for_each_encoder_on_crtc(dev, crtc, encoder)
5978 encoder->enable(encoder);
0b8765c6 5979}
79e53945 5980
87476d63
DV		 5981static void i9xx_pfit_disable(struct intel_crtc *crtc)
5982{
5983 struct drm_device *dev = crtc->base.dev;
5984 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 5985
6e3c9717 5986 if (!crtc->config->gmch_pfit.control)
328d8e82 5987 return;
87476d63 5988
328d8e82 5989 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 5990
328d8e82
DV		 5991 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5992 I915_READ(PFIT_CONTROL));
5993 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 5994}
5995
0b8765c6
JB		 5996static void i9xx_crtc_disable(struct drm_crtc *crtc)
5997{
5998 struct drm_device *dev = crtc->dev;
5999 struct drm_i915_private *dev_priv = dev->dev_private;
6000 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6001 struct intel_encoder *encoder;
0b8765c6 6002 int pipe = intel_crtc->pipe;
ef9c3aee 6003
f7abfe8b
CW		 6004 if (!intel_crtc->active)
6005 return;
6006
6304cd91
VS		 6007 /*
6008 * On gen2 planes are double buffered but the pipe isn't, so we must
6009 * wait for planes to fully turn off before disabling the pipe.
564ed191
ID		 6010 * We also need to wait on all gmch platforms because of the
6011 * self-refresh mode constraint explained above.
6304cd91 6012 */
564ed191 6013 intel_wait_for_vblank(dev, pipe);
6304cd91 6014
4b3a9526
VS		 6015 for_each_encoder_on_crtc(dev, crtc, encoder)
6016 encoder->disable(encoder);
6017
f9b61ff6
DV		 6018 drm_crtc_vblank_off(crtc);
6019 assert_vblank_disabled(crtc);
6020
575f7ab7 6021 intel_disable_pipe(intel_crtc);
24a1f16d 6022
87476d63 6023 i9xx_pfit_disable(intel_crtc);
24a1f16d 6024
89b667f8
JB		 6025 for_each_encoder_on_crtc(dev, crtc, encoder)
6026 if (encoder->post_disable)
6027 encoder->post_disable(encoder);
6028
409ee761 6029 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
076ed3b2
CML		 6030 if (IS_CHERRYVIEW(dev))
6031 chv_disable_pll(dev_priv, pipe);
6032 else if (IS_VALLEYVIEW(dev))
6033 vlv_disable_pll(dev_priv, pipe);
6034 else
1c4e0274 6035 i9xx_disable_pll(intel_crtc);
076ed3b2 6036 }
0b8765c6 6037
4a3436e8 6038 if (!IS_GEN2(dev))
a72e4c9f 6039 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4a3436e8 6040
f7abfe8b 6041 intel_crtc->active = false;
46ba614c 6042 intel_update_watermarks(crtc);
f37fcc2a 6043
efa9624e 6044 mutex_lock(&dev->struct_mutex);
7ff0ebcc 6045 intel_fbc_update(dev);
efa9624e 6046 mutex_unlock(&dev->struct_mutex);
0b8765c6
JB		 6047}
6048
ee7b9f93
JB		 6049static void i9xx_crtc_off(struct drm_crtc *crtc)
6050{
6051}
6052
b04c5bd6
BF		 6053/* Master function to enable/disable CRTC and corresponding power wells */
6054void intel_crtc_control(struct drm_crtc *crtc, bool enable)
976f8a20
DV		 6055{
6056 struct drm_device *dev = crtc->dev;
6057 struct drm_i915_private *dev_priv = dev->dev_private;
0e572fe7 6058 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
0e572fe7
DV		 6059 enum intel_display_power_domain domain;
6060 unsigned long domains;
976f8a20 6061
0e572fe7
DV		 6062 if (enable) {
6063 if (!intel_crtc->active) {
e1e9fb84
DV		 6064 domains = get_crtc_power_domains(crtc);
6065 for_each_power_domain(domain, domains)
6066 intel_display_power_get(dev_priv, domain);
6067 intel_crtc->enabled_power_domains = domains;
0e572fe7
DV		 6068
6069 dev_priv->display.crtc_enable(crtc);
ce22dba9 6070 intel_crtc_enable_planes(crtc);
0e572fe7
DV		 6071 }
6072 } else {
6073 if (intel_crtc->active) {
ce22dba9 6074 intel_crtc_disable_planes(crtc);
0e572fe7
DV		 6075 dev_priv->display.crtc_disable(crtc);
6076
e1e9fb84
DV		 6077 domains = intel_crtc->enabled_power_domains;
6078 for_each_power_domain(domain, domains)
6079 intel_display_power_put(dev_priv, domain);
6080 intel_crtc->enabled_power_domains = 0;
0e572fe7
DV		 6081 }
6082 }
b04c5bd6
BF		 6083}
6084
6085/**
6086 * Sets the power management mode of the pipe and plane.
6087 */
6088void intel_crtc_update_dpms(struct drm_crtc *crtc)
6089{
6090 struct drm_device *dev = crtc->dev;
6091 struct intel_encoder *intel_encoder;
6092 bool enable = false;
6093
6094 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
6095 enable |= intel_encoder->connectors_active;
6096
6097 intel_crtc_control(crtc, enable);
0f63cca2
ACO		 6098
6099 crtc->state->active = enable;
976f8a20
DV		 6100}
6101
cdd59983
CW		 6102static void intel_crtc_disable(struct drm_crtc *crtc)
6103{
cdd59983 6104 struct drm_device *dev = crtc->dev;
976f8a20 6105 struct drm_connector *connector;
ee7b9f93 6106 struct drm_i915_private *dev_priv = dev->dev_private;
cdd59983 6107
976f8a20 6108 /* crtc should still be enabled when we disable it. */
83d65738 6109 WARN_ON(!crtc->state->enable);
976f8a20 6110
ce22dba9 6111 intel_crtc_disable_planes(crtc);
976f8a20 6112 dev_priv->display.crtc_disable(crtc);
ee7b9f93
JB		 6113 dev_priv->display.off(crtc);
6114
70a101f8 6115 drm_plane_helper_disable(crtc->primary);
976f8a20
DV		 6116
6117 /* Update computed state. */
6118 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6119 if (!connector->encoder || !connector->encoder->crtc)
6120 continue;
6121
6122 if (connector->encoder->crtc != crtc)
6123 continue;
6124
6125 connector->dpms = DRM_MODE_DPMS_OFF;
6126 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 6127 }
6128}
6129
ea5b213a 6130void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 6131{
4ef69c7a 6132 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 6133
ea5b213a
CW		 6134 drm_encoder_cleanup(encoder);
6135 kfree(intel_encoder);
7e7d76c3
JB		 6136}
6137
9237329d 6138/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
DV		 6139 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6140 * state of the entire output pipe. */
9237329d 6141static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 6142{
5ab432ef
DV		 6143 if (mode == DRM_MODE_DPMS_ON) {
6144 encoder->connectors_active = true;
6145
b2cabb0e 6146 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 6147 } else {
6148 encoder->connectors_active = false;
6149
b2cabb0e 6150 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 6151 }
79e53945
JB		 6152}
6153
0a91ca29
DV		 6154/* Cross check the actual hw state with our own modeset state tracking (and it's
6155 * internal consistency). */
b980514c 6156static void intel_connector_check_state(struct intel_connector *connector)
79e53945 6157{
0a91ca29
DV		 6158 if (connector->get_hw_state(connector)) {
6159 struct intel_encoder *encoder = connector->encoder;
6160 struct drm_crtc *crtc;
6161 bool encoder_enabled;
6162 enum pipe pipe;
6163
6164 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6165 connector->base.base.id,
c23cc417 6166 connector->base.name);
0a91ca29 6167
0e32b39c
DA		 6168 /* there is no real hw state for MST connectors */
6169 if (connector->mst_port)
6170 return;
6171
e2c719b7 6172 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
0a91ca29 6173 "wrong connector dpms state\n");
e2c719b7 6174 I915_STATE_WARN(connector->base.encoder != &encoder->base,
0a91ca29 6175 "active connector not linked to encoder\n");
0a91ca29 6176
36cd7444 6177 if (encoder) {
e2c719b7 6178 I915_STATE_WARN(!encoder->connectors_active,
36cd7444
DA		 6179 "encoder->connectors_active not set\n");
6180
6181 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
e2c719b7
RC		 6182 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6183 if (I915_STATE_WARN_ON(!encoder->base.crtc))
36cd7444 6184 return;
0a91ca29 6185
36cd7444 6186 crtc = encoder->base.crtc;
0a91ca29 6187
83d65738
MR		 6188 I915_STATE_WARN(!crtc->state->enable,
6189 "crtc not enabled\n");
e2c719b7
RC		 6190 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6191 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
36cd7444
DA		 6192 "encoder active on the wrong pipe\n");
6193 }
0a91ca29 6194 }
79e53945
JB		 6195}
6196
08d9bc92
ACO		 6197int intel_connector_init(struct intel_connector *connector)
6198{
6199 struct drm_connector_state *connector_state;
6200
6201 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6202 if (!connector_state)
6203 return -ENOMEM;
6204
6205 connector->base.state = connector_state;
6206 return 0;
6207}
6208
6209struct intel_connector *intel_connector_alloc(void)
6210{
6211 struct intel_connector *connector;
6212
6213 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6214 if (!connector)
6215 return NULL;
6216
6217 if (intel_connector_init(connector) < 0) {
6218 kfree(connector);
6219 return NULL;
6220 }
6221
6222 return connector;
6223}
6224
5ab432ef
DV		 6225/* Even simpler default implementation, if there's really no special case to
6226 * consider. */
6227void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 6228{
5ab432ef
DV		 6229 /* All the simple cases only support two dpms states. */
6230 if (mode != DRM_MODE_DPMS_ON)
6231 mode = DRM_MODE_DPMS_OFF;
d4270e57 6232
5ab432ef
DV		 6233 if (mode == connector->dpms)
6234 return;
6235
6236 connector->dpms = mode;
6237
6238 /* Only need to change hw state when actually enabled */
c9976dcf
CW		 6239 if (connector->encoder)
6240 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
0a91ca29 6241
b980514c 6242 intel_modeset_check_state(connector->dev);
79e53945
JB		 6243}
6244
f0947c37
DV		 6245/* Simple connector->get_hw_state implementation for encoders that support only
6246 * one connector and no cloning and hence the encoder state determines the state
6247 * of the connector. */
6248bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 6249{
24929352 6250 enum pipe pipe = 0;
f0947c37 6251 struct intel_encoder *encoder = connector->encoder;
ea5b213a 6252
f0947c37 6253 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 6254}
6255
6d293983 6256static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
d272ddfa 6257{
6d293983
ACO		 6258 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6259 return crtc_state->fdi_lanes;
d272ddfa
VS		 6260
6261 return 0;
6262}
6263
6d293983 6264static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5cec258b 6265 struct intel_crtc_state *pipe_config)
1857e1da 6266{
6d293983
ACO		 6267 struct drm_atomic_state *state = pipe_config->base.state;
6268 struct intel_crtc *other_crtc;
6269 struct intel_crtc_state *other_crtc_state;
6270
1857e1da
DV		 6271 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6272 pipe_name(pipe), pipe_config->fdi_lanes);
6273 if (pipe_config->fdi_lanes > 4) {
6274 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6275 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6276 return -EINVAL;
1857e1da
DV		 6277 }
6278
bafb6553 6279 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1857e1da
DV		 6280 if (pipe_config->fdi_lanes > 2) {
6281 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6282 pipe_config->fdi_lanes);
6d293983 6283 return -EINVAL;
1857e1da 6284 } else {
6d293983 6285 return 0;
1857e1da
DV		 6286 }
6287 }
6288
6289 if (INTEL_INFO(dev)->num_pipes == 2)
6d293983 6290 return 0;
1857e1da
DV		 6291
6292 /* Ivybridge 3 pipe is really complicated */
6293 switch (pipe) {
6294 case PIPE_A:
6d293983 6295 return 0;
1857e1da 6296 case PIPE_B:
6d293983
ACO		 6297 if (pipe_config->fdi_lanes <= 2)
6298 return 0;
6299
6300 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6301 other_crtc_state =
6302 intel_atomic_get_crtc_state(state, other_crtc);
6303 if (IS_ERR(other_crtc_state))
6304 return PTR_ERR(other_crtc_state);
6305
6306 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
1857e1da
DV		 6307 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6308 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6309 return -EINVAL;
1857e1da 6310 }
6d293983 6311 return 0;
1857e1da 6312 case PIPE_C:
251cc67c
VS		 6313 if (pipe_config->fdi_lanes > 2) {
6314 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6315 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6316 return -EINVAL;
251cc67c 6317 }
6d293983
ACO		 6318
6319 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6320 other_crtc_state =
6321 intel_atomic_get_crtc_state(state, other_crtc);
6322 if (IS_ERR(other_crtc_state))
6323 return PTR_ERR(other_crtc_state);
6324
6325 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
1857e1da 6326 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6d293983 6327 return -EINVAL;
1857e1da 6328 }
6d293983 6329 return 0;
1857e1da
DV		 6330 default:
6331 BUG();
6332 }
6333}
6334
e29c22c0
DV		 6335#define RETRY 1
6336static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5cec258b 6337 struct intel_crtc_state *pipe_config)
877d48d5 6338{
1857e1da 6339 struct drm_device *dev = intel_crtc->base.dev;
2d112de7 6340 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6d293983
ACO		 6341 int lane, link_bw, fdi_dotclock, ret;
6342 bool needs_recompute = false;
877d48d5 6343
e29c22c0 6344retry:
877d48d5
DV		 6345 /* FDI is a binary signal running at ~2.7GHz, encoding
6346 * each output octet as 10 bits. The actual frequency
6347 * is stored as a divider into a 100MHz clock, and the
6348 * mode pixel clock is stored in units of 1KHz.
6349 * Hence the bw of each lane in terms of the mode signal
6350 * is:
6351 */
6352 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6353
241bfc38 6354 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 6355
2bd89a07 6356 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 6357 pipe_config->pipe_bpp);
6358
6359 pipe_config->fdi_lanes = lane;
6360
2bd89a07 6361 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 6362 link_bw, &pipe_config->fdi_m_n);
1857e1da 6363
6d293983
ACO		 6364 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6365 intel_crtc->pipe, pipe_config);
6366 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
e29c22c0
DV		 6367 pipe_config->pipe_bpp -= 2*3;
6368 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6369 pipe_config->pipe_bpp);
6370 needs_recompute = true;
6371 pipe_config->bw_constrained = true;
6372
6373 goto retry;
6374 }
6375
6376 if (needs_recompute)
6377 return RETRY;
6378
6d293983 6379 return ret;
877d48d5
DV		 6380}
6381
42db64ef 6382static void hsw_compute_ips_config(struct intel_crtc *crtc,
5cec258b 6383 struct intel_crtc_state *pipe_config)
42db64ef 6384{
d330a953 6385 pipe_config->ips_enabled = i915.enable_ips &&
3c4ca58c 6386 hsw_crtc_supports_ips(crtc) &&
b6dfdc9b 6387 pipe_config->pipe_bpp <= 24;
42db64ef
PZ		 6388}
6389
a43f6e0f 6390static int intel_crtc_compute_config(struct intel_crtc *crtc,
5cec258b 6391 struct intel_crtc_state *pipe_config)
79e53945 6392{
a43f6e0f 6393 struct drm_device *dev = crtc->base.dev;
8bd31e67 6394 struct drm_i915_private *dev_priv = dev->dev_private;
2d112de7 6395 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
d03c93d4 6396 int ret;
89749350 6397
ad3a4479 6398 /* FIXME should check pixel clock limits on all platforms */
cf532bb2 6399 if (INTEL_INFO(dev)->gen < 4) {
cf532bb2
VS		 6400 int clock_limit =
6401 dev_priv->display.get_display_clock_speed(dev);
6402
6403 /*
6404 * Enable pixel doubling when the dot clock
6405 * is > 90% of the (display) core speed.
6406 *
b397c96b
VS		 6407 * GDG double wide on either pipe,
6408 * otherwise pipe A only.
cf532bb2 6409 */
b397c96b 6410 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
241bfc38 6411 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
ad3a4479 6412 clock_limit *= 2;
cf532bb2 6413 pipe_config->double_wide = true;
ad3a4479
VS		 6414 }
6415
241bfc38 6416 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
e29c22c0 6417 return -EINVAL;
2c07245f 6418 }
89749350 6419
1d1d0e27
VS		 6420 /*
6421 * Pipe horizontal size must be even in:
6422 * - DVO ganged mode
6423 * - LVDS dual channel mode
6424 * - Double wide pipe
6425 */
a93e255f 6426 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
1d1d0e27
VS		 6427 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6428 pipe_config->pipe_src_w &= ~1;
6429
8693a824
DL		 6430 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6431 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 6432 */
6433 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6434 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 6435 return -EINVAL;
44f46b42 6436
f5adf94e 6437 if (HAS_IPS(dev))
a43f6e0f
DV		 6438 hsw_compute_ips_config(crtc, pipe_config);
6439
877d48d5 6440 if (pipe_config->has_pch_encoder)
a43f6e0f 6441 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 6442
d03c93d4
CK		 6443 /* FIXME: remove below call once atomic mode set is place and all crtc
6444 * related checks called from atomic_crtc_check function */
6445 ret = 0;
6446 DRM_DEBUG_KMS("intel_crtc = %p drm_state (pipe_config->base.state) = %p\n",
6447 crtc, pipe_config->base.state);
6448 ret = intel_atomic_setup_scalers(dev, crtc, pipe_config);
6449
6450 return ret;
79e53945
JB		 6451}
6452
1652d19e
VS		 6453static int skylake_get_display_clock_speed(struct drm_device *dev)
6454{
6455 struct drm_i915_private *dev_priv = to_i915(dev);
6456 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6457 uint32_t cdctl = I915_READ(CDCLK_CTL);
6458 uint32_t linkrate;
6459
6460 if (!(lcpll1 & LCPLL_PLL_ENABLE)) {
6461 WARN(1, "LCPLL1 not enabled\n");
6462 return 24000; /* 24MHz is the cd freq with NSSC ref */
6463 }
6464
6465 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6466 return 540000;
6467
6468 linkrate = (I915_READ(DPLL_CTRL1) &
71cd8423 6469 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
1652d19e 6470
71cd8423
DL		 6471 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6472 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
1652d19e
VS		 6473 /* vco 8640 */
6474 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6475 case CDCLK_FREQ_450_432:
6476 return 432000;
6477 case CDCLK_FREQ_337_308:
6478 return 308570;
6479 case CDCLK_FREQ_675_617:
6480 return 617140;
6481 default:
6482 WARN(1, "Unknown cd freq selection\n");
6483 }
6484 } else {
6485 /* vco 8100 */
6486 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6487 case CDCLK_FREQ_450_432:
6488 return 450000;
6489 case CDCLK_FREQ_337_308:
6490 return 337500;
6491 case CDCLK_FREQ_675_617:
6492 return 675000;
6493 default:
6494 WARN(1, "Unknown cd freq selection\n");
6495 }
6496 }
6497
6498 /* error case, do as if DPLL0 isn't enabled */
6499 return 24000;
6500}
6501
6502static int broadwell_get_display_clock_speed(struct drm_device *dev)
6503{
6504 struct drm_i915_private *dev_priv = dev->dev_private;
6505 uint32_t lcpll = I915_READ(LCPLL_CTL);
6506 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6507
6508 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6509 return 800000;
6510 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6511 return 450000;
6512 else if (freq == LCPLL_CLK_FREQ_450)
6513 return 450000;
6514 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6515 return 540000;
6516 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6517 return 337500;
6518 else
6519 return 675000;
6520}
6521
6522static int haswell_get_display_clock_speed(struct drm_device *dev)
6523{
6524 struct drm_i915_private *dev_priv = dev->dev_private;
6525 uint32_t lcpll = I915_READ(LCPLL_CTL);
6526 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6527
6528 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6529 return 800000;
6530 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6531 return 450000;
6532 else if (freq == LCPLL_CLK_FREQ_450)
6533 return 450000;
6534 else if (IS_HSW_ULT(dev))
6535 return 337500;
6536 else
6537 return 540000;
79e53945
JB		 6538}
6539
25eb05fc
JB		 6540static int valleyview_get_display_clock_speed(struct drm_device *dev)
6541{
d197b7d3 6542 struct drm_i915_private *dev_priv = dev->dev_private;
d197b7d3
VS		 6543 u32 val;
6544 int divider;
6545
6bcda4f0
VS		 6546 if (dev_priv->hpll_freq == 0)
6547 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6548
d197b7d3
VS		 6549 mutex_lock(&dev_priv->dpio_lock);
6550 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6551 mutex_unlock(&dev_priv->dpio_lock);
6552
6553 divider = val & DISPLAY_FREQUENCY_VALUES;
6554
7d007f40
VS		 6555 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6556 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6557 "cdclk change in progress\n");
6558
6bcda4f0 6559 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
25eb05fc
JB		 6560}
6561
b37a6434
VS		 6562static int ilk_get_display_clock_speed(struct drm_device *dev)
6563{
6564 return 450000;
6565}
6566
e70236a8
JB		 6567static int i945_get_display_clock_speed(struct drm_device *dev)
6568{
6569 return 400000;
6570}
79e53945 6571
e70236a8 6572static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 6573{
e907f170 6574 return 333333;
e70236a8 6575}
79e53945 6576
e70236a8
JB		 6577static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6578{
6579 return 200000;
6580}
79e53945 6581
257a7ffc
DV		 6582static int pnv_get_display_clock_speed(struct drm_device *dev)
6583{
6584 u16 gcfgc = 0;
6585
6586 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6587
6588 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6589 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
e907f170 6590 return 266667;
257a7ffc 6591 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
e907f170 6592 return 333333;
257a7ffc 6593 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
e907f170 6594 return 444444;
257a7ffc
DV		 6595 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6596 return 200000;
6597 default:
6598 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6599 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
e907f170 6600 return 133333;
257a7ffc 6601 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
e907f170 6602 return 166667;
257a7ffc
DV		 6603 }
6604}
6605
e70236a8
JB		 6606static int i915gm_get_display_clock_speed(struct drm_device *dev)
6607{
6608 u16 gcfgc = 0;
79e53945 6609
e70236a8
JB		 6610 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6611
6612 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
e907f170 6613 return 133333;
e70236a8
JB		 6614 else {
6615 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6616 case GC_DISPLAY_CLOCK_333_MHZ:
e907f170 6617 return 333333;
e70236a8
JB		 6618 default:
6619 case GC_DISPLAY_CLOCK_190_200_MHZ:
6620 return 190000;
79e53945 6621 }
e70236a8
JB		 6622 }
6623}
6624
6625static int i865_get_display_clock_speed(struct drm_device *dev)
6626{
e907f170 6627 return 266667;
e70236a8
JB		 6628}
6629
6630static int i855_get_display_clock_speed(struct drm_device *dev)
6631{
6632 u16 hpllcc = 0;
6633 /* Assume that the hardware is in the high speed state. This
6634 * should be the default.
6635 */
6636 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6637 case GC_CLOCK_133_200:
6638 case GC_CLOCK_100_200:
6639 return 200000;
6640 case GC_CLOCK_166_250:
6641 return 250000;
6642 case GC_CLOCK_100_133:
e907f170 6643 return 133333;
e70236a8 6644 }
79e53945 6645
e70236a8
JB		 6646 /* Shouldn't happen */
6647 return 0;
6648}
79e53945 6649
e70236a8
JB		 6650static int i830_get_display_clock_speed(struct drm_device *dev)
6651{
e907f170 6652 return 133333;
79e53945
JB		 6653}
6654
2c07245f 6655static void
a65851af 6656intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 6657{
a65851af
VS		 6658 while (*num > DATA_LINK_M_N_MASK ||
6659 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 6660 *num >>= 1;
6661 *den >>= 1;
6662 }
6663}
6664
a65851af
VS		 6665static void compute_m_n(unsigned int m, unsigned int n,
6666 uint32_t *ret_m, uint32_t *ret_n)
6667{
6668 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6669 *ret_m = div_u64((uint64_t) m * *ret_n, n);
6670 intel_reduce_m_n_ratio(ret_m, ret_n);
6671}
6672
e69d0bc1
DV		 6673void
6674intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6675 int pixel_clock, int link_clock,
6676 struct intel_link_m_n *m_n)
2c07245f 6677{
e69d0bc1 6678 m_n->tu = 64;
a65851af
VS		 6679
6680 compute_m_n(bits_per_pixel * pixel_clock,
6681 link_clock * nlanes * 8,
6682 &m_n->gmch_m, &m_n->gmch_n);
6683
6684 compute_m_n(pixel_clock, link_clock,
6685 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 6686}
6687
a7615030
CW		 6688static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6689{
d330a953
JN		 6690 if (i915.panel_use_ssc >= 0)
6691 return i915.panel_use_ssc != 0;
41aa3448 6692 return dev_priv->vbt.lvds_use_ssc
435793df 6693 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 6694}
6695
a93e255f
ACO		 6696static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
6697 int num_connectors)
c65d77d8 6698{
a93e255f 6699 struct drm_device *dev = crtc_state->base.crtc->dev;
c65d77d8
JB		 6700 struct drm_i915_private *dev_priv = dev->dev_private;
6701 int refclk;
6702
a93e255f
ACO		 6703 WARN_ON(!crtc_state->base.state);
6704
5ab7b0b7 6705 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
9a0ea498 6706 refclk = 100000;
a93e255f 6707 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
c65d77d8 6708 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b
VS		 6709 refclk = dev_priv->vbt.lvds_ssc_freq;
6710 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
c65d77d8
JB		 6711 } else if (!IS_GEN2(dev)) {
6712 refclk = 96000;
6713 } else {
6714 refclk = 48000;
6715 }
6716
6717 return refclk;
6718}
6719
7429e9d4 6720static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 6721{
7df00d7a 6722 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 6723}
f47709a9 6724
7429e9d4
DV		 6725static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6726{
6727 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 6728}
6729
f47709a9 6730static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
190f68c5 6731 struct intel_crtc_state *crtc_state,
a7516a05
JB		 6732 intel_clock_t *reduced_clock)
6733{
f47709a9 6734 struct drm_device *dev = crtc->base.dev;
a7516a05
JB		 6735 u32 fp, fp2 = 0;
6736
6737 if (IS_PINEVIEW(dev)) {
190f68c5 6738 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
a7516a05 6739 if (reduced_clock)
7429e9d4 6740 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 6741 } else {
190f68c5 6742 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
a7516a05 6743 if (reduced_clock)
7429e9d4 6744 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 6745 }
6746
190f68c5 6747 crtc_state->dpll_hw_state.fp0 = fp;
a7516a05 6748
f47709a9 6749 crtc->lowfreq_avail = false;
a93e255f 6750 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
ab585dea 6751 reduced_clock) {
190f68c5 6752 crtc_state->dpll_hw_state.fp1 = fp2;
f47709a9 6753 crtc->lowfreq_avail = true;
a7516a05 6754 } else {
190f68c5 6755 crtc_state->dpll_hw_state.fp1 = fp;
a7516a05
JB		 6756 }
6757}
6758
5e69f97f
CML		 6759static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6760 pipe)
89b667f8
JB		 6761{
6762 u32 reg_val;
6763
6764 /*
6765 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6766 * and set it to a reasonable value instead.
6767 */
ab3c759a 6768 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8
JB		 6769 reg_val &= 0xffffff00;
6770 reg_val |= 0x00000030;
ab3c759a 6771 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 6772
ab3c759a 6773 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 6774 reg_val &= 0x8cffffff;
6775 reg_val = 0x8c000000;
ab3c759a 6776 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8 6777
ab3c759a 6778 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8 6779 reg_val &= 0xffffff00;
ab3c759a 6780 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 6781
ab3c759a 6782 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 6783 reg_val &= 0x00ffffff;
6784 reg_val |= 0xb0000000;
ab3c759a 6785 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8
JB		 6786}
6787
b551842d
DV		 6788static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6789 struct intel_link_m_n *m_n)
6790{
6791 struct drm_device *dev = crtc->base.dev;
6792 struct drm_i915_private *dev_priv = dev->dev_private;
6793 int pipe = crtc->pipe;
6794
e3b95f1e
DV		 6795 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6796 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6797 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6798 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 6799}
6800
6801static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 6802 struct intel_link_m_n *m_n,
6803 struct intel_link_m_n *m2_n2)
b551842d
DV		 6804{
6805 struct drm_device *dev = crtc->base.dev;
6806 struct drm_i915_private *dev_priv = dev->dev_private;
6807 int pipe = crtc->pipe;
6e3c9717 6808 enum transcoder transcoder = crtc->config->cpu_transcoder;
b551842d
DV		 6809
6810 if (INTEL_INFO(dev)->gen >= 5) {
6811 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6812 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6813 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6814 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
f769cd24
VK		 6815 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6816 * for gen < 8) and if DRRS is supported (to make sure the
6817 * registers are not unnecessarily accessed).
6818 */
44395bfe 6819 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6e3c9717 6820 crtc->config->has_drrs) {
f769cd24
VK		 6821 I915_WRITE(PIPE_DATA_M2(transcoder),
6822 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6823 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6824 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6825 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6826 }
b551842d 6827 } else {
e3b95f1e
DV		 6828 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6829 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6830 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6831 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 6832 }
6833}
6834
fe3cd48d 6835void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
03afc4a2 6836{
fe3cd48d
R		 6837 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6838
6839 if (m_n == M1_N1) {
6840 dp_m_n = &crtc->config->dp_m_n;
6841 dp_m2_n2 = &crtc->config->dp_m2_n2;
6842 } else if (m_n == M2_N2) {
6843
6844 /*
6845 * M2_N2 registers are not supported. Hence m2_n2 divider value
6846 * needs to be programmed into M1_N1.
6847 */
6848 dp_m_n = &crtc->config->dp_m2_n2;
6849 } else {
6850 DRM_ERROR("Unsupported divider value\n");
6851 return;
6852 }
6853
6e3c9717
ACO		 6854 if (crtc->config->has_pch_encoder)
6855 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
03afc4a2 6856 else
fe3cd48d 6857 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
03afc4a2
DV		 6858}
6859
d288f65f 6860static void vlv_update_pll(struct intel_crtc *crtc,
5cec258b 6861 struct intel_crtc_state *pipe_config)
bdd4b6a6
DV		 6862{
6863 u32 dpll, dpll_md;
6864
6865 /*
6866 * Enable DPIO clock input. We should never disable the reference
6867 * clock for pipe B, since VGA hotplug / manual detection depends
6868 * on it.
6869 */
6870 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
6871 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
6872 /* We should never disable this, set it here for state tracking */
6873 if (crtc->pipe == PIPE_B)
6874 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6875 dpll |= DPLL_VCO_ENABLE;
d288f65f 6876 pipe_config->dpll_hw_state.dpll = dpll;
bdd4b6a6 6877
d288f65f 6878 dpll_md = (pipe_config->pixel_multiplier - 1)
bdd4b6a6 6879 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
d288f65f 6880 pipe_config->dpll_hw_state.dpll_md = dpll_md;
bdd4b6a6
DV		 6881}
6882
d288f65f 6883static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 6884 const struct intel_crtc_state *pipe_config)
a0c4da24 6885{
f47709a9 6886 struct drm_device *dev = crtc->base.dev;
a0c4da24 6887 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 6888 int pipe = crtc->pipe;
bdd4b6a6 6889 u32 mdiv;
a0c4da24 6890 u32 bestn, bestm1, bestm2, bestp1, bestp2;
bdd4b6a6 6891 u32 coreclk, reg_val;
a0c4da24 6892
09153000
DV		 6893 mutex_lock(&dev_priv->dpio_lock);
6894
d288f65f
VS		 6895 bestn = pipe_config->dpll.n;
6896 bestm1 = pipe_config->dpll.m1;
6897 bestm2 = pipe_config->dpll.m2;
6898 bestp1 = pipe_config->dpll.p1;
6899 bestp2 = pipe_config->dpll.p2;
a0c4da24 6900
89b667f8
JB		 6901 /* See eDP HDMI DPIO driver vbios notes doc */
6902
6903 /* PLL B needs special handling */
bdd4b6a6 6904 if (pipe == PIPE_B)
5e69f97f 6905 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 6906
6907 /* Set up Tx target for periodic Rcomp update */
ab3c759a 6908 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
89b667f8
JB		 6909
6910 /* Disable target IRef on PLL */
ab3c759a 6911 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
89b667f8 6912 reg_val &= 0x00ffffff;
ab3c759a 6913 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
89b667f8
JB		 6914
6915 /* Disable fast lock */
ab3c759a 6916 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
89b667f8
JB		 6917
6918 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 6919 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6920 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6921 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 6922 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 6923
6924 /*
6925 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6926 * but we don't support that).
6927 * Note: don't use the DAC post divider as it seems unstable.
6928 */
6929 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ab3c759a 6930 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 6931
a0c4da24 6932 mdiv |= DPIO_ENABLE_CALIBRATION;
ab3c759a 6933 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 6934
89b667f8 6935 /* Set HBR and RBR LPF coefficients */
d288f65f 6936 if (pipe_config->port_clock == 162000 ||
409ee761
ACO		 6937 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
6938 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
ab3c759a 6939 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
885b0120 6940 0x009f0003);
89b667f8 6941 else
ab3c759a 6942 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
89b667f8
JB		 6943 0x00d0000f);
6944
681a8504 6945 if (pipe_config->has_dp_encoder) {
89b667f8 6946 /* Use SSC source */
bdd4b6a6 6947 if (pipe == PIPE_A)
ab3c759a 6948 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6949 0x0df40000);
6950 else
ab3c759a 6951 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6952 0x0df70000);
6953 } else { /* HDMI or VGA */
6954 /* Use bend source */
bdd4b6a6 6955 if (pipe == PIPE_A)
ab3c759a 6956 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6957 0x0df70000);
6958 else
ab3c759a 6959 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6960 0x0df40000);
6961 }
a0c4da24 6962
ab3c759a 6963 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
89b667f8 6964 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
409ee761
ACO		 6965 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
6966 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
89b667f8 6967 coreclk |= 0x01000000;
ab3c759a 6968 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
a0c4da24 6969
ab3c759a 6970 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
09153000 6971 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 6972}
6973
d288f65f 6974static void chv_update_pll(struct intel_crtc *crtc,
5cec258b 6975 struct intel_crtc_state *pipe_config)
1ae0d137 6976{
d288f65f 6977 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
1ae0d137
VS		 6978 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
6979 DPLL_VCO_ENABLE;
6980 if (crtc->pipe != PIPE_A)
d288f65f 6981 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
1ae0d137 6982
d288f65f
VS		 6983 pipe_config->dpll_hw_state.dpll_md =
6984 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
1ae0d137
VS		 6985}
6986
d288f65f 6987static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 6988 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 6989{
6990 struct drm_device *dev = crtc->base.dev;
6991 struct drm_i915_private *dev_priv = dev->dev_private;
6992 int pipe = crtc->pipe;
6993 int dpll_reg = DPLL(crtc->pipe);
6994 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9cbe40c1 6995 u32 loopfilter, tribuf_calcntr;
9d556c99 6996 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
a945ce7e 6997 u32 dpio_val;
9cbe40c1 6998 int vco;
9d556c99 6999
d288f65f
VS		 7000 bestn = pipe_config->dpll.n;
7001 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7002 bestm1 = pipe_config->dpll.m1;
7003 bestm2 = pipe_config->dpll.m2 >> 22;
7004 bestp1 = pipe_config->dpll.p1;
7005 bestp2 = pipe_config->dpll.p2;
9cbe40c1 7006 vco = pipe_config->dpll.vco;
a945ce7e 7007 dpio_val = 0;
9cbe40c1 7008 loopfilter = 0;
9d556c99
CML		 7009
7010 /*
7011 * Enable Refclk and SSC
7012 */
a11b0703 7013 I915_WRITE(dpll_reg,
d288f65f 7014 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
a11b0703
VS		 7015
7016 mutex_lock(&dev_priv->dpio_lock);
9d556c99 7017
9d556c99
CML		 7018 /* p1 and p2 divider */
7019 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7020 5 << DPIO_CHV_S1_DIV_SHIFT |
7021 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7022 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7023 1 << DPIO_CHV_K_DIV_SHIFT);
7024
7025 /* Feedback post-divider - m2 */
7026 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7027
7028 /* Feedback refclk divider - n and m1 */
7029 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7030 DPIO_CHV_M1_DIV_BY_2 |
7031 1 << DPIO_CHV_N_DIV_SHIFT);
7032
7033 /* M2 fraction division */
a945ce7e
VP		 7034 if (bestm2_frac)
7035 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
9d556c99
CML		 7036
7037 /* M2 fraction division enable */
a945ce7e
VP		 7038 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7039 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7040 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7041 if (bestm2_frac)
7042 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7043 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
9d556c99 7044
de3a0fde
VP		 7045 /* Program digital lock detect threshold */
7046 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7047 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7048 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7049 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7050 if (!bestm2_frac)
7051 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7052 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7053
9d556c99 7054 /* Loop filter */
9cbe40c1
VP		 7055 if (vco == 5400000) {
7056 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7057 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7058 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7059 tribuf_calcntr = 0x9;
7060 } else if (vco <= 6200000) {
7061 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7062 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7063 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7064 tribuf_calcntr = 0x9;
7065 } else if (vco <= 6480000) {
7066 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7067 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7068 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7069 tribuf_calcntr = 0x8;
7070 } else {
7071 /* Not supported. Apply the same limits as in the max case */
7072 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7073 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7074 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7075 tribuf_calcntr = 0;
7076 }
9d556c99
CML		 7077 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7078
968040b2 7079 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
9cbe40c1
VP		 7080 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7081 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7082 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7083
9d556c99
CML		 7084 /* AFC Recal */
7085 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7086 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7087 DPIO_AFC_RECAL);
7088
7089 mutex_unlock(&dev_priv->dpio_lock);
7090}
7091
d288f65f
VS		 7092/**
7093 * vlv_force_pll_on - forcibly enable just the PLL
7094 * @dev_priv: i915 private structure
7095 * @pipe: pipe PLL to enable
7096 * @dpll: PLL configuration
7097 *
7098 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7099 * in cases where we need the PLL enabled even when @pipe is not going to
7100 * be enabled.
7101 */
7102void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7103 const struct dpll *dpll)
7104{
7105 struct intel_crtc *crtc =
7106 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5cec258b 7107 struct intel_crtc_state pipe_config = {
a93e255f 7108 .base.crtc = &crtc->base,
d288f65f
VS		 7109 .pixel_multiplier = 1,
7110 .dpll = *dpll,
7111 };
7112
7113 if (IS_CHERRYVIEW(dev)) {
7114 chv_update_pll(crtc, &pipe_config);
7115 chv_prepare_pll(crtc, &pipe_config);
7116 chv_enable_pll(crtc, &pipe_config);
7117 } else {
7118 vlv_update_pll(crtc, &pipe_config);
7119 vlv_prepare_pll(crtc, &pipe_config);
7120 vlv_enable_pll(crtc, &pipe_config);
7121 }
7122}
7123
7124/**
7125 * vlv_force_pll_off - forcibly disable just the PLL
7126 * @dev_priv: i915 private structure
7127 * @pipe: pipe PLL to disable
7128 *
7129 * Disable the PLL for @pipe. To be used in cases where we need
7130 * the PLL enabled even when @pipe is not going to be enabled.
7131 */
7132void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7133{
7134 if (IS_CHERRYVIEW(dev))
7135 chv_disable_pll(to_i915(dev), pipe);
7136 else
7137 vlv_disable_pll(to_i915(dev), pipe);
7138}
7139
f47709a9 7140static void i9xx_update_pll(struct intel_crtc *crtc,
190f68c5 7141 struct intel_crtc_state *crtc_state,
f47709a9 7142 intel_clock_t *reduced_clock,
eb1cbe48
DV		 7143 int num_connectors)
7144{
f47709a9 7145 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7146 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 7147 u32 dpll;
7148 bool is_sdvo;
190f68c5 7149 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7150
190f68c5 7151 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7152
a93e255f
ACO		 7153 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7154 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 7155
7156 dpll = DPLL_VGA_MODE_DIS;
7157
a93e255f 7158 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 7159 dpll |= DPLLB_MODE_LVDS;
7160 else
7161 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 7162
ef1b460d 7163 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
190f68c5 7164 dpll |= (crtc_state->pixel_multiplier - 1)
198a037f 7165 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 7166 }
198a037f
DV		 7167
7168 if (is_sdvo)
4a33e48d 7169 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 7170
190f68c5 7171 if (crtc_state->has_dp_encoder)
4a33e48d 7172 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 7173
7174 /* compute bitmask from p1 value */
7175 if (IS_PINEVIEW(dev))
7176 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7177 else {
7178 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7179 if (IS_G4X(dev) && reduced_clock)
7180 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7181 }
7182 switch (clock->p2) {
7183 case 5:
7184 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7185 break;
7186 case 7:
7187 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7188 break;
7189 case 10:
7190 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7191 break;
7192 case 14:
7193 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7194 break;
7195 }
7196 if (INTEL_INFO(dev)->gen >= 4)
7197 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7198
190f68c5 7199 if (crtc_state->sdvo_tv_clock)
eb1cbe48 7200 dpll |= PLL_REF_INPUT_TVCLKINBC;
a93e255f 7201 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7202 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7203 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7204 else
7205 dpll |= PLL_REF_INPUT_DREFCLK;
7206
7207 dpll |= DPLL_VCO_ENABLE;
190f68c5 7208 crtc_state->dpll_hw_state.dpll = dpll;
8bcc2795 7209
eb1cbe48 7210 if (INTEL_INFO(dev)->gen >= 4) {
190f68c5 7211 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
ef1b460d 7212 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
190f68c5 7213 crtc_state->dpll_hw_state.dpll_md = dpll_md;
eb1cbe48
DV		 7214 }
7215}
7216
f47709a9 7217static void i8xx_update_pll(struct intel_crtc *crtc,
190f68c5 7218 struct intel_crtc_state *crtc_state,
f47709a9 7219 intel_clock_t *reduced_clock,
eb1cbe48
DV		 7220 int num_connectors)
7221{
f47709a9 7222 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7223 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 7224 u32 dpll;
190f68c5 7225 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7226
190f68c5 7227 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7228
eb1cbe48
DV		 7229 dpll = DPLL_VGA_MODE_DIS;
7230
a93e255f 7231 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 7232 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7233 } else {
7234 if (clock->p1 == 2)
7235 dpll |= PLL_P1_DIVIDE_BY_TWO;
7236 else
7237 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7238 if (clock->p2 == 4)
7239 dpll |= PLL_P2_DIVIDE_BY_4;
7240 }
7241
a93e255f 7242 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
4a33e48d
DV		 7243 dpll |= DPLL_DVO_2X_MODE;
7244
a93e255f 7245 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7246 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7247 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7248 else
7249 dpll |= PLL_REF_INPUT_DREFCLK;
7250
7251 dpll |= DPLL_VCO_ENABLE;
190f68c5 7252 crtc_state->dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 7253}
7254
8a654f3b 7255static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 7256{
7257 struct drm_device *dev = intel_crtc->base.dev;
7258 struct drm_i915_private *dev_priv = dev->dev_private;
7259 enum pipe pipe = intel_crtc->pipe;
6e3c9717 7260 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8a654f3b 7261 struct drm_display_mode *adjusted_mode =
6e3c9717 7262 &intel_crtc->config->base.adjusted_mode;
1caea6e9
VS		 7263 uint32_t crtc_vtotal, crtc_vblank_end;
7264 int vsyncshift = 0;
4d8a62ea
DV		 7265
7266 /* We need to be careful not to changed the adjusted mode, for otherwise
7267 * the hw state checker will get angry at the mismatch. */
7268 crtc_vtotal = adjusted_mode->crtc_vtotal;
7269 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c 7270
609aeaca 7271 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
b0e77b9c 7272 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 7273 crtc_vtotal -= 1;
7274 crtc_vblank_end -= 1;
609aeaca 7275
409ee761 7276 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
609aeaca
VS		 7277 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7278 else
7279 vsyncshift = adjusted_mode->crtc_hsync_start -
7280 adjusted_mode->crtc_htotal / 2;
1caea6e9
VS		 7281 if (vsyncshift < 0)
7282 vsyncshift += adjusted_mode->crtc_htotal;
b0e77b9c
PZ		 7283 }
7284
7285 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 7286 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 7287
fe2b8f9d 7288 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 7289 (adjusted_mode->crtc_hdisplay - 1) |
7290 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 7291 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 7292 (adjusted_mode->crtc_hblank_start - 1) |
7293 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 7294 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 7295 (adjusted_mode->crtc_hsync_start - 1) |
7296 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7297
fe2b8f9d 7298 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 7299 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 7300 ((crtc_vtotal - 1) << 16));
fe2b8f9d 7301 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 7302 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 7303 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 7304 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 7305 (adjusted_mode->crtc_vsync_start - 1) |
7306 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7307
b5e508d4
PZ		 7308 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7309 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7310 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7311 * bits. */
7312 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7313 (pipe == PIPE_B || pipe == PIPE_C))
7314 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7315
b0e77b9c
PZ		 7316 /* pipesrc controls the size that is scaled from, which should
7317 * always be the user's requested size.
7318 */
7319 I915_WRITE(PIPESRC(pipe),
6e3c9717
ACO		 7320 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7321 (intel_crtc->config->pipe_src_h - 1));
b0e77b9c
PZ		 7322}
7323
1bd1bd80 7324static void intel_get_pipe_timings(struct intel_crtc *crtc,
5cec258b 7325 struct intel_crtc_state *pipe_config)
1bd1bd80
DV		 7326{
7327 struct drm_device *dev = crtc->base.dev;
7328 struct drm_i915_private *dev_priv = dev->dev_private;
7329 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7330 uint32_t tmp;
7331
7332 tmp = I915_READ(HTOTAL(cpu_transcoder));
2d112de7
ACO		 7333 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7334 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7335 tmp = I915_READ(HBLANK(cpu_transcoder));
2d112de7
ACO		 7336 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7337 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7338 tmp = I915_READ(HSYNC(cpu_transcoder));
2d112de7
ACO		 7339 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7340 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7341
7342 tmp = I915_READ(VTOTAL(cpu_transcoder));
2d112de7
ACO		 7343 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7344 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7345 tmp = I915_READ(VBLANK(cpu_transcoder));
2d112de7
ACO		 7346 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7347 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7348 tmp = I915_READ(VSYNC(cpu_transcoder));
2d112de7
ACO		 7349 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7350 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7351
7352 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
2d112de7
ACO		 7353 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7354 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7355 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
1bd1bd80
DV		 7356 }
7357
7358 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 7359 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7360 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7361
2d112de7
ACO		 7362 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7363 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 7364}
7365
f6a83288 7366void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5cec258b 7367 struct intel_crtc_state *pipe_config)
babea61d 7368{
2d112de7
ACO		 7369 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7370 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7371 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7372 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
babea61d 7373
2d112de7
ACO		 7374 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7375 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7376 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7377 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
babea61d 7378
2d112de7 7379 mode->flags = pipe_config->base.adjusted_mode.flags;
babea61d 7380
2d112de7
ACO		 7381 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7382 mode->flags |= pipe_config->base.adjusted_mode.flags;
babea61d
JB		 7383}
7384
84b046f3
DV		 7385static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7386{
7387 struct drm_device *dev = intel_crtc->base.dev;
7388 struct drm_i915_private *dev_priv = dev->dev_private;
7389 uint32_t pipeconf;
7390
9f11a9e4 7391 pipeconf = 0;
84b046f3 7392
b6b5d049
VS		 7393 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7394 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7395 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
67c72a12 7396
6e3c9717 7397 if (intel_crtc->config->double_wide)
cf532bb2 7398 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 7399
ff9ce46e
DV		 7400 /* only g4x and later have fancy bpc/dither controls */
7401 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e 7402 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6e3c9717 7403 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
ff9ce46e 7404 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 7405 PIPECONF_DITHER_TYPE_SP;
84b046f3 7406
6e3c9717 7407 switch (intel_crtc->config->pipe_bpp) {
ff9ce46e
DV		 7408 case 18:
7409 pipeconf |= PIPECONF_6BPC;
7410 break;
7411 case 24:
7412 pipeconf |= PIPECONF_8BPC;
7413 break;
7414 case 30:
7415 pipeconf |= PIPECONF_10BPC;
7416 break;
7417 default:
7418 /* Case prevented by intel_choose_pipe_bpp_dither. */
7419 BUG();
84b046f3
DV		 7420 }
7421 }
7422
7423 if (HAS_PIPE_CXSR(dev)) {
7424 if (intel_crtc->lowfreq_avail) {
7425 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7426 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7427 } else {
7428 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 7429 }
7430 }
7431
6e3c9717 7432 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
efc2cfff 7433 if (INTEL_INFO(dev)->gen < 4 ||
409ee761 7434 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
efc2cfff
VS		 7435 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7436 else
7437 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7438 } else
84b046f3
DV		 7439 pipeconf |= PIPECONF_PROGRESSIVE;
7440
6e3c9717 7441 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
9f11a9e4 7442 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 7443
84b046f3
DV		 7444 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7445 POSTING_READ(PIPECONF(intel_crtc->pipe));
7446}
7447
190f68c5
ACO		 7448static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7449 struct intel_crtc_state *crtc_state)
79e53945 7450{
c7653199 7451 struct drm_device *dev = crtc->base.dev;
79e53945 7452 struct drm_i915_private *dev_priv = dev->dev_private;
c751ce4f 7453 int refclk, num_connectors = 0;
652c393a 7454 intel_clock_t clock, reduced_clock;
a16af721 7455 bool ok, has_reduced_clock = false;
e9fd1c02 7456 bool is_lvds = false, is_dsi = false;
5eddb70b 7457 struct intel_encoder *encoder;
d4906093 7458 const intel_limit_t *limit;
55bb9992 7459 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 7460 struct drm_connector *connector;
55bb9992
ACO		 7461 struct drm_connector_state *connector_state;
7462 int i;
79e53945 7463
dd3cd74a
ACO		 7464 memset(&crtc_state->dpll_hw_state, 0,
7465 sizeof(crtc_state->dpll_hw_state));
7466
da3ced29 7467 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 7468 if (connector_state->crtc != &crtc->base)
7469 continue;
7470
7471 encoder = to_intel_encoder(connector_state->best_encoder);
7472
5eddb70b 7473 switch (encoder->type) {
79e53945
JB		 7474 case INTEL_OUTPUT_LVDS:
7475 is_lvds = true;
7476 break;
e9fd1c02
JN		 7477 case INTEL_OUTPUT_DSI:
7478 is_dsi = true;
7479 break;
6847d71b
PZ		 7480 default:
7481 break;
79e53945 7482 }
43565a06 7483
c751ce4f 7484 num_connectors++;
79e53945
JB		 7485 }
7486
f2335330 7487 if (is_dsi)
5b18e57c 7488 return 0;
f2335330 7489
190f68c5 7490 if (!crtc_state->clock_set) {
a93e255f 7491 refclk = i9xx_get_refclk(crtc_state, num_connectors);
79e53945 7492
e9fd1c02
JN		 7493 /*
7494 * Returns a set of divisors for the desired target clock with
7495 * the given refclk, or FALSE. The returned values represent
7496 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7497 * 2) / p1 / p2.
7498 */
a93e255f
ACO		 7499 limit = intel_limit(crtc_state, refclk);
7500 ok = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 7501 crtc_state->port_clock,
e9fd1c02 7502 refclk, NULL, &clock);
f2335330 7503 if (!ok) {
e9fd1c02
JN		 7504 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7505 return -EINVAL;
7506 }
79e53945 7507
f2335330
JN		 7508 if (is_lvds && dev_priv->lvds_downclock_avail) {
7509 /*
7510 * Ensure we match the reduced clock's P to the target
7511 * clock. If the clocks don't match, we can't switch
7512 * the display clock by using the FP0/FP1. In such case
7513 * we will disable the LVDS downclock feature.
7514 */
7515 has_reduced_clock =
a93e255f 7516 dev_priv->display.find_dpll(limit, crtc_state,
f2335330
JN		 7517 dev_priv->lvds_downclock,
7518 refclk, &clock,
7519 &reduced_clock);
7520 }
7521 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 7522 crtc_state->dpll.n = clock.n;
7523 crtc_state->dpll.m1 = clock.m1;
7524 crtc_state->dpll.m2 = clock.m2;
7525 crtc_state->dpll.p1 = clock.p1;
7526 crtc_state->dpll.p2 = clock.p2;
f47709a9 7527 }
7026d4ac 7528
e9fd1c02 7529 if (IS_GEN2(dev)) {
190f68c5 7530 i8xx_update_pll(crtc, crtc_state,
2a8f64ca
VP		 7531 has_reduced_clock ? &reduced_clock : NULL,
7532 num_connectors);
9d556c99 7533 } else if (IS_CHERRYVIEW(dev)) {
190f68c5 7534 chv_update_pll(crtc, crtc_state);
e9fd1c02 7535 } else if (IS_VALLEYVIEW(dev)) {
190f68c5 7536 vlv_update_pll(crtc, crtc_state);
e9fd1c02 7537 } else {
190f68c5 7538 i9xx_update_pll(crtc, crtc_state,
eb1cbe48 7539 has_reduced_clock ? &reduced_clock : NULL,
eba905b2 7540 num_connectors);
e9fd1c02 7541 }
79e53945 7542
c8f7a0db 7543 return 0;
f564048e
EA		 7544}
7545
2fa2fe9a 7546static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5cec258b 7547 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 7548{
7549 struct drm_device *dev = crtc->base.dev;
7550 struct drm_i915_private *dev_priv = dev->dev_private;
7551 uint32_t tmp;
7552
dc9e7dec
VS		 7553 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7554 return;
7555
2fa2fe9a 7556 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 7557 if (!(tmp & PFIT_ENABLE))
7558 return;
2fa2fe9a 7559
06922821 7560 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 7561 if (INTEL_INFO(dev)->gen < 4) {
7562 if (crtc->pipe != PIPE_B)
7563 return;
2fa2fe9a
DV		 7564 } else {
7565 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7566 return;
7567 }
7568
06922821 7569 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 7570 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7571 if (INTEL_INFO(dev)->gen < 5)
7572 pipe_config->gmch_pfit.lvds_border_bits =
7573 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7574}
7575
acbec814 7576static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7577 struct intel_crtc_state *pipe_config)
acbec814
JB		 7578{
7579 struct drm_device *dev = crtc->base.dev;
7580 struct drm_i915_private *dev_priv = dev->dev_private;
7581 int pipe = pipe_config->cpu_transcoder;
7582 intel_clock_t clock;
7583 u32 mdiv;
662c6ecb 7584 int refclk = 100000;
acbec814 7585
f573de5a
SK		 7586 /* In case of MIPI DPLL will not even be used */
7587 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7588 return;
7589
acbec814 7590 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 7591 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
acbec814
JB		 7592 mutex_unlock(&dev_priv->dpio_lock);
7593
7594 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7595 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7596 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7597 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7598 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7599
f646628b 7600 vlv_clock(refclk, &clock);
acbec814 7601
f646628b
VS		 7602 /* clock.dot is the fast clock */
7603 pipe_config->port_clock = clock.dot / 5;
acbec814
JB		 7604}
7605
5724dbd1
DL		 7606static void
7607i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7608 struct intel_initial_plane_config *plane_config)
1ad292b5
JB		 7609{
7610 struct drm_device *dev = crtc->base.dev;
7611 struct drm_i915_private *dev_priv = dev->dev_private;
7612 u32 val, base, offset;
7613 int pipe = crtc->pipe, plane = crtc->plane;
7614 int fourcc, pixel_format;
6761dd31 7615 unsigned int aligned_height;
b113d5ee 7616 struct drm_framebuffer *fb;
1b842c89 7617 struct intel_framebuffer *intel_fb;
1ad292b5 7618
42a7b088
DL		 7619 val = I915_READ(DSPCNTR(plane));
7620 if (!(val & DISPLAY_PLANE_ENABLE))
7621 return;
7622
d9806c9f 7623 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 7624 if (!intel_fb) {
1ad292b5
JB		 7625 DRM_DEBUG_KMS("failed to alloc fb\n");
7626 return;
7627 }
7628
1b842c89
DL		 7629 fb = &intel_fb->base;
7630
18c5247e
DV		 7631 if (INTEL_INFO(dev)->gen >= 4) {
7632 if (val & DISPPLANE_TILED) {
49af449b 7633 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 7634 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7635 }
7636 }
1ad292b5
JB		 7637
7638 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 7639 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 7640 fb->pixel_format = fourcc;
7641 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
1ad292b5
JB		 7642
7643 if (INTEL_INFO(dev)->gen >= 4) {
49af449b 7644 if (plane_config->tiling)
1ad292b5
JB		 7645 offset = I915_READ(DSPTILEOFF(plane));
7646 else
7647 offset = I915_READ(DSPLINOFF(plane));
7648 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7649 } else {
7650 base = I915_READ(DSPADDR(plane));
7651 }
7652 plane_config->base = base;
7653
7654 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 7655 fb->width = ((val >> 16) & 0xfff) + 1;
7656 fb->height = ((val >> 0) & 0xfff) + 1;
1ad292b5
JB		 7657
7658 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 7659 fb->pitches[0] = val & 0xffffffc0;
1ad292b5 7660
b113d5ee 7661 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 7662 fb->pixel_format,
7663 fb->modifier[0]);
1ad292b5 7664
f37b5c2b 7665 plane_config->size = fb->pitches[0] * aligned_height;
1ad292b5 7666
2844a921
DL		 7667 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7668 pipe_name(pipe), plane, fb->width, fb->height,
7669 fb->bits_per_pixel, base, fb->pitches[0],
7670 plane_config->size);
1ad292b5 7671
2d14030b 7672 plane_config->fb = intel_fb;
1ad292b5
JB		 7673}
7674
70b23a98 7675static void chv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7676 struct intel_crtc_state *pipe_config)
70b23a98
VS		 7677{
7678 struct drm_device *dev = crtc->base.dev;
7679 struct drm_i915_private *dev_priv = dev->dev_private;
7680 int pipe = pipe_config->cpu_transcoder;
7681 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7682 intel_clock_t clock;
7683 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
7684 int refclk = 100000;
7685
7686 mutex_lock(&dev_priv->dpio_lock);
7687 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7688 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7689 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7690 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7691 mutex_unlock(&dev_priv->dpio_lock);
7692
7693 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7694 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
7695 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7696 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7697 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7698
7699 chv_clock(refclk, &clock);
7700
7701 /* clock.dot is the fast clock */
7702 pipe_config->port_clock = clock.dot / 5;
7703}
7704
0e8ffe1b 7705static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5cec258b 7706 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 7707{
7708 struct drm_device *dev = crtc->base.dev;
7709 struct drm_i915_private *dev_priv = dev->dev_private;
7710 uint32_t tmp;
7711
f458ebbc
DV		 7712 if (!intel_display_power_is_enabled(dev_priv,
7713 POWER_DOMAIN_PIPE(crtc->pipe)))
b5482bd0
ID		 7714 return false;
7715
e143a21c 7716 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 7717 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 7718
0e8ffe1b
DV		 7719 tmp = I915_READ(PIPECONF(crtc->pipe));
7720 if (!(tmp & PIPECONF_ENABLE))
7721 return false;
7722
42571aef
VS		 7723 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7724 switch (tmp & PIPECONF_BPC_MASK) {
7725 case PIPECONF_6BPC:
7726 pipe_config->pipe_bpp = 18;
7727 break;
7728 case PIPECONF_8BPC:
7729 pipe_config->pipe_bpp = 24;
7730 break;
7731 case PIPECONF_10BPC:
7732 pipe_config->pipe_bpp = 30;
7733 break;
7734 default:
7735 break;
7736 }
7737 }
7738
b5a9fa09
DV		 7739 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
7740 pipe_config->limited_color_range = true;
7741
282740f7
VS		 7742 if (INTEL_INFO(dev)->gen < 4)
7743 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7744
1bd1bd80
DV		 7745 intel_get_pipe_timings(crtc, pipe_config);
7746
2fa2fe9a
DV		 7747 i9xx_get_pfit_config(crtc, pipe_config);
7748
6c49f241
DV		 7749 if (INTEL_INFO(dev)->gen >= 4) {
7750 tmp = I915_READ(DPLL_MD(crtc->pipe));
7751 pipe_config->pixel_multiplier =
7752 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7753 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 7754 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 7755 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7756 tmp = I915_READ(DPLL(crtc->pipe));
7757 pipe_config->pixel_multiplier =
7758 ((tmp & SDVO_MULTIPLIER_MASK)
7759 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7760 } else {
7761 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7762 * port and will be fixed up in the encoder->get_config
7763 * function. */
7764 pipe_config->pixel_multiplier = 1;
7765 }
8bcc2795
DV		 7766 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7767 if (!IS_VALLEYVIEW(dev)) {
1c4e0274
VS		 7768 /*
7769 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7770 * on 830. Filter it out here so that we don't
7771 * report errors due to that.
7772 */
7773 if (IS_I830(dev))
7774 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7775
8bcc2795
DV		 7776 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7777 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 7778 } else {
7779 /* Mask out read-only status bits. */
7780 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7781 DPLL_PORTC_READY_MASK |
7782 DPLL_PORTB_READY_MASK);
8bcc2795 7783 }
6c49f241 7784
70b23a98
VS		 7785 if (IS_CHERRYVIEW(dev))
7786 chv_crtc_clock_get(crtc, pipe_config);
7787 else if (IS_VALLEYVIEW(dev))
acbec814
JB		 7788 vlv_crtc_clock_get(crtc, pipe_config);
7789 else
7790 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 7791
0e8ffe1b
DV		 7792 return true;
7793}
7794
dde86e2d 7795static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 7796{
7797 struct drm_i915_private *dev_priv = dev->dev_private;
13d83a67 7798 struct intel_encoder *encoder;
74cfd7ac 7799 u32 val, final;
13d83a67 7800 bool has_lvds = false;
199e5d79 7801 bool has_cpu_edp = false;
199e5d79 7802 bool has_panel = false;
99eb6a01
KP		 7803 bool has_ck505 = false;
7804 bool can_ssc = false;
13d83a67
JB		 7805
7806 /* We need to take the global config into account */
b2784e15 7807 for_each_intel_encoder(dev, encoder) {
199e5d79
KP		 7808 switch (encoder->type) {
7809 case INTEL_OUTPUT_LVDS:
7810 has_panel = true;
7811 has_lvds = true;
7812 break;
7813 case INTEL_OUTPUT_EDP:
7814 has_panel = true;
2de6905f 7815 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 7816 has_cpu_edp = true;
7817 break;
6847d71b
PZ		 7818 default:
7819 break;
13d83a67
JB		 7820 }
7821 }
7822
99eb6a01 7823 if (HAS_PCH_IBX(dev)) {
41aa3448 7824 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 7825 can_ssc = has_ck505;
7826 } else {
7827 has_ck505 = false;
7828 can_ssc = true;
7829 }
7830
2de6905f
ID		 7831 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
7832 has_panel, has_lvds, has_ck505);
13d83a67
JB		 7833
7834 /* Ironlake: try to setup display ref clock before DPLL
7835 * enabling. This is only under driver's control after
7836 * PCH B stepping, previous chipset stepping should be
7837 * ignoring this setting.
7838 */
74cfd7ac
CW		 7839 val = I915_READ(PCH_DREF_CONTROL);
7840
7841 /* As we must carefully and slowly disable/enable each source in turn,
7842 * compute the final state we want first and check if we need to
7843 * make any changes at all.
7844 */
7845 final = val;
7846 final &= ~DREF_NONSPREAD_SOURCE_MASK;
7847 if (has_ck505)
7848 final |= DREF_NONSPREAD_CK505_ENABLE;
7849 else
7850 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7851
7852 final &= ~DREF_SSC_SOURCE_MASK;
7853 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7854 final &= ~DREF_SSC1_ENABLE;
7855
7856 if (has_panel) {
7857 final |= DREF_SSC_SOURCE_ENABLE;
7858
7859 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7860 final |= DREF_SSC1_ENABLE;
7861
7862 if (has_cpu_edp) {
7863 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7864 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7865 else
7866 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7867 } else
7868 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7869 } else {
7870 final |= DREF_SSC_SOURCE_DISABLE;
7871 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7872 }
7873
7874 if (final == val)
7875 return;
7876
13d83a67 7877 /* Always enable nonspread source */
74cfd7ac 7878 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 7879
99eb6a01 7880 if (has_ck505)
74cfd7ac 7881 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 7882 else
74cfd7ac 7883 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 7884
199e5d79 7885 if (has_panel) {
74cfd7ac
CW		 7886 val &= ~DREF_SSC_SOURCE_MASK;
7887 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 7888
199e5d79 7889 /* SSC must be turned on before enabling the CPU output */
99eb6a01 7890 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 7891 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 7892 val |= DREF_SSC1_ENABLE;
e77166b5 7893 } else
74cfd7ac 7894 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 7895
7896 /* Get SSC going before enabling the outputs */
74cfd7ac 7897 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 7898 POSTING_READ(PCH_DREF_CONTROL);
7899 udelay(200);
7900
74cfd7ac 7901 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 7902
7903 /* Enable CPU source on CPU attached eDP */
199e5d79 7904 if (has_cpu_edp) {
99eb6a01 7905 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 7906 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 7907 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
eba905b2 7908 } else
74cfd7ac 7909 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 7910 } else
74cfd7ac 7911 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 7912
74cfd7ac 7913 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 7914 POSTING_READ(PCH_DREF_CONTROL);
7915 udelay(200);
7916 } else {
7917 DRM_DEBUG_KMS("Disabling SSC entirely\n");
7918
74cfd7ac 7919 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 7920
7921 /* Turn off CPU output */
74cfd7ac 7922 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 7923
74cfd7ac 7924 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 7925 POSTING_READ(PCH_DREF_CONTROL);
7926 udelay(200);
7927
7928 /* Turn off the SSC source */
74cfd7ac
CW		 7929 val &= ~DREF_SSC_SOURCE_MASK;
7930 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 7931
7932 /* Turn off SSC1 */
74cfd7ac 7933 val &= ~DREF_SSC1_ENABLE;
199e5d79 7934
74cfd7ac 7935 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 7936 POSTING_READ(PCH_DREF_CONTROL);
7937 udelay(200);
7938 }
74cfd7ac
CW		 7939
7940 BUG_ON(val != final);
13d83a67
JB		 7941}
7942
f31f2d55 7943static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 7944{
f31f2d55 7945 uint32_t tmp;
dde86e2d 7946
0ff066a9
PZ		 7947 tmp = I915_READ(SOUTH_CHICKEN2);
7948 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7949 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 7950
0ff066a9
PZ		 7951 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
7952 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7953 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 7954
0ff066a9
PZ		 7955 tmp = I915_READ(SOUTH_CHICKEN2);
7956 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7957 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 7958
0ff066a9
PZ		 7959 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
7960 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7961 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 7962}
7963
7964/* WaMPhyProgramming:hsw */
7965static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7966{
7967 uint32_t tmp;
dde86e2d
PZ		 7968
7969 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7970 tmp &= ~(0xFF << 24);
7971 tmp |= (0x12 << 24);
7972 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7973
dde86e2d
PZ		 7974 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7975 tmp |= (1 << 11);
7976 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7977
7978 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7979 tmp |= (1 << 11);
7980 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7981
dde86e2d
PZ		 7982 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7983 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7984 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7985
7986 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7987 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7988 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7989
0ff066a9
PZ		 7990 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7991 tmp &= ~(7 << 13);
7992 tmp |= (5 << 13);
7993 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 7994
0ff066a9
PZ		 7995 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7996 tmp &= ~(7 << 13);
7997 tmp |= (5 << 13);
7998 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 7999
8000 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8001 tmp &= ~0xFF;
8002 tmp |= 0x1C;
8003 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8004
8005 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8006 tmp &= ~0xFF;
8007 tmp |= 0x1C;
8008 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8009
8010 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8011 tmp &= ~(0xFF << 16);
8012 tmp |= (0x1C << 16);
8013 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8014
8015 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8016 tmp &= ~(0xFF << 16);
8017 tmp |= (0x1C << 16);
8018 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8019
0ff066a9
PZ		 8020 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8021 tmp |= (1 << 27);
8022 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 8023
0ff066a9
PZ		 8024 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8025 tmp |= (1 << 27);
8026 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 8027
0ff066a9
PZ		 8028 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8029 tmp &= ~(0xF << 28);
8030 tmp |= (4 << 28);
8031 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 8032
0ff066a9
PZ		 8033 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8034 tmp &= ~(0xF << 28);
8035 tmp |= (4 << 28);
8036 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 8037}
8038
2fa86a1f
PZ		 8039/* Implements 3 different sequences from BSpec chapter "Display iCLK
8040 * Programming" based on the parameters passed:
8041 * - Sequence to enable CLKOUT_DP
8042 * - Sequence to enable CLKOUT_DP without spread
8043 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8044 */
8045static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8046 bool with_fdi)
f31f2d55
PZ		 8047{
8048 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 8049 uint32_t reg, tmp;
8050
8051 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8052 with_spread = true;
8053 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8054 with_fdi, "LP PCH doesn't have FDI\n"))
8055 with_fdi = false;
f31f2d55
PZ		 8056
8057 mutex_lock(&dev_priv->dpio_lock);
8058
8059 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8060 tmp &= ~SBI_SSCCTL_DISABLE;
8061 tmp |= SBI_SSCCTL_PATHALT;
8062 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8063
8064 udelay(24);
8065
2fa86a1f
PZ		 8066 if (with_spread) {
8067 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8068 tmp &= ~SBI_SSCCTL_PATHALT;
8069 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 8070
2fa86a1f
PZ		 8071 if (with_fdi) {
8072 lpt_reset_fdi_mphy(dev_priv);
8073 lpt_program_fdi_mphy(dev_priv);
8074 }
8075 }
dde86e2d 8076
2fa86a1f
PZ		 8077 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8078 SBI_GEN0 : SBI_DBUFF0;
8079 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8080 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8081 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246
DV		 8082
8083 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 8084}
8085
47701c3b
PZ		 8086/* Sequence to disable CLKOUT_DP */
8087static void lpt_disable_clkout_dp(struct drm_device *dev)
8088{
8089 struct drm_i915_private *dev_priv = dev->dev_private;
8090 uint32_t reg, tmp;
8091
8092 mutex_lock(&dev_priv->dpio_lock);
8093
8094 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8095 SBI_GEN0 : SBI_DBUFF0;
8096 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8097 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8098 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8099
8100 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8101 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8102 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8103 tmp |= SBI_SSCCTL_PATHALT;
8104 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8105 udelay(32);
8106 }
8107 tmp |= SBI_SSCCTL_DISABLE;
8108 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8109 }
8110
8111 mutex_unlock(&dev_priv->dpio_lock);
8112}
8113
bf8fa3d3
PZ		 8114static void lpt_init_pch_refclk(struct drm_device *dev)
8115{
bf8fa3d3
PZ		 8116 struct intel_encoder *encoder;
8117 bool has_vga = false;
8118
b2784e15 8119 for_each_intel_encoder(dev, encoder) {
bf8fa3d3
PZ		 8120 switch (encoder->type) {
8121 case INTEL_OUTPUT_ANALOG:
8122 has_vga = true;
8123 break;
6847d71b
PZ		 8124 default:
8125 break;
bf8fa3d3
PZ		 8126 }
8127 }
8128
47701c3b
PZ		 8129 if (has_vga)
8130 lpt_enable_clkout_dp(dev, true, true);
8131 else
8132 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 8133}
8134
dde86e2d
PZ		 8135/*
8136 * Initialize reference clocks when the driver loads
8137 */
8138void intel_init_pch_refclk(struct drm_device *dev)
8139{
8140 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8141 ironlake_init_pch_refclk(dev);
8142 else if (HAS_PCH_LPT(dev))
8143 lpt_init_pch_refclk(dev);
8144}
8145
55bb9992 8146static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
d9d444cb 8147{
55bb9992 8148 struct drm_device *dev = crtc_state->base.crtc->dev;
d9d444cb 8149 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8150 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8151 struct drm_connector *connector;
55bb9992 8152 struct drm_connector_state *connector_state;
d9d444cb 8153 struct intel_encoder *encoder;
55bb9992 8154 int num_connectors = 0, i;
d9d444cb
JB		 8155 bool is_lvds = false;
8156
da3ced29 8157 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8158 if (connector_state->crtc != crtc_state->base.crtc)
8159 continue;
8160
8161 encoder = to_intel_encoder(connector_state->best_encoder);
8162
d9d444cb
JB		 8163 switch (encoder->type) {
8164 case INTEL_OUTPUT_LVDS:
8165 is_lvds = true;
8166 break;
6847d71b
PZ		 8167 default:
8168 break;
d9d444cb
JB		 8169 }
8170 num_connectors++;
8171 }
8172
8173 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b 8174 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
41aa3448 8175 dev_priv->vbt.lvds_ssc_freq);
e91e941b 8176 return dev_priv->vbt.lvds_ssc_freq;
d9d444cb
JB		 8177 }
8178
8179 return 120000;
8180}
8181
6ff93609 8182static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 8183{
c8203565 8184 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 8185 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8186 int pipe = intel_crtc->pipe;
c8203565
PZ		 8187 uint32_t val;
8188
78114071 8189 val = 0;
c8203565 8190
6e3c9717 8191 switch (intel_crtc->config->pipe_bpp) {
c8203565 8192 case 18:
dfd07d72 8193 val |= PIPECONF_6BPC;
c8203565
PZ		 8194 break;
8195 case 24:
dfd07d72 8196 val |= PIPECONF_8BPC;
c8203565
PZ		 8197 break;
8198 case 30:
dfd07d72 8199 val |= PIPECONF_10BPC;
c8203565
PZ		 8200 break;
8201 case 36:
dfd07d72 8202 val |= PIPECONF_12BPC;
c8203565
PZ		 8203 break;
8204 default:
cc769b62
PZ		 8205 /* Case prevented by intel_choose_pipe_bpp_dither. */
8206 BUG();
c8203565
PZ		 8207 }
8208
6e3c9717 8209 if (intel_crtc->config->dither)
c8203565
PZ		 8210 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8211
6e3c9717 8212 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 8213 val |= PIPECONF_INTERLACED_ILK;
8214 else
8215 val |= PIPECONF_PROGRESSIVE;
8216
6e3c9717 8217 if (intel_crtc->config->limited_color_range)
3685a8f3 8218 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 8219
c8203565
PZ		 8220 I915_WRITE(PIPECONF(pipe), val);
8221 POSTING_READ(PIPECONF(pipe));
8222}
8223
86d3efce
VS		 8224/*
8225 * Set up the pipe CSC unit.
8226 *
8227 * Currently only full range RGB to limited range RGB conversion
8228 * is supported, but eventually this should handle various
8229 * RGB<->YCbCr scenarios as well.
8230 */
50f3b016 8231static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 8232{
8233 struct drm_device *dev = crtc->dev;
8234 struct drm_i915_private *dev_priv = dev->dev_private;
8235 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8236 int pipe = intel_crtc->pipe;
8237 uint16_t coeff = 0x7800; /* 1.0 */
8238
8239 /*
8240 * TODO: Check what kind of values actually come out of the pipe
8241 * with these coeff/postoff values and adjust to get the best
8242 * accuracy. Perhaps we even need to take the bpc value into
8243 * consideration.
8244 */
8245
6e3c9717 8246 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8247 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8248
8249 /*
8250 * GY/GU and RY/RU should be the other way around according
8251 * to BSpec, but reality doesn't agree. Just set them up in
8252 * a way that results in the correct picture.
8253 */
8254 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8255 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8256
8257 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8258 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8259
8260 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8261 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8262
8263 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8264 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8265 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8266
8267 if (INTEL_INFO(dev)->gen > 6) {
8268 uint16_t postoff = 0;
8269
6e3c9717 8270 if (intel_crtc->config->limited_color_range)
32cf0cb0 8271 postoff = (16 * (1 << 12) / 255) & 0x1fff;
86d3efce
VS		 8272
8273 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8274 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8275 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8276
8277 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8278 } else {
8279 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8280
6e3c9717 8281 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8282 mode |= CSC_BLACK_SCREEN_OFFSET;
8283
8284 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8285 }
8286}
8287
6ff93609 8288static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38 8289{
756f85cf
PZ		 8290 struct drm_device *dev = crtc->dev;
8291 struct drm_i915_private *dev_priv = dev->dev_private;
ee2b0b38 8292 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
756f85cf 8293 enum pipe pipe = intel_crtc->pipe;
6e3c9717 8294 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee2b0b38
PZ		 8295 uint32_t val;
8296
3eff4faa 8297 val = 0;
ee2b0b38 8298
6e3c9717 8299 if (IS_HASWELL(dev) && intel_crtc->config->dither)
ee2b0b38
PZ		 8300 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8301
6e3c9717 8302 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 8303 val |= PIPECONF_INTERLACED_ILK;
8304 else
8305 val |= PIPECONF_PROGRESSIVE;
8306
702e7a56
PZ		 8307 I915_WRITE(PIPECONF(cpu_transcoder), val);
8308 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 8309
8310 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8311 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
756f85cf 8312
3cdf122c 8313 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
756f85cf
PZ		 8314 val = 0;
8315
6e3c9717 8316 switch (intel_crtc->config->pipe_bpp) {
756f85cf
PZ		 8317 case 18:
8318 val |= PIPEMISC_DITHER_6_BPC;
8319 break;
8320 case 24:
8321 val |= PIPEMISC_DITHER_8_BPC;
8322 break;
8323 case 30:
8324 val |= PIPEMISC_DITHER_10_BPC;
8325 break;
8326 case 36:
8327 val |= PIPEMISC_DITHER_12_BPC;
8328 break;
8329 default:
8330 /* Case prevented by pipe_config_set_bpp. */
8331 BUG();
8332 }
8333
6e3c9717 8334 if (intel_crtc->config->dither)
756f85cf
PZ		 8335 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8336
8337 I915_WRITE(PIPEMISC(pipe), val);
8338 }
ee2b0b38
PZ		 8339}
8340
6591c6e4 8341static bool ironlake_compute_clocks(struct drm_crtc *crtc,
190f68c5 8342 struct intel_crtc_state *crtc_state,
6591c6e4
PZ		 8343 intel_clock_t *clock,
8344 bool *has_reduced_clock,
8345 intel_clock_t *reduced_clock)
8346{
8347 struct drm_device *dev = crtc->dev;
8348 struct drm_i915_private *dev_priv = dev->dev_private;
6591c6e4 8349 int refclk;
d4906093 8350 const intel_limit_t *limit;
a16af721 8351 bool ret, is_lvds = false;
79e53945 8352
a93e255f 8353 is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
79e53945 8354
55bb9992 8355 refclk = ironlake_get_refclk(crtc_state);
79e53945 8356
d4906093
ML		 8357 /*
8358 * Returns a set of divisors for the desired target clock with the given
8359 * refclk, or FALSE. The returned values represent the clock equation:
8360 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8361 */
a93e255f
ACO		 8362 limit = intel_limit(crtc_state, refclk);
8363 ret = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 8364 crtc_state->port_clock,
ee9300bb 8365 refclk, NULL, clock);
6591c6e4
PZ		 8366 if (!ret)
8367 return false;
cda4b7d3 8368
ddc9003c 8369 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 8370 /*
8371 * Ensure we match the reduced clock's P to the target clock.
8372 * If the clocks don't match, we can't switch the display clock
8373 * by using the FP0/FP1. In such case we will disable the LVDS
8374 * downclock feature.
8375 */
ee9300bb 8376 *has_reduced_clock =
a93e255f 8377 dev_priv->display.find_dpll(limit, crtc_state,
ee9300bb
DV		 8378 dev_priv->lvds_downclock,
8379 refclk, clock,
8380 reduced_clock);
652c393a 8381 }
61e9653f 8382
6591c6e4
PZ		 8383 return true;
8384}
8385
d4b1931c
PZ		 8386int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8387{
8388 /*
8389 * Account for spread spectrum to avoid
8390 * oversubscribing the link. Max center spread
8391 * is 2.5%; use 5% for safety's sake.
8392 */
8393 u32 bps = target_clock * bpp * 21 / 20;
619d4d04 8394 return DIV_ROUND_UP(bps, link_bw * 8);
d4b1931c
PZ		 8395}
8396
7429e9d4 8397static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 8398{
7429e9d4 8399 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 8400}
8401
de13a2e3 8402static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
190f68c5 8403 struct intel_crtc_state *crtc_state,
7429e9d4 8404 u32 *fp,
9a7c7890 8405 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 8406{
de13a2e3 8407 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 8408 struct drm_device *dev = crtc->dev;
8409 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8410 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8411 struct drm_connector *connector;
55bb9992
ACO		 8412 struct drm_connector_state *connector_state;
8413 struct intel_encoder *encoder;
de13a2e3 8414 uint32_t dpll;
55bb9992 8415 int factor, num_connectors = 0, i;
09ede541 8416 bool is_lvds = false, is_sdvo = false;
79e53945 8417
da3ced29 8418 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8419 if (connector_state->crtc != crtc_state->base.crtc)
8420 continue;
8421
8422 encoder = to_intel_encoder(connector_state->best_encoder);
8423
8424 switch (encoder->type) {
79e53945
JB		 8425 case INTEL_OUTPUT_LVDS:
8426 is_lvds = true;
8427 break;
8428 case INTEL_OUTPUT_SDVO:
7d57382e 8429 case INTEL_OUTPUT_HDMI:
79e53945 8430 is_sdvo = true;
79e53945 8431 break;
6847d71b
PZ		 8432 default:
8433 break;
79e53945 8434 }
43565a06 8435
c751ce4f 8436 num_connectors++;
79e53945 8437 }
79e53945 8438
c1858123 8439 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 8440 factor = 21;
8441 if (is_lvds) {
8442 if ((intel_panel_use_ssc(dev_priv) &&
e91e941b 8443 dev_priv->vbt.lvds_ssc_freq == 100000) ||
f0b44056 8444 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 8445 factor = 25;
190f68c5 8446 } else if (crtc_state->sdvo_tv_clock)
8febb297 8447 factor = 20;
c1858123 8448
190f68c5 8449 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7d0ac5b7 8450 *fp |= FP_CB_TUNE;
2c07245f 8451
9a7c7890
DV		 8452 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8453 *fp2 |= FP_CB_TUNE;
8454
5eddb70b 8455 dpll = 0;
2c07245f 8456
a07d6787
EA		 8457 if (is_lvds)
8458 dpll |= DPLLB_MODE_LVDS;
8459 else
8460 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 8461
190f68c5 8462 dpll |= (crtc_state->pixel_multiplier - 1)
ef1b460d 8463 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 8464
8465 if (is_sdvo)
4a33e48d 8466 dpll |= DPLL_SDVO_HIGH_SPEED;
190f68c5 8467 if (crtc_state->has_dp_encoder)
4a33e48d 8468 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 8469
a07d6787 8470 /* compute bitmask from p1 value */
190f68c5 8471 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 8472 /* also FPA1 */
190f68c5 8473 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 8474
190f68c5 8475 switch (crtc_state->dpll.p2) {
a07d6787
EA		 8476 case 5:
8477 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8478 break;
8479 case 7:
8480 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8481 break;
8482 case 10:
8483 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8484 break;
8485 case 14:
8486 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8487 break;
79e53945
JB		 8488 }
8489
b4c09f3b 8490 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 8491 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 8492 else
8493 dpll |= PLL_REF_INPUT_DREFCLK;
8494
959e16d6 8495 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 8496}
8497
190f68c5
ACO		 8498static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8499 struct intel_crtc_state *crtc_state)
de13a2e3 8500{
c7653199 8501 struct drm_device *dev = crtc->base.dev;
de13a2e3 8502 intel_clock_t clock, reduced_clock;
cbbab5bd 8503 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 8504 bool ok, has_reduced_clock = false;
8b47047b 8505 bool is_lvds = false;
e2b78267 8506 struct intel_shared_dpll *pll;
de13a2e3 8507
dd3cd74a
ACO		 8508 memset(&crtc_state->dpll_hw_state, 0,
8509 sizeof(crtc_state->dpll_hw_state));
8510
409ee761 8511 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
79e53945 8512
5dc5298b
PZ		 8513 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8514 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 8515
190f68c5 8516 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
de13a2e3 8517 &has_reduced_clock, &reduced_clock);
190f68c5 8518 if (!ok && !crtc_state->clock_set) {
de13a2e3
PZ		 8519 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8520 return -EINVAL;
79e53945 8521 }
f47709a9 8522 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 8523 if (!crtc_state->clock_set) {
8524 crtc_state->dpll.n = clock.n;
8525 crtc_state->dpll.m1 = clock.m1;
8526 crtc_state->dpll.m2 = clock.m2;
8527 crtc_state->dpll.p1 = clock.p1;
8528 crtc_state->dpll.p2 = clock.p2;
f47709a9 8529 }
79e53945 8530
5dc5298b 8531 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
190f68c5
ACO		 8532 if (crtc_state->has_pch_encoder) {
8533 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
cbbab5bd 8534 if (has_reduced_clock)
7429e9d4 8535 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 8536
190f68c5 8537 dpll = ironlake_compute_dpll(crtc, crtc_state,
cbbab5bd
DV		 8538 &fp, &reduced_clock,
8539 has_reduced_clock ? &fp2 : NULL);
8540
190f68c5
ACO		 8541 crtc_state->dpll_hw_state.dpll = dpll;
8542 crtc_state->dpll_hw_state.fp0 = fp;
66e985c0 8543 if (has_reduced_clock)
190f68c5 8544 crtc_state->dpll_hw_state.fp1 = fp2;
66e985c0 8545 else
190f68c5 8546 crtc_state->dpll_hw_state.fp1 = fp;
66e985c0 8547
190f68c5 8548 pll = intel_get_shared_dpll(crtc, crtc_state);
ee7b9f93 8549 if (pll == NULL) {
84f44ce7 8550 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
c7653199 8551 pipe_name(crtc->pipe));
4b645f14
JB		 8552 return -EINVAL;
8553 }
3fb37703 8554 }
79e53945 8555
ab585dea 8556 if (is_lvds && has_reduced_clock)
c7653199 8557 crtc->lowfreq_avail = true;
bcd644e0 8558 else
c7653199 8559 crtc->lowfreq_avail = false;
e2b78267 8560
c8f7a0db 8561 return 0;
79e53945
JB		 8562}
8563
eb14cb74
VS		 8564static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8565 struct intel_link_m_n *m_n)
8566{
8567 struct drm_device *dev = crtc->base.dev;
8568 struct drm_i915_private *dev_priv = dev->dev_private;
8569 enum pipe pipe = crtc->pipe;
8570
8571 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8572 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8573 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8574 & ~TU_SIZE_MASK;
8575 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8576 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8577 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8578}
8579
8580static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8581 enum transcoder transcoder,
b95af8be
VK		 8582 struct intel_link_m_n *m_n,
8583 struct intel_link_m_n *m2_n2)
72419203
DV		 8584{
8585 struct drm_device *dev = crtc->base.dev;
8586 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 8587 enum pipe pipe = crtc->pipe;
72419203 8588
eb14cb74
VS		 8589 if (INTEL_INFO(dev)->gen >= 5) {
8590 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8591 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8592 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8593 & ~TU_SIZE_MASK;
8594 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8595 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8596 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
b95af8be
VK		 8597 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8598 * gen < 8) and if DRRS is supported (to make sure the
8599 * registers are not unnecessarily read).
8600 */
8601 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
6e3c9717 8602 crtc->config->has_drrs) {
b95af8be
VK		 8603 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8604 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8605 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8606 & ~TU_SIZE_MASK;
8607 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8608 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8609 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8610 }
eb14cb74
VS		 8611 } else {
8612 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8613 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8614 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8615 & ~TU_SIZE_MASK;
8616 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8617 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8618 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8619 }
8620}
8621
8622void intel_dp_get_m_n(struct intel_crtc *crtc,
5cec258b 8623 struct intel_crtc_state *pipe_config)
eb14cb74 8624{
681a8504 8625 if (pipe_config->has_pch_encoder)
eb14cb74
VS		 8626 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8627 else
8628 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be
VK		 8629 &pipe_config->dp_m_n,
8630 &pipe_config->dp_m2_n2);
eb14cb74 8631}
72419203 8632
eb14cb74 8633static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5cec258b 8634 struct intel_crtc_state *pipe_config)
eb14cb74
VS		 8635{
8636 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be 8637 &pipe_config->fdi_m_n, NULL);
72419203
DV		 8638}
8639
bd2e244f 8640static void skylake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 8641 struct intel_crtc_state *pipe_config)
bd2e244f
JB		 8642{
8643 struct drm_device *dev = crtc->base.dev;
8644 struct drm_i915_private *dev_priv = dev->dev_private;
a1b2278e
CK		 8645 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8646 uint32_t ps_ctrl = 0;
8647 int id = -1;
8648 int i;
bd2e244f 8649
a1b2278e
CK		 8650 /* find scaler attached to this pipe */
8651 for (i = 0; i < crtc->num_scalers; i++) {
8652 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8653 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8654 id = i;
8655 pipe_config->pch_pfit.enabled = true;
8656 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8657 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8658 break;
8659 }
8660 }
bd2e244f 8661
a1b2278e
CK		 8662 scaler_state->scaler_id = id;
8663 if (id >= 0) {
8664 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8665 } else {
8666 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
bd2e244f
JB		 8667 }
8668}
8669
5724dbd1
DL		 8670static void
8671skylake_get_initial_plane_config(struct intel_crtc *crtc,
8672 struct intel_initial_plane_config *plane_config)
bc8d7dff
DL		 8673{
8674 struct drm_device *dev = crtc->base.dev;
8675 struct drm_i915_private *dev_priv = dev->dev_private;
40f46283 8676 u32 val, base, offset, stride_mult, tiling;
bc8d7dff
DL		 8677 int pipe = crtc->pipe;
8678 int fourcc, pixel_format;
6761dd31 8679 unsigned int aligned_height;
bc8d7dff 8680 struct drm_framebuffer *fb;
1b842c89 8681 struct intel_framebuffer *intel_fb;
bc8d7dff 8682
d9806c9f 8683 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 8684 if (!intel_fb) {
bc8d7dff
DL		 8685 DRM_DEBUG_KMS("failed to alloc fb\n");
8686 return;
8687 }
8688
1b842c89
DL		 8689 fb = &intel_fb->base;
8690
bc8d7dff 8691 val = I915_READ(PLANE_CTL(pipe, 0));
42a7b088
DL		 8692 if (!(val & PLANE_CTL_ENABLE))
8693 goto error;
8694
bc8d7dff
DL		 8695 pixel_format = val & PLANE_CTL_FORMAT_MASK;
8696 fourcc = skl_format_to_fourcc(pixel_format,
8697 val & PLANE_CTL_ORDER_RGBX,
8698 val & PLANE_CTL_ALPHA_MASK);
8699 fb->pixel_format = fourcc;
8700 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8701
40f46283
DL		 8702 tiling = val & PLANE_CTL_TILED_MASK;
8703 switch (tiling) {
8704 case PLANE_CTL_TILED_LINEAR:
8705 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
8706 break;
8707 case PLANE_CTL_TILED_X:
8708 plane_config->tiling = I915_TILING_X;
8709 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8710 break;
8711 case PLANE_CTL_TILED_Y:
8712 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
8713 break;
8714 case PLANE_CTL_TILED_YF:
8715 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
8716 break;
8717 default:
8718 MISSING_CASE(tiling);
8719 goto error;
8720 }
8721
bc8d7dff
DL		 8722 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8723 plane_config->base = base;
8724
8725 offset = I915_READ(PLANE_OFFSET(pipe, 0));
8726
8727 val = I915_READ(PLANE_SIZE(pipe, 0));
8728 fb->height = ((val >> 16) & 0xfff) + 1;
8729 fb->width = ((val >> 0) & 0x1fff) + 1;
8730
8731 val = I915_READ(PLANE_STRIDE(pipe, 0));
40f46283
DL		 8732 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
8733 fb->pixel_format);
bc8d7dff
DL		 8734 fb->pitches[0] = (val & 0x3ff) * stride_mult;
8735
8736 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 8737 fb->pixel_format,
8738 fb->modifier[0]);
bc8d7dff 8739
f37b5c2b 8740 plane_config->size = fb->pitches[0] * aligned_height;
bc8d7dff
DL		 8741
8742 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8743 pipe_name(pipe), fb->width, fb->height,
8744 fb->bits_per_pixel, base, fb->pitches[0],
8745 plane_config->size);
8746
2d14030b 8747 plane_config->fb = intel_fb;
bc8d7dff
DL		 8748 return;
8749
8750error:
8751 kfree(fb);
8752}
8753
2fa2fe9a 8754static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 8755 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 8756{
8757 struct drm_device *dev = crtc->base.dev;
8758 struct drm_i915_private *dev_priv = dev->dev_private;
8759 uint32_t tmp;
8760
8761 tmp = I915_READ(PF_CTL(crtc->pipe));
8762
8763 if (tmp & PF_ENABLE) {
fd4daa9c 8764 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV		 8765 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8766 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 8767
8768 /* We currently do not free assignements of panel fitters on
8769 * ivb/hsw (since we don't use the higher upscaling modes which
8770 * differentiates them) so just WARN about this case for now. */
8771 if (IS_GEN7(dev)) {
8772 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8773 PF_PIPE_SEL_IVB(crtc->pipe));
8774 }
2fa2fe9a 8775 }
79e53945
JB		 8776}
8777
5724dbd1
DL		 8778static void
8779ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8780 struct intel_initial_plane_config *plane_config)
4c6baa59
JB		 8781{
8782 struct drm_device *dev = crtc->base.dev;
8783 struct drm_i915_private *dev_priv = dev->dev_private;
8784 u32 val, base, offset;
aeee5a49 8785 int pipe = crtc->pipe;
4c6baa59 8786 int fourcc, pixel_format;
6761dd31 8787 unsigned int aligned_height;
b113d5ee 8788 struct drm_framebuffer *fb;
1b842c89 8789 struct intel_framebuffer *intel_fb;
4c6baa59 8790
42a7b088
DL		 8791 val = I915_READ(DSPCNTR(pipe));
8792 if (!(val & DISPLAY_PLANE_ENABLE))
8793 return;
8794
d9806c9f 8795 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 8796 if (!intel_fb) {
4c6baa59
JB		 8797 DRM_DEBUG_KMS("failed to alloc fb\n");
8798 return;
8799 }
8800
1b842c89
DL		 8801 fb = &intel_fb->base;
8802
18c5247e
DV		 8803 if (INTEL_INFO(dev)->gen >= 4) {
8804 if (val & DISPPLANE_TILED) {
49af449b 8805 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 8806 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8807 }
8808 }
4c6baa59
JB		 8809
8810 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 8811 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 8812 fb->pixel_format = fourcc;
8813 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
4c6baa59 8814
aeee5a49 8815 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
4c6baa59 8816 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
aeee5a49 8817 offset = I915_READ(DSPOFFSET(pipe));
4c6baa59 8818 } else {
49af449b 8819 if (plane_config->tiling)
aeee5a49 8820 offset = I915_READ(DSPTILEOFF(pipe));
4c6baa59 8821 else
aeee5a49 8822 offset = I915_READ(DSPLINOFF(pipe));
4c6baa59
JB		 8823 }
8824 plane_config->base = base;
8825
8826 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 8827 fb->width = ((val >> 16) & 0xfff) + 1;
8828 fb->height = ((val >> 0) & 0xfff) + 1;
4c6baa59
JB		 8829
8830 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 8831 fb->pitches[0] = val & 0xffffffc0;
4c6baa59 8832
b113d5ee 8833 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 8834 fb->pixel_format,
8835 fb->modifier[0]);
4c6baa59 8836
f37b5c2b 8837 plane_config->size = fb->pitches[0] * aligned_height;
4c6baa59 8838
2844a921
DL		 8839 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8840 pipe_name(pipe), fb->width, fb->height,
8841 fb->bits_per_pixel, base, fb->pitches[0],
8842 plane_config->size);
b113d5ee 8843
2d14030b 8844 plane_config->fb = intel_fb;
4c6baa59
JB		 8845}
8846
0e8ffe1b 8847static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5cec258b 8848 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 8849{
8850 struct drm_device *dev = crtc->base.dev;
8851 struct drm_i915_private *dev_priv = dev->dev_private;
8852 uint32_t tmp;
8853
f458ebbc
DV		 8854 if (!intel_display_power_is_enabled(dev_priv,
8855 POWER_DOMAIN_PIPE(crtc->pipe)))
930e8c9e
PZ		 8856 return false;
8857
e143a21c 8858 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 8859 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 8860
0e8ffe1b
DV		 8861 tmp = I915_READ(PIPECONF(crtc->pipe));
8862 if (!(tmp & PIPECONF_ENABLE))
8863 return false;
8864
42571aef
VS		 8865 switch (tmp & PIPECONF_BPC_MASK) {
8866 case PIPECONF_6BPC:
8867 pipe_config->pipe_bpp = 18;
8868 break;
8869 case PIPECONF_8BPC:
8870 pipe_config->pipe_bpp = 24;
8871 break;
8872 case PIPECONF_10BPC:
8873 pipe_config->pipe_bpp = 30;
8874 break;
8875 case PIPECONF_12BPC:
8876 pipe_config->pipe_bpp = 36;
8877 break;
8878 default:
8879 break;
8880 }
8881
b5a9fa09
DV		 8882 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8883 pipe_config->limited_color_range = true;
8884
ab9412ba 8885 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 8886 struct intel_shared_dpll *pll;
8887
88adfff1
DV		 8888 pipe_config->has_pch_encoder = true;
8889
627eb5a3
DV		 8890 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8891 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8892 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 8893
8894 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 8895
c0d43d62 8896 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 8897 pipe_config->shared_dpll =
8898 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 8899 } else {
8900 tmp = I915_READ(PCH_DPLL_SEL);
8901 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8902 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
8903 else
8904 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
8905 }
66e985c0
DV		 8906
8907 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8908
8909 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8910 &pipe_config->dpll_hw_state));
c93f54cf
DV		 8911
8912 tmp = pipe_config->dpll_hw_state.dpll;
8913 pipe_config->pixel_multiplier =
8914 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8915 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 8916
8917 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 8918 } else {
8919 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 8920 }
8921
1bd1bd80
DV		 8922 intel_get_pipe_timings(crtc, pipe_config);
8923
2fa2fe9a
DV		 8924 ironlake_get_pfit_config(crtc, pipe_config);
8925
0e8ffe1b
DV		 8926 return true;
8927}
8928
be256dc7
PZ		 8929static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8930{
8931 struct drm_device *dev = dev_priv->dev;
be256dc7 8932 struct intel_crtc *crtc;
be256dc7 8933
d3fcc808 8934 for_each_intel_crtc(dev, crtc)
e2c719b7 8935 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
be256dc7
PZ		 8936 pipe_name(crtc->pipe));
8937
e2c719b7
RC		 8938 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8939 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8940 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8941 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8942 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
8943 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
be256dc7 8944 "CPU PWM1 enabled\n");
c5107b87 8945 if (IS_HASWELL(dev))
e2c719b7 8946 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
c5107b87 8947 "CPU PWM2 enabled\n");
e2c719b7 8948 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
be256dc7 8949 "PCH PWM1 enabled\n");
e2c719b7 8950 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
be256dc7 8951 "Utility pin enabled\n");
e2c719b7 8952 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
be256dc7 8953
9926ada1
PZ		 8954 /*
8955 * In theory we can still leave IRQs enabled, as long as only the HPD
8956 * interrupts remain enabled. We used to check for that, but since it's
8957 * gen-specific and since we only disable LCPLL after we fully disable
8958 * the interrupts, the check below should be enough.
8959 */
e2c719b7 8960 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
be256dc7
PZ		 8961}
8962
9ccd5aeb
PZ		 8963static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8964{
8965 struct drm_device *dev = dev_priv->dev;
8966
8967 if (IS_HASWELL(dev))
8968 return I915_READ(D_COMP_HSW);
8969 else
8970 return I915_READ(D_COMP_BDW);
8971}
8972
3c4c9b81
PZ		 8973static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8974{
8975 struct drm_device *dev = dev_priv->dev;
8976
8977 if (IS_HASWELL(dev)) {
8978 mutex_lock(&dev_priv->rps.hw_lock);
8979 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8980 val))
f475dadf 8981 DRM_ERROR("Failed to write to D_COMP\n");
3c4c9b81
PZ		 8982 mutex_unlock(&dev_priv->rps.hw_lock);
8983 } else {
9ccd5aeb
PZ		 8984 I915_WRITE(D_COMP_BDW, val);
8985 POSTING_READ(D_COMP_BDW);
3c4c9b81 8986 }
be256dc7
PZ		 8987}
8988
8989/*
8990 * This function implements pieces of two sequences from BSpec:
8991 * - Sequence for display software to disable LCPLL
8992 * - Sequence for display software to allow package C8+
8993 * The steps implemented here are just the steps that actually touch the LCPLL
8994 * register. Callers should take care of disabling all the display engine
8995 * functions, doing the mode unset, fixing interrupts, etc.
8996 */
6ff58d53
PZ		 8997static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8998 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ		 8999{
9000 uint32_t val;
9001
9002 assert_can_disable_lcpll(dev_priv);
9003
9004 val = I915_READ(LCPLL_CTL);
9005
9006 if (switch_to_fclk) {
9007 val |= LCPLL_CD_SOURCE_FCLK;
9008 I915_WRITE(LCPLL_CTL, val);
9009
9010 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9011 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9012 DRM_ERROR("Switching to FCLK failed\n");
9013
9014 val = I915_READ(LCPLL_CTL);
9015 }
9016
9017 val |= LCPLL_PLL_DISABLE;
9018 I915_WRITE(LCPLL_CTL, val);
9019 POSTING_READ(LCPLL_CTL);
9020
9021 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9022 DRM_ERROR("LCPLL still locked\n");
9023
9ccd5aeb 9024 val = hsw_read_dcomp(dev_priv);
be256dc7 9025 val |= D_COMP_COMP_DISABLE;
3c4c9b81 9026 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9027 ndelay(100);
9028
9ccd5aeb
PZ		 9029 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9030 1))
be256dc7
PZ		 9031 DRM_ERROR("D_COMP RCOMP still in progress\n");
9032
9033 if (allow_power_down) {
9034 val = I915_READ(LCPLL_CTL);
9035 val |= LCPLL_POWER_DOWN_ALLOW;
9036 I915_WRITE(LCPLL_CTL, val);
9037 POSTING_READ(LCPLL_CTL);
9038 }
9039}
9040
9041/*
9042 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9043 * source.
9044 */
6ff58d53 9045static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ		 9046{
9047 uint32_t val;
9048
9049 val = I915_READ(LCPLL_CTL);
9050
9051 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9052 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9053 return;
9054
a8a8bd54
PZ		 9055 /*
9056 * Make sure we're not on PC8 state before disabling PC8, otherwise
9057 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
a8a8bd54 9058 */
59bad947 9059 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
215733fa 9060
be256dc7
PZ		 9061 if (val & LCPLL_POWER_DOWN_ALLOW) {
9062 val &= ~LCPLL_POWER_DOWN_ALLOW;
9063 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 9064 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 9065 }
9066
9ccd5aeb 9067 val = hsw_read_dcomp(dev_priv);
be256dc7
PZ		 9068 val |= D_COMP_COMP_FORCE;
9069 val &= ~D_COMP_COMP_DISABLE;
3c4c9b81 9070 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9071
9072 val = I915_READ(LCPLL_CTL);
9073 val &= ~LCPLL_PLL_DISABLE;
9074 I915_WRITE(LCPLL_CTL, val);
9075
9076 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9077 DRM_ERROR("LCPLL not locked yet\n");
9078
9079 if (val & LCPLL_CD_SOURCE_FCLK) {
9080 val = I915_READ(LCPLL_CTL);
9081 val &= ~LCPLL_CD_SOURCE_FCLK;
9082 I915_WRITE(LCPLL_CTL, val);
9083
9084 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9085 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9086 DRM_ERROR("Switching back to LCPLL failed\n");
9087 }
215733fa 9088
59bad947 9089 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
be256dc7
PZ		 9090}
9091
765dab67
PZ		 9092/*
9093 * Package states C8 and deeper are really deep PC states that can only be
9094 * reached when all the devices on the system allow it, so even if the graphics
9095 * device allows PC8+, it doesn't mean the system will actually get to these
9096 * states. Our driver only allows PC8+ when going into runtime PM.
9097 *
9098 * The requirements for PC8+ are that all the outputs are disabled, the power
9099 * well is disabled and most interrupts are disabled, and these are also
9100 * requirements for runtime PM. When these conditions are met, we manually do
9101 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9102 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9103 * hang the machine.
9104 *
9105 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9106 * the state of some registers, so when we come back from PC8+ we need to
9107 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9108 * need to take care of the registers kept by RC6. Notice that this happens even
9109 * if we don't put the device in PCI D3 state (which is what currently happens
9110 * because of the runtime PM support).
9111 *
9112 * For more, read "Display Sequences for Package C8" on the hardware
9113 * documentation.
9114 */
a14cb6fc 9115void hsw_enable_pc8(struct drm_i915_private *dev_priv)
c67a470b 9116{
c67a470b
PZ		 9117 struct drm_device *dev = dev_priv->dev;
9118 uint32_t val;
9119
c67a470b
PZ		 9120 DRM_DEBUG_KMS("Enabling package C8+\n");
9121
c67a470b
PZ		 9122 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9123 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9124 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9125 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9126 }
9127
9128 lpt_disable_clkout_dp(dev);
c67a470b
PZ		 9129 hsw_disable_lcpll(dev_priv, true, true);
9130}
9131
a14cb6fc 9132void hsw_disable_pc8(struct drm_i915_private *dev_priv)
c67a470b
PZ		 9133{
9134 struct drm_device *dev = dev_priv->dev;
9135 uint32_t val;
9136
c67a470b
PZ		 9137 DRM_DEBUG_KMS("Disabling package C8+\n");
9138
9139 hsw_restore_lcpll(dev_priv);
c67a470b
PZ		 9140 lpt_init_pch_refclk(dev);
9141
9142 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9143 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9144 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9145 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9146 }
9147
9148 intel_prepare_ddi(dev);
c67a470b
PZ		 9149}
9150
a821fc46 9151static void broxton_modeset_global_resources(struct drm_atomic_state *old_state)
f8437dd1 9152{
a821fc46 9153 struct drm_device *dev = old_state->dev;
f8437dd1 9154 struct drm_i915_private *dev_priv = dev->dev_private;
a821fc46 9155 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
f8437dd1
VK		 9156 int req_cdclk;
9157
9158 /* see the comment in valleyview_modeset_global_resources */
9159 if (WARN_ON(max_pixclk < 0))
9160 return;
9161
9162 req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
9163
9164 if (req_cdclk != dev_priv->cdclk_freq)
9165 broxton_set_cdclk(dev, req_cdclk);
9166}
9167
190f68c5
ACO		 9168static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9169 struct intel_crtc_state *crtc_state)
09b4ddf9 9170{
190f68c5 9171 if (!intel_ddi_pll_select(crtc, crtc_state))
6441ab5f 9172 return -EINVAL;
716c2e55 9173
c7653199 9174 crtc->lowfreq_avail = false;
644cef34 9175
c8f7a0db 9176 return 0;
79e53945
JB		 9177}
9178
3760b59c
S		 9179static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9180 enum port port,
9181 struct intel_crtc_state *pipe_config)
9182{
9183 switch (port) {
9184 case PORT_A:
9185 pipe_config->ddi_pll_sel = SKL_DPLL0;
9186 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9187 break;
9188 case PORT_B:
9189 pipe_config->ddi_pll_sel = SKL_DPLL1;
9190 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9191 break;
9192 case PORT_C:
9193 pipe_config->ddi_pll_sel = SKL_DPLL2;
9194 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9195 break;
9196 default:
9197 DRM_ERROR("Incorrect port type\n");
9198 }
9199}
9200
96b7dfb7
S		 9201static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9202 enum port port,
5cec258b 9203 struct intel_crtc_state *pipe_config)
96b7dfb7 9204{
3148ade7 9205 u32 temp, dpll_ctl1;
96b7dfb7
S		 9206
9207 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9208 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9209
9210 switch (pipe_config->ddi_pll_sel) {
3148ade7
DL		 9211 case SKL_DPLL0:
9212 /*
9213 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9214 * of the shared DPLL framework and thus needs to be read out
9215 * separately
9216 */
9217 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9218 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9219 break;
96b7dfb7
S		 9220 case SKL_DPLL1:
9221 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9222 break;
9223 case SKL_DPLL2:
9224 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9225 break;
9226 case SKL_DPLL3:
9227 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9228 break;
96b7dfb7
S		 9229 }
9230}
9231
7d2c8175
DL		 9232static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9233 enum port port,
5cec258b 9234 struct intel_crtc_state *pipe_config)
7d2c8175
DL		 9235{
9236 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9237
9238 switch (pipe_config->ddi_pll_sel) {
9239 case PORT_CLK_SEL_WRPLL1:
9240 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9241 break;
9242 case PORT_CLK_SEL_WRPLL2:
9243 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9244 break;
9245 }
9246}
9247
26804afd 9248static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
5cec258b 9249 struct intel_crtc_state *pipe_config)
26804afd
DV		 9250{
9251 struct drm_device *dev = crtc->base.dev;
9252 struct drm_i915_private *dev_priv = dev->dev_private;
d452c5b6 9253 struct intel_shared_dpll *pll;
26804afd
DV		 9254 enum port port;
9255 uint32_t tmp;
9256
9257 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9258
9259 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9260
96b7dfb7
S		 9261 if (IS_SKYLAKE(dev))
9262 skylake_get_ddi_pll(dev_priv, port, pipe_config);
3760b59c
S		 9263 else if (IS_BROXTON(dev))
9264 bxt_get_ddi_pll(dev_priv, port, pipe_config);
96b7dfb7
S		 9265 else
9266 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9cd86933 9267
d452c5b6
DV		 9268 if (pipe_config->shared_dpll >= 0) {
9269 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9270
9271 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9272 &pipe_config->dpll_hw_state));
9273 }
9274
26804afd
DV		 9275 /*
9276 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9277 * DDI E. So just check whether this pipe is wired to DDI E and whether
9278 * the PCH transcoder is on.
9279 */
ca370455
DL		 9280 if (INTEL_INFO(dev)->gen < 9 &&
9281 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
26804afd
DV		 9282 pipe_config->has_pch_encoder = true;
9283
9284 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9285 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9286 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9287
9288 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9289 }
9290}
9291
0e8ffe1b 9292static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9293 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9294{
9295 struct drm_device *dev = crtc->base.dev;
9296 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 9297 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 9298 uint32_t tmp;
9299
f458ebbc 9300 if (!intel_display_power_is_enabled(dev_priv,
b5482bd0
ID		 9301 POWER_DOMAIN_PIPE(crtc->pipe)))
9302 return false;
9303
e143a21c 9304 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 9305 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9306
eccb140b
DV		 9307 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9308 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9309 enum pipe trans_edp_pipe;
9310 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9311 default:
9312 WARN(1, "unknown pipe linked to edp transcoder\n");
9313 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9314 case TRANS_DDI_EDP_INPUT_A_ON:
9315 trans_edp_pipe = PIPE_A;
9316 break;
9317 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9318 trans_edp_pipe = PIPE_B;
9319 break;
9320 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9321 trans_edp_pipe = PIPE_C;
9322 break;
9323 }
9324
9325 if (trans_edp_pipe == crtc->pipe)
9326 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9327 }
9328
f458ebbc 9329 if (!intel_display_power_is_enabled(dev_priv,
eccb140b 9330 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 9331 return false;
9332
eccb140b 9333 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 9334 if (!(tmp & PIPECONF_ENABLE))
9335 return false;
9336
26804afd 9337 haswell_get_ddi_port_state(crtc, pipe_config);
627eb5a3 9338
1bd1bd80
DV		 9339 intel_get_pipe_timings(crtc, pipe_config);
9340
a1b2278e
CK		 9341 if (INTEL_INFO(dev)->gen >= 9) {
9342 skl_init_scalers(dev, crtc, pipe_config);
9343 }
9344
2fa2fe9a 9345 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
af99ceda
CK		 9346
9347 if (INTEL_INFO(dev)->gen >= 9) {
9348 pipe_config->scaler_state.scaler_id = -1;
9349 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9350 }
9351
bd2e244f 9352 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
ff6d9f55 9353 if (INTEL_INFO(dev)->gen == 9)
bd2e244f 9354 skylake_get_pfit_config(crtc, pipe_config);
ff6d9f55 9355 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 9356 ironlake_get_pfit_config(crtc, pipe_config);
ff6d9f55
JB		 9357 else
9358 MISSING_CASE(INTEL_INFO(dev)->gen);
bd2e244f 9359 }
88adfff1 9360
e59150dc
JB		 9361 if (IS_HASWELL(dev))
9362 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9363 (I915_READ(IPS_CTL) & IPS_ENABLE);
42db64ef 9364
ebb69c95
CT		 9365 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9366 pipe_config->pixel_multiplier =
9367 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9368 } else {
9369 pipe_config->pixel_multiplier = 1;
9370 }
6c49f241 9371
0e8ffe1b
DV		 9372 return true;
9373}
9374
560b85bb
CW		 9375static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9376{
9377 struct drm_device *dev = crtc->dev;
9378 struct drm_i915_private *dev_priv = dev->dev_private;
9379 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dc41c154 9380 uint32_t cntl = 0, size = 0;
560b85bb 9381
dc41c154 9382 if (base) {
3dd512fb
MR		 9383 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9384 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
dc41c154
VS		 9385 unsigned int stride = roundup_pow_of_two(width) * 4;
9386
9387 switch (stride) {
9388 default:
9389 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9390 width, stride);
9391 stride = 256;
9392 /* fallthrough */
9393 case 256:
9394 case 512:
9395 case 1024:
9396 case 2048:
9397 break;
4b0e333e
CW		 9398 }
9399
dc41c154
VS		 9400 cntl |= CURSOR_ENABLE |
9401 CURSOR_GAMMA_ENABLE |
9402 CURSOR_FORMAT_ARGB |
9403 CURSOR_STRIDE(stride);
9404
9405 size = (height << 12) | width;
4b0e333e 9406 }
560b85bb 9407
dc41c154
VS		 9408 if (intel_crtc->cursor_cntl != 0 &&
9409 (intel_crtc->cursor_base != base ||
9410 intel_crtc->cursor_size != size ||
9411 intel_crtc->cursor_cntl != cntl)) {
9412 /* On these chipsets we can only modify the base/size/stride
9413 * whilst the cursor is disabled.
9414 */
9415 I915_WRITE(_CURACNTR, 0);
4b0e333e 9416 POSTING_READ(_CURACNTR);
dc41c154 9417 intel_crtc->cursor_cntl = 0;
4b0e333e 9418 }
560b85bb 9419
99d1f387 9420 if (intel_crtc->cursor_base != base) {
9db4a9c7 9421 I915_WRITE(_CURABASE, base);
99d1f387
VS		 9422 intel_crtc->cursor_base = base;
9423 }
4726e0b0 9424
dc41c154
VS		 9425 if (intel_crtc->cursor_size != size) {
9426 I915_WRITE(CURSIZE, size);
9427 intel_crtc->cursor_size = size;
4b0e333e 9428 }
560b85bb 9429
4b0e333e 9430 if (intel_crtc->cursor_cntl != cntl) {
4b0e333e
CW		 9431 I915_WRITE(_CURACNTR, cntl);
9432 POSTING_READ(_CURACNTR);
4b0e333e 9433 intel_crtc->cursor_cntl = cntl;
560b85bb 9434 }
560b85bb
CW		 9435}
9436
560b85bb 9437static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
65a21cd6
JB		 9438{
9439 struct drm_device *dev = crtc->dev;
9440 struct drm_i915_private *dev_priv = dev->dev_private;
9441 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9442 int pipe = intel_crtc->pipe;
4b0e333e
CW		 9443 uint32_t cntl;
9444
9445 cntl = 0;
9446 if (base) {
9447 cntl = MCURSOR_GAMMA_ENABLE;
3dd512fb 9448 switch (intel_crtc->base.cursor->state->crtc_w) {
4726e0b0
SK		 9449 case 64:
9450 cntl |= CURSOR_MODE_64_ARGB_AX;
9451 break;
9452 case 128:
9453 cntl |= CURSOR_MODE_128_ARGB_AX;
9454 break;
9455 case 256:
9456 cntl |= CURSOR_MODE_256_ARGB_AX;
9457 break;
9458 default:
3dd512fb 9459 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
4726e0b0 9460 return;
65a21cd6 9461 }
4b0e333e 9462 cntl |= pipe << 28; /* Connect to correct pipe */
47bf17a7
VS		 9463
9464 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9465 cntl |= CURSOR_PIPE_CSC_ENABLE;
4b0e333e 9466 }
65a21cd6 9467
8e7d688b 9468 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
4398ad45
VS		 9469 cntl |= CURSOR_ROTATE_180;
9470
4b0e333e
CW		 9471 if (intel_crtc->cursor_cntl != cntl) {
9472 I915_WRITE(CURCNTR(pipe), cntl);
9473 POSTING_READ(CURCNTR(pipe));
9474 intel_crtc->cursor_cntl = cntl;
65a21cd6 9475 }
4b0e333e 9476
65a21cd6 9477 /* and commit changes on next vblank */
5efb3e28
VS		 9478 I915_WRITE(CURBASE(pipe), base);
9479 POSTING_READ(CURBASE(pipe));
99d1f387
VS		 9480
9481 intel_crtc->cursor_base = base;
65a21cd6
JB		 9482}
9483
cda4b7d3 9484/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 9485static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9486 bool on)
cda4b7d3
CW		 9487{
9488 struct drm_device *dev = crtc->dev;
9489 struct drm_i915_private *dev_priv = dev->dev_private;
9490 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9491 int pipe = intel_crtc->pipe;
3d7d6510
MR		 9492 int x = crtc->cursor_x;
9493 int y = crtc->cursor_y;
d6e4db15 9494 u32 base = 0, pos = 0;
cda4b7d3 9495
d6e4db15 9496 if (on)
cda4b7d3 9497 base = intel_crtc->cursor_addr;
cda4b7d3 9498
6e3c9717 9499 if (x >= intel_crtc->config->pipe_src_w)
d6e4db15
VS		 9500 base = 0;
9501
6e3c9717 9502 if (y >= intel_crtc->config->pipe_src_h)
cda4b7d3
CW		 9503 base = 0;
9504
9505 if (x < 0) {
3dd512fb 9506 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
cda4b7d3
CW		 9507 base = 0;
9508
9509 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9510 x = -x;
9511 }
9512 pos |= x << CURSOR_X_SHIFT;
9513
9514 if (y < 0) {
3dd512fb 9515 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
cda4b7d3
CW		 9516 base = 0;
9517
9518 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9519 y = -y;
9520 }
9521 pos |= y << CURSOR_Y_SHIFT;
9522
4b0e333e 9523 if (base == 0 && intel_crtc->cursor_base == 0)
cda4b7d3
CW		 9524 return;
9525
5efb3e28
VS		 9526 I915_WRITE(CURPOS(pipe), pos);
9527
4398ad45
VS		 9528 /* ILK+ do this automagically */
9529 if (HAS_GMCH_DISPLAY(dev) &&
8e7d688b 9530 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
3dd512fb
MR		 9531 base += (intel_crtc->base.cursor->state->crtc_h *
9532 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
4398ad45
VS		 9533 }
9534
8ac54669 9535 if (IS_845G(dev) || IS_I865G(dev))
5efb3e28
VS		 9536 i845_update_cursor(crtc, base);
9537 else
9538 i9xx_update_cursor(crtc, base);
cda4b7d3
CW		 9539}
9540
dc41c154
VS		 9541static bool cursor_size_ok(struct drm_device *dev,
9542 uint32_t width, uint32_t height)
9543{
9544 if (width == 0 || height == 0)
9545 return false;
9546
9547 /*
9548 * 845g/865g are special in that they are only limited by
9549 * the width of their cursors, the height is arbitrary up to
9550 * the precision of the register. Everything else requires
9551 * square cursors, limited to a few power-of-two sizes.
9552 */
9553 if (IS_845G(dev) || IS_I865G(dev)) {
9554 if ((width & 63) != 0)
9555 return false;
9556
9557 if (width > (IS_845G(dev) ? 64 : 512))
9558 return false;
9559
9560 if (height > 1023)
9561 return false;
9562 } else {
9563 switch (width | height) {
9564 case 256:
9565 case 128:
9566 if (IS_GEN2(dev))
9567 return false;
9568 case 64:
9569 break;
9570 default:
9571 return false;
9572 }
9573 }
9574
9575 return true;
9576}
9577
79e53945 9578static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 9579 u16 *blue, uint32_t start, uint32_t size)
79e53945 9580{
7203425a 9581 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 9582 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 9583
7203425a 9584 for (i = start; i < end; i++) {
79e53945
JB		 9585 intel_crtc->lut_r[i] = red[i] >> 8;
9586 intel_crtc->lut_g[i] = green[i] >> 8;
9587 intel_crtc->lut_b[i] = blue[i] >> 8;
9588 }
9589
9590 intel_crtc_load_lut(crtc);
9591}
9592
79e53945
JB		 9593/* VESA 640x480x72Hz mode to set on the pipe */
9594static struct drm_display_mode load_detect_mode = {
9595 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9596 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9597};
9598
a8bb6818
DV		 9599struct drm_framebuffer *
9600__intel_framebuffer_create(struct drm_device *dev,
9601 struct drm_mode_fb_cmd2 *mode_cmd,
9602 struct drm_i915_gem_object *obj)
d2dff872
CW		 9603{
9604 struct intel_framebuffer *intel_fb;
9605 int ret;
9606
9607 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9608 if (!intel_fb) {
6ccb81f2 9609 drm_gem_object_unreference(&obj->base);
d2dff872
CW		 9610 return ERR_PTR(-ENOMEM);
9611 }
9612
9613 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
dd4916c5
DV		 9614 if (ret)
9615 goto err;
d2dff872
CW		 9616
9617 return &intel_fb->base;
dd4916c5 9618err:
6ccb81f2 9619 drm_gem_object_unreference(&obj->base);
dd4916c5
DV		 9620 kfree(intel_fb);
9621
9622 return ERR_PTR(ret);
d2dff872
CW		 9623}
9624
b5ea642a 9625static struct drm_framebuffer *
a8bb6818
DV		 9626intel_framebuffer_create(struct drm_device *dev,
9627 struct drm_mode_fb_cmd2 *mode_cmd,
9628 struct drm_i915_gem_object *obj)
9629{
9630 struct drm_framebuffer *fb;
9631 int ret;
9632
9633 ret = i915_mutex_lock_interruptible(dev);
9634 if (ret)
9635 return ERR_PTR(ret);
9636 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
9637 mutex_unlock(&dev->struct_mutex);
9638
9639 return fb;
9640}
9641
d2dff872
CW		 9642static u32
9643intel_framebuffer_pitch_for_width(int width, int bpp)
9644{
9645 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
9646 return ALIGN(pitch, 64);
9647}
9648
9649static u32
9650intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
9651{
9652 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
1267a26b 9653 return PAGE_ALIGN(pitch * mode->vdisplay);
d2dff872
CW		 9654}
9655
9656static struct drm_framebuffer *
9657intel_framebuffer_create_for_mode(struct drm_device *dev,
9658 struct drm_display_mode *mode,
9659 int depth, int bpp)
9660{
9661 struct drm_i915_gem_object *obj;
0fed39bd 9662 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 9663
9664 obj = i915_gem_alloc_object(dev,
9665 intel_framebuffer_size_for_mode(mode, bpp));
9666 if (obj == NULL)
9667 return ERR_PTR(-ENOMEM);
9668
9669 mode_cmd.width = mode->hdisplay;
9670 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 9671 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
9672 bpp);
5ca0c34a 9673 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 9674
9675 return intel_framebuffer_create(dev, &mode_cmd, obj);
9676}
9677
9678static struct drm_framebuffer *
9679mode_fits_in_fbdev(struct drm_device *dev,
9680 struct drm_display_mode *mode)
9681{
4520f53a 9682#ifdef CONFIG_DRM_I915_FBDEV
d2dff872
CW		 9683 struct drm_i915_private *dev_priv = dev->dev_private;
9684 struct drm_i915_gem_object *obj;
9685 struct drm_framebuffer *fb;
9686
4c0e5528 9687 if (!dev_priv->fbdev)
d2dff872
CW		 9688 return NULL;
9689
4c0e5528 9690 if (!dev_priv->fbdev->fb)
d2dff872
CW		 9691 return NULL;
9692
4c0e5528
DV		 9693 obj = dev_priv->fbdev->fb->obj;
9694 BUG_ON(!obj);
9695
8bcd4553 9696 fb = &dev_priv->fbdev->fb->base;
01f2c773
VS		 9697 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
9698 fb->bits_per_pixel))
d2dff872
CW		 9699 return NULL;
9700
01f2c773 9701 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 9702 return NULL;
9703
9704 return fb;
4520f53a
DV		 9705#else
9706 return NULL;
9707#endif
d2dff872
CW		 9708}
9709
d3a40d1b
ACO		 9710static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
9711 struct drm_crtc *crtc,
9712 struct drm_display_mode *mode,
9713 struct drm_framebuffer *fb,
9714 int x, int y)
9715{
9716 struct drm_plane_state *plane_state;
9717 int hdisplay, vdisplay;
9718 int ret;
9719
9720 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
9721 if (IS_ERR(plane_state))
9722 return PTR_ERR(plane_state);
9723
9724 if (mode)
9725 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
9726 else
9727 hdisplay = vdisplay = 0;
9728
9729 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
9730 if (ret)
9731 return ret;
9732 drm_atomic_set_fb_for_plane(plane_state, fb);
9733 plane_state->crtc_x = 0;
9734 plane_state->crtc_y = 0;
9735 plane_state->crtc_w = hdisplay;
9736 plane_state->crtc_h = vdisplay;
9737 plane_state->src_x = x << 16;
9738 plane_state->src_y = y << 16;
9739 plane_state->src_w = hdisplay << 16;
9740 plane_state->src_h = vdisplay << 16;
9741
9742 return 0;
9743}
9744
d2434ab7 9745bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 9746 struct drm_display_mode *mode,
51fd371b
RC		 9747 struct intel_load_detect_pipe *old,
9748 struct drm_modeset_acquire_ctx *ctx)
79e53945
JB		 9749{
9750 struct intel_crtc *intel_crtc;
d2434ab7
DV		 9751 struct intel_encoder *intel_encoder =
9752 intel_attached_encoder(connector);
79e53945 9753 struct drm_crtc *possible_crtc;
4ef69c7a 9754 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 9755 struct drm_crtc *crtc = NULL;
9756 struct drm_device *dev = encoder->dev;
94352cf9 9757 struct drm_framebuffer *fb;
51fd371b 9758 struct drm_mode_config *config = &dev->mode_config;
83a57153 9759 struct drm_atomic_state *state = NULL;
944b0c76 9760 struct drm_connector_state *connector_state;
4be07317 9761 struct intel_crtc_state *crtc_state;
51fd371b 9762 int ret, i = -1;
79e53945 9763
d2dff872 9764 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 9765 connector->base.id, connector->name,
8e329a03 9766 encoder->base.id, encoder->name);
d2dff872 9767
51fd371b
RC		 9768retry:
9769 ret = drm_modeset_lock(&config->connection_mutex, ctx);
9770 if (ret)
9771 goto fail_unlock;
6e9f798d 9772
79e53945
JB		 9773 /*
9774 * Algorithm gets a little messy:
7a5e4805 9775 *
79e53945
JB		 9776 * - if the connector already has an assigned crtc, use it (but make
9777 * sure it's on first)
7a5e4805 9778 *
79e53945
JB		 9779 * - try to find the first unused crtc that can drive this connector,
9780 * and use that if we find one
79e53945
JB		 9781 */
9782
9783 /* See if we already have a CRTC for this connector */
9784 if (encoder->crtc) {
9785 crtc = encoder->crtc;
8261b191 9786
51fd371b 9787 ret = drm_modeset_lock(&crtc->mutex, ctx);
4d02e2de
DV		 9788 if (ret)
9789 goto fail_unlock;
9790 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
51fd371b
RC		 9791 if (ret)
9792 goto fail_unlock;
7b24056b 9793
24218aac 9794 old->dpms_mode = connector->dpms;
8261b191
CW		 9795 old->load_detect_temp = false;
9796
9797 /* Make sure the crtc and connector are running */
24218aac
DV		 9798 if (connector->dpms != DRM_MODE_DPMS_ON)
9799 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 9800
7173188d 9801 return true;
79e53945
JB		 9802 }
9803
9804 /* Find an unused one (if possible) */
70e1e0ec 9805 for_each_crtc(dev, possible_crtc) {
79e53945
JB		 9806 i++;
9807 if (!(encoder->possible_crtcs & (1 << i)))
9808 continue;
83d65738 9809 if (possible_crtc->state->enable)
a459249c
VS		 9810 continue;
9811 /* This can occur when applying the pipe A quirk on resume. */
9812 if (to_intel_crtc(possible_crtc)->new_enabled)
9813 continue;
9814
9815 crtc = possible_crtc;
9816 break;
79e53945
JB		 9817 }
9818
9819 /*
9820 * If we didn't find an unused CRTC, don't use any.
9821 */
9822 if (!crtc) {
7173188d 9823 DRM_DEBUG_KMS("no pipe available for load-detect\n");
51fd371b 9824 goto fail_unlock;
79e53945
JB		 9825 }
9826
51fd371b
RC		 9827 ret = drm_modeset_lock(&crtc->mutex, ctx);
9828 if (ret)
4d02e2de
DV		 9829 goto fail_unlock;
9830 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9831 if (ret)
51fd371b 9832 goto fail_unlock;
fc303101
DV		 9833 intel_encoder->new_crtc = to_intel_crtc(crtc);
9834 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 9835
9836 intel_crtc = to_intel_crtc(crtc);
412b61d8 9837 intel_crtc->new_enabled = true;
24218aac 9838 old->dpms_mode = connector->dpms;
8261b191 9839 old->load_detect_temp = true;
d2dff872 9840 old->release_fb = NULL;
79e53945 9841
83a57153
ACO		 9842 state = drm_atomic_state_alloc(dev);
9843 if (!state)
9844 return false;
9845
9846 state->acquire_ctx = ctx;
9847
944b0c76
ACO		 9848 connector_state = drm_atomic_get_connector_state(state, connector);
9849 if (IS_ERR(connector_state)) {
9850 ret = PTR_ERR(connector_state);
9851 goto fail;
9852 }
9853
9854 connector_state->crtc = crtc;
9855 connector_state->best_encoder = &intel_encoder->base;
9856
4be07317
ACO		 9857 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9858 if (IS_ERR(crtc_state)) {
9859 ret = PTR_ERR(crtc_state);
9860 goto fail;
9861 }
9862
49d6fa21 9863 crtc_state->base.active = crtc_state->base.enable = true;
4be07317 9864
6492711d
CW		 9865 if (!mode)
9866 mode = &load_detect_mode;
79e53945 9867
d2dff872
CW		 9868 /* We need a framebuffer large enough to accommodate all accesses
9869 * that the plane may generate whilst we perform load detection.
9870 * We can not rely on the fbcon either being present (we get called
9871 * during its initialisation to detect all boot displays, or it may
9872 * not even exist) or that it is large enough to satisfy the
9873 * requested mode.
9874 */
94352cf9
DV		 9875 fb = mode_fits_in_fbdev(dev, mode);
9876 if (fb == NULL) {
d2dff872 9877 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 9878 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
9879 old->release_fb = fb;
d2dff872
CW		 9880 } else
9881 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 9882 if (IS_ERR(fb)) {
d2dff872 9883 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
412b61d8 9884 goto fail;
79e53945 9885 }
79e53945 9886
d3a40d1b
ACO		 9887 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
9888 if (ret)
9889 goto fail;
9890
8c7b5ccb
ACO		 9891 drm_mode_copy(&crtc_state->base.mode, mode);
9892
9893 if (intel_set_mode(crtc, state)) {
6492711d 9894 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 9895 if (old->release_fb)
9896 old->release_fb->funcs->destroy(old->release_fb);
412b61d8 9897 goto fail;
79e53945 9898 }
9128b040 9899 crtc->primary->crtc = crtc;
7173188d 9900
79e53945 9901 /* let the connector get through one full cycle before testing */
9d0498a2 9902 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 9903 return true;
412b61d8
VS		 9904
9905 fail:
83d65738 9906 intel_crtc->new_enabled = crtc->state->enable;
51fd371b 9907fail_unlock:
e5d958ef
ACO		 9908 drm_atomic_state_free(state);
9909 state = NULL;
83a57153 9910
51fd371b
RC		 9911 if (ret == -EDEADLK) {
9912 drm_modeset_backoff(ctx);
9913 goto retry;
9914 }
9915
412b61d8 9916 return false;
79e53945
JB		 9917}
9918
d2434ab7 9919void intel_release_load_detect_pipe(struct drm_connector *connector,
49172fee
ACO		 9920 struct intel_load_detect_pipe *old,
9921 struct drm_modeset_acquire_ctx *ctx)
79e53945 9922{
83a57153 9923 struct drm_device *dev = connector->dev;
d2434ab7
DV		 9924 struct intel_encoder *intel_encoder =
9925 intel_attached_encoder(connector);
4ef69c7a 9926 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 9927 struct drm_crtc *crtc = encoder->crtc;
412b61d8 9928 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83a57153 9929 struct drm_atomic_state *state;
944b0c76 9930 struct drm_connector_state *connector_state;
4be07317 9931 struct intel_crtc_state *crtc_state;
d3a40d1b 9932 int ret;
79e53945 9933
d2dff872 9934 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 9935 connector->base.id, connector->name,
8e329a03 9936 encoder->base.id, encoder->name);
d2dff872 9937
8261b191 9938 if (old->load_detect_temp) {
83a57153 9939 state = drm_atomic_state_alloc(dev);
944b0c76
ACO		 9940 if (!state)
9941 goto fail;
83a57153
ACO		 9942
9943 state->acquire_ctx = ctx;
9944
944b0c76
ACO		 9945 connector_state = drm_atomic_get_connector_state(state, connector);
9946 if (IS_ERR(connector_state))
9947 goto fail;
9948
4be07317
ACO		 9949 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9950 if (IS_ERR(crtc_state))
9951 goto fail;
9952
fc303101
DV		 9953 to_intel_connector(connector)->new_encoder = NULL;
9954 intel_encoder->new_crtc = NULL;
412b61d8 9955 intel_crtc->new_enabled = false;
944b0c76
ACO		 9956
9957 connector_state->best_encoder = NULL;
9958 connector_state->crtc = NULL;
9959
49d6fa21 9960 crtc_state->base.enable = crtc_state->base.active = false;
4be07317 9961
d3a40d1b
ACO		 9962 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
9963 0, 0);
9964 if (ret)
9965 goto fail;
9966
2bfb4627
ACO		 9967 ret = intel_set_mode(crtc, state);
9968 if (ret)
9969 goto fail;
d2dff872 9970
36206361
DV		 9971 if (old->release_fb) {
9972 drm_framebuffer_unregister_private(old->release_fb);
9973 drm_framebuffer_unreference(old->release_fb);
9974 }
d2dff872 9975
0622a53c 9976 return;
79e53945
JB		 9977 }
9978
c751ce4f 9979 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 9980 if (old->dpms_mode != DRM_MODE_DPMS_ON)
9981 connector->funcs->dpms(connector, old->dpms_mode);
944b0c76
ACO		 9982
9983 return;
9984fail:
9985 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
9986 drm_atomic_state_free(state);
79e53945
JB		 9987}
9988
da4a1efa 9989static int i9xx_pll_refclk(struct drm_device *dev,
5cec258b 9990 const struct intel_crtc_state *pipe_config)
da4a1efa
VS		 9991{
9992 struct drm_i915_private *dev_priv = dev->dev_private;
9993 u32 dpll = pipe_config->dpll_hw_state.dpll;
9994
9995 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
e91e941b 9996 return dev_priv->vbt.lvds_ssc_freq;
da4a1efa
VS		 9997 else if (HAS_PCH_SPLIT(dev))
9998 return 120000;
9999 else if (!IS_GEN2(dev))
10000 return 96000;
10001 else
10002 return 48000;
10003}
10004
79e53945 10005/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc 10006static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 10007 struct intel_crtc_state *pipe_config)
79e53945 10008{
f1f644dc 10009 struct drm_device *dev = crtc->base.dev;
79e53945 10010 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 10011 int pipe = pipe_config->cpu_transcoder;
293623f7 10012 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 10013 u32 fp;
10014 intel_clock_t clock;
da4a1efa 10015 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 10016
10017 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 10018 fp = pipe_config->dpll_hw_state.fp0;
79e53945 10019 else
293623f7 10020 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 10021
10022 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 10023 if (IS_PINEVIEW(dev)) {
10024 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10025 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 10026 } else {
10027 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10028 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10029 }
10030
a6c45cf0 10031 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 10032 if (IS_PINEVIEW(dev))
10033 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10034 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 10035 else
10036 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 10037 DPLL_FPA01_P1_POST_DIV_SHIFT);
10038
10039 switch (dpll & DPLL_MODE_MASK) {
10040 case DPLLB_MODE_DAC_SERIAL:
10041 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10042 5 : 10;
10043 break;
10044 case DPLLB_MODE_LVDS:
10045 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10046 7 : 14;
10047 break;
10048 default:
28c97730 10049 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 10050 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 10051 return;
79e53945
JB		 10052 }
10053
ac58c3f0 10054 if (IS_PINEVIEW(dev))
da4a1efa 10055 pineview_clock(refclk, &clock);
ac58c3f0 10056 else
da4a1efa 10057 i9xx_clock(refclk, &clock);
79e53945 10058 } else {
0fb58223 10059 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
b1c560d1 10060 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
79e53945
JB		 10061
10062 if (is_lvds) {
10063 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10064 DPLL_FPA01_P1_POST_DIV_SHIFT);
b1c560d1
VS		 10065
10066 if (lvds & LVDS_CLKB_POWER_UP)
10067 clock.p2 = 7;
10068 else
10069 clock.p2 = 14;
79e53945
JB		 10070 } else {
10071 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10072 clock.p1 = 2;
10073 else {
10074 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10075 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10076 }
10077 if (dpll & PLL_P2_DIVIDE_BY_4)
10078 clock.p2 = 4;
10079 else
10080 clock.p2 = 2;
79e53945 10081 }
da4a1efa
VS		 10082
10083 i9xx_clock(refclk, &clock);
79e53945
JB		 10084 }
10085
18442d08
VS		 10086 /*
10087 * This value includes pixel_multiplier. We will use
241bfc38 10088 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS		 10089 * encoder's get_config() function.
10090 */
10091 pipe_config->port_clock = clock.dot;
f1f644dc
JB		 10092}
10093
6878da05
VS		 10094int intel_dotclock_calculate(int link_freq,
10095 const struct intel_link_m_n *m_n)
f1f644dc 10096{
f1f644dc
JB		 10097 /*
10098 * The calculation for the data clock is:
1041a02f 10099 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 10100 * But we want to avoid losing precison if possible, so:
1041a02f 10101 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 10102 *
10103 * and the link clock is simpler:
1041a02f 10104 * link_clock = (m * link_clock) / n
f1f644dc
JB		 10105 */
10106
6878da05
VS		 10107 if (!m_n->link_n)
10108 return 0;
f1f644dc 10109
6878da05
VS		 10110 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10111}
f1f644dc 10112
18442d08 10113static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 10114 struct intel_crtc_state *pipe_config)
6878da05
VS		 10115{
10116 struct drm_device *dev = crtc->base.dev;
79e53945 10117
18442d08
VS		 10118 /* read out port_clock from the DPLL */
10119 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 10120
f1f644dc 10121 /*
18442d08 10122 * This value does not include pixel_multiplier.
241bfc38 10123 * We will check that port_clock and adjusted_mode.crtc_clock
18442d08
VS		 10124 * agree once we know their relationship in the encoder's
10125 * get_config() function.
79e53945 10126 */
2d112de7 10127 pipe_config->base.adjusted_mode.crtc_clock =
18442d08
VS		 10128 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10129 &pipe_config->fdi_m_n);
79e53945
JB		 10130}
10131
10132/** Returns the currently programmed mode of the given pipe. */
10133struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10134 struct drm_crtc *crtc)
10135{
548f245b 10136 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 10137 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 10138 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
79e53945 10139 struct drm_display_mode *mode;
5cec258b 10140 struct intel_crtc_state pipe_config;
fe2b8f9d
PZ		 10141 int htot = I915_READ(HTOTAL(cpu_transcoder));
10142 int hsync = I915_READ(HSYNC(cpu_transcoder));
10143 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10144 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 10145 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 10146
10147 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10148 if (!mode)
10149 return NULL;
10150
f1f644dc
JB		 10151 /*
10152 * Construct a pipe_config sufficient for getting the clock info
10153 * back out of crtc_clock_get.
10154 *
10155 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10156 * to use a real value here instead.
10157 */
293623f7 10158 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 10159 pipe_config.pixel_multiplier = 1;
293623f7
VS		 10160 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10161 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10162 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 10163 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10164
773ae034 10165 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB		 10166 mode->hdisplay = (htot & 0xffff) + 1;
10167 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10168 mode->hsync_start = (hsync & 0xffff) + 1;
10169 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10170 mode->vdisplay = (vtot & 0xffff) + 1;
10171 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10172 mode->vsync_start = (vsync & 0xffff) + 1;
10173 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10174
10175 drm_mode_set_name(mode);
79e53945
JB		 10176
10177 return mode;
10178}
10179
652c393a
JB		 10180static void intel_decrease_pllclock(struct drm_crtc *crtc)
10181{
10182 struct drm_device *dev = crtc->dev;
fbee40df 10183 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 10184 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 10185
baff296c 10186 if (!HAS_GMCH_DISPLAY(dev))
652c393a
JB		 10187 return;
10188
10189 if (!dev_priv->lvds_downclock_avail)
10190 return;
10191
10192 /*
10193 * Since this is called by a timer, we should never get here in
10194 * the manual case.
10195 */
10196 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 10197 int pipe = intel_crtc->pipe;
10198 int dpll_reg = DPLL(pipe);
10199 int dpll;
f6e5b160 10200
44d98a61 10201 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 10202
8ac5a6d5 10203 assert_panel_unlocked(dev_priv, pipe);
652c393a 10204
dc257cf1 10205 dpll = I915_READ(dpll_reg);
652c393a
JB		 10206 dpll |= DISPLAY_RATE_SELECT_FPA1;
10207 I915_WRITE(dpll_reg, dpll);
9d0498a2 10208 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 10209 dpll = I915_READ(dpll_reg);
10210 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 10211 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 10212 }
10213
10214}
10215
f047e395
CW		 10216void intel_mark_busy(struct drm_device *dev)
10217{
c67a470b
PZ		 10218 struct drm_i915_private *dev_priv = dev->dev_private;
10219
f62a0076
CW		 10220 if (dev_priv->mm.busy)
10221 return;
10222
43694d69 10223 intel_runtime_pm_get(dev_priv);
c67a470b 10224 i915_update_gfx_val(dev_priv);
43cf3bf0
CW		 10225 if (INTEL_INFO(dev)->gen >= 6)
10226 gen6_rps_busy(dev_priv);
f62a0076 10227 dev_priv->mm.busy = true;
f047e395
CW		 10228}
10229
10230void intel_mark_idle(struct drm_device *dev)
652c393a 10231{
c67a470b 10232 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 10233 struct drm_crtc *crtc;
652c393a 10234
f62a0076
CW		 10235 if (!dev_priv->mm.busy)
10236 return;
10237
10238 dev_priv->mm.busy = false;
10239
70e1e0ec 10240 for_each_crtc(dev, crtc) {
f4510a27 10241 if (!crtc->primary->fb)
652c393a
JB		 10242 continue;
10243
725a5b54 10244 intel_decrease_pllclock(crtc);
652c393a 10245 }
b29c19b6 10246
3d13ef2e 10247 if (INTEL_INFO(dev)->gen >= 6)
b29c19b6 10248 gen6_rps_idle(dev->dev_private);
bb4cdd53 10249
43694d69 10250 intel_runtime_pm_put(dev_priv);
652c393a
JB		 10251}
10252
79e53945
JB		 10253static void intel_crtc_destroy(struct drm_crtc *crtc)
10254{
10255 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 10256 struct drm_device *dev = crtc->dev;
10257 struct intel_unpin_work *work;
67e77c5a 10258
5e2d7afc 10259 spin_lock_irq(&dev->event_lock);
67e77c5a
DV		 10260 work = intel_crtc->unpin_work;
10261 intel_crtc->unpin_work = NULL;
5e2d7afc 10262 spin_unlock_irq(&dev->event_lock);
67e77c5a
DV		 10263
10264 if (work) {
10265 cancel_work_sync(&work->work);
10266 kfree(work);
10267 }
79e53945
JB		 10268
10269 drm_crtc_cleanup(crtc);
67e77c5a 10270
79e53945
JB		 10271 kfree(intel_crtc);
10272}
10273
6b95a207
KH		 10274static void intel_unpin_work_fn(struct work_struct *__work)
10275{
10276 struct intel_unpin_work *work =
10277 container_of(__work, struct intel_unpin_work, work);
b4a98e57 10278 struct drm_device *dev = work->crtc->dev;
f99d7069 10279 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
6b95a207 10280
b4a98e57 10281 mutex_lock(&dev->struct_mutex);
82bc3b2d 10282 intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state);
05394f39 10283 drm_gem_object_unreference(&work->pending_flip_obj->base);
d9e86c0e 10284
7ff0ebcc 10285 intel_fbc_update(dev);
f06cc1b9
JH		 10286
10287 if (work->flip_queued_req)
146d84f0 10288 i915_gem_request_assign(&work->flip_queued_req, NULL);
b4a98e57
CW		 10289 mutex_unlock(&dev->struct_mutex);
10290
f99d7069 10291 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
89ed88ba 10292 drm_framebuffer_unreference(work->old_fb);
f99d7069 10293
b4a98e57
CW		 10294 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
10295 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
10296
6b95a207
KH		 10297 kfree(work);
10298}
10299
1afe3e9d 10300static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 10301 struct drm_crtc *crtc)
6b95a207 10302{
6b95a207
KH		 10303 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10304 struct intel_unpin_work *work;
6b95a207
KH		 10305 unsigned long flags;
10306
10307 /* Ignore early vblank irqs */
10308 if (intel_crtc == NULL)
10309 return;
10310
f326038a
DV		 10311 /*
10312 * This is called both by irq handlers and the reset code (to complete
10313 * lost pageflips) so needs the full irqsave spinlocks.
10314 */
6b95a207
KH		 10315 spin_lock_irqsave(&dev->event_lock, flags);
10316 work = intel_crtc->unpin_work;
e7d841ca
CW		 10317
10318 /* Ensure we don't miss a work->pending update ... */
10319 smp_rmb();
10320
10321 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 10322 spin_unlock_irqrestore(&dev->event_lock, flags);
10323 return;
10324 }
10325
d6bbafa1 10326 page_flip_completed(intel_crtc);
0af7e4df 10327
6b95a207 10328 spin_unlock_irqrestore(&dev->event_lock, flags);
6b95a207
KH		 10329}
10330
1afe3e9d
JB		 10331void intel_finish_page_flip(struct drm_device *dev, int pipe)
10332{
fbee40df 10333 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10334 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10335
49b14a5c 10336 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10337}
10338
10339void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10340{
fbee40df 10341 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10342 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10343
49b14a5c 10344 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10345}
10346
75f7f3ec
VS		 10347/* Is 'a' after or equal to 'b'? */
10348static bool g4x_flip_count_after_eq(u32 a, u32 b)
10349{
10350 return !((a - b) & 0x80000000);
10351}
10352
10353static bool page_flip_finished(struct intel_crtc *crtc)
10354{
10355 struct drm_device *dev = crtc->base.dev;
10356 struct drm_i915_private *dev_priv = dev->dev_private;
10357
bdfa7542
VS		 10358 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10359 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10360 return true;
10361
75f7f3ec
VS		 10362 /*
10363 * The relevant registers doen't exist on pre-ctg.
10364 * As the flip done interrupt doesn't trigger for mmio
10365 * flips on gmch platforms, a flip count check isn't
10366 * really needed there. But since ctg has the registers,
10367 * include it in the check anyway.
10368 */
10369 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10370 return true;
10371
10372 /*
10373 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10374 * used the same base address. In that case the mmio flip might
10375 * have completed, but the CS hasn't even executed the flip yet.
10376 *
10377 * A flip count check isn't enough as the CS might have updated
10378 * the base address just after start of vblank, but before we
10379 * managed to process the interrupt. This means we'd complete the
10380 * CS flip too soon.
10381 *
10382 * Combining both checks should get us a good enough result. It may
10383 * still happen that the CS flip has been executed, but has not
10384 * yet actually completed. But in case the base address is the same
10385 * anyway, we don't really care.
10386 */
10387 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10388 crtc->unpin_work->gtt_offset &&
10389 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10390 crtc->unpin_work->flip_count);
10391}
10392
6b95a207
KH		 10393void intel_prepare_page_flip(struct drm_device *dev, int plane)
10394{
fbee40df 10395 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 10396 struct intel_crtc *intel_crtc =
10397 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10398 unsigned long flags;
10399
f326038a
DV		 10400
10401 /*
10402 * This is called both by irq handlers and the reset code (to complete
10403 * lost pageflips) so needs the full irqsave spinlocks.
10404 *
10405 * NB: An MMIO update of the plane base pointer will also
e7d841ca
CW		 10406 * generate a page-flip completion irq, i.e. every modeset
10407 * is also accompanied by a spurious intel_prepare_page_flip().
10408 */
6b95a207 10409 spin_lock_irqsave(&dev->event_lock, flags);
75f7f3ec 10410 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
e7d841ca 10411 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 10412 spin_unlock_irqrestore(&dev->event_lock, flags);
10413}
10414
eba905b2 10415static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
e7d841ca
CW		 10416{
10417 /* Ensure that the work item is consistent when activating it ... */
10418 smp_wmb();
10419 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10420 /* and that it is marked active as soon as the irq could fire. */
10421 smp_wmb();
10422}
10423
8c9f3aaf
JB		 10424static int intel_gen2_queue_flip(struct drm_device *dev,
10425 struct drm_crtc *crtc,
10426 struct drm_framebuffer *fb,
ed8d1975 10427 struct drm_i915_gem_object *obj,
a4872ba6 10428 struct intel_engine_cs *ring,
ed8d1975 10429 uint32_t flags)
8c9f3aaf 10430{
8c9f3aaf 10431 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10432 u32 flip_mask;
10433 int ret;
10434
6d90c952 10435 ret = intel_ring_begin(ring, 6);
8c9f3aaf 10436 if (ret)
4fa62c89 10437 return ret;
8c9f3aaf
JB		 10438
10439 /* Can't queue multiple flips, so wait for the previous
10440 * one to finish before executing the next.
10441 */
10442 if (intel_crtc->plane)
10443 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10444 else
10445 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10446 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10447 intel_ring_emit(ring, MI_NOOP);
10448 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10449 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10450 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10451 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952 10452 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 10453
10454 intel_mark_page_flip_active(intel_crtc);
09246732 10455 __intel_ring_advance(ring);
83d4092b 10456 return 0;
8c9f3aaf
JB		 10457}
10458
10459static int intel_gen3_queue_flip(struct drm_device *dev,
10460 struct drm_crtc *crtc,
10461 struct drm_framebuffer *fb,
ed8d1975 10462 struct drm_i915_gem_object *obj,
a4872ba6 10463 struct intel_engine_cs *ring,
ed8d1975 10464 uint32_t flags)
8c9f3aaf 10465{
8c9f3aaf 10466 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10467 u32 flip_mask;
10468 int ret;
10469
6d90c952 10470 ret = intel_ring_begin(ring, 6);
8c9f3aaf 10471 if (ret)
4fa62c89 10472 return ret;
8c9f3aaf
JB		 10473
10474 if (intel_crtc->plane)
10475 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10476 else
10477 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10478 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10479 intel_ring_emit(ring, MI_NOOP);
10480 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10481 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10482 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10483 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952
DV		 10484 intel_ring_emit(ring, MI_NOOP);
10485
e7d841ca 10486 intel_mark_page_flip_active(intel_crtc);
09246732 10487 __intel_ring_advance(ring);
83d4092b 10488 return 0;
8c9f3aaf
JB		 10489}
10490
10491static int intel_gen4_queue_flip(struct drm_device *dev,
10492 struct drm_crtc *crtc,
10493 struct drm_framebuffer *fb,
ed8d1975 10494 struct drm_i915_gem_object *obj,
a4872ba6 10495 struct intel_engine_cs *ring,
ed8d1975 10496 uint32_t flags)
8c9f3aaf
JB		 10497{
10498 struct drm_i915_private *dev_priv = dev->dev_private;
10499 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10500 uint32_t pf, pipesrc;
10501 int ret;
10502
6d90c952 10503 ret = intel_ring_begin(ring, 4);
8c9f3aaf 10504 if (ret)
4fa62c89 10505 return ret;
8c9f3aaf
JB		 10506
10507 /* i965+ uses the linear or tiled offsets from the
10508 * Display Registers (which do not change across a page-flip)
10509 * so we need only reprogram the base address.
10510 */
6d90c952
DV		 10511 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10512 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10513 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10514 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
c2c75131 10515 obj->tiling_mode);
8c9f3aaf
JB		 10516
10517 /* XXX Enabling the panel-fitter across page-flip is so far
10518 * untested on non-native modes, so ignore it for now.
10519 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10520 */
10521 pf = 0;
10522 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10523 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 10524
10525 intel_mark_page_flip_active(intel_crtc);
09246732 10526 __intel_ring_advance(ring);
83d4092b 10527 return 0;
8c9f3aaf
JB		 10528}
10529
10530static int intel_gen6_queue_flip(struct drm_device *dev,
10531 struct drm_crtc *crtc,
10532 struct drm_framebuffer *fb,
ed8d1975 10533 struct drm_i915_gem_object *obj,
a4872ba6 10534 struct intel_engine_cs *ring,
ed8d1975 10535 uint32_t flags)
8c9f3aaf
JB		 10536{
10537 struct drm_i915_private *dev_priv = dev->dev_private;
10538 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10539 uint32_t pf, pipesrc;
10540 int ret;
10541
6d90c952 10542 ret = intel_ring_begin(ring, 4);
8c9f3aaf 10543 if (ret)
4fa62c89 10544 return ret;
8c9f3aaf 10545
6d90c952
DV		 10546 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10547 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10548 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
75f7f3ec 10549 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
8c9f3aaf 10550
dc257cf1
DV		 10551 /* Contrary to the suggestions in the documentation,
10552 * "Enable Panel Fitter" does not seem to be required when page
10553 * flipping with a non-native mode, and worse causes a normal
10554 * modeset to fail.
10555 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10556 */
10557 pf = 0;
8c9f3aaf 10558 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10559 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 10560
10561 intel_mark_page_flip_active(intel_crtc);
09246732 10562 __intel_ring_advance(ring);
83d4092b 10563 return 0;
8c9f3aaf
JB		 10564}
10565
7c9017e5
JB		 10566static int intel_gen7_queue_flip(struct drm_device *dev,
10567 struct drm_crtc *crtc,
10568 struct drm_framebuffer *fb,
ed8d1975 10569 struct drm_i915_gem_object *obj,
a4872ba6 10570 struct intel_engine_cs *ring,
ed8d1975 10571 uint32_t flags)
7c9017e5 10572{
7c9017e5 10573 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cb05d8de 10574 uint32_t plane_bit = 0;
ffe74d75
CW		 10575 int len, ret;
10576
eba905b2 10577 switch (intel_crtc->plane) {
cb05d8de
DV		 10578 case PLANE_A:
10579 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10580 break;
10581 case PLANE_B:
10582 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10583 break;
10584 case PLANE_C:
10585 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10586 break;
10587 default:
10588 WARN_ONCE(1, "unknown plane in flip command\n");
4fa62c89 10589 return -ENODEV;
cb05d8de
DV		 10590 }
10591
ffe74d75 10592 len = 4;
f476828a 10593 if (ring->id == RCS) {
ffe74d75 10594 len += 6;
f476828a
DL		 10595 /*
10596 * On Gen 8, SRM is now taking an extra dword to accommodate
10597 * 48bits addresses, and we need a NOOP for the batch size to
10598 * stay even.
10599 */
10600 if (IS_GEN8(dev))
10601 len += 2;
10602 }
ffe74d75 10603
f66fab8e
VS		 10604 /*
10605 * BSpec MI_DISPLAY_FLIP for IVB:
10606 * "The full packet must be contained within the same cache line."
10607 *
10608 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
10609 * cacheline, if we ever start emitting more commands before
10610 * the MI_DISPLAY_FLIP we may need to first emit everything else,
10611 * then do the cacheline alignment, and finally emit the
10612 * MI_DISPLAY_FLIP.
10613 */
10614 ret = intel_ring_cacheline_align(ring);
10615 if (ret)
4fa62c89 10616 return ret;
f66fab8e 10617
ffe74d75 10618 ret = intel_ring_begin(ring, len);
7c9017e5 10619 if (ret)
4fa62c89 10620 return ret;
7c9017e5 10621
ffe74d75
CW		 10622 /* Unmask the flip-done completion message. Note that the bspec says that
10623 * we should do this for both the BCS and RCS, and that we must not unmask
10624 * more than one flip event at any time (or ensure that one flip message
10625 * can be sent by waiting for flip-done prior to queueing new flips).
10626 * Experimentation says that BCS works despite DERRMR masking all
10627 * flip-done completion events and that unmasking all planes at once
10628 * for the RCS also doesn't appear to drop events. Setting the DERRMR
10629 * to zero does lead to lockups within MI_DISPLAY_FLIP.
10630 */
10631 if (ring->id == RCS) {
10632 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
10633 intel_ring_emit(ring, DERRMR);
10634 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
10635 DERRMR_PIPEB_PRI_FLIP_DONE |
10636 DERRMR_PIPEC_PRI_FLIP_DONE));
f476828a
DL		 10637 if (IS_GEN8(dev))
10638 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
10639 MI_SRM_LRM_GLOBAL_GTT);
10640 else
10641 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
10642 MI_SRM_LRM_GLOBAL_GTT);
ffe74d75
CW		 10643 intel_ring_emit(ring, DERRMR);
10644 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
f476828a
DL		 10645 if (IS_GEN8(dev)) {
10646 intel_ring_emit(ring, 0);
10647 intel_ring_emit(ring, MI_NOOP);
10648 }
ffe74d75
CW		 10649 }
10650
cb05d8de 10651 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 10652 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
75f7f3ec 10653 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
7c9017e5 10654 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 10655
10656 intel_mark_page_flip_active(intel_crtc);
09246732 10657 __intel_ring_advance(ring);
83d4092b 10658 return 0;
7c9017e5
JB		 10659}
10660
84c33a64
SG		 10661static bool use_mmio_flip(struct intel_engine_cs *ring,
10662 struct drm_i915_gem_object *obj)
10663{
10664 /*
10665 * This is not being used for older platforms, because
10666 * non-availability of flip done interrupt forces us to use
10667 * CS flips. Older platforms derive flip done using some clever
10668 * tricks involving the flip_pending status bits and vblank irqs.
10669 * So using MMIO flips there would disrupt this mechanism.
10670 */
10671
8e09bf83
CW		 10672 if (ring == NULL)
10673 return true;
10674
84c33a64
SG		 10675 if (INTEL_INFO(ring->dev)->gen < 5)
10676 return false;
10677
10678 if (i915.use_mmio_flip < 0)
10679 return false;
10680 else if (i915.use_mmio_flip > 0)
10681 return true;
14bf993e
OM		 10682 else if (i915.enable_execlists)
10683 return true;
84c33a64 10684 else
41c52415 10685 return ring != i915_gem_request_get_ring(obj->last_read_req);
84c33a64
SG		 10686}
10687
ff944564
DL		 10688static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
10689{
10690 struct drm_device *dev = intel_crtc->base.dev;
10691 struct drm_i915_private *dev_priv = dev->dev_private;
10692 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
ff944564
DL		 10693 const enum pipe pipe = intel_crtc->pipe;
10694 u32 ctl, stride;
10695
10696 ctl = I915_READ(PLANE_CTL(pipe, 0));
10697 ctl &= ~PLANE_CTL_TILED_MASK;
2ebef630
TU		 10698 switch (fb->modifier[0]) {
10699 case DRM_FORMAT_MOD_NONE:
10700 break;
10701 case I915_FORMAT_MOD_X_TILED:
ff944564 10702 ctl |= PLANE_CTL_TILED_X;
2ebef630
TU		 10703 break;
10704 case I915_FORMAT_MOD_Y_TILED:
10705 ctl |= PLANE_CTL_TILED_Y;
10706 break;
10707 case I915_FORMAT_MOD_Yf_TILED:
10708 ctl |= PLANE_CTL_TILED_YF;
10709 break;
10710 default:
10711 MISSING_CASE(fb->modifier[0]);
10712 }
ff944564
DL		 10713
10714 /*
10715 * The stride is either expressed as a multiple of 64 bytes chunks for
10716 * linear buffers or in number of tiles for tiled buffers.
10717 */
2ebef630
TU		 10718 stride = fb->pitches[0] /
10719 intel_fb_stride_alignment(dev, fb->modifier[0],
10720 fb->pixel_format);
ff944564
DL		 10721
10722 /*
10723 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
10724 * PLANE_SURF updates, the update is then guaranteed to be atomic.
10725 */
10726 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
10727 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
10728
10729 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
10730 POSTING_READ(PLANE_SURF(pipe, 0));
10731}
10732
10733static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
84c33a64
SG		 10734{
10735 struct drm_device *dev = intel_crtc->base.dev;
10736 struct drm_i915_private *dev_priv = dev->dev_private;
10737 struct intel_framebuffer *intel_fb =
10738 to_intel_framebuffer(intel_crtc->base.primary->fb);
10739 struct drm_i915_gem_object *obj = intel_fb->obj;
10740 u32 dspcntr;
10741 u32 reg;
10742
84c33a64
SG		 10743 reg = DSPCNTR(intel_crtc->plane);
10744 dspcntr = I915_READ(reg);
10745
c5d97472
DL		 10746 if (obj->tiling_mode != I915_TILING_NONE)
10747 dspcntr |= DISPPLANE_TILED;
10748 else
10749 dspcntr &= ~DISPPLANE_TILED;
10750
84c33a64
SG		 10751 I915_WRITE(reg, dspcntr);
10752
10753 I915_WRITE(DSPSURF(intel_crtc->plane),
10754 intel_crtc->unpin_work->gtt_offset);
10755 POSTING_READ(DSPSURF(intel_crtc->plane));
84c33a64 10756
ff944564
DL		 10757}
10758
10759/*
10760 * XXX: This is the temporary way to update the plane registers until we get
10761 * around to using the usual plane update functions for MMIO flips
10762 */
10763static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
10764{
10765 struct drm_device *dev = intel_crtc->base.dev;
10766 bool atomic_update;
10767 u32 start_vbl_count;
10768
10769 intel_mark_page_flip_active(intel_crtc);
10770
10771 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
10772
10773 if (INTEL_INFO(dev)->gen >= 9)
10774 skl_do_mmio_flip(intel_crtc);
10775 else
10776 /* use_mmio_flip() retricts MMIO flips to ilk+ */
10777 ilk_do_mmio_flip(intel_crtc);
10778
9362c7c5
ACO		 10779 if (atomic_update)
10780 intel_pipe_update_end(intel_crtc, start_vbl_count);
84c33a64
SG		 10781}
10782
9362c7c5 10783static void intel_mmio_flip_work_func(struct work_struct *work)
84c33a64 10784{
b2cfe0ab
CW		 10785 struct intel_mmio_flip *mmio_flip =
10786 container_of(work, struct intel_mmio_flip, work);
84c33a64 10787
b2cfe0ab
CW		 10788 if (mmio_flip->rq)
10789 WARN_ON(__i915_wait_request(mmio_flip->rq,
10790 mmio_flip->crtc->reset_counter,
10791 false, NULL, NULL));
84c33a64 10792
b2cfe0ab
CW		 10793 intel_do_mmio_flip(mmio_flip->crtc);
10794
10795 i915_gem_request_unreference__unlocked(mmio_flip->rq);
10796 kfree(mmio_flip);
84c33a64
SG		 10797}
10798
10799static int intel_queue_mmio_flip(struct drm_device *dev,
10800 struct drm_crtc *crtc,
10801 struct drm_framebuffer *fb,
10802 struct drm_i915_gem_object *obj,
10803 struct intel_engine_cs *ring,
10804 uint32_t flags)
10805{
b2cfe0ab
CW		 10806 struct intel_mmio_flip *mmio_flip;
10807
10808 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
10809 if (mmio_flip == NULL)
10810 return -ENOMEM;
84c33a64 10811
b2cfe0ab
CW		 10812 mmio_flip->rq = i915_gem_request_reference(obj->last_write_req);
10813 mmio_flip->crtc = to_intel_crtc(crtc);
536f5b5e 10814
b2cfe0ab
CW		 10815 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
10816 schedule_work(&mmio_flip->work);
84c33a64 10817
84c33a64
SG		 10818 return 0;
10819}
10820
8c9f3aaf
JB		 10821static int intel_default_queue_flip(struct drm_device *dev,
10822 struct drm_crtc *crtc,
10823 struct drm_framebuffer *fb,
ed8d1975 10824 struct drm_i915_gem_object *obj,
a4872ba6 10825 struct intel_engine_cs *ring,
ed8d1975 10826 uint32_t flags)
8c9f3aaf
JB		 10827{
10828 return -ENODEV;
10829}
10830
d6bbafa1
CW		 10831static bool __intel_pageflip_stall_check(struct drm_device *dev,
10832 struct drm_crtc *crtc)
10833{
10834 struct drm_i915_private *dev_priv = dev->dev_private;
10835 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10836 struct intel_unpin_work *work = intel_crtc->unpin_work;
10837 u32 addr;
10838
10839 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
10840 return true;
10841
10842 if (!work->enable_stall_check)
10843 return false;
10844
10845 if (work->flip_ready_vblank == 0) {
3a8a946e
DV		 10846 if (work->flip_queued_req &&
10847 !i915_gem_request_completed(work->flip_queued_req, true))
d6bbafa1
CW		 10848 return false;
10849
1e3feefd 10850 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1
CW		 10851 }
10852
1e3feefd 10853 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
d6bbafa1
CW		 10854 return false;
10855
10856 /* Potential stall - if we see that the flip has happened,
10857 * assume a missed interrupt. */
10858 if (INTEL_INFO(dev)->gen >= 4)
10859 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
10860 else
10861 addr = I915_READ(DSPADDR(intel_crtc->plane));
10862
10863 /* There is a potential issue here with a false positive after a flip
10864 * to the same address. We could address this by checking for a
10865 * non-incrementing frame counter.
10866 */
10867 return addr == work->gtt_offset;
10868}
10869
10870void intel_check_page_flip(struct drm_device *dev, int pipe)
10871{
10872 struct drm_i915_private *dev_priv = dev->dev_private;
10873 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10874 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6ad790c0 10875 struct intel_unpin_work *work;
f326038a 10876
6c51d46f 10877 WARN_ON(!in_interrupt());
d6bbafa1
CW		 10878
10879 if (crtc == NULL)
10880 return;
10881
f326038a 10882 spin_lock(&dev->event_lock);
6ad790c0
CW		 10883 work = intel_crtc->unpin_work;
10884 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
d6bbafa1 10885 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
6ad790c0 10886 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
d6bbafa1 10887 page_flip_completed(intel_crtc);
6ad790c0 10888 work = NULL;
d6bbafa1 10889 }
6ad790c0
CW		 10890 if (work != NULL &&
10891 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
10892 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
f326038a 10893 spin_unlock(&dev->event_lock);
d6bbafa1
CW		 10894}
10895
6b95a207
KH		 10896static int intel_crtc_page_flip(struct drm_crtc *crtc,
10897 struct drm_framebuffer *fb,
ed8d1975
KP		 10898 struct drm_pending_vblank_event *event,
10899 uint32_t page_flip_flags)
6b95a207
KH		 10900{
10901 struct drm_device *dev = crtc->dev;
10902 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 10903 struct drm_framebuffer *old_fb = crtc->primary->fb;
2ff8fde1 10904 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
6b95a207 10905 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
455a6808 10906 struct drm_plane *primary = crtc->primary;
a071fa00 10907 enum pipe pipe = intel_crtc->pipe;
6b95a207 10908 struct intel_unpin_work *work;
a4872ba6 10909 struct intel_engine_cs *ring;
cf5d8a46 10910 bool mmio_flip;
52e68630 10911 int ret;
6b95a207 10912
2ff8fde1
MR		 10913 /*
10914 * drm_mode_page_flip_ioctl() should already catch this, but double
10915 * check to be safe. In the future we may enable pageflipping from
10916 * a disabled primary plane.
10917 */
10918 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
10919 return -EBUSY;
10920
e6a595d2 10921 /* Can't change pixel format via MI display flips. */
f4510a27 10922 if (fb->pixel_format != crtc->primary->fb->pixel_format)
e6a595d2
VS		 10923 return -EINVAL;
10924
10925 /*
10926 * TILEOFF/LINOFF registers can't be changed via MI display flips.
10927 * Note that pitch changes could also affect these register.
10928 */
10929 if (INTEL_INFO(dev)->gen > 3 &&
f4510a27
MR		 10930 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
10931 fb->pitches[0] != crtc->primary->fb->pitches[0]))
e6a595d2
VS		 10932 return -EINVAL;
10933
f900db47
CW		 10934 if (i915_terminally_wedged(&dev_priv->gpu_error))
10935 goto out_hang;
10936
b14c5679 10937 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH		 10938 if (work == NULL)
10939 return -ENOMEM;
10940
6b95a207 10941 work->event = event;
b4a98e57 10942 work->crtc = crtc;
ab8d6675 10943 work->old_fb = old_fb;
6b95a207
KH		 10944 INIT_WORK(&work->work, intel_unpin_work_fn);
10945
87b6b101 10946 ret = drm_crtc_vblank_get(crtc);
7317c75e
JB		 10947 if (ret)
10948 goto free_work;
10949
6b95a207 10950 /* We borrow the event spin lock for protecting unpin_work */
5e2d7afc 10951 spin_lock_irq(&dev->event_lock);
6b95a207 10952 if (intel_crtc->unpin_work) {
d6bbafa1
CW		 10953 /* Before declaring the flip queue wedged, check if
10954 * the hardware completed the operation behind our backs.
10955 */
10956 if (__intel_pageflip_stall_check(dev, crtc)) {
10957 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
10958 page_flip_completed(intel_crtc);
10959 } else {
10960 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5e2d7afc 10961 spin_unlock_irq(&dev->event_lock);
468f0b44 10962
d6bbafa1
CW		 10963 drm_crtc_vblank_put(crtc);
10964 kfree(work);
10965 return -EBUSY;
10966 }
6b95a207
KH		 10967 }
10968 intel_crtc->unpin_work = work;
5e2d7afc 10969 spin_unlock_irq(&dev->event_lock);
6b95a207 10970
b4a98e57
CW		 10971 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
10972 flush_workqueue(dev_priv->wq);
10973
75dfca80 10974 /* Reference the objects for the scheduled work. */
ab8d6675 10975 drm_framebuffer_reference(work->old_fb);
05394f39 10976 drm_gem_object_reference(&obj->base);
6b95a207 10977
f4510a27 10978 crtc->primary->fb = fb;
afd65eb4 10979 update_state_fb(crtc->primary);
1ed1f968 10980
e1f99ce6 10981 work->pending_flip_obj = obj;
e1f99ce6 10982
89ed88ba
CW		 10983 ret = i915_mutex_lock_interruptible(dev);
10984 if (ret)
10985 goto cleanup;
10986
b4a98e57 10987 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 10988 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 10989
75f7f3ec 10990 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
a071fa00 10991 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
75f7f3ec 10992
4fa62c89
VS		 10993 if (IS_VALLEYVIEW(dev)) {
10994 ring = &dev_priv->ring[BCS];
ab8d6675 10995 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
8e09bf83
CW		 10996 /* vlv: DISPLAY_FLIP fails to change tiling */
10997 ring = NULL;
48bf5b2d 10998 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
2a92d5bc 10999 ring = &dev_priv->ring[BCS];
4fa62c89 11000 } else if (INTEL_INFO(dev)->gen >= 7) {
41c52415 11001 ring = i915_gem_request_get_ring(obj->last_read_req);
4fa62c89
VS		 11002 if (ring == NULL || ring->id != RCS)
11003 ring = &dev_priv->ring[BCS];
11004 } else {
11005 ring = &dev_priv->ring[RCS];
11006 }
11007
cf5d8a46
CW		 11008 mmio_flip = use_mmio_flip(ring, obj);
11009
11010 /* When using CS flips, we want to emit semaphores between rings.
11011 * However, when using mmio flips we will create a task to do the
11012 * synchronisation, so all we want here is to pin the framebuffer
11013 * into the display plane and skip any waits.
11014 */
82bc3b2d 11015 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
cf5d8a46
CW		 11016 crtc->primary->state,
11017 mmio_flip ? i915_gem_request_get_ring(obj->last_read_req) : ring);
8c9f3aaf
JB		 11018 if (ret)
11019 goto cleanup_pending;
6b95a207 11020
121920fa
TU		 11021 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11022 + intel_crtc->dspaddr_offset;
4fa62c89 11023
cf5d8a46 11024 if (mmio_flip) {
84c33a64
SG		 11025 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11026 page_flip_flags);
d6bbafa1
CW		 11027 if (ret)
11028 goto cleanup_unpin;
11029
f06cc1b9
JH		 11030 i915_gem_request_assign(&work->flip_queued_req,
11031 obj->last_write_req);
d6bbafa1 11032 } else {
d94b5030
CW		 11033 if (obj->last_write_req) {
11034 ret = i915_gem_check_olr(obj->last_write_req);
11035 if (ret)
11036 goto cleanup_unpin;
11037 }
11038
84c33a64 11039 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
d6bbafa1
CW		 11040 page_flip_flags);
11041 if (ret)
11042 goto cleanup_unpin;
11043
f06cc1b9
JH		 11044 i915_gem_request_assign(&work->flip_queued_req,
11045 intel_ring_get_request(ring));
d6bbafa1
CW		 11046 }
11047
1e3feefd 11048 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1 11049 work->enable_stall_check = true;
4fa62c89 11050
ab8d6675 11051 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
a071fa00
DV		 11052 INTEL_FRONTBUFFER_PRIMARY(pipe));
11053
7ff0ebcc 11054 intel_fbc_disable(dev);
f99d7069 11055 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
6b95a207
KH		 11056 mutex_unlock(&dev->struct_mutex);
11057
e5510fac
JB		 11058 trace_i915_flip_request(intel_crtc->plane, obj);
11059
6b95a207 11060 return 0;
96b099fd 11061
4fa62c89 11062cleanup_unpin:
82bc3b2d 11063 intel_unpin_fb_obj(fb, crtc->primary->state);
8c9f3aaf 11064cleanup_pending:
b4a98e57 11065 atomic_dec(&intel_crtc->unpin_work_count);
89ed88ba
CW		 11066 mutex_unlock(&dev->struct_mutex);
11067cleanup:
f4510a27 11068 crtc->primary->fb = old_fb;
afd65eb4 11069 update_state_fb(crtc->primary);
89ed88ba
CW		 11070
11071 drm_gem_object_unreference_unlocked(&obj->base);
ab8d6675 11072 drm_framebuffer_unreference(work->old_fb);
96b099fd 11073
5e2d7afc 11074 spin_lock_irq(&dev->event_lock);
96b099fd 11075 intel_crtc->unpin_work = NULL;
5e2d7afc 11076 spin_unlock_irq(&dev->event_lock);
96b099fd 11077
87b6b101 11078 drm_crtc_vblank_put(crtc);
7317c75e 11079free_work:
96b099fd
CW		 11080 kfree(work);
11081
f900db47
CW		 11082 if (ret == -EIO) {
11083out_hang:
53a366b9 11084 ret = intel_plane_restore(primary);
f0d3dad3 11085 if (ret == 0 && event) {
5e2d7afc 11086 spin_lock_irq(&dev->event_lock);
a071fa00 11087 drm_send_vblank_event(dev, pipe, event);
5e2d7afc 11088 spin_unlock_irq(&dev->event_lock);
f0d3dad3 11089 }
f900db47 11090 }
96b099fd 11091 return ret;
6b95a207
KH		 11092}
11093
65b38e0d 11094static const struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 11095 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11096 .load_lut = intel_crtc_load_lut,
ea2c67bb
MR		 11097 .atomic_begin = intel_begin_crtc_commit,
11098 .atomic_flush = intel_finish_crtc_commit,
f6e5b160
CW		 11099};
11100
9a935856
DV		 11101/**
11102 * intel_modeset_update_staged_output_state
11103 *
11104 * Updates the staged output configuration state, e.g. after we've read out the
11105 * current hw state.
11106 */
11107static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 11108{
7668851f 11109 struct intel_crtc *crtc;
9a935856
DV		 11110 struct intel_encoder *encoder;
11111 struct intel_connector *connector;
f6e5b160 11112
3a3371ff 11113 for_each_intel_connector(dev, connector) {
9a935856
DV		 11114 connector->new_encoder =
11115 to_intel_encoder(connector->base.encoder);
11116 }
f6e5b160 11117
b2784e15 11118 for_each_intel_encoder(dev, encoder) {
9a935856
DV		 11119 encoder->new_crtc =
11120 to_intel_crtc(encoder->base.crtc);
11121 }
7668851f 11122
d3fcc808 11123 for_each_intel_crtc(dev, crtc) {
83d65738 11124 crtc->new_enabled = crtc->base.state->enable;
7668851f 11125 }
f6e5b160
CW		 11126}
11127
d29b2f9d
ACO		 11128/* Transitional helper to copy current connector/encoder state to
11129 * connector->state. This is needed so that code that is partially
11130 * converted to atomic does the right thing.
11131 */
11132static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11133{
11134 struct intel_connector *connector;
11135
11136 for_each_intel_connector(dev, connector) {
11137 if (connector->base.encoder) {
11138 connector->base.state->best_encoder =
11139 connector->base.encoder;
11140 connector->base.state->crtc =
11141 connector->base.encoder->crtc;
11142 } else {
11143 connector->base.state->best_encoder = NULL;
11144 connector->base.state->crtc = NULL;
11145 }
11146 }
11147}
11148
a821fc46 11149/* Fixup legacy state after an atomic state swap.
9a935856 11150 */
a821fc46 11151static void intel_modeset_fixup_state(struct drm_atomic_state *state)
9a935856 11152{
a821fc46 11153 struct intel_crtc *crtc;
9a935856 11154 struct intel_encoder *encoder;
a821fc46 11155 struct intel_connector *connector;
d5432a9d 11156
a821fc46
ACO		 11157 for_each_intel_connector(state->dev, connector) {
11158 connector->base.encoder = connector->base.state->best_encoder;
11159 if (connector->base.encoder)
11160 connector->base.encoder->crtc =
11161 connector->base.state->crtc;
9a935856 11162 }
f6e5b160 11163
d5432a9d
ACO		 11164 /* Update crtc of disabled encoders */
11165 for_each_intel_encoder(state->dev, encoder) {
11166 int num_connectors = 0;
11167
a821fc46
ACO		 11168 for_each_intel_connector(state->dev, connector)
11169 if (connector->base.encoder == &encoder->base)
d5432a9d
ACO		 11170 num_connectors++;
11171
11172 if (num_connectors == 0)
11173 encoder->base.crtc = NULL;
9a935856 11174 }
7668851f 11175
a821fc46
ACO		 11176 for_each_intel_crtc(state->dev, crtc) {
11177 crtc->base.enabled = crtc->base.state->enable;
11178 crtc->config = to_intel_crtc_state(crtc->base.state);
7668851f 11179 }
d29b2f9d 11180
d5432a9d
ACO		 11181 /* Copy the new configuration to the staged state, to keep the few
11182 * pieces of code that haven't been converted yet happy */
11183 intel_modeset_update_staged_output_state(state->dev);
9a935856
DV		 11184}
11185
050f7aeb 11186static void
eba905b2 11187connected_sink_compute_bpp(struct intel_connector *connector,
5cec258b 11188 struct intel_crtc_state *pipe_config)
050f7aeb
DV		 11189{
11190 int bpp = pipe_config->pipe_bpp;
11191
11192 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11193 connector->base.base.id,
c23cc417 11194 connector->base.name);
050f7aeb
DV		 11195
11196 /* Don't use an invalid EDID bpc value */
11197 if (connector->base.display_info.bpc &&
11198 connector->base.display_info.bpc * 3 < bpp) {
11199 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11200 bpp, connector->base.display_info.bpc*3);
11201 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11202 }
11203
11204 /* Clamp bpp to 8 on screens without EDID 1.4 */
11205 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11206 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11207 bpp);
11208 pipe_config->pipe_bpp = 24;
11209 }
11210}
11211
4e53c2e0 11212static int
050f7aeb 11213compute_baseline_pipe_bpp(struct intel_crtc *crtc,
5cec258b 11214 struct intel_crtc_state *pipe_config)
4e53c2e0 11215{
050f7aeb 11216 struct drm_device *dev = crtc->base.dev;
1486017f 11217 struct drm_atomic_state *state;
da3ced29
ACO		 11218 struct drm_connector *connector;
11219 struct drm_connector_state *connector_state;
1486017f 11220 int bpp, i;
4e53c2e0 11221
d328c9d7 11222 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
4e53c2e0 11223 bpp = 10*3;
d328c9d7
DV		 11224 else if (INTEL_INFO(dev)->gen >= 5)
11225 bpp = 12*3;
11226 else
11227 bpp = 8*3;
11228
4e53c2e0 11229
4e53c2e0
DV		 11230 pipe_config->pipe_bpp = bpp;
11231
1486017f
ACO		 11232 state = pipe_config->base.state;
11233
4e53c2e0 11234 /* Clamp display bpp to EDID value */
da3ced29
ACO		 11235 for_each_connector_in_state(state, connector, connector_state, i) {
11236 if (connector_state->crtc != &crtc->base)
4e53c2e0
DV		 11237 continue;
11238
da3ced29
ACO		 11239 connected_sink_compute_bpp(to_intel_connector(connector),
11240 pipe_config);
4e53c2e0
DV		 11241 }
11242
11243 return bpp;
11244}
11245
644db711
DV		 11246static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11247{
11248 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11249 "type: 0x%x flags: 0x%x\n",
1342830c 11250 mode->crtc_clock,
644db711
DV		 11251 mode->crtc_hdisplay, mode->crtc_hsync_start,
11252 mode->crtc_hsync_end, mode->crtc_htotal,
11253 mode->crtc_vdisplay, mode->crtc_vsync_start,
11254 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11255}
11256
c0b03411 11257static void intel_dump_pipe_config(struct intel_crtc *crtc,
5cec258b 11258 struct intel_crtc_state *pipe_config,
c0b03411
DV		 11259 const char *context)
11260{
6a60cd87
CK		 11261 struct drm_device *dev = crtc->base.dev;
11262 struct drm_plane *plane;
11263 struct intel_plane *intel_plane;
11264 struct intel_plane_state *state;
11265 struct drm_framebuffer *fb;
11266
11267 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11268 context, pipe_config, pipe_name(crtc->pipe));
c0b03411
DV		 11269
11270 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11271 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11272 pipe_config->pipe_bpp, pipe_config->dither);
11273 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11274 pipe_config->has_pch_encoder,
11275 pipe_config->fdi_lanes,
11276 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11277 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11278 pipe_config->fdi_m_n.tu);
eb14cb74
VS		 11279 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11280 pipe_config->has_dp_encoder,
11281 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11282 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11283 pipe_config->dp_m_n.tu);
b95af8be
VK		 11284
11285 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11286 pipe_config->has_dp_encoder,
11287 pipe_config->dp_m2_n2.gmch_m,
11288 pipe_config->dp_m2_n2.gmch_n,
11289 pipe_config->dp_m2_n2.link_m,
11290 pipe_config->dp_m2_n2.link_n,
11291 pipe_config->dp_m2_n2.tu);
11292
55072d19
DV		 11293 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11294 pipe_config->has_audio,
11295 pipe_config->has_infoframe);
11296
c0b03411 11297 DRM_DEBUG_KMS("requested mode:\n");
2d112de7 11298 drm_mode_debug_printmodeline(&pipe_config->base.mode);
c0b03411 11299 DRM_DEBUG_KMS("adjusted mode:\n");
2d112de7
ACO		 11300 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11301 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
d71b8d4a 11302 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 11303 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11304 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
0ec463d3
TU		 11305 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11306 crtc->num_scalers,
11307 pipe_config->scaler_state.scaler_users,
11308 pipe_config->scaler_state.scaler_id);
c0b03411
DV		 11309 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11310 pipe_config->gmch_pfit.control,
11311 pipe_config->gmch_pfit.pgm_ratios,
11312 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 11313 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 11314 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 11315 pipe_config->pch_pfit.size,
11316 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 11317 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 11318 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
6a60cd87 11319
415ff0f6
TU		 11320 if (IS_BROXTON(dev)) {
11321 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, "
11322 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
11323 "pll6: 0x%x, pll8: 0x%x, pcsdw12: 0x%x\n",
11324 pipe_config->ddi_pll_sel,
11325 pipe_config->dpll_hw_state.ebb0,
11326 pipe_config->dpll_hw_state.pll0,
11327 pipe_config->dpll_hw_state.pll1,
11328 pipe_config->dpll_hw_state.pll2,
11329 pipe_config->dpll_hw_state.pll3,
11330 pipe_config->dpll_hw_state.pll6,
11331 pipe_config->dpll_hw_state.pll8,
11332 pipe_config->dpll_hw_state.pcsdw12);
11333 } else if (IS_SKYLAKE(dev)) {
11334 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
11335 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
11336 pipe_config->ddi_pll_sel,
11337 pipe_config->dpll_hw_state.ctrl1,
11338 pipe_config->dpll_hw_state.cfgcr1,
11339 pipe_config->dpll_hw_state.cfgcr2);
11340 } else if (HAS_DDI(dev)) {
11341 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
11342 pipe_config->ddi_pll_sel,
11343 pipe_config->dpll_hw_state.wrpll);
11344 } else {
11345 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
11346 "fp0: 0x%x, fp1: 0x%x\n",
11347 pipe_config->dpll_hw_state.dpll,
11348 pipe_config->dpll_hw_state.dpll_md,
11349 pipe_config->dpll_hw_state.fp0,
11350 pipe_config->dpll_hw_state.fp1);
11351 }
11352
6a60cd87
CK		 11353 DRM_DEBUG_KMS("planes on this crtc\n");
11354 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11355 intel_plane = to_intel_plane(plane);
11356 if (intel_plane->pipe != crtc->pipe)
11357 continue;
11358
11359 state = to_intel_plane_state(plane->state);
11360 fb = state->base.fb;
11361 if (!fb) {
11362 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11363 "disabled, scaler_id = %d\n",
11364 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11365 plane->base.id, intel_plane->pipe,
11366 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
11367 drm_plane_index(plane), state->scaler_id);
11368 continue;
11369 }
11370
11371 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
11372 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11373 plane->base.id, intel_plane->pipe,
11374 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
11375 drm_plane_index(plane));
11376 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
11377 fb->base.id, fb->width, fb->height, fb->pixel_format);
11378 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
11379 state->scaler_id,
11380 state->src.x1 >> 16, state->src.y1 >> 16,
11381 drm_rect_width(&state->src) >> 16,
11382 drm_rect_height(&state->src) >> 16,
11383 state->dst.x1, state->dst.y1,
11384 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
11385 }
c0b03411
DV		 11386}
11387
bc079e8b
VS		 11388static bool encoders_cloneable(const struct intel_encoder *a,
11389 const struct intel_encoder *b)
accfc0c5 11390{
bc079e8b
VS		 11391 /* masks could be asymmetric, so check both ways */
11392 return a == b || (a->cloneable & (1 << b->type) &&
11393 b->cloneable & (1 << a->type));
11394}
11395
98a221da
ACO		 11396static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11397 struct intel_crtc *crtc,
bc079e8b
VS		 11398 struct intel_encoder *encoder)
11399{
bc079e8b 11400 struct intel_encoder *source_encoder;
da3ced29 11401 struct drm_connector *connector;
98a221da
ACO		 11402 struct drm_connector_state *connector_state;
11403 int i;
bc079e8b 11404
da3ced29 11405 for_each_connector_in_state(state, connector, connector_state, i) {
98a221da 11406 if (connector_state->crtc != &crtc->base)
bc079e8b
VS		 11407 continue;
11408
98a221da
ACO		 11409 source_encoder =
11410 to_intel_encoder(connector_state->best_encoder);
bc079e8b
VS		 11411 if (!encoders_cloneable(encoder, source_encoder))
11412 return false;
11413 }
11414
11415 return true;
11416}
11417
98a221da
ACO		 11418static bool check_encoder_cloning(struct drm_atomic_state *state,
11419 struct intel_crtc *crtc)
bc079e8b 11420{
accfc0c5 11421 struct intel_encoder *encoder;
da3ced29 11422 struct drm_connector *connector;
98a221da
ACO		 11423 struct drm_connector_state *connector_state;
11424 int i;
accfc0c5 11425
da3ced29 11426 for_each_connector_in_state(state, connector, connector_state, i) {
98a221da
ACO		 11427 if (connector_state->crtc != &crtc->base)
11428 continue;
11429
11430 encoder = to_intel_encoder(connector_state->best_encoder);
11431 if (!check_single_encoder_cloning(state, crtc, encoder))
bc079e8b 11432 return false;
accfc0c5
DV		 11433 }
11434
bc079e8b 11435 return true;
accfc0c5
DV		 11436}
11437
5448a00d 11438static bool check_digital_port_conflicts(struct drm_atomic_state *state)
00f0b378 11439{
5448a00d
ACO		 11440 struct drm_device *dev = state->dev;
11441 struct intel_encoder *encoder;
da3ced29 11442 struct drm_connector *connector;
5448a00d 11443 struct drm_connector_state *connector_state;
00f0b378 11444 unsigned int used_ports = 0;
5448a00d 11445 int i;
00f0b378
VS		 11446
11447 /*
11448 * Walk the connector list instead of the encoder
11449 * list to detect the problem on ddi platforms
11450 * where there's just one encoder per digital port.
11451 */
da3ced29 11452 for_each_connector_in_state(state, connector, connector_state, i) {
5448a00d 11453 if (!connector_state->best_encoder)
00f0b378
VS		 11454 continue;
11455
5448a00d
ACO		 11456 encoder = to_intel_encoder(connector_state->best_encoder);
11457
11458 WARN_ON(!connector_state->crtc);
00f0b378
VS		 11459
11460 switch (encoder->type) {
11461 unsigned int port_mask;
11462 case INTEL_OUTPUT_UNKNOWN:
11463 if (WARN_ON(!HAS_DDI(dev)))
11464 break;
11465 case INTEL_OUTPUT_DISPLAYPORT:
11466 case INTEL_OUTPUT_HDMI:
11467 case INTEL_OUTPUT_EDP:
11468 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
11469
11470 /* the same port mustn't appear more than once */
11471 if (used_ports & port_mask)
11472 return false;
11473
11474 used_ports |= port_mask;
11475 default:
11476 break;
11477 }
11478 }
11479
11480 return true;
11481}
11482
83a57153
ACO		 11483static void
11484clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
11485{
11486 struct drm_crtc_state tmp_state;
663a3640 11487 struct intel_crtc_scaler_state scaler_state;
4978cc93
ACO		 11488 struct intel_dpll_hw_state dpll_hw_state;
11489 enum intel_dpll_id shared_dpll;
8504c74c 11490 uint32_t ddi_pll_sel;
83a57153 11491
7546a384
ACO		 11492 /* FIXME: before the switch to atomic started, a new pipe_config was
11493 * kzalloc'd. Code that depends on any field being zero should be
11494 * fixed, so that the crtc_state can be safely duplicated. For now,
11495 * only fields that are know to not cause problems are preserved. */
11496
83a57153 11497 tmp_state = crtc_state->base;
663a3640 11498 scaler_state = crtc_state->scaler_state;
4978cc93
ACO		 11499 shared_dpll = crtc_state->shared_dpll;
11500 dpll_hw_state = crtc_state->dpll_hw_state;
8504c74c 11501 ddi_pll_sel = crtc_state->ddi_pll_sel;
4978cc93 11502
83a57153 11503 memset(crtc_state, 0, sizeof *crtc_state);
4978cc93 11504
83a57153 11505 crtc_state->base = tmp_state;
663a3640 11506 crtc_state->scaler_state = scaler_state;
4978cc93
ACO		 11507 crtc_state->shared_dpll = shared_dpll;
11508 crtc_state->dpll_hw_state = dpll_hw_state;
8504c74c 11509 crtc_state->ddi_pll_sel = ddi_pll_sel;
83a57153
ACO		 11510}
11511
548ee15b 11512static int
b8cecdf5 11513intel_modeset_pipe_config(struct drm_crtc *crtc,
548ee15b
ACO		 11514 struct drm_atomic_state *state,
11515 struct intel_crtc_state *pipe_config)
ee7b9f93 11516{
7758a113 11517 struct intel_encoder *encoder;
da3ced29 11518 struct drm_connector *connector;
0b901879 11519 struct drm_connector_state *connector_state;
d328c9d7 11520 int base_bpp, ret = -EINVAL;
0b901879 11521 int i;
e29c22c0 11522 bool retry = true;
ee7b9f93 11523
98a221da 11524 if (!check_encoder_cloning(state, to_intel_crtc(crtc))) {
accfc0c5 11525 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
548ee15b 11526 return -EINVAL;
accfc0c5
DV		 11527 }
11528
5448a00d 11529 if (!check_digital_port_conflicts(state)) {
00f0b378 11530 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
548ee15b 11531 return -EINVAL;
00f0b378
VS		 11532 }
11533
83a57153 11534 clear_intel_crtc_state(pipe_config);
7758a113 11535
e143a21c
DV		 11536 pipe_config->cpu_transcoder =
11537 (enum transcoder) to_intel_crtc(crtc)->pipe;
b8cecdf5 11538
2960bc9c
ID		 11539 /*
11540 * Sanitize sync polarity flags based on requested ones. If neither
11541 * positive or negative polarity is requested, treat this as meaning
11542 * negative polarity.
11543 */
2d112de7 11544 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 11545 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
2d112de7 11546 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
2960bc9c 11547
2d112de7 11548 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 11549 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
2d112de7 11550 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
2960bc9c 11551
050f7aeb
DV		 11552 /* Compute a starting value for pipe_config->pipe_bpp taking the source
11553 * plane pixel format and any sink constraints into account. Returns the
11554 * source plane bpp so that dithering can be selected on mismatches
11555 * after encoders and crtc also have had their say. */
d328c9d7
DV		 11556 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
11557 pipe_config);
11558 if (base_bpp < 0)
4e53c2e0
DV		 11559 goto fail;
11560
e41a56be
VS		 11561 /*
11562 * Determine the real pipe dimensions. Note that stereo modes can
11563 * increase the actual pipe size due to the frame doubling and
11564 * insertion of additional space for blanks between the frame. This
11565 * is stored in the crtc timings. We use the requested mode to do this
11566 * computation to clearly distinguish it from the adjusted mode, which
11567 * can be changed by the connectors in the below retry loop.
11568 */
2d112de7 11569 drm_crtc_get_hv_timing(&pipe_config->base.mode,
ecb7e16b
GP		 11570 &pipe_config->pipe_src_w,
11571 &pipe_config->pipe_src_h);
e41a56be 11572
e29c22c0 11573encoder_retry:
ef1b460d 11574 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 11575 pipe_config->port_clock = 0;
ef1b460d 11576 pipe_config->pixel_multiplier = 1;
ff9a6750 11577
135c81b8 11578 /* Fill in default crtc timings, allow encoders to overwrite them. */
2d112de7
ACO		 11579 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
11580 CRTC_STEREO_DOUBLE);
135c81b8 11581
7758a113
DV		 11582 /* Pass our mode to the connectors and the CRTC to give them a chance to
11583 * adjust it according to limitations or connector properties, and also
11584 * a chance to reject the mode entirely.
47f1c6c9 11585 */
da3ced29 11586 for_each_connector_in_state(state, connector, connector_state, i) {
0b901879 11587 if (connector_state->crtc != crtc)
7758a113 11588 continue;
7ae89233 11589
0b901879
ACO		 11590 encoder = to_intel_encoder(connector_state->best_encoder);
11591
efea6e8e
DV		 11592 if (!(encoder->compute_config(encoder, pipe_config))) {
11593 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 11594 goto fail;
11595 }
ee7b9f93 11596 }
47f1c6c9 11597
ff9a6750
DV		 11598 /* Set default port clock if not overwritten by the encoder. Needs to be
11599 * done afterwards in case the encoder adjusts the mode. */
11600 if (!pipe_config->port_clock)
2d112de7 11601 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
241bfc38 11602 * pipe_config->pixel_multiplier;
ff9a6750 11603
a43f6e0f 11604 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 11605 if (ret < 0) {
7758a113
DV		 11606 DRM_DEBUG_KMS("CRTC fixup failed\n");
11607 goto fail;
ee7b9f93 11608 }
e29c22c0
DV		 11609
11610 if (ret == RETRY) {
11611 if (WARN(!retry, "loop in pipe configuration computation\n")) {
11612 ret = -EINVAL;
11613 goto fail;
11614 }
11615
11616 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11617 retry = false;
11618 goto encoder_retry;
11619 }
11620
d328c9d7 11621 pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
4e53c2e0 11622 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
d328c9d7 11623 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
4e53c2e0 11624
548ee15b 11625 return 0;
7758a113 11626fail:
548ee15b 11627 return ret;
ee7b9f93 11628}
47f1c6c9 11629
ea9d758d 11630static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 11631{
ea9d758d 11632 struct drm_encoder *encoder;
f6e5b160 11633 struct drm_device *dev = crtc->dev;
f6e5b160 11634
ea9d758d
DV		 11635 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
11636 if (encoder->crtc == crtc)
11637 return true;
11638
11639 return false;
11640}
11641
0a9ab303
ACO		 11642static bool
11643needs_modeset(struct drm_crtc_state *state)
11644{
11645 return state->mode_changed || state->active_changed;
11646}
11647
ea9d758d 11648static void
0a9ab303 11649intel_modeset_update_state(struct drm_atomic_state *state)
ea9d758d 11650{
0a9ab303 11651 struct drm_device *dev = state->dev;
ba41c0de 11652 struct drm_i915_private *dev_priv = dev->dev_private;
ea9d758d 11653 struct intel_encoder *intel_encoder;
0a9ab303
ACO		 11654 struct drm_crtc *crtc;
11655 struct drm_crtc_state *crtc_state;
ea9d758d 11656 struct drm_connector *connector;
0a9ab303 11657 int i;
ea9d758d 11658
ba41c0de
DV		 11659 intel_shared_dpll_commit(dev_priv);
11660
b2784e15 11661 for_each_intel_encoder(dev, intel_encoder) {
ea9d758d
DV		 11662 if (!intel_encoder->base.crtc)
11663 continue;
11664
0a9ab303
ACO		 11665 for_each_crtc_in_state(state, crtc, crtc_state, i)
11666 if (crtc == intel_encoder->base.crtc)
11667 break;
11668
11669 if (crtc != intel_encoder->base.crtc)
11670 continue;
ea9d758d 11671
0a9ab303 11672 if (crtc_state->enable && needs_modeset(crtc_state))
ea9d758d
DV		 11673 intel_encoder->connectors_active = false;
11674 }
11675
a821fc46
ACO		 11676 drm_atomic_helper_swap_state(state->dev, state);
11677 intel_modeset_fixup_state(state);
ea9d758d 11678
7668851f 11679 /* Double check state. */
0a9ab303
ACO		 11680 for_each_crtc(dev, crtc) {
11681 WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc));
ea9d758d
DV		 11682 }
11683
11684 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11685 if (!connector->encoder || !connector->encoder->crtc)
11686 continue;
11687
0a9ab303
ACO		 11688 for_each_crtc_in_state(state, crtc, crtc_state, i)
11689 if (crtc == connector->encoder->crtc)
11690 break;
11691
11692 if (crtc != connector->encoder->crtc)
11693 continue;
ea9d758d 11694
a821fc46 11695 if (crtc->state->enable && needs_modeset(crtc->state)) {
68d34720
DV		 11696 struct drm_property *dpms_property =
11697 dev->mode_config.dpms_property;
11698
ea9d758d 11699 connector->dpms = DRM_MODE_DPMS_ON;
662595df 11700 drm_object_property_set_value(&connector->base,
68d34720
DV		 11701 dpms_property,
11702 DRM_MODE_DPMS_ON);
ea9d758d
DV		 11703
11704 intel_encoder = to_intel_encoder(connector->encoder);
11705 intel_encoder->connectors_active = true;
11706 }
11707 }
11708
11709}
11710
3bd26263 11711static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 11712{
3bd26263 11713 int diff;
f1f644dc
JB		 11714
11715 if (clock1 == clock2)
11716 return true;
11717
11718 if (!clock1 || !clock2)
11719 return false;
11720
11721 diff = abs(clock1 - clock2);
11722
11723 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11724 return true;
11725
11726 return false;
11727}
11728
25c5b266
DV		 11729#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
11730 list_for_each_entry((intel_crtc), \
11731 &(dev)->mode_config.crtc_list, \
11732 base.head) \
0973f18f 11733 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 11734
0e8ffe1b 11735static bool
2fa2fe9a 11736intel_pipe_config_compare(struct drm_device *dev,
5cec258b
ACO		 11737 struct intel_crtc_state *current_config,
11738 struct intel_crtc_state *pipe_config)
0e8ffe1b 11739{
66e985c0
DV		 11740#define PIPE_CONF_CHECK_X(name) \
11741 if (current_config->name != pipe_config->name) { \
11742 DRM_ERROR("mismatch in " #name " " \
11743 "(expected 0x%08x, found 0x%08x)\n", \
11744 current_config->name, \
11745 pipe_config->name); \
11746 return false; \
11747 }
11748
08a24034
DV		 11749#define PIPE_CONF_CHECK_I(name) \
11750 if (current_config->name != pipe_config->name) { \
11751 DRM_ERROR("mismatch in " #name " " \
11752 "(expected %i, found %i)\n", \
11753 current_config->name, \
11754 pipe_config->name); \
11755 return false; \
88adfff1
DV		 11756 }
11757
b95af8be
VK		 11758/* This is required for BDW+ where there is only one set of registers for
11759 * switching between high and low RR.
11760 * This macro can be used whenever a comparison has to be made between one
11761 * hw state and multiple sw state variables.
11762 */
11763#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
11764 if ((current_config->name != pipe_config->name) && \
11765 (current_config->alt_name != pipe_config->name)) { \
11766 DRM_ERROR("mismatch in " #name " " \
11767 "(expected %i or %i, found %i)\n", \
11768 current_config->name, \
11769 current_config->alt_name, \
11770 pipe_config->name); \
11771 return false; \
11772 }
11773
1bd1bd80
DV		 11774#define PIPE_CONF_CHECK_FLAGS(name, mask) \
11775 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 11776 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 11777 "(expected %i, found %i)\n", \
11778 current_config->name & (mask), \
11779 pipe_config->name & (mask)); \
11780 return false; \
11781 }
11782
5e550656
VS		 11783#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11784 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11785 DRM_ERROR("mismatch in " #name " " \
11786 "(expected %i, found %i)\n", \
11787 current_config->name, \
11788 pipe_config->name); \
11789 return false; \
11790 }
11791
bb760063
DV		 11792#define PIPE_CONF_QUIRK(quirk) \
11793 ((current_config->quirks | pipe_config->quirks) & (quirk))
11794
eccb140b
DV		 11795 PIPE_CONF_CHECK_I(cpu_transcoder);
11796
08a24034
DV		 11797 PIPE_CONF_CHECK_I(has_pch_encoder);
11798 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 11799 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
11800 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
11801 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
11802 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
11803 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 11804
eb14cb74 11805 PIPE_CONF_CHECK_I(has_dp_encoder);
b95af8be
VK		 11806
11807 if (INTEL_INFO(dev)->gen < 8) {
11808 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
11809 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
11810 PIPE_CONF_CHECK_I(dp_m_n.link_m);
11811 PIPE_CONF_CHECK_I(dp_m_n.link_n);
11812 PIPE_CONF_CHECK_I(dp_m_n.tu);
11813
11814 if (current_config->has_drrs) {
11815 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
11816 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
11817 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
11818 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
11819 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
11820 }
11821 } else {
11822 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
11823 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
11824 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
11825 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
11826 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
11827 }
eb14cb74 11828
2d112de7
ACO		 11829 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11830 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11831 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11832 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11833 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11834 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
1bd1bd80 11835
2d112de7
ACO		 11836 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11837 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11838 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11839 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11840 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11841 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
1bd1bd80 11842
c93f54cf 11843 PIPE_CONF_CHECK_I(pixel_multiplier);
6897b4b5 11844 PIPE_CONF_CHECK_I(has_hdmi_sink);
b5a9fa09
DV		 11845 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
11846 IS_VALLEYVIEW(dev))
11847 PIPE_CONF_CHECK_I(limited_color_range);
e43823ec 11848 PIPE_CONF_CHECK_I(has_infoframe);
6c49f241 11849
9ed109a7
DV		 11850 PIPE_CONF_CHECK_I(has_audio);
11851
2d112de7 11852 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
1bd1bd80
DV		 11853 DRM_MODE_FLAG_INTERLACE);
11854
bb760063 11855 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
2d112de7 11856 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 11857 DRM_MODE_FLAG_PHSYNC);
2d112de7 11858 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 11859 DRM_MODE_FLAG_NHSYNC);
2d112de7 11860 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 11861 DRM_MODE_FLAG_PVSYNC);
2d112de7 11862 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063
DV		 11863 DRM_MODE_FLAG_NVSYNC);
11864 }
045ac3b5 11865
37327abd
VS		 11866 PIPE_CONF_CHECK_I(pipe_src_w);
11867 PIPE_CONF_CHECK_I(pipe_src_h);
1bd1bd80 11868
9953599b
DV		 11869 /*
11870 * FIXME: BIOS likes to set up a cloned config with lvds+external
11871 * screen. Since we don't yet re-compute the pipe config when moving
11872 * just the lvds port away to another pipe the sw tracking won't match.
11873 *
11874 * Proper atomic modesets with recomputed global state will fix this.
11875 * Until then just don't check gmch state for inherited modes.
11876 */
11877 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
11878 PIPE_CONF_CHECK_I(gmch_pfit.control);
11879 /* pfit ratios are autocomputed by the hw on gen4+ */
11880 if (INTEL_INFO(dev)->gen < 4)
11881 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
11882 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
11883 }
11884
fd4daa9c
CW		 11885 PIPE_CONF_CHECK_I(pch_pfit.enabled);
11886 if (current_config->pch_pfit.enabled) {
11887 PIPE_CONF_CHECK_I(pch_pfit.pos);
11888 PIPE_CONF_CHECK_I(pch_pfit.size);
11889 }
2fa2fe9a 11890
a1b2278e
CK		 11891 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
11892
e59150dc
JB		 11893 /* BDW+ don't expose a synchronous way to read the state */
11894 if (IS_HASWELL(dev))
11895 PIPE_CONF_CHECK_I(ips_enabled);
42db64ef 11896
282740f7
VS		 11897 PIPE_CONF_CHECK_I(double_wide);
11898
26804afd
DV		 11899 PIPE_CONF_CHECK_X(ddi_pll_sel);
11900
c0d43d62 11901 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 11902 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 11903 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 11904 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11905 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
d452c5b6 11906 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
3f4cd19f
DL		 11907 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11908 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11909 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
c0d43d62 11910
42571aef
VS		 11911 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
11912 PIPE_CONF_CHECK_I(pipe_bpp);
11913
2d112de7 11914 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
a9a7e98a 11915 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
5e550656 11916
66e985c0 11917#undef PIPE_CONF_CHECK_X
08a24034 11918#undef PIPE_CONF_CHECK_I
b95af8be 11919#undef PIPE_CONF_CHECK_I_ALT
1bd1bd80 11920#undef PIPE_CONF_CHECK_FLAGS
5e550656 11921#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 11922#undef PIPE_CONF_QUIRK
88adfff1 11923
0e8ffe1b
DV		 11924 return true;
11925}
11926
08db6652
DL		 11927static void check_wm_state(struct drm_device *dev)
11928{
11929 struct drm_i915_private *dev_priv = dev->dev_private;
11930 struct skl_ddb_allocation hw_ddb, *sw_ddb;
11931 struct intel_crtc *intel_crtc;
11932 int plane;
11933
11934 if (INTEL_INFO(dev)->gen < 9)
11935 return;
11936
11937 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
11938 sw_ddb = &dev_priv->wm.skl_hw.ddb;
11939
11940 for_each_intel_crtc(dev, intel_crtc) {
11941 struct skl_ddb_entry *hw_entry, *sw_entry;
11942 const enum pipe pipe = intel_crtc->pipe;
11943
11944 if (!intel_crtc->active)
11945 continue;
11946
11947 /* planes */
dd740780 11948 for_each_plane(dev_priv, pipe, plane) {
08db6652
DL		 11949 hw_entry = &hw_ddb.plane[pipe][plane];
11950 sw_entry = &sw_ddb->plane[pipe][plane];
11951
11952 if (skl_ddb_entry_equal(hw_entry, sw_entry))
11953 continue;
11954
11955 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
11956 "(expected (%u,%u), found (%u,%u))\n",
11957 pipe_name(pipe), plane + 1,
11958 sw_entry->start, sw_entry->end,
11959 hw_entry->start, hw_entry->end);
11960 }
11961
11962 /* cursor */
11963 hw_entry = &hw_ddb.cursor[pipe];
11964 sw_entry = &sw_ddb->cursor[pipe];
11965
11966 if (skl_ddb_entry_equal(hw_entry, sw_entry))
11967 continue;
11968
11969 DRM_ERROR("mismatch in DDB state pipe %c cursor "
11970 "(expected (%u,%u), found (%u,%u))\n",
11971 pipe_name(pipe),
11972 sw_entry->start, sw_entry->end,
11973 hw_entry->start, hw_entry->end);
11974 }
11975}
11976
91d1b4bd
DV		 11977static void
11978check_connector_state(struct drm_device *dev)
8af6cf88 11979{
8af6cf88
DV		 11980 struct intel_connector *connector;
11981
3a3371ff 11982 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 11983 /* This also checks the encoder/connector hw state with the
11984 * ->get_hw_state callbacks. */
11985 intel_connector_check_state(connector);
11986
e2c719b7 11987 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
8af6cf88
DV		 11988 "connector's staged encoder doesn't match current encoder\n");
11989 }
91d1b4bd
DV		 11990}
11991
11992static void
11993check_encoder_state(struct drm_device *dev)
11994{
11995 struct intel_encoder *encoder;
11996 struct intel_connector *connector;
8af6cf88 11997
b2784e15 11998 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 11999 bool enabled = false;
12000 bool active = false;
12001 enum pipe pipe, tracked_pipe;
12002
12003 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12004 encoder->base.base.id,
8e329a03 12005 encoder->base.name);
8af6cf88 12006
e2c719b7 12007 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
8af6cf88 12008 "encoder's stage crtc doesn't match current crtc\n");
e2c719b7 12009 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
8af6cf88
DV		 12010 "encoder's active_connectors set, but no crtc\n");
12011
3a3371ff 12012 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 12013 if (connector->base.encoder != &encoder->base)
12014 continue;
12015 enabled = true;
12016 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
12017 active = true;
12018 }
0e32b39c
DA		 12019 /*
12020 * for MST connectors if we unplug the connector is gone
12021 * away but the encoder is still connected to a crtc
12022 * until a modeset happens in response to the hotplug.
12023 */
12024 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
12025 continue;
12026
e2c719b7 12027 I915_STATE_WARN(!!encoder->base.crtc != enabled,
8af6cf88
DV		 12028 "encoder's enabled state mismatch "
12029 "(expected %i, found %i)\n",
12030 !!encoder->base.crtc, enabled);
e2c719b7 12031 I915_STATE_WARN(active && !encoder->base.crtc,
8af6cf88
DV		 12032 "active encoder with no crtc\n");
12033
e2c719b7 12034 I915_STATE_WARN(encoder->connectors_active != active,
8af6cf88
DV		 12035 "encoder's computed active state doesn't match tracked active state "
12036 "(expected %i, found %i)\n", active, encoder->connectors_active);
12037
12038 active = encoder->get_hw_state(encoder, &pipe);
e2c719b7 12039 I915_STATE_WARN(active != encoder->connectors_active,
8af6cf88
DV		 12040 "encoder's hw state doesn't match sw tracking "
12041 "(expected %i, found %i)\n",
12042 encoder->connectors_active, active);
12043
12044 if (!encoder->base.crtc)
12045 continue;
12046
12047 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
e2c719b7 12048 I915_STATE_WARN(active && pipe != tracked_pipe,
8af6cf88
DV		 12049 "active encoder's pipe doesn't match"
12050 "(expected %i, found %i)\n",
12051 tracked_pipe, pipe);
12052
12053 }
91d1b4bd
DV		 12054}
12055
12056static void
12057check_crtc_state(struct drm_device *dev)
12058{
fbee40df 12059 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 12060 struct intel_crtc *crtc;
12061 struct intel_encoder *encoder;
5cec258b 12062 struct intel_crtc_state pipe_config;
8af6cf88 12063
d3fcc808 12064 for_each_intel_crtc(dev, crtc) {
8af6cf88
DV		 12065 bool enabled = false;
12066 bool active = false;
12067
045ac3b5
JB		 12068 memset(&pipe_config, 0, sizeof(pipe_config));
12069
8af6cf88
DV		 12070 DRM_DEBUG_KMS("[CRTC:%d]\n",
12071 crtc->base.base.id);
12072
83d65738 12073 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
8af6cf88
DV		 12074 "active crtc, but not enabled in sw tracking\n");
12075
b2784e15 12076 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 12077 if (encoder->base.crtc != &crtc->base)
12078 continue;
12079 enabled = true;
12080 if (encoder->connectors_active)
12081 active = true;
12082 }
6c49f241 12083
e2c719b7 12084 I915_STATE_WARN(active != crtc->active,
8af6cf88
DV		 12085 "crtc's computed active state doesn't match tracked active state "
12086 "(expected %i, found %i)\n", active, crtc->active);
83d65738 12087 I915_STATE_WARN(enabled != crtc->base.state->enable,
8af6cf88 12088 "crtc's computed enabled state doesn't match tracked enabled state "
83d65738
MR		 12089 "(expected %i, found %i)\n", enabled,
12090 crtc->base.state->enable);
8af6cf88 12091
0e8ffe1b
DV		 12092 active = dev_priv->display.get_pipe_config(crtc,
12093 &pipe_config);
d62cf62a 12094
b6b5d049
VS		 12095 /* hw state is inconsistent with the pipe quirk */
12096 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12097 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
d62cf62a
DV		 12098 active = crtc->active;
12099
b2784e15 12100 for_each_intel_encoder(dev, encoder) {
3eaba51c 12101 enum pipe pipe;
6c49f241
DV		 12102 if (encoder->base.crtc != &crtc->base)
12103 continue;
1d37b689 12104 if (encoder->get_hw_state(encoder, &pipe))
6c49f241
DV		 12105 encoder->get_config(encoder, &pipe_config);
12106 }
12107
e2c719b7 12108 I915_STATE_WARN(crtc->active != active,
0e8ffe1b
DV		 12109 "crtc active state doesn't match with hw state "
12110 "(expected %i, found %i)\n", crtc->active, active);
12111
c0b03411 12112 if (active &&
6e3c9717 12113 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
e2c719b7 12114 I915_STATE_WARN(1, "pipe state doesn't match!\n");
c0b03411
DV		 12115 intel_dump_pipe_config(crtc, &pipe_config,
12116 "[hw state]");
6e3c9717 12117 intel_dump_pipe_config(crtc, crtc->config,
c0b03411
DV		 12118 "[sw state]");
12119 }
8af6cf88
DV		 12120 }
12121}
12122
91d1b4bd
DV		 12123static void
12124check_shared_dpll_state(struct drm_device *dev)
12125{
fbee40df 12126 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 12127 struct intel_crtc *crtc;
12128 struct intel_dpll_hw_state dpll_hw_state;
12129 int i;
5358901f
DV		 12130
12131 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12132 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12133 int enabled_crtcs = 0, active_crtcs = 0;
12134 bool active;
12135
12136 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12137
12138 DRM_DEBUG_KMS("%s\n", pll->name);
12139
12140 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12141
e2c719b7 12142 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
5358901f 12143 "more active pll users than references: %i vs %i\n",
3e369b76 12144 pll->active, hweight32(pll->config.crtc_mask));
e2c719b7 12145 I915_STATE_WARN(pll->active && !pll->on,
5358901f 12146 "pll in active use but not on in sw tracking\n");
e2c719b7 12147 I915_STATE_WARN(pll->on && !pll->active,
35c95375 12148 "pll in on but not on in use in sw tracking\n");
e2c719b7 12149 I915_STATE_WARN(pll->on != active,
5358901f
DV		 12150 "pll on state mismatch (expected %i, found %i)\n",
12151 pll->on, active);
12152
d3fcc808 12153 for_each_intel_crtc(dev, crtc) {
83d65738 12154 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
5358901f
DV		 12155 enabled_crtcs++;
12156 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12157 active_crtcs++;
12158 }
e2c719b7 12159 I915_STATE_WARN(pll->active != active_crtcs,
5358901f
DV		 12160 "pll active crtcs mismatch (expected %i, found %i)\n",
12161 pll->active, active_crtcs);
e2c719b7 12162 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
5358901f 12163 "pll enabled crtcs mismatch (expected %i, found %i)\n",
3e369b76 12164 hweight32(pll->config.crtc_mask), enabled_crtcs);
66e985c0 12165
e2c719b7 12166 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
66e985c0
DV		 12167 sizeof(dpll_hw_state)),
12168 "pll hw state mismatch\n");
5358901f 12169 }
8af6cf88
DV		 12170}
12171
91d1b4bd
DV		 12172void
12173intel_modeset_check_state(struct drm_device *dev)
12174{
08db6652 12175 check_wm_state(dev);
91d1b4bd
DV		 12176 check_connector_state(dev);
12177 check_encoder_state(dev);
12178 check_crtc_state(dev);
12179 check_shared_dpll_state(dev);
12180}
12181
5cec258b 12182void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
18442d08
VS		 12183 int dotclock)
12184{
12185 /*
12186 * FDI already provided one idea for the dotclock.
12187 * Yell if the encoder disagrees.
12188 */
2d112de7 12189 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
18442d08 12190 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
2d112de7 12191 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
18442d08
VS		 12192}
12193
80715b2f
VS		 12194static void update_scanline_offset(struct intel_crtc *crtc)
12195{
12196 struct drm_device *dev = crtc->base.dev;
12197
12198 /*
12199 * The scanline counter increments at the leading edge of hsync.
12200 *
12201 * On most platforms it starts counting from vtotal-1 on the
12202 * first active line. That means the scanline counter value is
12203 * always one less than what we would expect. Ie. just after
12204 * start of vblank, which also occurs at start of hsync (on the
12205 * last active line), the scanline counter will read vblank_start-1.
12206 *
12207 * On gen2 the scanline counter starts counting from 1 instead
12208 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12209 * to keep the value positive), instead of adding one.
12210 *
12211 * On HSW+ the behaviour of the scanline counter depends on the output
12212 * type. For DP ports it behaves like most other platforms, but on HDMI
12213 * there's an extra 1 line difference. So we need to add two instead of
12214 * one to the value.
12215 */
12216 if (IS_GEN2(dev)) {
6e3c9717 12217 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
80715b2f
VS		 12218 int vtotal;
12219
12220 vtotal = mode->crtc_vtotal;
12221 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12222 vtotal /= 2;
12223
12224 crtc->scanline_offset = vtotal - 1;
12225 } else if (HAS_DDI(dev) &&
409ee761 12226 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
80715b2f
VS		 12227 crtc->scanline_offset = 2;
12228 } else
12229 crtc->scanline_offset = 1;
12230}
12231
5cec258b 12232static struct intel_crtc_state *
7f27126e 12233intel_modeset_compute_config(struct drm_crtc *crtc,
0a9ab303 12234 struct drm_atomic_state *state)
7f27126e 12235{
548ee15b 12236 struct intel_crtc_state *pipe_config;
0b901879
ACO		 12237 int ret = 0;
12238
12239 ret = drm_atomic_add_affected_connectors(state, crtc);
12240 if (ret)
12241 return ERR_PTR(ret);
7f27126e 12242
8c7b5ccb
ACO		 12243 ret = drm_atomic_helper_check_modeset(state->dev, state);
12244 if (ret)
12245 return ERR_PTR(ret);
7f27126e 12246
7f27126e
JB		 12247 /*
12248 * Note this needs changes when we start tracking multiple modes
12249 * and crtcs. At that point we'll need to compute the whole config
12250 * (i.e. one pipe_config for each crtc) rather than just the one
12251 * for this crtc.
12252 */
548ee15b
ACO		 12253 pipe_config = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
12254 if (IS_ERR(pipe_config))
12255 return pipe_config;
83a57153 12256
4fed33f6 12257 if (!pipe_config->base.enable)
548ee15b 12258 return pipe_config;
7f27126e 12259
8c7b5ccb 12260 ret = intel_modeset_pipe_config(crtc, state, pipe_config);
548ee15b
ACO		 12261 if (ret)
12262 return ERR_PTR(ret);
12263
8d8c9b51
ACO		 12264 /* Check things that can only be changed through modeset */
12265 if (pipe_config->has_audio !=
12266 to_intel_crtc(crtc)->config->has_audio)
12267 pipe_config->base.mode_changed = true;
12268
12269 /*
12270 * Note we have an issue here with infoframes: current code
12271 * only updates them on the full mode set path per hw
12272 * requirements. So here we should be checking for any
12273 * required changes and forcing a mode set.
12274 */
12275
548ee15b 12276 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,"[modeset]");
db7542dd 12277
8c7b5ccb
ACO		 12278 ret = drm_atomic_helper_check_planes(state->dev, state);
12279 if (ret)
12280 return ERR_PTR(ret);
12281
548ee15b 12282 return pipe_config;
7f27126e
JB		 12283}
12284
0a9ab303 12285static int __intel_set_mode_setup_plls(struct drm_atomic_state *state)
ed6739ef 12286{
225da59b 12287 struct drm_device *dev = state->dev;
ed6739ef 12288 struct drm_i915_private *dev_priv = to_i915(dev);
0a9ab303 12289 unsigned clear_pipes = 0;
ed6739ef 12290 struct intel_crtc *intel_crtc;
0a9ab303
ACO		 12291 struct intel_crtc_state *intel_crtc_state;
12292 struct drm_crtc *crtc;
12293 struct drm_crtc_state *crtc_state;
ed6739ef 12294 int ret = 0;
0a9ab303 12295 int i;
ed6739ef
ACO		 12296
12297 if (!dev_priv->display.crtc_compute_clock)
12298 return 0;
12299
0a9ab303
ACO		 12300 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12301 intel_crtc = to_intel_crtc(crtc);
4978cc93 12302 intel_crtc_state = to_intel_crtc_state(crtc_state);
0a9ab303 12303
4978cc93 12304 if (needs_modeset(crtc_state)) {
0a9ab303 12305 clear_pipes |= 1 << intel_crtc->pipe;
4978cc93 12306 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
4978cc93 12307 }
0a9ab303
ACO		 12308 }
12309
ed6739ef
ACO		 12310 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
12311 if (ret)
12312 goto done;
12313
0a9ab303
ACO		 12314 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12315 if (!needs_modeset(crtc_state) || !crtc_state->enable)
225da59b
ACO		 12316 continue;
12317
0a9ab303
ACO		 12318 intel_crtc = to_intel_crtc(crtc);
12319 intel_crtc_state = to_intel_crtc_state(crtc_state);
12320
ed6739ef 12321 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
0a9ab303 12322 intel_crtc_state);
ed6739ef
ACO		 12323 if (ret) {
12324 intel_shared_dpll_abort_config(dev_priv);
12325 goto done;
12326 }
12327 }
12328
12329done:
12330 return ret;
12331}
12332
054518dd
ACO		 12333/* Code that should eventually be part of atomic_check() */
12334static int __intel_set_mode_checks(struct drm_atomic_state *state)
12335{
12336 struct drm_device *dev = state->dev;
12337 int ret;
12338
12339 /*
12340 * See if the config requires any additional preparation, e.g.
12341 * to adjust global state with pipes off. We need to do this
12342 * here so we can get the modeset_pipe updated config for the new
12343 * mode set on this crtc. For other crtcs we need to use the
12344 * adjusted_mode bits in the crtc directly.
12345 */
12346 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
12347 ret = valleyview_modeset_global_pipes(state);
12348 if (ret)
12349 return ret;
12350 }
12351
12352 ret = __intel_set_mode_setup_plls(state);
12353 if (ret)
12354 return ret;
12355
12356 return 0;
12357}
12358
0a9ab303 12359static int __intel_set_mode(struct drm_crtc *modeset_crtc,
0a9ab303 12360 struct intel_crtc_state *pipe_config)
a6778b3c 12361{
0a9ab303 12362 struct drm_device *dev = modeset_crtc->dev;
fbee40df 12363 struct drm_i915_private *dev_priv = dev->dev_private;
304603f4 12364 struct drm_atomic_state *state = pipe_config->base.state;
0a9ab303
ACO		 12365 struct drm_crtc *crtc;
12366 struct drm_crtc_state *crtc_state;
c0c36b94 12367 int ret = 0;
0a9ab303 12368 int i;
a6778b3c 12369
054518dd
ACO		 12370 ret = __intel_set_mode_checks(state);
12371 if (ret < 0)
12372 return ret;
12373
d4afb8cc
ACO		 12374 ret = drm_atomic_helper_prepare_planes(dev, state);
12375 if (ret)
12376 return ret;
12377
0a9ab303
ACO		 12378 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12379 if (!needs_modeset(crtc_state))
12380 continue;
460da916 12381
0a9ab303
ACO		 12382 if (!crtc_state->enable) {
12383 intel_crtc_disable(crtc);
12384 } else if (crtc->state->enable) {
12385 intel_crtc_disable_planes(crtc);
12386 dev_priv->display.crtc_disable(crtc);
ce22dba9 12387 }
ea9d758d 12388 }
a6778b3c 12389
6c4c86f5
DV		 12390 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
12391 * to set it here already despite that we pass it down the callchain.
7f27126e
JB		 12392 *
12393 * Note we'll need to fix this up when we start tracking multiple
12394 * pipes; here we assume a single modeset_pipe and only track the
12395 * single crtc and mode.
f6e5b160 12396 */
0a9ab303 12397 if (pipe_config->base.enable && needs_modeset(&pipe_config->base)) {
8c7b5ccb 12398 modeset_crtc->mode = pipe_config->base.mode;
c326c0a9
VS		 12399
12400 /*
12401 * Calculate and store various constants which
12402 * are later needed by vblank and swap-completion
12403 * timestamping. They are derived from true hwmode.
12404 */
0a9ab303 12405 drm_calc_timestamping_constants(modeset_crtc,
2d112de7 12406 &pipe_config->base.adjusted_mode);
b8cecdf5 12407 }
7758a113 12408
ea9d758d
DV		 12409 /* Only after disabling all output pipelines that will be changed can we
12410 * update the the output configuration. */
0a9ab303 12411 intel_modeset_update_state(state);
f6e5b160 12412
a821fc46
ACO		 12413 /* The state has been swaped above, so state actually contains the
12414 * old state now. */
12415
304603f4 12416 modeset_update_crtc_power_domains(state);
47fab737 12417
d4afb8cc 12418 drm_atomic_helper_commit_planes(dev, state);
a6778b3c
DV		 12419
12420 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
0a9ab303 12421 for_each_crtc_in_state(state, crtc, crtc_state, i) {
a821fc46 12422 if (!needs_modeset(crtc->state) || !crtc->state->enable)
0a9ab303
ACO		 12423 continue;
12424
12425 update_scanline_offset(to_intel_crtc(crtc));
80715b2f 12426
0a9ab303
ACO		 12427 dev_priv->display.crtc_enable(crtc);
12428 intel_crtc_enable_planes(crtc);
80715b2f 12429 }
a6778b3c 12430
a6778b3c 12431 /* FIXME: add subpixel order */
83a57153 12432
d4afb8cc
ACO		 12433 drm_atomic_helper_cleanup_planes(dev, state);
12434
2bfb4627
ACO		 12435 drm_atomic_state_free(state);
12436
9eb45f22 12437 return 0;
f6e5b160
CW		 12438}
12439
0a9ab303 12440static int intel_set_mode_with_config(struct drm_crtc *crtc,
0a9ab303 12441 struct intel_crtc_state *pipe_config)
f30da187
DV		 12442{
12443 int ret;
12444
8c7b5ccb 12445 ret = __intel_set_mode(crtc, pipe_config);
f30da187
DV		 12446
12447 if (ret == 0)
12448 intel_modeset_check_state(crtc->dev);
12449
12450 return ret;
12451}
12452
7f27126e 12453static int intel_set_mode(struct drm_crtc *crtc,
83a57153 12454 struct drm_atomic_state *state)
7f27126e 12455{
5cec258b 12456 struct intel_crtc_state *pipe_config;
83a57153 12457 int ret = 0;
7f27126e 12458
8c7b5ccb 12459 pipe_config = intel_modeset_compute_config(crtc, state);
83a57153
ACO		 12460 if (IS_ERR(pipe_config)) {
12461 ret = PTR_ERR(pipe_config);
12462 goto out;
12463 }
12464
8c7b5ccb 12465 ret = intel_set_mode_with_config(crtc, pipe_config);
83a57153
ACO		 12466 if (ret)
12467 goto out;
7f27126e 12468
83a57153
ACO		 12469out:
12470 return ret;
7f27126e
JB		 12471}
12472
c0c36b94
CW		 12473void intel_crtc_restore_mode(struct drm_crtc *crtc)
12474{
83a57153
ACO		 12475 struct drm_device *dev = crtc->dev;
12476 struct drm_atomic_state *state;
4be07317 12477 struct intel_crtc *intel_crtc;
83a57153
ACO		 12478 struct intel_encoder *encoder;
12479 struct intel_connector *connector;
12480 struct drm_connector_state *connector_state;
4be07317 12481 struct intel_crtc_state *crtc_state;
2bfb4627 12482 int ret;
83a57153
ACO		 12483
12484 state = drm_atomic_state_alloc(dev);
12485 if (!state) {
12486 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
12487 crtc->base.id);
12488 return;
12489 }
12490
12491 state->acquire_ctx = dev->mode_config.acquire_ctx;
12492
12493 /* The force restore path in the HW readout code relies on the staged
12494 * config still keeping the user requested config while the actual
12495 * state has been overwritten by the configuration read from HW. We
12496 * need to copy the staged config to the atomic state, otherwise the
12497 * mode set will just reapply the state the HW is already in. */
12498 for_each_intel_encoder(dev, encoder) {
12499 if (&encoder->new_crtc->base != crtc)
12500 continue;
12501
12502 for_each_intel_connector(dev, connector) {
12503 if (connector->new_encoder != encoder)
12504 continue;
12505
12506 connector_state = drm_atomic_get_connector_state(state, &connector->base);
12507 if (IS_ERR(connector_state)) {
12508 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
12509 connector->base.base.id,
12510 connector->base.name,
12511 PTR_ERR(connector_state));
12512 continue;
12513 }
12514
12515 connector_state->crtc = crtc;
12516 connector_state->best_encoder = &encoder->base;
12517 }
12518 }
12519
4be07317
ACO		 12520 for_each_intel_crtc(dev, intel_crtc) {
12521 if (intel_crtc->new_enabled == intel_crtc->base.enabled)
12522 continue;
12523
12524 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
12525 if (IS_ERR(crtc_state)) {
12526 DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n",
12527 intel_crtc->base.base.id,
12528 PTR_ERR(crtc_state));
12529 continue;
12530 }
12531
49d6fa21
ML		 12532 crtc_state->base.active = crtc_state->base.enable =
12533 intel_crtc->new_enabled;
8c7b5ccb
ACO		 12534
12535 if (&intel_crtc->base == crtc)
12536 drm_mode_copy(&crtc_state->base.mode, &crtc->mode);
4be07317
ACO		 12537 }
12538
d3a40d1b
ACO		 12539 intel_modeset_setup_plane_state(state, crtc, &crtc->mode,
12540 crtc->primary->fb, crtc->x, crtc->y);
12541
2bfb4627
ACO		 12542 ret = intel_set_mode(crtc, state);
12543 if (ret)
12544 drm_atomic_state_free(state);
c0c36b94
CW		 12545}
12546
25c5b266
DV		 12547#undef for_each_intel_crtc_masked
12548
b7885264
ACO		 12549static bool intel_connector_in_mode_set(struct intel_connector *connector,
12550 struct drm_mode_set *set)
12551{
12552 int ro;
12553
12554 for (ro = 0; ro < set->num_connectors; ro++)
12555 if (set->connectors[ro] == &connector->base)
12556 return true;
12557
12558 return false;
12559}
12560
2e431051 12561static int
9a935856
DV		 12562intel_modeset_stage_output_state(struct drm_device *dev,
12563 struct drm_mode_set *set,
944b0c76 12564 struct drm_atomic_state *state)
50f56119 12565{
9a935856 12566 struct intel_connector *connector;
d5432a9d 12567 struct drm_connector *drm_connector;
944b0c76 12568 struct drm_connector_state *connector_state;
d5432a9d
ACO		 12569 struct drm_crtc *crtc;
12570 struct drm_crtc_state *crtc_state;
12571 int i, ret;
50f56119 12572
9abdda74 12573 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 12574 * of connectors. For paranoia, double-check this. */
12575 WARN_ON(!set->fb && (set->num_connectors != 0));
12576 WARN_ON(set->fb && (set->num_connectors == 0));
12577
3a3371ff 12578 for_each_intel_connector(dev, connector) {
b7885264
ACO		 12579 bool in_mode_set = intel_connector_in_mode_set(connector, set);
12580
d5432a9d
ACO		 12581 if (!in_mode_set && connector->base.state->crtc != set->crtc)
12582 continue;
12583
12584 connector_state =
12585 drm_atomic_get_connector_state(state, &connector->base);
12586 if (IS_ERR(connector_state))
12587 return PTR_ERR(connector_state);
12588
b7885264
ACO		 12589 if (in_mode_set) {
12590 int pipe = to_intel_crtc(set->crtc)->pipe;
d5432a9d
ACO		 12591 connector_state->best_encoder =
12592 &intel_find_encoder(connector, pipe)->base;
50f56119
DV		 12593 }
12594
d5432a9d 12595 if (connector->base.state->crtc != set->crtc)
b7885264
ACO		 12596 continue;
12597
9a935856
DV		 12598 /* If we disable the crtc, disable all its connectors. Also, if
12599 * the connector is on the changing crtc but not on the new
12600 * connector list, disable it. */
b7885264 12601 if (!set->fb || !in_mode_set) {
d5432a9d 12602 connector_state->best_encoder = NULL;
9a935856
DV		 12603
12604 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
12605 connector->base.base.id,
c23cc417 12606 connector->base.name);
9a935856 12607 }
50f56119 12608 }
9a935856 12609 /* connector->new_encoder is now updated for all connectors. */
50f56119 12610
d5432a9d
ACO		 12611 for_each_connector_in_state(state, drm_connector, connector_state, i) {
12612 connector = to_intel_connector(drm_connector);
12613
12614 if (!connector_state->best_encoder) {
12615 ret = drm_atomic_set_crtc_for_connector(connector_state,
12616 NULL);
12617 if (ret)
12618 return ret;
7668851f 12619
50f56119 12620 continue;
d5432a9d 12621 }
50f56119 12622
d5432a9d
ACO		 12623 if (intel_connector_in_mode_set(connector, set)) {
12624 struct drm_crtc *crtc = connector->base.state->crtc;
12625
12626 /* If this connector was in a previous crtc, add it
12627 * to the state. We might need to disable it. */
12628 if (crtc) {
12629 crtc_state =
12630 drm_atomic_get_crtc_state(state, crtc);
12631 if (IS_ERR(crtc_state))
12632 return PTR_ERR(crtc_state);
12633 }
12634
12635 ret = drm_atomic_set_crtc_for_connector(connector_state,
12636 set->crtc);
12637 if (ret)
12638 return ret;
12639 }
50f56119
DV		 12640
12641 /* Make sure the new CRTC will work with the encoder */
d5432a9d
ACO		 12642 if (!drm_encoder_crtc_ok(connector_state->best_encoder,
12643 connector_state->crtc)) {
5e2b584e 12644 return -EINVAL;
50f56119 12645 }
944b0c76 12646
9a935856
DV		 12647 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
12648 connector->base.base.id,
c23cc417 12649 connector->base.name,
d5432a9d 12650 connector_state->crtc->base.id);
944b0c76 12651
d5432a9d
ACO		 12652 if (connector_state->best_encoder != &connector->encoder->base)
12653 connector->encoder =
12654 to_intel_encoder(connector_state->best_encoder);
0e32b39c 12655 }
7668851f 12656
d5432a9d 12657 for_each_crtc_in_state(state, crtc, crtc_state, i) {
49d6fa21
ML		 12658 bool has_connectors;
12659
d5432a9d
ACO		 12660 ret = drm_atomic_add_affected_connectors(state, crtc);
12661 if (ret)
12662 return ret;
4be07317 12663
49d6fa21
ML		 12664 has_connectors = !!drm_atomic_connectors_for_crtc(state, crtc);
12665 if (has_connectors != crtc_state->enable)
12666 crtc_state->enable =
12667 crtc_state->active = has_connectors;
7668851f
VS		 12668 }
12669
8c7b5ccb
ACO		 12670 ret = intel_modeset_setup_plane_state(state, set->crtc, set->mode,
12671 set->fb, set->x, set->y);
12672 if (ret)
12673 return ret;
12674
12675 crtc_state = drm_atomic_get_crtc_state(state, set->crtc);
12676 if (IS_ERR(crtc_state))
12677 return PTR_ERR(crtc_state);
12678
12679 if (set->mode)
12680 drm_mode_copy(&crtc_state->mode, set->mode);
12681
12682 if (set->num_connectors)
12683 crtc_state->active = true;
12684
2e431051
DV		 12685 return 0;
12686}
12687
bb546623
ACO		 12688static bool primary_plane_visible(struct drm_crtc *crtc)
12689{
12690 struct intel_plane_state *plane_state =
12691 to_intel_plane_state(crtc->primary->state);
12692
12693 return plane_state->visible;
12694}
12695
2e431051
DV		 12696static int intel_crtc_set_config(struct drm_mode_set *set)
12697{
12698 struct drm_device *dev;
83a57153 12699 struct drm_atomic_state *state = NULL;
5cec258b 12700 struct intel_crtc_state *pipe_config;
bb546623 12701 bool primary_plane_was_visible;
2e431051 12702 int ret;
2e431051 12703
8d3e375e
DV		 12704 BUG_ON(!set);
12705 BUG_ON(!set->crtc);
12706 BUG_ON(!set->crtc->helper_private);
2e431051 12707
7e53f3a4
DV		 12708 /* Enforce sane interface api - has been abused by the fb helper. */
12709 BUG_ON(!set->mode && set->fb);
12710 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 12711
2e431051
DV		 12712 if (set->fb) {
12713 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
12714 set->crtc->base.id, set->fb->base.id,
12715 (int)set->num_connectors, set->x, set->y);
12716 } else {
12717 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 12718 }
12719
12720 dev = set->crtc->dev;
12721
83a57153 12722 state = drm_atomic_state_alloc(dev);
7cbf41d6
ACO		 12723 if (!state)
12724 return -ENOMEM;
83a57153
ACO		 12725
12726 state->acquire_ctx = dev->mode_config.acquire_ctx;
12727
462a425a 12728 ret = intel_modeset_stage_output_state(dev, set, state);
2e431051 12729 if (ret)
7cbf41d6 12730 goto out;
2e431051 12731
8c7b5ccb 12732 pipe_config = intel_modeset_compute_config(set->crtc, state);
20664591 12733 if (IS_ERR(pipe_config)) {
6ac0483b 12734 ret = PTR_ERR(pipe_config);
7cbf41d6 12735 goto out;
20664591 12736 }
50f52756 12737
1f9954d0
JB		 12738 intel_update_pipe_size(to_intel_crtc(set->crtc));
12739
bb546623
ACO		 12740 primary_plane_was_visible = primary_plane_visible(set->crtc);
12741
8c7b5ccb 12742 ret = intel_set_mode_with_config(set->crtc, pipe_config);
bb546623
ACO		 12743
12744 if (ret == 0 &&
12745 pipe_config->base.enable &&
12746 pipe_config->base.planes_changed &&
12747 !needs_modeset(&pipe_config->base)) {
3b150f08 12748 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
3b150f08
MR		 12749
12750 /*
12751 * We need to make sure the primary plane is re-enabled if it
12752 * has previously been turned off.
12753 */
bb546623
ACO		 12754 if (ret == 0 && !primary_plane_was_visible &&
12755 primary_plane_visible(set->crtc)) {
3b150f08 12756 WARN_ON(!intel_crtc->active);
87d4300a 12757 intel_post_enable_primary(set->crtc);
3b150f08
MR		 12758 }
12759
7ca51a3a
JB		 12760 /*
12761 * In the fastboot case this may be our only check of the
12762 * state after boot. It would be better to only do it on
12763 * the first update, but we don't have a nice way of doing that
12764 * (and really, set_config isn't used much for high freq page
12765 * flipping, so increasing its cost here shouldn't be a big
12766 * deal).
12767 */
d330a953 12768 if (i915.fastboot && ret == 0)
7ca51a3a 12769 intel_modeset_check_state(set->crtc->dev);
50f56119
DV		 12770 }
12771
2d05eae1 12772 if (ret) {
bf67dfeb
DV		 12773 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
12774 set->crtc->base.id, ret);
2d05eae1 12775 }
50f56119 12776
7cbf41d6 12777out:
2bfb4627
ACO		 12778 if (ret)
12779 drm_atomic_state_free(state);
50f56119
DV		 12780 return ret;
12781}
f6e5b160
CW		 12782
12783static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160 12784 .gamma_set = intel_crtc_gamma_set,
50f56119 12785 .set_config = intel_crtc_set_config,
f6e5b160
CW		 12786 .destroy = intel_crtc_destroy,
12787 .page_flip = intel_crtc_page_flip,
1356837e
MR		 12788 .atomic_duplicate_state = intel_crtc_duplicate_state,
12789 .atomic_destroy_state = intel_crtc_destroy_state,
f6e5b160
CW		 12790};
12791
5358901f
DV		 12792static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
12793 struct intel_shared_dpll *pll,
12794 struct intel_dpll_hw_state *hw_state)
ee7b9f93 12795{
5358901f 12796 uint32_t val;
ee7b9f93 12797
f458ebbc 12798 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
bd2bb1b9
PZ		 12799 return false;
12800
5358901f 12801 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 12802 hw_state->dpll = val;
12803 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
12804 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 12805
12806 return val & DPLL_VCO_ENABLE;
12807}
12808
15bdd4cf
DV		 12809static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
12810 struct intel_shared_dpll *pll)
12811{
3e369b76
ACO		 12812 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
12813 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
15bdd4cf
DV		 12814}
12815
e7b903d2
DV		 12816static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
12817 struct intel_shared_dpll *pll)
12818{
e7b903d2 12819 /* PCH refclock must be enabled first */
89eff4be 12820 ibx_assert_pch_refclk_enabled(dev_priv);
e7b903d2 12821
3e369b76 12822 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf
DV		 12823
12824 /* Wait for the clocks to stabilize. */
12825 POSTING_READ(PCH_DPLL(pll->id));
12826 udelay(150);
12827
12828 /* The pixel multiplier can only be updated once the
12829 * DPLL is enabled and the clocks are stable.
12830 *
12831 * So write it again.
12832 */
3e369b76 12833 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf 12834 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 12835 udelay(200);
12836}
12837
12838static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
12839 struct intel_shared_dpll *pll)
12840{
12841 struct drm_device *dev = dev_priv->dev;
12842 struct intel_crtc *crtc;
e7b903d2
DV		 12843
12844 /* Make sure no transcoder isn't still depending on us. */
d3fcc808 12845 for_each_intel_crtc(dev, crtc) {
e7b903d2
DV		 12846 if (intel_crtc_to_shared_dpll(crtc) == pll)
12847 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 12848 }
12849
15bdd4cf
DV		 12850 I915_WRITE(PCH_DPLL(pll->id), 0);
12851 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 12852 udelay(200);
12853}
12854
46edb027
DV		 12855static char *ibx_pch_dpll_names[] = {
12856 "PCH DPLL A",
12857 "PCH DPLL B",
12858};
12859
7c74ade1 12860static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 12861{
e7b903d2 12862 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 12863 int i;
12864
7c74ade1 12865 dev_priv->num_shared_dpll = 2;
ee7b9f93 12866
e72f9fbf 12867 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 12868 dev_priv->shared_dplls[i].id = i;
12869 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 12870 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 12871 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
12872 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 12873 dev_priv->shared_dplls[i].get_hw_state =
12874 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 12875 }
12876}
12877
7c74ade1
DV		 12878static void intel_shared_dpll_init(struct drm_device *dev)
12879{
e7b903d2 12880 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1 12881
9cd86933
DV		 12882 if (HAS_DDI(dev))
12883 intel_ddi_pll_init(dev);
12884 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7c74ade1
DV		 12885 ibx_pch_dpll_init(dev);
12886 else
12887 dev_priv->num_shared_dpll = 0;
12888
12889 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
7c74ade1
DV		 12890}
12891
1fc0a8f7
TU		 12892/**
12893 * intel_wm_need_update - Check whether watermarks need updating
12894 * @plane: drm plane
12895 * @state: new plane state
12896 *
12897 * Check current plane state versus the new one to determine whether
12898 * watermarks need to be recalculated.
12899 *
12900 * Returns true or false.
12901 */
12902bool intel_wm_need_update(struct drm_plane *plane,
12903 struct drm_plane_state *state)
12904{
12905 /* Update watermarks on tiling changes. */
12906 if (!plane->state->fb || !state->fb ||
12907 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
12908 plane->state->rotation != state->rotation)
12909 return true;
12910
12911 return false;
12912}
12913
6beb8c23
MR		 12914/**
12915 * intel_prepare_plane_fb - Prepare fb for usage on plane
12916 * @plane: drm plane to prepare for
12917 * @fb: framebuffer to prepare for presentation
12918 *
12919 * Prepares a framebuffer for usage on a display plane. Generally this
12920 * involves pinning the underlying object and updating the frontbuffer tracking
12921 * bits. Some older platforms need special physical address handling for
12922 * cursor planes.
12923 *
12924 * Returns 0 on success, negative error code on failure.
12925 */
12926int
12927intel_prepare_plane_fb(struct drm_plane *plane,
d136dfee
TU		 12928 struct drm_framebuffer *fb,
12929 const struct drm_plane_state *new_state)
465c120c
MR		 12930{
12931 struct drm_device *dev = plane->dev;
6beb8c23
MR		 12932 struct intel_plane *intel_plane = to_intel_plane(plane);
12933 enum pipe pipe = intel_plane->pipe;
12934 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12935 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
12936 unsigned frontbuffer_bits = 0;
12937 int ret = 0;
465c120c 12938
ea2c67bb 12939 if (!obj)
465c120c
MR		 12940 return 0;
12941
6beb8c23
MR		 12942 switch (plane->type) {
12943 case DRM_PLANE_TYPE_PRIMARY:
12944 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
12945 break;
12946 case DRM_PLANE_TYPE_CURSOR:
12947 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
12948 break;
12949 case DRM_PLANE_TYPE_OVERLAY:
12950 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
12951 break;
12952 }
465c120c 12953
6beb8c23 12954 mutex_lock(&dev->struct_mutex);
465c120c 12955
6beb8c23
MR		 12956 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
12957 INTEL_INFO(dev)->cursor_needs_physical) {
12958 int align = IS_I830(dev) ? 16 * 1024 : 256;
12959 ret = i915_gem_object_attach_phys(obj, align);
12960 if (ret)
12961 DRM_DEBUG_KMS("failed to attach phys object\n");
12962 } else {
82bc3b2d 12963 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL);
6beb8c23 12964 }
465c120c 12965
6beb8c23
MR		 12966 if (ret == 0)
12967 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
fdd508a6 12968
4c34574f 12969 mutex_unlock(&dev->struct_mutex);
465c120c 12970
6beb8c23
MR		 12971 return ret;
12972}
12973
38f3ce3a
MR		 12974/**
12975 * intel_cleanup_plane_fb - Cleans up an fb after plane use
12976 * @plane: drm plane to clean up for
12977 * @fb: old framebuffer that was on plane
12978 *
12979 * Cleans up a framebuffer that has just been removed from a plane.
12980 */
12981void
12982intel_cleanup_plane_fb(struct drm_plane *plane,
d136dfee
TU		 12983 struct drm_framebuffer *fb,
12984 const struct drm_plane_state *old_state)
38f3ce3a
MR		 12985{
12986 struct drm_device *dev = plane->dev;
12987 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12988
12989 if (WARN_ON(!obj))
12990 return;
12991
12992 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
12993 !INTEL_INFO(dev)->cursor_needs_physical) {
12994 mutex_lock(&dev->struct_mutex);
82bc3b2d 12995 intel_unpin_fb_obj(fb, old_state);
38f3ce3a
MR		 12996 mutex_unlock(&dev->struct_mutex);
12997 }
465c120c
MR		 12998}
12999
6156a456
CK		 13000int
13001skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13002{
13003 int max_scale;
13004 struct drm_device *dev;
13005 struct drm_i915_private *dev_priv;
13006 int crtc_clock, cdclk;
13007
13008 if (!intel_crtc || !crtc_state)
13009 return DRM_PLANE_HELPER_NO_SCALING;
13010
13011 dev = intel_crtc->base.dev;
13012 dev_priv = dev->dev_private;
13013 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13014 cdclk = dev_priv->display.get_display_clock_speed(dev);
13015
13016 if (!crtc_clock || !cdclk)
13017 return DRM_PLANE_HELPER_NO_SCALING;
13018
13019 /*
13020 * skl max scale is lower of:
13021 * close to 3 but not 3, -1 is for that purpose
13022 * or
13023 * cdclk/crtc_clock
13024 */
13025 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13026
13027 return max_scale;
13028}
13029
465c120c 13030static int
3c692a41
GP		 13031intel_check_primary_plane(struct drm_plane *plane,
13032 struct intel_plane_state *state)
13033{
32b7eeec
MR		 13034 struct drm_device *dev = plane->dev;
13035 struct drm_i915_private *dev_priv = dev->dev_private;
2b875c22 13036 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb 13037 struct intel_crtc *intel_crtc;
6156a456 13038 struct intel_crtc_state *crtc_state;
2b875c22 13039 struct drm_framebuffer *fb = state->base.fb;
3c692a41
GP		 13040 struct drm_rect *dest = &state->dst;
13041 struct drm_rect *src = &state->src;
13042 const struct drm_rect *clip = &state->clip;
d8106366 13043 bool can_position = false;
6156a456
CK		 13044 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13045 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
465c120c
MR		 13046 int ret;
13047
ea2c67bb
MR		 13048 crtc = crtc ? crtc : plane->crtc;
13049 intel_crtc = to_intel_crtc(crtc);
6156a456
CK		 13050 crtc_state = state->base.state ?
13051 intel_atomic_get_crtc_state(state->base.state, intel_crtc) : NULL;
ea2c67bb 13052
6156a456
CK		 13053 if (INTEL_INFO(dev)->gen >= 9) {
13054 min_scale = 1;
13055 max_scale = skl_max_scale(intel_crtc, crtc_state);
d8106366 13056 can_position = true;
6156a456 13057 }
d8106366 13058
c59cb179
MR		 13059 ret = drm_plane_helper_check_update(plane, crtc, fb,
13060 src, dest, clip,
6156a456
CK		 13061 min_scale,
13062 max_scale,
d8106366
SJ		 13063 can_position, true,
13064 &state->visible);
c59cb179
MR		 13065 if (ret)
13066 return ret;
465c120c 13067
32b7eeec 13068 if (intel_crtc->active) {
b70709a6
ML		 13069 struct intel_plane_state *old_state =
13070 to_intel_plane_state(plane->state);
13071
32b7eeec
MR		 13072 intel_crtc->atomic.wait_for_flips = true;
13073
13074 /*
13075 * FBC does not work on some platforms for rotated
13076 * planes, so disable it when rotation is not 0 and
13077 * update it when rotation is set back to 0.
13078 *
13079 * FIXME: This is redundant with the fbc update done in
13080 * the primary plane enable function except that that
13081 * one is done too late. We eventually need to unify
13082 * this.
13083 */
b70709a6 13084 if (state->visible &&
32b7eeec 13085 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
e35fef21 13086 dev_priv->fbc.crtc == intel_crtc &&
8e7d688b 13087 state->base.rotation != BIT(DRM_ROTATE_0)) {
32b7eeec
MR		 13088 intel_crtc->atomic.disable_fbc = true;
13089 }
13090
b70709a6 13091 if (state->visible && !old_state->visible) {
32b7eeec
MR		 13092 /*
13093 * BDW signals flip done immediately if the plane
13094 * is disabled, even if the plane enable is already
13095 * armed to occur at the next vblank :(
13096 */
b70709a6 13097 if (IS_BROADWELL(dev))
32b7eeec
MR		 13098 intel_crtc->atomic.wait_vblank = true;
13099 }
13100
13101 intel_crtc->atomic.fb_bits |=
13102 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
13103
13104 intel_crtc->atomic.update_fbc = true;
0fda6568 13105
1fc0a8f7 13106 if (intel_wm_need_update(plane, &state->base))
0fda6568 13107 intel_crtc->atomic.update_wm = true;
ccc759dc
GP		 13108 }
13109
6156a456
CK		 13110 if (INTEL_INFO(dev)->gen >= 9) {
13111 ret = skl_update_scaler_users(intel_crtc, crtc_state,
13112 to_intel_plane(plane), state, 0);
13113 if (ret)
13114 return ret;
13115 }
13116
14af293f
GP		 13117 return 0;
13118}
13119
13120static void
13121intel_commit_primary_plane(struct drm_plane *plane,
13122 struct intel_plane_state *state)
13123{
2b875c22
MR		 13124 struct drm_crtc *crtc = state->base.crtc;
13125 struct drm_framebuffer *fb = state->base.fb;
13126 struct drm_device *dev = plane->dev;
14af293f 13127 struct drm_i915_private *dev_priv = dev->dev_private;
ea2c67bb 13128 struct intel_crtc *intel_crtc;
14af293f
GP		 13129 struct drm_rect *src = &state->src;
13130
ea2c67bb
MR		 13131 crtc = crtc ? crtc : plane->crtc;
13132 intel_crtc = to_intel_crtc(crtc);
cf4c7c12
MR		 13133
13134 plane->fb = fb;
9dc806fc
MR		 13135 crtc->x = src->x1 >> 16;
13136 crtc->y = src->y1 >> 16;
ccc759dc 13137
ccc759dc 13138 if (intel_crtc->active) {
27321ae8 13139 if (state->visible)
ccc759dc
GP		 13140 /* FIXME: kill this fastboot hack */
13141 intel_update_pipe_size(intel_crtc);
465c120c 13142
27321ae8
ML		 13143 dev_priv->display.update_primary_plane(crtc, plane->fb,
13144 crtc->x, crtc->y);
ccc759dc 13145 }
465c120c
MR		 13146}
13147
a8ad0d8e
ML		 13148static void
13149intel_disable_primary_plane(struct drm_plane *plane,
13150 struct drm_crtc *crtc,
13151 bool force)
13152{
13153 struct drm_device *dev = plane->dev;
13154 struct drm_i915_private *dev_priv = dev->dev_private;
13155
a8ad0d8e
ML		 13156 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13157}
13158
32b7eeec 13159static void intel_begin_crtc_commit(struct drm_crtc *crtc)
3c692a41 13160{
32b7eeec 13161 struct drm_device *dev = crtc->dev;
140fd38d 13162 struct drm_i915_private *dev_priv = dev->dev_private;
3c692a41 13163 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ea2c67bb
MR		 13164 struct intel_plane *intel_plane;
13165 struct drm_plane *p;
13166 unsigned fb_bits = 0;
13167
13168 /* Track fb's for any planes being disabled */
13169 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
13170 intel_plane = to_intel_plane(p);
13171
13172 if (intel_crtc->atomic.disabled_planes &
13173 (1 << drm_plane_index(p))) {
13174 switch (p->type) {
13175 case DRM_PLANE_TYPE_PRIMARY:
13176 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
13177 break;
13178 case DRM_PLANE_TYPE_CURSOR:
13179 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
13180 break;
13181 case DRM_PLANE_TYPE_OVERLAY:
13182 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
13183 break;
13184 }
3c692a41 13185
ea2c67bb
MR		 13186 mutex_lock(&dev->struct_mutex);
13187 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
13188 mutex_unlock(&dev->struct_mutex);
13189 }
13190 }
3c692a41 13191
32b7eeec
MR		 13192 if (intel_crtc->atomic.wait_for_flips)
13193 intel_crtc_wait_for_pending_flips(crtc);
3c692a41 13194
32b7eeec
MR		 13195 if (intel_crtc->atomic.disable_fbc)
13196 intel_fbc_disable(dev);
3c692a41 13197
32b7eeec
MR		 13198 if (intel_crtc->atomic.pre_disable_primary)
13199 intel_pre_disable_primary(crtc);
3c692a41 13200
32b7eeec
MR		 13201 if (intel_crtc->atomic.update_wm)
13202 intel_update_watermarks(crtc);
3c692a41 13203
32b7eeec 13204 intel_runtime_pm_get(dev_priv);
3c692a41 13205
c34c9ee4
MR		 13206 /* Perform vblank evasion around commit operation */
13207 if (intel_crtc->active)
13208 intel_crtc->atomic.evade =
13209 intel_pipe_update_start(intel_crtc,
13210 &intel_crtc->atomic.start_vbl_count);
32b7eeec
MR		 13211}
13212
13213static void intel_finish_crtc_commit(struct drm_crtc *crtc)
13214{
13215 struct drm_device *dev = crtc->dev;
13216 struct drm_i915_private *dev_priv = dev->dev_private;
13217 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13218 struct drm_plane *p;
13219
c34c9ee4
MR		 13220 if (intel_crtc->atomic.evade)
13221 intel_pipe_update_end(intel_crtc,
13222 intel_crtc->atomic.start_vbl_count);
3c692a41 13223
140fd38d 13224 intel_runtime_pm_put(dev_priv);
3c692a41 13225
32b7eeec
MR		 13226 if (intel_crtc->atomic.wait_vblank)
13227 intel_wait_for_vblank(dev, intel_crtc->pipe);
13228
13229 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
13230
13231 if (intel_crtc->atomic.update_fbc) {
ccc759dc 13232 mutex_lock(&dev->struct_mutex);
7ff0ebcc 13233 intel_fbc_update(dev);
ccc759dc 13234 mutex_unlock(&dev->struct_mutex);
38f3ce3a 13235 }
3c692a41 13236
32b7eeec
MR		 13237 if (intel_crtc->atomic.post_enable_primary)
13238 intel_post_enable_primary(crtc);
3c692a41 13239
32b7eeec
MR		 13240 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
13241 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
13242 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
13243 false, false);
13244
13245 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
3c692a41
GP		 13246}
13247
cf4c7c12 13248/**
4a3b8769
MR		 13249 * intel_plane_destroy - destroy a plane
13250 * @plane: plane to destroy
cf4c7c12 13251 *
4a3b8769
MR		 13252 * Common destruction function for all types of planes (primary, cursor,
13253 * sprite).
cf4c7c12 13254 */
4a3b8769 13255void intel_plane_destroy(struct drm_plane *plane)
465c120c
MR		 13256{
13257 struct intel_plane *intel_plane = to_intel_plane(plane);
13258 drm_plane_cleanup(plane);
13259 kfree(intel_plane);
13260}
13261
65a3fea0 13262const struct drm_plane_funcs intel_plane_funcs = {
70a101f8
MR		 13263 .update_plane = drm_atomic_helper_update_plane,
13264 .disable_plane = drm_atomic_helper_disable_plane,
3d7d6510 13265 .destroy = intel_plane_destroy,
c196e1d6 13266 .set_property = drm_atomic_helper_plane_set_property,
a98b3431
MR		 13267 .atomic_get_property = intel_plane_atomic_get_property,
13268 .atomic_set_property = intel_plane_atomic_set_property,
ea2c67bb
MR		 13269 .atomic_duplicate_state = intel_plane_duplicate_state,
13270 .atomic_destroy_state = intel_plane_destroy_state,
13271
465c120c
MR		 13272};
13273
13274static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13275 int pipe)
13276{
13277 struct intel_plane *primary;
8e7d688b 13278 struct intel_plane_state *state;
465c120c
MR		 13279 const uint32_t *intel_primary_formats;
13280 int num_formats;
13281
13282 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13283 if (primary == NULL)
13284 return NULL;
13285
8e7d688b
MR		 13286 state = intel_create_plane_state(&primary->base);
13287 if (!state) {
ea2c67bb
MR		 13288 kfree(primary);
13289 return NULL;
13290 }
8e7d688b 13291 primary->base.state = &state->base;
ea2c67bb 13292
465c120c
MR		 13293 primary->can_scale = false;
13294 primary->max_downscale = 1;
6156a456
CK		 13295 if (INTEL_INFO(dev)->gen >= 9) {
13296 primary->can_scale = true;
af99ceda 13297 state->scaler_id = -1;
6156a456 13298 }
465c120c
MR		 13299 primary->pipe = pipe;
13300 primary->plane = pipe;
c59cb179
MR		 13301 primary->check_plane = intel_check_primary_plane;
13302 primary->commit_plane = intel_commit_primary_plane;
a8ad0d8e 13303 primary->disable_plane = intel_disable_primary_plane;
08e221fb 13304 primary->ckey.flags = I915_SET_COLORKEY_NONE;
465c120c
MR		 13305 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13306 primary->plane = !pipe;
13307
6c0fd451
DL		 13308 if (INTEL_INFO(dev)->gen >= 9) {
13309 intel_primary_formats = skl_primary_formats;
13310 num_formats = ARRAY_SIZE(skl_primary_formats);
13311 } else if (INTEL_INFO(dev)->gen >= 4) {
568db4f2
DL		 13312 intel_primary_formats = i965_primary_formats;
13313 num_formats = ARRAY_SIZE(i965_primary_formats);
6c0fd451
DL		 13314 } else {
13315 intel_primary_formats = i8xx_primary_formats;
13316 num_formats = ARRAY_SIZE(i8xx_primary_formats);
465c120c
MR		 13317 }
13318
13319 drm_universal_plane_init(dev, &primary->base, 0,
65a3fea0 13320 &intel_plane_funcs,
465c120c
MR		 13321 intel_primary_formats, num_formats,
13322 DRM_PLANE_TYPE_PRIMARY);
48404c1e 13323
3b7a5119
SJ		 13324 if (INTEL_INFO(dev)->gen >= 4)
13325 intel_create_rotation_property(dev, primary);
48404c1e 13326
ea2c67bb
MR		 13327 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13328
465c120c
MR		 13329 return &primary->base;
13330}
13331
3b7a5119
SJ		 13332void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13333{
13334 if (!dev->mode_config.rotation_property) {
13335 unsigned long flags = BIT(DRM_ROTATE_0) |
13336 BIT(DRM_ROTATE_180);
13337
13338 if (INTEL_INFO(dev)->gen >= 9)
13339 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13340
13341 dev->mode_config.rotation_property =
13342 drm_mode_create_rotation_property(dev, flags);
13343 }
13344 if (dev->mode_config.rotation_property)
13345 drm_object_attach_property(&plane->base.base,
13346 dev->mode_config.rotation_property,
13347 plane->base.state->rotation);
13348}
13349
3d7d6510 13350static int
852e787c
GP		 13351intel_check_cursor_plane(struct drm_plane *plane,
13352 struct intel_plane_state *state)
3d7d6510 13353{
2b875c22 13354 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb 13355 struct drm_device *dev = plane->dev;
2b875c22 13356 struct drm_framebuffer *fb = state->base.fb;
852e787c
GP		 13357 struct drm_rect *dest = &state->dst;
13358 struct drm_rect *src = &state->src;
13359 const struct drm_rect *clip = &state->clip;
757f9a3e 13360 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
ea2c67bb 13361 struct intel_crtc *intel_crtc;
757f9a3e
GP		 13362 unsigned stride;
13363 int ret;
3d7d6510 13364
ea2c67bb
MR		 13365 crtc = crtc ? crtc : plane->crtc;
13366 intel_crtc = to_intel_crtc(crtc);
13367
757f9a3e 13368 ret = drm_plane_helper_check_update(plane, crtc, fb,
852e787c 13369 src, dest, clip,
3d7d6510
MR		 13370 DRM_PLANE_HELPER_NO_SCALING,
13371 DRM_PLANE_HELPER_NO_SCALING,
852e787c 13372 true, true, &state->visible);
757f9a3e
GP		 13373 if (ret)
13374 return ret;
13375
13376
13377 /* if we want to turn off the cursor ignore width and height */
13378 if (!obj)
32b7eeec 13379 goto finish;
757f9a3e 13380
757f9a3e 13381 /* Check for which cursor types we support */
ea2c67bb
MR		 13382 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
13383 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13384 state->base.crtc_w, state->base.crtc_h);
757f9a3e
GP		 13385 return -EINVAL;
13386 }
13387
ea2c67bb
MR		 13388 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13389 if (obj->base.size < stride * state->base.crtc_h) {
757f9a3e
GP		 13390 DRM_DEBUG_KMS("buffer is too small\n");
13391 return -ENOMEM;
13392 }
13393
3a656b54 13394 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
757f9a3e
GP		 13395 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13396 ret = -EINVAL;
13397 }
757f9a3e 13398
32b7eeec
MR		 13399finish:
13400 if (intel_crtc->active) {
3749f463 13401 if (plane->state->crtc_w != state->base.crtc_w)
32b7eeec
MR		 13402 intel_crtc->atomic.update_wm = true;
13403
13404 intel_crtc->atomic.fb_bits |=
13405 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
13406 }
13407
757f9a3e 13408 return ret;
852e787c 13409}
3d7d6510 13410
a8ad0d8e
ML		 13411static void
13412intel_disable_cursor_plane(struct drm_plane *plane,
13413 struct drm_crtc *crtc,
13414 bool force)
13415{
13416 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13417
13418 if (!force) {
13419 plane->fb = NULL;
13420 intel_crtc->cursor_bo = NULL;
13421 intel_crtc->cursor_addr = 0;
13422 }
13423
13424 intel_crtc_update_cursor(crtc, false);
13425}
13426
f4a2cf29 13427static void
852e787c
GP		 13428intel_commit_cursor_plane(struct drm_plane *plane,
13429 struct intel_plane_state *state)
13430{
2b875c22 13431 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb
MR		 13432 struct drm_device *dev = plane->dev;
13433 struct intel_crtc *intel_crtc;
2b875c22 13434 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
a912f12f 13435 uint32_t addr;
852e787c 13436
ea2c67bb
MR		 13437 crtc = crtc ? crtc : plane->crtc;
13438 intel_crtc = to_intel_crtc(crtc);
13439
2b875c22 13440 plane->fb = state->base.fb;
ea2c67bb
MR		 13441 crtc->cursor_x = state->base.crtc_x;
13442 crtc->cursor_y = state->base.crtc_y;
13443
a912f12f
GP		 13444 if (intel_crtc->cursor_bo == obj)
13445 goto update;
4ed91096 13446
f4a2cf29 13447 if (!obj)
a912f12f 13448 addr = 0;
f4a2cf29 13449 else if (!INTEL_INFO(dev)->cursor_needs_physical)
a912f12f 13450 addr = i915_gem_obj_ggtt_offset(obj);
f4a2cf29 13451 else
a912f12f 13452 addr = obj->phys_handle->busaddr;
852e787c 13453
a912f12f
GP		 13454 intel_crtc->cursor_addr = addr;
13455 intel_crtc->cursor_bo = obj;
13456update:
852e787c 13457
32b7eeec 13458 if (intel_crtc->active)
a912f12f 13459 intel_crtc_update_cursor(crtc, state->visible);
852e787c
GP		 13460}
13461
3d7d6510
MR		 13462static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13463 int pipe)
13464{
13465 struct intel_plane *cursor;
8e7d688b 13466 struct intel_plane_state *state;
3d7d6510
MR		 13467
13468 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13469 if (cursor == NULL)
13470 return NULL;
13471
8e7d688b
MR		 13472 state = intel_create_plane_state(&cursor->base);
13473 if (!state) {
ea2c67bb
MR		 13474 kfree(cursor);
13475 return NULL;
13476 }
8e7d688b 13477 cursor->base.state = &state->base;
ea2c67bb 13478
3d7d6510
MR		 13479 cursor->can_scale = false;
13480 cursor->max_downscale = 1;
13481 cursor->pipe = pipe;
13482 cursor->plane = pipe;
c59cb179
MR		 13483 cursor->check_plane = intel_check_cursor_plane;
13484 cursor->commit_plane = intel_commit_cursor_plane;
a8ad0d8e 13485 cursor->disable_plane = intel_disable_cursor_plane;
3d7d6510
MR		 13486
13487 drm_universal_plane_init(dev, &cursor->base, 0,
65a3fea0 13488 &intel_plane_funcs,
3d7d6510
MR		 13489 intel_cursor_formats,
13490 ARRAY_SIZE(intel_cursor_formats),
13491 DRM_PLANE_TYPE_CURSOR);
4398ad45
VS		 13492
13493 if (INTEL_INFO(dev)->gen >= 4) {
13494 if (!dev->mode_config.rotation_property)
13495 dev->mode_config.rotation_property =
13496 drm_mode_create_rotation_property(dev,
13497 BIT(DRM_ROTATE_0) |
13498 BIT(DRM_ROTATE_180));
13499 if (dev->mode_config.rotation_property)
13500 drm_object_attach_property(&cursor->base.base,
13501 dev->mode_config.rotation_property,
8e7d688b 13502 state->base.rotation);
4398ad45
VS		 13503 }
13504
af99ceda
CK		 13505 if (INTEL_INFO(dev)->gen >=9)
13506 state->scaler_id = -1;
13507
ea2c67bb
MR		 13508 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13509
3d7d6510
MR		 13510 return &cursor->base;
13511}
13512
549e2bfb
CK		 13513static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13514 struct intel_crtc_state *crtc_state)
13515{
13516 int i;
13517 struct intel_scaler *intel_scaler;
13518 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13519
13520 for (i = 0; i < intel_crtc->num_scalers; i++) {
13521 intel_scaler = &scaler_state->scalers[i];
13522 intel_scaler->in_use = 0;
13523 intel_scaler->id = i;
13524
13525 intel_scaler->mode = PS_SCALER_MODE_DYN;
13526 }
13527
13528 scaler_state->scaler_id = -1;
13529}
13530
b358d0a6 13531static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 13532{
fbee40df 13533 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 13534 struct intel_crtc *intel_crtc;
f5de6e07 13535 struct intel_crtc_state *crtc_state = NULL;
3d7d6510
MR		 13536 struct drm_plane *primary = NULL;
13537 struct drm_plane *cursor = NULL;
465c120c 13538 int i, ret;
79e53945 13539
955382f3 13540 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB		 13541 if (intel_crtc == NULL)
13542 return;
13543
f5de6e07
ACO		 13544 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13545 if (!crtc_state)
13546 goto fail;
550acefd
ACO		 13547 intel_crtc->config = crtc_state;
13548 intel_crtc->base.state = &crtc_state->base;
07878248 13549 crtc_state->base.crtc = &intel_crtc->base;
f5de6e07 13550
549e2bfb
CK		 13551 /* initialize shared scalers */
13552 if (INTEL_INFO(dev)->gen >= 9) {
13553 if (pipe == PIPE_C)
13554 intel_crtc->num_scalers = 1;
13555 else
13556 intel_crtc->num_scalers = SKL_NUM_SCALERS;
13557
13558 skl_init_scalers(dev, intel_crtc, crtc_state);
13559 }
13560
465c120c 13561 primary = intel_primary_plane_create(dev, pipe);
3d7d6510
MR		 13562 if (!primary)
13563 goto fail;
13564
13565 cursor = intel_cursor_plane_create(dev, pipe);
13566 if (!cursor)
13567 goto fail;
13568
465c120c 13569 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
3d7d6510
MR		 13570 cursor, &intel_crtc_funcs);
13571 if (ret)
13572 goto fail;
79e53945
JB		 13573
13574 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 13575 for (i = 0; i < 256; i++) {
13576 intel_crtc->lut_r[i] = i;
13577 intel_crtc->lut_g[i] = i;
13578 intel_crtc->lut_b[i] = i;
13579 }
13580
1f1c2e24
VS		 13581 /*
13582 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
8c0f92e1 13583 * is hooked to pipe B. Hence we want plane A feeding pipe B.
1f1c2e24 13584 */
80824003
JB		 13585 intel_crtc->pipe = pipe;
13586 intel_crtc->plane = pipe;
3a77c4c4 13587 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
28c97730 13588 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 13589 intel_crtc->plane = !pipe;
80824003
JB		 13590 }
13591
4b0e333e
CW		 13592 intel_crtc->cursor_base = ~0;
13593 intel_crtc->cursor_cntl = ~0;
dc41c154 13594 intel_crtc->cursor_size = ~0;
8d7849db 13595
22fd0fab
JB		 13596 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13597 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13598 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13599 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13600
79e53945 13601 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
87b6b101
DV		 13602
13603 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
3d7d6510
MR		 13604 return;
13605
13606fail:
13607 if (primary)
13608 drm_plane_cleanup(primary);
13609 if (cursor)
13610 drm_plane_cleanup(cursor);
f5de6e07 13611 kfree(crtc_state);
3d7d6510 13612 kfree(intel_crtc);
79e53945
JB		 13613}
13614
752aa88a
JB		 13615enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13616{
13617 struct drm_encoder *encoder = connector->base.encoder;
6e9f798d 13618 struct drm_device *dev = connector->base.dev;
752aa88a 13619
51fd371b 13620 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
752aa88a 13621
d3babd3f 13622 if (!encoder || WARN_ON(!encoder->crtc))
752aa88a
JB		 13623 return INVALID_PIPE;
13624
13625 return to_intel_crtc(encoder->crtc)->pipe;
13626}
13627
08d7b3d1 13628int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 13629 struct drm_file *file)
08d7b3d1 13630{
08d7b3d1 13631 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7707e653 13632 struct drm_crtc *drmmode_crtc;
c05422d5 13633 struct intel_crtc *crtc;
08d7b3d1 13634
7707e653 13635 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
08d7b3d1 13636
7707e653 13637 if (!drmmode_crtc) {
08d7b3d1 13638 DRM_ERROR("no such CRTC id\n");
3f2c2057 13639 return -ENOENT;
08d7b3d1
CW		 13640 }
13641
7707e653 13642 crtc = to_intel_crtc(drmmode_crtc);
c05422d5 13643 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 13644
c05422d5 13645 return 0;
08d7b3d1
CW		 13646}
13647
66a9278e 13648static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 13649{
66a9278e
DV		 13650 struct drm_device *dev = encoder->base.dev;
13651 struct intel_encoder *source_encoder;
79e53945 13652 int index_mask = 0;
79e53945
JB		 13653 int entry = 0;
13654
b2784e15 13655 for_each_intel_encoder(dev, source_encoder) {
bc079e8b 13656 if (encoders_cloneable(encoder, source_encoder))
66a9278e
DV		 13657 index_mask |= (1 << entry);
13658
79e53945
JB		 13659 entry++;
13660 }
4ef69c7a 13661
79e53945
JB		 13662 return index_mask;
13663}
13664
4d302442
CW		 13665static bool has_edp_a(struct drm_device *dev)
13666{
13667 struct drm_i915_private *dev_priv = dev->dev_private;
13668
13669 if (!IS_MOBILE(dev))
13670 return false;
13671
13672 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13673 return false;
13674
e3589908 13675 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
4d302442
CW		 13676 return false;
13677
13678 return true;
13679}
13680
84b4e042
JB		 13681static bool intel_crt_present(struct drm_device *dev)
13682{
13683 struct drm_i915_private *dev_priv = dev->dev_private;
13684
884497ed
DL		 13685 if (INTEL_INFO(dev)->gen >= 9)
13686 return false;
13687
cf404ce4 13688 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
84b4e042
JB		 13689 return false;
13690
13691 if (IS_CHERRYVIEW(dev))
13692 return false;
13693
13694 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
13695 return false;
13696
13697 return true;
13698}
13699
79e53945
JB		 13700static void intel_setup_outputs(struct drm_device *dev)
13701{
725e30ad 13702 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 13703 struct intel_encoder *encoder;
cb0953d7 13704 bool dpd_is_edp = false;
79e53945 13705
c9093354 13706 intel_lvds_init(dev);
79e53945 13707
84b4e042 13708 if (intel_crt_present(dev))
79935fca 13709 intel_crt_init(dev);
cb0953d7 13710
c776eb2e
VK		 13711 if (IS_BROXTON(dev)) {
13712 /*
13713 * FIXME: Broxton doesn't support port detection via the
13714 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13715 * detect the ports.
13716 */
13717 intel_ddi_init(dev, PORT_A);
13718 intel_ddi_init(dev, PORT_B);
13719 intel_ddi_init(dev, PORT_C);
13720 } else if (HAS_DDI(dev)) {
0e72a5b5
ED		 13721 int found;
13722
de31facd
JB		 13723 /*
13724 * Haswell uses DDI functions to detect digital outputs.
13725 * On SKL pre-D0 the strap isn't connected, so we assume
13726 * it's there.
13727 */
0e72a5b5 13728 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
de31facd
JB		 13729 /* WaIgnoreDDIAStrap: skl */
13730 if (found ||
13731 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
0e72a5b5
ED		 13732 intel_ddi_init(dev, PORT_A);
13733
13734 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13735 * register */
13736 found = I915_READ(SFUSE_STRAP);
13737
13738 if (found & SFUSE_STRAP_DDIB_DETECTED)
13739 intel_ddi_init(dev, PORT_B);
13740 if (found & SFUSE_STRAP_DDIC_DETECTED)
13741 intel_ddi_init(dev, PORT_C);
13742 if (found & SFUSE_STRAP_DDID_DETECTED)
13743 intel_ddi_init(dev, PORT_D);
13744 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 13745 int found;
5d8a7752 13746 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
270b3042
DV		 13747
13748 if (has_edp_a(dev))
13749 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 13750
dc0fa718 13751 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 13752 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 13753 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 13754 if (!found)
e2debe91 13755 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 13756 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 13757 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 13758 }
13759
dc0fa718 13760 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 13761 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 13762
dc0fa718 13763 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 13764 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 13765
5eb08b69 13766 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 13767 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 13768
270b3042 13769 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 13770 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 13771 } else if (IS_VALLEYVIEW(dev)) {
e17ac6db
VS		 13772 /*
13773 * The DP_DETECTED bit is the latched state of the DDC
13774 * SDA pin at boot. However since eDP doesn't require DDC
13775 * (no way to plug in a DP->HDMI dongle) the DDC pins for
13776 * eDP ports may have been muxed to an alternate function.
13777 * Thus we can't rely on the DP_DETECTED bit alone to detect
13778 * eDP ports. Consult the VBT as well as DP_DETECTED to
13779 * detect eDP ports.
13780 */
d2182a66
VS		 13781 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
13782 !intel_dp_is_edp(dev, PORT_B))
585a94b8
AB		 13783 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
13784 PORT_B);
e17ac6db
VS		 13785 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
13786 intel_dp_is_edp(dev, PORT_B))
13787 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
585a94b8 13788
d2182a66
VS		 13789 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
13790 !intel_dp_is_edp(dev, PORT_C))
6f6005a5
JB		 13791 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
13792 PORT_C);
e17ac6db
VS		 13793 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
13794 intel_dp_is_edp(dev, PORT_C))
13795 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 13796
9418c1f1 13797 if (IS_CHERRYVIEW(dev)) {
e17ac6db 13798 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
9418c1f1
VS		 13799 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
13800 PORT_D);
e17ac6db
VS		 13801 /* eDP not supported on port D, so don't check VBT */
13802 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
13803 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
9418c1f1
VS		 13804 }
13805
3cfca973 13806 intel_dsi_init(dev);
103a196f 13807 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 13808 bool found = false;
7d57382e 13809
e2debe91 13810 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 13811 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 13812 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 13813 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
13814 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 13815 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 13816 }
27185ae1 13817
e7281eab 13818 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 13819 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 13820 }
13520b05
KH		 13821
13822 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 13823
e2debe91 13824 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 13825 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 13826 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 13827 }
27185ae1 13828
e2debe91 13829 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 13830
b01f2c3a
JB		 13831 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
13832 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 13833 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 13834 }
e7281eab 13835 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 13836 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 13837 }
27185ae1 13838
b01f2c3a 13839 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 13840 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 13841 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 13842 } else if (IS_GEN2(dev))
79e53945
JB		 13843 intel_dvo_init(dev);
13844
103a196f 13845 if (SUPPORTS_TV(dev))
79e53945
JB		 13846 intel_tv_init(dev);
13847
0bc12bcb 13848 intel_psr_init(dev);
7c8f8a70 13849
b2784e15 13850 for_each_intel_encoder(dev, encoder) {
4ef69c7a
CW		 13851 encoder->base.possible_crtcs = encoder->crtc_mask;
13852 encoder->base.possible_clones =
66a9278e 13853 intel_encoder_clones(encoder);
79e53945 13854 }
47356eb6 13855
dde86e2d 13856 intel_init_pch_refclk(dev);
270b3042
DV		 13857
13858 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 13859}
13860
13861static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
13862{
60a5ca01 13863 struct drm_device *dev = fb->dev;
79e53945 13864 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 13865
ef2d633e 13866 drm_framebuffer_cleanup(fb);
60a5ca01 13867 mutex_lock(&dev->struct_mutex);
ef2d633e 13868 WARN_ON(!intel_fb->obj->framebuffer_references--);
60a5ca01
VS		 13869 drm_gem_object_unreference(&intel_fb->obj->base);
13870 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 13871 kfree(intel_fb);
13872}
13873
13874static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 13875 struct drm_file *file,
79e53945
JB		 13876 unsigned int *handle)
13877{
13878 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 13879 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 13880
05394f39 13881 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 13882}
13883
13884static const struct drm_framebuffer_funcs intel_fb_funcs = {
13885 .destroy = intel_user_framebuffer_destroy,
13886 .create_handle = intel_user_framebuffer_create_handle,
13887};
13888
b321803d
DL		 13889static
13890u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
13891 uint32_t pixel_format)
13892{
13893 u32 gen = INTEL_INFO(dev)->gen;
13894
13895 if (gen >= 9) {
13896 /* "The stride in bytes must not exceed the of the size of 8K
13897 * pixels and 32K bytes."
13898 */
13899 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
13900 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
13901 return 32*1024;
13902 } else if (gen >= 4) {
13903 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13904 return 16*1024;
13905 else
13906 return 32*1024;
13907 } else if (gen >= 3) {
13908 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13909 return 8*1024;
13910 else
13911 return 16*1024;
13912 } else {
13913 /* XXX DSPC is limited to 4k tiled */
13914 return 8*1024;
13915 }
13916}
13917
b5ea642a
DV		 13918static int intel_framebuffer_init(struct drm_device *dev,
13919 struct intel_framebuffer *intel_fb,
13920 struct drm_mode_fb_cmd2 *mode_cmd,
13921 struct drm_i915_gem_object *obj)
79e53945 13922{
6761dd31 13923 unsigned int aligned_height;
79e53945 13924 int ret;
b321803d 13925 u32 pitch_limit, stride_alignment;
79e53945 13926
dd4916c5
DV		 13927 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
13928
2a80eada
DV		 13929 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
13930 /* Enforce that fb modifier and tiling mode match, but only for
13931 * X-tiled. This is needed for FBC. */
13932 if (!!(obj->tiling_mode == I915_TILING_X) !=
13933 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
13934 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
13935 return -EINVAL;
13936 }
13937 } else {
13938 if (obj->tiling_mode == I915_TILING_X)
13939 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
13940 else if (obj->tiling_mode == I915_TILING_Y) {
13941 DRM_DEBUG("No Y tiling for legacy addfb\n");
13942 return -EINVAL;
13943 }
13944 }
13945
9a8f0a12
TU		 13946 /* Passed in modifier sanity checking. */
13947 switch (mode_cmd->modifier[0]) {
13948 case I915_FORMAT_MOD_Y_TILED:
13949 case I915_FORMAT_MOD_Yf_TILED:
13950 if (INTEL_INFO(dev)->gen < 9) {
13951 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
13952 mode_cmd->modifier[0]);
13953 return -EINVAL;
13954 }
13955 case DRM_FORMAT_MOD_NONE:
13956 case I915_FORMAT_MOD_X_TILED:
13957 break;
13958 default:
c0f40428
JB		 13959 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
13960 mode_cmd->modifier[0]);
57cd6508 13961 return -EINVAL;
c16ed4be 13962 }
57cd6508 13963
b321803d
DL		 13964 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
13965 mode_cmd->pixel_format);
13966 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
13967 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
13968 mode_cmd->pitches[0], stride_alignment);
57cd6508 13969 return -EINVAL;
c16ed4be 13970 }
57cd6508 13971
b321803d
DL		 13972 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
13973 mode_cmd->pixel_format);
a35cdaa0 13974 if (mode_cmd->pitches[0] > pitch_limit) {
b321803d
DL		 13975 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
13976 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
2a80eada 13977 "tiled" : "linear",
a35cdaa0 13978 mode_cmd->pitches[0], pitch_limit);
5d7bd705 13979 return -EINVAL;
c16ed4be 13980 }
5d7bd705 13981
2a80eada 13982 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
c16ed4be
CW		 13983 mode_cmd->pitches[0] != obj->stride) {
13984 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
13985 mode_cmd->pitches[0], obj->stride);
5d7bd705 13986 return -EINVAL;
c16ed4be 13987 }
5d7bd705 13988
57779d06 13989 /* Reject formats not supported by any plane early. */
308e5bcb 13990 switch (mode_cmd->pixel_format) {
57779d06 13991 case DRM_FORMAT_C8:
04b3924d
VS		 13992 case DRM_FORMAT_RGB565:
13993 case DRM_FORMAT_XRGB8888:
13994 case DRM_FORMAT_ARGB8888:
57779d06
VS		 13995 break;
13996 case DRM_FORMAT_XRGB1555:
c16ed4be 13997 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 13998 DRM_DEBUG("unsupported pixel format: %s\n",
13999 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14000 return -EINVAL;
c16ed4be 14001 }
57779d06 14002 break;
57779d06 14003 case DRM_FORMAT_ABGR8888:
6c0fd451
DL		 14004 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14005 DRM_DEBUG("unsupported pixel format: %s\n",
14006 drm_get_format_name(mode_cmd->pixel_format));
14007 return -EINVAL;
14008 }
14009 break;
14010 case DRM_FORMAT_XBGR8888:
04b3924d 14011 case DRM_FORMAT_XRGB2101010:
57779d06 14012 case DRM_FORMAT_XBGR2101010:
c16ed4be 14013 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 14014 DRM_DEBUG("unsupported pixel format: %s\n",
14015 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14016 return -EINVAL;
c16ed4be 14017 }
b5626747 14018 break;
7531208b
DL		 14019 case DRM_FORMAT_ABGR2101010:
14020 if (!IS_VALLEYVIEW(dev)) {
14021 DRM_DEBUG("unsupported pixel format: %s\n",
14022 drm_get_format_name(mode_cmd->pixel_format));
14023 return -EINVAL;
14024 }
14025 break;
04b3924d
VS		 14026 case DRM_FORMAT_YUYV:
14027 case DRM_FORMAT_UYVY:
14028 case DRM_FORMAT_YVYU:
14029 case DRM_FORMAT_VYUY:
c16ed4be 14030 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 14031 DRM_DEBUG("unsupported pixel format: %s\n",
14032 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14033 return -EINVAL;
c16ed4be 14034 }
57cd6508
CW		 14035 break;
14036 default:
4ee62c76
VS		 14037 DRM_DEBUG("unsupported pixel format: %s\n",
14038 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 14039 return -EINVAL;
14040 }
14041
90f9a336
VS		 14042 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14043 if (mode_cmd->offsets[0] != 0)
14044 return -EINVAL;
14045
ec2c981e 14046 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
091df6cb
DV		 14047 mode_cmd->pixel_format,
14048 mode_cmd->modifier[0]);
53155c0a
DV		 14049 /* FIXME drm helper for size checks (especially planar formats)? */
14050 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14051 return -EINVAL;
14052
c7d73f6a
DV		 14053 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14054 intel_fb->obj = obj;
80075d49 14055 intel_fb->obj->framebuffer_references++;
c7d73f6a 14056
79e53945
JB		 14057 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14058 if (ret) {
14059 DRM_ERROR("framebuffer init failed %d\n", ret);
14060 return ret;
14061 }
14062
79e53945
JB		 14063 return 0;
14064}
14065
79e53945
JB		 14066static struct drm_framebuffer *
14067intel_user_framebuffer_create(struct drm_device *dev,
14068 struct drm_file *filp,
308e5bcb 14069 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 14070{
05394f39 14071 struct drm_i915_gem_object *obj;
79e53945 14072
308e5bcb
JB		 14073 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14074 mode_cmd->handles[0]));
c8725226 14075 if (&obj->base == NULL)
cce13ff7 14076 return ERR_PTR(-ENOENT);
79e53945 14077
d2dff872 14078 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 14079}
14080
4520f53a 14081#ifndef CONFIG_DRM_I915_FBDEV
0632fef6 14082static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
4520f53a
DV		 14083{
14084}
14085#endif
14086
79e53945 14087static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 14088 .fb_create = intel_user_framebuffer_create,
0632fef6 14089 .output_poll_changed = intel_fbdev_output_poll_changed,
5ee67f1c
MR		 14090 .atomic_check = intel_atomic_check,
14091 .atomic_commit = intel_atomic_commit,
79e53945
JB		 14092};
14093
e70236a8
JB		 14094/* Set up chip specific display functions */
14095static void intel_init_display(struct drm_device *dev)
14096{
14097 struct drm_i915_private *dev_priv = dev->dev_private;
14098
ee9300bb
DV		 14099 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14100 dev_priv->display.find_dpll = g4x_find_best_dpll;
ef9348c8
CML		 14101 else if (IS_CHERRYVIEW(dev))
14102 dev_priv->display.find_dpll = chv_find_best_dpll;
ee9300bb
DV		 14103 else if (IS_VALLEYVIEW(dev))
14104 dev_priv->display.find_dpll = vlv_find_best_dpll;
14105 else if (IS_PINEVIEW(dev))
14106 dev_priv->display.find_dpll = pnv_find_best_dpll;
14107 else
14108 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14109
bc8d7dff
DL		 14110 if (INTEL_INFO(dev)->gen >= 9) {
14111 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14112 dev_priv->display.get_initial_plane_config =
14113 skylake_get_initial_plane_config;
bc8d7dff
DL		 14114 dev_priv->display.crtc_compute_clock =
14115 haswell_crtc_compute_clock;
14116 dev_priv->display.crtc_enable = haswell_crtc_enable;
14117 dev_priv->display.crtc_disable = haswell_crtc_disable;
14118 dev_priv->display.off = ironlake_crtc_off;
14119 dev_priv->display.update_primary_plane =
14120 skylake_update_primary_plane;
14121 } else if (HAS_DDI(dev)) {
0e8ffe1b 14122 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14123 dev_priv->display.get_initial_plane_config =
14124 ironlake_get_initial_plane_config;
797d0259
ACO		 14125 dev_priv->display.crtc_compute_clock =
14126 haswell_crtc_compute_clock;
4f771f10
PZ		 14127 dev_priv->display.crtc_enable = haswell_crtc_enable;
14128 dev_priv->display.crtc_disable = haswell_crtc_disable;
df8ad70c 14129 dev_priv->display.off = ironlake_crtc_off;
bc8d7dff
DL		 14130 dev_priv->display.update_primary_plane =
14131 ironlake_update_primary_plane;
09b4ddf9 14132 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 14133 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
5724dbd1
DL		 14134 dev_priv->display.get_initial_plane_config =
14135 ironlake_get_initial_plane_config;
3fb37703
ACO		 14136 dev_priv->display.crtc_compute_clock =
14137 ironlake_crtc_compute_clock;
76e5a89c
DV		 14138 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14139 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 14140 dev_priv->display.off = ironlake_crtc_off;
262ca2b0
MR		 14141 dev_priv->display.update_primary_plane =
14142 ironlake_update_primary_plane;
89b667f8
JB		 14143 } else if (IS_VALLEYVIEW(dev)) {
14144 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14145 dev_priv->display.get_initial_plane_config =
14146 i9xx_get_initial_plane_config;
d6dfee7a 14147 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
89b667f8
JB		 14148 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14149 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14150 dev_priv->display.off = i9xx_crtc_off;
262ca2b0
MR		 14151 dev_priv->display.update_primary_plane =
14152 i9xx_update_primary_plane;
f564048e 14153 } else {
0e8ffe1b 14154 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14155 dev_priv->display.get_initial_plane_config =
14156 i9xx_get_initial_plane_config;
d6dfee7a 14157 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
76e5a89c
DV		 14158 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14159 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 14160 dev_priv->display.off = i9xx_crtc_off;
262ca2b0
MR		 14161 dev_priv->display.update_primary_plane =
14162 i9xx_update_primary_plane;
f564048e 14163 }
e70236a8 14164
e70236a8 14165 /* Returns the core display clock speed */
1652d19e
VS		 14166 if (IS_SKYLAKE(dev))
14167 dev_priv->display.get_display_clock_speed =
14168 skylake_get_display_clock_speed;
14169 else if (IS_BROADWELL(dev))
14170 dev_priv->display.get_display_clock_speed =
14171 broadwell_get_display_clock_speed;
14172 else if (IS_HASWELL(dev))
14173 dev_priv->display.get_display_clock_speed =
14174 haswell_get_display_clock_speed;
14175 else if (IS_VALLEYVIEW(dev))
25eb05fc
JB		 14176 dev_priv->display.get_display_clock_speed =
14177 valleyview_get_display_clock_speed;
b37a6434
VS		 14178 else if (IS_GEN5(dev))
14179 dev_priv->display.get_display_clock_speed =
14180 ilk_get_display_clock_speed;
a7c66cd8
VS		 14181 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14182 IS_GEN6(dev) || IS_IVYBRIDGE(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 14183 dev_priv->display.get_display_clock_speed =
14184 i945_get_display_clock_speed;
14185 else if (IS_I915G(dev))
14186 dev_priv->display.get_display_clock_speed =
14187 i915_get_display_clock_speed;
257a7ffc 14188 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 14189 dev_priv->display.get_display_clock_speed =
14190 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 14191 else if (IS_PINEVIEW(dev))
14192 dev_priv->display.get_display_clock_speed =
14193 pnv_get_display_clock_speed;
e70236a8
JB		 14194 else if (IS_I915GM(dev))
14195 dev_priv->display.get_display_clock_speed =
14196 i915gm_get_display_clock_speed;
14197 else if (IS_I865G(dev))
14198 dev_priv->display.get_display_clock_speed =
14199 i865_get_display_clock_speed;
f0f8a9ce 14200 else if (IS_I85X(dev))
e70236a8
JB		 14201 dev_priv->display.get_display_clock_speed =
14202 i855_get_display_clock_speed;
14203 else /* 852, 830 */
14204 dev_priv->display.get_display_clock_speed =
14205 i830_get_display_clock_speed;
14206
7c10a2b5 14207 if (IS_GEN5(dev)) {
3bb11b53 14208 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
3bb11b53
SJ		 14209 } else if (IS_GEN6(dev)) {
14210 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
3bb11b53
SJ		 14211 } else if (IS_IVYBRIDGE(dev)) {
14212 /* FIXME: detect B0+ stepping and use auto training */
14213 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
059b2fe9 14214 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3bb11b53 14215 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
30a970c6
JB		 14216 } else if (IS_VALLEYVIEW(dev)) {
14217 dev_priv->display.modeset_global_resources =
14218 valleyview_modeset_global_resources;
f8437dd1
VK		 14219 } else if (IS_BROXTON(dev)) {
14220 dev_priv->display.modeset_global_resources =
14221 broxton_modeset_global_resources;
e70236a8 14222 }
8c9f3aaf 14223
8c9f3aaf
JB		 14224 switch (INTEL_INFO(dev)->gen) {
14225 case 2:
14226 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14227 break;
14228
14229 case 3:
14230 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14231 break;
14232
14233 case 4:
14234 case 5:
14235 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14236 break;
14237
14238 case 6:
14239 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14240 break;
7c9017e5 14241 case 7:
4e0bbc31 14242 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
7c9017e5
JB		 14243 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14244 break;
830c81db 14245 case 9:
ba343e02
TU		 14246 /* Drop through - unsupported since execlist only. */
14247 default:
14248 /* Default just returns -ENODEV to indicate unsupported */
14249 dev_priv->display.queue_flip = intel_default_queue_flip;
8c9f3aaf 14250 }
7bd688cd
JN		 14251
14252 intel_panel_init_backlight_funcs(dev);
e39b999a
VS		 14253
14254 mutex_init(&dev_priv->pps_mutex);
e70236a8
JB		 14255}
14256
b690e96c
JB		 14257/*
14258 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14259 * resume, or other times. This quirk makes sure that's the case for
14260 * affected systems.
14261 */
0206e353 14262static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 14263{
14264 struct drm_i915_private *dev_priv = dev->dev_private;
14265
14266 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 14267 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 14268}
14269
b6b5d049
VS		 14270static void quirk_pipeb_force(struct drm_device *dev)
14271{
14272 struct drm_i915_private *dev_priv = dev->dev_private;
14273
14274 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14275 DRM_INFO("applying pipe b force quirk\n");
14276}
14277
435793df
KP		 14278/*
14279 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14280 */
14281static void quirk_ssc_force_disable(struct drm_device *dev)
14282{
14283 struct drm_i915_private *dev_priv = dev->dev_private;
14284 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 14285 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 14286}
14287
4dca20ef 14288/*
5a15ab5b
CE		 14289 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14290 * brightness value
4dca20ef
CE		 14291 */
14292static void quirk_invert_brightness(struct drm_device *dev)
14293{
14294 struct drm_i915_private *dev_priv = dev->dev_private;
14295 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 14296 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 14297}
14298
9c72cc6f
SD		 14299/* Some VBT's incorrectly indicate no backlight is present */
14300static void quirk_backlight_present(struct drm_device *dev)
14301{
14302 struct drm_i915_private *dev_priv = dev->dev_private;
14303 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14304 DRM_INFO("applying backlight present quirk\n");
14305}
14306
b690e96c
JB		 14307struct intel_quirk {
14308 int device;
14309 int subsystem_vendor;
14310 int subsystem_device;
14311 void (*hook)(struct drm_device *dev);
14312};
14313
5f85f176
EE		 14314/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14315struct intel_dmi_quirk {
14316 void (*hook)(struct drm_device *dev);
14317 const struct dmi_system_id (*dmi_id_list)[];
14318};
14319
14320static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14321{
14322 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14323 return 1;
14324}
14325
14326static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14327 {
14328 .dmi_id_list = &(const struct dmi_system_id[]) {
14329 {
14330 .callback = intel_dmi_reverse_brightness,
14331 .ident = "NCR Corporation",
14332 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14333 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14334 },
14335 },
14336 { } /* terminating entry */
14337 },
14338 .hook = quirk_invert_brightness,
14339 },
14340};
14341
c43b5634 14342static struct intel_quirk intel_quirks[] = {
b690e96c
JB		 14343 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14344 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14345
b690e96c
JB		 14346 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14347 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14348
5f080c0f
VS		 14349 /* 830 needs to leave pipe A & dpll A up */
14350 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14351
b6b5d049
VS		 14352 /* 830 needs to leave pipe B & dpll B up */
14353 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14354
435793df
KP		 14355 /* Lenovo U160 cannot use SSC on LVDS */
14356 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 14357
14358 /* Sony Vaio Y cannot use SSC on LVDS */
14359 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 14360
be505f64
AH		 14361 /* Acer Aspire 5734Z must invert backlight brightness */
14362 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14363
14364 /* Acer/eMachines G725 */
14365 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14366
14367 /* Acer/eMachines e725 */
14368 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14369
14370 /* Acer/Packard Bell NCL20 */
14371 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14372
14373 /* Acer Aspire 4736Z */
14374 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
0f540c3a
JN		 14375
14376 /* Acer Aspire 5336 */
14377 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
2e93a1aa
SD		 14378
14379 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14380 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
d4967d8c 14381
dfb3d47b
SD		 14382 /* Acer C720 Chromebook (Core i3 4005U) */
14383 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14384
b2a9601c 14385 /* Apple Macbook 2,1 (Core 2 T7400) */
14386 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14387
d4967d8c
SD		 14388 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14389 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
724cb06f
SD		 14390
14391 /* HP Chromebook 14 (Celeron 2955U) */
14392 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
cf6f0af9
JN		 14393
14394 /* Dell Chromebook 11 */
14395 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
b690e96c
JB		 14396};
14397
14398static void intel_init_quirks(struct drm_device *dev)
14399{
14400 struct pci_dev *d = dev->pdev;
14401 int i;
14402
14403 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14404 struct intel_quirk *q = &intel_quirks[i];
14405
14406 if (d->device == q->device &&
14407 (d->subsystem_vendor == q->subsystem_vendor ||
14408 q->subsystem_vendor == PCI_ANY_ID) &&
14409 (d->subsystem_device == q->subsystem_device ||
14410 q->subsystem_device == PCI_ANY_ID))
14411 q->hook(dev);
14412 }
5f85f176
EE		 14413 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14414 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14415 intel_dmi_quirks[i].hook(dev);
14416 }
b690e96c
JB		 14417}
14418
9cce37f4
JB		 14419/* Disable the VGA plane that we never use */
14420static void i915_disable_vga(struct drm_device *dev)
14421{
14422 struct drm_i915_private *dev_priv = dev->dev_private;
14423 u8 sr1;
766aa1c4 14424 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4 14425
2b37c616 14426 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
9cce37f4 14427 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 14428 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 14429 sr1 = inb(VGA_SR_DATA);
14430 outb(sr1 | 1<<5, VGA_SR_DATA);
14431 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14432 udelay(300);
14433
01f5a626 14434 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9cce37f4
JB		 14435 POSTING_READ(vga_reg);
14436}
14437
f817586c
DV		 14438void intel_modeset_init_hw(struct drm_device *dev)
14439{
a8f78b58
ED		 14440 intel_prepare_ddi(dev);
14441
f8bf63fd
VS		 14442 if (IS_VALLEYVIEW(dev))
14443 vlv_update_cdclk(dev);
14444
f817586c
DV		 14445 intel_init_clock_gating(dev);
14446
8090c6b9 14447 intel_enable_gt_powersave(dev);
f817586c
DV		 14448}
14449
79e53945
JB		 14450void intel_modeset_init(struct drm_device *dev)
14451{
652c393a 14452 struct drm_i915_private *dev_priv = dev->dev_private;
1fe47785 14453 int sprite, ret;
8cc87b75 14454 enum pipe pipe;
46f297fb 14455 struct intel_crtc *crtc;
79e53945
JB		 14456
14457 drm_mode_config_init(dev);
14458
14459 dev->mode_config.min_width = 0;
14460 dev->mode_config.min_height = 0;
14461
019d96cb
DA		 14462 dev->mode_config.preferred_depth = 24;
14463 dev->mode_config.prefer_shadow = 1;
14464
25bab385
TU		 14465 dev->mode_config.allow_fb_modifiers = true;
14466
e6ecefaa 14467 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 14468
b690e96c
JB		 14469 intel_init_quirks(dev);
14470
1fa61106
ED		 14471 intel_init_pm(dev);
14472
e3c74757
BW		 14473 if (INTEL_INFO(dev)->num_pipes == 0)
14474 return;
14475
e70236a8 14476 intel_init_display(dev);
7c10a2b5 14477 intel_init_audio(dev);
e70236a8 14478
a6c45cf0
CW		 14479 if (IS_GEN2(dev)) {
14480 dev->mode_config.max_width = 2048;
14481 dev->mode_config.max_height = 2048;
14482 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 14483 dev->mode_config.max_width = 4096;
14484 dev->mode_config.max_height = 4096;
79e53945 14485 } else {
a6c45cf0
CW		 14486 dev->mode_config.max_width = 8192;
14487 dev->mode_config.max_height = 8192;
79e53945 14488 }
068be561 14489
dc41c154
VS		 14490 if (IS_845G(dev) || IS_I865G(dev)) {
14491 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14492 dev->mode_config.cursor_height = 1023;
14493 } else if (IS_GEN2(dev)) {
068be561
DL		 14494 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14495 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14496 } else {
14497 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14498 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14499 }
14500
5d4545ae 14501 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 14502
28c97730 14503 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 14504 INTEL_INFO(dev)->num_pipes,
14505 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 14506
055e393f 14507 for_each_pipe(dev_priv, pipe) {
8cc87b75 14508 intel_crtc_init(dev, pipe);
3bdcfc0c 14509 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 14510 ret = intel_plane_init(dev, pipe, sprite);
7f1f3851 14511 if (ret)
06da8da2 14512 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
1fe47785 14513 pipe_name(pipe), sprite_name(pipe, sprite), ret);
7f1f3851 14514 }
79e53945
JB		 14515 }
14516
f42bb70d
JB		 14517 intel_init_dpio(dev);
14518
e72f9fbf 14519 intel_shared_dpll_init(dev);
ee7b9f93 14520
9cce37f4
JB		 14521 /* Just disable it once at startup */
14522 i915_disable_vga(dev);
79e53945 14523 intel_setup_outputs(dev);
11be49eb
CW		 14524
14525 /* Just in case the BIOS is doing something questionable. */
7ff0ebcc 14526 intel_fbc_disable(dev);
fa9fa083 14527
6e9f798d 14528 drm_modeset_lock_all(dev);
fa9fa083 14529 intel_modeset_setup_hw_state(dev, false);
6e9f798d 14530 drm_modeset_unlock_all(dev);
46f297fb 14531
d3fcc808 14532 for_each_intel_crtc(dev, crtc) {
46f297fb
JB		 14533 if (!crtc->active)
14534 continue;
14535
46f297fb 14536 /*
46f297fb
JB		 14537 * Note that reserving the BIOS fb up front prevents us
14538 * from stuffing other stolen allocations like the ring
14539 * on top. This prevents some ugliness at boot time, and
14540 * can even allow for smooth boot transitions if the BIOS
14541 * fb is large enough for the active pipe configuration.
14542 */
5724dbd1
DL		 14543 if (dev_priv->display.get_initial_plane_config) {
14544 dev_priv->display.get_initial_plane_config(crtc,
46f297fb
JB		 14545 &crtc->plane_config);
14546 /*
14547 * If the fb is shared between multiple heads, we'll
14548 * just get the first one.
14549 */
f6936e29 14550 intel_find_initial_plane_obj(crtc, &crtc->plane_config);
46f297fb 14551 }
46f297fb 14552 }
2c7111db
CW		 14553}
14554
7fad798e
DV		 14555static void intel_enable_pipe_a(struct drm_device *dev)
14556{
14557 struct intel_connector *connector;
14558 struct drm_connector *crt = NULL;
14559 struct intel_load_detect_pipe load_detect_temp;
208bf9fd 14560 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
7fad798e
DV		 14561
14562 /* We can't just switch on the pipe A, we need to set things up with a
14563 * proper mode and output configuration. As a gross hack, enable pipe A
14564 * by enabling the load detect pipe once. */
3a3371ff 14565 for_each_intel_connector(dev, connector) {
7fad798e
DV		 14566 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14567 crt = &connector->base;
14568 break;
14569 }
14570 }
14571
14572 if (!crt)
14573 return;
14574
208bf9fd 14575 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
49172fee 14576 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
7fad798e
DV		 14577}
14578
fa555837
DV		 14579static bool
14580intel_check_plane_mapping(struct intel_crtc *crtc)
14581{
7eb552ae
BW		 14582 struct drm_device *dev = crtc->base.dev;
14583 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 14584 u32 reg, val;
14585
7eb552ae 14586 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 14587 return true;
14588
14589 reg = DSPCNTR(!crtc->plane);
14590 val = I915_READ(reg);
14591
14592 if ((val & DISPLAY_PLANE_ENABLE) &&
14593 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14594 return false;
14595
14596 return true;
14597}
14598
24929352
DV		 14599static void intel_sanitize_crtc(struct intel_crtc *crtc)
14600{
14601 struct drm_device *dev = crtc->base.dev;
14602 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 14603 u32 reg;
24929352 14604
24929352 14605 /* Clear any frame start delays used for debugging left by the BIOS */
6e3c9717 14606 reg = PIPECONF(crtc->config->cpu_transcoder);
24929352
DV		 14607 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14608
d3eaf884 14609 /* restore vblank interrupts to correct state */
9625604c 14610 drm_crtc_vblank_reset(&crtc->base);
d297e103
VS		 14611 if (crtc->active) {
14612 update_scanline_offset(crtc);
9625604c
DV		 14613 drm_crtc_vblank_on(&crtc->base);
14614 }
d3eaf884 14615
24929352 14616 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 14617 * disable the crtc (and hence change the state) if it is wrong. Note
14618 * that gen4+ has a fixed plane -> pipe mapping. */
14619 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 14620 struct intel_connector *connector;
14621 bool plane;
14622
24929352
DV		 14623 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14624 crtc->base.base.id);
14625
14626 /* Pipe has the wrong plane attached and the plane is active.
14627 * Temporarily change the plane mapping and disable everything
14628 * ... */
14629 plane = crtc->plane;
b70709a6 14630 to_intel_plane_state(crtc->base.primary->state)->visible = true;
24929352 14631 crtc->plane = !plane;
ce22dba9 14632 intel_crtc_disable_planes(&crtc->base);
24929352
DV		 14633 dev_priv->display.crtc_disable(&crtc->base);
14634 crtc->plane = plane;
14635
14636 /* ... and break all links. */
3a3371ff 14637 for_each_intel_connector(dev, connector) {
24929352
DV		 14638 if (connector->encoder->base.crtc != &crtc->base)
14639 continue;
14640
7f1950fb
EE		 14641 connector->base.dpms = DRM_MODE_DPMS_OFF;
14642 connector->base.encoder = NULL;
24929352 14643 }
7f1950fb
EE		 14644 /* multiple connectors may have the same encoder:
14645 * handle them and break crtc link separately */
3a3371ff 14646 for_each_intel_connector(dev, connector)
7f1950fb
EE		 14647 if (connector->encoder->base.crtc == &crtc->base) {
14648 connector->encoder->base.crtc = NULL;
14649 connector->encoder->connectors_active = false;
14650 }
24929352
DV		 14651
14652 WARN_ON(crtc->active);
83d65738 14653 crtc->base.state->enable = false;
49d6fa21 14654 crtc->base.state->active = false;
24929352
DV		 14655 crtc->base.enabled = false;
14656 }
24929352 14657
7fad798e
DV		 14658 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
14659 crtc->pipe == PIPE_A && !crtc->active) {
14660 /* BIOS forgot to enable pipe A, this mostly happens after
14661 * resume. Force-enable the pipe to fix this, the update_dpms
14662 * call below we restore the pipe to the right state, but leave
14663 * the required bits on. */
14664 intel_enable_pipe_a(dev);
14665 }
14666
24929352
DV		 14667 /* Adjust the state of the output pipe according to whether we
14668 * have active connectors/encoders. */
14669 intel_crtc_update_dpms(&crtc->base);
14670
83d65738 14671 if (crtc->active != crtc->base.state->enable) {
24929352
DV		 14672 struct intel_encoder *encoder;
14673
14674 /* This can happen either due to bugs in the get_hw_state
14675 * functions or because the pipe is force-enabled due to the
14676 * pipe A quirk. */
14677 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
14678 crtc->base.base.id,
83d65738 14679 crtc->base.state->enable ? "enabled" : "disabled",
24929352
DV		 14680 crtc->active ? "enabled" : "disabled");
14681
83d65738 14682 crtc->base.state->enable = crtc->active;
49d6fa21 14683 crtc->base.state->active = crtc->active;
24929352
DV		 14684 crtc->base.enabled = crtc->active;
14685
14686 /* Because we only establish the connector -> encoder ->
14687 * crtc links if something is active, this means the
14688 * crtc is now deactivated. Break the links. connector
14689 * -> encoder links are only establish when things are
14690 * actually up, hence no need to break them. */
14691 WARN_ON(crtc->active);
14692
14693 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
14694 WARN_ON(encoder->connectors_active);
14695 encoder->base.crtc = NULL;
14696 }
14697 }
c5ab3bc0 14698
a3ed6aad 14699 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
4cc31489
DV		 14700 /*
14701 * We start out with underrun reporting disabled to avoid races.
14702 * For correct bookkeeping mark this on active crtcs.
14703 *
c5ab3bc0
DV		 14704 * Also on gmch platforms we dont have any hardware bits to
14705 * disable the underrun reporting. Which means we need to start
14706 * out with underrun reporting disabled also on inactive pipes,
14707 * since otherwise we'll complain about the garbage we read when
14708 * e.g. coming up after runtime pm.
14709 *
4cc31489
DV		 14710 * No protection against concurrent access is required - at
14711 * worst a fifo underrun happens which also sets this to false.
14712 */
14713 crtc->cpu_fifo_underrun_disabled = true;
14714 crtc->pch_fifo_underrun_disabled = true;
14715 }
24929352
DV		 14716}
14717
14718static void intel_sanitize_encoder(struct intel_encoder *encoder)
14719{
14720 struct intel_connector *connector;
14721 struct drm_device *dev = encoder->base.dev;
14722
14723 /* We need to check both for a crtc link (meaning that the
14724 * encoder is active and trying to read from a pipe) and the
14725 * pipe itself being active. */
14726 bool has_active_crtc = encoder->base.crtc &&
14727 to_intel_crtc(encoder->base.crtc)->active;
14728
14729 if (encoder->connectors_active && !has_active_crtc) {
14730 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14731 encoder->base.base.id,
8e329a03 14732 encoder->base.name);
24929352
DV		 14733
14734 /* Connector is active, but has no active pipe. This is
14735 * fallout from our resume register restoring. Disable
14736 * the encoder manually again. */
14737 if (encoder->base.crtc) {
14738 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14739 encoder->base.base.id,
8e329a03 14740 encoder->base.name);
24929352 14741 encoder->disable(encoder);
a62d1497
VS		 14742 if (encoder->post_disable)
14743 encoder->post_disable(encoder);
24929352 14744 }
7f1950fb
EE		 14745 encoder->base.crtc = NULL;
14746 encoder->connectors_active = false;
24929352
DV		 14747
14748 /* Inconsistent output/port/pipe state happens presumably due to
14749 * a bug in one of the get_hw_state functions. Or someplace else
14750 * in our code, like the register restore mess on resume. Clamp
14751 * things to off as a safer default. */
3a3371ff 14752 for_each_intel_connector(dev, connector) {
24929352
DV		 14753 if (connector->encoder != encoder)
14754 continue;
7f1950fb
EE		 14755 connector->base.dpms = DRM_MODE_DPMS_OFF;
14756 connector->base.encoder = NULL;
24929352
DV		 14757 }
14758 }
14759 /* Enabled encoders without active connectors will be fixed in
14760 * the crtc fixup. */
14761}
14762
04098753 14763void i915_redisable_vga_power_on(struct drm_device *dev)
0fde901f
KM		 14764{
14765 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 14766 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 14767
04098753
ID		 14768 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
14769 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
14770 i915_disable_vga(dev);
14771 }
14772}
14773
14774void i915_redisable_vga(struct drm_device *dev)
14775{
14776 struct drm_i915_private *dev_priv = dev->dev_private;
14777
8dc8a27c
PZ		 14778 /* This function can be called both from intel_modeset_setup_hw_state or
14779 * at a very early point in our resume sequence, where the power well
14780 * structures are not yet restored. Since this function is at a very
14781 * paranoid "someone might have enabled VGA while we were not looking"
14782 * level, just check if the power well is enabled instead of trying to
14783 * follow the "don't touch the power well if we don't need it" policy
14784 * the rest of the driver uses. */
f458ebbc 14785 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
8dc8a27c
PZ		 14786 return;
14787
04098753 14788 i915_redisable_vga_power_on(dev);
0fde901f
KM		 14789}
14790
98ec7739
VS		 14791static bool primary_get_hw_state(struct intel_crtc *crtc)
14792{
14793 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
14794
14795 if (!crtc->active)
14796 return false;
14797
14798 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
14799}
14800
30e984df 14801static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 14802{
14803 struct drm_i915_private *dev_priv = dev->dev_private;
14804 enum pipe pipe;
24929352
DV		 14805 struct intel_crtc *crtc;
14806 struct intel_encoder *encoder;
14807 struct intel_connector *connector;
5358901f 14808 int i;
24929352 14809
d3fcc808 14810 for_each_intel_crtc(dev, crtc) {
b70709a6
ML		 14811 struct drm_plane *primary = crtc->base.primary;
14812 struct intel_plane_state *plane_state;
14813
6e3c9717 14814 memset(crtc->config, 0, sizeof(*crtc->config));
3b117c8f 14815
6e3c9717 14816 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
9953599b 14817
0e8ffe1b 14818 crtc->active = dev_priv->display.get_pipe_config(crtc,
6e3c9717 14819 crtc->config);
24929352 14820
83d65738 14821 crtc->base.state->enable = crtc->active;
49d6fa21 14822 crtc->base.state->active = crtc->active;
24929352 14823 crtc->base.enabled = crtc->active;
b70709a6
ML		 14824
14825 plane_state = to_intel_plane_state(primary->state);
14826 plane_state->visible = primary_get_hw_state(crtc);
24929352
DV		 14827
14828 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
14829 crtc->base.base.id,
14830 crtc->active ? "enabled" : "disabled");
14831 }
14832
5358901f
DV		 14833 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
14834 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
14835
3e369b76
ACO		 14836 pll->on = pll->get_hw_state(dev_priv, pll,
14837 &pll->config.hw_state);
5358901f 14838 pll->active = 0;
3e369b76 14839 pll->config.crtc_mask = 0;
d3fcc808 14840 for_each_intel_crtc(dev, crtc) {
1e6f2ddc 14841 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
5358901f 14842 pll->active++;
3e369b76 14843 pll->config.crtc_mask |= 1 << crtc->pipe;
1e6f2ddc 14844 }
5358901f 14845 }
5358901f 14846
1e6f2ddc 14847 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
3e369b76 14848 pll->name, pll->config.crtc_mask, pll->on);
bd2bb1b9 14849
3e369b76 14850 if (pll->config.crtc_mask)
bd2bb1b9 14851 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5358901f
DV		 14852 }
14853
b2784e15 14854 for_each_intel_encoder(dev, encoder) {
24929352
DV		 14855 pipe = 0;
14856
14857 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 14858 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
14859 encoder->base.crtc = &crtc->base;
6e3c9717 14860 encoder->get_config(encoder, crtc->config);
24929352
DV		 14861 } else {
14862 encoder->base.crtc = NULL;
14863 }
14864
14865 encoder->connectors_active = false;
6f2bcceb 14866 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
24929352 14867 encoder->base.base.id,
8e329a03 14868 encoder->base.name,
24929352 14869 encoder->base.crtc ? "enabled" : "disabled",
6f2bcceb 14870 pipe_name(pipe));
24929352
DV		 14871 }
14872
3a3371ff 14873 for_each_intel_connector(dev, connector) {
24929352
DV		 14874 if (connector->get_hw_state(connector)) {
14875 connector->base.dpms = DRM_MODE_DPMS_ON;
14876 connector->encoder->connectors_active = true;
14877 connector->base.encoder = &connector->encoder->base;
14878 } else {
14879 connector->base.dpms = DRM_MODE_DPMS_OFF;
14880 connector->base.encoder = NULL;
14881 }
14882 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
14883 connector->base.base.id,
c23cc417 14884 connector->base.name,
24929352
DV		 14885 connector->base.encoder ? "enabled" : "disabled");
14886 }
30e984df
DV		 14887}
14888
14889/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
14890 * and i915 state tracking structures. */
14891void intel_modeset_setup_hw_state(struct drm_device *dev,
14892 bool force_restore)
14893{
14894 struct drm_i915_private *dev_priv = dev->dev_private;
14895 enum pipe pipe;
30e984df
DV		 14896 struct intel_crtc *crtc;
14897 struct intel_encoder *encoder;
35c95375 14898 int i;
30e984df
DV		 14899
14900 intel_modeset_readout_hw_state(dev);
24929352 14901
babea61d
JB		 14902 /*
14903 * Now that we have the config, copy it to each CRTC struct
14904 * Note that this could go away if we move to using crtc_config
14905 * checking everywhere.
14906 */
d3fcc808 14907 for_each_intel_crtc(dev, crtc) {
d330a953 14908 if (crtc->active && i915.fastboot) {
6e3c9717
ACO		 14909 intel_mode_from_pipe_config(&crtc->base.mode,
14910 crtc->config);
babea61d
JB		 14911 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
14912 crtc->base.base.id);
14913 drm_mode_debug_printmodeline(&crtc->base.mode);
14914 }
14915 }
14916
24929352 14917 /* HW state is read out, now we need to sanitize this mess. */
b2784e15 14918 for_each_intel_encoder(dev, encoder) {
24929352
DV		 14919 intel_sanitize_encoder(encoder);
14920 }
14921
055e393f 14922 for_each_pipe(dev_priv, pipe) {
24929352
DV		 14923 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
14924 intel_sanitize_crtc(crtc);
6e3c9717
ACO		 14925 intel_dump_pipe_config(crtc, crtc->config,
14926 "[setup_hw_state]");
24929352 14927 }
9a935856 14928
d29b2f9d
ACO		 14929 intel_modeset_update_connector_atomic_state(dev);
14930
35c95375
DV		 14931 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
14932 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
14933
14934 if (!pll->on || pll->active)
14935 continue;
14936
14937 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
14938
14939 pll->disable(dev_priv, pll);
14940 pll->on = false;
14941 }
14942
3078999f
PB		 14943 if (IS_GEN9(dev))
14944 skl_wm_get_hw_state(dev);
14945 else if (HAS_PCH_SPLIT(dev))
243e6a44
VS		 14946 ilk_wm_get_hw_state(dev);
14947
45e2b5f6 14948 if (force_restore) {
7d0bc1ea
VS		 14949 i915_redisable_vga(dev);
14950
f30da187
DV		 14951 /*
14952 * We need to use raw interfaces for restoring state to avoid
14953 * checking (bogus) intermediate states.
14954 */
055e393f 14955 for_each_pipe(dev_priv, pipe) {
b5644d05
JB		 14956 struct drm_crtc *crtc =
14957 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187 14958
83a57153 14959 intel_crtc_restore_mode(crtc);
45e2b5f6
DV		 14960 }
14961 } else {
14962 intel_modeset_update_staged_output_state(dev);
14963 }
8af6cf88
DV		 14964
14965 intel_modeset_check_state(dev);
2c7111db
CW		 14966}
14967
14968void intel_modeset_gem_init(struct drm_device *dev)
14969{
92122789 14970 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd 14971 struct drm_crtc *c;
2ff8fde1 14972 struct drm_i915_gem_object *obj;
e0d6149b 14973 int ret;
484b41dd 14974
ae48434c
ID		 14975 mutex_lock(&dev->struct_mutex);
14976 intel_init_gt_powersave(dev);
14977 mutex_unlock(&dev->struct_mutex);
14978
92122789
JB		 14979 /*
14980 * There may be no VBT; and if the BIOS enabled SSC we can
14981 * just keep using it to avoid unnecessary flicker. Whereas if the
14982 * BIOS isn't using it, don't assume it will work even if the VBT
14983 * indicates as much.
14984 */
14985 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
14986 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14987 DREF_SSC1_ENABLE);
14988
1833b134 14989 intel_modeset_init_hw(dev);
02e792fb
DV		 14990
14991 intel_setup_overlay(dev);
484b41dd
JB		 14992
14993 /*
14994 * Make sure any fbs we allocated at startup are properly
14995 * pinned & fenced. When we do the allocation it's too early
14996 * for this.
14997 */
70e1e0ec 14998 for_each_crtc(dev, c) {
2ff8fde1
MR		 14999 obj = intel_fb_obj(c->primary->fb);
15000 if (obj == NULL)
484b41dd
JB		 15001 continue;
15002
e0d6149b
TU		 15003 mutex_lock(&dev->struct_mutex);
15004 ret = intel_pin_and_fence_fb_obj(c->primary,
15005 c->primary->fb,
15006 c->primary->state,
15007 NULL);
15008 mutex_unlock(&dev->struct_mutex);
15009 if (ret) {
484b41dd
JB		 15010 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15011 to_intel_crtc(c)->pipe);
66e514c1
DA		 15012 drm_framebuffer_unreference(c->primary->fb);
15013 c->primary->fb = NULL;
afd65eb4 15014 update_state_fb(c->primary);
484b41dd
JB		 15015 }
15016 }
0962c3c9
VS		 15017
15018 intel_backlight_register(dev);
79e53945
JB		 15019}
15020
4932e2c3
ID		 15021void intel_connector_unregister(struct intel_connector *intel_connector)
15022{
15023 struct drm_connector *connector = &intel_connector->base;
15024
15025 intel_panel_destroy_backlight(connector);
34ea3d38 15026 drm_connector_unregister(connector);
4932e2c3
ID		 15027}
15028
79e53945
JB		 15029void intel_modeset_cleanup(struct drm_device *dev)
15030{
652c393a 15031 struct drm_i915_private *dev_priv = dev->dev_private;
d9255d57 15032 struct drm_connector *connector;
652c393a 15033
2eb5252e
ID		 15034 intel_disable_gt_powersave(dev);
15035
0962c3c9
VS		 15036 intel_backlight_unregister(dev);
15037
fd0c0642
DV		 15038 /*
15039 * Interrupts and polling as the first thing to avoid creating havoc.
2eb5252e 15040 * Too much stuff here (turning of connectors, ...) would
fd0c0642
DV		 15041 * experience fancy races otherwise.
15042 */
2aeb7d3a 15043 intel_irq_uninstall(dev_priv);
eb21b92b 15044
fd0c0642
DV		 15045 /*
15046 * Due to the hpd irq storm handling the hotplug work can re-arm the
15047 * poll handlers. Hence disable polling after hpd handling is shut down.
15048 */
f87ea761 15049 drm_kms_helper_poll_fini(dev);
fd0c0642 15050
652c393a
JB		 15051 mutex_lock(&dev->struct_mutex);
15052
723bfd70
JB		 15053 intel_unregister_dsm_handler();
15054
7ff0ebcc 15055 intel_fbc_disable(dev);
e70236a8 15056
69341a5e
KH		 15057 mutex_unlock(&dev->struct_mutex);
15058
1630fe75
CW		 15059 /* flush any delayed tasks or pending work */
15060 flush_scheduled_work();
15061
db31af1d
JN		 15062 /* destroy the backlight and sysfs files before encoders/connectors */
15063 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4932e2c3
ID		 15064 struct intel_connector *intel_connector;
15065
15066 intel_connector = to_intel_connector(connector);
15067 intel_connector->unregister(intel_connector);
db31af1d 15068 }
d9255d57 15069
79e53945 15070 drm_mode_config_cleanup(dev);
4d7bb011
DV		 15071
15072 intel_cleanup_overlay(dev);
ae48434c
ID		 15073
15074 mutex_lock(&dev->struct_mutex);
15075 intel_cleanup_gt_powersave(dev);
15076 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 15077}
15078
f1c79df3
ZW		 15079/*
15080 * Return which encoder is currently attached for connector.
15081 */
df0e9248 15082struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 15083{
df0e9248
CW		 15084 return &intel_attached_encoder(connector)->base;
15085}
f1c79df3 15086
df0e9248
CW		 15087void intel_connector_attach_encoder(struct intel_connector *connector,
15088 struct intel_encoder *encoder)
15089{
15090 connector->encoder = encoder;
15091 drm_mode_connector_attach_encoder(&connector->base,
15092 &encoder->base);
79e53945 15093}
28d52043
DA		 15094
15095/*
15096 * set vga decode state - true == enable VGA decode
15097 */
15098int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15099{
15100 struct drm_i915_private *dev_priv = dev->dev_private;
a885b3cc 15101 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
28d52043
DA		 15102 u16 gmch_ctrl;
15103
75fa041d
CW		 15104 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15105 DRM_ERROR("failed to read control word\n");
15106 return -EIO;
15107 }
15108
c0cc8a55
CW		 15109 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15110 return 0;
15111
28d52043
DA		 15112 if (state)
15113 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15114 else
15115 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
75fa041d
CW		 15116
15117 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15118 DRM_ERROR("failed to write control word\n");
15119 return -EIO;
15120 }
15121
28d52043
DA		 15122 return 0;
15123}
c4a1d9e4 15124
c4a1d9e4 15125struct intel_display_error_state {
ff57f1b0
PZ		 15126
15127 u32 power_well_driver;
15128
63b66e5b
CW		 15129 int num_transcoders;
15130
c4a1d9e4
CW		 15131 struct intel_cursor_error_state {
15132 u32 control;
15133 u32 position;
15134 u32 base;
15135 u32 size;
52331309 15136 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 15137
15138 struct intel_pipe_error_state {
ddf9c536 15139 bool power_domain_on;
c4a1d9e4 15140 u32 source;
f301b1e1 15141 u32 stat;
52331309 15142 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 15143
15144 struct intel_plane_error_state {
15145 u32 control;
15146 u32 stride;
15147 u32 size;
15148 u32 pos;
15149 u32 addr;
15150 u32 surface;
15151 u32 tile_offset;
52331309 15152 } plane[I915_MAX_PIPES];
63b66e5b
CW		 15153
15154 struct intel_transcoder_error_state {
ddf9c536 15155 bool power_domain_on;
63b66e5b
CW		 15156 enum transcoder cpu_transcoder;
15157
15158 u32 conf;
15159
15160 u32 htotal;
15161 u32 hblank;
15162 u32 hsync;
15163 u32 vtotal;
15164 u32 vblank;
15165 u32 vsync;
15166 } transcoder[4];
c4a1d9e4
CW		 15167};
15168
15169struct intel_display_error_state *
15170intel_display_capture_error_state(struct drm_device *dev)
15171{
fbee40df 15172 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4 15173 struct intel_display_error_state *error;
63b66e5b
CW		 15174 int transcoders[] = {
15175 TRANSCODER_A,
15176 TRANSCODER_B,
15177 TRANSCODER_C,
15178 TRANSCODER_EDP,
15179 };
c4a1d9e4
CW		 15180 int i;
15181
63b66e5b
CW		 15182 if (INTEL_INFO(dev)->num_pipes == 0)
15183 return NULL;
15184
9d1cb914 15185 error = kzalloc(sizeof(*error), GFP_ATOMIC);
c4a1d9e4
CW		 15186 if (error == NULL)
15187 return NULL;
15188
190be112 15189 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ff57f1b0
PZ		 15190 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15191
055e393f 15192 for_each_pipe(dev_priv, i) {
ddf9c536 15193 error->pipe[i].power_domain_on =
f458ebbc
DV		 15194 __intel_display_power_is_enabled(dev_priv,
15195 POWER_DOMAIN_PIPE(i));
ddf9c536 15196 if (!error->pipe[i].power_domain_on)
9d1cb914
PZ		 15197 continue;
15198
5efb3e28
VS		 15199 error->cursor[i].control = I915_READ(CURCNTR(i));
15200 error->cursor[i].position = I915_READ(CURPOS(i));
15201 error->cursor[i].base = I915_READ(CURBASE(i));
c4a1d9e4
CW		 15202
15203 error->plane[i].control = I915_READ(DSPCNTR(i));
15204 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 15205 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 15206 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 15207 error->plane[i].pos = I915_READ(DSPPOS(i));
15208 }
ca291363
PZ		 15209 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15210 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 15211 if (INTEL_INFO(dev)->gen >= 4) {
15212 error->plane[i].surface = I915_READ(DSPSURF(i));
15213 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15214 }
15215
c4a1d9e4 15216 error->pipe[i].source = I915_READ(PIPESRC(i));
f301b1e1 15217
3abfce77 15218 if (HAS_GMCH_DISPLAY(dev))
f301b1e1 15219 error->pipe[i].stat = I915_READ(PIPESTAT(i));
63b66e5b
CW		 15220 }
15221
15222 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15223 if (HAS_DDI(dev_priv->dev))
15224 error->num_transcoders++; /* Account for eDP. */
15225
15226 for (i = 0; i < error->num_transcoders; i++) {
15227 enum transcoder cpu_transcoder = transcoders[i];
15228
ddf9c536 15229 error->transcoder[i].power_domain_on =
f458ebbc 15230 __intel_display_power_is_enabled(dev_priv,
38cc1daf 15231 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
ddf9c536 15232 if (!error->transcoder[i].power_domain_on)
9d1cb914
PZ		 15233 continue;
15234
63b66e5b
CW		 15235 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15236
15237 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15238 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15239 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15240 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15241 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15242 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15243 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 15244 }
15245
15246 return error;
15247}
15248
edc3d884
MK		 15249#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15250
c4a1d9e4 15251void
edc3d884 15252intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 15253 struct drm_device *dev,
15254 struct intel_display_error_state *error)
15255{
055e393f 15256 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4
CW		 15257 int i;
15258
63b66e5b
CW		 15259 if (!error)
15260 return;
15261
edc3d884 15262 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
190be112 15263 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
edc3d884 15264 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 15265 error->power_well_driver);
055e393f 15266 for_each_pipe(dev_priv, i) {
edc3d884 15267 err_printf(m, "Pipe [%d]:\n", i);
ddf9c536
ID		 15268 err_printf(m, " Power: %s\n",
15269 error->pipe[i].power_domain_on ? "on" : "off");
edc3d884 15270 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
f301b1e1 15271 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
edc3d884
MK		 15272
15273 err_printf(m, "Plane [%d]:\n", i);
15274 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15275 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 15276 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 15277 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15278 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 15279 }
4b71a570 15280 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 15281 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 15282 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 15283 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15284 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 15285 }
15286
edc3d884
MK		 15287 err_printf(m, "Cursor [%d]:\n", i);
15288 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15289 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15290 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 15291 }
63b66e5b
CW		 15292
15293 for (i = 0; i < error->num_transcoders; i++) {
1cf84bb6 15294 err_printf(m, "CPU transcoder: %c\n",
63b66e5b 15295 transcoder_name(error->transcoder[i].cpu_transcoder));
ddf9c536
ID		 15296 err_printf(m, " Power: %s\n",
15297 error->transcoder[i].power_domain_on ? "on" : "off");
63b66e5b
CW		 15298 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15299 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15300 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15301 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15302 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15303 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15304 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15305 }
c4a1d9e4 15306}
e2fcdaa9
VS		 15307
15308void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15309{
15310 struct intel_crtc *crtc;
15311
15312 for_each_intel_crtc(dev, crtc) {
15313 struct intel_unpin_work *work;
e2fcdaa9 15314
5e2d7afc 15315 spin_lock_irq(&dev->event_lock);
e2fcdaa9
VS		 15316
15317 work = crtc->unpin_work;
15318
15319 if (work && work->event &&
15320 work->event->base.file_priv == file) {
15321 kfree(work->event);
15322 work->event = NULL;
15323 }
15324
5e2d7afc 15325 spin_unlock_irq(&dev->event_lock);
e2fcdaa9
VS		 15326 }
15327}
Linux 6.x block layer and io_uring tree(s)