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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
27 | #include <linux/i2c.h> | |
28 | #include "drmP.h" | |
29 | #include "intel_drv.h" | |
30 | #include "i915_drm.h" | |
31 | #include "i915_drv.h" | |
32 | ||
33 | #include "drm_crtc_helper.h" | |
34 | ||
35 | bool intel_pipe_has_type (struct drm_crtc *crtc, int type); | |
36 | ||
37 | typedef struct { | |
38 | /* given values */ | |
39 | int n; | |
40 | int m1, m2; | |
41 | int p1, p2; | |
42 | /* derived values */ | |
43 | int dot; | |
44 | int vco; | |
45 | int m; | |
46 | int p; | |
47 | } intel_clock_t; | |
48 | ||
49 | typedef struct { | |
50 | int min, max; | |
51 | } intel_range_t; | |
52 | ||
53 | typedef struct { | |
54 | int dot_limit; | |
55 | int p2_slow, p2_fast; | |
56 | } intel_p2_t; | |
57 | ||
58 | #define INTEL_P2_NUM 2 | |
d4906093 ML |
59 | typedef struct intel_limit intel_limit_t; |
60 | struct intel_limit { | |
79e53945 JB |
61 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
62 | intel_p2_t p2; | |
d4906093 ML |
63 | bool (* find_pll)(const intel_limit_t *, struct drm_crtc *, |
64 | int, int, intel_clock_t *); | |
65 | }; | |
79e53945 JB |
66 | |
67 | #define I8XX_DOT_MIN 25000 | |
68 | #define I8XX_DOT_MAX 350000 | |
69 | #define I8XX_VCO_MIN 930000 | |
70 | #define I8XX_VCO_MAX 1400000 | |
71 | #define I8XX_N_MIN 3 | |
72 | #define I8XX_N_MAX 16 | |
73 | #define I8XX_M_MIN 96 | |
74 | #define I8XX_M_MAX 140 | |
75 | #define I8XX_M1_MIN 18 | |
76 | #define I8XX_M1_MAX 26 | |
77 | #define I8XX_M2_MIN 6 | |
78 | #define I8XX_M2_MAX 16 | |
79 | #define I8XX_P_MIN 4 | |
80 | #define I8XX_P_MAX 128 | |
81 | #define I8XX_P1_MIN 2 | |
82 | #define I8XX_P1_MAX 33 | |
83 | #define I8XX_P1_LVDS_MIN 1 | |
84 | #define I8XX_P1_LVDS_MAX 6 | |
85 | #define I8XX_P2_SLOW 4 | |
86 | #define I8XX_P2_FAST 2 | |
87 | #define I8XX_P2_LVDS_SLOW 14 | |
88 | #define I8XX_P2_LVDS_FAST 14 /* No fast option */ | |
89 | #define I8XX_P2_SLOW_LIMIT 165000 | |
90 | ||
91 | #define I9XX_DOT_MIN 20000 | |
92 | #define I9XX_DOT_MAX 400000 | |
93 | #define I9XX_VCO_MIN 1400000 | |
94 | #define I9XX_VCO_MAX 2800000 | |
2177832f SL |
95 | #define IGD_VCO_MIN 1700000 |
96 | #define IGD_VCO_MAX 3500000 | |
f3cade5c KH |
97 | #define I9XX_N_MIN 1 |
98 | #define I9XX_N_MAX 6 | |
2177832f SL |
99 | /* IGD's Ncounter is a ring counter */ |
100 | #define IGD_N_MIN 3 | |
101 | #define IGD_N_MAX 6 | |
79e53945 JB |
102 | #define I9XX_M_MIN 70 |
103 | #define I9XX_M_MAX 120 | |
2177832f SL |
104 | #define IGD_M_MIN 2 |
105 | #define IGD_M_MAX 256 | |
79e53945 | 106 | #define I9XX_M1_MIN 10 |
f3cade5c | 107 | #define I9XX_M1_MAX 22 |
79e53945 JB |
108 | #define I9XX_M2_MIN 5 |
109 | #define I9XX_M2_MAX 9 | |
2177832f SL |
110 | /* IGD M1 is reserved, and must be 0 */ |
111 | #define IGD_M1_MIN 0 | |
112 | #define IGD_M1_MAX 0 | |
113 | #define IGD_M2_MIN 0 | |
114 | #define IGD_M2_MAX 254 | |
79e53945 JB |
115 | #define I9XX_P_SDVO_DAC_MIN 5 |
116 | #define I9XX_P_SDVO_DAC_MAX 80 | |
117 | #define I9XX_P_LVDS_MIN 7 | |
118 | #define I9XX_P_LVDS_MAX 98 | |
2177832f SL |
119 | #define IGD_P_LVDS_MIN 7 |
120 | #define IGD_P_LVDS_MAX 112 | |
79e53945 JB |
121 | #define I9XX_P1_MIN 1 |
122 | #define I9XX_P1_MAX 8 | |
123 | #define I9XX_P2_SDVO_DAC_SLOW 10 | |
124 | #define I9XX_P2_SDVO_DAC_FAST 5 | |
125 | #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000 | |
126 | #define I9XX_P2_LVDS_SLOW 14 | |
127 | #define I9XX_P2_LVDS_FAST 7 | |
128 | #define I9XX_P2_LVDS_SLOW_LIMIT 112000 | |
129 | ||
130 | #define INTEL_LIMIT_I8XX_DVO_DAC 0 | |
131 | #define INTEL_LIMIT_I8XX_LVDS 1 | |
132 | #define INTEL_LIMIT_I9XX_SDVO_DAC 2 | |
133 | #define INTEL_LIMIT_I9XX_LVDS 3 | |
044c7c41 ML |
134 | #define INTEL_LIMIT_G4X_SDVO 4 |
135 | #define INTEL_LIMIT_G4X_HDMI_DAC 5 | |
136 | #define INTEL_LIMIT_G4X_SINGLE_CHANNEL_LVDS 6 | |
137 | #define INTEL_LIMIT_G4X_DUAL_CHANNEL_LVDS 7 | |
2177832f SL |
138 | #define INTEL_LIMIT_IGD_SDVO_DAC 8 |
139 | #define INTEL_LIMIT_IGD_LVDS 9 | |
044c7c41 ML |
140 | |
141 | /*The parameter is for SDVO on G4x platform*/ | |
142 | #define G4X_DOT_SDVO_MIN 25000 | |
143 | #define G4X_DOT_SDVO_MAX 270000 | |
144 | #define G4X_VCO_MIN 1750000 | |
145 | #define G4X_VCO_MAX 3500000 | |
146 | #define G4X_N_SDVO_MIN 1 | |
147 | #define G4X_N_SDVO_MAX 4 | |
148 | #define G4X_M_SDVO_MIN 104 | |
149 | #define G4X_M_SDVO_MAX 138 | |
150 | #define G4X_M1_SDVO_MIN 17 | |
151 | #define G4X_M1_SDVO_MAX 23 | |
152 | #define G4X_M2_SDVO_MIN 5 | |
153 | #define G4X_M2_SDVO_MAX 11 | |
154 | #define G4X_P_SDVO_MIN 10 | |
155 | #define G4X_P_SDVO_MAX 30 | |
156 | #define G4X_P1_SDVO_MIN 1 | |
157 | #define G4X_P1_SDVO_MAX 3 | |
158 | #define G4X_P2_SDVO_SLOW 10 | |
159 | #define G4X_P2_SDVO_FAST 10 | |
160 | #define G4X_P2_SDVO_LIMIT 270000 | |
161 | ||
162 | /*The parameter is for HDMI_DAC on G4x platform*/ | |
163 | #define G4X_DOT_HDMI_DAC_MIN 22000 | |
164 | #define G4X_DOT_HDMI_DAC_MAX 400000 | |
165 | #define G4X_N_HDMI_DAC_MIN 1 | |
166 | #define G4X_N_HDMI_DAC_MAX 4 | |
167 | #define G4X_M_HDMI_DAC_MIN 104 | |
168 | #define G4X_M_HDMI_DAC_MAX 138 | |
169 | #define G4X_M1_HDMI_DAC_MIN 16 | |
170 | #define G4X_M1_HDMI_DAC_MAX 23 | |
171 | #define G4X_M2_HDMI_DAC_MIN 5 | |
172 | #define G4X_M2_HDMI_DAC_MAX 11 | |
173 | #define G4X_P_HDMI_DAC_MIN 5 | |
174 | #define G4X_P_HDMI_DAC_MAX 80 | |
175 | #define G4X_P1_HDMI_DAC_MIN 1 | |
176 | #define G4X_P1_HDMI_DAC_MAX 8 | |
177 | #define G4X_P2_HDMI_DAC_SLOW 10 | |
178 | #define G4X_P2_HDMI_DAC_FAST 5 | |
179 | #define G4X_P2_HDMI_DAC_LIMIT 165000 | |
180 | ||
181 | /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/ | |
182 | #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000 | |
183 | #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000 | |
184 | #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1 | |
185 | #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3 | |
186 | #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104 | |
187 | #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138 | |
188 | #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17 | |
189 | #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23 | |
190 | #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5 | |
191 | #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11 | |
192 | #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28 | |
193 | #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112 | |
194 | #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2 | |
195 | #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8 | |
196 | #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14 | |
197 | #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14 | |
198 | #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0 | |
199 | ||
200 | /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/ | |
201 | #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000 | |
202 | #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000 | |
203 | #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1 | |
204 | #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3 | |
205 | #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104 | |
206 | #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138 | |
207 | #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17 | |
208 | #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23 | |
209 | #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5 | |
210 | #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11 | |
211 | #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14 | |
212 | #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42 | |
213 | #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2 | |
214 | #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6 | |
215 | #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7 | |
216 | #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7 | |
217 | #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0 | |
218 | ||
d4906093 ML |
219 | static bool |
220 | intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
221 | int target, int refclk, intel_clock_t *best_clock); | |
222 | static bool | |
223 | intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
224 | int target, int refclk, intel_clock_t *best_clock); | |
79e53945 JB |
225 | |
226 | static const intel_limit_t intel_limits[] = { | |
227 | { /* INTEL_LIMIT_I8XX_DVO_DAC */ | |
228 | .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX }, | |
229 | .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX }, | |
230 | .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX }, | |
231 | .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX }, | |
232 | .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX }, | |
233 | .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX }, | |
234 | .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX }, | |
235 | .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX }, | |
236 | .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT, | |
237 | .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST }, | |
d4906093 | 238 | .find_pll = intel_find_best_PLL, |
79e53945 JB |
239 | }, |
240 | { /* INTEL_LIMIT_I8XX_LVDS */ | |
241 | .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX }, | |
242 | .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX }, | |
243 | .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX }, | |
244 | .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX }, | |
245 | .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX }, | |
246 | .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX }, | |
247 | .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX }, | |
248 | .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX }, | |
249 | .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT, | |
250 | .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST }, | |
d4906093 | 251 | .find_pll = intel_find_best_PLL, |
79e53945 JB |
252 | }, |
253 | { /* INTEL_LIMIT_I9XX_SDVO_DAC */ | |
254 | .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX }, | |
255 | .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX }, | |
256 | .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX }, | |
257 | .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX }, | |
258 | .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX }, | |
259 | .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX }, | |
260 | .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX }, | |
261 | .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX }, | |
262 | .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT, | |
263 | .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST }, | |
d4906093 | 264 | .find_pll = intel_find_best_PLL, |
79e53945 JB |
265 | }, |
266 | { /* INTEL_LIMIT_I9XX_LVDS */ | |
267 | .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX }, | |
268 | .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX }, | |
269 | .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX }, | |
270 | .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX }, | |
271 | .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX }, | |
272 | .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX }, | |
273 | .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX }, | |
274 | .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX }, | |
275 | /* The single-channel range is 25-112Mhz, and dual-channel | |
276 | * is 80-224Mhz. Prefer single channel as much as possible. | |
277 | */ | |
278 | .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT, | |
279 | .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST }, | |
d4906093 | 280 | .find_pll = intel_find_best_PLL, |
79e53945 | 281 | }, |
044c7c41 ML |
282 | /* below parameter and function is for G4X Chipset Family*/ |
283 | { /* INTEL_LIMIT_G4X_SDVO */ | |
284 | .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX }, | |
285 | .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX}, | |
286 | .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX }, | |
287 | .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX }, | |
288 | .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX }, | |
289 | .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX }, | |
290 | .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX }, | |
291 | .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX}, | |
292 | .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT, | |
293 | .p2_slow = G4X_P2_SDVO_SLOW, | |
294 | .p2_fast = G4X_P2_SDVO_FAST | |
295 | }, | |
d4906093 | 296 | .find_pll = intel_g4x_find_best_PLL, |
044c7c41 ML |
297 | }, |
298 | { /* INTEL_LIMIT_G4X_HDMI_DAC */ | |
299 | .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX }, | |
300 | .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX}, | |
301 | .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX }, | |
302 | .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX }, | |
303 | .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX }, | |
304 | .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX }, | |
305 | .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX }, | |
306 | .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX}, | |
307 | .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT, | |
308 | .p2_slow = G4X_P2_HDMI_DAC_SLOW, | |
309 | .p2_fast = G4X_P2_HDMI_DAC_FAST | |
310 | }, | |
d4906093 | 311 | .find_pll = intel_g4x_find_best_PLL, |
044c7c41 ML |
312 | }, |
313 | { /* INTEL_LIMIT_G4X_SINGLE_CHANNEL_LVDS */ | |
314 | .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN, | |
315 | .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX }, | |
316 | .vco = { .min = G4X_VCO_MIN, | |
317 | .max = G4X_VCO_MAX }, | |
318 | .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN, | |
319 | .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX }, | |
320 | .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN, | |
321 | .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX }, | |
322 | .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN, | |
323 | .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX }, | |
324 | .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN, | |
325 | .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX }, | |
326 | .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN, | |
327 | .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX }, | |
328 | .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN, | |
329 | .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX }, | |
330 | .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT, | |
331 | .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW, | |
332 | .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST | |
333 | }, | |
d4906093 | 334 | .find_pll = intel_g4x_find_best_PLL, |
044c7c41 ML |
335 | }, |
336 | { /* INTEL_LIMIT_G4X_DUAL_CHANNEL_LVDS */ | |
337 | .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN, | |
338 | .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX }, | |
339 | .vco = { .min = G4X_VCO_MIN, | |
340 | .max = G4X_VCO_MAX }, | |
341 | .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN, | |
342 | .max = G4X_N_DUAL_CHANNEL_LVDS_MAX }, | |
343 | .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN, | |
344 | .max = G4X_M_DUAL_CHANNEL_LVDS_MAX }, | |
345 | .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN, | |
346 | .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX }, | |
347 | .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN, | |
348 | .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX }, | |
349 | .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN, | |
350 | .max = G4X_P_DUAL_CHANNEL_LVDS_MAX }, | |
351 | .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN, | |
352 | .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX }, | |
353 | .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT, | |
354 | .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW, | |
355 | .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST | |
356 | }, | |
d4906093 | 357 | .find_pll = intel_g4x_find_best_PLL, |
044c7c41 | 358 | }, |
2177832f SL |
359 | { /* INTEL_LIMIT_IGD_SDVO */ |
360 | .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX}, | |
361 | .vco = { .min = IGD_VCO_MIN, .max = IGD_VCO_MAX }, | |
362 | .n = { .min = IGD_N_MIN, .max = IGD_N_MAX }, | |
363 | .m = { .min = IGD_M_MIN, .max = IGD_M_MAX }, | |
364 | .m1 = { .min = IGD_M1_MIN, .max = IGD_M1_MAX }, | |
365 | .m2 = { .min = IGD_M2_MIN, .max = IGD_M2_MAX }, | |
366 | .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX }, | |
367 | .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX }, | |
368 | .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT, | |
369 | .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST }, | |
370 | }, | |
371 | { /* INTEL_LIMIT_IGD_LVDS */ | |
372 | .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX }, | |
373 | .vco = { .min = IGD_VCO_MIN, .max = IGD_VCO_MAX }, | |
374 | .n = { .min = IGD_N_MIN, .max = IGD_N_MAX }, | |
375 | .m = { .min = IGD_M_MIN, .max = IGD_M_MAX }, | |
376 | .m1 = { .min = IGD_M1_MIN, .max = IGD_M1_MAX }, | |
377 | .m2 = { .min = IGD_M2_MIN, .max = IGD_M2_MAX }, | |
378 | .p = { .min = IGD_P_LVDS_MIN, .max = IGD_P_LVDS_MAX }, | |
379 | .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX }, | |
380 | /* IGD only supports single-channel mode. */ | |
381 | .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT, | |
382 | .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW }, | |
383 | }, | |
384 | ||
79e53945 JB |
385 | }; |
386 | ||
044c7c41 ML |
387 | static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) |
388 | { | |
389 | struct drm_device *dev = crtc->dev; | |
390 | struct drm_i915_private *dev_priv = dev->dev_private; | |
391 | const intel_limit_t *limit; | |
392 | ||
393 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
394 | if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) == | |
395 | LVDS_CLKB_POWER_UP) | |
396 | /* LVDS with dual channel */ | |
397 | limit = &intel_limits | |
398 | [INTEL_LIMIT_G4X_DUAL_CHANNEL_LVDS]; | |
399 | else | |
400 | /* LVDS with dual channel */ | |
401 | limit = &intel_limits | |
402 | [INTEL_LIMIT_G4X_SINGLE_CHANNEL_LVDS]; | |
403 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || | |
404 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { | |
405 | limit = &intel_limits[INTEL_LIMIT_G4X_HDMI_DAC]; | |
406 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { | |
407 | limit = &intel_limits[INTEL_LIMIT_G4X_SDVO]; | |
408 | } else /* The option is for other outputs */ | |
409 | limit = &intel_limits[INTEL_LIMIT_I9XX_SDVO_DAC]; | |
410 | ||
411 | return limit; | |
412 | } | |
413 | ||
79e53945 JB |
414 | static const intel_limit_t *intel_limit(struct drm_crtc *crtc) |
415 | { | |
416 | struct drm_device *dev = crtc->dev; | |
417 | const intel_limit_t *limit; | |
418 | ||
044c7c41 ML |
419 | if (IS_G4X(dev)) { |
420 | limit = intel_g4x_limit(crtc); | |
2177832f | 421 | } else if (IS_I9XX(dev) && !IS_IGD(dev)) { |
79e53945 JB |
422 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
423 | limit = &intel_limits[INTEL_LIMIT_I9XX_LVDS]; | |
424 | else | |
425 | limit = &intel_limits[INTEL_LIMIT_I9XX_SDVO_DAC]; | |
2177832f SL |
426 | } else if (IS_IGD(dev)) { |
427 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
428 | limit = &intel_limits[INTEL_LIMIT_IGD_LVDS]; | |
429 | else | |
430 | limit = &intel_limits[INTEL_LIMIT_IGD_SDVO_DAC]; | |
79e53945 JB |
431 | } else { |
432 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
433 | limit = &intel_limits[INTEL_LIMIT_I8XX_LVDS]; | |
434 | else | |
435 | limit = &intel_limits[INTEL_LIMIT_I8XX_DVO_DAC]; | |
436 | } | |
437 | return limit; | |
438 | } | |
439 | ||
2177832f SL |
440 | /* m1 is reserved as 0 in IGD, n is a ring counter */ |
441 | static void igd_clock(int refclk, intel_clock_t *clock) | |
79e53945 | 442 | { |
2177832f SL |
443 | clock->m = clock->m2 + 2; |
444 | clock->p = clock->p1 * clock->p2; | |
445 | clock->vco = refclk * clock->m / clock->n; | |
446 | clock->dot = clock->vco / clock->p; | |
447 | } | |
448 | ||
449 | static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock) | |
450 | { | |
451 | if (IS_IGD(dev)) { | |
452 | igd_clock(refclk, clock); | |
453 | return; | |
454 | } | |
79e53945 JB |
455 | clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); |
456 | clock->p = clock->p1 * clock->p2; | |
457 | clock->vco = refclk * clock->m / (clock->n + 2); | |
458 | clock->dot = clock->vco / clock->p; | |
459 | } | |
460 | ||
79e53945 JB |
461 | /** |
462 | * Returns whether any output on the specified pipe is of the specified type | |
463 | */ | |
464 | bool intel_pipe_has_type (struct drm_crtc *crtc, int type) | |
465 | { | |
466 | struct drm_device *dev = crtc->dev; | |
467 | struct drm_mode_config *mode_config = &dev->mode_config; | |
468 | struct drm_connector *l_entry; | |
469 | ||
470 | list_for_each_entry(l_entry, &mode_config->connector_list, head) { | |
471 | if (l_entry->encoder && | |
472 | l_entry->encoder->crtc == crtc) { | |
473 | struct intel_output *intel_output = to_intel_output(l_entry); | |
474 | if (intel_output->type == type) | |
475 | return true; | |
476 | } | |
477 | } | |
478 | return false; | |
479 | } | |
480 | ||
7c04d1d9 | 481 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
482 | /** |
483 | * Returns whether the given set of divisors are valid for a given refclk with | |
484 | * the given connectors. | |
485 | */ | |
486 | ||
487 | static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock) | |
488 | { | |
489 | const intel_limit_t *limit = intel_limit (crtc); | |
2177832f | 490 | struct drm_device *dev = crtc->dev; |
79e53945 JB |
491 | |
492 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) | |
493 | INTELPllInvalid ("p1 out of range\n"); | |
494 | if (clock->p < limit->p.min || limit->p.max < clock->p) | |
495 | INTELPllInvalid ("p out of range\n"); | |
496 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) | |
497 | INTELPllInvalid ("m2 out of range\n"); | |
498 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) | |
499 | INTELPllInvalid ("m1 out of range\n"); | |
2177832f | 500 | if (clock->m1 <= clock->m2 && !IS_IGD(dev)) |
79e53945 JB |
501 | INTELPllInvalid ("m1 <= m2\n"); |
502 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
503 | INTELPllInvalid ("m out of range\n"); | |
504 | if (clock->n < limit->n.min || limit->n.max < clock->n) | |
505 | INTELPllInvalid ("n out of range\n"); | |
506 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) | |
507 | INTELPllInvalid ("vco out of range\n"); | |
508 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, | |
509 | * connector, etc., rather than just a single range. | |
510 | */ | |
511 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
512 | INTELPllInvalid ("dot out of range\n"); | |
513 | ||
514 | return true; | |
515 | } | |
516 | ||
d4906093 ML |
517 | static bool |
518 | intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
519 | int target, int refclk, intel_clock_t *best_clock) | |
520 | ||
79e53945 JB |
521 | { |
522 | struct drm_device *dev = crtc->dev; | |
523 | struct drm_i915_private *dev_priv = dev->dev_private; | |
524 | intel_clock_t clock; | |
79e53945 JB |
525 | int err = target; |
526 | ||
527 | if (IS_I9XX(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && | |
528 | (I915_READ(LVDS) & LVDS_PORT_EN) != 0) { | |
529 | /* | |
530 | * For LVDS, if the panel is on, just rely on its current | |
531 | * settings for dual-channel. We haven't figured out how to | |
532 | * reliably set up different single/dual channel state, if we | |
533 | * even can. | |
534 | */ | |
535 | if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) == | |
536 | LVDS_CLKB_POWER_UP) | |
537 | clock.p2 = limit->p2.p2_fast; | |
538 | else | |
539 | clock.p2 = limit->p2.p2_slow; | |
540 | } else { | |
541 | if (target < limit->p2.dot_limit) | |
542 | clock.p2 = limit->p2.p2_slow; | |
543 | else | |
544 | clock.p2 = limit->p2.p2_fast; | |
545 | } | |
546 | ||
547 | memset (best_clock, 0, sizeof (*best_clock)); | |
548 | ||
549 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { | |
2177832f SL |
550 | for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; clock.m2++) { |
551 | /* m1 is always 0 in IGD */ | |
552 | if (clock.m2 >= clock.m1 && !IS_IGD(dev)) | |
553 | break; | |
79e53945 JB |
554 | for (clock.n = limit->n.min; clock.n <= limit->n.max; |
555 | clock.n++) { | |
556 | for (clock.p1 = limit->p1.min; | |
557 | clock.p1 <= limit->p1.max; clock.p1++) { | |
558 | int this_err; | |
559 | ||
2177832f | 560 | intel_clock(dev, refclk, &clock); |
79e53945 JB |
561 | |
562 | if (!intel_PLL_is_valid(crtc, &clock)) | |
563 | continue; | |
564 | ||
565 | this_err = abs(clock.dot - target); | |
566 | if (this_err < err) { | |
567 | *best_clock = clock; | |
568 | err = this_err; | |
569 | } | |
570 | } | |
571 | } | |
572 | } | |
573 | } | |
574 | ||
575 | return (err != target); | |
576 | } | |
577 | ||
d4906093 ML |
578 | static bool |
579 | intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
580 | int target, int refclk, intel_clock_t *best_clock) | |
581 | { | |
582 | struct drm_device *dev = crtc->dev; | |
583 | struct drm_i915_private *dev_priv = dev->dev_private; | |
584 | intel_clock_t clock; | |
585 | int max_n; | |
586 | bool found; | |
587 | /* approximately equals target * 0.00488 */ | |
588 | int err_most = (target >> 8) + (target >> 10); | |
589 | found = false; | |
590 | ||
591 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
592 | if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) == | |
593 | LVDS_CLKB_POWER_UP) | |
594 | clock.p2 = limit->p2.p2_fast; | |
595 | else | |
596 | clock.p2 = limit->p2.p2_slow; | |
597 | } else { | |
598 | if (target < limit->p2.dot_limit) | |
599 | clock.p2 = limit->p2.p2_slow; | |
600 | else | |
601 | clock.p2 = limit->p2.p2_fast; | |
602 | } | |
603 | ||
604 | memset(best_clock, 0, sizeof(*best_clock)); | |
605 | max_n = limit->n.max; | |
606 | /* based on hardware requriment prefer smaller n to precision */ | |
607 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { | |
608 | /* based on hardware requirment prefere larger m1,m2, p1 */ | |
609 | for (clock.m1 = limit->m1.max; | |
610 | clock.m1 >= limit->m1.min; clock.m1--) { | |
611 | for (clock.m2 = limit->m2.max; | |
612 | clock.m2 >= limit->m2.min; clock.m2--) { | |
613 | for (clock.p1 = limit->p1.max; | |
614 | clock.p1 >= limit->p1.min; clock.p1--) { | |
615 | int this_err; | |
616 | ||
2177832f | 617 | intel_clock(dev, refclk, &clock); |
d4906093 ML |
618 | if (!intel_PLL_is_valid(crtc, &clock)) |
619 | continue; | |
620 | this_err = abs(clock.dot - target) ; | |
621 | if (this_err < err_most) { | |
622 | *best_clock = clock; | |
623 | err_most = this_err; | |
624 | max_n = clock.n; | |
625 | found = true; | |
626 | } | |
627 | } | |
628 | } | |
629 | } | |
630 | } | |
631 | ||
632 | return found; | |
633 | } | |
634 | ||
79e53945 JB |
635 | void |
636 | intel_wait_for_vblank(struct drm_device *dev) | |
637 | { | |
638 | /* Wait for 20ms, i.e. one cycle at 50hz. */ | |
580982d3 | 639 | mdelay(20); |
79e53945 JB |
640 | } |
641 | ||
5c3b82e2 | 642 | static int |
3c4fdcfb KH |
643 | intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
644 | struct drm_framebuffer *old_fb) | |
79e53945 JB |
645 | { |
646 | struct drm_device *dev = crtc->dev; | |
647 | struct drm_i915_private *dev_priv = dev->dev_private; | |
648 | struct drm_i915_master_private *master_priv; | |
649 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
650 | struct intel_framebuffer *intel_fb; | |
651 | struct drm_i915_gem_object *obj_priv; | |
652 | struct drm_gem_object *obj; | |
653 | int pipe = intel_crtc->pipe; | |
654 | unsigned long Start, Offset; | |
655 | int dspbase = (pipe == 0 ? DSPAADDR : DSPBADDR); | |
656 | int dspsurf = (pipe == 0 ? DSPASURF : DSPBSURF); | |
657 | int dspstride = (pipe == 0) ? DSPASTRIDE : DSPBSTRIDE; | |
658 | int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR; | |
3c4fdcfb | 659 | u32 dspcntr, alignment; |
5c3b82e2 | 660 | int ret; |
79e53945 JB |
661 | |
662 | /* no fb bound */ | |
663 | if (!crtc->fb) { | |
664 | DRM_DEBUG("No FB bound\n"); | |
5c3b82e2 CW |
665 | return 0; |
666 | } | |
667 | ||
668 | switch (pipe) { | |
669 | case 0: | |
670 | case 1: | |
671 | break; | |
672 | default: | |
673 | DRM_ERROR("Can't update pipe %d in SAREA\n", pipe); | |
674 | return -EINVAL; | |
79e53945 JB |
675 | } |
676 | ||
677 | intel_fb = to_intel_framebuffer(crtc->fb); | |
79e53945 JB |
678 | obj = intel_fb->obj; |
679 | obj_priv = obj->driver_private; | |
680 | ||
3c4fdcfb KH |
681 | switch (obj_priv->tiling_mode) { |
682 | case I915_TILING_NONE: | |
683 | alignment = 64 * 1024; | |
684 | break; | |
685 | case I915_TILING_X: | |
2ebed176 CW |
686 | /* pin() will align the object as required by fence */ |
687 | alignment = 0; | |
3c4fdcfb KH |
688 | break; |
689 | case I915_TILING_Y: | |
690 | /* FIXME: Is this true? */ | |
691 | DRM_ERROR("Y tiled not allowed for scan out buffers\n"); | |
5c3b82e2 | 692 | return -EINVAL; |
3c4fdcfb KH |
693 | default: |
694 | BUG(); | |
695 | } | |
696 | ||
5c3b82e2 CW |
697 | mutex_lock(&dev->struct_mutex); |
698 | ret = i915_gem_object_pin(intel_fb->obj, alignment); | |
699 | if (ret != 0) { | |
700 | mutex_unlock(&dev->struct_mutex); | |
701 | return ret; | |
702 | } | |
79e53945 | 703 | |
5c3b82e2 CW |
704 | ret = i915_gem_object_set_to_gtt_domain(intel_fb->obj, 1); |
705 | if (ret != 0) { | |
706 | i915_gem_object_unpin(intel_fb->obj); | |
707 | mutex_unlock(&dev->struct_mutex); | |
708 | return ret; | |
709 | } | |
79e53945 JB |
710 | |
711 | dspcntr = I915_READ(dspcntr_reg); | |
712531bf JB |
712 | /* Mask out pixel format bits in case we change it */ |
713 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
79e53945 JB |
714 | switch (crtc->fb->bits_per_pixel) { |
715 | case 8: | |
716 | dspcntr |= DISPPLANE_8BPP; | |
717 | break; | |
718 | case 16: | |
719 | if (crtc->fb->depth == 15) | |
720 | dspcntr |= DISPPLANE_15_16BPP; | |
721 | else | |
722 | dspcntr |= DISPPLANE_16BPP; | |
723 | break; | |
724 | case 24: | |
725 | case 32: | |
726 | dspcntr |= DISPPLANE_32BPP_NO_ALPHA; | |
727 | break; | |
728 | default: | |
729 | DRM_ERROR("Unknown color depth\n"); | |
5c3b82e2 CW |
730 | i915_gem_object_unpin(intel_fb->obj); |
731 | mutex_unlock(&dev->struct_mutex); | |
732 | return -EINVAL; | |
79e53945 JB |
733 | } |
734 | I915_WRITE(dspcntr_reg, dspcntr); | |
735 | ||
5c3b82e2 CW |
736 | Start = obj_priv->gtt_offset; |
737 | Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8); | |
738 | ||
79e53945 | 739 | DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y); |
5c3b82e2 | 740 | I915_WRITE(dspstride, crtc->fb->pitch); |
79e53945 JB |
741 | if (IS_I965G(dev)) { |
742 | I915_WRITE(dspbase, Offset); | |
743 | I915_READ(dspbase); | |
744 | I915_WRITE(dspsurf, Start); | |
745 | I915_READ(dspsurf); | |
746 | } else { | |
747 | I915_WRITE(dspbase, Start + Offset); | |
748 | I915_READ(dspbase); | |
749 | } | |
750 | ||
3c4fdcfb KH |
751 | intel_wait_for_vblank(dev); |
752 | ||
753 | if (old_fb) { | |
754 | intel_fb = to_intel_framebuffer(old_fb); | |
755 | i915_gem_object_unpin(intel_fb->obj); | |
756 | } | |
5c3b82e2 | 757 | mutex_unlock(&dev->struct_mutex); |
79e53945 JB |
758 | |
759 | if (!dev->primary->master) | |
5c3b82e2 | 760 | return 0; |
79e53945 JB |
761 | |
762 | master_priv = dev->primary->master->driver_priv; | |
763 | if (!master_priv->sarea_priv) | |
5c3b82e2 | 764 | return 0; |
79e53945 | 765 | |
5c3b82e2 | 766 | if (pipe) { |
79e53945 JB |
767 | master_priv->sarea_priv->pipeB_x = x; |
768 | master_priv->sarea_priv->pipeB_y = y; | |
5c3b82e2 CW |
769 | } else { |
770 | master_priv->sarea_priv->pipeA_x = x; | |
771 | master_priv->sarea_priv->pipeA_y = y; | |
79e53945 | 772 | } |
5c3b82e2 CW |
773 | |
774 | return 0; | |
79e53945 JB |
775 | } |
776 | ||
777 | ||
778 | ||
779 | /** | |
780 | * Sets the power management mode of the pipe and plane. | |
781 | * | |
782 | * This code should probably grow support for turning the cursor off and back | |
783 | * on appropriately at the same time as we're turning the pipe off/on. | |
784 | */ | |
785 | static void intel_crtc_dpms(struct drm_crtc *crtc, int mode) | |
786 | { | |
787 | struct drm_device *dev = crtc->dev; | |
788 | struct drm_i915_master_private *master_priv; | |
789 | struct drm_i915_private *dev_priv = dev->dev_private; | |
790 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
791 | int pipe = intel_crtc->pipe; | |
792 | int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; | |
793 | int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR; | |
794 | int dspbase_reg = (pipe == 0) ? DSPAADDR : DSPBADDR; | |
795 | int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF; | |
796 | u32 temp; | |
797 | bool enabled; | |
798 | ||
799 | /* XXX: When our outputs are all unaware of DPMS modes other than off | |
800 | * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. | |
801 | */ | |
802 | switch (mode) { | |
803 | case DRM_MODE_DPMS_ON: | |
804 | case DRM_MODE_DPMS_STANDBY: | |
805 | case DRM_MODE_DPMS_SUSPEND: | |
806 | /* Enable the DPLL */ | |
807 | temp = I915_READ(dpll_reg); | |
808 | if ((temp & DPLL_VCO_ENABLE) == 0) { | |
809 | I915_WRITE(dpll_reg, temp); | |
810 | I915_READ(dpll_reg); | |
811 | /* Wait for the clocks to stabilize. */ | |
812 | udelay(150); | |
813 | I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE); | |
814 | I915_READ(dpll_reg); | |
815 | /* Wait for the clocks to stabilize. */ | |
816 | udelay(150); | |
817 | I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE); | |
818 | I915_READ(dpll_reg); | |
819 | /* Wait for the clocks to stabilize. */ | |
820 | udelay(150); | |
821 | } | |
822 | ||
823 | /* Enable the pipe */ | |
824 | temp = I915_READ(pipeconf_reg); | |
825 | if ((temp & PIPEACONF_ENABLE) == 0) | |
826 | I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE); | |
827 | ||
828 | /* Enable the plane */ | |
829 | temp = I915_READ(dspcntr_reg); | |
830 | if ((temp & DISPLAY_PLANE_ENABLE) == 0) { | |
831 | I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE); | |
832 | /* Flush the plane changes */ | |
833 | I915_WRITE(dspbase_reg, I915_READ(dspbase_reg)); | |
834 | } | |
835 | ||
836 | intel_crtc_load_lut(crtc); | |
837 | ||
838 | /* Give the overlay scaler a chance to enable if it's on this pipe */ | |
839 | //intel_crtc_dpms_video(crtc, true); TODO | |
840 | break; | |
841 | case DRM_MODE_DPMS_OFF: | |
842 | /* Give the overlay scaler a chance to disable if it's on this pipe */ | |
843 | //intel_crtc_dpms_video(crtc, FALSE); TODO | |
844 | ||
845 | /* Disable the VGA plane that we never use */ | |
846 | I915_WRITE(VGACNTRL, VGA_DISP_DISABLE); | |
847 | ||
848 | /* Disable display plane */ | |
849 | temp = I915_READ(dspcntr_reg); | |
850 | if ((temp & DISPLAY_PLANE_ENABLE) != 0) { | |
851 | I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE); | |
852 | /* Flush the plane changes */ | |
853 | I915_WRITE(dspbase_reg, I915_READ(dspbase_reg)); | |
854 | I915_READ(dspbase_reg); | |
855 | } | |
856 | ||
857 | if (!IS_I9XX(dev)) { | |
858 | /* Wait for vblank for the disable to take effect */ | |
859 | intel_wait_for_vblank(dev); | |
860 | } | |
861 | ||
862 | /* Next, disable display pipes */ | |
863 | temp = I915_READ(pipeconf_reg); | |
864 | if ((temp & PIPEACONF_ENABLE) != 0) { | |
865 | I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE); | |
866 | I915_READ(pipeconf_reg); | |
867 | } | |
868 | ||
869 | /* Wait for vblank for the disable to take effect. */ | |
870 | intel_wait_for_vblank(dev); | |
871 | ||
872 | temp = I915_READ(dpll_reg); | |
873 | if ((temp & DPLL_VCO_ENABLE) != 0) { | |
874 | I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE); | |
875 | I915_READ(dpll_reg); | |
876 | } | |
877 | ||
878 | /* Wait for the clocks to turn off. */ | |
879 | udelay(150); | |
880 | break; | |
881 | } | |
882 | ||
883 | if (!dev->primary->master) | |
884 | return; | |
885 | ||
886 | master_priv = dev->primary->master->driver_priv; | |
887 | if (!master_priv->sarea_priv) | |
888 | return; | |
889 | ||
890 | enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF; | |
891 | ||
892 | switch (pipe) { | |
893 | case 0: | |
894 | master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; | |
895 | master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; | |
896 | break; | |
897 | case 1: | |
898 | master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; | |
899 | master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; | |
900 | break; | |
901 | default: | |
902 | DRM_ERROR("Can't update pipe %d in SAREA\n", pipe); | |
903 | break; | |
904 | } | |
905 | ||
906 | intel_crtc->dpms_mode = mode; | |
907 | } | |
908 | ||
909 | static void intel_crtc_prepare (struct drm_crtc *crtc) | |
910 | { | |
911 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; | |
912 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF); | |
913 | } | |
914 | ||
915 | static void intel_crtc_commit (struct drm_crtc *crtc) | |
916 | { | |
917 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; | |
918 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); | |
919 | } | |
920 | ||
921 | void intel_encoder_prepare (struct drm_encoder *encoder) | |
922 | { | |
923 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
924 | /* lvds has its own version of prepare see intel_lvds_prepare */ | |
925 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF); | |
926 | } | |
927 | ||
928 | void intel_encoder_commit (struct drm_encoder *encoder) | |
929 | { | |
930 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
931 | /* lvds has its own version of commit see intel_lvds_commit */ | |
932 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); | |
933 | } | |
934 | ||
935 | static bool intel_crtc_mode_fixup(struct drm_crtc *crtc, | |
936 | struct drm_display_mode *mode, | |
937 | struct drm_display_mode *adjusted_mode) | |
938 | { | |
939 | return true; | |
940 | } | |
941 | ||
942 | ||
943 | /** Returns the core display clock speed for i830 - i945 */ | |
944 | static int intel_get_core_clock_speed(struct drm_device *dev) | |
945 | { | |
946 | ||
947 | /* Core clock values taken from the published datasheets. | |
948 | * The 830 may go up to 166 Mhz, which we should check. | |
949 | */ | |
950 | if (IS_I945G(dev)) | |
951 | return 400000; | |
952 | else if (IS_I915G(dev)) | |
953 | return 333000; | |
2177832f | 954 | else if (IS_I945GM(dev) || IS_845G(dev) || IS_IGDGM(dev)) |
79e53945 JB |
955 | return 200000; |
956 | else if (IS_I915GM(dev)) { | |
957 | u16 gcfgc = 0; | |
958 | ||
959 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
960 | ||
961 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
962 | return 133000; | |
963 | else { | |
964 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
965 | case GC_DISPLAY_CLOCK_333_MHZ: | |
966 | return 333000; | |
967 | default: | |
968 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
969 | return 190000; | |
970 | } | |
971 | } | |
972 | } else if (IS_I865G(dev)) | |
973 | return 266000; | |
974 | else if (IS_I855(dev)) { | |
975 | u16 hpllcc = 0; | |
976 | /* Assume that the hardware is in the high speed state. This | |
977 | * should be the default. | |
978 | */ | |
979 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
980 | case GC_CLOCK_133_200: | |
981 | case GC_CLOCK_100_200: | |
982 | return 200000; | |
983 | case GC_CLOCK_166_250: | |
984 | return 250000; | |
985 | case GC_CLOCK_100_133: | |
986 | return 133000; | |
987 | } | |
988 | } else /* 852, 830 */ | |
989 | return 133000; | |
990 | ||
991 | return 0; /* Silence gcc warning */ | |
992 | } | |
993 | ||
994 | ||
995 | /** | |
996 | * Return the pipe currently connected to the panel fitter, | |
997 | * or -1 if the panel fitter is not present or not in use | |
998 | */ | |
999 | static int intel_panel_fitter_pipe (struct drm_device *dev) | |
1000 | { | |
1001 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1002 | u32 pfit_control; | |
1003 | ||
1004 | /* i830 doesn't have a panel fitter */ | |
1005 | if (IS_I830(dev)) | |
1006 | return -1; | |
1007 | ||
1008 | pfit_control = I915_READ(PFIT_CONTROL); | |
1009 | ||
1010 | /* See if the panel fitter is in use */ | |
1011 | if ((pfit_control & PFIT_ENABLE) == 0) | |
1012 | return -1; | |
1013 | ||
1014 | /* 965 can place panel fitter on either pipe */ | |
1015 | if (IS_I965G(dev)) | |
1016 | return (pfit_control >> 29) & 0x3; | |
1017 | ||
1018 | /* older chips can only use pipe 1 */ | |
1019 | return 1; | |
1020 | } | |
1021 | ||
5c3b82e2 CW |
1022 | static int intel_crtc_mode_set(struct drm_crtc *crtc, |
1023 | struct drm_display_mode *mode, | |
1024 | struct drm_display_mode *adjusted_mode, | |
1025 | int x, int y, | |
1026 | struct drm_framebuffer *old_fb) | |
79e53945 JB |
1027 | { |
1028 | struct drm_device *dev = crtc->dev; | |
1029 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1030 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1031 | int pipe = intel_crtc->pipe; | |
1032 | int fp_reg = (pipe == 0) ? FPA0 : FPB0; | |
1033 | int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; | |
1034 | int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD; | |
1035 | int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR; | |
1036 | int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF; | |
1037 | int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B; | |
1038 | int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B; | |
1039 | int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B; | |
1040 | int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B; | |
1041 | int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B; | |
1042 | int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B; | |
1043 | int dspsize_reg = (pipe == 0) ? DSPASIZE : DSPBSIZE; | |
1044 | int dsppos_reg = (pipe == 0) ? DSPAPOS : DSPBPOS; | |
1045 | int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC; | |
43565a06 | 1046 | int refclk, num_outputs = 0; |
79e53945 JB |
1047 | intel_clock_t clock; |
1048 | u32 dpll = 0, fp = 0, dspcntr, pipeconf; | |
1049 | bool ok, is_sdvo = false, is_dvo = false; | |
1050 | bool is_crt = false, is_lvds = false, is_tv = false; | |
1051 | struct drm_mode_config *mode_config = &dev->mode_config; | |
1052 | struct drm_connector *connector; | |
d4906093 | 1053 | const intel_limit_t *limit; |
5c3b82e2 | 1054 | int ret; |
79e53945 JB |
1055 | |
1056 | drm_vblank_pre_modeset(dev, pipe); | |
1057 | ||
1058 | list_for_each_entry(connector, &mode_config->connector_list, head) { | |
1059 | struct intel_output *intel_output = to_intel_output(connector); | |
1060 | ||
1061 | if (!connector->encoder || connector->encoder->crtc != crtc) | |
1062 | continue; | |
1063 | ||
1064 | switch (intel_output->type) { | |
1065 | case INTEL_OUTPUT_LVDS: | |
1066 | is_lvds = true; | |
1067 | break; | |
1068 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 1069 | case INTEL_OUTPUT_HDMI: |
79e53945 | 1070 | is_sdvo = true; |
e2f0ba97 JB |
1071 | if (intel_output->needs_tv_clock) |
1072 | is_tv = true; | |
79e53945 JB |
1073 | break; |
1074 | case INTEL_OUTPUT_DVO: | |
1075 | is_dvo = true; | |
1076 | break; | |
1077 | case INTEL_OUTPUT_TVOUT: | |
1078 | is_tv = true; | |
1079 | break; | |
1080 | case INTEL_OUTPUT_ANALOG: | |
1081 | is_crt = true; | |
1082 | break; | |
1083 | } | |
43565a06 KH |
1084 | |
1085 | num_outputs++; | |
79e53945 JB |
1086 | } |
1087 | ||
43565a06 KH |
1088 | if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) { |
1089 | refclk = dev_priv->lvds_ssc_freq * 1000; | |
1090 | DRM_DEBUG("using SSC reference clock of %d MHz\n", refclk / 1000); | |
1091 | } else if (IS_I9XX(dev)) { | |
79e53945 JB |
1092 | refclk = 96000; |
1093 | } else { | |
1094 | refclk = 48000; | |
1095 | } | |
1096 | ||
d4906093 ML |
1097 | /* |
1098 | * Returns a set of divisors for the desired target clock with the given | |
1099 | * refclk, or FALSE. The returned values represent the clock equation: | |
1100 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
1101 | */ | |
1102 | limit = intel_limit(crtc); | |
1103 | ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock); | |
79e53945 JB |
1104 | if (!ok) { |
1105 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
5c3b82e2 | 1106 | return -EINVAL; |
79e53945 JB |
1107 | } |
1108 | ||
7026d4ac ZW |
1109 | /* SDVO TV has fixed PLL values depend on its clock range, |
1110 | this mirrors vbios setting. */ | |
1111 | if (is_sdvo && is_tv) { | |
1112 | if (adjusted_mode->clock >= 100000 | |
1113 | && adjusted_mode->clock < 140500) { | |
1114 | clock.p1 = 2; | |
1115 | clock.p2 = 10; | |
1116 | clock.n = 3; | |
1117 | clock.m1 = 16; | |
1118 | clock.m2 = 8; | |
1119 | } else if (adjusted_mode->clock >= 140500 | |
1120 | && adjusted_mode->clock <= 200000) { | |
1121 | clock.p1 = 1; | |
1122 | clock.p2 = 10; | |
1123 | clock.n = 6; | |
1124 | clock.m1 = 12; | |
1125 | clock.m2 = 8; | |
1126 | } | |
1127 | } | |
1128 | ||
2177832f SL |
1129 | if (IS_IGD(dev)) |
1130 | fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2; | |
1131 | else | |
1132 | fp = clock.n << 16 | clock.m1 << 8 | clock.m2; | |
79e53945 JB |
1133 | |
1134 | dpll = DPLL_VGA_MODE_DIS; | |
1135 | if (IS_I9XX(dev)) { | |
1136 | if (is_lvds) | |
1137 | dpll |= DPLLB_MODE_LVDS; | |
1138 | else | |
1139 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
1140 | if (is_sdvo) { | |
1141 | dpll |= DPLL_DVO_HIGH_SPEED; | |
1142 | if (IS_I945G(dev) || IS_I945GM(dev)) { | |
1143 | int sdvo_pixel_multiply = adjusted_mode->clock / mode->clock; | |
1144 | dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES; | |
1145 | } | |
1146 | } | |
1147 | ||
1148 | /* compute bitmask from p1 value */ | |
2177832f SL |
1149 | if (IS_IGD(dev)) |
1150 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_IGD; | |
1151 | else | |
1152 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
79e53945 JB |
1153 | switch (clock.p2) { |
1154 | case 5: | |
1155 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
1156 | break; | |
1157 | case 7: | |
1158 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
1159 | break; | |
1160 | case 10: | |
1161 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
1162 | break; | |
1163 | case 14: | |
1164 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
1165 | break; | |
1166 | } | |
1167 | if (IS_I965G(dev)) | |
1168 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
1169 | } else { | |
1170 | if (is_lvds) { | |
1171 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
1172 | } else { | |
1173 | if (clock.p1 == 2) | |
1174 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
1175 | else | |
1176 | dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
1177 | if (clock.p2 == 4) | |
1178 | dpll |= PLL_P2_DIVIDE_BY_4; | |
1179 | } | |
1180 | } | |
1181 | ||
43565a06 KH |
1182 | if (is_sdvo && is_tv) |
1183 | dpll |= PLL_REF_INPUT_TVCLKINBC; | |
1184 | else if (is_tv) | |
79e53945 | 1185 | /* XXX: just matching BIOS for now */ |
43565a06 | 1186 | /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ |
79e53945 | 1187 | dpll |= 3; |
43565a06 KH |
1188 | else if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) |
1189 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
79e53945 JB |
1190 | else |
1191 | dpll |= PLL_REF_INPUT_DREFCLK; | |
1192 | ||
1193 | /* setup pipeconf */ | |
1194 | pipeconf = I915_READ(pipeconf_reg); | |
1195 | ||
1196 | /* Set up the display plane register */ | |
1197 | dspcntr = DISPPLANE_GAMMA_ENABLE; | |
1198 | ||
1199 | if (pipe == 0) | |
1200 | dspcntr |= DISPPLANE_SEL_PIPE_A; | |
1201 | else | |
1202 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
1203 | ||
1204 | if (pipe == 0 && !IS_I965G(dev)) { | |
1205 | /* Enable pixel doubling when the dot clock is > 90% of the (display) | |
1206 | * core speed. | |
1207 | * | |
1208 | * XXX: No double-wide on 915GM pipe B. Is that the only reason for the | |
1209 | * pipe == 0 check? | |
1210 | */ | |
1211 | if (mode->clock > intel_get_core_clock_speed(dev) * 9 / 10) | |
1212 | pipeconf |= PIPEACONF_DOUBLE_WIDE; | |
1213 | else | |
1214 | pipeconf &= ~PIPEACONF_DOUBLE_WIDE; | |
1215 | } | |
1216 | ||
1217 | dspcntr |= DISPLAY_PLANE_ENABLE; | |
1218 | pipeconf |= PIPEACONF_ENABLE; | |
1219 | dpll |= DPLL_VCO_ENABLE; | |
1220 | ||
1221 | ||
1222 | /* Disable the panel fitter if it was on our pipe */ | |
1223 | if (intel_panel_fitter_pipe(dev) == pipe) | |
1224 | I915_WRITE(PFIT_CONTROL, 0); | |
1225 | ||
1226 | DRM_DEBUG("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); | |
1227 | drm_mode_debug_printmodeline(mode); | |
1228 | ||
1229 | ||
1230 | if (dpll & DPLL_VCO_ENABLE) { | |
1231 | I915_WRITE(fp_reg, fp); | |
1232 | I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE); | |
1233 | I915_READ(dpll_reg); | |
1234 | udelay(150); | |
1235 | } | |
1236 | ||
1237 | /* The LVDS pin pair needs to be on before the DPLLs are enabled. | |
1238 | * This is an exception to the general rule that mode_set doesn't turn | |
1239 | * things on. | |
1240 | */ | |
1241 | if (is_lvds) { | |
1242 | u32 lvds = I915_READ(LVDS); | |
1243 | ||
1244 | lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT; | |
1245 | /* Set the B0-B3 data pairs corresponding to whether we're going to | |
1246 | * set the DPLLs for dual-channel mode or not. | |
1247 | */ | |
1248 | if (clock.p2 == 7) | |
1249 | lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; | |
1250 | else | |
1251 | lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); | |
1252 | ||
1253 | /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) | |
1254 | * appropriately here, but we need to look more thoroughly into how | |
1255 | * panels behave in the two modes. | |
1256 | */ | |
1257 | ||
1258 | I915_WRITE(LVDS, lvds); | |
1259 | I915_READ(LVDS); | |
1260 | } | |
1261 | ||
1262 | I915_WRITE(fp_reg, fp); | |
1263 | I915_WRITE(dpll_reg, dpll); | |
1264 | I915_READ(dpll_reg); | |
1265 | /* Wait for the clocks to stabilize. */ | |
1266 | udelay(150); | |
1267 | ||
1268 | if (IS_I965G(dev)) { | |
1269 | int sdvo_pixel_multiply = adjusted_mode->clock / mode->clock; | |
1270 | I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) | | |
1271 | ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT)); | |
1272 | } else { | |
1273 | /* write it again -- the BIOS does, after all */ | |
1274 | I915_WRITE(dpll_reg, dpll); | |
1275 | } | |
1276 | I915_READ(dpll_reg); | |
1277 | /* Wait for the clocks to stabilize. */ | |
1278 | udelay(150); | |
1279 | ||
1280 | I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) | | |
1281 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
1282 | I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) | | |
1283 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
1284 | I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) | | |
1285 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
1286 | I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) | | |
1287 | ((adjusted_mode->crtc_vtotal - 1) << 16)); | |
1288 | I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) | | |
1289 | ((adjusted_mode->crtc_vblank_end - 1) << 16)); | |
1290 | I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) | | |
1291 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
1292 | /* pipesrc and dspsize control the size that is scaled from, which should | |
1293 | * always be the user's requested size. | |
1294 | */ | |
1295 | I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1)); | |
1296 | I915_WRITE(dsppos_reg, 0); | |
1297 | I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); | |
1298 | I915_WRITE(pipeconf_reg, pipeconf); | |
1299 | I915_READ(pipeconf_reg); | |
1300 | ||
1301 | intel_wait_for_vblank(dev); | |
1302 | ||
1303 | I915_WRITE(dspcntr_reg, dspcntr); | |
1304 | ||
1305 | /* Flush the plane changes */ | |
5c3b82e2 CW |
1306 | ret = intel_pipe_set_base(crtc, x, y, old_fb); |
1307 | if (ret != 0) | |
1308 | return ret; | |
79e53945 JB |
1309 | |
1310 | drm_vblank_post_modeset(dev, pipe); | |
5c3b82e2 CW |
1311 | |
1312 | return 0; | |
79e53945 JB |
1313 | } |
1314 | ||
1315 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ | |
1316 | void intel_crtc_load_lut(struct drm_crtc *crtc) | |
1317 | { | |
1318 | struct drm_device *dev = crtc->dev; | |
1319 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1320 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1321 | int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B; | |
1322 | int i; | |
1323 | ||
1324 | /* The clocks have to be on to load the palette. */ | |
1325 | if (!crtc->enabled) | |
1326 | return; | |
1327 | ||
1328 | for (i = 0; i < 256; i++) { | |
1329 | I915_WRITE(palreg + 4 * i, | |
1330 | (intel_crtc->lut_r[i] << 16) | | |
1331 | (intel_crtc->lut_g[i] << 8) | | |
1332 | intel_crtc->lut_b[i]); | |
1333 | } | |
1334 | } | |
1335 | ||
1336 | static int intel_crtc_cursor_set(struct drm_crtc *crtc, | |
1337 | struct drm_file *file_priv, | |
1338 | uint32_t handle, | |
1339 | uint32_t width, uint32_t height) | |
1340 | { | |
1341 | struct drm_device *dev = crtc->dev; | |
1342 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1343 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1344 | struct drm_gem_object *bo; | |
1345 | struct drm_i915_gem_object *obj_priv; | |
1346 | int pipe = intel_crtc->pipe; | |
1347 | uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR; | |
1348 | uint32_t base = (pipe == 0) ? CURABASE : CURBBASE; | |
1349 | uint32_t temp; | |
1350 | size_t addr; | |
3f8bc370 | 1351 | int ret; |
79e53945 JB |
1352 | |
1353 | DRM_DEBUG("\n"); | |
1354 | ||
1355 | /* if we want to turn off the cursor ignore width and height */ | |
1356 | if (!handle) { | |
1357 | DRM_DEBUG("cursor off\n"); | |
3f8bc370 KH |
1358 | temp = CURSOR_MODE_DISABLE; |
1359 | addr = 0; | |
1360 | bo = NULL; | |
5004417d | 1361 | mutex_lock(&dev->struct_mutex); |
3f8bc370 | 1362 | goto finish; |
79e53945 JB |
1363 | } |
1364 | ||
1365 | /* Currently we only support 64x64 cursors */ | |
1366 | if (width != 64 || height != 64) { | |
1367 | DRM_ERROR("we currently only support 64x64 cursors\n"); | |
1368 | return -EINVAL; | |
1369 | } | |
1370 | ||
1371 | bo = drm_gem_object_lookup(dev, file_priv, handle); | |
1372 | if (!bo) | |
1373 | return -ENOENT; | |
1374 | ||
1375 | obj_priv = bo->driver_private; | |
1376 | ||
1377 | if (bo->size < width * height * 4) { | |
1378 | DRM_ERROR("buffer is to small\n"); | |
34b8686e DA |
1379 | ret = -ENOMEM; |
1380 | goto fail; | |
79e53945 JB |
1381 | } |
1382 | ||
71acb5eb | 1383 | /* we only need to pin inside GTT if cursor is non-phy */ |
7f9872e0 | 1384 | mutex_lock(&dev->struct_mutex); |
71acb5eb DA |
1385 | if (!dev_priv->cursor_needs_physical) { |
1386 | ret = i915_gem_object_pin(bo, PAGE_SIZE); | |
1387 | if (ret) { | |
1388 | DRM_ERROR("failed to pin cursor bo\n"); | |
7f9872e0 | 1389 | goto fail_locked; |
71acb5eb | 1390 | } |
79e53945 | 1391 | addr = obj_priv->gtt_offset; |
71acb5eb DA |
1392 | } else { |
1393 | ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1); | |
1394 | if (ret) { | |
1395 | DRM_ERROR("failed to attach phys object\n"); | |
7f9872e0 | 1396 | goto fail_locked; |
71acb5eb DA |
1397 | } |
1398 | addr = obj_priv->phys_obj->handle->busaddr; | |
3f8bc370 KH |
1399 | } |
1400 | ||
79e53945 JB |
1401 | temp = 0; |
1402 | /* set the pipe for the cursor */ | |
1403 | temp |= (pipe << 28); | |
1404 | temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; | |
1405 | ||
3f8bc370 | 1406 | finish: |
79e53945 JB |
1407 | I915_WRITE(control, temp); |
1408 | I915_WRITE(base, addr); | |
1409 | ||
3f8bc370 | 1410 | if (intel_crtc->cursor_bo) { |
71acb5eb DA |
1411 | if (dev_priv->cursor_needs_physical) { |
1412 | if (intel_crtc->cursor_bo != bo) | |
1413 | i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo); | |
1414 | } else | |
1415 | i915_gem_object_unpin(intel_crtc->cursor_bo); | |
3f8bc370 KH |
1416 | drm_gem_object_unreference(intel_crtc->cursor_bo); |
1417 | } | |
7f9872e0 | 1418 | mutex_unlock(&dev->struct_mutex); |
3f8bc370 KH |
1419 | |
1420 | intel_crtc->cursor_addr = addr; | |
1421 | intel_crtc->cursor_bo = bo; | |
1422 | ||
79e53945 | 1423 | return 0; |
34b8686e DA |
1424 | fail: |
1425 | mutex_lock(&dev->struct_mutex); | |
7f9872e0 | 1426 | fail_locked: |
34b8686e DA |
1427 | drm_gem_object_unreference(bo); |
1428 | mutex_unlock(&dev->struct_mutex); | |
1429 | return ret; | |
79e53945 JB |
1430 | } |
1431 | ||
1432 | static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) | |
1433 | { | |
1434 | struct drm_device *dev = crtc->dev; | |
1435 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1436 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1437 | int pipe = intel_crtc->pipe; | |
1438 | uint32_t temp = 0; | |
1439 | uint32_t adder; | |
1440 | ||
1441 | if (x < 0) { | |
1442 | temp |= (CURSOR_POS_SIGN << CURSOR_X_SHIFT); | |
1443 | x = -x; | |
1444 | } | |
1445 | if (y < 0) { | |
1446 | temp |= (CURSOR_POS_SIGN << CURSOR_Y_SHIFT); | |
1447 | y = -y; | |
1448 | } | |
1449 | ||
1450 | temp |= ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT); | |
1451 | temp |= ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT); | |
1452 | ||
1453 | adder = intel_crtc->cursor_addr; | |
1454 | I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp); | |
1455 | I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder); | |
1456 | ||
1457 | return 0; | |
1458 | } | |
1459 | ||
1460 | /** Sets the color ramps on behalf of RandR */ | |
1461 | void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, | |
1462 | u16 blue, int regno) | |
1463 | { | |
1464 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1465 | ||
1466 | intel_crtc->lut_r[regno] = red >> 8; | |
1467 | intel_crtc->lut_g[regno] = green >> 8; | |
1468 | intel_crtc->lut_b[regno] = blue >> 8; | |
1469 | } | |
1470 | ||
1471 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, | |
1472 | u16 *blue, uint32_t size) | |
1473 | { | |
1474 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1475 | int i; | |
1476 | ||
1477 | if (size != 256) | |
1478 | return; | |
1479 | ||
1480 | for (i = 0; i < 256; i++) { | |
1481 | intel_crtc->lut_r[i] = red[i] >> 8; | |
1482 | intel_crtc->lut_g[i] = green[i] >> 8; | |
1483 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
1484 | } | |
1485 | ||
1486 | intel_crtc_load_lut(crtc); | |
1487 | } | |
1488 | ||
1489 | /** | |
1490 | * Get a pipe with a simple mode set on it for doing load-based monitor | |
1491 | * detection. | |
1492 | * | |
1493 | * It will be up to the load-detect code to adjust the pipe as appropriate for | |
1494 | * its requirements. The pipe will be connected to no other outputs. | |
1495 | * | |
1496 | * Currently this code will only succeed if there is a pipe with no outputs | |
1497 | * configured for it. In the future, it could choose to temporarily disable | |
1498 | * some outputs to free up a pipe for its use. | |
1499 | * | |
1500 | * \return crtc, or NULL if no pipes are available. | |
1501 | */ | |
1502 | ||
1503 | /* VESA 640x480x72Hz mode to set on the pipe */ | |
1504 | static struct drm_display_mode load_detect_mode = { | |
1505 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
1506 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
1507 | }; | |
1508 | ||
1509 | struct drm_crtc *intel_get_load_detect_pipe(struct intel_output *intel_output, | |
1510 | struct drm_display_mode *mode, | |
1511 | int *dpms_mode) | |
1512 | { | |
1513 | struct intel_crtc *intel_crtc; | |
1514 | struct drm_crtc *possible_crtc; | |
1515 | struct drm_crtc *supported_crtc =NULL; | |
1516 | struct drm_encoder *encoder = &intel_output->enc; | |
1517 | struct drm_crtc *crtc = NULL; | |
1518 | struct drm_device *dev = encoder->dev; | |
1519 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
1520 | struct drm_crtc_helper_funcs *crtc_funcs; | |
1521 | int i = -1; | |
1522 | ||
1523 | /* | |
1524 | * Algorithm gets a little messy: | |
1525 | * - if the connector already has an assigned crtc, use it (but make | |
1526 | * sure it's on first) | |
1527 | * - try to find the first unused crtc that can drive this connector, | |
1528 | * and use that if we find one | |
1529 | * - if there are no unused crtcs available, try to use the first | |
1530 | * one we found that supports the connector | |
1531 | */ | |
1532 | ||
1533 | /* See if we already have a CRTC for this connector */ | |
1534 | if (encoder->crtc) { | |
1535 | crtc = encoder->crtc; | |
1536 | /* Make sure the crtc and connector are running */ | |
1537 | intel_crtc = to_intel_crtc(crtc); | |
1538 | *dpms_mode = intel_crtc->dpms_mode; | |
1539 | if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) { | |
1540 | crtc_funcs = crtc->helper_private; | |
1541 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); | |
1542 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); | |
1543 | } | |
1544 | return crtc; | |
1545 | } | |
1546 | ||
1547 | /* Find an unused one (if possible) */ | |
1548 | list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) { | |
1549 | i++; | |
1550 | if (!(encoder->possible_crtcs & (1 << i))) | |
1551 | continue; | |
1552 | if (!possible_crtc->enabled) { | |
1553 | crtc = possible_crtc; | |
1554 | break; | |
1555 | } | |
1556 | if (!supported_crtc) | |
1557 | supported_crtc = possible_crtc; | |
1558 | } | |
1559 | ||
1560 | /* | |
1561 | * If we didn't find an unused CRTC, don't use any. | |
1562 | */ | |
1563 | if (!crtc) { | |
1564 | return NULL; | |
1565 | } | |
1566 | ||
1567 | encoder->crtc = crtc; | |
1568 | intel_output->load_detect_temp = true; | |
1569 | ||
1570 | intel_crtc = to_intel_crtc(crtc); | |
1571 | *dpms_mode = intel_crtc->dpms_mode; | |
1572 | ||
1573 | if (!crtc->enabled) { | |
1574 | if (!mode) | |
1575 | mode = &load_detect_mode; | |
3c4fdcfb | 1576 | drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb); |
79e53945 JB |
1577 | } else { |
1578 | if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) { | |
1579 | crtc_funcs = crtc->helper_private; | |
1580 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); | |
1581 | } | |
1582 | ||
1583 | /* Add this connector to the crtc */ | |
1584 | encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode); | |
1585 | encoder_funcs->commit(encoder); | |
1586 | } | |
1587 | /* let the connector get through one full cycle before testing */ | |
1588 | intel_wait_for_vblank(dev); | |
1589 | ||
1590 | return crtc; | |
1591 | } | |
1592 | ||
1593 | void intel_release_load_detect_pipe(struct intel_output *intel_output, int dpms_mode) | |
1594 | { | |
1595 | struct drm_encoder *encoder = &intel_output->enc; | |
1596 | struct drm_device *dev = encoder->dev; | |
1597 | struct drm_crtc *crtc = encoder->crtc; | |
1598 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
1599 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; | |
1600 | ||
1601 | if (intel_output->load_detect_temp) { | |
1602 | encoder->crtc = NULL; | |
1603 | intel_output->load_detect_temp = false; | |
1604 | crtc->enabled = drm_helper_crtc_in_use(crtc); | |
1605 | drm_helper_disable_unused_functions(dev); | |
1606 | } | |
1607 | ||
1608 | /* Switch crtc and output back off if necessary */ | |
1609 | if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) { | |
1610 | if (encoder->crtc == crtc) | |
1611 | encoder_funcs->dpms(encoder, dpms_mode); | |
1612 | crtc_funcs->dpms(crtc, dpms_mode); | |
1613 | } | |
1614 | } | |
1615 | ||
1616 | /* Returns the clock of the currently programmed mode of the given pipe. */ | |
1617 | static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc) | |
1618 | { | |
1619 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1620 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1621 | int pipe = intel_crtc->pipe; | |
1622 | u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B); | |
1623 | u32 fp; | |
1624 | intel_clock_t clock; | |
1625 | ||
1626 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
1627 | fp = I915_READ((pipe == 0) ? FPA0 : FPB0); | |
1628 | else | |
1629 | fp = I915_READ((pipe == 0) ? FPA1 : FPB1); | |
1630 | ||
1631 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
2177832f SL |
1632 | if (IS_IGD(dev)) { |
1633 | clock.n = ffs((fp & FP_N_IGD_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
1634 | clock.m2 = (fp & FP_M2_IGD_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
1635 | } else { | |
1636 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
1637 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
1638 | } | |
1639 | ||
79e53945 | 1640 | if (IS_I9XX(dev)) { |
2177832f SL |
1641 | if (IS_IGD(dev)) |
1642 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_IGD) >> | |
1643 | DPLL_FPA01_P1_POST_DIV_SHIFT_IGD); | |
1644 | else | |
1645 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
1646 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
1647 | ||
1648 | switch (dpll & DPLL_MODE_MASK) { | |
1649 | case DPLLB_MODE_DAC_SERIAL: | |
1650 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
1651 | 5 : 10; | |
1652 | break; | |
1653 | case DPLLB_MODE_LVDS: | |
1654 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
1655 | 7 : 14; | |
1656 | break; | |
1657 | default: | |
1658 | DRM_DEBUG("Unknown DPLL mode %08x in programmed " | |
1659 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); | |
1660 | return 0; | |
1661 | } | |
1662 | ||
1663 | /* XXX: Handle the 100Mhz refclk */ | |
2177832f | 1664 | intel_clock(dev, 96000, &clock); |
79e53945 JB |
1665 | } else { |
1666 | bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN); | |
1667 | ||
1668 | if (is_lvds) { | |
1669 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
1670 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
1671 | clock.p2 = 14; | |
1672 | ||
1673 | if ((dpll & PLL_REF_INPUT_MASK) == | |
1674 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { | |
1675 | /* XXX: might not be 66MHz */ | |
2177832f | 1676 | intel_clock(dev, 66000, &clock); |
79e53945 | 1677 | } else |
2177832f | 1678 | intel_clock(dev, 48000, &clock); |
79e53945 JB |
1679 | } else { |
1680 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
1681 | clock.p1 = 2; | |
1682 | else { | |
1683 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
1684 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
1685 | } | |
1686 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
1687 | clock.p2 = 4; | |
1688 | else | |
1689 | clock.p2 = 2; | |
1690 | ||
2177832f | 1691 | intel_clock(dev, 48000, &clock); |
79e53945 JB |
1692 | } |
1693 | } | |
1694 | ||
1695 | /* XXX: It would be nice to validate the clocks, but we can't reuse | |
1696 | * i830PllIsValid() because it relies on the xf86_config connector | |
1697 | * configuration being accurate, which it isn't necessarily. | |
1698 | */ | |
1699 | ||
1700 | return clock.dot; | |
1701 | } | |
1702 | ||
1703 | /** Returns the currently programmed mode of the given pipe. */ | |
1704 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
1705 | struct drm_crtc *crtc) | |
1706 | { | |
1707 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1708 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1709 | int pipe = intel_crtc->pipe; | |
1710 | struct drm_display_mode *mode; | |
1711 | int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B); | |
1712 | int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B); | |
1713 | int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B); | |
1714 | int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B); | |
1715 | ||
1716 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
1717 | if (!mode) | |
1718 | return NULL; | |
1719 | ||
1720 | mode->clock = intel_crtc_clock_get(dev, crtc); | |
1721 | mode->hdisplay = (htot & 0xffff) + 1; | |
1722 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
1723 | mode->hsync_start = (hsync & 0xffff) + 1; | |
1724 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
1725 | mode->vdisplay = (vtot & 0xffff) + 1; | |
1726 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
1727 | mode->vsync_start = (vsync & 0xffff) + 1; | |
1728 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
1729 | ||
1730 | drm_mode_set_name(mode); | |
1731 | drm_mode_set_crtcinfo(mode, 0); | |
1732 | ||
1733 | return mode; | |
1734 | } | |
1735 | ||
1736 | static void intel_crtc_destroy(struct drm_crtc *crtc) | |
1737 | { | |
1738 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1739 | ||
1740 | drm_crtc_cleanup(crtc); | |
1741 | kfree(intel_crtc); | |
1742 | } | |
1743 | ||
1744 | static const struct drm_crtc_helper_funcs intel_helper_funcs = { | |
1745 | .dpms = intel_crtc_dpms, | |
1746 | .mode_fixup = intel_crtc_mode_fixup, | |
1747 | .mode_set = intel_crtc_mode_set, | |
1748 | .mode_set_base = intel_pipe_set_base, | |
1749 | .prepare = intel_crtc_prepare, | |
1750 | .commit = intel_crtc_commit, | |
1751 | }; | |
1752 | ||
1753 | static const struct drm_crtc_funcs intel_crtc_funcs = { | |
1754 | .cursor_set = intel_crtc_cursor_set, | |
1755 | .cursor_move = intel_crtc_cursor_move, | |
1756 | .gamma_set = intel_crtc_gamma_set, | |
1757 | .set_config = drm_crtc_helper_set_config, | |
1758 | .destroy = intel_crtc_destroy, | |
1759 | }; | |
1760 | ||
1761 | ||
b358d0a6 | 1762 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 JB |
1763 | { |
1764 | struct intel_crtc *intel_crtc; | |
1765 | int i; | |
1766 | ||
1767 | intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); | |
1768 | if (intel_crtc == NULL) | |
1769 | return; | |
1770 | ||
1771 | drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs); | |
1772 | ||
1773 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
1774 | intel_crtc->pipe = pipe; | |
1775 | for (i = 0; i < 256; i++) { | |
1776 | intel_crtc->lut_r[i] = i; | |
1777 | intel_crtc->lut_g[i] = i; | |
1778 | intel_crtc->lut_b[i] = i; | |
1779 | } | |
1780 | ||
1781 | intel_crtc->cursor_addr = 0; | |
1782 | intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF; | |
1783 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); | |
1784 | ||
1785 | intel_crtc->mode_set.crtc = &intel_crtc->base; | |
1786 | intel_crtc->mode_set.connectors = (struct drm_connector **)(intel_crtc + 1); | |
1787 | intel_crtc->mode_set.num_connectors = 0; | |
1788 | ||
1789 | if (i915_fbpercrtc) { | |
1790 | ||
1791 | ||
1792 | ||
1793 | } | |
1794 | } | |
1795 | ||
1796 | struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe) | |
1797 | { | |
1798 | struct drm_crtc *crtc = NULL; | |
1799 | ||
1800 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
1801 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1802 | if (intel_crtc->pipe == pipe) | |
1803 | break; | |
1804 | } | |
1805 | return crtc; | |
1806 | } | |
1807 | ||
b358d0a6 | 1808 | static int intel_connector_clones(struct drm_device *dev, int type_mask) |
79e53945 JB |
1809 | { |
1810 | int index_mask = 0; | |
1811 | struct drm_connector *connector; | |
1812 | int entry = 0; | |
1813 | ||
1814 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
1815 | struct intel_output *intel_output = to_intel_output(connector); | |
1816 | if (type_mask & (1 << intel_output->type)) | |
1817 | index_mask |= (1 << entry); | |
1818 | entry++; | |
1819 | } | |
1820 | return index_mask; | |
1821 | } | |
1822 | ||
1823 | ||
1824 | static void intel_setup_outputs(struct drm_device *dev) | |
1825 | { | |
725e30ad | 1826 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 JB |
1827 | struct drm_connector *connector; |
1828 | ||
1829 | intel_crt_init(dev); | |
1830 | ||
1831 | /* Set up integrated LVDS */ | |
1832 | if (IS_MOBILE(dev) && !IS_I830(dev)) | |
1833 | intel_lvds_init(dev); | |
1834 | ||
1835 | if (IS_I9XX(dev)) { | |
7d57382e | 1836 | int found; |
13520b05 | 1837 | u32 reg; |
7d57382e | 1838 | |
725e30ad EA |
1839 | if (I915_READ(SDVOB) & SDVO_DETECTED) { |
1840 | found = intel_sdvo_init(dev, SDVOB); | |
1841 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) | |
1842 | intel_hdmi_init(dev, SDVOB); | |
1843 | } | |
13520b05 KH |
1844 | |
1845 | /* Before G4X SDVOC doesn't have its own detect register */ | |
1846 | if (IS_G4X(dev)) | |
1847 | reg = SDVOC; | |
1848 | else | |
1849 | reg = SDVOB; | |
1850 | ||
1851 | if (I915_READ(reg) & SDVO_DETECTED) { | |
725e30ad EA |
1852 | found = intel_sdvo_init(dev, SDVOC); |
1853 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) | |
1854 | intel_hdmi_init(dev, SDVOC); | |
1855 | } | |
79e53945 JB |
1856 | } else |
1857 | intel_dvo_init(dev); | |
1858 | ||
1fc45d84 | 1859 | if (IS_I9XX(dev) && IS_MOBILE(dev)) |
79e53945 JB |
1860 | intel_tv_init(dev); |
1861 | ||
1862 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
1863 | struct intel_output *intel_output = to_intel_output(connector); | |
1864 | struct drm_encoder *encoder = &intel_output->enc; | |
1865 | int crtc_mask = 0, clone_mask = 0; | |
1866 | ||
1867 | /* valid crtcs */ | |
1868 | switch(intel_output->type) { | |
7d57382e EA |
1869 | case INTEL_OUTPUT_HDMI: |
1870 | crtc_mask = ((1 << 0)| | |
1871 | (1 << 1)); | |
1872 | clone_mask = ((1 << INTEL_OUTPUT_HDMI)); | |
1873 | break; | |
79e53945 JB |
1874 | case INTEL_OUTPUT_DVO: |
1875 | case INTEL_OUTPUT_SDVO: | |
1876 | crtc_mask = ((1 << 0)| | |
1877 | (1 << 1)); | |
1878 | clone_mask = ((1 << INTEL_OUTPUT_ANALOG) | | |
1879 | (1 << INTEL_OUTPUT_DVO) | | |
1880 | (1 << INTEL_OUTPUT_SDVO)); | |
1881 | break; | |
1882 | case INTEL_OUTPUT_ANALOG: | |
1883 | crtc_mask = ((1 << 0)| | |
1884 | (1 << 1)); | |
1885 | clone_mask = ((1 << INTEL_OUTPUT_ANALOG) | | |
1886 | (1 << INTEL_OUTPUT_DVO) | | |
1887 | (1 << INTEL_OUTPUT_SDVO)); | |
1888 | break; | |
1889 | case INTEL_OUTPUT_LVDS: | |
1890 | crtc_mask = (1 << 1); | |
1891 | clone_mask = (1 << INTEL_OUTPUT_LVDS); | |
1892 | break; | |
1893 | case INTEL_OUTPUT_TVOUT: | |
1894 | crtc_mask = ((1 << 0) | | |
1895 | (1 << 1)); | |
1896 | clone_mask = (1 << INTEL_OUTPUT_TVOUT); | |
1897 | break; | |
1898 | } | |
1899 | encoder->possible_crtcs = crtc_mask; | |
1900 | encoder->possible_clones = intel_connector_clones(dev, clone_mask); | |
1901 | } | |
1902 | } | |
1903 | ||
1904 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
1905 | { | |
1906 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
1907 | struct drm_device *dev = fb->dev; | |
1908 | ||
1909 | if (fb->fbdev) | |
1910 | intelfb_remove(dev, fb); | |
1911 | ||
1912 | drm_framebuffer_cleanup(fb); | |
1913 | mutex_lock(&dev->struct_mutex); | |
1914 | drm_gem_object_unreference(intel_fb->obj); | |
1915 | mutex_unlock(&dev->struct_mutex); | |
1916 | ||
1917 | kfree(intel_fb); | |
1918 | } | |
1919 | ||
1920 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
1921 | struct drm_file *file_priv, | |
1922 | unsigned int *handle) | |
1923 | { | |
1924 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
1925 | struct drm_gem_object *object = intel_fb->obj; | |
1926 | ||
1927 | return drm_gem_handle_create(file_priv, object, handle); | |
1928 | } | |
1929 | ||
1930 | static const struct drm_framebuffer_funcs intel_fb_funcs = { | |
1931 | .destroy = intel_user_framebuffer_destroy, | |
1932 | .create_handle = intel_user_framebuffer_create_handle, | |
1933 | }; | |
1934 | ||
1935 | int intel_framebuffer_create(struct drm_device *dev, | |
1936 | struct drm_mode_fb_cmd *mode_cmd, | |
1937 | struct drm_framebuffer **fb, | |
1938 | struct drm_gem_object *obj) | |
1939 | { | |
1940 | struct intel_framebuffer *intel_fb; | |
1941 | int ret; | |
1942 | ||
1943 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
1944 | if (!intel_fb) | |
1945 | return -ENOMEM; | |
1946 | ||
1947 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); | |
1948 | if (ret) { | |
1949 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
1950 | return ret; | |
1951 | } | |
1952 | ||
1953 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); | |
1954 | ||
1955 | intel_fb->obj = obj; | |
1956 | ||
1957 | *fb = &intel_fb->base; | |
1958 | ||
1959 | return 0; | |
1960 | } | |
1961 | ||
1962 | ||
1963 | static struct drm_framebuffer * | |
1964 | intel_user_framebuffer_create(struct drm_device *dev, | |
1965 | struct drm_file *filp, | |
1966 | struct drm_mode_fb_cmd *mode_cmd) | |
1967 | { | |
1968 | struct drm_gem_object *obj; | |
1969 | struct drm_framebuffer *fb; | |
1970 | int ret; | |
1971 | ||
1972 | obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle); | |
1973 | if (!obj) | |
1974 | return NULL; | |
1975 | ||
1976 | ret = intel_framebuffer_create(dev, mode_cmd, &fb, obj); | |
1977 | if (ret) { | |
496818f0 | 1978 | mutex_lock(&dev->struct_mutex); |
79e53945 | 1979 | drm_gem_object_unreference(obj); |
496818f0 | 1980 | mutex_unlock(&dev->struct_mutex); |
79e53945 JB |
1981 | return NULL; |
1982 | } | |
1983 | ||
1984 | return fb; | |
1985 | } | |
1986 | ||
79e53945 | 1987 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 JB |
1988 | .fb_create = intel_user_framebuffer_create, |
1989 | .fb_changed = intelfb_probe, | |
1990 | }; | |
1991 | ||
1992 | void intel_modeset_init(struct drm_device *dev) | |
1993 | { | |
1994 | int num_pipe; | |
1995 | int i; | |
1996 | ||
1997 | drm_mode_config_init(dev); | |
1998 | ||
1999 | dev->mode_config.min_width = 0; | |
2000 | dev->mode_config.min_height = 0; | |
2001 | ||
2002 | dev->mode_config.funcs = (void *)&intel_mode_funcs; | |
2003 | ||
2004 | if (IS_I965G(dev)) { | |
2005 | dev->mode_config.max_width = 8192; | |
2006 | dev->mode_config.max_height = 8192; | |
2007 | } else { | |
2008 | dev->mode_config.max_width = 2048; | |
2009 | dev->mode_config.max_height = 2048; | |
2010 | } | |
2011 | ||
2012 | /* set memory base */ | |
2013 | if (IS_I9XX(dev)) | |
2014 | dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2); | |
2015 | else | |
2016 | dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0); | |
2017 | ||
2018 | if (IS_MOBILE(dev) || IS_I9XX(dev)) | |
2019 | num_pipe = 2; | |
2020 | else | |
2021 | num_pipe = 1; | |
2022 | DRM_DEBUG("%d display pipe%s available.\n", | |
2023 | num_pipe, num_pipe > 1 ? "s" : ""); | |
2024 | ||
2025 | for (i = 0; i < num_pipe; i++) { | |
2026 | intel_crtc_init(dev, i); | |
2027 | } | |
2028 | ||
2029 | intel_setup_outputs(dev); | |
2030 | } | |
2031 | ||
2032 | void intel_modeset_cleanup(struct drm_device *dev) | |
2033 | { | |
2034 | drm_mode_config_cleanup(dev); | |
2035 | } | |
2036 | ||
2037 | ||
2038 | /* current intel driver doesn't take advantage of encoders | |
2039 | always give back the encoder for the connector | |
2040 | */ | |
2041 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) | |
2042 | { | |
2043 | struct intel_output *intel_output = to_intel_output(connector); | |
2044 | ||
2045 | return &intel_output->enc; | |
2046 | } |