Commit | Line | Data |
---|---|---|
79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
27 | #include <linux/i2c.h> | |
7662c8bd | 28 | #include <linux/kernel.h> |
79e53945 JB |
29 | #include "drmP.h" |
30 | #include "intel_drv.h" | |
31 | #include "i915_drm.h" | |
32 | #include "i915_drv.h" | |
a4fc5ed6 | 33 | #include "intel_dp.h" |
79e53945 JB |
34 | |
35 | #include "drm_crtc_helper.h" | |
36 | ||
37 | bool intel_pipe_has_type (struct drm_crtc *crtc, int type); | |
7662c8bd | 38 | static void intel_update_watermarks(struct drm_device *dev); |
79e53945 JB |
39 | |
40 | typedef struct { | |
41 | /* given values */ | |
42 | int n; | |
43 | int m1, m2; | |
44 | int p1, p2; | |
45 | /* derived values */ | |
46 | int dot; | |
47 | int vco; | |
48 | int m; | |
49 | int p; | |
50 | } intel_clock_t; | |
51 | ||
52 | typedef struct { | |
53 | int min, max; | |
54 | } intel_range_t; | |
55 | ||
56 | typedef struct { | |
57 | int dot_limit; | |
58 | int p2_slow, p2_fast; | |
59 | } intel_p2_t; | |
60 | ||
61 | #define INTEL_P2_NUM 2 | |
d4906093 ML |
62 | typedef struct intel_limit intel_limit_t; |
63 | struct intel_limit { | |
79e53945 JB |
64 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
65 | intel_p2_t p2; | |
d4906093 ML |
66 | bool (* find_pll)(const intel_limit_t *, struct drm_crtc *, |
67 | int, int, intel_clock_t *); | |
68 | }; | |
79e53945 JB |
69 | |
70 | #define I8XX_DOT_MIN 25000 | |
71 | #define I8XX_DOT_MAX 350000 | |
72 | #define I8XX_VCO_MIN 930000 | |
73 | #define I8XX_VCO_MAX 1400000 | |
74 | #define I8XX_N_MIN 3 | |
75 | #define I8XX_N_MAX 16 | |
76 | #define I8XX_M_MIN 96 | |
77 | #define I8XX_M_MAX 140 | |
78 | #define I8XX_M1_MIN 18 | |
79 | #define I8XX_M1_MAX 26 | |
80 | #define I8XX_M2_MIN 6 | |
81 | #define I8XX_M2_MAX 16 | |
82 | #define I8XX_P_MIN 4 | |
83 | #define I8XX_P_MAX 128 | |
84 | #define I8XX_P1_MIN 2 | |
85 | #define I8XX_P1_MAX 33 | |
86 | #define I8XX_P1_LVDS_MIN 1 | |
87 | #define I8XX_P1_LVDS_MAX 6 | |
88 | #define I8XX_P2_SLOW 4 | |
89 | #define I8XX_P2_FAST 2 | |
90 | #define I8XX_P2_LVDS_SLOW 14 | |
91 | #define I8XX_P2_LVDS_FAST 14 /* No fast option */ | |
92 | #define I8XX_P2_SLOW_LIMIT 165000 | |
93 | ||
94 | #define I9XX_DOT_MIN 20000 | |
95 | #define I9XX_DOT_MAX 400000 | |
96 | #define I9XX_VCO_MIN 1400000 | |
97 | #define I9XX_VCO_MAX 2800000 | |
2177832f SL |
98 | #define IGD_VCO_MIN 1700000 |
99 | #define IGD_VCO_MAX 3500000 | |
f3cade5c KH |
100 | #define I9XX_N_MIN 1 |
101 | #define I9XX_N_MAX 6 | |
2177832f SL |
102 | /* IGD's Ncounter is a ring counter */ |
103 | #define IGD_N_MIN 3 | |
104 | #define IGD_N_MAX 6 | |
79e53945 JB |
105 | #define I9XX_M_MIN 70 |
106 | #define I9XX_M_MAX 120 | |
2177832f SL |
107 | #define IGD_M_MIN 2 |
108 | #define IGD_M_MAX 256 | |
79e53945 | 109 | #define I9XX_M1_MIN 10 |
f3cade5c | 110 | #define I9XX_M1_MAX 22 |
79e53945 JB |
111 | #define I9XX_M2_MIN 5 |
112 | #define I9XX_M2_MAX 9 | |
2177832f SL |
113 | /* IGD M1 is reserved, and must be 0 */ |
114 | #define IGD_M1_MIN 0 | |
115 | #define IGD_M1_MAX 0 | |
116 | #define IGD_M2_MIN 0 | |
117 | #define IGD_M2_MAX 254 | |
79e53945 JB |
118 | #define I9XX_P_SDVO_DAC_MIN 5 |
119 | #define I9XX_P_SDVO_DAC_MAX 80 | |
120 | #define I9XX_P_LVDS_MIN 7 | |
121 | #define I9XX_P_LVDS_MAX 98 | |
2177832f SL |
122 | #define IGD_P_LVDS_MIN 7 |
123 | #define IGD_P_LVDS_MAX 112 | |
79e53945 JB |
124 | #define I9XX_P1_MIN 1 |
125 | #define I9XX_P1_MAX 8 | |
126 | #define I9XX_P2_SDVO_DAC_SLOW 10 | |
127 | #define I9XX_P2_SDVO_DAC_FAST 5 | |
128 | #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000 | |
129 | #define I9XX_P2_LVDS_SLOW 14 | |
130 | #define I9XX_P2_LVDS_FAST 7 | |
131 | #define I9XX_P2_LVDS_SLOW_LIMIT 112000 | |
132 | ||
044c7c41 ML |
133 | /*The parameter is for SDVO on G4x platform*/ |
134 | #define G4X_DOT_SDVO_MIN 25000 | |
135 | #define G4X_DOT_SDVO_MAX 270000 | |
136 | #define G4X_VCO_MIN 1750000 | |
137 | #define G4X_VCO_MAX 3500000 | |
138 | #define G4X_N_SDVO_MIN 1 | |
139 | #define G4X_N_SDVO_MAX 4 | |
140 | #define G4X_M_SDVO_MIN 104 | |
141 | #define G4X_M_SDVO_MAX 138 | |
142 | #define G4X_M1_SDVO_MIN 17 | |
143 | #define G4X_M1_SDVO_MAX 23 | |
144 | #define G4X_M2_SDVO_MIN 5 | |
145 | #define G4X_M2_SDVO_MAX 11 | |
146 | #define G4X_P_SDVO_MIN 10 | |
147 | #define G4X_P_SDVO_MAX 30 | |
148 | #define G4X_P1_SDVO_MIN 1 | |
149 | #define G4X_P1_SDVO_MAX 3 | |
150 | #define G4X_P2_SDVO_SLOW 10 | |
151 | #define G4X_P2_SDVO_FAST 10 | |
152 | #define G4X_P2_SDVO_LIMIT 270000 | |
153 | ||
154 | /*The parameter is for HDMI_DAC on G4x platform*/ | |
155 | #define G4X_DOT_HDMI_DAC_MIN 22000 | |
156 | #define G4X_DOT_HDMI_DAC_MAX 400000 | |
157 | #define G4X_N_HDMI_DAC_MIN 1 | |
158 | #define G4X_N_HDMI_DAC_MAX 4 | |
159 | #define G4X_M_HDMI_DAC_MIN 104 | |
160 | #define G4X_M_HDMI_DAC_MAX 138 | |
161 | #define G4X_M1_HDMI_DAC_MIN 16 | |
162 | #define G4X_M1_HDMI_DAC_MAX 23 | |
163 | #define G4X_M2_HDMI_DAC_MIN 5 | |
164 | #define G4X_M2_HDMI_DAC_MAX 11 | |
165 | #define G4X_P_HDMI_DAC_MIN 5 | |
166 | #define G4X_P_HDMI_DAC_MAX 80 | |
167 | #define G4X_P1_HDMI_DAC_MIN 1 | |
168 | #define G4X_P1_HDMI_DAC_MAX 8 | |
169 | #define G4X_P2_HDMI_DAC_SLOW 10 | |
170 | #define G4X_P2_HDMI_DAC_FAST 5 | |
171 | #define G4X_P2_HDMI_DAC_LIMIT 165000 | |
172 | ||
173 | /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/ | |
174 | #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000 | |
175 | #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000 | |
176 | #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1 | |
177 | #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3 | |
178 | #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104 | |
179 | #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138 | |
180 | #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17 | |
181 | #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23 | |
182 | #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5 | |
183 | #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11 | |
184 | #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28 | |
185 | #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112 | |
186 | #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2 | |
187 | #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8 | |
188 | #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14 | |
189 | #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14 | |
190 | #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0 | |
191 | ||
192 | /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/ | |
193 | #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000 | |
194 | #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000 | |
195 | #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1 | |
196 | #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3 | |
197 | #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104 | |
198 | #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138 | |
199 | #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17 | |
200 | #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23 | |
201 | #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5 | |
202 | #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11 | |
203 | #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14 | |
204 | #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42 | |
205 | #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2 | |
206 | #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6 | |
207 | #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7 | |
208 | #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7 | |
209 | #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0 | |
210 | ||
a4fc5ed6 KP |
211 | /*The parameter is for DISPLAY PORT on G4x platform*/ |
212 | #define G4X_DOT_DISPLAY_PORT_MIN 161670 | |
213 | #define G4X_DOT_DISPLAY_PORT_MAX 227000 | |
214 | #define G4X_N_DISPLAY_PORT_MIN 1 | |
215 | #define G4X_N_DISPLAY_PORT_MAX 2 | |
216 | #define G4X_M_DISPLAY_PORT_MIN 97 | |
217 | #define G4X_M_DISPLAY_PORT_MAX 108 | |
218 | #define G4X_M1_DISPLAY_PORT_MIN 0x10 | |
219 | #define G4X_M1_DISPLAY_PORT_MAX 0x12 | |
220 | #define G4X_M2_DISPLAY_PORT_MIN 0x05 | |
221 | #define G4X_M2_DISPLAY_PORT_MAX 0x06 | |
222 | #define G4X_P_DISPLAY_PORT_MIN 10 | |
223 | #define G4X_P_DISPLAY_PORT_MAX 20 | |
224 | #define G4X_P1_DISPLAY_PORT_MIN 1 | |
225 | #define G4X_P1_DISPLAY_PORT_MAX 2 | |
226 | #define G4X_P2_DISPLAY_PORT_SLOW 10 | |
227 | #define G4X_P2_DISPLAY_PORT_FAST 10 | |
228 | #define G4X_P2_DISPLAY_PORT_LIMIT 0 | |
229 | ||
2c07245f ZW |
230 | /* IGDNG */ |
231 | /* as we calculate clock using (register_value + 2) for | |
232 | N/M1/M2, so here the range value for them is (actual_value-2). | |
233 | */ | |
234 | #define IGDNG_DOT_MIN 25000 | |
235 | #define IGDNG_DOT_MAX 350000 | |
236 | #define IGDNG_VCO_MIN 1760000 | |
237 | #define IGDNG_VCO_MAX 3510000 | |
238 | #define IGDNG_N_MIN 1 | |
239 | #define IGDNG_N_MAX 5 | |
240 | #define IGDNG_M_MIN 79 | |
241 | #define IGDNG_M_MAX 118 | |
242 | #define IGDNG_M1_MIN 12 | |
243 | #define IGDNG_M1_MAX 23 | |
244 | #define IGDNG_M2_MIN 5 | |
245 | #define IGDNG_M2_MAX 9 | |
246 | #define IGDNG_P_SDVO_DAC_MIN 5 | |
247 | #define IGDNG_P_SDVO_DAC_MAX 80 | |
248 | #define IGDNG_P_LVDS_MIN 28 | |
249 | #define IGDNG_P_LVDS_MAX 112 | |
250 | #define IGDNG_P1_MIN 1 | |
251 | #define IGDNG_P1_MAX 8 | |
252 | #define IGDNG_P2_SDVO_DAC_SLOW 10 | |
253 | #define IGDNG_P2_SDVO_DAC_FAST 5 | |
254 | #define IGDNG_P2_LVDS_SLOW 14 /* single channel */ | |
255 | #define IGDNG_P2_LVDS_FAST 7 /* double channel */ | |
256 | #define IGDNG_P2_DOT_LIMIT 225000 /* 225Mhz */ | |
257 | ||
d4906093 ML |
258 | static bool |
259 | intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
260 | int target, int refclk, intel_clock_t *best_clock); | |
261 | static bool | |
262 | intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
263 | int target, int refclk, intel_clock_t *best_clock); | |
2c07245f ZW |
264 | static bool |
265 | intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
266 | int target, int refclk, intel_clock_t *best_clock); | |
79e53945 | 267 | |
a4fc5ed6 KP |
268 | static bool |
269 | intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc, | |
270 | int target, int refclk, intel_clock_t *best_clock); | |
5eb08b69 ZW |
271 | static bool |
272 | intel_find_pll_igdng_dp(const intel_limit_t *, struct drm_crtc *crtc, | |
273 | int target, int refclk, intel_clock_t *best_clock); | |
a4fc5ed6 | 274 | |
e4b36699 | 275 | static const intel_limit_t intel_limits_i8xx_dvo = { |
79e53945 JB |
276 | .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX }, |
277 | .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX }, | |
278 | .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX }, | |
279 | .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX }, | |
280 | .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX }, | |
281 | .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX }, | |
282 | .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX }, | |
283 | .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX }, | |
284 | .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT, | |
285 | .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST }, | |
d4906093 | 286 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
287 | }; |
288 | ||
289 | static const intel_limit_t intel_limits_i8xx_lvds = { | |
79e53945 JB |
290 | .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX }, |
291 | .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX }, | |
292 | .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX }, | |
293 | .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX }, | |
294 | .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX }, | |
295 | .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX }, | |
296 | .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX }, | |
297 | .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX }, | |
298 | .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT, | |
299 | .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST }, | |
d4906093 | 300 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
301 | }; |
302 | ||
303 | static const intel_limit_t intel_limits_i9xx_sdvo = { | |
79e53945 JB |
304 | .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX }, |
305 | .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX }, | |
306 | .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX }, | |
307 | .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX }, | |
308 | .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX }, | |
309 | .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX }, | |
310 | .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX }, | |
311 | .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX }, | |
312 | .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT, | |
313 | .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST }, | |
d4906093 | 314 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
315 | }; |
316 | ||
317 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
79e53945 JB |
318 | .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX }, |
319 | .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX }, | |
320 | .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX }, | |
321 | .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX }, | |
322 | .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX }, | |
323 | .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX }, | |
324 | .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX }, | |
325 | .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX }, | |
326 | /* The single-channel range is 25-112Mhz, and dual-channel | |
327 | * is 80-224Mhz. Prefer single channel as much as possible. | |
328 | */ | |
329 | .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT, | |
330 | .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST }, | |
d4906093 | 331 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
332 | }; |
333 | ||
044c7c41 | 334 | /* below parameter and function is for G4X Chipset Family*/ |
e4b36699 | 335 | static const intel_limit_t intel_limits_g4x_sdvo = { |
044c7c41 ML |
336 | .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX }, |
337 | .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX}, | |
338 | .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX }, | |
339 | .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX }, | |
340 | .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX }, | |
341 | .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX }, | |
342 | .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX }, | |
343 | .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX}, | |
344 | .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT, | |
345 | .p2_slow = G4X_P2_SDVO_SLOW, | |
346 | .p2_fast = G4X_P2_SDVO_FAST | |
347 | }, | |
d4906093 | 348 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
349 | }; |
350 | ||
351 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
044c7c41 ML |
352 | .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX }, |
353 | .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX}, | |
354 | .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX }, | |
355 | .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX }, | |
356 | .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX }, | |
357 | .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX }, | |
358 | .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX }, | |
359 | .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX}, | |
360 | .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT, | |
361 | .p2_slow = G4X_P2_HDMI_DAC_SLOW, | |
362 | .p2_fast = G4X_P2_HDMI_DAC_FAST | |
363 | }, | |
d4906093 | 364 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
365 | }; |
366 | ||
367 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
044c7c41 ML |
368 | .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN, |
369 | .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX }, | |
370 | .vco = { .min = G4X_VCO_MIN, | |
371 | .max = G4X_VCO_MAX }, | |
372 | .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN, | |
373 | .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX }, | |
374 | .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN, | |
375 | .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX }, | |
376 | .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN, | |
377 | .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX }, | |
378 | .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN, | |
379 | .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX }, | |
380 | .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN, | |
381 | .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX }, | |
382 | .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN, | |
383 | .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX }, | |
384 | .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT, | |
385 | .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW, | |
386 | .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST | |
387 | }, | |
d4906093 | 388 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
389 | }; |
390 | ||
391 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
044c7c41 ML |
392 | .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN, |
393 | .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX }, | |
394 | .vco = { .min = G4X_VCO_MIN, | |
395 | .max = G4X_VCO_MAX }, | |
396 | .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN, | |
397 | .max = G4X_N_DUAL_CHANNEL_LVDS_MAX }, | |
398 | .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN, | |
399 | .max = G4X_M_DUAL_CHANNEL_LVDS_MAX }, | |
400 | .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN, | |
401 | .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX }, | |
402 | .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN, | |
403 | .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX }, | |
404 | .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN, | |
405 | .max = G4X_P_DUAL_CHANNEL_LVDS_MAX }, | |
406 | .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN, | |
407 | .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX }, | |
408 | .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT, | |
409 | .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW, | |
410 | .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST | |
411 | }, | |
d4906093 | 412 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
413 | }; |
414 | ||
415 | static const intel_limit_t intel_limits_g4x_display_port = { | |
a4fc5ed6 KP |
416 | .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN, |
417 | .max = G4X_DOT_DISPLAY_PORT_MAX }, | |
418 | .vco = { .min = G4X_VCO_MIN, | |
419 | .max = G4X_VCO_MAX}, | |
420 | .n = { .min = G4X_N_DISPLAY_PORT_MIN, | |
421 | .max = G4X_N_DISPLAY_PORT_MAX }, | |
422 | .m = { .min = G4X_M_DISPLAY_PORT_MIN, | |
423 | .max = G4X_M_DISPLAY_PORT_MAX }, | |
424 | .m1 = { .min = G4X_M1_DISPLAY_PORT_MIN, | |
425 | .max = G4X_M1_DISPLAY_PORT_MAX }, | |
426 | .m2 = { .min = G4X_M2_DISPLAY_PORT_MIN, | |
427 | .max = G4X_M2_DISPLAY_PORT_MAX }, | |
428 | .p = { .min = G4X_P_DISPLAY_PORT_MIN, | |
429 | .max = G4X_P_DISPLAY_PORT_MAX }, | |
430 | .p1 = { .min = G4X_P1_DISPLAY_PORT_MIN, | |
431 | .max = G4X_P1_DISPLAY_PORT_MAX}, | |
432 | .p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT, | |
433 | .p2_slow = G4X_P2_DISPLAY_PORT_SLOW, | |
434 | .p2_fast = G4X_P2_DISPLAY_PORT_FAST }, | |
435 | .find_pll = intel_find_pll_g4x_dp, | |
e4b36699 KP |
436 | }; |
437 | ||
438 | static const intel_limit_t intel_limits_igd_sdvo = { | |
2177832f SL |
439 | .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX}, |
440 | .vco = { .min = IGD_VCO_MIN, .max = IGD_VCO_MAX }, | |
441 | .n = { .min = IGD_N_MIN, .max = IGD_N_MAX }, | |
442 | .m = { .min = IGD_M_MIN, .max = IGD_M_MAX }, | |
443 | .m1 = { .min = IGD_M1_MIN, .max = IGD_M1_MAX }, | |
444 | .m2 = { .min = IGD_M2_MIN, .max = IGD_M2_MAX }, | |
445 | .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX }, | |
446 | .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX }, | |
447 | .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT, | |
448 | .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST }, | |
6115707b | 449 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
450 | }; |
451 | ||
452 | static const intel_limit_t intel_limits_igd_lvds = { | |
2177832f SL |
453 | .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX }, |
454 | .vco = { .min = IGD_VCO_MIN, .max = IGD_VCO_MAX }, | |
455 | .n = { .min = IGD_N_MIN, .max = IGD_N_MAX }, | |
456 | .m = { .min = IGD_M_MIN, .max = IGD_M_MAX }, | |
457 | .m1 = { .min = IGD_M1_MIN, .max = IGD_M1_MAX }, | |
458 | .m2 = { .min = IGD_M2_MIN, .max = IGD_M2_MAX }, | |
459 | .p = { .min = IGD_P_LVDS_MIN, .max = IGD_P_LVDS_MAX }, | |
460 | .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX }, | |
461 | /* IGD only supports single-channel mode. */ | |
462 | .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT, | |
463 | .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW }, | |
6115707b | 464 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
465 | }; |
466 | ||
467 | static const intel_limit_t intel_limits_igdng_sdvo = { | |
2c07245f ZW |
468 | .dot = { .min = IGDNG_DOT_MIN, .max = IGDNG_DOT_MAX }, |
469 | .vco = { .min = IGDNG_VCO_MIN, .max = IGDNG_VCO_MAX }, | |
470 | .n = { .min = IGDNG_N_MIN, .max = IGDNG_N_MAX }, | |
471 | .m = { .min = IGDNG_M_MIN, .max = IGDNG_M_MAX }, | |
472 | .m1 = { .min = IGDNG_M1_MIN, .max = IGDNG_M1_MAX }, | |
473 | .m2 = { .min = IGDNG_M2_MIN, .max = IGDNG_M2_MAX }, | |
474 | .p = { .min = IGDNG_P_SDVO_DAC_MIN, .max = IGDNG_P_SDVO_DAC_MAX }, | |
475 | .p1 = { .min = IGDNG_P1_MIN, .max = IGDNG_P1_MAX }, | |
476 | .p2 = { .dot_limit = IGDNG_P2_DOT_LIMIT, | |
477 | .p2_slow = IGDNG_P2_SDVO_DAC_SLOW, | |
478 | .p2_fast = IGDNG_P2_SDVO_DAC_FAST }, | |
479 | .find_pll = intel_igdng_find_best_PLL, | |
e4b36699 KP |
480 | }; |
481 | ||
482 | static const intel_limit_t intel_limits_igdng_lvds = { | |
2c07245f ZW |
483 | .dot = { .min = IGDNG_DOT_MIN, .max = IGDNG_DOT_MAX }, |
484 | .vco = { .min = IGDNG_VCO_MIN, .max = IGDNG_VCO_MAX }, | |
485 | .n = { .min = IGDNG_N_MIN, .max = IGDNG_N_MAX }, | |
486 | .m = { .min = IGDNG_M_MIN, .max = IGDNG_M_MAX }, | |
487 | .m1 = { .min = IGDNG_M1_MIN, .max = IGDNG_M1_MAX }, | |
488 | .m2 = { .min = IGDNG_M2_MIN, .max = IGDNG_M2_MAX }, | |
489 | .p = { .min = IGDNG_P_LVDS_MIN, .max = IGDNG_P_LVDS_MAX }, | |
490 | .p1 = { .min = IGDNG_P1_MIN, .max = IGDNG_P1_MAX }, | |
491 | .p2 = { .dot_limit = IGDNG_P2_DOT_LIMIT, | |
492 | .p2_slow = IGDNG_P2_LVDS_SLOW, | |
493 | .p2_fast = IGDNG_P2_LVDS_FAST }, | |
494 | .find_pll = intel_igdng_find_best_PLL, | |
79e53945 JB |
495 | }; |
496 | ||
2c07245f ZW |
497 | static const intel_limit_t *intel_igdng_limit(struct drm_crtc *crtc) |
498 | { | |
499 | const intel_limit_t *limit; | |
500 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
e4b36699 | 501 | limit = &intel_limits_igdng_lvds; |
2c07245f | 502 | else |
e4b36699 | 503 | limit = &intel_limits_igdng_sdvo; |
2c07245f ZW |
504 | |
505 | return limit; | |
506 | } | |
507 | ||
044c7c41 ML |
508 | static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) |
509 | { | |
510 | struct drm_device *dev = crtc->dev; | |
511 | struct drm_i915_private *dev_priv = dev->dev_private; | |
512 | const intel_limit_t *limit; | |
513 | ||
514 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
515 | if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) == | |
516 | LVDS_CLKB_POWER_UP) | |
517 | /* LVDS with dual channel */ | |
e4b36699 | 518 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 ML |
519 | else |
520 | /* LVDS with dual channel */ | |
e4b36699 | 521 | limit = &intel_limits_g4x_single_channel_lvds; |
044c7c41 ML |
522 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || |
523 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 524 | limit = &intel_limits_g4x_hdmi; |
044c7c41 | 525 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 526 | limit = &intel_limits_g4x_sdvo; |
a4fc5ed6 | 527 | } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
e4b36699 | 528 | limit = &intel_limits_g4x_display_port; |
044c7c41 | 529 | } else /* The option is for other outputs */ |
e4b36699 | 530 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
531 | |
532 | return limit; | |
533 | } | |
534 | ||
79e53945 JB |
535 | static const intel_limit_t *intel_limit(struct drm_crtc *crtc) |
536 | { | |
537 | struct drm_device *dev = crtc->dev; | |
538 | const intel_limit_t *limit; | |
539 | ||
2c07245f ZW |
540 | if (IS_IGDNG(dev)) |
541 | limit = intel_igdng_limit(crtc); | |
542 | else if (IS_G4X(dev)) { | |
044c7c41 | 543 | limit = intel_g4x_limit(crtc); |
2177832f | 544 | } else if (IS_I9XX(dev) && !IS_IGD(dev)) { |
79e53945 | 545 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
e4b36699 | 546 | limit = &intel_limits_i9xx_lvds; |
79e53945 | 547 | else |
e4b36699 | 548 | limit = &intel_limits_i9xx_sdvo; |
2177832f SL |
549 | } else if (IS_IGD(dev)) { |
550 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
e4b36699 | 551 | limit = &intel_limits_igd_lvds; |
2177832f | 552 | else |
e4b36699 | 553 | limit = &intel_limits_igd_sdvo; |
79e53945 JB |
554 | } else { |
555 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
e4b36699 | 556 | limit = &intel_limits_i8xx_lvds; |
79e53945 | 557 | else |
e4b36699 | 558 | limit = &intel_limits_i8xx_dvo; |
79e53945 JB |
559 | } |
560 | return limit; | |
561 | } | |
562 | ||
2177832f SL |
563 | /* m1 is reserved as 0 in IGD, n is a ring counter */ |
564 | static void igd_clock(int refclk, intel_clock_t *clock) | |
79e53945 | 565 | { |
2177832f SL |
566 | clock->m = clock->m2 + 2; |
567 | clock->p = clock->p1 * clock->p2; | |
568 | clock->vco = refclk * clock->m / clock->n; | |
569 | clock->dot = clock->vco / clock->p; | |
570 | } | |
571 | ||
572 | static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock) | |
573 | { | |
574 | if (IS_IGD(dev)) { | |
575 | igd_clock(refclk, clock); | |
576 | return; | |
577 | } | |
79e53945 JB |
578 | clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); |
579 | clock->p = clock->p1 * clock->p2; | |
580 | clock->vco = refclk * clock->m / (clock->n + 2); | |
581 | clock->dot = clock->vco / clock->p; | |
582 | } | |
583 | ||
79e53945 JB |
584 | /** |
585 | * Returns whether any output on the specified pipe is of the specified type | |
586 | */ | |
587 | bool intel_pipe_has_type (struct drm_crtc *crtc, int type) | |
588 | { | |
589 | struct drm_device *dev = crtc->dev; | |
590 | struct drm_mode_config *mode_config = &dev->mode_config; | |
591 | struct drm_connector *l_entry; | |
592 | ||
593 | list_for_each_entry(l_entry, &mode_config->connector_list, head) { | |
594 | if (l_entry->encoder && | |
595 | l_entry->encoder->crtc == crtc) { | |
596 | struct intel_output *intel_output = to_intel_output(l_entry); | |
597 | if (intel_output->type == type) | |
598 | return true; | |
599 | } | |
600 | } | |
601 | return false; | |
602 | } | |
603 | ||
7c04d1d9 | 604 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
605 | /** |
606 | * Returns whether the given set of divisors are valid for a given refclk with | |
607 | * the given connectors. | |
608 | */ | |
609 | ||
610 | static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock) | |
611 | { | |
612 | const intel_limit_t *limit = intel_limit (crtc); | |
2177832f | 613 | struct drm_device *dev = crtc->dev; |
79e53945 JB |
614 | |
615 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) | |
616 | INTELPllInvalid ("p1 out of range\n"); | |
617 | if (clock->p < limit->p.min || limit->p.max < clock->p) | |
618 | INTELPllInvalid ("p out of range\n"); | |
619 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) | |
620 | INTELPllInvalid ("m2 out of range\n"); | |
621 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) | |
622 | INTELPllInvalid ("m1 out of range\n"); | |
2177832f | 623 | if (clock->m1 <= clock->m2 && !IS_IGD(dev)) |
79e53945 JB |
624 | INTELPllInvalid ("m1 <= m2\n"); |
625 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
626 | INTELPllInvalid ("m out of range\n"); | |
627 | if (clock->n < limit->n.min || limit->n.max < clock->n) | |
628 | INTELPllInvalid ("n out of range\n"); | |
629 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) | |
630 | INTELPllInvalid ("vco out of range\n"); | |
631 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, | |
632 | * connector, etc., rather than just a single range. | |
633 | */ | |
634 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
635 | INTELPllInvalid ("dot out of range\n"); | |
636 | ||
637 | return true; | |
638 | } | |
639 | ||
d4906093 ML |
640 | static bool |
641 | intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
642 | int target, int refclk, intel_clock_t *best_clock) | |
643 | ||
79e53945 JB |
644 | { |
645 | struct drm_device *dev = crtc->dev; | |
646 | struct drm_i915_private *dev_priv = dev->dev_private; | |
647 | intel_clock_t clock; | |
79e53945 JB |
648 | int err = target; |
649 | ||
650 | if (IS_I9XX(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && | |
832cc28d | 651 | (I915_READ(LVDS)) != 0) { |
79e53945 JB |
652 | /* |
653 | * For LVDS, if the panel is on, just rely on its current | |
654 | * settings for dual-channel. We haven't figured out how to | |
655 | * reliably set up different single/dual channel state, if we | |
656 | * even can. | |
657 | */ | |
658 | if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) == | |
659 | LVDS_CLKB_POWER_UP) | |
660 | clock.p2 = limit->p2.p2_fast; | |
661 | else | |
662 | clock.p2 = limit->p2.p2_slow; | |
663 | } else { | |
664 | if (target < limit->p2.dot_limit) | |
665 | clock.p2 = limit->p2.p2_slow; | |
666 | else | |
667 | clock.p2 = limit->p2.p2_fast; | |
668 | } | |
669 | ||
670 | memset (best_clock, 0, sizeof (*best_clock)); | |
671 | ||
672 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { | |
2177832f SL |
673 | for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max; clock.m2++) { |
674 | /* m1 is always 0 in IGD */ | |
675 | if (clock.m2 >= clock.m1 && !IS_IGD(dev)) | |
676 | break; | |
79e53945 JB |
677 | for (clock.n = limit->n.min; clock.n <= limit->n.max; |
678 | clock.n++) { | |
679 | for (clock.p1 = limit->p1.min; | |
680 | clock.p1 <= limit->p1.max; clock.p1++) { | |
681 | int this_err; | |
682 | ||
2177832f | 683 | intel_clock(dev, refclk, &clock); |
79e53945 JB |
684 | |
685 | if (!intel_PLL_is_valid(crtc, &clock)) | |
686 | continue; | |
687 | ||
688 | this_err = abs(clock.dot - target); | |
689 | if (this_err < err) { | |
690 | *best_clock = clock; | |
691 | err = this_err; | |
692 | } | |
693 | } | |
694 | } | |
695 | } | |
696 | } | |
697 | ||
698 | return (err != target); | |
699 | } | |
700 | ||
d4906093 ML |
701 | static bool |
702 | intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
703 | int target, int refclk, intel_clock_t *best_clock) | |
704 | { | |
705 | struct drm_device *dev = crtc->dev; | |
706 | struct drm_i915_private *dev_priv = dev->dev_private; | |
707 | intel_clock_t clock; | |
708 | int max_n; | |
709 | bool found; | |
710 | /* approximately equals target * 0.00488 */ | |
711 | int err_most = (target >> 8) + (target >> 10); | |
712 | found = false; | |
713 | ||
714 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
715 | if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) == | |
716 | LVDS_CLKB_POWER_UP) | |
717 | clock.p2 = limit->p2.p2_fast; | |
718 | else | |
719 | clock.p2 = limit->p2.p2_slow; | |
720 | } else { | |
721 | if (target < limit->p2.dot_limit) | |
722 | clock.p2 = limit->p2.p2_slow; | |
723 | else | |
724 | clock.p2 = limit->p2.p2_fast; | |
725 | } | |
726 | ||
727 | memset(best_clock, 0, sizeof(*best_clock)); | |
728 | max_n = limit->n.max; | |
729 | /* based on hardware requriment prefer smaller n to precision */ | |
730 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { | |
731 | /* based on hardware requirment prefere larger m1,m2, p1 */ | |
732 | for (clock.m1 = limit->m1.max; | |
733 | clock.m1 >= limit->m1.min; clock.m1--) { | |
734 | for (clock.m2 = limit->m2.max; | |
735 | clock.m2 >= limit->m2.min; clock.m2--) { | |
736 | for (clock.p1 = limit->p1.max; | |
737 | clock.p1 >= limit->p1.min; clock.p1--) { | |
738 | int this_err; | |
739 | ||
2177832f | 740 | intel_clock(dev, refclk, &clock); |
d4906093 ML |
741 | if (!intel_PLL_is_valid(crtc, &clock)) |
742 | continue; | |
743 | this_err = abs(clock.dot - target) ; | |
744 | if (this_err < err_most) { | |
745 | *best_clock = clock; | |
746 | err_most = this_err; | |
747 | max_n = clock.n; | |
748 | found = true; | |
749 | } | |
750 | } | |
751 | } | |
752 | } | |
753 | } | |
2c07245f ZW |
754 | return found; |
755 | } | |
756 | ||
5eb08b69 ZW |
757 | static bool |
758 | intel_find_pll_igdng_dp(const intel_limit_t *limit, struct drm_crtc *crtc, | |
759 | int target, int refclk, intel_clock_t *best_clock) | |
760 | { | |
761 | struct drm_device *dev = crtc->dev; | |
762 | intel_clock_t clock; | |
763 | if (target < 200000) { | |
764 | clock.n = 1; | |
765 | clock.p1 = 2; | |
766 | clock.p2 = 10; | |
767 | clock.m1 = 12; | |
768 | clock.m2 = 9; | |
769 | } else { | |
770 | clock.n = 2; | |
771 | clock.p1 = 1; | |
772 | clock.p2 = 10; | |
773 | clock.m1 = 14; | |
774 | clock.m2 = 8; | |
775 | } | |
776 | intel_clock(dev, refclk, &clock); | |
777 | memcpy(best_clock, &clock, sizeof(intel_clock_t)); | |
778 | return true; | |
779 | } | |
780 | ||
2c07245f ZW |
781 | static bool |
782 | intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
783 | int target, int refclk, intel_clock_t *best_clock) | |
784 | { | |
785 | struct drm_device *dev = crtc->dev; | |
786 | struct drm_i915_private *dev_priv = dev->dev_private; | |
787 | intel_clock_t clock; | |
788 | int max_n; | |
789 | bool found; | |
790 | int err_most = 47; | |
791 | found = false; | |
792 | ||
5eb08b69 ZW |
793 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) |
794 | return intel_find_pll_igdng_dp(limit, crtc, target, | |
795 | refclk, best_clock); | |
796 | ||
2c07245f ZW |
797 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
798 | if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) == | |
799 | LVDS_CLKB_POWER_UP) | |
800 | clock.p2 = limit->p2.p2_fast; | |
801 | else | |
802 | clock.p2 = limit->p2.p2_slow; | |
803 | } else { | |
804 | if (target < limit->p2.dot_limit) | |
805 | clock.p2 = limit->p2.p2_slow; | |
806 | else | |
807 | clock.p2 = limit->p2.p2_fast; | |
808 | } | |
809 | ||
810 | memset(best_clock, 0, sizeof(*best_clock)); | |
811 | max_n = limit->n.max; | |
812 | /* based on hardware requriment prefer smaller n to precision */ | |
813 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { | |
814 | /* based on hardware requirment prefere larger m1,m2, p1 */ | |
815 | for (clock.m1 = limit->m1.max; | |
816 | clock.m1 >= limit->m1.min; clock.m1--) { | |
817 | for (clock.m2 = limit->m2.max; | |
818 | clock.m2 >= limit->m2.min; clock.m2--) { | |
819 | for (clock.p1 = limit->p1.max; | |
820 | clock.p1 >= limit->p1.min; clock.p1--) { | |
821 | int this_err; | |
d4906093 | 822 | |
2c07245f ZW |
823 | intel_clock(dev, refclk, &clock); |
824 | if (!intel_PLL_is_valid(crtc, &clock)) | |
825 | continue; | |
826 | this_err = abs((10000 - (target*10000/clock.dot))); | |
827 | if (this_err < err_most) { | |
828 | *best_clock = clock; | |
829 | err_most = this_err; | |
830 | max_n = clock.n; | |
831 | found = true; | |
832 | /* found on first matching */ | |
833 | goto out; | |
834 | } | |
835 | } | |
836 | } | |
837 | } | |
838 | } | |
839 | out: | |
d4906093 ML |
840 | return found; |
841 | } | |
842 | ||
a4fc5ed6 KP |
843 | /* DisplayPort has only two frequencies, 162MHz and 270MHz */ |
844 | static bool | |
845 | intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc, | |
846 | int target, int refclk, intel_clock_t *best_clock) | |
847 | { | |
848 | intel_clock_t clock; | |
849 | if (target < 200000) { | |
a4fc5ed6 KP |
850 | clock.p1 = 2; |
851 | clock.p2 = 10; | |
b3d25495 KP |
852 | clock.n = 2; |
853 | clock.m1 = 23; | |
854 | clock.m2 = 8; | |
a4fc5ed6 | 855 | } else { |
a4fc5ed6 KP |
856 | clock.p1 = 1; |
857 | clock.p2 = 10; | |
b3d25495 KP |
858 | clock.n = 1; |
859 | clock.m1 = 14; | |
860 | clock.m2 = 2; | |
a4fc5ed6 | 861 | } |
b3d25495 KP |
862 | clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2); |
863 | clock.p = (clock.p1 * clock.p2); | |
864 | clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p; | |
a4fc5ed6 KP |
865 | memcpy(best_clock, &clock, sizeof(intel_clock_t)); |
866 | return true; | |
867 | } | |
868 | ||
79e53945 JB |
869 | void |
870 | intel_wait_for_vblank(struct drm_device *dev) | |
871 | { | |
872 | /* Wait for 20ms, i.e. one cycle at 50hz. */ | |
580982d3 | 873 | mdelay(20); |
79e53945 JB |
874 | } |
875 | ||
5c3b82e2 | 876 | static int |
3c4fdcfb KH |
877 | intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
878 | struct drm_framebuffer *old_fb) | |
79e53945 JB |
879 | { |
880 | struct drm_device *dev = crtc->dev; | |
881 | struct drm_i915_private *dev_priv = dev->dev_private; | |
882 | struct drm_i915_master_private *master_priv; | |
883 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
884 | struct intel_framebuffer *intel_fb; | |
885 | struct drm_i915_gem_object *obj_priv; | |
886 | struct drm_gem_object *obj; | |
887 | int pipe = intel_crtc->pipe; | |
888 | unsigned long Start, Offset; | |
889 | int dspbase = (pipe == 0 ? DSPAADDR : DSPBADDR); | |
890 | int dspsurf = (pipe == 0 ? DSPASURF : DSPBSURF); | |
891 | int dspstride = (pipe == 0) ? DSPASTRIDE : DSPBSTRIDE; | |
f544847f | 892 | int dsptileoff = (pipe == 0 ? DSPATILEOFF : DSPBTILEOFF); |
79e53945 | 893 | int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR; |
3c4fdcfb | 894 | u32 dspcntr, alignment; |
5c3b82e2 | 895 | int ret; |
79e53945 JB |
896 | |
897 | /* no fb bound */ | |
898 | if (!crtc->fb) { | |
899 | DRM_DEBUG("No FB bound\n"); | |
5c3b82e2 CW |
900 | return 0; |
901 | } | |
902 | ||
903 | switch (pipe) { | |
904 | case 0: | |
905 | case 1: | |
906 | break; | |
907 | default: | |
908 | DRM_ERROR("Can't update pipe %d in SAREA\n", pipe); | |
909 | return -EINVAL; | |
79e53945 JB |
910 | } |
911 | ||
912 | intel_fb = to_intel_framebuffer(crtc->fb); | |
79e53945 JB |
913 | obj = intel_fb->obj; |
914 | obj_priv = obj->driver_private; | |
915 | ||
3c4fdcfb KH |
916 | switch (obj_priv->tiling_mode) { |
917 | case I915_TILING_NONE: | |
918 | alignment = 64 * 1024; | |
919 | break; | |
920 | case I915_TILING_X: | |
2ebed176 CW |
921 | /* pin() will align the object as required by fence */ |
922 | alignment = 0; | |
3c4fdcfb KH |
923 | break; |
924 | case I915_TILING_Y: | |
925 | /* FIXME: Is this true? */ | |
926 | DRM_ERROR("Y tiled not allowed for scan out buffers\n"); | |
5c3b82e2 | 927 | return -EINVAL; |
3c4fdcfb KH |
928 | default: |
929 | BUG(); | |
930 | } | |
931 | ||
5c3b82e2 | 932 | mutex_lock(&dev->struct_mutex); |
8c4b8c3f | 933 | ret = i915_gem_object_pin(obj, alignment); |
5c3b82e2 CW |
934 | if (ret != 0) { |
935 | mutex_unlock(&dev->struct_mutex); | |
936 | return ret; | |
937 | } | |
79e53945 | 938 | |
8c4b8c3f | 939 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
5c3b82e2 | 940 | if (ret != 0) { |
8c4b8c3f | 941 | i915_gem_object_unpin(obj); |
5c3b82e2 CW |
942 | mutex_unlock(&dev->struct_mutex); |
943 | return ret; | |
944 | } | |
79e53945 | 945 | |
8c4b8c3f CW |
946 | /* Pre-i965 needs to install a fence for tiled scan-out */ |
947 | if (!IS_I965G(dev) && | |
948 | obj_priv->fence_reg == I915_FENCE_REG_NONE && | |
949 | obj_priv->tiling_mode != I915_TILING_NONE) { | |
950 | ret = i915_gem_object_get_fence_reg(obj); | |
951 | if (ret != 0) { | |
952 | i915_gem_object_unpin(obj); | |
953 | mutex_unlock(&dev->struct_mutex); | |
954 | return ret; | |
955 | } | |
956 | } | |
957 | ||
79e53945 | 958 | dspcntr = I915_READ(dspcntr_reg); |
712531bf JB |
959 | /* Mask out pixel format bits in case we change it */ |
960 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
79e53945 JB |
961 | switch (crtc->fb->bits_per_pixel) { |
962 | case 8: | |
963 | dspcntr |= DISPPLANE_8BPP; | |
964 | break; | |
965 | case 16: | |
966 | if (crtc->fb->depth == 15) | |
967 | dspcntr |= DISPPLANE_15_16BPP; | |
968 | else | |
969 | dspcntr |= DISPPLANE_16BPP; | |
970 | break; | |
971 | case 24: | |
972 | case 32: | |
973 | dspcntr |= DISPPLANE_32BPP_NO_ALPHA; | |
974 | break; | |
975 | default: | |
976 | DRM_ERROR("Unknown color depth\n"); | |
8c4b8c3f | 977 | i915_gem_object_unpin(obj); |
5c3b82e2 CW |
978 | mutex_unlock(&dev->struct_mutex); |
979 | return -EINVAL; | |
79e53945 | 980 | } |
f544847f JB |
981 | if (IS_I965G(dev)) { |
982 | if (obj_priv->tiling_mode != I915_TILING_NONE) | |
983 | dspcntr |= DISPPLANE_TILED; | |
984 | else | |
985 | dspcntr &= ~DISPPLANE_TILED; | |
986 | } | |
987 | ||
79e53945 JB |
988 | I915_WRITE(dspcntr_reg, dspcntr); |
989 | ||
5c3b82e2 CW |
990 | Start = obj_priv->gtt_offset; |
991 | Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8); | |
992 | ||
79e53945 | 993 | DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y); |
5c3b82e2 | 994 | I915_WRITE(dspstride, crtc->fb->pitch); |
79e53945 JB |
995 | if (IS_I965G(dev)) { |
996 | I915_WRITE(dspbase, Offset); | |
997 | I915_READ(dspbase); | |
998 | I915_WRITE(dspsurf, Start); | |
999 | I915_READ(dspsurf); | |
f544847f | 1000 | I915_WRITE(dsptileoff, (y << 16) | x); |
79e53945 JB |
1001 | } else { |
1002 | I915_WRITE(dspbase, Start + Offset); | |
1003 | I915_READ(dspbase); | |
1004 | } | |
1005 | ||
3c4fdcfb KH |
1006 | intel_wait_for_vblank(dev); |
1007 | ||
1008 | if (old_fb) { | |
1009 | intel_fb = to_intel_framebuffer(old_fb); | |
1010 | i915_gem_object_unpin(intel_fb->obj); | |
1011 | } | |
5c3b82e2 | 1012 | mutex_unlock(&dev->struct_mutex); |
79e53945 JB |
1013 | |
1014 | if (!dev->primary->master) | |
5c3b82e2 | 1015 | return 0; |
79e53945 JB |
1016 | |
1017 | master_priv = dev->primary->master->driver_priv; | |
1018 | if (!master_priv->sarea_priv) | |
5c3b82e2 | 1019 | return 0; |
79e53945 | 1020 | |
5c3b82e2 | 1021 | if (pipe) { |
79e53945 JB |
1022 | master_priv->sarea_priv->pipeB_x = x; |
1023 | master_priv->sarea_priv->pipeB_y = y; | |
5c3b82e2 CW |
1024 | } else { |
1025 | master_priv->sarea_priv->pipeA_x = x; | |
1026 | master_priv->sarea_priv->pipeA_y = y; | |
79e53945 | 1027 | } |
5c3b82e2 CW |
1028 | |
1029 | return 0; | |
79e53945 JB |
1030 | } |
1031 | ||
24f119c7 ZW |
1032 | /* Disable the VGA plane that we never use */ |
1033 | static void i915_disable_vga (struct drm_device *dev) | |
1034 | { | |
1035 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1036 | u8 sr1; | |
1037 | u32 vga_reg; | |
1038 | ||
1039 | if (IS_IGDNG(dev)) | |
1040 | vga_reg = CPU_VGACNTRL; | |
1041 | else | |
1042 | vga_reg = VGACNTRL; | |
1043 | ||
1044 | if (I915_READ(vga_reg) & VGA_DISP_DISABLE) | |
1045 | return; | |
1046 | ||
1047 | I915_WRITE8(VGA_SR_INDEX, 1); | |
1048 | sr1 = I915_READ8(VGA_SR_DATA); | |
1049 | I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5)); | |
1050 | udelay(100); | |
1051 | ||
1052 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); | |
1053 | } | |
1054 | ||
2c07245f ZW |
1055 | static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode) |
1056 | { | |
1057 | struct drm_device *dev = crtc->dev; | |
1058 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1059 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1060 | int pipe = intel_crtc->pipe; | |
7662c8bd | 1061 | int plane = intel_crtc->plane; |
2c07245f ZW |
1062 | int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B; |
1063 | int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF; | |
1064 | int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR; | |
1065 | int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR; | |
1066 | int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL; | |
1067 | int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL; | |
1068 | int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR; | |
1069 | int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR; | |
1070 | int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF; | |
1071 | int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1; | |
249c0e64 | 1072 | int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ; |
2c07245f ZW |
1073 | int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B; |
1074 | int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B; | |
1075 | int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B; | |
1076 | int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B; | |
1077 | int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B; | |
1078 | int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B; | |
1079 | int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B; | |
1080 | int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B; | |
1081 | int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B; | |
1082 | int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B; | |
1083 | int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B; | |
1084 | int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B; | |
1085 | u32 temp; | |
249c0e64 | 1086 | int tries = 5, j, n; |
79e53945 | 1087 | |
2c07245f ZW |
1088 | /* XXX: When our outputs are all unaware of DPMS modes other than off |
1089 | * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. | |
1090 | */ | |
1091 | switch (mode) { | |
1092 | case DRM_MODE_DPMS_ON: | |
1093 | case DRM_MODE_DPMS_STANDBY: | |
1094 | case DRM_MODE_DPMS_SUSPEND: | |
1095 | DRM_DEBUG("crtc %d dpms on\n", pipe); | |
1096 | /* enable PCH DPLL */ | |
1097 | temp = I915_READ(pch_dpll_reg); | |
1098 | if ((temp & DPLL_VCO_ENABLE) == 0) { | |
1099 | I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE); | |
1100 | I915_READ(pch_dpll_reg); | |
1101 | } | |
79e53945 | 1102 | |
2c07245f ZW |
1103 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
1104 | temp = I915_READ(fdi_rx_reg); | |
1105 | I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE | | |
1106 | FDI_SEL_PCDCLK | | |
1107 | FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */ | |
1108 | I915_READ(fdi_rx_reg); | |
1109 | udelay(200); | |
1110 | ||
1111 | /* Enable CPU FDI TX PLL, always on for IGDNG */ | |
1112 | temp = I915_READ(fdi_tx_reg); | |
1113 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
1114 | I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE); | |
1115 | I915_READ(fdi_tx_reg); | |
1116 | udelay(100); | |
1117 | } | |
1118 | ||
1119 | /* Enable CPU pipe */ | |
1120 | temp = I915_READ(pipeconf_reg); | |
1121 | if ((temp & PIPEACONF_ENABLE) == 0) { | |
1122 | I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE); | |
1123 | I915_READ(pipeconf_reg); | |
1124 | udelay(100); | |
1125 | } | |
1126 | ||
1127 | /* configure and enable CPU plane */ | |
1128 | temp = I915_READ(dspcntr_reg); | |
1129 | if ((temp & DISPLAY_PLANE_ENABLE) == 0) { | |
1130 | I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE); | |
1131 | /* Flush the plane changes */ | |
1132 | I915_WRITE(dspbase_reg, I915_READ(dspbase_reg)); | |
1133 | } | |
1134 | ||
1135 | /* enable CPU FDI TX and PCH FDI RX */ | |
1136 | temp = I915_READ(fdi_tx_reg); | |
1137 | temp |= FDI_TX_ENABLE; | |
1138 | temp |= FDI_DP_PORT_WIDTH_X4; /* default */ | |
1139 | temp &= ~FDI_LINK_TRAIN_NONE; | |
1140 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
1141 | I915_WRITE(fdi_tx_reg, temp); | |
1142 | I915_READ(fdi_tx_reg); | |
1143 | ||
1144 | temp = I915_READ(fdi_rx_reg); | |
1145 | temp &= ~FDI_LINK_TRAIN_NONE; | |
1146 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
1147 | I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE); | |
1148 | I915_READ(fdi_rx_reg); | |
1149 | ||
1150 | udelay(150); | |
1151 | ||
1152 | /* Train FDI. */ | |
1153 | /* umask FDI RX Interrupt symbol_lock and bit_lock bit | |
1154 | for train result */ | |
1155 | temp = I915_READ(fdi_rx_imr_reg); | |
1156 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
1157 | temp &= ~FDI_RX_BIT_LOCK; | |
1158 | I915_WRITE(fdi_rx_imr_reg, temp); | |
1159 | I915_READ(fdi_rx_imr_reg); | |
1160 | udelay(150); | |
1161 | ||
1162 | temp = I915_READ(fdi_rx_iir_reg); | |
1163 | DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp); | |
1164 | ||
1165 | if ((temp & FDI_RX_BIT_LOCK) == 0) { | |
1166 | for (j = 0; j < tries; j++) { | |
1167 | temp = I915_READ(fdi_rx_iir_reg); | |
1168 | DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp); | |
1169 | if (temp & FDI_RX_BIT_LOCK) | |
1170 | break; | |
1171 | udelay(200); | |
1172 | } | |
1173 | if (j != tries) | |
1174 | I915_WRITE(fdi_rx_iir_reg, | |
1175 | temp | FDI_RX_BIT_LOCK); | |
1176 | else | |
1177 | DRM_DEBUG("train 1 fail\n"); | |
1178 | } else { | |
1179 | I915_WRITE(fdi_rx_iir_reg, | |
1180 | temp | FDI_RX_BIT_LOCK); | |
1181 | DRM_DEBUG("train 1 ok 2!\n"); | |
1182 | } | |
1183 | temp = I915_READ(fdi_tx_reg); | |
1184 | temp &= ~FDI_LINK_TRAIN_NONE; | |
1185 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
1186 | I915_WRITE(fdi_tx_reg, temp); | |
1187 | ||
1188 | temp = I915_READ(fdi_rx_reg); | |
1189 | temp &= ~FDI_LINK_TRAIN_NONE; | |
1190 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
1191 | I915_WRITE(fdi_rx_reg, temp); | |
1192 | ||
1193 | udelay(150); | |
1194 | ||
1195 | temp = I915_READ(fdi_rx_iir_reg); | |
1196 | DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp); | |
1197 | ||
1198 | if ((temp & FDI_RX_SYMBOL_LOCK) == 0) { | |
1199 | for (j = 0; j < tries; j++) { | |
1200 | temp = I915_READ(fdi_rx_iir_reg); | |
1201 | DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp); | |
1202 | if (temp & FDI_RX_SYMBOL_LOCK) | |
1203 | break; | |
1204 | udelay(200); | |
1205 | } | |
1206 | if (j != tries) { | |
1207 | I915_WRITE(fdi_rx_iir_reg, | |
1208 | temp | FDI_RX_SYMBOL_LOCK); | |
1209 | DRM_DEBUG("train 2 ok 1!\n"); | |
1210 | } else | |
1211 | DRM_DEBUG("train 2 fail\n"); | |
1212 | } else { | |
1213 | I915_WRITE(fdi_rx_iir_reg, temp | FDI_RX_SYMBOL_LOCK); | |
1214 | DRM_DEBUG("train 2 ok 2!\n"); | |
1215 | } | |
1216 | DRM_DEBUG("train done\n"); | |
1217 | ||
1218 | /* set transcoder timing */ | |
1219 | I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg)); | |
1220 | I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg)); | |
1221 | I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg)); | |
1222 | ||
1223 | I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg)); | |
1224 | I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg)); | |
1225 | I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg)); | |
1226 | ||
1227 | /* enable PCH transcoder */ | |
1228 | temp = I915_READ(transconf_reg); | |
1229 | I915_WRITE(transconf_reg, temp | TRANS_ENABLE); | |
1230 | I915_READ(transconf_reg); | |
1231 | ||
1232 | while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0) | |
1233 | ; | |
1234 | ||
1235 | /* enable normal */ | |
1236 | ||
1237 | temp = I915_READ(fdi_tx_reg); | |
1238 | temp &= ~FDI_LINK_TRAIN_NONE; | |
1239 | I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE | | |
1240 | FDI_TX_ENHANCE_FRAME_ENABLE); | |
1241 | I915_READ(fdi_tx_reg); | |
1242 | ||
1243 | temp = I915_READ(fdi_rx_reg); | |
1244 | temp &= ~FDI_LINK_TRAIN_NONE; | |
1245 | I915_WRITE(fdi_rx_reg, temp | FDI_LINK_TRAIN_NONE | | |
1246 | FDI_RX_ENHANCE_FRAME_ENABLE); | |
1247 | I915_READ(fdi_rx_reg); | |
1248 | ||
1249 | /* wait one idle pattern time */ | |
1250 | udelay(100); | |
1251 | ||
1252 | intel_crtc_load_lut(crtc); | |
1253 | ||
1254 | break; | |
1255 | case DRM_MODE_DPMS_OFF: | |
1256 | DRM_DEBUG("crtc %d dpms off\n", pipe); | |
1257 | ||
24f119c7 | 1258 | i915_disable_vga(dev); |
2c07245f ZW |
1259 | |
1260 | /* Disable display plane */ | |
1261 | temp = I915_READ(dspcntr_reg); | |
1262 | if ((temp & DISPLAY_PLANE_ENABLE) != 0) { | |
1263 | I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE); | |
1264 | /* Flush the plane changes */ | |
1265 | I915_WRITE(dspbase_reg, I915_READ(dspbase_reg)); | |
1266 | I915_READ(dspbase_reg); | |
1267 | } | |
1268 | ||
1269 | /* disable cpu pipe, disable after all planes disabled */ | |
1270 | temp = I915_READ(pipeconf_reg); | |
1271 | if ((temp & PIPEACONF_ENABLE) != 0) { | |
1272 | I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE); | |
1273 | I915_READ(pipeconf_reg); | |
249c0e64 | 1274 | n = 0; |
2c07245f | 1275 | /* wait for cpu pipe off, pipe state */ |
249c0e64 ZW |
1276 | while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) { |
1277 | n++; | |
1278 | if (n < 60) { | |
1279 | udelay(500); | |
1280 | continue; | |
1281 | } else { | |
1282 | DRM_DEBUG("pipe %d off delay\n", pipe); | |
1283 | break; | |
1284 | } | |
1285 | } | |
2c07245f ZW |
1286 | } else |
1287 | DRM_DEBUG("crtc %d is disabled\n", pipe); | |
1288 | ||
2c07245f ZW |
1289 | /* disable CPU FDI tx and PCH FDI rx */ |
1290 | temp = I915_READ(fdi_tx_reg); | |
1291 | I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE); | |
1292 | I915_READ(fdi_tx_reg); | |
1293 | ||
1294 | temp = I915_READ(fdi_rx_reg); | |
1295 | I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE); | |
1296 | I915_READ(fdi_rx_reg); | |
1297 | ||
249c0e64 ZW |
1298 | udelay(100); |
1299 | ||
2c07245f ZW |
1300 | /* still set train pattern 1 */ |
1301 | temp = I915_READ(fdi_tx_reg); | |
1302 | temp &= ~FDI_LINK_TRAIN_NONE; | |
1303 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
1304 | I915_WRITE(fdi_tx_reg, temp); | |
1305 | ||
1306 | temp = I915_READ(fdi_rx_reg); | |
1307 | temp &= ~FDI_LINK_TRAIN_NONE; | |
1308 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
1309 | I915_WRITE(fdi_rx_reg, temp); | |
1310 | ||
249c0e64 ZW |
1311 | udelay(100); |
1312 | ||
2c07245f ZW |
1313 | /* disable PCH transcoder */ |
1314 | temp = I915_READ(transconf_reg); | |
1315 | if ((temp & TRANS_ENABLE) != 0) { | |
1316 | I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE); | |
1317 | I915_READ(transconf_reg); | |
249c0e64 | 1318 | n = 0; |
2c07245f | 1319 | /* wait for PCH transcoder off, transcoder state */ |
249c0e64 ZW |
1320 | while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) { |
1321 | n++; | |
1322 | if (n < 60) { | |
1323 | udelay(500); | |
1324 | continue; | |
1325 | } else { | |
1326 | DRM_DEBUG("transcoder %d off delay\n", pipe); | |
1327 | break; | |
1328 | } | |
1329 | } | |
2c07245f ZW |
1330 | } |
1331 | ||
1332 | /* disable PCH DPLL */ | |
1333 | temp = I915_READ(pch_dpll_reg); | |
1334 | if ((temp & DPLL_VCO_ENABLE) != 0) { | |
1335 | I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE); | |
1336 | I915_READ(pch_dpll_reg); | |
1337 | } | |
1338 | ||
1339 | temp = I915_READ(fdi_rx_reg); | |
1340 | if ((temp & FDI_RX_PLL_ENABLE) != 0) { | |
1341 | temp &= ~FDI_SEL_PCDCLK; | |
1342 | temp &= ~FDI_RX_PLL_ENABLE; | |
1343 | I915_WRITE(fdi_rx_reg, temp); | |
1344 | I915_READ(fdi_rx_reg); | |
1345 | } | |
1346 | ||
249c0e64 ZW |
1347 | /* Disable CPU FDI TX PLL */ |
1348 | temp = I915_READ(fdi_tx_reg); | |
1349 | if ((temp & FDI_TX_PLL_ENABLE) != 0) { | |
1350 | I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE); | |
1351 | I915_READ(fdi_tx_reg); | |
1352 | udelay(100); | |
1353 | } | |
1354 | ||
1355 | /* Disable PF */ | |
1356 | temp = I915_READ(pf_ctl_reg); | |
1357 | if ((temp & PF_ENABLE) != 0) { | |
1358 | I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE); | |
1359 | I915_READ(pf_ctl_reg); | |
1360 | } | |
1361 | I915_WRITE(pf_win_size, 0); | |
1362 | ||
2c07245f ZW |
1363 | /* Wait for the clocks to turn off. */ |
1364 | udelay(150); | |
1365 | break; | |
1366 | } | |
1367 | } | |
1368 | ||
1369 | static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode) | |
79e53945 JB |
1370 | { |
1371 | struct drm_device *dev = crtc->dev; | |
79e53945 JB |
1372 | struct drm_i915_private *dev_priv = dev->dev_private; |
1373 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1374 | int pipe = intel_crtc->pipe; | |
1375 | int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; | |
1376 | int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR; | |
1377 | int dspbase_reg = (pipe == 0) ? DSPAADDR : DSPBADDR; | |
1378 | int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF; | |
1379 | u32 temp; | |
79e53945 JB |
1380 | |
1381 | /* XXX: When our outputs are all unaware of DPMS modes other than off | |
1382 | * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. | |
1383 | */ | |
1384 | switch (mode) { | |
1385 | case DRM_MODE_DPMS_ON: | |
1386 | case DRM_MODE_DPMS_STANDBY: | |
1387 | case DRM_MODE_DPMS_SUSPEND: | |
1388 | /* Enable the DPLL */ | |
1389 | temp = I915_READ(dpll_reg); | |
1390 | if ((temp & DPLL_VCO_ENABLE) == 0) { | |
1391 | I915_WRITE(dpll_reg, temp); | |
1392 | I915_READ(dpll_reg); | |
1393 | /* Wait for the clocks to stabilize. */ | |
1394 | udelay(150); | |
1395 | I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE); | |
1396 | I915_READ(dpll_reg); | |
1397 | /* Wait for the clocks to stabilize. */ | |
1398 | udelay(150); | |
1399 | I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE); | |
1400 | I915_READ(dpll_reg); | |
1401 | /* Wait for the clocks to stabilize. */ | |
1402 | udelay(150); | |
1403 | } | |
1404 | ||
1405 | /* Enable the pipe */ | |
1406 | temp = I915_READ(pipeconf_reg); | |
1407 | if ((temp & PIPEACONF_ENABLE) == 0) | |
1408 | I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE); | |
1409 | ||
1410 | /* Enable the plane */ | |
1411 | temp = I915_READ(dspcntr_reg); | |
1412 | if ((temp & DISPLAY_PLANE_ENABLE) == 0) { | |
1413 | I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE); | |
1414 | /* Flush the plane changes */ | |
1415 | I915_WRITE(dspbase_reg, I915_READ(dspbase_reg)); | |
1416 | } | |
1417 | ||
1418 | intel_crtc_load_lut(crtc); | |
1419 | ||
1420 | /* Give the overlay scaler a chance to enable if it's on this pipe */ | |
1421 | //intel_crtc_dpms_video(crtc, true); TODO | |
7662c8bd | 1422 | intel_update_watermarks(dev); |
79e53945 JB |
1423 | break; |
1424 | case DRM_MODE_DPMS_OFF: | |
7662c8bd | 1425 | intel_update_watermarks(dev); |
79e53945 JB |
1426 | /* Give the overlay scaler a chance to disable if it's on this pipe */ |
1427 | //intel_crtc_dpms_video(crtc, FALSE); TODO | |
1428 | ||
1429 | /* Disable the VGA plane that we never use */ | |
24f119c7 | 1430 | i915_disable_vga(dev); |
79e53945 JB |
1431 | |
1432 | /* Disable display plane */ | |
1433 | temp = I915_READ(dspcntr_reg); | |
1434 | if ((temp & DISPLAY_PLANE_ENABLE) != 0) { | |
1435 | I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE); | |
1436 | /* Flush the plane changes */ | |
1437 | I915_WRITE(dspbase_reg, I915_READ(dspbase_reg)); | |
1438 | I915_READ(dspbase_reg); | |
1439 | } | |
1440 | ||
1441 | if (!IS_I9XX(dev)) { | |
1442 | /* Wait for vblank for the disable to take effect */ | |
1443 | intel_wait_for_vblank(dev); | |
1444 | } | |
1445 | ||
1446 | /* Next, disable display pipes */ | |
1447 | temp = I915_READ(pipeconf_reg); | |
1448 | if ((temp & PIPEACONF_ENABLE) != 0) { | |
1449 | I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE); | |
1450 | I915_READ(pipeconf_reg); | |
1451 | } | |
1452 | ||
1453 | /* Wait for vblank for the disable to take effect. */ | |
1454 | intel_wait_for_vblank(dev); | |
1455 | ||
1456 | temp = I915_READ(dpll_reg); | |
1457 | if ((temp & DPLL_VCO_ENABLE) != 0) { | |
1458 | I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE); | |
1459 | I915_READ(dpll_reg); | |
1460 | } | |
1461 | ||
1462 | /* Wait for the clocks to turn off. */ | |
1463 | udelay(150); | |
1464 | break; | |
1465 | } | |
2c07245f ZW |
1466 | } |
1467 | ||
1468 | /** | |
1469 | * Sets the power management mode of the pipe and plane. | |
1470 | * | |
1471 | * This code should probably grow support for turning the cursor off and back | |
1472 | * on appropriately at the same time as we're turning the pipe off/on. | |
1473 | */ | |
1474 | static void intel_crtc_dpms(struct drm_crtc *crtc, int mode) | |
1475 | { | |
1476 | struct drm_device *dev = crtc->dev; | |
1477 | struct drm_i915_master_private *master_priv; | |
1478 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1479 | int pipe = intel_crtc->pipe; | |
1480 | bool enabled; | |
1481 | ||
1482 | if (IS_IGDNG(dev)) | |
1483 | igdng_crtc_dpms(crtc, mode); | |
1484 | else | |
1485 | i9xx_crtc_dpms(crtc, mode); | |
79e53945 JB |
1486 | |
1487 | if (!dev->primary->master) | |
1488 | return; | |
1489 | ||
1490 | master_priv = dev->primary->master->driver_priv; | |
1491 | if (!master_priv->sarea_priv) | |
1492 | return; | |
1493 | ||
1494 | enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF; | |
1495 | ||
1496 | switch (pipe) { | |
1497 | case 0: | |
1498 | master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; | |
1499 | master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; | |
1500 | break; | |
1501 | case 1: | |
1502 | master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; | |
1503 | master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; | |
1504 | break; | |
1505 | default: | |
1506 | DRM_ERROR("Can't update pipe %d in SAREA\n", pipe); | |
1507 | break; | |
1508 | } | |
1509 | ||
1510 | intel_crtc->dpms_mode = mode; | |
1511 | } | |
1512 | ||
1513 | static void intel_crtc_prepare (struct drm_crtc *crtc) | |
1514 | { | |
1515 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; | |
1516 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF); | |
1517 | } | |
1518 | ||
1519 | static void intel_crtc_commit (struct drm_crtc *crtc) | |
1520 | { | |
1521 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; | |
1522 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); | |
1523 | } | |
1524 | ||
1525 | void intel_encoder_prepare (struct drm_encoder *encoder) | |
1526 | { | |
1527 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
1528 | /* lvds has its own version of prepare see intel_lvds_prepare */ | |
1529 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF); | |
1530 | } | |
1531 | ||
1532 | void intel_encoder_commit (struct drm_encoder *encoder) | |
1533 | { | |
1534 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
1535 | /* lvds has its own version of commit see intel_lvds_commit */ | |
1536 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); | |
1537 | } | |
1538 | ||
1539 | static bool intel_crtc_mode_fixup(struct drm_crtc *crtc, | |
1540 | struct drm_display_mode *mode, | |
1541 | struct drm_display_mode *adjusted_mode) | |
1542 | { | |
2c07245f ZW |
1543 | struct drm_device *dev = crtc->dev; |
1544 | if (IS_IGDNG(dev)) { | |
1545 | /* FDI link clock is fixed at 2.7G */ | |
1546 | if (mode->clock * 3 > 27000 * 4) | |
1547 | return MODE_CLOCK_HIGH; | |
1548 | } | |
79e53945 JB |
1549 | return true; |
1550 | } | |
1551 | ||
1552 | ||
1553 | /** Returns the core display clock speed for i830 - i945 */ | |
1554 | static int intel_get_core_clock_speed(struct drm_device *dev) | |
1555 | { | |
1556 | ||
1557 | /* Core clock values taken from the published datasheets. | |
1558 | * The 830 may go up to 166 Mhz, which we should check. | |
1559 | */ | |
1560 | if (IS_I945G(dev)) | |
1561 | return 400000; | |
1562 | else if (IS_I915G(dev)) | |
1563 | return 333000; | |
2177832f | 1564 | else if (IS_I945GM(dev) || IS_845G(dev) || IS_IGDGM(dev)) |
79e53945 JB |
1565 | return 200000; |
1566 | else if (IS_I915GM(dev)) { | |
1567 | u16 gcfgc = 0; | |
1568 | ||
1569 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
1570 | ||
1571 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
1572 | return 133000; | |
1573 | else { | |
1574 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
1575 | case GC_DISPLAY_CLOCK_333_MHZ: | |
1576 | return 333000; | |
1577 | default: | |
1578 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
1579 | return 190000; | |
1580 | } | |
1581 | } | |
1582 | } else if (IS_I865G(dev)) | |
1583 | return 266000; | |
1584 | else if (IS_I855(dev)) { | |
1585 | u16 hpllcc = 0; | |
1586 | /* Assume that the hardware is in the high speed state. This | |
1587 | * should be the default. | |
1588 | */ | |
1589 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
1590 | case GC_CLOCK_133_200: | |
1591 | case GC_CLOCK_100_200: | |
1592 | return 200000; | |
1593 | case GC_CLOCK_166_250: | |
1594 | return 250000; | |
1595 | case GC_CLOCK_100_133: | |
1596 | return 133000; | |
1597 | } | |
1598 | } else /* 852, 830 */ | |
1599 | return 133000; | |
1600 | ||
1601 | return 0; /* Silence gcc warning */ | |
1602 | } | |
1603 | ||
79e53945 JB |
1604 | /** |
1605 | * Return the pipe currently connected to the panel fitter, | |
1606 | * or -1 if the panel fitter is not present or not in use | |
1607 | */ | |
1608 | static int intel_panel_fitter_pipe (struct drm_device *dev) | |
1609 | { | |
1610 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1611 | u32 pfit_control; | |
1612 | ||
1613 | /* i830 doesn't have a panel fitter */ | |
1614 | if (IS_I830(dev)) | |
1615 | return -1; | |
1616 | ||
1617 | pfit_control = I915_READ(PFIT_CONTROL); | |
1618 | ||
1619 | /* See if the panel fitter is in use */ | |
1620 | if ((pfit_control & PFIT_ENABLE) == 0) | |
1621 | return -1; | |
1622 | ||
1623 | /* 965 can place panel fitter on either pipe */ | |
1624 | if (IS_I965G(dev)) | |
1625 | return (pfit_control >> 29) & 0x3; | |
1626 | ||
1627 | /* older chips can only use pipe 1 */ | |
1628 | return 1; | |
1629 | } | |
1630 | ||
2c07245f ZW |
1631 | struct fdi_m_n { |
1632 | u32 tu; | |
1633 | u32 gmch_m; | |
1634 | u32 gmch_n; | |
1635 | u32 link_m; | |
1636 | u32 link_n; | |
1637 | }; | |
1638 | ||
1639 | static void | |
1640 | fdi_reduce_ratio(u32 *num, u32 *den) | |
1641 | { | |
1642 | while (*num > 0xffffff || *den > 0xffffff) { | |
1643 | *num >>= 1; | |
1644 | *den >>= 1; | |
1645 | } | |
1646 | } | |
1647 | ||
1648 | #define DATA_N 0x800000 | |
1649 | #define LINK_N 0x80000 | |
1650 | ||
1651 | static void | |
1652 | igdng_compute_m_n(int bytes_per_pixel, int nlanes, | |
1653 | int pixel_clock, int link_clock, | |
1654 | struct fdi_m_n *m_n) | |
1655 | { | |
1656 | u64 temp; | |
1657 | ||
1658 | m_n->tu = 64; /* default size */ | |
1659 | ||
1660 | temp = (u64) DATA_N * pixel_clock; | |
1661 | temp = div_u64(temp, link_clock); | |
956dba3c | 1662 | m_n->gmch_m = div_u64(temp * bytes_per_pixel, nlanes); |
2c07245f ZW |
1663 | m_n->gmch_n = DATA_N; |
1664 | fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); | |
1665 | ||
1666 | temp = (u64) LINK_N * pixel_clock; | |
1667 | m_n->link_m = div_u64(temp, link_clock); | |
1668 | m_n->link_n = LINK_N; | |
1669 | fdi_reduce_ratio(&m_n->link_m, &m_n->link_n); | |
1670 | } | |
1671 | ||
1672 | ||
7662c8bd SL |
1673 | struct intel_watermark_params { |
1674 | unsigned long fifo_size; | |
1675 | unsigned long max_wm; | |
1676 | unsigned long default_wm; | |
1677 | unsigned long guard_size; | |
1678 | unsigned long cacheline_size; | |
1679 | }; | |
1680 | ||
1681 | /* IGD has different values for various configs */ | |
1682 | static struct intel_watermark_params igd_display_wm = { | |
1683 | IGD_DISPLAY_FIFO, | |
1684 | IGD_MAX_WM, | |
1685 | IGD_DFT_WM, | |
1686 | IGD_GUARD_WM, | |
1687 | IGD_FIFO_LINE_SIZE | |
1688 | }; | |
1689 | static struct intel_watermark_params igd_display_hplloff_wm = { | |
1690 | IGD_DISPLAY_FIFO, | |
1691 | IGD_MAX_WM, | |
1692 | IGD_DFT_HPLLOFF_WM, | |
1693 | IGD_GUARD_WM, | |
1694 | IGD_FIFO_LINE_SIZE | |
1695 | }; | |
1696 | static struct intel_watermark_params igd_cursor_wm = { | |
1697 | IGD_CURSOR_FIFO, | |
1698 | IGD_CURSOR_MAX_WM, | |
1699 | IGD_CURSOR_DFT_WM, | |
1700 | IGD_CURSOR_GUARD_WM, | |
1701 | IGD_FIFO_LINE_SIZE, | |
1702 | }; | |
1703 | static struct intel_watermark_params igd_cursor_hplloff_wm = { | |
1704 | IGD_CURSOR_FIFO, | |
1705 | IGD_CURSOR_MAX_WM, | |
1706 | IGD_CURSOR_DFT_WM, | |
1707 | IGD_CURSOR_GUARD_WM, | |
1708 | IGD_FIFO_LINE_SIZE | |
1709 | }; | |
1710 | static struct intel_watermark_params i945_wm_info = { | |
dff33cfc | 1711 | I945_FIFO_SIZE, |
7662c8bd SL |
1712 | I915_MAX_WM, |
1713 | 1, | |
dff33cfc JB |
1714 | 2, |
1715 | I915_FIFO_LINE_SIZE | |
7662c8bd SL |
1716 | }; |
1717 | static struct intel_watermark_params i915_wm_info = { | |
dff33cfc | 1718 | I915_FIFO_SIZE, |
7662c8bd SL |
1719 | I915_MAX_WM, |
1720 | 1, | |
dff33cfc | 1721 | 2, |
7662c8bd SL |
1722 | I915_FIFO_LINE_SIZE |
1723 | }; | |
1724 | static struct intel_watermark_params i855_wm_info = { | |
1725 | I855GM_FIFO_SIZE, | |
1726 | I915_MAX_WM, | |
1727 | 1, | |
dff33cfc | 1728 | 2, |
7662c8bd SL |
1729 | I830_FIFO_LINE_SIZE |
1730 | }; | |
1731 | static struct intel_watermark_params i830_wm_info = { | |
1732 | I830_FIFO_SIZE, | |
1733 | I915_MAX_WM, | |
1734 | 1, | |
dff33cfc | 1735 | 2, |
7662c8bd SL |
1736 | I830_FIFO_LINE_SIZE |
1737 | }; | |
1738 | ||
dff33cfc JB |
1739 | /** |
1740 | * intel_calculate_wm - calculate watermark level | |
1741 | * @clock_in_khz: pixel clock | |
1742 | * @wm: chip FIFO params | |
1743 | * @pixel_size: display pixel size | |
1744 | * @latency_ns: memory latency for the platform | |
1745 | * | |
1746 | * Calculate the watermark level (the level at which the display plane will | |
1747 | * start fetching from memory again). Each chip has a different display | |
1748 | * FIFO size and allocation, so the caller needs to figure that out and pass | |
1749 | * in the correct intel_watermark_params structure. | |
1750 | * | |
1751 | * As the pixel clock runs, the FIFO will be drained at a rate that depends | |
1752 | * on the pixel size. When it reaches the watermark level, it'll start | |
1753 | * fetching FIFO line sized based chunks from memory until the FIFO fills | |
1754 | * past the watermark point. If the FIFO drains completely, a FIFO underrun | |
1755 | * will occur, and a display engine hang could result. | |
1756 | */ | |
7662c8bd SL |
1757 | static unsigned long intel_calculate_wm(unsigned long clock_in_khz, |
1758 | struct intel_watermark_params *wm, | |
1759 | int pixel_size, | |
1760 | unsigned long latency_ns) | |
1761 | { | |
390c4dd4 | 1762 | long entries_required, wm_size; |
dff33cfc JB |
1763 | |
1764 | entries_required = (clock_in_khz * pixel_size * latency_ns) / 1000000; | |
1765 | entries_required /= wm->cacheline_size; | |
7662c8bd | 1766 | |
dff33cfc JB |
1767 | DRM_DEBUG("FIFO entries required for mode: %d\n", entries_required); |
1768 | ||
1769 | wm_size = wm->fifo_size - (entries_required + wm->guard_size); | |
1770 | ||
1771 | DRM_DEBUG("FIFO watermark level: %d\n", wm_size); | |
7662c8bd | 1772 | |
390c4dd4 JB |
1773 | /* Don't promote wm_size to unsigned... */ |
1774 | if (wm_size > (long)wm->max_wm) | |
7662c8bd | 1775 | wm_size = wm->max_wm; |
390c4dd4 | 1776 | if (wm_size <= 0) |
7662c8bd SL |
1777 | wm_size = wm->default_wm; |
1778 | return wm_size; | |
1779 | } | |
1780 | ||
1781 | struct cxsr_latency { | |
1782 | int is_desktop; | |
1783 | unsigned long fsb_freq; | |
1784 | unsigned long mem_freq; | |
1785 | unsigned long display_sr; | |
1786 | unsigned long display_hpll_disable; | |
1787 | unsigned long cursor_sr; | |
1788 | unsigned long cursor_hpll_disable; | |
1789 | }; | |
1790 | ||
1791 | static struct cxsr_latency cxsr_latency_table[] = { | |
1792 | {1, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */ | |
1793 | {1, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */ | |
1794 | {1, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */ | |
1795 | ||
1796 | {1, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */ | |
1797 | {1, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */ | |
1798 | {1, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */ | |
1799 | ||
1800 | {1, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */ | |
1801 | {1, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */ | |
1802 | {1, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */ | |
1803 | ||
1804 | {0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */ | |
1805 | {0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */ | |
1806 | {0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */ | |
1807 | ||
1808 | {0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */ | |
1809 | {0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */ | |
1810 | {0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */ | |
1811 | ||
1812 | {0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */ | |
1813 | {0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */ | |
1814 | {0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */ | |
1815 | }; | |
1816 | ||
1817 | static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int fsb, | |
1818 | int mem) | |
1819 | { | |
1820 | int i; | |
1821 | struct cxsr_latency *latency; | |
1822 | ||
1823 | if (fsb == 0 || mem == 0) | |
1824 | return NULL; | |
1825 | ||
1826 | for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) { | |
1827 | latency = &cxsr_latency_table[i]; | |
1828 | if (is_desktop == latency->is_desktop && | |
1829 | fsb == latency->fsb_freq && mem == latency->mem_freq) | |
1830 | break; | |
1831 | } | |
1832 | if (i >= ARRAY_SIZE(cxsr_latency_table)) { | |
1833 | DRM_DEBUG("Unknown FSB/MEM found, disable CxSR\n"); | |
1834 | return NULL; | |
1835 | } | |
1836 | return latency; | |
1837 | } | |
1838 | ||
1839 | static void igd_disable_cxsr(struct drm_device *dev) | |
1840 | { | |
1841 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1842 | u32 reg; | |
1843 | ||
1844 | /* deactivate cxsr */ | |
1845 | reg = I915_READ(DSPFW3); | |
1846 | reg &= ~(IGD_SELF_REFRESH_EN); | |
1847 | I915_WRITE(DSPFW3, reg); | |
1848 | DRM_INFO("Big FIFO is disabled\n"); | |
1849 | } | |
1850 | ||
1851 | static void igd_enable_cxsr(struct drm_device *dev, unsigned long clock, | |
1852 | int pixel_size) | |
1853 | { | |
1854 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1855 | u32 reg; | |
1856 | unsigned long wm; | |
1857 | struct cxsr_latency *latency; | |
1858 | ||
1859 | latency = intel_get_cxsr_latency(IS_IGDG(dev), dev_priv->fsb_freq, | |
1860 | dev_priv->mem_freq); | |
1861 | if (!latency) { | |
1862 | DRM_DEBUG("Unknown FSB/MEM found, disable CxSR\n"); | |
1863 | igd_disable_cxsr(dev); | |
1864 | return; | |
1865 | } | |
1866 | ||
1867 | /* Display SR */ | |
1868 | wm = intel_calculate_wm(clock, &igd_display_wm, pixel_size, | |
1869 | latency->display_sr); | |
1870 | reg = I915_READ(DSPFW1); | |
1871 | reg &= 0x7fffff; | |
1872 | reg |= wm << 23; | |
1873 | I915_WRITE(DSPFW1, reg); | |
1874 | DRM_DEBUG("DSPFW1 register is %x\n", reg); | |
1875 | ||
1876 | /* cursor SR */ | |
1877 | wm = intel_calculate_wm(clock, &igd_cursor_wm, pixel_size, | |
1878 | latency->cursor_sr); | |
1879 | reg = I915_READ(DSPFW3); | |
1880 | reg &= ~(0x3f << 24); | |
1881 | reg |= (wm & 0x3f) << 24; | |
1882 | I915_WRITE(DSPFW3, reg); | |
1883 | ||
1884 | /* Display HPLL off SR */ | |
1885 | wm = intel_calculate_wm(clock, &igd_display_hplloff_wm, | |
1886 | latency->display_hpll_disable, I915_FIFO_LINE_SIZE); | |
1887 | reg = I915_READ(DSPFW3); | |
1888 | reg &= 0xfffffe00; | |
1889 | reg |= wm & 0x1ff; | |
1890 | I915_WRITE(DSPFW3, reg); | |
1891 | ||
1892 | /* cursor HPLL off SR */ | |
1893 | wm = intel_calculate_wm(clock, &igd_cursor_hplloff_wm, pixel_size, | |
1894 | latency->cursor_hpll_disable); | |
1895 | reg = I915_READ(DSPFW3); | |
1896 | reg &= ~(0x3f << 16); | |
1897 | reg |= (wm & 0x3f) << 16; | |
1898 | I915_WRITE(DSPFW3, reg); | |
1899 | DRM_DEBUG("DSPFW3 register is %x\n", reg); | |
1900 | ||
1901 | /* activate cxsr */ | |
1902 | reg = I915_READ(DSPFW3); | |
1903 | reg |= IGD_SELF_REFRESH_EN; | |
1904 | I915_WRITE(DSPFW3, reg); | |
1905 | ||
1906 | DRM_INFO("Big FIFO is enabled\n"); | |
1907 | ||
1908 | return; | |
1909 | } | |
1910 | ||
dff33cfc | 1911 | const static int latency_ns = 3000; /* default for non-igd platforms */ |
7662c8bd | 1912 | |
dff33cfc JB |
1913 | static int intel_get_fifo_size(struct drm_device *dev, int plane) |
1914 | { | |
1915 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1916 | uint32_t dsparb = I915_READ(DSPARB); | |
1917 | int size; | |
1918 | ||
1919 | if (IS_I9XX(dev)) { | |
1920 | if (plane == 0) | |
1921 | size = dsparb & 0x7f; | |
1922 | else | |
1923 | size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - | |
1924 | (dsparb & 0x7f); | |
1925 | } else if (IS_I85X(dev)) { | |
1926 | if (plane == 0) | |
1927 | size = dsparb & 0x1ff; | |
1928 | else | |
1929 | size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - | |
1930 | (dsparb & 0x1ff); | |
1931 | size >>= 1; /* Convert to cachelines */ | |
1932 | } else { | |
1933 | size = dsparb & 0x7f; | |
1934 | size >>= 1; /* Convert to cachelines */ | |
1935 | } | |
1936 | ||
1937 | DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb, plane ? "B" : "A", | |
1938 | size); | |
1939 | ||
1940 | return size; | |
1941 | } | |
7662c8bd SL |
1942 | |
1943 | static void i965_update_wm(struct drm_device *dev) | |
1944 | { | |
1945 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1946 | ||
1947 | DRM_DEBUG("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR 8\n"); | |
1948 | ||
1949 | /* 965 has limitations... */ | |
1950 | I915_WRITE(DSPFW1, (8 << 16) | (8 << 8) | (8 << 0)); | |
1951 | I915_WRITE(DSPFW2, (8 << 8) | (8 << 0)); | |
1952 | } | |
1953 | ||
1954 | static void i9xx_update_wm(struct drm_device *dev, int planea_clock, | |
1955 | int planeb_clock, int sr_hdisplay, int pixel_size) | |
1956 | { | |
1957 | struct drm_i915_private *dev_priv = dev->dev_private; | |
dff33cfc JB |
1958 | uint32_t fwater_lo; |
1959 | uint32_t fwater_hi; | |
1960 | int total_size, cacheline_size, cwm, srwm = 1; | |
1961 | int planea_wm, planeb_wm; | |
1962 | struct intel_watermark_params planea_params, planeb_params; | |
7662c8bd SL |
1963 | unsigned long line_time_us; |
1964 | int sr_clock, sr_entries = 0; | |
1965 | ||
dff33cfc | 1966 | /* Create copies of the base settings for each pipe */ |
7662c8bd | 1967 | if (IS_I965GM(dev) || IS_I945GM(dev)) |
dff33cfc | 1968 | planea_params = planeb_params = i945_wm_info; |
7662c8bd | 1969 | else if (IS_I9XX(dev)) |
dff33cfc | 1970 | planea_params = planeb_params = i915_wm_info; |
7662c8bd | 1971 | else |
dff33cfc | 1972 | planea_params = planeb_params = i855_wm_info; |
7662c8bd | 1973 | |
dff33cfc JB |
1974 | /* Grab a couple of global values before we overwrite them */ |
1975 | total_size = planea_params.fifo_size; | |
1976 | cacheline_size = planea_params.cacheline_size; | |
7662c8bd | 1977 | |
dff33cfc JB |
1978 | /* Update per-plane FIFO sizes */ |
1979 | planea_params.fifo_size = intel_get_fifo_size(dev, 0); | |
1980 | planeb_params.fifo_size = intel_get_fifo_size(dev, 1); | |
7662c8bd | 1981 | |
dff33cfc JB |
1982 | planea_wm = intel_calculate_wm(planea_clock, &planea_params, |
1983 | pixel_size, latency_ns); | |
1984 | planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params, | |
1985 | pixel_size, latency_ns); | |
1986 | DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); | |
7662c8bd SL |
1987 | |
1988 | /* | |
1989 | * Overlay gets an aggressive default since video jitter is bad. | |
1990 | */ | |
1991 | cwm = 2; | |
1992 | ||
dff33cfc | 1993 | /* Calc sr entries for one plane configs */ |
2a2430f4 | 1994 | if (sr_hdisplay && (!planea_clock || !planeb_clock)) { |
dff33cfc JB |
1995 | /* self-refresh has much higher latency */ |
1996 | const static int sr_latency_ns = 6000; | |
1997 | ||
7662c8bd | 1998 | sr_clock = planea_clock ? planea_clock : planeb_clock; |
dff33cfc JB |
1999 | line_time_us = ((sr_hdisplay * 1000) / sr_clock); |
2000 | ||
2001 | /* Use ns/us then divide to preserve precision */ | |
2002 | sr_entries = (((sr_latency_ns / line_time_us) + 1) * | |
2003 | pixel_size * sr_hdisplay) / 1000; | |
2004 | sr_entries = roundup(sr_entries / cacheline_size, 1); | |
2005 | DRM_DEBUG("self-refresh entries: %d\n", sr_entries); | |
2006 | srwm = total_size - sr_entries; | |
2007 | if (srwm < 0) | |
2008 | srwm = 1; | |
2a2430f4 JB |
2009 | if (IS_I9XX(dev)) |
2010 | I915_WRITE(FW_BLC_SELF, (srwm & 0x3f)); | |
7662c8bd SL |
2011 | } |
2012 | ||
2013 | DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", | |
dff33cfc | 2014 | planea_wm, planeb_wm, cwm, srwm); |
7662c8bd | 2015 | |
dff33cfc JB |
2016 | fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f); |
2017 | fwater_hi = (cwm & 0x1f); | |
2018 | ||
2019 | /* Set request length to 8 cachelines per fetch */ | |
2020 | fwater_lo = fwater_lo | (1 << 24) | (1 << 8); | |
2021 | fwater_hi = fwater_hi | (1 << 8); | |
7662c8bd SL |
2022 | |
2023 | I915_WRITE(FW_BLC, fwater_lo); | |
2024 | I915_WRITE(FW_BLC2, fwater_hi); | |
7662c8bd SL |
2025 | } |
2026 | ||
2027 | static void i830_update_wm(struct drm_device *dev, int planea_clock, | |
2028 | int pixel_size) | |
2029 | { | |
2030 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7662c8bd | 2031 | uint32_t fwater_lo = I915_READ(FW_BLC) & MM_FIFO_WATERMARK; |
dff33cfc | 2032 | int planea_wm; |
7662c8bd | 2033 | |
dff33cfc | 2034 | i830_wm_info.fifo_size = intel_get_fifo_size(dev, 0); |
7662c8bd | 2035 | |
dff33cfc JB |
2036 | planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info, |
2037 | pixel_size, latency_ns); | |
2038 | fwater_lo = fwater_lo | planea_wm; | |
7662c8bd SL |
2039 | |
2040 | I915_WRITE(FW_BLC, fwater_lo); | |
2041 | } | |
2042 | ||
2043 | /** | |
2044 | * intel_update_watermarks - update FIFO watermark values based on current modes | |
2045 | * | |
2046 | * Calculate watermark values for the various WM regs based on current mode | |
2047 | * and plane configuration. | |
2048 | * | |
2049 | * There are several cases to deal with here: | |
2050 | * - normal (i.e. non-self-refresh) | |
2051 | * - self-refresh (SR) mode | |
2052 | * - lines are large relative to FIFO size (buffer can hold up to 2) | |
2053 | * - lines are small relative to FIFO size (buffer can hold more than 2 | |
2054 | * lines), so need to account for TLB latency | |
2055 | * | |
2056 | * The normal calculation is: | |
2057 | * watermark = dotclock * bytes per pixel * latency | |
2058 | * where latency is platform & configuration dependent (we assume pessimal | |
2059 | * values here). | |
2060 | * | |
2061 | * The SR calculation is: | |
2062 | * watermark = (trunc(latency/line time)+1) * surface width * | |
2063 | * bytes per pixel | |
2064 | * where | |
2065 | * line time = htotal / dotclock | |
2066 | * and latency is assumed to be high, as above. | |
2067 | * | |
2068 | * The final value programmed to the register should always be rounded up, | |
2069 | * and include an extra 2 entries to account for clock crossings. | |
2070 | * | |
2071 | * We don't use the sprite, so we can ignore that. And on Crestline we have | |
2072 | * to set the non-SR watermarks to 8. | |
2073 | */ | |
2074 | static void intel_update_watermarks(struct drm_device *dev) | |
2075 | { | |
2076 | struct drm_crtc *crtc; | |
2077 | struct intel_crtc *intel_crtc; | |
2078 | int sr_hdisplay = 0; | |
2079 | unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0; | |
2080 | int enabled = 0, pixel_size = 0; | |
2081 | ||
2082 | if (DSPARB_HWCONTROL(dev)) | |
2083 | return; | |
2084 | ||
2085 | /* Get the clock config from both planes */ | |
2086 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
2087 | intel_crtc = to_intel_crtc(crtc); | |
2088 | if (crtc->enabled) { | |
2089 | enabled++; | |
2090 | if (intel_crtc->plane == 0) { | |
2091 | DRM_DEBUG("plane A (pipe %d) clock: %d\n", | |
2092 | intel_crtc->pipe, crtc->mode.clock); | |
2093 | planea_clock = crtc->mode.clock; | |
2094 | } else { | |
2095 | DRM_DEBUG("plane B (pipe %d) clock: %d\n", | |
2096 | intel_crtc->pipe, crtc->mode.clock); | |
2097 | planeb_clock = crtc->mode.clock; | |
2098 | } | |
2099 | sr_hdisplay = crtc->mode.hdisplay; | |
2100 | sr_clock = crtc->mode.clock; | |
2101 | if (crtc->fb) | |
2102 | pixel_size = crtc->fb->bits_per_pixel / 8; | |
2103 | else | |
2104 | pixel_size = 4; /* by default */ | |
2105 | } | |
2106 | } | |
2107 | ||
2108 | if (enabled <= 0) | |
2109 | return; | |
2110 | ||
dff33cfc | 2111 | /* Single plane configs can enable self refresh */ |
7662c8bd SL |
2112 | if (enabled == 1 && IS_IGD(dev)) |
2113 | igd_enable_cxsr(dev, sr_clock, pixel_size); | |
2114 | else if (IS_IGD(dev)) | |
2115 | igd_disable_cxsr(dev); | |
2116 | ||
2117 | if (IS_I965G(dev)) | |
2118 | i965_update_wm(dev); | |
2119 | else if (IS_I9XX(dev) || IS_MOBILE(dev)) | |
2120 | i9xx_update_wm(dev, planea_clock, planeb_clock, sr_hdisplay, | |
2121 | pixel_size); | |
2122 | else | |
2123 | i830_update_wm(dev, planea_clock, pixel_size); | |
2124 | } | |
2125 | ||
5c3b82e2 CW |
2126 | static int intel_crtc_mode_set(struct drm_crtc *crtc, |
2127 | struct drm_display_mode *mode, | |
2128 | struct drm_display_mode *adjusted_mode, | |
2129 | int x, int y, | |
2130 | struct drm_framebuffer *old_fb) | |
79e53945 JB |
2131 | { |
2132 | struct drm_device *dev = crtc->dev; | |
2133 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2134 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2135 | int pipe = intel_crtc->pipe; | |
2136 | int fp_reg = (pipe == 0) ? FPA0 : FPB0; | |
2137 | int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; | |
2138 | int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD; | |
2139 | int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR; | |
2140 | int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF; | |
2141 | int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B; | |
2142 | int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B; | |
2143 | int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B; | |
2144 | int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B; | |
2145 | int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B; | |
2146 | int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B; | |
2147 | int dspsize_reg = (pipe == 0) ? DSPASIZE : DSPBSIZE; | |
2148 | int dsppos_reg = (pipe == 0) ? DSPAPOS : DSPBPOS; | |
2149 | int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC; | |
43565a06 | 2150 | int refclk, num_outputs = 0; |
79e53945 JB |
2151 | intel_clock_t clock; |
2152 | u32 dpll = 0, fp = 0, dspcntr, pipeconf; | |
2153 | bool ok, is_sdvo = false, is_dvo = false; | |
a4fc5ed6 | 2154 | bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false; |
79e53945 JB |
2155 | struct drm_mode_config *mode_config = &dev->mode_config; |
2156 | struct drm_connector *connector; | |
d4906093 | 2157 | const intel_limit_t *limit; |
5c3b82e2 | 2158 | int ret; |
2c07245f ZW |
2159 | struct fdi_m_n m_n = {0}; |
2160 | int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1; | |
2161 | int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1; | |
2162 | int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1; | |
2163 | int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1; | |
2164 | int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0; | |
2165 | int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B; | |
2166 | int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL; | |
541998a1 | 2167 | int lvds_reg = LVDS; |
2c07245f ZW |
2168 | u32 temp; |
2169 | int sdvo_pixel_multiply; | |
5eb08b69 | 2170 | int target_clock; |
79e53945 JB |
2171 | |
2172 | drm_vblank_pre_modeset(dev, pipe); | |
2173 | ||
2174 | list_for_each_entry(connector, &mode_config->connector_list, head) { | |
2175 | struct intel_output *intel_output = to_intel_output(connector); | |
2176 | ||
2177 | if (!connector->encoder || connector->encoder->crtc != crtc) | |
2178 | continue; | |
2179 | ||
2180 | switch (intel_output->type) { | |
2181 | case INTEL_OUTPUT_LVDS: | |
2182 | is_lvds = true; | |
2183 | break; | |
2184 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 2185 | case INTEL_OUTPUT_HDMI: |
79e53945 | 2186 | is_sdvo = true; |
e2f0ba97 JB |
2187 | if (intel_output->needs_tv_clock) |
2188 | is_tv = true; | |
79e53945 JB |
2189 | break; |
2190 | case INTEL_OUTPUT_DVO: | |
2191 | is_dvo = true; | |
2192 | break; | |
2193 | case INTEL_OUTPUT_TVOUT: | |
2194 | is_tv = true; | |
2195 | break; | |
2196 | case INTEL_OUTPUT_ANALOG: | |
2197 | is_crt = true; | |
2198 | break; | |
a4fc5ed6 KP |
2199 | case INTEL_OUTPUT_DISPLAYPORT: |
2200 | is_dp = true; | |
2201 | break; | |
79e53945 | 2202 | } |
43565a06 KH |
2203 | |
2204 | num_outputs++; | |
79e53945 JB |
2205 | } |
2206 | ||
43565a06 KH |
2207 | if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) { |
2208 | refclk = dev_priv->lvds_ssc_freq * 1000; | |
2209 | DRM_DEBUG("using SSC reference clock of %d MHz\n", refclk / 1000); | |
2210 | } else if (IS_I9XX(dev)) { | |
79e53945 | 2211 | refclk = 96000; |
2c07245f ZW |
2212 | if (IS_IGDNG(dev)) |
2213 | refclk = 120000; /* 120Mhz refclk */ | |
79e53945 JB |
2214 | } else { |
2215 | refclk = 48000; | |
2216 | } | |
a4fc5ed6 | 2217 | |
79e53945 | 2218 | |
d4906093 ML |
2219 | /* |
2220 | * Returns a set of divisors for the desired target clock with the given | |
2221 | * refclk, or FALSE. The returned values represent the clock equation: | |
2222 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
2223 | */ | |
2224 | limit = intel_limit(crtc); | |
2225 | ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock); | |
79e53945 JB |
2226 | if (!ok) { |
2227 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
1f803ee5 | 2228 | drm_vblank_post_modeset(dev, pipe); |
5c3b82e2 | 2229 | return -EINVAL; |
79e53945 JB |
2230 | } |
2231 | ||
7026d4ac ZW |
2232 | /* SDVO TV has fixed PLL values depend on its clock range, |
2233 | this mirrors vbios setting. */ | |
2234 | if (is_sdvo && is_tv) { | |
2235 | if (adjusted_mode->clock >= 100000 | |
2236 | && adjusted_mode->clock < 140500) { | |
2237 | clock.p1 = 2; | |
2238 | clock.p2 = 10; | |
2239 | clock.n = 3; | |
2240 | clock.m1 = 16; | |
2241 | clock.m2 = 8; | |
2242 | } else if (adjusted_mode->clock >= 140500 | |
2243 | && adjusted_mode->clock <= 200000) { | |
2244 | clock.p1 = 1; | |
2245 | clock.p2 = 10; | |
2246 | clock.n = 6; | |
2247 | clock.m1 = 12; | |
2248 | clock.m2 = 8; | |
2249 | } | |
2250 | } | |
2251 | ||
2c07245f | 2252 | /* FDI link */ |
5eb08b69 ZW |
2253 | if (IS_IGDNG(dev)) { |
2254 | /* DP over FDI requires target mode clock | |
2255 | instead of link clock */ | |
2256 | if (is_dp) | |
2257 | target_clock = mode->clock; | |
2258 | else | |
2259 | target_clock = adjusted_mode->clock; | |
2c07245f | 2260 | igdng_compute_m_n(3, 4, /* lane num 4 */ |
5eb08b69 | 2261 | target_clock, |
2c07245f ZW |
2262 | 270000, /* lane clock */ |
2263 | &m_n); | |
5eb08b69 | 2264 | } |
2c07245f | 2265 | |
2177832f SL |
2266 | if (IS_IGD(dev)) |
2267 | fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2; | |
2268 | else | |
2269 | fp = clock.n << 16 | clock.m1 << 8 | clock.m2; | |
79e53945 | 2270 | |
2c07245f ZW |
2271 | if (!IS_IGDNG(dev)) |
2272 | dpll = DPLL_VGA_MODE_DIS; | |
2273 | ||
79e53945 JB |
2274 | if (IS_I9XX(dev)) { |
2275 | if (is_lvds) | |
2276 | dpll |= DPLLB_MODE_LVDS; | |
2277 | else | |
2278 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
2279 | if (is_sdvo) { | |
2280 | dpll |= DPLL_DVO_HIGH_SPEED; | |
2c07245f ZW |
2281 | sdvo_pixel_multiply = adjusted_mode->clock / mode->clock; |
2282 | if (IS_I945G(dev) || IS_I945GM(dev)) | |
79e53945 | 2283 | dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES; |
2c07245f ZW |
2284 | else if (IS_IGDNG(dev)) |
2285 | dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; | |
79e53945 | 2286 | } |
a4fc5ed6 KP |
2287 | if (is_dp) |
2288 | dpll |= DPLL_DVO_HIGH_SPEED; | |
79e53945 JB |
2289 | |
2290 | /* compute bitmask from p1 value */ | |
2177832f SL |
2291 | if (IS_IGD(dev)) |
2292 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_IGD; | |
2c07245f | 2293 | else { |
2177832f | 2294 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
2c07245f ZW |
2295 | /* also FPA1 */ |
2296 | if (IS_IGDNG(dev)) | |
2297 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
2298 | } | |
79e53945 JB |
2299 | switch (clock.p2) { |
2300 | case 5: | |
2301 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
2302 | break; | |
2303 | case 7: | |
2304 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
2305 | break; | |
2306 | case 10: | |
2307 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
2308 | break; | |
2309 | case 14: | |
2310 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
2311 | break; | |
2312 | } | |
2c07245f | 2313 | if (IS_I965G(dev) && !IS_IGDNG(dev)) |
79e53945 JB |
2314 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); |
2315 | } else { | |
2316 | if (is_lvds) { | |
2317 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
2318 | } else { | |
2319 | if (clock.p1 == 2) | |
2320 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
2321 | else | |
2322 | dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
2323 | if (clock.p2 == 4) | |
2324 | dpll |= PLL_P2_DIVIDE_BY_4; | |
2325 | } | |
2326 | } | |
2327 | ||
43565a06 KH |
2328 | if (is_sdvo && is_tv) |
2329 | dpll |= PLL_REF_INPUT_TVCLKINBC; | |
2330 | else if (is_tv) | |
79e53945 | 2331 | /* XXX: just matching BIOS for now */ |
43565a06 | 2332 | /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ |
79e53945 | 2333 | dpll |= 3; |
43565a06 KH |
2334 | else if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) |
2335 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
79e53945 JB |
2336 | else |
2337 | dpll |= PLL_REF_INPUT_DREFCLK; | |
2338 | ||
2339 | /* setup pipeconf */ | |
2340 | pipeconf = I915_READ(pipeconf_reg); | |
2341 | ||
2342 | /* Set up the display plane register */ | |
2343 | dspcntr = DISPPLANE_GAMMA_ENABLE; | |
2344 | ||
2c07245f ZW |
2345 | /* IGDNG's plane is forced to pipe, bit 24 is to |
2346 | enable color space conversion */ | |
2347 | if (!IS_IGDNG(dev)) { | |
2348 | if (pipe == 0) | |
2349 | dspcntr |= DISPPLANE_SEL_PIPE_A; | |
2350 | else | |
2351 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
2352 | } | |
79e53945 JB |
2353 | |
2354 | if (pipe == 0 && !IS_I965G(dev)) { | |
2355 | /* Enable pixel doubling when the dot clock is > 90% of the (display) | |
2356 | * core speed. | |
2357 | * | |
2358 | * XXX: No double-wide on 915GM pipe B. Is that the only reason for the | |
2359 | * pipe == 0 check? | |
2360 | */ | |
2361 | if (mode->clock > intel_get_core_clock_speed(dev) * 9 / 10) | |
2362 | pipeconf |= PIPEACONF_DOUBLE_WIDE; | |
2363 | else | |
2364 | pipeconf &= ~PIPEACONF_DOUBLE_WIDE; | |
2365 | } | |
2366 | ||
2367 | dspcntr |= DISPLAY_PLANE_ENABLE; | |
2368 | pipeconf |= PIPEACONF_ENABLE; | |
2369 | dpll |= DPLL_VCO_ENABLE; | |
2370 | ||
2371 | ||
2372 | /* Disable the panel fitter if it was on our pipe */ | |
2c07245f | 2373 | if (!IS_IGDNG(dev) && intel_panel_fitter_pipe(dev) == pipe) |
79e53945 JB |
2374 | I915_WRITE(PFIT_CONTROL, 0); |
2375 | ||
2376 | DRM_DEBUG("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); | |
2377 | drm_mode_debug_printmodeline(mode); | |
2378 | ||
2c07245f ZW |
2379 | /* assign to IGDNG registers */ |
2380 | if (IS_IGDNG(dev)) { | |
2381 | fp_reg = pch_fp_reg; | |
2382 | dpll_reg = pch_dpll_reg; | |
2383 | } | |
79e53945 JB |
2384 | |
2385 | if (dpll & DPLL_VCO_ENABLE) { | |
2386 | I915_WRITE(fp_reg, fp); | |
2387 | I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE); | |
2388 | I915_READ(dpll_reg); | |
2389 | udelay(150); | |
2390 | } | |
2391 | ||
2c07245f ZW |
2392 | if (IS_IGDNG(dev)) { |
2393 | /* enable PCH clock reference source */ | |
2394 | /* XXX need to change the setting for other outputs */ | |
2395 | u32 temp; | |
2396 | temp = I915_READ(PCH_DREF_CONTROL); | |
2397 | temp &= ~DREF_NONSPREAD_SOURCE_MASK; | |
2398 | temp |= DREF_NONSPREAD_CK505_ENABLE; | |
2399 | temp &= ~DREF_SSC_SOURCE_MASK; | |
2400 | temp |= DREF_SSC_SOURCE_ENABLE; | |
2401 | temp &= ~DREF_SSC1_ENABLE; | |
2402 | /* if no eDP, disable source output to CPU */ | |
2403 | temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
2404 | temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
2405 | I915_WRITE(PCH_DREF_CONTROL, temp); | |
2406 | } | |
2407 | ||
79e53945 JB |
2408 | /* The LVDS pin pair needs to be on before the DPLLs are enabled. |
2409 | * This is an exception to the general rule that mode_set doesn't turn | |
2410 | * things on. | |
2411 | */ | |
2412 | if (is_lvds) { | |
541998a1 | 2413 | u32 lvds; |
79e53945 | 2414 | |
541998a1 ZW |
2415 | if (IS_IGDNG(dev)) |
2416 | lvds_reg = PCH_LVDS; | |
2417 | ||
2418 | lvds = I915_READ(lvds_reg); | |
79e53945 JB |
2419 | lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT; |
2420 | /* Set the B0-B3 data pairs corresponding to whether we're going to | |
2421 | * set the DPLLs for dual-channel mode or not. | |
2422 | */ | |
2423 | if (clock.p2 == 7) | |
2424 | lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; | |
2425 | else | |
2426 | lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); | |
2427 | ||
2428 | /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) | |
2429 | * appropriately here, but we need to look more thoroughly into how | |
2430 | * panels behave in the two modes. | |
2431 | */ | |
2432 | ||
541998a1 ZW |
2433 | I915_WRITE(lvds_reg, lvds); |
2434 | I915_READ(lvds_reg); | |
79e53945 | 2435 | } |
a4fc5ed6 KP |
2436 | if (is_dp) |
2437 | intel_dp_set_m_n(crtc, mode, adjusted_mode); | |
79e53945 JB |
2438 | |
2439 | I915_WRITE(fp_reg, fp); | |
2440 | I915_WRITE(dpll_reg, dpll); | |
2441 | I915_READ(dpll_reg); | |
2442 | /* Wait for the clocks to stabilize. */ | |
2443 | udelay(150); | |
2444 | ||
2c07245f ZW |
2445 | if (IS_I965G(dev) && !IS_IGDNG(dev)) { |
2446 | sdvo_pixel_multiply = adjusted_mode->clock / mode->clock; | |
79e53945 JB |
2447 | I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) | |
2448 | ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT)); | |
2449 | } else { | |
2450 | /* write it again -- the BIOS does, after all */ | |
2451 | I915_WRITE(dpll_reg, dpll); | |
2452 | } | |
2453 | I915_READ(dpll_reg); | |
2454 | /* Wait for the clocks to stabilize. */ | |
2455 | udelay(150); | |
2456 | ||
2457 | I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) | | |
2458 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
2459 | I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) | | |
2460 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
2461 | I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) | | |
2462 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
2463 | I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) | | |
2464 | ((adjusted_mode->crtc_vtotal - 1) << 16)); | |
2465 | I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) | | |
2466 | ((adjusted_mode->crtc_vblank_end - 1) << 16)); | |
2467 | I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) | | |
2468 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
2469 | /* pipesrc and dspsize control the size that is scaled from, which should | |
2470 | * always be the user's requested size. | |
2471 | */ | |
2c07245f ZW |
2472 | if (!IS_IGDNG(dev)) { |
2473 | I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) | | |
2474 | (mode->hdisplay - 1)); | |
2475 | I915_WRITE(dsppos_reg, 0); | |
2476 | } | |
79e53945 | 2477 | I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); |
2c07245f ZW |
2478 | |
2479 | if (IS_IGDNG(dev)) { | |
2480 | I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m); | |
2481 | I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n); | |
2482 | I915_WRITE(link_m1_reg, m_n.link_m); | |
2483 | I915_WRITE(link_n1_reg, m_n.link_n); | |
2484 | ||
2485 | /* enable FDI RX PLL too */ | |
2486 | temp = I915_READ(fdi_rx_reg); | |
2487 | I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE); | |
2488 | udelay(200); | |
2489 | } | |
2490 | ||
79e53945 JB |
2491 | I915_WRITE(pipeconf_reg, pipeconf); |
2492 | I915_READ(pipeconf_reg); | |
2493 | ||
2494 | intel_wait_for_vblank(dev); | |
2495 | ||
2496 | I915_WRITE(dspcntr_reg, dspcntr); | |
2497 | ||
2498 | /* Flush the plane changes */ | |
5c3b82e2 | 2499 | ret = intel_pipe_set_base(crtc, x, y, old_fb); |
7662c8bd SL |
2500 | |
2501 | intel_update_watermarks(dev); | |
2502 | ||
79e53945 | 2503 | drm_vblank_post_modeset(dev, pipe); |
5c3b82e2 | 2504 | |
1f803ee5 | 2505 | return ret; |
79e53945 JB |
2506 | } |
2507 | ||
2508 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ | |
2509 | void intel_crtc_load_lut(struct drm_crtc *crtc) | |
2510 | { | |
2511 | struct drm_device *dev = crtc->dev; | |
2512 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2513 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2514 | int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B; | |
2515 | int i; | |
2516 | ||
2517 | /* The clocks have to be on to load the palette. */ | |
2518 | if (!crtc->enabled) | |
2519 | return; | |
2520 | ||
2c07245f ZW |
2521 | /* use legacy palette for IGDNG */ |
2522 | if (IS_IGDNG(dev)) | |
2523 | palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A : | |
2524 | LGC_PALETTE_B; | |
2525 | ||
79e53945 JB |
2526 | for (i = 0; i < 256; i++) { |
2527 | I915_WRITE(palreg + 4 * i, | |
2528 | (intel_crtc->lut_r[i] << 16) | | |
2529 | (intel_crtc->lut_g[i] << 8) | | |
2530 | intel_crtc->lut_b[i]); | |
2531 | } | |
2532 | } | |
2533 | ||
2534 | static int intel_crtc_cursor_set(struct drm_crtc *crtc, | |
2535 | struct drm_file *file_priv, | |
2536 | uint32_t handle, | |
2537 | uint32_t width, uint32_t height) | |
2538 | { | |
2539 | struct drm_device *dev = crtc->dev; | |
2540 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2541 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2542 | struct drm_gem_object *bo; | |
2543 | struct drm_i915_gem_object *obj_priv; | |
2544 | int pipe = intel_crtc->pipe; | |
2545 | uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR; | |
2546 | uint32_t base = (pipe == 0) ? CURABASE : CURBBASE; | |
14b60391 | 2547 | uint32_t temp = I915_READ(control); |
79e53945 | 2548 | size_t addr; |
3f8bc370 | 2549 | int ret; |
79e53945 JB |
2550 | |
2551 | DRM_DEBUG("\n"); | |
2552 | ||
2553 | /* if we want to turn off the cursor ignore width and height */ | |
2554 | if (!handle) { | |
2555 | DRM_DEBUG("cursor off\n"); | |
14b60391 JB |
2556 | if (IS_MOBILE(dev) || IS_I9XX(dev)) { |
2557 | temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); | |
2558 | temp |= CURSOR_MODE_DISABLE; | |
2559 | } else { | |
2560 | temp &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE); | |
2561 | } | |
3f8bc370 KH |
2562 | addr = 0; |
2563 | bo = NULL; | |
5004417d | 2564 | mutex_lock(&dev->struct_mutex); |
3f8bc370 | 2565 | goto finish; |
79e53945 JB |
2566 | } |
2567 | ||
2568 | /* Currently we only support 64x64 cursors */ | |
2569 | if (width != 64 || height != 64) { | |
2570 | DRM_ERROR("we currently only support 64x64 cursors\n"); | |
2571 | return -EINVAL; | |
2572 | } | |
2573 | ||
2574 | bo = drm_gem_object_lookup(dev, file_priv, handle); | |
2575 | if (!bo) | |
2576 | return -ENOENT; | |
2577 | ||
2578 | obj_priv = bo->driver_private; | |
2579 | ||
2580 | if (bo->size < width * height * 4) { | |
2581 | DRM_ERROR("buffer is to small\n"); | |
34b8686e DA |
2582 | ret = -ENOMEM; |
2583 | goto fail; | |
79e53945 JB |
2584 | } |
2585 | ||
71acb5eb | 2586 | /* we only need to pin inside GTT if cursor is non-phy */ |
7f9872e0 | 2587 | mutex_lock(&dev->struct_mutex); |
71acb5eb DA |
2588 | if (!dev_priv->cursor_needs_physical) { |
2589 | ret = i915_gem_object_pin(bo, PAGE_SIZE); | |
2590 | if (ret) { | |
2591 | DRM_ERROR("failed to pin cursor bo\n"); | |
7f9872e0 | 2592 | goto fail_locked; |
71acb5eb | 2593 | } |
79e53945 | 2594 | addr = obj_priv->gtt_offset; |
71acb5eb DA |
2595 | } else { |
2596 | ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1); | |
2597 | if (ret) { | |
2598 | DRM_ERROR("failed to attach phys object\n"); | |
7f9872e0 | 2599 | goto fail_locked; |
71acb5eb DA |
2600 | } |
2601 | addr = obj_priv->phys_obj->handle->busaddr; | |
3f8bc370 KH |
2602 | } |
2603 | ||
14b60391 JB |
2604 | if (!IS_I9XX(dev)) |
2605 | I915_WRITE(CURSIZE, (height << 12) | width); | |
2606 | ||
2607 | /* Hooray for CUR*CNTR differences */ | |
2608 | if (IS_MOBILE(dev) || IS_I9XX(dev)) { | |
2609 | temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT); | |
2610 | temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; | |
2611 | temp |= (pipe << 28); /* Connect to correct pipe */ | |
2612 | } else { | |
2613 | temp &= ~(CURSOR_FORMAT_MASK); | |
2614 | temp |= CURSOR_ENABLE; | |
2615 | temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE; | |
2616 | } | |
79e53945 | 2617 | |
3f8bc370 | 2618 | finish: |
79e53945 JB |
2619 | I915_WRITE(control, temp); |
2620 | I915_WRITE(base, addr); | |
2621 | ||
3f8bc370 | 2622 | if (intel_crtc->cursor_bo) { |
71acb5eb DA |
2623 | if (dev_priv->cursor_needs_physical) { |
2624 | if (intel_crtc->cursor_bo != bo) | |
2625 | i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo); | |
2626 | } else | |
2627 | i915_gem_object_unpin(intel_crtc->cursor_bo); | |
3f8bc370 KH |
2628 | drm_gem_object_unreference(intel_crtc->cursor_bo); |
2629 | } | |
7f9872e0 | 2630 | mutex_unlock(&dev->struct_mutex); |
3f8bc370 KH |
2631 | |
2632 | intel_crtc->cursor_addr = addr; | |
2633 | intel_crtc->cursor_bo = bo; | |
2634 | ||
79e53945 | 2635 | return 0; |
34b8686e DA |
2636 | fail: |
2637 | mutex_lock(&dev->struct_mutex); | |
7f9872e0 | 2638 | fail_locked: |
34b8686e DA |
2639 | drm_gem_object_unreference(bo); |
2640 | mutex_unlock(&dev->struct_mutex); | |
2641 | return ret; | |
79e53945 JB |
2642 | } |
2643 | ||
2644 | static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) | |
2645 | { | |
2646 | struct drm_device *dev = crtc->dev; | |
2647 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2648 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2649 | int pipe = intel_crtc->pipe; | |
2650 | uint32_t temp = 0; | |
2651 | uint32_t adder; | |
2652 | ||
2653 | if (x < 0) { | |
2245fda8 | 2654 | temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; |
79e53945 JB |
2655 | x = -x; |
2656 | } | |
2657 | if (y < 0) { | |
2245fda8 | 2658 | temp |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; |
79e53945 JB |
2659 | y = -y; |
2660 | } | |
2661 | ||
2245fda8 KP |
2662 | temp |= x << CURSOR_X_SHIFT; |
2663 | temp |= y << CURSOR_Y_SHIFT; | |
79e53945 JB |
2664 | |
2665 | adder = intel_crtc->cursor_addr; | |
2666 | I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp); | |
2667 | I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder); | |
2668 | ||
2669 | return 0; | |
2670 | } | |
2671 | ||
2672 | /** Sets the color ramps on behalf of RandR */ | |
2673 | void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, | |
2674 | u16 blue, int regno) | |
2675 | { | |
2676 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2677 | ||
2678 | intel_crtc->lut_r[regno] = red >> 8; | |
2679 | intel_crtc->lut_g[regno] = green >> 8; | |
2680 | intel_crtc->lut_b[regno] = blue >> 8; | |
2681 | } | |
2682 | ||
2683 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, | |
2684 | u16 *blue, uint32_t size) | |
2685 | { | |
2686 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2687 | int i; | |
2688 | ||
2689 | if (size != 256) | |
2690 | return; | |
2691 | ||
2692 | for (i = 0; i < 256; i++) { | |
2693 | intel_crtc->lut_r[i] = red[i] >> 8; | |
2694 | intel_crtc->lut_g[i] = green[i] >> 8; | |
2695 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
2696 | } | |
2697 | ||
2698 | intel_crtc_load_lut(crtc); | |
2699 | } | |
2700 | ||
2701 | /** | |
2702 | * Get a pipe with a simple mode set on it for doing load-based monitor | |
2703 | * detection. | |
2704 | * | |
2705 | * It will be up to the load-detect code to adjust the pipe as appropriate for | |
2706 | * its requirements. The pipe will be connected to no other outputs. | |
2707 | * | |
2708 | * Currently this code will only succeed if there is a pipe with no outputs | |
2709 | * configured for it. In the future, it could choose to temporarily disable | |
2710 | * some outputs to free up a pipe for its use. | |
2711 | * | |
2712 | * \return crtc, or NULL if no pipes are available. | |
2713 | */ | |
2714 | ||
2715 | /* VESA 640x480x72Hz mode to set on the pipe */ | |
2716 | static struct drm_display_mode load_detect_mode = { | |
2717 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
2718 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
2719 | }; | |
2720 | ||
2721 | struct drm_crtc *intel_get_load_detect_pipe(struct intel_output *intel_output, | |
2722 | struct drm_display_mode *mode, | |
2723 | int *dpms_mode) | |
2724 | { | |
2725 | struct intel_crtc *intel_crtc; | |
2726 | struct drm_crtc *possible_crtc; | |
2727 | struct drm_crtc *supported_crtc =NULL; | |
2728 | struct drm_encoder *encoder = &intel_output->enc; | |
2729 | struct drm_crtc *crtc = NULL; | |
2730 | struct drm_device *dev = encoder->dev; | |
2731 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
2732 | struct drm_crtc_helper_funcs *crtc_funcs; | |
2733 | int i = -1; | |
2734 | ||
2735 | /* | |
2736 | * Algorithm gets a little messy: | |
2737 | * - if the connector already has an assigned crtc, use it (but make | |
2738 | * sure it's on first) | |
2739 | * - try to find the first unused crtc that can drive this connector, | |
2740 | * and use that if we find one | |
2741 | * - if there are no unused crtcs available, try to use the first | |
2742 | * one we found that supports the connector | |
2743 | */ | |
2744 | ||
2745 | /* See if we already have a CRTC for this connector */ | |
2746 | if (encoder->crtc) { | |
2747 | crtc = encoder->crtc; | |
2748 | /* Make sure the crtc and connector are running */ | |
2749 | intel_crtc = to_intel_crtc(crtc); | |
2750 | *dpms_mode = intel_crtc->dpms_mode; | |
2751 | if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) { | |
2752 | crtc_funcs = crtc->helper_private; | |
2753 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); | |
2754 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); | |
2755 | } | |
2756 | return crtc; | |
2757 | } | |
2758 | ||
2759 | /* Find an unused one (if possible) */ | |
2760 | list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) { | |
2761 | i++; | |
2762 | if (!(encoder->possible_crtcs & (1 << i))) | |
2763 | continue; | |
2764 | if (!possible_crtc->enabled) { | |
2765 | crtc = possible_crtc; | |
2766 | break; | |
2767 | } | |
2768 | if (!supported_crtc) | |
2769 | supported_crtc = possible_crtc; | |
2770 | } | |
2771 | ||
2772 | /* | |
2773 | * If we didn't find an unused CRTC, don't use any. | |
2774 | */ | |
2775 | if (!crtc) { | |
2776 | return NULL; | |
2777 | } | |
2778 | ||
2779 | encoder->crtc = crtc; | |
03d60699 | 2780 | intel_output->base.encoder = encoder; |
79e53945 JB |
2781 | intel_output->load_detect_temp = true; |
2782 | ||
2783 | intel_crtc = to_intel_crtc(crtc); | |
2784 | *dpms_mode = intel_crtc->dpms_mode; | |
2785 | ||
2786 | if (!crtc->enabled) { | |
2787 | if (!mode) | |
2788 | mode = &load_detect_mode; | |
3c4fdcfb | 2789 | drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb); |
79e53945 JB |
2790 | } else { |
2791 | if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) { | |
2792 | crtc_funcs = crtc->helper_private; | |
2793 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); | |
2794 | } | |
2795 | ||
2796 | /* Add this connector to the crtc */ | |
2797 | encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode); | |
2798 | encoder_funcs->commit(encoder); | |
2799 | } | |
2800 | /* let the connector get through one full cycle before testing */ | |
2801 | intel_wait_for_vblank(dev); | |
2802 | ||
2803 | return crtc; | |
2804 | } | |
2805 | ||
2806 | void intel_release_load_detect_pipe(struct intel_output *intel_output, int dpms_mode) | |
2807 | { | |
2808 | struct drm_encoder *encoder = &intel_output->enc; | |
2809 | struct drm_device *dev = encoder->dev; | |
2810 | struct drm_crtc *crtc = encoder->crtc; | |
2811 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
2812 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; | |
2813 | ||
2814 | if (intel_output->load_detect_temp) { | |
2815 | encoder->crtc = NULL; | |
03d60699 | 2816 | intel_output->base.encoder = NULL; |
79e53945 JB |
2817 | intel_output->load_detect_temp = false; |
2818 | crtc->enabled = drm_helper_crtc_in_use(crtc); | |
2819 | drm_helper_disable_unused_functions(dev); | |
2820 | } | |
2821 | ||
2822 | /* Switch crtc and output back off if necessary */ | |
2823 | if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) { | |
2824 | if (encoder->crtc == crtc) | |
2825 | encoder_funcs->dpms(encoder, dpms_mode); | |
2826 | crtc_funcs->dpms(crtc, dpms_mode); | |
2827 | } | |
2828 | } | |
2829 | ||
2830 | /* Returns the clock of the currently programmed mode of the given pipe. */ | |
2831 | static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc) | |
2832 | { | |
2833 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2834 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2835 | int pipe = intel_crtc->pipe; | |
2836 | u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B); | |
2837 | u32 fp; | |
2838 | intel_clock_t clock; | |
2839 | ||
2840 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
2841 | fp = I915_READ((pipe == 0) ? FPA0 : FPB0); | |
2842 | else | |
2843 | fp = I915_READ((pipe == 0) ? FPA1 : FPB1); | |
2844 | ||
2845 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
2177832f SL |
2846 | if (IS_IGD(dev)) { |
2847 | clock.n = ffs((fp & FP_N_IGD_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
2848 | clock.m2 = (fp & FP_M2_IGD_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2849 | } else { | |
2850 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
2851 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2852 | } | |
2853 | ||
79e53945 | 2854 | if (IS_I9XX(dev)) { |
2177832f SL |
2855 | if (IS_IGD(dev)) |
2856 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_IGD) >> | |
2857 | DPLL_FPA01_P1_POST_DIV_SHIFT_IGD); | |
2858 | else | |
2859 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
2860 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
2861 | ||
2862 | switch (dpll & DPLL_MODE_MASK) { | |
2863 | case DPLLB_MODE_DAC_SERIAL: | |
2864 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
2865 | 5 : 10; | |
2866 | break; | |
2867 | case DPLLB_MODE_LVDS: | |
2868 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
2869 | 7 : 14; | |
2870 | break; | |
2871 | default: | |
2872 | DRM_DEBUG("Unknown DPLL mode %08x in programmed " | |
2873 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); | |
2874 | return 0; | |
2875 | } | |
2876 | ||
2877 | /* XXX: Handle the 100Mhz refclk */ | |
2177832f | 2878 | intel_clock(dev, 96000, &clock); |
79e53945 JB |
2879 | } else { |
2880 | bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN); | |
2881 | ||
2882 | if (is_lvds) { | |
2883 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
2884 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
2885 | clock.p2 = 14; | |
2886 | ||
2887 | if ((dpll & PLL_REF_INPUT_MASK) == | |
2888 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { | |
2889 | /* XXX: might not be 66MHz */ | |
2177832f | 2890 | intel_clock(dev, 66000, &clock); |
79e53945 | 2891 | } else |
2177832f | 2892 | intel_clock(dev, 48000, &clock); |
79e53945 JB |
2893 | } else { |
2894 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
2895 | clock.p1 = 2; | |
2896 | else { | |
2897 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
2898 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
2899 | } | |
2900 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
2901 | clock.p2 = 4; | |
2902 | else | |
2903 | clock.p2 = 2; | |
2904 | ||
2177832f | 2905 | intel_clock(dev, 48000, &clock); |
79e53945 JB |
2906 | } |
2907 | } | |
2908 | ||
2909 | /* XXX: It would be nice to validate the clocks, but we can't reuse | |
2910 | * i830PllIsValid() because it relies on the xf86_config connector | |
2911 | * configuration being accurate, which it isn't necessarily. | |
2912 | */ | |
2913 | ||
2914 | return clock.dot; | |
2915 | } | |
2916 | ||
2917 | /** Returns the currently programmed mode of the given pipe. */ | |
2918 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
2919 | struct drm_crtc *crtc) | |
2920 | { | |
2921 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2922 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2923 | int pipe = intel_crtc->pipe; | |
2924 | struct drm_display_mode *mode; | |
2925 | int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B); | |
2926 | int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B); | |
2927 | int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B); | |
2928 | int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B); | |
2929 | ||
2930 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
2931 | if (!mode) | |
2932 | return NULL; | |
2933 | ||
2934 | mode->clock = intel_crtc_clock_get(dev, crtc); | |
2935 | mode->hdisplay = (htot & 0xffff) + 1; | |
2936 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
2937 | mode->hsync_start = (hsync & 0xffff) + 1; | |
2938 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
2939 | mode->vdisplay = (vtot & 0xffff) + 1; | |
2940 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
2941 | mode->vsync_start = (vsync & 0xffff) + 1; | |
2942 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
2943 | ||
2944 | drm_mode_set_name(mode); | |
2945 | drm_mode_set_crtcinfo(mode, 0); | |
2946 | ||
2947 | return mode; | |
2948 | } | |
2949 | ||
2950 | static void intel_crtc_destroy(struct drm_crtc *crtc) | |
2951 | { | |
2952 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2953 | ||
7ff14559 DA |
2954 | if (intel_crtc->mode_set.mode) |
2955 | drm_mode_destroy(crtc->dev, intel_crtc->mode_set.mode); | |
79e53945 JB |
2956 | drm_crtc_cleanup(crtc); |
2957 | kfree(intel_crtc); | |
2958 | } | |
2959 | ||
2960 | static const struct drm_crtc_helper_funcs intel_helper_funcs = { | |
2961 | .dpms = intel_crtc_dpms, | |
2962 | .mode_fixup = intel_crtc_mode_fixup, | |
2963 | .mode_set = intel_crtc_mode_set, | |
2964 | .mode_set_base = intel_pipe_set_base, | |
2965 | .prepare = intel_crtc_prepare, | |
2966 | .commit = intel_crtc_commit, | |
2967 | }; | |
2968 | ||
2969 | static const struct drm_crtc_funcs intel_crtc_funcs = { | |
2970 | .cursor_set = intel_crtc_cursor_set, | |
2971 | .cursor_move = intel_crtc_cursor_move, | |
2972 | .gamma_set = intel_crtc_gamma_set, | |
2973 | .set_config = drm_crtc_helper_set_config, | |
2974 | .destroy = intel_crtc_destroy, | |
2975 | }; | |
2976 | ||
2977 | ||
b358d0a6 | 2978 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 JB |
2979 | { |
2980 | struct intel_crtc *intel_crtc; | |
2981 | int i; | |
2982 | ||
2983 | intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); | |
2984 | if (intel_crtc == NULL) | |
2985 | return; | |
2986 | ||
2987 | drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs); | |
2988 | ||
2989 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
2990 | intel_crtc->pipe = pipe; | |
7662c8bd | 2991 | intel_crtc->plane = pipe; |
79e53945 JB |
2992 | for (i = 0; i < 256; i++) { |
2993 | intel_crtc->lut_r[i] = i; | |
2994 | intel_crtc->lut_g[i] = i; | |
2995 | intel_crtc->lut_b[i] = i; | |
2996 | } | |
2997 | ||
2998 | intel_crtc->cursor_addr = 0; | |
2999 | intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF; | |
3000 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); | |
3001 | ||
3002 | intel_crtc->mode_set.crtc = &intel_crtc->base; | |
3003 | intel_crtc->mode_set.connectors = (struct drm_connector **)(intel_crtc + 1); | |
3004 | intel_crtc->mode_set.num_connectors = 0; | |
3005 | ||
3006 | if (i915_fbpercrtc) { | |
3007 | ||
3008 | ||
3009 | ||
3010 | } | |
3011 | } | |
3012 | ||
08d7b3d1 CW |
3013 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
3014 | struct drm_file *file_priv) | |
3015 | { | |
3016 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3017 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; | |
3018 | struct drm_crtc *crtc = NULL; | |
3019 | int pipe = -1; | |
3020 | ||
3021 | if (!dev_priv) { | |
3022 | DRM_ERROR("called with no initialization\n"); | |
3023 | return -EINVAL; | |
3024 | } | |
3025 | ||
3026 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
3027 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3028 | if (crtc->base.id == pipe_from_crtc_id->crtc_id) { | |
3029 | pipe = intel_crtc->pipe; | |
3030 | break; | |
3031 | } | |
3032 | } | |
3033 | ||
3034 | if (pipe == -1) { | |
3035 | DRM_ERROR("no such CRTC id\n"); | |
3036 | return -EINVAL; | |
3037 | } | |
3038 | ||
3039 | pipe_from_crtc_id->pipe = pipe; | |
3040 | ||
3041 | return 0; | |
3042 | } | |
3043 | ||
79e53945 JB |
3044 | struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe) |
3045 | { | |
3046 | struct drm_crtc *crtc = NULL; | |
3047 | ||
3048 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
3049 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3050 | if (intel_crtc->pipe == pipe) | |
3051 | break; | |
3052 | } | |
3053 | return crtc; | |
3054 | } | |
3055 | ||
b358d0a6 | 3056 | static int intel_connector_clones(struct drm_device *dev, int type_mask) |
79e53945 JB |
3057 | { |
3058 | int index_mask = 0; | |
3059 | struct drm_connector *connector; | |
3060 | int entry = 0; | |
3061 | ||
3062 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
3063 | struct intel_output *intel_output = to_intel_output(connector); | |
3064 | if (type_mask & (1 << intel_output->type)) | |
3065 | index_mask |= (1 << entry); | |
3066 | entry++; | |
3067 | } | |
3068 | return index_mask; | |
3069 | } | |
3070 | ||
3071 | ||
3072 | static void intel_setup_outputs(struct drm_device *dev) | |
3073 | { | |
725e30ad | 3074 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 JB |
3075 | struct drm_connector *connector; |
3076 | ||
3077 | intel_crt_init(dev); | |
3078 | ||
3079 | /* Set up integrated LVDS */ | |
541998a1 | 3080 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
79e53945 JB |
3081 | intel_lvds_init(dev); |
3082 | ||
2c07245f | 3083 | if (IS_IGDNG(dev)) { |
30ad48b7 ZW |
3084 | int found; |
3085 | ||
3086 | if (I915_READ(HDMIB) & PORT_DETECTED) { | |
3087 | /* check SDVOB */ | |
3088 | /* found = intel_sdvo_init(dev, HDMIB); */ | |
3089 | found = 0; | |
3090 | if (!found) | |
3091 | intel_hdmi_init(dev, HDMIB); | |
5eb08b69 ZW |
3092 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
3093 | intel_dp_init(dev, PCH_DP_B); | |
30ad48b7 ZW |
3094 | } |
3095 | ||
3096 | if (I915_READ(HDMIC) & PORT_DETECTED) | |
3097 | intel_hdmi_init(dev, HDMIC); | |
3098 | ||
3099 | if (I915_READ(HDMID) & PORT_DETECTED) | |
3100 | intel_hdmi_init(dev, HDMID); | |
3101 | ||
5eb08b69 ZW |
3102 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
3103 | intel_dp_init(dev, PCH_DP_C); | |
3104 | ||
3105 | if (I915_READ(PCH_DP_D) & DP_DETECTED) | |
3106 | intel_dp_init(dev, PCH_DP_D); | |
3107 | ||
2c07245f | 3108 | } else if (IS_I9XX(dev)) { |
7d57382e | 3109 | int found; |
13520b05 | 3110 | u32 reg; |
7d57382e | 3111 | |
725e30ad EA |
3112 | if (I915_READ(SDVOB) & SDVO_DETECTED) { |
3113 | found = intel_sdvo_init(dev, SDVOB); | |
3114 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) | |
3115 | intel_hdmi_init(dev, SDVOB); | |
a4fc5ed6 KP |
3116 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) |
3117 | intel_dp_init(dev, DP_B); | |
725e30ad | 3118 | } |
13520b05 KH |
3119 | |
3120 | /* Before G4X SDVOC doesn't have its own detect register */ | |
3121 | if (IS_G4X(dev)) | |
3122 | reg = SDVOC; | |
3123 | else | |
3124 | reg = SDVOB; | |
3125 | ||
3126 | if (I915_READ(reg) & SDVO_DETECTED) { | |
725e30ad EA |
3127 | found = intel_sdvo_init(dev, SDVOC); |
3128 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) | |
3129 | intel_hdmi_init(dev, SDVOC); | |
a4fc5ed6 KP |
3130 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) |
3131 | intel_dp_init(dev, DP_C); | |
725e30ad | 3132 | } |
a4fc5ed6 KP |
3133 | if (SUPPORTS_INTEGRATED_DP(dev) && (I915_READ(DP_D) & DP_DETECTED)) |
3134 | intel_dp_init(dev, DP_D); | |
79e53945 JB |
3135 | } else |
3136 | intel_dvo_init(dev); | |
3137 | ||
2c07245f | 3138 | if (IS_I9XX(dev) && IS_MOBILE(dev) && !IS_IGDNG(dev)) |
79e53945 JB |
3139 | intel_tv_init(dev); |
3140 | ||
3141 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
3142 | struct intel_output *intel_output = to_intel_output(connector); | |
3143 | struct drm_encoder *encoder = &intel_output->enc; | |
3144 | int crtc_mask = 0, clone_mask = 0; | |
3145 | ||
3146 | /* valid crtcs */ | |
3147 | switch(intel_output->type) { | |
7d57382e EA |
3148 | case INTEL_OUTPUT_HDMI: |
3149 | crtc_mask = ((1 << 0)| | |
3150 | (1 << 1)); | |
3151 | clone_mask = ((1 << INTEL_OUTPUT_HDMI)); | |
3152 | break; | |
79e53945 JB |
3153 | case INTEL_OUTPUT_DVO: |
3154 | case INTEL_OUTPUT_SDVO: | |
3155 | crtc_mask = ((1 << 0)| | |
3156 | (1 << 1)); | |
3157 | clone_mask = ((1 << INTEL_OUTPUT_ANALOG) | | |
3158 | (1 << INTEL_OUTPUT_DVO) | | |
3159 | (1 << INTEL_OUTPUT_SDVO)); | |
3160 | break; | |
3161 | case INTEL_OUTPUT_ANALOG: | |
3162 | crtc_mask = ((1 << 0)| | |
3163 | (1 << 1)); | |
3164 | clone_mask = ((1 << INTEL_OUTPUT_ANALOG) | | |
3165 | (1 << INTEL_OUTPUT_DVO) | | |
3166 | (1 << INTEL_OUTPUT_SDVO)); | |
3167 | break; | |
3168 | case INTEL_OUTPUT_LVDS: | |
3169 | crtc_mask = (1 << 1); | |
3170 | clone_mask = (1 << INTEL_OUTPUT_LVDS); | |
3171 | break; | |
3172 | case INTEL_OUTPUT_TVOUT: | |
3173 | crtc_mask = ((1 << 0) | | |
3174 | (1 << 1)); | |
3175 | clone_mask = (1 << INTEL_OUTPUT_TVOUT); | |
3176 | break; | |
a4fc5ed6 KP |
3177 | case INTEL_OUTPUT_DISPLAYPORT: |
3178 | crtc_mask = ((1 << 0) | | |
3179 | (1 << 1)); | |
3180 | clone_mask = (1 << INTEL_OUTPUT_DISPLAYPORT); | |
3181 | break; | |
79e53945 JB |
3182 | } |
3183 | encoder->possible_crtcs = crtc_mask; | |
3184 | encoder->possible_clones = intel_connector_clones(dev, clone_mask); | |
3185 | } | |
3186 | } | |
3187 | ||
3188 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
3189 | { | |
3190 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
3191 | struct drm_device *dev = fb->dev; | |
3192 | ||
3193 | if (fb->fbdev) | |
3194 | intelfb_remove(dev, fb); | |
3195 | ||
3196 | drm_framebuffer_cleanup(fb); | |
3197 | mutex_lock(&dev->struct_mutex); | |
3198 | drm_gem_object_unreference(intel_fb->obj); | |
3199 | mutex_unlock(&dev->struct_mutex); | |
3200 | ||
3201 | kfree(intel_fb); | |
3202 | } | |
3203 | ||
3204 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
3205 | struct drm_file *file_priv, | |
3206 | unsigned int *handle) | |
3207 | { | |
3208 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
3209 | struct drm_gem_object *object = intel_fb->obj; | |
3210 | ||
3211 | return drm_gem_handle_create(file_priv, object, handle); | |
3212 | } | |
3213 | ||
3214 | static const struct drm_framebuffer_funcs intel_fb_funcs = { | |
3215 | .destroy = intel_user_framebuffer_destroy, | |
3216 | .create_handle = intel_user_framebuffer_create_handle, | |
3217 | }; | |
3218 | ||
3219 | int intel_framebuffer_create(struct drm_device *dev, | |
3220 | struct drm_mode_fb_cmd *mode_cmd, | |
3221 | struct drm_framebuffer **fb, | |
3222 | struct drm_gem_object *obj) | |
3223 | { | |
3224 | struct intel_framebuffer *intel_fb; | |
3225 | int ret; | |
3226 | ||
3227 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
3228 | if (!intel_fb) | |
3229 | return -ENOMEM; | |
3230 | ||
3231 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); | |
3232 | if (ret) { | |
3233 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
3234 | return ret; | |
3235 | } | |
3236 | ||
3237 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); | |
3238 | ||
3239 | intel_fb->obj = obj; | |
3240 | ||
3241 | *fb = &intel_fb->base; | |
3242 | ||
3243 | return 0; | |
3244 | } | |
3245 | ||
3246 | ||
3247 | static struct drm_framebuffer * | |
3248 | intel_user_framebuffer_create(struct drm_device *dev, | |
3249 | struct drm_file *filp, | |
3250 | struct drm_mode_fb_cmd *mode_cmd) | |
3251 | { | |
3252 | struct drm_gem_object *obj; | |
3253 | struct drm_framebuffer *fb; | |
3254 | int ret; | |
3255 | ||
3256 | obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle); | |
3257 | if (!obj) | |
3258 | return NULL; | |
3259 | ||
3260 | ret = intel_framebuffer_create(dev, mode_cmd, &fb, obj); | |
3261 | if (ret) { | |
496818f0 | 3262 | mutex_lock(&dev->struct_mutex); |
79e53945 | 3263 | drm_gem_object_unreference(obj); |
496818f0 | 3264 | mutex_unlock(&dev->struct_mutex); |
79e53945 JB |
3265 | return NULL; |
3266 | } | |
3267 | ||
3268 | return fb; | |
3269 | } | |
3270 | ||
79e53945 | 3271 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 JB |
3272 | .fb_create = intel_user_framebuffer_create, |
3273 | .fb_changed = intelfb_probe, | |
3274 | }; | |
3275 | ||
3276 | void intel_modeset_init(struct drm_device *dev) | |
3277 | { | |
3278 | int num_pipe; | |
3279 | int i; | |
3280 | ||
3281 | drm_mode_config_init(dev); | |
3282 | ||
3283 | dev->mode_config.min_width = 0; | |
3284 | dev->mode_config.min_height = 0; | |
3285 | ||
3286 | dev->mode_config.funcs = (void *)&intel_mode_funcs; | |
3287 | ||
3288 | if (IS_I965G(dev)) { | |
3289 | dev->mode_config.max_width = 8192; | |
3290 | dev->mode_config.max_height = 8192; | |
5e4d6fa7 KP |
3291 | } else if (IS_I9XX(dev)) { |
3292 | dev->mode_config.max_width = 4096; | |
3293 | dev->mode_config.max_height = 4096; | |
79e53945 JB |
3294 | } else { |
3295 | dev->mode_config.max_width = 2048; | |
3296 | dev->mode_config.max_height = 2048; | |
3297 | } | |
3298 | ||
3299 | /* set memory base */ | |
3300 | if (IS_I9XX(dev)) | |
3301 | dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2); | |
3302 | else | |
3303 | dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0); | |
3304 | ||
3305 | if (IS_MOBILE(dev) || IS_I9XX(dev)) | |
3306 | num_pipe = 2; | |
3307 | else | |
3308 | num_pipe = 1; | |
3309 | DRM_DEBUG("%d display pipe%s available.\n", | |
3310 | num_pipe, num_pipe > 1 ? "s" : ""); | |
3311 | ||
3312 | for (i = 0; i < num_pipe; i++) { | |
3313 | intel_crtc_init(dev, i); | |
3314 | } | |
3315 | ||
3316 | intel_setup_outputs(dev); | |
3317 | } | |
3318 | ||
3319 | void intel_modeset_cleanup(struct drm_device *dev) | |
3320 | { | |
3321 | drm_mode_config_cleanup(dev); | |
3322 | } | |
3323 | ||
3324 | ||
3325 | /* current intel driver doesn't take advantage of encoders | |
3326 | always give back the encoder for the connector | |
3327 | */ | |
3328 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) | |
3329 | { | |
3330 | struct intel_output *intel_output = to_intel_output(connector); | |
3331 | ||
3332 | return &intel_output->enc; | |
3333 | } |