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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
e5510fac | 39 | #include "i915_trace.h" |
319c1d42 | 40 | #include <drm/drm_atomic.h> |
c196e1d6 | 41 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
42 | #include <drm/drm_dp_helper.h> |
43 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
44 | #include <drm/drm_plane_helper.h> |
45 | #include <drm/drm_rect.h> | |
c0f372b3 | 46 | #include <linux/dma_remapping.h> |
79e53945 | 47 | |
465c120c | 48 | /* Primary plane formats for gen <= 3 */ |
568db4f2 | 49 | static const uint32_t i8xx_primary_formats[] = { |
67fe7dc5 DL |
50 | DRM_FORMAT_C8, |
51 | DRM_FORMAT_RGB565, | |
465c120c | 52 | DRM_FORMAT_XRGB1555, |
67fe7dc5 | 53 | DRM_FORMAT_XRGB8888, |
465c120c MR |
54 | }; |
55 | ||
56 | /* Primary plane formats for gen >= 4 */ | |
568db4f2 | 57 | static const uint32_t i965_primary_formats[] = { |
6c0fd451 DL |
58 | DRM_FORMAT_C8, |
59 | DRM_FORMAT_RGB565, | |
60 | DRM_FORMAT_XRGB8888, | |
61 | DRM_FORMAT_XBGR8888, | |
62 | DRM_FORMAT_XRGB2101010, | |
63 | DRM_FORMAT_XBGR2101010, | |
64 | }; | |
65 | ||
66 | static const uint32_t skl_primary_formats[] = { | |
67fe7dc5 DL |
67 | DRM_FORMAT_C8, |
68 | DRM_FORMAT_RGB565, | |
69 | DRM_FORMAT_XRGB8888, | |
465c120c | 70 | DRM_FORMAT_XBGR8888, |
67fe7dc5 | 71 | DRM_FORMAT_ARGB8888, |
465c120c MR |
72 | DRM_FORMAT_ABGR8888, |
73 | DRM_FORMAT_XRGB2101010, | |
465c120c | 74 | DRM_FORMAT_XBGR2101010, |
ea916ea0 KM |
75 | DRM_FORMAT_YUYV, |
76 | DRM_FORMAT_YVYU, | |
77 | DRM_FORMAT_UYVY, | |
78 | DRM_FORMAT_VYUY, | |
465c120c MR |
79 | }; |
80 | ||
3d7d6510 MR |
81 | /* Cursor formats */ |
82 | static const uint32_t intel_cursor_formats[] = { | |
83 | DRM_FORMAT_ARGB8888, | |
84 | }; | |
85 | ||
6b383a7f | 86 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
79e53945 | 87 | |
f1f644dc | 88 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 89 | struct intel_crtc_state *pipe_config); |
18442d08 | 90 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 91 | struct intel_crtc_state *pipe_config); |
f1f644dc | 92 | |
eb1bfe80 JB |
93 | static int intel_framebuffer_init(struct drm_device *dev, |
94 | struct intel_framebuffer *ifb, | |
95 | struct drm_mode_fb_cmd2 *mode_cmd, | |
96 | struct drm_i915_gem_object *obj); | |
5b18e57c DV |
97 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
98 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
29407aab | 99 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
f769cd24 VK |
100 | struct intel_link_m_n *m_n, |
101 | struct intel_link_m_n *m2_n2); | |
29407aab | 102 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
229fca97 DV |
103 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
104 | static void intel_set_pipe_csc(struct drm_crtc *crtc); | |
d288f65f | 105 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 106 | const struct intel_crtc_state *pipe_config); |
d288f65f | 107 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 108 | const struct intel_crtc_state *pipe_config); |
613d2b27 ML |
109 | static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); |
110 | static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); | |
549e2bfb CK |
111 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
112 | struct intel_crtc_state *crtc_state); | |
5ab7b0b7 ID |
113 | static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, |
114 | int num_connectors); | |
bfd16b2a ML |
115 | static void skylake_pfit_enable(struct intel_crtc *crtc); |
116 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force); | |
117 | static void ironlake_pfit_enable(struct intel_crtc *crtc); | |
043e9bda | 118 | static void intel_modeset_setup_hw_state(struct drm_device *dev); |
e7457a9a | 119 | |
79e53945 | 120 | typedef struct { |
0206e353 | 121 | int min, max; |
79e53945 JB |
122 | } intel_range_t; |
123 | ||
124 | typedef struct { | |
0206e353 AJ |
125 | int dot_limit; |
126 | int p2_slow, p2_fast; | |
79e53945 JB |
127 | } intel_p2_t; |
128 | ||
d4906093 ML |
129 | typedef struct intel_limit intel_limit_t; |
130 | struct intel_limit { | |
0206e353 AJ |
131 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
132 | intel_p2_t p2; | |
d4906093 | 133 | }; |
79e53945 | 134 | |
d2acd215 DV |
135 | int |
136 | intel_pch_rawclk(struct drm_device *dev) | |
137 | { | |
138 | struct drm_i915_private *dev_priv = dev->dev_private; | |
139 | ||
140 | WARN_ON(!HAS_PCH_SPLIT(dev)); | |
141 | ||
142 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; | |
143 | } | |
144 | ||
79e50a4f JN |
145 | /* hrawclock is 1/4 the FSB frequency */ |
146 | int intel_hrawclk(struct drm_device *dev) | |
147 | { | |
148 | struct drm_i915_private *dev_priv = dev->dev_private; | |
149 | uint32_t clkcfg; | |
150 | ||
151 | /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */ | |
152 | if (IS_VALLEYVIEW(dev)) | |
153 | return 200; | |
154 | ||
155 | clkcfg = I915_READ(CLKCFG); | |
156 | switch (clkcfg & CLKCFG_FSB_MASK) { | |
157 | case CLKCFG_FSB_400: | |
158 | return 100; | |
159 | case CLKCFG_FSB_533: | |
160 | return 133; | |
161 | case CLKCFG_FSB_667: | |
162 | return 166; | |
163 | case CLKCFG_FSB_800: | |
164 | return 200; | |
165 | case CLKCFG_FSB_1067: | |
166 | return 266; | |
167 | case CLKCFG_FSB_1333: | |
168 | return 333; | |
169 | /* these two are just a guess; one of them might be right */ | |
170 | case CLKCFG_FSB_1600: | |
171 | case CLKCFG_FSB_1600_ALT: | |
172 | return 400; | |
173 | default: | |
174 | return 133; | |
175 | } | |
176 | } | |
177 | ||
021357ac CW |
178 | static inline u32 /* units of 100MHz */ |
179 | intel_fdi_link_freq(struct drm_device *dev) | |
180 | { | |
8b99e68c CW |
181 | if (IS_GEN5(dev)) { |
182 | struct drm_i915_private *dev_priv = dev->dev_private; | |
183 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
184 | } else | |
185 | return 27; | |
021357ac CW |
186 | } |
187 | ||
5d536e28 | 188 | static const intel_limit_t intel_limits_i8xx_dac = { |
0206e353 | 189 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 190 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 191 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
192 | .m = { .min = 96, .max = 140 }, |
193 | .m1 = { .min = 18, .max = 26 }, | |
194 | .m2 = { .min = 6, .max = 16 }, | |
195 | .p = { .min = 4, .max = 128 }, | |
196 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
197 | .p2 = { .dot_limit = 165000, |
198 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
199 | }; |
200 | ||
5d536e28 DV |
201 | static const intel_limit_t intel_limits_i8xx_dvo = { |
202 | .dot = { .min = 25000, .max = 350000 }, | |
9c333719 | 203 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 204 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
205 | .m = { .min = 96, .max = 140 }, |
206 | .m1 = { .min = 18, .max = 26 }, | |
207 | .m2 = { .min = 6, .max = 16 }, | |
208 | .p = { .min = 4, .max = 128 }, | |
209 | .p1 = { .min = 2, .max = 33 }, | |
210 | .p2 = { .dot_limit = 165000, | |
211 | .p2_slow = 4, .p2_fast = 4 }, | |
212 | }; | |
213 | ||
e4b36699 | 214 | static const intel_limit_t intel_limits_i8xx_lvds = { |
0206e353 | 215 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 216 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 217 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
218 | .m = { .min = 96, .max = 140 }, |
219 | .m1 = { .min = 18, .max = 26 }, | |
220 | .m2 = { .min = 6, .max = 16 }, | |
221 | .p = { .min = 4, .max = 128 }, | |
222 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
223 | .p2 = { .dot_limit = 165000, |
224 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 225 | }; |
273e27ca | 226 | |
e4b36699 | 227 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
228 | .dot = { .min = 20000, .max = 400000 }, |
229 | .vco = { .min = 1400000, .max = 2800000 }, | |
230 | .n = { .min = 1, .max = 6 }, | |
231 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
232 | .m1 = { .min = 8, .max = 18 }, |
233 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
234 | .p = { .min = 5, .max = 80 }, |
235 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
236 | .p2 = { .dot_limit = 200000, |
237 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
238 | }; |
239 | ||
240 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
241 | .dot = { .min = 20000, .max = 400000 }, |
242 | .vco = { .min = 1400000, .max = 2800000 }, | |
243 | .n = { .min = 1, .max = 6 }, | |
244 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
245 | .m1 = { .min = 8, .max = 18 }, |
246 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
247 | .p = { .min = 7, .max = 98 }, |
248 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
249 | .p2 = { .dot_limit = 112000, |
250 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
251 | }; |
252 | ||
273e27ca | 253 | |
e4b36699 | 254 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
255 | .dot = { .min = 25000, .max = 270000 }, |
256 | .vco = { .min = 1750000, .max = 3500000}, | |
257 | .n = { .min = 1, .max = 4 }, | |
258 | .m = { .min = 104, .max = 138 }, | |
259 | .m1 = { .min = 17, .max = 23 }, | |
260 | .m2 = { .min = 5, .max = 11 }, | |
261 | .p = { .min = 10, .max = 30 }, | |
262 | .p1 = { .min = 1, .max = 3}, | |
263 | .p2 = { .dot_limit = 270000, | |
264 | .p2_slow = 10, | |
265 | .p2_fast = 10 | |
044c7c41 | 266 | }, |
e4b36699 KP |
267 | }; |
268 | ||
269 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
270 | .dot = { .min = 22000, .max = 400000 }, |
271 | .vco = { .min = 1750000, .max = 3500000}, | |
272 | .n = { .min = 1, .max = 4 }, | |
273 | .m = { .min = 104, .max = 138 }, | |
274 | .m1 = { .min = 16, .max = 23 }, | |
275 | .m2 = { .min = 5, .max = 11 }, | |
276 | .p = { .min = 5, .max = 80 }, | |
277 | .p1 = { .min = 1, .max = 8}, | |
278 | .p2 = { .dot_limit = 165000, | |
279 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
280 | }; |
281 | ||
282 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
283 | .dot = { .min = 20000, .max = 115000 }, |
284 | .vco = { .min = 1750000, .max = 3500000 }, | |
285 | .n = { .min = 1, .max = 3 }, | |
286 | .m = { .min = 104, .max = 138 }, | |
287 | .m1 = { .min = 17, .max = 23 }, | |
288 | .m2 = { .min = 5, .max = 11 }, | |
289 | .p = { .min = 28, .max = 112 }, | |
290 | .p1 = { .min = 2, .max = 8 }, | |
291 | .p2 = { .dot_limit = 0, | |
292 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 293 | }, |
e4b36699 KP |
294 | }; |
295 | ||
296 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
297 | .dot = { .min = 80000, .max = 224000 }, |
298 | .vco = { .min = 1750000, .max = 3500000 }, | |
299 | .n = { .min = 1, .max = 3 }, | |
300 | .m = { .min = 104, .max = 138 }, | |
301 | .m1 = { .min = 17, .max = 23 }, | |
302 | .m2 = { .min = 5, .max = 11 }, | |
303 | .p = { .min = 14, .max = 42 }, | |
304 | .p1 = { .min = 2, .max = 6 }, | |
305 | .p2 = { .dot_limit = 0, | |
306 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 307 | }, |
e4b36699 KP |
308 | }; |
309 | ||
f2b115e6 | 310 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
311 | .dot = { .min = 20000, .max = 400000}, |
312 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 313 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
314 | .n = { .min = 3, .max = 6 }, |
315 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 316 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
317 | .m1 = { .min = 0, .max = 0 }, |
318 | .m2 = { .min = 0, .max = 254 }, | |
319 | .p = { .min = 5, .max = 80 }, | |
320 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
321 | .p2 = { .dot_limit = 200000, |
322 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
323 | }; |
324 | ||
f2b115e6 | 325 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
326 | .dot = { .min = 20000, .max = 400000 }, |
327 | .vco = { .min = 1700000, .max = 3500000 }, | |
328 | .n = { .min = 3, .max = 6 }, | |
329 | .m = { .min = 2, .max = 256 }, | |
330 | .m1 = { .min = 0, .max = 0 }, | |
331 | .m2 = { .min = 0, .max = 254 }, | |
332 | .p = { .min = 7, .max = 112 }, | |
333 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
334 | .p2 = { .dot_limit = 112000, |
335 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
336 | }; |
337 | ||
273e27ca EA |
338 | /* Ironlake / Sandybridge |
339 | * | |
340 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
341 | * the range value for them is (actual_value - 2). | |
342 | */ | |
b91ad0ec | 343 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
344 | .dot = { .min = 25000, .max = 350000 }, |
345 | .vco = { .min = 1760000, .max = 3510000 }, | |
346 | .n = { .min = 1, .max = 5 }, | |
347 | .m = { .min = 79, .max = 127 }, | |
348 | .m1 = { .min = 12, .max = 22 }, | |
349 | .m2 = { .min = 5, .max = 9 }, | |
350 | .p = { .min = 5, .max = 80 }, | |
351 | .p1 = { .min = 1, .max = 8 }, | |
352 | .p2 = { .dot_limit = 225000, | |
353 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
354 | }; |
355 | ||
b91ad0ec | 356 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
357 | .dot = { .min = 25000, .max = 350000 }, |
358 | .vco = { .min = 1760000, .max = 3510000 }, | |
359 | .n = { .min = 1, .max = 3 }, | |
360 | .m = { .min = 79, .max = 118 }, | |
361 | .m1 = { .min = 12, .max = 22 }, | |
362 | .m2 = { .min = 5, .max = 9 }, | |
363 | .p = { .min = 28, .max = 112 }, | |
364 | .p1 = { .min = 2, .max = 8 }, | |
365 | .p2 = { .dot_limit = 225000, | |
366 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
367 | }; |
368 | ||
369 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
370 | .dot = { .min = 25000, .max = 350000 }, |
371 | .vco = { .min = 1760000, .max = 3510000 }, | |
372 | .n = { .min = 1, .max = 3 }, | |
373 | .m = { .min = 79, .max = 127 }, | |
374 | .m1 = { .min = 12, .max = 22 }, | |
375 | .m2 = { .min = 5, .max = 9 }, | |
376 | .p = { .min = 14, .max = 56 }, | |
377 | .p1 = { .min = 2, .max = 8 }, | |
378 | .p2 = { .dot_limit = 225000, | |
379 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
380 | }; |
381 | ||
273e27ca | 382 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 383 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
384 | .dot = { .min = 25000, .max = 350000 }, |
385 | .vco = { .min = 1760000, .max = 3510000 }, | |
386 | .n = { .min = 1, .max = 2 }, | |
387 | .m = { .min = 79, .max = 126 }, | |
388 | .m1 = { .min = 12, .max = 22 }, | |
389 | .m2 = { .min = 5, .max = 9 }, | |
390 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 391 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
392 | .p2 = { .dot_limit = 225000, |
393 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
394 | }; |
395 | ||
396 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
397 | .dot = { .min = 25000, .max = 350000 }, |
398 | .vco = { .min = 1760000, .max = 3510000 }, | |
399 | .n = { .min = 1, .max = 3 }, | |
400 | .m = { .min = 79, .max = 126 }, | |
401 | .m1 = { .min = 12, .max = 22 }, | |
402 | .m2 = { .min = 5, .max = 9 }, | |
403 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 404 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
405 | .p2 = { .dot_limit = 225000, |
406 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
407 | }; |
408 | ||
dc730512 | 409 | static const intel_limit_t intel_limits_vlv = { |
f01b7962 VS |
410 | /* |
411 | * These are the data rate limits (measured in fast clocks) | |
412 | * since those are the strictest limits we have. The fast | |
413 | * clock and actual rate limits are more relaxed, so checking | |
414 | * them would make no difference. | |
415 | */ | |
416 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 417 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 418 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
419 | .m1 = { .min = 2, .max = 3 }, |
420 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 421 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 422 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
423 | }; |
424 | ||
ef9348c8 CML |
425 | static const intel_limit_t intel_limits_chv = { |
426 | /* | |
427 | * These are the data rate limits (measured in fast clocks) | |
428 | * since those are the strictest limits we have. The fast | |
429 | * clock and actual rate limits are more relaxed, so checking | |
430 | * them would make no difference. | |
431 | */ | |
432 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
17fe1021 | 433 | .vco = { .min = 4800000, .max = 6480000 }, |
ef9348c8 CML |
434 | .n = { .min = 1, .max = 1 }, |
435 | .m1 = { .min = 2, .max = 2 }, | |
436 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
437 | .p1 = { .min = 2, .max = 4 }, | |
438 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
439 | }; | |
440 | ||
5ab7b0b7 ID |
441 | static const intel_limit_t intel_limits_bxt = { |
442 | /* FIXME: find real dot limits */ | |
443 | .dot = { .min = 0, .max = INT_MAX }, | |
e6292556 | 444 | .vco = { .min = 4800000, .max = 6700000 }, |
5ab7b0b7 ID |
445 | .n = { .min = 1, .max = 1 }, |
446 | .m1 = { .min = 2, .max = 2 }, | |
447 | /* FIXME: find real m2 limits */ | |
448 | .m2 = { .min = 2 << 22, .max = 255 << 22 }, | |
449 | .p1 = { .min = 2, .max = 4 }, | |
450 | .p2 = { .p2_slow = 1, .p2_fast = 20 }, | |
451 | }; | |
452 | ||
cdba954e ACO |
453 | static bool |
454 | needs_modeset(struct drm_crtc_state *state) | |
455 | { | |
fc596660 | 456 | return drm_atomic_crtc_needs_modeset(state); |
cdba954e ACO |
457 | } |
458 | ||
e0638cdf PZ |
459 | /** |
460 | * Returns whether any output on the specified pipe is of the specified type | |
461 | */ | |
4093561b | 462 | bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type) |
e0638cdf | 463 | { |
409ee761 | 464 | struct drm_device *dev = crtc->base.dev; |
e0638cdf PZ |
465 | struct intel_encoder *encoder; |
466 | ||
409ee761 | 467 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
e0638cdf PZ |
468 | if (encoder->type == type) |
469 | return true; | |
470 | ||
471 | return false; | |
472 | } | |
473 | ||
d0737e1d ACO |
474 | /** |
475 | * Returns whether any output on the specified pipe will have the specified | |
476 | * type after a staged modeset is complete, i.e., the same as | |
477 | * intel_pipe_has_type() but looking at encoder->new_crtc instead of | |
478 | * encoder->crtc. | |
479 | */ | |
a93e255f ACO |
480 | static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state, |
481 | int type) | |
d0737e1d | 482 | { |
a93e255f | 483 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 484 | struct drm_connector *connector; |
a93e255f | 485 | struct drm_connector_state *connector_state; |
d0737e1d | 486 | struct intel_encoder *encoder; |
a93e255f ACO |
487 | int i, num_connectors = 0; |
488 | ||
da3ced29 | 489 | for_each_connector_in_state(state, connector, connector_state, i) { |
a93e255f ACO |
490 | if (connector_state->crtc != crtc_state->base.crtc) |
491 | continue; | |
492 | ||
493 | num_connectors++; | |
d0737e1d | 494 | |
a93e255f ACO |
495 | encoder = to_intel_encoder(connector_state->best_encoder); |
496 | if (encoder->type == type) | |
d0737e1d | 497 | return true; |
a93e255f ACO |
498 | } |
499 | ||
500 | WARN_ON(num_connectors == 0); | |
d0737e1d ACO |
501 | |
502 | return false; | |
503 | } | |
504 | ||
a93e255f ACO |
505 | static const intel_limit_t * |
506 | intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk) | |
2c07245f | 507 | { |
a93e255f | 508 | struct drm_device *dev = crtc_state->base.crtc->dev; |
2c07245f | 509 | const intel_limit_t *limit; |
b91ad0ec | 510 | |
a93e255f | 511 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 512 | if (intel_is_dual_link_lvds(dev)) { |
1b894b59 | 513 | if (refclk == 100000) |
b91ad0ec ZW |
514 | limit = &intel_limits_ironlake_dual_lvds_100m; |
515 | else | |
516 | limit = &intel_limits_ironlake_dual_lvds; | |
517 | } else { | |
1b894b59 | 518 | if (refclk == 100000) |
b91ad0ec ZW |
519 | limit = &intel_limits_ironlake_single_lvds_100m; |
520 | else | |
521 | limit = &intel_limits_ironlake_single_lvds; | |
522 | } | |
c6bb3538 | 523 | } else |
b91ad0ec | 524 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
525 | |
526 | return limit; | |
527 | } | |
528 | ||
a93e255f ACO |
529 | static const intel_limit_t * |
530 | intel_g4x_limit(struct intel_crtc_state *crtc_state) | |
044c7c41 | 531 | { |
a93e255f | 532 | struct drm_device *dev = crtc_state->base.crtc->dev; |
044c7c41 ML |
533 | const intel_limit_t *limit; |
534 | ||
a93e255f | 535 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 536 | if (intel_is_dual_link_lvds(dev)) |
e4b36699 | 537 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 | 538 | else |
e4b36699 | 539 | limit = &intel_limits_g4x_single_channel_lvds; |
a93e255f ACO |
540 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) || |
541 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 542 | limit = &intel_limits_g4x_hdmi; |
a93e255f | 543 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 544 | limit = &intel_limits_g4x_sdvo; |
044c7c41 | 545 | } else /* The option is for other outputs */ |
e4b36699 | 546 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
547 | |
548 | return limit; | |
549 | } | |
550 | ||
a93e255f ACO |
551 | static const intel_limit_t * |
552 | intel_limit(struct intel_crtc_state *crtc_state, int refclk) | |
79e53945 | 553 | { |
a93e255f | 554 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 JB |
555 | const intel_limit_t *limit; |
556 | ||
5ab7b0b7 ID |
557 | if (IS_BROXTON(dev)) |
558 | limit = &intel_limits_bxt; | |
559 | else if (HAS_PCH_SPLIT(dev)) | |
a93e255f | 560 | limit = intel_ironlake_limit(crtc_state, refclk); |
2c07245f | 561 | else if (IS_G4X(dev)) { |
a93e255f | 562 | limit = intel_g4x_limit(crtc_state); |
f2b115e6 | 563 | } else if (IS_PINEVIEW(dev)) { |
a93e255f | 564 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 565 | limit = &intel_limits_pineview_lvds; |
2177832f | 566 | else |
f2b115e6 | 567 | limit = &intel_limits_pineview_sdvo; |
ef9348c8 CML |
568 | } else if (IS_CHERRYVIEW(dev)) { |
569 | limit = &intel_limits_chv; | |
a0c4da24 | 570 | } else if (IS_VALLEYVIEW(dev)) { |
dc730512 | 571 | limit = &intel_limits_vlv; |
a6c45cf0 | 572 | } else if (!IS_GEN2(dev)) { |
a93e255f | 573 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
a6c45cf0 CW |
574 | limit = &intel_limits_i9xx_lvds; |
575 | else | |
576 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 | 577 | } else { |
a93e255f | 578 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
e4b36699 | 579 | limit = &intel_limits_i8xx_lvds; |
a93e255f | 580 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
e4b36699 | 581 | limit = &intel_limits_i8xx_dvo; |
5d536e28 DV |
582 | else |
583 | limit = &intel_limits_i8xx_dac; | |
79e53945 JB |
584 | } |
585 | return limit; | |
586 | } | |
587 | ||
dccbea3b ID |
588 | /* |
589 | * Platform specific helpers to calculate the port PLL loopback- (clock.m), | |
590 | * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast | |
591 | * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic. | |
592 | * The helpers' return value is the rate of the clock that is fed to the | |
593 | * display engine's pipe which can be the above fast dot clock rate or a | |
594 | * divided-down version of it. | |
595 | */ | |
f2b115e6 | 596 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
dccbea3b | 597 | static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock) |
79e53945 | 598 | { |
2177832f SL |
599 | clock->m = clock->m2 + 2; |
600 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e | 601 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
dccbea3b | 602 | return 0; |
fb03ac01 VS |
603 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
604 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
605 | |
606 | return clock->dot; | |
2177832f SL |
607 | } |
608 | ||
7429e9d4 DV |
609 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
610 | { | |
611 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
612 | } | |
613 | ||
dccbea3b | 614 | static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock) |
2177832f | 615 | { |
7429e9d4 | 616 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 617 | clock->p = clock->p1 * clock->p2; |
ed5ca77e | 618 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
dccbea3b | 619 | return 0; |
fb03ac01 VS |
620 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
621 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
622 | |
623 | return clock->dot; | |
79e53945 JB |
624 | } |
625 | ||
dccbea3b | 626 | static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock) |
589eca67 ID |
627 | { |
628 | clock->m = clock->m1 * clock->m2; | |
629 | clock->p = clock->p1 * clock->p2; | |
630 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 631 | return 0; |
589eca67 ID |
632 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
633 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
634 | |
635 | return clock->dot / 5; | |
589eca67 ID |
636 | } |
637 | ||
dccbea3b | 638 | int chv_calc_dpll_params(int refclk, intel_clock_t *clock) |
ef9348c8 CML |
639 | { |
640 | clock->m = clock->m1 * clock->m2; | |
641 | clock->p = clock->p1 * clock->p2; | |
642 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 643 | return 0; |
ef9348c8 CML |
644 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, |
645 | clock->n << 22); | |
646 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
647 | |
648 | return clock->dot / 5; | |
ef9348c8 CML |
649 | } |
650 | ||
7c04d1d9 | 651 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
652 | /** |
653 | * Returns whether the given set of divisors are valid for a given refclk with | |
654 | * the given connectors. | |
655 | */ | |
656 | ||
1b894b59 CW |
657 | static bool intel_PLL_is_valid(struct drm_device *dev, |
658 | const intel_limit_t *limit, | |
659 | const intel_clock_t *clock) | |
79e53945 | 660 | { |
f01b7962 VS |
661 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
662 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 663 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 664 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 665 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 666 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 667 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 668 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 | 669 | |
5ab7b0b7 | 670 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) |
f01b7962 VS |
671 | if (clock->m1 <= clock->m2) |
672 | INTELPllInvalid("m1 <= m2\n"); | |
673 | ||
5ab7b0b7 | 674 | if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) { |
f01b7962 VS |
675 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
676 | INTELPllInvalid("p out of range\n"); | |
677 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
678 | INTELPllInvalid("m out of range\n"); | |
679 | } | |
680 | ||
79e53945 | 681 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 682 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
683 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
684 | * connector, etc., rather than just a single range. | |
685 | */ | |
686 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 687 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
688 | |
689 | return true; | |
690 | } | |
691 | ||
3b1429d9 VS |
692 | static int |
693 | i9xx_select_p2_div(const intel_limit_t *limit, | |
694 | const struct intel_crtc_state *crtc_state, | |
695 | int target) | |
79e53945 | 696 | { |
3b1429d9 | 697 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 | 698 | |
a93e255f | 699 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 700 | /* |
a210b028 DV |
701 | * For LVDS just rely on its current settings for dual-channel. |
702 | * We haven't figured out how to reliably set up different | |
703 | * single/dual channel state, if we even can. | |
79e53945 | 704 | */ |
1974cad0 | 705 | if (intel_is_dual_link_lvds(dev)) |
3b1429d9 | 706 | return limit->p2.p2_fast; |
79e53945 | 707 | else |
3b1429d9 | 708 | return limit->p2.p2_slow; |
79e53945 JB |
709 | } else { |
710 | if (target < limit->p2.dot_limit) | |
3b1429d9 | 711 | return limit->p2.p2_slow; |
79e53945 | 712 | else |
3b1429d9 | 713 | return limit->p2.p2_fast; |
79e53945 | 714 | } |
3b1429d9 VS |
715 | } |
716 | ||
717 | static bool | |
718 | i9xx_find_best_dpll(const intel_limit_t *limit, | |
719 | struct intel_crtc_state *crtc_state, | |
720 | int target, int refclk, intel_clock_t *match_clock, | |
721 | intel_clock_t *best_clock) | |
722 | { | |
723 | struct drm_device *dev = crtc_state->base.crtc->dev; | |
724 | intel_clock_t clock; | |
725 | int err = target; | |
79e53945 | 726 | |
0206e353 | 727 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 728 | |
3b1429d9 VS |
729 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
730 | ||
42158660 ZY |
731 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
732 | clock.m1++) { | |
733 | for (clock.m2 = limit->m2.min; | |
734 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 735 | if (clock.m2 >= clock.m1) |
42158660 ZY |
736 | break; |
737 | for (clock.n = limit->n.min; | |
738 | clock.n <= limit->n.max; clock.n++) { | |
739 | for (clock.p1 = limit->p1.min; | |
740 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
741 | int this_err; |
742 | ||
dccbea3b | 743 | i9xx_calc_dpll_params(refclk, &clock); |
ac58c3f0 DV |
744 | if (!intel_PLL_is_valid(dev, limit, |
745 | &clock)) | |
746 | continue; | |
747 | if (match_clock && | |
748 | clock.p != match_clock->p) | |
749 | continue; | |
750 | ||
751 | this_err = abs(clock.dot - target); | |
752 | if (this_err < err) { | |
753 | *best_clock = clock; | |
754 | err = this_err; | |
755 | } | |
756 | } | |
757 | } | |
758 | } | |
759 | } | |
760 | ||
761 | return (err != target); | |
762 | } | |
763 | ||
764 | static bool | |
a93e255f ACO |
765 | pnv_find_best_dpll(const intel_limit_t *limit, |
766 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
767 | int target, int refclk, intel_clock_t *match_clock, |
768 | intel_clock_t *best_clock) | |
79e53945 | 769 | { |
3b1429d9 | 770 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 | 771 | intel_clock_t clock; |
79e53945 JB |
772 | int err = target; |
773 | ||
0206e353 | 774 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 775 | |
3b1429d9 VS |
776 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
777 | ||
42158660 ZY |
778 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
779 | clock.m1++) { | |
780 | for (clock.m2 = limit->m2.min; | |
781 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
782 | for (clock.n = limit->n.min; |
783 | clock.n <= limit->n.max; clock.n++) { | |
784 | for (clock.p1 = limit->p1.min; | |
785 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
786 | int this_err; |
787 | ||
dccbea3b | 788 | pnv_calc_dpll_params(refclk, &clock); |
1b894b59 CW |
789 | if (!intel_PLL_is_valid(dev, limit, |
790 | &clock)) | |
79e53945 | 791 | continue; |
cec2f356 SP |
792 | if (match_clock && |
793 | clock.p != match_clock->p) | |
794 | continue; | |
79e53945 JB |
795 | |
796 | this_err = abs(clock.dot - target); | |
797 | if (this_err < err) { | |
798 | *best_clock = clock; | |
799 | err = this_err; | |
800 | } | |
801 | } | |
802 | } | |
803 | } | |
804 | } | |
805 | ||
806 | return (err != target); | |
807 | } | |
808 | ||
d4906093 | 809 | static bool |
a93e255f ACO |
810 | g4x_find_best_dpll(const intel_limit_t *limit, |
811 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
812 | int target, int refclk, intel_clock_t *match_clock, |
813 | intel_clock_t *best_clock) | |
d4906093 | 814 | { |
3b1429d9 | 815 | struct drm_device *dev = crtc_state->base.crtc->dev; |
d4906093 ML |
816 | intel_clock_t clock; |
817 | int max_n; | |
3b1429d9 | 818 | bool found = false; |
6ba770dc AJ |
819 | /* approximately equals target * 0.00585 */ |
820 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
821 | |
822 | memset(best_clock, 0, sizeof(*best_clock)); | |
3b1429d9 VS |
823 | |
824 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); | |
825 | ||
d4906093 | 826 | max_n = limit->n.max; |
f77f13e2 | 827 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 828 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 829 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
830 | for (clock.m1 = limit->m1.max; |
831 | clock.m1 >= limit->m1.min; clock.m1--) { | |
832 | for (clock.m2 = limit->m2.max; | |
833 | clock.m2 >= limit->m2.min; clock.m2--) { | |
834 | for (clock.p1 = limit->p1.max; | |
835 | clock.p1 >= limit->p1.min; clock.p1--) { | |
836 | int this_err; | |
837 | ||
dccbea3b | 838 | i9xx_calc_dpll_params(refclk, &clock); |
1b894b59 CW |
839 | if (!intel_PLL_is_valid(dev, limit, |
840 | &clock)) | |
d4906093 | 841 | continue; |
1b894b59 CW |
842 | |
843 | this_err = abs(clock.dot - target); | |
d4906093 ML |
844 | if (this_err < err_most) { |
845 | *best_clock = clock; | |
846 | err_most = this_err; | |
847 | max_n = clock.n; | |
848 | found = true; | |
849 | } | |
850 | } | |
851 | } | |
852 | } | |
853 | } | |
2c07245f ZW |
854 | return found; |
855 | } | |
856 | ||
d5dd62bd ID |
857 | /* |
858 | * Check if the calculated PLL configuration is more optimal compared to the | |
859 | * best configuration and error found so far. Return the calculated error. | |
860 | */ | |
861 | static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, | |
862 | const intel_clock_t *calculated_clock, | |
863 | const intel_clock_t *best_clock, | |
864 | unsigned int best_error_ppm, | |
865 | unsigned int *error_ppm) | |
866 | { | |
9ca3ba01 ID |
867 | /* |
868 | * For CHV ignore the error and consider only the P value. | |
869 | * Prefer a bigger P value based on HW requirements. | |
870 | */ | |
871 | if (IS_CHERRYVIEW(dev)) { | |
872 | *error_ppm = 0; | |
873 | ||
874 | return calculated_clock->p > best_clock->p; | |
875 | } | |
876 | ||
24be4e46 ID |
877 | if (WARN_ON_ONCE(!target_freq)) |
878 | return false; | |
879 | ||
d5dd62bd ID |
880 | *error_ppm = div_u64(1000000ULL * |
881 | abs(target_freq - calculated_clock->dot), | |
882 | target_freq); | |
883 | /* | |
884 | * Prefer a better P value over a better (smaller) error if the error | |
885 | * is small. Ensure this preference for future configurations too by | |
886 | * setting the error to 0. | |
887 | */ | |
888 | if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { | |
889 | *error_ppm = 0; | |
890 | ||
891 | return true; | |
892 | } | |
893 | ||
894 | return *error_ppm + 10 < best_error_ppm; | |
895 | } | |
896 | ||
a0c4da24 | 897 | static bool |
a93e255f ACO |
898 | vlv_find_best_dpll(const intel_limit_t *limit, |
899 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
900 | int target, int refclk, intel_clock_t *match_clock, |
901 | intel_clock_t *best_clock) | |
a0c4da24 | 902 | { |
a93e255f | 903 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 904 | struct drm_device *dev = crtc->base.dev; |
6b4bf1c4 | 905 | intel_clock_t clock; |
69e4f900 | 906 | unsigned int bestppm = 1000000; |
27e639bf VS |
907 | /* min update 19.2 MHz */ |
908 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 909 | bool found = false; |
a0c4da24 | 910 | |
6b4bf1c4 VS |
911 | target *= 5; /* fast clock */ |
912 | ||
913 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
914 | |
915 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 916 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 917 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 918 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 919 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 920 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 921 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 922 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
d5dd62bd | 923 | unsigned int ppm; |
69e4f900 | 924 | |
6b4bf1c4 VS |
925 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
926 | refclk * clock.m1); | |
927 | ||
dccbea3b | 928 | vlv_calc_dpll_params(refclk, &clock); |
43b0ac53 | 929 | |
f01b7962 VS |
930 | if (!intel_PLL_is_valid(dev, limit, |
931 | &clock)) | |
43b0ac53 VS |
932 | continue; |
933 | ||
d5dd62bd ID |
934 | if (!vlv_PLL_is_optimal(dev, target, |
935 | &clock, | |
936 | best_clock, | |
937 | bestppm, &ppm)) | |
938 | continue; | |
6b4bf1c4 | 939 | |
d5dd62bd ID |
940 | *best_clock = clock; |
941 | bestppm = ppm; | |
942 | found = true; | |
a0c4da24 JB |
943 | } |
944 | } | |
945 | } | |
946 | } | |
a0c4da24 | 947 | |
49e497ef | 948 | return found; |
a0c4da24 | 949 | } |
a4fc5ed6 | 950 | |
ef9348c8 | 951 | static bool |
a93e255f ACO |
952 | chv_find_best_dpll(const intel_limit_t *limit, |
953 | struct intel_crtc_state *crtc_state, | |
ef9348c8 CML |
954 | int target, int refclk, intel_clock_t *match_clock, |
955 | intel_clock_t *best_clock) | |
956 | { | |
a93e255f | 957 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 958 | struct drm_device *dev = crtc->base.dev; |
9ca3ba01 | 959 | unsigned int best_error_ppm; |
ef9348c8 CML |
960 | intel_clock_t clock; |
961 | uint64_t m2; | |
962 | int found = false; | |
963 | ||
964 | memset(best_clock, 0, sizeof(*best_clock)); | |
9ca3ba01 | 965 | best_error_ppm = 1000000; |
ef9348c8 CML |
966 | |
967 | /* | |
968 | * Based on hardware doc, the n always set to 1, and m1 always | |
969 | * set to 2. If requires to support 200Mhz refclk, we need to | |
970 | * revisit this because n may not 1 anymore. | |
971 | */ | |
972 | clock.n = 1, clock.m1 = 2; | |
973 | target *= 5; /* fast clock */ | |
974 | ||
975 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
976 | for (clock.p2 = limit->p2.p2_fast; | |
977 | clock.p2 >= limit->p2.p2_slow; | |
978 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
9ca3ba01 | 979 | unsigned int error_ppm; |
ef9348c8 CML |
980 | |
981 | clock.p = clock.p1 * clock.p2; | |
982 | ||
983 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
984 | clock.n) << 22, refclk * clock.m1); | |
985 | ||
986 | if (m2 > INT_MAX/clock.m1) | |
987 | continue; | |
988 | ||
989 | clock.m2 = m2; | |
990 | ||
dccbea3b | 991 | chv_calc_dpll_params(refclk, &clock); |
ef9348c8 CML |
992 | |
993 | if (!intel_PLL_is_valid(dev, limit, &clock)) | |
994 | continue; | |
995 | ||
9ca3ba01 ID |
996 | if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, |
997 | best_error_ppm, &error_ppm)) | |
998 | continue; | |
999 | ||
1000 | *best_clock = clock; | |
1001 | best_error_ppm = error_ppm; | |
1002 | found = true; | |
ef9348c8 CML |
1003 | } |
1004 | } | |
1005 | ||
1006 | return found; | |
1007 | } | |
1008 | ||
5ab7b0b7 ID |
1009 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, |
1010 | intel_clock_t *best_clock) | |
1011 | { | |
1012 | int refclk = i9xx_get_refclk(crtc_state, 0); | |
1013 | ||
1014 | return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state, | |
1015 | target_clock, refclk, NULL, best_clock); | |
1016 | } | |
1017 | ||
20ddf665 VS |
1018 | bool intel_crtc_active(struct drm_crtc *crtc) |
1019 | { | |
1020 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1021 | ||
1022 | /* Be paranoid as we can arrive here with only partial | |
1023 | * state retrieved from the hardware during setup. | |
1024 | * | |
241bfc38 | 1025 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
1026 | * as Haswell has gained clock readout/fastboot support. |
1027 | * | |
66e514c1 | 1028 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 | 1029 | * properly reconstruct framebuffers. |
c3d1f436 MR |
1030 | * |
1031 | * FIXME: The intel_crtc->active here should be switched to | |
1032 | * crtc->state->active once we have proper CRTC states wired up | |
1033 | * for atomic. | |
20ddf665 | 1034 | */ |
c3d1f436 | 1035 | return intel_crtc->active && crtc->primary->state->fb && |
6e3c9717 | 1036 | intel_crtc->config->base.adjusted_mode.crtc_clock; |
20ddf665 VS |
1037 | } |
1038 | ||
a5c961d1 PZ |
1039 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
1040 | enum pipe pipe) | |
1041 | { | |
1042 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
1043 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1044 | ||
6e3c9717 | 1045 | return intel_crtc->config->cpu_transcoder; |
a5c961d1 PZ |
1046 | } |
1047 | ||
fbf49ea2 VS |
1048 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
1049 | { | |
1050 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1051 | u32 reg = PIPEDSL(pipe); | |
1052 | u32 line1, line2; | |
1053 | u32 line_mask; | |
1054 | ||
1055 | if (IS_GEN2(dev)) | |
1056 | line_mask = DSL_LINEMASK_GEN2; | |
1057 | else | |
1058 | line_mask = DSL_LINEMASK_GEN3; | |
1059 | ||
1060 | line1 = I915_READ(reg) & line_mask; | |
6adfb1ef | 1061 | msleep(5); |
fbf49ea2 VS |
1062 | line2 = I915_READ(reg) & line_mask; |
1063 | ||
1064 | return line1 == line2; | |
1065 | } | |
1066 | ||
ab7ad7f6 KP |
1067 | /* |
1068 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
575f7ab7 | 1069 | * @crtc: crtc whose pipe to wait for |
9d0498a2 JB |
1070 | * |
1071 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
1072 | * spinning on the vblank interrupt status bit, since we won't actually | |
1073 | * see an interrupt when the pipe is disabled. | |
1074 | * | |
ab7ad7f6 KP |
1075 | * On Gen4 and above: |
1076 | * wait for the pipe register state bit to turn off | |
1077 | * | |
1078 | * Otherwise: | |
1079 | * wait for the display line value to settle (it usually | |
1080 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 1081 | * |
9d0498a2 | 1082 | */ |
575f7ab7 | 1083 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
9d0498a2 | 1084 | { |
575f7ab7 | 1085 | struct drm_device *dev = crtc->base.dev; |
9d0498a2 | 1086 | struct drm_i915_private *dev_priv = dev->dev_private; |
6e3c9717 | 1087 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 1088 | enum pipe pipe = crtc->pipe; |
ab7ad7f6 KP |
1089 | |
1090 | if (INTEL_INFO(dev)->gen >= 4) { | |
702e7a56 | 1091 | int reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
1092 | |
1093 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
1094 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
1095 | 100)) | |
284637d9 | 1096 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1097 | } else { |
ab7ad7f6 | 1098 | /* Wait for the display line to settle */ |
fbf49ea2 | 1099 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 1100 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1101 | } |
79e53945 JB |
1102 | } |
1103 | ||
b24e7179 JB |
1104 | static const char *state_string(bool enabled) |
1105 | { | |
1106 | return enabled ? "on" : "off"; | |
1107 | } | |
1108 | ||
1109 | /* Only for pre-ILK configs */ | |
55607e8a DV |
1110 | void assert_pll(struct drm_i915_private *dev_priv, |
1111 | enum pipe pipe, bool state) | |
b24e7179 JB |
1112 | { |
1113 | int reg; | |
1114 | u32 val; | |
1115 | bool cur_state; | |
1116 | ||
1117 | reg = DPLL(pipe); | |
1118 | val = I915_READ(reg); | |
1119 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
e2c719b7 | 1120 | I915_STATE_WARN(cur_state != state, |
b24e7179 JB |
1121 | "PLL state assertion failure (expected %s, current %s)\n", |
1122 | state_string(state), state_string(cur_state)); | |
1123 | } | |
b24e7179 | 1124 | |
23538ef1 JN |
1125 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
1126 | static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) | |
1127 | { | |
1128 | u32 val; | |
1129 | bool cur_state; | |
1130 | ||
a580516d | 1131 | mutex_lock(&dev_priv->sb_lock); |
23538ef1 | 1132 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
a580516d | 1133 | mutex_unlock(&dev_priv->sb_lock); |
23538ef1 JN |
1134 | |
1135 | cur_state = val & DSI_PLL_VCO_EN; | |
e2c719b7 | 1136 | I915_STATE_WARN(cur_state != state, |
23538ef1 JN |
1137 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
1138 | state_string(state), state_string(cur_state)); | |
1139 | } | |
1140 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) | |
1141 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) | |
1142 | ||
55607e8a | 1143 | struct intel_shared_dpll * |
e2b78267 DV |
1144 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
1145 | { | |
1146 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
1147 | ||
6e3c9717 | 1148 | if (crtc->config->shared_dpll < 0) |
e2b78267 DV |
1149 | return NULL; |
1150 | ||
6e3c9717 | 1151 | return &dev_priv->shared_dplls[crtc->config->shared_dpll]; |
e2b78267 DV |
1152 | } |
1153 | ||
040484af | 1154 | /* For ILK+ */ |
55607e8a DV |
1155 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
1156 | struct intel_shared_dpll *pll, | |
1157 | bool state) | |
040484af | 1158 | { |
040484af | 1159 | bool cur_state; |
5358901f | 1160 | struct intel_dpll_hw_state hw_state; |
040484af | 1161 | |
92b27b08 | 1162 | if (WARN (!pll, |
46edb027 | 1163 | "asserting DPLL %s with no DPLL\n", state_string(state))) |
ee7b9f93 | 1164 | return; |
ee7b9f93 | 1165 | |
5358901f | 1166 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
e2c719b7 | 1167 | I915_STATE_WARN(cur_state != state, |
5358901f DV |
1168 | "%s assertion failure (expected %s, current %s)\n", |
1169 | pll->name, state_string(state), state_string(cur_state)); | |
040484af | 1170 | } |
040484af JB |
1171 | |
1172 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
1173 | enum pipe pipe, bool state) | |
1174 | { | |
1175 | int reg; | |
1176 | u32 val; | |
1177 | bool cur_state; | |
ad80a810 PZ |
1178 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1179 | pipe); | |
040484af | 1180 | |
affa9354 PZ |
1181 | if (HAS_DDI(dev_priv->dev)) { |
1182 | /* DDI does not have a specific FDI_TX register */ | |
ad80a810 | 1183 | reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
bf507ef7 | 1184 | val = I915_READ(reg); |
ad80a810 | 1185 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 ED |
1186 | } else { |
1187 | reg = FDI_TX_CTL(pipe); | |
1188 | val = I915_READ(reg); | |
1189 | cur_state = !!(val & FDI_TX_ENABLE); | |
1190 | } | |
e2c719b7 | 1191 | I915_STATE_WARN(cur_state != state, |
040484af JB |
1192 | "FDI TX state assertion failure (expected %s, current %s)\n", |
1193 | state_string(state), state_string(cur_state)); | |
1194 | } | |
1195 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1196 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1197 | ||
1198 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1199 | enum pipe pipe, bool state) | |
1200 | { | |
1201 | int reg; | |
1202 | u32 val; | |
1203 | bool cur_state; | |
1204 | ||
d63fa0dc PZ |
1205 | reg = FDI_RX_CTL(pipe); |
1206 | val = I915_READ(reg); | |
1207 | cur_state = !!(val & FDI_RX_ENABLE); | |
e2c719b7 | 1208 | I915_STATE_WARN(cur_state != state, |
040484af JB |
1209 | "FDI RX state assertion failure (expected %s, current %s)\n", |
1210 | state_string(state), state_string(cur_state)); | |
1211 | } | |
1212 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1213 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1214 | ||
1215 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1216 | enum pipe pipe) | |
1217 | { | |
1218 | int reg; | |
1219 | u32 val; | |
1220 | ||
1221 | /* ILK FDI PLL is always enabled */ | |
3d13ef2e | 1222 | if (INTEL_INFO(dev_priv->dev)->gen == 5) |
040484af JB |
1223 | return; |
1224 | ||
bf507ef7 | 1225 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
affa9354 | 1226 | if (HAS_DDI(dev_priv->dev)) |
bf507ef7 ED |
1227 | return; |
1228 | ||
040484af JB |
1229 | reg = FDI_TX_CTL(pipe); |
1230 | val = I915_READ(reg); | |
e2c719b7 | 1231 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
040484af JB |
1232 | } |
1233 | ||
55607e8a DV |
1234 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1235 | enum pipe pipe, bool state) | |
040484af JB |
1236 | { |
1237 | int reg; | |
1238 | u32 val; | |
55607e8a | 1239 | bool cur_state; |
040484af JB |
1240 | |
1241 | reg = FDI_RX_CTL(pipe); | |
1242 | val = I915_READ(reg); | |
55607e8a | 1243 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
e2c719b7 | 1244 | I915_STATE_WARN(cur_state != state, |
55607e8a DV |
1245 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
1246 | state_string(state), state_string(cur_state)); | |
040484af JB |
1247 | } |
1248 | ||
b680c37a DV |
1249 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1250 | enum pipe pipe) | |
ea0760cf | 1251 | { |
bedd4dba JN |
1252 | struct drm_device *dev = dev_priv->dev; |
1253 | int pp_reg; | |
ea0760cf JB |
1254 | u32 val; |
1255 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1256 | bool locked = true; |
ea0760cf | 1257 | |
bedd4dba JN |
1258 | if (WARN_ON(HAS_DDI(dev))) |
1259 | return; | |
1260 | ||
1261 | if (HAS_PCH_SPLIT(dev)) { | |
1262 | u32 port_sel; | |
1263 | ||
ea0760cf | 1264 | pp_reg = PCH_PP_CONTROL; |
bedd4dba JN |
1265 | port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK; |
1266 | ||
1267 | if (port_sel == PANEL_PORT_SELECT_LVDS && | |
1268 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) | |
1269 | panel_pipe = PIPE_B; | |
1270 | /* XXX: else fix for eDP */ | |
1271 | } else if (IS_VALLEYVIEW(dev)) { | |
1272 | /* presumably write lock depends on pipe, not port select */ | |
1273 | pp_reg = VLV_PIPE_PP_CONTROL(pipe); | |
1274 | panel_pipe = pipe; | |
ea0760cf JB |
1275 | } else { |
1276 | pp_reg = PP_CONTROL; | |
bedd4dba JN |
1277 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
1278 | panel_pipe = PIPE_B; | |
ea0760cf JB |
1279 | } |
1280 | ||
1281 | val = I915_READ(pp_reg); | |
1282 | if (!(val & PANEL_POWER_ON) || | |
ec49ba2d | 1283 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1284 | locked = false; |
1285 | ||
e2c719b7 | 1286 | I915_STATE_WARN(panel_pipe == pipe && locked, |
ea0760cf | 1287 | "panel assertion failure, pipe %c regs locked\n", |
9db4a9c7 | 1288 | pipe_name(pipe)); |
ea0760cf JB |
1289 | } |
1290 | ||
93ce0ba6 JN |
1291 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1292 | enum pipe pipe, bool state) | |
1293 | { | |
1294 | struct drm_device *dev = dev_priv->dev; | |
1295 | bool cur_state; | |
1296 | ||
d9d82081 | 1297 | if (IS_845G(dev) || IS_I865G(dev)) |
93ce0ba6 | 1298 | cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE; |
d9d82081 | 1299 | else |
5efb3e28 | 1300 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 | 1301 | |
e2c719b7 | 1302 | I915_STATE_WARN(cur_state != state, |
93ce0ba6 JN |
1303 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
1304 | pipe_name(pipe), state_string(state), state_string(cur_state)); | |
1305 | } | |
1306 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1307 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1308 | ||
b840d907 JB |
1309 | void assert_pipe(struct drm_i915_private *dev_priv, |
1310 | enum pipe pipe, bool state) | |
b24e7179 JB |
1311 | { |
1312 | int reg; | |
1313 | u32 val; | |
63d7bbe9 | 1314 | bool cur_state; |
702e7a56 PZ |
1315 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1316 | pipe); | |
b24e7179 | 1317 | |
b6b5d049 VS |
1318 | /* if we need the pipe quirk it must be always on */ |
1319 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1320 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
8e636784 DV |
1321 | state = true; |
1322 | ||
f458ebbc | 1323 | if (!intel_display_power_is_enabled(dev_priv, |
b97186f0 | 1324 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { |
69310161 PZ |
1325 | cur_state = false; |
1326 | } else { | |
1327 | reg = PIPECONF(cpu_transcoder); | |
1328 | val = I915_READ(reg); | |
1329 | cur_state = !!(val & PIPECONF_ENABLE); | |
1330 | } | |
1331 | ||
e2c719b7 | 1332 | I915_STATE_WARN(cur_state != state, |
63d7bbe9 | 1333 | "pipe %c assertion failure (expected %s, current %s)\n", |
9db4a9c7 | 1334 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
b24e7179 JB |
1335 | } |
1336 | ||
931872fc CW |
1337 | static void assert_plane(struct drm_i915_private *dev_priv, |
1338 | enum plane plane, bool state) | |
b24e7179 JB |
1339 | { |
1340 | int reg; | |
1341 | u32 val; | |
931872fc | 1342 | bool cur_state; |
b24e7179 JB |
1343 | |
1344 | reg = DSPCNTR(plane); | |
1345 | val = I915_READ(reg); | |
931872fc | 1346 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
e2c719b7 | 1347 | I915_STATE_WARN(cur_state != state, |
931872fc CW |
1348 | "plane %c assertion failure (expected %s, current %s)\n", |
1349 | plane_name(plane), state_string(state), state_string(cur_state)); | |
b24e7179 JB |
1350 | } |
1351 | ||
931872fc CW |
1352 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1353 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1354 | ||
b24e7179 JB |
1355 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1356 | enum pipe pipe) | |
1357 | { | |
653e1026 | 1358 | struct drm_device *dev = dev_priv->dev; |
b24e7179 JB |
1359 | int reg, i; |
1360 | u32 val; | |
1361 | int cur_pipe; | |
1362 | ||
653e1026 VS |
1363 | /* Primary planes are fixed to pipes on gen4+ */ |
1364 | if (INTEL_INFO(dev)->gen >= 4) { | |
28c05794 AJ |
1365 | reg = DSPCNTR(pipe); |
1366 | val = I915_READ(reg); | |
e2c719b7 | 1367 | I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1368 | "plane %c assertion failure, should be disabled but not\n", |
1369 | plane_name(pipe)); | |
19ec1358 | 1370 | return; |
28c05794 | 1371 | } |
19ec1358 | 1372 | |
b24e7179 | 1373 | /* Need to check both planes against the pipe */ |
055e393f | 1374 | for_each_pipe(dev_priv, i) { |
b24e7179 JB |
1375 | reg = DSPCNTR(i); |
1376 | val = I915_READ(reg); | |
1377 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
1378 | DISPPLANE_SEL_PIPE_SHIFT; | |
e2c719b7 | 1379 | I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
9db4a9c7 JB |
1380 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1381 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1382 | } |
1383 | } | |
1384 | ||
19332d7a JB |
1385 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1386 | enum pipe pipe) | |
1387 | { | |
20674eef | 1388 | struct drm_device *dev = dev_priv->dev; |
1fe47785 | 1389 | int reg, sprite; |
19332d7a JB |
1390 | u32 val; |
1391 | ||
7feb8b88 | 1392 | if (INTEL_INFO(dev)->gen >= 9) { |
3bdcfc0c | 1393 | for_each_sprite(dev_priv, pipe, sprite) { |
7feb8b88 | 1394 | val = I915_READ(PLANE_CTL(pipe, sprite)); |
e2c719b7 | 1395 | I915_STATE_WARN(val & PLANE_CTL_ENABLE, |
7feb8b88 DL |
1396 | "plane %d assertion failure, should be off on pipe %c but is still active\n", |
1397 | sprite, pipe_name(pipe)); | |
1398 | } | |
1399 | } else if (IS_VALLEYVIEW(dev)) { | |
3bdcfc0c | 1400 | for_each_sprite(dev_priv, pipe, sprite) { |
1fe47785 | 1401 | reg = SPCNTR(pipe, sprite); |
20674eef | 1402 | val = I915_READ(reg); |
e2c719b7 | 1403 | I915_STATE_WARN(val & SP_ENABLE, |
20674eef | 1404 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1405 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef VS |
1406 | } |
1407 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
1408 | reg = SPRCTL(pipe); | |
19332d7a | 1409 | val = I915_READ(reg); |
e2c719b7 | 1410 | I915_STATE_WARN(val & SPRITE_ENABLE, |
06da8da2 | 1411 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1412 | plane_name(pipe), pipe_name(pipe)); |
1413 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
1414 | reg = DVSCNTR(pipe); | |
19332d7a | 1415 | val = I915_READ(reg); |
e2c719b7 | 1416 | I915_STATE_WARN(val & DVS_ENABLE, |
06da8da2 | 1417 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1418 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1419 | } |
1420 | } | |
1421 | ||
08c71e5e VS |
1422 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
1423 | { | |
e2c719b7 | 1424 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
08c71e5e VS |
1425 | drm_crtc_vblank_put(crtc); |
1426 | } | |
1427 | ||
89eff4be | 1428 | static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
92f2584a JB |
1429 | { |
1430 | u32 val; | |
1431 | bool enabled; | |
1432 | ||
e2c719b7 | 1433 | I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))); |
9d82aa17 | 1434 | |
92f2584a JB |
1435 | val = I915_READ(PCH_DREF_CONTROL); |
1436 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1437 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
e2c719b7 | 1438 | I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); |
92f2584a JB |
1439 | } |
1440 | ||
ab9412ba DV |
1441 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1442 | enum pipe pipe) | |
92f2584a JB |
1443 | { |
1444 | int reg; | |
1445 | u32 val; | |
1446 | bool enabled; | |
1447 | ||
ab9412ba | 1448 | reg = PCH_TRANSCONF(pipe); |
92f2584a JB |
1449 | val = I915_READ(reg); |
1450 | enabled = !!(val & TRANS_ENABLE); | |
e2c719b7 | 1451 | I915_STATE_WARN(enabled, |
9db4a9c7 JB |
1452 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1453 | pipe_name(pipe)); | |
92f2584a JB |
1454 | } |
1455 | ||
4e634389 KP |
1456 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1457 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1458 | { |
1459 | if ((val & DP_PORT_EN) == 0) | |
1460 | return false; | |
1461 | ||
1462 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1463 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); | |
1464 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); | |
1465 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) | |
1466 | return false; | |
44f37d1f CML |
1467 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1468 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) | |
1469 | return false; | |
f0575e92 KP |
1470 | } else { |
1471 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1472 | return false; | |
1473 | } | |
1474 | return true; | |
1475 | } | |
1476 | ||
1519b995 KP |
1477 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1478 | enum pipe pipe, u32 val) | |
1479 | { | |
dc0fa718 | 1480 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1481 | return false; |
1482 | ||
1483 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
dc0fa718 | 1484 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1485 | return false; |
44f37d1f CML |
1486 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1487 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) | |
1488 | return false; | |
1519b995 | 1489 | } else { |
dc0fa718 | 1490 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1491 | return false; |
1492 | } | |
1493 | return true; | |
1494 | } | |
1495 | ||
1496 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1497 | enum pipe pipe, u32 val) | |
1498 | { | |
1499 | if ((val & LVDS_PORT_EN) == 0) | |
1500 | return false; | |
1501 | ||
1502 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1503 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1504 | return false; | |
1505 | } else { | |
1506 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1507 | return false; | |
1508 | } | |
1509 | return true; | |
1510 | } | |
1511 | ||
1512 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1513 | enum pipe pipe, u32 val) | |
1514 | { | |
1515 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1516 | return false; | |
1517 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1518 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1519 | return false; | |
1520 | } else { | |
1521 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1522 | return false; | |
1523 | } | |
1524 | return true; | |
1525 | } | |
1526 | ||
291906f1 | 1527 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0575e92 | 1528 | enum pipe pipe, int reg, u32 port_sel) |
291906f1 | 1529 | { |
47a05eca | 1530 | u32 val = I915_READ(reg); |
e2c719b7 | 1531 | I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1532 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1533 | reg, pipe_name(pipe)); |
de9a35ab | 1534 | |
e2c719b7 | 1535 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
75c5da27 | 1536 | && (val & DP_PIPEB_SELECT), |
de9a35ab | 1537 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1538 | } |
1539 | ||
1540 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
1541 | enum pipe pipe, int reg) | |
1542 | { | |
47a05eca | 1543 | u32 val = I915_READ(reg); |
e2c719b7 | 1544 | I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1545 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1546 | reg, pipe_name(pipe)); |
de9a35ab | 1547 | |
e2c719b7 | 1548 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1549 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1550 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1551 | } |
1552 | ||
1553 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1554 | enum pipe pipe) | |
1555 | { | |
1556 | int reg; | |
1557 | u32 val; | |
291906f1 | 1558 | |
f0575e92 KP |
1559 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1560 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1561 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 JB |
1562 | |
1563 | reg = PCH_ADPA; | |
1564 | val = I915_READ(reg); | |
e2c719b7 | 1565 | I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1566 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1567 | pipe_name(pipe)); |
291906f1 JB |
1568 | |
1569 | reg = PCH_LVDS; | |
1570 | val = I915_READ(reg); | |
e2c719b7 | 1571 | I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1572 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1573 | pipe_name(pipe)); |
291906f1 | 1574 | |
e2debe91 PZ |
1575 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1576 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1577 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1578 | } |
1579 | ||
d288f65f | 1580 | static void vlv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1581 | const struct intel_crtc_state *pipe_config) |
87442f73 | 1582 | { |
426115cf DV |
1583 | struct drm_device *dev = crtc->base.dev; |
1584 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1585 | int reg = DPLL(crtc->pipe); | |
d288f65f | 1586 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
87442f73 | 1587 | |
426115cf | 1588 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87442f73 DV |
1589 | |
1590 | /* No really, not for ILK+ */ | |
1591 | BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); | |
1592 | ||
1593 | /* PLL is protected by panel, make sure we can write it */ | |
6a9e7363 | 1594 | if (IS_MOBILE(dev_priv->dev)) |
426115cf | 1595 | assert_panel_unlocked(dev_priv, crtc->pipe); |
87442f73 | 1596 | |
426115cf DV |
1597 | I915_WRITE(reg, dpll); |
1598 | POSTING_READ(reg); | |
1599 | udelay(150); | |
1600 | ||
1601 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
1602 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); | |
1603 | ||
d288f65f | 1604 | I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md); |
426115cf | 1605 | POSTING_READ(DPLL_MD(crtc->pipe)); |
87442f73 DV |
1606 | |
1607 | /* We do this three times for luck */ | |
426115cf | 1608 | I915_WRITE(reg, dpll); |
87442f73 DV |
1609 | POSTING_READ(reg); |
1610 | udelay(150); /* wait for warmup */ | |
426115cf | 1611 | I915_WRITE(reg, dpll); |
87442f73 DV |
1612 | POSTING_READ(reg); |
1613 | udelay(150); /* wait for warmup */ | |
426115cf | 1614 | I915_WRITE(reg, dpll); |
87442f73 DV |
1615 | POSTING_READ(reg); |
1616 | udelay(150); /* wait for warmup */ | |
1617 | } | |
1618 | ||
d288f65f | 1619 | static void chv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1620 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
1621 | { |
1622 | struct drm_device *dev = crtc->base.dev; | |
1623 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1624 | int pipe = crtc->pipe; | |
1625 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9d556c99 CML |
1626 | u32 tmp; |
1627 | ||
1628 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
1629 | ||
1630 | BUG_ON(!IS_CHERRYVIEW(dev_priv->dev)); | |
1631 | ||
a580516d | 1632 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 CML |
1633 | |
1634 | /* Enable back the 10bit clock to display controller */ | |
1635 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1636 | tmp |= DPIO_DCLKP_EN; | |
1637 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1638 | ||
54433e91 VS |
1639 | mutex_unlock(&dev_priv->sb_lock); |
1640 | ||
9d556c99 CML |
1641 | /* |
1642 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1643 | */ | |
1644 | udelay(1); | |
1645 | ||
1646 | /* Enable PLL */ | |
d288f65f | 1647 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
9d556c99 CML |
1648 | |
1649 | /* Check PLL is locked */ | |
a11b0703 | 1650 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
9d556c99 CML |
1651 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
1652 | ||
a11b0703 | 1653 | /* not sure when this should be written */ |
d288f65f | 1654 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
a11b0703 | 1655 | POSTING_READ(DPLL_MD(pipe)); |
9d556c99 CML |
1656 | } |
1657 | ||
1c4e0274 VS |
1658 | static int intel_num_dvo_pipes(struct drm_device *dev) |
1659 | { | |
1660 | struct intel_crtc *crtc; | |
1661 | int count = 0; | |
1662 | ||
1663 | for_each_intel_crtc(dev, crtc) | |
3538b9df | 1664 | count += crtc->base.state->active && |
409ee761 | 1665 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO); |
1c4e0274 VS |
1666 | |
1667 | return count; | |
1668 | } | |
1669 | ||
66e3d5c0 | 1670 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1671 | { |
66e3d5c0 DV |
1672 | struct drm_device *dev = crtc->base.dev; |
1673 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1674 | int reg = DPLL(crtc->pipe); | |
6e3c9717 | 1675 | u32 dpll = crtc->config->dpll_hw_state.dpll; |
63d7bbe9 | 1676 | |
66e3d5c0 | 1677 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1678 | |
63d7bbe9 | 1679 | /* No really, not for ILK+ */ |
3d13ef2e | 1680 | BUG_ON(INTEL_INFO(dev)->gen >= 5); |
63d7bbe9 JB |
1681 | |
1682 | /* PLL is protected by panel, make sure we can write it */ | |
66e3d5c0 DV |
1683 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1684 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1685 | |
1c4e0274 VS |
1686 | /* Enable DVO 2x clock on both PLLs if necessary */ |
1687 | if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) { | |
1688 | /* | |
1689 | * It appears to be important that we don't enable this | |
1690 | * for the current pipe before otherwise configuring the | |
1691 | * PLL. No idea how this should be handled if multiple | |
1692 | * DVO outputs are enabled simultaneosly. | |
1693 | */ | |
1694 | dpll |= DPLL_DVO_2X_MODE; | |
1695 | I915_WRITE(DPLL(!crtc->pipe), | |
1696 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); | |
1697 | } | |
66e3d5c0 DV |
1698 | |
1699 | /* Wait for the clocks to stabilize. */ | |
1700 | POSTING_READ(reg); | |
1701 | udelay(150); | |
1702 | ||
1703 | if (INTEL_INFO(dev)->gen >= 4) { | |
1704 | I915_WRITE(DPLL_MD(crtc->pipe), | |
6e3c9717 | 1705 | crtc->config->dpll_hw_state.dpll_md); |
66e3d5c0 DV |
1706 | } else { |
1707 | /* The pixel multiplier can only be updated once the | |
1708 | * DPLL is enabled and the clocks are stable. | |
1709 | * | |
1710 | * So write it again. | |
1711 | */ | |
1712 | I915_WRITE(reg, dpll); | |
1713 | } | |
63d7bbe9 JB |
1714 | |
1715 | /* We do this three times for luck */ | |
66e3d5c0 | 1716 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1717 | POSTING_READ(reg); |
1718 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1719 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1720 | POSTING_READ(reg); |
1721 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1722 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1723 | POSTING_READ(reg); |
1724 | udelay(150); /* wait for warmup */ | |
1725 | } | |
1726 | ||
1727 | /** | |
50b44a44 | 1728 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1729 | * @dev_priv: i915 private structure |
1730 | * @pipe: pipe PLL to disable | |
1731 | * | |
1732 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1733 | * | |
1734 | * Note! This is for pre-ILK only. | |
1735 | */ | |
1c4e0274 | 1736 | static void i9xx_disable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1737 | { |
1c4e0274 VS |
1738 | struct drm_device *dev = crtc->base.dev; |
1739 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1740 | enum pipe pipe = crtc->pipe; | |
1741 | ||
1742 | /* Disable DVO 2x clock on both PLLs if necessary */ | |
1743 | if (IS_I830(dev) && | |
409ee761 | 1744 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) && |
3538b9df | 1745 | !intel_num_dvo_pipes(dev)) { |
1c4e0274 VS |
1746 | I915_WRITE(DPLL(PIPE_B), |
1747 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); | |
1748 | I915_WRITE(DPLL(PIPE_A), | |
1749 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); | |
1750 | } | |
1751 | ||
b6b5d049 VS |
1752 | /* Don't disable pipe or pipe PLLs if needed */ |
1753 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1754 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
63d7bbe9 JB |
1755 | return; |
1756 | ||
1757 | /* Make sure the pipe isn't still relying on us */ | |
1758 | assert_pipe_disabled(dev_priv, pipe); | |
1759 | ||
b8afb911 | 1760 | I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); |
50b44a44 | 1761 | POSTING_READ(DPLL(pipe)); |
63d7bbe9 JB |
1762 | } |
1763 | ||
f6071166 JB |
1764 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1765 | { | |
b8afb911 | 1766 | u32 val; |
f6071166 JB |
1767 | |
1768 | /* Make sure the pipe isn't still relying on us */ | |
1769 | assert_pipe_disabled(dev_priv, pipe); | |
1770 | ||
e5cbfbfb ID |
1771 | /* |
1772 | * Leave integrated clock source and reference clock enabled for pipe B. | |
1773 | * The latter is needed for VGA hotplug / manual detection. | |
1774 | */ | |
b8afb911 | 1775 | val = DPLL_VGA_MODE_DIS; |
f6071166 | 1776 | if (pipe == PIPE_B) |
60bfe44f | 1777 | val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV; |
f6071166 JB |
1778 | I915_WRITE(DPLL(pipe), val); |
1779 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1780 | |
1781 | } | |
1782 | ||
1783 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1784 | { | |
d752048d | 1785 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1786 | u32 val; |
1787 | ||
a11b0703 VS |
1788 | /* Make sure the pipe isn't still relying on us */ |
1789 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1790 | |
a11b0703 | 1791 | /* Set PLL en = 0 */ |
60bfe44f VS |
1792 | val = DPLL_SSC_REF_CLK_CHV | |
1793 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
a11b0703 VS |
1794 | if (pipe != PIPE_A) |
1795 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1796 | I915_WRITE(DPLL(pipe), val); | |
1797 | POSTING_READ(DPLL(pipe)); | |
d752048d | 1798 | |
a580516d | 1799 | mutex_lock(&dev_priv->sb_lock); |
d752048d VS |
1800 | |
1801 | /* Disable 10bit clock to display controller */ | |
1802 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1803 | val &= ~DPIO_DCLKP_EN; | |
1804 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1805 | ||
a580516d | 1806 | mutex_unlock(&dev_priv->sb_lock); |
f6071166 JB |
1807 | } |
1808 | ||
e4607fcf | 1809 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
9b6de0a1 VS |
1810 | struct intel_digital_port *dport, |
1811 | unsigned int expected_mask) | |
89b667f8 JB |
1812 | { |
1813 | u32 port_mask; | |
00fc31b7 | 1814 | int dpll_reg; |
89b667f8 | 1815 | |
e4607fcf CML |
1816 | switch (dport->port) { |
1817 | case PORT_B: | |
89b667f8 | 1818 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1819 | dpll_reg = DPLL(0); |
e4607fcf CML |
1820 | break; |
1821 | case PORT_C: | |
89b667f8 | 1822 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 | 1823 | dpll_reg = DPLL(0); |
9b6de0a1 | 1824 | expected_mask <<= 4; |
00fc31b7 CML |
1825 | break; |
1826 | case PORT_D: | |
1827 | port_mask = DPLL_PORTD_READY_MASK; | |
1828 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1829 | break; |
1830 | default: | |
1831 | BUG(); | |
1832 | } | |
89b667f8 | 1833 | |
9b6de0a1 VS |
1834 | if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000)) |
1835 | WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n", | |
1836 | port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask); | |
89b667f8 JB |
1837 | } |
1838 | ||
b14b1055 DV |
1839 | static void intel_prepare_shared_dpll(struct intel_crtc *crtc) |
1840 | { | |
1841 | struct drm_device *dev = crtc->base.dev; | |
1842 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1843 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
1844 | ||
be19f0ff CW |
1845 | if (WARN_ON(pll == NULL)) |
1846 | return; | |
1847 | ||
3e369b76 | 1848 | WARN_ON(!pll->config.crtc_mask); |
b14b1055 DV |
1849 | if (pll->active == 0) { |
1850 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); | |
1851 | WARN_ON(pll->on); | |
1852 | assert_shared_dpll_disabled(dev_priv, pll); | |
1853 | ||
1854 | pll->mode_set(dev_priv, pll); | |
1855 | } | |
1856 | } | |
1857 | ||
92f2584a | 1858 | /** |
85b3894f | 1859 | * intel_enable_shared_dpll - enable PCH PLL |
92f2584a JB |
1860 | * @dev_priv: i915 private structure |
1861 | * @pipe: pipe PLL to enable | |
1862 | * | |
1863 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1864 | * drives the transcoder clock. | |
1865 | */ | |
85b3894f | 1866 | static void intel_enable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1867 | { |
3d13ef2e DL |
1868 | struct drm_device *dev = crtc->base.dev; |
1869 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1870 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
92f2584a | 1871 | |
87a875bb | 1872 | if (WARN_ON(pll == NULL)) |
48da64a8 CW |
1873 | return; |
1874 | ||
3e369b76 | 1875 | if (WARN_ON(pll->config.crtc_mask == 0)) |
48da64a8 | 1876 | return; |
ee7b9f93 | 1877 | |
74dd6928 | 1878 | DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n", |
46edb027 | 1879 | pll->name, pll->active, pll->on, |
e2b78267 | 1880 | crtc->base.base.id); |
92f2584a | 1881 | |
cdbd2316 DV |
1882 | if (pll->active++) { |
1883 | WARN_ON(!pll->on); | |
e9d6944e | 1884 | assert_shared_dpll_enabled(dev_priv, pll); |
ee7b9f93 JB |
1885 | return; |
1886 | } | |
f4a091c7 | 1887 | WARN_ON(pll->on); |
ee7b9f93 | 1888 | |
bd2bb1b9 PZ |
1889 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
1890 | ||
46edb027 | 1891 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
e7b903d2 | 1892 | pll->enable(dev_priv, pll); |
ee7b9f93 | 1893 | pll->on = true; |
92f2584a JB |
1894 | } |
1895 | ||
f6daaec2 | 1896 | static void intel_disable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1897 | { |
3d13ef2e DL |
1898 | struct drm_device *dev = crtc->base.dev; |
1899 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1900 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
4c609cb8 | 1901 | |
92f2584a | 1902 | /* PCH only available on ILK+ */ |
80aa9312 JB |
1903 | if (INTEL_INFO(dev)->gen < 5) |
1904 | return; | |
1905 | ||
eddfcbcd ML |
1906 | if (pll == NULL) |
1907 | return; | |
92f2584a | 1908 | |
eddfcbcd | 1909 | if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base))))) |
48da64a8 | 1910 | return; |
7a419866 | 1911 | |
46edb027 DV |
1912 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
1913 | pll->name, pll->active, pll->on, | |
e2b78267 | 1914 | crtc->base.base.id); |
7a419866 | 1915 | |
48da64a8 | 1916 | if (WARN_ON(pll->active == 0)) { |
e9d6944e | 1917 | assert_shared_dpll_disabled(dev_priv, pll); |
48da64a8 CW |
1918 | return; |
1919 | } | |
1920 | ||
e9d6944e | 1921 | assert_shared_dpll_enabled(dev_priv, pll); |
f4a091c7 | 1922 | WARN_ON(!pll->on); |
cdbd2316 | 1923 | if (--pll->active) |
7a419866 | 1924 | return; |
ee7b9f93 | 1925 | |
46edb027 | 1926 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
e7b903d2 | 1927 | pll->disable(dev_priv, pll); |
ee7b9f93 | 1928 | pll->on = false; |
bd2bb1b9 PZ |
1929 | |
1930 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
92f2584a JB |
1931 | } |
1932 | ||
b8a4f404 PZ |
1933 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1934 | enum pipe pipe) | |
040484af | 1935 | { |
23670b32 | 1936 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1937 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1938 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
23670b32 | 1939 | uint32_t reg, val, pipeconf_val; |
040484af JB |
1940 | |
1941 | /* PCH only available on ILK+ */ | |
55522f37 | 1942 | BUG_ON(!HAS_PCH_SPLIT(dev)); |
040484af JB |
1943 | |
1944 | /* Make sure PCH DPLL is enabled */ | |
e72f9fbf | 1945 | assert_shared_dpll_enabled(dev_priv, |
e9d6944e | 1946 | intel_crtc_to_shared_dpll(intel_crtc)); |
040484af JB |
1947 | |
1948 | /* FDI must be feeding us bits for PCH ports */ | |
1949 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1950 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1951 | ||
23670b32 DV |
1952 | if (HAS_PCH_CPT(dev)) { |
1953 | /* Workaround: Set the timing override bit before enabling the | |
1954 | * pch transcoder. */ | |
1955 | reg = TRANS_CHICKEN2(pipe); | |
1956 | val = I915_READ(reg); | |
1957 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1958 | I915_WRITE(reg, val); | |
59c859d6 | 1959 | } |
23670b32 | 1960 | |
ab9412ba | 1961 | reg = PCH_TRANSCONF(pipe); |
040484af | 1962 | val = I915_READ(reg); |
5f7f726d | 1963 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
1964 | |
1965 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
1966 | /* | |
c5de7c6f VS |
1967 | * Make the BPC in transcoder be consistent with |
1968 | * that in pipeconf reg. For HDMI we must use 8bpc | |
1969 | * here for both 8bpc and 12bpc. | |
e9bcff5c | 1970 | */ |
dfd07d72 | 1971 | val &= ~PIPECONF_BPC_MASK; |
c5de7c6f VS |
1972 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI)) |
1973 | val |= PIPECONF_8BPC; | |
1974 | else | |
1975 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1976 | } |
5f7f726d PZ |
1977 | |
1978 | val &= ~TRANS_INTERLACE_MASK; | |
1979 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 | 1980 | if (HAS_PCH_IBX(dev_priv->dev) && |
409ee761 | 1981 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
7c26e5c6 PZ |
1982 | val |= TRANS_LEGACY_INTERLACED_ILK; |
1983 | else | |
1984 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1985 | else |
1986 | val |= TRANS_PROGRESSIVE; | |
1987 | ||
040484af JB |
1988 | I915_WRITE(reg, val | TRANS_ENABLE); |
1989 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
4bb6f1f3 | 1990 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
1991 | } |
1992 | ||
8fb033d7 | 1993 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 1994 | enum transcoder cpu_transcoder) |
040484af | 1995 | { |
8fb033d7 | 1996 | u32 val, pipeconf_val; |
8fb033d7 PZ |
1997 | |
1998 | /* PCH only available on ILK+ */ | |
55522f37 | 1999 | BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev)); |
8fb033d7 | 2000 | |
8fb033d7 | 2001 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 2002 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 2003 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 2004 | |
223a6fdf PZ |
2005 | /* Workaround: set timing override bit. */ |
2006 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 2007 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf PZ |
2008 | I915_WRITE(_TRANSA_CHICKEN2, val); |
2009 | ||
25f3ef11 | 2010 | val = TRANS_ENABLE; |
937bb610 | 2011 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 2012 | |
9a76b1c6 PZ |
2013 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
2014 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 2015 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
2016 | else |
2017 | val |= TRANS_PROGRESSIVE; | |
2018 | ||
ab9412ba DV |
2019 | I915_WRITE(LPT_TRANSCONF, val); |
2020 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) | |
937bb610 | 2021 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
2022 | } |
2023 | ||
b8a4f404 PZ |
2024 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
2025 | enum pipe pipe) | |
040484af | 2026 | { |
23670b32 DV |
2027 | struct drm_device *dev = dev_priv->dev; |
2028 | uint32_t reg, val; | |
040484af JB |
2029 | |
2030 | /* FDI relies on the transcoder */ | |
2031 | assert_fdi_tx_disabled(dev_priv, pipe); | |
2032 | assert_fdi_rx_disabled(dev_priv, pipe); | |
2033 | ||
291906f1 JB |
2034 | /* Ports must be off as well */ |
2035 | assert_pch_ports_disabled(dev_priv, pipe); | |
2036 | ||
ab9412ba | 2037 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
2038 | val = I915_READ(reg); |
2039 | val &= ~TRANS_ENABLE; | |
2040 | I915_WRITE(reg, val); | |
2041 | /* wait for PCH transcoder off, transcoder state */ | |
2042 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4bb6f1f3 | 2043 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 DV |
2044 | |
2045 | if (!HAS_PCH_IBX(dev)) { | |
2046 | /* Workaround: Clear the timing override chicken bit again. */ | |
2047 | reg = TRANS_CHICKEN2(pipe); | |
2048 | val = I915_READ(reg); | |
2049 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
2050 | I915_WRITE(reg, val); | |
2051 | } | |
040484af JB |
2052 | } |
2053 | ||
ab4d966c | 2054 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 2055 | { |
8fb033d7 PZ |
2056 | u32 val; |
2057 | ||
ab9412ba | 2058 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 2059 | val &= ~TRANS_ENABLE; |
ab9412ba | 2060 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 2061 | /* wait for PCH transcoder off, transcoder state */ |
ab9412ba | 2062 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
8a52fd9f | 2063 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
2064 | |
2065 | /* Workaround: clear timing override bit. */ | |
2066 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 2067 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf | 2068 | I915_WRITE(_TRANSA_CHICKEN2, val); |
040484af JB |
2069 | } |
2070 | ||
b24e7179 | 2071 | /** |
309cfea8 | 2072 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 2073 | * @crtc: crtc responsible for the pipe |
b24e7179 | 2074 | * |
0372264a | 2075 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 2076 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 2077 | */ |
e1fdc473 | 2078 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2079 | { |
0372264a PZ |
2080 | struct drm_device *dev = crtc->base.dev; |
2081 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2082 | enum pipe pipe = crtc->pipe; | |
702e7a56 PZ |
2083 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
2084 | pipe); | |
1a240d4d | 2085 | enum pipe pch_transcoder; |
b24e7179 JB |
2086 | int reg; |
2087 | u32 val; | |
2088 | ||
9e2ee2dd VS |
2089 | DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe)); |
2090 | ||
58c6eaa2 | 2091 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 2092 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
2093 | assert_sprites_disabled(dev_priv, pipe); |
2094 | ||
681e5811 | 2095 | if (HAS_PCH_LPT(dev_priv->dev)) |
cc391bbb PZ |
2096 | pch_transcoder = TRANSCODER_A; |
2097 | else | |
2098 | pch_transcoder = pipe; | |
2099 | ||
b24e7179 JB |
2100 | /* |
2101 | * A pipe without a PLL won't actually be able to drive bits from | |
2102 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
2103 | * need the check. | |
2104 | */ | |
50360403 | 2105 | if (HAS_GMCH_DISPLAY(dev_priv->dev)) |
409ee761 | 2106 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) |
23538ef1 JN |
2107 | assert_dsi_pll_enabled(dev_priv); |
2108 | else | |
2109 | assert_pll_enabled(dev_priv, pipe); | |
040484af | 2110 | else { |
6e3c9717 | 2111 | if (crtc->config->has_pch_encoder) { |
040484af | 2112 | /* if driving the PCH, we need FDI enabled */ |
cc391bbb | 2113 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
2114 | assert_fdi_tx_pll_enabled(dev_priv, |
2115 | (enum pipe) cpu_transcoder); | |
040484af JB |
2116 | } |
2117 | /* FIXME: assert CPU port conditions for SNB+ */ | |
2118 | } | |
b24e7179 | 2119 | |
702e7a56 | 2120 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2121 | val = I915_READ(reg); |
7ad25d48 | 2122 | if (val & PIPECONF_ENABLE) { |
b6b5d049 VS |
2123 | WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
2124 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); | |
00d70b15 | 2125 | return; |
7ad25d48 | 2126 | } |
00d70b15 CW |
2127 | |
2128 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 2129 | POSTING_READ(reg); |
b24e7179 JB |
2130 | } |
2131 | ||
2132 | /** | |
309cfea8 | 2133 | * intel_disable_pipe - disable a pipe, asserting requirements |
575f7ab7 | 2134 | * @crtc: crtc whose pipes is to be disabled |
b24e7179 | 2135 | * |
575f7ab7 VS |
2136 | * Disable the pipe of @crtc, making sure that various hardware |
2137 | * specific requirements are met, if applicable, e.g. plane | |
2138 | * disabled, panel fitter off, etc. | |
b24e7179 JB |
2139 | * |
2140 | * Will wait until the pipe has shut down before returning. | |
2141 | */ | |
575f7ab7 | 2142 | static void intel_disable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2143 | { |
575f7ab7 | 2144 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
6e3c9717 | 2145 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 2146 | enum pipe pipe = crtc->pipe; |
b24e7179 JB |
2147 | int reg; |
2148 | u32 val; | |
2149 | ||
9e2ee2dd VS |
2150 | DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe)); |
2151 | ||
b24e7179 JB |
2152 | /* |
2153 | * Make sure planes won't keep trying to pump pixels to us, | |
2154 | * or we might hang the display. | |
2155 | */ | |
2156 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 2157 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 2158 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 | 2159 | |
702e7a56 | 2160 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2161 | val = I915_READ(reg); |
00d70b15 CW |
2162 | if ((val & PIPECONF_ENABLE) == 0) |
2163 | return; | |
2164 | ||
67adc644 VS |
2165 | /* |
2166 | * Double wide has implications for planes | |
2167 | * so best keep it disabled when not needed. | |
2168 | */ | |
6e3c9717 | 2169 | if (crtc->config->double_wide) |
67adc644 VS |
2170 | val &= ~PIPECONF_DOUBLE_WIDE; |
2171 | ||
2172 | /* Don't disable pipe or pipe PLLs if needed */ | |
b6b5d049 VS |
2173 | if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && |
2174 | !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
67adc644 VS |
2175 | val &= ~PIPECONF_ENABLE; |
2176 | ||
2177 | I915_WRITE(reg, val); | |
2178 | if ((val & PIPECONF_ENABLE) == 0) | |
2179 | intel_wait_for_pipe_off(crtc); | |
b24e7179 JB |
2180 | } |
2181 | ||
693db184 CW |
2182 | static bool need_vtd_wa(struct drm_device *dev) |
2183 | { | |
2184 | #ifdef CONFIG_INTEL_IOMMU | |
2185 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) | |
2186 | return true; | |
2187 | #endif | |
2188 | return false; | |
2189 | } | |
2190 | ||
50470bb0 | 2191 | unsigned int |
6761dd31 TU |
2192 | intel_tile_height(struct drm_device *dev, uint32_t pixel_format, |
2193 | uint64_t fb_format_modifier) | |
a57ce0b2 | 2194 | { |
6761dd31 TU |
2195 | unsigned int tile_height; |
2196 | uint32_t pixel_bytes; | |
a57ce0b2 | 2197 | |
b5d0e9bf DL |
2198 | switch (fb_format_modifier) { |
2199 | case DRM_FORMAT_MOD_NONE: | |
2200 | tile_height = 1; | |
2201 | break; | |
2202 | case I915_FORMAT_MOD_X_TILED: | |
2203 | tile_height = IS_GEN2(dev) ? 16 : 8; | |
2204 | break; | |
2205 | case I915_FORMAT_MOD_Y_TILED: | |
2206 | tile_height = 32; | |
2207 | break; | |
2208 | case I915_FORMAT_MOD_Yf_TILED: | |
6761dd31 TU |
2209 | pixel_bytes = drm_format_plane_cpp(pixel_format, 0); |
2210 | switch (pixel_bytes) { | |
b5d0e9bf | 2211 | default: |
6761dd31 | 2212 | case 1: |
b5d0e9bf DL |
2213 | tile_height = 64; |
2214 | break; | |
6761dd31 TU |
2215 | case 2: |
2216 | case 4: | |
b5d0e9bf DL |
2217 | tile_height = 32; |
2218 | break; | |
6761dd31 | 2219 | case 8: |
b5d0e9bf DL |
2220 | tile_height = 16; |
2221 | break; | |
6761dd31 | 2222 | case 16: |
b5d0e9bf DL |
2223 | WARN_ONCE(1, |
2224 | "128-bit pixels are not supported for display!"); | |
2225 | tile_height = 16; | |
2226 | break; | |
2227 | } | |
2228 | break; | |
2229 | default: | |
2230 | MISSING_CASE(fb_format_modifier); | |
2231 | tile_height = 1; | |
2232 | break; | |
2233 | } | |
091df6cb | 2234 | |
6761dd31 TU |
2235 | return tile_height; |
2236 | } | |
2237 | ||
2238 | unsigned int | |
2239 | intel_fb_align_height(struct drm_device *dev, unsigned int height, | |
2240 | uint32_t pixel_format, uint64_t fb_format_modifier) | |
2241 | { | |
2242 | return ALIGN(height, intel_tile_height(dev, pixel_format, | |
2243 | fb_format_modifier)); | |
a57ce0b2 JB |
2244 | } |
2245 | ||
f64b98cd TU |
2246 | static int |
2247 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb, | |
2248 | const struct drm_plane_state *plane_state) | |
2249 | { | |
50470bb0 | 2250 | struct intel_rotation_info *info = &view->rotation_info; |
84fe03f7 | 2251 | unsigned int tile_height, tile_pitch; |
50470bb0 | 2252 | |
f64b98cd TU |
2253 | *view = i915_ggtt_view_normal; |
2254 | ||
50470bb0 TU |
2255 | if (!plane_state) |
2256 | return 0; | |
2257 | ||
121920fa | 2258 | if (!intel_rotation_90_or_270(plane_state->rotation)) |
50470bb0 TU |
2259 | return 0; |
2260 | ||
9abc4648 | 2261 | *view = i915_ggtt_view_rotated; |
50470bb0 TU |
2262 | |
2263 | info->height = fb->height; | |
2264 | info->pixel_format = fb->pixel_format; | |
2265 | info->pitch = fb->pitches[0]; | |
2266 | info->fb_modifier = fb->modifier[0]; | |
2267 | ||
84fe03f7 TU |
2268 | tile_height = intel_tile_height(fb->dev, fb->pixel_format, |
2269 | fb->modifier[0]); | |
2270 | tile_pitch = PAGE_SIZE / tile_height; | |
2271 | info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch); | |
2272 | info->height_pages = DIV_ROUND_UP(fb->height, tile_height); | |
2273 | info->size = info->width_pages * info->height_pages * PAGE_SIZE; | |
2274 | ||
f64b98cd TU |
2275 | return 0; |
2276 | } | |
2277 | ||
4e9a86b6 VS |
2278 | static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv) |
2279 | { | |
2280 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2281 | return 256 * 1024; | |
985b8bb4 VS |
2282 | else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) || |
2283 | IS_VALLEYVIEW(dev_priv)) | |
4e9a86b6 VS |
2284 | return 128 * 1024; |
2285 | else if (INTEL_INFO(dev_priv)->gen >= 4) | |
2286 | return 4 * 1024; | |
2287 | else | |
44c5905e | 2288 | return 0; |
4e9a86b6 VS |
2289 | } |
2290 | ||
127bd2ac | 2291 | int |
850c4cdc TU |
2292 | intel_pin_and_fence_fb_obj(struct drm_plane *plane, |
2293 | struct drm_framebuffer *fb, | |
82bc3b2d | 2294 | const struct drm_plane_state *plane_state, |
91af127f JH |
2295 | struct intel_engine_cs *pipelined, |
2296 | struct drm_i915_gem_request **pipelined_request) | |
6b95a207 | 2297 | { |
850c4cdc | 2298 | struct drm_device *dev = fb->dev; |
ce453d81 | 2299 | struct drm_i915_private *dev_priv = dev->dev_private; |
850c4cdc | 2300 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2301 | struct i915_ggtt_view view; |
6b95a207 KH |
2302 | u32 alignment; |
2303 | int ret; | |
2304 | ||
ebcdd39e MR |
2305 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2306 | ||
7b911adc TU |
2307 | switch (fb->modifier[0]) { |
2308 | case DRM_FORMAT_MOD_NONE: | |
4e9a86b6 | 2309 | alignment = intel_linear_alignment(dev_priv); |
6b95a207 | 2310 | break; |
7b911adc | 2311 | case I915_FORMAT_MOD_X_TILED: |
1fada4cc DL |
2312 | if (INTEL_INFO(dev)->gen >= 9) |
2313 | alignment = 256 * 1024; | |
2314 | else { | |
2315 | /* pin() will align the object as required by fence */ | |
2316 | alignment = 0; | |
2317 | } | |
6b95a207 | 2318 | break; |
7b911adc | 2319 | case I915_FORMAT_MOD_Y_TILED: |
1327b9a1 DL |
2320 | case I915_FORMAT_MOD_Yf_TILED: |
2321 | if (WARN_ONCE(INTEL_INFO(dev)->gen < 9, | |
2322 | "Y tiling bo slipped through, driver bug!\n")) | |
2323 | return -EINVAL; | |
2324 | alignment = 1 * 1024 * 1024; | |
2325 | break; | |
6b95a207 | 2326 | default: |
7b911adc TU |
2327 | MISSING_CASE(fb->modifier[0]); |
2328 | return -EINVAL; | |
6b95a207 KH |
2329 | } |
2330 | ||
f64b98cd TU |
2331 | ret = intel_fill_fb_ggtt_view(&view, fb, plane_state); |
2332 | if (ret) | |
2333 | return ret; | |
2334 | ||
693db184 CW |
2335 | /* Note that the w/a also requires 64 PTE of padding following the |
2336 | * bo. We currently fill all unused PTE with the shadow page and so | |
2337 | * we should always have valid PTE following the scanout preventing | |
2338 | * the VT-d warning. | |
2339 | */ | |
2340 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | |
2341 | alignment = 256 * 1024; | |
2342 | ||
d6dd6843 PZ |
2343 | /* |
2344 | * Global gtt pte registers are special registers which actually forward | |
2345 | * writes to a chunk of system memory. Which means that there is no risk | |
2346 | * that the register values disappear as soon as we call | |
2347 | * intel_runtime_pm_put(), so it is correct to wrap only the | |
2348 | * pin/unpin/fence and not more. | |
2349 | */ | |
2350 | intel_runtime_pm_get(dev_priv); | |
2351 | ||
ce453d81 | 2352 | dev_priv->mm.interruptible = false; |
e6617330 | 2353 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined, |
91af127f | 2354 | pipelined_request, &view); |
48b956c5 | 2355 | if (ret) |
ce453d81 | 2356 | goto err_interruptible; |
6b95a207 KH |
2357 | |
2358 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
2359 | * fence, whereas 965+ only requires a fence if using | |
2360 | * framebuffer compression. For simplicity, we always install | |
2361 | * a fence as the cost is not that onerous. | |
2362 | */ | |
06d98131 | 2363 | ret = i915_gem_object_get_fence(obj); |
842315ee ML |
2364 | if (ret == -EDEADLK) { |
2365 | /* | |
2366 | * -EDEADLK means there are no free fences | |
2367 | * no pending flips. | |
2368 | * | |
2369 | * This is propagated to atomic, but it uses | |
2370 | * -EDEADLK to force a locking recovery, so | |
2371 | * change the returned error to -EBUSY. | |
2372 | */ | |
2373 | ret = -EBUSY; | |
2374 | goto err_unpin; | |
2375 | } else if (ret) | |
9a5a53b3 | 2376 | goto err_unpin; |
1690e1eb | 2377 | |
9a5a53b3 | 2378 | i915_gem_object_pin_fence(obj); |
6b95a207 | 2379 | |
ce453d81 | 2380 | dev_priv->mm.interruptible = true; |
d6dd6843 | 2381 | intel_runtime_pm_put(dev_priv); |
6b95a207 | 2382 | return 0; |
48b956c5 CW |
2383 | |
2384 | err_unpin: | |
f64b98cd | 2385 | i915_gem_object_unpin_from_display_plane(obj, &view); |
ce453d81 CW |
2386 | err_interruptible: |
2387 | dev_priv->mm.interruptible = true; | |
d6dd6843 | 2388 | intel_runtime_pm_put(dev_priv); |
48b956c5 | 2389 | return ret; |
6b95a207 KH |
2390 | } |
2391 | ||
82bc3b2d TU |
2392 | static void intel_unpin_fb_obj(struct drm_framebuffer *fb, |
2393 | const struct drm_plane_state *plane_state) | |
1690e1eb | 2394 | { |
82bc3b2d | 2395 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd TU |
2396 | struct i915_ggtt_view view; |
2397 | int ret; | |
82bc3b2d | 2398 | |
ebcdd39e MR |
2399 | WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex)); |
2400 | ||
f64b98cd TU |
2401 | ret = intel_fill_fb_ggtt_view(&view, fb, plane_state); |
2402 | WARN_ONCE(ret, "Couldn't get view from plane state!"); | |
2403 | ||
1690e1eb | 2404 | i915_gem_object_unpin_fence(obj); |
f64b98cd | 2405 | i915_gem_object_unpin_from_display_plane(obj, &view); |
1690e1eb CW |
2406 | } |
2407 | ||
c2c75131 DV |
2408 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
2409 | * is assumed to be a power-of-two. */ | |
4e9a86b6 VS |
2410 | unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv, |
2411 | int *x, int *y, | |
bc752862 CW |
2412 | unsigned int tiling_mode, |
2413 | unsigned int cpp, | |
2414 | unsigned int pitch) | |
c2c75131 | 2415 | { |
bc752862 CW |
2416 | if (tiling_mode != I915_TILING_NONE) { |
2417 | unsigned int tile_rows, tiles; | |
c2c75131 | 2418 | |
bc752862 CW |
2419 | tile_rows = *y / 8; |
2420 | *y %= 8; | |
c2c75131 | 2421 | |
bc752862 CW |
2422 | tiles = *x / (512/cpp); |
2423 | *x %= 512/cpp; | |
2424 | ||
2425 | return tile_rows * pitch * 8 + tiles * 4096; | |
2426 | } else { | |
4e9a86b6 | 2427 | unsigned int alignment = intel_linear_alignment(dev_priv) - 1; |
bc752862 CW |
2428 | unsigned int offset; |
2429 | ||
2430 | offset = *y * pitch + *x * cpp; | |
4e9a86b6 VS |
2431 | *y = (offset & alignment) / pitch; |
2432 | *x = ((offset & alignment) - *y * pitch) / cpp; | |
2433 | return offset & ~alignment; | |
bc752862 | 2434 | } |
c2c75131 DV |
2435 | } |
2436 | ||
b35d63fa | 2437 | static int i9xx_format_to_fourcc(int format) |
46f297fb JB |
2438 | { |
2439 | switch (format) { | |
2440 | case DISPPLANE_8BPP: | |
2441 | return DRM_FORMAT_C8; | |
2442 | case DISPPLANE_BGRX555: | |
2443 | return DRM_FORMAT_XRGB1555; | |
2444 | case DISPPLANE_BGRX565: | |
2445 | return DRM_FORMAT_RGB565; | |
2446 | default: | |
2447 | case DISPPLANE_BGRX888: | |
2448 | return DRM_FORMAT_XRGB8888; | |
2449 | case DISPPLANE_RGBX888: | |
2450 | return DRM_FORMAT_XBGR8888; | |
2451 | case DISPPLANE_BGRX101010: | |
2452 | return DRM_FORMAT_XRGB2101010; | |
2453 | case DISPPLANE_RGBX101010: | |
2454 | return DRM_FORMAT_XBGR2101010; | |
2455 | } | |
2456 | } | |
2457 | ||
bc8d7dff DL |
2458 | static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) |
2459 | { | |
2460 | switch (format) { | |
2461 | case PLANE_CTL_FORMAT_RGB_565: | |
2462 | return DRM_FORMAT_RGB565; | |
2463 | default: | |
2464 | case PLANE_CTL_FORMAT_XRGB_8888: | |
2465 | if (rgb_order) { | |
2466 | if (alpha) | |
2467 | return DRM_FORMAT_ABGR8888; | |
2468 | else | |
2469 | return DRM_FORMAT_XBGR8888; | |
2470 | } else { | |
2471 | if (alpha) | |
2472 | return DRM_FORMAT_ARGB8888; | |
2473 | else | |
2474 | return DRM_FORMAT_XRGB8888; | |
2475 | } | |
2476 | case PLANE_CTL_FORMAT_XRGB_2101010: | |
2477 | if (rgb_order) | |
2478 | return DRM_FORMAT_XBGR2101010; | |
2479 | else | |
2480 | return DRM_FORMAT_XRGB2101010; | |
2481 | } | |
2482 | } | |
2483 | ||
5724dbd1 | 2484 | static bool |
f6936e29 DV |
2485 | intel_alloc_initial_plane_obj(struct intel_crtc *crtc, |
2486 | struct intel_initial_plane_config *plane_config) | |
46f297fb JB |
2487 | { |
2488 | struct drm_device *dev = crtc->base.dev; | |
2489 | struct drm_i915_gem_object *obj = NULL; | |
2490 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2d14030b | 2491 | struct drm_framebuffer *fb = &plane_config->fb->base; |
f37b5c2b DV |
2492 | u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); |
2493 | u32 size_aligned = round_up(plane_config->base + plane_config->size, | |
2494 | PAGE_SIZE); | |
2495 | ||
2496 | size_aligned -= base_aligned; | |
46f297fb | 2497 | |
ff2652ea CW |
2498 | if (plane_config->size == 0) |
2499 | return false; | |
2500 | ||
f37b5c2b DV |
2501 | obj = i915_gem_object_create_stolen_for_preallocated(dev, |
2502 | base_aligned, | |
2503 | base_aligned, | |
2504 | size_aligned); | |
46f297fb | 2505 | if (!obj) |
484b41dd | 2506 | return false; |
46f297fb | 2507 | |
49af449b DL |
2508 | obj->tiling_mode = plane_config->tiling; |
2509 | if (obj->tiling_mode == I915_TILING_X) | |
6bf129df | 2510 | obj->stride = fb->pitches[0]; |
46f297fb | 2511 | |
6bf129df DL |
2512 | mode_cmd.pixel_format = fb->pixel_format; |
2513 | mode_cmd.width = fb->width; | |
2514 | mode_cmd.height = fb->height; | |
2515 | mode_cmd.pitches[0] = fb->pitches[0]; | |
18c5247e DV |
2516 | mode_cmd.modifier[0] = fb->modifier[0]; |
2517 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; | |
46f297fb JB |
2518 | |
2519 | mutex_lock(&dev->struct_mutex); | |
6bf129df | 2520 | if (intel_framebuffer_init(dev, to_intel_framebuffer(fb), |
484b41dd | 2521 | &mode_cmd, obj)) { |
46f297fb JB |
2522 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2523 | goto out_unref_obj; | |
2524 | } | |
46f297fb | 2525 | mutex_unlock(&dev->struct_mutex); |
484b41dd | 2526 | |
f6936e29 | 2527 | DRM_DEBUG_KMS("initial plane fb obj %p\n", obj); |
484b41dd | 2528 | return true; |
46f297fb JB |
2529 | |
2530 | out_unref_obj: | |
2531 | drm_gem_object_unreference(&obj->base); | |
2532 | mutex_unlock(&dev->struct_mutex); | |
484b41dd JB |
2533 | return false; |
2534 | } | |
2535 | ||
afd65eb4 MR |
2536 | /* Update plane->state->fb to match plane->fb after driver-internal updates */ |
2537 | static void | |
2538 | update_state_fb(struct drm_plane *plane) | |
2539 | { | |
2540 | if (plane->fb == plane->state->fb) | |
2541 | return; | |
2542 | ||
2543 | if (plane->state->fb) | |
2544 | drm_framebuffer_unreference(plane->state->fb); | |
2545 | plane->state->fb = plane->fb; | |
2546 | if (plane->state->fb) | |
2547 | drm_framebuffer_reference(plane->state->fb); | |
2548 | } | |
2549 | ||
5724dbd1 | 2550 | static void |
f6936e29 DV |
2551 | intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, |
2552 | struct intel_initial_plane_config *plane_config) | |
484b41dd JB |
2553 | { |
2554 | struct drm_device *dev = intel_crtc->base.dev; | |
d9ceb816 | 2555 | struct drm_i915_private *dev_priv = dev->dev_private; |
484b41dd JB |
2556 | struct drm_crtc *c; |
2557 | struct intel_crtc *i; | |
2ff8fde1 | 2558 | struct drm_i915_gem_object *obj; |
88595ac9 | 2559 | struct drm_plane *primary = intel_crtc->base.primary; |
be5651f2 | 2560 | struct drm_plane_state *plane_state = primary->state; |
88595ac9 | 2561 | struct drm_framebuffer *fb; |
484b41dd | 2562 | |
2d14030b | 2563 | if (!plane_config->fb) |
484b41dd JB |
2564 | return; |
2565 | ||
f6936e29 | 2566 | if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { |
88595ac9 DV |
2567 | fb = &plane_config->fb->base; |
2568 | goto valid_fb; | |
f55548b5 | 2569 | } |
484b41dd | 2570 | |
2d14030b | 2571 | kfree(plane_config->fb); |
484b41dd JB |
2572 | |
2573 | /* | |
2574 | * Failed to alloc the obj, check to see if we should share | |
2575 | * an fb with another CRTC instead | |
2576 | */ | |
70e1e0ec | 2577 | for_each_crtc(dev, c) { |
484b41dd JB |
2578 | i = to_intel_crtc(c); |
2579 | ||
2580 | if (c == &intel_crtc->base) | |
2581 | continue; | |
2582 | ||
2ff8fde1 MR |
2583 | if (!i->active) |
2584 | continue; | |
2585 | ||
88595ac9 DV |
2586 | fb = c->primary->fb; |
2587 | if (!fb) | |
484b41dd JB |
2588 | continue; |
2589 | ||
88595ac9 | 2590 | obj = intel_fb_obj(fb); |
2ff8fde1 | 2591 | if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) { |
88595ac9 DV |
2592 | drm_framebuffer_reference(fb); |
2593 | goto valid_fb; | |
484b41dd JB |
2594 | } |
2595 | } | |
88595ac9 DV |
2596 | |
2597 | return; | |
2598 | ||
2599 | valid_fb: | |
be5651f2 ML |
2600 | plane_state->src_x = plane_state->src_y = 0; |
2601 | plane_state->src_w = fb->width << 16; | |
2602 | plane_state->src_h = fb->height << 16; | |
2603 | ||
2604 | plane_state->crtc_x = plane_state->src_y = 0; | |
2605 | plane_state->crtc_w = fb->width; | |
2606 | plane_state->crtc_h = fb->height; | |
2607 | ||
88595ac9 DV |
2608 | obj = intel_fb_obj(fb); |
2609 | if (obj->tiling_mode != I915_TILING_NONE) | |
2610 | dev_priv->preserve_bios_swizzle = true; | |
2611 | ||
be5651f2 ML |
2612 | drm_framebuffer_reference(fb); |
2613 | primary->fb = primary->state->fb = fb; | |
36750f28 | 2614 | primary->crtc = primary->state->crtc = &intel_crtc->base; |
36750f28 | 2615 | intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary)); |
a9ff8714 | 2616 | obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit; |
46f297fb JB |
2617 | } |
2618 | ||
29b9bde6 DV |
2619 | static void i9xx_update_primary_plane(struct drm_crtc *crtc, |
2620 | struct drm_framebuffer *fb, | |
2621 | int x, int y) | |
81255565 JB |
2622 | { |
2623 | struct drm_device *dev = crtc->dev; | |
2624 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2625 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b70709a6 ML |
2626 | struct drm_plane *primary = crtc->primary; |
2627 | bool visible = to_intel_plane_state(primary->state)->visible; | |
c9ba6fad | 2628 | struct drm_i915_gem_object *obj; |
81255565 | 2629 | int plane = intel_crtc->plane; |
e506a0c6 | 2630 | unsigned long linear_offset; |
81255565 | 2631 | u32 dspcntr; |
f45651ba | 2632 | u32 reg = DSPCNTR(plane); |
48404c1e | 2633 | int pixel_size; |
f45651ba | 2634 | |
b70709a6 | 2635 | if (!visible || !fb) { |
fdd508a6 VS |
2636 | I915_WRITE(reg, 0); |
2637 | if (INTEL_INFO(dev)->gen >= 4) | |
2638 | I915_WRITE(DSPSURF(plane), 0); | |
2639 | else | |
2640 | I915_WRITE(DSPADDR(plane), 0); | |
2641 | POSTING_READ(reg); | |
2642 | return; | |
2643 | } | |
2644 | ||
c9ba6fad VS |
2645 | obj = intel_fb_obj(fb); |
2646 | if (WARN_ON(obj == NULL)) | |
2647 | return; | |
2648 | ||
2649 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
2650 | ||
f45651ba VS |
2651 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2652 | ||
fdd508a6 | 2653 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2654 | |
2655 | if (INTEL_INFO(dev)->gen < 4) { | |
2656 | if (intel_crtc->pipe == PIPE_B) | |
2657 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
2658 | ||
2659 | /* pipesrc and dspsize control the size that is scaled from, | |
2660 | * which should always be the user's requested size. | |
2661 | */ | |
2662 | I915_WRITE(DSPSIZE(plane), | |
6e3c9717 ACO |
2663 | ((intel_crtc->config->pipe_src_h - 1) << 16) | |
2664 | (intel_crtc->config->pipe_src_w - 1)); | |
f45651ba | 2665 | I915_WRITE(DSPPOS(plane), 0); |
c14b0485 VS |
2666 | } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) { |
2667 | I915_WRITE(PRIMSIZE(plane), | |
6e3c9717 ACO |
2668 | ((intel_crtc->config->pipe_src_h - 1) << 16) | |
2669 | (intel_crtc->config->pipe_src_w - 1)); | |
c14b0485 VS |
2670 | I915_WRITE(PRIMPOS(plane), 0); |
2671 | I915_WRITE(PRIMCNSTALPHA(plane), 0); | |
f45651ba | 2672 | } |
81255565 | 2673 | |
57779d06 VS |
2674 | switch (fb->pixel_format) { |
2675 | case DRM_FORMAT_C8: | |
81255565 JB |
2676 | dspcntr |= DISPPLANE_8BPP; |
2677 | break; | |
57779d06 | 2678 | case DRM_FORMAT_XRGB1555: |
57779d06 | 2679 | dspcntr |= DISPPLANE_BGRX555; |
81255565 | 2680 | break; |
57779d06 VS |
2681 | case DRM_FORMAT_RGB565: |
2682 | dspcntr |= DISPPLANE_BGRX565; | |
2683 | break; | |
2684 | case DRM_FORMAT_XRGB8888: | |
57779d06 VS |
2685 | dspcntr |= DISPPLANE_BGRX888; |
2686 | break; | |
2687 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
2688 | dspcntr |= DISPPLANE_RGBX888; |
2689 | break; | |
2690 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2691 | dspcntr |= DISPPLANE_BGRX101010; |
2692 | break; | |
2693 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 2694 | dspcntr |= DISPPLANE_RGBX101010; |
81255565 JB |
2695 | break; |
2696 | default: | |
baba133a | 2697 | BUG(); |
81255565 | 2698 | } |
57779d06 | 2699 | |
f45651ba VS |
2700 | if (INTEL_INFO(dev)->gen >= 4 && |
2701 | obj->tiling_mode != I915_TILING_NONE) | |
2702 | dspcntr |= DISPPLANE_TILED; | |
81255565 | 2703 | |
de1aa629 VS |
2704 | if (IS_G4X(dev)) |
2705 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2706 | ||
b9897127 | 2707 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
81255565 | 2708 | |
c2c75131 DV |
2709 | if (INTEL_INFO(dev)->gen >= 4) { |
2710 | intel_crtc->dspaddr_offset = | |
4e9a86b6 VS |
2711 | intel_gen4_compute_page_offset(dev_priv, |
2712 | &x, &y, obj->tiling_mode, | |
b9897127 | 2713 | pixel_size, |
bc752862 | 2714 | fb->pitches[0]); |
c2c75131 DV |
2715 | linear_offset -= intel_crtc->dspaddr_offset; |
2716 | } else { | |
e506a0c6 | 2717 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2718 | } |
e506a0c6 | 2719 | |
8e7d688b | 2720 | if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2721 | dspcntr |= DISPPLANE_ROTATE_180; |
2722 | ||
6e3c9717 ACO |
2723 | x += (intel_crtc->config->pipe_src_w - 1); |
2724 | y += (intel_crtc->config->pipe_src_h - 1); | |
48404c1e SJ |
2725 | |
2726 | /* Finding the last pixel of the last line of the display | |
2727 | data and adding to linear_offset*/ | |
2728 | linear_offset += | |
6e3c9717 ACO |
2729 | (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] + |
2730 | (intel_crtc->config->pipe_src_w - 1) * pixel_size; | |
48404c1e SJ |
2731 | } |
2732 | ||
2db3366b PZ |
2733 | intel_crtc->adjusted_x = x; |
2734 | intel_crtc->adjusted_y = y; | |
2735 | ||
48404c1e SJ |
2736 | I915_WRITE(reg, dspcntr); |
2737 | ||
01f2c773 | 2738 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2739 | if (INTEL_INFO(dev)->gen >= 4) { |
85ba7b7d DV |
2740 | I915_WRITE(DSPSURF(plane), |
2741 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
5eddb70b | 2742 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2743 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2744 | } else |
f343c5f6 | 2745 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2746 | POSTING_READ(reg); |
17638cd6 JB |
2747 | } |
2748 | ||
29b9bde6 DV |
2749 | static void ironlake_update_primary_plane(struct drm_crtc *crtc, |
2750 | struct drm_framebuffer *fb, | |
2751 | int x, int y) | |
17638cd6 JB |
2752 | { |
2753 | struct drm_device *dev = crtc->dev; | |
2754 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2755 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b70709a6 ML |
2756 | struct drm_plane *primary = crtc->primary; |
2757 | bool visible = to_intel_plane_state(primary->state)->visible; | |
c9ba6fad | 2758 | struct drm_i915_gem_object *obj; |
17638cd6 | 2759 | int plane = intel_crtc->plane; |
e506a0c6 | 2760 | unsigned long linear_offset; |
17638cd6 | 2761 | u32 dspcntr; |
f45651ba | 2762 | u32 reg = DSPCNTR(plane); |
48404c1e | 2763 | int pixel_size; |
f45651ba | 2764 | |
b70709a6 | 2765 | if (!visible || !fb) { |
fdd508a6 VS |
2766 | I915_WRITE(reg, 0); |
2767 | I915_WRITE(DSPSURF(plane), 0); | |
2768 | POSTING_READ(reg); | |
2769 | return; | |
2770 | } | |
2771 | ||
c9ba6fad VS |
2772 | obj = intel_fb_obj(fb); |
2773 | if (WARN_ON(obj == NULL)) | |
2774 | return; | |
2775 | ||
2776 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
2777 | ||
f45651ba VS |
2778 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2779 | ||
fdd508a6 | 2780 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2781 | |
2782 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
2783 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; | |
17638cd6 | 2784 | |
57779d06 VS |
2785 | switch (fb->pixel_format) { |
2786 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2787 | dspcntr |= DISPPLANE_8BPP; |
2788 | break; | |
57779d06 VS |
2789 | case DRM_FORMAT_RGB565: |
2790 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2791 | break; |
57779d06 | 2792 | case DRM_FORMAT_XRGB8888: |
57779d06 VS |
2793 | dspcntr |= DISPPLANE_BGRX888; |
2794 | break; | |
2795 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
2796 | dspcntr |= DISPPLANE_RGBX888; |
2797 | break; | |
2798 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2799 | dspcntr |= DISPPLANE_BGRX101010; |
2800 | break; | |
2801 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 2802 | dspcntr |= DISPPLANE_RGBX101010; |
17638cd6 JB |
2803 | break; |
2804 | default: | |
baba133a | 2805 | BUG(); |
17638cd6 JB |
2806 | } |
2807 | ||
2808 | if (obj->tiling_mode != I915_TILING_NONE) | |
2809 | dspcntr |= DISPPLANE_TILED; | |
17638cd6 | 2810 | |
f45651ba | 2811 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) |
1f5d76db | 2812 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
17638cd6 | 2813 | |
b9897127 | 2814 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
c2c75131 | 2815 | intel_crtc->dspaddr_offset = |
4e9a86b6 VS |
2816 | intel_gen4_compute_page_offset(dev_priv, |
2817 | &x, &y, obj->tiling_mode, | |
b9897127 | 2818 | pixel_size, |
bc752862 | 2819 | fb->pitches[0]); |
c2c75131 | 2820 | linear_offset -= intel_crtc->dspaddr_offset; |
8e7d688b | 2821 | if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2822 | dspcntr |= DISPPLANE_ROTATE_180; |
2823 | ||
2824 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { | |
6e3c9717 ACO |
2825 | x += (intel_crtc->config->pipe_src_w - 1); |
2826 | y += (intel_crtc->config->pipe_src_h - 1); | |
48404c1e SJ |
2827 | |
2828 | /* Finding the last pixel of the last line of the display | |
2829 | data and adding to linear_offset*/ | |
2830 | linear_offset += | |
6e3c9717 ACO |
2831 | (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] + |
2832 | (intel_crtc->config->pipe_src_w - 1) * pixel_size; | |
48404c1e SJ |
2833 | } |
2834 | } | |
2835 | ||
2db3366b PZ |
2836 | intel_crtc->adjusted_x = x; |
2837 | intel_crtc->adjusted_y = y; | |
2838 | ||
48404c1e | 2839 | I915_WRITE(reg, dspcntr); |
17638cd6 | 2840 | |
01f2c773 | 2841 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d DV |
2842 | I915_WRITE(DSPSURF(plane), |
2843 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
b3dc685e | 2844 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
bc1c91eb DL |
2845 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2846 | } else { | |
2847 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2848 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2849 | } | |
17638cd6 | 2850 | POSTING_READ(reg); |
17638cd6 JB |
2851 | } |
2852 | ||
b321803d DL |
2853 | u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier, |
2854 | uint32_t pixel_format) | |
2855 | { | |
2856 | u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8; | |
2857 | ||
2858 | /* | |
2859 | * The stride is either expressed as a multiple of 64 bytes | |
2860 | * chunks for linear buffers or in number of tiles for tiled | |
2861 | * buffers. | |
2862 | */ | |
2863 | switch (fb_modifier) { | |
2864 | case DRM_FORMAT_MOD_NONE: | |
2865 | return 64; | |
2866 | case I915_FORMAT_MOD_X_TILED: | |
2867 | if (INTEL_INFO(dev)->gen == 2) | |
2868 | return 128; | |
2869 | return 512; | |
2870 | case I915_FORMAT_MOD_Y_TILED: | |
2871 | /* No need to check for old gens and Y tiling since this is | |
2872 | * about the display engine and those will be blocked before | |
2873 | * we get here. | |
2874 | */ | |
2875 | return 128; | |
2876 | case I915_FORMAT_MOD_Yf_TILED: | |
2877 | if (bits_per_pixel == 8) | |
2878 | return 64; | |
2879 | else | |
2880 | return 128; | |
2881 | default: | |
2882 | MISSING_CASE(fb_modifier); | |
2883 | return 64; | |
2884 | } | |
2885 | } | |
2886 | ||
121920fa TU |
2887 | unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane, |
2888 | struct drm_i915_gem_object *obj) | |
2889 | { | |
9abc4648 | 2890 | const struct i915_ggtt_view *view = &i915_ggtt_view_normal; |
121920fa TU |
2891 | |
2892 | if (intel_rotation_90_or_270(intel_plane->base.state->rotation)) | |
9abc4648 | 2893 | view = &i915_ggtt_view_rotated; |
121920fa TU |
2894 | |
2895 | return i915_gem_obj_ggtt_offset_view(obj, view); | |
2896 | } | |
2897 | ||
e435d6e5 ML |
2898 | static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id) |
2899 | { | |
2900 | struct drm_device *dev = intel_crtc->base.dev; | |
2901 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2902 | ||
2903 | I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0); | |
2904 | I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0); | |
2905 | I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0); | |
e435d6e5 ML |
2906 | } |
2907 | ||
a1b2278e CK |
2908 | /* |
2909 | * This function detaches (aka. unbinds) unused scalers in hardware | |
2910 | */ | |
0583236e | 2911 | static void skl_detach_scalers(struct intel_crtc *intel_crtc) |
a1b2278e | 2912 | { |
a1b2278e CK |
2913 | struct intel_crtc_scaler_state *scaler_state; |
2914 | int i; | |
2915 | ||
a1b2278e CK |
2916 | scaler_state = &intel_crtc->config->scaler_state; |
2917 | ||
2918 | /* loop through and disable scalers that aren't in use */ | |
2919 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
e435d6e5 ML |
2920 | if (!scaler_state->scalers[i].in_use) |
2921 | skl_detach_scaler(intel_crtc, i); | |
a1b2278e CK |
2922 | } |
2923 | } | |
2924 | ||
6156a456 | 2925 | u32 skl_plane_ctl_format(uint32_t pixel_format) |
70d21f0e | 2926 | { |
6156a456 | 2927 | switch (pixel_format) { |
d161cf7a | 2928 | case DRM_FORMAT_C8: |
c34ce3d1 | 2929 | return PLANE_CTL_FORMAT_INDEXED; |
70d21f0e | 2930 | case DRM_FORMAT_RGB565: |
c34ce3d1 | 2931 | return PLANE_CTL_FORMAT_RGB_565; |
70d21f0e | 2932 | case DRM_FORMAT_XBGR8888: |
c34ce3d1 | 2933 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; |
6156a456 | 2934 | case DRM_FORMAT_XRGB8888: |
c34ce3d1 | 2935 | return PLANE_CTL_FORMAT_XRGB_8888; |
6156a456 CK |
2936 | /* |
2937 | * XXX: For ARBG/ABGR formats we default to expecting scanout buffers | |
2938 | * to be already pre-multiplied. We need to add a knob (or a different | |
2939 | * DRM_FORMAT) for user-space to configure that. | |
2940 | */ | |
f75fb42a | 2941 | case DRM_FORMAT_ABGR8888: |
c34ce3d1 | 2942 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX | |
6156a456 | 2943 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
6156a456 | 2944 | case DRM_FORMAT_ARGB8888: |
c34ce3d1 | 2945 | return PLANE_CTL_FORMAT_XRGB_8888 | |
6156a456 | 2946 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
70d21f0e | 2947 | case DRM_FORMAT_XRGB2101010: |
c34ce3d1 | 2948 | return PLANE_CTL_FORMAT_XRGB_2101010; |
70d21f0e | 2949 | case DRM_FORMAT_XBGR2101010: |
c34ce3d1 | 2950 | return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; |
6156a456 | 2951 | case DRM_FORMAT_YUYV: |
c34ce3d1 | 2952 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; |
6156a456 | 2953 | case DRM_FORMAT_YVYU: |
c34ce3d1 | 2954 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; |
6156a456 | 2955 | case DRM_FORMAT_UYVY: |
c34ce3d1 | 2956 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; |
6156a456 | 2957 | case DRM_FORMAT_VYUY: |
c34ce3d1 | 2958 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; |
70d21f0e | 2959 | default: |
4249eeef | 2960 | MISSING_CASE(pixel_format); |
70d21f0e | 2961 | } |
8cfcba41 | 2962 | |
c34ce3d1 | 2963 | return 0; |
6156a456 | 2964 | } |
70d21f0e | 2965 | |
6156a456 CK |
2966 | u32 skl_plane_ctl_tiling(uint64_t fb_modifier) |
2967 | { | |
6156a456 | 2968 | switch (fb_modifier) { |
30af77c4 | 2969 | case DRM_FORMAT_MOD_NONE: |
70d21f0e | 2970 | break; |
30af77c4 | 2971 | case I915_FORMAT_MOD_X_TILED: |
c34ce3d1 | 2972 | return PLANE_CTL_TILED_X; |
b321803d | 2973 | case I915_FORMAT_MOD_Y_TILED: |
c34ce3d1 | 2974 | return PLANE_CTL_TILED_Y; |
b321803d | 2975 | case I915_FORMAT_MOD_Yf_TILED: |
c34ce3d1 | 2976 | return PLANE_CTL_TILED_YF; |
70d21f0e | 2977 | default: |
6156a456 | 2978 | MISSING_CASE(fb_modifier); |
70d21f0e | 2979 | } |
8cfcba41 | 2980 | |
c34ce3d1 | 2981 | return 0; |
6156a456 | 2982 | } |
70d21f0e | 2983 | |
6156a456 CK |
2984 | u32 skl_plane_ctl_rotation(unsigned int rotation) |
2985 | { | |
3b7a5119 | 2986 | switch (rotation) { |
6156a456 CK |
2987 | case BIT(DRM_ROTATE_0): |
2988 | break; | |
1e8df167 SJ |
2989 | /* |
2990 | * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr | |
2991 | * while i915 HW rotation is clockwise, thats why this swapping. | |
2992 | */ | |
3b7a5119 | 2993 | case BIT(DRM_ROTATE_90): |
1e8df167 | 2994 | return PLANE_CTL_ROTATE_270; |
3b7a5119 | 2995 | case BIT(DRM_ROTATE_180): |
c34ce3d1 | 2996 | return PLANE_CTL_ROTATE_180; |
3b7a5119 | 2997 | case BIT(DRM_ROTATE_270): |
1e8df167 | 2998 | return PLANE_CTL_ROTATE_90; |
6156a456 CK |
2999 | default: |
3000 | MISSING_CASE(rotation); | |
3001 | } | |
3002 | ||
c34ce3d1 | 3003 | return 0; |
6156a456 CK |
3004 | } |
3005 | ||
3006 | static void skylake_update_primary_plane(struct drm_crtc *crtc, | |
3007 | struct drm_framebuffer *fb, | |
3008 | int x, int y) | |
3009 | { | |
3010 | struct drm_device *dev = crtc->dev; | |
3011 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3012 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b70709a6 ML |
3013 | struct drm_plane *plane = crtc->primary; |
3014 | bool visible = to_intel_plane_state(plane->state)->visible; | |
6156a456 CK |
3015 | struct drm_i915_gem_object *obj; |
3016 | int pipe = intel_crtc->pipe; | |
3017 | u32 plane_ctl, stride_div, stride; | |
3018 | u32 tile_height, plane_offset, plane_size; | |
3019 | unsigned int rotation; | |
3020 | int x_offset, y_offset; | |
3021 | unsigned long surf_addr; | |
6156a456 CK |
3022 | struct intel_crtc_state *crtc_state = intel_crtc->config; |
3023 | struct intel_plane_state *plane_state; | |
3024 | int src_x = 0, src_y = 0, src_w = 0, src_h = 0; | |
3025 | int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0; | |
3026 | int scaler_id = -1; | |
3027 | ||
6156a456 CK |
3028 | plane_state = to_intel_plane_state(plane->state); |
3029 | ||
b70709a6 | 3030 | if (!visible || !fb) { |
6156a456 CK |
3031 | I915_WRITE(PLANE_CTL(pipe, 0), 0); |
3032 | I915_WRITE(PLANE_SURF(pipe, 0), 0); | |
3033 | POSTING_READ(PLANE_CTL(pipe, 0)); | |
3034 | return; | |
3b7a5119 | 3035 | } |
70d21f0e | 3036 | |
6156a456 CK |
3037 | plane_ctl = PLANE_CTL_ENABLE | |
3038 | PLANE_CTL_PIPE_GAMMA_ENABLE | | |
3039 | PLANE_CTL_PIPE_CSC_ENABLE; | |
3040 | ||
3041 | plane_ctl |= skl_plane_ctl_format(fb->pixel_format); | |
3042 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]); | |
3043 | plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; | |
3044 | ||
3045 | rotation = plane->state->rotation; | |
3046 | plane_ctl |= skl_plane_ctl_rotation(rotation); | |
3047 | ||
b321803d DL |
3048 | obj = intel_fb_obj(fb); |
3049 | stride_div = intel_fb_stride_alignment(dev, fb->modifier[0], | |
3050 | fb->pixel_format); | |
3b7a5119 SJ |
3051 | surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj); |
3052 | ||
6156a456 CK |
3053 | /* |
3054 | * FIXME: intel_plane_state->src, dst aren't set when transitional | |
3055 | * update_plane helpers are called from legacy paths. | |
3056 | * Once full atomic crtc is available, below check can be avoided. | |
3057 | */ | |
3058 | if (drm_rect_width(&plane_state->src)) { | |
3059 | scaler_id = plane_state->scaler_id; | |
3060 | src_x = plane_state->src.x1 >> 16; | |
3061 | src_y = plane_state->src.y1 >> 16; | |
3062 | src_w = drm_rect_width(&plane_state->src) >> 16; | |
3063 | src_h = drm_rect_height(&plane_state->src) >> 16; | |
3064 | dst_x = plane_state->dst.x1; | |
3065 | dst_y = plane_state->dst.y1; | |
3066 | dst_w = drm_rect_width(&plane_state->dst); | |
3067 | dst_h = drm_rect_height(&plane_state->dst); | |
3068 | ||
3069 | WARN_ON(x != src_x || y != src_y); | |
3070 | } else { | |
3071 | src_w = intel_crtc->config->pipe_src_w; | |
3072 | src_h = intel_crtc->config->pipe_src_h; | |
3073 | } | |
3074 | ||
3b7a5119 SJ |
3075 | if (intel_rotation_90_or_270(rotation)) { |
3076 | /* stride = Surface height in tiles */ | |
2614f17d | 3077 | tile_height = intel_tile_height(dev, fb->pixel_format, |
3b7a5119 SJ |
3078 | fb->modifier[0]); |
3079 | stride = DIV_ROUND_UP(fb->height, tile_height); | |
6156a456 | 3080 | x_offset = stride * tile_height - y - src_h; |
3b7a5119 | 3081 | y_offset = x; |
6156a456 | 3082 | plane_size = (src_w - 1) << 16 | (src_h - 1); |
3b7a5119 SJ |
3083 | } else { |
3084 | stride = fb->pitches[0] / stride_div; | |
3085 | x_offset = x; | |
3086 | y_offset = y; | |
6156a456 | 3087 | plane_size = (src_h - 1) << 16 | (src_w - 1); |
3b7a5119 SJ |
3088 | } |
3089 | plane_offset = y_offset << 16 | x_offset; | |
b321803d | 3090 | |
2db3366b PZ |
3091 | intel_crtc->adjusted_x = x_offset; |
3092 | intel_crtc->adjusted_y = y_offset; | |
3093 | ||
70d21f0e | 3094 | I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); |
3b7a5119 SJ |
3095 | I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset); |
3096 | I915_WRITE(PLANE_SIZE(pipe, 0), plane_size); | |
3097 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
6156a456 CK |
3098 | |
3099 | if (scaler_id >= 0) { | |
3100 | uint32_t ps_ctrl = 0; | |
3101 | ||
3102 | WARN_ON(!dst_w || !dst_h); | |
3103 | ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) | | |
3104 | crtc_state->scaler_state.scalers[scaler_id].mode; | |
3105 | I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); | |
3106 | I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); | |
3107 | I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y); | |
3108 | I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h); | |
3109 | I915_WRITE(PLANE_POS(pipe, 0), 0); | |
3110 | } else { | |
3111 | I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x); | |
3112 | } | |
3113 | ||
121920fa | 3114 | I915_WRITE(PLANE_SURF(pipe, 0), surf_addr); |
70d21f0e DL |
3115 | |
3116 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3117 | } | |
3118 | ||
17638cd6 JB |
3119 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
3120 | static int | |
3121 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
3122 | int x, int y, enum mode_set_atomic state) | |
3123 | { | |
3124 | struct drm_device *dev = crtc->dev; | |
3125 | struct drm_i915_private *dev_priv = dev->dev_private; | |
17638cd6 | 3126 | |
ff2a3117 | 3127 | if (dev_priv->fbc.disable_fbc) |
7733b49b | 3128 | dev_priv->fbc.disable_fbc(dev_priv); |
81255565 | 3129 | |
29b9bde6 DV |
3130 | dev_priv->display.update_primary_plane(crtc, fb, x, y); |
3131 | ||
3132 | return 0; | |
81255565 JB |
3133 | } |
3134 | ||
7514747d | 3135 | static void intel_complete_page_flips(struct drm_device *dev) |
96a02917 | 3136 | { |
96a02917 VS |
3137 | struct drm_crtc *crtc; |
3138 | ||
70e1e0ec | 3139 | for_each_crtc(dev, crtc) { |
96a02917 VS |
3140 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3141 | enum plane plane = intel_crtc->plane; | |
3142 | ||
3143 | intel_prepare_page_flip(dev, plane); | |
3144 | intel_finish_page_flip_plane(dev, plane); | |
3145 | } | |
7514747d VS |
3146 | } |
3147 | ||
3148 | static void intel_update_primary_planes(struct drm_device *dev) | |
3149 | { | |
7514747d | 3150 | struct drm_crtc *crtc; |
96a02917 | 3151 | |
70e1e0ec | 3152 | for_each_crtc(dev, crtc) { |
11c22da6 ML |
3153 | struct intel_plane *plane = to_intel_plane(crtc->primary); |
3154 | struct intel_plane_state *plane_state; | |
96a02917 | 3155 | |
11c22da6 ML |
3156 | drm_modeset_lock_crtc(crtc, &plane->base); |
3157 | ||
3158 | plane_state = to_intel_plane_state(plane->base.state); | |
3159 | ||
3160 | if (plane_state->base.fb) | |
3161 | plane->commit_plane(&plane->base, plane_state); | |
3162 | ||
3163 | drm_modeset_unlock_crtc(crtc); | |
96a02917 VS |
3164 | } |
3165 | } | |
3166 | ||
7514747d VS |
3167 | void intel_prepare_reset(struct drm_device *dev) |
3168 | { | |
3169 | /* no reset support for gen2 */ | |
3170 | if (IS_GEN2(dev)) | |
3171 | return; | |
3172 | ||
3173 | /* reset doesn't touch the display */ | |
3174 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
3175 | return; | |
3176 | ||
3177 | drm_modeset_lock_all(dev); | |
f98ce92f VS |
3178 | /* |
3179 | * Disabling the crtcs gracefully seems nicer. Also the | |
3180 | * g33 docs say we should at least disable all the planes. | |
3181 | */ | |
6b72d486 | 3182 | intel_display_suspend(dev); |
7514747d VS |
3183 | } |
3184 | ||
3185 | void intel_finish_reset(struct drm_device *dev) | |
3186 | { | |
3187 | struct drm_i915_private *dev_priv = to_i915(dev); | |
3188 | ||
3189 | /* | |
3190 | * Flips in the rings will be nuked by the reset, | |
3191 | * so complete all pending flips so that user space | |
3192 | * will get its events and not get stuck. | |
3193 | */ | |
3194 | intel_complete_page_flips(dev); | |
3195 | ||
3196 | /* no reset support for gen2 */ | |
3197 | if (IS_GEN2(dev)) | |
3198 | return; | |
3199 | ||
3200 | /* reset doesn't touch the display */ | |
3201 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) { | |
3202 | /* | |
3203 | * Flips in the rings have been nuked by the reset, | |
3204 | * so update the base address of all primary | |
3205 | * planes to the the last fb to make sure we're | |
3206 | * showing the correct fb after a reset. | |
11c22da6 ML |
3207 | * |
3208 | * FIXME: Atomic will make this obsolete since we won't schedule | |
3209 | * CS-based flips (which might get lost in gpu resets) any more. | |
7514747d VS |
3210 | */ |
3211 | intel_update_primary_planes(dev); | |
3212 | return; | |
3213 | } | |
3214 | ||
3215 | /* | |
3216 | * The display has been reset as well, | |
3217 | * so need a full re-initialization. | |
3218 | */ | |
3219 | intel_runtime_pm_disable_interrupts(dev_priv); | |
3220 | intel_runtime_pm_enable_interrupts(dev_priv); | |
3221 | ||
3222 | intel_modeset_init_hw(dev); | |
3223 | ||
3224 | spin_lock_irq(&dev_priv->irq_lock); | |
3225 | if (dev_priv->display.hpd_irq_setup) | |
3226 | dev_priv->display.hpd_irq_setup(dev); | |
3227 | spin_unlock_irq(&dev_priv->irq_lock); | |
3228 | ||
043e9bda | 3229 | intel_display_resume(dev); |
7514747d VS |
3230 | |
3231 | intel_hpd_init(dev_priv); | |
3232 | ||
3233 | drm_modeset_unlock_all(dev); | |
3234 | } | |
3235 | ||
2e2f351d | 3236 | static void |
14667a4b CW |
3237 | intel_finish_fb(struct drm_framebuffer *old_fb) |
3238 | { | |
2ff8fde1 | 3239 | struct drm_i915_gem_object *obj = intel_fb_obj(old_fb); |
2e2f351d | 3240 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
14667a4b CW |
3241 | bool was_interruptible = dev_priv->mm.interruptible; |
3242 | int ret; | |
3243 | ||
14667a4b CW |
3244 | /* Big Hammer, we also need to ensure that any pending |
3245 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
3246 | * current scanout is retired before unpinning the old | |
2e2f351d CW |
3247 | * framebuffer. Note that we rely on userspace rendering |
3248 | * into the buffer attached to the pipe they are waiting | |
3249 | * on. If not, userspace generates a GPU hang with IPEHR | |
3250 | * point to the MI_WAIT_FOR_EVENT. | |
14667a4b CW |
3251 | * |
3252 | * This should only fail upon a hung GPU, in which case we | |
3253 | * can safely continue. | |
3254 | */ | |
3255 | dev_priv->mm.interruptible = false; | |
2e2f351d | 3256 | ret = i915_gem_object_wait_rendering(obj, true); |
14667a4b CW |
3257 | dev_priv->mm.interruptible = was_interruptible; |
3258 | ||
2e2f351d | 3259 | WARN_ON(ret); |
14667a4b CW |
3260 | } |
3261 | ||
7d5e3799 CW |
3262 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
3263 | { | |
3264 | struct drm_device *dev = crtc->dev; | |
3265 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3266 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7d5e3799 CW |
3267 | bool pending; |
3268 | ||
3269 | if (i915_reset_in_progress(&dev_priv->gpu_error) || | |
3270 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
3271 | return false; | |
3272 | ||
5e2d7afc | 3273 | spin_lock_irq(&dev->event_lock); |
7d5e3799 | 3274 | pending = to_intel_crtc(crtc)->unpin_work != NULL; |
5e2d7afc | 3275 | spin_unlock_irq(&dev->event_lock); |
7d5e3799 CW |
3276 | |
3277 | return pending; | |
3278 | } | |
3279 | ||
bfd16b2a ML |
3280 | static void intel_update_pipe_config(struct intel_crtc *crtc, |
3281 | struct intel_crtc_state *old_crtc_state) | |
e30e8f75 GP |
3282 | { |
3283 | struct drm_device *dev = crtc->base.dev; | |
3284 | struct drm_i915_private *dev_priv = dev->dev_private; | |
bfd16b2a ML |
3285 | struct intel_crtc_state *pipe_config = |
3286 | to_intel_crtc_state(crtc->base.state); | |
e30e8f75 | 3287 | |
bfd16b2a ML |
3288 | /* drm_atomic_helper_update_legacy_modeset_state might not be called. */ |
3289 | crtc->base.mode = crtc->base.state->mode; | |
3290 | ||
3291 | DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n", | |
3292 | old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h, | |
3293 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
e30e8f75 | 3294 | |
44522d85 ML |
3295 | if (HAS_DDI(dev)) |
3296 | intel_set_pipe_csc(&crtc->base); | |
3297 | ||
e30e8f75 GP |
3298 | /* |
3299 | * Update pipe size and adjust fitter if needed: the reason for this is | |
3300 | * that in compute_mode_changes we check the native mode (not the pfit | |
3301 | * mode) to see if we can flip rather than do a full mode set. In the | |
3302 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
3303 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
3304 | * sized surface. | |
e30e8f75 GP |
3305 | */ |
3306 | ||
e30e8f75 | 3307 | I915_WRITE(PIPESRC(crtc->pipe), |
bfd16b2a ML |
3308 | ((pipe_config->pipe_src_w - 1) << 16) | |
3309 | (pipe_config->pipe_src_h - 1)); | |
3310 | ||
3311 | /* on skylake this is done by detaching scalers */ | |
3312 | if (INTEL_INFO(dev)->gen >= 9) { | |
3313 | skl_detach_scalers(crtc); | |
3314 | ||
3315 | if (pipe_config->pch_pfit.enabled) | |
3316 | skylake_pfit_enable(crtc); | |
3317 | } else if (HAS_PCH_SPLIT(dev)) { | |
3318 | if (pipe_config->pch_pfit.enabled) | |
3319 | ironlake_pfit_enable(crtc); | |
3320 | else if (old_crtc_state->pch_pfit.enabled) | |
3321 | ironlake_pfit_disable(crtc, true); | |
e30e8f75 | 3322 | } |
e30e8f75 GP |
3323 | } |
3324 | ||
5e84e1a4 ZW |
3325 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
3326 | { | |
3327 | struct drm_device *dev = crtc->dev; | |
3328 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3329 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3330 | int pipe = intel_crtc->pipe; | |
3331 | u32 reg, temp; | |
3332 | ||
3333 | /* enable normal train */ | |
3334 | reg = FDI_TX_CTL(pipe); | |
3335 | temp = I915_READ(reg); | |
61e499bf | 3336 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
3337 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3338 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
3339 | } else { |
3340 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3341 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 3342 | } |
5e84e1a4 ZW |
3343 | I915_WRITE(reg, temp); |
3344 | ||
3345 | reg = FDI_RX_CTL(pipe); | |
3346 | temp = I915_READ(reg); | |
3347 | if (HAS_PCH_CPT(dev)) { | |
3348 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3349 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
3350 | } else { | |
3351 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3352 | temp |= FDI_LINK_TRAIN_NONE; | |
3353 | } | |
3354 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
3355 | ||
3356 | /* wait one idle pattern time */ | |
3357 | POSTING_READ(reg); | |
3358 | udelay(1000); | |
357555c0 JB |
3359 | |
3360 | /* IVB wants error correction enabled */ | |
3361 | if (IS_IVYBRIDGE(dev)) | |
3362 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
3363 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
3364 | } |
3365 | ||
8db9d77b ZW |
3366 | /* The FDI link training functions for ILK/Ibexpeak. */ |
3367 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
3368 | { | |
3369 | struct drm_device *dev = crtc->dev; | |
3370 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3371 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3372 | int pipe = intel_crtc->pipe; | |
5eddb70b | 3373 | u32 reg, temp, tries; |
8db9d77b | 3374 | |
1c8562f6 | 3375 | /* FDI needs bits from pipe first */ |
0fc932b8 | 3376 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 3377 | |
e1a44743 AJ |
3378 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3379 | for train result */ | |
5eddb70b CW |
3380 | reg = FDI_RX_IMR(pipe); |
3381 | temp = I915_READ(reg); | |
e1a44743 AJ |
3382 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3383 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3384 | I915_WRITE(reg, temp); |
3385 | I915_READ(reg); | |
e1a44743 AJ |
3386 | udelay(150); |
3387 | ||
8db9d77b | 3388 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3389 | reg = FDI_TX_CTL(pipe); |
3390 | temp = I915_READ(reg); | |
627eb5a3 | 3391 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3392 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3393 | temp &= ~FDI_LINK_TRAIN_NONE; |
3394 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 3395 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3396 | |
5eddb70b CW |
3397 | reg = FDI_RX_CTL(pipe); |
3398 | temp = I915_READ(reg); | |
8db9d77b ZW |
3399 | temp &= ~FDI_LINK_TRAIN_NONE; |
3400 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
3401 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3402 | ||
3403 | POSTING_READ(reg); | |
8db9d77b ZW |
3404 | udelay(150); |
3405 | ||
5b2adf89 | 3406 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
3407 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
3408 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
3409 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 3410 | |
5eddb70b | 3411 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3412 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3413 | temp = I915_READ(reg); |
8db9d77b ZW |
3414 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3415 | ||
3416 | if ((temp & FDI_RX_BIT_LOCK)) { | |
3417 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 3418 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
3419 | break; |
3420 | } | |
8db9d77b | 3421 | } |
e1a44743 | 3422 | if (tries == 5) |
5eddb70b | 3423 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3424 | |
3425 | /* Train 2 */ | |
5eddb70b CW |
3426 | reg = FDI_TX_CTL(pipe); |
3427 | temp = I915_READ(reg); | |
8db9d77b ZW |
3428 | temp &= ~FDI_LINK_TRAIN_NONE; |
3429 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3430 | I915_WRITE(reg, temp); |
8db9d77b | 3431 | |
5eddb70b CW |
3432 | reg = FDI_RX_CTL(pipe); |
3433 | temp = I915_READ(reg); | |
8db9d77b ZW |
3434 | temp &= ~FDI_LINK_TRAIN_NONE; |
3435 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3436 | I915_WRITE(reg, temp); |
8db9d77b | 3437 | |
5eddb70b CW |
3438 | POSTING_READ(reg); |
3439 | udelay(150); | |
8db9d77b | 3440 | |
5eddb70b | 3441 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3442 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3443 | temp = I915_READ(reg); |
8db9d77b ZW |
3444 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3445 | ||
3446 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 3447 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
3448 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
3449 | break; | |
3450 | } | |
8db9d77b | 3451 | } |
e1a44743 | 3452 | if (tries == 5) |
5eddb70b | 3453 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3454 | |
3455 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 3456 | |
8db9d77b ZW |
3457 | } |
3458 | ||
0206e353 | 3459 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
3460 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
3461 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
3462 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
3463 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
3464 | }; | |
3465 | ||
3466 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
3467 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
3468 | { | |
3469 | struct drm_device *dev = crtc->dev; | |
3470 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3471 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3472 | int pipe = intel_crtc->pipe; | |
fa37d39e | 3473 | u32 reg, temp, i, retry; |
8db9d77b | 3474 | |
e1a44743 AJ |
3475 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3476 | for train result */ | |
5eddb70b CW |
3477 | reg = FDI_RX_IMR(pipe); |
3478 | temp = I915_READ(reg); | |
e1a44743 AJ |
3479 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3480 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3481 | I915_WRITE(reg, temp); |
3482 | ||
3483 | POSTING_READ(reg); | |
e1a44743 AJ |
3484 | udelay(150); |
3485 | ||
8db9d77b | 3486 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3487 | reg = FDI_TX_CTL(pipe); |
3488 | temp = I915_READ(reg); | |
627eb5a3 | 3489 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3490 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3491 | temp &= ~FDI_LINK_TRAIN_NONE; |
3492 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3493 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3494 | /* SNB-B */ | |
3495 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 3496 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3497 | |
d74cf324 DV |
3498 | I915_WRITE(FDI_RX_MISC(pipe), |
3499 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
3500 | ||
5eddb70b CW |
3501 | reg = FDI_RX_CTL(pipe); |
3502 | temp = I915_READ(reg); | |
8db9d77b ZW |
3503 | if (HAS_PCH_CPT(dev)) { |
3504 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3505 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3506 | } else { | |
3507 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3508 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3509 | } | |
5eddb70b CW |
3510 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3511 | ||
3512 | POSTING_READ(reg); | |
8db9d77b ZW |
3513 | udelay(150); |
3514 | ||
0206e353 | 3515 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3516 | reg = FDI_TX_CTL(pipe); |
3517 | temp = I915_READ(reg); | |
8db9d77b ZW |
3518 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3519 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3520 | I915_WRITE(reg, temp); |
3521 | ||
3522 | POSTING_READ(reg); | |
8db9d77b ZW |
3523 | udelay(500); |
3524 | ||
fa37d39e SP |
3525 | for (retry = 0; retry < 5; retry++) { |
3526 | reg = FDI_RX_IIR(pipe); | |
3527 | temp = I915_READ(reg); | |
3528 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3529 | if (temp & FDI_RX_BIT_LOCK) { | |
3530 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3531 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3532 | break; | |
3533 | } | |
3534 | udelay(50); | |
8db9d77b | 3535 | } |
fa37d39e SP |
3536 | if (retry < 5) |
3537 | break; | |
8db9d77b ZW |
3538 | } |
3539 | if (i == 4) | |
5eddb70b | 3540 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3541 | |
3542 | /* Train 2 */ | |
5eddb70b CW |
3543 | reg = FDI_TX_CTL(pipe); |
3544 | temp = I915_READ(reg); | |
8db9d77b ZW |
3545 | temp &= ~FDI_LINK_TRAIN_NONE; |
3546 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3547 | if (IS_GEN6(dev)) { | |
3548 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3549 | /* SNB-B */ | |
3550 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3551 | } | |
5eddb70b | 3552 | I915_WRITE(reg, temp); |
8db9d77b | 3553 | |
5eddb70b CW |
3554 | reg = FDI_RX_CTL(pipe); |
3555 | temp = I915_READ(reg); | |
8db9d77b ZW |
3556 | if (HAS_PCH_CPT(dev)) { |
3557 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3558 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3559 | } else { | |
3560 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3561 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3562 | } | |
5eddb70b CW |
3563 | I915_WRITE(reg, temp); |
3564 | ||
3565 | POSTING_READ(reg); | |
8db9d77b ZW |
3566 | udelay(150); |
3567 | ||
0206e353 | 3568 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3569 | reg = FDI_TX_CTL(pipe); |
3570 | temp = I915_READ(reg); | |
8db9d77b ZW |
3571 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3572 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3573 | I915_WRITE(reg, temp); |
3574 | ||
3575 | POSTING_READ(reg); | |
8db9d77b ZW |
3576 | udelay(500); |
3577 | ||
fa37d39e SP |
3578 | for (retry = 0; retry < 5; retry++) { |
3579 | reg = FDI_RX_IIR(pipe); | |
3580 | temp = I915_READ(reg); | |
3581 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3582 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3583 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3584 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3585 | break; | |
3586 | } | |
3587 | udelay(50); | |
8db9d77b | 3588 | } |
fa37d39e SP |
3589 | if (retry < 5) |
3590 | break; | |
8db9d77b ZW |
3591 | } |
3592 | if (i == 4) | |
5eddb70b | 3593 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3594 | |
3595 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3596 | } | |
3597 | ||
357555c0 JB |
3598 | /* Manual link training for Ivy Bridge A0 parts */ |
3599 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
3600 | { | |
3601 | struct drm_device *dev = crtc->dev; | |
3602 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3603 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3604 | int pipe = intel_crtc->pipe; | |
139ccd3f | 3605 | u32 reg, temp, i, j; |
357555c0 JB |
3606 | |
3607 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
3608 | for train result */ | |
3609 | reg = FDI_RX_IMR(pipe); | |
3610 | temp = I915_READ(reg); | |
3611 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
3612 | temp &= ~FDI_RX_BIT_LOCK; | |
3613 | I915_WRITE(reg, temp); | |
3614 | ||
3615 | POSTING_READ(reg); | |
3616 | udelay(150); | |
3617 | ||
01a415fd DV |
3618 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
3619 | I915_READ(FDI_RX_IIR(pipe))); | |
3620 | ||
139ccd3f JB |
3621 | /* Try each vswing and preemphasis setting twice before moving on */ |
3622 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
3623 | /* disable first in case we need to retry */ | |
3624 | reg = FDI_TX_CTL(pipe); | |
3625 | temp = I915_READ(reg); | |
3626 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
3627 | temp &= ~FDI_TX_ENABLE; | |
3628 | I915_WRITE(reg, temp); | |
357555c0 | 3629 | |
139ccd3f JB |
3630 | reg = FDI_RX_CTL(pipe); |
3631 | temp = I915_READ(reg); | |
3632 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
3633 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3634 | temp &= ~FDI_RX_ENABLE; | |
3635 | I915_WRITE(reg, temp); | |
357555c0 | 3636 | |
139ccd3f | 3637 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
3638 | reg = FDI_TX_CTL(pipe); |
3639 | temp = I915_READ(reg); | |
139ccd3f | 3640 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3641 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
139ccd3f | 3642 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
357555c0 | 3643 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
3644 | temp |= snb_b_fdi_train_param[j/2]; |
3645 | temp |= FDI_COMPOSITE_SYNC; | |
3646 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 3647 | |
139ccd3f JB |
3648 | I915_WRITE(FDI_RX_MISC(pipe), |
3649 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 3650 | |
139ccd3f | 3651 | reg = FDI_RX_CTL(pipe); |
357555c0 | 3652 | temp = I915_READ(reg); |
139ccd3f JB |
3653 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
3654 | temp |= FDI_COMPOSITE_SYNC; | |
3655 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 3656 | |
139ccd3f JB |
3657 | POSTING_READ(reg); |
3658 | udelay(1); /* should be 0.5us */ | |
357555c0 | 3659 | |
139ccd3f JB |
3660 | for (i = 0; i < 4; i++) { |
3661 | reg = FDI_RX_IIR(pipe); | |
3662 | temp = I915_READ(reg); | |
3663 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3664 | |
139ccd3f JB |
3665 | if (temp & FDI_RX_BIT_LOCK || |
3666 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
3667 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3668 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
3669 | i); | |
3670 | break; | |
3671 | } | |
3672 | udelay(1); /* should be 0.5us */ | |
3673 | } | |
3674 | if (i == 4) { | |
3675 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
3676 | continue; | |
3677 | } | |
357555c0 | 3678 | |
139ccd3f | 3679 | /* Train 2 */ |
357555c0 JB |
3680 | reg = FDI_TX_CTL(pipe); |
3681 | temp = I915_READ(reg); | |
139ccd3f JB |
3682 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3683 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
3684 | I915_WRITE(reg, temp); | |
3685 | ||
3686 | reg = FDI_RX_CTL(pipe); | |
3687 | temp = I915_READ(reg); | |
3688 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3689 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
3690 | I915_WRITE(reg, temp); |
3691 | ||
3692 | POSTING_READ(reg); | |
139ccd3f | 3693 | udelay(2); /* should be 1.5us */ |
357555c0 | 3694 | |
139ccd3f JB |
3695 | for (i = 0; i < 4; i++) { |
3696 | reg = FDI_RX_IIR(pipe); | |
3697 | temp = I915_READ(reg); | |
3698 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3699 | |
139ccd3f JB |
3700 | if (temp & FDI_RX_SYMBOL_LOCK || |
3701 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
3702 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3703 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
3704 | i); | |
3705 | goto train_done; | |
3706 | } | |
3707 | udelay(2); /* should be 1.5us */ | |
357555c0 | 3708 | } |
139ccd3f JB |
3709 | if (i == 4) |
3710 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 3711 | } |
357555c0 | 3712 | |
139ccd3f | 3713 | train_done: |
357555c0 JB |
3714 | DRM_DEBUG_KMS("FDI train done.\n"); |
3715 | } | |
3716 | ||
88cefb6c | 3717 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 3718 | { |
88cefb6c | 3719 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 3720 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 3721 | int pipe = intel_crtc->pipe; |
5eddb70b | 3722 | u32 reg, temp; |
79e53945 | 3723 | |
c64e311e | 3724 | |
c98e9dcf | 3725 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
3726 | reg = FDI_RX_CTL(pipe); |
3727 | temp = I915_READ(reg); | |
627eb5a3 | 3728 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
6e3c9717 | 3729 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
dfd07d72 | 3730 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
3731 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
3732 | ||
3733 | POSTING_READ(reg); | |
c98e9dcf JB |
3734 | udelay(200); |
3735 | ||
3736 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
3737 | temp = I915_READ(reg); |
3738 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
3739 | ||
3740 | POSTING_READ(reg); | |
c98e9dcf JB |
3741 | udelay(200); |
3742 | ||
20749730 PZ |
3743 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
3744 | reg = FDI_TX_CTL(pipe); | |
3745 | temp = I915_READ(reg); | |
3746 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
3747 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 3748 | |
20749730 PZ |
3749 | POSTING_READ(reg); |
3750 | udelay(100); | |
6be4a607 | 3751 | } |
0e23b99d JB |
3752 | } |
3753 | ||
88cefb6c DV |
3754 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
3755 | { | |
3756 | struct drm_device *dev = intel_crtc->base.dev; | |
3757 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3758 | int pipe = intel_crtc->pipe; | |
3759 | u32 reg, temp; | |
3760 | ||
3761 | /* Switch from PCDclk to Rawclk */ | |
3762 | reg = FDI_RX_CTL(pipe); | |
3763 | temp = I915_READ(reg); | |
3764 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
3765 | ||
3766 | /* Disable CPU FDI TX PLL */ | |
3767 | reg = FDI_TX_CTL(pipe); | |
3768 | temp = I915_READ(reg); | |
3769 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
3770 | ||
3771 | POSTING_READ(reg); | |
3772 | udelay(100); | |
3773 | ||
3774 | reg = FDI_RX_CTL(pipe); | |
3775 | temp = I915_READ(reg); | |
3776 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
3777 | ||
3778 | /* Wait for the clocks to turn off. */ | |
3779 | POSTING_READ(reg); | |
3780 | udelay(100); | |
3781 | } | |
3782 | ||
0fc932b8 JB |
3783 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
3784 | { | |
3785 | struct drm_device *dev = crtc->dev; | |
3786 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3787 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3788 | int pipe = intel_crtc->pipe; | |
3789 | u32 reg, temp; | |
3790 | ||
3791 | /* disable CPU FDI tx and PCH FDI rx */ | |
3792 | reg = FDI_TX_CTL(pipe); | |
3793 | temp = I915_READ(reg); | |
3794 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
3795 | POSTING_READ(reg); | |
3796 | ||
3797 | reg = FDI_RX_CTL(pipe); | |
3798 | temp = I915_READ(reg); | |
3799 | temp &= ~(0x7 << 16); | |
dfd07d72 | 3800 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3801 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
3802 | ||
3803 | POSTING_READ(reg); | |
3804 | udelay(100); | |
3805 | ||
3806 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
eba905b2 | 3807 | if (HAS_PCH_IBX(dev)) |
6f06ce18 | 3808 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
3809 | |
3810 | /* still set train pattern 1 */ | |
3811 | reg = FDI_TX_CTL(pipe); | |
3812 | temp = I915_READ(reg); | |
3813 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3814 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3815 | I915_WRITE(reg, temp); | |
3816 | ||
3817 | reg = FDI_RX_CTL(pipe); | |
3818 | temp = I915_READ(reg); | |
3819 | if (HAS_PCH_CPT(dev)) { | |
3820 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3821 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3822 | } else { | |
3823 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3824 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3825 | } | |
3826 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
3827 | temp &= ~(0x07 << 16); | |
dfd07d72 | 3828 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3829 | I915_WRITE(reg, temp); |
3830 | ||
3831 | POSTING_READ(reg); | |
3832 | udelay(100); | |
3833 | } | |
3834 | ||
5dce5b93 CW |
3835 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
3836 | { | |
3837 | struct intel_crtc *crtc; | |
3838 | ||
3839 | /* Note that we don't need to be called with mode_config.lock here | |
3840 | * as our list of CRTC objects is static for the lifetime of the | |
3841 | * device and so cannot disappear as we iterate. Similarly, we can | |
3842 | * happily treat the predicates as racy, atomic checks as userspace | |
3843 | * cannot claim and pin a new fb without at least acquring the | |
3844 | * struct_mutex and so serialising with us. | |
3845 | */ | |
d3fcc808 | 3846 | for_each_intel_crtc(dev, crtc) { |
5dce5b93 CW |
3847 | if (atomic_read(&crtc->unpin_work_count) == 0) |
3848 | continue; | |
3849 | ||
3850 | if (crtc->unpin_work) | |
3851 | intel_wait_for_vblank(dev, crtc->pipe); | |
3852 | ||
3853 | return true; | |
3854 | } | |
3855 | ||
3856 | return false; | |
3857 | } | |
3858 | ||
d6bbafa1 CW |
3859 | static void page_flip_completed(struct intel_crtc *intel_crtc) |
3860 | { | |
3861 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); | |
3862 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
3863 | ||
3864 | /* ensure that the unpin work is consistent wrt ->pending. */ | |
3865 | smp_rmb(); | |
3866 | intel_crtc->unpin_work = NULL; | |
3867 | ||
3868 | if (work->event) | |
3869 | drm_send_vblank_event(intel_crtc->base.dev, | |
3870 | intel_crtc->pipe, | |
3871 | work->event); | |
3872 | ||
3873 | drm_crtc_vblank_put(&intel_crtc->base); | |
3874 | ||
3875 | wake_up_all(&dev_priv->pending_flip_queue); | |
3876 | queue_work(dev_priv->wq, &work->work); | |
3877 | ||
3878 | trace_i915_flip_complete(intel_crtc->plane, | |
3879 | work->pending_flip_obj); | |
3880 | } | |
3881 | ||
46a55d30 | 3882 | void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
e6c3a2a6 | 3883 | { |
0f91128d | 3884 | struct drm_device *dev = crtc->dev; |
5bb61643 | 3885 | struct drm_i915_private *dev_priv = dev->dev_private; |
e6c3a2a6 | 3886 | |
2c10d571 | 3887 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
9c787942 CW |
3888 | if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue, |
3889 | !intel_crtc_has_pending_flip(crtc), | |
3890 | 60*HZ) == 0)) { | |
3891 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2c10d571 | 3892 | |
5e2d7afc | 3893 | spin_lock_irq(&dev->event_lock); |
9c787942 CW |
3894 | if (intel_crtc->unpin_work) { |
3895 | WARN_ONCE(1, "Removing stuck page flip\n"); | |
3896 | page_flip_completed(intel_crtc); | |
3897 | } | |
5e2d7afc | 3898 | spin_unlock_irq(&dev->event_lock); |
9c787942 | 3899 | } |
5bb61643 | 3900 | |
975d568a CW |
3901 | if (crtc->primary->fb) { |
3902 | mutex_lock(&dev->struct_mutex); | |
3903 | intel_finish_fb(crtc->primary->fb); | |
3904 | mutex_unlock(&dev->struct_mutex); | |
3905 | } | |
e6c3a2a6 CW |
3906 | } |
3907 | ||
e615efe4 ED |
3908 | /* Program iCLKIP clock to the desired frequency */ |
3909 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
3910 | { | |
3911 | struct drm_device *dev = crtc->dev; | |
3912 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 3913 | int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; |
e615efe4 ED |
3914 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
3915 | u32 temp; | |
3916 | ||
a580516d | 3917 | mutex_lock(&dev_priv->sb_lock); |
09153000 | 3918 | |
e615efe4 ED |
3919 | /* It is necessary to ungate the pixclk gate prior to programming |
3920 | * the divisors, and gate it back when it is done. | |
3921 | */ | |
3922 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
3923 | ||
3924 | /* Disable SSCCTL */ | |
3925 | intel_sbi_write(dev_priv, SBI_SSCCTL6, | |
988d6ee8 PZ |
3926 | intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) | |
3927 | SBI_SSCCTL_DISABLE, | |
3928 | SBI_ICLK); | |
e615efe4 ED |
3929 | |
3930 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ | |
12d7ceed | 3931 | if (clock == 20000) { |
e615efe4 ED |
3932 | auxdiv = 1; |
3933 | divsel = 0x41; | |
3934 | phaseinc = 0x20; | |
3935 | } else { | |
3936 | /* The iCLK virtual clock root frequency is in MHz, | |
241bfc38 DL |
3937 | * but the adjusted_mode->crtc_clock in in KHz. To get the |
3938 | * divisors, it is necessary to divide one by another, so we | |
e615efe4 ED |
3939 | * convert the virtual clock precision to KHz here for higher |
3940 | * precision. | |
3941 | */ | |
3942 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
3943 | u32 iclk_pi_range = 64; | |
3944 | u32 desired_divisor, msb_divisor_value, pi_value; | |
3945 | ||
12d7ceed | 3946 | desired_divisor = (iclk_virtual_root_freq / clock); |
e615efe4 ED |
3947 | msb_divisor_value = desired_divisor / iclk_pi_range; |
3948 | pi_value = desired_divisor % iclk_pi_range; | |
3949 | ||
3950 | auxdiv = 0; | |
3951 | divsel = msb_divisor_value - 2; | |
3952 | phaseinc = pi_value; | |
3953 | } | |
3954 | ||
3955 | /* This should not happen with any sane values */ | |
3956 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
3957 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
3958 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
3959 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
3960 | ||
3961 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 3962 | clock, |
e615efe4 ED |
3963 | auxdiv, |
3964 | divsel, | |
3965 | phasedir, | |
3966 | phaseinc); | |
3967 | ||
3968 | /* Program SSCDIVINTPHASE6 */ | |
988d6ee8 | 3969 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
3970 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
3971 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
3972 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
3973 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
3974 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
3975 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 3976 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
3977 | |
3978 | /* Program SSCAUXDIV */ | |
988d6ee8 | 3979 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
3980 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
3981 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 3982 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
3983 | |
3984 | /* Enable modulator and associated divider */ | |
988d6ee8 | 3985 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 3986 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 3987 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 ED |
3988 | |
3989 | /* Wait for initialization time */ | |
3990 | udelay(24); | |
3991 | ||
3992 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
09153000 | 3993 | |
a580516d | 3994 | mutex_unlock(&dev_priv->sb_lock); |
e615efe4 ED |
3995 | } |
3996 | ||
275f01b2 DV |
3997 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
3998 | enum pipe pch_transcoder) | |
3999 | { | |
4000 | struct drm_device *dev = crtc->base.dev; | |
4001 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 4002 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
275f01b2 DV |
4003 | |
4004 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
4005 | I915_READ(HTOTAL(cpu_transcoder))); | |
4006 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
4007 | I915_READ(HBLANK(cpu_transcoder))); | |
4008 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
4009 | I915_READ(HSYNC(cpu_transcoder))); | |
4010 | ||
4011 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
4012 | I915_READ(VTOTAL(cpu_transcoder))); | |
4013 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
4014 | I915_READ(VBLANK(cpu_transcoder))); | |
4015 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
4016 | I915_READ(VSYNC(cpu_transcoder))); | |
4017 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
4018 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
4019 | } | |
4020 | ||
003632d9 | 4021 | static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) |
1fbc0d78 DV |
4022 | { |
4023 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4024 | uint32_t temp; | |
4025 | ||
4026 | temp = I915_READ(SOUTH_CHICKEN1); | |
003632d9 | 4027 | if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) |
1fbc0d78 DV |
4028 | return; |
4029 | ||
4030 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
4031 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
4032 | ||
003632d9 ACO |
4033 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
4034 | if (enable) | |
4035 | temp |= FDI_BC_BIFURCATION_SELECT; | |
4036 | ||
4037 | DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis"); | |
1fbc0d78 DV |
4038 | I915_WRITE(SOUTH_CHICKEN1, temp); |
4039 | POSTING_READ(SOUTH_CHICKEN1); | |
4040 | } | |
4041 | ||
4042 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
4043 | { | |
4044 | struct drm_device *dev = intel_crtc->base.dev; | |
1fbc0d78 DV |
4045 | |
4046 | switch (intel_crtc->pipe) { | |
4047 | case PIPE_A: | |
4048 | break; | |
4049 | case PIPE_B: | |
6e3c9717 | 4050 | if (intel_crtc->config->fdi_lanes > 2) |
003632d9 | 4051 | cpt_set_fdi_bc_bifurcation(dev, false); |
1fbc0d78 | 4052 | else |
003632d9 | 4053 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4054 | |
4055 | break; | |
4056 | case PIPE_C: | |
003632d9 | 4057 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4058 | |
4059 | break; | |
4060 | default: | |
4061 | BUG(); | |
4062 | } | |
4063 | } | |
4064 | ||
f67a559d JB |
4065 | /* |
4066 | * Enable PCH resources required for PCH ports: | |
4067 | * - PCH PLLs | |
4068 | * - FDI training & RX/TX | |
4069 | * - update transcoder timings | |
4070 | * - DP transcoding bits | |
4071 | * - transcoder | |
4072 | */ | |
4073 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
4074 | { |
4075 | struct drm_device *dev = crtc->dev; | |
4076 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4077 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4078 | int pipe = intel_crtc->pipe; | |
ee7b9f93 | 4079 | u32 reg, temp; |
2c07245f | 4080 | |
ab9412ba | 4081 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 4082 | |
1fbc0d78 DV |
4083 | if (IS_IVYBRIDGE(dev)) |
4084 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
4085 | ||
cd986abb DV |
4086 | /* Write the TU size bits before fdi link training, so that error |
4087 | * detection works. */ | |
4088 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
4089 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
4090 | ||
c98e9dcf | 4091 | /* For PCH output, training FDI link */ |
674cf967 | 4092 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 4093 | |
3ad8a208 DV |
4094 | /* We need to program the right clock selection before writing the pixel |
4095 | * mutliplier into the DPLL. */ | |
303b81e0 | 4096 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 4097 | u32 sel; |
4b645f14 | 4098 | |
c98e9dcf | 4099 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
4100 | temp |= TRANS_DPLL_ENABLE(pipe); |
4101 | sel = TRANS_DPLLB_SEL(pipe); | |
6e3c9717 | 4102 | if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B) |
ee7b9f93 JB |
4103 | temp |= sel; |
4104 | else | |
4105 | temp &= ~sel; | |
c98e9dcf | 4106 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 4107 | } |
5eddb70b | 4108 | |
3ad8a208 DV |
4109 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
4110 | * transcoder, and we actually should do this to not upset any PCH | |
4111 | * transcoder that already use the clock when we share it. | |
4112 | * | |
4113 | * Note that enable_shared_dpll tries to do the right thing, but | |
4114 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
4115 | * the right LVDS enable sequence. */ | |
85b3894f | 4116 | intel_enable_shared_dpll(intel_crtc); |
3ad8a208 | 4117 | |
d9b6cb56 JB |
4118 | /* set transcoder timing, panel must allow it */ |
4119 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 4120 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 4121 | |
303b81e0 | 4122 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 4123 | |
c98e9dcf | 4124 | /* For PCH DP, enable TRANS_DP_CTL */ |
6e3c9717 | 4125 | if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) { |
dfd07d72 | 4126 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
5eddb70b CW |
4127 | reg = TRANS_DP_CTL(pipe); |
4128 | temp = I915_READ(reg); | |
4129 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
4130 | TRANS_DP_SYNC_MASK | |
4131 | TRANS_DP_BPC_MASK); | |
e3ef4479 | 4132 | temp |= TRANS_DP_OUTPUT_ENABLE; |
9325c9f0 | 4133 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf JB |
4134 | |
4135 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) | |
5eddb70b | 4136 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
c98e9dcf | 4137 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 4138 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
4139 | |
4140 | switch (intel_trans_dp_port_sel(crtc)) { | |
4141 | case PCH_DP_B: | |
5eddb70b | 4142 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf JB |
4143 | break; |
4144 | case PCH_DP_C: | |
5eddb70b | 4145 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf JB |
4146 | break; |
4147 | case PCH_DP_D: | |
5eddb70b | 4148 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
4149 | break; |
4150 | default: | |
e95d41e1 | 4151 | BUG(); |
32f9d658 | 4152 | } |
2c07245f | 4153 | |
5eddb70b | 4154 | I915_WRITE(reg, temp); |
6be4a607 | 4155 | } |
b52eb4dc | 4156 | |
b8a4f404 | 4157 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
4158 | } |
4159 | ||
1507e5bd PZ |
4160 | static void lpt_pch_enable(struct drm_crtc *crtc) |
4161 | { | |
4162 | struct drm_device *dev = crtc->dev; | |
4163 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4164 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6e3c9717 | 4165 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
1507e5bd | 4166 | |
ab9412ba | 4167 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 4168 | |
8c52b5e8 | 4169 | lpt_program_iclkip(crtc); |
1507e5bd | 4170 | |
0540e488 | 4171 | /* Set transcoder timing. */ |
275f01b2 | 4172 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 4173 | |
937bb610 | 4174 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
4175 | } |
4176 | ||
190f68c5 ACO |
4177 | struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, |
4178 | struct intel_crtc_state *crtc_state) | |
ee7b9f93 | 4179 | { |
e2b78267 | 4180 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
8bd31e67 | 4181 | struct intel_shared_dpll *pll; |
de419ab6 | 4182 | struct intel_shared_dpll_config *shared_dpll; |
e2b78267 | 4183 | enum intel_dpll_id i; |
ee7b9f93 | 4184 | |
de419ab6 ML |
4185 | shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state); |
4186 | ||
98b6bd99 DV |
4187 | if (HAS_PCH_IBX(dev_priv->dev)) { |
4188 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ | |
d94ab068 | 4189 | i = (enum intel_dpll_id) crtc->pipe; |
e72f9fbf | 4190 | pll = &dev_priv->shared_dplls[i]; |
98b6bd99 | 4191 | |
46edb027 DV |
4192 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
4193 | crtc->base.base.id, pll->name); | |
98b6bd99 | 4194 | |
de419ab6 | 4195 | WARN_ON(shared_dpll[i].crtc_mask); |
f2a69f44 | 4196 | |
98b6bd99 DV |
4197 | goto found; |
4198 | } | |
4199 | ||
bcddf610 S |
4200 | if (IS_BROXTON(dev_priv->dev)) { |
4201 | /* PLL is attached to port in bxt */ | |
4202 | struct intel_encoder *encoder; | |
4203 | struct intel_digital_port *intel_dig_port; | |
4204 | ||
4205 | encoder = intel_ddi_get_crtc_new_encoder(crtc_state); | |
4206 | if (WARN_ON(!encoder)) | |
4207 | return NULL; | |
4208 | ||
4209 | intel_dig_port = enc_to_dig_port(&encoder->base); | |
4210 | /* 1:1 mapping between ports and PLLs */ | |
4211 | i = (enum intel_dpll_id)intel_dig_port->port; | |
4212 | pll = &dev_priv->shared_dplls[i]; | |
4213 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", | |
4214 | crtc->base.base.id, pll->name); | |
de419ab6 | 4215 | WARN_ON(shared_dpll[i].crtc_mask); |
bcddf610 S |
4216 | |
4217 | goto found; | |
4218 | } | |
4219 | ||
e72f9fbf DV |
4220 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
4221 | pll = &dev_priv->shared_dplls[i]; | |
ee7b9f93 JB |
4222 | |
4223 | /* Only want to check enabled timings first */ | |
de419ab6 | 4224 | if (shared_dpll[i].crtc_mask == 0) |
ee7b9f93 JB |
4225 | continue; |
4226 | ||
190f68c5 | 4227 | if (memcmp(&crtc_state->dpll_hw_state, |
de419ab6 ML |
4228 | &shared_dpll[i].hw_state, |
4229 | sizeof(crtc_state->dpll_hw_state)) == 0) { | |
8bd31e67 | 4230 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n", |
1e6f2ddc | 4231 | crtc->base.base.id, pll->name, |
de419ab6 | 4232 | shared_dpll[i].crtc_mask, |
8bd31e67 | 4233 | pll->active); |
ee7b9f93 JB |
4234 | goto found; |
4235 | } | |
4236 | } | |
4237 | ||
4238 | /* Ok no matching timings, maybe there's a free one? */ | |
e72f9fbf DV |
4239 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
4240 | pll = &dev_priv->shared_dplls[i]; | |
de419ab6 | 4241 | if (shared_dpll[i].crtc_mask == 0) { |
46edb027 DV |
4242 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
4243 | crtc->base.base.id, pll->name); | |
ee7b9f93 JB |
4244 | goto found; |
4245 | } | |
4246 | } | |
4247 | ||
4248 | return NULL; | |
4249 | ||
4250 | found: | |
de419ab6 ML |
4251 | if (shared_dpll[i].crtc_mask == 0) |
4252 | shared_dpll[i].hw_state = | |
4253 | crtc_state->dpll_hw_state; | |
f2a69f44 | 4254 | |
190f68c5 | 4255 | crtc_state->shared_dpll = i; |
46edb027 DV |
4256 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
4257 | pipe_name(crtc->pipe)); | |
ee7b9f93 | 4258 | |
de419ab6 | 4259 | shared_dpll[i].crtc_mask |= 1 << crtc->pipe; |
e04c7350 | 4260 | |
ee7b9f93 JB |
4261 | return pll; |
4262 | } | |
4263 | ||
de419ab6 | 4264 | static void intel_shared_dpll_commit(struct drm_atomic_state *state) |
8bd31e67 | 4265 | { |
de419ab6 ML |
4266 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
4267 | struct intel_shared_dpll_config *shared_dpll; | |
8bd31e67 ACO |
4268 | struct intel_shared_dpll *pll; |
4269 | enum intel_dpll_id i; | |
4270 | ||
de419ab6 ML |
4271 | if (!to_intel_atomic_state(state)->dpll_set) |
4272 | return; | |
8bd31e67 | 4273 | |
de419ab6 | 4274 | shared_dpll = to_intel_atomic_state(state)->shared_dpll; |
8bd31e67 ACO |
4275 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
4276 | pll = &dev_priv->shared_dplls[i]; | |
de419ab6 | 4277 | pll->config = shared_dpll[i]; |
8bd31e67 ACO |
4278 | } |
4279 | } | |
4280 | ||
a1520318 | 4281 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 JB |
4282 | { |
4283 | struct drm_i915_private *dev_priv = dev->dev_private; | |
23670b32 | 4284 | int dslreg = PIPEDSL(pipe); |
d4270e57 JB |
4285 | u32 temp; |
4286 | ||
4287 | temp = I915_READ(dslreg); | |
4288 | udelay(500); | |
4289 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 4290 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 4291 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
4292 | } |
4293 | } | |
4294 | ||
86adf9d7 ML |
4295 | static int |
4296 | skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, | |
4297 | unsigned scaler_user, int *scaler_id, unsigned int rotation, | |
4298 | int src_w, int src_h, int dst_w, int dst_h) | |
a1b2278e | 4299 | { |
86adf9d7 ML |
4300 | struct intel_crtc_scaler_state *scaler_state = |
4301 | &crtc_state->scaler_state; | |
4302 | struct intel_crtc *intel_crtc = | |
4303 | to_intel_crtc(crtc_state->base.crtc); | |
a1b2278e | 4304 | int need_scaling; |
6156a456 CK |
4305 | |
4306 | need_scaling = intel_rotation_90_or_270(rotation) ? | |
4307 | (src_h != dst_w || src_w != dst_h): | |
4308 | (src_w != dst_w || src_h != dst_h); | |
a1b2278e CK |
4309 | |
4310 | /* | |
4311 | * if plane is being disabled or scaler is no more required or force detach | |
4312 | * - free scaler binded to this plane/crtc | |
4313 | * - in order to do this, update crtc->scaler_usage | |
4314 | * | |
4315 | * Here scaler state in crtc_state is set free so that | |
4316 | * scaler can be assigned to other user. Actual register | |
4317 | * update to free the scaler is done in plane/panel-fit programming. | |
4318 | * For this purpose crtc/plane_state->scaler_id isn't reset here. | |
4319 | */ | |
86adf9d7 | 4320 | if (force_detach || !need_scaling) { |
a1b2278e | 4321 | if (*scaler_id >= 0) { |
86adf9d7 | 4322 | scaler_state->scaler_users &= ~(1 << scaler_user); |
a1b2278e CK |
4323 | scaler_state->scalers[*scaler_id].in_use = 0; |
4324 | ||
86adf9d7 ML |
4325 | DRM_DEBUG_KMS("scaler_user index %u.%u: " |
4326 | "Staged freeing scaler id %d scaler_users = 0x%x\n", | |
4327 | intel_crtc->pipe, scaler_user, *scaler_id, | |
a1b2278e CK |
4328 | scaler_state->scaler_users); |
4329 | *scaler_id = -1; | |
4330 | } | |
4331 | return 0; | |
4332 | } | |
4333 | ||
4334 | /* range checks */ | |
4335 | if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || | |
4336 | dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || | |
4337 | ||
4338 | src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || | |
4339 | dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) { | |
86adf9d7 | 4340 | DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u " |
a1b2278e | 4341 | "size is out of scaler range\n", |
86adf9d7 | 4342 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h); |
a1b2278e CK |
4343 | return -EINVAL; |
4344 | } | |
4345 | ||
86adf9d7 ML |
4346 | /* mark this plane as a scaler user in crtc_state */ |
4347 | scaler_state->scaler_users |= (1 << scaler_user); | |
4348 | DRM_DEBUG_KMS("scaler_user index %u.%u: " | |
4349 | "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n", | |
4350 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, | |
4351 | scaler_state->scaler_users); | |
4352 | ||
4353 | return 0; | |
4354 | } | |
4355 | ||
4356 | /** | |
4357 | * skl_update_scaler_crtc - Stages update to scaler state for a given crtc. | |
4358 | * | |
4359 | * @state: crtc's scaler state | |
86adf9d7 ML |
4360 | * |
4361 | * Return | |
4362 | * 0 - scaler_usage updated successfully | |
4363 | * error - requested scaling cannot be supported or other error condition | |
4364 | */ | |
e435d6e5 | 4365 | int skl_update_scaler_crtc(struct intel_crtc_state *state) |
86adf9d7 ML |
4366 | { |
4367 | struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc); | |
4368 | struct drm_display_mode *adjusted_mode = | |
4369 | &state->base.adjusted_mode; | |
4370 | ||
4371 | DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n", | |
4372 | intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX); | |
4373 | ||
e435d6e5 | 4374 | return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX, |
86adf9d7 ML |
4375 | &state->scaler_state.scaler_id, DRM_ROTATE_0, |
4376 | state->pipe_src_w, state->pipe_src_h, | |
8c6cda29 | 4377 | adjusted_mode->hdisplay, adjusted_mode->vdisplay); |
86adf9d7 ML |
4378 | } |
4379 | ||
4380 | /** | |
4381 | * skl_update_scaler_plane - Stages update to scaler state for a given plane. | |
4382 | * | |
4383 | * @state: crtc's scaler state | |
86adf9d7 ML |
4384 | * @plane_state: atomic plane state to update |
4385 | * | |
4386 | * Return | |
4387 | * 0 - scaler_usage updated successfully | |
4388 | * error - requested scaling cannot be supported or other error condition | |
4389 | */ | |
da20eabd ML |
4390 | static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, |
4391 | struct intel_plane_state *plane_state) | |
86adf9d7 ML |
4392 | { |
4393 | ||
4394 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); | |
da20eabd ML |
4395 | struct intel_plane *intel_plane = |
4396 | to_intel_plane(plane_state->base.plane); | |
86adf9d7 ML |
4397 | struct drm_framebuffer *fb = plane_state->base.fb; |
4398 | int ret; | |
4399 | ||
4400 | bool force_detach = !fb || !plane_state->visible; | |
4401 | ||
4402 | DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n", | |
4403 | intel_plane->base.base.id, intel_crtc->pipe, | |
4404 | drm_plane_index(&intel_plane->base)); | |
4405 | ||
4406 | ret = skl_update_scaler(crtc_state, force_detach, | |
4407 | drm_plane_index(&intel_plane->base), | |
4408 | &plane_state->scaler_id, | |
4409 | plane_state->base.rotation, | |
4410 | drm_rect_width(&plane_state->src) >> 16, | |
4411 | drm_rect_height(&plane_state->src) >> 16, | |
4412 | drm_rect_width(&plane_state->dst), | |
4413 | drm_rect_height(&plane_state->dst)); | |
4414 | ||
4415 | if (ret || plane_state->scaler_id < 0) | |
4416 | return ret; | |
4417 | ||
a1b2278e | 4418 | /* check colorkey */ |
818ed961 | 4419 | if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) { |
86adf9d7 | 4420 | DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed", |
818ed961 | 4421 | intel_plane->base.base.id); |
a1b2278e CK |
4422 | return -EINVAL; |
4423 | } | |
4424 | ||
4425 | /* Check src format */ | |
86adf9d7 ML |
4426 | switch (fb->pixel_format) { |
4427 | case DRM_FORMAT_RGB565: | |
4428 | case DRM_FORMAT_XBGR8888: | |
4429 | case DRM_FORMAT_XRGB8888: | |
4430 | case DRM_FORMAT_ABGR8888: | |
4431 | case DRM_FORMAT_ARGB8888: | |
4432 | case DRM_FORMAT_XRGB2101010: | |
4433 | case DRM_FORMAT_XBGR2101010: | |
4434 | case DRM_FORMAT_YUYV: | |
4435 | case DRM_FORMAT_YVYU: | |
4436 | case DRM_FORMAT_UYVY: | |
4437 | case DRM_FORMAT_VYUY: | |
4438 | break; | |
4439 | default: | |
4440 | DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n", | |
4441 | intel_plane->base.base.id, fb->base.id, fb->pixel_format); | |
4442 | return -EINVAL; | |
a1b2278e CK |
4443 | } |
4444 | ||
a1b2278e CK |
4445 | return 0; |
4446 | } | |
4447 | ||
e435d6e5 ML |
4448 | static void skylake_scaler_disable(struct intel_crtc *crtc) |
4449 | { | |
4450 | int i; | |
4451 | ||
4452 | for (i = 0; i < crtc->num_scalers; i++) | |
4453 | skl_detach_scaler(crtc, i); | |
4454 | } | |
4455 | ||
4456 | static void skylake_pfit_enable(struct intel_crtc *crtc) | |
bd2e244f JB |
4457 | { |
4458 | struct drm_device *dev = crtc->base.dev; | |
4459 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4460 | int pipe = crtc->pipe; | |
a1b2278e CK |
4461 | struct intel_crtc_scaler_state *scaler_state = |
4462 | &crtc->config->scaler_state; | |
4463 | ||
4464 | DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config); | |
4465 | ||
6e3c9717 | 4466 | if (crtc->config->pch_pfit.enabled) { |
a1b2278e CK |
4467 | int id; |
4468 | ||
4469 | if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) { | |
4470 | DRM_ERROR("Requesting pfit without getting a scaler first\n"); | |
4471 | return; | |
4472 | } | |
4473 | ||
4474 | id = scaler_state->scaler_id; | |
4475 | I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | | |
4476 | PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); | |
4477 | I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos); | |
4478 | I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size); | |
4479 | ||
4480 | DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id); | |
bd2e244f JB |
4481 | } |
4482 | } | |
4483 | ||
b074cec8 JB |
4484 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
4485 | { | |
4486 | struct drm_device *dev = crtc->base.dev; | |
4487 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4488 | int pipe = crtc->pipe; | |
4489 | ||
6e3c9717 | 4490 | if (crtc->config->pch_pfit.enabled) { |
b074cec8 JB |
4491 | /* Force use of hard-coded filter coefficients |
4492 | * as some pre-programmed values are broken, | |
4493 | * e.g. x201. | |
4494 | */ | |
4495 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
4496 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
4497 | PF_PIPE_SEL_IVB(pipe)); | |
4498 | else | |
4499 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
6e3c9717 ACO |
4500 | I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
4501 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); | |
d4270e57 JB |
4502 | } |
4503 | } | |
4504 | ||
20bc8673 | 4505 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 4506 | { |
cea165c3 VS |
4507 | struct drm_device *dev = crtc->base.dev; |
4508 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d77e4531 | 4509 | |
6e3c9717 | 4510 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4511 | return; |
4512 | ||
cea165c3 VS |
4513 | /* We can only enable IPS after we enable a plane and wait for a vblank */ |
4514 | intel_wait_for_vblank(dev, crtc->pipe); | |
4515 | ||
d77e4531 | 4516 | assert_plane_enabled(dev_priv, crtc->plane); |
cea165c3 | 4517 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4518 | mutex_lock(&dev_priv->rps.hw_lock); |
4519 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
4520 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4521 | /* Quoting Art Runyan: "its not safe to expect any particular | |
4522 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
4523 | * mailbox." Moreover, the mailbox may return a bogus state, |
4524 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
4525 | */ |
4526 | } else { | |
4527 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
4528 | /* The bit only becomes 1 in the next vblank, so this wait here | |
4529 | * is essentially intel_wait_for_vblank. If we don't have this | |
4530 | * and don't wait for vblanks until the end of crtc_enable, then | |
4531 | * the HW state readout code will complain that the expected | |
4532 | * IPS_CTL value is not the one we read. */ | |
4533 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) | |
4534 | DRM_ERROR("Timed out waiting for IPS enable\n"); | |
4535 | } | |
d77e4531 PZ |
4536 | } |
4537 | ||
20bc8673 | 4538 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
4539 | { |
4540 | struct drm_device *dev = crtc->base.dev; | |
4541 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4542 | ||
6e3c9717 | 4543 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4544 | return; |
4545 | ||
4546 | assert_plane_enabled(dev_priv, crtc->plane); | |
23d0b130 | 4547 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4548 | mutex_lock(&dev_priv->rps.hw_lock); |
4549 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
4550 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 BW |
4551 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
4552 | if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42)) | |
4553 | DRM_ERROR("Timed out waiting for IPS disable\n"); | |
e59150dc | 4554 | } else { |
2a114cc1 | 4555 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
4556 | POSTING_READ(IPS_CTL); |
4557 | } | |
d77e4531 PZ |
4558 | |
4559 | /* We need to wait for a vblank before we can disable the plane. */ | |
4560 | intel_wait_for_vblank(dev, crtc->pipe); | |
4561 | } | |
4562 | ||
4563 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ | |
4564 | static void intel_crtc_load_lut(struct drm_crtc *crtc) | |
4565 | { | |
4566 | struct drm_device *dev = crtc->dev; | |
4567 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4568 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4569 | enum pipe pipe = intel_crtc->pipe; | |
4570 | int palreg = PALETTE(pipe); | |
4571 | int i; | |
4572 | bool reenable_ips = false; | |
4573 | ||
4574 | /* The clocks have to be on to load the palette. */ | |
53d9f4e9 | 4575 | if (!crtc->state->active) |
d77e4531 PZ |
4576 | return; |
4577 | ||
50360403 | 4578 | if (HAS_GMCH_DISPLAY(dev_priv->dev)) { |
409ee761 | 4579 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) |
d77e4531 PZ |
4580 | assert_dsi_pll_enabled(dev_priv); |
4581 | else | |
4582 | assert_pll_enabled(dev_priv, pipe); | |
4583 | } | |
4584 | ||
4585 | /* use legacy palette for Ironlake */ | |
7a1db49a | 4586 | if (!HAS_GMCH_DISPLAY(dev)) |
d77e4531 PZ |
4587 | palreg = LGC_PALETTE(pipe); |
4588 | ||
4589 | /* Workaround : Do not read or write the pipe palette/gamma data while | |
4590 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. | |
4591 | */ | |
6e3c9717 | 4592 | if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled && |
d77e4531 PZ |
4593 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == |
4594 | GAMMA_MODE_MODE_SPLIT)) { | |
4595 | hsw_disable_ips(intel_crtc); | |
4596 | reenable_ips = true; | |
4597 | } | |
4598 | ||
4599 | for (i = 0; i < 256; i++) { | |
4600 | I915_WRITE(palreg + 4 * i, | |
4601 | (intel_crtc->lut_r[i] << 16) | | |
4602 | (intel_crtc->lut_g[i] << 8) | | |
4603 | intel_crtc->lut_b[i]); | |
4604 | } | |
4605 | ||
4606 | if (reenable_ips) | |
4607 | hsw_enable_ips(intel_crtc); | |
4608 | } | |
4609 | ||
7cac945f | 4610 | static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc) |
d3eedb1a | 4611 | { |
7cac945f | 4612 | if (intel_crtc->overlay) { |
d3eedb1a VS |
4613 | struct drm_device *dev = intel_crtc->base.dev; |
4614 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4615 | ||
4616 | mutex_lock(&dev->struct_mutex); | |
4617 | dev_priv->mm.interruptible = false; | |
4618 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
4619 | dev_priv->mm.interruptible = true; | |
4620 | mutex_unlock(&dev->struct_mutex); | |
4621 | } | |
4622 | ||
4623 | /* Let userspace switch the overlay on again. In most cases userspace | |
4624 | * has to recompute where to put it anyway. | |
4625 | */ | |
4626 | } | |
4627 | ||
87d4300a ML |
4628 | /** |
4629 | * intel_post_enable_primary - Perform operations after enabling primary plane | |
4630 | * @crtc: the CRTC whose primary plane was just enabled | |
4631 | * | |
4632 | * Performs potentially sleeping operations that must be done after the primary | |
4633 | * plane is enabled, such as updating FBC and IPS. Note that this may be | |
4634 | * called due to an explicit primary plane update, or due to an implicit | |
4635 | * re-enable that is caused when a sprite plane is updated to no longer | |
4636 | * completely hide the primary plane. | |
4637 | */ | |
4638 | static void | |
4639 | intel_post_enable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4640 | { |
4641 | struct drm_device *dev = crtc->dev; | |
87d4300a | 4642 | struct drm_i915_private *dev_priv = dev->dev_private; |
a5c4d7bc VS |
4643 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4644 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4645 | |
87d4300a ML |
4646 | /* |
4647 | * BDW signals flip done immediately if the plane | |
4648 | * is disabled, even if the plane enable is already | |
4649 | * armed to occur at the next vblank :( | |
4650 | */ | |
4651 | if (IS_BROADWELL(dev)) | |
4652 | intel_wait_for_vblank(dev, pipe); | |
a5c4d7bc | 4653 | |
87d4300a ML |
4654 | /* |
4655 | * FIXME IPS should be fine as long as one plane is | |
4656 | * enabled, but in practice it seems to have problems | |
4657 | * when going from primary only to sprite only and vice | |
4658 | * versa. | |
4659 | */ | |
a5c4d7bc VS |
4660 | hsw_enable_ips(intel_crtc); |
4661 | ||
f99d7069 | 4662 | /* |
87d4300a ML |
4663 | * Gen2 reports pipe underruns whenever all planes are disabled. |
4664 | * So don't enable underrun reporting before at least some planes | |
4665 | * are enabled. | |
4666 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4667 | * but leave the pipe running. | |
f99d7069 | 4668 | */ |
87d4300a ML |
4669 | if (IS_GEN2(dev)) |
4670 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
4671 | ||
4672 | /* Underruns don't raise interrupts, so check manually. */ | |
4673 | if (HAS_GMCH_DISPLAY(dev)) | |
4674 | i9xx_check_fifo_underruns(dev_priv); | |
a5c4d7bc VS |
4675 | } |
4676 | ||
87d4300a ML |
4677 | /** |
4678 | * intel_pre_disable_primary - Perform operations before disabling primary plane | |
4679 | * @crtc: the CRTC whose primary plane is to be disabled | |
4680 | * | |
4681 | * Performs potentially sleeping operations that must be done before the | |
4682 | * primary plane is disabled, such as updating FBC and IPS. Note that this may | |
4683 | * be called due to an explicit primary plane update, or due to an implicit | |
4684 | * disable that is caused when a sprite plane completely hides the primary | |
4685 | * plane. | |
4686 | */ | |
4687 | static void | |
4688 | intel_pre_disable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4689 | { |
4690 | struct drm_device *dev = crtc->dev; | |
4691 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4692 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4693 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4694 | |
87d4300a ML |
4695 | /* |
4696 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
4697 | * So diasble underrun reporting before all the planes get disabled. | |
4698 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4699 | * but leave the pipe running. | |
4700 | */ | |
4701 | if (IS_GEN2(dev)) | |
4702 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
a5c4d7bc | 4703 | |
87d4300a ML |
4704 | /* |
4705 | * Vblank time updates from the shadow to live plane control register | |
4706 | * are blocked if the memory self-refresh mode is active at that | |
4707 | * moment. So to make sure the plane gets truly disabled, disable | |
4708 | * first the self-refresh mode. The self-refresh enable bit in turn | |
4709 | * will be checked/applied by the HW only at the next frame start | |
4710 | * event which is after the vblank start event, so we need to have a | |
4711 | * wait-for-vblank between disabling the plane and the pipe. | |
4712 | */ | |
262cd2e1 | 4713 | if (HAS_GMCH_DISPLAY(dev)) { |
87d4300a | 4714 | intel_set_memory_cxsr(dev_priv, false); |
262cd2e1 VS |
4715 | dev_priv->wm.vlv.cxsr = false; |
4716 | intel_wait_for_vblank(dev, pipe); | |
4717 | } | |
87d4300a | 4718 | |
87d4300a ML |
4719 | /* |
4720 | * FIXME IPS should be fine as long as one plane is | |
4721 | * enabled, but in practice it seems to have problems | |
4722 | * when going from primary only to sprite only and vice | |
4723 | * versa. | |
4724 | */ | |
a5c4d7bc | 4725 | hsw_disable_ips(intel_crtc); |
87d4300a ML |
4726 | } |
4727 | ||
ac21b225 ML |
4728 | static void intel_post_plane_update(struct intel_crtc *crtc) |
4729 | { | |
4730 | struct intel_crtc_atomic_commit *atomic = &crtc->atomic; | |
4731 | struct drm_device *dev = crtc->base.dev; | |
7733b49b | 4732 | struct drm_i915_private *dev_priv = dev->dev_private; |
ac21b225 ML |
4733 | struct drm_plane *plane; |
4734 | ||
4735 | if (atomic->wait_vblank) | |
4736 | intel_wait_for_vblank(dev, crtc->pipe); | |
4737 | ||
4738 | intel_frontbuffer_flip(dev, atomic->fb_bits); | |
4739 | ||
852eb00d VS |
4740 | if (atomic->disable_cxsr) |
4741 | crtc->wm.cxsr_allowed = true; | |
4742 | ||
f015c551 VS |
4743 | if (crtc->atomic.update_wm_post) |
4744 | intel_update_watermarks(&crtc->base); | |
4745 | ||
c80ac854 | 4746 | if (atomic->update_fbc) |
7733b49b | 4747 | intel_fbc_update(dev_priv); |
ac21b225 ML |
4748 | |
4749 | if (atomic->post_enable_primary) | |
4750 | intel_post_enable_primary(&crtc->base); | |
4751 | ||
4752 | drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks) | |
4753 | intel_update_sprite_watermarks(plane, &crtc->base, | |
4754 | 0, 0, 0, false, false); | |
4755 | ||
4756 | memset(atomic, 0, sizeof(*atomic)); | |
4757 | } | |
4758 | ||
4759 | static void intel_pre_plane_update(struct intel_crtc *crtc) | |
4760 | { | |
4761 | struct drm_device *dev = crtc->base.dev; | |
eddfcbcd | 4762 | struct drm_i915_private *dev_priv = dev->dev_private; |
ac21b225 ML |
4763 | struct intel_crtc_atomic_commit *atomic = &crtc->atomic; |
4764 | struct drm_plane *p; | |
4765 | ||
4766 | /* Track fb's for any planes being disabled */ | |
ac21b225 ML |
4767 | drm_for_each_plane_mask(p, dev, atomic->disabled_planes) { |
4768 | struct intel_plane *plane = to_intel_plane(p); | |
ac21b225 ML |
4769 | |
4770 | mutex_lock(&dev->struct_mutex); | |
a9ff8714 VS |
4771 | i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL, |
4772 | plane->frontbuffer_bit); | |
ac21b225 ML |
4773 | mutex_unlock(&dev->struct_mutex); |
4774 | } | |
4775 | ||
4776 | if (atomic->wait_for_flips) | |
4777 | intel_crtc_wait_for_pending_flips(&crtc->base); | |
4778 | ||
c80ac854 | 4779 | if (atomic->disable_fbc) |
25ad93fd | 4780 | intel_fbc_disable_crtc(crtc); |
ac21b225 | 4781 | |
066cf55b RV |
4782 | if (crtc->atomic.disable_ips) |
4783 | hsw_disable_ips(crtc); | |
4784 | ||
ac21b225 ML |
4785 | if (atomic->pre_disable_primary) |
4786 | intel_pre_disable_primary(&crtc->base); | |
852eb00d VS |
4787 | |
4788 | if (atomic->disable_cxsr) { | |
4789 | crtc->wm.cxsr_allowed = false; | |
4790 | intel_set_memory_cxsr(dev_priv, false); | |
4791 | } | |
ac21b225 ML |
4792 | } |
4793 | ||
d032ffa0 | 4794 | static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask) |
87d4300a ML |
4795 | { |
4796 | struct drm_device *dev = crtc->dev; | |
4797 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
d032ffa0 | 4798 | struct drm_plane *p; |
87d4300a ML |
4799 | int pipe = intel_crtc->pipe; |
4800 | ||
7cac945f | 4801 | intel_crtc_dpms_overlay_disable(intel_crtc); |
27321ae8 | 4802 | |
d032ffa0 ML |
4803 | drm_for_each_plane_mask(p, dev, plane_mask) |
4804 | to_intel_plane(p)->disable_plane(p, crtc); | |
f98551ae | 4805 | |
f99d7069 DV |
4806 | /* |
4807 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
4808 | * to compute the mask of flip planes precisely. For the time being | |
4809 | * consider this a flip to a NULL plane. | |
4810 | */ | |
4811 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
a5c4d7bc VS |
4812 | } |
4813 | ||
f67a559d JB |
4814 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
4815 | { | |
4816 | struct drm_device *dev = crtc->dev; | |
4817 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4818 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4819 | struct intel_encoder *encoder; |
f67a559d | 4820 | int pipe = intel_crtc->pipe; |
f67a559d | 4821 | |
53d9f4e9 | 4822 | if (WARN_ON(intel_crtc->active)) |
f67a559d JB |
4823 | return; |
4824 | ||
6e3c9717 | 4825 | if (intel_crtc->config->has_pch_encoder) |
b14b1055 DV |
4826 | intel_prepare_shared_dpll(intel_crtc); |
4827 | ||
6e3c9717 | 4828 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4829 | intel_dp_set_m_n(intel_crtc, M1_N1); |
29407aab DV |
4830 | |
4831 | intel_set_pipe_timings(intel_crtc); | |
4832 | ||
6e3c9717 | 4833 | if (intel_crtc->config->has_pch_encoder) { |
29407aab | 4834 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4835 | &intel_crtc->config->fdi_m_n, NULL); |
29407aab DV |
4836 | } |
4837 | ||
4838 | ironlake_set_pipeconf(crtc); | |
4839 | ||
f67a559d | 4840 | intel_crtc->active = true; |
8664281b | 4841 | |
a72e4c9f DV |
4842 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4843 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); | |
8664281b | 4844 | |
f6736a1a | 4845 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
4846 | if (encoder->pre_enable) |
4847 | encoder->pre_enable(encoder); | |
f67a559d | 4848 | |
6e3c9717 | 4849 | if (intel_crtc->config->has_pch_encoder) { |
fff367c7 DV |
4850 | /* Note: FDI PLL enabling _must_ be done before we enable the |
4851 | * cpu pipes, hence this is separate from all the other fdi/pch | |
4852 | * enabling. */ | |
88cefb6c | 4853 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
4854 | } else { |
4855 | assert_fdi_tx_disabled(dev_priv, pipe); | |
4856 | assert_fdi_rx_disabled(dev_priv, pipe); | |
4857 | } | |
f67a559d | 4858 | |
b074cec8 | 4859 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 4860 | |
9c54c0dd JB |
4861 | /* |
4862 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4863 | * clocks enabled | |
4864 | */ | |
4865 | intel_crtc_load_lut(crtc); | |
4866 | ||
f37fcc2a | 4867 | intel_update_watermarks(crtc); |
e1fdc473 | 4868 | intel_enable_pipe(intel_crtc); |
f67a559d | 4869 | |
6e3c9717 | 4870 | if (intel_crtc->config->has_pch_encoder) |
f67a559d | 4871 | ironlake_pch_enable(crtc); |
c98e9dcf | 4872 | |
f9b61ff6 DV |
4873 | assert_vblank_disabled(crtc); |
4874 | drm_crtc_vblank_on(crtc); | |
4875 | ||
fa5c73b1 DV |
4876 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4877 | encoder->enable(encoder); | |
61b77ddd DV |
4878 | |
4879 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 4880 | cpt_verify_modeset(dev, intel_crtc->pipe); |
6be4a607 JB |
4881 | } |
4882 | ||
42db64ef PZ |
4883 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
4884 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
4885 | { | |
f5adf94e | 4886 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
4887 | } |
4888 | ||
4f771f10 PZ |
4889 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
4890 | { | |
4891 | struct drm_device *dev = crtc->dev; | |
4892 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4893 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4894 | struct intel_encoder *encoder; | |
99d736a2 ML |
4895 | int pipe = intel_crtc->pipe, hsw_workaround_pipe; |
4896 | struct intel_crtc_state *pipe_config = | |
4897 | to_intel_crtc_state(crtc->state); | |
4f771f10 | 4898 | |
53d9f4e9 | 4899 | if (WARN_ON(intel_crtc->active)) |
4f771f10 PZ |
4900 | return; |
4901 | ||
df8ad70c DV |
4902 | if (intel_crtc_to_shared_dpll(intel_crtc)) |
4903 | intel_enable_shared_dpll(intel_crtc); | |
4904 | ||
6e3c9717 | 4905 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4906 | intel_dp_set_m_n(intel_crtc, M1_N1); |
229fca97 DV |
4907 | |
4908 | intel_set_pipe_timings(intel_crtc); | |
4909 | ||
6e3c9717 ACO |
4910 | if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) { |
4911 | I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder), | |
4912 | intel_crtc->config->pixel_multiplier - 1); | |
ebb69c95 CT |
4913 | } |
4914 | ||
6e3c9717 | 4915 | if (intel_crtc->config->has_pch_encoder) { |
229fca97 | 4916 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4917 | &intel_crtc->config->fdi_m_n, NULL); |
229fca97 DV |
4918 | } |
4919 | ||
4920 | haswell_set_pipeconf(crtc); | |
4921 | ||
4922 | intel_set_pipe_csc(crtc); | |
4923 | ||
4f771f10 | 4924 | intel_crtc->active = true; |
8664281b | 4925 | |
a72e4c9f | 4926 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4f771f10 PZ |
4927 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4928 | if (encoder->pre_enable) | |
4929 | encoder->pre_enable(encoder); | |
4930 | ||
6e3c9717 | 4931 | if (intel_crtc->config->has_pch_encoder) { |
a72e4c9f DV |
4932 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
4933 | true); | |
4fe9467d ID |
4934 | dev_priv->display.fdi_link_train(crtc); |
4935 | } | |
4936 | ||
1f544388 | 4937 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 4938 | |
1c132b44 | 4939 | if (INTEL_INFO(dev)->gen >= 9) |
e435d6e5 | 4940 | skylake_pfit_enable(intel_crtc); |
ff6d9f55 | 4941 | else |
1c132b44 | 4942 | ironlake_pfit_enable(intel_crtc); |
4f771f10 PZ |
4943 | |
4944 | /* | |
4945 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4946 | * clocks enabled | |
4947 | */ | |
4948 | intel_crtc_load_lut(crtc); | |
4949 | ||
1f544388 | 4950 | intel_ddi_set_pipe_settings(crtc); |
8228c251 | 4951 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 4952 | |
f37fcc2a | 4953 | intel_update_watermarks(crtc); |
e1fdc473 | 4954 | intel_enable_pipe(intel_crtc); |
42db64ef | 4955 | |
6e3c9717 | 4956 | if (intel_crtc->config->has_pch_encoder) |
1507e5bd | 4957 | lpt_pch_enable(crtc); |
4f771f10 | 4958 | |
6e3c9717 | 4959 | if (intel_crtc->config->dp_encoder_is_mst) |
0e32b39c DA |
4960 | intel_ddi_set_vc_payload_alloc(crtc, true); |
4961 | ||
f9b61ff6 DV |
4962 | assert_vblank_disabled(crtc); |
4963 | drm_crtc_vblank_on(crtc); | |
4964 | ||
8807e55b | 4965 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 4966 | encoder->enable(encoder); |
8807e55b JN |
4967 | intel_opregion_notify_encoder(encoder, true); |
4968 | } | |
4f771f10 | 4969 | |
e4916946 PZ |
4970 | /* If we change the relative order between pipe/planes enabling, we need |
4971 | * to change the workaround. */ | |
99d736a2 ML |
4972 | hsw_workaround_pipe = pipe_config->hsw_workaround_pipe; |
4973 | if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) { | |
4974 | intel_wait_for_vblank(dev, hsw_workaround_pipe); | |
4975 | intel_wait_for_vblank(dev, hsw_workaround_pipe); | |
4976 | } | |
4f771f10 PZ |
4977 | } |
4978 | ||
bfd16b2a | 4979 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force) |
3f8dce3a DV |
4980 | { |
4981 | struct drm_device *dev = crtc->base.dev; | |
4982 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4983 | int pipe = crtc->pipe; | |
4984 | ||
4985 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
4986 | * it's in use. The hw state code will make sure we get this right. */ | |
bfd16b2a | 4987 | if (force || crtc->config->pch_pfit.enabled) { |
3f8dce3a DV |
4988 | I915_WRITE(PF_CTL(pipe), 0); |
4989 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
4990 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
4991 | } | |
4992 | } | |
4993 | ||
6be4a607 JB |
4994 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
4995 | { | |
4996 | struct drm_device *dev = crtc->dev; | |
4997 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4998 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4999 | struct intel_encoder *encoder; |
6be4a607 | 5000 | int pipe = intel_crtc->pipe; |
5eddb70b | 5001 | u32 reg, temp; |
b52eb4dc | 5002 | |
ea9d758d DV |
5003 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5004 | encoder->disable(encoder); | |
5005 | ||
f9b61ff6 DV |
5006 | drm_crtc_vblank_off(crtc); |
5007 | assert_vblank_disabled(crtc); | |
5008 | ||
6e3c9717 | 5009 | if (intel_crtc->config->has_pch_encoder) |
a72e4c9f | 5010 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); |
d925c59a | 5011 | |
575f7ab7 | 5012 | intel_disable_pipe(intel_crtc); |
32f9d658 | 5013 | |
bfd16b2a | 5014 | ironlake_pfit_disable(intel_crtc, false); |
2c07245f | 5015 | |
5a74f70a VS |
5016 | if (intel_crtc->config->has_pch_encoder) |
5017 | ironlake_fdi_disable(crtc); | |
5018 | ||
bf49ec8c DV |
5019 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5020 | if (encoder->post_disable) | |
5021 | encoder->post_disable(encoder); | |
2c07245f | 5022 | |
6e3c9717 | 5023 | if (intel_crtc->config->has_pch_encoder) { |
d925c59a | 5024 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
6be4a607 | 5025 | |
d925c59a DV |
5026 | if (HAS_PCH_CPT(dev)) { |
5027 | /* disable TRANS_DP_CTL */ | |
5028 | reg = TRANS_DP_CTL(pipe); | |
5029 | temp = I915_READ(reg); | |
5030 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
5031 | TRANS_DP_PORT_SEL_MASK); | |
5032 | temp |= TRANS_DP_PORT_SEL_NONE; | |
5033 | I915_WRITE(reg, temp); | |
5034 | ||
5035 | /* disable DPLL_SEL */ | |
5036 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 5037 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 5038 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 5039 | } |
e3421a18 | 5040 | |
d925c59a DV |
5041 | ironlake_fdi_pll_disable(intel_crtc); |
5042 | } | |
e4ca0612 PJ |
5043 | |
5044 | intel_crtc->active = false; | |
5045 | intel_update_watermarks(crtc); | |
6be4a607 | 5046 | } |
1b3c7a47 | 5047 | |
4f771f10 | 5048 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 5049 | { |
4f771f10 PZ |
5050 | struct drm_device *dev = crtc->dev; |
5051 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 5052 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 | 5053 | struct intel_encoder *encoder; |
6e3c9717 | 5054 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee7b9f93 | 5055 | |
8807e55b JN |
5056 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5057 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 5058 | encoder->disable(encoder); |
8807e55b | 5059 | } |
4f771f10 | 5060 | |
f9b61ff6 DV |
5061 | drm_crtc_vblank_off(crtc); |
5062 | assert_vblank_disabled(crtc); | |
5063 | ||
6e3c9717 | 5064 | if (intel_crtc->config->has_pch_encoder) |
a72e4c9f DV |
5065 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5066 | false); | |
575f7ab7 | 5067 | intel_disable_pipe(intel_crtc); |
4f771f10 | 5068 | |
6e3c9717 | 5069 | if (intel_crtc->config->dp_encoder_is_mst) |
a4bf214f VS |
5070 | intel_ddi_set_vc_payload_alloc(crtc, false); |
5071 | ||
ad80a810 | 5072 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 5073 | |
1c132b44 | 5074 | if (INTEL_INFO(dev)->gen >= 9) |
e435d6e5 | 5075 | skylake_scaler_disable(intel_crtc); |
ff6d9f55 | 5076 | else |
bfd16b2a | 5077 | ironlake_pfit_disable(intel_crtc, false); |
4f771f10 | 5078 | |
1f544388 | 5079 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 | 5080 | |
6e3c9717 | 5081 | if (intel_crtc->config->has_pch_encoder) { |
ab4d966c | 5082 | lpt_disable_pch_transcoder(dev_priv); |
1ad960f2 | 5083 | intel_ddi_fdi_disable(crtc); |
83616634 | 5084 | } |
4f771f10 | 5085 | |
97b040aa ID |
5086 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5087 | if (encoder->post_disable) | |
5088 | encoder->post_disable(encoder); | |
e4ca0612 PJ |
5089 | |
5090 | intel_crtc->active = false; | |
5091 | intel_update_watermarks(crtc); | |
4f771f10 PZ |
5092 | } |
5093 | ||
2dd24552 JB |
5094 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
5095 | { | |
5096 | struct drm_device *dev = crtc->base.dev; | |
5097 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 5098 | struct intel_crtc_state *pipe_config = crtc->config; |
2dd24552 | 5099 | |
681a8504 | 5100 | if (!pipe_config->gmch_pfit.control) |
2dd24552 JB |
5101 | return; |
5102 | ||
2dd24552 | 5103 | /* |
c0b03411 DV |
5104 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
5105 | * according to register description and PRM. | |
2dd24552 | 5106 | */ |
c0b03411 DV |
5107 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
5108 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 5109 | |
b074cec8 JB |
5110 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
5111 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
5112 | |
5113 | /* Border color in case we don't scale up to the full screen. Black by | |
5114 | * default, change to something else for debugging. */ | |
5115 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
5116 | } |
5117 | ||
d05410f9 DA |
5118 | static enum intel_display_power_domain port_to_power_domain(enum port port) |
5119 | { | |
5120 | switch (port) { | |
5121 | case PORT_A: | |
5122 | return POWER_DOMAIN_PORT_DDI_A_4_LANES; | |
5123 | case PORT_B: | |
5124 | return POWER_DOMAIN_PORT_DDI_B_4_LANES; | |
5125 | case PORT_C: | |
5126 | return POWER_DOMAIN_PORT_DDI_C_4_LANES; | |
5127 | case PORT_D: | |
5128 | return POWER_DOMAIN_PORT_DDI_D_4_LANES; | |
d8e19f99 XZ |
5129 | case PORT_E: |
5130 | return POWER_DOMAIN_PORT_DDI_E_2_LANES; | |
d05410f9 DA |
5131 | default: |
5132 | WARN_ON_ONCE(1); | |
5133 | return POWER_DOMAIN_PORT_OTHER; | |
5134 | } | |
5135 | } | |
5136 | ||
77d22dca ID |
5137 | #define for_each_power_domain(domain, mask) \ |
5138 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ | |
5139 | if ((1 << (domain)) & (mask)) | |
5140 | ||
319be8ae ID |
5141 | enum intel_display_power_domain |
5142 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) | |
5143 | { | |
5144 | struct drm_device *dev = intel_encoder->base.dev; | |
5145 | struct intel_digital_port *intel_dig_port; | |
5146 | ||
5147 | switch (intel_encoder->type) { | |
5148 | case INTEL_OUTPUT_UNKNOWN: | |
5149 | /* Only DDI platforms should ever use this output type */ | |
5150 | WARN_ON_ONCE(!HAS_DDI(dev)); | |
5151 | case INTEL_OUTPUT_DISPLAYPORT: | |
5152 | case INTEL_OUTPUT_HDMI: | |
5153 | case INTEL_OUTPUT_EDP: | |
5154 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
d05410f9 | 5155 | return port_to_power_domain(intel_dig_port->port); |
0e32b39c DA |
5156 | case INTEL_OUTPUT_DP_MST: |
5157 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5158 | return port_to_power_domain(intel_dig_port->port); | |
319be8ae ID |
5159 | case INTEL_OUTPUT_ANALOG: |
5160 | return POWER_DOMAIN_PORT_CRT; | |
5161 | case INTEL_OUTPUT_DSI: | |
5162 | return POWER_DOMAIN_PORT_DSI; | |
5163 | default: | |
5164 | return POWER_DOMAIN_PORT_OTHER; | |
5165 | } | |
5166 | } | |
5167 | ||
5168 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc) | |
77d22dca | 5169 | { |
319be8ae ID |
5170 | struct drm_device *dev = crtc->dev; |
5171 | struct intel_encoder *intel_encoder; | |
5172 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5173 | enum pipe pipe = intel_crtc->pipe; | |
77d22dca ID |
5174 | unsigned long mask; |
5175 | enum transcoder transcoder; | |
5176 | ||
292b990e ML |
5177 | if (!crtc->state->active) |
5178 | return 0; | |
5179 | ||
77d22dca ID |
5180 | transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe); |
5181 | ||
5182 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); | |
5183 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
6e3c9717 ACO |
5184 | if (intel_crtc->config->pch_pfit.enabled || |
5185 | intel_crtc->config->pch_pfit.force_thru) | |
77d22dca ID |
5186 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
5187 | ||
319be8ae ID |
5188 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
5189 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); | |
5190 | ||
77d22dca ID |
5191 | return mask; |
5192 | } | |
5193 | ||
292b990e | 5194 | static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc) |
77d22dca | 5195 | { |
292b990e ML |
5196 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
5197 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5198 | enum intel_display_power_domain domain; | |
5199 | unsigned long domains, new_domains, old_domains; | |
77d22dca | 5200 | |
292b990e ML |
5201 | old_domains = intel_crtc->enabled_power_domains; |
5202 | intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc); | |
77d22dca | 5203 | |
292b990e ML |
5204 | domains = new_domains & ~old_domains; |
5205 | ||
5206 | for_each_power_domain(domain, domains) | |
5207 | intel_display_power_get(dev_priv, domain); | |
5208 | ||
5209 | return old_domains & ~new_domains; | |
5210 | } | |
5211 | ||
5212 | static void modeset_put_power_domains(struct drm_i915_private *dev_priv, | |
5213 | unsigned long domains) | |
5214 | { | |
5215 | enum intel_display_power_domain domain; | |
5216 | ||
5217 | for_each_power_domain(domain, domains) | |
5218 | intel_display_power_put(dev_priv, domain); | |
5219 | } | |
77d22dca | 5220 | |
292b990e ML |
5221 | static void modeset_update_crtc_power_domains(struct drm_atomic_state *state) |
5222 | { | |
5223 | struct drm_device *dev = state->dev; | |
5224 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5225 | unsigned long put_domains[I915_MAX_PIPES] = {}; | |
5226 | struct drm_crtc_state *crtc_state; | |
5227 | struct drm_crtc *crtc; | |
5228 | int i; | |
77d22dca | 5229 | |
292b990e ML |
5230 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
5231 | if (needs_modeset(crtc->state)) | |
5232 | put_domains[to_intel_crtc(crtc)->pipe] = | |
5233 | modeset_get_crtc_power_domains(crtc); | |
77d22dca ID |
5234 | } |
5235 | ||
27c329ed ML |
5236 | if (dev_priv->display.modeset_commit_cdclk) { |
5237 | unsigned int cdclk = to_intel_atomic_state(state)->cdclk; | |
5238 | ||
5239 | if (cdclk != dev_priv->cdclk_freq && | |
5240 | !WARN_ON(!state->allow_modeset)) | |
5241 | dev_priv->display.modeset_commit_cdclk(state); | |
5242 | } | |
50f6e502 | 5243 | |
292b990e ML |
5244 | for (i = 0; i < I915_MAX_PIPES; i++) |
5245 | if (put_domains[i]) | |
5246 | modeset_put_power_domains(dev_priv, put_domains[i]); | |
77d22dca ID |
5247 | } |
5248 | ||
adafdc6f MK |
5249 | static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) |
5250 | { | |
5251 | int max_cdclk_freq = dev_priv->max_cdclk_freq; | |
5252 | ||
5253 | if (INTEL_INFO(dev_priv)->gen >= 9 || | |
5254 | IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) | |
5255 | return max_cdclk_freq; | |
5256 | else if (IS_CHERRYVIEW(dev_priv)) | |
5257 | return max_cdclk_freq*95/100; | |
5258 | else if (INTEL_INFO(dev_priv)->gen < 4) | |
5259 | return 2*max_cdclk_freq*90/100; | |
5260 | else | |
5261 | return max_cdclk_freq*90/100; | |
5262 | } | |
5263 | ||
560a7ae4 DL |
5264 | static void intel_update_max_cdclk(struct drm_device *dev) |
5265 | { | |
5266 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5267 | ||
5268 | if (IS_SKYLAKE(dev)) { | |
5269 | u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; | |
5270 | ||
5271 | if (limit == SKL_DFSM_CDCLK_LIMIT_675) | |
5272 | dev_priv->max_cdclk_freq = 675000; | |
5273 | else if (limit == SKL_DFSM_CDCLK_LIMIT_540) | |
5274 | dev_priv->max_cdclk_freq = 540000; | |
5275 | else if (limit == SKL_DFSM_CDCLK_LIMIT_450) | |
5276 | dev_priv->max_cdclk_freq = 450000; | |
5277 | else | |
5278 | dev_priv->max_cdclk_freq = 337500; | |
5279 | } else if (IS_BROADWELL(dev)) { | |
5280 | /* | |
5281 | * FIXME with extra cooling we can allow | |
5282 | * 540 MHz for ULX and 675 Mhz for ULT. | |
5283 | * How can we know if extra cooling is | |
5284 | * available? PCI ID, VTB, something else? | |
5285 | */ | |
5286 | if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
5287 | dev_priv->max_cdclk_freq = 450000; | |
5288 | else if (IS_BDW_ULX(dev)) | |
5289 | dev_priv->max_cdclk_freq = 450000; | |
5290 | else if (IS_BDW_ULT(dev)) | |
5291 | dev_priv->max_cdclk_freq = 540000; | |
5292 | else | |
5293 | dev_priv->max_cdclk_freq = 675000; | |
0904deaf MK |
5294 | } else if (IS_CHERRYVIEW(dev)) { |
5295 | dev_priv->max_cdclk_freq = 320000; | |
560a7ae4 DL |
5296 | } else if (IS_VALLEYVIEW(dev)) { |
5297 | dev_priv->max_cdclk_freq = 400000; | |
5298 | } else { | |
5299 | /* otherwise assume cdclk is fixed */ | |
5300 | dev_priv->max_cdclk_freq = dev_priv->cdclk_freq; | |
5301 | } | |
5302 | ||
adafdc6f MK |
5303 | dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); |
5304 | ||
560a7ae4 DL |
5305 | DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n", |
5306 | dev_priv->max_cdclk_freq); | |
adafdc6f MK |
5307 | |
5308 | DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n", | |
5309 | dev_priv->max_dotclk_freq); | |
560a7ae4 DL |
5310 | } |
5311 | ||
5312 | static void intel_update_cdclk(struct drm_device *dev) | |
5313 | { | |
5314 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5315 | ||
5316 | dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev); | |
5317 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n", | |
5318 | dev_priv->cdclk_freq); | |
5319 | ||
5320 | /* | |
5321 | * Program the gmbus_freq based on the cdclk frequency. | |
5322 | * BSpec erroneously claims we should aim for 4MHz, but | |
5323 | * in fact 1MHz is the correct frequency. | |
5324 | */ | |
5325 | if (IS_VALLEYVIEW(dev)) { | |
5326 | /* | |
5327 | * Program the gmbus_freq based on the cdclk frequency. | |
5328 | * BSpec erroneously claims we should aim for 4MHz, but | |
5329 | * in fact 1MHz is the correct frequency. | |
5330 | */ | |
5331 | I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000)); | |
5332 | } | |
5333 | ||
5334 | if (dev_priv->max_cdclk_freq == 0) | |
5335 | intel_update_max_cdclk(dev); | |
5336 | } | |
5337 | ||
70d0c574 | 5338 | static void broxton_set_cdclk(struct drm_device *dev, int frequency) |
f8437dd1 VK |
5339 | { |
5340 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5341 | uint32_t divider; | |
5342 | uint32_t ratio; | |
5343 | uint32_t current_freq; | |
5344 | int ret; | |
5345 | ||
5346 | /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */ | |
5347 | switch (frequency) { | |
5348 | case 144000: | |
5349 | divider = BXT_CDCLK_CD2X_DIV_SEL_4; | |
5350 | ratio = BXT_DE_PLL_RATIO(60); | |
5351 | break; | |
5352 | case 288000: | |
5353 | divider = BXT_CDCLK_CD2X_DIV_SEL_2; | |
5354 | ratio = BXT_DE_PLL_RATIO(60); | |
5355 | break; | |
5356 | case 384000: | |
5357 | divider = BXT_CDCLK_CD2X_DIV_SEL_1_5; | |
5358 | ratio = BXT_DE_PLL_RATIO(60); | |
5359 | break; | |
5360 | case 576000: | |
5361 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
5362 | ratio = BXT_DE_PLL_RATIO(60); | |
5363 | break; | |
5364 | case 624000: | |
5365 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
5366 | ratio = BXT_DE_PLL_RATIO(65); | |
5367 | break; | |
5368 | case 19200: | |
5369 | /* | |
5370 | * Bypass frequency with DE PLL disabled. Init ratio, divider | |
5371 | * to suppress GCC warning. | |
5372 | */ | |
5373 | ratio = 0; | |
5374 | divider = 0; | |
5375 | break; | |
5376 | default: | |
5377 | DRM_ERROR("unsupported CDCLK freq %d", frequency); | |
5378 | ||
5379 | return; | |
5380 | } | |
5381 | ||
5382 | mutex_lock(&dev_priv->rps.hw_lock); | |
5383 | /* Inform power controller of upcoming frequency change */ | |
5384 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
5385 | 0x80000000); | |
5386 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5387 | ||
5388 | if (ret) { | |
5389 | DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n", | |
5390 | ret, frequency); | |
5391 | return; | |
5392 | } | |
5393 | ||
5394 | current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK; | |
5395 | /* convert from .1 fixpoint MHz with -1MHz offset to kHz */ | |
5396 | current_freq = current_freq * 500 + 1000; | |
5397 | ||
5398 | /* | |
5399 | * DE PLL has to be disabled when | |
5400 | * - setting to 19.2MHz (bypass, PLL isn't used) | |
5401 | * - before setting to 624MHz (PLL needs toggling) | |
5402 | * - before setting to any frequency from 624MHz (PLL needs toggling) | |
5403 | */ | |
5404 | if (frequency == 19200 || frequency == 624000 || | |
5405 | current_freq == 624000) { | |
5406 | I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE); | |
5407 | /* Timeout 200us */ | |
5408 | if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK), | |
5409 | 1)) | |
5410 | DRM_ERROR("timout waiting for DE PLL unlock\n"); | |
5411 | } | |
5412 | ||
5413 | if (frequency != 19200) { | |
5414 | uint32_t val; | |
5415 | ||
5416 | val = I915_READ(BXT_DE_PLL_CTL); | |
5417 | val &= ~BXT_DE_PLL_RATIO_MASK; | |
5418 | val |= ratio; | |
5419 | I915_WRITE(BXT_DE_PLL_CTL, val); | |
5420 | ||
5421 | I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); | |
5422 | /* Timeout 200us */ | |
5423 | if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1)) | |
5424 | DRM_ERROR("timeout waiting for DE PLL lock\n"); | |
5425 | ||
5426 | val = I915_READ(CDCLK_CTL); | |
5427 | val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK; | |
5428 | val |= divider; | |
5429 | /* | |
5430 | * Disable SSA Precharge when CD clock frequency < 500 MHz, | |
5431 | * enable otherwise. | |
5432 | */ | |
5433 | val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5434 | if (frequency >= 500000) | |
5435 | val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5436 | ||
5437 | val &= ~CDCLK_FREQ_DECIMAL_MASK; | |
5438 | /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ | |
5439 | val |= (frequency - 1000) / 500; | |
5440 | I915_WRITE(CDCLK_CTL, val); | |
5441 | } | |
5442 | ||
5443 | mutex_lock(&dev_priv->rps.hw_lock); | |
5444 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
5445 | DIV_ROUND_UP(frequency, 25000)); | |
5446 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5447 | ||
5448 | if (ret) { | |
5449 | DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n", | |
5450 | ret, frequency); | |
5451 | return; | |
5452 | } | |
5453 | ||
a47871bd | 5454 | intel_update_cdclk(dev); |
f8437dd1 VK |
5455 | } |
5456 | ||
5457 | void broxton_init_cdclk(struct drm_device *dev) | |
5458 | { | |
5459 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5460 | uint32_t val; | |
5461 | ||
5462 | /* | |
5463 | * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT | |
5464 | * or else the reset will hang because there is no PCH to respond. | |
5465 | * Move the handshake programming to initialization sequence. | |
5466 | * Previously was left up to BIOS. | |
5467 | */ | |
5468 | val = I915_READ(HSW_NDE_RSTWRN_OPT); | |
5469 | val &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
5470 | I915_WRITE(HSW_NDE_RSTWRN_OPT, val); | |
5471 | ||
5472 | /* Enable PG1 for cdclk */ | |
5473 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); | |
5474 | ||
5475 | /* check if cd clock is enabled */ | |
5476 | if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) { | |
5477 | DRM_DEBUG_KMS("Display already initialized\n"); | |
5478 | return; | |
5479 | } | |
5480 | ||
5481 | /* | |
5482 | * FIXME: | |
5483 | * - The initial CDCLK needs to be read from VBT. | |
5484 | * Need to make this change after VBT has changes for BXT. | |
5485 | * - check if setting the max (or any) cdclk freq is really necessary | |
5486 | * here, it belongs to modeset time | |
5487 | */ | |
5488 | broxton_set_cdclk(dev, 624000); | |
5489 | ||
5490 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); | |
22e02c0b VS |
5491 | POSTING_READ(DBUF_CTL); |
5492 | ||
f8437dd1 VK |
5493 | udelay(10); |
5494 | ||
5495 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) | |
5496 | DRM_ERROR("DBuf power enable timeout!\n"); | |
5497 | } | |
5498 | ||
5499 | void broxton_uninit_cdclk(struct drm_device *dev) | |
5500 | { | |
5501 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5502 | ||
5503 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); | |
22e02c0b VS |
5504 | POSTING_READ(DBUF_CTL); |
5505 | ||
f8437dd1 VK |
5506 | udelay(10); |
5507 | ||
5508 | if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) | |
5509 | DRM_ERROR("DBuf power disable timeout!\n"); | |
5510 | ||
5511 | /* Set minimum (bypass) frequency, in effect turning off the DE PLL */ | |
5512 | broxton_set_cdclk(dev, 19200); | |
5513 | ||
5514 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
5515 | } | |
5516 | ||
5d96d8af DL |
5517 | static const struct skl_cdclk_entry { |
5518 | unsigned int freq; | |
5519 | unsigned int vco; | |
5520 | } skl_cdclk_frequencies[] = { | |
5521 | { .freq = 308570, .vco = 8640 }, | |
5522 | { .freq = 337500, .vco = 8100 }, | |
5523 | { .freq = 432000, .vco = 8640 }, | |
5524 | { .freq = 450000, .vco = 8100 }, | |
5525 | { .freq = 540000, .vco = 8100 }, | |
5526 | { .freq = 617140, .vco = 8640 }, | |
5527 | { .freq = 675000, .vco = 8100 }, | |
5528 | }; | |
5529 | ||
5530 | static unsigned int skl_cdclk_decimal(unsigned int freq) | |
5531 | { | |
5532 | return (freq - 1000) / 500; | |
5533 | } | |
5534 | ||
5535 | static unsigned int skl_cdclk_get_vco(unsigned int freq) | |
5536 | { | |
5537 | unsigned int i; | |
5538 | ||
5539 | for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) { | |
5540 | const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i]; | |
5541 | ||
5542 | if (e->freq == freq) | |
5543 | return e->vco; | |
5544 | } | |
5545 | ||
5546 | return 8100; | |
5547 | } | |
5548 | ||
5549 | static void | |
5550 | skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco) | |
5551 | { | |
5552 | unsigned int min_freq; | |
5553 | u32 val; | |
5554 | ||
5555 | /* select the minimum CDCLK before enabling DPLL 0 */ | |
5556 | val = I915_READ(CDCLK_CTL); | |
5557 | val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK; | |
5558 | val |= CDCLK_FREQ_337_308; | |
5559 | ||
5560 | if (required_vco == 8640) | |
5561 | min_freq = 308570; | |
5562 | else | |
5563 | min_freq = 337500; | |
5564 | ||
5565 | val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq); | |
5566 | ||
5567 | I915_WRITE(CDCLK_CTL, val); | |
5568 | POSTING_READ(CDCLK_CTL); | |
5569 | ||
5570 | /* | |
5571 | * We always enable DPLL0 with the lowest link rate possible, but still | |
5572 | * taking into account the VCO required to operate the eDP panel at the | |
5573 | * desired frequency. The usual DP link rates operate with a VCO of | |
5574 | * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. | |
5575 | * The modeset code is responsible for the selection of the exact link | |
5576 | * rate later on, with the constraint of choosing a frequency that | |
5577 | * works with required_vco. | |
5578 | */ | |
5579 | val = I915_READ(DPLL_CTRL1); | |
5580 | ||
5581 | val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) | | |
5582 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); | |
5583 | val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0); | |
5584 | if (required_vco == 8640) | |
5585 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, | |
5586 | SKL_DPLL0); | |
5587 | else | |
5588 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, | |
5589 | SKL_DPLL0); | |
5590 | ||
5591 | I915_WRITE(DPLL_CTRL1, val); | |
5592 | POSTING_READ(DPLL_CTRL1); | |
5593 | ||
5594 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE); | |
5595 | ||
5596 | if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5)) | |
5597 | DRM_ERROR("DPLL0 not locked\n"); | |
5598 | } | |
5599 | ||
5600 | static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv) | |
5601 | { | |
5602 | int ret; | |
5603 | u32 val; | |
5604 | ||
5605 | /* inform PCU we want to change CDCLK */ | |
5606 | val = SKL_CDCLK_PREPARE_FOR_CHANGE; | |
5607 | mutex_lock(&dev_priv->rps.hw_lock); | |
5608 | ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val); | |
5609 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5610 | ||
5611 | return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE); | |
5612 | } | |
5613 | ||
5614 | static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv) | |
5615 | { | |
5616 | unsigned int i; | |
5617 | ||
5618 | for (i = 0; i < 15; i++) { | |
5619 | if (skl_cdclk_pcu_ready(dev_priv)) | |
5620 | return true; | |
5621 | udelay(10); | |
5622 | } | |
5623 | ||
5624 | return false; | |
5625 | } | |
5626 | ||
5627 | static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq) | |
5628 | { | |
560a7ae4 | 5629 | struct drm_device *dev = dev_priv->dev; |
5d96d8af DL |
5630 | u32 freq_select, pcu_ack; |
5631 | ||
5632 | DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq); | |
5633 | ||
5634 | if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) { | |
5635 | DRM_ERROR("failed to inform PCU about cdclk change\n"); | |
5636 | return; | |
5637 | } | |
5638 | ||
5639 | /* set CDCLK_CTL */ | |
5640 | switch(freq) { | |
5641 | case 450000: | |
5642 | case 432000: | |
5643 | freq_select = CDCLK_FREQ_450_432; | |
5644 | pcu_ack = 1; | |
5645 | break; | |
5646 | case 540000: | |
5647 | freq_select = CDCLK_FREQ_540; | |
5648 | pcu_ack = 2; | |
5649 | break; | |
5650 | case 308570: | |
5651 | case 337500: | |
5652 | default: | |
5653 | freq_select = CDCLK_FREQ_337_308; | |
5654 | pcu_ack = 0; | |
5655 | break; | |
5656 | case 617140: | |
5657 | case 675000: | |
5658 | freq_select = CDCLK_FREQ_675_617; | |
5659 | pcu_ack = 3; | |
5660 | break; | |
5661 | } | |
5662 | ||
5663 | I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq)); | |
5664 | POSTING_READ(CDCLK_CTL); | |
5665 | ||
5666 | /* inform PCU of the change */ | |
5667 | mutex_lock(&dev_priv->rps.hw_lock); | |
5668 | sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack); | |
5669 | mutex_unlock(&dev_priv->rps.hw_lock); | |
560a7ae4 DL |
5670 | |
5671 | intel_update_cdclk(dev); | |
5d96d8af DL |
5672 | } |
5673 | ||
5674 | void skl_uninit_cdclk(struct drm_i915_private *dev_priv) | |
5675 | { | |
5676 | /* disable DBUF power */ | |
5677 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); | |
5678 | POSTING_READ(DBUF_CTL); | |
5679 | ||
5680 | udelay(10); | |
5681 | ||
5682 | if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) | |
5683 | DRM_ERROR("DBuf power disable timeout\n"); | |
5684 | ||
5685 | /* disable DPLL0 */ | |
5686 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE); | |
5687 | if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1)) | |
5688 | DRM_ERROR("Couldn't disable DPLL0\n"); | |
5689 | ||
5690 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
5691 | } | |
5692 | ||
5693 | void skl_init_cdclk(struct drm_i915_private *dev_priv) | |
5694 | { | |
5695 | u32 val; | |
5696 | unsigned int required_vco; | |
5697 | ||
5698 | /* enable PCH reset handshake */ | |
5699 | val = I915_READ(HSW_NDE_RSTWRN_OPT); | |
5700 | I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE); | |
5701 | ||
5702 | /* enable PG1 and Misc I/O */ | |
5703 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); | |
5704 | ||
39d9b85a GW |
5705 | /* DPLL0 not enabled (happens on early BIOS versions) */ |
5706 | if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) { | |
5707 | /* enable DPLL0 */ | |
5708 | required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk); | |
5709 | skl_dpll0_enable(dev_priv, required_vco); | |
5d96d8af DL |
5710 | } |
5711 | ||
5d96d8af DL |
5712 | /* set CDCLK to the frequency the BIOS chose */ |
5713 | skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk); | |
5714 | ||
5715 | /* enable DBUF power */ | |
5716 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); | |
5717 | POSTING_READ(DBUF_CTL); | |
5718 | ||
5719 | udelay(10); | |
5720 | ||
5721 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) | |
5722 | DRM_ERROR("DBuf power enable timeout\n"); | |
5723 | } | |
5724 | ||
dfcab17e | 5725 | /* returns HPLL frequency in kHz */ |
f8bf63fd | 5726 | static int valleyview_get_vco(struct drm_i915_private *dev_priv) |
30a970c6 | 5727 | { |
586f49dc | 5728 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; |
30a970c6 | 5729 | |
586f49dc | 5730 | /* Obtain SKU information */ |
a580516d | 5731 | mutex_lock(&dev_priv->sb_lock); |
586f49dc JB |
5732 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & |
5733 | CCK_FUSE_HPLL_FREQ_MASK; | |
a580516d | 5734 | mutex_unlock(&dev_priv->sb_lock); |
30a970c6 | 5735 | |
dfcab17e | 5736 | return vco_freq[hpll_freq] * 1000; |
30a970c6 JB |
5737 | } |
5738 | ||
5739 | /* Adjust CDclk dividers to allow high res or save power if possible */ | |
5740 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
5741 | { | |
5742 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5743 | u32 val, cmd; | |
5744 | ||
164dfd28 VK |
5745 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5746 | != dev_priv->cdclk_freq); | |
d60c4473 | 5747 | |
dfcab17e | 5748 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
30a970c6 | 5749 | cmd = 2; |
dfcab17e | 5750 | else if (cdclk == 266667) |
30a970c6 JB |
5751 | cmd = 1; |
5752 | else | |
5753 | cmd = 0; | |
5754 | ||
5755 | mutex_lock(&dev_priv->rps.hw_lock); | |
5756 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5757 | val &= ~DSPFREQGUAR_MASK; | |
5758 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
5759 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5760 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5761 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
5762 | 50)) { | |
5763 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5764 | } | |
5765 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5766 | ||
54433e91 VS |
5767 | mutex_lock(&dev_priv->sb_lock); |
5768 | ||
dfcab17e | 5769 | if (cdclk == 400000) { |
6bcda4f0 | 5770 | u32 divider; |
30a970c6 | 5771 | |
6bcda4f0 | 5772 | divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; |
30a970c6 | 5773 | |
30a970c6 JB |
5774 | /* adjust cdclk divider */ |
5775 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
9cf33db5 | 5776 | val &= ~DISPLAY_FREQUENCY_VALUES; |
30a970c6 JB |
5777 | val |= divider; |
5778 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
a877e801 VS |
5779 | |
5780 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & | |
5781 | DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT), | |
5782 | 50)) | |
5783 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
30a970c6 JB |
5784 | } |
5785 | ||
30a970c6 JB |
5786 | /* adjust self-refresh exit latency value */ |
5787 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
5788 | val &= ~0x7f; | |
5789 | ||
5790 | /* | |
5791 | * For high bandwidth configs, we set a higher latency in the bunit | |
5792 | * so that the core display fetch happens in time to avoid underruns. | |
5793 | */ | |
dfcab17e | 5794 | if (cdclk == 400000) |
30a970c6 JB |
5795 | val |= 4500 / 250; /* 4.5 usec */ |
5796 | else | |
5797 | val |= 3000 / 250; /* 3.0 usec */ | |
5798 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
54433e91 | 5799 | |
a580516d | 5800 | mutex_unlock(&dev_priv->sb_lock); |
30a970c6 | 5801 | |
b6283055 | 5802 | intel_update_cdclk(dev); |
30a970c6 JB |
5803 | } |
5804 | ||
383c5a6a VS |
5805 | static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) |
5806 | { | |
5807 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5808 | u32 val, cmd; | |
5809 | ||
164dfd28 VK |
5810 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5811 | != dev_priv->cdclk_freq); | |
383c5a6a VS |
5812 | |
5813 | switch (cdclk) { | |
383c5a6a VS |
5814 | case 333333: |
5815 | case 320000: | |
383c5a6a | 5816 | case 266667: |
383c5a6a | 5817 | case 200000: |
383c5a6a VS |
5818 | break; |
5819 | default: | |
5f77eeb0 | 5820 | MISSING_CASE(cdclk); |
383c5a6a VS |
5821 | return; |
5822 | } | |
5823 | ||
9d0d3fda VS |
5824 | /* |
5825 | * Specs are full of misinformation, but testing on actual | |
5826 | * hardware has shown that we just need to write the desired | |
5827 | * CCK divider into the Punit register. | |
5828 | */ | |
5829 | cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; | |
5830 | ||
383c5a6a VS |
5831 | mutex_lock(&dev_priv->rps.hw_lock); |
5832 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5833 | val &= ~DSPFREQGUAR_MASK_CHV; | |
5834 | val |= (cmd << DSPFREQGUAR_SHIFT_CHV); | |
5835 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5836 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5837 | DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), | |
5838 | 50)) { | |
5839 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5840 | } | |
5841 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5842 | ||
b6283055 | 5843 | intel_update_cdclk(dev); |
383c5a6a VS |
5844 | } |
5845 | ||
30a970c6 JB |
5846 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
5847 | int max_pixclk) | |
5848 | { | |
6bcda4f0 | 5849 | int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000; |
6cca3195 | 5850 | int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90; |
29dc7ef3 | 5851 | |
30a970c6 JB |
5852 | /* |
5853 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
5854 | * 200MHz | |
5855 | * 267MHz | |
29dc7ef3 | 5856 | * 320/333MHz (depends on HPLL freq) |
6cca3195 VS |
5857 | * 400MHz (VLV only) |
5858 | * So we check to see whether we're above 90% (VLV) or 95% (CHV) | |
5859 | * of the lower bin and adjust if needed. | |
e37c67a1 VS |
5860 | * |
5861 | * We seem to get an unstable or solid color picture at 200MHz. | |
5862 | * Not sure what's wrong. For now use 200MHz only when all pipes | |
5863 | * are off. | |
30a970c6 | 5864 | */ |
6cca3195 VS |
5865 | if (!IS_CHERRYVIEW(dev_priv) && |
5866 | max_pixclk > freq_320*limit/100) | |
dfcab17e | 5867 | return 400000; |
6cca3195 | 5868 | else if (max_pixclk > 266667*limit/100) |
29dc7ef3 | 5869 | return freq_320; |
e37c67a1 | 5870 | else if (max_pixclk > 0) |
dfcab17e | 5871 | return 266667; |
e37c67a1 VS |
5872 | else |
5873 | return 200000; | |
30a970c6 JB |
5874 | } |
5875 | ||
f8437dd1 VK |
5876 | static int broxton_calc_cdclk(struct drm_i915_private *dev_priv, |
5877 | int max_pixclk) | |
5878 | { | |
5879 | /* | |
5880 | * FIXME: | |
5881 | * - remove the guardband, it's not needed on BXT | |
5882 | * - set 19.2MHz bypass frequency if there are no active pipes | |
5883 | */ | |
5884 | if (max_pixclk > 576000*9/10) | |
5885 | return 624000; | |
5886 | else if (max_pixclk > 384000*9/10) | |
5887 | return 576000; | |
5888 | else if (max_pixclk > 288000*9/10) | |
5889 | return 384000; | |
5890 | else if (max_pixclk > 144000*9/10) | |
5891 | return 288000; | |
5892 | else | |
5893 | return 144000; | |
5894 | } | |
5895 | ||
a821fc46 ACO |
5896 | /* Compute the max pixel clock for new configuration. Uses atomic state if |
5897 | * that's non-NULL, look at current state otherwise. */ | |
5898 | static int intel_mode_max_pixclk(struct drm_device *dev, | |
5899 | struct drm_atomic_state *state) | |
30a970c6 | 5900 | { |
30a970c6 | 5901 | struct intel_crtc *intel_crtc; |
304603f4 | 5902 | struct intel_crtc_state *crtc_state; |
30a970c6 JB |
5903 | int max_pixclk = 0; |
5904 | ||
d3fcc808 | 5905 | for_each_intel_crtc(dev, intel_crtc) { |
27c329ed | 5906 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
304603f4 ACO |
5907 | if (IS_ERR(crtc_state)) |
5908 | return PTR_ERR(crtc_state); | |
5909 | ||
5910 | if (!crtc_state->base.enable) | |
5911 | continue; | |
5912 | ||
5913 | max_pixclk = max(max_pixclk, | |
5914 | crtc_state->base.adjusted_mode.crtc_clock); | |
30a970c6 JB |
5915 | } |
5916 | ||
5917 | return max_pixclk; | |
5918 | } | |
5919 | ||
27c329ed | 5920 | static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state) |
30a970c6 | 5921 | { |
27c329ed ML |
5922 | struct drm_device *dev = state->dev; |
5923 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5924 | int max_pixclk = intel_mode_max_pixclk(dev, state); | |
30a970c6 | 5925 | |
304603f4 ACO |
5926 | if (max_pixclk < 0) |
5927 | return max_pixclk; | |
30a970c6 | 5928 | |
27c329ed ML |
5929 | to_intel_atomic_state(state)->cdclk = |
5930 | valleyview_calc_cdclk(dev_priv, max_pixclk); | |
0a9ab303 | 5931 | |
27c329ed ML |
5932 | return 0; |
5933 | } | |
304603f4 | 5934 | |
27c329ed ML |
5935 | static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state) |
5936 | { | |
5937 | struct drm_device *dev = state->dev; | |
5938 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5939 | int max_pixclk = intel_mode_max_pixclk(dev, state); | |
85a96e7a | 5940 | |
27c329ed ML |
5941 | if (max_pixclk < 0) |
5942 | return max_pixclk; | |
85a96e7a | 5943 | |
27c329ed ML |
5944 | to_intel_atomic_state(state)->cdclk = |
5945 | broxton_calc_cdclk(dev_priv, max_pixclk); | |
85a96e7a | 5946 | |
27c329ed | 5947 | return 0; |
30a970c6 JB |
5948 | } |
5949 | ||
1e69cd74 VS |
5950 | static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) |
5951 | { | |
5952 | unsigned int credits, default_credits; | |
5953 | ||
5954 | if (IS_CHERRYVIEW(dev_priv)) | |
5955 | default_credits = PFI_CREDIT(12); | |
5956 | else | |
5957 | default_credits = PFI_CREDIT(8); | |
5958 | ||
164dfd28 | 5959 | if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) { |
1e69cd74 VS |
5960 | /* CHV suggested value is 31 or 63 */ |
5961 | if (IS_CHERRYVIEW(dev_priv)) | |
fcc0008f | 5962 | credits = PFI_CREDIT_63; |
1e69cd74 VS |
5963 | else |
5964 | credits = PFI_CREDIT(15); | |
5965 | } else { | |
5966 | credits = default_credits; | |
5967 | } | |
5968 | ||
5969 | /* | |
5970 | * WA - write default credits before re-programming | |
5971 | * FIXME: should we also set the resend bit here? | |
5972 | */ | |
5973 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
5974 | default_credits); | |
5975 | ||
5976 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
5977 | credits | PFI_CREDIT_RESEND); | |
5978 | ||
5979 | /* | |
5980 | * FIXME is this guaranteed to clear | |
5981 | * immediately or should we poll for it? | |
5982 | */ | |
5983 | WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); | |
5984 | } | |
5985 | ||
27c329ed | 5986 | static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
30a970c6 | 5987 | { |
a821fc46 | 5988 | struct drm_device *dev = old_state->dev; |
27c329ed | 5989 | unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk; |
30a970c6 | 5990 | struct drm_i915_private *dev_priv = dev->dev_private; |
30a970c6 | 5991 | |
27c329ed ML |
5992 | /* |
5993 | * FIXME: We can end up here with all power domains off, yet | |
5994 | * with a CDCLK frequency other than the minimum. To account | |
5995 | * for this take the PIPE-A power domain, which covers the HW | |
5996 | * blocks needed for the following programming. This can be | |
5997 | * removed once it's guaranteed that we get here either with | |
5998 | * the minimum CDCLK set, or the required power domains | |
5999 | * enabled. | |
6000 | */ | |
6001 | intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); | |
738c05c0 | 6002 | |
27c329ed ML |
6003 | if (IS_CHERRYVIEW(dev)) |
6004 | cherryview_set_cdclk(dev, req_cdclk); | |
6005 | else | |
6006 | valleyview_set_cdclk(dev, req_cdclk); | |
738c05c0 | 6007 | |
27c329ed | 6008 | vlv_program_pfi_credits(dev_priv); |
1e69cd74 | 6009 | |
27c329ed | 6010 | intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); |
30a970c6 JB |
6011 | } |
6012 | ||
89b667f8 JB |
6013 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
6014 | { | |
6015 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 6016 | struct drm_i915_private *dev_priv = to_i915(dev); |
89b667f8 JB |
6017 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6018 | struct intel_encoder *encoder; | |
6019 | int pipe = intel_crtc->pipe; | |
23538ef1 | 6020 | bool is_dsi; |
89b667f8 | 6021 | |
53d9f4e9 | 6022 | if (WARN_ON(intel_crtc->active)) |
89b667f8 JB |
6023 | return; |
6024 | ||
409ee761 | 6025 | is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI); |
8525a235 | 6026 | |
6e3c9717 | 6027 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 6028 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6029 | |
6030 | intel_set_pipe_timings(intel_crtc); | |
6031 | ||
c14b0485 VS |
6032 | if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) { |
6033 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6034 | ||
6035 | I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); | |
6036 | I915_WRITE(CHV_CANVAS(pipe), 0); | |
6037 | } | |
6038 | ||
5b18e57c DV |
6039 | i9xx_set_pipeconf(intel_crtc); |
6040 | ||
89b667f8 | 6041 | intel_crtc->active = true; |
89b667f8 | 6042 | |
a72e4c9f | 6043 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6044 | |
89b667f8 JB |
6045 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6046 | if (encoder->pre_pll_enable) | |
6047 | encoder->pre_pll_enable(encoder); | |
6048 | ||
9d556c99 | 6049 | if (!is_dsi) { |
c0b4c660 VS |
6050 | if (IS_CHERRYVIEW(dev)) { |
6051 | chv_prepare_pll(intel_crtc, intel_crtc->config); | |
6e3c9717 | 6052 | chv_enable_pll(intel_crtc, intel_crtc->config); |
c0b4c660 VS |
6053 | } else { |
6054 | vlv_prepare_pll(intel_crtc, intel_crtc->config); | |
6e3c9717 | 6055 | vlv_enable_pll(intel_crtc, intel_crtc->config); |
c0b4c660 | 6056 | } |
9d556c99 | 6057 | } |
89b667f8 JB |
6058 | |
6059 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
6060 | if (encoder->pre_enable) | |
6061 | encoder->pre_enable(encoder); | |
6062 | ||
2dd24552 JB |
6063 | i9xx_pfit_enable(intel_crtc); |
6064 | ||
63cbb074 VS |
6065 | intel_crtc_load_lut(crtc); |
6066 | ||
e1fdc473 | 6067 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6068 | |
4b3a9526 VS |
6069 | assert_vblank_disabled(crtc); |
6070 | drm_crtc_vblank_on(crtc); | |
6071 | ||
f9b61ff6 DV |
6072 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6073 | encoder->enable(encoder); | |
89b667f8 JB |
6074 | } |
6075 | ||
f13c2ef3 DV |
6076 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
6077 | { | |
6078 | struct drm_device *dev = crtc->base.dev; | |
6079 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6080 | ||
6e3c9717 ACO |
6081 | I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); |
6082 | I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); | |
f13c2ef3 DV |
6083 | } |
6084 | ||
0b8765c6 | 6085 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
6086 | { |
6087 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 6088 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 6089 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 6090 | struct intel_encoder *encoder; |
79e53945 | 6091 | int pipe = intel_crtc->pipe; |
79e53945 | 6092 | |
53d9f4e9 | 6093 | if (WARN_ON(intel_crtc->active)) |
f7abfe8b CW |
6094 | return; |
6095 | ||
f13c2ef3 DV |
6096 | i9xx_set_pll_dividers(intel_crtc); |
6097 | ||
6e3c9717 | 6098 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 6099 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6100 | |
6101 | intel_set_pipe_timings(intel_crtc); | |
6102 | ||
5b18e57c DV |
6103 | i9xx_set_pipeconf(intel_crtc); |
6104 | ||
f7abfe8b | 6105 | intel_crtc->active = true; |
6b383a7f | 6106 | |
4a3436e8 | 6107 | if (!IS_GEN2(dev)) |
a72e4c9f | 6108 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6109 | |
9d6d9f19 MK |
6110 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6111 | if (encoder->pre_enable) | |
6112 | encoder->pre_enable(encoder); | |
6113 | ||
f6736a1a DV |
6114 | i9xx_enable_pll(intel_crtc); |
6115 | ||
2dd24552 JB |
6116 | i9xx_pfit_enable(intel_crtc); |
6117 | ||
63cbb074 VS |
6118 | intel_crtc_load_lut(crtc); |
6119 | ||
f37fcc2a | 6120 | intel_update_watermarks(crtc); |
e1fdc473 | 6121 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6122 | |
4b3a9526 VS |
6123 | assert_vblank_disabled(crtc); |
6124 | drm_crtc_vblank_on(crtc); | |
6125 | ||
f9b61ff6 DV |
6126 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6127 | encoder->enable(encoder); | |
0b8765c6 | 6128 | } |
79e53945 | 6129 | |
87476d63 DV |
6130 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
6131 | { | |
6132 | struct drm_device *dev = crtc->base.dev; | |
6133 | struct drm_i915_private *dev_priv = dev->dev_private; | |
87476d63 | 6134 | |
6e3c9717 | 6135 | if (!crtc->config->gmch_pfit.control) |
328d8e82 | 6136 | return; |
87476d63 | 6137 | |
328d8e82 | 6138 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 6139 | |
328d8e82 DV |
6140 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
6141 | I915_READ(PFIT_CONTROL)); | |
6142 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
6143 | } |
6144 | ||
0b8765c6 JB |
6145 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
6146 | { | |
6147 | struct drm_device *dev = crtc->dev; | |
6148 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6149 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 6150 | struct intel_encoder *encoder; |
0b8765c6 | 6151 | int pipe = intel_crtc->pipe; |
ef9c3aee | 6152 | |
6304cd91 VS |
6153 | /* |
6154 | * On gen2 planes are double buffered but the pipe isn't, so we must | |
6155 | * wait for planes to fully turn off before disabling the pipe. | |
564ed191 ID |
6156 | * We also need to wait on all gmch platforms because of the |
6157 | * self-refresh mode constraint explained above. | |
6304cd91 | 6158 | */ |
564ed191 | 6159 | intel_wait_for_vblank(dev, pipe); |
6304cd91 | 6160 | |
4b3a9526 VS |
6161 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6162 | encoder->disable(encoder); | |
6163 | ||
f9b61ff6 DV |
6164 | drm_crtc_vblank_off(crtc); |
6165 | assert_vblank_disabled(crtc); | |
6166 | ||
575f7ab7 | 6167 | intel_disable_pipe(intel_crtc); |
24a1f16d | 6168 | |
87476d63 | 6169 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 6170 | |
89b667f8 JB |
6171 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6172 | if (encoder->post_disable) | |
6173 | encoder->post_disable(encoder); | |
6174 | ||
409ee761 | 6175 | if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) { |
076ed3b2 CML |
6176 | if (IS_CHERRYVIEW(dev)) |
6177 | chv_disable_pll(dev_priv, pipe); | |
6178 | else if (IS_VALLEYVIEW(dev)) | |
6179 | vlv_disable_pll(dev_priv, pipe); | |
6180 | else | |
1c4e0274 | 6181 | i9xx_disable_pll(intel_crtc); |
076ed3b2 | 6182 | } |
0b8765c6 | 6183 | |
d6db995f VS |
6184 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6185 | if (encoder->post_pll_disable) | |
6186 | encoder->post_pll_disable(encoder); | |
6187 | ||
4a3436e8 | 6188 | if (!IS_GEN2(dev)) |
a72e4c9f | 6189 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
e4ca0612 PJ |
6190 | |
6191 | intel_crtc->active = false; | |
6192 | intel_update_watermarks(crtc); | |
0b8765c6 JB |
6193 | } |
6194 | ||
b17d48e2 ML |
6195 | static void intel_crtc_disable_noatomic(struct drm_crtc *crtc) |
6196 | { | |
6197 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6198 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); | |
6199 | enum intel_display_power_domain domain; | |
6200 | unsigned long domains; | |
6201 | ||
6202 | if (!intel_crtc->active) | |
6203 | return; | |
6204 | ||
a539205a ML |
6205 | if (to_intel_plane_state(crtc->primary->state)->visible) { |
6206 | intel_crtc_wait_for_pending_flips(crtc); | |
6207 | intel_pre_disable_primary(crtc); | |
6208 | } | |
6209 | ||
d032ffa0 | 6210 | intel_crtc_disable_planes(crtc, crtc->state->plane_mask); |
b17d48e2 | 6211 | dev_priv->display.crtc_disable(crtc); |
1f7457b1 | 6212 | intel_disable_shared_dpll(intel_crtc); |
b17d48e2 ML |
6213 | |
6214 | domains = intel_crtc->enabled_power_domains; | |
6215 | for_each_power_domain(domain, domains) | |
6216 | intel_display_power_put(dev_priv, domain); | |
6217 | intel_crtc->enabled_power_domains = 0; | |
6218 | } | |
6219 | ||
6b72d486 ML |
6220 | /* |
6221 | * turn all crtc's off, but do not adjust state | |
6222 | * This has to be paired with a call to intel_modeset_setup_hw_state. | |
6223 | */ | |
70e0bd74 | 6224 | int intel_display_suspend(struct drm_device *dev) |
ee7b9f93 | 6225 | { |
70e0bd74 ML |
6226 | struct drm_mode_config *config = &dev->mode_config; |
6227 | struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx; | |
6228 | struct drm_atomic_state *state; | |
6b72d486 | 6229 | struct drm_crtc *crtc; |
70e0bd74 ML |
6230 | unsigned crtc_mask = 0; |
6231 | int ret = 0; | |
6232 | ||
6233 | if (WARN_ON(!ctx)) | |
6234 | return 0; | |
6235 | ||
6236 | lockdep_assert_held(&ctx->ww_ctx); | |
6237 | state = drm_atomic_state_alloc(dev); | |
6238 | if (WARN_ON(!state)) | |
6239 | return -ENOMEM; | |
6240 | ||
6241 | state->acquire_ctx = ctx; | |
6242 | state->allow_modeset = true; | |
6243 | ||
6244 | for_each_crtc(dev, crtc) { | |
6245 | struct drm_crtc_state *crtc_state = | |
6246 | drm_atomic_get_crtc_state(state, crtc); | |
6b72d486 | 6247 | |
70e0bd74 ML |
6248 | ret = PTR_ERR_OR_ZERO(crtc_state); |
6249 | if (ret) | |
6250 | goto free; | |
6251 | ||
6252 | if (!crtc_state->active) | |
6253 | continue; | |
6254 | ||
6255 | crtc_state->active = false; | |
6256 | crtc_mask |= 1 << drm_crtc_index(crtc); | |
6257 | } | |
6258 | ||
6259 | if (crtc_mask) { | |
74c090b1 | 6260 | ret = drm_atomic_commit(state); |
70e0bd74 ML |
6261 | |
6262 | if (!ret) { | |
6263 | for_each_crtc(dev, crtc) | |
6264 | if (crtc_mask & (1 << drm_crtc_index(crtc))) | |
6265 | crtc->state->active = true; | |
6266 | ||
6267 | return ret; | |
6268 | } | |
6269 | } | |
6270 | ||
6271 | free: | |
6272 | if (ret) | |
6273 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); | |
6274 | drm_atomic_state_free(state); | |
6275 | return ret; | |
ee7b9f93 JB |
6276 | } |
6277 | ||
ea5b213a | 6278 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 6279 | { |
4ef69c7a | 6280 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 6281 | |
ea5b213a CW |
6282 | drm_encoder_cleanup(encoder); |
6283 | kfree(intel_encoder); | |
7e7d76c3 JB |
6284 | } |
6285 | ||
0a91ca29 DV |
6286 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
6287 | * internal consistency). */ | |
b980514c | 6288 | static void intel_connector_check_state(struct intel_connector *connector) |
79e53945 | 6289 | { |
35dd3c64 ML |
6290 | struct drm_crtc *crtc = connector->base.state->crtc; |
6291 | ||
6292 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
6293 | connector->base.base.id, | |
6294 | connector->base.name); | |
6295 | ||
0a91ca29 | 6296 | if (connector->get_hw_state(connector)) { |
35dd3c64 ML |
6297 | struct drm_encoder *encoder = &connector->encoder->base; |
6298 | struct drm_connector_state *conn_state = connector->base.state; | |
0a91ca29 | 6299 | |
35dd3c64 ML |
6300 | I915_STATE_WARN(!crtc, |
6301 | "connector enabled without attached crtc\n"); | |
0a91ca29 | 6302 | |
35dd3c64 ML |
6303 | if (!crtc) |
6304 | return; | |
6305 | ||
6306 | I915_STATE_WARN(!crtc->state->active, | |
6307 | "connector is active, but attached crtc isn't\n"); | |
6308 | ||
6309 | if (!encoder) | |
6310 | return; | |
6311 | ||
6312 | I915_STATE_WARN(conn_state->best_encoder != encoder, | |
6313 | "atomic encoder doesn't match attached encoder\n"); | |
6314 | ||
6315 | I915_STATE_WARN(conn_state->crtc != encoder->crtc, | |
6316 | "attached encoder crtc differs from connector crtc\n"); | |
6317 | } else { | |
4d688a2a ML |
6318 | I915_STATE_WARN(crtc && crtc->state->active, |
6319 | "attached crtc is active, but connector isn't\n"); | |
35dd3c64 ML |
6320 | I915_STATE_WARN(!crtc && connector->base.state->best_encoder, |
6321 | "best encoder set without crtc!\n"); | |
0a91ca29 | 6322 | } |
79e53945 JB |
6323 | } |
6324 | ||
08d9bc92 ACO |
6325 | int intel_connector_init(struct intel_connector *connector) |
6326 | { | |
6327 | struct drm_connector_state *connector_state; | |
6328 | ||
6329 | connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL); | |
6330 | if (!connector_state) | |
6331 | return -ENOMEM; | |
6332 | ||
6333 | connector->base.state = connector_state; | |
6334 | return 0; | |
6335 | } | |
6336 | ||
6337 | struct intel_connector *intel_connector_alloc(void) | |
6338 | { | |
6339 | struct intel_connector *connector; | |
6340 | ||
6341 | connector = kzalloc(sizeof *connector, GFP_KERNEL); | |
6342 | if (!connector) | |
6343 | return NULL; | |
6344 | ||
6345 | if (intel_connector_init(connector) < 0) { | |
6346 | kfree(connector); | |
6347 | return NULL; | |
6348 | } | |
6349 | ||
6350 | return connector; | |
6351 | } | |
6352 | ||
f0947c37 DV |
6353 | /* Simple connector->get_hw_state implementation for encoders that support only |
6354 | * one connector and no cloning and hence the encoder state determines the state | |
6355 | * of the connector. */ | |
6356 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 6357 | { |
24929352 | 6358 | enum pipe pipe = 0; |
f0947c37 | 6359 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 6360 | |
f0947c37 | 6361 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
6362 | } |
6363 | ||
6d293983 | 6364 | static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) |
d272ddfa | 6365 | { |
6d293983 ACO |
6366 | if (crtc_state->base.enable && crtc_state->has_pch_encoder) |
6367 | return crtc_state->fdi_lanes; | |
d272ddfa VS |
6368 | |
6369 | return 0; | |
6370 | } | |
6371 | ||
6d293983 | 6372 | static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5cec258b | 6373 | struct intel_crtc_state *pipe_config) |
1857e1da | 6374 | { |
6d293983 ACO |
6375 | struct drm_atomic_state *state = pipe_config->base.state; |
6376 | struct intel_crtc *other_crtc; | |
6377 | struct intel_crtc_state *other_crtc_state; | |
6378 | ||
1857e1da DV |
6379 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
6380 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6381 | if (pipe_config->fdi_lanes > 4) { | |
6382 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
6383 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6384 | return -EINVAL; |
1857e1da DV |
6385 | } |
6386 | ||
bafb6553 | 6387 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1857e1da DV |
6388 | if (pipe_config->fdi_lanes > 2) { |
6389 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
6390 | pipe_config->fdi_lanes); | |
6d293983 | 6391 | return -EINVAL; |
1857e1da | 6392 | } else { |
6d293983 | 6393 | return 0; |
1857e1da DV |
6394 | } |
6395 | } | |
6396 | ||
6397 | if (INTEL_INFO(dev)->num_pipes == 2) | |
6d293983 | 6398 | return 0; |
1857e1da DV |
6399 | |
6400 | /* Ivybridge 3 pipe is really complicated */ | |
6401 | switch (pipe) { | |
6402 | case PIPE_A: | |
6d293983 | 6403 | return 0; |
1857e1da | 6404 | case PIPE_B: |
6d293983 ACO |
6405 | if (pipe_config->fdi_lanes <= 2) |
6406 | return 0; | |
6407 | ||
6408 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C)); | |
6409 | other_crtc_state = | |
6410 | intel_atomic_get_crtc_state(state, other_crtc); | |
6411 | if (IS_ERR(other_crtc_state)) | |
6412 | return PTR_ERR(other_crtc_state); | |
6413 | ||
6414 | if (pipe_required_fdi_lanes(other_crtc_state) > 0) { | |
1857e1da DV |
6415 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
6416 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6417 | return -EINVAL; |
1857e1da | 6418 | } |
6d293983 | 6419 | return 0; |
1857e1da | 6420 | case PIPE_C: |
251cc67c VS |
6421 | if (pipe_config->fdi_lanes > 2) { |
6422 | DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", | |
6423 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6424 | return -EINVAL; |
251cc67c | 6425 | } |
6d293983 ACO |
6426 | |
6427 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B)); | |
6428 | other_crtc_state = | |
6429 | intel_atomic_get_crtc_state(state, other_crtc); | |
6430 | if (IS_ERR(other_crtc_state)) | |
6431 | return PTR_ERR(other_crtc_state); | |
6432 | ||
6433 | if (pipe_required_fdi_lanes(other_crtc_state) > 2) { | |
1857e1da | 6434 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
6d293983 | 6435 | return -EINVAL; |
1857e1da | 6436 | } |
6d293983 | 6437 | return 0; |
1857e1da DV |
6438 | default: |
6439 | BUG(); | |
6440 | } | |
6441 | } | |
6442 | ||
e29c22c0 DV |
6443 | #define RETRY 1 |
6444 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5cec258b | 6445 | struct intel_crtc_state *pipe_config) |
877d48d5 | 6446 | { |
1857e1da | 6447 | struct drm_device *dev = intel_crtc->base.dev; |
2d112de7 | 6448 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
6d293983 ACO |
6449 | int lane, link_bw, fdi_dotclock, ret; |
6450 | bool needs_recompute = false; | |
877d48d5 | 6451 | |
e29c22c0 | 6452 | retry: |
877d48d5 DV |
6453 | /* FDI is a binary signal running at ~2.7GHz, encoding |
6454 | * each output octet as 10 bits. The actual frequency | |
6455 | * is stored as a divider into a 100MHz clock, and the | |
6456 | * mode pixel clock is stored in units of 1KHz. | |
6457 | * Hence the bw of each lane in terms of the mode signal | |
6458 | * is: | |
6459 | */ | |
6460 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
6461 | ||
241bfc38 | 6462 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 6463 | |
2bd89a07 | 6464 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
6465 | pipe_config->pipe_bpp); |
6466 | ||
6467 | pipe_config->fdi_lanes = lane; | |
6468 | ||
2bd89a07 | 6469 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 6470 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 6471 | |
6d293983 ACO |
6472 | ret = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
6473 | intel_crtc->pipe, pipe_config); | |
6474 | if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { | |
e29c22c0 DV |
6475 | pipe_config->pipe_bpp -= 2*3; |
6476 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
6477 | pipe_config->pipe_bpp); | |
6478 | needs_recompute = true; | |
6479 | pipe_config->bw_constrained = true; | |
6480 | ||
6481 | goto retry; | |
6482 | } | |
6483 | ||
6484 | if (needs_recompute) | |
6485 | return RETRY; | |
6486 | ||
6d293983 | 6487 | return ret; |
877d48d5 DV |
6488 | } |
6489 | ||
8cfb3407 VS |
6490 | static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, |
6491 | struct intel_crtc_state *pipe_config) | |
6492 | { | |
6493 | if (pipe_config->pipe_bpp > 24) | |
6494 | return false; | |
6495 | ||
6496 | /* HSW can handle pixel rate up to cdclk? */ | |
6497 | if (IS_HASWELL(dev_priv->dev)) | |
6498 | return true; | |
6499 | ||
6500 | /* | |
b432e5cf VS |
6501 | * We compare against max which means we must take |
6502 | * the increased cdclk requirement into account when | |
6503 | * calculating the new cdclk. | |
6504 | * | |
6505 | * Should measure whether using a lower cdclk w/o IPS | |
8cfb3407 VS |
6506 | */ |
6507 | return ilk_pipe_pixel_rate(pipe_config) <= | |
6508 | dev_priv->max_cdclk_freq * 95 / 100; | |
6509 | } | |
6510 | ||
42db64ef | 6511 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
5cec258b | 6512 | struct intel_crtc_state *pipe_config) |
42db64ef | 6513 | { |
8cfb3407 VS |
6514 | struct drm_device *dev = crtc->base.dev; |
6515 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6516 | ||
d330a953 | 6517 | pipe_config->ips_enabled = i915.enable_ips && |
8cfb3407 VS |
6518 | hsw_crtc_supports_ips(crtc) && |
6519 | pipe_config_supports_ips(dev_priv, pipe_config); | |
42db64ef PZ |
6520 | } |
6521 | ||
a43f6e0f | 6522 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
5cec258b | 6523 | struct intel_crtc_state *pipe_config) |
79e53945 | 6524 | { |
a43f6e0f | 6525 | struct drm_device *dev = crtc->base.dev; |
8bd31e67 | 6526 | struct drm_i915_private *dev_priv = dev->dev_private; |
2d112de7 | 6527 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
89749350 | 6528 | |
ad3a4479 | 6529 | /* FIXME should check pixel clock limits on all platforms */ |
cf532bb2 | 6530 | if (INTEL_INFO(dev)->gen < 4) { |
44913155 | 6531 | int clock_limit = dev_priv->max_cdclk_freq; |
cf532bb2 VS |
6532 | |
6533 | /* | |
6534 | * Enable pixel doubling when the dot clock | |
6535 | * is > 90% of the (display) core speed. | |
6536 | * | |
b397c96b VS |
6537 | * GDG double wide on either pipe, |
6538 | * otherwise pipe A only. | |
cf532bb2 | 6539 | */ |
b397c96b | 6540 | if ((crtc->pipe == PIPE_A || IS_I915G(dev)) && |
241bfc38 | 6541 | adjusted_mode->crtc_clock > clock_limit * 9 / 10) { |
ad3a4479 | 6542 | clock_limit *= 2; |
cf532bb2 | 6543 | pipe_config->double_wide = true; |
ad3a4479 VS |
6544 | } |
6545 | ||
241bfc38 | 6546 | if (adjusted_mode->crtc_clock > clock_limit * 9 / 10) |
e29c22c0 | 6547 | return -EINVAL; |
2c07245f | 6548 | } |
89749350 | 6549 | |
1d1d0e27 VS |
6550 | /* |
6551 | * Pipe horizontal size must be even in: | |
6552 | * - DVO ganged mode | |
6553 | * - LVDS dual channel mode | |
6554 | * - Double wide pipe | |
6555 | */ | |
a93e255f | 6556 | if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) && |
1d1d0e27 VS |
6557 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) |
6558 | pipe_config->pipe_src_w &= ~1; | |
6559 | ||
8693a824 DL |
6560 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
6561 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
6562 | */ |
6563 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
6564 | adjusted_mode->hsync_start == adjusted_mode->hdisplay) | |
e29c22c0 | 6565 | return -EINVAL; |
44f46b42 | 6566 | |
f5adf94e | 6567 | if (HAS_IPS(dev)) |
a43f6e0f DV |
6568 | hsw_compute_ips_config(crtc, pipe_config); |
6569 | ||
877d48d5 | 6570 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 6571 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 6572 | |
cf5a15be | 6573 | return 0; |
79e53945 JB |
6574 | } |
6575 | ||
1652d19e VS |
6576 | static int skylake_get_display_clock_speed(struct drm_device *dev) |
6577 | { | |
6578 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6579 | uint32_t lcpll1 = I915_READ(LCPLL1_CTL); | |
6580 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
6581 | uint32_t linkrate; | |
6582 | ||
414355a7 | 6583 | if (!(lcpll1 & LCPLL_PLL_ENABLE)) |
1652d19e | 6584 | return 24000; /* 24MHz is the cd freq with NSSC ref */ |
1652d19e VS |
6585 | |
6586 | if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540) | |
6587 | return 540000; | |
6588 | ||
6589 | linkrate = (I915_READ(DPLL_CTRL1) & | |
71cd8423 | 6590 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1; |
1652d19e | 6591 | |
71cd8423 DL |
6592 | if (linkrate == DPLL_CTRL1_LINK_RATE_2160 || |
6593 | linkrate == DPLL_CTRL1_LINK_RATE_1080) { | |
1652d19e VS |
6594 | /* vco 8640 */ |
6595 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
6596 | case CDCLK_FREQ_450_432: | |
6597 | return 432000; | |
6598 | case CDCLK_FREQ_337_308: | |
6599 | return 308570; | |
6600 | case CDCLK_FREQ_675_617: | |
6601 | return 617140; | |
6602 | default: | |
6603 | WARN(1, "Unknown cd freq selection\n"); | |
6604 | } | |
6605 | } else { | |
6606 | /* vco 8100 */ | |
6607 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
6608 | case CDCLK_FREQ_450_432: | |
6609 | return 450000; | |
6610 | case CDCLK_FREQ_337_308: | |
6611 | return 337500; | |
6612 | case CDCLK_FREQ_675_617: | |
6613 | return 675000; | |
6614 | default: | |
6615 | WARN(1, "Unknown cd freq selection\n"); | |
6616 | } | |
6617 | } | |
6618 | ||
6619 | /* error case, do as if DPLL0 isn't enabled */ | |
6620 | return 24000; | |
6621 | } | |
6622 | ||
acd3f3d3 BP |
6623 | static int broxton_get_display_clock_speed(struct drm_device *dev) |
6624 | { | |
6625 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6626 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
6627 | uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK; | |
6628 | uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE); | |
6629 | int cdclk; | |
6630 | ||
6631 | if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE)) | |
6632 | return 19200; | |
6633 | ||
6634 | cdclk = 19200 * pll_ratio / 2; | |
6635 | ||
6636 | switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) { | |
6637 | case BXT_CDCLK_CD2X_DIV_SEL_1: | |
6638 | return cdclk; /* 576MHz or 624MHz */ | |
6639 | case BXT_CDCLK_CD2X_DIV_SEL_1_5: | |
6640 | return cdclk * 2 / 3; /* 384MHz */ | |
6641 | case BXT_CDCLK_CD2X_DIV_SEL_2: | |
6642 | return cdclk / 2; /* 288MHz */ | |
6643 | case BXT_CDCLK_CD2X_DIV_SEL_4: | |
6644 | return cdclk / 4; /* 144MHz */ | |
6645 | } | |
6646 | ||
6647 | /* error case, do as if DE PLL isn't enabled */ | |
6648 | return 19200; | |
6649 | } | |
6650 | ||
1652d19e VS |
6651 | static int broadwell_get_display_clock_speed(struct drm_device *dev) |
6652 | { | |
6653 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6654 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6655 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6656 | ||
6657 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6658 | return 800000; | |
6659 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6660 | return 450000; | |
6661 | else if (freq == LCPLL_CLK_FREQ_450) | |
6662 | return 450000; | |
6663 | else if (freq == LCPLL_CLK_FREQ_54O_BDW) | |
6664 | return 540000; | |
6665 | else if (freq == LCPLL_CLK_FREQ_337_5_BDW) | |
6666 | return 337500; | |
6667 | else | |
6668 | return 675000; | |
6669 | } | |
6670 | ||
6671 | static int haswell_get_display_clock_speed(struct drm_device *dev) | |
6672 | { | |
6673 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6674 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6675 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6676 | ||
6677 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6678 | return 800000; | |
6679 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6680 | return 450000; | |
6681 | else if (freq == LCPLL_CLK_FREQ_450) | |
6682 | return 450000; | |
6683 | else if (IS_HSW_ULT(dev)) | |
6684 | return 337500; | |
6685 | else | |
6686 | return 540000; | |
79e53945 JB |
6687 | } |
6688 | ||
25eb05fc JB |
6689 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
6690 | { | |
d197b7d3 | 6691 | struct drm_i915_private *dev_priv = dev->dev_private; |
d197b7d3 VS |
6692 | u32 val; |
6693 | int divider; | |
6694 | ||
6bcda4f0 VS |
6695 | if (dev_priv->hpll_freq == 0) |
6696 | dev_priv->hpll_freq = valleyview_get_vco(dev_priv); | |
6697 | ||
a580516d | 6698 | mutex_lock(&dev_priv->sb_lock); |
d197b7d3 | 6699 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); |
a580516d | 6700 | mutex_unlock(&dev_priv->sb_lock); |
d197b7d3 VS |
6701 | |
6702 | divider = val & DISPLAY_FREQUENCY_VALUES; | |
6703 | ||
7d007f40 VS |
6704 | WARN((val & DISPLAY_FREQUENCY_STATUS) != |
6705 | (divider << DISPLAY_FREQUENCY_STATUS_SHIFT), | |
6706 | "cdclk change in progress\n"); | |
6707 | ||
6bcda4f0 | 6708 | return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1); |
25eb05fc JB |
6709 | } |
6710 | ||
b37a6434 VS |
6711 | static int ilk_get_display_clock_speed(struct drm_device *dev) |
6712 | { | |
6713 | return 450000; | |
6714 | } | |
6715 | ||
e70236a8 JB |
6716 | static int i945_get_display_clock_speed(struct drm_device *dev) |
6717 | { | |
6718 | return 400000; | |
6719 | } | |
79e53945 | 6720 | |
e70236a8 | 6721 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 6722 | { |
e907f170 | 6723 | return 333333; |
e70236a8 | 6724 | } |
79e53945 | 6725 | |
e70236a8 JB |
6726 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
6727 | { | |
6728 | return 200000; | |
6729 | } | |
79e53945 | 6730 | |
257a7ffc DV |
6731 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
6732 | { | |
6733 | u16 gcfgc = 0; | |
6734 | ||
6735 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
6736 | ||
6737 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6738 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
e907f170 | 6739 | return 266667; |
257a7ffc | 6740 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: |
e907f170 | 6741 | return 333333; |
257a7ffc | 6742 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: |
e907f170 | 6743 | return 444444; |
257a7ffc DV |
6744 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: |
6745 | return 200000; | |
6746 | default: | |
6747 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
6748 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
e907f170 | 6749 | return 133333; |
257a7ffc | 6750 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: |
e907f170 | 6751 | return 166667; |
257a7ffc DV |
6752 | } |
6753 | } | |
6754 | ||
e70236a8 JB |
6755 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
6756 | { | |
6757 | u16 gcfgc = 0; | |
79e53945 | 6758 | |
e70236a8 JB |
6759 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
6760 | ||
6761 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
e907f170 | 6762 | return 133333; |
e70236a8 JB |
6763 | else { |
6764 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6765 | case GC_DISPLAY_CLOCK_333_MHZ: | |
e907f170 | 6766 | return 333333; |
e70236a8 JB |
6767 | default: |
6768 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
6769 | return 190000; | |
79e53945 | 6770 | } |
e70236a8 JB |
6771 | } |
6772 | } | |
6773 | ||
6774 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
6775 | { | |
e907f170 | 6776 | return 266667; |
e70236a8 JB |
6777 | } |
6778 | ||
1b1d2716 | 6779 | static int i85x_get_display_clock_speed(struct drm_device *dev) |
e70236a8 JB |
6780 | { |
6781 | u16 hpllcc = 0; | |
1b1d2716 | 6782 | |
65cd2b3f VS |
6783 | /* |
6784 | * 852GM/852GMV only supports 133 MHz and the HPLLCC | |
6785 | * encoding is different :( | |
6786 | * FIXME is this the right way to detect 852GM/852GMV? | |
6787 | */ | |
6788 | if (dev->pdev->revision == 0x1) | |
6789 | return 133333; | |
6790 | ||
1b1d2716 VS |
6791 | pci_bus_read_config_word(dev->pdev->bus, |
6792 | PCI_DEVFN(0, 3), HPLLCC, &hpllcc); | |
6793 | ||
e70236a8 JB |
6794 | /* Assume that the hardware is in the high speed state. This |
6795 | * should be the default. | |
6796 | */ | |
6797 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
6798 | case GC_CLOCK_133_200: | |
1b1d2716 | 6799 | case GC_CLOCK_133_200_2: |
e70236a8 JB |
6800 | case GC_CLOCK_100_200: |
6801 | return 200000; | |
6802 | case GC_CLOCK_166_250: | |
6803 | return 250000; | |
6804 | case GC_CLOCK_100_133: | |
e907f170 | 6805 | return 133333; |
1b1d2716 VS |
6806 | case GC_CLOCK_133_266: |
6807 | case GC_CLOCK_133_266_2: | |
6808 | case GC_CLOCK_166_266: | |
6809 | return 266667; | |
e70236a8 | 6810 | } |
79e53945 | 6811 | |
e70236a8 JB |
6812 | /* Shouldn't happen */ |
6813 | return 0; | |
6814 | } | |
79e53945 | 6815 | |
e70236a8 JB |
6816 | static int i830_get_display_clock_speed(struct drm_device *dev) |
6817 | { | |
e907f170 | 6818 | return 133333; |
79e53945 JB |
6819 | } |
6820 | ||
34edce2f VS |
6821 | static unsigned int intel_hpll_vco(struct drm_device *dev) |
6822 | { | |
6823 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6824 | static const unsigned int blb_vco[8] = { | |
6825 | [0] = 3200000, | |
6826 | [1] = 4000000, | |
6827 | [2] = 5333333, | |
6828 | [3] = 4800000, | |
6829 | [4] = 6400000, | |
6830 | }; | |
6831 | static const unsigned int pnv_vco[8] = { | |
6832 | [0] = 3200000, | |
6833 | [1] = 4000000, | |
6834 | [2] = 5333333, | |
6835 | [3] = 4800000, | |
6836 | [4] = 2666667, | |
6837 | }; | |
6838 | static const unsigned int cl_vco[8] = { | |
6839 | [0] = 3200000, | |
6840 | [1] = 4000000, | |
6841 | [2] = 5333333, | |
6842 | [3] = 6400000, | |
6843 | [4] = 3333333, | |
6844 | [5] = 3566667, | |
6845 | [6] = 4266667, | |
6846 | }; | |
6847 | static const unsigned int elk_vco[8] = { | |
6848 | [0] = 3200000, | |
6849 | [1] = 4000000, | |
6850 | [2] = 5333333, | |
6851 | [3] = 4800000, | |
6852 | }; | |
6853 | static const unsigned int ctg_vco[8] = { | |
6854 | [0] = 3200000, | |
6855 | [1] = 4000000, | |
6856 | [2] = 5333333, | |
6857 | [3] = 6400000, | |
6858 | [4] = 2666667, | |
6859 | [5] = 4266667, | |
6860 | }; | |
6861 | const unsigned int *vco_table; | |
6862 | unsigned int vco; | |
6863 | uint8_t tmp = 0; | |
6864 | ||
6865 | /* FIXME other chipsets? */ | |
6866 | if (IS_GM45(dev)) | |
6867 | vco_table = ctg_vco; | |
6868 | else if (IS_G4X(dev)) | |
6869 | vco_table = elk_vco; | |
6870 | else if (IS_CRESTLINE(dev)) | |
6871 | vco_table = cl_vco; | |
6872 | else if (IS_PINEVIEW(dev)) | |
6873 | vco_table = pnv_vco; | |
6874 | else if (IS_G33(dev)) | |
6875 | vco_table = blb_vco; | |
6876 | else | |
6877 | return 0; | |
6878 | ||
6879 | tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO); | |
6880 | ||
6881 | vco = vco_table[tmp & 0x7]; | |
6882 | if (vco == 0) | |
6883 | DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp); | |
6884 | else | |
6885 | DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco); | |
6886 | ||
6887 | return vco; | |
6888 | } | |
6889 | ||
6890 | static int gm45_get_display_clock_speed(struct drm_device *dev) | |
6891 | { | |
6892 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
6893 | uint16_t tmp = 0; | |
6894 | ||
6895 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
6896 | ||
6897 | cdclk_sel = (tmp >> 12) & 0x1; | |
6898 | ||
6899 | switch (vco) { | |
6900 | case 2666667: | |
6901 | case 4000000: | |
6902 | case 5333333: | |
6903 | return cdclk_sel ? 333333 : 222222; | |
6904 | case 3200000: | |
6905 | return cdclk_sel ? 320000 : 228571; | |
6906 | default: | |
6907 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp); | |
6908 | return 222222; | |
6909 | } | |
6910 | } | |
6911 | ||
6912 | static int i965gm_get_display_clock_speed(struct drm_device *dev) | |
6913 | { | |
6914 | static const uint8_t div_3200[] = { 16, 10, 8 }; | |
6915 | static const uint8_t div_4000[] = { 20, 12, 10 }; | |
6916 | static const uint8_t div_5333[] = { 24, 16, 14 }; | |
6917 | const uint8_t *div_table; | |
6918 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
6919 | uint16_t tmp = 0; | |
6920 | ||
6921 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
6922 | ||
6923 | cdclk_sel = ((tmp >> 8) & 0x1f) - 1; | |
6924 | ||
6925 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
6926 | goto fail; | |
6927 | ||
6928 | switch (vco) { | |
6929 | case 3200000: | |
6930 | div_table = div_3200; | |
6931 | break; | |
6932 | case 4000000: | |
6933 | div_table = div_4000; | |
6934 | break; | |
6935 | case 5333333: | |
6936 | div_table = div_5333; | |
6937 | break; | |
6938 | default: | |
6939 | goto fail; | |
6940 | } | |
6941 | ||
6942 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
6943 | ||
caf4e252 | 6944 | fail: |
34edce2f VS |
6945 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp); |
6946 | return 200000; | |
6947 | } | |
6948 | ||
6949 | static int g33_get_display_clock_speed(struct drm_device *dev) | |
6950 | { | |
6951 | static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 }; | |
6952 | static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 }; | |
6953 | static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 }; | |
6954 | static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 }; | |
6955 | const uint8_t *div_table; | |
6956 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
6957 | uint16_t tmp = 0; | |
6958 | ||
6959 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
6960 | ||
6961 | cdclk_sel = (tmp >> 4) & 0x7; | |
6962 | ||
6963 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
6964 | goto fail; | |
6965 | ||
6966 | switch (vco) { | |
6967 | case 3200000: | |
6968 | div_table = div_3200; | |
6969 | break; | |
6970 | case 4000000: | |
6971 | div_table = div_4000; | |
6972 | break; | |
6973 | case 4800000: | |
6974 | div_table = div_4800; | |
6975 | break; | |
6976 | case 5333333: | |
6977 | div_table = div_5333; | |
6978 | break; | |
6979 | default: | |
6980 | goto fail; | |
6981 | } | |
6982 | ||
6983 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
6984 | ||
caf4e252 | 6985 | fail: |
34edce2f VS |
6986 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp); |
6987 | return 190476; | |
6988 | } | |
6989 | ||
2c07245f | 6990 | static void |
a65851af | 6991 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 6992 | { |
a65851af VS |
6993 | while (*num > DATA_LINK_M_N_MASK || |
6994 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
6995 | *num >>= 1; |
6996 | *den >>= 1; | |
6997 | } | |
6998 | } | |
6999 | ||
a65851af VS |
7000 | static void compute_m_n(unsigned int m, unsigned int n, |
7001 | uint32_t *ret_m, uint32_t *ret_n) | |
7002 | { | |
7003 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
7004 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
7005 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
7006 | } | |
7007 | ||
e69d0bc1 DV |
7008 | void |
7009 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
7010 | int pixel_clock, int link_clock, | |
7011 | struct intel_link_m_n *m_n) | |
2c07245f | 7012 | { |
e69d0bc1 | 7013 | m_n->tu = 64; |
a65851af VS |
7014 | |
7015 | compute_m_n(bits_per_pixel * pixel_clock, | |
7016 | link_clock * nlanes * 8, | |
7017 | &m_n->gmch_m, &m_n->gmch_n); | |
7018 | ||
7019 | compute_m_n(pixel_clock, link_clock, | |
7020 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
7021 | } |
7022 | ||
a7615030 CW |
7023 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
7024 | { | |
d330a953 JN |
7025 | if (i915.panel_use_ssc >= 0) |
7026 | return i915.panel_use_ssc != 0; | |
41aa3448 | 7027 | return dev_priv->vbt.lvds_use_ssc |
435793df | 7028 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
7029 | } |
7030 | ||
a93e255f ACO |
7031 | static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, |
7032 | int num_connectors) | |
c65d77d8 | 7033 | { |
a93e255f | 7034 | struct drm_device *dev = crtc_state->base.crtc->dev; |
c65d77d8 JB |
7035 | struct drm_i915_private *dev_priv = dev->dev_private; |
7036 | int refclk; | |
7037 | ||
a93e255f ACO |
7038 | WARN_ON(!crtc_state->base.state); |
7039 | ||
5ab7b0b7 | 7040 | if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) { |
9a0ea498 | 7041 | refclk = 100000; |
a93e255f | 7042 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
c65d77d8 | 7043 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
e91e941b VS |
7044 | refclk = dev_priv->vbt.lvds_ssc_freq; |
7045 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
c65d77d8 JB |
7046 | } else if (!IS_GEN2(dev)) { |
7047 | refclk = 96000; | |
7048 | } else { | |
7049 | refclk = 48000; | |
7050 | } | |
7051 | ||
7052 | return refclk; | |
7053 | } | |
7054 | ||
7429e9d4 | 7055 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 7056 | { |
7df00d7a | 7057 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 7058 | } |
f47709a9 | 7059 | |
7429e9d4 DV |
7060 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
7061 | { | |
7062 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
7063 | } |
7064 | ||
f47709a9 | 7065 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
190f68c5 | 7066 | struct intel_crtc_state *crtc_state, |
a7516a05 JB |
7067 | intel_clock_t *reduced_clock) |
7068 | { | |
f47709a9 | 7069 | struct drm_device *dev = crtc->base.dev; |
a7516a05 JB |
7070 | u32 fp, fp2 = 0; |
7071 | ||
7072 | if (IS_PINEVIEW(dev)) { | |
190f68c5 | 7073 | fp = pnv_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7074 | if (reduced_clock) |
7429e9d4 | 7075 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 7076 | } else { |
190f68c5 | 7077 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7078 | if (reduced_clock) |
7429e9d4 | 7079 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
7080 | } |
7081 | ||
190f68c5 | 7082 | crtc_state->dpll_hw_state.fp0 = fp; |
a7516a05 | 7083 | |
f47709a9 | 7084 | crtc->lowfreq_avail = false; |
a93e255f | 7085 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ab585dea | 7086 | reduced_clock) { |
190f68c5 | 7087 | crtc_state->dpll_hw_state.fp1 = fp2; |
f47709a9 | 7088 | crtc->lowfreq_avail = true; |
a7516a05 | 7089 | } else { |
190f68c5 | 7090 | crtc_state->dpll_hw_state.fp1 = fp; |
a7516a05 JB |
7091 | } |
7092 | } | |
7093 | ||
5e69f97f CML |
7094 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
7095 | pipe) | |
89b667f8 JB |
7096 | { |
7097 | u32 reg_val; | |
7098 | ||
7099 | /* | |
7100 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
7101 | * and set it to a reasonable value instead. | |
7102 | */ | |
ab3c759a | 7103 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
7104 | reg_val &= 0xffffff00; |
7105 | reg_val |= 0x00000030; | |
ab3c759a | 7106 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7107 | |
ab3c759a | 7108 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7109 | reg_val &= 0x8cffffff; |
7110 | reg_val = 0x8c000000; | |
ab3c759a | 7111 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 7112 | |
ab3c759a | 7113 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 7114 | reg_val &= 0xffffff00; |
ab3c759a | 7115 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7116 | |
ab3c759a | 7117 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7118 | reg_val &= 0x00ffffff; |
7119 | reg_val |= 0xb0000000; | |
ab3c759a | 7120 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
7121 | } |
7122 | ||
b551842d DV |
7123 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
7124 | struct intel_link_m_n *m_n) | |
7125 | { | |
7126 | struct drm_device *dev = crtc->base.dev; | |
7127 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7128 | int pipe = crtc->pipe; | |
7129 | ||
e3b95f1e DV |
7130 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7131 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
7132 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
7133 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
7134 | } |
7135 | ||
7136 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
f769cd24 VK |
7137 | struct intel_link_m_n *m_n, |
7138 | struct intel_link_m_n *m2_n2) | |
b551842d DV |
7139 | { |
7140 | struct drm_device *dev = crtc->base.dev; | |
7141 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7142 | int pipe = crtc->pipe; | |
6e3c9717 | 7143 | enum transcoder transcoder = crtc->config->cpu_transcoder; |
b551842d DV |
7144 | |
7145 | if (INTEL_INFO(dev)->gen >= 5) { | |
7146 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
7147 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
7148 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
7149 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
f769cd24 VK |
7150 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
7151 | * for gen < 8) and if DRRS is supported (to make sure the | |
7152 | * registers are not unnecessarily accessed). | |
7153 | */ | |
44395bfe | 7154 | if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) && |
6e3c9717 | 7155 | crtc->config->has_drrs) { |
f769cd24 VK |
7156 | I915_WRITE(PIPE_DATA_M2(transcoder), |
7157 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
7158 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
7159 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
7160 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
7161 | } | |
b551842d | 7162 | } else { |
e3b95f1e DV |
7163 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7164 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
7165 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
7166 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
7167 | } |
7168 | } | |
7169 | ||
fe3cd48d | 7170 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) |
03afc4a2 | 7171 | { |
fe3cd48d R |
7172 | struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; |
7173 | ||
7174 | if (m_n == M1_N1) { | |
7175 | dp_m_n = &crtc->config->dp_m_n; | |
7176 | dp_m2_n2 = &crtc->config->dp_m2_n2; | |
7177 | } else if (m_n == M2_N2) { | |
7178 | ||
7179 | /* | |
7180 | * M2_N2 registers are not supported. Hence m2_n2 divider value | |
7181 | * needs to be programmed into M1_N1. | |
7182 | */ | |
7183 | dp_m_n = &crtc->config->dp_m2_n2; | |
7184 | } else { | |
7185 | DRM_ERROR("Unsupported divider value\n"); | |
7186 | return; | |
7187 | } | |
7188 | ||
6e3c9717 ACO |
7189 | if (crtc->config->has_pch_encoder) |
7190 | intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); | |
03afc4a2 | 7191 | else |
fe3cd48d | 7192 | intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); |
03afc4a2 DV |
7193 | } |
7194 | ||
251ac862 DV |
7195 | static void vlv_compute_dpll(struct intel_crtc *crtc, |
7196 | struct intel_crtc_state *pipe_config) | |
bdd4b6a6 DV |
7197 | { |
7198 | u32 dpll, dpll_md; | |
7199 | ||
7200 | /* | |
7201 | * Enable DPIO clock input. We should never disable the reference | |
7202 | * clock for pipe B, since VGA hotplug / manual detection depends | |
7203 | * on it. | |
7204 | */ | |
60bfe44f VS |
7205 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV | |
7206 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV; | |
bdd4b6a6 DV |
7207 | /* We should never disable this, set it here for state tracking */ |
7208 | if (crtc->pipe == PIPE_B) | |
7209 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
7210 | dpll |= DPLL_VCO_ENABLE; | |
d288f65f | 7211 | pipe_config->dpll_hw_state.dpll = dpll; |
bdd4b6a6 | 7212 | |
d288f65f | 7213 | dpll_md = (pipe_config->pixel_multiplier - 1) |
bdd4b6a6 | 7214 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
d288f65f | 7215 | pipe_config->dpll_hw_state.dpll_md = dpll_md; |
bdd4b6a6 DV |
7216 | } |
7217 | ||
d288f65f | 7218 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7219 | const struct intel_crtc_state *pipe_config) |
a0c4da24 | 7220 | { |
f47709a9 | 7221 | struct drm_device *dev = crtc->base.dev; |
a0c4da24 | 7222 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 7223 | int pipe = crtc->pipe; |
bdd4b6a6 | 7224 | u32 mdiv; |
a0c4da24 | 7225 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 7226 | u32 coreclk, reg_val; |
a0c4da24 | 7227 | |
a580516d | 7228 | mutex_lock(&dev_priv->sb_lock); |
09153000 | 7229 | |
d288f65f VS |
7230 | bestn = pipe_config->dpll.n; |
7231 | bestm1 = pipe_config->dpll.m1; | |
7232 | bestm2 = pipe_config->dpll.m2; | |
7233 | bestp1 = pipe_config->dpll.p1; | |
7234 | bestp2 = pipe_config->dpll.p2; | |
a0c4da24 | 7235 | |
89b667f8 JB |
7236 | /* See eDP HDMI DPIO driver vbios notes doc */ |
7237 | ||
7238 | /* PLL B needs special handling */ | |
bdd4b6a6 | 7239 | if (pipe == PIPE_B) |
5e69f97f | 7240 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
7241 | |
7242 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 7243 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
7244 | |
7245 | /* Disable target IRef on PLL */ | |
ab3c759a | 7246 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 7247 | reg_val &= 0x00ffffff; |
ab3c759a | 7248 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
7249 | |
7250 | /* Disable fast lock */ | |
ab3c759a | 7251 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
7252 | |
7253 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
7254 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
7255 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
7256 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 7257 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
7258 | |
7259 | /* | |
7260 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
7261 | * but we don't support that). | |
7262 | * Note: don't use the DAC post divider as it seems unstable. | |
7263 | */ | |
7264 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 7265 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7266 | |
a0c4da24 | 7267 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 7268 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7269 | |
89b667f8 | 7270 | /* Set HBR and RBR LPF coefficients */ |
d288f65f | 7271 | if (pipe_config->port_clock == 162000 || |
409ee761 ACO |
7272 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) || |
7273 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) | |
ab3c759a | 7274 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 7275 | 0x009f0003); |
89b667f8 | 7276 | else |
ab3c759a | 7277 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
7278 | 0x00d0000f); |
7279 | ||
681a8504 | 7280 | if (pipe_config->has_dp_encoder) { |
89b667f8 | 7281 | /* Use SSC source */ |
bdd4b6a6 | 7282 | if (pipe == PIPE_A) |
ab3c759a | 7283 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7284 | 0x0df40000); |
7285 | else | |
ab3c759a | 7286 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7287 | 0x0df70000); |
7288 | } else { /* HDMI or VGA */ | |
7289 | /* Use bend source */ | |
bdd4b6a6 | 7290 | if (pipe == PIPE_A) |
ab3c759a | 7291 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7292 | 0x0df70000); |
7293 | else | |
ab3c759a | 7294 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7295 | 0x0df40000); |
7296 | } | |
a0c4da24 | 7297 | |
ab3c759a | 7298 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 | 7299 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
409ee761 ACO |
7300 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
7301 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) | |
89b667f8 | 7302 | coreclk |= 0x01000000; |
ab3c759a | 7303 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 7304 | |
ab3c759a | 7305 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
a580516d | 7306 | mutex_unlock(&dev_priv->sb_lock); |
a0c4da24 JB |
7307 | } |
7308 | ||
251ac862 DV |
7309 | static void chv_compute_dpll(struct intel_crtc *crtc, |
7310 | struct intel_crtc_state *pipe_config) | |
1ae0d137 | 7311 | { |
60bfe44f VS |
7312 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | |
7313 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS | | |
1ae0d137 VS |
7314 | DPLL_VCO_ENABLE; |
7315 | if (crtc->pipe != PIPE_A) | |
d288f65f | 7316 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
1ae0d137 | 7317 | |
d288f65f VS |
7318 | pipe_config->dpll_hw_state.dpll_md = |
7319 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
1ae0d137 VS |
7320 | } |
7321 | ||
d288f65f | 7322 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7323 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
7324 | { |
7325 | struct drm_device *dev = crtc->base.dev; | |
7326 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7327 | int pipe = crtc->pipe; | |
7328 | int dpll_reg = DPLL(crtc->pipe); | |
7329 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9cbe40c1 | 7330 | u32 loopfilter, tribuf_calcntr; |
9d556c99 | 7331 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
a945ce7e | 7332 | u32 dpio_val; |
9cbe40c1 | 7333 | int vco; |
9d556c99 | 7334 | |
d288f65f VS |
7335 | bestn = pipe_config->dpll.n; |
7336 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; | |
7337 | bestm1 = pipe_config->dpll.m1; | |
7338 | bestm2 = pipe_config->dpll.m2 >> 22; | |
7339 | bestp1 = pipe_config->dpll.p1; | |
7340 | bestp2 = pipe_config->dpll.p2; | |
9cbe40c1 | 7341 | vco = pipe_config->dpll.vco; |
a945ce7e | 7342 | dpio_val = 0; |
9cbe40c1 | 7343 | loopfilter = 0; |
9d556c99 CML |
7344 | |
7345 | /* | |
7346 | * Enable Refclk and SSC | |
7347 | */ | |
a11b0703 | 7348 | I915_WRITE(dpll_reg, |
d288f65f | 7349 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); |
a11b0703 | 7350 | |
a580516d | 7351 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 | 7352 | |
9d556c99 CML |
7353 | /* p1 and p2 divider */ |
7354 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
7355 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
7356 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
7357 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
7358 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
7359 | ||
7360 | /* Feedback post-divider - m2 */ | |
7361 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
7362 | ||
7363 | /* Feedback refclk divider - n and m1 */ | |
7364 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
7365 | DPIO_CHV_M1_DIV_BY_2 | | |
7366 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
7367 | ||
7368 | /* M2 fraction division */ | |
25a25dfc | 7369 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); |
9d556c99 CML |
7370 | |
7371 | /* M2 fraction division enable */ | |
a945ce7e VP |
7372 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
7373 | dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); | |
7374 | dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); | |
7375 | if (bestm2_frac) | |
7376 | dpio_val |= DPIO_CHV_FRAC_DIV_EN; | |
7377 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); | |
9d556c99 | 7378 | |
de3a0fde VP |
7379 | /* Program digital lock detect threshold */ |
7380 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); | |
7381 | dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | | |
7382 | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); | |
7383 | dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); | |
7384 | if (!bestm2_frac) | |
7385 | dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; | |
7386 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); | |
7387 | ||
9d556c99 | 7388 | /* Loop filter */ |
9cbe40c1 VP |
7389 | if (vco == 5400000) { |
7390 | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7391 | loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); | |
7392 | loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7393 | tribuf_calcntr = 0x9; | |
7394 | } else if (vco <= 6200000) { | |
7395 | loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7396 | loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); | |
7397 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7398 | tribuf_calcntr = 0x9; | |
7399 | } else if (vco <= 6480000) { | |
7400 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7401 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7402 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7403 | tribuf_calcntr = 0x8; | |
7404 | } else { | |
7405 | /* Not supported. Apply the same limits as in the max case */ | |
7406 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7407 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7408 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7409 | tribuf_calcntr = 0; | |
7410 | } | |
9d556c99 CML |
7411 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
7412 | ||
968040b2 | 7413 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); |
9cbe40c1 VP |
7414 | dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; |
7415 | dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); | |
7416 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); | |
7417 | ||
9d556c99 CML |
7418 | /* AFC Recal */ |
7419 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
7420 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
7421 | DPIO_AFC_RECAL); | |
7422 | ||
a580516d | 7423 | mutex_unlock(&dev_priv->sb_lock); |
9d556c99 CML |
7424 | } |
7425 | ||
d288f65f VS |
7426 | /** |
7427 | * vlv_force_pll_on - forcibly enable just the PLL | |
7428 | * @dev_priv: i915 private structure | |
7429 | * @pipe: pipe PLL to enable | |
7430 | * @dpll: PLL configuration | |
7431 | * | |
7432 | * Enable the PLL for @pipe using the supplied @dpll config. To be used | |
7433 | * in cases where we need the PLL enabled even when @pipe is not going to | |
7434 | * be enabled. | |
7435 | */ | |
7436 | void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, | |
7437 | const struct dpll *dpll) | |
7438 | { | |
7439 | struct intel_crtc *crtc = | |
7440 | to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); | |
5cec258b | 7441 | struct intel_crtc_state pipe_config = { |
a93e255f | 7442 | .base.crtc = &crtc->base, |
d288f65f VS |
7443 | .pixel_multiplier = 1, |
7444 | .dpll = *dpll, | |
7445 | }; | |
7446 | ||
7447 | if (IS_CHERRYVIEW(dev)) { | |
251ac862 | 7448 | chv_compute_dpll(crtc, &pipe_config); |
d288f65f VS |
7449 | chv_prepare_pll(crtc, &pipe_config); |
7450 | chv_enable_pll(crtc, &pipe_config); | |
7451 | } else { | |
251ac862 | 7452 | vlv_compute_dpll(crtc, &pipe_config); |
d288f65f VS |
7453 | vlv_prepare_pll(crtc, &pipe_config); |
7454 | vlv_enable_pll(crtc, &pipe_config); | |
7455 | } | |
7456 | } | |
7457 | ||
7458 | /** | |
7459 | * vlv_force_pll_off - forcibly disable just the PLL | |
7460 | * @dev_priv: i915 private structure | |
7461 | * @pipe: pipe PLL to disable | |
7462 | * | |
7463 | * Disable the PLL for @pipe. To be used in cases where we need | |
7464 | * the PLL enabled even when @pipe is not going to be enabled. | |
7465 | */ | |
7466 | void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe) | |
7467 | { | |
7468 | if (IS_CHERRYVIEW(dev)) | |
7469 | chv_disable_pll(to_i915(dev), pipe); | |
7470 | else | |
7471 | vlv_disable_pll(to_i915(dev), pipe); | |
7472 | } | |
7473 | ||
251ac862 DV |
7474 | static void i9xx_compute_dpll(struct intel_crtc *crtc, |
7475 | struct intel_crtc_state *crtc_state, | |
7476 | intel_clock_t *reduced_clock, | |
7477 | int num_connectors) | |
eb1cbe48 | 7478 | { |
f47709a9 | 7479 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 7480 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 DV |
7481 | u32 dpll; |
7482 | bool is_sdvo; | |
190f68c5 | 7483 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7484 | |
190f68c5 | 7485 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7486 | |
a93e255f ACO |
7487 | is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) || |
7488 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI); | |
eb1cbe48 DV |
7489 | |
7490 | dpll = DPLL_VGA_MODE_DIS; | |
7491 | ||
a93e255f | 7492 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
7493 | dpll |= DPLLB_MODE_LVDS; |
7494 | else | |
7495 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 7496 | |
ef1b460d | 7497 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
190f68c5 | 7498 | dpll |= (crtc_state->pixel_multiplier - 1) |
198a037f | 7499 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
eb1cbe48 | 7500 | } |
198a037f DV |
7501 | |
7502 | if (is_sdvo) | |
4a33e48d | 7503 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 7504 | |
190f68c5 | 7505 | if (crtc_state->has_dp_encoder) |
4a33e48d | 7506 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
7507 | |
7508 | /* compute bitmask from p1 value */ | |
7509 | if (IS_PINEVIEW(dev)) | |
7510 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
7511 | else { | |
7512 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7513 | if (IS_G4X(dev) && reduced_clock) | |
7514 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
7515 | } | |
7516 | switch (clock->p2) { | |
7517 | case 5: | |
7518 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
7519 | break; | |
7520 | case 7: | |
7521 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
7522 | break; | |
7523 | case 10: | |
7524 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
7525 | break; | |
7526 | case 14: | |
7527 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
7528 | break; | |
7529 | } | |
7530 | if (INTEL_INFO(dev)->gen >= 4) | |
7531 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
7532 | ||
190f68c5 | 7533 | if (crtc_state->sdvo_tv_clock) |
eb1cbe48 | 7534 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
a93e255f | 7535 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
7536 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
7537 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
7538 | else | |
7539 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7540 | ||
7541 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7542 | crtc_state->dpll_hw_state.dpll = dpll; |
8bcc2795 | 7543 | |
eb1cbe48 | 7544 | if (INTEL_INFO(dev)->gen >= 4) { |
190f68c5 | 7545 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
ef1b460d | 7546 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
190f68c5 | 7547 | crtc_state->dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
7548 | } |
7549 | } | |
7550 | ||
251ac862 DV |
7551 | static void i8xx_compute_dpll(struct intel_crtc *crtc, |
7552 | struct intel_crtc_state *crtc_state, | |
7553 | intel_clock_t *reduced_clock, | |
7554 | int num_connectors) | |
eb1cbe48 | 7555 | { |
f47709a9 | 7556 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 7557 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 | 7558 | u32 dpll; |
190f68c5 | 7559 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7560 | |
190f68c5 | 7561 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7562 | |
eb1cbe48 DV |
7563 | dpll = DPLL_VGA_MODE_DIS; |
7564 | ||
a93e255f | 7565 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
7566 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
7567 | } else { | |
7568 | if (clock->p1 == 2) | |
7569 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
7570 | else | |
7571 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7572 | if (clock->p2 == 4) | |
7573 | dpll |= PLL_P2_DIVIDE_BY_4; | |
7574 | } | |
7575 | ||
a93e255f | 7576 | if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
4a33e48d DV |
7577 | dpll |= DPLL_DVO_2X_MODE; |
7578 | ||
a93e255f | 7579 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
7580 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
7581 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
7582 | else | |
7583 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7584 | ||
7585 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7586 | crtc_state->dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
7587 | } |
7588 | ||
8a654f3b | 7589 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
7590 | { |
7591 | struct drm_device *dev = intel_crtc->base.dev; | |
7592 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7593 | enum pipe pipe = intel_crtc->pipe; | |
6e3c9717 | 7594 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
8a654f3b | 7595 | struct drm_display_mode *adjusted_mode = |
6e3c9717 | 7596 | &intel_crtc->config->base.adjusted_mode; |
1caea6e9 VS |
7597 | uint32_t crtc_vtotal, crtc_vblank_end; |
7598 | int vsyncshift = 0; | |
4d8a62ea DV |
7599 | |
7600 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
7601 | * the hw state checker will get angry at the mismatch. */ | |
7602 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
7603 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 7604 | |
609aeaca | 7605 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 7606 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
7607 | crtc_vtotal -= 1; |
7608 | crtc_vblank_end -= 1; | |
609aeaca | 7609 | |
409ee761 | 7610 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
609aeaca VS |
7611 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
7612 | else | |
7613 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
7614 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
7615 | if (vsyncshift < 0) |
7616 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
7617 | } |
7618 | ||
7619 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 7620 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 7621 | |
fe2b8f9d | 7622 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
7623 | (adjusted_mode->crtc_hdisplay - 1) | |
7624 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 7625 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
7626 | (adjusted_mode->crtc_hblank_start - 1) | |
7627 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 7628 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
7629 | (adjusted_mode->crtc_hsync_start - 1) | |
7630 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
7631 | ||
fe2b8f9d | 7632 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 7633 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 7634 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 7635 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 7636 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 7637 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 7638 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
7639 | (adjusted_mode->crtc_vsync_start - 1) | |
7640 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
7641 | ||
b5e508d4 PZ |
7642 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
7643 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
7644 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
7645 | * bits. */ | |
7646 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
7647 | (pipe == PIPE_B || pipe == PIPE_C)) | |
7648 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
7649 | ||
b0e77b9c PZ |
7650 | /* pipesrc controls the size that is scaled from, which should |
7651 | * always be the user's requested size. | |
7652 | */ | |
7653 | I915_WRITE(PIPESRC(pipe), | |
6e3c9717 ACO |
7654 | ((intel_crtc->config->pipe_src_w - 1) << 16) | |
7655 | (intel_crtc->config->pipe_src_h - 1)); | |
b0e77b9c PZ |
7656 | } |
7657 | ||
1bd1bd80 | 7658 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5cec258b | 7659 | struct intel_crtc_state *pipe_config) |
1bd1bd80 DV |
7660 | { |
7661 | struct drm_device *dev = crtc->base.dev; | |
7662 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7663 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; | |
7664 | uint32_t tmp; | |
7665 | ||
7666 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7667 | pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
7668 | pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7669 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
2d112de7 ACO |
7670 | pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
7671 | pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7672 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
2d112de7 ACO |
7673 | pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
7674 | pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7675 | |
7676 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7677 | pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
7678 | pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7679 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
2d112de7 ACO |
7680 | pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
7681 | pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7682 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
2d112de7 ACO |
7683 | pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
7684 | pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7685 | |
7686 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
2d112de7 ACO |
7687 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
7688 | pipe_config->base.adjusted_mode.crtc_vtotal += 1; | |
7689 | pipe_config->base.adjusted_mode.crtc_vblank_end += 1; | |
1bd1bd80 DV |
7690 | } |
7691 | ||
7692 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
7693 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
7694 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
7695 | ||
2d112de7 ACO |
7696 | pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; |
7697 | pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
7698 | } |
7699 | ||
f6a83288 | 7700 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 7701 | struct intel_crtc_state *pipe_config) |
babea61d | 7702 | { |
2d112de7 ACO |
7703 | mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; |
7704 | mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; | |
7705 | mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; | |
7706 | mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; | |
babea61d | 7707 | |
2d112de7 ACO |
7708 | mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; |
7709 | mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; | |
7710 | mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; | |
7711 | mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; | |
babea61d | 7712 | |
2d112de7 | 7713 | mode->flags = pipe_config->base.adjusted_mode.flags; |
cd13f5ab | 7714 | mode->type = DRM_MODE_TYPE_DRIVER; |
babea61d | 7715 | |
2d112de7 ACO |
7716 | mode->clock = pipe_config->base.adjusted_mode.crtc_clock; |
7717 | mode->flags |= pipe_config->base.adjusted_mode.flags; | |
cd13f5ab ML |
7718 | |
7719 | mode->hsync = drm_mode_hsync(mode); | |
7720 | mode->vrefresh = drm_mode_vrefresh(mode); | |
7721 | drm_mode_set_name(mode); | |
babea61d JB |
7722 | } |
7723 | ||
84b046f3 DV |
7724 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
7725 | { | |
7726 | struct drm_device *dev = intel_crtc->base.dev; | |
7727 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7728 | uint32_t pipeconf; | |
7729 | ||
9f11a9e4 | 7730 | pipeconf = 0; |
84b046f3 | 7731 | |
b6b5d049 VS |
7732 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
7733 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
7734 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; | |
67c72a12 | 7735 | |
6e3c9717 | 7736 | if (intel_crtc->config->double_wide) |
cf532bb2 | 7737 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
84b046f3 | 7738 | |
ff9ce46e DV |
7739 | /* only g4x and later have fancy bpc/dither controls */ |
7740 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { | |
ff9ce46e | 7741 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
6e3c9717 | 7742 | if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) |
ff9ce46e | 7743 | pipeconf |= PIPECONF_DITHER_EN | |
84b046f3 | 7744 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 7745 | |
6e3c9717 | 7746 | switch (intel_crtc->config->pipe_bpp) { |
ff9ce46e DV |
7747 | case 18: |
7748 | pipeconf |= PIPECONF_6BPC; | |
7749 | break; | |
7750 | case 24: | |
7751 | pipeconf |= PIPECONF_8BPC; | |
7752 | break; | |
7753 | case 30: | |
7754 | pipeconf |= PIPECONF_10BPC; | |
7755 | break; | |
7756 | default: | |
7757 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
7758 | BUG(); | |
84b046f3 DV |
7759 | } |
7760 | } | |
7761 | ||
7762 | if (HAS_PIPE_CXSR(dev)) { | |
7763 | if (intel_crtc->lowfreq_avail) { | |
7764 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
7765 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
7766 | } else { | |
7767 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
7768 | } |
7769 | } | |
7770 | ||
6e3c9717 | 7771 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
efc2cfff | 7772 | if (INTEL_INFO(dev)->gen < 4 || |
409ee761 | 7773 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
efc2cfff VS |
7774 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
7775 | else | |
7776 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
7777 | } else | |
84b046f3 DV |
7778 | pipeconf |= PIPECONF_PROGRESSIVE; |
7779 | ||
6e3c9717 | 7780 | if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range) |
9f11a9e4 | 7781 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
9c8e09b7 | 7782 | |
84b046f3 DV |
7783 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
7784 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
7785 | } | |
7786 | ||
190f68c5 ACO |
7787 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, |
7788 | struct intel_crtc_state *crtc_state) | |
79e53945 | 7789 | { |
c7653199 | 7790 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 7791 | struct drm_i915_private *dev_priv = dev->dev_private; |
c751ce4f | 7792 | int refclk, num_connectors = 0; |
c329a4ec DV |
7793 | intel_clock_t clock; |
7794 | bool ok; | |
7795 | bool is_dsi = false; | |
5eddb70b | 7796 | struct intel_encoder *encoder; |
d4906093 | 7797 | const intel_limit_t *limit; |
55bb9992 | 7798 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 7799 | struct drm_connector *connector; |
55bb9992 ACO |
7800 | struct drm_connector_state *connector_state; |
7801 | int i; | |
79e53945 | 7802 | |
dd3cd74a ACO |
7803 | memset(&crtc_state->dpll_hw_state, 0, |
7804 | sizeof(crtc_state->dpll_hw_state)); | |
7805 | ||
da3ced29 | 7806 | for_each_connector_in_state(state, connector, connector_state, i) { |
55bb9992 ACO |
7807 | if (connector_state->crtc != &crtc->base) |
7808 | continue; | |
7809 | ||
7810 | encoder = to_intel_encoder(connector_state->best_encoder); | |
7811 | ||
5eddb70b | 7812 | switch (encoder->type) { |
e9fd1c02 JN |
7813 | case INTEL_OUTPUT_DSI: |
7814 | is_dsi = true; | |
7815 | break; | |
6847d71b PZ |
7816 | default: |
7817 | break; | |
79e53945 | 7818 | } |
43565a06 | 7819 | |
c751ce4f | 7820 | num_connectors++; |
79e53945 JB |
7821 | } |
7822 | ||
f2335330 | 7823 | if (is_dsi) |
5b18e57c | 7824 | return 0; |
f2335330 | 7825 | |
190f68c5 | 7826 | if (!crtc_state->clock_set) { |
a93e255f | 7827 | refclk = i9xx_get_refclk(crtc_state, num_connectors); |
79e53945 | 7828 | |
e9fd1c02 JN |
7829 | /* |
7830 | * Returns a set of divisors for the desired target clock with | |
7831 | * the given refclk, or FALSE. The returned values represent | |
7832 | * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + | |
7833 | * 2) / p1 / p2. | |
7834 | */ | |
a93e255f ACO |
7835 | limit = intel_limit(crtc_state, refclk); |
7836 | ok = dev_priv->display.find_dpll(limit, crtc_state, | |
190f68c5 | 7837 | crtc_state->port_clock, |
e9fd1c02 | 7838 | refclk, NULL, &clock); |
f2335330 | 7839 | if (!ok) { |
e9fd1c02 JN |
7840 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
7841 | return -EINVAL; | |
7842 | } | |
79e53945 | 7843 | |
f2335330 | 7844 | /* Compat-code for transition, will disappear. */ |
190f68c5 ACO |
7845 | crtc_state->dpll.n = clock.n; |
7846 | crtc_state->dpll.m1 = clock.m1; | |
7847 | crtc_state->dpll.m2 = clock.m2; | |
7848 | crtc_state->dpll.p1 = clock.p1; | |
7849 | crtc_state->dpll.p2 = clock.p2; | |
f47709a9 | 7850 | } |
7026d4ac | 7851 | |
e9fd1c02 | 7852 | if (IS_GEN2(dev)) { |
c329a4ec | 7853 | i8xx_compute_dpll(crtc, crtc_state, NULL, |
251ac862 | 7854 | num_connectors); |
9d556c99 | 7855 | } else if (IS_CHERRYVIEW(dev)) { |
251ac862 | 7856 | chv_compute_dpll(crtc, crtc_state); |
e9fd1c02 | 7857 | } else if (IS_VALLEYVIEW(dev)) { |
251ac862 | 7858 | vlv_compute_dpll(crtc, crtc_state); |
e9fd1c02 | 7859 | } else { |
c329a4ec | 7860 | i9xx_compute_dpll(crtc, crtc_state, NULL, |
251ac862 | 7861 | num_connectors); |
e9fd1c02 | 7862 | } |
79e53945 | 7863 | |
c8f7a0db | 7864 | return 0; |
f564048e EA |
7865 | } |
7866 | ||
2fa2fe9a | 7867 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 7868 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
7869 | { |
7870 | struct drm_device *dev = crtc->base.dev; | |
7871 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7872 | uint32_t tmp; | |
7873 | ||
dc9e7dec VS |
7874 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
7875 | return; | |
7876 | ||
2fa2fe9a | 7877 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
7878 | if (!(tmp & PFIT_ENABLE)) |
7879 | return; | |
2fa2fe9a | 7880 | |
06922821 | 7881 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
7882 | if (INTEL_INFO(dev)->gen < 4) { |
7883 | if (crtc->pipe != PIPE_B) | |
7884 | return; | |
2fa2fe9a DV |
7885 | } else { |
7886 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
7887 | return; | |
7888 | } | |
7889 | ||
06922821 | 7890 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a DV |
7891 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
7892 | if (INTEL_INFO(dev)->gen < 5) | |
7893 | pipe_config->gmch_pfit.lvds_border_bits = | |
7894 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; | |
7895 | } | |
7896 | ||
acbec814 | 7897 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 7898 | struct intel_crtc_state *pipe_config) |
acbec814 JB |
7899 | { |
7900 | struct drm_device *dev = crtc->base.dev; | |
7901 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7902 | int pipe = pipe_config->cpu_transcoder; | |
7903 | intel_clock_t clock; | |
7904 | u32 mdiv; | |
662c6ecb | 7905 | int refclk = 100000; |
acbec814 | 7906 | |
f573de5a SK |
7907 | /* In case of MIPI DPLL will not even be used */ |
7908 | if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)) | |
7909 | return; | |
7910 | ||
a580516d | 7911 | mutex_lock(&dev_priv->sb_lock); |
ab3c759a | 7912 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
a580516d | 7913 | mutex_unlock(&dev_priv->sb_lock); |
acbec814 JB |
7914 | |
7915 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
7916 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
7917 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
7918 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
7919 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
7920 | ||
dccbea3b | 7921 | pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); |
acbec814 JB |
7922 | } |
7923 | ||
5724dbd1 DL |
7924 | static void |
7925 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, | |
7926 | struct intel_initial_plane_config *plane_config) | |
1ad292b5 JB |
7927 | { |
7928 | struct drm_device *dev = crtc->base.dev; | |
7929 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7930 | u32 val, base, offset; | |
7931 | int pipe = crtc->pipe, plane = crtc->plane; | |
7932 | int fourcc, pixel_format; | |
6761dd31 | 7933 | unsigned int aligned_height; |
b113d5ee | 7934 | struct drm_framebuffer *fb; |
1b842c89 | 7935 | struct intel_framebuffer *intel_fb; |
1ad292b5 | 7936 | |
42a7b088 DL |
7937 | val = I915_READ(DSPCNTR(plane)); |
7938 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
7939 | return; | |
7940 | ||
d9806c9f | 7941 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 7942 | if (!intel_fb) { |
1ad292b5 JB |
7943 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
7944 | return; | |
7945 | } | |
7946 | ||
1b842c89 DL |
7947 | fb = &intel_fb->base; |
7948 | ||
18c5247e DV |
7949 | if (INTEL_INFO(dev)->gen >= 4) { |
7950 | if (val & DISPPLANE_TILED) { | |
49af449b | 7951 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
7952 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
7953 | } | |
7954 | } | |
1ad292b5 JB |
7955 | |
7956 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 7957 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
7958 | fb->pixel_format = fourcc; |
7959 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
1ad292b5 JB |
7960 | |
7961 | if (INTEL_INFO(dev)->gen >= 4) { | |
49af449b | 7962 | if (plane_config->tiling) |
1ad292b5 JB |
7963 | offset = I915_READ(DSPTILEOFF(plane)); |
7964 | else | |
7965 | offset = I915_READ(DSPLINOFF(plane)); | |
7966 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
7967 | } else { | |
7968 | base = I915_READ(DSPADDR(plane)); | |
7969 | } | |
7970 | plane_config->base = base; | |
7971 | ||
7972 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
7973 | fb->width = ((val >> 16) & 0xfff) + 1; |
7974 | fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
7975 | |
7976 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 7977 | fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 7978 | |
b113d5ee | 7979 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
7980 | fb->pixel_format, |
7981 | fb->modifier[0]); | |
1ad292b5 | 7982 | |
f37b5c2b | 7983 | plane_config->size = fb->pitches[0] * aligned_height; |
1ad292b5 | 7984 | |
2844a921 DL |
7985 | DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
7986 | pipe_name(pipe), plane, fb->width, fb->height, | |
7987 | fb->bits_per_pixel, base, fb->pitches[0], | |
7988 | plane_config->size); | |
1ad292b5 | 7989 | |
2d14030b | 7990 | plane_config->fb = intel_fb; |
1ad292b5 JB |
7991 | } |
7992 | ||
70b23a98 | 7993 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 7994 | struct intel_crtc_state *pipe_config) |
70b23a98 VS |
7995 | { |
7996 | struct drm_device *dev = crtc->base.dev; | |
7997 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7998 | int pipe = pipe_config->cpu_transcoder; | |
7999 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
8000 | intel_clock_t clock; | |
0d7b6b11 | 8001 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; |
70b23a98 VS |
8002 | int refclk = 100000; |
8003 | ||
a580516d | 8004 | mutex_lock(&dev_priv->sb_lock); |
70b23a98 VS |
8005 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); |
8006 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
8007 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
8008 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
0d7b6b11 | 8009 | pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
a580516d | 8010 | mutex_unlock(&dev_priv->sb_lock); |
70b23a98 VS |
8011 | |
8012 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
0d7b6b11 ID |
8013 | clock.m2 = (pll_dw0 & 0xff) << 22; |
8014 | if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) | |
8015 | clock.m2 |= pll_dw2 & 0x3fffff; | |
70b23a98 VS |
8016 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; |
8017 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
8018 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
8019 | ||
dccbea3b | 8020 | pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); |
70b23a98 VS |
8021 | } |
8022 | ||
0e8ffe1b | 8023 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 8024 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
8025 | { |
8026 | struct drm_device *dev = crtc->base.dev; | |
8027 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8028 | uint32_t tmp; | |
8029 | ||
f458ebbc DV |
8030 | if (!intel_display_power_is_enabled(dev_priv, |
8031 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
b5482bd0 ID |
8032 | return false; |
8033 | ||
e143a21c | 8034 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 8035 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 8036 | |
0e8ffe1b DV |
8037 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
8038 | if (!(tmp & PIPECONF_ENABLE)) | |
8039 | return false; | |
8040 | ||
42571aef VS |
8041 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
8042 | switch (tmp & PIPECONF_BPC_MASK) { | |
8043 | case PIPECONF_6BPC: | |
8044 | pipe_config->pipe_bpp = 18; | |
8045 | break; | |
8046 | case PIPECONF_8BPC: | |
8047 | pipe_config->pipe_bpp = 24; | |
8048 | break; | |
8049 | case PIPECONF_10BPC: | |
8050 | pipe_config->pipe_bpp = 30; | |
8051 | break; | |
8052 | default: | |
8053 | break; | |
8054 | } | |
8055 | } | |
8056 | ||
b5a9fa09 DV |
8057 | if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT)) |
8058 | pipe_config->limited_color_range = true; | |
8059 | ||
282740f7 VS |
8060 | if (INTEL_INFO(dev)->gen < 4) |
8061 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
8062 | ||
1bd1bd80 DV |
8063 | intel_get_pipe_timings(crtc, pipe_config); |
8064 | ||
2fa2fe9a DV |
8065 | i9xx_get_pfit_config(crtc, pipe_config); |
8066 | ||
6c49f241 DV |
8067 | if (INTEL_INFO(dev)->gen >= 4) { |
8068 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
8069 | pipe_config->pixel_multiplier = | |
8070 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
8071 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 8072 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
8073 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
8074 | tmp = I915_READ(DPLL(crtc->pipe)); | |
8075 | pipe_config->pixel_multiplier = | |
8076 | ((tmp & SDVO_MULTIPLIER_MASK) | |
8077 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
8078 | } else { | |
8079 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
8080 | * port and will be fixed up in the encoder->get_config | |
8081 | * function. */ | |
8082 | pipe_config->pixel_multiplier = 1; | |
8083 | } | |
8bcc2795 DV |
8084 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
8085 | if (!IS_VALLEYVIEW(dev)) { | |
1c4e0274 VS |
8086 | /* |
8087 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs | |
8088 | * on 830. Filter it out here so that we don't | |
8089 | * report errors due to that. | |
8090 | */ | |
8091 | if (IS_I830(dev)) | |
8092 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; | |
8093 | ||
8bcc2795 DV |
8094 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
8095 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
8096 | } else { |
8097 | /* Mask out read-only status bits. */ | |
8098 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
8099 | DPLL_PORTC_READY_MASK | | |
8100 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 8101 | } |
6c49f241 | 8102 | |
70b23a98 VS |
8103 | if (IS_CHERRYVIEW(dev)) |
8104 | chv_crtc_clock_get(crtc, pipe_config); | |
8105 | else if (IS_VALLEYVIEW(dev)) | |
acbec814 JB |
8106 | vlv_crtc_clock_get(crtc, pipe_config); |
8107 | else | |
8108 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 8109 | |
0f64614d VS |
8110 | /* |
8111 | * Normally the dotclock is filled in by the encoder .get_config() | |
8112 | * but in case the pipe is enabled w/o any ports we need a sane | |
8113 | * default. | |
8114 | */ | |
8115 | pipe_config->base.adjusted_mode.crtc_clock = | |
8116 | pipe_config->port_clock / pipe_config->pixel_multiplier; | |
8117 | ||
0e8ffe1b DV |
8118 | return true; |
8119 | } | |
8120 | ||
dde86e2d | 8121 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 JB |
8122 | { |
8123 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13d83a67 | 8124 | struct intel_encoder *encoder; |
74cfd7ac | 8125 | u32 val, final; |
13d83a67 | 8126 | bool has_lvds = false; |
199e5d79 | 8127 | bool has_cpu_edp = false; |
199e5d79 | 8128 | bool has_panel = false; |
99eb6a01 KP |
8129 | bool has_ck505 = false; |
8130 | bool can_ssc = false; | |
13d83a67 JB |
8131 | |
8132 | /* We need to take the global config into account */ | |
b2784e15 | 8133 | for_each_intel_encoder(dev, encoder) { |
199e5d79 KP |
8134 | switch (encoder->type) { |
8135 | case INTEL_OUTPUT_LVDS: | |
8136 | has_panel = true; | |
8137 | has_lvds = true; | |
8138 | break; | |
8139 | case INTEL_OUTPUT_EDP: | |
8140 | has_panel = true; | |
2de6905f | 8141 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
8142 | has_cpu_edp = true; |
8143 | break; | |
6847d71b PZ |
8144 | default: |
8145 | break; | |
13d83a67 JB |
8146 | } |
8147 | } | |
8148 | ||
99eb6a01 | 8149 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 8150 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
8151 | can_ssc = has_ck505; |
8152 | } else { | |
8153 | has_ck505 = false; | |
8154 | can_ssc = true; | |
8155 | } | |
8156 | ||
2de6905f ID |
8157 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
8158 | has_panel, has_lvds, has_ck505); | |
13d83a67 JB |
8159 | |
8160 | /* Ironlake: try to setup display ref clock before DPLL | |
8161 | * enabling. This is only under driver's control after | |
8162 | * PCH B stepping, previous chipset stepping should be | |
8163 | * ignoring this setting. | |
8164 | */ | |
74cfd7ac CW |
8165 | val = I915_READ(PCH_DREF_CONTROL); |
8166 | ||
8167 | /* As we must carefully and slowly disable/enable each source in turn, | |
8168 | * compute the final state we want first and check if we need to | |
8169 | * make any changes at all. | |
8170 | */ | |
8171 | final = val; | |
8172 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
8173 | if (has_ck505) | |
8174 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
8175 | else | |
8176 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
8177 | ||
8178 | final &= ~DREF_SSC_SOURCE_MASK; | |
8179 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
8180 | final &= ~DREF_SSC1_ENABLE; | |
8181 | ||
8182 | if (has_panel) { | |
8183 | final |= DREF_SSC_SOURCE_ENABLE; | |
8184 | ||
8185 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8186 | final |= DREF_SSC1_ENABLE; | |
8187 | ||
8188 | if (has_cpu_edp) { | |
8189 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8190 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
8191 | else | |
8192 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
8193 | } else | |
8194 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
8195 | } else { | |
8196 | final |= DREF_SSC_SOURCE_DISABLE; | |
8197 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
8198 | } | |
8199 | ||
8200 | if (final == val) | |
8201 | return; | |
8202 | ||
13d83a67 | 8203 | /* Always enable nonspread source */ |
74cfd7ac | 8204 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 8205 | |
99eb6a01 | 8206 | if (has_ck505) |
74cfd7ac | 8207 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 8208 | else |
74cfd7ac | 8209 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 8210 | |
199e5d79 | 8211 | if (has_panel) { |
74cfd7ac CW |
8212 | val &= ~DREF_SSC_SOURCE_MASK; |
8213 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 8214 | |
199e5d79 | 8215 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 8216 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 8217 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 8218 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 8219 | } else |
74cfd7ac | 8220 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
8221 | |
8222 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 8223 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8224 | POSTING_READ(PCH_DREF_CONTROL); |
8225 | udelay(200); | |
8226 | ||
74cfd7ac | 8227 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
8228 | |
8229 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 8230 | if (has_cpu_edp) { |
99eb6a01 | 8231 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 8232 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 8233 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 8234 | } else |
74cfd7ac | 8235 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 8236 | } else |
74cfd7ac | 8237 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 8238 | |
74cfd7ac | 8239 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8240 | POSTING_READ(PCH_DREF_CONTROL); |
8241 | udelay(200); | |
8242 | } else { | |
8243 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
8244 | ||
74cfd7ac | 8245 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
8246 | |
8247 | /* Turn off CPU output */ | |
74cfd7ac | 8248 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 8249 | |
74cfd7ac | 8250 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8251 | POSTING_READ(PCH_DREF_CONTROL); |
8252 | udelay(200); | |
8253 | ||
8254 | /* Turn off the SSC source */ | |
74cfd7ac CW |
8255 | val &= ~DREF_SSC_SOURCE_MASK; |
8256 | val |= DREF_SSC_SOURCE_DISABLE; | |
199e5d79 KP |
8257 | |
8258 | /* Turn off SSC1 */ | |
74cfd7ac | 8259 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 | 8260 | |
74cfd7ac | 8261 | I915_WRITE(PCH_DREF_CONTROL, val); |
13d83a67 JB |
8262 | POSTING_READ(PCH_DREF_CONTROL); |
8263 | udelay(200); | |
8264 | } | |
74cfd7ac CW |
8265 | |
8266 | BUG_ON(val != final); | |
13d83a67 JB |
8267 | } |
8268 | ||
f31f2d55 | 8269 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 8270 | { |
f31f2d55 | 8271 | uint32_t tmp; |
dde86e2d | 8272 | |
0ff066a9 PZ |
8273 | tmp = I915_READ(SOUTH_CHICKEN2); |
8274 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
8275 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 8276 | |
0ff066a9 PZ |
8277 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
8278 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
8279 | DRM_ERROR("FDI mPHY reset assert timeout\n"); | |
dde86e2d | 8280 | |
0ff066a9 PZ |
8281 | tmp = I915_READ(SOUTH_CHICKEN2); |
8282 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
8283 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 8284 | |
0ff066a9 PZ |
8285 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
8286 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
8287 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); | |
f31f2d55 PZ |
8288 | } |
8289 | ||
8290 | /* WaMPhyProgramming:hsw */ | |
8291 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
8292 | { | |
8293 | uint32_t tmp; | |
dde86e2d PZ |
8294 | |
8295 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
8296 | tmp &= ~(0xFF << 24); | |
8297 | tmp |= (0x12 << 24); | |
8298 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
8299 | ||
dde86e2d PZ |
8300 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
8301 | tmp |= (1 << 11); | |
8302 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
8303 | ||
8304 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
8305 | tmp |= (1 << 11); | |
8306 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
8307 | ||
dde86e2d PZ |
8308 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
8309 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
8310 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
8311 | ||
8312 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
8313 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
8314 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
8315 | ||
0ff066a9 PZ |
8316 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
8317 | tmp &= ~(7 << 13); | |
8318 | tmp |= (5 << 13); | |
8319 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 8320 | |
0ff066a9 PZ |
8321 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
8322 | tmp &= ~(7 << 13); | |
8323 | tmp |= (5 << 13); | |
8324 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
8325 | |
8326 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
8327 | tmp &= ~0xFF; | |
8328 | tmp |= 0x1C; | |
8329 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
8330 | ||
8331 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
8332 | tmp &= ~0xFF; | |
8333 | tmp |= 0x1C; | |
8334 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
8335 | ||
8336 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
8337 | tmp &= ~(0xFF << 16); | |
8338 | tmp |= (0x1C << 16); | |
8339 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
8340 | ||
8341 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
8342 | tmp &= ~(0xFF << 16); | |
8343 | tmp |= (0x1C << 16); | |
8344 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
8345 | ||
0ff066a9 PZ |
8346 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
8347 | tmp |= (1 << 27); | |
8348 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 8349 | |
0ff066a9 PZ |
8350 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
8351 | tmp |= (1 << 27); | |
8352 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 8353 | |
0ff066a9 PZ |
8354 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
8355 | tmp &= ~(0xF << 28); | |
8356 | tmp |= (4 << 28); | |
8357 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 8358 | |
0ff066a9 PZ |
8359 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
8360 | tmp &= ~(0xF << 28); | |
8361 | tmp |= (4 << 28); | |
8362 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
8363 | } |
8364 | ||
2fa86a1f PZ |
8365 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
8366 | * Programming" based on the parameters passed: | |
8367 | * - Sequence to enable CLKOUT_DP | |
8368 | * - Sequence to enable CLKOUT_DP without spread | |
8369 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
8370 | */ | |
8371 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
8372 | bool with_fdi) | |
f31f2d55 PZ |
8373 | { |
8374 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa86a1f PZ |
8375 | uint32_t reg, tmp; |
8376 | ||
8377 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
8378 | with_spread = true; | |
c2699524 | 8379 | if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n")) |
2fa86a1f | 8380 | with_fdi = false; |
f31f2d55 | 8381 | |
a580516d | 8382 | mutex_lock(&dev_priv->sb_lock); |
f31f2d55 PZ |
8383 | |
8384 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8385 | tmp &= ~SBI_SSCCTL_DISABLE; | |
8386 | tmp |= SBI_SSCCTL_PATHALT; | |
8387 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8388 | ||
8389 | udelay(24); | |
8390 | ||
2fa86a1f PZ |
8391 | if (with_spread) { |
8392 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8393 | tmp &= ~SBI_SSCCTL_PATHALT; | |
8394 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 8395 | |
2fa86a1f PZ |
8396 | if (with_fdi) { |
8397 | lpt_reset_fdi_mphy(dev_priv); | |
8398 | lpt_program_fdi_mphy(dev_priv); | |
8399 | } | |
8400 | } | |
dde86e2d | 8401 | |
c2699524 | 8402 | reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; |
2fa86a1f PZ |
8403 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
8404 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8405 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 | 8406 | |
a580516d | 8407 | mutex_unlock(&dev_priv->sb_lock); |
dde86e2d PZ |
8408 | } |
8409 | ||
47701c3b PZ |
8410 | /* Sequence to disable CLKOUT_DP */ |
8411 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
8412 | { | |
8413 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8414 | uint32_t reg, tmp; | |
8415 | ||
a580516d | 8416 | mutex_lock(&dev_priv->sb_lock); |
47701c3b | 8417 | |
c2699524 | 8418 | reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; |
47701c3b PZ |
8419 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
8420 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8421 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
8422 | ||
8423 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8424 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
8425 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
8426 | tmp |= SBI_SSCCTL_PATHALT; | |
8427 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8428 | udelay(32); | |
8429 | } | |
8430 | tmp |= SBI_SSCCTL_DISABLE; | |
8431 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8432 | } | |
8433 | ||
a580516d | 8434 | mutex_unlock(&dev_priv->sb_lock); |
47701c3b PZ |
8435 | } |
8436 | ||
bf8fa3d3 PZ |
8437 | static void lpt_init_pch_refclk(struct drm_device *dev) |
8438 | { | |
bf8fa3d3 PZ |
8439 | struct intel_encoder *encoder; |
8440 | bool has_vga = false; | |
8441 | ||
b2784e15 | 8442 | for_each_intel_encoder(dev, encoder) { |
bf8fa3d3 PZ |
8443 | switch (encoder->type) { |
8444 | case INTEL_OUTPUT_ANALOG: | |
8445 | has_vga = true; | |
8446 | break; | |
6847d71b PZ |
8447 | default: |
8448 | break; | |
bf8fa3d3 PZ |
8449 | } |
8450 | } | |
8451 | ||
47701c3b PZ |
8452 | if (has_vga) |
8453 | lpt_enable_clkout_dp(dev, true, true); | |
8454 | else | |
8455 | lpt_disable_clkout_dp(dev); | |
bf8fa3d3 PZ |
8456 | } |
8457 | ||
dde86e2d PZ |
8458 | /* |
8459 | * Initialize reference clocks when the driver loads | |
8460 | */ | |
8461 | void intel_init_pch_refclk(struct drm_device *dev) | |
8462 | { | |
8463 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
8464 | ironlake_init_pch_refclk(dev); | |
8465 | else if (HAS_PCH_LPT(dev)) | |
8466 | lpt_init_pch_refclk(dev); | |
8467 | } | |
8468 | ||
55bb9992 | 8469 | static int ironlake_get_refclk(struct intel_crtc_state *crtc_state) |
d9d444cb | 8470 | { |
55bb9992 | 8471 | struct drm_device *dev = crtc_state->base.crtc->dev; |
d9d444cb | 8472 | struct drm_i915_private *dev_priv = dev->dev_private; |
55bb9992 | 8473 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 8474 | struct drm_connector *connector; |
55bb9992 | 8475 | struct drm_connector_state *connector_state; |
d9d444cb | 8476 | struct intel_encoder *encoder; |
55bb9992 | 8477 | int num_connectors = 0, i; |
d9d444cb JB |
8478 | bool is_lvds = false; |
8479 | ||
da3ced29 | 8480 | for_each_connector_in_state(state, connector, connector_state, i) { |
55bb9992 ACO |
8481 | if (connector_state->crtc != crtc_state->base.crtc) |
8482 | continue; | |
8483 | ||
8484 | encoder = to_intel_encoder(connector_state->best_encoder); | |
8485 | ||
d9d444cb JB |
8486 | switch (encoder->type) { |
8487 | case INTEL_OUTPUT_LVDS: | |
8488 | is_lvds = true; | |
8489 | break; | |
6847d71b PZ |
8490 | default: |
8491 | break; | |
d9d444cb JB |
8492 | } |
8493 | num_connectors++; | |
8494 | } | |
8495 | ||
8496 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
e91e941b | 8497 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", |
41aa3448 | 8498 | dev_priv->vbt.lvds_ssc_freq); |
e91e941b | 8499 | return dev_priv->vbt.lvds_ssc_freq; |
d9d444cb JB |
8500 | } |
8501 | ||
8502 | return 120000; | |
8503 | } | |
8504 | ||
6ff93609 | 8505 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 8506 | { |
c8203565 | 8507 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
8508 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8509 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
8510 | uint32_t val; |
8511 | ||
78114071 | 8512 | val = 0; |
c8203565 | 8513 | |
6e3c9717 | 8514 | switch (intel_crtc->config->pipe_bpp) { |
c8203565 | 8515 | case 18: |
dfd07d72 | 8516 | val |= PIPECONF_6BPC; |
c8203565 PZ |
8517 | break; |
8518 | case 24: | |
dfd07d72 | 8519 | val |= PIPECONF_8BPC; |
c8203565 PZ |
8520 | break; |
8521 | case 30: | |
dfd07d72 | 8522 | val |= PIPECONF_10BPC; |
c8203565 PZ |
8523 | break; |
8524 | case 36: | |
dfd07d72 | 8525 | val |= PIPECONF_12BPC; |
c8203565 PZ |
8526 | break; |
8527 | default: | |
cc769b62 PZ |
8528 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
8529 | BUG(); | |
c8203565 PZ |
8530 | } |
8531 | ||
6e3c9717 | 8532 | if (intel_crtc->config->dither) |
c8203565 PZ |
8533 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8534 | ||
6e3c9717 | 8535 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
8536 | val |= PIPECONF_INTERLACED_ILK; |
8537 | else | |
8538 | val |= PIPECONF_PROGRESSIVE; | |
8539 | ||
6e3c9717 | 8540 | if (intel_crtc->config->limited_color_range) |
3685a8f3 | 8541 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 8542 | |
c8203565 PZ |
8543 | I915_WRITE(PIPECONF(pipe), val); |
8544 | POSTING_READ(PIPECONF(pipe)); | |
8545 | } | |
8546 | ||
86d3efce VS |
8547 | /* |
8548 | * Set up the pipe CSC unit. | |
8549 | * | |
8550 | * Currently only full range RGB to limited range RGB conversion | |
8551 | * is supported, but eventually this should handle various | |
8552 | * RGB<->YCbCr scenarios as well. | |
8553 | */ | |
50f3b016 | 8554 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
86d3efce VS |
8555 | { |
8556 | struct drm_device *dev = crtc->dev; | |
8557 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8558 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8559 | int pipe = intel_crtc->pipe; | |
8560 | uint16_t coeff = 0x7800; /* 1.0 */ | |
8561 | ||
8562 | /* | |
8563 | * TODO: Check what kind of values actually come out of the pipe | |
8564 | * with these coeff/postoff values and adjust to get the best | |
8565 | * accuracy. Perhaps we even need to take the bpc value into | |
8566 | * consideration. | |
8567 | */ | |
8568 | ||
6e3c9717 | 8569 | if (intel_crtc->config->limited_color_range) |
86d3efce VS |
8570 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
8571 | ||
8572 | /* | |
8573 | * GY/GU and RY/RU should be the other way around according | |
8574 | * to BSpec, but reality doesn't agree. Just set them up in | |
8575 | * a way that results in the correct picture. | |
8576 | */ | |
8577 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); | |
8578 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); | |
8579 | ||
8580 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); | |
8581 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); | |
8582 | ||
8583 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); | |
8584 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); | |
8585 | ||
8586 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); | |
8587 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); | |
8588 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); | |
8589 | ||
8590 | if (INTEL_INFO(dev)->gen > 6) { | |
8591 | uint16_t postoff = 0; | |
8592 | ||
6e3c9717 | 8593 | if (intel_crtc->config->limited_color_range) |
32cf0cb0 | 8594 | postoff = (16 * (1 << 12) / 255) & 0x1fff; |
86d3efce VS |
8595 | |
8596 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); | |
8597 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); | |
8598 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); | |
8599 | ||
8600 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); | |
8601 | } else { | |
8602 | uint32_t mode = CSC_MODE_YUV_TO_RGB; | |
8603 | ||
6e3c9717 | 8604 | if (intel_crtc->config->limited_color_range) |
86d3efce VS |
8605 | mode |= CSC_BLACK_SCREEN_OFFSET; |
8606 | ||
8607 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); | |
8608 | } | |
8609 | } | |
8610 | ||
6ff93609 | 8611 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 8612 | { |
756f85cf PZ |
8613 | struct drm_device *dev = crtc->dev; |
8614 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee2b0b38 | 8615 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 8616 | enum pipe pipe = intel_crtc->pipe; |
6e3c9717 | 8617 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee2b0b38 PZ |
8618 | uint32_t val; |
8619 | ||
3eff4faa | 8620 | val = 0; |
ee2b0b38 | 8621 | |
6e3c9717 | 8622 | if (IS_HASWELL(dev) && intel_crtc->config->dither) |
ee2b0b38 PZ |
8623 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8624 | ||
6e3c9717 | 8625 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
8626 | val |= PIPECONF_INTERLACED_ILK; |
8627 | else | |
8628 | val |= PIPECONF_PROGRESSIVE; | |
8629 | ||
702e7a56 PZ |
8630 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
8631 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
3eff4faa DV |
8632 | |
8633 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); | |
8634 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); | |
756f85cf | 8635 | |
3cdf122c | 8636 | if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) { |
756f85cf PZ |
8637 | val = 0; |
8638 | ||
6e3c9717 | 8639 | switch (intel_crtc->config->pipe_bpp) { |
756f85cf PZ |
8640 | case 18: |
8641 | val |= PIPEMISC_DITHER_6_BPC; | |
8642 | break; | |
8643 | case 24: | |
8644 | val |= PIPEMISC_DITHER_8_BPC; | |
8645 | break; | |
8646 | case 30: | |
8647 | val |= PIPEMISC_DITHER_10_BPC; | |
8648 | break; | |
8649 | case 36: | |
8650 | val |= PIPEMISC_DITHER_12_BPC; | |
8651 | break; | |
8652 | default: | |
8653 | /* Case prevented by pipe_config_set_bpp. */ | |
8654 | BUG(); | |
8655 | } | |
8656 | ||
6e3c9717 | 8657 | if (intel_crtc->config->dither) |
756f85cf PZ |
8658 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
8659 | ||
8660 | I915_WRITE(PIPEMISC(pipe), val); | |
8661 | } | |
ee2b0b38 PZ |
8662 | } |
8663 | ||
6591c6e4 | 8664 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
190f68c5 | 8665 | struct intel_crtc_state *crtc_state, |
6591c6e4 PZ |
8666 | intel_clock_t *clock, |
8667 | bool *has_reduced_clock, | |
8668 | intel_clock_t *reduced_clock) | |
8669 | { | |
8670 | struct drm_device *dev = crtc->dev; | |
8671 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6591c6e4 | 8672 | int refclk; |
d4906093 | 8673 | const intel_limit_t *limit; |
c329a4ec | 8674 | bool ret; |
79e53945 | 8675 | |
55bb9992 | 8676 | refclk = ironlake_get_refclk(crtc_state); |
79e53945 | 8677 | |
d4906093 ML |
8678 | /* |
8679 | * Returns a set of divisors for the desired target clock with the given | |
8680 | * refclk, or FALSE. The returned values represent the clock equation: | |
8681 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
8682 | */ | |
a93e255f ACO |
8683 | limit = intel_limit(crtc_state, refclk); |
8684 | ret = dev_priv->display.find_dpll(limit, crtc_state, | |
190f68c5 | 8685 | crtc_state->port_clock, |
ee9300bb | 8686 | refclk, NULL, clock); |
6591c6e4 PZ |
8687 | if (!ret) |
8688 | return false; | |
cda4b7d3 | 8689 | |
6591c6e4 PZ |
8690 | return true; |
8691 | } | |
8692 | ||
d4b1931c PZ |
8693 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
8694 | { | |
8695 | /* | |
8696 | * Account for spread spectrum to avoid | |
8697 | * oversubscribing the link. Max center spread | |
8698 | * is 2.5%; use 5% for safety's sake. | |
8699 | */ | |
8700 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 8701 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
8702 | } |
8703 | ||
7429e9d4 | 8704 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 8705 | { |
7429e9d4 | 8706 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
8707 | } |
8708 | ||
de13a2e3 | 8709 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
190f68c5 | 8710 | struct intel_crtc_state *crtc_state, |
7429e9d4 | 8711 | u32 *fp, |
9a7c7890 | 8712 | intel_clock_t *reduced_clock, u32 *fp2) |
79e53945 | 8713 | { |
de13a2e3 | 8714 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
8715 | struct drm_device *dev = crtc->dev; |
8716 | struct drm_i915_private *dev_priv = dev->dev_private; | |
55bb9992 | 8717 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 8718 | struct drm_connector *connector; |
55bb9992 ACO |
8719 | struct drm_connector_state *connector_state; |
8720 | struct intel_encoder *encoder; | |
de13a2e3 | 8721 | uint32_t dpll; |
55bb9992 | 8722 | int factor, num_connectors = 0, i; |
09ede541 | 8723 | bool is_lvds = false, is_sdvo = false; |
79e53945 | 8724 | |
da3ced29 | 8725 | for_each_connector_in_state(state, connector, connector_state, i) { |
55bb9992 ACO |
8726 | if (connector_state->crtc != crtc_state->base.crtc) |
8727 | continue; | |
8728 | ||
8729 | encoder = to_intel_encoder(connector_state->best_encoder); | |
8730 | ||
8731 | switch (encoder->type) { | |
79e53945 JB |
8732 | case INTEL_OUTPUT_LVDS: |
8733 | is_lvds = true; | |
8734 | break; | |
8735 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 8736 | case INTEL_OUTPUT_HDMI: |
79e53945 | 8737 | is_sdvo = true; |
79e53945 | 8738 | break; |
6847d71b PZ |
8739 | default: |
8740 | break; | |
79e53945 | 8741 | } |
43565a06 | 8742 | |
c751ce4f | 8743 | num_connectors++; |
79e53945 | 8744 | } |
79e53945 | 8745 | |
c1858123 | 8746 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
8747 | factor = 21; |
8748 | if (is_lvds) { | |
8749 | if ((intel_panel_use_ssc(dev_priv) && | |
e91e941b | 8750 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
f0b44056 | 8751 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 8752 | factor = 25; |
190f68c5 | 8753 | } else if (crtc_state->sdvo_tv_clock) |
8febb297 | 8754 | factor = 20; |
c1858123 | 8755 | |
190f68c5 | 8756 | if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) |
7d0ac5b7 | 8757 | *fp |= FP_CB_TUNE; |
2c07245f | 8758 | |
9a7c7890 DV |
8759 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
8760 | *fp2 |= FP_CB_TUNE; | |
8761 | ||
5eddb70b | 8762 | dpll = 0; |
2c07245f | 8763 | |
a07d6787 EA |
8764 | if (is_lvds) |
8765 | dpll |= DPLLB_MODE_LVDS; | |
8766 | else | |
8767 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 8768 | |
190f68c5 | 8769 | dpll |= (crtc_state->pixel_multiplier - 1) |
ef1b460d | 8770 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
198a037f DV |
8771 | |
8772 | if (is_sdvo) | |
4a33e48d | 8773 | dpll |= DPLL_SDVO_HIGH_SPEED; |
190f68c5 | 8774 | if (crtc_state->has_dp_encoder) |
4a33e48d | 8775 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 8776 | |
a07d6787 | 8777 | /* compute bitmask from p1 value */ |
190f68c5 | 8778 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 8779 | /* also FPA1 */ |
190f68c5 | 8780 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 8781 | |
190f68c5 | 8782 | switch (crtc_state->dpll.p2) { |
a07d6787 EA |
8783 | case 5: |
8784 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
8785 | break; | |
8786 | case 7: | |
8787 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
8788 | break; | |
8789 | case 10: | |
8790 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
8791 | break; | |
8792 | case 14: | |
8793 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
8794 | break; | |
79e53945 JB |
8795 | } |
8796 | ||
b4c09f3b | 8797 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 8798 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
8799 | else |
8800 | dpll |= PLL_REF_INPUT_DREFCLK; | |
8801 | ||
959e16d6 | 8802 | return dpll | DPLL_VCO_ENABLE; |
de13a2e3 PZ |
8803 | } |
8804 | ||
190f68c5 ACO |
8805 | static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, |
8806 | struct intel_crtc_state *crtc_state) | |
de13a2e3 | 8807 | { |
c7653199 | 8808 | struct drm_device *dev = crtc->base.dev; |
de13a2e3 | 8809 | intel_clock_t clock, reduced_clock; |
cbbab5bd | 8810 | u32 dpll = 0, fp = 0, fp2 = 0; |
e2f12b07 | 8811 | bool ok, has_reduced_clock = false; |
8b47047b | 8812 | bool is_lvds = false; |
e2b78267 | 8813 | struct intel_shared_dpll *pll; |
de13a2e3 | 8814 | |
dd3cd74a ACO |
8815 | memset(&crtc_state->dpll_hw_state, 0, |
8816 | sizeof(crtc_state->dpll_hw_state)); | |
8817 | ||
409ee761 | 8818 | is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS); |
79e53945 | 8819 | |
5dc5298b PZ |
8820 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
8821 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); | |
a07d6787 | 8822 | |
190f68c5 | 8823 | ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock, |
de13a2e3 | 8824 | &has_reduced_clock, &reduced_clock); |
190f68c5 | 8825 | if (!ok && !crtc_state->clock_set) { |
de13a2e3 PZ |
8826 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
8827 | return -EINVAL; | |
79e53945 | 8828 | } |
f47709a9 | 8829 | /* Compat-code for transition, will disappear. */ |
190f68c5 ACO |
8830 | if (!crtc_state->clock_set) { |
8831 | crtc_state->dpll.n = clock.n; | |
8832 | crtc_state->dpll.m1 = clock.m1; | |
8833 | crtc_state->dpll.m2 = clock.m2; | |
8834 | crtc_state->dpll.p1 = clock.p1; | |
8835 | crtc_state->dpll.p2 = clock.p2; | |
f47709a9 | 8836 | } |
79e53945 | 8837 | |
5dc5298b | 8838 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
190f68c5 ACO |
8839 | if (crtc_state->has_pch_encoder) { |
8840 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); | |
cbbab5bd | 8841 | if (has_reduced_clock) |
7429e9d4 | 8842 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
cbbab5bd | 8843 | |
190f68c5 | 8844 | dpll = ironlake_compute_dpll(crtc, crtc_state, |
cbbab5bd DV |
8845 | &fp, &reduced_clock, |
8846 | has_reduced_clock ? &fp2 : NULL); | |
8847 | ||
190f68c5 ACO |
8848 | crtc_state->dpll_hw_state.dpll = dpll; |
8849 | crtc_state->dpll_hw_state.fp0 = fp; | |
66e985c0 | 8850 | if (has_reduced_clock) |
190f68c5 | 8851 | crtc_state->dpll_hw_state.fp1 = fp2; |
66e985c0 | 8852 | else |
190f68c5 | 8853 | crtc_state->dpll_hw_state.fp1 = fp; |
66e985c0 | 8854 | |
190f68c5 | 8855 | pll = intel_get_shared_dpll(crtc, crtc_state); |
ee7b9f93 | 8856 | if (pll == NULL) { |
84f44ce7 | 8857 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
c7653199 | 8858 | pipe_name(crtc->pipe)); |
4b645f14 JB |
8859 | return -EINVAL; |
8860 | } | |
3fb37703 | 8861 | } |
79e53945 | 8862 | |
ab585dea | 8863 | if (is_lvds && has_reduced_clock) |
c7653199 | 8864 | crtc->lowfreq_avail = true; |
bcd644e0 | 8865 | else |
c7653199 | 8866 | crtc->lowfreq_avail = false; |
e2b78267 | 8867 | |
c8f7a0db | 8868 | return 0; |
79e53945 JB |
8869 | } |
8870 | ||
eb14cb74 VS |
8871 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
8872 | struct intel_link_m_n *m_n) | |
8873 | { | |
8874 | struct drm_device *dev = crtc->base.dev; | |
8875 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8876 | enum pipe pipe = crtc->pipe; | |
8877 | ||
8878 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
8879 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
8880 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
8881 | & ~TU_SIZE_MASK; | |
8882 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
8883 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
8884 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8885 | } | |
8886 | ||
8887 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
8888 | enum transcoder transcoder, | |
b95af8be VK |
8889 | struct intel_link_m_n *m_n, |
8890 | struct intel_link_m_n *m2_n2) | |
72419203 DV |
8891 | { |
8892 | struct drm_device *dev = crtc->base.dev; | |
8893 | struct drm_i915_private *dev_priv = dev->dev_private; | |
eb14cb74 | 8894 | enum pipe pipe = crtc->pipe; |
72419203 | 8895 | |
eb14cb74 VS |
8896 | if (INTEL_INFO(dev)->gen >= 5) { |
8897 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
8898 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
8899 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
8900 | & ~TU_SIZE_MASK; | |
8901 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
8902 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
8903 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
b95af8be VK |
8904 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
8905 | * gen < 8) and if DRRS is supported (to make sure the | |
8906 | * registers are not unnecessarily read). | |
8907 | */ | |
8908 | if (m2_n2 && INTEL_INFO(dev)->gen < 8 && | |
6e3c9717 | 8909 | crtc->config->has_drrs) { |
b95af8be VK |
8910 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); |
8911 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
8912 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
8913 | & ~TU_SIZE_MASK; | |
8914 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
8915 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
8916 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8917 | } | |
eb14cb74 VS |
8918 | } else { |
8919 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
8920 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
8921 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
8922 | & ~TU_SIZE_MASK; | |
8923 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
8924 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
8925 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8926 | } | |
8927 | } | |
8928 | ||
8929 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
5cec258b | 8930 | struct intel_crtc_state *pipe_config) |
eb14cb74 | 8931 | { |
681a8504 | 8932 | if (pipe_config->has_pch_encoder) |
eb14cb74 VS |
8933 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
8934 | else | |
8935 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
8936 | &pipe_config->dp_m_n, |
8937 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 8938 | } |
72419203 | 8939 | |
eb14cb74 | 8940 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5cec258b | 8941 | struct intel_crtc_state *pipe_config) |
eb14cb74 VS |
8942 | { |
8943 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 8944 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
8945 | } |
8946 | ||
bd2e244f | 8947 | static void skylake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 8948 | struct intel_crtc_state *pipe_config) |
bd2e244f JB |
8949 | { |
8950 | struct drm_device *dev = crtc->base.dev; | |
8951 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a1b2278e CK |
8952 | struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; |
8953 | uint32_t ps_ctrl = 0; | |
8954 | int id = -1; | |
8955 | int i; | |
bd2e244f | 8956 | |
a1b2278e CK |
8957 | /* find scaler attached to this pipe */ |
8958 | for (i = 0; i < crtc->num_scalers; i++) { | |
8959 | ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); | |
8960 | if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) { | |
8961 | id = i; | |
8962 | pipe_config->pch_pfit.enabled = true; | |
8963 | pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); | |
8964 | pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); | |
8965 | break; | |
8966 | } | |
8967 | } | |
bd2e244f | 8968 | |
a1b2278e CK |
8969 | scaler_state->scaler_id = id; |
8970 | if (id >= 0) { | |
8971 | scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); | |
8972 | } else { | |
8973 | scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
bd2e244f JB |
8974 | } |
8975 | } | |
8976 | ||
5724dbd1 DL |
8977 | static void |
8978 | skylake_get_initial_plane_config(struct intel_crtc *crtc, | |
8979 | struct intel_initial_plane_config *plane_config) | |
bc8d7dff DL |
8980 | { |
8981 | struct drm_device *dev = crtc->base.dev; | |
8982 | struct drm_i915_private *dev_priv = dev->dev_private; | |
40f46283 | 8983 | u32 val, base, offset, stride_mult, tiling; |
bc8d7dff DL |
8984 | int pipe = crtc->pipe; |
8985 | int fourcc, pixel_format; | |
6761dd31 | 8986 | unsigned int aligned_height; |
bc8d7dff | 8987 | struct drm_framebuffer *fb; |
1b842c89 | 8988 | struct intel_framebuffer *intel_fb; |
bc8d7dff | 8989 | |
d9806c9f | 8990 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8991 | if (!intel_fb) { |
bc8d7dff DL |
8992 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8993 | return; | |
8994 | } | |
8995 | ||
1b842c89 DL |
8996 | fb = &intel_fb->base; |
8997 | ||
bc8d7dff | 8998 | val = I915_READ(PLANE_CTL(pipe, 0)); |
42a7b088 DL |
8999 | if (!(val & PLANE_CTL_ENABLE)) |
9000 | goto error; | |
9001 | ||
bc8d7dff DL |
9002 | pixel_format = val & PLANE_CTL_FORMAT_MASK; |
9003 | fourcc = skl_format_to_fourcc(pixel_format, | |
9004 | val & PLANE_CTL_ORDER_RGBX, | |
9005 | val & PLANE_CTL_ALPHA_MASK); | |
9006 | fb->pixel_format = fourcc; | |
9007 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
9008 | ||
40f46283 DL |
9009 | tiling = val & PLANE_CTL_TILED_MASK; |
9010 | switch (tiling) { | |
9011 | case PLANE_CTL_TILED_LINEAR: | |
9012 | fb->modifier[0] = DRM_FORMAT_MOD_NONE; | |
9013 | break; | |
9014 | case PLANE_CTL_TILED_X: | |
9015 | plane_config->tiling = I915_TILING_X; | |
9016 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
9017 | break; | |
9018 | case PLANE_CTL_TILED_Y: | |
9019 | fb->modifier[0] = I915_FORMAT_MOD_Y_TILED; | |
9020 | break; | |
9021 | case PLANE_CTL_TILED_YF: | |
9022 | fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED; | |
9023 | break; | |
9024 | default: | |
9025 | MISSING_CASE(tiling); | |
9026 | goto error; | |
9027 | } | |
9028 | ||
bc8d7dff DL |
9029 | base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; |
9030 | plane_config->base = base; | |
9031 | ||
9032 | offset = I915_READ(PLANE_OFFSET(pipe, 0)); | |
9033 | ||
9034 | val = I915_READ(PLANE_SIZE(pipe, 0)); | |
9035 | fb->height = ((val >> 16) & 0xfff) + 1; | |
9036 | fb->width = ((val >> 0) & 0x1fff) + 1; | |
9037 | ||
9038 | val = I915_READ(PLANE_STRIDE(pipe, 0)); | |
40f46283 DL |
9039 | stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0], |
9040 | fb->pixel_format); | |
bc8d7dff DL |
9041 | fb->pitches[0] = (val & 0x3ff) * stride_mult; |
9042 | ||
9043 | aligned_height = intel_fb_align_height(dev, fb->height, | |
091df6cb DV |
9044 | fb->pixel_format, |
9045 | fb->modifier[0]); | |
bc8d7dff | 9046 | |
f37b5c2b | 9047 | plane_config->size = fb->pitches[0] * aligned_height; |
bc8d7dff DL |
9048 | |
9049 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
9050 | pipe_name(pipe), fb->width, fb->height, | |
9051 | fb->bits_per_pixel, base, fb->pitches[0], | |
9052 | plane_config->size); | |
9053 | ||
2d14030b | 9054 | plane_config->fb = intel_fb; |
bc8d7dff DL |
9055 | return; |
9056 | ||
9057 | error: | |
9058 | kfree(fb); | |
9059 | } | |
9060 | ||
2fa2fe9a | 9061 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 9062 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
9063 | { |
9064 | struct drm_device *dev = crtc->base.dev; | |
9065 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9066 | uint32_t tmp; | |
9067 | ||
9068 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
9069 | ||
9070 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 9071 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
9072 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
9073 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
9074 | |
9075 | /* We currently do not free assignements of panel fitters on | |
9076 | * ivb/hsw (since we don't use the higher upscaling modes which | |
9077 | * differentiates them) so just WARN about this case for now. */ | |
9078 | if (IS_GEN7(dev)) { | |
9079 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
9080 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
9081 | } | |
2fa2fe9a | 9082 | } |
79e53945 JB |
9083 | } |
9084 | ||
5724dbd1 DL |
9085 | static void |
9086 | ironlake_get_initial_plane_config(struct intel_crtc *crtc, | |
9087 | struct intel_initial_plane_config *plane_config) | |
4c6baa59 JB |
9088 | { |
9089 | struct drm_device *dev = crtc->base.dev; | |
9090 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9091 | u32 val, base, offset; | |
aeee5a49 | 9092 | int pipe = crtc->pipe; |
4c6baa59 | 9093 | int fourcc, pixel_format; |
6761dd31 | 9094 | unsigned int aligned_height; |
b113d5ee | 9095 | struct drm_framebuffer *fb; |
1b842c89 | 9096 | struct intel_framebuffer *intel_fb; |
4c6baa59 | 9097 | |
42a7b088 DL |
9098 | val = I915_READ(DSPCNTR(pipe)); |
9099 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
9100 | return; | |
9101 | ||
d9806c9f | 9102 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9103 | if (!intel_fb) { |
4c6baa59 JB |
9104 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9105 | return; | |
9106 | } | |
9107 | ||
1b842c89 DL |
9108 | fb = &intel_fb->base; |
9109 | ||
18c5247e DV |
9110 | if (INTEL_INFO(dev)->gen >= 4) { |
9111 | if (val & DISPPLANE_TILED) { | |
49af449b | 9112 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
9113 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
9114 | } | |
9115 | } | |
4c6baa59 JB |
9116 | |
9117 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 9118 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
9119 | fb->pixel_format = fourcc; |
9120 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
4c6baa59 | 9121 | |
aeee5a49 | 9122 | base = I915_READ(DSPSURF(pipe)) & 0xfffff000; |
4c6baa59 | 9123 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
aeee5a49 | 9124 | offset = I915_READ(DSPOFFSET(pipe)); |
4c6baa59 | 9125 | } else { |
49af449b | 9126 | if (plane_config->tiling) |
aeee5a49 | 9127 | offset = I915_READ(DSPTILEOFF(pipe)); |
4c6baa59 | 9128 | else |
aeee5a49 | 9129 | offset = I915_READ(DSPLINOFF(pipe)); |
4c6baa59 JB |
9130 | } |
9131 | plane_config->base = base; | |
9132 | ||
9133 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
9134 | fb->width = ((val >> 16) & 0xfff) + 1; |
9135 | fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
9136 | |
9137 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 9138 | fb->pitches[0] = val & 0xffffffc0; |
4c6baa59 | 9139 | |
b113d5ee | 9140 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
9141 | fb->pixel_format, |
9142 | fb->modifier[0]); | |
4c6baa59 | 9143 | |
f37b5c2b | 9144 | plane_config->size = fb->pitches[0] * aligned_height; |
4c6baa59 | 9145 | |
2844a921 DL |
9146 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
9147 | pipe_name(pipe), fb->width, fb->height, | |
9148 | fb->bits_per_pixel, base, fb->pitches[0], | |
9149 | plane_config->size); | |
b113d5ee | 9150 | |
2d14030b | 9151 | plane_config->fb = intel_fb; |
4c6baa59 JB |
9152 | } |
9153 | ||
0e8ffe1b | 9154 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9155 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
9156 | { |
9157 | struct drm_device *dev = crtc->base.dev; | |
9158 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9159 | uint32_t tmp; | |
9160 | ||
f458ebbc DV |
9161 | if (!intel_display_power_is_enabled(dev_priv, |
9162 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
930e8c9e PZ |
9163 | return false; |
9164 | ||
e143a21c | 9165 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 9166 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 9167 | |
0e8ffe1b DV |
9168 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
9169 | if (!(tmp & PIPECONF_ENABLE)) | |
9170 | return false; | |
9171 | ||
42571aef VS |
9172 | switch (tmp & PIPECONF_BPC_MASK) { |
9173 | case PIPECONF_6BPC: | |
9174 | pipe_config->pipe_bpp = 18; | |
9175 | break; | |
9176 | case PIPECONF_8BPC: | |
9177 | pipe_config->pipe_bpp = 24; | |
9178 | break; | |
9179 | case PIPECONF_10BPC: | |
9180 | pipe_config->pipe_bpp = 30; | |
9181 | break; | |
9182 | case PIPECONF_12BPC: | |
9183 | pipe_config->pipe_bpp = 36; | |
9184 | break; | |
9185 | default: | |
9186 | break; | |
9187 | } | |
9188 | ||
b5a9fa09 DV |
9189 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
9190 | pipe_config->limited_color_range = true; | |
9191 | ||
ab9412ba | 9192 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 DV |
9193 | struct intel_shared_dpll *pll; |
9194 | ||
88adfff1 DV |
9195 | pipe_config->has_pch_encoder = true; |
9196 | ||
627eb5a3 DV |
9197 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
9198 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9199 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
9200 | |
9201 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 9202 | |
c0d43d62 | 9203 | if (HAS_PCH_IBX(dev_priv->dev)) { |
d94ab068 DV |
9204 | pipe_config->shared_dpll = |
9205 | (enum intel_dpll_id) crtc->pipe; | |
c0d43d62 DV |
9206 | } else { |
9207 | tmp = I915_READ(PCH_DPLL_SEL); | |
9208 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
9209 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; | |
9210 | else | |
9211 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; | |
9212 | } | |
66e985c0 DV |
9213 | |
9214 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
9215 | ||
9216 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
9217 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
9218 | |
9219 | tmp = pipe_config->dpll_hw_state.dpll; | |
9220 | pipe_config->pixel_multiplier = | |
9221 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
9222 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
9223 | |
9224 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
9225 | } else { |
9226 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
9227 | } |
9228 | ||
1bd1bd80 DV |
9229 | intel_get_pipe_timings(crtc, pipe_config); |
9230 | ||
2fa2fe9a DV |
9231 | ironlake_get_pfit_config(crtc, pipe_config); |
9232 | ||
0e8ffe1b DV |
9233 | return true; |
9234 | } | |
9235 | ||
be256dc7 PZ |
9236 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
9237 | { | |
9238 | struct drm_device *dev = dev_priv->dev; | |
be256dc7 | 9239 | struct intel_crtc *crtc; |
be256dc7 | 9240 | |
d3fcc808 | 9241 | for_each_intel_crtc(dev, crtc) |
e2c719b7 | 9242 | I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
9243 | pipe_name(crtc->pipe)); |
9244 | ||
e2c719b7 RC |
9245 | I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
9246 | I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); | |
9247 | I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); | |
9248 | I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
9249 | I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); | |
9250 | I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, | |
be256dc7 | 9251 | "CPU PWM1 enabled\n"); |
c5107b87 | 9252 | if (IS_HASWELL(dev)) |
e2c719b7 | 9253 | I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
c5107b87 | 9254 | "CPU PWM2 enabled\n"); |
e2c719b7 | 9255 | I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
be256dc7 | 9256 | "PCH PWM1 enabled\n"); |
e2c719b7 | 9257 | I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
be256dc7 | 9258 | "Utility pin enabled\n"); |
e2c719b7 | 9259 | I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
be256dc7 | 9260 | |
9926ada1 PZ |
9261 | /* |
9262 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
9263 | * interrupts remain enabled. We used to check for that, but since it's | |
9264 | * gen-specific and since we only disable LCPLL after we fully disable | |
9265 | * the interrupts, the check below should be enough. | |
9266 | */ | |
e2c719b7 | 9267 | I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
be256dc7 PZ |
9268 | } |
9269 | ||
9ccd5aeb PZ |
9270 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
9271 | { | |
9272 | struct drm_device *dev = dev_priv->dev; | |
9273 | ||
9274 | if (IS_HASWELL(dev)) | |
9275 | return I915_READ(D_COMP_HSW); | |
9276 | else | |
9277 | return I915_READ(D_COMP_BDW); | |
9278 | } | |
9279 | ||
3c4c9b81 PZ |
9280 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
9281 | { | |
9282 | struct drm_device *dev = dev_priv->dev; | |
9283 | ||
9284 | if (IS_HASWELL(dev)) { | |
9285 | mutex_lock(&dev_priv->rps.hw_lock); | |
9286 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
9287 | val)) | |
f475dadf | 9288 | DRM_ERROR("Failed to write to D_COMP\n"); |
3c4c9b81 PZ |
9289 | mutex_unlock(&dev_priv->rps.hw_lock); |
9290 | } else { | |
9ccd5aeb PZ |
9291 | I915_WRITE(D_COMP_BDW, val); |
9292 | POSTING_READ(D_COMP_BDW); | |
3c4c9b81 | 9293 | } |
be256dc7 PZ |
9294 | } |
9295 | ||
9296 | /* | |
9297 | * This function implements pieces of two sequences from BSpec: | |
9298 | * - Sequence for display software to disable LCPLL | |
9299 | * - Sequence for display software to allow package C8+ | |
9300 | * The steps implemented here are just the steps that actually touch the LCPLL | |
9301 | * register. Callers should take care of disabling all the display engine | |
9302 | * functions, doing the mode unset, fixing interrupts, etc. | |
9303 | */ | |
6ff58d53 PZ |
9304 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
9305 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
9306 | { |
9307 | uint32_t val; | |
9308 | ||
9309 | assert_can_disable_lcpll(dev_priv); | |
9310 | ||
9311 | val = I915_READ(LCPLL_CTL); | |
9312 | ||
9313 | if (switch_to_fclk) { | |
9314 | val |= LCPLL_CD_SOURCE_FCLK; | |
9315 | I915_WRITE(LCPLL_CTL, val); | |
9316 | ||
9317 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
9318 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
9319 | DRM_ERROR("Switching to FCLK failed\n"); | |
9320 | ||
9321 | val = I915_READ(LCPLL_CTL); | |
9322 | } | |
9323 | ||
9324 | val |= LCPLL_PLL_DISABLE; | |
9325 | I915_WRITE(LCPLL_CTL, val); | |
9326 | POSTING_READ(LCPLL_CTL); | |
9327 | ||
9328 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) | |
9329 | DRM_ERROR("LCPLL still locked\n"); | |
9330 | ||
9ccd5aeb | 9331 | val = hsw_read_dcomp(dev_priv); |
be256dc7 | 9332 | val |= D_COMP_COMP_DISABLE; |
3c4c9b81 | 9333 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9334 | ndelay(100); |
9335 | ||
9ccd5aeb PZ |
9336 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
9337 | 1)) | |
be256dc7 PZ |
9338 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
9339 | ||
9340 | if (allow_power_down) { | |
9341 | val = I915_READ(LCPLL_CTL); | |
9342 | val |= LCPLL_POWER_DOWN_ALLOW; | |
9343 | I915_WRITE(LCPLL_CTL, val); | |
9344 | POSTING_READ(LCPLL_CTL); | |
9345 | } | |
9346 | } | |
9347 | ||
9348 | /* | |
9349 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
9350 | * source. | |
9351 | */ | |
6ff58d53 | 9352 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
9353 | { |
9354 | uint32_t val; | |
9355 | ||
9356 | val = I915_READ(LCPLL_CTL); | |
9357 | ||
9358 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
9359 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
9360 | return; | |
9361 | ||
a8a8bd54 PZ |
9362 | /* |
9363 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
9364 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
a8a8bd54 | 9365 | */ |
59bad947 | 9366 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
215733fa | 9367 | |
be256dc7 PZ |
9368 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
9369 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
9370 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 9371 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
9372 | } |
9373 | ||
9ccd5aeb | 9374 | val = hsw_read_dcomp(dev_priv); |
be256dc7 PZ |
9375 | val |= D_COMP_COMP_FORCE; |
9376 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 9377 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9378 | |
9379 | val = I915_READ(LCPLL_CTL); | |
9380 | val &= ~LCPLL_PLL_DISABLE; | |
9381 | I915_WRITE(LCPLL_CTL, val); | |
9382 | ||
9383 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) | |
9384 | DRM_ERROR("LCPLL not locked yet\n"); | |
9385 | ||
9386 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
9387 | val = I915_READ(LCPLL_CTL); | |
9388 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9389 | I915_WRITE(LCPLL_CTL, val); | |
9390 | ||
9391 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
9392 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
9393 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
9394 | } | |
215733fa | 9395 | |
59bad947 | 9396 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
b6283055 | 9397 | intel_update_cdclk(dev_priv->dev); |
be256dc7 PZ |
9398 | } |
9399 | ||
765dab67 PZ |
9400 | /* |
9401 | * Package states C8 and deeper are really deep PC states that can only be | |
9402 | * reached when all the devices on the system allow it, so even if the graphics | |
9403 | * device allows PC8+, it doesn't mean the system will actually get to these | |
9404 | * states. Our driver only allows PC8+ when going into runtime PM. | |
9405 | * | |
9406 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
9407 | * well is disabled and most interrupts are disabled, and these are also | |
9408 | * requirements for runtime PM. When these conditions are met, we manually do | |
9409 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
9410 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
9411 | * hang the machine. | |
9412 | * | |
9413 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
9414 | * the state of some registers, so when we come back from PC8+ we need to | |
9415 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
9416 | * need to take care of the registers kept by RC6. Notice that this happens even | |
9417 | * if we don't put the device in PCI D3 state (which is what currently happens | |
9418 | * because of the runtime PM support). | |
9419 | * | |
9420 | * For more, read "Display Sequences for Package C8" on the hardware | |
9421 | * documentation. | |
9422 | */ | |
a14cb6fc | 9423 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 9424 | { |
c67a470b PZ |
9425 | struct drm_device *dev = dev_priv->dev; |
9426 | uint32_t val; | |
9427 | ||
c67a470b PZ |
9428 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
9429 | ||
c2699524 | 9430 | if (HAS_PCH_LPT_LP(dev)) { |
c67a470b PZ |
9431 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
9432 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
9433 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9434 | } | |
9435 | ||
9436 | lpt_disable_clkout_dp(dev); | |
c67a470b PZ |
9437 | hsw_disable_lcpll(dev_priv, true, true); |
9438 | } | |
9439 | ||
a14cb6fc | 9440 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b PZ |
9441 | { |
9442 | struct drm_device *dev = dev_priv->dev; | |
9443 | uint32_t val; | |
9444 | ||
c67a470b PZ |
9445 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
9446 | ||
9447 | hsw_restore_lcpll(dev_priv); | |
c67a470b PZ |
9448 | lpt_init_pch_refclk(dev); |
9449 | ||
c2699524 | 9450 | if (HAS_PCH_LPT_LP(dev)) { |
c67a470b PZ |
9451 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
9452 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
9453 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9454 | } | |
9455 | ||
9456 | intel_prepare_ddi(dev); | |
c67a470b PZ |
9457 | } |
9458 | ||
27c329ed | 9459 | static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
f8437dd1 | 9460 | { |
a821fc46 | 9461 | struct drm_device *dev = old_state->dev; |
27c329ed | 9462 | unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk; |
f8437dd1 | 9463 | |
27c329ed | 9464 | broxton_set_cdclk(dev, req_cdclk); |
f8437dd1 VK |
9465 | } |
9466 | ||
b432e5cf | 9467 | /* compute the max rate for new configuration */ |
27c329ed | 9468 | static int ilk_max_pixel_rate(struct drm_atomic_state *state) |
b432e5cf | 9469 | { |
b432e5cf | 9470 | struct intel_crtc *intel_crtc; |
27c329ed | 9471 | struct intel_crtc_state *crtc_state; |
b432e5cf | 9472 | int max_pixel_rate = 0; |
b432e5cf | 9473 | |
27c329ed ML |
9474 | for_each_intel_crtc(state->dev, intel_crtc) { |
9475 | int pixel_rate; | |
9476 | ||
9477 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); | |
9478 | if (IS_ERR(crtc_state)) | |
9479 | return PTR_ERR(crtc_state); | |
9480 | ||
9481 | if (!crtc_state->base.enable) | |
b432e5cf VS |
9482 | continue; |
9483 | ||
27c329ed | 9484 | pixel_rate = ilk_pipe_pixel_rate(crtc_state); |
b432e5cf VS |
9485 | |
9486 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
27c329ed | 9487 | if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled) |
b432e5cf VS |
9488 | pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); |
9489 | ||
9490 | max_pixel_rate = max(max_pixel_rate, pixel_rate); | |
9491 | } | |
9492 | ||
9493 | return max_pixel_rate; | |
9494 | } | |
9495 | ||
9496 | static void broadwell_set_cdclk(struct drm_device *dev, int cdclk) | |
9497 | { | |
9498 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9499 | uint32_t val, data; | |
9500 | int ret; | |
9501 | ||
9502 | if (WARN((I915_READ(LCPLL_CTL) & | |
9503 | (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | | |
9504 | LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | | |
9505 | LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | | |
9506 | LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, | |
9507 | "trying to change cdclk frequency with cdclk not enabled\n")) | |
9508 | return; | |
9509 | ||
9510 | mutex_lock(&dev_priv->rps.hw_lock); | |
9511 | ret = sandybridge_pcode_write(dev_priv, | |
9512 | BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); | |
9513 | mutex_unlock(&dev_priv->rps.hw_lock); | |
9514 | if (ret) { | |
9515 | DRM_ERROR("failed to inform pcode about cdclk change\n"); | |
9516 | return; | |
9517 | } | |
9518 | ||
9519 | val = I915_READ(LCPLL_CTL); | |
9520 | val |= LCPLL_CD_SOURCE_FCLK; | |
9521 | I915_WRITE(LCPLL_CTL, val); | |
9522 | ||
9523 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
9524 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
9525 | DRM_ERROR("Switching to FCLK failed\n"); | |
9526 | ||
9527 | val = I915_READ(LCPLL_CTL); | |
9528 | val &= ~LCPLL_CLK_FREQ_MASK; | |
9529 | ||
9530 | switch (cdclk) { | |
9531 | case 450000: | |
9532 | val |= LCPLL_CLK_FREQ_450; | |
9533 | data = 0; | |
9534 | break; | |
9535 | case 540000: | |
9536 | val |= LCPLL_CLK_FREQ_54O_BDW; | |
9537 | data = 1; | |
9538 | break; | |
9539 | case 337500: | |
9540 | val |= LCPLL_CLK_FREQ_337_5_BDW; | |
9541 | data = 2; | |
9542 | break; | |
9543 | case 675000: | |
9544 | val |= LCPLL_CLK_FREQ_675_BDW; | |
9545 | data = 3; | |
9546 | break; | |
9547 | default: | |
9548 | WARN(1, "invalid cdclk frequency\n"); | |
9549 | return; | |
9550 | } | |
9551 | ||
9552 | I915_WRITE(LCPLL_CTL, val); | |
9553 | ||
9554 | val = I915_READ(LCPLL_CTL); | |
9555 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9556 | I915_WRITE(LCPLL_CTL, val); | |
9557 | ||
9558 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
9559 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
9560 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
9561 | ||
9562 | mutex_lock(&dev_priv->rps.hw_lock); | |
9563 | sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data); | |
9564 | mutex_unlock(&dev_priv->rps.hw_lock); | |
9565 | ||
9566 | intel_update_cdclk(dev); | |
9567 | ||
9568 | WARN(cdclk != dev_priv->cdclk_freq, | |
9569 | "cdclk requested %d kHz but got %d kHz\n", | |
9570 | cdclk, dev_priv->cdclk_freq); | |
9571 | } | |
9572 | ||
27c329ed | 9573 | static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state) |
b432e5cf | 9574 | { |
27c329ed ML |
9575 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
9576 | int max_pixclk = ilk_max_pixel_rate(state); | |
b432e5cf VS |
9577 | int cdclk; |
9578 | ||
9579 | /* | |
9580 | * FIXME should also account for plane ratio | |
9581 | * once 64bpp pixel formats are supported. | |
9582 | */ | |
27c329ed | 9583 | if (max_pixclk > 540000) |
b432e5cf | 9584 | cdclk = 675000; |
27c329ed | 9585 | else if (max_pixclk > 450000) |
b432e5cf | 9586 | cdclk = 540000; |
27c329ed | 9587 | else if (max_pixclk > 337500) |
b432e5cf VS |
9588 | cdclk = 450000; |
9589 | else | |
9590 | cdclk = 337500; | |
9591 | ||
9592 | /* | |
9593 | * FIXME move the cdclk caclulation to | |
9594 | * compute_config() so we can fail gracegully. | |
9595 | */ | |
9596 | if (cdclk > dev_priv->max_cdclk_freq) { | |
9597 | DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n", | |
9598 | cdclk, dev_priv->max_cdclk_freq); | |
9599 | cdclk = dev_priv->max_cdclk_freq; | |
9600 | } | |
9601 | ||
27c329ed | 9602 | to_intel_atomic_state(state)->cdclk = cdclk; |
b432e5cf VS |
9603 | |
9604 | return 0; | |
9605 | } | |
9606 | ||
27c329ed | 9607 | static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
b432e5cf | 9608 | { |
27c329ed ML |
9609 | struct drm_device *dev = old_state->dev; |
9610 | unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk; | |
b432e5cf | 9611 | |
27c329ed | 9612 | broadwell_set_cdclk(dev, req_cdclk); |
b432e5cf VS |
9613 | } |
9614 | ||
190f68c5 ACO |
9615 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, |
9616 | struct intel_crtc_state *crtc_state) | |
09b4ddf9 | 9617 | { |
190f68c5 | 9618 | if (!intel_ddi_pll_select(crtc, crtc_state)) |
6441ab5f | 9619 | return -EINVAL; |
716c2e55 | 9620 | |
c7653199 | 9621 | crtc->lowfreq_avail = false; |
644cef34 | 9622 | |
c8f7a0db | 9623 | return 0; |
79e53945 JB |
9624 | } |
9625 | ||
3760b59c S |
9626 | static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, |
9627 | enum port port, | |
9628 | struct intel_crtc_state *pipe_config) | |
9629 | { | |
9630 | switch (port) { | |
9631 | case PORT_A: | |
9632 | pipe_config->ddi_pll_sel = SKL_DPLL0; | |
9633 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; | |
9634 | break; | |
9635 | case PORT_B: | |
9636 | pipe_config->ddi_pll_sel = SKL_DPLL1; | |
9637 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; | |
9638 | break; | |
9639 | case PORT_C: | |
9640 | pipe_config->ddi_pll_sel = SKL_DPLL2; | |
9641 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; | |
9642 | break; | |
9643 | default: | |
9644 | DRM_ERROR("Incorrect port type\n"); | |
9645 | } | |
9646 | } | |
9647 | ||
96b7dfb7 S |
9648 | static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, |
9649 | enum port port, | |
5cec258b | 9650 | struct intel_crtc_state *pipe_config) |
96b7dfb7 | 9651 | { |
3148ade7 | 9652 | u32 temp, dpll_ctl1; |
96b7dfb7 S |
9653 | |
9654 | temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); | |
9655 | pipe_config->ddi_pll_sel = temp >> (port * 3 + 1); | |
9656 | ||
9657 | switch (pipe_config->ddi_pll_sel) { | |
3148ade7 DL |
9658 | case SKL_DPLL0: |
9659 | /* | |
9660 | * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part | |
9661 | * of the shared DPLL framework and thus needs to be read out | |
9662 | * separately | |
9663 | */ | |
9664 | dpll_ctl1 = I915_READ(DPLL_CTRL1); | |
9665 | pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f; | |
9666 | break; | |
96b7dfb7 S |
9667 | case SKL_DPLL1: |
9668 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; | |
9669 | break; | |
9670 | case SKL_DPLL2: | |
9671 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; | |
9672 | break; | |
9673 | case SKL_DPLL3: | |
9674 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; | |
9675 | break; | |
96b7dfb7 S |
9676 | } |
9677 | } | |
9678 | ||
7d2c8175 DL |
9679 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
9680 | enum port port, | |
5cec258b | 9681 | struct intel_crtc_state *pipe_config) |
7d2c8175 DL |
9682 | { |
9683 | pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); | |
9684 | ||
9685 | switch (pipe_config->ddi_pll_sel) { | |
9686 | case PORT_CLK_SEL_WRPLL1: | |
9687 | pipe_config->shared_dpll = DPLL_ID_WRPLL1; | |
9688 | break; | |
9689 | case PORT_CLK_SEL_WRPLL2: | |
9690 | pipe_config->shared_dpll = DPLL_ID_WRPLL2; | |
9691 | break; | |
9692 | } | |
9693 | } | |
9694 | ||
26804afd | 9695 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
5cec258b | 9696 | struct intel_crtc_state *pipe_config) |
26804afd DV |
9697 | { |
9698 | struct drm_device *dev = crtc->base.dev; | |
9699 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d452c5b6 | 9700 | struct intel_shared_dpll *pll; |
26804afd DV |
9701 | enum port port; |
9702 | uint32_t tmp; | |
9703 | ||
9704 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
9705 | ||
9706 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
9707 | ||
96b7dfb7 S |
9708 | if (IS_SKYLAKE(dev)) |
9709 | skylake_get_ddi_pll(dev_priv, port, pipe_config); | |
3760b59c S |
9710 | else if (IS_BROXTON(dev)) |
9711 | bxt_get_ddi_pll(dev_priv, port, pipe_config); | |
96b7dfb7 S |
9712 | else |
9713 | haswell_get_ddi_pll(dev_priv, port, pipe_config); | |
9cd86933 | 9714 | |
d452c5b6 DV |
9715 | if (pipe_config->shared_dpll >= 0) { |
9716 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
9717 | ||
9718 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
9719 | &pipe_config->dpll_hw_state)); | |
9720 | } | |
9721 | ||
26804afd DV |
9722 | /* |
9723 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
9724 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
9725 | * the PCH transcoder is on. | |
9726 | */ | |
ca370455 DL |
9727 | if (INTEL_INFO(dev)->gen < 9 && |
9728 | (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { | |
26804afd DV |
9729 | pipe_config->has_pch_encoder = true; |
9730 | ||
9731 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
9732 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9733 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
9734 | ||
9735 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
9736 | } | |
9737 | } | |
9738 | ||
0e8ffe1b | 9739 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9740 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
9741 | { |
9742 | struct drm_device *dev = crtc->base.dev; | |
9743 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa2fe9a | 9744 | enum intel_display_power_domain pfit_domain; |
0e8ffe1b DV |
9745 | uint32_t tmp; |
9746 | ||
f458ebbc | 9747 | if (!intel_display_power_is_enabled(dev_priv, |
b5482bd0 ID |
9748 | POWER_DOMAIN_PIPE(crtc->pipe))) |
9749 | return false; | |
9750 | ||
e143a21c | 9751 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 DV |
9752 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
9753 | ||
eccb140b DV |
9754 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
9755 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
9756 | enum pipe trans_edp_pipe; | |
9757 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
9758 | default: | |
9759 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
9760 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
9761 | case TRANS_DDI_EDP_INPUT_A_ON: | |
9762 | trans_edp_pipe = PIPE_A; | |
9763 | break; | |
9764 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
9765 | trans_edp_pipe = PIPE_B; | |
9766 | break; | |
9767 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
9768 | trans_edp_pipe = PIPE_C; | |
9769 | break; | |
9770 | } | |
9771 | ||
9772 | if (trans_edp_pipe == crtc->pipe) | |
9773 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
9774 | } | |
9775 | ||
f458ebbc | 9776 | if (!intel_display_power_is_enabled(dev_priv, |
eccb140b | 9777 | POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) |
2bfce950 PZ |
9778 | return false; |
9779 | ||
eccb140b | 9780 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
0e8ffe1b DV |
9781 | if (!(tmp & PIPECONF_ENABLE)) |
9782 | return false; | |
9783 | ||
26804afd | 9784 | haswell_get_ddi_port_state(crtc, pipe_config); |
627eb5a3 | 9785 | |
1bd1bd80 DV |
9786 | intel_get_pipe_timings(crtc, pipe_config); |
9787 | ||
a1b2278e CK |
9788 | if (INTEL_INFO(dev)->gen >= 9) { |
9789 | skl_init_scalers(dev, crtc, pipe_config); | |
9790 | } | |
9791 | ||
2fa2fe9a | 9792 | pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
af99ceda CK |
9793 | |
9794 | if (INTEL_INFO(dev)->gen >= 9) { | |
9795 | pipe_config->scaler_state.scaler_id = -1; | |
9796 | pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
9797 | } | |
9798 | ||
bd2e244f | 9799 | if (intel_display_power_is_enabled(dev_priv, pfit_domain)) { |
1c132b44 | 9800 | if (INTEL_INFO(dev)->gen >= 9) |
bd2e244f | 9801 | skylake_get_pfit_config(crtc, pipe_config); |
ff6d9f55 | 9802 | else |
1c132b44 | 9803 | ironlake_get_pfit_config(crtc, pipe_config); |
bd2e244f | 9804 | } |
88adfff1 | 9805 | |
e59150dc JB |
9806 | if (IS_HASWELL(dev)) |
9807 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && | |
9808 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 9809 | |
ebb69c95 CT |
9810 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP) { |
9811 | pipe_config->pixel_multiplier = | |
9812 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; | |
9813 | } else { | |
9814 | pipe_config->pixel_multiplier = 1; | |
9815 | } | |
6c49f241 | 9816 | |
0e8ffe1b DV |
9817 | return true; |
9818 | } | |
9819 | ||
560b85bb CW |
9820 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
9821 | { | |
9822 | struct drm_device *dev = crtc->dev; | |
9823 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9824 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
dc41c154 | 9825 | uint32_t cntl = 0, size = 0; |
560b85bb | 9826 | |
dc41c154 | 9827 | if (base) { |
3dd512fb MR |
9828 | unsigned int width = intel_crtc->base.cursor->state->crtc_w; |
9829 | unsigned int height = intel_crtc->base.cursor->state->crtc_h; | |
dc41c154 VS |
9830 | unsigned int stride = roundup_pow_of_two(width) * 4; |
9831 | ||
9832 | switch (stride) { | |
9833 | default: | |
9834 | WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n", | |
9835 | width, stride); | |
9836 | stride = 256; | |
9837 | /* fallthrough */ | |
9838 | case 256: | |
9839 | case 512: | |
9840 | case 1024: | |
9841 | case 2048: | |
9842 | break; | |
4b0e333e CW |
9843 | } |
9844 | ||
dc41c154 VS |
9845 | cntl |= CURSOR_ENABLE | |
9846 | CURSOR_GAMMA_ENABLE | | |
9847 | CURSOR_FORMAT_ARGB | | |
9848 | CURSOR_STRIDE(stride); | |
9849 | ||
9850 | size = (height << 12) | width; | |
4b0e333e | 9851 | } |
560b85bb | 9852 | |
dc41c154 VS |
9853 | if (intel_crtc->cursor_cntl != 0 && |
9854 | (intel_crtc->cursor_base != base || | |
9855 | intel_crtc->cursor_size != size || | |
9856 | intel_crtc->cursor_cntl != cntl)) { | |
9857 | /* On these chipsets we can only modify the base/size/stride | |
9858 | * whilst the cursor is disabled. | |
9859 | */ | |
9860 | I915_WRITE(_CURACNTR, 0); | |
4b0e333e | 9861 | POSTING_READ(_CURACNTR); |
dc41c154 | 9862 | intel_crtc->cursor_cntl = 0; |
4b0e333e | 9863 | } |
560b85bb | 9864 | |
99d1f387 | 9865 | if (intel_crtc->cursor_base != base) { |
9db4a9c7 | 9866 | I915_WRITE(_CURABASE, base); |
99d1f387 VS |
9867 | intel_crtc->cursor_base = base; |
9868 | } | |
4726e0b0 | 9869 | |
dc41c154 VS |
9870 | if (intel_crtc->cursor_size != size) { |
9871 | I915_WRITE(CURSIZE, size); | |
9872 | intel_crtc->cursor_size = size; | |
4b0e333e | 9873 | } |
560b85bb | 9874 | |
4b0e333e | 9875 | if (intel_crtc->cursor_cntl != cntl) { |
4b0e333e CW |
9876 | I915_WRITE(_CURACNTR, cntl); |
9877 | POSTING_READ(_CURACNTR); | |
4b0e333e | 9878 | intel_crtc->cursor_cntl = cntl; |
560b85bb | 9879 | } |
560b85bb CW |
9880 | } |
9881 | ||
560b85bb | 9882 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) |
65a21cd6 JB |
9883 | { |
9884 | struct drm_device *dev = crtc->dev; | |
9885 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9886 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9887 | int pipe = intel_crtc->pipe; | |
4b0e333e CW |
9888 | uint32_t cntl; |
9889 | ||
9890 | cntl = 0; | |
9891 | if (base) { | |
9892 | cntl = MCURSOR_GAMMA_ENABLE; | |
3dd512fb | 9893 | switch (intel_crtc->base.cursor->state->crtc_w) { |
4726e0b0 SK |
9894 | case 64: |
9895 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
9896 | break; | |
9897 | case 128: | |
9898 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
9899 | break; | |
9900 | case 256: | |
9901 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
9902 | break; | |
9903 | default: | |
3dd512fb | 9904 | MISSING_CASE(intel_crtc->base.cursor->state->crtc_w); |
4726e0b0 | 9905 | return; |
65a21cd6 | 9906 | } |
4b0e333e | 9907 | cntl |= pipe << 28; /* Connect to correct pipe */ |
47bf17a7 VS |
9908 | |
9909 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
9910 | cntl |= CURSOR_PIPE_CSC_ENABLE; | |
4b0e333e | 9911 | } |
65a21cd6 | 9912 | |
8e7d688b | 9913 | if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) |
4398ad45 VS |
9914 | cntl |= CURSOR_ROTATE_180; |
9915 | ||
4b0e333e CW |
9916 | if (intel_crtc->cursor_cntl != cntl) { |
9917 | I915_WRITE(CURCNTR(pipe), cntl); | |
9918 | POSTING_READ(CURCNTR(pipe)); | |
9919 | intel_crtc->cursor_cntl = cntl; | |
65a21cd6 | 9920 | } |
4b0e333e | 9921 | |
65a21cd6 | 9922 | /* and commit changes on next vblank */ |
5efb3e28 VS |
9923 | I915_WRITE(CURBASE(pipe), base); |
9924 | POSTING_READ(CURBASE(pipe)); | |
99d1f387 VS |
9925 | |
9926 | intel_crtc->cursor_base = base; | |
65a21cd6 JB |
9927 | } |
9928 | ||
cda4b7d3 | 9929 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f CW |
9930 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
9931 | bool on) | |
cda4b7d3 CW |
9932 | { |
9933 | struct drm_device *dev = crtc->dev; | |
9934 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9935 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9936 | int pipe = intel_crtc->pipe; | |
9b4101be ML |
9937 | struct drm_plane_state *cursor_state = crtc->cursor->state; |
9938 | int x = cursor_state->crtc_x; | |
9939 | int y = cursor_state->crtc_y; | |
d6e4db15 | 9940 | u32 base = 0, pos = 0; |
cda4b7d3 | 9941 | |
d6e4db15 | 9942 | if (on) |
cda4b7d3 | 9943 | base = intel_crtc->cursor_addr; |
cda4b7d3 | 9944 | |
6e3c9717 | 9945 | if (x >= intel_crtc->config->pipe_src_w) |
d6e4db15 VS |
9946 | base = 0; |
9947 | ||
6e3c9717 | 9948 | if (y >= intel_crtc->config->pipe_src_h) |
cda4b7d3 CW |
9949 | base = 0; |
9950 | ||
9951 | if (x < 0) { | |
9b4101be | 9952 | if (x + cursor_state->crtc_w <= 0) |
cda4b7d3 CW |
9953 | base = 0; |
9954 | ||
9955 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
9956 | x = -x; | |
9957 | } | |
9958 | pos |= x << CURSOR_X_SHIFT; | |
9959 | ||
9960 | if (y < 0) { | |
9b4101be | 9961 | if (y + cursor_state->crtc_h <= 0) |
cda4b7d3 CW |
9962 | base = 0; |
9963 | ||
9964 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
9965 | y = -y; | |
9966 | } | |
9967 | pos |= y << CURSOR_Y_SHIFT; | |
9968 | ||
4b0e333e | 9969 | if (base == 0 && intel_crtc->cursor_base == 0) |
cda4b7d3 CW |
9970 | return; |
9971 | ||
5efb3e28 VS |
9972 | I915_WRITE(CURPOS(pipe), pos); |
9973 | ||
4398ad45 VS |
9974 | /* ILK+ do this automagically */ |
9975 | if (HAS_GMCH_DISPLAY(dev) && | |
8e7d688b | 9976 | crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) { |
9b4101be ML |
9977 | base += (cursor_state->crtc_h * |
9978 | cursor_state->crtc_w - 1) * 4; | |
4398ad45 VS |
9979 | } |
9980 | ||
8ac54669 | 9981 | if (IS_845G(dev) || IS_I865G(dev)) |
5efb3e28 VS |
9982 | i845_update_cursor(crtc, base); |
9983 | else | |
9984 | i9xx_update_cursor(crtc, base); | |
cda4b7d3 CW |
9985 | } |
9986 | ||
dc41c154 VS |
9987 | static bool cursor_size_ok(struct drm_device *dev, |
9988 | uint32_t width, uint32_t height) | |
9989 | { | |
9990 | if (width == 0 || height == 0) | |
9991 | return false; | |
9992 | ||
9993 | /* | |
9994 | * 845g/865g are special in that they are only limited by | |
9995 | * the width of their cursors, the height is arbitrary up to | |
9996 | * the precision of the register. Everything else requires | |
9997 | * square cursors, limited to a few power-of-two sizes. | |
9998 | */ | |
9999 | if (IS_845G(dev) || IS_I865G(dev)) { | |
10000 | if ((width & 63) != 0) | |
10001 | return false; | |
10002 | ||
10003 | if (width > (IS_845G(dev) ? 64 : 512)) | |
10004 | return false; | |
10005 | ||
10006 | if (height > 1023) | |
10007 | return false; | |
10008 | } else { | |
10009 | switch (width | height) { | |
10010 | case 256: | |
10011 | case 128: | |
10012 | if (IS_GEN2(dev)) | |
10013 | return false; | |
10014 | case 64: | |
10015 | break; | |
10016 | default: | |
10017 | return false; | |
10018 | } | |
10019 | } | |
10020 | ||
10021 | return true; | |
10022 | } | |
10023 | ||
79e53945 | 10024 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 10025 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 10026 | { |
7203425a | 10027 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 10028 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 10029 | |
7203425a | 10030 | for (i = start; i < end; i++) { |
79e53945 JB |
10031 | intel_crtc->lut_r[i] = red[i] >> 8; |
10032 | intel_crtc->lut_g[i] = green[i] >> 8; | |
10033 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
10034 | } | |
10035 | ||
10036 | intel_crtc_load_lut(crtc); | |
10037 | } | |
10038 | ||
79e53945 JB |
10039 | /* VESA 640x480x72Hz mode to set on the pipe */ |
10040 | static struct drm_display_mode load_detect_mode = { | |
10041 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
10042 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
10043 | }; | |
10044 | ||
a8bb6818 DV |
10045 | struct drm_framebuffer * |
10046 | __intel_framebuffer_create(struct drm_device *dev, | |
10047 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10048 | struct drm_i915_gem_object *obj) | |
d2dff872 CW |
10049 | { |
10050 | struct intel_framebuffer *intel_fb; | |
10051 | int ret; | |
10052 | ||
10053 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
10054 | if (!intel_fb) { | |
6ccb81f2 | 10055 | drm_gem_object_unreference(&obj->base); |
d2dff872 CW |
10056 | return ERR_PTR(-ENOMEM); |
10057 | } | |
10058 | ||
10059 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
dd4916c5 DV |
10060 | if (ret) |
10061 | goto err; | |
d2dff872 CW |
10062 | |
10063 | return &intel_fb->base; | |
dd4916c5 | 10064 | err: |
6ccb81f2 | 10065 | drm_gem_object_unreference(&obj->base); |
dd4916c5 DV |
10066 | kfree(intel_fb); |
10067 | ||
10068 | return ERR_PTR(ret); | |
d2dff872 CW |
10069 | } |
10070 | ||
b5ea642a | 10071 | static struct drm_framebuffer * |
a8bb6818 DV |
10072 | intel_framebuffer_create(struct drm_device *dev, |
10073 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10074 | struct drm_i915_gem_object *obj) | |
10075 | { | |
10076 | struct drm_framebuffer *fb; | |
10077 | int ret; | |
10078 | ||
10079 | ret = i915_mutex_lock_interruptible(dev); | |
10080 | if (ret) | |
10081 | return ERR_PTR(ret); | |
10082 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
10083 | mutex_unlock(&dev->struct_mutex); | |
10084 | ||
10085 | return fb; | |
10086 | } | |
10087 | ||
d2dff872 CW |
10088 | static u32 |
10089 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
10090 | { | |
10091 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
10092 | return ALIGN(pitch, 64); | |
10093 | } | |
10094 | ||
10095 | static u32 | |
10096 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
10097 | { | |
10098 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 10099 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
10100 | } |
10101 | ||
10102 | static struct drm_framebuffer * | |
10103 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
10104 | struct drm_display_mode *mode, | |
10105 | int depth, int bpp) | |
10106 | { | |
10107 | struct drm_i915_gem_object *obj; | |
0fed39bd | 10108 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 CW |
10109 | |
10110 | obj = i915_gem_alloc_object(dev, | |
10111 | intel_framebuffer_size_for_mode(mode, bpp)); | |
10112 | if (obj == NULL) | |
10113 | return ERR_PTR(-ENOMEM); | |
10114 | ||
10115 | mode_cmd.width = mode->hdisplay; | |
10116 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
10117 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
10118 | bpp); | |
5ca0c34a | 10119 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 CW |
10120 | |
10121 | return intel_framebuffer_create(dev, &mode_cmd, obj); | |
10122 | } | |
10123 | ||
10124 | static struct drm_framebuffer * | |
10125 | mode_fits_in_fbdev(struct drm_device *dev, | |
10126 | struct drm_display_mode *mode) | |
10127 | { | |
0695726e | 10128 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
d2dff872 CW |
10129 | struct drm_i915_private *dev_priv = dev->dev_private; |
10130 | struct drm_i915_gem_object *obj; | |
10131 | struct drm_framebuffer *fb; | |
10132 | ||
4c0e5528 | 10133 | if (!dev_priv->fbdev) |
d2dff872 CW |
10134 | return NULL; |
10135 | ||
4c0e5528 | 10136 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
10137 | return NULL; |
10138 | ||
4c0e5528 DV |
10139 | obj = dev_priv->fbdev->fb->obj; |
10140 | BUG_ON(!obj); | |
10141 | ||
8bcd4553 | 10142 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
10143 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
10144 | fb->bits_per_pixel)) | |
d2dff872 CW |
10145 | return NULL; |
10146 | ||
01f2c773 | 10147 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
10148 | return NULL; |
10149 | ||
10150 | return fb; | |
4520f53a DV |
10151 | #else |
10152 | return NULL; | |
10153 | #endif | |
d2dff872 CW |
10154 | } |
10155 | ||
d3a40d1b ACO |
10156 | static int intel_modeset_setup_plane_state(struct drm_atomic_state *state, |
10157 | struct drm_crtc *crtc, | |
10158 | struct drm_display_mode *mode, | |
10159 | struct drm_framebuffer *fb, | |
10160 | int x, int y) | |
10161 | { | |
10162 | struct drm_plane_state *plane_state; | |
10163 | int hdisplay, vdisplay; | |
10164 | int ret; | |
10165 | ||
10166 | plane_state = drm_atomic_get_plane_state(state, crtc->primary); | |
10167 | if (IS_ERR(plane_state)) | |
10168 | return PTR_ERR(plane_state); | |
10169 | ||
10170 | if (mode) | |
10171 | drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay); | |
10172 | else | |
10173 | hdisplay = vdisplay = 0; | |
10174 | ||
10175 | ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL); | |
10176 | if (ret) | |
10177 | return ret; | |
10178 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
10179 | plane_state->crtc_x = 0; | |
10180 | plane_state->crtc_y = 0; | |
10181 | plane_state->crtc_w = hdisplay; | |
10182 | plane_state->crtc_h = vdisplay; | |
10183 | plane_state->src_x = x << 16; | |
10184 | plane_state->src_y = y << 16; | |
10185 | plane_state->src_w = hdisplay << 16; | |
10186 | plane_state->src_h = vdisplay << 16; | |
10187 | ||
10188 | return 0; | |
10189 | } | |
10190 | ||
d2434ab7 | 10191 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 10192 | struct drm_display_mode *mode, |
51fd371b RC |
10193 | struct intel_load_detect_pipe *old, |
10194 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
10195 | { |
10196 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
10197 | struct intel_encoder *intel_encoder = |
10198 | intel_attached_encoder(connector); | |
79e53945 | 10199 | struct drm_crtc *possible_crtc; |
4ef69c7a | 10200 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
10201 | struct drm_crtc *crtc = NULL; |
10202 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 10203 | struct drm_framebuffer *fb; |
51fd371b | 10204 | struct drm_mode_config *config = &dev->mode_config; |
83a57153 | 10205 | struct drm_atomic_state *state = NULL; |
944b0c76 | 10206 | struct drm_connector_state *connector_state; |
4be07317 | 10207 | struct intel_crtc_state *crtc_state; |
51fd371b | 10208 | int ret, i = -1; |
79e53945 | 10209 | |
d2dff872 | 10210 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10211 | connector->base.id, connector->name, |
8e329a03 | 10212 | encoder->base.id, encoder->name); |
d2dff872 | 10213 | |
51fd371b RC |
10214 | retry: |
10215 | ret = drm_modeset_lock(&config->connection_mutex, ctx); | |
10216 | if (ret) | |
ad3c558f | 10217 | goto fail; |
6e9f798d | 10218 | |
79e53945 JB |
10219 | /* |
10220 | * Algorithm gets a little messy: | |
7a5e4805 | 10221 | * |
79e53945 JB |
10222 | * - if the connector already has an assigned crtc, use it (but make |
10223 | * sure it's on first) | |
7a5e4805 | 10224 | * |
79e53945 JB |
10225 | * - try to find the first unused crtc that can drive this connector, |
10226 | * and use that if we find one | |
79e53945 JB |
10227 | */ |
10228 | ||
10229 | /* See if we already have a CRTC for this connector */ | |
10230 | if (encoder->crtc) { | |
10231 | crtc = encoder->crtc; | |
8261b191 | 10232 | |
51fd371b | 10233 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
4d02e2de | 10234 | if (ret) |
ad3c558f | 10235 | goto fail; |
4d02e2de | 10236 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
51fd371b | 10237 | if (ret) |
ad3c558f | 10238 | goto fail; |
7b24056b | 10239 | |
24218aac | 10240 | old->dpms_mode = connector->dpms; |
8261b191 CW |
10241 | old->load_detect_temp = false; |
10242 | ||
10243 | /* Make sure the crtc and connector are running */ | |
24218aac DV |
10244 | if (connector->dpms != DRM_MODE_DPMS_ON) |
10245 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); | |
8261b191 | 10246 | |
7173188d | 10247 | return true; |
79e53945 JB |
10248 | } |
10249 | ||
10250 | /* Find an unused one (if possible) */ | |
70e1e0ec | 10251 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
10252 | i++; |
10253 | if (!(encoder->possible_crtcs & (1 << i))) | |
10254 | continue; | |
83d65738 | 10255 | if (possible_crtc->state->enable) |
a459249c | 10256 | continue; |
a459249c VS |
10257 | |
10258 | crtc = possible_crtc; | |
10259 | break; | |
79e53945 JB |
10260 | } |
10261 | ||
10262 | /* | |
10263 | * If we didn't find an unused CRTC, don't use any. | |
10264 | */ | |
10265 | if (!crtc) { | |
7173188d | 10266 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
ad3c558f | 10267 | goto fail; |
79e53945 JB |
10268 | } |
10269 | ||
51fd371b RC |
10270 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
10271 | if (ret) | |
ad3c558f | 10272 | goto fail; |
4d02e2de DV |
10273 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
10274 | if (ret) | |
ad3c558f | 10275 | goto fail; |
79e53945 JB |
10276 | |
10277 | intel_crtc = to_intel_crtc(crtc); | |
24218aac | 10278 | old->dpms_mode = connector->dpms; |
8261b191 | 10279 | old->load_detect_temp = true; |
d2dff872 | 10280 | old->release_fb = NULL; |
79e53945 | 10281 | |
83a57153 ACO |
10282 | state = drm_atomic_state_alloc(dev); |
10283 | if (!state) | |
10284 | return false; | |
10285 | ||
10286 | state->acquire_ctx = ctx; | |
10287 | ||
944b0c76 ACO |
10288 | connector_state = drm_atomic_get_connector_state(state, connector); |
10289 | if (IS_ERR(connector_state)) { | |
10290 | ret = PTR_ERR(connector_state); | |
10291 | goto fail; | |
10292 | } | |
10293 | ||
10294 | connector_state->crtc = crtc; | |
10295 | connector_state->best_encoder = &intel_encoder->base; | |
10296 | ||
4be07317 ACO |
10297 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
10298 | if (IS_ERR(crtc_state)) { | |
10299 | ret = PTR_ERR(crtc_state); | |
10300 | goto fail; | |
10301 | } | |
10302 | ||
49d6fa21 | 10303 | crtc_state->base.active = crtc_state->base.enable = true; |
4be07317 | 10304 | |
6492711d CW |
10305 | if (!mode) |
10306 | mode = &load_detect_mode; | |
79e53945 | 10307 | |
d2dff872 CW |
10308 | /* We need a framebuffer large enough to accommodate all accesses |
10309 | * that the plane may generate whilst we perform load detection. | |
10310 | * We can not rely on the fbcon either being present (we get called | |
10311 | * during its initialisation to detect all boot displays, or it may | |
10312 | * not even exist) or that it is large enough to satisfy the | |
10313 | * requested mode. | |
10314 | */ | |
94352cf9 DV |
10315 | fb = mode_fits_in_fbdev(dev, mode); |
10316 | if (fb == NULL) { | |
d2dff872 | 10317 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 DV |
10318 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
10319 | old->release_fb = fb; | |
d2dff872 CW |
10320 | } else |
10321 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 10322 | if (IS_ERR(fb)) { |
d2dff872 | 10323 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 10324 | goto fail; |
79e53945 | 10325 | } |
79e53945 | 10326 | |
d3a40d1b ACO |
10327 | ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0); |
10328 | if (ret) | |
10329 | goto fail; | |
10330 | ||
8c7b5ccb ACO |
10331 | drm_mode_copy(&crtc_state->base.mode, mode); |
10332 | ||
74c090b1 | 10333 | if (drm_atomic_commit(state)) { |
6492711d | 10334 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
d2dff872 CW |
10335 | if (old->release_fb) |
10336 | old->release_fb->funcs->destroy(old->release_fb); | |
412b61d8 | 10337 | goto fail; |
79e53945 | 10338 | } |
9128b040 | 10339 | crtc->primary->crtc = crtc; |
7173188d | 10340 | |
79e53945 | 10341 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 10342 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 10343 | return true; |
412b61d8 | 10344 | |
ad3c558f | 10345 | fail: |
e5d958ef ACO |
10346 | drm_atomic_state_free(state); |
10347 | state = NULL; | |
83a57153 | 10348 | |
51fd371b RC |
10349 | if (ret == -EDEADLK) { |
10350 | drm_modeset_backoff(ctx); | |
10351 | goto retry; | |
10352 | } | |
10353 | ||
412b61d8 | 10354 | return false; |
79e53945 JB |
10355 | } |
10356 | ||
d2434ab7 | 10357 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
10358 | struct intel_load_detect_pipe *old, |
10359 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 | 10360 | { |
83a57153 | 10361 | struct drm_device *dev = connector->dev; |
d2434ab7 DV |
10362 | struct intel_encoder *intel_encoder = |
10363 | intel_attached_encoder(connector); | |
4ef69c7a | 10364 | struct drm_encoder *encoder = &intel_encoder->base; |
7b24056b | 10365 | struct drm_crtc *crtc = encoder->crtc; |
412b61d8 | 10366 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
83a57153 | 10367 | struct drm_atomic_state *state; |
944b0c76 | 10368 | struct drm_connector_state *connector_state; |
4be07317 | 10369 | struct intel_crtc_state *crtc_state; |
d3a40d1b | 10370 | int ret; |
79e53945 | 10371 | |
d2dff872 | 10372 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10373 | connector->base.id, connector->name, |
8e329a03 | 10374 | encoder->base.id, encoder->name); |
d2dff872 | 10375 | |
8261b191 | 10376 | if (old->load_detect_temp) { |
83a57153 | 10377 | state = drm_atomic_state_alloc(dev); |
944b0c76 ACO |
10378 | if (!state) |
10379 | goto fail; | |
83a57153 ACO |
10380 | |
10381 | state->acquire_ctx = ctx; | |
10382 | ||
944b0c76 ACO |
10383 | connector_state = drm_atomic_get_connector_state(state, connector); |
10384 | if (IS_ERR(connector_state)) | |
10385 | goto fail; | |
10386 | ||
4be07317 ACO |
10387 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
10388 | if (IS_ERR(crtc_state)) | |
10389 | goto fail; | |
10390 | ||
944b0c76 ACO |
10391 | connector_state->best_encoder = NULL; |
10392 | connector_state->crtc = NULL; | |
10393 | ||
49d6fa21 | 10394 | crtc_state->base.enable = crtc_state->base.active = false; |
4be07317 | 10395 | |
d3a40d1b ACO |
10396 | ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL, |
10397 | 0, 0); | |
10398 | if (ret) | |
10399 | goto fail; | |
10400 | ||
74c090b1 | 10401 | ret = drm_atomic_commit(state); |
2bfb4627 ACO |
10402 | if (ret) |
10403 | goto fail; | |
d2dff872 | 10404 | |
36206361 DV |
10405 | if (old->release_fb) { |
10406 | drm_framebuffer_unregister_private(old->release_fb); | |
10407 | drm_framebuffer_unreference(old->release_fb); | |
10408 | } | |
d2dff872 | 10409 | |
0622a53c | 10410 | return; |
79e53945 JB |
10411 | } |
10412 | ||
c751ce4f | 10413 | /* Switch crtc and encoder back off if necessary */ |
24218aac DV |
10414 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
10415 | connector->funcs->dpms(connector, old->dpms_mode); | |
944b0c76 ACO |
10416 | |
10417 | return; | |
10418 | fail: | |
10419 | DRM_DEBUG_KMS("Couldn't release load detect pipe.\n"); | |
10420 | drm_atomic_state_free(state); | |
79e53945 JB |
10421 | } |
10422 | ||
da4a1efa | 10423 | static int i9xx_pll_refclk(struct drm_device *dev, |
5cec258b | 10424 | const struct intel_crtc_state *pipe_config) |
da4a1efa VS |
10425 | { |
10426 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10427 | u32 dpll = pipe_config->dpll_hw_state.dpll; | |
10428 | ||
10429 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 10430 | return dev_priv->vbt.lvds_ssc_freq; |
da4a1efa VS |
10431 | else if (HAS_PCH_SPLIT(dev)) |
10432 | return 120000; | |
10433 | else if (!IS_GEN2(dev)) | |
10434 | return 96000; | |
10435 | else | |
10436 | return 48000; | |
10437 | } | |
10438 | ||
79e53945 | 10439 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc | 10440 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 10441 | struct intel_crtc_state *pipe_config) |
79e53945 | 10442 | { |
f1f644dc | 10443 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 10444 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1f644dc | 10445 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 10446 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 JB |
10447 | u32 fp; |
10448 | intel_clock_t clock; | |
dccbea3b | 10449 | int port_clock; |
da4a1efa | 10450 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
10451 | |
10452 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 10453 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 10454 | else |
293623f7 | 10455 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
10456 | |
10457 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
10458 | if (IS_PINEVIEW(dev)) { |
10459 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
10460 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
10461 | } else { |
10462 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
10463 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
10464 | } | |
10465 | ||
a6c45cf0 | 10466 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
10467 | if (IS_PINEVIEW(dev)) |
10468 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
10469 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
10470 | else |
10471 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
10472 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
10473 | ||
10474 | switch (dpll & DPLL_MODE_MASK) { | |
10475 | case DPLLB_MODE_DAC_SERIAL: | |
10476 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
10477 | 5 : 10; | |
10478 | break; | |
10479 | case DPLLB_MODE_LVDS: | |
10480 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
10481 | 7 : 14; | |
10482 | break; | |
10483 | default: | |
28c97730 | 10484 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 10485 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 10486 | return; |
79e53945 JB |
10487 | } |
10488 | ||
ac58c3f0 | 10489 | if (IS_PINEVIEW(dev)) |
dccbea3b | 10490 | port_clock = pnv_calc_dpll_params(refclk, &clock); |
ac58c3f0 | 10491 | else |
dccbea3b | 10492 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 | 10493 | } else { |
0fb58223 | 10494 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
b1c560d1 | 10495 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
10496 | |
10497 | if (is_lvds) { | |
10498 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
10499 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
10500 | |
10501 | if (lvds & LVDS_CLKB_POWER_UP) | |
10502 | clock.p2 = 7; | |
10503 | else | |
10504 | clock.p2 = 14; | |
79e53945 JB |
10505 | } else { |
10506 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
10507 | clock.p1 = 2; | |
10508 | else { | |
10509 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
10510 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
10511 | } | |
10512 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
10513 | clock.p2 = 4; | |
10514 | else | |
10515 | clock.p2 = 2; | |
79e53945 | 10516 | } |
da4a1efa | 10517 | |
dccbea3b | 10518 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 JB |
10519 | } |
10520 | ||
18442d08 VS |
10521 | /* |
10522 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 10523 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
10524 | * encoder's get_config() function. |
10525 | */ | |
dccbea3b | 10526 | pipe_config->port_clock = port_clock; |
f1f644dc JB |
10527 | } |
10528 | ||
6878da05 VS |
10529 | int intel_dotclock_calculate(int link_freq, |
10530 | const struct intel_link_m_n *m_n) | |
f1f644dc | 10531 | { |
f1f644dc JB |
10532 | /* |
10533 | * The calculation for the data clock is: | |
1041a02f | 10534 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 10535 | * But we want to avoid losing precison if possible, so: |
1041a02f | 10536 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
10537 | * |
10538 | * and the link clock is simpler: | |
1041a02f | 10539 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
10540 | */ |
10541 | ||
6878da05 VS |
10542 | if (!m_n->link_n) |
10543 | return 0; | |
f1f644dc | 10544 | |
6878da05 VS |
10545 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
10546 | } | |
f1f644dc | 10547 | |
18442d08 | 10548 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 10549 | struct intel_crtc_state *pipe_config) |
6878da05 VS |
10550 | { |
10551 | struct drm_device *dev = crtc->base.dev; | |
79e53945 | 10552 | |
18442d08 VS |
10553 | /* read out port_clock from the DPLL */ |
10554 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 10555 | |
f1f644dc | 10556 | /* |
18442d08 | 10557 | * This value does not include pixel_multiplier. |
241bfc38 | 10558 | * We will check that port_clock and adjusted_mode.crtc_clock |
18442d08 VS |
10559 | * agree once we know their relationship in the encoder's |
10560 | * get_config() function. | |
79e53945 | 10561 | */ |
2d112de7 | 10562 | pipe_config->base.adjusted_mode.crtc_clock = |
18442d08 VS |
10563 | intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000, |
10564 | &pipe_config->fdi_m_n); | |
79e53945 JB |
10565 | } |
10566 | ||
10567 | /** Returns the currently programmed mode of the given pipe. */ | |
10568 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
10569 | struct drm_crtc *crtc) | |
10570 | { | |
548f245b | 10571 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 10572 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 10573 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
79e53945 | 10574 | struct drm_display_mode *mode; |
5cec258b | 10575 | struct intel_crtc_state pipe_config; |
fe2b8f9d PZ |
10576 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
10577 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
10578 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
10579 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 10580 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
10581 | |
10582 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
10583 | if (!mode) | |
10584 | return NULL; | |
10585 | ||
f1f644dc JB |
10586 | /* |
10587 | * Construct a pipe_config sufficient for getting the clock info | |
10588 | * back out of crtc_clock_get. | |
10589 | * | |
10590 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
10591 | * to use a real value here instead. | |
10592 | */ | |
293623f7 | 10593 | pipe_config.cpu_transcoder = (enum transcoder) pipe; |
f1f644dc | 10594 | pipe_config.pixel_multiplier = 1; |
293623f7 VS |
10595 | pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); |
10596 | pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
10597 | pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
f1f644dc JB |
10598 | i9xx_crtc_clock_get(intel_crtc, &pipe_config); |
10599 | ||
773ae034 | 10600 | mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier; |
79e53945 JB |
10601 | mode->hdisplay = (htot & 0xffff) + 1; |
10602 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
10603 | mode->hsync_start = (hsync & 0xffff) + 1; | |
10604 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
10605 | mode->vdisplay = (vtot & 0xffff) + 1; | |
10606 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
10607 | mode->vsync_start = (vsync & 0xffff) + 1; | |
10608 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
10609 | ||
10610 | drm_mode_set_name(mode); | |
79e53945 JB |
10611 | |
10612 | return mode; | |
10613 | } | |
10614 | ||
f047e395 CW |
10615 | void intel_mark_busy(struct drm_device *dev) |
10616 | { | |
c67a470b PZ |
10617 | struct drm_i915_private *dev_priv = dev->dev_private; |
10618 | ||
f62a0076 CW |
10619 | if (dev_priv->mm.busy) |
10620 | return; | |
10621 | ||
43694d69 | 10622 | intel_runtime_pm_get(dev_priv); |
c67a470b | 10623 | i915_update_gfx_val(dev_priv); |
43cf3bf0 CW |
10624 | if (INTEL_INFO(dev)->gen >= 6) |
10625 | gen6_rps_busy(dev_priv); | |
f62a0076 | 10626 | dev_priv->mm.busy = true; |
f047e395 CW |
10627 | } |
10628 | ||
10629 | void intel_mark_idle(struct drm_device *dev) | |
652c393a | 10630 | { |
c67a470b | 10631 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 10632 | |
f62a0076 CW |
10633 | if (!dev_priv->mm.busy) |
10634 | return; | |
10635 | ||
10636 | dev_priv->mm.busy = false; | |
10637 | ||
3d13ef2e | 10638 | if (INTEL_INFO(dev)->gen >= 6) |
b29c19b6 | 10639 | gen6_rps_idle(dev->dev_private); |
bb4cdd53 | 10640 | |
43694d69 | 10641 | intel_runtime_pm_put(dev_priv); |
652c393a JB |
10642 | } |
10643 | ||
79e53945 JB |
10644 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
10645 | { | |
10646 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
10647 | struct drm_device *dev = crtc->dev; |
10648 | struct intel_unpin_work *work; | |
67e77c5a | 10649 | |
5e2d7afc | 10650 | spin_lock_irq(&dev->event_lock); |
67e77c5a DV |
10651 | work = intel_crtc->unpin_work; |
10652 | intel_crtc->unpin_work = NULL; | |
5e2d7afc | 10653 | spin_unlock_irq(&dev->event_lock); |
67e77c5a DV |
10654 | |
10655 | if (work) { | |
10656 | cancel_work_sync(&work->work); | |
10657 | kfree(work); | |
10658 | } | |
79e53945 JB |
10659 | |
10660 | drm_crtc_cleanup(crtc); | |
67e77c5a | 10661 | |
79e53945 JB |
10662 | kfree(intel_crtc); |
10663 | } | |
10664 | ||
6b95a207 KH |
10665 | static void intel_unpin_work_fn(struct work_struct *__work) |
10666 | { | |
10667 | struct intel_unpin_work *work = | |
10668 | container_of(__work, struct intel_unpin_work, work); | |
a9ff8714 VS |
10669 | struct intel_crtc *crtc = to_intel_crtc(work->crtc); |
10670 | struct drm_device *dev = crtc->base.dev; | |
10671 | struct drm_plane *primary = crtc->base.primary; | |
6b95a207 | 10672 | |
b4a98e57 | 10673 | mutex_lock(&dev->struct_mutex); |
a9ff8714 | 10674 | intel_unpin_fb_obj(work->old_fb, primary->state); |
05394f39 | 10675 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
d9e86c0e | 10676 | |
f06cc1b9 | 10677 | if (work->flip_queued_req) |
146d84f0 | 10678 | i915_gem_request_assign(&work->flip_queued_req, NULL); |
b4a98e57 CW |
10679 | mutex_unlock(&dev->struct_mutex); |
10680 | ||
a9ff8714 | 10681 | intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit); |
89ed88ba | 10682 | drm_framebuffer_unreference(work->old_fb); |
f99d7069 | 10683 | |
a9ff8714 VS |
10684 | BUG_ON(atomic_read(&crtc->unpin_work_count) == 0); |
10685 | atomic_dec(&crtc->unpin_work_count); | |
b4a98e57 | 10686 | |
6b95a207 KH |
10687 | kfree(work); |
10688 | } | |
10689 | ||
1afe3e9d | 10690 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 10691 | struct drm_crtc *crtc) |
6b95a207 | 10692 | { |
6b95a207 KH |
10693 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
10694 | struct intel_unpin_work *work; | |
6b95a207 KH |
10695 | unsigned long flags; |
10696 | ||
10697 | /* Ignore early vblank irqs */ | |
10698 | if (intel_crtc == NULL) | |
10699 | return; | |
10700 | ||
f326038a DV |
10701 | /* |
10702 | * This is called both by irq handlers and the reset code (to complete | |
10703 | * lost pageflips) so needs the full irqsave spinlocks. | |
10704 | */ | |
6b95a207 KH |
10705 | spin_lock_irqsave(&dev->event_lock, flags); |
10706 | work = intel_crtc->unpin_work; | |
e7d841ca CW |
10707 | |
10708 | /* Ensure we don't miss a work->pending update ... */ | |
10709 | smp_rmb(); | |
10710 | ||
10711 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { | |
6b95a207 KH |
10712 | spin_unlock_irqrestore(&dev->event_lock, flags); |
10713 | return; | |
10714 | } | |
10715 | ||
d6bbafa1 | 10716 | page_flip_completed(intel_crtc); |
0af7e4df | 10717 | |
6b95a207 | 10718 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6b95a207 KH |
10719 | } |
10720 | ||
1afe3e9d JB |
10721 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
10722 | { | |
fbee40df | 10723 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
10724 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
10725 | ||
49b14a5c | 10726 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
10727 | } |
10728 | ||
10729 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
10730 | { | |
fbee40df | 10731 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
10732 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
10733 | ||
49b14a5c | 10734 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
10735 | } |
10736 | ||
75f7f3ec VS |
10737 | /* Is 'a' after or equal to 'b'? */ |
10738 | static bool g4x_flip_count_after_eq(u32 a, u32 b) | |
10739 | { | |
10740 | return !((a - b) & 0x80000000); | |
10741 | } | |
10742 | ||
10743 | static bool page_flip_finished(struct intel_crtc *crtc) | |
10744 | { | |
10745 | struct drm_device *dev = crtc->base.dev; | |
10746 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10747 | ||
bdfa7542 VS |
10748 | if (i915_reset_in_progress(&dev_priv->gpu_error) || |
10749 | crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
10750 | return true; | |
10751 | ||
75f7f3ec VS |
10752 | /* |
10753 | * The relevant registers doen't exist on pre-ctg. | |
10754 | * As the flip done interrupt doesn't trigger for mmio | |
10755 | * flips on gmch platforms, a flip count check isn't | |
10756 | * really needed there. But since ctg has the registers, | |
10757 | * include it in the check anyway. | |
10758 | */ | |
10759 | if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) | |
10760 | return true; | |
10761 | ||
10762 | /* | |
10763 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips | |
10764 | * used the same base address. In that case the mmio flip might | |
10765 | * have completed, but the CS hasn't even executed the flip yet. | |
10766 | * | |
10767 | * A flip count check isn't enough as the CS might have updated | |
10768 | * the base address just after start of vblank, but before we | |
10769 | * managed to process the interrupt. This means we'd complete the | |
10770 | * CS flip too soon. | |
10771 | * | |
10772 | * Combining both checks should get us a good enough result. It may | |
10773 | * still happen that the CS flip has been executed, but has not | |
10774 | * yet actually completed. But in case the base address is the same | |
10775 | * anyway, we don't really care. | |
10776 | */ | |
10777 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == | |
10778 | crtc->unpin_work->gtt_offset && | |
10779 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)), | |
10780 | crtc->unpin_work->flip_count); | |
10781 | } | |
10782 | ||
6b95a207 KH |
10783 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
10784 | { | |
fbee40df | 10785 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
10786 | struct intel_crtc *intel_crtc = |
10787 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
10788 | unsigned long flags; | |
10789 | ||
f326038a DV |
10790 | |
10791 | /* | |
10792 | * This is called both by irq handlers and the reset code (to complete | |
10793 | * lost pageflips) so needs the full irqsave spinlocks. | |
10794 | * | |
10795 | * NB: An MMIO update of the plane base pointer will also | |
e7d841ca CW |
10796 | * generate a page-flip completion irq, i.e. every modeset |
10797 | * is also accompanied by a spurious intel_prepare_page_flip(). | |
10798 | */ | |
6b95a207 | 10799 | spin_lock_irqsave(&dev->event_lock, flags); |
75f7f3ec | 10800 | if (intel_crtc->unpin_work && page_flip_finished(intel_crtc)) |
e7d841ca | 10801 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); |
6b95a207 KH |
10802 | spin_unlock_irqrestore(&dev->event_lock, flags); |
10803 | } | |
10804 | ||
eba905b2 | 10805 | static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc) |
e7d841ca CW |
10806 | { |
10807 | /* Ensure that the work item is consistent when activating it ... */ | |
10808 | smp_wmb(); | |
10809 | atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING); | |
10810 | /* and that it is marked active as soon as the irq could fire. */ | |
10811 | smp_wmb(); | |
10812 | } | |
10813 | ||
8c9f3aaf JB |
10814 | static int intel_gen2_queue_flip(struct drm_device *dev, |
10815 | struct drm_crtc *crtc, | |
10816 | struct drm_framebuffer *fb, | |
ed8d1975 | 10817 | struct drm_i915_gem_object *obj, |
6258fbe2 | 10818 | struct drm_i915_gem_request *req, |
ed8d1975 | 10819 | uint32_t flags) |
8c9f3aaf | 10820 | { |
6258fbe2 | 10821 | struct intel_engine_cs *ring = req->ring; |
8c9f3aaf | 10822 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
10823 | u32 flip_mask; |
10824 | int ret; | |
10825 | ||
5fb9de1a | 10826 | ret = intel_ring_begin(req, 6); |
8c9f3aaf | 10827 | if (ret) |
4fa62c89 | 10828 | return ret; |
8c9f3aaf JB |
10829 | |
10830 | /* Can't queue multiple flips, so wait for the previous | |
10831 | * one to finish before executing the next. | |
10832 | */ | |
10833 | if (intel_crtc->plane) | |
10834 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
10835 | else | |
10836 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
10837 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
10838 | intel_ring_emit(ring, MI_NOOP); | |
10839 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
10840 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
10841 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 10842 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 | 10843 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
e7d841ca CW |
10844 | |
10845 | intel_mark_page_flip_active(intel_crtc); | |
83d4092b | 10846 | return 0; |
8c9f3aaf JB |
10847 | } |
10848 | ||
10849 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
10850 | struct drm_crtc *crtc, | |
10851 | struct drm_framebuffer *fb, | |
ed8d1975 | 10852 | struct drm_i915_gem_object *obj, |
6258fbe2 | 10853 | struct drm_i915_gem_request *req, |
ed8d1975 | 10854 | uint32_t flags) |
8c9f3aaf | 10855 | { |
6258fbe2 | 10856 | struct intel_engine_cs *ring = req->ring; |
8c9f3aaf | 10857 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
10858 | u32 flip_mask; |
10859 | int ret; | |
10860 | ||
5fb9de1a | 10861 | ret = intel_ring_begin(req, 6); |
8c9f3aaf | 10862 | if (ret) |
4fa62c89 | 10863 | return ret; |
8c9f3aaf JB |
10864 | |
10865 | if (intel_crtc->plane) | |
10866 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
10867 | else | |
10868 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
10869 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
10870 | intel_ring_emit(ring, MI_NOOP); | |
10871 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
10872 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
10873 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 10874 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 DV |
10875 | intel_ring_emit(ring, MI_NOOP); |
10876 | ||
e7d841ca | 10877 | intel_mark_page_flip_active(intel_crtc); |
83d4092b | 10878 | return 0; |
8c9f3aaf JB |
10879 | } |
10880 | ||
10881 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
10882 | struct drm_crtc *crtc, | |
10883 | struct drm_framebuffer *fb, | |
ed8d1975 | 10884 | struct drm_i915_gem_object *obj, |
6258fbe2 | 10885 | struct drm_i915_gem_request *req, |
ed8d1975 | 10886 | uint32_t flags) |
8c9f3aaf | 10887 | { |
6258fbe2 | 10888 | struct intel_engine_cs *ring = req->ring; |
8c9f3aaf JB |
10889 | struct drm_i915_private *dev_priv = dev->dev_private; |
10890 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10891 | uint32_t pf, pipesrc; | |
10892 | int ret; | |
10893 | ||
5fb9de1a | 10894 | ret = intel_ring_begin(req, 4); |
8c9f3aaf | 10895 | if (ret) |
4fa62c89 | 10896 | return ret; |
8c9f3aaf JB |
10897 | |
10898 | /* i965+ uses the linear or tiled offsets from the | |
10899 | * Display Registers (which do not change across a page-flip) | |
10900 | * so we need only reprogram the base address. | |
10901 | */ | |
6d90c952 DV |
10902 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
10903 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
10904 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 10905 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset | |
c2c75131 | 10906 | obj->tiling_mode); |
8c9f3aaf JB |
10907 | |
10908 | /* XXX Enabling the panel-fitter across page-flip is so far | |
10909 | * untested on non-native modes, so ignore it for now. | |
10910 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
10911 | */ | |
10912 | pf = 0; | |
10913 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
6d90c952 | 10914 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
10915 | |
10916 | intel_mark_page_flip_active(intel_crtc); | |
83d4092b | 10917 | return 0; |
8c9f3aaf JB |
10918 | } |
10919 | ||
10920 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
10921 | struct drm_crtc *crtc, | |
10922 | struct drm_framebuffer *fb, | |
ed8d1975 | 10923 | struct drm_i915_gem_object *obj, |
6258fbe2 | 10924 | struct drm_i915_gem_request *req, |
ed8d1975 | 10925 | uint32_t flags) |
8c9f3aaf | 10926 | { |
6258fbe2 | 10927 | struct intel_engine_cs *ring = req->ring; |
8c9f3aaf JB |
10928 | struct drm_i915_private *dev_priv = dev->dev_private; |
10929 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10930 | uint32_t pf, pipesrc; | |
10931 | int ret; | |
10932 | ||
5fb9de1a | 10933 | ret = intel_ring_begin(req, 4); |
8c9f3aaf | 10934 | if (ret) |
4fa62c89 | 10935 | return ret; |
8c9f3aaf | 10936 | |
6d90c952 DV |
10937 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
10938 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
10939 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); | |
75f7f3ec | 10940 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
8c9f3aaf | 10941 | |
dc257cf1 DV |
10942 | /* Contrary to the suggestions in the documentation, |
10943 | * "Enable Panel Fitter" does not seem to be required when page | |
10944 | * flipping with a non-native mode, and worse causes a normal | |
10945 | * modeset to fail. | |
10946 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
10947 | */ | |
10948 | pf = 0; | |
8c9f3aaf | 10949 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
6d90c952 | 10950 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
10951 | |
10952 | intel_mark_page_flip_active(intel_crtc); | |
83d4092b | 10953 | return 0; |
8c9f3aaf JB |
10954 | } |
10955 | ||
7c9017e5 JB |
10956 | static int intel_gen7_queue_flip(struct drm_device *dev, |
10957 | struct drm_crtc *crtc, | |
10958 | struct drm_framebuffer *fb, | |
ed8d1975 | 10959 | struct drm_i915_gem_object *obj, |
6258fbe2 | 10960 | struct drm_i915_gem_request *req, |
ed8d1975 | 10961 | uint32_t flags) |
7c9017e5 | 10962 | { |
6258fbe2 | 10963 | struct intel_engine_cs *ring = req->ring; |
7c9017e5 | 10964 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cb05d8de | 10965 | uint32_t plane_bit = 0; |
ffe74d75 CW |
10966 | int len, ret; |
10967 | ||
eba905b2 | 10968 | switch (intel_crtc->plane) { |
cb05d8de DV |
10969 | case PLANE_A: |
10970 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
10971 | break; | |
10972 | case PLANE_B: | |
10973 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
10974 | break; | |
10975 | case PLANE_C: | |
10976 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
10977 | break; | |
10978 | default: | |
10979 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
4fa62c89 | 10980 | return -ENODEV; |
cb05d8de DV |
10981 | } |
10982 | ||
ffe74d75 | 10983 | len = 4; |
f476828a | 10984 | if (ring->id == RCS) { |
ffe74d75 | 10985 | len += 6; |
f476828a DL |
10986 | /* |
10987 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
10988 | * 48bits addresses, and we need a NOOP for the batch size to | |
10989 | * stay even. | |
10990 | */ | |
10991 | if (IS_GEN8(dev)) | |
10992 | len += 2; | |
10993 | } | |
ffe74d75 | 10994 | |
f66fab8e VS |
10995 | /* |
10996 | * BSpec MI_DISPLAY_FLIP for IVB: | |
10997 | * "The full packet must be contained within the same cache line." | |
10998 | * | |
10999 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
11000 | * cacheline, if we ever start emitting more commands before | |
11001 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
11002 | * then do the cacheline alignment, and finally emit the | |
11003 | * MI_DISPLAY_FLIP. | |
11004 | */ | |
bba09b12 | 11005 | ret = intel_ring_cacheline_align(req); |
f66fab8e | 11006 | if (ret) |
4fa62c89 | 11007 | return ret; |
f66fab8e | 11008 | |
5fb9de1a | 11009 | ret = intel_ring_begin(req, len); |
7c9017e5 | 11010 | if (ret) |
4fa62c89 | 11011 | return ret; |
7c9017e5 | 11012 | |
ffe74d75 CW |
11013 | /* Unmask the flip-done completion message. Note that the bspec says that |
11014 | * we should do this for both the BCS and RCS, and that we must not unmask | |
11015 | * more than one flip event at any time (or ensure that one flip message | |
11016 | * can be sent by waiting for flip-done prior to queueing new flips). | |
11017 | * Experimentation says that BCS works despite DERRMR masking all | |
11018 | * flip-done completion events and that unmasking all planes at once | |
11019 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
11020 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
11021 | */ | |
11022 | if (ring->id == RCS) { | |
11023 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
11024 | intel_ring_emit(ring, DERRMR); | |
11025 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
11026 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
11027 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
f476828a | 11028 | if (IS_GEN8(dev)) |
f1afe24f | 11029 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 | |
f476828a DL |
11030 | MI_SRM_LRM_GLOBAL_GTT); |
11031 | else | |
f1afe24f | 11032 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM | |
f476828a | 11033 | MI_SRM_LRM_GLOBAL_GTT); |
ffe74d75 CW |
11034 | intel_ring_emit(ring, DERRMR); |
11035 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); | |
f476828a DL |
11036 | if (IS_GEN8(dev)) { |
11037 | intel_ring_emit(ring, 0); | |
11038 | intel_ring_emit(ring, MI_NOOP); | |
11039 | } | |
ffe74d75 CW |
11040 | } |
11041 | ||
cb05d8de | 11042 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
01f2c773 | 11043 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
75f7f3ec | 11044 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
7c9017e5 | 11045 | intel_ring_emit(ring, (MI_NOOP)); |
e7d841ca CW |
11046 | |
11047 | intel_mark_page_flip_active(intel_crtc); | |
83d4092b | 11048 | return 0; |
7c9017e5 JB |
11049 | } |
11050 | ||
84c33a64 SG |
11051 | static bool use_mmio_flip(struct intel_engine_cs *ring, |
11052 | struct drm_i915_gem_object *obj) | |
11053 | { | |
11054 | /* | |
11055 | * This is not being used for older platforms, because | |
11056 | * non-availability of flip done interrupt forces us to use | |
11057 | * CS flips. Older platforms derive flip done using some clever | |
11058 | * tricks involving the flip_pending status bits and vblank irqs. | |
11059 | * So using MMIO flips there would disrupt this mechanism. | |
11060 | */ | |
11061 | ||
8e09bf83 CW |
11062 | if (ring == NULL) |
11063 | return true; | |
11064 | ||
84c33a64 SG |
11065 | if (INTEL_INFO(ring->dev)->gen < 5) |
11066 | return false; | |
11067 | ||
11068 | if (i915.use_mmio_flip < 0) | |
11069 | return false; | |
11070 | else if (i915.use_mmio_flip > 0) | |
11071 | return true; | |
14bf993e OM |
11072 | else if (i915.enable_execlists) |
11073 | return true; | |
84c33a64 | 11074 | else |
b4716185 | 11075 | return ring != i915_gem_request_get_ring(obj->last_write_req); |
84c33a64 SG |
11076 | } |
11077 | ||
ff944564 DL |
11078 | static void skl_do_mmio_flip(struct intel_crtc *intel_crtc) |
11079 | { | |
11080 | struct drm_device *dev = intel_crtc->base.dev; | |
11081 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11082 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; | |
ff944564 DL |
11083 | const enum pipe pipe = intel_crtc->pipe; |
11084 | u32 ctl, stride; | |
11085 | ||
11086 | ctl = I915_READ(PLANE_CTL(pipe, 0)); | |
11087 | ctl &= ~PLANE_CTL_TILED_MASK; | |
2ebef630 TU |
11088 | switch (fb->modifier[0]) { |
11089 | case DRM_FORMAT_MOD_NONE: | |
11090 | break; | |
11091 | case I915_FORMAT_MOD_X_TILED: | |
ff944564 | 11092 | ctl |= PLANE_CTL_TILED_X; |
2ebef630 TU |
11093 | break; |
11094 | case I915_FORMAT_MOD_Y_TILED: | |
11095 | ctl |= PLANE_CTL_TILED_Y; | |
11096 | break; | |
11097 | case I915_FORMAT_MOD_Yf_TILED: | |
11098 | ctl |= PLANE_CTL_TILED_YF; | |
11099 | break; | |
11100 | default: | |
11101 | MISSING_CASE(fb->modifier[0]); | |
11102 | } | |
ff944564 DL |
11103 | |
11104 | /* | |
11105 | * The stride is either expressed as a multiple of 64 bytes chunks for | |
11106 | * linear buffers or in number of tiles for tiled buffers. | |
11107 | */ | |
2ebef630 TU |
11108 | stride = fb->pitches[0] / |
11109 | intel_fb_stride_alignment(dev, fb->modifier[0], | |
11110 | fb->pixel_format); | |
ff944564 DL |
11111 | |
11112 | /* | |
11113 | * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on | |
11114 | * PLANE_SURF updates, the update is then guaranteed to be atomic. | |
11115 | */ | |
11116 | I915_WRITE(PLANE_CTL(pipe, 0), ctl); | |
11117 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
11118 | ||
11119 | I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset); | |
11120 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
11121 | } | |
11122 | ||
11123 | static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc) | |
84c33a64 SG |
11124 | { |
11125 | struct drm_device *dev = intel_crtc->base.dev; | |
11126 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11127 | struct intel_framebuffer *intel_fb = | |
11128 | to_intel_framebuffer(intel_crtc->base.primary->fb); | |
11129 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
11130 | u32 dspcntr; | |
11131 | u32 reg; | |
11132 | ||
84c33a64 SG |
11133 | reg = DSPCNTR(intel_crtc->plane); |
11134 | dspcntr = I915_READ(reg); | |
11135 | ||
c5d97472 DL |
11136 | if (obj->tiling_mode != I915_TILING_NONE) |
11137 | dspcntr |= DISPPLANE_TILED; | |
11138 | else | |
11139 | dspcntr &= ~DISPPLANE_TILED; | |
11140 | ||
84c33a64 SG |
11141 | I915_WRITE(reg, dspcntr); |
11142 | ||
11143 | I915_WRITE(DSPSURF(intel_crtc->plane), | |
11144 | intel_crtc->unpin_work->gtt_offset); | |
11145 | POSTING_READ(DSPSURF(intel_crtc->plane)); | |
84c33a64 | 11146 | |
ff944564 DL |
11147 | } |
11148 | ||
11149 | /* | |
11150 | * XXX: This is the temporary way to update the plane registers until we get | |
11151 | * around to using the usual plane update functions for MMIO flips | |
11152 | */ | |
11153 | static void intel_do_mmio_flip(struct intel_crtc *intel_crtc) | |
11154 | { | |
11155 | struct drm_device *dev = intel_crtc->base.dev; | |
ff944564 DL |
11156 | |
11157 | intel_mark_page_flip_active(intel_crtc); | |
11158 | ||
34e0adbb | 11159 | intel_pipe_update_start(intel_crtc); |
ff944564 DL |
11160 | |
11161 | if (INTEL_INFO(dev)->gen >= 9) | |
11162 | skl_do_mmio_flip(intel_crtc); | |
11163 | else | |
11164 | /* use_mmio_flip() retricts MMIO flips to ilk+ */ | |
11165 | ilk_do_mmio_flip(intel_crtc); | |
11166 | ||
34e0adbb | 11167 | intel_pipe_update_end(intel_crtc); |
84c33a64 SG |
11168 | } |
11169 | ||
9362c7c5 | 11170 | static void intel_mmio_flip_work_func(struct work_struct *work) |
84c33a64 | 11171 | { |
b2cfe0ab CW |
11172 | struct intel_mmio_flip *mmio_flip = |
11173 | container_of(work, struct intel_mmio_flip, work); | |
84c33a64 | 11174 | |
eed29a5b DV |
11175 | if (mmio_flip->req) |
11176 | WARN_ON(__i915_wait_request(mmio_flip->req, | |
b2cfe0ab | 11177 | mmio_flip->crtc->reset_counter, |
bcafc4e3 CW |
11178 | false, NULL, |
11179 | &mmio_flip->i915->rps.mmioflips)); | |
84c33a64 | 11180 | |
b2cfe0ab CW |
11181 | intel_do_mmio_flip(mmio_flip->crtc); |
11182 | ||
eed29a5b | 11183 | i915_gem_request_unreference__unlocked(mmio_flip->req); |
b2cfe0ab | 11184 | kfree(mmio_flip); |
84c33a64 SG |
11185 | } |
11186 | ||
11187 | static int intel_queue_mmio_flip(struct drm_device *dev, | |
11188 | struct drm_crtc *crtc, | |
11189 | struct drm_framebuffer *fb, | |
11190 | struct drm_i915_gem_object *obj, | |
11191 | struct intel_engine_cs *ring, | |
11192 | uint32_t flags) | |
11193 | { | |
b2cfe0ab CW |
11194 | struct intel_mmio_flip *mmio_flip; |
11195 | ||
11196 | mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL); | |
11197 | if (mmio_flip == NULL) | |
11198 | return -ENOMEM; | |
84c33a64 | 11199 | |
bcafc4e3 | 11200 | mmio_flip->i915 = to_i915(dev); |
eed29a5b | 11201 | mmio_flip->req = i915_gem_request_reference(obj->last_write_req); |
b2cfe0ab | 11202 | mmio_flip->crtc = to_intel_crtc(crtc); |
536f5b5e | 11203 | |
b2cfe0ab CW |
11204 | INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func); |
11205 | schedule_work(&mmio_flip->work); | |
84c33a64 | 11206 | |
84c33a64 SG |
11207 | return 0; |
11208 | } | |
11209 | ||
8c9f3aaf JB |
11210 | static int intel_default_queue_flip(struct drm_device *dev, |
11211 | struct drm_crtc *crtc, | |
11212 | struct drm_framebuffer *fb, | |
ed8d1975 | 11213 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11214 | struct drm_i915_gem_request *req, |
ed8d1975 | 11215 | uint32_t flags) |
8c9f3aaf JB |
11216 | { |
11217 | return -ENODEV; | |
11218 | } | |
11219 | ||
d6bbafa1 CW |
11220 | static bool __intel_pageflip_stall_check(struct drm_device *dev, |
11221 | struct drm_crtc *crtc) | |
11222 | { | |
11223 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11224 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11225 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
11226 | u32 addr; | |
11227 | ||
11228 | if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE) | |
11229 | return true; | |
11230 | ||
908565c2 CW |
11231 | if (atomic_read(&work->pending) < INTEL_FLIP_PENDING) |
11232 | return false; | |
11233 | ||
d6bbafa1 CW |
11234 | if (!work->enable_stall_check) |
11235 | return false; | |
11236 | ||
11237 | if (work->flip_ready_vblank == 0) { | |
3a8a946e DV |
11238 | if (work->flip_queued_req && |
11239 | !i915_gem_request_completed(work->flip_queued_req, true)) | |
d6bbafa1 CW |
11240 | return false; |
11241 | ||
1e3feefd | 11242 | work->flip_ready_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 CW |
11243 | } |
11244 | ||
1e3feefd | 11245 | if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3) |
d6bbafa1 CW |
11246 | return false; |
11247 | ||
11248 | /* Potential stall - if we see that the flip has happened, | |
11249 | * assume a missed interrupt. */ | |
11250 | if (INTEL_INFO(dev)->gen >= 4) | |
11251 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); | |
11252 | else | |
11253 | addr = I915_READ(DSPADDR(intel_crtc->plane)); | |
11254 | ||
11255 | /* There is a potential issue here with a false positive after a flip | |
11256 | * to the same address. We could address this by checking for a | |
11257 | * non-incrementing frame counter. | |
11258 | */ | |
11259 | return addr == work->gtt_offset; | |
11260 | } | |
11261 | ||
11262 | void intel_check_page_flip(struct drm_device *dev, int pipe) | |
11263 | { | |
11264 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11265 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
11266 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6ad790c0 | 11267 | struct intel_unpin_work *work; |
f326038a | 11268 | |
6c51d46f | 11269 | WARN_ON(!in_interrupt()); |
d6bbafa1 CW |
11270 | |
11271 | if (crtc == NULL) | |
11272 | return; | |
11273 | ||
f326038a | 11274 | spin_lock(&dev->event_lock); |
6ad790c0 CW |
11275 | work = intel_crtc->unpin_work; |
11276 | if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) { | |
d6bbafa1 | 11277 | WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n", |
6ad790c0 | 11278 | work->flip_queued_vblank, drm_vblank_count(dev, pipe)); |
d6bbafa1 | 11279 | page_flip_completed(intel_crtc); |
6ad790c0 | 11280 | work = NULL; |
d6bbafa1 | 11281 | } |
6ad790c0 CW |
11282 | if (work != NULL && |
11283 | drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1) | |
11284 | intel_queue_rps_boost_for_request(dev, work->flip_queued_req); | |
f326038a | 11285 | spin_unlock(&dev->event_lock); |
d6bbafa1 CW |
11286 | } |
11287 | ||
6b95a207 KH |
11288 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
11289 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
11290 | struct drm_pending_vblank_event *event, |
11291 | uint32_t page_flip_flags) | |
6b95a207 KH |
11292 | { |
11293 | struct drm_device *dev = crtc->dev; | |
11294 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f4510a27 | 11295 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
2ff8fde1 | 11296 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
6b95a207 | 11297 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
455a6808 | 11298 | struct drm_plane *primary = crtc->primary; |
a071fa00 | 11299 | enum pipe pipe = intel_crtc->pipe; |
6b95a207 | 11300 | struct intel_unpin_work *work; |
a4872ba6 | 11301 | struct intel_engine_cs *ring; |
cf5d8a46 | 11302 | bool mmio_flip; |
91af127f | 11303 | struct drm_i915_gem_request *request = NULL; |
52e68630 | 11304 | int ret; |
6b95a207 | 11305 | |
2ff8fde1 MR |
11306 | /* |
11307 | * drm_mode_page_flip_ioctl() should already catch this, but double | |
11308 | * check to be safe. In the future we may enable pageflipping from | |
11309 | * a disabled primary plane. | |
11310 | */ | |
11311 | if (WARN_ON(intel_fb_obj(old_fb) == NULL)) | |
11312 | return -EBUSY; | |
11313 | ||
e6a595d2 | 11314 | /* Can't change pixel format via MI display flips. */ |
f4510a27 | 11315 | if (fb->pixel_format != crtc->primary->fb->pixel_format) |
e6a595d2 VS |
11316 | return -EINVAL; |
11317 | ||
11318 | /* | |
11319 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
11320 | * Note that pitch changes could also affect these register. | |
11321 | */ | |
11322 | if (INTEL_INFO(dev)->gen > 3 && | |
f4510a27 MR |
11323 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || |
11324 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
e6a595d2 VS |
11325 | return -EINVAL; |
11326 | ||
f900db47 CW |
11327 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
11328 | goto out_hang; | |
11329 | ||
b14c5679 | 11330 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
6b95a207 KH |
11331 | if (work == NULL) |
11332 | return -ENOMEM; | |
11333 | ||
6b95a207 | 11334 | work->event = event; |
b4a98e57 | 11335 | work->crtc = crtc; |
ab8d6675 | 11336 | work->old_fb = old_fb; |
6b95a207 KH |
11337 | INIT_WORK(&work->work, intel_unpin_work_fn); |
11338 | ||
87b6b101 | 11339 | ret = drm_crtc_vblank_get(crtc); |
7317c75e JB |
11340 | if (ret) |
11341 | goto free_work; | |
11342 | ||
6b95a207 | 11343 | /* We borrow the event spin lock for protecting unpin_work */ |
5e2d7afc | 11344 | spin_lock_irq(&dev->event_lock); |
6b95a207 | 11345 | if (intel_crtc->unpin_work) { |
d6bbafa1 CW |
11346 | /* Before declaring the flip queue wedged, check if |
11347 | * the hardware completed the operation behind our backs. | |
11348 | */ | |
11349 | if (__intel_pageflip_stall_check(dev, crtc)) { | |
11350 | DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n"); | |
11351 | page_flip_completed(intel_crtc); | |
11352 | } else { | |
11353 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
5e2d7afc | 11354 | spin_unlock_irq(&dev->event_lock); |
468f0b44 | 11355 | |
d6bbafa1 CW |
11356 | drm_crtc_vblank_put(crtc); |
11357 | kfree(work); | |
11358 | return -EBUSY; | |
11359 | } | |
6b95a207 KH |
11360 | } |
11361 | intel_crtc->unpin_work = work; | |
5e2d7afc | 11362 | spin_unlock_irq(&dev->event_lock); |
6b95a207 | 11363 | |
b4a98e57 CW |
11364 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
11365 | flush_workqueue(dev_priv->wq); | |
11366 | ||
75dfca80 | 11367 | /* Reference the objects for the scheduled work. */ |
ab8d6675 | 11368 | drm_framebuffer_reference(work->old_fb); |
05394f39 | 11369 | drm_gem_object_reference(&obj->base); |
6b95a207 | 11370 | |
f4510a27 | 11371 | crtc->primary->fb = fb; |
afd65eb4 | 11372 | update_state_fb(crtc->primary); |
1ed1f968 | 11373 | |
e1f99ce6 | 11374 | work->pending_flip_obj = obj; |
e1f99ce6 | 11375 | |
89ed88ba CW |
11376 | ret = i915_mutex_lock_interruptible(dev); |
11377 | if (ret) | |
11378 | goto cleanup; | |
11379 | ||
b4a98e57 | 11380 | atomic_inc(&intel_crtc->unpin_work_count); |
10d83730 | 11381 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
e1f99ce6 | 11382 | |
75f7f3ec | 11383 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) |
a071fa00 | 11384 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1; |
75f7f3ec | 11385 | |
4fa62c89 VS |
11386 | if (IS_VALLEYVIEW(dev)) { |
11387 | ring = &dev_priv->ring[BCS]; | |
ab8d6675 | 11388 | if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode) |
8e09bf83 CW |
11389 | /* vlv: DISPLAY_FLIP fails to change tiling */ |
11390 | ring = NULL; | |
48bf5b2d | 11391 | } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
2a92d5bc | 11392 | ring = &dev_priv->ring[BCS]; |
4fa62c89 | 11393 | } else if (INTEL_INFO(dev)->gen >= 7) { |
b4716185 | 11394 | ring = i915_gem_request_get_ring(obj->last_write_req); |
4fa62c89 VS |
11395 | if (ring == NULL || ring->id != RCS) |
11396 | ring = &dev_priv->ring[BCS]; | |
11397 | } else { | |
11398 | ring = &dev_priv->ring[RCS]; | |
11399 | } | |
11400 | ||
cf5d8a46 CW |
11401 | mmio_flip = use_mmio_flip(ring, obj); |
11402 | ||
11403 | /* When using CS flips, we want to emit semaphores between rings. | |
11404 | * However, when using mmio flips we will create a task to do the | |
11405 | * synchronisation, so all we want here is to pin the framebuffer | |
11406 | * into the display plane and skip any waits. | |
11407 | */ | |
82bc3b2d | 11408 | ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, |
cf5d8a46 | 11409 | crtc->primary->state, |
91af127f | 11410 | mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request); |
8c9f3aaf JB |
11411 | if (ret) |
11412 | goto cleanup_pending; | |
6b95a207 | 11413 | |
121920fa TU |
11414 | work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj) |
11415 | + intel_crtc->dspaddr_offset; | |
4fa62c89 | 11416 | |
cf5d8a46 | 11417 | if (mmio_flip) { |
84c33a64 SG |
11418 | ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring, |
11419 | page_flip_flags); | |
d6bbafa1 CW |
11420 | if (ret) |
11421 | goto cleanup_unpin; | |
11422 | ||
f06cc1b9 JH |
11423 | i915_gem_request_assign(&work->flip_queued_req, |
11424 | obj->last_write_req); | |
d6bbafa1 | 11425 | } else { |
6258fbe2 JH |
11426 | if (!request) { |
11427 | ret = i915_gem_request_alloc(ring, ring->default_context, &request); | |
11428 | if (ret) | |
11429 | goto cleanup_unpin; | |
11430 | } | |
11431 | ||
11432 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request, | |
d6bbafa1 CW |
11433 | page_flip_flags); |
11434 | if (ret) | |
11435 | goto cleanup_unpin; | |
11436 | ||
6258fbe2 | 11437 | i915_gem_request_assign(&work->flip_queued_req, request); |
d6bbafa1 CW |
11438 | } |
11439 | ||
91af127f | 11440 | if (request) |
75289874 | 11441 | i915_add_request_no_flush(request); |
91af127f | 11442 | |
1e3feefd | 11443 | work->flip_queued_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 | 11444 | work->enable_stall_check = true; |
4fa62c89 | 11445 | |
ab8d6675 | 11446 | i915_gem_track_fb(intel_fb_obj(work->old_fb), obj, |
a9ff8714 | 11447 | to_intel_plane(primary)->frontbuffer_bit); |
c80ac854 | 11448 | mutex_unlock(&dev->struct_mutex); |
a071fa00 | 11449 | |
4e1e26f1 | 11450 | intel_fbc_disable_crtc(intel_crtc); |
a9ff8714 VS |
11451 | intel_frontbuffer_flip_prepare(dev, |
11452 | to_intel_plane(primary)->frontbuffer_bit); | |
6b95a207 | 11453 | |
e5510fac JB |
11454 | trace_i915_flip_request(intel_crtc->plane, obj); |
11455 | ||
6b95a207 | 11456 | return 0; |
96b099fd | 11457 | |
4fa62c89 | 11458 | cleanup_unpin: |
82bc3b2d | 11459 | intel_unpin_fb_obj(fb, crtc->primary->state); |
8c9f3aaf | 11460 | cleanup_pending: |
91af127f JH |
11461 | if (request) |
11462 | i915_gem_request_cancel(request); | |
b4a98e57 | 11463 | atomic_dec(&intel_crtc->unpin_work_count); |
89ed88ba CW |
11464 | mutex_unlock(&dev->struct_mutex); |
11465 | cleanup: | |
f4510a27 | 11466 | crtc->primary->fb = old_fb; |
afd65eb4 | 11467 | update_state_fb(crtc->primary); |
89ed88ba CW |
11468 | |
11469 | drm_gem_object_unreference_unlocked(&obj->base); | |
ab8d6675 | 11470 | drm_framebuffer_unreference(work->old_fb); |
96b099fd | 11471 | |
5e2d7afc | 11472 | spin_lock_irq(&dev->event_lock); |
96b099fd | 11473 | intel_crtc->unpin_work = NULL; |
5e2d7afc | 11474 | spin_unlock_irq(&dev->event_lock); |
96b099fd | 11475 | |
87b6b101 | 11476 | drm_crtc_vblank_put(crtc); |
7317c75e | 11477 | free_work: |
96b099fd CW |
11478 | kfree(work); |
11479 | ||
f900db47 | 11480 | if (ret == -EIO) { |
02e0efb5 ML |
11481 | struct drm_atomic_state *state; |
11482 | struct drm_plane_state *plane_state; | |
11483 | ||
f900db47 | 11484 | out_hang: |
02e0efb5 ML |
11485 | state = drm_atomic_state_alloc(dev); |
11486 | if (!state) | |
11487 | return -ENOMEM; | |
11488 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); | |
11489 | ||
11490 | retry: | |
11491 | plane_state = drm_atomic_get_plane_state(state, primary); | |
11492 | ret = PTR_ERR_OR_ZERO(plane_state); | |
11493 | if (!ret) { | |
11494 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
11495 | ||
11496 | ret = drm_atomic_set_crtc_for_plane(plane_state, crtc); | |
11497 | if (!ret) | |
11498 | ret = drm_atomic_commit(state); | |
11499 | } | |
11500 | ||
11501 | if (ret == -EDEADLK) { | |
11502 | drm_modeset_backoff(state->acquire_ctx); | |
11503 | drm_atomic_state_clear(state); | |
11504 | goto retry; | |
11505 | } | |
11506 | ||
11507 | if (ret) | |
11508 | drm_atomic_state_free(state); | |
11509 | ||
f0d3dad3 | 11510 | if (ret == 0 && event) { |
5e2d7afc | 11511 | spin_lock_irq(&dev->event_lock); |
a071fa00 | 11512 | drm_send_vblank_event(dev, pipe, event); |
5e2d7afc | 11513 | spin_unlock_irq(&dev->event_lock); |
f0d3dad3 | 11514 | } |
f900db47 | 11515 | } |
96b099fd | 11516 | return ret; |
6b95a207 KH |
11517 | } |
11518 | ||
da20eabd ML |
11519 | |
11520 | /** | |
11521 | * intel_wm_need_update - Check whether watermarks need updating | |
11522 | * @plane: drm plane | |
11523 | * @state: new plane state | |
11524 | * | |
11525 | * Check current plane state versus the new one to determine whether | |
11526 | * watermarks need to be recalculated. | |
11527 | * | |
11528 | * Returns true or false. | |
11529 | */ | |
11530 | static bool intel_wm_need_update(struct drm_plane *plane, | |
11531 | struct drm_plane_state *state) | |
11532 | { | |
11533 | /* Update watermarks on tiling changes. */ | |
11534 | if (!plane->state->fb || !state->fb || | |
11535 | plane->state->fb->modifier[0] != state->fb->modifier[0] || | |
11536 | plane->state->rotation != state->rotation) | |
11537 | return true; | |
11538 | ||
11539 | if (plane->state->crtc_w != state->crtc_w) | |
11540 | return true; | |
11541 | ||
11542 | return false; | |
11543 | } | |
11544 | ||
11545 | int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, | |
11546 | struct drm_plane_state *plane_state) | |
11547 | { | |
11548 | struct drm_crtc *crtc = crtc_state->crtc; | |
11549 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11550 | struct drm_plane *plane = plane_state->plane; | |
11551 | struct drm_device *dev = crtc->dev; | |
11552 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11553 | struct intel_plane_state *old_plane_state = | |
11554 | to_intel_plane_state(plane->state); | |
11555 | int idx = intel_crtc->base.base.id, ret; | |
11556 | int i = drm_plane_index(plane); | |
11557 | bool mode_changed = needs_modeset(crtc_state); | |
11558 | bool was_crtc_enabled = crtc->state->active; | |
11559 | bool is_crtc_enabled = crtc_state->active; | |
11560 | ||
11561 | bool turn_off, turn_on, visible, was_visible; | |
11562 | struct drm_framebuffer *fb = plane_state->fb; | |
11563 | ||
11564 | if (crtc_state && INTEL_INFO(dev)->gen >= 9 && | |
11565 | plane->type != DRM_PLANE_TYPE_CURSOR) { | |
11566 | ret = skl_update_scaler_plane( | |
11567 | to_intel_crtc_state(crtc_state), | |
11568 | to_intel_plane_state(plane_state)); | |
11569 | if (ret) | |
11570 | return ret; | |
11571 | } | |
11572 | ||
11573 | /* | |
11574 | * Disabling a plane is always okay; we just need to update | |
11575 | * fb tracking in a special way since cleanup_fb() won't | |
11576 | * get called by the plane helpers. | |
11577 | */ | |
11578 | if (old_plane_state->base.fb && !fb) | |
11579 | intel_crtc->atomic.disabled_planes |= 1 << i; | |
11580 | ||
da20eabd ML |
11581 | was_visible = old_plane_state->visible; |
11582 | visible = to_intel_plane_state(plane_state)->visible; | |
11583 | ||
11584 | if (!was_crtc_enabled && WARN_ON(was_visible)) | |
11585 | was_visible = false; | |
11586 | ||
11587 | if (!is_crtc_enabled && WARN_ON(visible)) | |
11588 | visible = false; | |
11589 | ||
11590 | if (!was_visible && !visible) | |
11591 | return 0; | |
11592 | ||
11593 | turn_off = was_visible && (!visible || mode_changed); | |
11594 | turn_on = visible && (!was_visible || mode_changed); | |
11595 | ||
11596 | DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx, | |
11597 | plane->base.id, fb ? fb->base.id : -1); | |
11598 | ||
11599 | DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n", | |
11600 | plane->base.id, was_visible, visible, | |
11601 | turn_off, turn_on, mode_changed); | |
11602 | ||
852eb00d | 11603 | if (turn_on) { |
f015c551 | 11604 | intel_crtc->atomic.update_wm_pre = true; |
852eb00d VS |
11605 | /* must disable cxsr around plane enable/disable */ |
11606 | if (plane->type != DRM_PLANE_TYPE_CURSOR) { | |
11607 | intel_crtc->atomic.disable_cxsr = true; | |
11608 | /* to potentially re-enable cxsr */ | |
11609 | intel_crtc->atomic.wait_vblank = true; | |
11610 | intel_crtc->atomic.update_wm_post = true; | |
11611 | } | |
11612 | } else if (turn_off) { | |
f015c551 | 11613 | intel_crtc->atomic.update_wm_post = true; |
852eb00d VS |
11614 | /* must disable cxsr around plane enable/disable */ |
11615 | if (plane->type != DRM_PLANE_TYPE_CURSOR) { | |
11616 | if (is_crtc_enabled) | |
11617 | intel_crtc->atomic.wait_vblank = true; | |
11618 | intel_crtc->atomic.disable_cxsr = true; | |
11619 | } | |
11620 | } else if (intel_wm_need_update(plane, plane_state)) { | |
f015c551 | 11621 | intel_crtc->atomic.update_wm_pre = true; |
852eb00d | 11622 | } |
da20eabd | 11623 | |
8be6ca85 | 11624 | if (visible || was_visible) |
a9ff8714 VS |
11625 | intel_crtc->atomic.fb_bits |= |
11626 | to_intel_plane(plane)->frontbuffer_bit; | |
11627 | ||
da20eabd ML |
11628 | switch (plane->type) { |
11629 | case DRM_PLANE_TYPE_PRIMARY: | |
da20eabd ML |
11630 | intel_crtc->atomic.wait_for_flips = true; |
11631 | intel_crtc->atomic.pre_disable_primary = turn_off; | |
11632 | intel_crtc->atomic.post_enable_primary = turn_on; | |
11633 | ||
066cf55b RV |
11634 | if (turn_off) { |
11635 | /* | |
11636 | * FIXME: Actually if we will still have any other | |
11637 | * plane enabled on the pipe we could let IPS enabled | |
11638 | * still, but for now lets consider that when we make | |
11639 | * primary invisible by setting DSPCNTR to 0 on | |
11640 | * update_primary_plane function IPS needs to be | |
11641 | * disable. | |
11642 | */ | |
11643 | intel_crtc->atomic.disable_ips = true; | |
11644 | ||
da20eabd | 11645 | intel_crtc->atomic.disable_fbc = true; |
066cf55b | 11646 | } |
da20eabd ML |
11647 | |
11648 | /* | |
11649 | * FBC does not work on some platforms for rotated | |
11650 | * planes, so disable it when rotation is not 0 and | |
11651 | * update it when rotation is set back to 0. | |
11652 | * | |
11653 | * FIXME: This is redundant with the fbc update done in | |
11654 | * the primary plane enable function except that that | |
11655 | * one is done too late. We eventually need to unify | |
11656 | * this. | |
11657 | */ | |
11658 | ||
11659 | if (visible && | |
11660 | INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) && | |
11661 | dev_priv->fbc.crtc == intel_crtc && | |
11662 | plane_state->rotation != BIT(DRM_ROTATE_0)) | |
11663 | intel_crtc->atomic.disable_fbc = true; | |
11664 | ||
11665 | /* | |
11666 | * BDW signals flip done immediately if the plane | |
11667 | * is disabled, even if the plane enable is already | |
11668 | * armed to occur at the next vblank :( | |
11669 | */ | |
11670 | if (turn_on && IS_BROADWELL(dev)) | |
11671 | intel_crtc->atomic.wait_vblank = true; | |
11672 | ||
11673 | intel_crtc->atomic.update_fbc |= visible || mode_changed; | |
11674 | break; | |
11675 | case DRM_PLANE_TYPE_CURSOR: | |
da20eabd ML |
11676 | break; |
11677 | case DRM_PLANE_TYPE_OVERLAY: | |
d032ffa0 | 11678 | if (turn_off && !mode_changed) { |
da20eabd ML |
11679 | intel_crtc->atomic.wait_vblank = true; |
11680 | intel_crtc->atomic.update_sprite_watermarks |= | |
11681 | 1 << i; | |
11682 | } | |
da20eabd ML |
11683 | } |
11684 | return 0; | |
11685 | } | |
11686 | ||
6d3a1ce7 ML |
11687 | static bool encoders_cloneable(const struct intel_encoder *a, |
11688 | const struct intel_encoder *b) | |
11689 | { | |
11690 | /* masks could be asymmetric, so check both ways */ | |
11691 | return a == b || (a->cloneable & (1 << b->type) && | |
11692 | b->cloneable & (1 << a->type)); | |
11693 | } | |
11694 | ||
11695 | static bool check_single_encoder_cloning(struct drm_atomic_state *state, | |
11696 | struct intel_crtc *crtc, | |
11697 | struct intel_encoder *encoder) | |
11698 | { | |
11699 | struct intel_encoder *source_encoder; | |
11700 | struct drm_connector *connector; | |
11701 | struct drm_connector_state *connector_state; | |
11702 | int i; | |
11703 | ||
11704 | for_each_connector_in_state(state, connector, connector_state, i) { | |
11705 | if (connector_state->crtc != &crtc->base) | |
11706 | continue; | |
11707 | ||
11708 | source_encoder = | |
11709 | to_intel_encoder(connector_state->best_encoder); | |
11710 | if (!encoders_cloneable(encoder, source_encoder)) | |
11711 | return false; | |
11712 | } | |
11713 | ||
11714 | return true; | |
11715 | } | |
11716 | ||
11717 | static bool check_encoder_cloning(struct drm_atomic_state *state, | |
11718 | struct intel_crtc *crtc) | |
11719 | { | |
11720 | struct intel_encoder *encoder; | |
11721 | struct drm_connector *connector; | |
11722 | struct drm_connector_state *connector_state; | |
11723 | int i; | |
11724 | ||
11725 | for_each_connector_in_state(state, connector, connector_state, i) { | |
11726 | if (connector_state->crtc != &crtc->base) | |
11727 | continue; | |
11728 | ||
11729 | encoder = to_intel_encoder(connector_state->best_encoder); | |
11730 | if (!check_single_encoder_cloning(state, crtc, encoder)) | |
11731 | return false; | |
11732 | } | |
11733 | ||
11734 | return true; | |
11735 | } | |
11736 | ||
11737 | static int intel_crtc_atomic_check(struct drm_crtc *crtc, | |
11738 | struct drm_crtc_state *crtc_state) | |
11739 | { | |
cf5a15be | 11740 | struct drm_device *dev = crtc->dev; |
ad421372 | 11741 | struct drm_i915_private *dev_priv = dev->dev_private; |
6d3a1ce7 | 11742 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cf5a15be ML |
11743 | struct intel_crtc_state *pipe_config = |
11744 | to_intel_crtc_state(crtc_state); | |
6d3a1ce7 | 11745 | struct drm_atomic_state *state = crtc_state->state; |
4d20cd86 | 11746 | int ret; |
6d3a1ce7 ML |
11747 | bool mode_changed = needs_modeset(crtc_state); |
11748 | ||
11749 | if (mode_changed && !check_encoder_cloning(state, intel_crtc)) { | |
11750 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); | |
11751 | return -EINVAL; | |
11752 | } | |
11753 | ||
852eb00d VS |
11754 | if (mode_changed && !crtc_state->active) |
11755 | intel_crtc->atomic.update_wm_post = true; | |
eddfcbcd | 11756 | |
ad421372 ML |
11757 | if (mode_changed && crtc_state->enable && |
11758 | dev_priv->display.crtc_compute_clock && | |
11759 | !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) { | |
11760 | ret = dev_priv->display.crtc_compute_clock(intel_crtc, | |
11761 | pipe_config); | |
11762 | if (ret) | |
11763 | return ret; | |
11764 | } | |
11765 | ||
e435d6e5 ML |
11766 | ret = 0; |
11767 | if (INTEL_INFO(dev)->gen >= 9) { | |
11768 | if (mode_changed) | |
11769 | ret = skl_update_scaler_crtc(pipe_config); | |
11770 | ||
11771 | if (!ret) | |
11772 | ret = intel_atomic_setup_scalers(dev, intel_crtc, | |
11773 | pipe_config); | |
11774 | } | |
11775 | ||
11776 | return ret; | |
6d3a1ce7 ML |
11777 | } |
11778 | ||
65b38e0d | 11779 | static const struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 CW |
11780 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
11781 | .load_lut = intel_crtc_load_lut, | |
ea2c67bb MR |
11782 | .atomic_begin = intel_begin_crtc_commit, |
11783 | .atomic_flush = intel_finish_crtc_commit, | |
6d3a1ce7 | 11784 | .atomic_check = intel_crtc_atomic_check, |
f6e5b160 CW |
11785 | }; |
11786 | ||
d29b2f9d ACO |
11787 | static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) |
11788 | { | |
11789 | struct intel_connector *connector; | |
11790 | ||
11791 | for_each_intel_connector(dev, connector) { | |
11792 | if (connector->base.encoder) { | |
11793 | connector->base.state->best_encoder = | |
11794 | connector->base.encoder; | |
11795 | connector->base.state->crtc = | |
11796 | connector->base.encoder->crtc; | |
11797 | } else { | |
11798 | connector->base.state->best_encoder = NULL; | |
11799 | connector->base.state->crtc = NULL; | |
11800 | } | |
11801 | } | |
11802 | } | |
11803 | ||
050f7aeb | 11804 | static void |
eba905b2 | 11805 | connected_sink_compute_bpp(struct intel_connector *connector, |
5cec258b | 11806 | struct intel_crtc_state *pipe_config) |
050f7aeb DV |
11807 | { |
11808 | int bpp = pipe_config->pipe_bpp; | |
11809 | ||
11810 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
11811 | connector->base.base.id, | |
c23cc417 | 11812 | connector->base.name); |
050f7aeb DV |
11813 | |
11814 | /* Don't use an invalid EDID bpc value */ | |
11815 | if (connector->base.display_info.bpc && | |
11816 | connector->base.display_info.bpc * 3 < bpp) { | |
11817 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
11818 | bpp, connector->base.display_info.bpc*3); | |
11819 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
11820 | } | |
11821 | ||
11822 | /* Clamp bpp to 8 on screens without EDID 1.4 */ | |
11823 | if (connector->base.display_info.bpc == 0 && bpp > 24) { | |
11824 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", | |
11825 | bpp); | |
11826 | pipe_config->pipe_bpp = 24; | |
11827 | } | |
11828 | } | |
11829 | ||
4e53c2e0 | 11830 | static int |
050f7aeb | 11831 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
5cec258b | 11832 | struct intel_crtc_state *pipe_config) |
4e53c2e0 | 11833 | { |
050f7aeb | 11834 | struct drm_device *dev = crtc->base.dev; |
1486017f | 11835 | struct drm_atomic_state *state; |
da3ced29 ACO |
11836 | struct drm_connector *connector; |
11837 | struct drm_connector_state *connector_state; | |
1486017f | 11838 | int bpp, i; |
4e53c2e0 | 11839 | |
d328c9d7 | 11840 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev))) |
4e53c2e0 | 11841 | bpp = 10*3; |
d328c9d7 DV |
11842 | else if (INTEL_INFO(dev)->gen >= 5) |
11843 | bpp = 12*3; | |
11844 | else | |
11845 | bpp = 8*3; | |
11846 | ||
4e53c2e0 | 11847 | |
4e53c2e0 DV |
11848 | pipe_config->pipe_bpp = bpp; |
11849 | ||
1486017f ACO |
11850 | state = pipe_config->base.state; |
11851 | ||
4e53c2e0 | 11852 | /* Clamp display bpp to EDID value */ |
da3ced29 ACO |
11853 | for_each_connector_in_state(state, connector, connector_state, i) { |
11854 | if (connector_state->crtc != &crtc->base) | |
4e53c2e0 DV |
11855 | continue; |
11856 | ||
da3ced29 ACO |
11857 | connected_sink_compute_bpp(to_intel_connector(connector), |
11858 | pipe_config); | |
4e53c2e0 DV |
11859 | } |
11860 | ||
11861 | return bpp; | |
11862 | } | |
11863 | ||
644db711 DV |
11864 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
11865 | { | |
11866 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
11867 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 11868 | mode->crtc_clock, |
644db711 DV |
11869 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
11870 | mode->crtc_hsync_end, mode->crtc_htotal, | |
11871 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
11872 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
11873 | } | |
11874 | ||
c0b03411 | 11875 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
5cec258b | 11876 | struct intel_crtc_state *pipe_config, |
c0b03411 DV |
11877 | const char *context) |
11878 | { | |
6a60cd87 CK |
11879 | struct drm_device *dev = crtc->base.dev; |
11880 | struct drm_plane *plane; | |
11881 | struct intel_plane *intel_plane; | |
11882 | struct intel_plane_state *state; | |
11883 | struct drm_framebuffer *fb; | |
11884 | ||
11885 | DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id, | |
11886 | context, pipe_config, pipe_name(crtc->pipe)); | |
c0b03411 DV |
11887 | |
11888 | DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); | |
11889 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", | |
11890 | pipe_config->pipe_bpp, pipe_config->dither); | |
11891 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
11892 | pipe_config->has_pch_encoder, | |
11893 | pipe_config->fdi_lanes, | |
11894 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
11895 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
11896 | pipe_config->fdi_m_n.tu); | |
90a6b7b0 | 11897 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
eb14cb74 | 11898 | pipe_config->has_dp_encoder, |
90a6b7b0 | 11899 | pipe_config->lane_count, |
eb14cb74 VS |
11900 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, |
11901 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
11902 | pipe_config->dp_m_n.tu); | |
b95af8be | 11903 | |
90a6b7b0 | 11904 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n", |
b95af8be | 11905 | pipe_config->has_dp_encoder, |
90a6b7b0 | 11906 | pipe_config->lane_count, |
b95af8be VK |
11907 | pipe_config->dp_m2_n2.gmch_m, |
11908 | pipe_config->dp_m2_n2.gmch_n, | |
11909 | pipe_config->dp_m2_n2.link_m, | |
11910 | pipe_config->dp_m2_n2.link_n, | |
11911 | pipe_config->dp_m2_n2.tu); | |
11912 | ||
55072d19 DV |
11913 | DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", |
11914 | pipe_config->has_audio, | |
11915 | pipe_config->has_infoframe); | |
11916 | ||
c0b03411 | 11917 | DRM_DEBUG_KMS("requested mode:\n"); |
2d112de7 | 11918 | drm_mode_debug_printmodeline(&pipe_config->base.mode); |
c0b03411 | 11919 | DRM_DEBUG_KMS("adjusted mode:\n"); |
2d112de7 ACO |
11920 | drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); |
11921 | intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); | |
d71b8d4a | 11922 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
11923 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
11924 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
0ec463d3 TU |
11925 | DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", |
11926 | crtc->num_scalers, | |
11927 | pipe_config->scaler_state.scaler_users, | |
11928 | pipe_config->scaler_state.scaler_id); | |
c0b03411 DV |
11929 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
11930 | pipe_config->gmch_pfit.control, | |
11931 | pipe_config->gmch_pfit.pgm_ratios, | |
11932 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 11933 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 11934 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
11935 | pipe_config->pch_pfit.size, |
11936 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 11937 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 11938 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
6a60cd87 | 11939 | |
415ff0f6 | 11940 | if (IS_BROXTON(dev)) { |
05712c15 | 11941 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x," |
415ff0f6 | 11942 | "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " |
c8453338 | 11943 | "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n", |
415ff0f6 TU |
11944 | pipe_config->ddi_pll_sel, |
11945 | pipe_config->dpll_hw_state.ebb0, | |
05712c15 | 11946 | pipe_config->dpll_hw_state.ebb4, |
415ff0f6 TU |
11947 | pipe_config->dpll_hw_state.pll0, |
11948 | pipe_config->dpll_hw_state.pll1, | |
11949 | pipe_config->dpll_hw_state.pll2, | |
11950 | pipe_config->dpll_hw_state.pll3, | |
11951 | pipe_config->dpll_hw_state.pll6, | |
11952 | pipe_config->dpll_hw_state.pll8, | |
05712c15 | 11953 | pipe_config->dpll_hw_state.pll9, |
c8453338 | 11954 | pipe_config->dpll_hw_state.pll10, |
415ff0f6 TU |
11955 | pipe_config->dpll_hw_state.pcsdw12); |
11956 | } else if (IS_SKYLAKE(dev)) { | |
11957 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: " | |
11958 | "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n", | |
11959 | pipe_config->ddi_pll_sel, | |
11960 | pipe_config->dpll_hw_state.ctrl1, | |
11961 | pipe_config->dpll_hw_state.cfgcr1, | |
11962 | pipe_config->dpll_hw_state.cfgcr2); | |
11963 | } else if (HAS_DDI(dev)) { | |
11964 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n", | |
11965 | pipe_config->ddi_pll_sel, | |
11966 | pipe_config->dpll_hw_state.wrpll); | |
11967 | } else { | |
11968 | DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " | |
11969 | "fp0: 0x%x, fp1: 0x%x\n", | |
11970 | pipe_config->dpll_hw_state.dpll, | |
11971 | pipe_config->dpll_hw_state.dpll_md, | |
11972 | pipe_config->dpll_hw_state.fp0, | |
11973 | pipe_config->dpll_hw_state.fp1); | |
11974 | } | |
11975 | ||
6a60cd87 CK |
11976 | DRM_DEBUG_KMS("planes on this crtc\n"); |
11977 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
11978 | intel_plane = to_intel_plane(plane); | |
11979 | if (intel_plane->pipe != crtc->pipe) | |
11980 | continue; | |
11981 | ||
11982 | state = to_intel_plane_state(plane->state); | |
11983 | fb = state->base.fb; | |
11984 | if (!fb) { | |
11985 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d " | |
11986 | "disabled, scaler_id = %d\n", | |
11987 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
11988 | plane->base.id, intel_plane->pipe, | |
11989 | (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1, | |
11990 | drm_plane_index(plane), state->scaler_id); | |
11991 | continue; | |
11992 | } | |
11993 | ||
11994 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled", | |
11995 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
11996 | plane->base.id, intel_plane->pipe, | |
11997 | crtc->base.primary == plane ? 0 : intel_plane->plane + 1, | |
11998 | drm_plane_index(plane)); | |
11999 | DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x", | |
12000 | fb->base.id, fb->width, fb->height, fb->pixel_format); | |
12001 | DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n", | |
12002 | state->scaler_id, | |
12003 | state->src.x1 >> 16, state->src.y1 >> 16, | |
12004 | drm_rect_width(&state->src) >> 16, | |
12005 | drm_rect_height(&state->src) >> 16, | |
12006 | state->dst.x1, state->dst.y1, | |
12007 | drm_rect_width(&state->dst), drm_rect_height(&state->dst)); | |
12008 | } | |
c0b03411 DV |
12009 | } |
12010 | ||
5448a00d | 12011 | static bool check_digital_port_conflicts(struct drm_atomic_state *state) |
00f0b378 | 12012 | { |
5448a00d ACO |
12013 | struct drm_device *dev = state->dev; |
12014 | struct intel_encoder *encoder; | |
da3ced29 | 12015 | struct drm_connector *connector; |
5448a00d | 12016 | struct drm_connector_state *connector_state; |
00f0b378 | 12017 | unsigned int used_ports = 0; |
5448a00d | 12018 | int i; |
00f0b378 VS |
12019 | |
12020 | /* | |
12021 | * Walk the connector list instead of the encoder | |
12022 | * list to detect the problem on ddi platforms | |
12023 | * where there's just one encoder per digital port. | |
12024 | */ | |
da3ced29 | 12025 | for_each_connector_in_state(state, connector, connector_state, i) { |
5448a00d | 12026 | if (!connector_state->best_encoder) |
00f0b378 VS |
12027 | continue; |
12028 | ||
5448a00d ACO |
12029 | encoder = to_intel_encoder(connector_state->best_encoder); |
12030 | ||
12031 | WARN_ON(!connector_state->crtc); | |
00f0b378 VS |
12032 | |
12033 | switch (encoder->type) { | |
12034 | unsigned int port_mask; | |
12035 | case INTEL_OUTPUT_UNKNOWN: | |
12036 | if (WARN_ON(!HAS_DDI(dev))) | |
12037 | break; | |
12038 | case INTEL_OUTPUT_DISPLAYPORT: | |
12039 | case INTEL_OUTPUT_HDMI: | |
12040 | case INTEL_OUTPUT_EDP: | |
12041 | port_mask = 1 << enc_to_dig_port(&encoder->base)->port; | |
12042 | ||
12043 | /* the same port mustn't appear more than once */ | |
12044 | if (used_ports & port_mask) | |
12045 | return false; | |
12046 | ||
12047 | used_ports |= port_mask; | |
12048 | default: | |
12049 | break; | |
12050 | } | |
12051 | } | |
12052 | ||
12053 | return true; | |
12054 | } | |
12055 | ||
83a57153 ACO |
12056 | static void |
12057 | clear_intel_crtc_state(struct intel_crtc_state *crtc_state) | |
12058 | { | |
12059 | struct drm_crtc_state tmp_state; | |
663a3640 | 12060 | struct intel_crtc_scaler_state scaler_state; |
4978cc93 ACO |
12061 | struct intel_dpll_hw_state dpll_hw_state; |
12062 | enum intel_dpll_id shared_dpll; | |
8504c74c | 12063 | uint32_t ddi_pll_sel; |
c4e2d043 | 12064 | bool force_thru; |
83a57153 | 12065 | |
7546a384 ACO |
12066 | /* FIXME: before the switch to atomic started, a new pipe_config was |
12067 | * kzalloc'd. Code that depends on any field being zero should be | |
12068 | * fixed, so that the crtc_state can be safely duplicated. For now, | |
12069 | * only fields that are know to not cause problems are preserved. */ | |
12070 | ||
83a57153 | 12071 | tmp_state = crtc_state->base; |
663a3640 | 12072 | scaler_state = crtc_state->scaler_state; |
4978cc93 ACO |
12073 | shared_dpll = crtc_state->shared_dpll; |
12074 | dpll_hw_state = crtc_state->dpll_hw_state; | |
8504c74c | 12075 | ddi_pll_sel = crtc_state->ddi_pll_sel; |
c4e2d043 | 12076 | force_thru = crtc_state->pch_pfit.force_thru; |
4978cc93 | 12077 | |
83a57153 | 12078 | memset(crtc_state, 0, sizeof *crtc_state); |
4978cc93 | 12079 | |
83a57153 | 12080 | crtc_state->base = tmp_state; |
663a3640 | 12081 | crtc_state->scaler_state = scaler_state; |
4978cc93 ACO |
12082 | crtc_state->shared_dpll = shared_dpll; |
12083 | crtc_state->dpll_hw_state = dpll_hw_state; | |
8504c74c | 12084 | crtc_state->ddi_pll_sel = ddi_pll_sel; |
c4e2d043 | 12085 | crtc_state->pch_pfit.force_thru = force_thru; |
83a57153 ACO |
12086 | } |
12087 | ||
548ee15b | 12088 | static int |
b8cecdf5 | 12089 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
b359283a | 12090 | struct intel_crtc_state *pipe_config) |
ee7b9f93 | 12091 | { |
b359283a | 12092 | struct drm_atomic_state *state = pipe_config->base.state; |
7758a113 | 12093 | struct intel_encoder *encoder; |
da3ced29 | 12094 | struct drm_connector *connector; |
0b901879 | 12095 | struct drm_connector_state *connector_state; |
d328c9d7 | 12096 | int base_bpp, ret = -EINVAL; |
0b901879 | 12097 | int i; |
e29c22c0 | 12098 | bool retry = true; |
ee7b9f93 | 12099 | |
83a57153 | 12100 | clear_intel_crtc_state(pipe_config); |
7758a113 | 12101 | |
e143a21c DV |
12102 | pipe_config->cpu_transcoder = |
12103 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
b8cecdf5 | 12104 | |
2960bc9c ID |
12105 | /* |
12106 | * Sanitize sync polarity flags based on requested ones. If neither | |
12107 | * positive or negative polarity is requested, treat this as meaning | |
12108 | * negative polarity. | |
12109 | */ | |
2d112de7 | 12110 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 12111 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
2d112de7 | 12112 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
2960bc9c | 12113 | |
2d112de7 | 12114 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 12115 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
2d112de7 | 12116 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
2960bc9c | 12117 | |
d328c9d7 DV |
12118 | base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
12119 | pipe_config); | |
12120 | if (base_bpp < 0) | |
4e53c2e0 DV |
12121 | goto fail; |
12122 | ||
e41a56be VS |
12123 | /* |
12124 | * Determine the real pipe dimensions. Note that stereo modes can | |
12125 | * increase the actual pipe size due to the frame doubling and | |
12126 | * insertion of additional space for blanks between the frame. This | |
12127 | * is stored in the crtc timings. We use the requested mode to do this | |
12128 | * computation to clearly distinguish it from the adjusted mode, which | |
12129 | * can be changed by the connectors in the below retry loop. | |
12130 | */ | |
2d112de7 | 12131 | drm_crtc_get_hv_timing(&pipe_config->base.mode, |
ecb7e16b GP |
12132 | &pipe_config->pipe_src_w, |
12133 | &pipe_config->pipe_src_h); | |
e41a56be | 12134 | |
e29c22c0 | 12135 | encoder_retry: |
ef1b460d | 12136 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 12137 | pipe_config->port_clock = 0; |
ef1b460d | 12138 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 12139 | |
135c81b8 | 12140 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
2d112de7 ACO |
12141 | drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, |
12142 | CRTC_STEREO_DOUBLE); | |
135c81b8 | 12143 | |
7758a113 DV |
12144 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
12145 | * adjust it according to limitations or connector properties, and also | |
12146 | * a chance to reject the mode entirely. | |
47f1c6c9 | 12147 | */ |
da3ced29 | 12148 | for_each_connector_in_state(state, connector, connector_state, i) { |
0b901879 | 12149 | if (connector_state->crtc != crtc) |
7758a113 | 12150 | continue; |
7ae89233 | 12151 | |
0b901879 ACO |
12152 | encoder = to_intel_encoder(connector_state->best_encoder); |
12153 | ||
efea6e8e DV |
12154 | if (!(encoder->compute_config(encoder, pipe_config))) { |
12155 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
12156 | goto fail; |
12157 | } | |
ee7b9f93 | 12158 | } |
47f1c6c9 | 12159 | |
ff9a6750 DV |
12160 | /* Set default port clock if not overwritten by the encoder. Needs to be |
12161 | * done afterwards in case the encoder adjusts the mode. */ | |
12162 | if (!pipe_config->port_clock) | |
2d112de7 | 12163 | pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock |
241bfc38 | 12164 | * pipe_config->pixel_multiplier; |
ff9a6750 | 12165 | |
a43f6e0f | 12166 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 12167 | if (ret < 0) { |
7758a113 DV |
12168 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
12169 | goto fail; | |
ee7b9f93 | 12170 | } |
e29c22c0 DV |
12171 | |
12172 | if (ret == RETRY) { | |
12173 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
12174 | ret = -EINVAL; | |
12175 | goto fail; | |
12176 | } | |
12177 | ||
12178 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
12179 | retry = false; | |
12180 | goto encoder_retry; | |
12181 | } | |
12182 | ||
e8fa4270 DV |
12183 | /* Dithering seems to not pass-through bits correctly when it should, so |
12184 | * only enable it on 6bpc panels. */ | |
12185 | pipe_config->dither = pipe_config->pipe_bpp == 6*3; | |
62f0ace5 | 12186 | DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n", |
d328c9d7 | 12187 | base_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
4e53c2e0 | 12188 | |
7758a113 | 12189 | fail: |
548ee15b | 12190 | return ret; |
ee7b9f93 | 12191 | } |
47f1c6c9 | 12192 | |
ea9d758d | 12193 | static void |
4740b0f2 | 12194 | intel_modeset_update_crtc_state(struct drm_atomic_state *state) |
ea9d758d | 12195 | { |
0a9ab303 ACO |
12196 | struct drm_crtc *crtc; |
12197 | struct drm_crtc_state *crtc_state; | |
8a75d157 | 12198 | int i; |
ea9d758d | 12199 | |
7668851f | 12200 | /* Double check state. */ |
8a75d157 | 12201 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
3cb480bc | 12202 | to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state); |
fc467a22 ML |
12203 | |
12204 | /* Update hwmode for vblank functions */ | |
12205 | if (crtc->state->active) | |
12206 | crtc->hwmode = crtc->state->adjusted_mode; | |
12207 | else | |
12208 | crtc->hwmode.crtc_clock = 0; | |
ea9d758d | 12209 | } |
ea9d758d DV |
12210 | } |
12211 | ||
3bd26263 | 12212 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 12213 | { |
3bd26263 | 12214 | int diff; |
f1f644dc JB |
12215 | |
12216 | if (clock1 == clock2) | |
12217 | return true; | |
12218 | ||
12219 | if (!clock1 || !clock2) | |
12220 | return false; | |
12221 | ||
12222 | diff = abs(clock1 - clock2); | |
12223 | ||
12224 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
12225 | return true; | |
12226 | ||
12227 | return false; | |
12228 | } | |
12229 | ||
25c5b266 DV |
12230 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
12231 | list_for_each_entry((intel_crtc), \ | |
12232 | &(dev)->mode_config.crtc_list, \ | |
12233 | base.head) \ | |
0973f18f | 12234 | if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 12235 | |
cfb23ed6 ML |
12236 | static bool |
12237 | intel_compare_m_n(unsigned int m, unsigned int n, | |
12238 | unsigned int m2, unsigned int n2, | |
12239 | bool exact) | |
12240 | { | |
12241 | if (m == m2 && n == n2) | |
12242 | return true; | |
12243 | ||
12244 | if (exact || !m || !n || !m2 || !n2) | |
12245 | return false; | |
12246 | ||
12247 | BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); | |
12248 | ||
12249 | if (m > m2) { | |
12250 | while (m > m2) { | |
12251 | m2 <<= 1; | |
12252 | n2 <<= 1; | |
12253 | } | |
12254 | } else if (m < m2) { | |
12255 | while (m < m2) { | |
12256 | m <<= 1; | |
12257 | n <<= 1; | |
12258 | } | |
12259 | } | |
12260 | ||
12261 | return m == m2 && n == n2; | |
12262 | } | |
12263 | ||
12264 | static bool | |
12265 | intel_compare_link_m_n(const struct intel_link_m_n *m_n, | |
12266 | struct intel_link_m_n *m2_n2, | |
12267 | bool adjust) | |
12268 | { | |
12269 | if (m_n->tu == m2_n2->tu && | |
12270 | intel_compare_m_n(m_n->gmch_m, m_n->gmch_n, | |
12271 | m2_n2->gmch_m, m2_n2->gmch_n, !adjust) && | |
12272 | intel_compare_m_n(m_n->link_m, m_n->link_n, | |
12273 | m2_n2->link_m, m2_n2->link_n, !adjust)) { | |
12274 | if (adjust) | |
12275 | *m2_n2 = *m_n; | |
12276 | ||
12277 | return true; | |
12278 | } | |
12279 | ||
12280 | return false; | |
12281 | } | |
12282 | ||
0e8ffe1b | 12283 | static bool |
2fa2fe9a | 12284 | intel_pipe_config_compare(struct drm_device *dev, |
5cec258b | 12285 | struct intel_crtc_state *current_config, |
cfb23ed6 ML |
12286 | struct intel_crtc_state *pipe_config, |
12287 | bool adjust) | |
0e8ffe1b | 12288 | { |
cfb23ed6 ML |
12289 | bool ret = true; |
12290 | ||
12291 | #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \ | |
12292 | do { \ | |
12293 | if (!adjust) \ | |
12294 | DRM_ERROR(fmt, ##__VA_ARGS__); \ | |
12295 | else \ | |
12296 | DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \ | |
12297 | } while (0) | |
12298 | ||
66e985c0 DV |
12299 | #define PIPE_CONF_CHECK_X(name) \ |
12300 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 12301 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
66e985c0 DV |
12302 | "(expected 0x%08x, found 0x%08x)\n", \ |
12303 | current_config->name, \ | |
12304 | pipe_config->name); \ | |
cfb23ed6 | 12305 | ret = false; \ |
66e985c0 DV |
12306 | } |
12307 | ||
08a24034 DV |
12308 | #define PIPE_CONF_CHECK_I(name) \ |
12309 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 12310 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
08a24034 DV |
12311 | "(expected %i, found %i)\n", \ |
12312 | current_config->name, \ | |
12313 | pipe_config->name); \ | |
cfb23ed6 ML |
12314 | ret = false; \ |
12315 | } | |
12316 | ||
12317 | #define PIPE_CONF_CHECK_M_N(name) \ | |
12318 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
12319 | &pipe_config->name,\ | |
12320 | adjust)) { \ | |
12321 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12322 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
12323 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
12324 | current_config->name.tu, \ | |
12325 | current_config->name.gmch_m, \ | |
12326 | current_config->name.gmch_n, \ | |
12327 | current_config->name.link_m, \ | |
12328 | current_config->name.link_n, \ | |
12329 | pipe_config->name.tu, \ | |
12330 | pipe_config->name.gmch_m, \ | |
12331 | pipe_config->name.gmch_n, \ | |
12332 | pipe_config->name.link_m, \ | |
12333 | pipe_config->name.link_n); \ | |
12334 | ret = false; \ | |
12335 | } | |
12336 | ||
12337 | #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \ | |
12338 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
12339 | &pipe_config->name, adjust) && \ | |
12340 | !intel_compare_link_m_n(¤t_config->alt_name, \ | |
12341 | &pipe_config->name, adjust)) { \ | |
12342 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12343 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
12344 | "or tu %i gmch %i/%i link %i/%i, " \ | |
12345 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
12346 | current_config->name.tu, \ | |
12347 | current_config->name.gmch_m, \ | |
12348 | current_config->name.gmch_n, \ | |
12349 | current_config->name.link_m, \ | |
12350 | current_config->name.link_n, \ | |
12351 | current_config->alt_name.tu, \ | |
12352 | current_config->alt_name.gmch_m, \ | |
12353 | current_config->alt_name.gmch_n, \ | |
12354 | current_config->alt_name.link_m, \ | |
12355 | current_config->alt_name.link_n, \ | |
12356 | pipe_config->name.tu, \ | |
12357 | pipe_config->name.gmch_m, \ | |
12358 | pipe_config->name.gmch_n, \ | |
12359 | pipe_config->name.link_m, \ | |
12360 | pipe_config->name.link_n); \ | |
12361 | ret = false; \ | |
88adfff1 DV |
12362 | } |
12363 | ||
b95af8be VK |
12364 | /* This is required for BDW+ where there is only one set of registers for |
12365 | * switching between high and low RR. | |
12366 | * This macro can be used whenever a comparison has to be made between one | |
12367 | * hw state and multiple sw state variables. | |
12368 | */ | |
12369 | #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \ | |
12370 | if ((current_config->name != pipe_config->name) && \ | |
12371 | (current_config->alt_name != pipe_config->name)) { \ | |
cfb23ed6 | 12372 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
b95af8be VK |
12373 | "(expected %i or %i, found %i)\n", \ |
12374 | current_config->name, \ | |
12375 | current_config->alt_name, \ | |
12376 | pipe_config->name); \ | |
cfb23ed6 | 12377 | ret = false; \ |
b95af8be VK |
12378 | } |
12379 | ||
1bd1bd80 DV |
12380 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
12381 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
cfb23ed6 | 12382 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
12383 | "(expected %i, found %i)\n", \ |
12384 | current_config->name & (mask), \ | |
12385 | pipe_config->name & (mask)); \ | |
cfb23ed6 | 12386 | ret = false; \ |
1bd1bd80 DV |
12387 | } |
12388 | ||
5e550656 VS |
12389 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
12390 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
cfb23ed6 | 12391 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
5e550656 VS |
12392 | "(expected %i, found %i)\n", \ |
12393 | current_config->name, \ | |
12394 | pipe_config->name); \ | |
cfb23ed6 | 12395 | ret = false; \ |
5e550656 VS |
12396 | } |
12397 | ||
bb760063 DV |
12398 | #define PIPE_CONF_QUIRK(quirk) \ |
12399 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
12400 | ||
eccb140b DV |
12401 | PIPE_CONF_CHECK_I(cpu_transcoder); |
12402 | ||
08a24034 DV |
12403 | PIPE_CONF_CHECK_I(has_pch_encoder); |
12404 | PIPE_CONF_CHECK_I(fdi_lanes); | |
cfb23ed6 | 12405 | PIPE_CONF_CHECK_M_N(fdi_m_n); |
08a24034 | 12406 | |
eb14cb74 | 12407 | PIPE_CONF_CHECK_I(has_dp_encoder); |
90a6b7b0 | 12408 | PIPE_CONF_CHECK_I(lane_count); |
b95af8be VK |
12409 | |
12410 | if (INTEL_INFO(dev)->gen < 8) { | |
cfb23ed6 ML |
12411 | PIPE_CONF_CHECK_M_N(dp_m_n); |
12412 | ||
12413 | PIPE_CONF_CHECK_I(has_drrs); | |
12414 | if (current_config->has_drrs) | |
12415 | PIPE_CONF_CHECK_M_N(dp_m2_n2); | |
12416 | } else | |
12417 | PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); | |
eb14cb74 | 12418 | |
2d112de7 ACO |
12419 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); |
12420 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); | |
12421 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); | |
12422 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); | |
12423 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); | |
12424 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); | |
1bd1bd80 | 12425 | |
2d112de7 ACO |
12426 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); |
12427 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); | |
12428 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); | |
12429 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); | |
12430 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); | |
12431 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); | |
1bd1bd80 | 12432 | |
c93f54cf | 12433 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 12434 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
b5a9fa09 DV |
12435 | if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || |
12436 | IS_VALLEYVIEW(dev)) | |
12437 | PIPE_CONF_CHECK_I(limited_color_range); | |
e43823ec | 12438 | PIPE_CONF_CHECK_I(has_infoframe); |
6c49f241 | 12439 | |
9ed109a7 DV |
12440 | PIPE_CONF_CHECK_I(has_audio); |
12441 | ||
2d112de7 | 12442 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
1bd1bd80 DV |
12443 | DRM_MODE_FLAG_INTERLACE); |
12444 | ||
bb760063 | 12445 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
2d112de7 | 12446 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12447 | DRM_MODE_FLAG_PHSYNC); |
2d112de7 | 12448 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12449 | DRM_MODE_FLAG_NHSYNC); |
2d112de7 | 12450 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12451 | DRM_MODE_FLAG_PVSYNC); |
2d112de7 | 12452 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 DV |
12453 | DRM_MODE_FLAG_NVSYNC); |
12454 | } | |
045ac3b5 | 12455 | |
333b8ca8 | 12456 | PIPE_CONF_CHECK_X(gmch_pfit.control); |
e2ff2d4a DV |
12457 | /* pfit ratios are autocomputed by the hw on gen4+ */ |
12458 | if (INTEL_INFO(dev)->gen < 4) | |
12459 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); | |
333b8ca8 | 12460 | PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); |
9953599b | 12461 | |
bfd16b2a ML |
12462 | if (!adjust) { |
12463 | PIPE_CONF_CHECK_I(pipe_src_w); | |
12464 | PIPE_CONF_CHECK_I(pipe_src_h); | |
12465 | ||
12466 | PIPE_CONF_CHECK_I(pch_pfit.enabled); | |
12467 | if (current_config->pch_pfit.enabled) { | |
12468 | PIPE_CONF_CHECK_X(pch_pfit.pos); | |
12469 | PIPE_CONF_CHECK_X(pch_pfit.size); | |
12470 | } | |
2fa2fe9a | 12471 | |
7aefe2b5 ML |
12472 | PIPE_CONF_CHECK_I(scaler_state.scaler_id); |
12473 | } | |
a1b2278e | 12474 | |
e59150dc JB |
12475 | /* BDW+ don't expose a synchronous way to read the state */ |
12476 | if (IS_HASWELL(dev)) | |
12477 | PIPE_CONF_CHECK_I(ips_enabled); | |
42db64ef | 12478 | |
282740f7 VS |
12479 | PIPE_CONF_CHECK_I(double_wide); |
12480 | ||
26804afd DV |
12481 | PIPE_CONF_CHECK_X(ddi_pll_sel); |
12482 | ||
c0d43d62 | 12483 | PIPE_CONF_CHECK_I(shared_dpll); |
66e985c0 | 12484 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 12485 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
12486 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
12487 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 12488 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
3f4cd19f DL |
12489 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
12490 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); | |
12491 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); | |
c0d43d62 | 12492 | |
42571aef VS |
12493 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
12494 | PIPE_CONF_CHECK_I(pipe_bpp); | |
12495 | ||
2d112de7 | 12496 | PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); |
a9a7e98a | 12497 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
5e550656 | 12498 | |
66e985c0 | 12499 | #undef PIPE_CONF_CHECK_X |
08a24034 | 12500 | #undef PIPE_CONF_CHECK_I |
b95af8be | 12501 | #undef PIPE_CONF_CHECK_I_ALT |
1bd1bd80 | 12502 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 12503 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 12504 | #undef PIPE_CONF_QUIRK |
cfb23ed6 | 12505 | #undef INTEL_ERR_OR_DBG_KMS |
88adfff1 | 12506 | |
cfb23ed6 | 12507 | return ret; |
0e8ffe1b DV |
12508 | } |
12509 | ||
08db6652 DL |
12510 | static void check_wm_state(struct drm_device *dev) |
12511 | { | |
12512 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12513 | struct skl_ddb_allocation hw_ddb, *sw_ddb; | |
12514 | struct intel_crtc *intel_crtc; | |
12515 | int plane; | |
12516 | ||
12517 | if (INTEL_INFO(dev)->gen < 9) | |
12518 | return; | |
12519 | ||
12520 | skl_ddb_get_hw_state(dev_priv, &hw_ddb); | |
12521 | sw_ddb = &dev_priv->wm.skl_hw.ddb; | |
12522 | ||
12523 | for_each_intel_crtc(dev, intel_crtc) { | |
12524 | struct skl_ddb_entry *hw_entry, *sw_entry; | |
12525 | const enum pipe pipe = intel_crtc->pipe; | |
12526 | ||
12527 | if (!intel_crtc->active) | |
12528 | continue; | |
12529 | ||
12530 | /* planes */ | |
dd740780 | 12531 | for_each_plane(dev_priv, pipe, plane) { |
08db6652 DL |
12532 | hw_entry = &hw_ddb.plane[pipe][plane]; |
12533 | sw_entry = &sw_ddb->plane[pipe][plane]; | |
12534 | ||
12535 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
12536 | continue; | |
12537 | ||
12538 | DRM_ERROR("mismatch in DDB state pipe %c plane %d " | |
12539 | "(expected (%u,%u), found (%u,%u))\n", | |
12540 | pipe_name(pipe), plane + 1, | |
12541 | sw_entry->start, sw_entry->end, | |
12542 | hw_entry->start, hw_entry->end); | |
12543 | } | |
12544 | ||
12545 | /* cursor */ | |
12546 | hw_entry = &hw_ddb.cursor[pipe]; | |
12547 | sw_entry = &sw_ddb->cursor[pipe]; | |
12548 | ||
12549 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
12550 | continue; | |
12551 | ||
12552 | DRM_ERROR("mismatch in DDB state pipe %c cursor " | |
12553 | "(expected (%u,%u), found (%u,%u))\n", | |
12554 | pipe_name(pipe), | |
12555 | sw_entry->start, sw_entry->end, | |
12556 | hw_entry->start, hw_entry->end); | |
12557 | } | |
12558 | } | |
12559 | ||
91d1b4bd | 12560 | static void |
35dd3c64 ML |
12561 | check_connector_state(struct drm_device *dev, |
12562 | struct drm_atomic_state *old_state) | |
8af6cf88 | 12563 | { |
35dd3c64 ML |
12564 | struct drm_connector_state *old_conn_state; |
12565 | struct drm_connector *connector; | |
12566 | int i; | |
8af6cf88 | 12567 | |
35dd3c64 ML |
12568 | for_each_connector_in_state(old_state, connector, old_conn_state, i) { |
12569 | struct drm_encoder *encoder = connector->encoder; | |
12570 | struct drm_connector_state *state = connector->state; | |
ad3c558f | 12571 | |
8af6cf88 DV |
12572 | /* This also checks the encoder/connector hw state with the |
12573 | * ->get_hw_state callbacks. */ | |
35dd3c64 | 12574 | intel_connector_check_state(to_intel_connector(connector)); |
8af6cf88 | 12575 | |
ad3c558f | 12576 | I915_STATE_WARN(state->best_encoder != encoder, |
35dd3c64 | 12577 | "connector's atomic encoder doesn't match legacy encoder\n"); |
8af6cf88 | 12578 | } |
91d1b4bd DV |
12579 | } |
12580 | ||
12581 | static void | |
12582 | check_encoder_state(struct drm_device *dev) | |
12583 | { | |
12584 | struct intel_encoder *encoder; | |
12585 | struct intel_connector *connector; | |
8af6cf88 | 12586 | |
b2784e15 | 12587 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 | 12588 | bool enabled = false; |
4d20cd86 | 12589 | enum pipe pipe; |
8af6cf88 DV |
12590 | |
12591 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
12592 | encoder->base.base.id, | |
8e329a03 | 12593 | encoder->base.name); |
8af6cf88 | 12594 | |
3a3371ff | 12595 | for_each_intel_connector(dev, connector) { |
4d20cd86 | 12596 | if (connector->base.state->best_encoder != &encoder->base) |
8af6cf88 DV |
12597 | continue; |
12598 | enabled = true; | |
ad3c558f ML |
12599 | |
12600 | I915_STATE_WARN(connector->base.state->crtc != | |
12601 | encoder->base.crtc, | |
12602 | "connector's crtc doesn't match encoder crtc\n"); | |
8af6cf88 | 12603 | } |
0e32b39c | 12604 | |
e2c719b7 | 12605 | I915_STATE_WARN(!!encoder->base.crtc != enabled, |
8af6cf88 DV |
12606 | "encoder's enabled state mismatch " |
12607 | "(expected %i, found %i)\n", | |
12608 | !!encoder->base.crtc, enabled); | |
7c60d198 ML |
12609 | |
12610 | if (!encoder->base.crtc) { | |
4d20cd86 | 12611 | bool active; |
7c60d198 | 12612 | |
4d20cd86 ML |
12613 | active = encoder->get_hw_state(encoder, &pipe); |
12614 | I915_STATE_WARN(active, | |
12615 | "encoder detached but still enabled on pipe %c.\n", | |
12616 | pipe_name(pipe)); | |
7c60d198 | 12617 | } |
8af6cf88 | 12618 | } |
91d1b4bd DV |
12619 | } |
12620 | ||
12621 | static void | |
4d20cd86 | 12622 | check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state) |
91d1b4bd | 12623 | { |
fbee40df | 12624 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd | 12625 | struct intel_encoder *encoder; |
4d20cd86 ML |
12626 | struct drm_crtc_state *old_crtc_state; |
12627 | struct drm_crtc *crtc; | |
12628 | int i; | |
8af6cf88 | 12629 | |
4d20cd86 ML |
12630 | for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) { |
12631 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
12632 | struct intel_crtc_state *pipe_config, *sw_config; | |
7b89b8de | 12633 | bool active; |
8af6cf88 | 12634 | |
bfd16b2a ML |
12635 | if (!needs_modeset(crtc->state) && |
12636 | !to_intel_crtc_state(crtc->state)->update_pipe) | |
4d20cd86 | 12637 | continue; |
045ac3b5 | 12638 | |
4d20cd86 ML |
12639 | __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state); |
12640 | pipe_config = to_intel_crtc_state(old_crtc_state); | |
12641 | memset(pipe_config, 0, sizeof(*pipe_config)); | |
12642 | pipe_config->base.crtc = crtc; | |
12643 | pipe_config->base.state = old_state; | |
8af6cf88 | 12644 | |
4d20cd86 ML |
12645 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
12646 | crtc->base.id); | |
8af6cf88 | 12647 | |
4d20cd86 ML |
12648 | active = dev_priv->display.get_pipe_config(intel_crtc, |
12649 | pipe_config); | |
d62cf62a | 12650 | |
b6b5d049 | 12651 | /* hw state is inconsistent with the pipe quirk */ |
4d20cd86 ML |
12652 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
12653 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
12654 | active = crtc->state->active; | |
6c49f241 | 12655 | |
4d20cd86 | 12656 | I915_STATE_WARN(crtc->state->active != active, |
0e8ffe1b | 12657 | "crtc active state doesn't match with hw state " |
4d20cd86 | 12658 | "(expected %i, found %i)\n", crtc->state->active, active); |
0e8ffe1b | 12659 | |
4d20cd86 | 12660 | I915_STATE_WARN(intel_crtc->active != crtc->state->active, |
53d9f4e9 | 12661 | "transitional active state does not match atomic hw state " |
4d20cd86 ML |
12662 | "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active); |
12663 | ||
12664 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
12665 | enum pipe pipe; | |
12666 | ||
12667 | active = encoder->get_hw_state(encoder, &pipe); | |
12668 | I915_STATE_WARN(active != crtc->state->active, | |
12669 | "[ENCODER:%i] active %i with crtc active %i\n", | |
12670 | encoder->base.base.id, active, crtc->state->active); | |
12671 | ||
12672 | I915_STATE_WARN(active && intel_crtc->pipe != pipe, | |
12673 | "Encoder connected to wrong pipe %c\n", | |
12674 | pipe_name(pipe)); | |
12675 | ||
12676 | if (active) | |
12677 | encoder->get_config(encoder, pipe_config); | |
12678 | } | |
53d9f4e9 | 12679 | |
4d20cd86 | 12680 | if (!crtc->state->active) |
cfb23ed6 ML |
12681 | continue; |
12682 | ||
4d20cd86 ML |
12683 | sw_config = to_intel_crtc_state(crtc->state); |
12684 | if (!intel_pipe_config_compare(dev, sw_config, | |
12685 | pipe_config, false)) { | |
e2c719b7 | 12686 | I915_STATE_WARN(1, "pipe state doesn't match!\n"); |
4d20cd86 | 12687 | intel_dump_pipe_config(intel_crtc, pipe_config, |
c0b03411 | 12688 | "[hw state]"); |
4d20cd86 | 12689 | intel_dump_pipe_config(intel_crtc, sw_config, |
c0b03411 DV |
12690 | "[sw state]"); |
12691 | } | |
8af6cf88 DV |
12692 | } |
12693 | } | |
12694 | ||
91d1b4bd DV |
12695 | static void |
12696 | check_shared_dpll_state(struct drm_device *dev) | |
12697 | { | |
fbee40df | 12698 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
12699 | struct intel_crtc *crtc; |
12700 | struct intel_dpll_hw_state dpll_hw_state; | |
12701 | int i; | |
5358901f DV |
12702 | |
12703 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
12704 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
12705 | int enabled_crtcs = 0, active_crtcs = 0; | |
12706 | bool active; | |
12707 | ||
12708 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); | |
12709 | ||
12710 | DRM_DEBUG_KMS("%s\n", pll->name); | |
12711 | ||
12712 | active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); | |
12713 | ||
e2c719b7 | 12714 | I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask), |
5358901f | 12715 | "more active pll users than references: %i vs %i\n", |
3e369b76 | 12716 | pll->active, hweight32(pll->config.crtc_mask)); |
e2c719b7 | 12717 | I915_STATE_WARN(pll->active && !pll->on, |
5358901f | 12718 | "pll in active use but not on in sw tracking\n"); |
e2c719b7 | 12719 | I915_STATE_WARN(pll->on && !pll->active, |
35c95375 | 12720 | "pll in on but not on in use in sw tracking\n"); |
e2c719b7 | 12721 | I915_STATE_WARN(pll->on != active, |
5358901f DV |
12722 | "pll on state mismatch (expected %i, found %i)\n", |
12723 | pll->on, active); | |
12724 | ||
d3fcc808 | 12725 | for_each_intel_crtc(dev, crtc) { |
83d65738 | 12726 | if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll) |
5358901f DV |
12727 | enabled_crtcs++; |
12728 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) | |
12729 | active_crtcs++; | |
12730 | } | |
e2c719b7 | 12731 | I915_STATE_WARN(pll->active != active_crtcs, |
5358901f DV |
12732 | "pll active crtcs mismatch (expected %i, found %i)\n", |
12733 | pll->active, active_crtcs); | |
e2c719b7 | 12734 | I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs, |
5358901f | 12735 | "pll enabled crtcs mismatch (expected %i, found %i)\n", |
3e369b76 | 12736 | hweight32(pll->config.crtc_mask), enabled_crtcs); |
66e985c0 | 12737 | |
e2c719b7 | 12738 | I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state, |
66e985c0 DV |
12739 | sizeof(dpll_hw_state)), |
12740 | "pll hw state mismatch\n"); | |
5358901f | 12741 | } |
8af6cf88 DV |
12742 | } |
12743 | ||
ee165b1a ML |
12744 | static void |
12745 | intel_modeset_check_state(struct drm_device *dev, | |
12746 | struct drm_atomic_state *old_state) | |
91d1b4bd | 12747 | { |
08db6652 | 12748 | check_wm_state(dev); |
35dd3c64 | 12749 | check_connector_state(dev, old_state); |
91d1b4bd | 12750 | check_encoder_state(dev); |
4d20cd86 | 12751 | check_crtc_state(dev, old_state); |
91d1b4bd DV |
12752 | check_shared_dpll_state(dev); |
12753 | } | |
12754 | ||
5cec258b | 12755 | void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config, |
18442d08 VS |
12756 | int dotclock) |
12757 | { | |
12758 | /* | |
12759 | * FDI already provided one idea for the dotclock. | |
12760 | * Yell if the encoder disagrees. | |
12761 | */ | |
2d112de7 | 12762 | WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock), |
18442d08 | 12763 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", |
2d112de7 | 12764 | pipe_config->base.adjusted_mode.crtc_clock, dotclock); |
18442d08 VS |
12765 | } |
12766 | ||
80715b2f VS |
12767 | static void update_scanline_offset(struct intel_crtc *crtc) |
12768 | { | |
12769 | struct drm_device *dev = crtc->base.dev; | |
12770 | ||
12771 | /* | |
12772 | * The scanline counter increments at the leading edge of hsync. | |
12773 | * | |
12774 | * On most platforms it starts counting from vtotal-1 on the | |
12775 | * first active line. That means the scanline counter value is | |
12776 | * always one less than what we would expect. Ie. just after | |
12777 | * start of vblank, which also occurs at start of hsync (on the | |
12778 | * last active line), the scanline counter will read vblank_start-1. | |
12779 | * | |
12780 | * On gen2 the scanline counter starts counting from 1 instead | |
12781 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
12782 | * to keep the value positive), instead of adding one. | |
12783 | * | |
12784 | * On HSW+ the behaviour of the scanline counter depends on the output | |
12785 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
12786 | * there's an extra 1 line difference. So we need to add two instead of | |
12787 | * one to the value. | |
12788 | */ | |
12789 | if (IS_GEN2(dev)) { | |
6e3c9717 | 12790 | const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode; |
80715b2f VS |
12791 | int vtotal; |
12792 | ||
12793 | vtotal = mode->crtc_vtotal; | |
12794 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
12795 | vtotal /= 2; | |
12796 | ||
12797 | crtc->scanline_offset = vtotal - 1; | |
12798 | } else if (HAS_DDI(dev) && | |
409ee761 | 12799 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) { |
80715b2f VS |
12800 | crtc->scanline_offset = 2; |
12801 | } else | |
12802 | crtc->scanline_offset = 1; | |
12803 | } | |
12804 | ||
ad421372 | 12805 | static void intel_modeset_clear_plls(struct drm_atomic_state *state) |
ed6739ef | 12806 | { |
225da59b | 12807 | struct drm_device *dev = state->dev; |
ed6739ef | 12808 | struct drm_i915_private *dev_priv = to_i915(dev); |
ad421372 | 12809 | struct intel_shared_dpll_config *shared_dpll = NULL; |
ed6739ef | 12810 | struct intel_crtc *intel_crtc; |
0a9ab303 ACO |
12811 | struct intel_crtc_state *intel_crtc_state; |
12812 | struct drm_crtc *crtc; | |
12813 | struct drm_crtc_state *crtc_state; | |
0a9ab303 | 12814 | int i; |
ed6739ef ACO |
12815 | |
12816 | if (!dev_priv->display.crtc_compute_clock) | |
ad421372 | 12817 | return; |
ed6739ef | 12818 | |
0a9ab303 | 12819 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
ad421372 ML |
12820 | int dpll; |
12821 | ||
0a9ab303 | 12822 | intel_crtc = to_intel_crtc(crtc); |
4978cc93 | 12823 | intel_crtc_state = to_intel_crtc_state(crtc_state); |
ad421372 | 12824 | dpll = intel_crtc_state->shared_dpll; |
0a9ab303 | 12825 | |
ad421372 | 12826 | if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE) |
225da59b ACO |
12827 | continue; |
12828 | ||
ad421372 | 12829 | intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE; |
0a9ab303 | 12830 | |
ad421372 ML |
12831 | if (!shared_dpll) |
12832 | shared_dpll = intel_atomic_get_shared_dpll_state(state); | |
ed6739ef | 12833 | |
ad421372 ML |
12834 | shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe); |
12835 | } | |
ed6739ef ACO |
12836 | } |
12837 | ||
99d736a2 ML |
12838 | /* |
12839 | * This implements the workaround described in the "notes" section of the mode | |
12840 | * set sequence documentation. When going from no pipes or single pipe to | |
12841 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
12842 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
12843 | */ | |
12844 | static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state) | |
12845 | { | |
12846 | struct drm_crtc_state *crtc_state; | |
12847 | struct intel_crtc *intel_crtc; | |
12848 | struct drm_crtc *crtc; | |
12849 | struct intel_crtc_state *first_crtc_state = NULL; | |
12850 | struct intel_crtc_state *other_crtc_state = NULL; | |
12851 | enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; | |
12852 | int i; | |
12853 | ||
12854 | /* look at all crtc's that are going to be enabled in during modeset */ | |
12855 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
12856 | intel_crtc = to_intel_crtc(crtc); | |
12857 | ||
12858 | if (!crtc_state->active || !needs_modeset(crtc_state)) | |
12859 | continue; | |
12860 | ||
12861 | if (first_crtc_state) { | |
12862 | other_crtc_state = to_intel_crtc_state(crtc_state); | |
12863 | break; | |
12864 | } else { | |
12865 | first_crtc_state = to_intel_crtc_state(crtc_state); | |
12866 | first_pipe = intel_crtc->pipe; | |
12867 | } | |
12868 | } | |
12869 | ||
12870 | /* No workaround needed? */ | |
12871 | if (!first_crtc_state) | |
12872 | return 0; | |
12873 | ||
12874 | /* w/a possibly needed, check how many crtc's are already enabled. */ | |
12875 | for_each_intel_crtc(state->dev, intel_crtc) { | |
12876 | struct intel_crtc_state *pipe_config; | |
12877 | ||
12878 | pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); | |
12879 | if (IS_ERR(pipe_config)) | |
12880 | return PTR_ERR(pipe_config); | |
12881 | ||
12882 | pipe_config->hsw_workaround_pipe = INVALID_PIPE; | |
12883 | ||
12884 | if (!pipe_config->base.active || | |
12885 | needs_modeset(&pipe_config->base)) | |
12886 | continue; | |
12887 | ||
12888 | /* 2 or more enabled crtcs means no need for w/a */ | |
12889 | if (enabled_pipe != INVALID_PIPE) | |
12890 | return 0; | |
12891 | ||
12892 | enabled_pipe = intel_crtc->pipe; | |
12893 | } | |
12894 | ||
12895 | if (enabled_pipe != INVALID_PIPE) | |
12896 | first_crtc_state->hsw_workaround_pipe = enabled_pipe; | |
12897 | else if (other_crtc_state) | |
12898 | other_crtc_state->hsw_workaround_pipe = first_pipe; | |
12899 | ||
12900 | return 0; | |
12901 | } | |
12902 | ||
27c329ed ML |
12903 | static int intel_modeset_all_pipes(struct drm_atomic_state *state) |
12904 | { | |
12905 | struct drm_crtc *crtc; | |
12906 | struct drm_crtc_state *crtc_state; | |
12907 | int ret = 0; | |
12908 | ||
12909 | /* add all active pipes to the state */ | |
12910 | for_each_crtc(state->dev, crtc) { | |
12911 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
12912 | if (IS_ERR(crtc_state)) | |
12913 | return PTR_ERR(crtc_state); | |
12914 | ||
12915 | if (!crtc_state->active || needs_modeset(crtc_state)) | |
12916 | continue; | |
12917 | ||
12918 | crtc_state->mode_changed = true; | |
12919 | ||
12920 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
12921 | if (ret) | |
12922 | break; | |
12923 | ||
12924 | ret = drm_atomic_add_affected_planes(state, crtc); | |
12925 | if (ret) | |
12926 | break; | |
12927 | } | |
12928 | ||
12929 | return ret; | |
12930 | } | |
12931 | ||
c347a676 | 12932 | static int intel_modeset_checks(struct drm_atomic_state *state) |
054518dd ACO |
12933 | { |
12934 | struct drm_device *dev = state->dev; | |
27c329ed | 12935 | struct drm_i915_private *dev_priv = dev->dev_private; |
054518dd ACO |
12936 | int ret; |
12937 | ||
b359283a ML |
12938 | if (!check_digital_port_conflicts(state)) { |
12939 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); | |
12940 | return -EINVAL; | |
12941 | } | |
12942 | ||
054518dd ACO |
12943 | /* |
12944 | * See if the config requires any additional preparation, e.g. | |
12945 | * to adjust global state with pipes off. We need to do this | |
12946 | * here so we can get the modeset_pipe updated config for the new | |
12947 | * mode set on this crtc. For other crtcs we need to use the | |
12948 | * adjusted_mode bits in the crtc directly. | |
12949 | */ | |
27c329ed ML |
12950 | if (dev_priv->display.modeset_calc_cdclk) { |
12951 | unsigned int cdclk; | |
b432e5cf | 12952 | |
27c329ed ML |
12953 | ret = dev_priv->display.modeset_calc_cdclk(state); |
12954 | ||
12955 | cdclk = to_intel_atomic_state(state)->cdclk; | |
12956 | if (!ret && cdclk != dev_priv->cdclk_freq) | |
12957 | ret = intel_modeset_all_pipes(state); | |
12958 | ||
12959 | if (ret < 0) | |
054518dd | 12960 | return ret; |
27c329ed ML |
12961 | } else |
12962 | to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq; | |
054518dd | 12963 | |
ad421372 | 12964 | intel_modeset_clear_plls(state); |
054518dd | 12965 | |
99d736a2 | 12966 | if (IS_HASWELL(dev)) |
ad421372 | 12967 | return haswell_mode_set_planes_workaround(state); |
99d736a2 | 12968 | |
ad421372 | 12969 | return 0; |
c347a676 ACO |
12970 | } |
12971 | ||
74c090b1 ML |
12972 | /** |
12973 | * intel_atomic_check - validate state object | |
12974 | * @dev: drm device | |
12975 | * @state: state to validate | |
12976 | */ | |
12977 | static int intel_atomic_check(struct drm_device *dev, | |
12978 | struct drm_atomic_state *state) | |
c347a676 ACO |
12979 | { |
12980 | struct drm_crtc *crtc; | |
12981 | struct drm_crtc_state *crtc_state; | |
12982 | int ret, i; | |
61333b60 | 12983 | bool any_ms = false; |
c347a676 | 12984 | |
74c090b1 | 12985 | ret = drm_atomic_helper_check_modeset(dev, state); |
054518dd ACO |
12986 | if (ret) |
12987 | return ret; | |
12988 | ||
c347a676 | 12989 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
cfb23ed6 ML |
12990 | struct intel_crtc_state *pipe_config = |
12991 | to_intel_crtc_state(crtc_state); | |
1ed51de9 DV |
12992 | |
12993 | /* Catch I915_MODE_FLAG_INHERITED */ | |
12994 | if (crtc_state->mode.private_flags != crtc->state->mode.private_flags) | |
12995 | crtc_state->mode_changed = true; | |
cfb23ed6 | 12996 | |
61333b60 ML |
12997 | if (!crtc_state->enable) { |
12998 | if (needs_modeset(crtc_state)) | |
12999 | any_ms = true; | |
c347a676 | 13000 | continue; |
61333b60 | 13001 | } |
c347a676 | 13002 | |
26495481 | 13003 | if (!needs_modeset(crtc_state)) |
cfb23ed6 ML |
13004 | continue; |
13005 | ||
26495481 DV |
13006 | /* FIXME: For only active_changed we shouldn't need to do any |
13007 | * state recomputation at all. */ | |
13008 | ||
1ed51de9 DV |
13009 | ret = drm_atomic_add_affected_connectors(state, crtc); |
13010 | if (ret) | |
13011 | return ret; | |
b359283a | 13012 | |
cfb23ed6 | 13013 | ret = intel_modeset_pipe_config(crtc, pipe_config); |
c347a676 ACO |
13014 | if (ret) |
13015 | return ret; | |
13016 | ||
6764e9f8 | 13017 | if (intel_pipe_config_compare(state->dev, |
cfb23ed6 | 13018 | to_intel_crtc_state(crtc->state), |
1ed51de9 | 13019 | pipe_config, true)) { |
26495481 | 13020 | crtc_state->mode_changed = false; |
bfd16b2a | 13021 | to_intel_crtc_state(crtc_state)->update_pipe = true; |
26495481 DV |
13022 | } |
13023 | ||
13024 | if (needs_modeset(crtc_state)) { | |
13025 | any_ms = true; | |
cfb23ed6 ML |
13026 | |
13027 | ret = drm_atomic_add_affected_planes(state, crtc); | |
13028 | if (ret) | |
13029 | return ret; | |
13030 | } | |
61333b60 | 13031 | |
26495481 DV |
13032 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
13033 | needs_modeset(crtc_state) ? | |
13034 | "[modeset]" : "[fastset]"); | |
c347a676 ACO |
13035 | } |
13036 | ||
61333b60 ML |
13037 | if (any_ms) { |
13038 | ret = intel_modeset_checks(state); | |
13039 | ||
13040 | if (ret) | |
13041 | return ret; | |
27c329ed ML |
13042 | } else |
13043 | to_intel_atomic_state(state)->cdclk = | |
13044 | to_i915(state->dev)->cdclk_freq; | |
c347a676 ACO |
13045 | |
13046 | return drm_atomic_helper_check_planes(state->dev, state); | |
054518dd ACO |
13047 | } |
13048 | ||
74c090b1 ML |
13049 | /** |
13050 | * intel_atomic_commit - commit validated state object | |
13051 | * @dev: DRM device | |
13052 | * @state: the top-level driver state object | |
13053 | * @async: asynchronous commit | |
13054 | * | |
13055 | * This function commits a top-level state object that has been validated | |
13056 | * with drm_atomic_helper_check(). | |
13057 | * | |
13058 | * FIXME: Atomic modeset support for i915 is not yet complete. At the moment | |
13059 | * we can only handle plane-related operations and do not yet support | |
13060 | * asynchronous commit. | |
13061 | * | |
13062 | * RETURNS | |
13063 | * Zero for success or -errno. | |
13064 | */ | |
13065 | static int intel_atomic_commit(struct drm_device *dev, | |
13066 | struct drm_atomic_state *state, | |
13067 | bool async) | |
a6778b3c | 13068 | { |
fbee40df | 13069 | struct drm_i915_private *dev_priv = dev->dev_private; |
0a9ab303 ACO |
13070 | struct drm_crtc *crtc; |
13071 | struct drm_crtc_state *crtc_state; | |
c0c36b94 | 13072 | int ret = 0; |
0a9ab303 | 13073 | int i; |
61333b60 | 13074 | bool any_ms = false; |
a6778b3c | 13075 | |
74c090b1 ML |
13076 | if (async) { |
13077 | DRM_DEBUG_KMS("i915 does not yet support async commit\n"); | |
13078 | return -EINVAL; | |
13079 | } | |
13080 | ||
d4afb8cc ACO |
13081 | ret = drm_atomic_helper_prepare_planes(dev, state); |
13082 | if (ret) | |
13083 | return ret; | |
13084 | ||
1c5e19f8 ML |
13085 | drm_atomic_helper_swap_state(dev, state); |
13086 | ||
0a9ab303 | 13087 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
a539205a ML |
13088 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13089 | ||
61333b60 ML |
13090 | if (!needs_modeset(crtc->state)) |
13091 | continue; | |
13092 | ||
13093 | any_ms = true; | |
a539205a | 13094 | intel_pre_plane_update(intel_crtc); |
460da916 | 13095 | |
a539205a ML |
13096 | if (crtc_state->active) { |
13097 | intel_crtc_disable_planes(crtc, crtc_state->plane_mask); | |
13098 | dev_priv->display.crtc_disable(crtc); | |
eddfcbcd ML |
13099 | intel_crtc->active = false; |
13100 | intel_disable_shared_dpll(intel_crtc); | |
a539205a | 13101 | } |
b8cecdf5 | 13102 | } |
7758a113 | 13103 | |
ea9d758d DV |
13104 | /* Only after disabling all output pipelines that will be changed can we |
13105 | * update the the output configuration. */ | |
4740b0f2 | 13106 | intel_modeset_update_crtc_state(state); |
f6e5b160 | 13107 | |
4740b0f2 ML |
13108 | if (any_ms) { |
13109 | intel_shared_dpll_commit(state); | |
13110 | ||
13111 | drm_atomic_helper_update_legacy_modeset_state(state->dev, state); | |
61333b60 | 13112 | modeset_update_crtc_power_domains(state); |
4740b0f2 | 13113 | } |
47fab737 | 13114 | |
a6778b3c | 13115 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
0a9ab303 | 13116 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
f6ac4b2a ML |
13117 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13118 | bool modeset = needs_modeset(crtc->state); | |
bfd16b2a ML |
13119 | bool update_pipe = !modeset && |
13120 | to_intel_crtc_state(crtc->state)->update_pipe; | |
13121 | unsigned long put_domains = 0; | |
f6ac4b2a ML |
13122 | |
13123 | if (modeset && crtc->state->active) { | |
a539205a ML |
13124 | update_scanline_offset(to_intel_crtc(crtc)); |
13125 | dev_priv->display.crtc_enable(crtc); | |
13126 | } | |
80715b2f | 13127 | |
bfd16b2a ML |
13128 | if (update_pipe) { |
13129 | put_domains = modeset_get_crtc_power_domains(crtc); | |
13130 | ||
13131 | /* make sure intel_modeset_check_state runs */ | |
13132 | any_ms = true; | |
13133 | } | |
13134 | ||
f6ac4b2a ML |
13135 | if (!modeset) |
13136 | intel_pre_plane_update(intel_crtc); | |
13137 | ||
a539205a | 13138 | drm_atomic_helper_commit_planes_on_crtc(crtc_state); |
bfd16b2a ML |
13139 | |
13140 | if (put_domains) | |
13141 | modeset_put_power_domains(dev_priv, put_domains); | |
13142 | ||
f6ac4b2a | 13143 | intel_post_plane_update(intel_crtc); |
80715b2f | 13144 | } |
a6778b3c | 13145 | |
a6778b3c | 13146 | /* FIXME: add subpixel order */ |
83a57153 | 13147 | |
74c090b1 | 13148 | drm_atomic_helper_wait_for_vblanks(dev, state); |
d4afb8cc | 13149 | drm_atomic_helper_cleanup_planes(dev, state); |
2bfb4627 | 13150 | |
74c090b1 | 13151 | if (any_ms) |
ee165b1a ML |
13152 | intel_modeset_check_state(dev, state); |
13153 | ||
13154 | drm_atomic_state_free(state); | |
f30da187 | 13155 | |
74c090b1 | 13156 | return 0; |
7f27126e JB |
13157 | } |
13158 | ||
c0c36b94 CW |
13159 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
13160 | { | |
83a57153 ACO |
13161 | struct drm_device *dev = crtc->dev; |
13162 | struct drm_atomic_state *state; | |
e694eb02 | 13163 | struct drm_crtc_state *crtc_state; |
2bfb4627 | 13164 | int ret; |
83a57153 ACO |
13165 | |
13166 | state = drm_atomic_state_alloc(dev); | |
13167 | if (!state) { | |
e694eb02 | 13168 | DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory", |
83a57153 ACO |
13169 | crtc->base.id); |
13170 | return; | |
13171 | } | |
13172 | ||
e694eb02 | 13173 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); |
83a57153 | 13174 | |
e694eb02 ML |
13175 | retry: |
13176 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
13177 | ret = PTR_ERR_OR_ZERO(crtc_state); | |
13178 | if (!ret) { | |
13179 | if (!crtc_state->active) | |
13180 | goto out; | |
83a57153 | 13181 | |
e694eb02 | 13182 | crtc_state->mode_changed = true; |
74c090b1 | 13183 | ret = drm_atomic_commit(state); |
83a57153 ACO |
13184 | } |
13185 | ||
e694eb02 ML |
13186 | if (ret == -EDEADLK) { |
13187 | drm_atomic_state_clear(state); | |
13188 | drm_modeset_backoff(state->acquire_ctx); | |
13189 | goto retry; | |
4ed9fb37 | 13190 | } |
4be07317 | 13191 | |
2bfb4627 | 13192 | if (ret) |
e694eb02 | 13193 | out: |
2bfb4627 | 13194 | drm_atomic_state_free(state); |
c0c36b94 CW |
13195 | } |
13196 | ||
25c5b266 DV |
13197 | #undef for_each_intel_crtc_masked |
13198 | ||
f6e5b160 | 13199 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
f6e5b160 | 13200 | .gamma_set = intel_crtc_gamma_set, |
74c090b1 | 13201 | .set_config = drm_atomic_helper_set_config, |
f6e5b160 CW |
13202 | .destroy = intel_crtc_destroy, |
13203 | .page_flip = intel_crtc_page_flip, | |
1356837e MR |
13204 | .atomic_duplicate_state = intel_crtc_duplicate_state, |
13205 | .atomic_destroy_state = intel_crtc_destroy_state, | |
f6e5b160 CW |
13206 | }; |
13207 | ||
5358901f DV |
13208 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
13209 | struct intel_shared_dpll *pll, | |
13210 | struct intel_dpll_hw_state *hw_state) | |
ee7b9f93 | 13211 | { |
5358901f | 13212 | uint32_t val; |
ee7b9f93 | 13213 | |
f458ebbc | 13214 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
bd2bb1b9 PZ |
13215 | return false; |
13216 | ||
5358901f | 13217 | val = I915_READ(PCH_DPLL(pll->id)); |
66e985c0 DV |
13218 | hw_state->dpll = val; |
13219 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); | |
13220 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); | |
5358901f DV |
13221 | |
13222 | return val & DPLL_VCO_ENABLE; | |
13223 | } | |
13224 | ||
15bdd4cf DV |
13225 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
13226 | struct intel_shared_dpll *pll) | |
13227 | { | |
3e369b76 ACO |
13228 | I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0); |
13229 | I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1); | |
15bdd4cf DV |
13230 | } |
13231 | ||
e7b903d2 DV |
13232 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
13233 | struct intel_shared_dpll *pll) | |
13234 | { | |
e7b903d2 | 13235 | /* PCH refclock must be enabled first */ |
89eff4be | 13236 | ibx_assert_pch_refclk_enabled(dev_priv); |
e7b903d2 | 13237 | |
3e369b76 | 13238 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf DV |
13239 | |
13240 | /* Wait for the clocks to stabilize. */ | |
13241 | POSTING_READ(PCH_DPLL(pll->id)); | |
13242 | udelay(150); | |
13243 | ||
13244 | /* The pixel multiplier can only be updated once the | |
13245 | * DPLL is enabled and the clocks are stable. | |
13246 | * | |
13247 | * So write it again. | |
13248 | */ | |
3e369b76 | 13249 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf | 13250 | POSTING_READ(PCH_DPLL(pll->id)); |
e7b903d2 DV |
13251 | udelay(200); |
13252 | } | |
13253 | ||
13254 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, | |
13255 | struct intel_shared_dpll *pll) | |
13256 | { | |
13257 | struct drm_device *dev = dev_priv->dev; | |
13258 | struct intel_crtc *crtc; | |
e7b903d2 DV |
13259 | |
13260 | /* Make sure no transcoder isn't still depending on us. */ | |
d3fcc808 | 13261 | for_each_intel_crtc(dev, crtc) { |
e7b903d2 DV |
13262 | if (intel_crtc_to_shared_dpll(crtc) == pll) |
13263 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); | |
ee7b9f93 JB |
13264 | } |
13265 | ||
15bdd4cf DV |
13266 | I915_WRITE(PCH_DPLL(pll->id), 0); |
13267 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
13268 | udelay(200); |
13269 | } | |
13270 | ||
46edb027 DV |
13271 | static char *ibx_pch_dpll_names[] = { |
13272 | "PCH DPLL A", | |
13273 | "PCH DPLL B", | |
13274 | }; | |
13275 | ||
7c74ade1 | 13276 | static void ibx_pch_dpll_init(struct drm_device *dev) |
ee7b9f93 | 13277 | { |
e7b903d2 | 13278 | struct drm_i915_private *dev_priv = dev->dev_private; |
ee7b9f93 JB |
13279 | int i; |
13280 | ||
7c74ade1 | 13281 | dev_priv->num_shared_dpll = 2; |
ee7b9f93 | 13282 | |
e72f9fbf | 13283 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
46edb027 DV |
13284 | dev_priv->shared_dplls[i].id = i; |
13285 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; | |
15bdd4cf | 13286 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
e7b903d2 DV |
13287 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
13288 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; | |
5358901f DV |
13289 | dev_priv->shared_dplls[i].get_hw_state = |
13290 | ibx_pch_dpll_get_hw_state; | |
ee7b9f93 JB |
13291 | } |
13292 | } | |
13293 | ||
7c74ade1 DV |
13294 | static void intel_shared_dpll_init(struct drm_device *dev) |
13295 | { | |
e7b903d2 | 13296 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c74ade1 | 13297 | |
b6283055 VS |
13298 | intel_update_cdclk(dev); |
13299 | ||
9cd86933 DV |
13300 | if (HAS_DDI(dev)) |
13301 | intel_ddi_pll_init(dev); | |
13302 | else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
7c74ade1 DV |
13303 | ibx_pch_dpll_init(dev); |
13304 | else | |
13305 | dev_priv->num_shared_dpll = 0; | |
13306 | ||
13307 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); | |
7c74ade1 DV |
13308 | } |
13309 | ||
6beb8c23 MR |
13310 | /** |
13311 | * intel_prepare_plane_fb - Prepare fb for usage on plane | |
13312 | * @plane: drm plane to prepare for | |
13313 | * @fb: framebuffer to prepare for presentation | |
13314 | * | |
13315 | * Prepares a framebuffer for usage on a display plane. Generally this | |
13316 | * involves pinning the underlying object and updating the frontbuffer tracking | |
13317 | * bits. Some older platforms need special physical address handling for | |
13318 | * cursor planes. | |
13319 | * | |
13320 | * Returns 0 on success, negative error code on failure. | |
13321 | */ | |
13322 | int | |
13323 | intel_prepare_plane_fb(struct drm_plane *plane, | |
d136dfee TU |
13324 | struct drm_framebuffer *fb, |
13325 | const struct drm_plane_state *new_state) | |
465c120c MR |
13326 | { |
13327 | struct drm_device *dev = plane->dev; | |
6beb8c23 | 13328 | struct intel_plane *intel_plane = to_intel_plane(plane); |
6beb8c23 MR |
13329 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
13330 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb); | |
6beb8c23 | 13331 | int ret = 0; |
465c120c | 13332 | |
ea2c67bb | 13333 | if (!obj) |
465c120c MR |
13334 | return 0; |
13335 | ||
6beb8c23 | 13336 | mutex_lock(&dev->struct_mutex); |
465c120c | 13337 | |
6beb8c23 MR |
13338 | if (plane->type == DRM_PLANE_TYPE_CURSOR && |
13339 | INTEL_INFO(dev)->cursor_needs_physical) { | |
13340 | int align = IS_I830(dev) ? 16 * 1024 : 256; | |
13341 | ret = i915_gem_object_attach_phys(obj, align); | |
13342 | if (ret) | |
13343 | DRM_DEBUG_KMS("failed to attach phys object\n"); | |
13344 | } else { | |
91af127f | 13345 | ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL); |
6beb8c23 | 13346 | } |
465c120c | 13347 | |
6beb8c23 | 13348 | if (ret == 0) |
a9ff8714 | 13349 | i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit); |
fdd508a6 | 13350 | |
4c34574f | 13351 | mutex_unlock(&dev->struct_mutex); |
465c120c | 13352 | |
6beb8c23 MR |
13353 | return ret; |
13354 | } | |
13355 | ||
38f3ce3a MR |
13356 | /** |
13357 | * intel_cleanup_plane_fb - Cleans up an fb after plane use | |
13358 | * @plane: drm plane to clean up for | |
13359 | * @fb: old framebuffer that was on plane | |
13360 | * | |
13361 | * Cleans up a framebuffer that has just been removed from a plane. | |
13362 | */ | |
13363 | void | |
13364 | intel_cleanup_plane_fb(struct drm_plane *plane, | |
d136dfee TU |
13365 | struct drm_framebuffer *fb, |
13366 | const struct drm_plane_state *old_state) | |
38f3ce3a MR |
13367 | { |
13368 | struct drm_device *dev = plane->dev; | |
13369 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
13370 | ||
13371 | if (WARN_ON(!obj)) | |
13372 | return; | |
13373 | ||
13374 | if (plane->type != DRM_PLANE_TYPE_CURSOR || | |
13375 | !INTEL_INFO(dev)->cursor_needs_physical) { | |
13376 | mutex_lock(&dev->struct_mutex); | |
82bc3b2d | 13377 | intel_unpin_fb_obj(fb, old_state); |
38f3ce3a MR |
13378 | mutex_unlock(&dev->struct_mutex); |
13379 | } | |
465c120c MR |
13380 | } |
13381 | ||
6156a456 CK |
13382 | int |
13383 | skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) | |
13384 | { | |
13385 | int max_scale; | |
13386 | struct drm_device *dev; | |
13387 | struct drm_i915_private *dev_priv; | |
13388 | int crtc_clock, cdclk; | |
13389 | ||
13390 | if (!intel_crtc || !crtc_state) | |
13391 | return DRM_PLANE_HELPER_NO_SCALING; | |
13392 | ||
13393 | dev = intel_crtc->base.dev; | |
13394 | dev_priv = dev->dev_private; | |
13395 | crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; | |
27c329ed | 13396 | cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk; |
6156a456 CK |
13397 | |
13398 | if (!crtc_clock || !cdclk) | |
13399 | return DRM_PLANE_HELPER_NO_SCALING; | |
13400 | ||
13401 | /* | |
13402 | * skl max scale is lower of: | |
13403 | * close to 3 but not 3, -1 is for that purpose | |
13404 | * or | |
13405 | * cdclk/crtc_clock | |
13406 | */ | |
13407 | max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock)); | |
13408 | ||
13409 | return max_scale; | |
13410 | } | |
13411 | ||
465c120c | 13412 | static int |
3c692a41 | 13413 | intel_check_primary_plane(struct drm_plane *plane, |
061e4b8d | 13414 | struct intel_crtc_state *crtc_state, |
3c692a41 GP |
13415 | struct intel_plane_state *state) |
13416 | { | |
2b875c22 MR |
13417 | struct drm_crtc *crtc = state->base.crtc; |
13418 | struct drm_framebuffer *fb = state->base.fb; | |
6156a456 | 13419 | int min_scale = DRM_PLANE_HELPER_NO_SCALING; |
061e4b8d ML |
13420 | int max_scale = DRM_PLANE_HELPER_NO_SCALING; |
13421 | bool can_position = false; | |
465c120c | 13422 | |
061e4b8d ML |
13423 | /* use scaler when colorkey is not required */ |
13424 | if (INTEL_INFO(plane->dev)->gen >= 9 && | |
818ed961 | 13425 | state->ckey.flags == I915_SET_COLORKEY_NONE) { |
061e4b8d ML |
13426 | min_scale = 1; |
13427 | max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state); | |
d8106366 | 13428 | can_position = true; |
6156a456 | 13429 | } |
d8106366 | 13430 | |
061e4b8d ML |
13431 | return drm_plane_helper_check_update(plane, crtc, fb, &state->src, |
13432 | &state->dst, &state->clip, | |
da20eabd ML |
13433 | min_scale, max_scale, |
13434 | can_position, true, | |
13435 | &state->visible); | |
14af293f GP |
13436 | } |
13437 | ||
13438 | static void | |
13439 | intel_commit_primary_plane(struct drm_plane *plane, | |
13440 | struct intel_plane_state *state) | |
13441 | { | |
2b875c22 MR |
13442 | struct drm_crtc *crtc = state->base.crtc; |
13443 | struct drm_framebuffer *fb = state->base.fb; | |
13444 | struct drm_device *dev = plane->dev; | |
14af293f | 13445 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea2c67bb | 13446 | struct intel_crtc *intel_crtc; |
14af293f GP |
13447 | struct drm_rect *src = &state->src; |
13448 | ||
ea2c67bb MR |
13449 | crtc = crtc ? crtc : plane->crtc; |
13450 | intel_crtc = to_intel_crtc(crtc); | |
cf4c7c12 MR |
13451 | |
13452 | plane->fb = fb; | |
9dc806fc MR |
13453 | crtc->x = src->x1 >> 16; |
13454 | crtc->y = src->y1 >> 16; | |
ccc759dc | 13455 | |
a539205a | 13456 | if (!crtc->state->active) |
302d19ac | 13457 | return; |
465c120c | 13458 | |
d4b08630 ML |
13459 | dev_priv->display.update_primary_plane(crtc, fb, |
13460 | state->src.x1 >> 16, | |
13461 | state->src.y1 >> 16); | |
465c120c MR |
13462 | } |
13463 | ||
a8ad0d8e ML |
13464 | static void |
13465 | intel_disable_primary_plane(struct drm_plane *plane, | |
7fabf5ef | 13466 | struct drm_crtc *crtc) |
a8ad0d8e ML |
13467 | { |
13468 | struct drm_device *dev = plane->dev; | |
13469 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13470 | ||
a8ad0d8e ML |
13471 | dev_priv->display.update_primary_plane(crtc, NULL, 0, 0); |
13472 | } | |
13473 | ||
613d2b27 ML |
13474 | static void intel_begin_crtc_commit(struct drm_crtc *crtc, |
13475 | struct drm_crtc_state *old_crtc_state) | |
3c692a41 | 13476 | { |
32b7eeec | 13477 | struct drm_device *dev = crtc->dev; |
3c692a41 | 13478 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
bfd16b2a ML |
13479 | struct intel_crtc_state *old_intel_state = |
13480 | to_intel_crtc_state(old_crtc_state); | |
13481 | bool modeset = needs_modeset(crtc->state); | |
3c692a41 | 13482 | |
f015c551 | 13483 | if (intel_crtc->atomic.update_wm_pre) |
32b7eeec | 13484 | intel_update_watermarks(crtc); |
3c692a41 | 13485 | |
c34c9ee4 | 13486 | /* Perform vblank evasion around commit operation */ |
a539205a | 13487 | if (crtc->state->active) |
34e0adbb | 13488 | intel_pipe_update_start(intel_crtc); |
0583236e | 13489 | |
bfd16b2a ML |
13490 | if (modeset) |
13491 | return; | |
13492 | ||
13493 | if (to_intel_crtc_state(crtc->state)->update_pipe) | |
13494 | intel_update_pipe_config(intel_crtc, old_intel_state); | |
13495 | else if (INTEL_INFO(dev)->gen >= 9) | |
0583236e | 13496 | skl_detach_scalers(intel_crtc); |
32b7eeec MR |
13497 | } |
13498 | ||
613d2b27 ML |
13499 | static void intel_finish_crtc_commit(struct drm_crtc *crtc, |
13500 | struct drm_crtc_state *old_crtc_state) | |
32b7eeec | 13501 | { |
32b7eeec | 13502 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
32b7eeec | 13503 | |
8f539a83 | 13504 | if (crtc->state->active) |
34e0adbb | 13505 | intel_pipe_update_end(intel_crtc); |
3c692a41 GP |
13506 | } |
13507 | ||
cf4c7c12 | 13508 | /** |
4a3b8769 MR |
13509 | * intel_plane_destroy - destroy a plane |
13510 | * @plane: plane to destroy | |
cf4c7c12 | 13511 | * |
4a3b8769 MR |
13512 | * Common destruction function for all types of planes (primary, cursor, |
13513 | * sprite). | |
cf4c7c12 | 13514 | */ |
4a3b8769 | 13515 | void intel_plane_destroy(struct drm_plane *plane) |
465c120c MR |
13516 | { |
13517 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
13518 | drm_plane_cleanup(plane); | |
13519 | kfree(intel_plane); | |
13520 | } | |
13521 | ||
65a3fea0 | 13522 | const struct drm_plane_funcs intel_plane_funcs = { |
70a101f8 MR |
13523 | .update_plane = drm_atomic_helper_update_plane, |
13524 | .disable_plane = drm_atomic_helper_disable_plane, | |
3d7d6510 | 13525 | .destroy = intel_plane_destroy, |
c196e1d6 | 13526 | .set_property = drm_atomic_helper_plane_set_property, |
a98b3431 MR |
13527 | .atomic_get_property = intel_plane_atomic_get_property, |
13528 | .atomic_set_property = intel_plane_atomic_set_property, | |
ea2c67bb MR |
13529 | .atomic_duplicate_state = intel_plane_duplicate_state, |
13530 | .atomic_destroy_state = intel_plane_destroy_state, | |
13531 | ||
465c120c MR |
13532 | }; |
13533 | ||
13534 | static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, | |
13535 | int pipe) | |
13536 | { | |
13537 | struct intel_plane *primary; | |
8e7d688b | 13538 | struct intel_plane_state *state; |
465c120c | 13539 | const uint32_t *intel_primary_formats; |
45e3743a | 13540 | unsigned int num_formats; |
465c120c MR |
13541 | |
13542 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
13543 | if (primary == NULL) | |
13544 | return NULL; | |
13545 | ||
8e7d688b MR |
13546 | state = intel_create_plane_state(&primary->base); |
13547 | if (!state) { | |
ea2c67bb MR |
13548 | kfree(primary); |
13549 | return NULL; | |
13550 | } | |
8e7d688b | 13551 | primary->base.state = &state->base; |
ea2c67bb | 13552 | |
465c120c MR |
13553 | primary->can_scale = false; |
13554 | primary->max_downscale = 1; | |
6156a456 CK |
13555 | if (INTEL_INFO(dev)->gen >= 9) { |
13556 | primary->can_scale = true; | |
af99ceda | 13557 | state->scaler_id = -1; |
6156a456 | 13558 | } |
465c120c MR |
13559 | primary->pipe = pipe; |
13560 | primary->plane = pipe; | |
a9ff8714 | 13561 | primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe); |
c59cb179 MR |
13562 | primary->check_plane = intel_check_primary_plane; |
13563 | primary->commit_plane = intel_commit_primary_plane; | |
a8ad0d8e | 13564 | primary->disable_plane = intel_disable_primary_plane; |
465c120c MR |
13565 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) |
13566 | primary->plane = !pipe; | |
13567 | ||
6c0fd451 DL |
13568 | if (INTEL_INFO(dev)->gen >= 9) { |
13569 | intel_primary_formats = skl_primary_formats; | |
13570 | num_formats = ARRAY_SIZE(skl_primary_formats); | |
13571 | } else if (INTEL_INFO(dev)->gen >= 4) { | |
568db4f2 DL |
13572 | intel_primary_formats = i965_primary_formats; |
13573 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
6c0fd451 DL |
13574 | } else { |
13575 | intel_primary_formats = i8xx_primary_formats; | |
13576 | num_formats = ARRAY_SIZE(i8xx_primary_formats); | |
465c120c MR |
13577 | } |
13578 | ||
13579 | drm_universal_plane_init(dev, &primary->base, 0, | |
65a3fea0 | 13580 | &intel_plane_funcs, |
465c120c MR |
13581 | intel_primary_formats, num_formats, |
13582 | DRM_PLANE_TYPE_PRIMARY); | |
48404c1e | 13583 | |
3b7a5119 SJ |
13584 | if (INTEL_INFO(dev)->gen >= 4) |
13585 | intel_create_rotation_property(dev, primary); | |
48404c1e | 13586 | |
ea2c67bb MR |
13587 | drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); |
13588 | ||
465c120c MR |
13589 | return &primary->base; |
13590 | } | |
13591 | ||
3b7a5119 SJ |
13592 | void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane) |
13593 | { | |
13594 | if (!dev->mode_config.rotation_property) { | |
13595 | unsigned long flags = BIT(DRM_ROTATE_0) | | |
13596 | BIT(DRM_ROTATE_180); | |
13597 | ||
13598 | if (INTEL_INFO(dev)->gen >= 9) | |
13599 | flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270); | |
13600 | ||
13601 | dev->mode_config.rotation_property = | |
13602 | drm_mode_create_rotation_property(dev, flags); | |
13603 | } | |
13604 | if (dev->mode_config.rotation_property) | |
13605 | drm_object_attach_property(&plane->base.base, | |
13606 | dev->mode_config.rotation_property, | |
13607 | plane->base.state->rotation); | |
13608 | } | |
13609 | ||
3d7d6510 | 13610 | static int |
852e787c | 13611 | intel_check_cursor_plane(struct drm_plane *plane, |
061e4b8d | 13612 | struct intel_crtc_state *crtc_state, |
852e787c | 13613 | struct intel_plane_state *state) |
3d7d6510 | 13614 | { |
061e4b8d | 13615 | struct drm_crtc *crtc = crtc_state->base.crtc; |
2b875c22 | 13616 | struct drm_framebuffer *fb = state->base.fb; |
757f9a3e | 13617 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
757f9a3e GP |
13618 | unsigned stride; |
13619 | int ret; | |
3d7d6510 | 13620 | |
061e4b8d ML |
13621 | ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src, |
13622 | &state->dst, &state->clip, | |
3d7d6510 MR |
13623 | DRM_PLANE_HELPER_NO_SCALING, |
13624 | DRM_PLANE_HELPER_NO_SCALING, | |
852e787c | 13625 | true, true, &state->visible); |
757f9a3e GP |
13626 | if (ret) |
13627 | return ret; | |
13628 | ||
757f9a3e GP |
13629 | /* if we want to turn off the cursor ignore width and height */ |
13630 | if (!obj) | |
da20eabd | 13631 | return 0; |
757f9a3e | 13632 | |
757f9a3e | 13633 | /* Check for which cursor types we support */ |
061e4b8d | 13634 | if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) { |
ea2c67bb MR |
13635 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", |
13636 | state->base.crtc_w, state->base.crtc_h); | |
757f9a3e GP |
13637 | return -EINVAL; |
13638 | } | |
13639 | ||
ea2c67bb MR |
13640 | stride = roundup_pow_of_two(state->base.crtc_w) * 4; |
13641 | if (obj->base.size < stride * state->base.crtc_h) { | |
757f9a3e GP |
13642 | DRM_DEBUG_KMS("buffer is too small\n"); |
13643 | return -ENOMEM; | |
13644 | } | |
13645 | ||
3a656b54 | 13646 | if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) { |
757f9a3e | 13647 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
da20eabd | 13648 | return -EINVAL; |
32b7eeec MR |
13649 | } |
13650 | ||
da20eabd | 13651 | return 0; |
852e787c | 13652 | } |
3d7d6510 | 13653 | |
a8ad0d8e ML |
13654 | static void |
13655 | intel_disable_cursor_plane(struct drm_plane *plane, | |
7fabf5ef | 13656 | struct drm_crtc *crtc) |
a8ad0d8e | 13657 | { |
a8ad0d8e ML |
13658 | intel_crtc_update_cursor(crtc, false); |
13659 | } | |
13660 | ||
f4a2cf29 | 13661 | static void |
852e787c GP |
13662 | intel_commit_cursor_plane(struct drm_plane *plane, |
13663 | struct intel_plane_state *state) | |
13664 | { | |
2b875c22 | 13665 | struct drm_crtc *crtc = state->base.crtc; |
ea2c67bb MR |
13666 | struct drm_device *dev = plane->dev; |
13667 | struct intel_crtc *intel_crtc; | |
2b875c22 | 13668 | struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb); |
a912f12f | 13669 | uint32_t addr; |
852e787c | 13670 | |
ea2c67bb MR |
13671 | crtc = crtc ? crtc : plane->crtc; |
13672 | intel_crtc = to_intel_crtc(crtc); | |
13673 | ||
a912f12f GP |
13674 | if (intel_crtc->cursor_bo == obj) |
13675 | goto update; | |
4ed91096 | 13676 | |
f4a2cf29 | 13677 | if (!obj) |
a912f12f | 13678 | addr = 0; |
f4a2cf29 | 13679 | else if (!INTEL_INFO(dev)->cursor_needs_physical) |
a912f12f | 13680 | addr = i915_gem_obj_ggtt_offset(obj); |
f4a2cf29 | 13681 | else |
a912f12f | 13682 | addr = obj->phys_handle->busaddr; |
852e787c | 13683 | |
a912f12f GP |
13684 | intel_crtc->cursor_addr = addr; |
13685 | intel_crtc->cursor_bo = obj; | |
852e787c | 13686 | |
302d19ac | 13687 | update: |
a539205a | 13688 | if (crtc->state->active) |
a912f12f | 13689 | intel_crtc_update_cursor(crtc, state->visible); |
852e787c GP |
13690 | } |
13691 | ||
3d7d6510 MR |
13692 | static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, |
13693 | int pipe) | |
13694 | { | |
13695 | struct intel_plane *cursor; | |
8e7d688b | 13696 | struct intel_plane_state *state; |
3d7d6510 MR |
13697 | |
13698 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
13699 | if (cursor == NULL) | |
13700 | return NULL; | |
13701 | ||
8e7d688b MR |
13702 | state = intel_create_plane_state(&cursor->base); |
13703 | if (!state) { | |
ea2c67bb MR |
13704 | kfree(cursor); |
13705 | return NULL; | |
13706 | } | |
8e7d688b | 13707 | cursor->base.state = &state->base; |
ea2c67bb | 13708 | |
3d7d6510 MR |
13709 | cursor->can_scale = false; |
13710 | cursor->max_downscale = 1; | |
13711 | cursor->pipe = pipe; | |
13712 | cursor->plane = pipe; | |
a9ff8714 | 13713 | cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe); |
c59cb179 MR |
13714 | cursor->check_plane = intel_check_cursor_plane; |
13715 | cursor->commit_plane = intel_commit_cursor_plane; | |
a8ad0d8e | 13716 | cursor->disable_plane = intel_disable_cursor_plane; |
3d7d6510 MR |
13717 | |
13718 | drm_universal_plane_init(dev, &cursor->base, 0, | |
65a3fea0 | 13719 | &intel_plane_funcs, |
3d7d6510 MR |
13720 | intel_cursor_formats, |
13721 | ARRAY_SIZE(intel_cursor_formats), | |
13722 | DRM_PLANE_TYPE_CURSOR); | |
4398ad45 VS |
13723 | |
13724 | if (INTEL_INFO(dev)->gen >= 4) { | |
13725 | if (!dev->mode_config.rotation_property) | |
13726 | dev->mode_config.rotation_property = | |
13727 | drm_mode_create_rotation_property(dev, | |
13728 | BIT(DRM_ROTATE_0) | | |
13729 | BIT(DRM_ROTATE_180)); | |
13730 | if (dev->mode_config.rotation_property) | |
13731 | drm_object_attach_property(&cursor->base.base, | |
13732 | dev->mode_config.rotation_property, | |
8e7d688b | 13733 | state->base.rotation); |
4398ad45 VS |
13734 | } |
13735 | ||
af99ceda CK |
13736 | if (INTEL_INFO(dev)->gen >=9) |
13737 | state->scaler_id = -1; | |
13738 | ||
ea2c67bb MR |
13739 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
13740 | ||
3d7d6510 MR |
13741 | return &cursor->base; |
13742 | } | |
13743 | ||
549e2bfb CK |
13744 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
13745 | struct intel_crtc_state *crtc_state) | |
13746 | { | |
13747 | int i; | |
13748 | struct intel_scaler *intel_scaler; | |
13749 | struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; | |
13750 | ||
13751 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
13752 | intel_scaler = &scaler_state->scalers[i]; | |
13753 | intel_scaler->in_use = 0; | |
549e2bfb CK |
13754 | intel_scaler->mode = PS_SCALER_MODE_DYN; |
13755 | } | |
13756 | ||
13757 | scaler_state->scaler_id = -1; | |
13758 | } | |
13759 | ||
b358d0a6 | 13760 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 13761 | { |
fbee40df | 13762 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 13763 | struct intel_crtc *intel_crtc; |
f5de6e07 | 13764 | struct intel_crtc_state *crtc_state = NULL; |
3d7d6510 MR |
13765 | struct drm_plane *primary = NULL; |
13766 | struct drm_plane *cursor = NULL; | |
465c120c | 13767 | int i, ret; |
79e53945 | 13768 | |
955382f3 | 13769 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
13770 | if (intel_crtc == NULL) |
13771 | return; | |
13772 | ||
f5de6e07 ACO |
13773 | crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); |
13774 | if (!crtc_state) | |
13775 | goto fail; | |
550acefd ACO |
13776 | intel_crtc->config = crtc_state; |
13777 | intel_crtc->base.state = &crtc_state->base; | |
07878248 | 13778 | crtc_state->base.crtc = &intel_crtc->base; |
f5de6e07 | 13779 | |
549e2bfb CK |
13780 | /* initialize shared scalers */ |
13781 | if (INTEL_INFO(dev)->gen >= 9) { | |
13782 | if (pipe == PIPE_C) | |
13783 | intel_crtc->num_scalers = 1; | |
13784 | else | |
13785 | intel_crtc->num_scalers = SKL_NUM_SCALERS; | |
13786 | ||
13787 | skl_init_scalers(dev, intel_crtc, crtc_state); | |
13788 | } | |
13789 | ||
465c120c | 13790 | primary = intel_primary_plane_create(dev, pipe); |
3d7d6510 MR |
13791 | if (!primary) |
13792 | goto fail; | |
13793 | ||
13794 | cursor = intel_cursor_plane_create(dev, pipe); | |
13795 | if (!cursor) | |
13796 | goto fail; | |
13797 | ||
465c120c | 13798 | ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, |
3d7d6510 MR |
13799 | cursor, &intel_crtc_funcs); |
13800 | if (ret) | |
13801 | goto fail; | |
79e53945 JB |
13802 | |
13803 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
13804 | for (i = 0; i < 256; i++) { |
13805 | intel_crtc->lut_r[i] = i; | |
13806 | intel_crtc->lut_g[i] = i; | |
13807 | intel_crtc->lut_b[i] = i; | |
13808 | } | |
13809 | ||
1f1c2e24 VS |
13810 | /* |
13811 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port | |
8c0f92e1 | 13812 | * is hooked to pipe B. Hence we want plane A feeding pipe B. |
1f1c2e24 | 13813 | */ |
80824003 JB |
13814 | intel_crtc->pipe = pipe; |
13815 | intel_crtc->plane = pipe; | |
3a77c4c4 | 13816 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
28c97730 | 13817 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 13818 | intel_crtc->plane = !pipe; |
80824003 JB |
13819 | } |
13820 | ||
4b0e333e CW |
13821 | intel_crtc->cursor_base = ~0; |
13822 | intel_crtc->cursor_cntl = ~0; | |
dc41c154 | 13823 | intel_crtc->cursor_size = ~0; |
8d7849db | 13824 | |
852eb00d VS |
13825 | intel_crtc->wm.cxsr_allowed = true; |
13826 | ||
22fd0fab JB |
13827 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
13828 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
13829 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
13830 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
13831 | ||
79e53945 | 13832 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 DV |
13833 | |
13834 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); | |
3d7d6510 MR |
13835 | return; |
13836 | ||
13837 | fail: | |
13838 | if (primary) | |
13839 | drm_plane_cleanup(primary); | |
13840 | if (cursor) | |
13841 | drm_plane_cleanup(cursor); | |
f5de6e07 | 13842 | kfree(crtc_state); |
3d7d6510 | 13843 | kfree(intel_crtc); |
79e53945 JB |
13844 | } |
13845 | ||
752aa88a JB |
13846 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
13847 | { | |
13848 | struct drm_encoder *encoder = connector->base.encoder; | |
6e9f798d | 13849 | struct drm_device *dev = connector->base.dev; |
752aa88a | 13850 | |
51fd371b | 13851 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a | 13852 | |
d3babd3f | 13853 | if (!encoder || WARN_ON(!encoder->crtc)) |
752aa88a JB |
13854 | return INVALID_PIPE; |
13855 | ||
13856 | return to_intel_crtc(encoder->crtc)->pipe; | |
13857 | } | |
13858 | ||
08d7b3d1 | 13859 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 13860 | struct drm_file *file) |
08d7b3d1 | 13861 | { |
08d7b3d1 | 13862 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 13863 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 13864 | struct intel_crtc *crtc; |
08d7b3d1 | 13865 | |
7707e653 | 13866 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
08d7b3d1 | 13867 | |
7707e653 | 13868 | if (!drmmode_crtc) { |
08d7b3d1 | 13869 | DRM_ERROR("no such CRTC id\n"); |
3f2c2057 | 13870 | return -ENOENT; |
08d7b3d1 CW |
13871 | } |
13872 | ||
7707e653 | 13873 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 13874 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 13875 | |
c05422d5 | 13876 | return 0; |
08d7b3d1 CW |
13877 | } |
13878 | ||
66a9278e | 13879 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 13880 | { |
66a9278e DV |
13881 | struct drm_device *dev = encoder->base.dev; |
13882 | struct intel_encoder *source_encoder; | |
79e53945 | 13883 | int index_mask = 0; |
79e53945 JB |
13884 | int entry = 0; |
13885 | ||
b2784e15 | 13886 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 13887 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
13888 | index_mask |= (1 << entry); |
13889 | ||
79e53945 JB |
13890 | entry++; |
13891 | } | |
4ef69c7a | 13892 | |
79e53945 JB |
13893 | return index_mask; |
13894 | } | |
13895 | ||
4d302442 CW |
13896 | static bool has_edp_a(struct drm_device *dev) |
13897 | { | |
13898 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13899 | ||
13900 | if (!IS_MOBILE(dev)) | |
13901 | return false; | |
13902 | ||
13903 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
13904 | return false; | |
13905 | ||
e3589908 | 13906 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
13907 | return false; |
13908 | ||
13909 | return true; | |
13910 | } | |
13911 | ||
84b4e042 JB |
13912 | static bool intel_crt_present(struct drm_device *dev) |
13913 | { | |
13914 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13915 | ||
884497ed DL |
13916 | if (INTEL_INFO(dev)->gen >= 9) |
13917 | return false; | |
13918 | ||
cf404ce4 | 13919 | if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) |
84b4e042 JB |
13920 | return false; |
13921 | ||
13922 | if (IS_CHERRYVIEW(dev)) | |
13923 | return false; | |
13924 | ||
13925 | if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support) | |
13926 | return false; | |
13927 | ||
13928 | return true; | |
13929 | } | |
13930 | ||
79e53945 JB |
13931 | static void intel_setup_outputs(struct drm_device *dev) |
13932 | { | |
725e30ad | 13933 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 13934 | struct intel_encoder *encoder; |
cb0953d7 | 13935 | bool dpd_is_edp = false; |
79e53945 | 13936 | |
c9093354 | 13937 | intel_lvds_init(dev); |
79e53945 | 13938 | |
84b4e042 | 13939 | if (intel_crt_present(dev)) |
79935fca | 13940 | intel_crt_init(dev); |
cb0953d7 | 13941 | |
c776eb2e VK |
13942 | if (IS_BROXTON(dev)) { |
13943 | /* | |
13944 | * FIXME: Broxton doesn't support port detection via the | |
13945 | * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to | |
13946 | * detect the ports. | |
13947 | */ | |
13948 | intel_ddi_init(dev, PORT_A); | |
13949 | intel_ddi_init(dev, PORT_B); | |
13950 | intel_ddi_init(dev, PORT_C); | |
13951 | } else if (HAS_DDI(dev)) { | |
0e72a5b5 ED |
13952 | int found; |
13953 | ||
de31facd JB |
13954 | /* |
13955 | * Haswell uses DDI functions to detect digital outputs. | |
13956 | * On SKL pre-D0 the strap isn't connected, so we assume | |
13957 | * it's there. | |
13958 | */ | |
0e72a5b5 | 13959 | found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED; |
de31facd | 13960 | /* WaIgnoreDDIAStrap: skl */ |
5a2376d1 | 13961 | if (found || IS_SKYLAKE(dev)) |
0e72a5b5 ED |
13962 | intel_ddi_init(dev, PORT_A); |
13963 | ||
13964 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
13965 | * register */ | |
13966 | found = I915_READ(SFUSE_STRAP); | |
13967 | ||
13968 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
13969 | intel_ddi_init(dev, PORT_B); | |
13970 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
13971 | intel_ddi_init(dev, PORT_C); | |
13972 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
13973 | intel_ddi_init(dev, PORT_D); | |
2800e4c2 RV |
13974 | /* |
13975 | * On SKL we don't have a way to detect DDI-E so we rely on VBT. | |
13976 | */ | |
13977 | if (IS_SKYLAKE(dev) && | |
13978 | (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp || | |
13979 | dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi || | |
13980 | dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi)) | |
13981 | intel_ddi_init(dev, PORT_E); | |
13982 | ||
0e72a5b5 | 13983 | } else if (HAS_PCH_SPLIT(dev)) { |
cb0953d7 | 13984 | int found; |
5d8a7752 | 13985 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
270b3042 DV |
13986 | |
13987 | if (has_edp_a(dev)) | |
13988 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 13989 | |
dc0fa718 | 13990 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 13991 | /* PCH SDVOB multiplex with HDMIB */ |
eef4eacb | 13992 | found = intel_sdvo_init(dev, PCH_SDVOB, true); |
30ad48b7 | 13993 | if (!found) |
e2debe91 | 13994 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 13995 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 13996 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
13997 | } |
13998 | ||
dc0fa718 | 13999 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 14000 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 14001 | |
dc0fa718 | 14002 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 14003 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 14004 | |
5eb08b69 | 14005 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 14006 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 14007 | |
270b3042 | 14008 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 14009 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
4a87d65d | 14010 | } else if (IS_VALLEYVIEW(dev)) { |
e17ac6db VS |
14011 | /* |
14012 | * The DP_DETECTED bit is the latched state of the DDC | |
14013 | * SDA pin at boot. However since eDP doesn't require DDC | |
14014 | * (no way to plug in a DP->HDMI dongle) the DDC pins for | |
14015 | * eDP ports may have been muxed to an alternate function. | |
14016 | * Thus we can't rely on the DP_DETECTED bit alone to detect | |
14017 | * eDP ports. Consult the VBT as well as DP_DETECTED to | |
14018 | * detect eDP ports. | |
14019 | */ | |
d2182a66 VS |
14020 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED && |
14021 | !intel_dp_is_edp(dev, PORT_B)) | |
585a94b8 AB |
14022 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB, |
14023 | PORT_B); | |
e17ac6db VS |
14024 | if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED || |
14025 | intel_dp_is_edp(dev, PORT_B)) | |
14026 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B); | |
585a94b8 | 14027 | |
d2182a66 VS |
14028 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED && |
14029 | !intel_dp_is_edp(dev, PORT_C)) | |
6f6005a5 JB |
14030 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC, |
14031 | PORT_C); | |
e17ac6db VS |
14032 | if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED || |
14033 | intel_dp_is_edp(dev, PORT_C)) | |
14034 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C); | |
19c03924 | 14035 | |
9418c1f1 | 14036 | if (IS_CHERRYVIEW(dev)) { |
e17ac6db | 14037 | if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) |
9418c1f1 VS |
14038 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID, |
14039 | PORT_D); | |
e17ac6db VS |
14040 | /* eDP not supported on port D, so don't check VBT */ |
14041 | if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED) | |
14042 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D); | |
9418c1f1 VS |
14043 | } |
14044 | ||
3cfca973 | 14045 | intel_dsi_init(dev); |
09da55dc | 14046 | } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) { |
27185ae1 | 14047 | bool found = false; |
7d57382e | 14048 | |
e2debe91 | 14049 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14050 | DRM_DEBUG_KMS("probing SDVOB\n"); |
e2debe91 | 14051 | found = intel_sdvo_init(dev, GEN3_SDVOB, true); |
3fec3d2f | 14052 | if (!found && IS_G4X(dev)) { |
b01f2c3a | 14053 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); |
e2debe91 | 14054 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 14055 | } |
27185ae1 | 14056 | |
3fec3d2f | 14057 | if (!found && IS_G4X(dev)) |
ab9d7c30 | 14058 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 14059 | } |
13520b05 KH |
14060 | |
14061 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 14062 | |
e2debe91 | 14063 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14064 | DRM_DEBUG_KMS("probing SDVOC\n"); |
e2debe91 | 14065 | found = intel_sdvo_init(dev, GEN3_SDVOC, false); |
b01f2c3a | 14066 | } |
27185ae1 | 14067 | |
e2debe91 | 14068 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 14069 | |
3fec3d2f | 14070 | if (IS_G4X(dev)) { |
b01f2c3a | 14071 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); |
e2debe91 | 14072 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 14073 | } |
3fec3d2f | 14074 | if (IS_G4X(dev)) |
ab9d7c30 | 14075 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 14076 | } |
27185ae1 | 14077 | |
3fec3d2f | 14078 | if (IS_G4X(dev) && |
e7281eab | 14079 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 14080 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 14081 | } else if (IS_GEN2(dev)) |
79e53945 JB |
14082 | intel_dvo_init(dev); |
14083 | ||
103a196f | 14084 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
14085 | intel_tv_init(dev); |
14086 | ||
0bc12bcb | 14087 | intel_psr_init(dev); |
7c8f8a70 | 14088 | |
b2784e15 | 14089 | for_each_intel_encoder(dev, encoder) { |
4ef69c7a CW |
14090 | encoder->base.possible_crtcs = encoder->crtc_mask; |
14091 | encoder->base.possible_clones = | |
66a9278e | 14092 | intel_encoder_clones(encoder); |
79e53945 | 14093 | } |
47356eb6 | 14094 | |
dde86e2d | 14095 | intel_init_pch_refclk(dev); |
270b3042 DV |
14096 | |
14097 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
14098 | } |
14099 | ||
14100 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
14101 | { | |
60a5ca01 | 14102 | struct drm_device *dev = fb->dev; |
79e53945 | 14103 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
79e53945 | 14104 | |
ef2d633e | 14105 | drm_framebuffer_cleanup(fb); |
60a5ca01 | 14106 | mutex_lock(&dev->struct_mutex); |
ef2d633e | 14107 | WARN_ON(!intel_fb->obj->framebuffer_references--); |
60a5ca01 VS |
14108 | drm_gem_object_unreference(&intel_fb->obj->base); |
14109 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
14110 | kfree(intel_fb); |
14111 | } | |
14112 | ||
14113 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 14114 | struct drm_file *file, |
79e53945 JB |
14115 | unsigned int *handle) |
14116 | { | |
14117 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 14118 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 14119 | |
05394f39 | 14120 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
14121 | } |
14122 | ||
86c98588 RV |
14123 | static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb, |
14124 | struct drm_file *file, | |
14125 | unsigned flags, unsigned color, | |
14126 | struct drm_clip_rect *clips, | |
14127 | unsigned num_clips) | |
14128 | { | |
14129 | struct drm_device *dev = fb->dev; | |
14130 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
14131 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
14132 | ||
14133 | mutex_lock(&dev->struct_mutex); | |
74b4ea1e | 14134 | intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB); |
86c98588 RV |
14135 | mutex_unlock(&dev->struct_mutex); |
14136 | ||
14137 | return 0; | |
14138 | } | |
14139 | ||
79e53945 JB |
14140 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
14141 | .destroy = intel_user_framebuffer_destroy, | |
14142 | .create_handle = intel_user_framebuffer_create_handle, | |
86c98588 | 14143 | .dirty = intel_user_framebuffer_dirty, |
79e53945 JB |
14144 | }; |
14145 | ||
b321803d DL |
14146 | static |
14147 | u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier, | |
14148 | uint32_t pixel_format) | |
14149 | { | |
14150 | u32 gen = INTEL_INFO(dev)->gen; | |
14151 | ||
14152 | if (gen >= 9) { | |
14153 | /* "The stride in bytes must not exceed the of the size of 8K | |
14154 | * pixels and 32K bytes." | |
14155 | */ | |
14156 | return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768); | |
14157 | } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) { | |
14158 | return 32*1024; | |
14159 | } else if (gen >= 4) { | |
14160 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14161 | return 16*1024; | |
14162 | else | |
14163 | return 32*1024; | |
14164 | } else if (gen >= 3) { | |
14165 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14166 | return 8*1024; | |
14167 | else | |
14168 | return 16*1024; | |
14169 | } else { | |
14170 | /* XXX DSPC is limited to 4k tiled */ | |
14171 | return 8*1024; | |
14172 | } | |
14173 | } | |
14174 | ||
b5ea642a DV |
14175 | static int intel_framebuffer_init(struct drm_device *dev, |
14176 | struct intel_framebuffer *intel_fb, | |
14177 | struct drm_mode_fb_cmd2 *mode_cmd, | |
14178 | struct drm_i915_gem_object *obj) | |
79e53945 | 14179 | { |
6761dd31 | 14180 | unsigned int aligned_height; |
79e53945 | 14181 | int ret; |
b321803d | 14182 | u32 pitch_limit, stride_alignment; |
79e53945 | 14183 | |
dd4916c5 DV |
14184 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
14185 | ||
2a80eada DV |
14186 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { |
14187 | /* Enforce that fb modifier and tiling mode match, but only for | |
14188 | * X-tiled. This is needed for FBC. */ | |
14189 | if (!!(obj->tiling_mode == I915_TILING_X) != | |
14190 | !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) { | |
14191 | DRM_DEBUG("tiling_mode doesn't match fb modifier\n"); | |
14192 | return -EINVAL; | |
14193 | } | |
14194 | } else { | |
14195 | if (obj->tiling_mode == I915_TILING_X) | |
14196 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
14197 | else if (obj->tiling_mode == I915_TILING_Y) { | |
14198 | DRM_DEBUG("No Y tiling for legacy addfb\n"); | |
14199 | return -EINVAL; | |
14200 | } | |
14201 | } | |
14202 | ||
9a8f0a12 TU |
14203 | /* Passed in modifier sanity checking. */ |
14204 | switch (mode_cmd->modifier[0]) { | |
14205 | case I915_FORMAT_MOD_Y_TILED: | |
14206 | case I915_FORMAT_MOD_Yf_TILED: | |
14207 | if (INTEL_INFO(dev)->gen < 9) { | |
14208 | DRM_DEBUG("Unsupported tiling 0x%llx!\n", | |
14209 | mode_cmd->modifier[0]); | |
14210 | return -EINVAL; | |
14211 | } | |
14212 | case DRM_FORMAT_MOD_NONE: | |
14213 | case I915_FORMAT_MOD_X_TILED: | |
14214 | break; | |
14215 | default: | |
c0f40428 JB |
14216 | DRM_DEBUG("Unsupported fb modifier 0x%llx!\n", |
14217 | mode_cmd->modifier[0]); | |
57cd6508 | 14218 | return -EINVAL; |
c16ed4be | 14219 | } |
57cd6508 | 14220 | |
b321803d DL |
14221 | stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0], |
14222 | mode_cmd->pixel_format); | |
14223 | if (mode_cmd->pitches[0] & (stride_alignment - 1)) { | |
14224 | DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n", | |
14225 | mode_cmd->pitches[0], stride_alignment); | |
57cd6508 | 14226 | return -EINVAL; |
c16ed4be | 14227 | } |
57cd6508 | 14228 | |
b321803d DL |
14229 | pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0], |
14230 | mode_cmd->pixel_format); | |
a35cdaa0 | 14231 | if (mode_cmd->pitches[0] > pitch_limit) { |
b321803d DL |
14232 | DRM_DEBUG("%s pitch (%u) must be at less than %d\n", |
14233 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ? | |
2a80eada | 14234 | "tiled" : "linear", |
a35cdaa0 | 14235 | mode_cmd->pitches[0], pitch_limit); |
5d7bd705 | 14236 | return -EINVAL; |
c16ed4be | 14237 | } |
5d7bd705 | 14238 | |
2a80eada | 14239 | if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED && |
c16ed4be CW |
14240 | mode_cmd->pitches[0] != obj->stride) { |
14241 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
14242 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 14243 | return -EINVAL; |
c16ed4be | 14244 | } |
5d7bd705 | 14245 | |
57779d06 | 14246 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 14247 | switch (mode_cmd->pixel_format) { |
57779d06 | 14248 | case DRM_FORMAT_C8: |
04b3924d VS |
14249 | case DRM_FORMAT_RGB565: |
14250 | case DRM_FORMAT_XRGB8888: | |
14251 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
14252 | break; |
14253 | case DRM_FORMAT_XRGB1555: | |
c16ed4be | 14254 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
14255 | DRM_DEBUG("unsupported pixel format: %s\n", |
14256 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14257 | return -EINVAL; |
c16ed4be | 14258 | } |
57779d06 | 14259 | break; |
57779d06 | 14260 | case DRM_FORMAT_ABGR8888: |
6c0fd451 DL |
14261 | if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) { |
14262 | DRM_DEBUG("unsupported pixel format: %s\n", | |
14263 | drm_get_format_name(mode_cmd->pixel_format)); | |
14264 | return -EINVAL; | |
14265 | } | |
14266 | break; | |
14267 | case DRM_FORMAT_XBGR8888: | |
04b3924d | 14268 | case DRM_FORMAT_XRGB2101010: |
57779d06 | 14269 | case DRM_FORMAT_XBGR2101010: |
c16ed4be | 14270 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
14271 | DRM_DEBUG("unsupported pixel format: %s\n", |
14272 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14273 | return -EINVAL; |
c16ed4be | 14274 | } |
b5626747 | 14275 | break; |
7531208b DL |
14276 | case DRM_FORMAT_ABGR2101010: |
14277 | if (!IS_VALLEYVIEW(dev)) { | |
14278 | DRM_DEBUG("unsupported pixel format: %s\n", | |
14279 | drm_get_format_name(mode_cmd->pixel_format)); | |
14280 | return -EINVAL; | |
14281 | } | |
14282 | break; | |
04b3924d VS |
14283 | case DRM_FORMAT_YUYV: |
14284 | case DRM_FORMAT_UYVY: | |
14285 | case DRM_FORMAT_YVYU: | |
14286 | case DRM_FORMAT_VYUY: | |
c16ed4be | 14287 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
14288 | DRM_DEBUG("unsupported pixel format: %s\n", |
14289 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14290 | return -EINVAL; |
c16ed4be | 14291 | } |
57cd6508 CW |
14292 | break; |
14293 | default: | |
4ee62c76 VS |
14294 | DRM_DEBUG("unsupported pixel format: %s\n", |
14295 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
14296 | return -EINVAL; |
14297 | } | |
14298 | ||
90f9a336 VS |
14299 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
14300 | if (mode_cmd->offsets[0] != 0) | |
14301 | return -EINVAL; | |
14302 | ||
ec2c981e | 14303 | aligned_height = intel_fb_align_height(dev, mode_cmd->height, |
091df6cb DV |
14304 | mode_cmd->pixel_format, |
14305 | mode_cmd->modifier[0]); | |
53155c0a DV |
14306 | /* FIXME drm helper for size checks (especially planar formats)? */ |
14307 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) | |
14308 | return -EINVAL; | |
14309 | ||
c7d73f6a DV |
14310 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
14311 | intel_fb->obj = obj; | |
80075d49 | 14312 | intel_fb->obj->framebuffer_references++; |
c7d73f6a | 14313 | |
79e53945 JB |
14314 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
14315 | if (ret) { | |
14316 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
14317 | return ret; | |
14318 | } | |
14319 | ||
79e53945 JB |
14320 | return 0; |
14321 | } | |
14322 | ||
79e53945 JB |
14323 | static struct drm_framebuffer * |
14324 | intel_user_framebuffer_create(struct drm_device *dev, | |
14325 | struct drm_file *filp, | |
308e5bcb | 14326 | struct drm_mode_fb_cmd2 *mode_cmd) |
79e53945 | 14327 | { |
05394f39 | 14328 | struct drm_i915_gem_object *obj; |
79e53945 | 14329 | |
308e5bcb JB |
14330 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
14331 | mode_cmd->handles[0])); | |
c8725226 | 14332 | if (&obj->base == NULL) |
cce13ff7 | 14333 | return ERR_PTR(-ENOENT); |
79e53945 | 14334 | |
d2dff872 | 14335 | return intel_framebuffer_create(dev, mode_cmd, obj); |
79e53945 JB |
14336 | } |
14337 | ||
0695726e | 14338 | #ifndef CONFIG_DRM_FBDEV_EMULATION |
0632fef6 | 14339 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
4520f53a DV |
14340 | { |
14341 | } | |
14342 | #endif | |
14343 | ||
79e53945 | 14344 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 14345 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 14346 | .output_poll_changed = intel_fbdev_output_poll_changed, |
5ee67f1c MR |
14347 | .atomic_check = intel_atomic_check, |
14348 | .atomic_commit = intel_atomic_commit, | |
de419ab6 ML |
14349 | .atomic_state_alloc = intel_atomic_state_alloc, |
14350 | .atomic_state_clear = intel_atomic_state_clear, | |
79e53945 JB |
14351 | }; |
14352 | ||
e70236a8 JB |
14353 | /* Set up chip specific display functions */ |
14354 | static void intel_init_display(struct drm_device *dev) | |
14355 | { | |
14356 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14357 | ||
ee9300bb DV |
14358 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
14359 | dev_priv->display.find_dpll = g4x_find_best_dpll; | |
ef9348c8 CML |
14360 | else if (IS_CHERRYVIEW(dev)) |
14361 | dev_priv->display.find_dpll = chv_find_best_dpll; | |
ee9300bb DV |
14362 | else if (IS_VALLEYVIEW(dev)) |
14363 | dev_priv->display.find_dpll = vlv_find_best_dpll; | |
14364 | else if (IS_PINEVIEW(dev)) | |
14365 | dev_priv->display.find_dpll = pnv_find_best_dpll; | |
14366 | else | |
14367 | dev_priv->display.find_dpll = i9xx_find_best_dpll; | |
14368 | ||
bc8d7dff DL |
14369 | if (INTEL_INFO(dev)->gen >= 9) { |
14370 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; | |
5724dbd1 DL |
14371 | dev_priv->display.get_initial_plane_config = |
14372 | skylake_get_initial_plane_config; | |
bc8d7dff DL |
14373 | dev_priv->display.crtc_compute_clock = |
14374 | haswell_crtc_compute_clock; | |
14375 | dev_priv->display.crtc_enable = haswell_crtc_enable; | |
14376 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
bc8d7dff DL |
14377 | dev_priv->display.update_primary_plane = |
14378 | skylake_update_primary_plane; | |
14379 | } else if (HAS_DDI(dev)) { | |
0e8ffe1b | 14380 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
14381 | dev_priv->display.get_initial_plane_config = |
14382 | ironlake_get_initial_plane_config; | |
797d0259 ACO |
14383 | dev_priv->display.crtc_compute_clock = |
14384 | haswell_crtc_compute_clock; | |
4f771f10 PZ |
14385 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
14386 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
bc8d7dff DL |
14387 | dev_priv->display.update_primary_plane = |
14388 | ironlake_update_primary_plane; | |
09b4ddf9 | 14389 | } else if (HAS_PCH_SPLIT(dev)) { |
0e8ffe1b | 14390 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
5724dbd1 DL |
14391 | dev_priv->display.get_initial_plane_config = |
14392 | ironlake_get_initial_plane_config; | |
3fb37703 ACO |
14393 | dev_priv->display.crtc_compute_clock = |
14394 | ironlake_crtc_compute_clock; | |
76e5a89c DV |
14395 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
14396 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
262ca2b0 MR |
14397 | dev_priv->display.update_primary_plane = |
14398 | ironlake_update_primary_plane; | |
89b667f8 JB |
14399 | } else if (IS_VALLEYVIEW(dev)) { |
14400 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
5724dbd1 DL |
14401 | dev_priv->display.get_initial_plane_config = |
14402 | i9xx_get_initial_plane_config; | |
d6dfee7a | 14403 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
89b667f8 JB |
14404 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
14405 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
262ca2b0 MR |
14406 | dev_priv->display.update_primary_plane = |
14407 | i9xx_update_primary_plane; | |
f564048e | 14408 | } else { |
0e8ffe1b | 14409 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
14410 | dev_priv->display.get_initial_plane_config = |
14411 | i9xx_get_initial_plane_config; | |
d6dfee7a | 14412 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
76e5a89c DV |
14413 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
14414 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
262ca2b0 MR |
14415 | dev_priv->display.update_primary_plane = |
14416 | i9xx_update_primary_plane; | |
f564048e | 14417 | } |
e70236a8 | 14418 | |
e70236a8 | 14419 | /* Returns the core display clock speed */ |
1652d19e VS |
14420 | if (IS_SKYLAKE(dev)) |
14421 | dev_priv->display.get_display_clock_speed = | |
14422 | skylake_get_display_clock_speed; | |
acd3f3d3 BP |
14423 | else if (IS_BROXTON(dev)) |
14424 | dev_priv->display.get_display_clock_speed = | |
14425 | broxton_get_display_clock_speed; | |
1652d19e VS |
14426 | else if (IS_BROADWELL(dev)) |
14427 | dev_priv->display.get_display_clock_speed = | |
14428 | broadwell_get_display_clock_speed; | |
14429 | else if (IS_HASWELL(dev)) | |
14430 | dev_priv->display.get_display_clock_speed = | |
14431 | haswell_get_display_clock_speed; | |
14432 | else if (IS_VALLEYVIEW(dev)) | |
25eb05fc JB |
14433 | dev_priv->display.get_display_clock_speed = |
14434 | valleyview_get_display_clock_speed; | |
b37a6434 VS |
14435 | else if (IS_GEN5(dev)) |
14436 | dev_priv->display.get_display_clock_speed = | |
14437 | ilk_get_display_clock_speed; | |
a7c66cd8 | 14438 | else if (IS_I945G(dev) || IS_BROADWATER(dev) || |
34edce2f | 14439 | IS_GEN6(dev) || IS_IVYBRIDGE(dev)) |
e70236a8 JB |
14440 | dev_priv->display.get_display_clock_speed = |
14441 | i945_get_display_clock_speed; | |
34edce2f VS |
14442 | else if (IS_GM45(dev)) |
14443 | dev_priv->display.get_display_clock_speed = | |
14444 | gm45_get_display_clock_speed; | |
14445 | else if (IS_CRESTLINE(dev)) | |
14446 | dev_priv->display.get_display_clock_speed = | |
14447 | i965gm_get_display_clock_speed; | |
14448 | else if (IS_PINEVIEW(dev)) | |
14449 | dev_priv->display.get_display_clock_speed = | |
14450 | pnv_get_display_clock_speed; | |
14451 | else if (IS_G33(dev) || IS_G4X(dev)) | |
14452 | dev_priv->display.get_display_clock_speed = | |
14453 | g33_get_display_clock_speed; | |
e70236a8 JB |
14454 | else if (IS_I915G(dev)) |
14455 | dev_priv->display.get_display_clock_speed = | |
14456 | i915_get_display_clock_speed; | |
257a7ffc | 14457 | else if (IS_I945GM(dev) || IS_845G(dev)) |
e70236a8 JB |
14458 | dev_priv->display.get_display_clock_speed = |
14459 | i9xx_misc_get_display_clock_speed; | |
257a7ffc DV |
14460 | else if (IS_PINEVIEW(dev)) |
14461 | dev_priv->display.get_display_clock_speed = | |
14462 | pnv_get_display_clock_speed; | |
e70236a8 JB |
14463 | else if (IS_I915GM(dev)) |
14464 | dev_priv->display.get_display_clock_speed = | |
14465 | i915gm_get_display_clock_speed; | |
14466 | else if (IS_I865G(dev)) | |
14467 | dev_priv->display.get_display_clock_speed = | |
14468 | i865_get_display_clock_speed; | |
f0f8a9ce | 14469 | else if (IS_I85X(dev)) |
e70236a8 | 14470 | dev_priv->display.get_display_clock_speed = |
1b1d2716 | 14471 | i85x_get_display_clock_speed; |
623e01e5 VS |
14472 | else { /* 830 */ |
14473 | WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n"); | |
e70236a8 JB |
14474 | dev_priv->display.get_display_clock_speed = |
14475 | i830_get_display_clock_speed; | |
623e01e5 | 14476 | } |
e70236a8 | 14477 | |
7c10a2b5 | 14478 | if (IS_GEN5(dev)) { |
3bb11b53 | 14479 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
3bb11b53 SJ |
14480 | } else if (IS_GEN6(dev)) { |
14481 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; | |
3bb11b53 SJ |
14482 | } else if (IS_IVYBRIDGE(dev)) { |
14483 | /* FIXME: detect B0+ stepping and use auto training */ | |
14484 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
059b2fe9 | 14485 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
3bb11b53 | 14486 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
27c329ed ML |
14487 | if (IS_BROADWELL(dev)) { |
14488 | dev_priv->display.modeset_commit_cdclk = | |
14489 | broadwell_modeset_commit_cdclk; | |
14490 | dev_priv->display.modeset_calc_cdclk = | |
14491 | broadwell_modeset_calc_cdclk; | |
14492 | } | |
30a970c6 | 14493 | } else if (IS_VALLEYVIEW(dev)) { |
27c329ed ML |
14494 | dev_priv->display.modeset_commit_cdclk = |
14495 | valleyview_modeset_commit_cdclk; | |
14496 | dev_priv->display.modeset_calc_cdclk = | |
14497 | valleyview_modeset_calc_cdclk; | |
f8437dd1 | 14498 | } else if (IS_BROXTON(dev)) { |
27c329ed ML |
14499 | dev_priv->display.modeset_commit_cdclk = |
14500 | broxton_modeset_commit_cdclk; | |
14501 | dev_priv->display.modeset_calc_cdclk = | |
14502 | broxton_modeset_calc_cdclk; | |
e70236a8 | 14503 | } |
8c9f3aaf | 14504 | |
8c9f3aaf JB |
14505 | switch (INTEL_INFO(dev)->gen) { |
14506 | case 2: | |
14507 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
14508 | break; | |
14509 | ||
14510 | case 3: | |
14511 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
14512 | break; | |
14513 | ||
14514 | case 4: | |
14515 | case 5: | |
14516 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
14517 | break; | |
14518 | ||
14519 | case 6: | |
14520 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
14521 | break; | |
7c9017e5 | 14522 | case 7: |
4e0bbc31 | 14523 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ |
7c9017e5 JB |
14524 | dev_priv->display.queue_flip = intel_gen7_queue_flip; |
14525 | break; | |
830c81db | 14526 | case 9: |
ba343e02 TU |
14527 | /* Drop through - unsupported since execlist only. */ |
14528 | default: | |
14529 | /* Default just returns -ENODEV to indicate unsupported */ | |
14530 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
8c9f3aaf | 14531 | } |
7bd688cd JN |
14532 | |
14533 | intel_panel_init_backlight_funcs(dev); | |
e39b999a VS |
14534 | |
14535 | mutex_init(&dev_priv->pps_mutex); | |
e70236a8 JB |
14536 | } |
14537 | ||
b690e96c JB |
14538 | /* |
14539 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
14540 | * resume, or other times. This quirk makes sure that's the case for | |
14541 | * affected systems. | |
14542 | */ | |
0206e353 | 14543 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
14544 | { |
14545 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14546 | ||
14547 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 14548 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
14549 | } |
14550 | ||
b6b5d049 VS |
14551 | static void quirk_pipeb_force(struct drm_device *dev) |
14552 | { | |
14553 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14554 | ||
14555 | dev_priv->quirks |= QUIRK_PIPEB_FORCE; | |
14556 | DRM_INFO("applying pipe b force quirk\n"); | |
14557 | } | |
14558 | ||
435793df KP |
14559 | /* |
14560 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
14561 | */ | |
14562 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
14563 | { | |
14564 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14565 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 14566 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
14567 | } |
14568 | ||
4dca20ef | 14569 | /* |
5a15ab5b CE |
14570 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
14571 | * brightness value | |
4dca20ef CE |
14572 | */ |
14573 | static void quirk_invert_brightness(struct drm_device *dev) | |
14574 | { | |
14575 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14576 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 14577 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
14578 | } |
14579 | ||
9c72cc6f SD |
14580 | /* Some VBT's incorrectly indicate no backlight is present */ |
14581 | static void quirk_backlight_present(struct drm_device *dev) | |
14582 | { | |
14583 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14584 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; | |
14585 | DRM_INFO("applying backlight present quirk\n"); | |
14586 | } | |
14587 | ||
b690e96c JB |
14588 | struct intel_quirk { |
14589 | int device; | |
14590 | int subsystem_vendor; | |
14591 | int subsystem_device; | |
14592 | void (*hook)(struct drm_device *dev); | |
14593 | }; | |
14594 | ||
5f85f176 EE |
14595 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
14596 | struct intel_dmi_quirk { | |
14597 | void (*hook)(struct drm_device *dev); | |
14598 | const struct dmi_system_id (*dmi_id_list)[]; | |
14599 | }; | |
14600 | ||
14601 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
14602 | { | |
14603 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
14604 | return 1; | |
14605 | } | |
14606 | ||
14607 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
14608 | { | |
14609 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
14610 | { | |
14611 | .callback = intel_dmi_reverse_brightness, | |
14612 | .ident = "NCR Corporation", | |
14613 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
14614 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
14615 | }, | |
14616 | }, | |
14617 | { } /* terminating entry */ | |
14618 | }, | |
14619 | .hook = quirk_invert_brightness, | |
14620 | }, | |
14621 | }; | |
14622 | ||
c43b5634 | 14623 | static struct intel_quirk intel_quirks[] = { |
b690e96c JB |
14624 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
14625 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
14626 | ||
b690e96c JB |
14627 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
14628 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
14629 | ||
5f080c0f VS |
14630 | /* 830 needs to leave pipe A & dpll A up */ |
14631 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
14632 | ||
b6b5d049 VS |
14633 | /* 830 needs to leave pipe B & dpll B up */ |
14634 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force }, | |
14635 | ||
435793df KP |
14636 | /* Lenovo U160 cannot use SSC on LVDS */ |
14637 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
14638 | |
14639 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
14640 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 14641 | |
be505f64 AH |
14642 | /* Acer Aspire 5734Z must invert backlight brightness */ |
14643 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
14644 | ||
14645 | /* Acer/eMachines G725 */ | |
14646 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
14647 | ||
14648 | /* Acer/eMachines e725 */ | |
14649 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
14650 | ||
14651 | /* Acer/Packard Bell NCL20 */ | |
14652 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
14653 | ||
14654 | /* Acer Aspire 4736Z */ | |
14655 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
14656 | |
14657 | /* Acer Aspire 5336 */ | |
14658 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
2e93a1aa SD |
14659 | |
14660 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
14661 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
d4967d8c | 14662 | |
dfb3d47b SD |
14663 | /* Acer C720 Chromebook (Core i3 4005U) */ |
14664 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, | |
14665 | ||
b2a9601c | 14666 | /* Apple Macbook 2,1 (Core 2 T7400) */ |
14667 | { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, | |
14668 | ||
d4967d8c SD |
14669 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
14670 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
724cb06f SD |
14671 | |
14672 | /* HP Chromebook 14 (Celeron 2955U) */ | |
14673 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
cf6f0af9 JN |
14674 | |
14675 | /* Dell Chromebook 11 */ | |
14676 | { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, | |
b690e96c JB |
14677 | }; |
14678 | ||
14679 | static void intel_init_quirks(struct drm_device *dev) | |
14680 | { | |
14681 | struct pci_dev *d = dev->pdev; | |
14682 | int i; | |
14683 | ||
14684 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
14685 | struct intel_quirk *q = &intel_quirks[i]; | |
14686 | ||
14687 | if (d->device == q->device && | |
14688 | (d->subsystem_vendor == q->subsystem_vendor || | |
14689 | q->subsystem_vendor == PCI_ANY_ID) && | |
14690 | (d->subsystem_device == q->subsystem_device || | |
14691 | q->subsystem_device == PCI_ANY_ID)) | |
14692 | q->hook(dev); | |
14693 | } | |
5f85f176 EE |
14694 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
14695 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
14696 | intel_dmi_quirks[i].hook(dev); | |
14697 | } | |
b690e96c JB |
14698 | } |
14699 | ||
9cce37f4 JB |
14700 | /* Disable the VGA plane that we never use */ |
14701 | static void i915_disable_vga(struct drm_device *dev) | |
14702 | { | |
14703 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14704 | u8 sr1; | |
766aa1c4 | 14705 | u32 vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 | 14706 | |
2b37c616 | 14707 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
9cce37f4 | 14708 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 14709 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
14710 | sr1 = inb(VGA_SR_DATA); |
14711 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
14712 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
14713 | udelay(300); | |
14714 | ||
01f5a626 | 14715 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
9cce37f4 JB |
14716 | POSTING_READ(vga_reg); |
14717 | } | |
14718 | ||
f817586c DV |
14719 | void intel_modeset_init_hw(struct drm_device *dev) |
14720 | { | |
b6283055 | 14721 | intel_update_cdclk(dev); |
a8f78b58 | 14722 | intel_prepare_ddi(dev); |
f817586c | 14723 | intel_init_clock_gating(dev); |
8090c6b9 | 14724 | intel_enable_gt_powersave(dev); |
f817586c DV |
14725 | } |
14726 | ||
79e53945 JB |
14727 | void intel_modeset_init(struct drm_device *dev) |
14728 | { | |
652c393a | 14729 | struct drm_i915_private *dev_priv = dev->dev_private; |
1fe47785 | 14730 | int sprite, ret; |
8cc87b75 | 14731 | enum pipe pipe; |
46f297fb | 14732 | struct intel_crtc *crtc; |
79e53945 JB |
14733 | |
14734 | drm_mode_config_init(dev); | |
14735 | ||
14736 | dev->mode_config.min_width = 0; | |
14737 | dev->mode_config.min_height = 0; | |
14738 | ||
019d96cb DA |
14739 | dev->mode_config.preferred_depth = 24; |
14740 | dev->mode_config.prefer_shadow = 1; | |
14741 | ||
25bab385 TU |
14742 | dev->mode_config.allow_fb_modifiers = true; |
14743 | ||
e6ecefaa | 14744 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 14745 | |
b690e96c JB |
14746 | intel_init_quirks(dev); |
14747 | ||
1fa61106 ED |
14748 | intel_init_pm(dev); |
14749 | ||
e3c74757 BW |
14750 | if (INTEL_INFO(dev)->num_pipes == 0) |
14751 | return; | |
14752 | ||
69f92f67 LW |
14753 | /* |
14754 | * There may be no VBT; and if the BIOS enabled SSC we can | |
14755 | * just keep using it to avoid unnecessary flicker. Whereas if the | |
14756 | * BIOS isn't using it, don't assume it will work even if the VBT | |
14757 | * indicates as much. | |
14758 | */ | |
14759 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { | |
14760 | bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & | |
14761 | DREF_SSC1_ENABLE); | |
14762 | ||
14763 | if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { | |
14764 | DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n", | |
14765 | bios_lvds_use_ssc ? "en" : "dis", | |
14766 | dev_priv->vbt.lvds_use_ssc ? "en" : "dis"); | |
14767 | dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; | |
14768 | } | |
14769 | } | |
14770 | ||
e70236a8 | 14771 | intel_init_display(dev); |
7c10a2b5 | 14772 | intel_init_audio(dev); |
e70236a8 | 14773 | |
a6c45cf0 CW |
14774 | if (IS_GEN2(dev)) { |
14775 | dev->mode_config.max_width = 2048; | |
14776 | dev->mode_config.max_height = 2048; | |
14777 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
14778 | dev->mode_config.max_width = 4096; |
14779 | dev->mode_config.max_height = 4096; | |
79e53945 | 14780 | } else { |
a6c45cf0 CW |
14781 | dev->mode_config.max_width = 8192; |
14782 | dev->mode_config.max_height = 8192; | |
79e53945 | 14783 | } |
068be561 | 14784 | |
dc41c154 VS |
14785 | if (IS_845G(dev) || IS_I865G(dev)) { |
14786 | dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512; | |
14787 | dev->mode_config.cursor_height = 1023; | |
14788 | } else if (IS_GEN2(dev)) { | |
068be561 DL |
14789 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
14790 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
14791 | } else { | |
14792 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
14793 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
14794 | } | |
14795 | ||
5d4545ae | 14796 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
79e53945 | 14797 | |
28c97730 | 14798 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
14799 | INTEL_INFO(dev)->num_pipes, |
14800 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 14801 | |
055e393f | 14802 | for_each_pipe(dev_priv, pipe) { |
8cc87b75 | 14803 | intel_crtc_init(dev, pipe); |
3bdcfc0c | 14804 | for_each_sprite(dev_priv, pipe, sprite) { |
1fe47785 | 14805 | ret = intel_plane_init(dev, pipe, sprite); |
7f1f3851 | 14806 | if (ret) |
06da8da2 | 14807 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
1fe47785 | 14808 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
7f1f3851 | 14809 | } |
79e53945 JB |
14810 | } |
14811 | ||
e72f9fbf | 14812 | intel_shared_dpll_init(dev); |
ee7b9f93 | 14813 | |
9cce37f4 JB |
14814 | /* Just disable it once at startup */ |
14815 | i915_disable_vga(dev); | |
79e53945 | 14816 | intel_setup_outputs(dev); |
11be49eb CW |
14817 | |
14818 | /* Just in case the BIOS is doing something questionable. */ | |
7733b49b | 14819 | intel_fbc_disable(dev_priv); |
fa9fa083 | 14820 | |
6e9f798d | 14821 | drm_modeset_lock_all(dev); |
043e9bda | 14822 | intel_modeset_setup_hw_state(dev); |
6e9f798d | 14823 | drm_modeset_unlock_all(dev); |
46f297fb | 14824 | |
d3fcc808 | 14825 | for_each_intel_crtc(dev, crtc) { |
eeebeac5 ML |
14826 | struct intel_initial_plane_config plane_config = {}; |
14827 | ||
46f297fb JB |
14828 | if (!crtc->active) |
14829 | continue; | |
14830 | ||
46f297fb | 14831 | /* |
46f297fb JB |
14832 | * Note that reserving the BIOS fb up front prevents us |
14833 | * from stuffing other stolen allocations like the ring | |
14834 | * on top. This prevents some ugliness at boot time, and | |
14835 | * can even allow for smooth boot transitions if the BIOS | |
14836 | * fb is large enough for the active pipe configuration. | |
14837 | */ | |
eeebeac5 ML |
14838 | dev_priv->display.get_initial_plane_config(crtc, |
14839 | &plane_config); | |
14840 | ||
14841 | /* | |
14842 | * If the fb is shared between multiple heads, we'll | |
14843 | * just get the first one. | |
14844 | */ | |
14845 | intel_find_initial_plane_obj(crtc, &plane_config); | |
46f297fb | 14846 | } |
2c7111db CW |
14847 | } |
14848 | ||
7fad798e DV |
14849 | static void intel_enable_pipe_a(struct drm_device *dev) |
14850 | { | |
14851 | struct intel_connector *connector; | |
14852 | struct drm_connector *crt = NULL; | |
14853 | struct intel_load_detect_pipe load_detect_temp; | |
208bf9fd | 14854 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; |
7fad798e DV |
14855 | |
14856 | /* We can't just switch on the pipe A, we need to set things up with a | |
14857 | * proper mode and output configuration. As a gross hack, enable pipe A | |
14858 | * by enabling the load detect pipe once. */ | |
3a3371ff | 14859 | for_each_intel_connector(dev, connector) { |
7fad798e DV |
14860 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
14861 | crt = &connector->base; | |
14862 | break; | |
14863 | } | |
14864 | } | |
14865 | ||
14866 | if (!crt) | |
14867 | return; | |
14868 | ||
208bf9fd | 14869 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) |
49172fee | 14870 | intel_release_load_detect_pipe(crt, &load_detect_temp, ctx); |
7fad798e DV |
14871 | } |
14872 | ||
fa555837 DV |
14873 | static bool |
14874 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
14875 | { | |
7eb552ae BW |
14876 | struct drm_device *dev = crtc->base.dev; |
14877 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 DV |
14878 | u32 reg, val; |
14879 | ||
7eb552ae | 14880 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
14881 | return true; |
14882 | ||
14883 | reg = DSPCNTR(!crtc->plane); | |
14884 | val = I915_READ(reg); | |
14885 | ||
14886 | if ((val & DISPLAY_PLANE_ENABLE) && | |
14887 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
14888 | return false; | |
14889 | ||
14890 | return true; | |
14891 | } | |
14892 | ||
02e93c35 VS |
14893 | static bool intel_crtc_has_encoders(struct intel_crtc *crtc) |
14894 | { | |
14895 | struct drm_device *dev = crtc->base.dev; | |
14896 | struct intel_encoder *encoder; | |
14897 | ||
14898 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) | |
14899 | return true; | |
14900 | ||
14901 | return false; | |
14902 | } | |
14903 | ||
24929352 DV |
14904 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
14905 | { | |
14906 | struct drm_device *dev = crtc->base.dev; | |
14907 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 | 14908 | u32 reg; |
24929352 | 14909 | |
24929352 | 14910 | /* Clear any frame start delays used for debugging left by the BIOS */ |
6e3c9717 | 14911 | reg = PIPECONF(crtc->config->cpu_transcoder); |
24929352 DV |
14912 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
14913 | ||
d3eaf884 | 14914 | /* restore vblank interrupts to correct state */ |
9625604c | 14915 | drm_crtc_vblank_reset(&crtc->base); |
d297e103 | 14916 | if (crtc->active) { |
f9cd7b88 VS |
14917 | struct intel_plane *plane; |
14918 | ||
9625604c | 14919 | drm_crtc_vblank_on(&crtc->base); |
f9cd7b88 VS |
14920 | |
14921 | /* Disable everything but the primary plane */ | |
14922 | for_each_intel_plane_on_crtc(dev, crtc, plane) { | |
14923 | if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) | |
14924 | continue; | |
14925 | ||
14926 | plane->disable_plane(&plane->base, &crtc->base); | |
14927 | } | |
9625604c | 14928 | } |
d3eaf884 | 14929 | |
24929352 | 14930 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
14931 | * disable the crtc (and hence change the state) if it is wrong. Note |
14932 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
14933 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
14934 | bool plane; |
14935 | ||
24929352 DV |
14936 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
14937 | crtc->base.base.id); | |
14938 | ||
14939 | /* Pipe has the wrong plane attached and the plane is active. | |
14940 | * Temporarily change the plane mapping and disable everything | |
14941 | * ... */ | |
14942 | plane = crtc->plane; | |
b70709a6 | 14943 | to_intel_plane_state(crtc->base.primary->state)->visible = true; |
24929352 | 14944 | crtc->plane = !plane; |
b17d48e2 | 14945 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 14946 | crtc->plane = plane; |
24929352 | 14947 | } |
24929352 | 14948 | |
7fad798e DV |
14949 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
14950 | crtc->pipe == PIPE_A && !crtc->active) { | |
14951 | /* BIOS forgot to enable pipe A, this mostly happens after | |
14952 | * resume. Force-enable the pipe to fix this, the update_dpms | |
14953 | * call below we restore the pipe to the right state, but leave | |
14954 | * the required bits on. */ | |
14955 | intel_enable_pipe_a(dev); | |
14956 | } | |
14957 | ||
24929352 DV |
14958 | /* Adjust the state of the output pipe according to whether we |
14959 | * have active connectors/encoders. */ | |
02e93c35 | 14960 | if (!intel_crtc_has_encoders(crtc)) |
b17d48e2 | 14961 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 14962 | |
53d9f4e9 | 14963 | if (crtc->active != crtc->base.state->active) { |
02e93c35 | 14964 | struct intel_encoder *encoder; |
24929352 DV |
14965 | |
14966 | /* This can happen either due to bugs in the get_hw_state | |
b17d48e2 ML |
14967 | * functions or because of calls to intel_crtc_disable_noatomic, |
14968 | * or because the pipe is force-enabled due to the | |
24929352 DV |
14969 | * pipe A quirk. */ |
14970 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", | |
14971 | crtc->base.base.id, | |
83d65738 | 14972 | crtc->base.state->enable ? "enabled" : "disabled", |
24929352 DV |
14973 | crtc->active ? "enabled" : "disabled"); |
14974 | ||
4be40c98 | 14975 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0); |
49d6fa21 | 14976 | crtc->base.state->active = crtc->active; |
24929352 DV |
14977 | crtc->base.enabled = crtc->active; |
14978 | ||
14979 | /* Because we only establish the connector -> encoder -> | |
14980 | * crtc links if something is active, this means the | |
14981 | * crtc is now deactivated. Break the links. connector | |
14982 | * -> encoder links are only establish when things are | |
14983 | * actually up, hence no need to break them. */ | |
14984 | WARN_ON(crtc->active); | |
14985 | ||
2d406bb0 | 14986 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
24929352 | 14987 | encoder->base.crtc = NULL; |
24929352 | 14988 | } |
c5ab3bc0 | 14989 | |
a3ed6aad | 14990 | if (crtc->active || HAS_GMCH_DISPLAY(dev)) { |
4cc31489 DV |
14991 | /* |
14992 | * We start out with underrun reporting disabled to avoid races. | |
14993 | * For correct bookkeeping mark this on active crtcs. | |
14994 | * | |
c5ab3bc0 DV |
14995 | * Also on gmch platforms we dont have any hardware bits to |
14996 | * disable the underrun reporting. Which means we need to start | |
14997 | * out with underrun reporting disabled also on inactive pipes, | |
14998 | * since otherwise we'll complain about the garbage we read when | |
14999 | * e.g. coming up after runtime pm. | |
15000 | * | |
4cc31489 DV |
15001 | * No protection against concurrent access is required - at |
15002 | * worst a fifo underrun happens which also sets this to false. | |
15003 | */ | |
15004 | crtc->cpu_fifo_underrun_disabled = true; | |
15005 | crtc->pch_fifo_underrun_disabled = true; | |
15006 | } | |
24929352 DV |
15007 | } |
15008 | ||
15009 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
15010 | { | |
15011 | struct intel_connector *connector; | |
15012 | struct drm_device *dev = encoder->base.dev; | |
873ffe69 | 15013 | bool active = false; |
24929352 DV |
15014 | |
15015 | /* We need to check both for a crtc link (meaning that the | |
15016 | * encoder is active and trying to read from a pipe) and the | |
15017 | * pipe itself being active. */ | |
15018 | bool has_active_crtc = encoder->base.crtc && | |
15019 | to_intel_crtc(encoder->base.crtc)->active; | |
15020 | ||
873ffe69 ML |
15021 | for_each_intel_connector(dev, connector) { |
15022 | if (connector->base.encoder != &encoder->base) | |
15023 | continue; | |
15024 | ||
15025 | active = true; | |
15026 | break; | |
15027 | } | |
15028 | ||
15029 | if (active && !has_active_crtc) { | |
24929352 DV |
15030 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", |
15031 | encoder->base.base.id, | |
8e329a03 | 15032 | encoder->base.name); |
24929352 DV |
15033 | |
15034 | /* Connector is active, but has no active pipe. This is | |
15035 | * fallout from our resume register restoring. Disable | |
15036 | * the encoder manually again. */ | |
15037 | if (encoder->base.crtc) { | |
15038 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
15039 | encoder->base.base.id, | |
8e329a03 | 15040 | encoder->base.name); |
24929352 | 15041 | encoder->disable(encoder); |
a62d1497 VS |
15042 | if (encoder->post_disable) |
15043 | encoder->post_disable(encoder); | |
24929352 | 15044 | } |
7f1950fb | 15045 | encoder->base.crtc = NULL; |
24929352 DV |
15046 | |
15047 | /* Inconsistent output/port/pipe state happens presumably due to | |
15048 | * a bug in one of the get_hw_state functions. Or someplace else | |
15049 | * in our code, like the register restore mess on resume. Clamp | |
15050 | * things to off as a safer default. */ | |
3a3371ff | 15051 | for_each_intel_connector(dev, connector) { |
24929352 DV |
15052 | if (connector->encoder != encoder) |
15053 | continue; | |
7f1950fb EE |
15054 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
15055 | connector->base.encoder = NULL; | |
24929352 DV |
15056 | } |
15057 | } | |
15058 | /* Enabled encoders without active connectors will be fixed in | |
15059 | * the crtc fixup. */ | |
15060 | } | |
15061 | ||
04098753 | 15062 | void i915_redisable_vga_power_on(struct drm_device *dev) |
0fde901f KM |
15063 | { |
15064 | struct drm_i915_private *dev_priv = dev->dev_private; | |
766aa1c4 | 15065 | u32 vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 15066 | |
04098753 ID |
15067 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
15068 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
15069 | i915_disable_vga(dev); | |
15070 | } | |
15071 | } | |
15072 | ||
15073 | void i915_redisable_vga(struct drm_device *dev) | |
15074 | { | |
15075 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15076 | ||
8dc8a27c PZ |
15077 | /* This function can be called both from intel_modeset_setup_hw_state or |
15078 | * at a very early point in our resume sequence, where the power well | |
15079 | * structures are not yet restored. Since this function is at a very | |
15080 | * paranoid "someone might have enabled VGA while we were not looking" | |
15081 | * level, just check if the power well is enabled instead of trying to | |
15082 | * follow the "don't touch the power well if we don't need it" policy | |
15083 | * the rest of the driver uses. */ | |
f458ebbc | 15084 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
15085 | return; |
15086 | ||
04098753 | 15087 | i915_redisable_vga_power_on(dev); |
0fde901f KM |
15088 | } |
15089 | ||
f9cd7b88 | 15090 | static bool primary_get_hw_state(struct intel_plane *plane) |
98ec7739 | 15091 | { |
f9cd7b88 | 15092 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
98ec7739 | 15093 | |
f9cd7b88 | 15094 | return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE; |
d032ffa0 ML |
15095 | } |
15096 | ||
f9cd7b88 VS |
15097 | /* FIXME read out full plane state for all planes */ |
15098 | static void readout_plane_state(struct intel_crtc *crtc) | |
d032ffa0 | 15099 | { |
f9cd7b88 VS |
15100 | struct intel_plane_state *plane_state = |
15101 | to_intel_plane_state(crtc->base.primary->state); | |
d032ffa0 | 15102 | |
f9cd7b88 VS |
15103 | plane_state->visible = |
15104 | primary_get_hw_state(to_intel_plane(crtc->base.primary)); | |
98ec7739 VS |
15105 | } |
15106 | ||
30e984df | 15107 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 DV |
15108 | { |
15109 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15110 | enum pipe pipe; | |
24929352 DV |
15111 | struct intel_crtc *crtc; |
15112 | struct intel_encoder *encoder; | |
15113 | struct intel_connector *connector; | |
5358901f | 15114 | int i; |
24929352 | 15115 | |
d3fcc808 | 15116 | for_each_intel_crtc(dev, crtc) { |
b06f8b0d | 15117 | __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state); |
6e3c9717 | 15118 | memset(crtc->config, 0, sizeof(*crtc->config)); |
f7217905 | 15119 | crtc->config->base.crtc = &crtc->base; |
3b117c8f | 15120 | |
0e8ffe1b | 15121 | crtc->active = dev_priv->display.get_pipe_config(crtc, |
6e3c9717 | 15122 | crtc->config); |
24929352 | 15123 | |
49d6fa21 | 15124 | crtc->base.state->active = crtc->active; |
24929352 | 15125 | crtc->base.enabled = crtc->active; |
b70709a6 | 15126 | |
f9cd7b88 | 15127 | readout_plane_state(crtc); |
24929352 DV |
15128 | |
15129 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
15130 | crtc->base.base.id, | |
15131 | crtc->active ? "enabled" : "disabled"); | |
15132 | } | |
15133 | ||
5358901f DV |
15134 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15135 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15136 | ||
3e369b76 ACO |
15137 | pll->on = pll->get_hw_state(dev_priv, pll, |
15138 | &pll->config.hw_state); | |
5358901f | 15139 | pll->active = 0; |
3e369b76 | 15140 | pll->config.crtc_mask = 0; |
d3fcc808 | 15141 | for_each_intel_crtc(dev, crtc) { |
1e6f2ddc | 15142 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) { |
5358901f | 15143 | pll->active++; |
3e369b76 | 15144 | pll->config.crtc_mask |= 1 << crtc->pipe; |
1e6f2ddc | 15145 | } |
5358901f | 15146 | } |
5358901f | 15147 | |
1e6f2ddc | 15148 | DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", |
3e369b76 | 15149 | pll->name, pll->config.crtc_mask, pll->on); |
bd2bb1b9 | 15150 | |
3e369b76 | 15151 | if (pll->config.crtc_mask) |
bd2bb1b9 | 15152 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
5358901f DV |
15153 | } |
15154 | ||
b2784e15 | 15155 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
15156 | pipe = 0; |
15157 | ||
15158 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
15159 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
15160 | encoder->base.crtc = &crtc->base; | |
6e3c9717 | 15161 | encoder->get_config(encoder, crtc->config); |
24929352 DV |
15162 | } else { |
15163 | encoder->base.crtc = NULL; | |
15164 | } | |
15165 | ||
6f2bcceb | 15166 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
24929352 | 15167 | encoder->base.base.id, |
8e329a03 | 15168 | encoder->base.name, |
24929352 | 15169 | encoder->base.crtc ? "enabled" : "disabled", |
6f2bcceb | 15170 | pipe_name(pipe)); |
24929352 DV |
15171 | } |
15172 | ||
3a3371ff | 15173 | for_each_intel_connector(dev, connector) { |
24929352 DV |
15174 | if (connector->get_hw_state(connector)) { |
15175 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
24929352 DV |
15176 | connector->base.encoder = &connector->encoder->base; |
15177 | } else { | |
15178 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
15179 | connector->base.encoder = NULL; | |
15180 | } | |
15181 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
15182 | connector->base.base.id, | |
c23cc417 | 15183 | connector->base.name, |
24929352 DV |
15184 | connector->base.encoder ? "enabled" : "disabled"); |
15185 | } | |
7f4c6284 VS |
15186 | |
15187 | for_each_intel_crtc(dev, crtc) { | |
15188 | crtc->base.hwmode = crtc->config->base.adjusted_mode; | |
15189 | ||
15190 | memset(&crtc->base.mode, 0, sizeof(crtc->base.mode)); | |
15191 | if (crtc->base.state->active) { | |
15192 | intel_mode_from_pipe_config(&crtc->base.mode, crtc->config); | |
15193 | intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config); | |
15194 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode)); | |
15195 | ||
15196 | /* | |
15197 | * The initial mode needs to be set in order to keep | |
15198 | * the atomic core happy. It wants a valid mode if the | |
15199 | * crtc's enabled, so we do the above call. | |
15200 | * | |
15201 | * At this point some state updated by the connectors | |
15202 | * in their ->detect() callback has not run yet, so | |
15203 | * no recalculation can be done yet. | |
15204 | * | |
15205 | * Even if we could do a recalculation and modeset | |
15206 | * right now it would cause a double modeset if | |
15207 | * fbdev or userspace chooses a different initial mode. | |
15208 | * | |
15209 | * If that happens, someone indicated they wanted a | |
15210 | * mode change, which means it's safe to do a full | |
15211 | * recalculation. | |
15212 | */ | |
15213 | crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED; | |
9eca6832 VS |
15214 | |
15215 | drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode); | |
15216 | update_scanline_offset(crtc); | |
7f4c6284 VS |
15217 | } |
15218 | } | |
30e984df DV |
15219 | } |
15220 | ||
043e9bda ML |
15221 | /* Scan out the current hw modeset state, |
15222 | * and sanitizes it to the current state | |
15223 | */ | |
15224 | static void | |
15225 | intel_modeset_setup_hw_state(struct drm_device *dev) | |
30e984df DV |
15226 | { |
15227 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15228 | enum pipe pipe; | |
30e984df DV |
15229 | struct intel_crtc *crtc; |
15230 | struct intel_encoder *encoder; | |
35c95375 | 15231 | int i; |
30e984df DV |
15232 | |
15233 | intel_modeset_readout_hw_state(dev); | |
24929352 DV |
15234 | |
15235 | /* HW state is read out, now we need to sanitize this mess. */ | |
b2784e15 | 15236 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
15237 | intel_sanitize_encoder(encoder); |
15238 | } | |
15239 | ||
055e393f | 15240 | for_each_pipe(dev_priv, pipe) { |
24929352 DV |
15241 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
15242 | intel_sanitize_crtc(crtc); | |
6e3c9717 ACO |
15243 | intel_dump_pipe_config(crtc, crtc->config, |
15244 | "[setup_hw_state]"); | |
24929352 | 15245 | } |
9a935856 | 15246 | |
d29b2f9d ACO |
15247 | intel_modeset_update_connector_atomic_state(dev); |
15248 | ||
35c95375 DV |
15249 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15250 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15251 | ||
15252 | if (!pll->on || pll->active) | |
15253 | continue; | |
15254 | ||
15255 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
15256 | ||
15257 | pll->disable(dev_priv, pll); | |
15258 | pll->on = false; | |
15259 | } | |
15260 | ||
26e1fe4f | 15261 | if (IS_VALLEYVIEW(dev)) |
6eb1a681 VS |
15262 | vlv_wm_get_hw_state(dev); |
15263 | else if (IS_GEN9(dev)) | |
3078999f PB |
15264 | skl_wm_get_hw_state(dev); |
15265 | else if (HAS_PCH_SPLIT(dev)) | |
243e6a44 | 15266 | ilk_wm_get_hw_state(dev); |
292b990e ML |
15267 | |
15268 | for_each_intel_crtc(dev, crtc) { | |
15269 | unsigned long put_domains; | |
15270 | ||
15271 | put_domains = modeset_get_crtc_power_domains(&crtc->base); | |
15272 | if (WARN_ON(put_domains)) | |
15273 | modeset_put_power_domains(dev_priv, put_domains); | |
15274 | } | |
15275 | intel_display_set_init_power(dev_priv, false); | |
043e9bda | 15276 | } |
7d0bc1ea | 15277 | |
043e9bda ML |
15278 | void intel_display_resume(struct drm_device *dev) |
15279 | { | |
15280 | struct drm_atomic_state *state = drm_atomic_state_alloc(dev); | |
15281 | struct intel_connector *conn; | |
15282 | struct intel_plane *plane; | |
15283 | struct drm_crtc *crtc; | |
15284 | int ret; | |
f30da187 | 15285 | |
043e9bda ML |
15286 | if (!state) |
15287 | return; | |
15288 | ||
15289 | state->acquire_ctx = dev->mode_config.acquire_ctx; | |
15290 | ||
15291 | /* preserve complete old state, including dpll */ | |
15292 | intel_atomic_get_shared_dpll_state(state); | |
15293 | ||
15294 | for_each_crtc(dev, crtc) { | |
15295 | struct drm_crtc_state *crtc_state = | |
15296 | drm_atomic_get_crtc_state(state, crtc); | |
15297 | ||
15298 | ret = PTR_ERR_OR_ZERO(crtc_state); | |
15299 | if (ret) | |
15300 | goto err; | |
15301 | ||
15302 | /* force a restore */ | |
15303 | crtc_state->mode_changed = true; | |
45e2b5f6 | 15304 | } |
8af6cf88 | 15305 | |
043e9bda ML |
15306 | for_each_intel_plane(dev, plane) { |
15307 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base)); | |
15308 | if (ret) | |
15309 | goto err; | |
15310 | } | |
15311 | ||
15312 | for_each_intel_connector(dev, conn) { | |
15313 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base)); | |
15314 | if (ret) | |
15315 | goto err; | |
15316 | } | |
15317 | ||
15318 | intel_modeset_setup_hw_state(dev); | |
15319 | ||
15320 | i915_redisable_vga(dev); | |
74c090b1 | 15321 | ret = drm_atomic_commit(state); |
043e9bda ML |
15322 | if (!ret) |
15323 | return; | |
15324 | ||
15325 | err: | |
15326 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
15327 | drm_atomic_state_free(state); | |
2c7111db CW |
15328 | } |
15329 | ||
15330 | void intel_modeset_gem_init(struct drm_device *dev) | |
15331 | { | |
484b41dd | 15332 | struct drm_crtc *c; |
2ff8fde1 | 15333 | struct drm_i915_gem_object *obj; |
e0d6149b | 15334 | int ret; |
484b41dd | 15335 | |
ae48434c ID |
15336 | mutex_lock(&dev->struct_mutex); |
15337 | intel_init_gt_powersave(dev); | |
15338 | mutex_unlock(&dev->struct_mutex); | |
15339 | ||
1833b134 | 15340 | intel_modeset_init_hw(dev); |
02e792fb DV |
15341 | |
15342 | intel_setup_overlay(dev); | |
484b41dd JB |
15343 | |
15344 | /* | |
15345 | * Make sure any fbs we allocated at startup are properly | |
15346 | * pinned & fenced. When we do the allocation it's too early | |
15347 | * for this. | |
15348 | */ | |
70e1e0ec | 15349 | for_each_crtc(dev, c) { |
2ff8fde1 MR |
15350 | obj = intel_fb_obj(c->primary->fb); |
15351 | if (obj == NULL) | |
484b41dd JB |
15352 | continue; |
15353 | ||
e0d6149b TU |
15354 | mutex_lock(&dev->struct_mutex); |
15355 | ret = intel_pin_and_fence_fb_obj(c->primary, | |
15356 | c->primary->fb, | |
15357 | c->primary->state, | |
91af127f | 15358 | NULL, NULL); |
e0d6149b TU |
15359 | mutex_unlock(&dev->struct_mutex); |
15360 | if (ret) { | |
484b41dd JB |
15361 | DRM_ERROR("failed to pin boot fb on pipe %d\n", |
15362 | to_intel_crtc(c)->pipe); | |
66e514c1 DA |
15363 | drm_framebuffer_unreference(c->primary->fb); |
15364 | c->primary->fb = NULL; | |
36750f28 | 15365 | c->primary->crtc = c->primary->state->crtc = NULL; |
afd65eb4 | 15366 | update_state_fb(c->primary); |
36750f28 | 15367 | c->state->plane_mask &= ~(1 << drm_plane_index(c->primary)); |
484b41dd JB |
15368 | } |
15369 | } | |
0962c3c9 VS |
15370 | |
15371 | intel_backlight_register(dev); | |
79e53945 JB |
15372 | } |
15373 | ||
4932e2c3 ID |
15374 | void intel_connector_unregister(struct intel_connector *intel_connector) |
15375 | { | |
15376 | struct drm_connector *connector = &intel_connector->base; | |
15377 | ||
15378 | intel_panel_destroy_backlight(connector); | |
34ea3d38 | 15379 | drm_connector_unregister(connector); |
4932e2c3 ID |
15380 | } |
15381 | ||
79e53945 JB |
15382 | void intel_modeset_cleanup(struct drm_device *dev) |
15383 | { | |
652c393a | 15384 | struct drm_i915_private *dev_priv = dev->dev_private; |
d9255d57 | 15385 | struct drm_connector *connector; |
652c393a | 15386 | |
2eb5252e ID |
15387 | intel_disable_gt_powersave(dev); |
15388 | ||
0962c3c9 VS |
15389 | intel_backlight_unregister(dev); |
15390 | ||
fd0c0642 DV |
15391 | /* |
15392 | * Interrupts and polling as the first thing to avoid creating havoc. | |
2eb5252e | 15393 | * Too much stuff here (turning of connectors, ...) would |
fd0c0642 DV |
15394 | * experience fancy races otherwise. |
15395 | */ | |
2aeb7d3a | 15396 | intel_irq_uninstall(dev_priv); |
eb21b92b | 15397 | |
fd0c0642 DV |
15398 | /* |
15399 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
15400 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
15401 | */ | |
f87ea761 | 15402 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 15403 | |
723bfd70 JB |
15404 | intel_unregister_dsm_handler(); |
15405 | ||
7733b49b | 15406 | intel_fbc_disable(dev_priv); |
69341a5e | 15407 | |
1630fe75 CW |
15408 | /* flush any delayed tasks or pending work */ |
15409 | flush_scheduled_work(); | |
15410 | ||
db31af1d JN |
15411 | /* destroy the backlight and sysfs files before encoders/connectors */ |
15412 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
4932e2c3 ID |
15413 | struct intel_connector *intel_connector; |
15414 | ||
15415 | intel_connector = to_intel_connector(connector); | |
15416 | intel_connector->unregister(intel_connector); | |
db31af1d | 15417 | } |
d9255d57 | 15418 | |
79e53945 | 15419 | drm_mode_config_cleanup(dev); |
4d7bb011 DV |
15420 | |
15421 | intel_cleanup_overlay(dev); | |
ae48434c ID |
15422 | |
15423 | mutex_lock(&dev->struct_mutex); | |
15424 | intel_cleanup_gt_powersave(dev); | |
15425 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
15426 | } |
15427 | ||
f1c79df3 ZW |
15428 | /* |
15429 | * Return which encoder is currently attached for connector. | |
15430 | */ | |
df0e9248 | 15431 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 15432 | { |
df0e9248 CW |
15433 | return &intel_attached_encoder(connector)->base; |
15434 | } | |
f1c79df3 | 15435 | |
df0e9248 CW |
15436 | void intel_connector_attach_encoder(struct intel_connector *connector, |
15437 | struct intel_encoder *encoder) | |
15438 | { | |
15439 | connector->encoder = encoder; | |
15440 | drm_mode_connector_attach_encoder(&connector->base, | |
15441 | &encoder->base); | |
79e53945 | 15442 | } |
28d52043 DA |
15443 | |
15444 | /* | |
15445 | * set vga decode state - true == enable VGA decode | |
15446 | */ | |
15447 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
15448 | { | |
15449 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a885b3cc | 15450 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
15451 | u16 gmch_ctrl; |
15452 | ||
75fa041d CW |
15453 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
15454 | DRM_ERROR("failed to read control word\n"); | |
15455 | return -EIO; | |
15456 | } | |
15457 | ||
c0cc8a55 CW |
15458 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
15459 | return 0; | |
15460 | ||
28d52043 DA |
15461 | if (state) |
15462 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
15463 | else | |
15464 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
15465 | |
15466 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
15467 | DRM_ERROR("failed to write control word\n"); | |
15468 | return -EIO; | |
15469 | } | |
15470 | ||
28d52043 DA |
15471 | return 0; |
15472 | } | |
c4a1d9e4 | 15473 | |
c4a1d9e4 | 15474 | struct intel_display_error_state { |
ff57f1b0 PZ |
15475 | |
15476 | u32 power_well_driver; | |
15477 | ||
63b66e5b CW |
15478 | int num_transcoders; |
15479 | ||
c4a1d9e4 CW |
15480 | struct intel_cursor_error_state { |
15481 | u32 control; | |
15482 | u32 position; | |
15483 | u32 base; | |
15484 | u32 size; | |
52331309 | 15485 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
15486 | |
15487 | struct intel_pipe_error_state { | |
ddf9c536 | 15488 | bool power_domain_on; |
c4a1d9e4 | 15489 | u32 source; |
f301b1e1 | 15490 | u32 stat; |
52331309 | 15491 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
15492 | |
15493 | struct intel_plane_error_state { | |
15494 | u32 control; | |
15495 | u32 stride; | |
15496 | u32 size; | |
15497 | u32 pos; | |
15498 | u32 addr; | |
15499 | u32 surface; | |
15500 | u32 tile_offset; | |
52331309 | 15501 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
15502 | |
15503 | struct intel_transcoder_error_state { | |
ddf9c536 | 15504 | bool power_domain_on; |
63b66e5b CW |
15505 | enum transcoder cpu_transcoder; |
15506 | ||
15507 | u32 conf; | |
15508 | ||
15509 | u32 htotal; | |
15510 | u32 hblank; | |
15511 | u32 hsync; | |
15512 | u32 vtotal; | |
15513 | u32 vblank; | |
15514 | u32 vsync; | |
15515 | } transcoder[4]; | |
c4a1d9e4 CW |
15516 | }; |
15517 | ||
15518 | struct intel_display_error_state * | |
15519 | intel_display_capture_error_state(struct drm_device *dev) | |
15520 | { | |
fbee40df | 15521 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 | 15522 | struct intel_display_error_state *error; |
63b66e5b CW |
15523 | int transcoders[] = { |
15524 | TRANSCODER_A, | |
15525 | TRANSCODER_B, | |
15526 | TRANSCODER_C, | |
15527 | TRANSCODER_EDP, | |
15528 | }; | |
c4a1d9e4 CW |
15529 | int i; |
15530 | ||
63b66e5b CW |
15531 | if (INTEL_INFO(dev)->num_pipes == 0) |
15532 | return NULL; | |
15533 | ||
9d1cb914 | 15534 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
15535 | if (error == NULL) |
15536 | return NULL; | |
15537 | ||
190be112 | 15538 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ff57f1b0 PZ |
15539 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
15540 | ||
055e393f | 15541 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 15542 | error->pipe[i].power_domain_on = |
f458ebbc DV |
15543 | __intel_display_power_is_enabled(dev_priv, |
15544 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 15545 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
15546 | continue; |
15547 | ||
5efb3e28 VS |
15548 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
15549 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
15550 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
15551 | |
15552 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
15553 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
80ca378b | 15554 | if (INTEL_INFO(dev)->gen <= 3) { |
51889b35 | 15555 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
15556 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
15557 | } | |
ca291363 PZ |
15558 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
15559 | error->plane[i].addr = I915_READ(DSPADDR(i)); | |
c4a1d9e4 CW |
15560 | if (INTEL_INFO(dev)->gen >= 4) { |
15561 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
15562 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
15563 | } | |
15564 | ||
c4a1d9e4 | 15565 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 | 15566 | |
3abfce77 | 15567 | if (HAS_GMCH_DISPLAY(dev)) |
f301b1e1 | 15568 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
63b66e5b CW |
15569 | } |
15570 | ||
15571 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; | |
15572 | if (HAS_DDI(dev_priv->dev)) | |
15573 | error->num_transcoders++; /* Account for eDP. */ | |
15574 | ||
15575 | for (i = 0; i < error->num_transcoders; i++) { | |
15576 | enum transcoder cpu_transcoder = transcoders[i]; | |
15577 | ||
ddf9c536 | 15578 | error->transcoder[i].power_domain_on = |
f458ebbc | 15579 | __intel_display_power_is_enabled(dev_priv, |
38cc1daf | 15580 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 15581 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
15582 | continue; |
15583 | ||
63b66e5b CW |
15584 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
15585 | ||
15586 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
15587 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
15588 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
15589 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
15590 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
15591 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
15592 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
15593 | } |
15594 | ||
15595 | return error; | |
15596 | } | |
15597 | ||
edc3d884 MK |
15598 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
15599 | ||
c4a1d9e4 | 15600 | void |
edc3d884 | 15601 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
15602 | struct drm_device *dev, |
15603 | struct intel_display_error_state *error) | |
15604 | { | |
055e393f | 15605 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 CW |
15606 | int i; |
15607 | ||
63b66e5b CW |
15608 | if (!error) |
15609 | return; | |
15610 | ||
edc3d884 | 15611 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
190be112 | 15612 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
edc3d884 | 15613 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 15614 | error->power_well_driver); |
055e393f | 15615 | for_each_pipe(dev_priv, i) { |
edc3d884 | 15616 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 ID |
15617 | err_printf(m, " Power: %s\n", |
15618 | error->pipe[i].power_domain_on ? "on" : "off"); | |
edc3d884 | 15619 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 15620 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
15621 | |
15622 | err_printf(m, "Plane [%d]:\n", i); | |
15623 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
15624 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 15625 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
15626 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
15627 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 15628 | } |
4b71a570 | 15629 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 15630 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 15631 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
15632 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
15633 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
15634 | } |
15635 | ||
edc3d884 MK |
15636 | err_printf(m, "Cursor [%d]:\n", i); |
15637 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
15638 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
15639 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 15640 | } |
63b66e5b CW |
15641 | |
15642 | for (i = 0; i < error->num_transcoders; i++) { | |
1cf84bb6 | 15643 | err_printf(m, "CPU transcoder: %c\n", |
63b66e5b | 15644 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 ID |
15645 | err_printf(m, " Power: %s\n", |
15646 | error->transcoder[i].power_domain_on ? "on" : "off"); | |
63b66e5b CW |
15647 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
15648 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
15649 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
15650 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
15651 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
15652 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
15653 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
15654 | } | |
c4a1d9e4 | 15655 | } |
e2fcdaa9 VS |
15656 | |
15657 | void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file) | |
15658 | { | |
15659 | struct intel_crtc *crtc; | |
15660 | ||
15661 | for_each_intel_crtc(dev, crtc) { | |
15662 | struct intel_unpin_work *work; | |
e2fcdaa9 | 15663 | |
5e2d7afc | 15664 | spin_lock_irq(&dev->event_lock); |
e2fcdaa9 VS |
15665 | |
15666 | work = crtc->unpin_work; | |
15667 | ||
15668 | if (work && work->event && | |
15669 | work->event->base.file_priv == file) { | |
15670 | kfree(work->event); | |
15671 | work->event = NULL; | |
15672 | } | |
15673 | ||
5e2d7afc | 15674 | spin_unlock_irq(&dev->event_lock); |
e2fcdaa9 VS |
15675 | } |
15676 | } |