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drm/i915: implement WaDisableRenderCachePipelinedFlush
[linux-block.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
32f9d658
ZW		 44#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
0206e353 46bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 47static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 48static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 49
50typedef struct {
0206e353
AJ		 51 /* given values */
52 int n;
53 int m1, m2;
54 int p1, p2;
55 /* derived values */
56 int dot;
57 int vco;
58 int m;
59 int p;
79e53945
JB		 60} intel_clock_t;
61
62typedef struct {
0206e353 63 int min, max;
79e53945
JB		 64} intel_range_t;
65
66typedef struct {
0206e353
AJ		 67 int dot_limit;
68 int p2_slow, p2_fast;
79e53945
JB		 69} intel_p2_t;
70
71#define INTEL_P2_NUM 2
d4906093
ML		 72typedef struct intel_limit intel_limit_t;
73struct intel_limit {
0206e353
AJ		 74 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 intel_p2_t p2;
76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
cec2f356 77 int, int, intel_clock_t *, intel_clock_t *);
d4906093 78};
79e53945 79
2377b741
JB		 80/* FDI */
81#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
82
d2acd215
DV		 83int
84intel_pch_rawclk(struct drm_device *dev)
85{
86 struct drm_i915_private *dev_priv = dev->dev_private;
87
88 WARN_ON(!HAS_PCH_SPLIT(dev));
89
90 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
91}
92
d4906093
ML		 93static bool
94intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 95 int target, int refclk, intel_clock_t *match_clock,
96 intel_clock_t *best_clock);
d4906093
ML		 97static bool
98intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 99 int target, int refclk, intel_clock_t *match_clock,
100 intel_clock_t *best_clock);
79e53945 101
a4fc5ed6
KP		 102static bool
103intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 104 int target, int refclk, intel_clock_t *match_clock,
105 intel_clock_t *best_clock);
5eb08b69 106static bool
f2b115e6 107intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 108 int target, int refclk, intel_clock_t *match_clock,
109 intel_clock_t *best_clock);
a4fc5ed6 110
a0c4da24
JB		 111static bool
112intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
113 int target, int refclk, intel_clock_t *match_clock,
114 intel_clock_t *best_clock);
115
021357ac
CW		 116static inline u32 /* units of 100MHz */
117intel_fdi_link_freq(struct drm_device *dev)
118{
8b99e68c
CW		 119 if (IS_GEN5(dev)) {
120 struct drm_i915_private *dev_priv = dev->dev_private;
121 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
122 } else
123 return 27;
021357ac
CW		 124}
125
e4b36699 126static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 127 .dot = { .min = 25000, .max = 350000 },
128 .vco = { .min = 930000, .max = 1400000 },
129 .n = { .min = 3, .max = 16 },
130 .m = { .min = 96, .max = 140 },
131 .m1 = { .min = 18, .max = 26 },
132 .m2 = { .min = 6, .max = 16 },
133 .p = { .min = 4, .max = 128 },
134 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 135 .p2 = { .dot_limit = 165000,
136 .p2_slow = 4, .p2_fast = 2 },
d4906093 137 .find_pll = intel_find_best_PLL,
e4b36699
KP		 138};
139
140static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 141 .dot = { .min = 25000, .max = 350000 },
142 .vco = { .min = 930000, .max = 1400000 },
143 .n = { .min = 3, .max = 16 },
144 .m = { .min = 96, .max = 140 },
145 .m1 = { .min = 18, .max = 26 },
146 .m2 = { .min = 6, .max = 16 },
147 .p = { .min = 4, .max = 128 },
148 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 149 .p2 = { .dot_limit = 165000,
150 .p2_slow = 14, .p2_fast = 7 },
d4906093 151 .find_pll = intel_find_best_PLL,
e4b36699 152};
273e27ca 153
e4b36699 154static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 155 .dot = { .min = 20000, .max = 400000 },
156 .vco = { .min = 1400000, .max = 2800000 },
157 .n = { .min = 1, .max = 6 },
158 .m = { .min = 70, .max = 120 },
159 .m1 = { .min = 10, .max = 22 },
160 .m2 = { .min = 5, .max = 9 },
161 .p = { .min = 5, .max = 80 },
162 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 163 .p2 = { .dot_limit = 200000,
164 .p2_slow = 10, .p2_fast = 5 },
d4906093 165 .find_pll = intel_find_best_PLL,
e4b36699
KP		 166};
167
168static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 169 .dot = { .min = 20000, .max = 400000 },
170 .vco = { .min = 1400000, .max = 2800000 },
171 .n = { .min = 1, .max = 6 },
172 .m = { .min = 70, .max = 120 },
173 .m1 = { .min = 10, .max = 22 },
174 .m2 = { .min = 5, .max = 9 },
175 .p = { .min = 7, .max = 98 },
176 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 177 .p2 = { .dot_limit = 112000,
178 .p2_slow = 14, .p2_fast = 7 },
d4906093 179 .find_pll = intel_find_best_PLL,
e4b36699
KP		 180};
181
273e27ca 182
e4b36699 183static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 184 .dot = { .min = 25000, .max = 270000 },
185 .vco = { .min = 1750000, .max = 3500000},
186 .n = { .min = 1, .max = 4 },
187 .m = { .min = 104, .max = 138 },
188 .m1 = { .min = 17, .max = 23 },
189 .m2 = { .min = 5, .max = 11 },
190 .p = { .min = 10, .max = 30 },
191 .p1 = { .min = 1, .max = 3},
192 .p2 = { .dot_limit = 270000,
193 .p2_slow = 10,
194 .p2_fast = 10
044c7c41 195 },
d4906093 196 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 197};
198
199static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 200 .dot = { .min = 22000, .max = 400000 },
201 .vco = { .min = 1750000, .max = 3500000},
202 .n = { .min = 1, .max = 4 },
203 .m = { .min = 104, .max = 138 },
204 .m1 = { .min = 16, .max = 23 },
205 .m2 = { .min = 5, .max = 11 },
206 .p = { .min = 5, .max = 80 },
207 .p1 = { .min = 1, .max = 8},
208 .p2 = { .dot_limit = 165000,
209 .p2_slow = 10, .p2_fast = 5 },
d4906093 210 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 211};
212
213static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 214 .dot = { .min = 20000, .max = 115000 },
215 .vco = { .min = 1750000, .max = 3500000 },
216 .n = { .min = 1, .max = 3 },
217 .m = { .min = 104, .max = 138 },
218 .m1 = { .min = 17, .max = 23 },
219 .m2 = { .min = 5, .max = 11 },
220 .p = { .min = 28, .max = 112 },
221 .p1 = { .min = 2, .max = 8 },
222 .p2 = { .dot_limit = 0,
223 .p2_slow = 14, .p2_fast = 14
044c7c41 224 },
d4906093 225 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 226};
227
228static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 229 .dot = { .min = 80000, .max = 224000 },
230 .vco = { .min = 1750000, .max = 3500000 },
231 .n = { .min = 1, .max = 3 },
232 .m = { .min = 104, .max = 138 },
233 .m1 = { .min = 17, .max = 23 },
234 .m2 = { .min = 5, .max = 11 },
235 .p = { .min = 14, .max = 42 },
236 .p1 = { .min = 2, .max = 6 },
237 .p2 = { .dot_limit = 0,
238 .p2_slow = 7, .p2_fast = 7
044c7c41 239 },
d4906093 240 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 241};
242
243static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 244 .dot = { .min = 161670, .max = 227000 },
245 .vco = { .min = 1750000, .max = 3500000},
246 .n = { .min = 1, .max = 2 },
247 .m = { .min = 97, .max = 108 },
248 .m1 = { .min = 0x10, .max = 0x12 },
249 .m2 = { .min = 0x05, .max = 0x06 },
250 .p = { .min = 10, .max = 20 },
251 .p1 = { .min = 1, .max = 2},
252 .p2 = { .dot_limit = 0,
273e27ca 253 .p2_slow = 10, .p2_fast = 10 },
0206e353 254 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 255};
256
f2b115e6 257static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 258 .dot = { .min = 20000, .max = 400000},
259 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 260 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 261 .n = { .min = 3, .max = 6 },
262 .m = { .min = 2, .max = 256 },
273e27ca 263 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 264 .m1 = { .min = 0, .max = 0 },
265 .m2 = { .min = 0, .max = 254 },
266 .p = { .min = 5, .max = 80 },
267 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 268 .p2 = { .dot_limit = 200000,
269 .p2_slow = 10, .p2_fast = 5 },
6115707b 270 .find_pll = intel_find_best_PLL,
e4b36699
KP		 271};
272
f2b115e6 273static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 274 .dot = { .min = 20000, .max = 400000 },
275 .vco = { .min = 1700000, .max = 3500000 },
276 .n = { .min = 3, .max = 6 },
277 .m = { .min = 2, .max = 256 },
278 .m1 = { .min = 0, .max = 0 },
279 .m2 = { .min = 0, .max = 254 },
280 .p = { .min = 7, .max = 112 },
281 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 282 .p2 = { .dot_limit = 112000,
283 .p2_slow = 14, .p2_fast = 14 },
6115707b 284 .find_pll = intel_find_best_PLL,
e4b36699
KP		 285};
286
273e27ca
EA		 287/* Ironlake / Sandybridge
288 *
289 * We calculate clock using (register_value + 2) for N/M1/M2, so here
290 * the range value for them is (actual_value - 2).
291 */
b91ad0ec 292static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 293 .dot = { .min = 25000, .max = 350000 },
294 .vco = { .min = 1760000, .max = 3510000 },
295 .n = { .min = 1, .max = 5 },
296 .m = { .min = 79, .max = 127 },
297 .m1 = { .min = 12, .max = 22 },
298 .m2 = { .min = 5, .max = 9 },
299 .p = { .min = 5, .max = 80 },
300 .p1 = { .min = 1, .max = 8 },
301 .p2 = { .dot_limit = 225000,
302 .p2_slow = 10, .p2_fast = 5 },
4547668a 303 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 304};
305
b91ad0ec 306static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 307 .dot = { .min = 25000, .max = 350000 },
308 .vco = { .min = 1760000, .max = 3510000 },
309 .n = { .min = 1, .max = 3 },
310 .m = { .min = 79, .max = 118 },
311 .m1 = { .min = 12, .max = 22 },
312 .m2 = { .min = 5, .max = 9 },
313 .p = { .min = 28, .max = 112 },
314 .p1 = { .min = 2, .max = 8 },
315 .p2 = { .dot_limit = 225000,
316 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 317 .find_pll = intel_g4x_find_best_PLL,
318};
319
320static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 321 .dot = { .min = 25000, .max = 350000 },
322 .vco = { .min = 1760000, .max = 3510000 },
323 .n = { .min = 1, .max = 3 },
324 .m = { .min = 79, .max = 127 },
325 .m1 = { .min = 12, .max = 22 },
326 .m2 = { .min = 5, .max = 9 },
327 .p = { .min = 14, .max = 56 },
328 .p1 = { .min = 2, .max = 8 },
329 .p2 = { .dot_limit = 225000,
330 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 331 .find_pll = intel_g4x_find_best_PLL,
332};
333
273e27ca 334/* LVDS 100mhz refclk limits. */
b91ad0ec 335static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 336 .dot = { .min = 25000, .max = 350000 },
337 .vco = { .min = 1760000, .max = 3510000 },
338 .n = { .min = 1, .max = 2 },
339 .m = { .min = 79, .max = 126 },
340 .m1 = { .min = 12, .max = 22 },
341 .m2 = { .min = 5, .max = 9 },
342 .p = { .min = 28, .max = 112 },
0206e353 343 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 344 .p2 = { .dot_limit = 225000,
345 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 346 .find_pll = intel_g4x_find_best_PLL,
347};
348
349static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 350 .dot = { .min = 25000, .max = 350000 },
351 .vco = { .min = 1760000, .max = 3510000 },
352 .n = { .min = 1, .max = 3 },
353 .m = { .min = 79, .max = 126 },
354 .m1 = { .min = 12, .max = 22 },
355 .m2 = { .min = 5, .max = 9 },
356 .p = { .min = 14, .max = 42 },
0206e353 357 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 358 .p2 = { .dot_limit = 225000,
359 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 360 .find_pll = intel_g4x_find_best_PLL,
361};
362
363static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 364 .dot = { .min = 25000, .max = 350000 },
365 .vco = { .min = 1760000, .max = 3510000},
366 .n = { .min = 1, .max = 2 },
367 .m = { .min = 81, .max = 90 },
368 .m1 = { .min = 12, .max = 22 },
369 .m2 = { .min = 5, .max = 9 },
370 .p = { .min = 10, .max = 20 },
371 .p1 = { .min = 1, .max = 2},
372 .p2 = { .dot_limit = 0,
273e27ca 373 .p2_slow = 10, .p2_fast = 10 },
0206e353 374 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 375};
376
a0c4da24
JB		 377static const intel_limit_t intel_limits_vlv_dac = {
378 .dot = { .min = 25000, .max = 270000 },
379 .vco = { .min = 4000000, .max = 6000000 },
380 .n = { .min = 1, .max = 7 },
381 .m = { .min = 22, .max = 450 }, /* guess */
382 .m1 = { .min = 2, .max = 3 },
383 .m2 = { .min = 11, .max = 156 },
384 .p = { .min = 10, .max = 30 },
385 .p1 = { .min = 2, .max = 3 },
386 .p2 = { .dot_limit = 270000,
387 .p2_slow = 2, .p2_fast = 20 },
388 .find_pll = intel_vlv_find_best_pll,
389};
390
391static const intel_limit_t intel_limits_vlv_hdmi = {
392 .dot = { .min = 20000, .max = 165000 },
17dc9257 393 .vco = { .min = 4000000, .max = 5994000},
a0c4da24
JB		 394 .n = { .min = 1, .max = 7 },
395 .m = { .min = 60, .max = 300 }, /* guess */
396 .m1 = { .min = 2, .max = 3 },
397 .m2 = { .min = 11, .max = 156 },
398 .p = { .min = 10, .max = 30 },
399 .p1 = { .min = 2, .max = 3 },
400 .p2 = { .dot_limit = 270000,
401 .p2_slow = 2, .p2_fast = 20 },
402 .find_pll = intel_vlv_find_best_pll,
403};
404
405static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 406 .dot = { .min = 25000, .max = 270000 },
407 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 408 .n = { .min = 1, .max = 7 },
74a4dd2e 409 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 410 .m1 = { .min = 2, .max = 3 },
411 .m2 = { .min = 11, .max = 156 },
412 .p = { .min = 10, .max = 30 },
413 .p1 = { .min = 2, .max = 3 },
414 .p2 = { .dot_limit = 270000,
415 .p2_slow = 2, .p2_fast = 20 },
416 .find_pll = intel_vlv_find_best_pll,
417};
418
57f350b6
JB		 419u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
420{
421 unsigned long flags;
422 u32 val = 0;
423
424 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
425 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
426 DRM_ERROR("DPIO idle wait timed out\n");
427 goto out_unlock;
428 }
429
430 I915_WRITE(DPIO_REG, reg);
431 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
432 DPIO_BYTE);
433 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
434 DRM_ERROR("DPIO read wait timed out\n");
435 goto out_unlock;
436 }
437 val = I915_READ(DPIO_DATA);
438
439out_unlock:
440 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
441 return val;
442}
443
a0c4da24
JB		 444static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
445 u32 val)
446{
447 unsigned long flags;
448
449 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
450 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
451 DRM_ERROR("DPIO idle wait timed out\n");
452 goto out_unlock;
453 }
454
455 I915_WRITE(DPIO_DATA, val);
456 I915_WRITE(DPIO_REG, reg);
457 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
458 DPIO_BYTE);
459 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
460 DRM_ERROR("DPIO write wait timed out\n");
461
462out_unlock:
463 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
464}
465
57f350b6
JB		 466static void vlv_init_dpio(struct drm_device *dev)
467{
468 struct drm_i915_private *dev_priv = dev->dev_private;
469
470 /* Reset the DPIO config */
471 I915_WRITE(DPIO_CTL, 0);
472 POSTING_READ(DPIO_CTL);
473 I915_WRITE(DPIO_CTL, 1);
474 POSTING_READ(DPIO_CTL);
475}
476
618563e3
DV		 477static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
478{
479 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
480 return 1;
481}
482
483static const struct dmi_system_id intel_dual_link_lvds[] = {
484 {
485 .callback = intel_dual_link_lvds_callback,
486 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
487 .matches = {
488 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
489 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
490 },
491 },
492 { } /* terminating entry */
493};
494
b0354385
TI		 495static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
496 unsigned int reg)
497{
498 unsigned int val;
499
121d527a
TI		 500 /* use the module option value if specified */
501 if (i915_lvds_channel_mode > 0)
502 return i915_lvds_channel_mode == 2;
503
618563e3
DV		 504 if (dmi_check_system(intel_dual_link_lvds))
505 return true;
506
b0354385
TI		 507 if (dev_priv->lvds_val)
508 val = dev_priv->lvds_val;
509 else {
510 /* BIOS should set the proper LVDS register value at boot, but
511 * in reality, it doesn't set the value when the lid is closed;
512 * we need to check "the value to be set" in VBT when LVDS
513 * register is uninitialized.
514 */
515 val = I915_READ(reg);
14d94a3d 516 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
b0354385
TI		 517 val = dev_priv->bios_lvds_val;
518 dev_priv->lvds_val = val;
519 }
520 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
521}
522
1b894b59
CW		 523static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
524 int refclk)
2c07245f 525{
b91ad0ec
ZW		 526 struct drm_device *dev = crtc->dev;
527 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 528 const intel_limit_t *limit;
b91ad0ec
ZW		 529
530 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 531 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
b91ad0ec 532 /* LVDS dual channel */
1b894b59 533 if (refclk == 100000)
b91ad0ec
ZW		 534 limit = &intel_limits_ironlake_dual_lvds_100m;
535 else
536 limit = &intel_limits_ironlake_dual_lvds;
537 } else {
1b894b59 538 if (refclk == 100000)
b91ad0ec
ZW		 539 limit = &intel_limits_ironlake_single_lvds_100m;
540 else
541 limit = &intel_limits_ironlake_single_lvds;
542 }
543 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
4547668a
ZY		 544 HAS_eDP)
545 limit = &intel_limits_ironlake_display_port;
2c07245f 546 else
b91ad0ec 547 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 548
549 return limit;
550}
551
044c7c41
ML		 552static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
553{
554 struct drm_device *dev = crtc->dev;
555 struct drm_i915_private *dev_priv = dev->dev_private;
556 const intel_limit_t *limit;
557
558 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 559 if (is_dual_link_lvds(dev_priv, LVDS))
044c7c41 560 /* LVDS with dual channel */
e4b36699 561 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 562 else
563 /* LVDS with dual channel */
e4b36699 564 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 565 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
566 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 567 limit = &intel_limits_g4x_hdmi;
044c7c41 568 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 569 limit = &intel_limits_g4x_sdvo;
0206e353 570 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 571 limit = &intel_limits_g4x_display_port;
044c7c41 572 } else /* The option is for other outputs */
e4b36699 573 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 574
575 return limit;
576}
577
1b894b59 578static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 579{
580 struct drm_device *dev = crtc->dev;
581 const intel_limit_t *limit;
582
bad720ff 583 if (HAS_PCH_SPLIT(dev))
1b894b59 584 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 585 else if (IS_G4X(dev)) {
044c7c41 586 limit = intel_g4x_limit(crtc);
f2b115e6 587 } else if (IS_PINEVIEW(dev)) {
2177832f 588 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 589 limit = &intel_limits_pineview_lvds;
2177832f 590 else
f2b115e6 591 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 592 } else if (IS_VALLEYVIEW(dev)) {
593 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
594 limit = &intel_limits_vlv_dac;
595 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
596 limit = &intel_limits_vlv_hdmi;
597 else
598 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 599 } else if (!IS_GEN2(dev)) {
600 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
601 limit = &intel_limits_i9xx_lvds;
602 else
603 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 604 } else {
605 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 606 limit = &intel_limits_i8xx_lvds;
79e53945 607 else
e4b36699 608 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 609 }
610 return limit;
611}
612
f2b115e6
AJ		 613/* m1 is reserved as 0 in Pineview, n is a ring counter */
614static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 615{
2177832f
SL		 616 clock->m = clock->m2 + 2;
617 clock->p = clock->p1 * clock->p2;
618 clock->vco = refclk * clock->m / clock->n;
619 clock->dot = clock->vco / clock->p;
620}
621
622static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
623{
f2b115e6
AJ		 624 if (IS_PINEVIEW(dev)) {
625 pineview_clock(refclk, clock);
2177832f
SL		 626 return;
627 }
79e53945
JB		 628 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
629 clock->p = clock->p1 * clock->p2;
630 clock->vco = refclk * clock->m / (clock->n + 2);
631 clock->dot = clock->vco / clock->p;
632}
633
79e53945
JB		 634/**
635 * Returns whether any output on the specified pipe is of the specified type
636 */
4ef69c7a 637bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 638{
4ef69c7a 639 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 640 struct intel_encoder *encoder;
641
6c2b7c12
DV		 642 for_each_encoder_on_crtc(dev, crtc, encoder)
643 if (encoder->type == type)
4ef69c7a
CW		 644 return true;
645
646 return false;
79e53945
JB		 647}
648
7c04d1d9 649#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 650/**
651 * Returns whether the given set of divisors are valid for a given refclk with
652 * the given connectors.
653 */
654
1b894b59
CW		 655static bool intel_PLL_is_valid(struct drm_device *dev,
656 const intel_limit_t *limit,
657 const intel_clock_t *clock)
79e53945 658{
79e53945 659 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 660 INTELPllInvalid("p1 out of range\n");
79e53945 661 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 662 INTELPllInvalid("p out of range\n");
79e53945 663 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 664 INTELPllInvalid("m2 out of range\n");
79e53945 665 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 666 INTELPllInvalid("m1 out of range\n");
f2b115e6 667 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 668 INTELPllInvalid("m1 <= m2\n");
79e53945 669 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 670 INTELPllInvalid("m out of range\n");
79e53945 671 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 672 INTELPllInvalid("n out of range\n");
79e53945 673 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 674 INTELPllInvalid("vco out of range\n");
79e53945
JB		 675 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
676 * connector, etc., rather than just a single range.
677 */
678 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 679 INTELPllInvalid("dot out of range\n");
79e53945
JB		 680
681 return true;
682}
683
d4906093
ML		 684static bool
685intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 686 int target, int refclk, intel_clock_t *match_clock,
687 intel_clock_t *best_clock)
d4906093 688
79e53945
JB		 689{
690 struct drm_device *dev = crtc->dev;
691 struct drm_i915_private *dev_priv = dev->dev_private;
692 intel_clock_t clock;
79e53945
JB		 693 int err = target;
694
bc5e5718 695 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
832cc28d 696 (I915_READ(LVDS)) != 0) {
79e53945
JB		 697 /*
698 * For LVDS, if the panel is on, just rely on its current
699 * settings for dual-channel. We haven't figured out how to
700 * reliably set up different single/dual channel state, if we
701 * even can.
702 */
b0354385 703 if (is_dual_link_lvds(dev_priv, LVDS))
79e53945
JB		 704 clock.p2 = limit->p2.p2_fast;
705 else
706 clock.p2 = limit->p2.p2_slow;
707 } else {
708 if (target < limit->p2.dot_limit)
709 clock.p2 = limit->p2.p2_slow;
710 else
711 clock.p2 = limit->p2.p2_fast;
712 }
713
0206e353 714 memset(best_clock, 0, sizeof(*best_clock));
79e53945 715
42158660
ZY		 716 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
717 clock.m1++) {
718 for (clock.m2 = limit->m2.min;
719 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 720 /* m1 is always 0 in Pineview */
721 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 722 break;
723 for (clock.n = limit->n.min;
724 clock.n <= limit->n.max; clock.n++) {
725 for (clock.p1 = limit->p1.min;
726 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 727 int this_err;
728
2177832f 729 intel_clock(dev, refclk, &clock);
1b894b59
CW		 730 if (!intel_PLL_is_valid(dev, limit,
731 &clock))
79e53945 732 continue;
cec2f356
SP		 733 if (match_clock &&
734 clock.p != match_clock->p)
735 continue;
79e53945
JB		 736
737 this_err = abs(clock.dot - target);
738 if (this_err < err) {
739 *best_clock = clock;
740 err = this_err;
741 }
742 }
743 }
744 }
745 }
746
747 return (err != target);
748}
749
d4906093
ML		 750static bool
751intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 752 int target, int refclk, intel_clock_t *match_clock,
753 intel_clock_t *best_clock)
d4906093
ML		 754{
755 struct drm_device *dev = crtc->dev;
756 struct drm_i915_private *dev_priv = dev->dev_private;
757 intel_clock_t clock;
758 int max_n;
759 bool found;
6ba770dc
AJ		 760 /* approximately equals target * 0.00585 */
761 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 762 found = false;
763
764 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 765 int lvds_reg;
766
c619eed4 767 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 768 lvds_reg = PCH_LVDS;
769 else
770 lvds_reg = LVDS;
771 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
d4906093
ML		 772 LVDS_CLKB_POWER_UP)
773 clock.p2 = limit->p2.p2_fast;
774 else
775 clock.p2 = limit->p2.p2_slow;
776 } else {
777 if (target < limit->p2.dot_limit)
778 clock.p2 = limit->p2.p2_slow;
779 else
780 clock.p2 = limit->p2.p2_fast;
781 }
782
783 memset(best_clock, 0, sizeof(*best_clock));
784 max_n = limit->n.max;
f77f13e2 785 /* based on hardware requirement, prefer smaller n to precision */
d4906093 786 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 787 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 788 for (clock.m1 = limit->m1.max;
789 clock.m1 >= limit->m1.min; clock.m1--) {
790 for (clock.m2 = limit->m2.max;
791 clock.m2 >= limit->m2.min; clock.m2--) {
792 for (clock.p1 = limit->p1.max;
793 clock.p1 >= limit->p1.min; clock.p1--) {
794 int this_err;
795
2177832f 796 intel_clock(dev, refclk, &clock);
1b894b59
CW		 797 if (!intel_PLL_is_valid(dev, limit,
798 &clock))
d4906093 799 continue;
cec2f356
SP		 800 if (match_clock &&
801 clock.p != match_clock->p)
802 continue;
1b894b59
CW		 803
804 this_err = abs(clock.dot - target);
d4906093
ML		 805 if (this_err < err_most) {
806 *best_clock = clock;
807 err_most = this_err;
808 max_n = clock.n;
809 found = true;
810 }
811 }
812 }
813 }
814 }
2c07245f
ZW		 815 return found;
816}
817
5eb08b69 818static bool
f2b115e6 819intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 820 int target, int refclk, intel_clock_t *match_clock,
821 intel_clock_t *best_clock)
5eb08b69
ZW		 822{
823 struct drm_device *dev = crtc->dev;
824 intel_clock_t clock;
4547668a 825
5eb08b69
ZW		 826 if (target < 200000) {
827 clock.n = 1;
828 clock.p1 = 2;
829 clock.p2 = 10;
830 clock.m1 = 12;
831 clock.m2 = 9;
832 } else {
833 clock.n = 2;
834 clock.p1 = 1;
835 clock.p2 = 10;
836 clock.m1 = 14;
837 clock.m2 = 8;
838 }
839 intel_clock(dev, refclk, &clock);
840 memcpy(best_clock, &clock, sizeof(intel_clock_t));
841 return true;
842}
843
a4fc5ed6
KP		 844/* DisplayPort has only two frequencies, 162MHz and 270MHz */
845static bool
846intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 847 int target, int refclk, intel_clock_t *match_clock,
848 intel_clock_t *best_clock)
a4fc5ed6 849{
5eddb70b
CW		 850 intel_clock_t clock;
851 if (target < 200000) {
852 clock.p1 = 2;
853 clock.p2 = 10;
854 clock.n = 2;
855 clock.m1 = 23;
856 clock.m2 = 8;
857 } else {
858 clock.p1 = 1;
859 clock.p2 = 10;
860 clock.n = 1;
861 clock.m1 = 14;
862 clock.m2 = 2;
863 }
864 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
865 clock.p = (clock.p1 * clock.p2);
866 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
867 clock.vco = 0;
868 memcpy(best_clock, &clock, sizeof(intel_clock_t));
869 return true;
a4fc5ed6 870}
a0c4da24
JB		 871static bool
872intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
873 int target, int refclk, intel_clock_t *match_clock,
874 intel_clock_t *best_clock)
875{
876 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
877 u32 m, n, fastclk;
878 u32 updrate, minupdate, fracbits, p;
879 unsigned long bestppm, ppm, absppm;
880 int dotclk, flag;
881
af447bd3 882 flag = 0;
a0c4da24
JB		 883 dotclk = target * 1000;
884 bestppm = 1000000;
885 ppm = absppm = 0;
886 fastclk = dotclk / (2*100);
887 updrate = 0;
888 minupdate = 19200;
889 fracbits = 1;
890 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
891 bestm1 = bestm2 = bestp1 = bestp2 = 0;
892
893 /* based on hardware requirement, prefer smaller n to precision */
894 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
895 updrate = refclk / n;
896 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
897 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
898 if (p2 > 10)
899 p2 = p2 - 1;
900 p = p1 * p2;
901 /* based on hardware requirement, prefer bigger m1,m2 values */
902 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
903 m2 = (((2*(fastclk * p * n / m1 )) +
904 refclk) / (2*refclk));
905 m = m1 * m2;
906 vco = updrate * m;
907 if (vco >= limit->vco.min && vco < limit->vco.max) {
908 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
909 absppm = (ppm > 0) ? ppm : (-ppm);
910 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
911 bestppm = 0;
912 flag = 1;
913 }
914 if (absppm < bestppm - 10) {
915 bestppm = absppm;
916 flag = 1;
917 }
918 if (flag) {
919 bestn = n;
920 bestm1 = m1;
921 bestm2 = m2;
922 bestp1 = p1;
923 bestp2 = p2;
924 flag = 0;
925 }
926 }
927 }
928 }
929 }
930 }
931 best_clock->n = bestn;
932 best_clock->m1 = bestm1;
933 best_clock->m2 = bestm2;
934 best_clock->p1 = bestp1;
935 best_clock->p2 = bestp2;
936
937 return true;
938}
a4fc5ed6 939
a5c961d1
PZ		 940enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
941 enum pipe pipe)
942{
943 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
944 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
945
946 return intel_crtc->cpu_transcoder;
947}
948
a928d536
PZ		 949static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
950{
951 struct drm_i915_private *dev_priv = dev->dev_private;
952 u32 frame, frame_reg = PIPEFRAME(pipe);
953
954 frame = I915_READ(frame_reg);
955
956 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
957 DRM_DEBUG_KMS("vblank wait timed out\n");
958}
959
9d0498a2
JB		 960/**
961 * intel_wait_for_vblank - wait for vblank on a given pipe
962 * @dev: drm device
963 * @pipe: pipe to wait for
964 *
965 * Wait for vblank to occur on a given pipe. Needed for various bits of
966 * mode setting code.
967 */
968void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 969{
9d0498a2 970 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 971 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 972
a928d536
PZ		 973 if (INTEL_INFO(dev)->gen >= 5) {
974 ironlake_wait_for_vblank(dev, pipe);
975 return;
976 }
977
300387c0
CW		 978 /* Clear existing vblank status. Note this will clear any other
979 * sticky status fields as well.
980 *
981 * This races with i915_driver_irq_handler() with the result
982 * that either function could miss a vblank event. Here it is not
983 * fatal, as we will either wait upon the next vblank interrupt or
984 * timeout. Generally speaking intel_wait_for_vblank() is only
985 * called during modeset at which time the GPU should be idle and
986 * should *not* be performing page flips and thus not waiting on
987 * vblanks...
988 * Currently, the result of us stealing a vblank from the irq
989 * handler is that a single frame will be skipped during swapbuffers.
990 */
991 I915_WRITE(pipestat_reg,
992 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
993
9d0498a2 994 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 995 if (wait_for(I915_READ(pipestat_reg) &
996 PIPE_VBLANK_INTERRUPT_STATUS,
997 50))
9d0498a2
JB		 998 DRM_DEBUG_KMS("vblank wait timed out\n");
999}
1000
ab7ad7f6
KP		 1001/*
1002 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 1003 * @dev: drm device
1004 * @pipe: pipe to wait for
1005 *
1006 * After disabling a pipe, we can't wait for vblank in the usual way,
1007 * spinning on the vblank interrupt status bit, since we won't actually
1008 * see an interrupt when the pipe is disabled.
1009 *
ab7ad7f6
KP		 1010 * On Gen4 and above:
1011 * wait for the pipe register state bit to turn off
1012 *
1013 * Otherwise:
1014 * wait for the display line value to settle (it usually
1015 * ends up stopping at the start of the next frame).
58e10eb9 1016 *
9d0498a2 1017 */
58e10eb9 1018void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 1019{
1020 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 1021 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1022 pipe);
ab7ad7f6
KP		 1023
1024 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1025 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 1026
1027 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1028 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1029 100))
284637d9 1030 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1031 } else {
837ba00f 1032 u32 last_line, line_mask;
58e10eb9 1033 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 1034 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1035
837ba00f
PZ		 1036 if (IS_GEN2(dev))
1037 line_mask = DSL_LINEMASK_GEN2;
1038 else
1039 line_mask = DSL_LINEMASK_GEN3;
1040
ab7ad7f6
KP		 1041 /* Wait for the display line to settle */
1042 do {
837ba00f 1043 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 1044 mdelay(5);
837ba00f 1045 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 1046 time_after(timeout, jiffies));
1047 if (time_after(jiffies, timeout))
284637d9 1048 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1049 }
79e53945
JB		 1050}
1051
b24e7179
JB		 1052static const char *state_string(bool enabled)
1053{
1054 return enabled ? "on" : "off";
1055}
1056
1057/* Only for pre-ILK configs */
1058static void assert_pll(struct drm_i915_private *dev_priv,
1059 enum pipe pipe, bool state)
1060{
1061 int reg;
1062 u32 val;
1063 bool cur_state;
1064
1065 reg = DPLL(pipe);
1066 val = I915_READ(reg);
1067 cur_state = !!(val & DPLL_VCO_ENABLE);
1068 WARN(cur_state != state,
1069 "PLL state assertion failure (expected %s, current %s)\n",
1070 state_string(state), state_string(cur_state));
1071}
1072#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1073#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1074
040484af
JB		 1075/* For ILK+ */
1076static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 1077 struct intel_pch_pll *pll,
1078 struct intel_crtc *crtc,
1079 bool state)
040484af 1080{
040484af
JB		 1081 u32 val;
1082 bool cur_state;
1083
9d82aa17
ED		 1084 if (HAS_PCH_LPT(dev_priv->dev)) {
1085 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1086 return;
1087 }
1088
92b27b08
CW		 1089 if (WARN (!pll,
1090 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 1091 return;
ee7b9f93 1092
92b27b08
CW		 1093 val = I915_READ(pll->pll_reg);
1094 cur_state = !!(val & DPLL_VCO_ENABLE);
1095 WARN(cur_state != state,
1096 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1097 pll->pll_reg, state_string(state), state_string(cur_state), val);
1098
1099 /* Make sure the selected PLL is correctly attached to the transcoder */
1100 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 1101 u32 pch_dpll;
1102
1103 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 1104 cur_state = pll->pll_reg == _PCH_DPLL_B;
1105 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1106 "PLL[%d] not attached to this transcoder %d: %08x\n",
1107 cur_state, crtc->pipe, pch_dpll)) {
1108 cur_state = !!(val >> (4*crtc->pipe + 3));
1109 WARN(cur_state != state,
1110 "PLL[%d] not %s on this transcoder %d: %08x\n",
1111 pll->pll_reg == _PCH_DPLL_B,
1112 state_string(state),
1113 crtc->pipe,
1114 val);
1115 }
d3ccbe86 1116 }
040484af 1117}
92b27b08
CW		 1118#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1119#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 1120
1121static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1122 enum pipe pipe, bool state)
1123{
1124 int reg;
1125 u32 val;
1126 bool cur_state;
ad80a810
PZ		 1127 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1128 pipe);
040484af 1129
bf507ef7
ED		 1130 if (IS_HASWELL(dev_priv->dev)) {
1131 /* On Haswell, DDI is used instead of FDI_TX_CTL */
ad80a810 1132 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1133 val = I915_READ(reg);
ad80a810 1134 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1135 } else {
1136 reg = FDI_TX_CTL(pipe);
1137 val = I915_READ(reg);
1138 cur_state = !!(val & FDI_TX_ENABLE);
1139 }
040484af
JB		 1140 WARN(cur_state != state,
1141 "FDI TX state assertion failure (expected %s, current %s)\n",
1142 state_string(state), state_string(cur_state));
1143}
1144#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1145#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1146
1147static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1148 enum pipe pipe, bool state)
1149{
1150 int reg;
1151 u32 val;
1152 bool cur_state;
1153
59c859d6
ED		 1154 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1155 DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1156 return;
1157 } else {
1158 reg = FDI_RX_CTL(pipe);
1159 val = I915_READ(reg);
1160 cur_state = !!(val & FDI_RX_ENABLE);
1161 }
040484af
JB		 1162 WARN(cur_state != state,
1163 "FDI RX state assertion failure (expected %s, current %s)\n",
1164 state_string(state), state_string(cur_state));
1165}
1166#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1167#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1168
1169static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1170 enum pipe pipe)
1171{
1172 int reg;
1173 u32 val;
1174
1175 /* ILK FDI PLL is always enabled */
1176 if (dev_priv->info->gen == 5)
1177 return;
1178
bf507ef7
ED		 1179 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1180 if (IS_HASWELL(dev_priv->dev))
1181 return;
1182
040484af
JB		 1183 reg = FDI_TX_CTL(pipe);
1184 val = I915_READ(reg);
1185 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1186}
1187
1188static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1189 enum pipe pipe)
1190{
1191 int reg;
1192 u32 val;
1193
59c859d6
ED		 1194 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1195 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1196 return;
1197 }
040484af
JB		 1198 reg = FDI_RX_CTL(pipe);
1199 val = I915_READ(reg);
1200 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1201}
1202
ea0760cf
JB		 1203static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1204 enum pipe pipe)
1205{
1206 int pp_reg, lvds_reg;
1207 u32 val;
1208 enum pipe panel_pipe = PIPE_A;
0de3b485 1209 bool locked = true;
ea0760cf
JB		 1210
1211 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1212 pp_reg = PCH_PP_CONTROL;
1213 lvds_reg = PCH_LVDS;
1214 } else {
1215 pp_reg = PP_CONTROL;
1216 lvds_reg = LVDS;
1217 }
1218
1219 val = I915_READ(pp_reg);
1220 if (!(val & PANEL_POWER_ON) ||
1221 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1222 locked = false;
1223
1224 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1225 panel_pipe = PIPE_B;
1226
1227 WARN(panel_pipe == pipe && locked,
1228 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1229 pipe_name(pipe));
ea0760cf
JB		 1230}
1231
b840d907
JB		 1232void assert_pipe(struct drm_i915_private *dev_priv,
1233 enum pipe pipe, bool state)
b24e7179
JB		 1234{
1235 int reg;
1236 u32 val;
63d7bbe9 1237 bool cur_state;
702e7a56
PZ		 1238 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1239 pipe);
b24e7179 1240
8e636784
DV		 1241 /* if we need the pipe A quirk it must be always on */
1242 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1243 state = true;
1244
702e7a56 1245 reg = PIPECONF(cpu_transcoder);
b24e7179 1246 val = I915_READ(reg);
63d7bbe9
JB		 1247 cur_state = !!(val & PIPECONF_ENABLE);
1248 WARN(cur_state != state,
1249 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1250 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1251}
1252
931872fc
CW		 1253static void assert_plane(struct drm_i915_private *dev_priv,
1254 enum plane plane, bool state)
b24e7179
JB		 1255{
1256 int reg;
1257 u32 val;
931872fc 1258 bool cur_state;
b24e7179
JB		 1259
1260 reg = DSPCNTR(plane);
1261 val = I915_READ(reg);
931872fc
CW		 1262 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1263 WARN(cur_state != state,
1264 "plane %c assertion failure (expected %s, current %s)\n",
1265 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1266}
1267
931872fc
CW		 1268#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1269#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1270
b24e7179
JB		 1271static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1272 enum pipe pipe)
1273{
1274 int reg, i;
1275 u32 val;
1276 int cur_pipe;
1277
19ec1358 1278 /* Planes are fixed to pipes on ILK+ */
28c05794
AJ		 1279 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1280 reg = DSPCNTR(pipe);
1281 val = I915_READ(reg);
1282 WARN((val & DISPLAY_PLANE_ENABLE),
1283 "plane %c assertion failure, should be disabled but not\n",
1284 plane_name(pipe));
19ec1358 1285 return;
28c05794 1286 }
19ec1358 1287
b24e7179
JB		 1288 /* Need to check both planes against the pipe */
1289 for (i = 0; i < 2; i++) {
1290 reg = DSPCNTR(i);
1291 val = I915_READ(reg);
1292 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1293 DISPPLANE_SEL_PIPE_SHIFT;
1294 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1295 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1296 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1297 }
1298}
1299
92f2584a
JB		 1300static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1301{
1302 u32 val;
1303 bool enabled;
1304
9d82aa17
ED		 1305 if (HAS_PCH_LPT(dev_priv->dev)) {
1306 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1307 return;
1308 }
1309
92f2584a
JB		 1310 val = I915_READ(PCH_DREF_CONTROL);
1311 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1312 DREF_SUPERSPREAD_SOURCE_MASK));
1313 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1314}
1315
1316static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1317 enum pipe pipe)
1318{
1319 int reg;
1320 u32 val;
1321 bool enabled;
1322
1323 reg = TRANSCONF(pipe);
1324 val = I915_READ(reg);
1325 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1326 WARN(enabled,
1327 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1328 pipe_name(pipe));
92f2584a
JB		 1329}
1330
4e634389
KP		 1331static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1332 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1333{
1334 if ((val & DP_PORT_EN) == 0)
1335 return false;
1336
1337 if (HAS_PCH_CPT(dev_priv->dev)) {
1338 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1339 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1340 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1341 return false;
1342 } else {
1343 if ((val & DP_PIPE_MASK) != (pipe << 30))
1344 return false;
1345 }
1346 return true;
1347}
1348
1519b995
KP		 1349static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1350 enum pipe pipe, u32 val)
1351{
1352 if ((val & PORT_ENABLE) == 0)
1353 return false;
1354
1355 if (HAS_PCH_CPT(dev_priv->dev)) {
1356 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1357 return false;
1358 } else {
1359 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1360 return false;
1361 }
1362 return true;
1363}
1364
1365static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1366 enum pipe pipe, u32 val)
1367{
1368 if ((val & LVDS_PORT_EN) == 0)
1369 return false;
1370
1371 if (HAS_PCH_CPT(dev_priv->dev)) {
1372 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1373 return false;
1374 } else {
1375 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1376 return false;
1377 }
1378 return true;
1379}
1380
1381static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1382 enum pipe pipe, u32 val)
1383{
1384 if ((val & ADPA_DAC_ENABLE) == 0)
1385 return false;
1386 if (HAS_PCH_CPT(dev_priv->dev)) {
1387 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1388 return false;
1389 } else {
1390 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1391 return false;
1392 }
1393 return true;
1394}
1395
291906f1 1396static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1397 enum pipe pipe, int reg, u32 port_sel)
291906f1 1398{
47a05eca 1399 u32 val = I915_READ(reg);
4e634389 1400 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1401 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1402 reg, pipe_name(pipe));
de9a35ab 1403
75c5da27
DV		 1404 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1405 && (val & DP_PIPEB_SELECT),
de9a35ab 1406 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1407}
1408
1409static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1410 enum pipe pipe, int reg)
1411{
47a05eca 1412 u32 val = I915_READ(reg);
e9a851ed 1413 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1414 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1415 reg, pipe_name(pipe));
de9a35ab 1416
75c5da27
DV		 1417 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1418 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1419 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1420}
1421
1422static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1423 enum pipe pipe)
1424{
1425 int reg;
1426 u32 val;
291906f1 1427
f0575e92
KP		 1428 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1429 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1430 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1431
1432 reg = PCH_ADPA;
1433 val = I915_READ(reg);
e9a851ed 1434 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1435 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1436 pipe_name(pipe));
291906f1
JB		 1437
1438 reg = PCH_LVDS;
1439 val = I915_READ(reg);
e9a851ed 1440 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1441 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1442 pipe_name(pipe));
291906f1
JB		 1443
1444 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1445 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1446 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1447}
1448
63d7bbe9
JB		 1449/**
1450 * intel_enable_pll - enable a PLL
1451 * @dev_priv: i915 private structure
1452 * @pipe: pipe PLL to enable
1453 *
1454 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1455 * make sure the PLL reg is writable first though, since the panel write
1456 * protect mechanism may be enabled.
1457 *
1458 * Note! This is for pre-ILK only.
7434a255
TR		 1459 *
1460 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9 1461 */
a37b9b34 1462static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
63d7bbe9
JB		 1463{
1464 int reg;
1465 u32 val;
1466
1467 /* No really, not for ILK+ */
a0c4da24 1468 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1469
1470 /* PLL is protected by panel, make sure we can write it */
1471 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1472 assert_panel_unlocked(dev_priv, pipe);
1473
1474 reg = DPLL(pipe);
1475 val = I915_READ(reg);
1476 val |= DPLL_VCO_ENABLE;
1477
1478 /* We do this three times for luck */
1479 I915_WRITE(reg, val);
1480 POSTING_READ(reg);
1481 udelay(150); /* wait for warmup */
1482 I915_WRITE(reg, val);
1483 POSTING_READ(reg);
1484 udelay(150); /* wait for warmup */
1485 I915_WRITE(reg, val);
1486 POSTING_READ(reg);
1487 udelay(150); /* wait for warmup */
1488}
1489
1490/**
1491 * intel_disable_pll - disable a PLL
1492 * @dev_priv: i915 private structure
1493 * @pipe: pipe PLL to disable
1494 *
1495 * Disable the PLL for @pipe, making sure the pipe is off first.
1496 *
1497 * Note! This is for pre-ILK only.
1498 */
1499static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1500{
1501 int reg;
1502 u32 val;
1503
1504 /* Don't disable pipe A or pipe A PLLs if needed */
1505 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1506 return;
1507
1508 /* Make sure the pipe isn't still relying on us */
1509 assert_pipe_disabled(dev_priv, pipe);
1510
1511 reg = DPLL(pipe);
1512 val = I915_READ(reg);
1513 val &= ~DPLL_VCO_ENABLE;
1514 I915_WRITE(reg, val);
1515 POSTING_READ(reg);
1516}
1517
a416edef
ED		 1518/* SBI access */
1519static void
1520intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1521{
1522 unsigned long flags;
1523
1524 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
39fb50f6 1525 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1526 100)) {
1527 DRM_ERROR("timeout waiting for SBI to become ready\n");
1528 goto out_unlock;
1529 }
1530
1531 I915_WRITE(SBI_ADDR,
1532 (reg << 16));
1533 I915_WRITE(SBI_DATA,
1534 value);
1535 I915_WRITE(SBI_CTL_STAT,
1536 SBI_BUSY |
1537 SBI_CTL_OP_CRWR);
1538
39fb50f6 1539 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1540 100)) {
1541 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1542 goto out_unlock;
1543 }
1544
1545out_unlock:
1546 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1547}
1548
1549static u32
1550intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1551{
1552 unsigned long flags;
39fb50f6 1553 u32 value = 0;
a416edef
ED		 1554
1555 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
39fb50f6 1556 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1557 100)) {
1558 DRM_ERROR("timeout waiting for SBI to become ready\n");
1559 goto out_unlock;
1560 }
1561
1562 I915_WRITE(SBI_ADDR,
1563 (reg << 16));
1564 I915_WRITE(SBI_CTL_STAT,
1565 SBI_BUSY |
1566 SBI_CTL_OP_CRRD);
1567
39fb50f6 1568 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1569 100)) {
1570 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1571 goto out_unlock;
1572 }
1573
1574 value = I915_READ(SBI_DATA);
1575
1576out_unlock:
1577 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1578 return value;
1579}
1580
92f2584a
JB		 1581/**
1582 * intel_enable_pch_pll - enable PCH PLL
1583 * @dev_priv: i915 private structure
1584 * @pipe: pipe PLL to enable
1585 *
1586 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1587 * drives the transcoder clock.
1588 */
ee7b9f93 1589static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1590{
ee7b9f93 1591 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1592 struct intel_pch_pll *pll;
92f2584a
JB		 1593 int reg;
1594 u32 val;
1595
48da64a8 1596 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1597 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1598 pll = intel_crtc->pch_pll;
1599 if (pll == NULL)
1600 return;
1601
1602 if (WARN_ON(pll->refcount == 0))
1603 return;
ee7b9f93
JB		 1604
1605 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1606 pll->pll_reg, pll->active, pll->on,
1607 intel_crtc->base.base.id);
92f2584a
JB		 1608
1609 /* PCH refclock must be enabled first */
1610 assert_pch_refclk_enabled(dev_priv);
1611
ee7b9f93 1612 if (pll->active++ && pll->on) {
92b27b08 1613 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1614 return;
1615 }
1616
1617 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1618
1619 reg = pll->pll_reg;
92f2584a
JB		 1620 val = I915_READ(reg);
1621 val |= DPLL_VCO_ENABLE;
1622 I915_WRITE(reg, val);
1623 POSTING_READ(reg);
1624 udelay(200);
ee7b9f93
JB		 1625
1626 pll->on = true;
92f2584a
JB		 1627}
1628
ee7b9f93 1629static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1630{
ee7b9f93
JB		 1631 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1632 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1633 int reg;
ee7b9f93 1634 u32 val;
4c609cb8 1635
92f2584a
JB		 1636 /* PCH only available on ILK+ */
1637 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1638 if (pll == NULL)
1639 return;
92f2584a 1640
48da64a8
CW		 1641 if (WARN_ON(pll->refcount == 0))
1642 return;
7a419866 1643
ee7b9f93
JB		 1644 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1645 pll->pll_reg, pll->active, pll->on,
1646 intel_crtc->base.base.id);
7a419866 1647
48da64a8 1648 if (WARN_ON(pll->active == 0)) {
92b27b08 1649 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1650 return;
1651 }
1652
ee7b9f93 1653 if (--pll->active) {
92b27b08 1654 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1655 return;
ee7b9f93
JB		 1656 }
1657
1658 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1659
1660 /* Make sure transcoder isn't still depending on us */
1661 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1662
ee7b9f93 1663 reg = pll->pll_reg;
92f2584a
JB		 1664 val = I915_READ(reg);
1665 val &= ~DPLL_VCO_ENABLE;
1666 I915_WRITE(reg, val);
1667 POSTING_READ(reg);
1668 udelay(200);
ee7b9f93
JB		 1669
1670 pll->on = false;
92f2584a
JB		 1671}
1672
040484af
JB		 1673static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1674 enum pipe pipe)
1675{
1676 int reg;
5f7f726d 1677 u32 val, pipeconf_val;
7c26e5c6 1678 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
040484af
JB		 1679
1680 /* PCH only available on ILK+ */
1681 BUG_ON(dev_priv->info->gen < 5);
1682
1683 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1684 assert_pch_pll_enabled(dev_priv,
1685 to_intel_crtc(crtc)->pch_pll,
1686 to_intel_crtc(crtc));
040484af
JB		 1687
1688 /* FDI must be feeding us bits for PCH ports */
1689 assert_fdi_tx_enabled(dev_priv, pipe);
1690 assert_fdi_rx_enabled(dev_priv, pipe);
1691
59c859d6
ED		 1692 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1693 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1694 return;
1695 }
040484af
JB		 1696 reg = TRANSCONF(pipe);
1697 val = I915_READ(reg);
5f7f726d 1698 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1699
1700 if (HAS_PCH_IBX(dev_priv->dev)) {
1701 /*
1702 * make the BPC in transcoder be consistent with
1703 * that in pipeconf reg.
1704 */
1705 val &= ~PIPE_BPC_MASK;
5f7f726d 1706 val |= pipeconf_val & PIPE_BPC_MASK;
e9bcff5c 1707 }
5f7f726d
PZ		 1708
1709 val &= ~TRANS_INTERLACE_MASK;
1710 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1711 if (HAS_PCH_IBX(dev_priv->dev) &&
1712 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1713 val |= TRANS_LEGACY_INTERLACED_ILK;
1714 else
1715 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1716 else
1717 val |= TRANS_PROGRESSIVE;
1718
040484af
JB		 1719 I915_WRITE(reg, val | TRANS_ENABLE);
1720 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1721 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1722}
1723
1724static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1725 enum pipe pipe)
1726{
1727 int reg;
1728 u32 val;
1729
1730 /* FDI relies on the transcoder */
1731 assert_fdi_tx_disabled(dev_priv, pipe);
1732 assert_fdi_rx_disabled(dev_priv, pipe);
1733
291906f1
JB		 1734 /* Ports must be off as well */
1735 assert_pch_ports_disabled(dev_priv, pipe);
1736
040484af
JB		 1737 reg = TRANSCONF(pipe);
1738 val = I915_READ(reg);
1739 val &= ~TRANS_ENABLE;
1740 I915_WRITE(reg, val);
1741 /* wait for PCH transcoder off, transcoder state */
1742 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1743 DRM_ERROR("failed to disable transcoder %d\n", pipe);
040484af
JB		 1744}
1745
b24e7179 1746/**
309cfea8 1747 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1748 * @dev_priv: i915 private structure
1749 * @pipe: pipe to enable
040484af 1750 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1751 *
1752 * Enable @pipe, making sure that various hardware specific requirements
1753 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1754 *
1755 * @pipe should be %PIPE_A or %PIPE_B.
1756 *
1757 * Will wait until the pipe is actually running (i.e. first vblank) before
1758 * returning.
1759 */
040484af
JB		 1760static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1761 bool pch_port)
b24e7179 1762{
702e7a56
PZ		 1763 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1764 pipe);
b24e7179
JB		 1765 int reg;
1766 u32 val;
1767
1768 /*
1769 * A pipe without a PLL won't actually be able to drive bits from
1770 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1771 * need the check.
1772 */
1773 if (!HAS_PCH_SPLIT(dev_priv->dev))
1774 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1775 else {
1776 if (pch_port) {
1777 /* if driving the PCH, we need FDI enabled */
1778 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1779 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1780 }
1781 /* FIXME: assert CPU port conditions for SNB+ */
1782 }
b24e7179 1783
702e7a56 1784 reg = PIPECONF(cpu_transcoder);
b24e7179 1785 val = I915_READ(reg);
00d70b15
CW		 1786 if (val & PIPECONF_ENABLE)
1787 return;
1788
1789 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1790 intel_wait_for_vblank(dev_priv->dev, pipe);
1791}
1792
1793/**
309cfea8 1794 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1795 * @dev_priv: i915 private structure
1796 * @pipe: pipe to disable
1797 *
1798 * Disable @pipe, making sure that various hardware specific requirements
1799 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1800 *
1801 * @pipe should be %PIPE_A or %PIPE_B.
1802 *
1803 * Will wait until the pipe has shut down before returning.
1804 */
1805static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1806 enum pipe pipe)
1807{
702e7a56
PZ		 1808 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1809 pipe);
b24e7179
JB		 1810 int reg;
1811 u32 val;
1812
1813 /*
1814 * Make sure planes won't keep trying to pump pixels to us,
1815 * or we might hang the display.
1816 */
1817 assert_planes_disabled(dev_priv, pipe);
1818
1819 /* Don't disable pipe A or pipe A PLLs if needed */
1820 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1821 return;
1822
702e7a56 1823 reg = PIPECONF(cpu_transcoder);
b24e7179 1824 val = I915_READ(reg);
00d70b15
CW		 1825 if ((val & PIPECONF_ENABLE) == 0)
1826 return;
1827
1828 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1829 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1830}
1831
d74362c9
KP		 1832/*
1833 * Plane regs are double buffered, going from enabled->disabled needs a
1834 * trigger in order to latch. The display address reg provides this.
1835 */
6f1d69b0 1836void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1837 enum plane plane)
1838{
1839 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1840 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1841}
1842
b24e7179
JB		 1843/**
1844 * intel_enable_plane - enable a display plane on a given pipe
1845 * @dev_priv: i915 private structure
1846 * @plane: plane to enable
1847 * @pipe: pipe being fed
1848 *
1849 * Enable @plane on @pipe, making sure that @pipe is running first.
1850 */
1851static void intel_enable_plane(struct drm_i915_private *dev_priv,
1852 enum plane plane, enum pipe pipe)
1853{
1854 int reg;
1855 u32 val;
1856
1857 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1858 assert_pipe_enabled(dev_priv, pipe);
1859
1860 reg = DSPCNTR(plane);
1861 val = I915_READ(reg);
00d70b15
CW		 1862 if (val & DISPLAY_PLANE_ENABLE)
1863 return;
1864
1865 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1866 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1867 intel_wait_for_vblank(dev_priv->dev, pipe);
1868}
1869
b24e7179
JB		 1870/**
1871 * intel_disable_plane - disable a display plane
1872 * @dev_priv: i915 private structure
1873 * @plane: plane to disable
1874 * @pipe: pipe consuming the data
1875 *
1876 * Disable @plane; should be an independent operation.
1877 */
1878static void intel_disable_plane(struct drm_i915_private *dev_priv,
1879 enum plane plane, enum pipe pipe)
1880{
1881 int reg;
1882 u32 val;
1883
1884 reg = DSPCNTR(plane);
1885 val = I915_READ(reg);
00d70b15
CW		 1886 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1887 return;
1888
1889 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1890 intel_flush_display_plane(dev_priv, plane);
1891 intel_wait_for_vblank(dev_priv->dev, pipe);
1892}
1893
127bd2ac 1894int
48b956c5 1895intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1896 struct drm_i915_gem_object *obj,
919926ae 1897 struct intel_ring_buffer *pipelined)
6b95a207 1898{
ce453d81 1899 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1900 u32 alignment;
1901 int ret;
1902
05394f39 1903 switch (obj->tiling_mode) {
6b95a207 1904 case I915_TILING_NONE:
534843da
CW		 1905 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1906 alignment = 128 * 1024;
a6c45cf0 1907 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1908 alignment = 4 * 1024;
1909 else
1910 alignment = 64 * 1024;
6b95a207
KH		 1911 break;
1912 case I915_TILING_X:
1913 /* pin() will align the object as required by fence */
1914 alignment = 0;
1915 break;
1916 case I915_TILING_Y:
1917 /* FIXME: Is this true? */
1918 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1919 return -EINVAL;
1920 default:
1921 BUG();
1922 }
1923
ce453d81 1924 dev_priv->mm.interruptible = false;
2da3b9b9 1925 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1926 if (ret)
ce453d81 1927 goto err_interruptible;
6b95a207
KH		 1928
1929 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1930 * fence, whereas 965+ only requires a fence if using
1931 * framebuffer compression. For simplicity, we always install
1932 * a fence as the cost is not that onerous.
1933 */
06d98131 1934 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1935 if (ret)
1936 goto err_unpin;
1690e1eb 1937
9a5a53b3 1938 i915_gem_object_pin_fence(obj);
6b95a207 1939
ce453d81 1940 dev_priv->mm.interruptible = true;
6b95a207 1941 return 0;
48b956c5
CW		 1942
1943err_unpin:
1944 i915_gem_object_unpin(obj);
ce453d81
CW		 1945err_interruptible:
1946 dev_priv->mm.interruptible = true;
48b956c5 1947 return ret;
6b95a207
KH		 1948}
1949
1690e1eb
CW		 1950void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1951{
1952 i915_gem_object_unpin_fence(obj);
1953 i915_gem_object_unpin(obj);
1954}
1955
c2c75131
DV		 1956/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1957 * is assumed to be a power-of-two. */
5a35e99e
DL		 1958unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
1959 unsigned int bpp,
1960 unsigned int pitch)
c2c75131
DV		 1961{
1962 int tile_rows, tiles;
1963
1964 tile_rows = *y / 8;
1965 *y %= 8;
1966 tiles = *x / (512/bpp);
1967 *x %= 512/bpp;
1968
1969 return tile_rows * pitch * 8 + tiles * 4096;
1970}
1971
17638cd6
JB		 1972static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1973 int x, int y)
81255565
JB		 1974{
1975 struct drm_device *dev = crtc->dev;
1976 struct drm_i915_private *dev_priv = dev->dev_private;
1977 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1978 struct intel_framebuffer *intel_fb;
05394f39 1979 struct drm_i915_gem_object *obj;
81255565 1980 int plane = intel_crtc->plane;
e506a0c6 1981 unsigned long linear_offset;
81255565 1982 u32 dspcntr;
5eddb70b 1983 u32 reg;
81255565
JB		 1984
1985 switch (plane) {
1986 case 0:
1987 case 1:
1988 break;
1989 default:
1990 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1991 return -EINVAL;
1992 }
1993
1994 intel_fb = to_intel_framebuffer(fb);
1995 obj = intel_fb->obj;
81255565 1996
5eddb70b
CW		 1997 reg = DSPCNTR(plane);
1998 dspcntr = I915_READ(reg);
81255565
JB		 1999 /* Mask out pixel format bits in case we change it */
2000 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2001 switch (fb->bits_per_pixel) {
2002 case 8:
2003 dspcntr |= DISPPLANE_8BPP;
2004 break;
2005 case 16:
2006 if (fb->depth == 15)
2007 dspcntr |= DISPPLANE_15_16BPP;
2008 else
2009 dspcntr |= DISPPLANE_16BPP;
2010 break;
2011 case 24:
2012 case 32:
2013 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2014 break;
2015 default:
17638cd6 2016 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
81255565
JB		 2017 return -EINVAL;
2018 }
a6c45cf0 2019 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2020 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2021 dspcntr |= DISPPLANE_TILED;
2022 else
2023 dspcntr &= ~DISPPLANE_TILED;
2024 }
2025
5eddb70b 2026 I915_WRITE(reg, dspcntr);
81255565 2027
e506a0c6 2028 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2029
c2c75131
DV		 2030 if (INTEL_INFO(dev)->gen >= 4) {
2031 intel_crtc->dspaddr_offset =
5a35e99e
DL		 2032 intel_gen4_compute_offset_xtiled(&x, &y,
2033 fb->bits_per_pixel / 8,
2034 fb->pitches[0]);
c2c75131
DV		 2035 linear_offset -= intel_crtc->dspaddr_offset;
2036 } else {
e506a0c6 2037 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2038 }
e506a0c6
DV		 2039
2040 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2041 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2042 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2043 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 2044 I915_MODIFY_DISPBASE(DSPSURF(plane),
2045 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 2046 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2047 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2048 } else
e506a0c6 2049 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2050 POSTING_READ(reg);
81255565 2051
17638cd6
JB		 2052 return 0;
2053}
2054
2055static int ironlake_update_plane(struct drm_crtc *crtc,
2056 struct drm_framebuffer *fb, int x, int y)
2057{
2058 struct drm_device *dev = crtc->dev;
2059 struct drm_i915_private *dev_priv = dev->dev_private;
2060 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2061 struct intel_framebuffer *intel_fb;
2062 struct drm_i915_gem_object *obj;
2063 int plane = intel_crtc->plane;
e506a0c6 2064 unsigned long linear_offset;
17638cd6
JB		 2065 u32 dspcntr;
2066 u32 reg;
2067
2068 switch (plane) {
2069 case 0:
2070 case 1:
27f8227b 2071 case 2:
17638cd6
JB		 2072 break;
2073 default:
2074 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2075 return -EINVAL;
2076 }
2077
2078 intel_fb = to_intel_framebuffer(fb);
2079 obj = intel_fb->obj;
2080
2081 reg = DSPCNTR(plane);
2082 dspcntr = I915_READ(reg);
2083 /* Mask out pixel format bits in case we change it */
2084 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2085 switch (fb->bits_per_pixel) {
2086 case 8:
2087 dspcntr |= DISPPLANE_8BPP;
2088 break;
2089 case 16:
2090 if (fb->depth != 16)
2091 return -EINVAL;
2092
2093 dspcntr |= DISPPLANE_16BPP;
2094 break;
2095 case 24:
2096 case 32:
2097 if (fb->depth == 24)
2098 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2099 else if (fb->depth == 30)
2100 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2101 else
2102 return -EINVAL;
2103 break;
2104 default:
2105 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2106 return -EINVAL;
2107 }
2108
2109 if (obj->tiling_mode != I915_TILING_NONE)
2110 dspcntr |= DISPPLANE_TILED;
2111 else
2112 dspcntr &= ~DISPPLANE_TILED;
2113
2114 /* must disable */
2115 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2116
2117 I915_WRITE(reg, dspcntr);
2118
e506a0c6 2119 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2120 intel_crtc->dspaddr_offset =
5a35e99e
DL		 2121 intel_gen4_compute_offset_xtiled(&x, &y,
2122 fb->bits_per_pixel / 8,
2123 fb->pitches[0]);
c2c75131 2124 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2125
e506a0c6
DV		 2126 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2127 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2128 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2129 I915_MODIFY_DISPBASE(DSPSURF(plane),
2130 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2131 if (IS_HASWELL(dev)) {
2132 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2133 } else {
2134 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2135 I915_WRITE(DSPLINOFF(plane), linear_offset);
2136 }
17638cd6
JB		 2137 POSTING_READ(reg);
2138
2139 return 0;
2140}
2141
2142/* Assume fb object is pinned & idle & fenced and just update base pointers */
2143static int
2144intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2145 int x, int y, enum mode_set_atomic state)
2146{
2147 struct drm_device *dev = crtc->dev;
2148 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2149
6b8e6ed0
CW		 2150 if (dev_priv->display.disable_fbc)
2151 dev_priv->display.disable_fbc(dev);
3dec0095 2152 intel_increase_pllclock(crtc);
81255565 2153
6b8e6ed0 2154 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2155}
2156
14667a4b
CW		 2157static int
2158intel_finish_fb(struct drm_framebuffer *old_fb)
2159{
2160 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2161 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2162 bool was_interruptible = dev_priv->mm.interruptible;
2163 int ret;
2164
2165 wait_event(dev_priv->pending_flip_queue,
2166 atomic_read(&dev_priv->mm.wedged) ||
2167 atomic_read(&obj->pending_flip) == 0);
2168
2169 /* Big Hammer, we also need to ensure that any pending
2170 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2171 * current scanout is retired before unpinning the old
2172 * framebuffer.
2173 *
2174 * This should only fail upon a hung GPU, in which case we
2175 * can safely continue.
2176 */
2177 dev_priv->mm.interruptible = false;
2178 ret = i915_gem_object_finish_gpu(obj);
2179 dev_priv->mm.interruptible = was_interruptible;
2180
2181 return ret;
2182}
2183
5c3b82e2 2184static int
3c4fdcfb 2185intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2186 struct drm_framebuffer *fb)
79e53945
JB		 2187{
2188 struct drm_device *dev = crtc->dev;
6b8e6ed0 2189 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 2190 struct drm_i915_master_private *master_priv;
2191 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2192 struct drm_framebuffer *old_fb;
5c3b82e2 2193 int ret;
79e53945
JB		 2194
2195 /* no fb bound */
94352cf9 2196 if (!fb) {
a5071c2f 2197 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2198 return 0;
2199 }
2200
5826eca5
ED		 2201 if(intel_crtc->plane > dev_priv->num_pipe) {
2202 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2203 intel_crtc->plane,
2204 dev_priv->num_pipe);
5c3b82e2 2205 return -EINVAL;
79e53945
JB		 2206 }
2207
5c3b82e2 2208 mutex_lock(&dev->struct_mutex);
265db958 2209 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2210 to_intel_framebuffer(fb)->obj,
919926ae 2211 NULL);
5c3b82e2
CW		 2212 if (ret != 0) {
2213 mutex_unlock(&dev->struct_mutex);
a5071c2f 2214 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2215 return ret;
2216 }
79e53945 2217
94352cf9
DV		 2218 if (crtc->fb)
2219 intel_finish_fb(crtc->fb);
265db958 2220
94352cf9 2221 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2222 if (ret) {
94352cf9 2223 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2224 mutex_unlock(&dev->struct_mutex);
a5071c2f 2225 DRM_ERROR("failed to update base address\n");
4e6cfefc 2226 return ret;
79e53945 2227 }
3c4fdcfb 2228
94352cf9
DV		 2229 old_fb = crtc->fb;
2230 crtc->fb = fb;
6c4c86f5
DV		 2231 crtc->x = x;
2232 crtc->y = y;
94352cf9 2233
b7f1de28
CW		 2234 if (old_fb) {
2235 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2236 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2237 }
652c393a 2238
6b8e6ed0 2239 intel_update_fbc(dev);
5c3b82e2 2240 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 2241
2242 if (!dev->primary->master)
5c3b82e2 2243 return 0;
79e53945
JB		 2244
2245 master_priv = dev->primary->master->driver_priv;
2246 if (!master_priv->sarea_priv)
5c3b82e2 2247 return 0;
79e53945 2248
265db958 2249 if (intel_crtc->pipe) {
79e53945
JB		 2250 master_priv->sarea_priv->pipeB_x = x;
2251 master_priv->sarea_priv->pipeB_y = y;
5c3b82e2
CW		 2252 } else {
2253 master_priv->sarea_priv->pipeA_x = x;
2254 master_priv->sarea_priv->pipeA_y = y;
79e53945 2255 }
5c3b82e2
CW		 2256
2257 return 0;
79e53945
JB		 2258}
2259
5eddb70b 2260static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
32f9d658
ZW		 2261{
2262 struct drm_device *dev = crtc->dev;
2263 struct drm_i915_private *dev_priv = dev->dev_private;
2264 u32 dpa_ctl;
2265
28c97730 2266 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
32f9d658
ZW		 2267 dpa_ctl = I915_READ(DP_A);
2268 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2269
2270 if (clock < 200000) {
2271 u32 temp;
2272 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2273 /* workaround for 160Mhz:
2274 1) program 0x4600c bits 15:0 = 0x8124
2275 2) program 0x46010 bit 0 = 1
2276 3) program 0x46034 bit 24 = 1
2277 4) program 0x64000 bit 14 = 1
2278 */
2279 temp = I915_READ(0x4600c);
2280 temp &= 0xffff0000;
2281 I915_WRITE(0x4600c, temp | 0x8124);
2282
2283 temp = I915_READ(0x46010);
2284 I915_WRITE(0x46010, temp | 1);
2285
2286 temp = I915_READ(0x46034);
2287 I915_WRITE(0x46034, temp | (1 << 24));
2288 } else {
2289 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2290 }
2291 I915_WRITE(DP_A, dpa_ctl);
2292
5eddb70b 2293 POSTING_READ(DP_A);
32f9d658
ZW		 2294 udelay(500);
2295}
2296
5e84e1a4
ZW		 2297static void intel_fdi_normal_train(struct drm_crtc *crtc)
2298{
2299 struct drm_device *dev = crtc->dev;
2300 struct drm_i915_private *dev_priv = dev->dev_private;
2301 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2302 int pipe = intel_crtc->pipe;
2303 u32 reg, temp;
2304
2305 /* enable normal train */
2306 reg = FDI_TX_CTL(pipe);
2307 temp = I915_READ(reg);
61e499bf 2308 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2309 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2310 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2311 } else {
2312 temp &= ~FDI_LINK_TRAIN_NONE;
2313 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2314 }
5e84e1a4
ZW		 2315 I915_WRITE(reg, temp);
2316
2317 reg = FDI_RX_CTL(pipe);
2318 temp = I915_READ(reg);
2319 if (HAS_PCH_CPT(dev)) {
2320 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2321 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2322 } else {
2323 temp &= ~FDI_LINK_TRAIN_NONE;
2324 temp |= FDI_LINK_TRAIN_NONE;
2325 }
2326 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2327
2328 /* wait one idle pattern time */
2329 POSTING_READ(reg);
2330 udelay(1000);
357555c0
JB		 2331
2332 /* IVB wants error correction enabled */
2333 if (IS_IVYBRIDGE(dev))
2334 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2335 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2336}
2337
291427f5
JB		 2338static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2339{
2340 struct drm_i915_private *dev_priv = dev->dev_private;
2341 u32 flags = I915_READ(SOUTH_CHICKEN1);
2342
2343 flags |= FDI_PHASE_SYNC_OVR(pipe);
2344 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2345 flags |= FDI_PHASE_SYNC_EN(pipe);
2346 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2347 POSTING_READ(SOUTH_CHICKEN1);
2348}
2349
01a415fd
DV		 2350static void ivb_modeset_global_resources(struct drm_device *dev)
2351{
2352 struct drm_i915_private *dev_priv = dev->dev_private;
2353 struct intel_crtc *pipe_B_crtc =
2354 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2355 struct intel_crtc *pipe_C_crtc =
2356 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2357 uint32_t temp;
2358
2359 /* When everything is off disable fdi C so that we could enable fdi B
2360 * with all lanes. XXX: This misses the case where a pipe is not using
2361 * any pch resources and so doesn't need any fdi lanes. */
2362 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2363 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2364 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2365
2366 temp = I915_READ(SOUTH_CHICKEN1);
2367 temp &= ~FDI_BC_BIFURCATION_SELECT;
2368 DRM_DEBUG_KMS("disabling fdi C rx\n");
2369 I915_WRITE(SOUTH_CHICKEN1, temp);
2370 }
2371}
2372
8db9d77b
ZW		 2373/* The FDI link training functions for ILK/Ibexpeak. */
2374static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2375{
2376 struct drm_device *dev = crtc->dev;
2377 struct drm_i915_private *dev_priv = dev->dev_private;
2378 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2379 int pipe = intel_crtc->pipe;
0fc932b8 2380 int plane = intel_crtc->plane;
5eddb70b 2381 u32 reg, temp, tries;
8db9d77b 2382
0fc932b8
JB		 2383 /* FDI needs bits from pipe & plane first */
2384 assert_pipe_enabled(dev_priv, pipe);
2385 assert_plane_enabled(dev_priv, plane);
2386
e1a44743
AJ		 2387 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2388 for train result */
5eddb70b
CW		 2389 reg = FDI_RX_IMR(pipe);
2390 temp = I915_READ(reg);
e1a44743
AJ		 2391 temp &= ~FDI_RX_SYMBOL_LOCK;
2392 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2393 I915_WRITE(reg, temp);
2394 I915_READ(reg);
e1a44743
AJ		 2395 udelay(150);
2396
8db9d77b 2397 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2398 reg = FDI_TX_CTL(pipe);
2399 temp = I915_READ(reg);
77ffb597
AJ		 2400 temp &= ~(7 << 19);
2401 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2402 temp &= ~FDI_LINK_TRAIN_NONE;
2403 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2404 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2405
5eddb70b
CW		 2406 reg = FDI_RX_CTL(pipe);
2407 temp = I915_READ(reg);
8db9d77b
ZW		 2408 temp &= ~FDI_LINK_TRAIN_NONE;
2409 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2410 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2411
2412 POSTING_READ(reg);
8db9d77b
ZW		 2413 udelay(150);
2414
5b2adf89 2415 /* Ironlake workaround, enable clock pointer after FDI enable*/
6f06ce18
JB		 2416 if (HAS_PCH_IBX(dev)) {
2417 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2418 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2419 FDI_RX_PHASE_SYNC_POINTER_EN);
2420 }
5b2adf89 2421
5eddb70b 2422 reg = FDI_RX_IIR(pipe);
e1a44743 2423 for (tries = 0; tries < 5; tries++) {
5eddb70b 2424 temp = I915_READ(reg);
8db9d77b
ZW		 2425 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2426
2427 if ((temp & FDI_RX_BIT_LOCK)) {
2428 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2429 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2430 break;
2431 }
8db9d77b 2432 }
e1a44743 2433 if (tries == 5)
5eddb70b 2434 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2435
2436 /* Train 2 */
5eddb70b
CW		 2437 reg = FDI_TX_CTL(pipe);
2438 temp = I915_READ(reg);
8db9d77b
ZW		 2439 temp &= ~FDI_LINK_TRAIN_NONE;
2440 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2441 I915_WRITE(reg, temp);
8db9d77b 2442
5eddb70b
CW		 2443 reg = FDI_RX_CTL(pipe);
2444 temp = I915_READ(reg);
8db9d77b
ZW		 2445 temp &= ~FDI_LINK_TRAIN_NONE;
2446 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2447 I915_WRITE(reg, temp);
8db9d77b 2448
5eddb70b
CW		 2449 POSTING_READ(reg);
2450 udelay(150);
8db9d77b 2451
5eddb70b 2452 reg = FDI_RX_IIR(pipe);
e1a44743 2453 for (tries = 0; tries < 5; tries++) {
5eddb70b 2454 temp = I915_READ(reg);
8db9d77b
ZW		 2455 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2456
2457 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2458 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2459 DRM_DEBUG_KMS("FDI train 2 done.\n");
2460 break;
2461 }
8db9d77b 2462 }
e1a44743 2463 if (tries == 5)
5eddb70b 2464 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2465
2466 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2467
8db9d77b
ZW		 2468}
2469
0206e353 2470static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2471 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2472 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2473 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2474 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2475};
2476
2477/* The FDI link training functions for SNB/Cougarpoint. */
2478static void gen6_fdi_link_train(struct drm_crtc *crtc)
2479{
2480 struct drm_device *dev = crtc->dev;
2481 struct drm_i915_private *dev_priv = dev->dev_private;
2482 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2483 int pipe = intel_crtc->pipe;
fa37d39e 2484 u32 reg, temp, i, retry;
8db9d77b 2485
e1a44743
AJ		 2486 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2487 for train result */
5eddb70b
CW		 2488 reg = FDI_RX_IMR(pipe);
2489 temp = I915_READ(reg);
e1a44743
AJ		 2490 temp &= ~FDI_RX_SYMBOL_LOCK;
2491 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2492 I915_WRITE(reg, temp);
2493
2494 POSTING_READ(reg);
e1a44743
AJ		 2495 udelay(150);
2496
8db9d77b 2497 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2498 reg = FDI_TX_CTL(pipe);
2499 temp = I915_READ(reg);
77ffb597
AJ		 2500 temp &= ~(7 << 19);
2501 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2502 temp &= ~FDI_LINK_TRAIN_NONE;
2503 temp |= FDI_LINK_TRAIN_PATTERN_1;
2504 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2505 /* SNB-B */
2506 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2507 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2508
d74cf324
DV		 2509 I915_WRITE(FDI_RX_MISC(pipe),
2510 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2511
5eddb70b
CW		 2512 reg = FDI_RX_CTL(pipe);
2513 temp = I915_READ(reg);
8db9d77b
ZW		 2514 if (HAS_PCH_CPT(dev)) {
2515 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2516 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2517 } else {
2518 temp &= ~FDI_LINK_TRAIN_NONE;
2519 temp |= FDI_LINK_TRAIN_PATTERN_1;
2520 }
5eddb70b
CW		 2521 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2522
2523 POSTING_READ(reg);
8db9d77b
ZW		 2524 udelay(150);
2525
291427f5
JB		 2526 if (HAS_PCH_CPT(dev))
2527 cpt_phase_pointer_enable(dev, pipe);
2528
0206e353 2529 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2530 reg = FDI_TX_CTL(pipe);
2531 temp = I915_READ(reg);
8db9d77b
ZW		 2532 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2533 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2534 I915_WRITE(reg, temp);
2535
2536 POSTING_READ(reg);
8db9d77b
ZW		 2537 udelay(500);
2538
fa37d39e
SP		 2539 for (retry = 0; retry < 5; retry++) {
2540 reg = FDI_RX_IIR(pipe);
2541 temp = I915_READ(reg);
2542 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2543 if (temp & FDI_RX_BIT_LOCK) {
2544 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2545 DRM_DEBUG_KMS("FDI train 1 done.\n");
2546 break;
2547 }
2548 udelay(50);
8db9d77b 2549 }
fa37d39e
SP		 2550 if (retry < 5)
2551 break;
8db9d77b
ZW		 2552 }
2553 if (i == 4)
5eddb70b 2554 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2555
2556 /* Train 2 */
5eddb70b
CW		 2557 reg = FDI_TX_CTL(pipe);
2558 temp = I915_READ(reg);
8db9d77b
ZW		 2559 temp &= ~FDI_LINK_TRAIN_NONE;
2560 temp |= FDI_LINK_TRAIN_PATTERN_2;
2561 if (IS_GEN6(dev)) {
2562 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2563 /* SNB-B */
2564 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2565 }
5eddb70b 2566 I915_WRITE(reg, temp);
8db9d77b 2567
5eddb70b
CW		 2568 reg = FDI_RX_CTL(pipe);
2569 temp = I915_READ(reg);
8db9d77b
ZW		 2570 if (HAS_PCH_CPT(dev)) {
2571 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2572 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2573 } else {
2574 temp &= ~FDI_LINK_TRAIN_NONE;
2575 temp |= FDI_LINK_TRAIN_PATTERN_2;
2576 }
5eddb70b
CW		 2577 I915_WRITE(reg, temp);
2578
2579 POSTING_READ(reg);
8db9d77b
ZW		 2580 udelay(150);
2581
0206e353 2582 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2583 reg = FDI_TX_CTL(pipe);
2584 temp = I915_READ(reg);
8db9d77b
ZW		 2585 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2586 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2587 I915_WRITE(reg, temp);
2588
2589 POSTING_READ(reg);
8db9d77b
ZW		 2590 udelay(500);
2591
fa37d39e
SP		 2592 for (retry = 0; retry < 5; retry++) {
2593 reg = FDI_RX_IIR(pipe);
2594 temp = I915_READ(reg);
2595 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2596 if (temp & FDI_RX_SYMBOL_LOCK) {
2597 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2598 DRM_DEBUG_KMS("FDI train 2 done.\n");
2599 break;
2600 }
2601 udelay(50);
8db9d77b 2602 }
fa37d39e
SP		 2603 if (retry < 5)
2604 break;
8db9d77b
ZW		 2605 }
2606 if (i == 4)
5eddb70b 2607 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2608
2609 DRM_DEBUG_KMS("FDI train done.\n");
2610}
2611
357555c0
JB		 2612/* Manual link training for Ivy Bridge A0 parts */
2613static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2614{
2615 struct drm_device *dev = crtc->dev;
2616 struct drm_i915_private *dev_priv = dev->dev_private;
2617 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2618 int pipe = intel_crtc->pipe;
2619 u32 reg, temp, i;
2620
2621 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2622 for train result */
2623 reg = FDI_RX_IMR(pipe);
2624 temp = I915_READ(reg);
2625 temp &= ~FDI_RX_SYMBOL_LOCK;
2626 temp &= ~FDI_RX_BIT_LOCK;
2627 I915_WRITE(reg, temp);
2628
2629 POSTING_READ(reg);
2630 udelay(150);
2631
01a415fd
DV		 2632 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2633 I915_READ(FDI_RX_IIR(pipe)));
2634
357555c0
JB		 2635 /* enable CPU FDI TX and PCH FDI RX */
2636 reg = FDI_TX_CTL(pipe);
2637 temp = I915_READ(reg);
2638 temp &= ~(7 << 19);
2639 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2640 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2641 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2642 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2643 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2644 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2645 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2646
d74cf324
DV		 2647 I915_WRITE(FDI_RX_MISC(pipe),
2648 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2649
357555c0
JB		 2650 reg = FDI_RX_CTL(pipe);
2651 temp = I915_READ(reg);
2652 temp &= ~FDI_LINK_TRAIN_AUTO;
2653 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2654 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2655 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2656 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2657
2658 POSTING_READ(reg);
2659 udelay(150);
2660
291427f5
JB		 2661 if (HAS_PCH_CPT(dev))
2662 cpt_phase_pointer_enable(dev, pipe);
2663
0206e353 2664 for (i = 0; i < 4; i++) {
357555c0
JB		 2665 reg = FDI_TX_CTL(pipe);
2666 temp = I915_READ(reg);
2667 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2668 temp |= snb_b_fdi_train_param[i];
2669 I915_WRITE(reg, temp);
2670
2671 POSTING_READ(reg);
2672 udelay(500);
2673
2674 reg = FDI_RX_IIR(pipe);
2675 temp = I915_READ(reg);
2676 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2677
2678 if (temp & FDI_RX_BIT_LOCK ||
2679 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2680 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2681 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2682 break;
2683 }
2684 }
2685 if (i == 4)
2686 DRM_ERROR("FDI train 1 fail!\n");
2687
2688 /* Train 2 */
2689 reg = FDI_TX_CTL(pipe);
2690 temp = I915_READ(reg);
2691 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2692 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2693 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2694 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2695 I915_WRITE(reg, temp);
2696
2697 reg = FDI_RX_CTL(pipe);
2698 temp = I915_READ(reg);
2699 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2700 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2701 I915_WRITE(reg, temp);
2702
2703 POSTING_READ(reg);
2704 udelay(150);
2705
0206e353 2706 for (i = 0; i < 4; i++) {
357555c0
JB		 2707 reg = FDI_TX_CTL(pipe);
2708 temp = I915_READ(reg);
2709 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2710 temp |= snb_b_fdi_train_param[i];
2711 I915_WRITE(reg, temp);
2712
2713 POSTING_READ(reg);
2714 udelay(500);
2715
2716 reg = FDI_RX_IIR(pipe);
2717 temp = I915_READ(reg);
2718 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2719
2720 if (temp & FDI_RX_SYMBOL_LOCK) {
2721 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2722 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2723 break;
2724 }
2725 }
2726 if (i == 4)
2727 DRM_ERROR("FDI train 2 fail!\n");
2728
2729 DRM_DEBUG_KMS("FDI train done.\n");
2730}
2731
88cefb6c 2732static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2733{
88cefb6c 2734 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2735 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2736 int pipe = intel_crtc->pipe;
5eddb70b 2737 u32 reg, temp;
79e53945 2738
c64e311e 2739
c98e9dcf 2740 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2741 reg = FDI_RX_CTL(pipe);
2742 temp = I915_READ(reg);
2743 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2744 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW		 2745 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2746 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2747
2748 POSTING_READ(reg);
c98e9dcf
JB		 2749 udelay(200);
2750
2751 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2752 temp = I915_READ(reg);
2753 I915_WRITE(reg, temp | FDI_PCDCLK);
2754
2755 POSTING_READ(reg);
c98e9dcf
JB		 2756 udelay(200);
2757
bf507ef7
ED		 2758 /* On Haswell, the PLL configuration for ports and pipes is handled
2759 * separately, as part of DDI setup */
2760 if (!IS_HASWELL(dev)) {
2761 /* Enable CPU FDI TX PLL, always on for Ironlake */
2762 reg = FDI_TX_CTL(pipe);
2763 temp = I915_READ(reg);
2764 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2765 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2766
bf507ef7
ED		 2767 POSTING_READ(reg);
2768 udelay(100);
2769 }
6be4a607 2770 }
0e23b99d
JB		 2771}
2772
88cefb6c
DV		 2773static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2774{
2775 struct drm_device *dev = intel_crtc->base.dev;
2776 struct drm_i915_private *dev_priv = dev->dev_private;
2777 int pipe = intel_crtc->pipe;
2778 u32 reg, temp;
2779
2780 /* Switch from PCDclk to Rawclk */
2781 reg = FDI_RX_CTL(pipe);
2782 temp = I915_READ(reg);
2783 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2784
2785 /* Disable CPU FDI TX PLL */
2786 reg = FDI_TX_CTL(pipe);
2787 temp = I915_READ(reg);
2788 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2789
2790 POSTING_READ(reg);
2791 udelay(100);
2792
2793 reg = FDI_RX_CTL(pipe);
2794 temp = I915_READ(reg);
2795 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2796
2797 /* Wait for the clocks to turn off. */
2798 POSTING_READ(reg);
2799 udelay(100);
2800}
2801
291427f5
JB		 2802static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2803{
2804 struct drm_i915_private *dev_priv = dev->dev_private;
2805 u32 flags = I915_READ(SOUTH_CHICKEN1);
2806
2807 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2808 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2809 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2810 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2811 POSTING_READ(SOUTH_CHICKEN1);
2812}
0fc932b8
JB		 2813static void ironlake_fdi_disable(struct drm_crtc *crtc)
2814{
2815 struct drm_device *dev = crtc->dev;
2816 struct drm_i915_private *dev_priv = dev->dev_private;
2817 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2818 int pipe = intel_crtc->pipe;
2819 u32 reg, temp;
2820
2821 /* disable CPU FDI tx and PCH FDI rx */
2822 reg = FDI_TX_CTL(pipe);
2823 temp = I915_READ(reg);
2824 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2825 POSTING_READ(reg);
2826
2827 reg = FDI_RX_CTL(pipe);
2828 temp = I915_READ(reg);
2829 temp &= ~(0x7 << 16);
2830 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2831 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2832
2833 POSTING_READ(reg);
2834 udelay(100);
2835
2836 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2837 if (HAS_PCH_IBX(dev)) {
2838 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 2839 I915_WRITE(FDI_RX_CHICKEN(pipe),
2840 I915_READ(FDI_RX_CHICKEN(pipe) &
6f06ce18 2841 ~FDI_RX_PHASE_SYNC_POINTER_EN));
291427f5
JB		 2842 } else if (HAS_PCH_CPT(dev)) {
2843 cpt_phase_pointer_disable(dev, pipe);
6f06ce18 2844 }
0fc932b8
JB		 2845
2846 /* still set train pattern 1 */
2847 reg = FDI_TX_CTL(pipe);
2848 temp = I915_READ(reg);
2849 temp &= ~FDI_LINK_TRAIN_NONE;
2850 temp |= FDI_LINK_TRAIN_PATTERN_1;
2851 I915_WRITE(reg, temp);
2852
2853 reg = FDI_RX_CTL(pipe);
2854 temp = I915_READ(reg);
2855 if (HAS_PCH_CPT(dev)) {
2856 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2857 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2858 } else {
2859 temp &= ~FDI_LINK_TRAIN_NONE;
2860 temp |= FDI_LINK_TRAIN_PATTERN_1;
2861 }
2862 /* BPC in FDI rx is consistent with that in PIPECONF */
2863 temp &= ~(0x07 << 16);
2864 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2865 I915_WRITE(reg, temp);
2866
2867 POSTING_READ(reg);
2868 udelay(100);
2869}
2870
5bb61643
CW		 2871static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2872{
2873 struct drm_device *dev = crtc->dev;
2874 struct drm_i915_private *dev_priv = dev->dev_private;
2875 unsigned long flags;
2876 bool pending;
2877
2878 if (atomic_read(&dev_priv->mm.wedged))
2879 return false;
2880
2881 spin_lock_irqsave(&dev->event_lock, flags);
2882 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2883 spin_unlock_irqrestore(&dev->event_lock, flags);
2884
2885 return pending;
2886}
2887
e6c3a2a6
CW		 2888static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2889{
0f91128d 2890 struct drm_device *dev = crtc->dev;
5bb61643 2891 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2892
2893 if (crtc->fb == NULL)
2894 return;
2895
5bb61643
CW		 2896 wait_event(dev_priv->pending_flip_queue,
2897 !intel_crtc_has_pending_flip(crtc));
2898
0f91128d
CW		 2899 mutex_lock(&dev->struct_mutex);
2900 intel_finish_fb(crtc->fb);
2901 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2902}
2903
fc316cbe 2904static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
040484af
JB		 2905{
2906 struct drm_device *dev = crtc->dev;
228d3e36 2907 struct intel_encoder *intel_encoder;
040484af
JB		 2908
2909 /*
2910 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2911 * must be driven by its own crtc; no sharing is possible.
2912 */
228d3e36 2913 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
228d3e36 2914 switch (intel_encoder->type) {
040484af 2915 case INTEL_OUTPUT_EDP:
228d3e36 2916 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
040484af
JB		 2917 return false;
2918 continue;
2919 }
2920 }
2921
2922 return true;
2923}
2924
fc316cbe
PZ		 2925static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
2926{
2927 return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
2928}
2929
e615efe4
ED		 2930/* Program iCLKIP clock to the desired frequency */
2931static void lpt_program_iclkip(struct drm_crtc *crtc)
2932{
2933 struct drm_device *dev = crtc->dev;
2934 struct drm_i915_private *dev_priv = dev->dev_private;
2935 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2936 u32 temp;
2937
2938 /* It is necessary to ungate the pixclk gate prior to programming
2939 * the divisors, and gate it back when it is done.
2940 */
2941 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2942
2943 /* Disable SSCCTL */
2944 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2945 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2946 SBI_SSCCTL_DISABLE);
2947
2948 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2949 if (crtc->mode.clock == 20000) {
2950 auxdiv = 1;
2951 divsel = 0x41;
2952 phaseinc = 0x20;
2953 } else {
2954 /* The iCLK virtual clock root frequency is in MHz,
2955 * but the crtc->mode.clock in in KHz. To get the divisors,
2956 * it is necessary to divide one by another, so we
2957 * convert the virtual clock precision to KHz here for higher
2958 * precision.
2959 */
2960 u32 iclk_virtual_root_freq = 172800 * 1000;
2961 u32 iclk_pi_range = 64;
2962 u32 desired_divisor, msb_divisor_value, pi_value;
2963
2964 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2965 msb_divisor_value = desired_divisor / iclk_pi_range;
2966 pi_value = desired_divisor % iclk_pi_range;
2967
2968 auxdiv = 0;
2969 divsel = msb_divisor_value - 2;
2970 phaseinc = pi_value;
2971 }
2972
2973 /* This should not happen with any sane values */
2974 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2975 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2976 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2977 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2978
2979 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2980 crtc->mode.clock,
2981 auxdiv,
2982 divsel,
2983 phasedir,
2984 phaseinc);
2985
2986 /* Program SSCDIVINTPHASE6 */
2987 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
2988 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2989 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2990 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2991 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2992 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2993 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2994
2995 intel_sbi_write(dev_priv,
2996 SBI_SSCDIVINTPHASE6,
2997 temp);
2998
2999 /* Program SSCAUXDIV */
3000 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
3001 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3002 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3003 intel_sbi_write(dev_priv,
3004 SBI_SSCAUXDIV6,
3005 temp);
3006
3007
3008 /* Enable modulator and associated divider */
3009 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
3010 temp &= ~SBI_SSCCTL_DISABLE;
3011 intel_sbi_write(dev_priv,
3012 SBI_SSCCTL6,
3013 temp);
3014
3015 /* Wait for initialization time */
3016 udelay(24);
3017
3018 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3019}
3020
f67a559d
JB		 3021/*
3022 * Enable PCH resources required for PCH ports:
3023 * - PCH PLLs
3024 * - FDI training & RX/TX
3025 * - update transcoder timings
3026 * - DP transcoding bits
3027 * - transcoder
3028 */
3029static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3030{
3031 struct drm_device *dev = crtc->dev;
3032 struct drm_i915_private *dev_priv = dev->dev_private;
3033 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3034 int pipe = intel_crtc->pipe;
ee7b9f93 3035 u32 reg, temp;
2c07245f 3036
e7e164db
CW		 3037 assert_transcoder_disabled(dev_priv, pipe);
3038
cd986abb
DV		 3039 /* Write the TU size bits before fdi link training, so that error
3040 * detection works. */
3041 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3042 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3043
c98e9dcf 3044 /* For PCH output, training FDI link */
674cf967 3045 dev_priv->display.fdi_link_train(crtc);
2c07245f 3046
572deb37
DV		 3047 /* XXX: pch pll's can be enabled any time before we enable the PCH
3048 * transcoder, and we actually should do this to not upset any PCH
3049 * transcoder that already use the clock when we share it.
3050 *
3051 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3052 * unconditionally resets the pll - we need that to have the right LVDS
3053 * enable sequence. */
6f13b7b5
CW		 3054 intel_enable_pch_pll(intel_crtc);
3055
e615efe4
ED		 3056 if (HAS_PCH_LPT(dev)) {
3057 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
3058 lpt_program_iclkip(crtc);
3059 } else if (HAS_PCH_CPT(dev)) {
ee7b9f93 3060 u32 sel;
4b645f14 3061
c98e9dcf 3062 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 3063 switch (pipe) {
3064 default:
3065 case 0:
3066 temp |= TRANSA_DPLL_ENABLE;
3067 sel = TRANSA_DPLLB_SEL;
3068 break;
3069 case 1:
3070 temp |= TRANSB_DPLL_ENABLE;
3071 sel = TRANSB_DPLLB_SEL;
3072 break;
3073 case 2:
3074 temp |= TRANSC_DPLL_ENABLE;
3075 sel = TRANSC_DPLLB_SEL;
3076 break;
d64311ab 3077 }
ee7b9f93
JB		 3078 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3079 temp |= sel;
3080 else
3081 temp &= ~sel;
c98e9dcf 3082 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3083 }
5eddb70b 3084
d9b6cb56
JB		 3085 /* set transcoder timing, panel must allow it */
3086 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 3087 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3088 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3089 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 3090
5eddb70b
CW		 3091 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3092 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3093 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 3094 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 3095
f57e1e3a
ED		 3096 if (!IS_HASWELL(dev))
3097 intel_fdi_normal_train(crtc);
5e84e1a4 3098
c98e9dcf
JB		 3099 /* For PCH DP, enable TRANS_DP_CTL */
3100 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3101 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3102 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
9325c9f0 3103 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
5eddb70b
CW		 3104 reg = TRANS_DP_CTL(pipe);
3105 temp = I915_READ(reg);
3106 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3107 TRANS_DP_SYNC_MASK |
3108 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3109 temp |= (TRANS_DP_OUTPUT_ENABLE |
3110 TRANS_DP_ENH_FRAMING);
9325c9f0 3111 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3112
3113 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3114 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3115 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3116 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3117
3118 switch (intel_trans_dp_port_sel(crtc)) {
3119 case PCH_DP_B:
5eddb70b 3120 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3121 break;
3122 case PCH_DP_C:
5eddb70b 3123 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3124 break;
3125 case PCH_DP_D:
5eddb70b 3126 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3127 break;
3128 default:
e95d41e1 3129 BUG();
32f9d658 3130 }
2c07245f 3131
5eddb70b 3132 I915_WRITE(reg, temp);
6be4a607 3133 }
b52eb4dc 3134
040484af 3135 intel_enable_transcoder(dev_priv, pipe);
f67a559d
JB		 3136}
3137
ee7b9f93
JB		 3138static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3139{
3140 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3141
3142 if (pll == NULL)
3143 return;
3144
3145 if (pll->refcount == 0) {
3146 WARN(1, "bad PCH PLL refcount\n");
3147 return;
3148 }
3149
3150 --pll->refcount;
3151 intel_crtc->pch_pll = NULL;
3152}
3153
3154static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3155{
3156 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3157 struct intel_pch_pll *pll;
3158 int i;
3159
3160 pll = intel_crtc->pch_pll;
3161 if (pll) {
3162 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3163 intel_crtc->base.base.id, pll->pll_reg);
3164 goto prepare;
3165 }
3166
98b6bd99
DV		 3167 if (HAS_PCH_IBX(dev_priv->dev)) {
3168 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3169 i = intel_crtc->pipe;
3170 pll = &dev_priv->pch_plls[i];
3171
3172 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3173 intel_crtc->base.base.id, pll->pll_reg);
3174
3175 goto found;
3176 }
3177
ee7b9f93
JB		 3178 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3179 pll = &dev_priv->pch_plls[i];
3180
3181 /* Only want to check enabled timings first */
3182 if (pll->refcount == 0)
3183 continue;
3184
3185 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3186 fp == I915_READ(pll->fp0_reg)) {
3187 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3188 intel_crtc->base.base.id,
3189 pll->pll_reg, pll->refcount, pll->active);
3190
3191 goto found;
3192 }
3193 }
3194
3195 /* Ok no matching timings, maybe there's a free one? */
3196 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3197 pll = &dev_priv->pch_plls[i];
3198 if (pll->refcount == 0) {
3199 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3200 intel_crtc->base.base.id, pll->pll_reg);
3201 goto found;
3202 }
3203 }
3204
3205 return NULL;
3206
3207found:
3208 intel_crtc->pch_pll = pll;
3209 pll->refcount++;
3210 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3211prepare: /* separate function? */
3212 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3213
e04c7350
CW		 3214 /* Wait for the clocks to stabilize before rewriting the regs */
3215 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3216 POSTING_READ(pll->pll_reg);
3217 udelay(150);
e04c7350
CW		 3218
3219 I915_WRITE(pll->fp0_reg, fp);
3220 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3221 pll->on = false;
3222 return pll;
3223}
3224
d4270e57
JB		 3225void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3226{
3227 struct drm_i915_private *dev_priv = dev->dev_private;
3228 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3229 u32 temp;
3230
3231 temp = I915_READ(dslreg);
3232 udelay(500);
3233 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3234 /* Without this, mode sets may fail silently on FDI */
3235 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3236 udelay(250);
3237 I915_WRITE(tc2reg, 0);
3238 if (wait_for(I915_READ(dslreg) != temp, 5))
3239 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3240 }
3241}
3242
f67a559d
JB		 3243static void ironlake_crtc_enable(struct drm_crtc *crtc)
3244{
3245 struct drm_device *dev = crtc->dev;
3246 struct drm_i915_private *dev_priv = dev->dev_private;
3247 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3248 struct intel_encoder *encoder;
f67a559d
JB		 3249 int pipe = intel_crtc->pipe;
3250 int plane = intel_crtc->plane;
3251 u32 temp;
3252 bool is_pch_port;
3253
08a48469
DV		 3254 WARN_ON(!crtc->enabled);
3255
f67a559d
JB		 3256 if (intel_crtc->active)
3257 return;
3258
3259 intel_crtc->active = true;
3260 intel_update_watermarks(dev);
3261
3262 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3263 temp = I915_READ(PCH_LVDS);
3264 if ((temp & LVDS_PORT_EN) == 0)
3265 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3266 }
3267
fc316cbe 3268 is_pch_port = ironlake_crtc_driving_pch(crtc);
f67a559d 3269
46b6f814 3270 if (is_pch_port) {
fff367c7
DV		 3271 /* Note: FDI PLL enabling _must_ be done before we enable the
3272 * cpu pipes, hence this is separate from all the other fdi/pch
3273 * enabling. */
88cefb6c 3274 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3275 } else {
3276 assert_fdi_tx_disabled(dev_priv, pipe);
3277 assert_fdi_rx_disabled(dev_priv, pipe);
3278 }
f67a559d 3279
bf49ec8c
DV		 3280 for_each_encoder_on_crtc(dev, crtc, encoder)
3281 if (encoder->pre_enable)
3282 encoder->pre_enable(encoder);
3283
f67a559d
JB		 3284 /* Enable panel fitting for LVDS */
3285 if (dev_priv->pch_pf_size &&
3286 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3287 /* Force use of hard-coded filter coefficients
3288 * as some pre-programmed values are broken,
3289 * e.g. x201.
3290 */
9db4a9c7
JB		 3291 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3292 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3293 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3294 }
3295
9c54c0dd
JB		 3296 /*
3297 * On ILK+ LUT must be loaded before the pipe is running but with
3298 * clocks enabled
3299 */
3300 intel_crtc_load_lut(crtc);
3301
f67a559d
JB		 3302 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3303 intel_enable_plane(dev_priv, plane, pipe);
3304
3305 if (is_pch_port)
3306 ironlake_pch_enable(crtc);
c98e9dcf 3307
d1ebd816 3308 mutex_lock(&dev->struct_mutex);
bed4a673 3309 intel_update_fbc(dev);
d1ebd816
BW		 3310 mutex_unlock(&dev->struct_mutex);
3311
6b383a7f 3312 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3313
fa5c73b1
DV		 3314 for_each_encoder_on_crtc(dev, crtc, encoder)
3315 encoder->enable(encoder);
61b77ddd
DV		 3316
3317 if (HAS_PCH_CPT(dev))
3318 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3319
3320 /*
3321 * There seems to be a race in PCH platform hw (at least on some
3322 * outputs) where an enabled pipe still completes any pageflip right
3323 * away (as if the pipe is off) instead of waiting for vblank. As soon
3324 * as the first vblank happend, everything works as expected. Hence just
3325 * wait for one vblank before returning to avoid strange things
3326 * happening.
3327 */
3328 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3329}
3330
4f771f10
PZ		 3331static void haswell_crtc_enable(struct drm_crtc *crtc)
3332{
3333 struct drm_device *dev = crtc->dev;
3334 struct drm_i915_private *dev_priv = dev->dev_private;
3335 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3336 struct intel_encoder *encoder;
3337 int pipe = intel_crtc->pipe;
3338 int plane = intel_crtc->plane;
4f771f10
PZ		 3339 bool is_pch_port;
3340
3341 WARN_ON(!crtc->enabled);
3342
3343 if (intel_crtc->active)
3344 return;
3345
3346 intel_crtc->active = true;
3347 intel_update_watermarks(dev);
3348
fc316cbe 3349 is_pch_port = haswell_crtc_driving_pch(crtc);
4f771f10 3350
83616634 3351 if (is_pch_port)
4f771f10 3352 ironlake_fdi_pll_enable(intel_crtc);
4f771f10
PZ		 3353
3354 for_each_encoder_on_crtc(dev, crtc, encoder)
3355 if (encoder->pre_enable)
3356 encoder->pre_enable(encoder);
3357
1f544388 3358 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3359
1f544388
PZ		 3360 /* Enable panel fitting for eDP */
3361 if (dev_priv->pch_pf_size && HAS_eDP) {
4f771f10
PZ		 3362 /* Force use of hard-coded filter coefficients
3363 * as some pre-programmed values are broken,
3364 * e.g. x201.
3365 */
3366 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3367 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3368 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3369 }
3370
3371 /*
3372 * On ILK+ LUT must be loaded before the pipe is running but with
3373 * clocks enabled
3374 */
3375 intel_crtc_load_lut(crtc);
3376
1f544388
PZ		 3377 intel_ddi_set_pipe_settings(crtc);
3378 intel_ddi_enable_pipe_func(crtc);
4f771f10
PZ		 3379
3380 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3381 intel_enable_plane(dev_priv, plane, pipe);
3382
3383 if (is_pch_port)
3384 ironlake_pch_enable(crtc);
3385
3386 mutex_lock(&dev->struct_mutex);
3387 intel_update_fbc(dev);
3388 mutex_unlock(&dev->struct_mutex);
3389
3390 intel_crtc_update_cursor(crtc, true);
3391
3392 for_each_encoder_on_crtc(dev, crtc, encoder)
3393 encoder->enable(encoder);
3394
4f771f10
PZ		 3395 /*
3396 * There seems to be a race in PCH platform hw (at least on some
3397 * outputs) where an enabled pipe still completes any pageflip right
3398 * away (as if the pipe is off) instead of waiting for vblank. As soon
3399 * as the first vblank happend, everything works as expected. Hence just
3400 * wait for one vblank before returning to avoid strange things
3401 * happening.
3402 */
3403 intel_wait_for_vblank(dev, intel_crtc->pipe);
3404}
3405
6be4a607
JB		 3406static void ironlake_crtc_disable(struct drm_crtc *crtc)
3407{
3408 struct drm_device *dev = crtc->dev;
3409 struct drm_i915_private *dev_priv = dev->dev_private;
3410 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3411 struct intel_encoder *encoder;
6be4a607
JB		 3412 int pipe = intel_crtc->pipe;
3413 int plane = intel_crtc->plane;
5eddb70b 3414 u32 reg, temp;
b52eb4dc 3415
ef9c3aee 3416
f7abfe8b
CW		 3417 if (!intel_crtc->active)
3418 return;
3419
ea9d758d
DV		 3420 for_each_encoder_on_crtc(dev, crtc, encoder)
3421 encoder->disable(encoder);
3422
e6c3a2a6 3423 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3424 drm_vblank_off(dev, pipe);
6b383a7f 3425 intel_crtc_update_cursor(crtc, false);
5eddb70b 3426
b24e7179 3427 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3428
973d04f9
CW		 3429 if (dev_priv->cfb_plane == plane)
3430 intel_disable_fbc(dev);
2c07245f 3431
b24e7179 3432 intel_disable_pipe(dev_priv, pipe);
32f9d658 3433
6be4a607 3434 /* Disable PF */
9db4a9c7
JB		 3435 I915_WRITE(PF_CTL(pipe), 0);
3436 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3437
bf49ec8c
DV		 3438 for_each_encoder_on_crtc(dev, crtc, encoder)
3439 if (encoder->post_disable)
3440 encoder->post_disable(encoder);
3441
0fc932b8 3442 ironlake_fdi_disable(crtc);
2c07245f 3443
040484af 3444 intel_disable_transcoder(dev_priv, pipe);
913d8d11 3445
6be4a607
JB		 3446 if (HAS_PCH_CPT(dev)) {
3447 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3448 reg = TRANS_DP_CTL(pipe);
3449 temp = I915_READ(reg);
3450 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3451 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3452 I915_WRITE(reg, temp);
6be4a607
JB		 3453
3454 /* disable DPLL_SEL */
3455 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3456 switch (pipe) {
3457 case 0:
d64311ab 3458 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3459 break;
3460 case 1:
6be4a607 3461 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3462 break;
3463 case 2:
4b645f14 3464 /* C shares PLL A or B */
d64311ab 3465 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3466 break;
3467 default:
3468 BUG(); /* wtf */
3469 }
6be4a607 3470 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3471 }
e3421a18 3472
6be4a607 3473 /* disable PCH DPLL */
ee7b9f93 3474 intel_disable_pch_pll(intel_crtc);
8db9d77b 3475
88cefb6c 3476 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3477
f7abfe8b 3478 intel_crtc->active = false;
6b383a7f 3479 intel_update_watermarks(dev);
d1ebd816
BW		 3480
3481 mutex_lock(&dev->struct_mutex);
6b383a7f 3482 intel_update_fbc(dev);
d1ebd816 3483 mutex_unlock(&dev->struct_mutex);
6be4a607 3484}
1b3c7a47 3485
4f771f10
PZ		 3486static void haswell_crtc_disable(struct drm_crtc *crtc)
3487{
3488 struct drm_device *dev = crtc->dev;
3489 struct drm_i915_private *dev_priv = dev->dev_private;
3490 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3491 struct intel_encoder *encoder;
3492 int pipe = intel_crtc->pipe;
3493 int plane = intel_crtc->plane;
ad80a810 3494 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
83616634 3495 bool is_pch_port;
4f771f10
PZ		 3496
3497 if (!intel_crtc->active)
3498 return;
3499
83616634
PZ		 3500 is_pch_port = haswell_crtc_driving_pch(crtc);
3501
4f771f10
PZ		 3502 for_each_encoder_on_crtc(dev, crtc, encoder)
3503 encoder->disable(encoder);
3504
3505 intel_crtc_wait_for_pending_flips(crtc);
3506 drm_vblank_off(dev, pipe);
3507 intel_crtc_update_cursor(crtc, false);
3508
3509 intel_disable_plane(dev_priv, plane, pipe);
3510
3511 if (dev_priv->cfb_plane == plane)
3512 intel_disable_fbc(dev);
3513
3514 intel_disable_pipe(dev_priv, pipe);
3515
ad80a810 3516 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10
PZ		 3517
3518 /* Disable PF */
3519 I915_WRITE(PF_CTL(pipe), 0);
3520 I915_WRITE(PF_WIN_SZ(pipe), 0);
3521
1f544388 3522 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3523
3524 for_each_encoder_on_crtc(dev, crtc, encoder)
3525 if (encoder->post_disable)
3526 encoder->post_disable(encoder);
3527
83616634
PZ		 3528 if (is_pch_port) {
3529 ironlake_fdi_disable(crtc);
3530 intel_disable_transcoder(dev_priv, pipe);
3531 intel_disable_pch_pll(intel_crtc);
3532 ironlake_fdi_pll_disable(intel_crtc);
3533 }
4f771f10
PZ		 3534
3535 intel_crtc->active = false;
3536 intel_update_watermarks(dev);
3537
3538 mutex_lock(&dev->struct_mutex);
3539 intel_update_fbc(dev);
3540 mutex_unlock(&dev->struct_mutex);
3541}
3542
ee7b9f93
JB		 3543static void ironlake_crtc_off(struct drm_crtc *crtc)
3544{
3545 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3546 intel_put_pch_pll(intel_crtc);
3547}
3548
6441ab5f
PZ		 3549static void haswell_crtc_off(struct drm_crtc *crtc)
3550{
a5c961d1
PZ		 3551 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3552
3553 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3554 * start using it. */
3555 intel_crtc->cpu_transcoder = intel_crtc->pipe;
3556
6441ab5f
PZ		 3557 intel_ddi_put_crtc_pll(crtc);
3558}
3559
02e792fb
DV		 3560static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3561{
02e792fb 3562 if (!enable && intel_crtc->overlay) {
23f09ce3 3563 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3564 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3565
23f09ce3 3566 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3567 dev_priv->mm.interruptible = false;
3568 (void) intel_overlay_switch_off(intel_crtc->overlay);
3569 dev_priv->mm.interruptible = true;
23f09ce3 3570 mutex_unlock(&dev->struct_mutex);
02e792fb 3571 }
02e792fb 3572
5dcdbcb0
CW		 3573 /* Let userspace switch the overlay on again. In most cases userspace
3574 * has to recompute where to put it anyway.
3575 */
02e792fb
DV		 3576}
3577
0b8765c6 3578static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3579{
3580 struct drm_device *dev = crtc->dev;
79e53945
JB		 3581 struct drm_i915_private *dev_priv = dev->dev_private;
3582 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3583 struct intel_encoder *encoder;
79e53945 3584 int pipe = intel_crtc->pipe;
80824003 3585 int plane = intel_crtc->plane;
79e53945 3586
08a48469
DV		 3587 WARN_ON(!crtc->enabled);
3588
f7abfe8b
CW		 3589 if (intel_crtc->active)
3590 return;
3591
3592 intel_crtc->active = true;
6b383a7f
CW		 3593 intel_update_watermarks(dev);
3594
63d7bbe9 3595 intel_enable_pll(dev_priv, pipe);
040484af 3596 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3597 intel_enable_plane(dev_priv, plane, pipe);
79e53945 3598
0b8765c6 3599 intel_crtc_load_lut(crtc);
bed4a673 3600 intel_update_fbc(dev);
79e53945 3601
0b8765c6
JB		 3602 /* Give the overlay scaler a chance to enable if it's on this pipe */
3603 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3604 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3605
fa5c73b1
DV		 3606 for_each_encoder_on_crtc(dev, crtc, encoder)
3607 encoder->enable(encoder);
0b8765c6 3608}
79e53945 3609
0b8765c6
JB		 3610static void i9xx_crtc_disable(struct drm_crtc *crtc)
3611{
3612 struct drm_device *dev = crtc->dev;
3613 struct drm_i915_private *dev_priv = dev->dev_private;
3614 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3615 struct intel_encoder *encoder;
0b8765c6
JB		 3616 int pipe = intel_crtc->pipe;
3617 int plane = intel_crtc->plane;
b690e96c 3618
ef9c3aee 3619
f7abfe8b
CW		 3620 if (!intel_crtc->active)
3621 return;
3622
ea9d758d
DV		 3623 for_each_encoder_on_crtc(dev, crtc, encoder)
3624 encoder->disable(encoder);
3625
0b8765c6 3626 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3627 intel_crtc_wait_for_pending_flips(crtc);
3628 drm_vblank_off(dev, pipe);
0b8765c6 3629 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3630 intel_crtc_update_cursor(crtc, false);
0b8765c6 3631
973d04f9
CW		 3632 if (dev_priv->cfb_plane == plane)
3633 intel_disable_fbc(dev);
79e53945 3634
b24e7179 3635 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3636 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 3637 intel_disable_pll(dev_priv, pipe);
0b8765c6 3638
f7abfe8b 3639 intel_crtc->active = false;
6b383a7f
CW		 3640 intel_update_fbc(dev);
3641 intel_update_watermarks(dev);
0b8765c6
JB		 3642}
3643
ee7b9f93
JB		 3644static void i9xx_crtc_off(struct drm_crtc *crtc)
3645{
3646}
3647
976f8a20
DV		 3648static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3649 bool enabled)
2c07245f
ZW		 3650{
3651 struct drm_device *dev = crtc->dev;
3652 struct drm_i915_master_private *master_priv;
3653 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3654 int pipe = intel_crtc->pipe;
79e53945
JB		 3655
3656 if (!dev->primary->master)
3657 return;
3658
3659 master_priv = dev->primary->master->driver_priv;
3660 if (!master_priv->sarea_priv)
3661 return;
3662
79e53945
JB		 3663 switch (pipe) {
3664 case 0:
3665 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3666 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3667 break;
3668 case 1:
3669 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3670 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3671 break;
3672 default:
9db4a9c7 3673 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3674 break;
3675 }
79e53945
JB		 3676}
3677
976f8a20
DV		 3678/**
3679 * Sets the power management mode of the pipe and plane.
3680 */
3681void intel_crtc_update_dpms(struct drm_crtc *crtc)
3682{
3683 struct drm_device *dev = crtc->dev;
3684 struct drm_i915_private *dev_priv = dev->dev_private;
3685 struct intel_encoder *intel_encoder;
3686 bool enable = false;
3687
3688 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3689 enable |= intel_encoder->connectors_active;
3690
3691 if (enable)
3692 dev_priv->display.crtc_enable(crtc);
3693 else
3694 dev_priv->display.crtc_disable(crtc);
3695
3696 intel_crtc_update_sarea(crtc, enable);
3697}
3698
3699static void intel_crtc_noop(struct drm_crtc *crtc)
3700{
3701}
3702
cdd59983
CW		 3703static void intel_crtc_disable(struct drm_crtc *crtc)
3704{
cdd59983 3705 struct drm_device *dev = crtc->dev;
976f8a20 3706 struct drm_connector *connector;
ee7b9f93 3707 struct drm_i915_private *dev_priv = dev->dev_private;
cdd59983 3708
976f8a20
DV		 3709 /* crtc should still be enabled when we disable it. */
3710 WARN_ON(!crtc->enabled);
3711
3712 dev_priv->display.crtc_disable(crtc);
3713 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3714 dev_priv->display.off(crtc);
3715
931872fc
CW		 3716 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3717 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3718
3719 if (crtc->fb) {
3720 mutex_lock(&dev->struct_mutex);
1690e1eb 3721 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3722 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3723 crtc->fb = NULL;
3724 }
3725
3726 /* Update computed state. */
3727 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3728 if (!connector->encoder || !connector->encoder->crtc)
3729 continue;
3730
3731 if (connector->encoder->crtc != crtc)
3732 continue;
3733
3734 connector->dpms = DRM_MODE_DPMS_OFF;
3735 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3736 }
3737}
3738
a261b246 3739void intel_modeset_disable(struct drm_device *dev)
79e53945 3740{
a261b246
DV		 3741 struct drm_crtc *crtc;
3742
3743 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3744 if (crtc->enabled)
3745 intel_crtc_disable(crtc);
3746 }
79e53945
JB		 3747}
3748
1f703855 3749void intel_encoder_noop(struct drm_encoder *encoder)
79e53945 3750{
7e7d76c3
JB		 3751}
3752
ea5b213a 3753void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3754{
4ef69c7a 3755 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3756
ea5b213a
CW		 3757 drm_encoder_cleanup(encoder);
3758 kfree(intel_encoder);
7e7d76c3
JB		 3759}
3760
5ab432ef
DV		 3761/* Simple dpms helper for encodres with just one connector, no cloning and only
3762 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3763 * state of the entire output pipe. */
3764void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3765{
5ab432ef
DV		 3766 if (mode == DRM_MODE_DPMS_ON) {
3767 encoder->connectors_active = true;
3768
b2cabb0e 3769 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3770 } else {
3771 encoder->connectors_active = false;
3772
b2cabb0e 3773 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3774 }
79e53945
JB		 3775}
3776
0a91ca29
DV		 3777/* Cross check the actual hw state with our own modeset state tracking (and it's
3778 * internal consistency). */
b980514c 3779static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3780{
0a91ca29
DV		 3781 if (connector->get_hw_state(connector)) {
3782 struct intel_encoder *encoder = connector->encoder;
3783 struct drm_crtc *crtc;
3784 bool encoder_enabled;
3785 enum pipe pipe;
3786
3787 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3788 connector->base.base.id,
3789 drm_get_connector_name(&connector->base));
3790
3791 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3792 "wrong connector dpms state\n");
3793 WARN(connector->base.encoder != &encoder->base,
3794 "active connector not linked to encoder\n");
3795 WARN(!encoder->connectors_active,
3796 "encoder->connectors_active not set\n");
3797
3798 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3799 WARN(!encoder_enabled, "encoder not enabled\n");
3800 if (WARN_ON(!encoder->base.crtc))
3801 return;
3802
3803 crtc = encoder->base.crtc;
3804
3805 WARN(!crtc->enabled, "crtc not enabled\n");
3806 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3807 WARN(pipe != to_intel_crtc(crtc)->pipe,
3808 "encoder active on the wrong pipe\n");
3809 }
79e53945
JB		 3810}
3811
5ab432ef
DV		 3812/* Even simpler default implementation, if there's really no special case to
3813 * consider. */
3814void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3815{
5ab432ef 3816 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3817
5ab432ef
DV		 3818 /* All the simple cases only support two dpms states. */
3819 if (mode != DRM_MODE_DPMS_ON)
3820 mode = DRM_MODE_DPMS_OFF;
d4270e57 3821
5ab432ef
DV		 3822 if (mode == connector->dpms)
3823 return;
3824
3825 connector->dpms = mode;
3826
3827 /* Only need to change hw state when actually enabled */
3828 if (encoder->base.crtc)
3829 intel_encoder_dpms(encoder, mode);
3830 else
8af6cf88 3831 WARN_ON(encoder->connectors_active != false);
0a91ca29 3832
b980514c 3833 intel_modeset_check_state(connector->dev);
79e53945
JB		 3834}
3835
f0947c37
DV		 3836/* Simple connector->get_hw_state implementation for encoders that support only
3837 * one connector and no cloning and hence the encoder state determines the state
3838 * of the connector. */
3839bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3840{
24929352 3841 enum pipe pipe = 0;
f0947c37 3842 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3843
f0947c37 3844 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3845}
3846
79e53945 3847static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
35313cde 3848 const struct drm_display_mode *mode,
79e53945
JB		 3849 struct drm_display_mode *adjusted_mode)
3850{
2c07245f 3851 struct drm_device *dev = crtc->dev;
89749350 3852
bad720ff 3853 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3854 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3855 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3856 return false;
2c07245f 3857 }
89749350 3858
f9bef081
DV		 3859 /* All interlaced capable intel hw wants timings in frames. Note though
3860 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3861 * timings, so we need to be careful not to clobber these.*/
3862 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3863 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3864
44f46b42
CW		 3865 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3866 * with a hsync front porch of 0.
3867 */
3868 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3869 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3870 return false;
3871
79e53945
JB		 3872 return true;
3873}
3874
25eb05fc
JB		 3875static int valleyview_get_display_clock_speed(struct drm_device *dev)
3876{
3877 return 400000; /* FIXME */
3878}
3879
e70236a8
JB		 3880static int i945_get_display_clock_speed(struct drm_device *dev)
3881{
3882 return 400000;
3883}
79e53945 3884
e70236a8 3885static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3886{
e70236a8
JB		 3887 return 333000;
3888}
79e53945 3889
e70236a8
JB		 3890static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3891{
3892 return 200000;
3893}
79e53945 3894
e70236a8
JB		 3895static int i915gm_get_display_clock_speed(struct drm_device *dev)
3896{
3897 u16 gcfgc = 0;
79e53945 3898
e70236a8
JB		 3899 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3900
3901 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3902 return 133000;
3903 else {
3904 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3905 case GC_DISPLAY_CLOCK_333_MHZ:
3906 return 333000;
3907 default:
3908 case GC_DISPLAY_CLOCK_190_200_MHZ:
3909 return 190000;
79e53945 3910 }
e70236a8
JB		 3911 }
3912}
3913
3914static int i865_get_display_clock_speed(struct drm_device *dev)
3915{
3916 return 266000;
3917}
3918
3919static int i855_get_display_clock_speed(struct drm_device *dev)
3920{
3921 u16 hpllcc = 0;
3922 /* Assume that the hardware is in the high speed state. This
3923 * should be the default.
3924 */
3925 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3926 case GC_CLOCK_133_200:
3927 case GC_CLOCK_100_200:
3928 return 200000;
3929 case GC_CLOCK_166_250:
3930 return 250000;
3931 case GC_CLOCK_100_133:
79e53945 3932 return 133000;
e70236a8 3933 }
79e53945 3934
e70236a8
JB		 3935 /* Shouldn't happen */
3936 return 0;
3937}
79e53945 3938
e70236a8
JB		 3939static int i830_get_display_clock_speed(struct drm_device *dev)
3940{
3941 return 133000;
79e53945
JB		 3942}
3943
2c07245f
ZW		 3944struct fdi_m_n {
3945 u32 tu;
3946 u32 gmch_m;
3947 u32 gmch_n;
3948 u32 link_m;
3949 u32 link_n;
3950};
3951
3952static void
3953fdi_reduce_ratio(u32 *num, u32 *den)
3954{
3955 while (*num > 0xffffff || *den > 0xffffff) {
3956 *num >>= 1;
3957 *den >>= 1;
3958 }
3959}
3960
2c07245f 3961static void
f2b115e6
AJ		 3962ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3963 int link_clock, struct fdi_m_n *m_n)
2c07245f 3964{
2c07245f
ZW		 3965 m_n->tu = 64; /* default size */
3966
22ed1113
CW		 3967 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3968 m_n->gmch_m = bits_per_pixel * pixel_clock;
3969 m_n->gmch_n = link_clock * nlanes * 8;
2c07245f
ZW		 3970 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3971
22ed1113
CW		 3972 m_n->link_m = pixel_clock;
3973 m_n->link_n = link_clock;
2c07245f
ZW		 3974 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3975}
3976
a7615030
CW		 3977static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3978{
72bbe58c
KP		 3979 if (i915_panel_use_ssc >= 0)
3980 return i915_panel_use_ssc != 0;
3981 return dev_priv->lvds_use_ssc
435793df 3982 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 3983}
3984
5a354204
JB		 3985/**
3986 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3987 * @crtc: CRTC structure
3b5c78a3 3988 * @mode: requested mode
5a354204
JB		 3989 *
3990 * A pipe may be connected to one or more outputs. Based on the depth of the
3991 * attached framebuffer, choose a good color depth to use on the pipe.
3992 *
3993 * If possible, match the pipe depth to the fb depth. In some cases, this
3994 * isn't ideal, because the connected output supports a lesser or restricted
3995 * set of depths. Resolve that here:
3996 * LVDS typically supports only 6bpc, so clamp down in that case
3997 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3998 * Displays may support a restricted set as well, check EDID and clamp as
3999 * appropriate.
3b5c78a3 4000 * DP may want to dither down to 6bpc to fit larger modes
5a354204
JB		 4001 *
4002 * RETURNS:
4003 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4004 * true if they don't match).
4005 */
4006static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
94352cf9 4007 struct drm_framebuffer *fb,
3b5c78a3
AJ		 4008 unsigned int *pipe_bpp,
4009 struct drm_display_mode *mode)
5a354204
JB		 4010{
4011 struct drm_device *dev = crtc->dev;
4012 struct drm_i915_private *dev_priv = dev->dev_private;
5a354204 4013 struct drm_connector *connector;
6c2b7c12 4014 struct intel_encoder *intel_encoder;
5a354204
JB		 4015 unsigned int display_bpc = UINT_MAX, bpc;
4016
4017 /* Walk the encoders & connectors on this crtc, get min bpc */
6c2b7c12 4018 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5a354204
JB		 4019
4020 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4021 unsigned int lvds_bpc;
4022
4023 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4024 LVDS_A3_POWER_UP)
4025 lvds_bpc = 8;
4026 else
4027 lvds_bpc = 6;
4028
4029 if (lvds_bpc < display_bpc) {
82820490 4030 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5a354204
JB		 4031 display_bpc = lvds_bpc;
4032 }
4033 continue;
4034 }
4035
5a354204
JB		 4036 /* Not one of the known troublemakers, check the EDID */
4037 list_for_each_entry(connector, &dev->mode_config.connector_list,
4038 head) {
6c2b7c12 4039 if (connector->encoder != &intel_encoder->base)
5a354204
JB		 4040 continue;
4041
62ac41a6
JB		 4042 /* Don't use an invalid EDID bpc value */
4043 if (connector->display_info.bpc &&
4044 connector->display_info.bpc < display_bpc) {
82820490 4045 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5a354204
JB		 4046 display_bpc = connector->display_info.bpc;
4047 }
4048 }
4049
4050 /*
4051 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4052 * through, clamp it down. (Note: >12bpc will be caught below.)
4053 */
4054 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4055 if (display_bpc > 8 && display_bpc < 12) {
82820490 4056 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5a354204
JB		 4057 display_bpc = 12;
4058 } else {
82820490 4059 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5a354204
JB		 4060 display_bpc = 8;
4061 }
4062 }
4063 }
4064
3b5c78a3
AJ		 4065 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4066 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4067 display_bpc = 6;
4068 }
4069
5a354204
JB		 4070 /*
4071 * We could just drive the pipe at the highest bpc all the time and
4072 * enable dithering as needed, but that costs bandwidth. So choose
4073 * the minimum value that expresses the full color range of the fb but
4074 * also stays within the max display bpc discovered above.
4075 */
4076
94352cf9 4077 switch (fb->depth) {
5a354204
JB		 4078 case 8:
4079 bpc = 8; /* since we go through a colormap */
4080 break;
4081 case 15:
4082 case 16:
4083 bpc = 6; /* min is 18bpp */
4084 break;
4085 case 24:
578393cd 4086 bpc = 8;
5a354204
JB		 4087 break;
4088 case 30:
578393cd 4089 bpc = 10;
5a354204
JB		 4090 break;
4091 case 48:
578393cd 4092 bpc = 12;
5a354204
JB		 4093 break;
4094 default:
4095 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4096 bpc = min((unsigned int)8, display_bpc);
4097 break;
4098 }
4099
578393cd
KP		 4100 display_bpc = min(display_bpc, bpc);
4101
82820490
AJ		 4102 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4103 bpc, display_bpc);
5a354204 4104
578393cd 4105 *pipe_bpp = display_bpc * 3;
5a354204
JB		 4106
4107 return display_bpc != bpc;
4108}
4109
a0c4da24
JB		 4110static int vlv_get_refclk(struct drm_crtc *crtc)
4111{
4112 struct drm_device *dev = crtc->dev;
4113 struct drm_i915_private *dev_priv = dev->dev_private;
4114 int refclk = 27000; /* for DP & HDMI */
4115
4116 return 100000; /* only one validated so far */
4117
4118 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4119 refclk = 96000;
4120 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4121 if (intel_panel_use_ssc(dev_priv))
4122 refclk = 100000;
4123 else
4124 refclk = 96000;
4125 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4126 refclk = 100000;
4127 }
4128
4129 return refclk;
4130}
4131
c65d77d8
JB		 4132static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4133{
4134 struct drm_device *dev = crtc->dev;
4135 struct drm_i915_private *dev_priv = dev->dev_private;
4136 int refclk;
4137
a0c4da24
JB		 4138 if (IS_VALLEYVIEW(dev)) {
4139 refclk = vlv_get_refclk(crtc);
4140 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8
JB		 4141 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4142 refclk = dev_priv->lvds_ssc_freq * 1000;
4143 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4144 refclk / 1000);
4145 } else if (!IS_GEN2(dev)) {
4146 refclk = 96000;
4147 } else {
4148 refclk = 48000;
4149 }
4150
4151 return refclk;
4152}
4153
4154static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4155 intel_clock_t *clock)
4156{
4157 /* SDVO TV has fixed PLL values depend on its clock range,
4158 this mirrors vbios setting. */
4159 if (adjusted_mode->clock >= 100000
4160 && adjusted_mode->clock < 140500) {
4161 clock->p1 = 2;
4162 clock->p2 = 10;
4163 clock->n = 3;
4164 clock->m1 = 16;
4165 clock->m2 = 8;
4166 } else if (adjusted_mode->clock >= 140500
4167 && adjusted_mode->clock <= 200000) {
4168 clock->p1 = 1;
4169 clock->p2 = 10;
4170 clock->n = 6;
4171 clock->m1 = 12;
4172 clock->m2 = 8;
4173 }
4174}
4175
a7516a05
JB		 4176static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4177 intel_clock_t *clock,
4178 intel_clock_t *reduced_clock)
4179{
4180 struct drm_device *dev = crtc->dev;
4181 struct drm_i915_private *dev_priv = dev->dev_private;
4182 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4183 int pipe = intel_crtc->pipe;
4184 u32 fp, fp2 = 0;
4185
4186 if (IS_PINEVIEW(dev)) {
4187 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4188 if (reduced_clock)
4189 fp2 = (1 << reduced_clock->n) << 16 |
4190 reduced_clock->m1 << 8 | reduced_clock->m2;
4191 } else {
4192 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4193 if (reduced_clock)
4194 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4195 reduced_clock->m2;
4196 }
4197
4198 I915_WRITE(FP0(pipe), fp);
4199
4200 intel_crtc->lowfreq_avail = false;
4201 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4202 reduced_clock && i915_powersave) {
4203 I915_WRITE(FP1(pipe), fp2);
4204 intel_crtc->lowfreq_avail = true;
4205 } else {
4206 I915_WRITE(FP1(pipe), fp);
4207 }
4208}
4209
93e537a1
DV		 4210static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
4211 struct drm_display_mode *adjusted_mode)
4212{
4213 struct drm_device *dev = crtc->dev;
4214 struct drm_i915_private *dev_priv = dev->dev_private;
4215 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4216 int pipe = intel_crtc->pipe;
284d5df5 4217 u32 temp;
93e537a1
DV		 4218
4219 temp = I915_READ(LVDS);
4220 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4221 if (pipe == 1) {
4222 temp |= LVDS_PIPEB_SELECT;
4223 } else {
4224 temp &= ~LVDS_PIPEB_SELECT;
4225 }
4226 /* set the corresponsding LVDS_BORDER bit */
4227 temp |= dev_priv->lvds_border_bits;
4228 /* Set the B0-B3 data pairs corresponding to whether we're going to
4229 * set the DPLLs for dual-channel mode or not.
4230 */
4231 if (clock->p2 == 7)
4232 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4233 else
4234 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4235
4236 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4237 * appropriately here, but we need to look more thoroughly into how
4238 * panels behave in the two modes.
4239 */
4240 /* set the dithering flag on LVDS as needed */
4241 if (INTEL_INFO(dev)->gen >= 4) {
4242 if (dev_priv->lvds_dither)
4243 temp |= LVDS_ENABLE_DITHER;
4244 else
4245 temp &= ~LVDS_ENABLE_DITHER;
4246 }
284d5df5 4247 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
93e537a1 4248 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 4249 temp |= LVDS_HSYNC_POLARITY;
93e537a1 4250 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 4251 temp |= LVDS_VSYNC_POLARITY;
93e537a1
DV		 4252 I915_WRITE(LVDS, temp);
4253}
4254
a0c4da24
JB		 4255static void vlv_update_pll(struct drm_crtc *crtc,
4256 struct drm_display_mode *mode,
4257 struct drm_display_mode *adjusted_mode,
4258 intel_clock_t *clock, intel_clock_t *reduced_clock,
2a8f64ca 4259 int num_connectors)
a0c4da24
JB		 4260{
4261 struct drm_device *dev = crtc->dev;
4262 struct drm_i915_private *dev_priv = dev->dev_private;
4263 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4264 int pipe = intel_crtc->pipe;
4265 u32 dpll, mdiv, pdiv;
4266 u32 bestn, bestm1, bestm2, bestp1, bestp2;
2a8f64ca
VP		 4267 bool is_sdvo;
4268 u32 temp;
4269
4270 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4271 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
a0c4da24 4272
2a8f64ca
VP		 4273 dpll = DPLL_VGA_MODE_DIS;
4274 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4275 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4276 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4277
4278 I915_WRITE(DPLL(pipe), dpll);
4279 POSTING_READ(DPLL(pipe));
a0c4da24
JB		 4280
4281 bestn = clock->n;
4282 bestm1 = clock->m1;
4283 bestm2 = clock->m2;
4284 bestp1 = clock->p1;
4285 bestp2 = clock->p2;
4286
2a8f64ca
VP		 4287 /*
4288 * In Valleyview PLL and program lane counter registers are exposed
4289 * through DPIO interface
4290 */
a0c4da24
JB		 4291 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4292 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4293 mdiv |= ((bestn << DPIO_N_SHIFT));
4294 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4295 mdiv |= (1 << DPIO_K_SHIFT);
4296 mdiv |= DPIO_ENABLE_CALIBRATION;
4297 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4298
4299 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4300
2a8f64ca 4301 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
a0c4da24 4302 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
2a8f64ca
VP		 4303 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4304 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
a0c4da24
JB		 4305 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4306
2a8f64ca 4307 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
a0c4da24
JB		 4308
4309 dpll |= DPLL_VCO_ENABLE;
4310 I915_WRITE(DPLL(pipe), dpll);
4311 POSTING_READ(DPLL(pipe));
4312 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4313 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4314
2a8f64ca
VP		 4315 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4316
4317 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4318 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4319
4320 I915_WRITE(DPLL(pipe), dpll);
4321
4322 /* Wait for the clocks to stabilize. */
4323 POSTING_READ(DPLL(pipe));
4324 udelay(150);
a0c4da24 4325
2a8f64ca
VP		 4326 temp = 0;
4327 if (is_sdvo) {
4328 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
a0c4da24
JB		 4329 if (temp > 1)
4330 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4331 else
4332 temp = 0;
a0c4da24 4333 }
2a8f64ca
VP		 4334 I915_WRITE(DPLL_MD(pipe), temp);
4335 POSTING_READ(DPLL_MD(pipe));
a0c4da24 4336
2a8f64ca
VP		 4337 /* Now program lane control registers */
4338 if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4339 || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4340 {
4341 temp = 0x1000C4;
4342 if(pipe == 1)
4343 temp |= (1 << 21);
4344 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4345 }
4346 if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4347 {
4348 temp = 0x1000C4;
4349 if(pipe == 1)
4350 temp |= (1 << 21);
4351 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4352 }
a0c4da24
JB		 4353}
4354
eb1cbe48
DV		 4355static void i9xx_update_pll(struct drm_crtc *crtc,
4356 struct drm_display_mode *mode,
4357 struct drm_display_mode *adjusted_mode,
4358 intel_clock_t *clock, intel_clock_t *reduced_clock,
4359 int num_connectors)
4360{
4361 struct drm_device *dev = crtc->dev;
4362 struct drm_i915_private *dev_priv = dev->dev_private;
4363 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4364 int pipe = intel_crtc->pipe;
4365 u32 dpll;
4366 bool is_sdvo;
4367
2a8f64ca
VP		 4368 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4369
eb1cbe48
DV		 4370 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4371 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4372
4373 dpll = DPLL_VGA_MODE_DIS;
4374
4375 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4376 dpll |= DPLLB_MODE_LVDS;
4377 else
4378 dpll |= DPLLB_MODE_DAC_SERIAL;
4379 if (is_sdvo) {
4380 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4381 if (pixel_multiplier > 1) {
4382 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4383 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4384 }
4385 dpll |= DPLL_DVO_HIGH_SPEED;
4386 }
4387 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4388 dpll |= DPLL_DVO_HIGH_SPEED;
4389
4390 /* compute bitmask from p1 value */
4391 if (IS_PINEVIEW(dev))
4392 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4393 else {
4394 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4395 if (IS_G4X(dev) && reduced_clock)
4396 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4397 }
4398 switch (clock->p2) {
4399 case 5:
4400 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4401 break;
4402 case 7:
4403 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4404 break;
4405 case 10:
4406 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4407 break;
4408 case 14:
4409 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4410 break;
4411 }
4412 if (INTEL_INFO(dev)->gen >= 4)
4413 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4414
4415 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4416 dpll |= PLL_REF_INPUT_TVCLKINBC;
4417 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4418 /* XXX: just matching BIOS for now */
4419 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4420 dpll |= 3;
4421 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4422 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4423 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4424 else
4425 dpll |= PLL_REF_INPUT_DREFCLK;
4426
4427 dpll |= DPLL_VCO_ENABLE;
4428 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4429 POSTING_READ(DPLL(pipe));
4430 udelay(150);
4431
4432 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4433 * This is an exception to the general rule that mode_set doesn't turn
4434 * things on.
4435 */
4436 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4437 intel_update_lvds(crtc, clock, adjusted_mode);
4438
4439 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4440 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4441
4442 I915_WRITE(DPLL(pipe), dpll);
4443
4444 /* Wait for the clocks to stabilize. */
4445 POSTING_READ(DPLL(pipe));
4446 udelay(150);
4447
4448 if (INTEL_INFO(dev)->gen >= 4) {
4449 u32 temp = 0;
4450 if (is_sdvo) {
4451 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4452 if (temp > 1)
4453 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4454 else
4455 temp = 0;
4456 }
4457 I915_WRITE(DPLL_MD(pipe), temp);
4458 } else {
4459 /* The pixel multiplier can only be updated once the
4460 * DPLL is enabled and the clocks are stable.
4461 *
4462 * So write it again.
4463 */
4464 I915_WRITE(DPLL(pipe), dpll);
4465 }
4466}
4467
4468static void i8xx_update_pll(struct drm_crtc *crtc,
4469 struct drm_display_mode *adjusted_mode,
2a8f64ca 4470 intel_clock_t *clock, intel_clock_t *reduced_clock,
eb1cbe48
DV		 4471 int num_connectors)
4472{
4473 struct drm_device *dev = crtc->dev;
4474 struct drm_i915_private *dev_priv = dev->dev_private;
4475 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4476 int pipe = intel_crtc->pipe;
4477 u32 dpll;
4478
2a8f64ca
VP		 4479 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4480
eb1cbe48
DV		 4481 dpll = DPLL_VGA_MODE_DIS;
4482
4483 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4484 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4485 } else {
4486 if (clock->p1 == 2)
4487 dpll |= PLL_P1_DIVIDE_BY_TWO;
4488 else
4489 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4490 if (clock->p2 == 4)
4491 dpll |= PLL_P2_DIVIDE_BY_4;
4492 }
4493
4494 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4495 /* XXX: just matching BIOS for now */
4496 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4497 dpll |= 3;
4498 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4499 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4500 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4501 else
4502 dpll |= PLL_REF_INPUT_DREFCLK;
4503
4504 dpll |= DPLL_VCO_ENABLE;
4505 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4506 POSTING_READ(DPLL(pipe));
4507 udelay(150);
4508
eb1cbe48
DV		 4509 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4510 * This is an exception to the general rule that mode_set doesn't turn
4511 * things on.
4512 */
4513 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4514 intel_update_lvds(crtc, clock, adjusted_mode);
4515
5b5896e4
DV		 4516 I915_WRITE(DPLL(pipe), dpll);
4517
4518 /* Wait for the clocks to stabilize. */
4519 POSTING_READ(DPLL(pipe));
4520 udelay(150);
4521
eb1cbe48
DV		 4522 /* The pixel multiplier can only be updated once the
4523 * DPLL is enabled and the clocks are stable.
4524 *
4525 * So write it again.
4526 */
4527 I915_WRITE(DPLL(pipe), dpll);
4528}
4529
b0e77b9c
PZ		 4530static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4531 struct drm_display_mode *mode,
4532 struct drm_display_mode *adjusted_mode)
4533{
4534 struct drm_device *dev = intel_crtc->base.dev;
4535 struct drm_i915_private *dev_priv = dev->dev_private;
4536 enum pipe pipe = intel_crtc->pipe;
fe2b8f9d 4537 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
b0e77b9c
PZ		 4538 uint32_t vsyncshift;
4539
4540 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4541 /* the chip adds 2 halflines automatically */
4542 adjusted_mode->crtc_vtotal -= 1;
4543 adjusted_mode->crtc_vblank_end -= 1;
4544 vsyncshift = adjusted_mode->crtc_hsync_start
4545 - adjusted_mode->crtc_htotal / 2;
4546 } else {
4547 vsyncshift = 0;
4548 }
4549
4550 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4551 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4552
fe2b8f9d 4553 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4554 (adjusted_mode->crtc_hdisplay - 1) |
4555 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4556 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4557 (adjusted_mode->crtc_hblank_start - 1) |
4558 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4559 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4560 (adjusted_mode->crtc_hsync_start - 1) |
4561 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4562
fe2b8f9d 4563 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4564 (adjusted_mode->crtc_vdisplay - 1) |
4565 ((adjusted_mode->crtc_vtotal - 1) << 16));
fe2b8f9d 4566 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c
PZ		 4567 (adjusted_mode->crtc_vblank_start - 1) |
4568 ((adjusted_mode->crtc_vblank_end - 1) << 16));
fe2b8f9d 4569 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4570 (adjusted_mode->crtc_vsync_start - 1) |
4571 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4572
b5e508d4
PZ		 4573 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4574 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4575 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4576 * bits. */
4577 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4578 (pipe == PIPE_B || pipe == PIPE_C))
4579 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4580
b0e77b9c
PZ		 4581 /* pipesrc controls the size that is scaled from, which should
4582 * always be the user's requested size.
4583 */
4584 I915_WRITE(PIPESRC(pipe),
4585 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4586}
4587
f564048e
EA		 4588static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4589 struct drm_display_mode *mode,
4590 struct drm_display_mode *adjusted_mode,
4591 int x, int y,
94352cf9 4592 struct drm_framebuffer *fb)
79e53945
JB		 4593{
4594 struct drm_device *dev = crtc->dev;
4595 struct drm_i915_private *dev_priv = dev->dev_private;
4596 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4597 int pipe = intel_crtc->pipe;
80824003 4598 int plane = intel_crtc->plane;
c751ce4f 4599 int refclk, num_connectors = 0;
652c393a 4600 intel_clock_t clock, reduced_clock;
b0e77b9c 4601 u32 dspcntr, pipeconf;
eb1cbe48
DV		 4602 bool ok, has_reduced_clock = false, is_sdvo = false;
4603 bool is_lvds = false, is_tv = false, is_dp = false;
5eddb70b 4604 struct intel_encoder *encoder;
d4906093 4605 const intel_limit_t *limit;
5c3b82e2 4606 int ret;
79e53945 4607
6c2b7c12 4608 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4609 switch (encoder->type) {
79e53945
JB		 4610 case INTEL_OUTPUT_LVDS:
4611 is_lvds = true;
4612 break;
4613 case INTEL_OUTPUT_SDVO:
7d57382e 4614 case INTEL_OUTPUT_HDMI:
79e53945 4615 is_sdvo = true;
5eddb70b 4616 if (encoder->needs_tv_clock)
e2f0ba97 4617 is_tv = true;
79e53945 4618 break;
79e53945
JB		 4619 case INTEL_OUTPUT_TVOUT:
4620 is_tv = true;
4621 break;
a4fc5ed6
KP		 4622 case INTEL_OUTPUT_DISPLAYPORT:
4623 is_dp = true;
4624 break;
79e53945 4625 }
43565a06 4626
c751ce4f 4627 num_connectors++;
79e53945
JB		 4628 }
4629
c65d77d8 4630 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4631
d4906093
ML		 4632 /*
4633 * Returns a set of divisors for the desired target clock with the given
4634 * refclk, or FALSE. The returned values represent the clock equation:
4635 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4636 */
1b894b59 4637 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4638 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4639 &clock);
79e53945
JB		 4640 if (!ok) {
4641 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4642 return -EINVAL;
79e53945
JB		 4643 }
4644
cda4b7d3 4645 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4646 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4647
ddc9003c 4648 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4649 /*
4650 * Ensure we match the reduced clock's P to the target clock.
4651 * If the clocks don't match, we can't switch the display clock
4652 * by using the FP0/FP1. In such case we will disable the LVDS
4653 * downclock feature.
4654 */
ddc9003c 4655 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4656 dev_priv->lvds_downclock,
4657 refclk,
cec2f356 4658 &clock,
5eddb70b 4659 &reduced_clock);
7026d4ac
ZW		 4660 }
4661
c65d77d8
JB		 4662 if (is_sdvo && is_tv)
4663 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
7026d4ac 4664
eb1cbe48 4665 if (IS_GEN2(dev))
2a8f64ca
VP		 4666 i8xx_update_pll(crtc, adjusted_mode, &clock,
4667 has_reduced_clock ? &reduced_clock : NULL,
4668 num_connectors);
a0c4da24 4669 else if (IS_VALLEYVIEW(dev))
2a8f64ca
VP		 4670 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4671 has_reduced_clock ? &reduced_clock : NULL,
4672 num_connectors);
79e53945 4673 else
eb1cbe48
DV		 4674 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4675 has_reduced_clock ? &reduced_clock : NULL,
4676 num_connectors);
79e53945
JB		 4677
4678 /* setup pipeconf */
5eddb70b 4679 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4680
4681 /* Set up the display plane register */
4682 dspcntr = DISPPLANE_GAMMA_ENABLE;
4683
929c77fb
EA		 4684 if (pipe == 0)
4685 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4686 else
4687 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 4688
a6c45cf0 4689 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 4690 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4691 * core speed.
4692 *
4693 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4694 * pipe == 0 check?
4695 */
e70236a8
JB		 4696 if (mode->clock >
4697 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 4698 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 4699 else
5eddb70b 4700 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 4701 }
4702
3b5c78a3
AJ		 4703 /* default to 8bpc */
4704 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4705 if (is_dp) {
0c96c65b 4706 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3b5c78a3
AJ		 4707 pipeconf |= PIPECONF_BPP_6 |
4708 PIPECONF_DITHER_EN |
4709 PIPECONF_DITHER_TYPE_SP;
4710 }
4711 }
4712
19c03924
GB		 4713 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4714 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4715 pipeconf |= PIPECONF_BPP_6 |
4716 PIPECONF_ENABLE |
4717 I965_PIPECONF_ACTIVE;
4718 }
4719 }
4720
28c97730 4721 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4722 drm_mode_debug_printmodeline(mode);
4723
a7516a05
JB		 4724 if (HAS_PIPE_CXSR(dev)) {
4725 if (intel_crtc->lowfreq_avail) {
28c97730 4726 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a 4727 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
a7516a05 4728 } else {
28c97730 4729 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 4730 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4731 }
4732 }
4733
617cf884 4734 pipeconf &= ~PIPECONF_INTERLACE_MASK;
dbb02575 4735 if (!IS_GEN2(dev) &&
b0e77b9c 4736 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
734b4157 4737 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
b0e77b9c 4738 else
617cf884 4739 pipeconf |= PIPECONF_PROGRESSIVE;
734b4157 4740
b0e77b9c 4741 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b
CW		 4742
4743 /* pipesrc and dspsize control the size that is scaled from,
4744 * which should always be the user's requested size.
79e53945 4745 */
929c77fb
EA		 4746 I915_WRITE(DSPSIZE(plane),
4747 ((mode->vdisplay - 1) << 16) |
4748 (mode->hdisplay - 1));
4749 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4750
f564048e
EA		 4751 I915_WRITE(PIPECONF(pipe), pipeconf);
4752 POSTING_READ(PIPECONF(pipe));
929c77fb 4753 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 4754
4755 intel_wait_for_vblank(dev, pipe);
4756
f564048e
EA		 4757 I915_WRITE(DSPCNTR(plane), dspcntr);
4758 POSTING_READ(DSPCNTR(plane));
4759
94352cf9 4760 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4761
4762 intel_update_watermarks(dev);
4763
f564048e
EA		 4764 return ret;
4765}
4766
9fb526db
KP		 4767/*
4768 * Initialize reference clocks when the driver loads
4769 */
4770void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4771{
4772 struct drm_i915_private *dev_priv = dev->dev_private;
4773 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4774 struct intel_encoder *encoder;
13d83a67
JB		 4775 u32 temp;
4776 bool has_lvds = false;
199e5d79
KP		 4777 bool has_cpu_edp = false;
4778 bool has_pch_edp = false;
4779 bool has_panel = false;
99eb6a01
KP		 4780 bool has_ck505 = false;
4781 bool can_ssc = false;
13d83a67
JB		 4782
4783 /* We need to take the global config into account */
199e5d79
KP		 4784 list_for_each_entry(encoder, &mode_config->encoder_list,
4785 base.head) {
4786 switch (encoder->type) {
4787 case INTEL_OUTPUT_LVDS:
4788 has_panel = true;
4789 has_lvds = true;
4790 break;
4791 case INTEL_OUTPUT_EDP:
4792 has_panel = true;
4793 if (intel_encoder_is_pch_edp(&encoder->base))
4794 has_pch_edp = true;
4795 else
4796 has_cpu_edp = true;
4797 break;
13d83a67
JB		 4798 }
4799 }
4800
99eb6a01
KP		 4801 if (HAS_PCH_IBX(dev)) {
4802 has_ck505 = dev_priv->display_clock_mode;
4803 can_ssc = has_ck505;
4804 } else {
4805 has_ck505 = false;
4806 can_ssc = true;
4807 }
4808
4809 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4810 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4811 has_ck505);
13d83a67
JB		 4812
4813 /* Ironlake: try to setup display ref clock before DPLL
4814 * enabling. This is only under driver's control after
4815 * PCH B stepping, previous chipset stepping should be
4816 * ignoring this setting.
4817 */
4818 temp = I915_READ(PCH_DREF_CONTROL);
4819 /* Always enable nonspread source */
4820 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 4821
99eb6a01
KP		 4822 if (has_ck505)
4823 temp |= DREF_NONSPREAD_CK505_ENABLE;
4824 else
4825 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 4826
199e5d79
KP		 4827 if (has_panel) {
4828 temp &= ~DREF_SSC_SOURCE_MASK;
4829 temp |= DREF_SSC_SOURCE_ENABLE;
13d83a67 4830
199e5d79 4831 /* SSC must be turned on before enabling the CPU output */
99eb6a01 4832 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4833 DRM_DEBUG_KMS("Using SSC on panel\n");
13d83a67 4834 temp |= DREF_SSC1_ENABLE;
e77166b5
DV		 4835 } else
4836 temp &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 4837
4838 /* Get SSC going before enabling the outputs */
4839 I915_WRITE(PCH_DREF_CONTROL, temp);
4840 POSTING_READ(PCH_DREF_CONTROL);
4841 udelay(200);
4842
13d83a67
JB		 4843 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4844
4845 /* Enable CPU source on CPU attached eDP */
199e5d79 4846 if (has_cpu_edp) {
99eb6a01 4847 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4848 DRM_DEBUG_KMS("Using SSC on eDP\n");
13d83a67 4849 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 4850 }
13d83a67
JB		 4851 else
4852 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79
KP		 4853 } else
4854 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4855
4856 I915_WRITE(PCH_DREF_CONTROL, temp);
4857 POSTING_READ(PCH_DREF_CONTROL);
4858 udelay(200);
4859 } else {
4860 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4861
4862 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4863
4864 /* Turn off CPU output */
4865 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4866
4867 I915_WRITE(PCH_DREF_CONTROL, temp);
4868 POSTING_READ(PCH_DREF_CONTROL);
4869 udelay(200);
4870
4871 /* Turn off the SSC source */
4872 temp &= ~DREF_SSC_SOURCE_MASK;
4873 temp |= DREF_SSC_SOURCE_DISABLE;
4874
4875 /* Turn off SSC1 */
4876 temp &= ~ DREF_SSC1_ENABLE;
4877
13d83a67
JB		 4878 I915_WRITE(PCH_DREF_CONTROL, temp);
4879 POSTING_READ(PCH_DREF_CONTROL);
4880 udelay(200);
4881 }
4882}
4883
d9d444cb
JB		 4884static int ironlake_get_refclk(struct drm_crtc *crtc)
4885{
4886 struct drm_device *dev = crtc->dev;
4887 struct drm_i915_private *dev_priv = dev->dev_private;
4888 struct intel_encoder *encoder;
d9d444cb
JB		 4889 struct intel_encoder *edp_encoder = NULL;
4890 int num_connectors = 0;
4891 bool is_lvds = false;
4892
6c2b7c12 4893 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 4894 switch (encoder->type) {
4895 case INTEL_OUTPUT_LVDS:
4896 is_lvds = true;
4897 break;
4898 case INTEL_OUTPUT_EDP:
4899 edp_encoder = encoder;
4900 break;
4901 }
4902 num_connectors++;
4903 }
4904
4905 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4906 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4907 dev_priv->lvds_ssc_freq);
4908 return dev_priv->lvds_ssc_freq * 1000;
4909 }
4910
4911 return 120000;
4912}
4913
c8203565
PZ		 4914static void ironlake_set_pipeconf(struct drm_crtc *crtc,
4915 struct drm_display_mode *adjusted_mode,
4916 bool dither)
4917{
4918 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4919 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4920 int pipe = intel_crtc->pipe;
4921 uint32_t val;
4922
4923 val = I915_READ(PIPECONF(pipe));
4924
4925 val &= ~PIPE_BPC_MASK;
4926 switch (intel_crtc->bpp) {
4927 case 18:
4928 val |= PIPE_6BPC;
4929 break;
4930 case 24:
4931 val |= PIPE_8BPC;
4932 break;
4933 case 30:
4934 val |= PIPE_10BPC;
4935 break;
4936 case 36:
4937 val |= PIPE_12BPC;
4938 break;
4939 default:
cc769b62
PZ		 4940 /* Case prevented by intel_choose_pipe_bpp_dither. */
4941 BUG();
c8203565
PZ		 4942 }
4943
4944 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4945 if (dither)
4946 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
4947
4948 val &= ~PIPECONF_INTERLACE_MASK;
4949 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4950 val |= PIPECONF_INTERLACED_ILK;
4951 else
4952 val |= PIPECONF_PROGRESSIVE;
4953
4954 I915_WRITE(PIPECONF(pipe), val);
4955 POSTING_READ(PIPECONF(pipe));
4956}
4957
ee2b0b38
PZ		 4958static void haswell_set_pipeconf(struct drm_crtc *crtc,
4959 struct drm_display_mode *adjusted_mode,
4960 bool dither)
4961{
4962 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4963 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
702e7a56 4964 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
ee2b0b38
PZ		 4965 uint32_t val;
4966
702e7a56 4967 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 4968
4969 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4970 if (dither)
4971 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
4972
4973 val &= ~PIPECONF_INTERLACE_MASK_HSW;
4974 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4975 val |= PIPECONF_INTERLACED_ILK;
4976 else
4977 val |= PIPECONF_PROGRESSIVE;
4978
702e7a56
PZ		 4979 I915_WRITE(PIPECONF(cpu_transcoder), val);
4980 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 4981}
4982
6591c6e4
PZ		 4983static bool ironlake_compute_clocks(struct drm_crtc *crtc,
4984 struct drm_display_mode *adjusted_mode,
4985 intel_clock_t *clock,
4986 bool *has_reduced_clock,
4987 intel_clock_t *reduced_clock)
4988{
4989 struct drm_device *dev = crtc->dev;
4990 struct drm_i915_private *dev_priv = dev->dev_private;
4991 struct intel_encoder *intel_encoder;
4992 int refclk;
4993 const intel_limit_t *limit;
4994 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
4995
4996 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4997 switch (intel_encoder->type) {
4998 case INTEL_OUTPUT_LVDS:
4999 is_lvds = true;
5000 break;
5001 case INTEL_OUTPUT_SDVO:
5002 case INTEL_OUTPUT_HDMI:
5003 is_sdvo = true;
5004 if (intel_encoder->needs_tv_clock)
5005 is_tv = true;
5006 break;
5007 case INTEL_OUTPUT_TVOUT:
5008 is_tv = true;
5009 break;
5010 }
5011 }
5012
5013 refclk = ironlake_get_refclk(crtc);
5014
5015 /*
5016 * Returns a set of divisors for the desired target clock with the given
5017 * refclk, or FALSE. The returned values represent the clock equation:
5018 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5019 */
5020 limit = intel_limit(crtc, refclk);
5021 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5022 clock);
5023 if (!ret)
5024 return false;
5025
5026 if (is_lvds && dev_priv->lvds_downclock_avail) {
5027 /*
5028 * Ensure we match the reduced clock's P to the target clock.
5029 * If the clocks don't match, we can't switch the display clock
5030 * by using the FP0/FP1. In such case we will disable the LVDS
5031 * downclock feature.
5032 */
5033 *has_reduced_clock = limit->find_pll(limit, crtc,
5034 dev_priv->lvds_downclock,
5035 refclk,
5036 clock,
5037 reduced_clock);
5038 }
5039
5040 if (is_sdvo && is_tv)
5041 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5042
5043 return true;
5044}
5045
01a415fd
DV		 5046static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5047{
5048 struct drm_i915_private *dev_priv = dev->dev_private;
5049 uint32_t temp;
5050
5051 temp = I915_READ(SOUTH_CHICKEN1);
5052 if (temp & FDI_BC_BIFURCATION_SELECT)
5053 return;
5054
5055 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5056 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5057
5058 temp |= FDI_BC_BIFURCATION_SELECT;
5059 DRM_DEBUG_KMS("enabling fdi C rx\n");
5060 I915_WRITE(SOUTH_CHICKEN1, temp);
5061 POSTING_READ(SOUTH_CHICKEN1);
5062}
5063
5064static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5065{
5066 struct drm_device *dev = intel_crtc->base.dev;
5067 struct drm_i915_private *dev_priv = dev->dev_private;
5068 struct intel_crtc *pipe_B_crtc =
5069 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5070
5071 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5072 intel_crtc->pipe, intel_crtc->fdi_lanes);
5073 if (intel_crtc->fdi_lanes > 4) {
5074 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5075 intel_crtc->pipe, intel_crtc->fdi_lanes);
5076 /* Clamp lanes to avoid programming the hw with bogus values. */
5077 intel_crtc->fdi_lanes = 4;
5078
5079 return false;
5080 }
5081
5082 if (dev_priv->num_pipe == 2)
5083 return true;
5084
5085 switch (intel_crtc->pipe) {
5086 case PIPE_A:
5087 return true;
5088 case PIPE_B:
5089 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5090 intel_crtc->fdi_lanes > 2) {
5091 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5092 intel_crtc->pipe, intel_crtc->fdi_lanes);
5093 /* Clamp lanes to avoid programming the hw with bogus values. */
5094 intel_crtc->fdi_lanes = 2;
5095
5096 return false;
5097 }
5098
5099 if (intel_crtc->fdi_lanes > 2)
5100 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5101 else
5102 cpt_enable_fdi_bc_bifurcation(dev);
5103
5104 return true;
5105 case PIPE_C:
5106 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5107 if (intel_crtc->fdi_lanes > 2) {
5108 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5109 intel_crtc->pipe, intel_crtc->fdi_lanes);
5110 /* Clamp lanes to avoid programming the hw with bogus values. */
5111 intel_crtc->fdi_lanes = 2;
5112
5113 return false;
5114 }
5115 } else {
5116 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5117 return false;
5118 }
5119
5120 cpt_enable_fdi_bc_bifurcation(dev);
5121
5122 return true;
5123 default:
5124 BUG();
5125 }
5126}
5127
f48d8f23
PZ		 5128static void ironlake_set_m_n(struct drm_crtc *crtc,
5129 struct drm_display_mode *mode,
5130 struct drm_display_mode *adjusted_mode)
5131{
5132 struct drm_device *dev = crtc->dev;
5133 struct drm_i915_private *dev_priv = dev->dev_private;
5134 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
afe2fcf5 5135 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
f48d8f23
PZ		 5136 struct intel_encoder *intel_encoder, *edp_encoder = NULL;
5137 struct fdi_m_n m_n = {0};
5138 int target_clock, pixel_multiplier, lane, link_bw;
5139 bool is_dp = false, is_cpu_edp = false;
5140
5141 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5142 switch (intel_encoder->type) {
5143 case INTEL_OUTPUT_DISPLAYPORT:
5144 is_dp = true;
5145 break;
5146 case INTEL_OUTPUT_EDP:
5147 is_dp = true;
5148 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5149 is_cpu_edp = true;
5150 edp_encoder = intel_encoder;
5151 break;
5152 }
5153 }
5154
5155 /* FDI link */
5156 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5157 lane = 0;
5158 /* CPU eDP doesn't require FDI link, so just set DP M/N
5159 according to current link config */
5160 if (is_cpu_edp) {
5161 intel_edp_link_config(edp_encoder, &lane, &link_bw);
5162 } else {
5163 /* FDI is a binary signal running at ~2.7GHz, encoding
5164 * each output octet as 10 bits. The actual frequency
5165 * is stored as a divider into a 100MHz clock, and the
5166 * mode pixel clock is stored in units of 1KHz.
5167 * Hence the bw of each lane in terms of the mode signal
5168 * is:
5169 */
5170 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5171 }
5172
5173 /* [e]DP over FDI requires target mode clock instead of link clock. */
5174 if (edp_encoder)
5175 target_clock = intel_edp_target_clock(edp_encoder, mode);
5176 else if (is_dp)
5177 target_clock = mode->clock;
5178 else
5179 target_clock = adjusted_mode->clock;
5180
5181 if (!lane) {
5182 /*
5183 * Account for spread spectrum to avoid
5184 * oversubscribing the link. Max center spread
5185 * is 2.5%; use 5% for safety's sake.
5186 */
5187 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5188 lane = bps / (link_bw * 8) + 1;
5189 }
5190
5191 intel_crtc->fdi_lanes = lane;
5192
5193 if (pixel_multiplier > 1)
5194 link_bw *= pixel_multiplier;
5195 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5196 &m_n);
5197
afe2fcf5
PZ		 5198 I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5199 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5200 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5201 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
f48d8f23
PZ		 5202}
5203
de13a2e3
PZ		 5204static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5205 struct drm_display_mode *adjusted_mode,
5206 intel_clock_t *clock, u32 fp)
79e53945 5207{
de13a2e3 5208 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5209 struct drm_device *dev = crtc->dev;
5210 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5211 struct intel_encoder *intel_encoder;
5212 uint32_t dpll;
5213 int factor, pixel_multiplier, num_connectors = 0;
5214 bool is_lvds = false, is_sdvo = false, is_tv = false;
5215 bool is_dp = false, is_cpu_edp = false;
79e53945 5216
de13a2e3
PZ		 5217 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5218 switch (intel_encoder->type) {
79e53945
JB		 5219 case INTEL_OUTPUT_LVDS:
5220 is_lvds = true;
5221 break;
5222 case INTEL_OUTPUT_SDVO:
7d57382e 5223 case INTEL_OUTPUT_HDMI:
79e53945 5224 is_sdvo = true;
de13a2e3 5225 if (intel_encoder->needs_tv_clock)
e2f0ba97 5226 is_tv = true;
79e53945 5227 break;
79e53945
JB		 5228 case INTEL_OUTPUT_TVOUT:
5229 is_tv = true;
5230 break;
a4fc5ed6
KP		 5231 case INTEL_OUTPUT_DISPLAYPORT:
5232 is_dp = true;
5233 break;
32f9d658 5234 case INTEL_OUTPUT_EDP:
e3aef172 5235 is_dp = true;
de13a2e3 5236 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
e3aef172 5237 is_cpu_edp = true;
32f9d658 5238 break;
79e53945 5239 }
43565a06 5240
c751ce4f 5241 num_connectors++;
79e53945
JB		 5242 }
5243
c1858123 5244 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5245 factor = 21;
5246 if (is_lvds) {
5247 if ((intel_panel_use_ssc(dev_priv) &&
5248 dev_priv->lvds_ssc_freq == 100) ||
5249 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5250 factor = 25;
5251 } else if (is_sdvo && is_tv)
5252 factor = 20;
c1858123 5253
de13a2e3 5254 if (clock->m < factor * clock->n)
8febb297 5255 fp |= FP_CB_TUNE;
2c07245f 5256
5eddb70b 5257 dpll = 0;
2c07245f 5258
a07d6787
EA		 5259 if (is_lvds)
5260 dpll |= DPLLB_MODE_LVDS;
5261 else
5262 dpll |= DPLLB_MODE_DAC_SERIAL;
5263 if (is_sdvo) {
de13a2e3 5264 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
a07d6787
EA		 5265 if (pixel_multiplier > 1) {
5266 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 5267 }
a07d6787
EA		 5268 dpll |= DPLL_DVO_HIGH_SPEED;
5269 }
e3aef172 5270 if (is_dp && !is_cpu_edp)
a07d6787 5271 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5272
a07d6787 5273 /* compute bitmask from p1 value */
de13a2e3 5274 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5275 /* also FPA1 */
de13a2e3 5276 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5277
de13a2e3 5278 switch (clock->p2) {
a07d6787
EA		 5279 case 5:
5280 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5281 break;
5282 case 7:
5283 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5284 break;
5285 case 10:
5286 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5287 break;
5288 case 14:
5289 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5290 break;
79e53945
JB		 5291 }
5292
43565a06
KH		 5293 if (is_sdvo && is_tv)
5294 dpll |= PLL_REF_INPUT_TVCLKINBC;
5295 else if (is_tv)
79e53945 5296 /* XXX: just matching BIOS for now */
43565a06 5297 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5298 dpll |= 3;
a7615030 5299 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5300 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5301 else
5302 dpll |= PLL_REF_INPUT_DREFCLK;
5303
de13a2e3
PZ		 5304 return dpll;
5305}
5306
5307static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5308 struct drm_display_mode *mode,
5309 struct drm_display_mode *adjusted_mode,
5310 int x, int y,
5311 struct drm_framebuffer *fb)
5312{
5313 struct drm_device *dev = crtc->dev;
5314 struct drm_i915_private *dev_priv = dev->dev_private;
5315 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5316 int pipe = intel_crtc->pipe;
5317 int plane = intel_crtc->plane;
5318 int num_connectors = 0;
5319 intel_clock_t clock, reduced_clock;
5320 u32 dpll, fp = 0, fp2 = 0;
e2f12b07
PZ		 5321 bool ok, has_reduced_clock = false;
5322 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
de13a2e3
PZ		 5323 struct intel_encoder *encoder;
5324 u32 temp;
5325 int ret;
01a415fd 5326 bool dither, fdi_config_ok;
de13a2e3
PZ		 5327
5328 for_each_encoder_on_crtc(dev, crtc, encoder) {
5329 switch (encoder->type) {
5330 case INTEL_OUTPUT_LVDS:
5331 is_lvds = true;
5332 break;
de13a2e3
PZ		 5333 case INTEL_OUTPUT_DISPLAYPORT:
5334 is_dp = true;
5335 break;
5336 case INTEL_OUTPUT_EDP:
5337 is_dp = true;
e2f12b07 5338 if (!intel_encoder_is_pch_edp(&encoder->base))
de13a2e3
PZ		 5339 is_cpu_edp = true;
5340 break;
5341 }
5342
5343 num_connectors++;
5344 }
5345
5dc5298b
PZ		 5346 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5347 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5348
de13a2e3
PZ		 5349 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5350 &has_reduced_clock, &reduced_clock);
5351 if (!ok) {
5352 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5353 return -EINVAL;
5354 }
5355
5356 /* Ensure that the cursor is valid for the new mode before changing... */
5357 intel_crtc_update_cursor(crtc, true);
5358
5359 /* determine panel color depth */
c8241969
JN		 5360 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5361 adjusted_mode);
de13a2e3
PZ		 5362 if (is_lvds && dev_priv->lvds_dither)
5363 dither = true;
5364
5365 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5366 if (has_reduced_clock)
5367 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5368 reduced_clock.m2;
5369
5370 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
5371
f7cb34d4 5372 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 5373 drm_mode_debug_printmodeline(mode);
5374
5dc5298b
PZ		 5375 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5376 if (!is_cpu_edp) {
ee7b9f93 5377 struct intel_pch_pll *pll;
4b645f14 5378
ee7b9f93
JB		 5379 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5380 if (pll == NULL) {
5381 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5382 pipe);
4b645f14
JB		 5383 return -EINVAL;
5384 }
ee7b9f93
JB		 5385 } else
5386 intel_put_pch_pll(intel_crtc);
79e53945
JB		 5387
5388 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5389 * This is an exception to the general rule that mode_set doesn't turn
5390 * things on.
5391 */
5392 if (is_lvds) {
fae14981 5393 temp = I915_READ(PCH_LVDS);
5eddb70b 5394 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
7885d205
JB		 5395 if (HAS_PCH_CPT(dev)) {
5396 temp &= ~PORT_TRANS_SEL_MASK;
4b645f14 5397 temp |= PORT_TRANS_SEL_CPT(pipe);
7885d205
JB		 5398 } else {
5399 if (pipe == 1)
5400 temp |= LVDS_PIPEB_SELECT;
5401 else
5402 temp &= ~LVDS_PIPEB_SELECT;
5403 }
4b645f14 5404
a3e17eb8 5405 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 5406 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 5407 /* Set the B0-B3 data pairs corresponding to whether we're going to
5408 * set the DPLLs for dual-channel mode or not.
5409 */
5410 if (clock.p2 == 7)
5eddb70b 5411 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 5412 else
5eddb70b 5413 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 5414
5415 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5416 * appropriately here, but we need to look more thoroughly into how
5417 * panels behave in the two modes.
5418 */
284d5df5 5419 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
aa9b500d 5420 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 5421 temp |= LVDS_HSYNC_POLARITY;
aa9b500d 5422 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 5423 temp |= LVDS_VSYNC_POLARITY;
fae14981 5424 I915_WRITE(PCH_LVDS, temp);
79e53945 5425 }
434ed097 5426
e3aef172 5427 if (is_dp && !is_cpu_edp) {
a4fc5ed6 5428 intel_dp_set_m_n(crtc, mode, adjusted_mode);
8febb297 5429 } else {
8db9d77b 5430 /* For non-DP output, clear any trans DP clock recovery setting.*/
9db4a9c7
JB		 5431 I915_WRITE(TRANSDATA_M1(pipe), 0);
5432 I915_WRITE(TRANSDATA_N1(pipe), 0);
5433 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5434 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
8db9d77b 5435 }
79e53945 5436
ee7b9f93
JB		 5437 if (intel_crtc->pch_pll) {
5438 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 5439
32f9d658 5440 /* Wait for the clocks to stabilize. */
ee7b9f93 5441 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 5442 udelay(150);
5443
8febb297
EA		 5444 /* The pixel multiplier can only be updated once the
5445 * DPLL is enabled and the clocks are stable.
5446 *
5447 * So write it again.
5448 */
ee7b9f93 5449 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 5450 }
79e53945 5451
5eddb70b 5452 intel_crtc->lowfreq_avail = false;
ee7b9f93 5453 if (intel_crtc->pch_pll) {
4b645f14 5454 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 5455 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 5456 intel_crtc->lowfreq_avail = true;
4b645f14 5457 } else {
ee7b9f93 5458 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 5459 }
5460 }
5461
b0e77b9c 5462 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
2c07245f 5463
01a415fd
DV		 5464 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5465 * ironlake_check_fdi_lanes. */
f48d8f23 5466 ironlake_set_m_n(crtc, mode, adjusted_mode);
2c07245f 5467
01a415fd
DV		 5468 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
5469
e3aef172 5470 if (is_cpu_edp)
8febb297 5471 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
2c07245f 5472
c8203565 5473 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
79e53945 5474
9d0498a2 5475 intel_wait_for_vblank(dev, pipe);
79e53945 5476
a1f9e77e
PZ		 5477 /* Set up the display plane register */
5478 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5479 POSTING_READ(DSPCNTR(plane));
79e53945 5480
94352cf9 5481 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5482
5483 intel_update_watermarks(dev);
5484
1f8eeabf
ED		 5485 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5486
01a415fd 5487 return fdi_config_ok ? ret : -EINVAL;
79e53945
JB		 5488}
5489
09b4ddf9
PZ		 5490static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5491 struct drm_display_mode *mode,
5492 struct drm_display_mode *adjusted_mode,
5493 int x, int y,
5494 struct drm_framebuffer *fb)
5495{
5496 struct drm_device *dev = crtc->dev;
5497 struct drm_i915_private *dev_priv = dev->dev_private;
5498 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5499 int pipe = intel_crtc->pipe;
5500 int plane = intel_crtc->plane;
5501 int num_connectors = 0;
5502 intel_clock_t clock, reduced_clock;
5dc5298b 5503 u32 dpll = 0, fp = 0, fp2 = 0;
09b4ddf9
PZ		 5504 bool ok, has_reduced_clock = false;
5505 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5506 struct intel_encoder *encoder;
5507 u32 temp;
5508 int ret;
5509 bool dither;
5510
5511 for_each_encoder_on_crtc(dev, crtc, encoder) {
5512 switch (encoder->type) {
5513 case INTEL_OUTPUT_LVDS:
5514 is_lvds = true;
5515 break;
5516 case INTEL_OUTPUT_DISPLAYPORT:
5517 is_dp = true;
5518 break;
5519 case INTEL_OUTPUT_EDP:
5520 is_dp = true;
5521 if (!intel_encoder_is_pch_edp(&encoder->base))
5522 is_cpu_edp = true;
5523 break;
5524 }
5525
5526 num_connectors++;
5527 }
5528
a5c961d1
PZ		 5529 if (is_cpu_edp)
5530 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5531 else
5532 intel_crtc->cpu_transcoder = pipe;
5533
5dc5298b
PZ		 5534 /* We are not sure yet this won't happen. */
5535 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5536 INTEL_PCH_TYPE(dev));
5537
5538 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5539 num_connectors, pipe_name(pipe));
5540
702e7a56 5541 WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
1ce42920
PZ		 5542 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5543
5544 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5545
6441ab5f
PZ		 5546 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5547 return -EINVAL;
5548
5dc5298b
PZ		 5549 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5550 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5551 &has_reduced_clock,
5552 &reduced_clock);
5553 if (!ok) {
5554 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5555 return -EINVAL;
5556 }
09b4ddf9
PZ		 5557 }
5558
5559 /* Ensure that the cursor is valid for the new mode before changing... */
5560 intel_crtc_update_cursor(crtc, true);
5561
5562 /* determine panel color depth */
c8241969
JN		 5563 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5564 adjusted_mode);
09b4ddf9
PZ		 5565 if (is_lvds && dev_priv->lvds_dither)
5566 dither = true;
5567
09b4ddf9
PZ		 5568 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5569 drm_mode_debug_printmodeline(mode);
5570
5dc5298b
PZ		 5571 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5572 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5573 if (has_reduced_clock)
5574 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5575 reduced_clock.m2;
5576
5577 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock,
5578 fp);
5579
5580 /* CPU eDP is the only output that doesn't need a PCH PLL of its
5581 * own on pre-Haswell/LPT generation */
5582 if (!is_cpu_edp) {
5583 struct intel_pch_pll *pll;
5584
5585 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5586 if (pll == NULL) {
5587 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5588 pipe);
5589 return -EINVAL;
5590 }
5591 } else
5592 intel_put_pch_pll(intel_crtc);
09b4ddf9 5593
5dc5298b
PZ		 5594 /* The LVDS pin pair needs to be on before the DPLLs are
5595 * enabled. This is an exception to the general rule that
5596 * mode_set doesn't turn things on.
5597 */
5598 if (is_lvds) {
5599 temp = I915_READ(PCH_LVDS);
5600 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5601 if (HAS_PCH_CPT(dev)) {
5602 temp &= ~PORT_TRANS_SEL_MASK;
5603 temp |= PORT_TRANS_SEL_CPT(pipe);
5604 } else {
5605 if (pipe == 1)
5606 temp |= LVDS_PIPEB_SELECT;
5607 else
5608 temp &= ~LVDS_PIPEB_SELECT;
5609 }
09b4ddf9 5610
5dc5298b
PZ		 5611 /* set the corresponsding LVDS_BORDER bit */
5612 temp |= dev_priv->lvds_border_bits;
5613 /* Set the B0-B3 data pairs corresponding to whether
5614 * we're going to set the DPLLs for dual-channel mode or
5615 * not.
5616 */
5617 if (clock.p2 == 7)
5618 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
09b4ddf9 5619 else
5dc5298b
PZ		 5620 temp &= ~(LVDS_B0B3_POWER_UP |
5621 LVDS_CLKB_POWER_UP);
5622
5623 /* It would be nice to set 24 vs 18-bit mode
5624 * (LVDS_A3_POWER_UP) appropriately here, but we need to
5625 * look more thoroughly into how panels behave in the
5626 * two modes.
5627 */
5628 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5629 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5630 temp |= LVDS_HSYNC_POLARITY;
5631 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5632 temp |= LVDS_VSYNC_POLARITY;
5633 I915_WRITE(PCH_LVDS, temp);
09b4ddf9 5634 }
09b4ddf9
PZ		 5635 }
5636
5637 if (is_dp && !is_cpu_edp) {
5638 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5639 } else {
5dc5298b
PZ		 5640 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5641 /* For non-DP output, clear any trans DP clock recovery
5642 * setting.*/
5643 I915_WRITE(TRANSDATA_M1(pipe), 0);
5644 I915_WRITE(TRANSDATA_N1(pipe), 0);
5645 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5646 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5647 }
09b4ddf9
PZ		 5648 }
5649
5650 intel_crtc->lowfreq_avail = false;
5dc5298b
PZ		 5651 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5652 if (intel_crtc->pch_pll) {
5653 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5654
5655 /* Wait for the clocks to stabilize. */
5656 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5657 udelay(150);
5658
5659 /* The pixel multiplier can only be updated once the
5660 * DPLL is enabled and the clocks are stable.
5661 *
5662 * So write it again.
5663 */
5664 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5665 }
5666
5667 if (intel_crtc->pch_pll) {
5668 if (is_lvds && has_reduced_clock && i915_powersave) {
5669 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5670 intel_crtc->lowfreq_avail = true;
5671 } else {
5672 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5673 }
09b4ddf9
PZ		 5674 }
5675 }
5676
5677 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5678
1eb8dfec
PZ		 5679 if (!is_dp || is_cpu_edp)
5680 ironlake_set_m_n(crtc, mode, adjusted_mode);
09b4ddf9 5681
5dc5298b
PZ		 5682 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5683 if (is_cpu_edp)
5684 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
09b4ddf9 5685
ee2b0b38 5686 haswell_set_pipeconf(crtc, adjusted_mode, dither);
09b4ddf9 5687
09b4ddf9
PZ		 5688 /* Set up the display plane register */
5689 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5690 POSTING_READ(DSPCNTR(plane));
5691
5692 ret = intel_pipe_set_base(crtc, x, y, fb);
5693
5694 intel_update_watermarks(dev);
5695
5696 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5697
5698 return ret;
5699}
5700
f564048e
EA		 5701static int intel_crtc_mode_set(struct drm_crtc *crtc,
5702 struct drm_display_mode *mode,
5703 struct drm_display_mode *adjusted_mode,
5704 int x, int y,
94352cf9 5705 struct drm_framebuffer *fb)
f564048e
EA		 5706{
5707 struct drm_device *dev = crtc->dev;
5708 struct drm_i915_private *dev_priv = dev->dev_private;
0b701d27
EA		 5709 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5710 int pipe = intel_crtc->pipe;
f564048e
EA		 5711 int ret;
5712
0b701d27 5713 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5714
f564048e 5715 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
94352cf9 5716 x, y, fb);
79e53945 5717 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5718
1f803ee5 5719 return ret;
79e53945
JB		 5720}
5721
3a9627f4
WF		 5722static bool intel_eld_uptodate(struct drm_connector *connector,
5723 int reg_eldv, uint32_t bits_eldv,
5724 int reg_elda, uint32_t bits_elda,
5725 int reg_edid)
5726{
5727 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5728 uint8_t *eld = connector->eld;
5729 uint32_t i;
5730
5731 i = I915_READ(reg_eldv);
5732 i &= bits_eldv;
5733
5734 if (!eld[0])
5735 return !i;
5736
5737 if (!i)
5738 return false;
5739
5740 i = I915_READ(reg_elda);
5741 i &= ~bits_elda;
5742 I915_WRITE(reg_elda, i);
5743
5744 for (i = 0; i < eld[2]; i++)
5745 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5746 return false;
5747
5748 return true;
5749}
5750
e0dac65e
WF		 5751static void g4x_write_eld(struct drm_connector *connector,
5752 struct drm_crtc *crtc)
5753{
5754 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5755 uint8_t *eld = connector->eld;
5756 uint32_t eldv;
5757 uint32_t len;
5758 uint32_t i;
5759
5760 i = I915_READ(G4X_AUD_VID_DID);
5761
5762 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5763 eldv = G4X_ELDV_DEVCL_DEVBLC;
5764 else
5765 eldv = G4X_ELDV_DEVCTG;
5766
3a9627f4
WF		 5767 if (intel_eld_uptodate(connector,
5768 G4X_AUD_CNTL_ST, eldv,
5769 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5770 G4X_HDMIW_HDMIEDID))
5771 return;
5772
e0dac65e
WF		 5773 i = I915_READ(G4X_AUD_CNTL_ST);
5774 i &= ~(eldv | G4X_ELD_ADDR);
5775 len = (i >> 9) & 0x1f; /* ELD buffer size */
5776 I915_WRITE(G4X_AUD_CNTL_ST, i);
5777
5778 if (!eld[0])
5779 return;
5780
5781 len = min_t(uint8_t, eld[2], len);
5782 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5783 for (i = 0; i < len; i++)
5784 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5785
5786 i = I915_READ(G4X_AUD_CNTL_ST);
5787 i |= eldv;
5788 I915_WRITE(G4X_AUD_CNTL_ST, i);
5789}
5790
83358c85
WX		 5791static void haswell_write_eld(struct drm_connector *connector,
5792 struct drm_crtc *crtc)
5793{
5794 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5795 uint8_t *eld = connector->eld;
5796 struct drm_device *dev = crtc->dev;
5797 uint32_t eldv;
5798 uint32_t i;
5799 int len;
5800 int pipe = to_intel_crtc(crtc)->pipe;
5801 int tmp;
5802
5803 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5804 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5805 int aud_config = HSW_AUD_CFG(pipe);
5806 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5807
5808
5809 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5810
5811 /* Audio output enable */
5812 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5813 tmp = I915_READ(aud_cntrl_st2);
5814 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5815 I915_WRITE(aud_cntrl_st2, tmp);
5816
5817 /* Wait for 1 vertical blank */
5818 intel_wait_for_vblank(dev, pipe);
5819
5820 /* Set ELD valid state */
5821 tmp = I915_READ(aud_cntrl_st2);
5822 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5823 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5824 I915_WRITE(aud_cntrl_st2, tmp);
5825 tmp = I915_READ(aud_cntrl_st2);
5826 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5827
5828 /* Enable HDMI mode */
5829 tmp = I915_READ(aud_config);
5830 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5831 /* clear N_programing_enable and N_value_index */
5832 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5833 I915_WRITE(aud_config, tmp);
5834
5835 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5836
5837 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5838
5839 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5840 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5841 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5842 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5843 } else
5844 I915_WRITE(aud_config, 0);
5845
5846 if (intel_eld_uptodate(connector,
5847 aud_cntrl_st2, eldv,
5848 aud_cntl_st, IBX_ELD_ADDRESS,
5849 hdmiw_hdmiedid))
5850 return;
5851
5852 i = I915_READ(aud_cntrl_st2);
5853 i &= ~eldv;
5854 I915_WRITE(aud_cntrl_st2, i);
5855
5856 if (!eld[0])
5857 return;
5858
5859 i = I915_READ(aud_cntl_st);
5860 i &= ~IBX_ELD_ADDRESS;
5861 I915_WRITE(aud_cntl_st, i);
5862 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5863 DRM_DEBUG_DRIVER("port num:%d\n", i);
5864
5865 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5866 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5867 for (i = 0; i < len; i++)
5868 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5869
5870 i = I915_READ(aud_cntrl_st2);
5871 i |= eldv;
5872 I915_WRITE(aud_cntrl_st2, i);
5873
5874}
5875
e0dac65e
WF		 5876static void ironlake_write_eld(struct drm_connector *connector,
5877 struct drm_crtc *crtc)
5878{
5879 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5880 uint8_t *eld = connector->eld;
5881 uint32_t eldv;
5882 uint32_t i;
5883 int len;
5884 int hdmiw_hdmiedid;
b6daa025 5885 int aud_config;
e0dac65e
WF		 5886 int aud_cntl_st;
5887 int aud_cntrl_st2;
9b138a83 5888 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 5889
b3f33cbf 5890 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 5891 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
5892 aud_config = IBX_AUD_CFG(pipe);
5893 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 5894 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 5895 } else {
9b138a83
WX		 5896 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
5897 aud_config = CPT_AUD_CFG(pipe);
5898 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 5899 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 5900 }
5901
9b138a83 5902 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 5903
5904 i = I915_READ(aud_cntl_st);
9b138a83 5905 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 5906 if (!i) {
5907 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5908 /* operate blindly on all ports */
1202b4c6
WF		 5909 eldv = IBX_ELD_VALIDB;
5910 eldv |= IBX_ELD_VALIDB << 4;
5911 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 5912 } else {
5913 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 5914 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 5915 }
5916
3a9627f4
WF		 5917 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5918 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5919 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 5920 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5921 } else
5922 I915_WRITE(aud_config, 0);
e0dac65e 5923
3a9627f4
WF		 5924 if (intel_eld_uptodate(connector,
5925 aud_cntrl_st2, eldv,
5926 aud_cntl_st, IBX_ELD_ADDRESS,
5927 hdmiw_hdmiedid))
5928 return;
5929
e0dac65e
WF		 5930 i = I915_READ(aud_cntrl_st2);
5931 i &= ~eldv;
5932 I915_WRITE(aud_cntrl_st2, i);
5933
5934 if (!eld[0])
5935 return;
5936
e0dac65e 5937 i = I915_READ(aud_cntl_st);
1202b4c6 5938 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 5939 I915_WRITE(aud_cntl_st, i);
5940
5941 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5942 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5943 for (i = 0; i < len; i++)
5944 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5945
5946 i = I915_READ(aud_cntrl_st2);
5947 i |= eldv;
5948 I915_WRITE(aud_cntrl_st2, i);
5949}
5950
5951void intel_write_eld(struct drm_encoder *encoder,
5952 struct drm_display_mode *mode)
5953{
5954 struct drm_crtc *crtc = encoder->crtc;
5955 struct drm_connector *connector;
5956 struct drm_device *dev = encoder->dev;
5957 struct drm_i915_private *dev_priv = dev->dev_private;
5958
5959 connector = drm_select_eld(encoder, mode);
5960 if (!connector)
5961 return;
5962
5963 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5964 connector->base.id,
5965 drm_get_connector_name(connector),
5966 connector->encoder->base.id,
5967 drm_get_encoder_name(connector->encoder));
5968
5969 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5970
5971 if (dev_priv->display.write_eld)
5972 dev_priv->display.write_eld(connector, crtc);
5973}
5974
79e53945
JB		 5975/** Loads the palette/gamma unit for the CRTC with the prepared values */
5976void intel_crtc_load_lut(struct drm_crtc *crtc)
5977{
5978 struct drm_device *dev = crtc->dev;
5979 struct drm_i915_private *dev_priv = dev->dev_private;
5980 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 5981 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 5982 int i;
5983
5984 /* The clocks have to be on to load the palette. */
aed3f09d 5985 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 5986 return;
5987
f2b115e6 5988 /* use legacy palette for Ironlake */
bad720ff 5989 if (HAS_PCH_SPLIT(dev))
9db4a9c7 5990 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 5991
79e53945
JB		 5992 for (i = 0; i < 256; i++) {
5993 I915_WRITE(palreg + 4 * i,
5994 (intel_crtc->lut_r[i] << 16) |
5995 (intel_crtc->lut_g[i] << 8) |
5996 intel_crtc->lut_b[i]);
5997 }
5998}
5999
560b85bb
CW		 6000static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6001{
6002 struct drm_device *dev = crtc->dev;
6003 struct drm_i915_private *dev_priv = dev->dev_private;
6004 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6005 bool visible = base != 0;
6006 u32 cntl;
6007
6008 if (intel_crtc->cursor_visible == visible)
6009 return;
6010
9db4a9c7 6011 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6012 if (visible) {
6013 /* On these chipsets we can only modify the base whilst
6014 * the cursor is disabled.
6015 */
9db4a9c7 6016 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6017
6018 cntl &= ~(CURSOR_FORMAT_MASK);
6019 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6020 cntl |= CURSOR_ENABLE |
6021 CURSOR_GAMMA_ENABLE |
6022 CURSOR_FORMAT_ARGB;
6023 } else
6024 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6025 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6026
6027 intel_crtc->cursor_visible = visible;
6028}
6029
6030static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6031{
6032 struct drm_device *dev = crtc->dev;
6033 struct drm_i915_private *dev_priv = dev->dev_private;
6034 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6035 int pipe = intel_crtc->pipe;
6036 bool visible = base != 0;
6037
6038 if (intel_crtc->cursor_visible != visible) {
548f245b 6039 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6040 if (base) {
6041 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6042 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6043 cntl |= pipe << 28; /* Connect to correct pipe */
6044 } else {
6045 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6046 cntl |= CURSOR_MODE_DISABLE;
6047 }
9db4a9c7 6048 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6049
6050 intel_crtc->cursor_visible = visible;
6051 }
6052 /* and commit changes on next vblank */
9db4a9c7 6053 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6054}
6055
65a21cd6
JB		 6056static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6057{
6058 struct drm_device *dev = crtc->dev;
6059 struct drm_i915_private *dev_priv = dev->dev_private;
6060 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6061 int pipe = intel_crtc->pipe;
6062 bool visible = base != 0;
6063
6064 if (intel_crtc->cursor_visible != visible) {
6065 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6066 if (base) {
6067 cntl &= ~CURSOR_MODE;
6068 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6069 } else {
6070 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6071 cntl |= CURSOR_MODE_DISABLE;
6072 }
6073 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6074
6075 intel_crtc->cursor_visible = visible;
6076 }
6077 /* and commit changes on next vblank */
6078 I915_WRITE(CURBASE_IVB(pipe), base);
6079}
6080
cda4b7d3 6081/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6082static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6083 bool on)
cda4b7d3
CW		 6084{
6085 struct drm_device *dev = crtc->dev;
6086 struct drm_i915_private *dev_priv = dev->dev_private;
6087 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6088 int pipe = intel_crtc->pipe;
6089 int x = intel_crtc->cursor_x;
6090 int y = intel_crtc->cursor_y;
560b85bb 6091 u32 base, pos;
cda4b7d3
CW		 6092 bool visible;
6093
6094 pos = 0;
6095
6b383a7f 6096 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6097 base = intel_crtc->cursor_addr;
6098 if (x > (int) crtc->fb->width)
6099 base = 0;
6100
6101 if (y > (int) crtc->fb->height)
6102 base = 0;
6103 } else
6104 base = 0;
6105
6106 if (x < 0) {
6107 if (x + intel_crtc->cursor_width < 0)
6108 base = 0;
6109
6110 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6111 x = -x;
6112 }
6113 pos |= x << CURSOR_X_SHIFT;
6114
6115 if (y < 0) {
6116 if (y + intel_crtc->cursor_height < 0)
6117 base = 0;
6118
6119 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6120 y = -y;
6121 }
6122 pos |= y << CURSOR_Y_SHIFT;
6123
6124 visible = base != 0;
560b85bb 6125 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6126 return;
6127
0cd83aa9 6128 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6129 I915_WRITE(CURPOS_IVB(pipe), pos);
6130 ivb_update_cursor(crtc, base);
6131 } else {
6132 I915_WRITE(CURPOS(pipe), pos);
6133 if (IS_845G(dev) || IS_I865G(dev))
6134 i845_update_cursor(crtc, base);
6135 else
6136 i9xx_update_cursor(crtc, base);
6137 }
cda4b7d3
CW		 6138}
6139
79e53945 6140static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6141 struct drm_file *file,
79e53945
JB		 6142 uint32_t handle,
6143 uint32_t width, uint32_t height)
6144{
6145 struct drm_device *dev = crtc->dev;
6146 struct drm_i915_private *dev_priv = dev->dev_private;
6147 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6148 struct drm_i915_gem_object *obj;
cda4b7d3 6149 uint32_t addr;
3f8bc370 6150 int ret;
79e53945 6151
79e53945
JB		 6152 /* if we want to turn off the cursor ignore width and height */
6153 if (!handle) {
28c97730 6154 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6155 addr = 0;
05394f39 6156 obj = NULL;
5004417d 6157 mutex_lock(&dev->struct_mutex);
3f8bc370 6158 goto finish;
79e53945
JB		 6159 }
6160
6161 /* Currently we only support 64x64 cursors */
6162 if (width != 64 || height != 64) {
6163 DRM_ERROR("we currently only support 64x64 cursors\n");
6164 return -EINVAL;
6165 }
6166
05394f39 6167 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6168 if (&obj->base == NULL)
79e53945
JB		 6169 return -ENOENT;
6170
05394f39 6171 if (obj->base.size < width * height * 4) {
79e53945 6172 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6173 ret = -ENOMEM;
6174 goto fail;
79e53945
JB		 6175 }
6176
71acb5eb 6177 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6178 mutex_lock(&dev->struct_mutex);
b295d1b6 6179 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 6180 if (obj->tiling_mode) {
6181 DRM_ERROR("cursor cannot be tiled\n");
6182 ret = -EINVAL;
6183 goto fail_locked;
6184 }
6185
2da3b9b9 6186 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 6187 if (ret) {
6188 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6189 goto fail_locked;
e7b526bb
CW		 6190 }
6191
d9e86c0e
CW		 6192 ret = i915_gem_object_put_fence(obj);
6193 if (ret) {
2da3b9b9 6194 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6195 goto fail_unpin;
6196 }
6197
05394f39 6198 addr = obj->gtt_offset;
71acb5eb 6199 } else {
6eeefaf3 6200 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6201 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6202 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6203 align);
71acb5eb
DA		 6204 if (ret) {
6205 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6206 goto fail_locked;
71acb5eb 6207 }
05394f39 6208 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6209 }
6210
a6c45cf0 6211 if (IS_GEN2(dev))
14b60391
JB		 6212 I915_WRITE(CURSIZE, (height << 12) | width);
6213
3f8bc370 6214 finish:
3f8bc370 6215 if (intel_crtc->cursor_bo) {
b295d1b6 6216 if (dev_priv->info->cursor_needs_physical) {
05394f39 6217 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6218 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6219 } else
6220 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6221 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6222 }
80824003 6223
7f9872e0 6224 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6225
6226 intel_crtc->cursor_addr = addr;
05394f39 6227 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6228 intel_crtc->cursor_width = width;
6229 intel_crtc->cursor_height = height;
6230
6b383a7f 6231 intel_crtc_update_cursor(crtc, true);
3f8bc370 6232
79e53945 6233 return 0;
e7b526bb 6234fail_unpin:
05394f39 6235 i915_gem_object_unpin(obj);
7f9872e0 6236fail_locked:
34b8686e 6237 mutex_unlock(&dev->struct_mutex);
bc9025bd 6238fail:
05394f39 6239 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6240 return ret;
79e53945
JB		 6241}
6242
6243static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6244{
79e53945 6245 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6246
cda4b7d3
CW		 6247 intel_crtc->cursor_x = x;
6248 intel_crtc->cursor_y = y;
652c393a 6249
6b383a7f 6250 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 6251
6252 return 0;
6253}
6254
6255/** Sets the color ramps on behalf of RandR */
6256void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6257 u16 blue, int regno)
6258{
6259 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6260
6261 intel_crtc->lut_r[regno] = red >> 8;
6262 intel_crtc->lut_g[regno] = green >> 8;
6263 intel_crtc->lut_b[regno] = blue >> 8;
6264}
6265
b8c00ac5
DA		 6266void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6267 u16 *blue, int regno)
6268{
6269 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6270
6271 *red = intel_crtc->lut_r[regno] << 8;
6272 *green = intel_crtc->lut_g[regno] << 8;
6273 *blue = intel_crtc->lut_b[regno] << 8;
6274}
6275
79e53945 6276static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6277 u16 *blue, uint32_t start, uint32_t size)
79e53945 6278{
7203425a 6279 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6280 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6281
7203425a 6282 for (i = start; i < end; i++) {
79e53945
JB		 6283 intel_crtc->lut_r[i] = red[i] >> 8;
6284 intel_crtc->lut_g[i] = green[i] >> 8;
6285 intel_crtc->lut_b[i] = blue[i] >> 8;
6286 }
6287
6288 intel_crtc_load_lut(crtc);
6289}
6290
6291/**
6292 * Get a pipe with a simple mode set on it for doing load-based monitor
6293 * detection.
6294 *
6295 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 6296 * its requirements. The pipe will be connected to no other encoders.
79e53945 6297 *
c751ce4f 6298 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 6299 * configured for it. In the future, it could choose to temporarily disable
6300 * some outputs to free up a pipe for its use.
6301 *
6302 * \return crtc, or NULL if no pipes are available.
6303 */
6304
6305/* VESA 640x480x72Hz mode to set on the pipe */
6306static struct drm_display_mode load_detect_mode = {
6307 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6308 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6309};
6310
d2dff872
CW		 6311static struct drm_framebuffer *
6312intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6313 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6314 struct drm_i915_gem_object *obj)
6315{
6316 struct intel_framebuffer *intel_fb;
6317 int ret;
6318
6319 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6320 if (!intel_fb) {
6321 drm_gem_object_unreference_unlocked(&obj->base);
6322 return ERR_PTR(-ENOMEM);
6323 }
6324
6325 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6326 if (ret) {
6327 drm_gem_object_unreference_unlocked(&obj->base);
6328 kfree(intel_fb);
6329 return ERR_PTR(ret);
6330 }
6331
6332 return &intel_fb->base;
6333}
6334
6335static u32
6336intel_framebuffer_pitch_for_width(int width, int bpp)
6337{
6338 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6339 return ALIGN(pitch, 64);
6340}
6341
6342static u32
6343intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6344{
6345 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6346 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6347}
6348
6349static struct drm_framebuffer *
6350intel_framebuffer_create_for_mode(struct drm_device *dev,
6351 struct drm_display_mode *mode,
6352 int depth, int bpp)
6353{
6354 struct drm_i915_gem_object *obj;
308e5bcb 6355 struct drm_mode_fb_cmd2 mode_cmd;
d2dff872
CW		 6356
6357 obj = i915_gem_alloc_object(dev,
6358 intel_framebuffer_size_for_mode(mode, bpp));
6359 if (obj == NULL)
6360 return ERR_PTR(-ENOMEM);
6361
6362 mode_cmd.width = mode->hdisplay;
6363 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6364 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6365 bpp);
5ca0c34a 6366 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6367
6368 return intel_framebuffer_create(dev, &mode_cmd, obj);
6369}
6370
6371static struct drm_framebuffer *
6372mode_fits_in_fbdev(struct drm_device *dev,
6373 struct drm_display_mode *mode)
6374{
6375 struct drm_i915_private *dev_priv = dev->dev_private;
6376 struct drm_i915_gem_object *obj;
6377 struct drm_framebuffer *fb;
6378
6379 if (dev_priv->fbdev == NULL)
6380 return NULL;
6381
6382 obj = dev_priv->fbdev->ifb.obj;
6383 if (obj == NULL)
6384 return NULL;
6385
6386 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6387 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6388 fb->bits_per_pixel))
d2dff872
CW		 6389 return NULL;
6390
01f2c773 6391 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6392 return NULL;
6393
6394 return fb;
6395}
6396
d2434ab7 6397bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6398 struct drm_display_mode *mode,
8261b191 6399 struct intel_load_detect_pipe *old)
79e53945
JB		 6400{
6401 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6402 struct intel_encoder *intel_encoder =
6403 intel_attached_encoder(connector);
79e53945 6404 struct drm_crtc *possible_crtc;
4ef69c7a 6405 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6406 struct drm_crtc *crtc = NULL;
6407 struct drm_device *dev = encoder->dev;
94352cf9 6408 struct drm_framebuffer *fb;
79e53945
JB		 6409 int i = -1;
6410
d2dff872
CW		 6411 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6412 connector->base.id, drm_get_connector_name(connector),
6413 encoder->base.id, drm_get_encoder_name(encoder));
6414
79e53945
JB		 6415 /*
6416 * Algorithm gets a little messy:
7a5e4805 6417 *
79e53945
JB		 6418 * - if the connector already has an assigned crtc, use it (but make
6419 * sure it's on first)
7a5e4805 6420 *
79e53945
JB		 6421 * - try to find the first unused crtc that can drive this connector,
6422 * and use that if we find one
79e53945
JB		 6423 */
6424
6425 /* See if we already have a CRTC for this connector */
6426 if (encoder->crtc) {
6427 crtc = encoder->crtc;
8261b191 6428
24218aac 6429 old->dpms_mode = connector->dpms;
8261b191
CW		 6430 old->load_detect_temp = false;
6431
6432 /* Make sure the crtc and connector are running */
24218aac
DV		 6433 if (connector->dpms != DRM_MODE_DPMS_ON)
6434 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6435
7173188d 6436 return true;
79e53945
JB		 6437 }
6438
6439 /* Find an unused one (if possible) */
6440 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6441 i++;
6442 if (!(encoder->possible_crtcs & (1 << i)))
6443 continue;
6444 if (!possible_crtc->enabled) {
6445 crtc = possible_crtc;
6446 break;
6447 }
79e53945
JB		 6448 }
6449
6450 /*
6451 * If we didn't find an unused CRTC, don't use any.
6452 */
6453 if (!crtc) {
7173188d
CW		 6454 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6455 return false;
79e53945
JB		 6456 }
6457
fc303101
DV		 6458 intel_encoder->new_crtc = to_intel_crtc(crtc);
6459 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6460
6461 intel_crtc = to_intel_crtc(crtc);
24218aac 6462 old->dpms_mode = connector->dpms;
8261b191 6463 old->load_detect_temp = true;
d2dff872 6464 old->release_fb = NULL;
79e53945 6465
6492711d
CW		 6466 if (!mode)
6467 mode = &load_detect_mode;
79e53945 6468
d2dff872
CW		 6469 /* We need a framebuffer large enough to accommodate all accesses
6470 * that the plane may generate whilst we perform load detection.
6471 * We can not rely on the fbcon either being present (we get called
6472 * during its initialisation to detect all boot displays, or it may
6473 * not even exist) or that it is large enough to satisfy the
6474 * requested mode.
6475 */
94352cf9
DV		 6476 fb = mode_fits_in_fbdev(dev, mode);
6477 if (fb == NULL) {
d2dff872 6478 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6479 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6480 old->release_fb = fb;
d2dff872
CW		 6481 } else
6482 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6483 if (IS_ERR(fb)) {
d2dff872 6484 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
24218aac 6485 goto fail;
79e53945 6486 }
79e53945 6487
94352cf9 6488 if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6489 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6490 if (old->release_fb)
6491 old->release_fb->funcs->destroy(old->release_fb);
24218aac 6492 goto fail;
79e53945 6493 }
7173188d 6494
79e53945 6495 /* let the connector get through one full cycle before testing */
9d0498a2 6496 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 6497
7173188d 6498 return true;
24218aac
DV		 6499fail:
6500 connector->encoder = NULL;
6501 encoder->crtc = NULL;
24218aac 6502 return false;
79e53945
JB		 6503}
6504
d2434ab7 6505void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6506 struct intel_load_detect_pipe *old)
79e53945 6507{
d2434ab7
DV		 6508 struct intel_encoder *intel_encoder =
6509 intel_attached_encoder(connector);
4ef69c7a 6510 struct drm_encoder *encoder = &intel_encoder->base;
79e53945 6511
d2dff872
CW		 6512 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6513 connector->base.id, drm_get_connector_name(connector),
6514 encoder->base.id, drm_get_encoder_name(encoder));
6515
8261b191 6516 if (old->load_detect_temp) {
fc303101
DV		 6517 struct drm_crtc *crtc = encoder->crtc;
6518
6519 to_intel_connector(connector)->new_encoder = NULL;
6520 intel_encoder->new_crtc = NULL;
6521 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872
CW		 6522
6523 if (old->release_fb)
6524 old->release_fb->funcs->destroy(old->release_fb);
6525
0622a53c 6526 return;
79e53945
JB		 6527 }
6528
c751ce4f 6529 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6530 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6531 connector->funcs->dpms(connector, old->dpms_mode);
79e53945
JB		 6532}
6533
6534/* Returns the clock of the currently programmed mode of the given pipe. */
6535static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6536{
6537 struct drm_i915_private *dev_priv = dev->dev_private;
6538 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6539 int pipe = intel_crtc->pipe;
548f245b 6540 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6541 u32 fp;
6542 intel_clock_t clock;
6543
6544 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6545 fp = I915_READ(FP0(pipe));
79e53945 6546 else
39adb7a5 6547 fp = I915_READ(FP1(pipe));
79e53945
JB		 6548
6549 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6550 if (IS_PINEVIEW(dev)) {
6551 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6552 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6553 } else {
6554 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6555 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6556 }
6557
a6c45cf0 6558 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6559 if (IS_PINEVIEW(dev))
6560 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6561 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6562 else
6563 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6564 DPLL_FPA01_P1_POST_DIV_SHIFT);
6565
6566 switch (dpll & DPLL_MODE_MASK) {
6567 case DPLLB_MODE_DAC_SERIAL:
6568 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6569 5 : 10;
6570 break;
6571 case DPLLB_MODE_LVDS:
6572 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6573 7 : 14;
6574 break;
6575 default:
28c97730 6576 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6577 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6578 return 0;
6579 }
6580
6581 /* XXX: Handle the 100Mhz refclk */
2177832f 6582 intel_clock(dev, 96000, &clock);
79e53945
JB		 6583 } else {
6584 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6585
6586 if (is_lvds) {
6587 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6588 DPLL_FPA01_P1_POST_DIV_SHIFT);
6589 clock.p2 = 14;
6590
6591 if ((dpll & PLL_REF_INPUT_MASK) ==
6592 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6593 /* XXX: might not be 66MHz */
2177832f 6594 intel_clock(dev, 66000, &clock);
79e53945 6595 } else
2177832f 6596 intel_clock(dev, 48000, &clock);
79e53945
JB		 6597 } else {
6598 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6599 clock.p1 = 2;
6600 else {
6601 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6602 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6603 }
6604 if (dpll & PLL_P2_DIVIDE_BY_4)
6605 clock.p2 = 4;
6606 else
6607 clock.p2 = 2;
6608
2177832f 6609 intel_clock(dev, 48000, &clock);
79e53945
JB		 6610 }
6611 }
6612
6613 /* XXX: It would be nice to validate the clocks, but we can't reuse
6614 * i830PllIsValid() because it relies on the xf86_config connector
6615 * configuration being accurate, which it isn't necessarily.
6616 */
6617
6618 return clock.dot;
6619}
6620
6621/** Returns the currently programmed mode of the given pipe. */
6622struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6623 struct drm_crtc *crtc)
6624{
548f245b 6625 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 6626 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fe2b8f9d 6627 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
79e53945 6628 struct drm_display_mode *mode;
fe2b8f9d
PZ		 6629 int htot = I915_READ(HTOTAL(cpu_transcoder));
6630 int hsync = I915_READ(HSYNC(cpu_transcoder));
6631 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6632 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 6633
6634 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6635 if (!mode)
6636 return NULL;
6637
6638 mode->clock = intel_crtc_clock_get(dev, crtc);
6639 mode->hdisplay = (htot & 0xffff) + 1;
6640 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6641 mode->hsync_start = (hsync & 0xffff) + 1;
6642 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6643 mode->vdisplay = (vtot & 0xffff) + 1;
6644 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6645 mode->vsync_start = (vsync & 0xffff) + 1;
6646 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6647
6648 drm_mode_set_name(mode);
79e53945
JB		 6649
6650 return mode;
6651}
6652
3dec0095 6653static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6654{
6655 struct drm_device *dev = crtc->dev;
6656 drm_i915_private_t *dev_priv = dev->dev_private;
6657 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6658 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6659 int dpll_reg = DPLL(pipe);
6660 int dpll;
652c393a 6661
bad720ff 6662 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6663 return;
6664
6665 if (!dev_priv->lvds_downclock_avail)
6666 return;
6667
dbdc6479 6668 dpll = I915_READ(dpll_reg);
652c393a 6669 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6670 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 6671
8ac5a6d5 6672 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 6673
6674 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6675 I915_WRITE(dpll_reg, dpll);
9d0498a2 6676 intel_wait_for_vblank(dev, pipe);
dbdc6479 6677
652c393a
JB		 6678 dpll = I915_READ(dpll_reg);
6679 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6680 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 6681 }
652c393a
JB		 6682}
6683
6684static void intel_decrease_pllclock(struct drm_crtc *crtc)
6685{
6686 struct drm_device *dev = crtc->dev;
6687 drm_i915_private_t *dev_priv = dev->dev_private;
6688 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 6689
bad720ff 6690 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6691 return;
6692
6693 if (!dev_priv->lvds_downclock_avail)
6694 return;
6695
6696 /*
6697 * Since this is called by a timer, we should never get here in
6698 * the manual case.
6699 */
6700 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 6701 int pipe = intel_crtc->pipe;
6702 int dpll_reg = DPLL(pipe);
6703 int dpll;
f6e5b160 6704
44d98a61 6705 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 6706
8ac5a6d5 6707 assert_panel_unlocked(dev_priv, pipe);
652c393a 6708
dc257cf1 6709 dpll = I915_READ(dpll_reg);
652c393a
JB		 6710 dpll |= DISPLAY_RATE_SELECT_FPA1;
6711 I915_WRITE(dpll_reg, dpll);
9d0498a2 6712 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 6713 dpll = I915_READ(dpll_reg);
6714 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 6715 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 6716 }
6717
6718}
6719
f047e395
CW		 6720void intel_mark_busy(struct drm_device *dev)
6721{
f047e395
CW		 6722 i915_update_gfx_val(dev->dev_private);
6723}
6724
6725void intel_mark_idle(struct drm_device *dev)
652c393a 6726{
f047e395
CW		 6727}
6728
6729void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6730{
6731 struct drm_device *dev = obj->base.dev;
652c393a 6732 struct drm_crtc *crtc;
652c393a
JB		 6733
6734 if (!i915_powersave)
6735 return;
6736
652c393a 6737 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 6738 if (!crtc->fb)
6739 continue;
6740
f047e395
CW		 6741 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6742 intel_increase_pllclock(crtc);
652c393a 6743 }
652c393a
JB		 6744}
6745
f047e395 6746void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
652c393a 6747{
f047e395
CW		 6748 struct drm_device *dev = obj->base.dev;
6749 struct drm_crtc *crtc;
652c393a 6750
f047e395 6751 if (!i915_powersave)
acb87dfb
CW		 6752 return;
6753
652c393a
JB		 6754 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6755 if (!crtc->fb)
6756 continue;
6757
f047e395
CW		 6758 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6759 intel_decrease_pllclock(crtc);
652c393a
JB		 6760 }
6761}
6762
79e53945
JB		 6763static void intel_crtc_destroy(struct drm_crtc *crtc)
6764{
6765 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6766 struct drm_device *dev = crtc->dev;
6767 struct intel_unpin_work *work;
6768 unsigned long flags;
6769
6770 spin_lock_irqsave(&dev->event_lock, flags);
6771 work = intel_crtc->unpin_work;
6772 intel_crtc->unpin_work = NULL;
6773 spin_unlock_irqrestore(&dev->event_lock, flags);
6774
6775 if (work) {
6776 cancel_work_sync(&work->work);
6777 kfree(work);
6778 }
79e53945
JB		 6779
6780 drm_crtc_cleanup(crtc);
67e77c5a 6781
79e53945
JB		 6782 kfree(intel_crtc);
6783}
6784
6b95a207
KH		 6785static void intel_unpin_work_fn(struct work_struct *__work)
6786{
6787 struct intel_unpin_work *work =
6788 container_of(__work, struct intel_unpin_work, work);
6789
6790 mutex_lock(&work->dev->struct_mutex);
1690e1eb 6791 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 6792 drm_gem_object_unreference(&work->pending_flip_obj->base);
6793 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 6794
7782de3b 6795 intel_update_fbc(work->dev);
6b95a207
KH		 6796 mutex_unlock(&work->dev->struct_mutex);
6797 kfree(work);
6798}
6799
1afe3e9d 6800static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 6801 struct drm_crtc *crtc)
6b95a207
KH		 6802{
6803 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 6804 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6805 struct intel_unpin_work *work;
05394f39 6806 struct drm_i915_gem_object *obj;
6b95a207 6807 struct drm_pending_vblank_event *e;
95cb1b02 6808 struct timeval tvbl;
6b95a207
KH		 6809 unsigned long flags;
6810
6811 /* Ignore early vblank irqs */
6812 if (intel_crtc == NULL)
6813 return;
6814
6815 spin_lock_irqsave(&dev->event_lock, flags);
6816 work = intel_crtc->unpin_work;
6817 if (work == NULL || !work->pending) {
6818 spin_unlock_irqrestore(&dev->event_lock, flags);
6819 return;
6820 }
6821
6822 intel_crtc->unpin_work = NULL;
6b95a207
KH		 6823
6824 if (work->event) {
6825 e = work->event;
49b14a5c 6826 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
0af7e4df 6827
49b14a5c
MK		 6828 e->event.tv_sec = tvbl.tv_sec;
6829 e->event.tv_usec = tvbl.tv_usec;
0af7e4df 6830
6b95a207
KH		 6831 list_add_tail(&e->base.link,
6832 &e->base.file_priv->event_list);
6833 wake_up_interruptible(&e->base.file_priv->event_wait);
6834 }
6835
0af7e4df
MK		 6836 drm_vblank_put(dev, intel_crtc->pipe);
6837
6b95a207
KH		 6838 spin_unlock_irqrestore(&dev->event_lock, flags);
6839
05394f39 6840 obj = work->old_fb_obj;
d9e86c0e 6841
e59f2bac 6842 atomic_clear_mask(1 << intel_crtc->plane,
05394f39 6843 &obj->pending_flip.counter);
d9e86c0e 6844
5bb61643 6845 wake_up(&dev_priv->pending_flip_queue);
6b95a207 6846 schedule_work(&work->work);
e5510fac
JB		 6847
6848 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 6849}
6850
1afe3e9d
JB		 6851void intel_finish_page_flip(struct drm_device *dev, int pipe)
6852{
6853 drm_i915_private_t *dev_priv = dev->dev_private;
6854 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6855
49b14a5c 6856 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6857}
6858
6859void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6860{
6861 drm_i915_private_t *dev_priv = dev->dev_private;
6862 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6863
49b14a5c 6864 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6865}
6866
6b95a207
KH		 6867void intel_prepare_page_flip(struct drm_device *dev, int plane)
6868{
6869 drm_i915_private_t *dev_priv = dev->dev_private;
6870 struct intel_crtc *intel_crtc =
6871 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6872 unsigned long flags;
6873
6874 spin_lock_irqsave(&dev->event_lock, flags);
de3f440f 6875 if (intel_crtc->unpin_work) {
4e5359cd
SF		 6876 if ((++intel_crtc->unpin_work->pending) > 1)
6877 DRM_ERROR("Prepared flip multiple times\n");
de3f440f
JB		 6878 } else {
6879 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6880 }
6b95a207
KH		 6881 spin_unlock_irqrestore(&dev->event_lock, flags);
6882}
6883
8c9f3aaf
JB		 6884static int intel_gen2_queue_flip(struct drm_device *dev,
6885 struct drm_crtc *crtc,
6886 struct drm_framebuffer *fb,
6887 struct drm_i915_gem_object *obj)
6888{
6889 struct drm_i915_private *dev_priv = dev->dev_private;
6890 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 6891 u32 flip_mask;
6d90c952 6892 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6893 int ret;
6894
6d90c952 6895 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6896 if (ret)
83d4092b 6897 goto err;
8c9f3aaf 6898
6d90c952 6899 ret = intel_ring_begin(ring, 6);
8c9f3aaf 6900 if (ret)
83d4092b 6901 goto err_unpin;
8c9f3aaf
JB		 6902
6903 /* Can't queue multiple flips, so wait for the previous
6904 * one to finish before executing the next.
6905 */
6906 if (intel_crtc->plane)
6907 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6908 else
6909 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 6910 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6911 intel_ring_emit(ring, MI_NOOP);
6912 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6913 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6914 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 6915 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 6916 intel_ring_emit(ring, 0); /* aux display base address, unused */
6917 intel_ring_advance(ring);
83d4092b
CW		 6918 return 0;
6919
6920err_unpin:
6921 intel_unpin_fb_obj(obj);
6922err:
8c9f3aaf
JB		 6923 return ret;
6924}
6925
6926static int intel_gen3_queue_flip(struct drm_device *dev,
6927 struct drm_crtc *crtc,
6928 struct drm_framebuffer *fb,
6929 struct drm_i915_gem_object *obj)
6930{
6931 struct drm_i915_private *dev_priv = dev->dev_private;
6932 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 6933 u32 flip_mask;
6d90c952 6934 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6935 int ret;
6936
6d90c952 6937 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6938 if (ret)
83d4092b 6939 goto err;
8c9f3aaf 6940
6d90c952 6941 ret = intel_ring_begin(ring, 6);
8c9f3aaf 6942 if (ret)
83d4092b 6943 goto err_unpin;
8c9f3aaf
JB		 6944
6945 if (intel_crtc->plane)
6946 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6947 else
6948 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 6949 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6950 intel_ring_emit(ring, MI_NOOP);
6951 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6952 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6953 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 6954 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 6955 intel_ring_emit(ring, MI_NOOP);
6956
6957 intel_ring_advance(ring);
83d4092b
CW		 6958 return 0;
6959
6960err_unpin:
6961 intel_unpin_fb_obj(obj);
6962err:
8c9f3aaf
JB		 6963 return ret;
6964}
6965
6966static int intel_gen4_queue_flip(struct drm_device *dev,
6967 struct drm_crtc *crtc,
6968 struct drm_framebuffer *fb,
6969 struct drm_i915_gem_object *obj)
6970{
6971 struct drm_i915_private *dev_priv = dev->dev_private;
6972 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6973 uint32_t pf, pipesrc;
6d90c952 6974 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6975 int ret;
6976
6d90c952 6977 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6978 if (ret)
83d4092b 6979 goto err;
8c9f3aaf 6980
6d90c952 6981 ret = intel_ring_begin(ring, 4);
8c9f3aaf 6982 if (ret)
83d4092b 6983 goto err_unpin;
8c9f3aaf
JB		 6984
6985 /* i965+ uses the linear or tiled offsets from the
6986 * Display Registers (which do not change across a page-flip)
6987 * so we need only reprogram the base address.
6988 */
6d90c952
DV		 6989 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6990 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6991 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 6992 intel_ring_emit(ring,
6993 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
6994 obj->tiling_mode);
8c9f3aaf
JB		 6995
6996 /* XXX Enabling the panel-fitter across page-flip is so far
6997 * untested on non-native modes, so ignore it for now.
6998 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6999 */
7000 pf = 0;
7001 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 7002 intel_ring_emit(ring, pf | pipesrc);
7003 intel_ring_advance(ring);
83d4092b
CW		 7004 return 0;
7005
7006err_unpin:
7007 intel_unpin_fb_obj(obj);
7008err:
8c9f3aaf
JB		 7009 return ret;
7010}
7011
7012static int intel_gen6_queue_flip(struct drm_device *dev,
7013 struct drm_crtc *crtc,
7014 struct drm_framebuffer *fb,
7015 struct drm_i915_gem_object *obj)
7016{
7017 struct drm_i915_private *dev_priv = dev->dev_private;
7018 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7019 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7020 uint32_t pf, pipesrc;
7021 int ret;
7022
6d90c952 7023 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7024 if (ret)
83d4092b 7025 goto err;
8c9f3aaf 7026
6d90c952 7027 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7028 if (ret)
83d4092b 7029 goto err_unpin;
8c9f3aaf 7030
6d90c952
DV		 7031 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7032 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7033 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7034 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7035
dc257cf1
DV		 7036 /* Contrary to the suggestions in the documentation,
7037 * "Enable Panel Fitter" does not seem to be required when page
7038 * flipping with a non-native mode, and worse causes a normal
7039 * modeset to fail.
7040 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7041 */
7042 pf = 0;
8c9f3aaf 7043 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 7044 intel_ring_emit(ring, pf | pipesrc);
7045 intel_ring_advance(ring);
83d4092b
CW		 7046 return 0;
7047
7048err_unpin:
7049 intel_unpin_fb_obj(obj);
7050err:
8c9f3aaf
JB		 7051 return ret;
7052}
7053
7c9017e5
JB		 7054/*
7055 * On gen7 we currently use the blit ring because (in early silicon at least)
7056 * the render ring doesn't give us interrpts for page flip completion, which
7057 * means clients will hang after the first flip is queued. Fortunately the
7058 * blit ring generates interrupts properly, so use it instead.
7059 */
7060static int intel_gen7_queue_flip(struct drm_device *dev,
7061 struct drm_crtc *crtc,
7062 struct drm_framebuffer *fb,
7063 struct drm_i915_gem_object *obj)
7064{
7065 struct drm_i915_private *dev_priv = dev->dev_private;
7066 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7067 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7068 uint32_t plane_bit = 0;
7c9017e5
JB		 7069 int ret;
7070
7071 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7072 if (ret)
83d4092b 7073 goto err;
7c9017e5 7074
cb05d8de
DV		 7075 switch(intel_crtc->plane) {
7076 case PLANE_A:
7077 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7078 break;
7079 case PLANE_B:
7080 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7081 break;
7082 case PLANE_C:
7083 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7084 break;
7085 default:
7086 WARN_ONCE(1, "unknown plane in flip command\n");
7087 ret = -ENODEV;
ab3951eb 7088 goto err_unpin;
cb05d8de
DV		 7089 }
7090
7c9017e5
JB		 7091 ret = intel_ring_begin(ring, 4);
7092 if (ret)
83d4092b 7093 goto err_unpin;
7c9017e5 7094
cb05d8de 7095 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7096 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7097 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5
JB		 7098 intel_ring_emit(ring, (MI_NOOP));
7099 intel_ring_advance(ring);
83d4092b
CW		 7100 return 0;
7101
7102err_unpin:
7103 intel_unpin_fb_obj(obj);
7104err:
7c9017e5
JB		 7105 return ret;
7106}
7107
8c9f3aaf
JB		 7108static int intel_default_queue_flip(struct drm_device *dev,
7109 struct drm_crtc *crtc,
7110 struct drm_framebuffer *fb,
7111 struct drm_i915_gem_object *obj)
7112{
7113 return -ENODEV;
7114}
7115
6b95a207
KH		 7116static int intel_crtc_page_flip(struct drm_crtc *crtc,
7117 struct drm_framebuffer *fb,
7118 struct drm_pending_vblank_event *event)
7119{
7120 struct drm_device *dev = crtc->dev;
7121 struct drm_i915_private *dev_priv = dev->dev_private;
7122 struct intel_framebuffer *intel_fb;
05394f39 7123 struct drm_i915_gem_object *obj;
6b95a207
KH		 7124 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7125 struct intel_unpin_work *work;
8c9f3aaf 7126 unsigned long flags;
52e68630 7127 int ret;
6b95a207 7128
e6a595d2
VS		 7129 /* Can't change pixel format via MI display flips. */
7130 if (fb->pixel_format != crtc->fb->pixel_format)
7131 return -EINVAL;
7132
7133 /*
7134 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7135 * Note that pitch changes could also affect these register.
7136 */
7137 if (INTEL_INFO(dev)->gen > 3 &&
7138 (fb->offsets[0] != crtc->fb->offsets[0] ||
7139 fb->pitches[0] != crtc->fb->pitches[0]))
7140 return -EINVAL;
7141
6b95a207
KH		 7142 work = kzalloc(sizeof *work, GFP_KERNEL);
7143 if (work == NULL)
7144 return -ENOMEM;
7145
6b95a207
KH		 7146 work->event = event;
7147 work->dev = crtc->dev;
7148 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 7149 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 7150 INIT_WORK(&work->work, intel_unpin_work_fn);
7151
7317c75e
JB		 7152 ret = drm_vblank_get(dev, intel_crtc->pipe);
7153 if (ret)
7154 goto free_work;
7155
6b95a207
KH		 7156 /* We borrow the event spin lock for protecting unpin_work */
7157 spin_lock_irqsave(&dev->event_lock, flags);
7158 if (intel_crtc->unpin_work) {
7159 spin_unlock_irqrestore(&dev->event_lock, flags);
7160 kfree(work);
7317c75e 7161 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7162
7163 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7164 return -EBUSY;
7165 }
7166 intel_crtc->unpin_work = work;
7167 spin_unlock_irqrestore(&dev->event_lock, flags);
7168
7169 intel_fb = to_intel_framebuffer(fb);
7170 obj = intel_fb->obj;
7171
79158103
CW		 7172 ret = i915_mutex_lock_interruptible(dev);
7173 if (ret)
7174 goto cleanup;
6b95a207 7175
75dfca80 7176 /* Reference the objects for the scheduled work. */
05394f39
CW		 7177 drm_gem_object_reference(&work->old_fb_obj->base);
7178 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7179
7180 crtc->fb = fb;
96b099fd 7181
e1f99ce6 7182 work->pending_flip_obj = obj;
e1f99ce6 7183
4e5359cd
SF		 7184 work->enable_stall_check = true;
7185
e1f99ce6
CW		 7186 /* Block clients from rendering to the new back buffer until
7187 * the flip occurs and the object is no longer visible.
7188 */
05394f39 7189 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
e1f99ce6 7190
8c9f3aaf
JB		 7191 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7192 if (ret)
7193 goto cleanup_pending;
6b95a207 7194
7782de3b 7195 intel_disable_fbc(dev);
f047e395 7196 intel_mark_fb_busy(obj);
6b95a207
KH		 7197 mutex_unlock(&dev->struct_mutex);
7198
e5510fac
JB		 7199 trace_i915_flip_request(intel_crtc->plane, obj);
7200
6b95a207 7201 return 0;
96b099fd 7202
8c9f3aaf
JB		 7203cleanup_pending:
7204 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
05394f39
CW		 7205 drm_gem_object_unreference(&work->old_fb_obj->base);
7206 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7207 mutex_unlock(&dev->struct_mutex);
7208
79158103 7209cleanup:
96b099fd
CW		 7210 spin_lock_irqsave(&dev->event_lock, flags);
7211 intel_crtc->unpin_work = NULL;
7212 spin_unlock_irqrestore(&dev->event_lock, flags);
7213
7317c75e
JB		 7214 drm_vblank_put(dev, intel_crtc->pipe);
7215free_work:
96b099fd
CW		 7216 kfree(work);
7217
7218 return ret;
6b95a207
KH		 7219}
7220
f6e5b160 7221static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7222 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7223 .load_lut = intel_crtc_load_lut,
976f8a20 7224 .disable = intel_crtc_noop,
f6e5b160
CW		 7225};
7226
6ed0f796 7227bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
47f1c6c9 7228{
6ed0f796
DV		 7229 struct intel_encoder *other_encoder;
7230 struct drm_crtc *crtc = &encoder->new_crtc->base;
47f1c6c9 7231
6ed0f796
DV		 7232 if (WARN_ON(!crtc))
7233 return false;
7234
7235 list_for_each_entry(other_encoder,
7236 &crtc->dev->mode_config.encoder_list,
7237 base.head) {
7238
7239 if (&other_encoder->new_crtc->base != crtc ||
7240 encoder == other_encoder)
7241 continue;
7242 else
7243 return true;
f47166d2
CW		 7244 }
7245
6ed0f796
DV		 7246 return false;
7247}
47f1c6c9 7248
50f56119
DV		 7249static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7250 struct drm_crtc *crtc)
7251{
7252 struct drm_device *dev;
7253 struct drm_crtc *tmp;
7254 int crtc_mask = 1;
47f1c6c9 7255
50f56119 7256 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7257
50f56119 7258 dev = crtc->dev;
47f1c6c9 7259
50f56119
DV		 7260 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7261 if (tmp == crtc)
7262 break;
7263 crtc_mask <<= 1;
7264 }
47f1c6c9 7265
50f56119
DV		 7266 if (encoder->possible_crtcs & crtc_mask)
7267 return true;
7268 return false;
47f1c6c9 7269}
79e53945 7270
9a935856
DV		 7271/**
7272 * intel_modeset_update_staged_output_state
7273 *
7274 * Updates the staged output configuration state, e.g. after we've read out the
7275 * current hw state.
7276 */
7277static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7278{
9a935856
DV		 7279 struct intel_encoder *encoder;
7280 struct intel_connector *connector;
f6e5b160 7281
9a935856
DV		 7282 list_for_each_entry(connector, &dev->mode_config.connector_list,
7283 base.head) {
7284 connector->new_encoder =
7285 to_intel_encoder(connector->base.encoder);
7286 }
f6e5b160 7287
9a935856
DV		 7288 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7289 base.head) {
7290 encoder->new_crtc =
7291 to_intel_crtc(encoder->base.crtc);
7292 }
f6e5b160
CW		 7293}
7294
9a935856
DV		 7295/**
7296 * intel_modeset_commit_output_state
7297 *
7298 * This function copies the stage display pipe configuration to the real one.
7299 */
7300static void intel_modeset_commit_output_state(struct drm_device *dev)
7301{
7302 struct intel_encoder *encoder;
7303 struct intel_connector *connector;
f6e5b160 7304
9a935856
DV		 7305 list_for_each_entry(connector, &dev->mode_config.connector_list,
7306 base.head) {
7307 connector->base.encoder = &connector->new_encoder->base;
7308 }
f6e5b160 7309
9a935856
DV		 7310 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7311 base.head) {
7312 encoder->base.crtc = &encoder->new_crtc->base;
7313 }
7314}
7315
7758a113
DV		 7316static struct drm_display_mode *
7317intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7318 struct drm_display_mode *mode)
ee7b9f93 7319{
7758a113
DV		 7320 struct drm_device *dev = crtc->dev;
7321 struct drm_display_mode *adjusted_mode;
7322 struct drm_encoder_helper_funcs *encoder_funcs;
7323 struct intel_encoder *encoder;
ee7b9f93 7324
7758a113
DV		 7325 adjusted_mode = drm_mode_duplicate(dev, mode);
7326 if (!adjusted_mode)
7327 return ERR_PTR(-ENOMEM);
7328
7329 /* Pass our mode to the connectors and the CRTC to give them a chance to
7330 * adjust it according to limitations or connector properties, and also
7331 * a chance to reject the mode entirely.
7332 */
7333 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7334 base.head) {
7335
7336 if (&encoder->new_crtc->base != crtc)
7337 continue;
7338 encoder_funcs = encoder->base.helper_private;
7339 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7340 adjusted_mode))) {
7341 DRM_DEBUG_KMS("Encoder fixup failed\n");
7342 goto fail;
7343 }
ee7b9f93
JB		 7344 }
7345
7758a113
DV		 7346 if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7347 DRM_DEBUG_KMS("CRTC fixup failed\n");
7348 goto fail;
ee7b9f93 7349 }
7758a113
DV		 7350 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7351
7352 return adjusted_mode;
7353fail:
7354 drm_mode_destroy(dev, adjusted_mode);
7355 return ERR_PTR(-EINVAL);
ee7b9f93
JB		 7356}
7357
e2e1ed41
DV		 7358/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7359 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7360static void
7361intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7362 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7363{
7364 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7365 struct drm_device *dev = crtc->dev;
7366 struct intel_encoder *encoder;
7367 struct intel_connector *connector;
7368 struct drm_crtc *tmp_crtc;
79e53945 7369
e2e1ed41 7370 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7371
e2e1ed41
DV		 7372 /* Check which crtcs have changed outputs connected to them, these need
7373 * to be part of the prepare_pipes mask. We don't (yet) support global
7374 * modeset across multiple crtcs, so modeset_pipes will only have one
7375 * bit set at most. */
7376 list_for_each_entry(connector, &dev->mode_config.connector_list,
7377 base.head) {
7378 if (connector->base.encoder == &connector->new_encoder->base)
7379 continue;
79e53945 7380
e2e1ed41
DV		 7381 if (connector->base.encoder) {
7382 tmp_crtc = connector->base.encoder->crtc;
7383
7384 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7385 }
7386
7387 if (connector->new_encoder)
7388 *prepare_pipes |=
7389 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7390 }
7391
e2e1ed41
DV		 7392 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7393 base.head) {
7394 if (encoder->base.crtc == &encoder->new_crtc->base)
7395 continue;
7396
7397 if (encoder->base.crtc) {
7398 tmp_crtc = encoder->base.crtc;
7399
7400 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7401 }
7402
7403 if (encoder->new_crtc)
7404 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7405 }
7406
e2e1ed41
DV		 7407 /* Check for any pipes that will be fully disabled ... */
7408 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7409 base.head) {
7410 bool used = false;
22fd0fab 7411
e2e1ed41
DV		 7412 /* Don't try to disable disabled crtcs. */
7413 if (!intel_crtc->base.enabled)
7414 continue;
7e7d76c3 7415
e2e1ed41
DV		 7416 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7417 base.head) {
7418 if (encoder->new_crtc == intel_crtc)
7419 used = true;
7420 }
7421
7422 if (!used)
7423 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7424 }
7425
e2e1ed41
DV		 7426
7427 /* set_mode is also used to update properties on life display pipes. */
7428 intel_crtc = to_intel_crtc(crtc);
7429 if (crtc->enabled)
7430 *prepare_pipes |= 1 << intel_crtc->pipe;
7431
7432 /* We only support modeset on one single crtc, hence we need to do that
7433 * only for the passed in crtc iff we change anything else than just
7434 * disable crtcs.
7435 *
7436 * This is actually not true, to be fully compatible with the old crtc
7437 * helper we automatically disable _any_ output (i.e. doesn't need to be
7438 * connected to the crtc we're modesetting on) if it's disconnected.
7439 * Which is a rather nutty api (since changed the output configuration
7440 * without userspace's explicit request can lead to confusion), but
7441 * alas. Hence we currently need to modeset on all pipes we prepare. */
7442 if (*prepare_pipes)
7443 *modeset_pipes = *prepare_pipes;
7444
7445 /* ... and mask these out. */
7446 *modeset_pipes &= ~(*disable_pipes);
7447 *prepare_pipes &= ~(*disable_pipes);
7448}
7449
ea9d758d
DV		 7450static bool intel_crtc_in_use(struct drm_crtc *crtc)
7451{
7452 struct drm_encoder *encoder;
7453 struct drm_device *dev = crtc->dev;
7454
7455 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7456 if (encoder->crtc == crtc)
7457 return true;
7458
7459 return false;
7460}
7461
7462static void
7463intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7464{
7465 struct intel_encoder *intel_encoder;
7466 struct intel_crtc *intel_crtc;
7467 struct drm_connector *connector;
7468
7469 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7470 base.head) {
7471 if (!intel_encoder->base.crtc)
7472 continue;
7473
7474 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7475
7476 if (prepare_pipes & (1 << intel_crtc->pipe))
7477 intel_encoder->connectors_active = false;
7478 }
7479
7480 intel_modeset_commit_output_state(dev);
7481
7482 /* Update computed state. */
7483 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7484 base.head) {
7485 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7486 }
7487
7488 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7489 if (!connector->encoder || !connector->encoder->crtc)
7490 continue;
7491
7492 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7493
7494 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 7495 struct drm_property *dpms_property =
7496 dev->mode_config.dpms_property;
7497
ea9d758d 7498 connector->dpms = DRM_MODE_DPMS_ON;
68d34720
DV		 7499 drm_connector_property_set_value(connector,
7500 dpms_property,
7501 DRM_MODE_DPMS_ON);
ea9d758d
DV		 7502
7503 intel_encoder = to_intel_encoder(connector->encoder);
7504 intel_encoder->connectors_active = true;
7505 }
7506 }
7507
7508}
7509
25c5b266
DV		 7510#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7511 list_for_each_entry((intel_crtc), \
7512 &(dev)->mode_config.crtc_list, \
7513 base.head) \
7514 if (mask & (1 <<(intel_crtc)->pipe)) \
7515
b980514c 7516void
8af6cf88
DV		 7517intel_modeset_check_state(struct drm_device *dev)
7518{
7519 struct intel_crtc *crtc;
7520 struct intel_encoder *encoder;
7521 struct intel_connector *connector;
7522
7523 list_for_each_entry(connector, &dev->mode_config.connector_list,
7524 base.head) {
7525 /* This also checks the encoder/connector hw state with the
7526 * ->get_hw_state callbacks. */
7527 intel_connector_check_state(connector);
7528
7529 WARN(&connector->new_encoder->base != connector->base.encoder,
7530 "connector's staged encoder doesn't match current encoder\n");
7531 }
7532
7533 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7534 base.head) {
7535 bool enabled = false;
7536 bool active = false;
7537 enum pipe pipe, tracked_pipe;
7538
7539 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7540 encoder->base.base.id,
7541 drm_get_encoder_name(&encoder->base));
7542
7543 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7544 "encoder's stage crtc doesn't match current crtc\n");
7545 WARN(encoder->connectors_active && !encoder->base.crtc,
7546 "encoder's active_connectors set, but no crtc\n");
7547
7548 list_for_each_entry(connector, &dev->mode_config.connector_list,
7549 base.head) {
7550 if (connector->base.encoder != &encoder->base)
7551 continue;
7552 enabled = true;
7553 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7554 active = true;
7555 }
7556 WARN(!!encoder->base.crtc != enabled,
7557 "encoder's enabled state mismatch "
7558 "(expected %i, found %i)\n",
7559 !!encoder->base.crtc, enabled);
7560 WARN(active && !encoder->base.crtc,
7561 "active encoder with no crtc\n");
7562
7563 WARN(encoder->connectors_active != active,
7564 "encoder's computed active state doesn't match tracked active state "
7565 "(expected %i, found %i)\n", active, encoder->connectors_active);
7566
7567 active = encoder->get_hw_state(encoder, &pipe);
7568 WARN(active != encoder->connectors_active,
7569 "encoder's hw state doesn't match sw tracking "
7570 "(expected %i, found %i)\n",
7571 encoder->connectors_active, active);
7572
7573 if (!encoder->base.crtc)
7574 continue;
7575
7576 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7577 WARN(active && pipe != tracked_pipe,
7578 "active encoder's pipe doesn't match"
7579 "(expected %i, found %i)\n",
7580 tracked_pipe, pipe);
7581
7582 }
7583
7584 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7585 base.head) {
7586 bool enabled = false;
7587 bool active = false;
7588
7589 DRM_DEBUG_KMS("[CRTC:%d]\n",
7590 crtc->base.base.id);
7591
7592 WARN(crtc->active && !crtc->base.enabled,
7593 "active crtc, but not enabled in sw tracking\n");
7594
7595 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7596 base.head) {
7597 if (encoder->base.crtc != &crtc->base)
7598 continue;
7599 enabled = true;
7600 if (encoder->connectors_active)
7601 active = true;
7602 }
7603 WARN(active != crtc->active,
7604 "crtc's computed active state doesn't match tracked active state "
7605 "(expected %i, found %i)\n", active, crtc->active);
7606 WARN(enabled != crtc->base.enabled,
7607 "crtc's computed enabled state doesn't match tracked enabled state "
7608 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7609
7610 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7611 }
7612}
7613
a6778b3c
DV		 7614bool intel_set_mode(struct drm_crtc *crtc,
7615 struct drm_display_mode *mode,
94352cf9 7616 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 7617{
7618 struct drm_device *dev = crtc->dev;
dbf2b54e 7619 drm_i915_private_t *dev_priv = dev->dev_private;
a6778b3c 7620 struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
a6778b3c 7621 struct drm_encoder_helper_funcs *encoder_funcs;
a6778b3c 7622 struct drm_encoder *encoder;
25c5b266
DV		 7623 struct intel_crtc *intel_crtc;
7624 unsigned disable_pipes, prepare_pipes, modeset_pipes;
a6778b3c
DV		 7625 bool ret = true;
7626
e2e1ed41 7627 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 7628 &prepare_pipes, &disable_pipes);
7629
7630 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7631 modeset_pipes, prepare_pipes, disable_pipes);
e2e1ed41 7632
976f8a20
DV		 7633 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7634 intel_crtc_disable(&intel_crtc->base);
87f1faa6 7635
a6778b3c
DV		 7636 saved_hwmode = crtc->hwmode;
7637 saved_mode = crtc->mode;
a6778b3c 7638
25c5b266
DV		 7639 /* Hack: Because we don't (yet) support global modeset on multiple
7640 * crtcs, we don't keep track of the new mode for more than one crtc.
7641 * Hence simply check whether any bit is set in modeset_pipes in all the
7642 * pieces of code that are not yet converted to deal with mutliple crtcs
7643 * changing their mode at the same time. */
7644 adjusted_mode = NULL;
7645 if (modeset_pipes) {
7646 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7647 if (IS_ERR(adjusted_mode)) {
7648 return false;
7649 }
25c5b266 7650 }
a6778b3c 7651
ea9d758d
DV		 7652 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7653 if (intel_crtc->base.enabled)
7654 dev_priv->display.crtc_disable(&intel_crtc->base);
7655 }
a6778b3c 7656
6c4c86f5
DV		 7657 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7658 * to set it here already despite that we pass it down the callchain.
7659 */
7660 if (modeset_pipes)
25c5b266 7661 crtc->mode = *mode;
7758a113 7662
ea9d758d
DV		 7663 /* Only after disabling all output pipelines that will be changed can we
7664 * update the the output configuration. */
7665 intel_modeset_update_state(dev, prepare_pipes);
7666
47fab737
DV		 7667 if (dev_priv->display.modeset_global_resources)
7668 dev_priv->display.modeset_global_resources(dev);
7669
a6778b3c
DV		 7670 /* Set up the DPLL and any encoders state that needs to adjust or depend
7671 * on the DPLL.
7672 */
25c5b266
DV		 7673 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7674 ret = !intel_crtc_mode_set(&intel_crtc->base,
7675 mode, adjusted_mode,
7676 x, y, fb);
7677 if (!ret)
7678 goto done;
a6778b3c 7679
25c5b266 7680 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
a6778b3c 7681
25c5b266
DV		 7682 if (encoder->crtc != &intel_crtc->base)
7683 continue;
a6778b3c 7684
25c5b266
DV		 7685 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
7686 encoder->base.id, drm_get_encoder_name(encoder),
7687 mode->base.id, mode->name);
7688 encoder_funcs = encoder->helper_private;
7689 encoder_funcs->mode_set(encoder, mode, adjusted_mode);
7690 }
a6778b3c
DV		 7691 }
7692
7693 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 7694 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7695 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 7696
25c5b266
DV		 7697 if (modeset_pipes) {
7698 /* Store real post-adjustment hardware mode. */
7699 crtc->hwmode = *adjusted_mode;
a6778b3c 7700
25c5b266
DV		 7701 /* Calculate and store various constants which
7702 * are later needed by vblank and swap-completion
7703 * timestamping. They are derived from true hwmode.
7704 */
7705 drm_calc_timestamping_constants(crtc);
7706 }
a6778b3c
DV		 7707
7708 /* FIXME: add subpixel order */
7709done:
7710 drm_mode_destroy(dev, adjusted_mode);
25c5b266 7711 if (!ret && crtc->enabled) {
a6778b3c
DV		 7712 crtc->hwmode = saved_hwmode;
7713 crtc->mode = saved_mode;
8af6cf88
DV		 7714 } else {
7715 intel_modeset_check_state(dev);
a6778b3c
DV		 7716 }
7717
7718 return ret;
7719}
7720
25c5b266
DV		 7721#undef for_each_intel_crtc_masked
7722
d9e55608
DV		 7723static void intel_set_config_free(struct intel_set_config *config)
7724{
7725 if (!config)
7726 return;
7727
1aa4b628
DV		 7728 kfree(config->save_connector_encoders);
7729 kfree(config->save_encoder_crtcs);
d9e55608
DV		 7730 kfree(config);
7731}
7732
85f9eb71
DV		 7733static int intel_set_config_save_state(struct drm_device *dev,
7734 struct intel_set_config *config)
7735{
85f9eb71
DV		 7736 struct drm_encoder *encoder;
7737 struct drm_connector *connector;
7738 int count;
7739
1aa4b628
DV		 7740 config->save_encoder_crtcs =
7741 kcalloc(dev->mode_config.num_encoder,
7742 sizeof(struct drm_crtc *), GFP_KERNEL);
7743 if (!config->save_encoder_crtcs)
85f9eb71
DV		 7744 return -ENOMEM;
7745
1aa4b628
DV		 7746 config->save_connector_encoders =
7747 kcalloc(dev->mode_config.num_connector,
7748 sizeof(struct drm_encoder *), GFP_KERNEL);
7749 if (!config->save_connector_encoders)
85f9eb71
DV		 7750 return -ENOMEM;
7751
7752 /* Copy data. Note that driver private data is not affected.
7753 * Should anything bad happen only the expected state is
7754 * restored, not the drivers personal bookkeeping.
7755 */
85f9eb71
DV		 7756 count = 0;
7757 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 7758 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 7759 }
7760
7761 count = 0;
7762 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 7763 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 7764 }
7765
7766 return 0;
7767}
7768
7769static void intel_set_config_restore_state(struct drm_device *dev,
7770 struct intel_set_config *config)
7771{
9a935856
DV		 7772 struct intel_encoder *encoder;
7773 struct intel_connector *connector;
85f9eb71
DV		 7774 int count;
7775
85f9eb71 7776 count = 0;
9a935856
DV		 7777 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7778 encoder->new_crtc =
7779 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 7780 }
7781
7782 count = 0;
9a935856
DV		 7783 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7784 connector->new_encoder =
7785 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 7786 }
7787}
7788
5e2b584e
DV		 7789static void
7790intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7791 struct intel_set_config *config)
7792{
7793
7794 /* We should be able to check here if the fb has the same properties
7795 * and then just flip_or_move it */
7796 if (set->crtc->fb != set->fb) {
7797 /* If we have no fb then treat it as a full mode set */
7798 if (set->crtc->fb == NULL) {
7799 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7800 config->mode_changed = true;
7801 } else if (set->fb == NULL) {
7802 config->mode_changed = true;
7803 } else if (set->fb->depth != set->crtc->fb->depth) {
7804 config->mode_changed = true;
7805 } else if (set->fb->bits_per_pixel !=
7806 set->crtc->fb->bits_per_pixel) {
7807 config->mode_changed = true;
7808 } else
7809 config->fb_changed = true;
7810 }
7811
835c5873 7812 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 7813 config->fb_changed = true;
7814
7815 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7816 DRM_DEBUG_KMS("modes are different, full mode set\n");
7817 drm_mode_debug_printmodeline(&set->crtc->mode);
7818 drm_mode_debug_printmodeline(set->mode);
7819 config->mode_changed = true;
7820 }
7821}
7822
2e431051 7823static int
9a935856
DV		 7824intel_modeset_stage_output_state(struct drm_device *dev,
7825 struct drm_mode_set *set,
7826 struct intel_set_config *config)
50f56119 7827{
85f9eb71 7828 struct drm_crtc *new_crtc;
9a935856
DV		 7829 struct intel_connector *connector;
7830 struct intel_encoder *encoder;
2e431051 7831 int count, ro;
50f56119 7832
9a935856
DV		 7833 /* The upper layers ensure that we either disabl a crtc or have a list
7834 * of connectors. For paranoia, double-check this. */
7835 WARN_ON(!set->fb && (set->num_connectors != 0));
7836 WARN_ON(set->fb && (set->num_connectors == 0));
7837
50f56119 7838 count = 0;
9a935856
DV		 7839 list_for_each_entry(connector, &dev->mode_config.connector_list,
7840 base.head) {
7841 /* Otherwise traverse passed in connector list and get encoders
7842 * for them. */
50f56119 7843 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 7844 if (set->connectors[ro] == &connector->base) {
7845 connector->new_encoder = connector->encoder;
50f56119
DV		 7846 break;
7847 }
7848 }
7849
9a935856
DV		 7850 /* If we disable the crtc, disable all its connectors. Also, if
7851 * the connector is on the changing crtc but not on the new
7852 * connector list, disable it. */
7853 if ((!set->fb || ro == set->num_connectors) &&
7854 connector->base.encoder &&
7855 connector->base.encoder->crtc == set->crtc) {
7856 connector->new_encoder = NULL;
7857
7858 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7859 connector->base.base.id,
7860 drm_get_connector_name(&connector->base));
7861 }
7862
7863
7864 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 7865 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 7866 config->mode_changed = true;
50f56119 7867 }
9a935856
DV		 7868
7869 /* Disable all disconnected encoders. */
7870 if (connector->base.status == connector_status_disconnected)
7871 connector->new_encoder = NULL;
50f56119 7872 }
9a935856 7873 /* connector->new_encoder is now updated for all connectors. */
50f56119 7874
9a935856 7875 /* Update crtc of enabled connectors. */
50f56119 7876 count = 0;
9a935856
DV		 7877 list_for_each_entry(connector, &dev->mode_config.connector_list,
7878 base.head) {
7879 if (!connector->new_encoder)
50f56119
DV		 7880 continue;
7881
9a935856 7882 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 7883
7884 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 7885 if (set->connectors[ro] == &connector->base)
50f56119
DV		 7886 new_crtc = set->crtc;
7887 }
7888
7889 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 7890 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
7891 new_crtc)) {
5e2b584e 7892 return -EINVAL;
50f56119 7893 }
9a935856
DV		 7894 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
7895
7896 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
7897 connector->base.base.id,
7898 drm_get_connector_name(&connector->base),
7899 new_crtc->base.id);
7900 }
7901
7902 /* Check for any encoders that needs to be disabled. */
7903 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7904 base.head) {
7905 list_for_each_entry(connector,
7906 &dev->mode_config.connector_list,
7907 base.head) {
7908 if (connector->new_encoder == encoder) {
7909 WARN_ON(!connector->new_encoder->new_crtc);
7910
7911 goto next_encoder;
7912 }
7913 }
7914 encoder->new_crtc = NULL;
7915next_encoder:
7916 /* Only now check for crtc changes so we don't miss encoders
7917 * that will be disabled. */
7918 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 7919 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 7920 config->mode_changed = true;
50f56119
DV		 7921 }
7922 }
9a935856 7923 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 7924
2e431051
DV		 7925 return 0;
7926}
7927
7928static int intel_crtc_set_config(struct drm_mode_set *set)
7929{
7930 struct drm_device *dev;
2e431051
DV		 7931 struct drm_mode_set save_set;
7932 struct intel_set_config *config;
7933 int ret;
2e431051 7934
8d3e375e
DV		 7935 BUG_ON(!set);
7936 BUG_ON(!set->crtc);
7937 BUG_ON(!set->crtc->helper_private);
2e431051
DV		 7938
7939 if (!set->mode)
7940 set->fb = NULL;
7941
431e50f7
DV		 7942 /* The fb helper likes to play gross jokes with ->mode_set_config.
7943 * Unfortunately the crtc helper doesn't do much at all for this case,
7944 * so we have to cope with this madness until the fb helper is fixed up. */
7945 if (set->fb && set->num_connectors == 0)
7946 return 0;
7947
2e431051
DV		 7948 if (set->fb) {
7949 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
7950 set->crtc->base.id, set->fb->base.id,
7951 (int)set->num_connectors, set->x, set->y);
7952 } else {
7953 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 7954 }
7955
7956 dev = set->crtc->dev;
7957
7958 ret = -ENOMEM;
7959 config = kzalloc(sizeof(*config), GFP_KERNEL);
7960 if (!config)
7961 goto out_config;
7962
7963 ret = intel_set_config_save_state(dev, config);
7964 if (ret)
7965 goto out_config;
7966
7967 save_set.crtc = set->crtc;
7968 save_set.mode = &set->crtc->mode;
7969 save_set.x = set->crtc->x;
7970 save_set.y = set->crtc->y;
7971 save_set.fb = set->crtc->fb;
7972
7973 /* Compute whether we need a full modeset, only an fb base update or no
7974 * change at all. In the future we might also check whether only the
7975 * mode changed, e.g. for LVDS where we only change the panel fitter in
7976 * such cases. */
7977 intel_set_config_compute_mode_changes(set, config);
7978
9a935856 7979 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 7980 if (ret)
7981 goto fail;
7982
5e2b584e 7983 if (config->mode_changed) {
87f1faa6 7984 if (set->mode) {
50f56119
DV		 7985 DRM_DEBUG_KMS("attempting to set mode from"
7986 " userspace\n");
7987 drm_mode_debug_printmodeline(set->mode);
87f1faa6
DV		 7988 }
7989
7990 if (!intel_set_mode(set->crtc, set->mode,
7991 set->x, set->y, set->fb)) {
7992 DRM_ERROR("failed to set mode on [CRTC:%d]\n",
7993 set->crtc->base.id);
7994 ret = -EINVAL;
7995 goto fail;
7996 }
5e2b584e 7997 } else if (config->fb_changed) {
4f660f49 7998 ret = intel_pipe_set_base(set->crtc,
94352cf9 7999 set->x, set->y, set->fb);
50f56119
DV		 8000 }
8001
d9e55608
DV		 8002 intel_set_config_free(config);
8003
50f56119
DV		 8004 return 0;
8005
8006fail:
85f9eb71 8007 intel_set_config_restore_state(dev, config);
50f56119
DV		 8008
8009 /* Try to restore the config */
5e2b584e 8010 if (config->mode_changed &&
a6778b3c
DV		 8011 !intel_set_mode(save_set.crtc, save_set.mode,
8012 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 8013 DRM_ERROR("failed to restore config after modeset failure\n");
8014
d9e55608
DV		 8015out_config:
8016 intel_set_config_free(config);
50f56119
DV		 8017 return ret;
8018}
8019
f6e5b160 8020static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8021 .cursor_set = intel_crtc_cursor_set,
8022 .cursor_move = intel_crtc_cursor_move,
8023 .gamma_set = intel_crtc_gamma_set,
50f56119 8024 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8025 .destroy = intel_crtc_destroy,
8026 .page_flip = intel_crtc_page_flip,
8027};
8028
79f689aa
PZ		 8029static void intel_cpu_pll_init(struct drm_device *dev)
8030{
8031 if (IS_HASWELL(dev))
8032 intel_ddi_pll_init(dev);
8033}
8034
ee7b9f93
JB		 8035static void intel_pch_pll_init(struct drm_device *dev)
8036{
8037 drm_i915_private_t *dev_priv = dev->dev_private;
8038 int i;
8039
8040 if (dev_priv->num_pch_pll == 0) {
8041 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8042 return;
8043 }
8044
8045 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8046 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8047 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8048 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8049 }
8050}
8051
b358d0a6 8052static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8053{
22fd0fab 8054 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8055 struct intel_crtc *intel_crtc;
8056 int i;
8057
8058 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8059 if (intel_crtc == NULL)
8060 return;
8061
8062 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8063
8064 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8065 for (i = 0; i < 256; i++) {
8066 intel_crtc->lut_r[i] = i;
8067 intel_crtc->lut_g[i] = i;
8068 intel_crtc->lut_b[i] = i;
8069 }
8070
80824003
JB		 8071 /* Swap pipes & planes for FBC on pre-965 */
8072 intel_crtc->pipe = pipe;
8073 intel_crtc->plane = pipe;
a5c961d1 8074 intel_crtc->cpu_transcoder = pipe;
e2e767ab 8075 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8076 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8077 intel_crtc->plane = !pipe;
80824003
JB		 8078 }
8079
22fd0fab
JB		 8080 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8081 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8082 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8083 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8084
5a354204 8085 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3 8086
79e53945 8087 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8088}
8089
08d7b3d1 8090int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8091 struct drm_file *file)
08d7b3d1 8092{
08d7b3d1 8093 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8094 struct drm_mode_object *drmmode_obj;
8095 struct intel_crtc *crtc;
08d7b3d1 8096
1cff8f6b
DV		 8097 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8098 return -ENODEV;
08d7b3d1 8099
c05422d5
DV		 8100 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8101 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8102
c05422d5 8103 if (!drmmode_obj) {
08d7b3d1
CW		 8104 DRM_ERROR("no such CRTC id\n");
8105 return -EINVAL;
8106 }
8107
c05422d5
DV		 8108 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8109 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8110
c05422d5 8111 return 0;
08d7b3d1
CW		 8112}
8113
66a9278e 8114static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8115{
66a9278e
DV		 8116 struct drm_device *dev = encoder->base.dev;
8117 struct intel_encoder *source_encoder;
79e53945 8118 int index_mask = 0;
79e53945
JB		 8119 int entry = 0;
8120
66a9278e
DV		 8121 list_for_each_entry(source_encoder,
8122 &dev->mode_config.encoder_list, base.head) {
8123
8124 if (encoder == source_encoder)
79e53945 8125 index_mask |= (1 << entry);
66a9278e
DV		 8126
8127 /* Intel hw has only one MUX where enocoders could be cloned. */
8128 if (encoder->cloneable && source_encoder->cloneable)
8129 index_mask |= (1 << entry);
8130
79e53945
JB		 8131 entry++;
8132 }
4ef69c7a 8133
79e53945
JB		 8134 return index_mask;
8135}
8136
4d302442
CW		 8137static bool has_edp_a(struct drm_device *dev)
8138{
8139 struct drm_i915_private *dev_priv = dev->dev_private;
8140
8141 if (!IS_MOBILE(dev))
8142 return false;
8143
8144 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8145 return false;
8146
8147 if (IS_GEN5(dev) &&
8148 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8149 return false;
8150
8151 return true;
8152}
8153
79e53945
JB		 8154static void intel_setup_outputs(struct drm_device *dev)
8155{
725e30ad 8156 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8157 struct intel_encoder *encoder;
cb0953d7 8158 bool dpd_is_edp = false;
f3cfcba6 8159 bool has_lvds;
79e53945 8160
f3cfcba6 8161 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 8162 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8163 /* disable the panel fitter on everything but LVDS */
8164 I915_WRITE(PFIT_CONTROL, 0);
8165 }
79e53945 8166
bad720ff 8167 if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8168 dpd_is_edp = intel_dpd_is_edp(dev);
30ad48b7 8169
4d302442 8170 if (has_edp_a(dev))
ab9d7c30 8171 intel_dp_init(dev, DP_A, PORT_A);
32f9d658 8172
cb0953d7 8173 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
ab9d7c30 8174 intel_dp_init(dev, PCH_DP_D, PORT_D);
cb0953d7
AJ		 8175 }
8176
8177 intel_crt_init(dev);
8178
0e72a5b5
ED		 8179 if (IS_HASWELL(dev)) {
8180 int found;
8181
8182 /* Haswell uses DDI functions to detect digital outputs */
8183 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8184 /* DDI A only supports eDP */
8185 if (found)
8186 intel_ddi_init(dev, PORT_A);
8187
8188 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8189 * register */
8190 found = I915_READ(SFUSE_STRAP);
8191
8192 if (found & SFUSE_STRAP_DDIB_DETECTED)
8193 intel_ddi_init(dev, PORT_B);
8194 if (found & SFUSE_STRAP_DDIC_DETECTED)
8195 intel_ddi_init(dev, PORT_C);
8196 if (found & SFUSE_STRAP_DDID_DETECTED)
8197 intel_ddi_init(dev, PORT_D);
8198 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7
AJ		 8199 int found;
8200
30ad48b7 8201 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca 8202 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8203 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 8204 if (!found)
08d644ad 8205 intel_hdmi_init(dev, HDMIB, PORT_B);
5eb08b69 8206 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 8207 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 8208 }
8209
8210 if (I915_READ(HDMIC) & PORT_DETECTED)
08d644ad 8211 intel_hdmi_init(dev, HDMIC, PORT_C);
30ad48b7 8212
b708a1d5 8213 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
08d644ad 8214 intel_hdmi_init(dev, HDMID, PORT_D);
30ad48b7 8215
5eb08b69 8216 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 8217 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 8218
cb0953d7 8219 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
ab9d7c30 8220 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d
JB		 8221 } else if (IS_VALLEYVIEW(dev)) {
8222 int found;
8223
19c03924
GB		 8224 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8225 if (I915_READ(DP_C) & DP_DETECTED)
8226 intel_dp_init(dev, DP_C, PORT_C);
8227
4a87d65d
JB		 8228 if (I915_READ(SDVOB) & PORT_DETECTED) {
8229 /* SDVOB multiplex with HDMIB */
8230 found = intel_sdvo_init(dev, SDVOB, true);
8231 if (!found)
08d644ad 8232 intel_hdmi_init(dev, SDVOB, PORT_B);
4a87d65d 8233 if (!found && (I915_READ(DP_B) & DP_DETECTED))
ab9d7c30 8234 intel_dp_init(dev, DP_B, PORT_B);
4a87d65d
JB		 8235 }
8236
8237 if (I915_READ(SDVOC) & PORT_DETECTED)
08d644ad 8238 intel_hdmi_init(dev, SDVOC, PORT_C);
5eb08b69 8239
103a196f 8240 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 8241 bool found = false;
7d57382e 8242
725e30ad 8243 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 8244 DRM_DEBUG_KMS("probing SDVOB\n");
eef4eacb 8245 found = intel_sdvo_init(dev, SDVOB, true);
b01f2c3a
JB		 8246 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8247 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
08d644ad 8248 intel_hdmi_init(dev, SDVOB, PORT_B);
b01f2c3a 8249 }
27185ae1 8250
b01f2c3a
JB		 8251 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8252 DRM_DEBUG_KMS("probing DP_B\n");
ab9d7c30 8253 intel_dp_init(dev, DP_B, PORT_B);
b01f2c3a 8254 }
725e30ad 8255 }
13520b05
KH		 8256
8257 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 8258
b01f2c3a
JB		 8259 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8260 DRM_DEBUG_KMS("probing SDVOC\n");
eef4eacb 8261 found = intel_sdvo_init(dev, SDVOC, false);
b01f2c3a 8262 }
27185ae1
ML		 8263
8264 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8265
b01f2c3a
JB		 8266 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8267 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
08d644ad 8268 intel_hdmi_init(dev, SDVOC, PORT_C);
b01f2c3a
JB		 8269 }
8270 if (SUPPORTS_INTEGRATED_DP(dev)) {
8271 DRM_DEBUG_KMS("probing DP_C\n");
ab9d7c30 8272 intel_dp_init(dev, DP_C, PORT_C);
b01f2c3a 8273 }
725e30ad 8274 }
27185ae1 8275
b01f2c3a
JB		 8276 if (SUPPORTS_INTEGRATED_DP(dev) &&
8277 (I915_READ(DP_D) & DP_DETECTED)) {
8278 DRM_DEBUG_KMS("probing DP_D\n");
ab9d7c30 8279 intel_dp_init(dev, DP_D, PORT_D);
b01f2c3a 8280 }
bad720ff 8281 } else if (IS_GEN2(dev))
79e53945
JB		 8282 intel_dvo_init(dev);
8283
103a196f 8284 if (SUPPORTS_TV(dev))
79e53945
JB		 8285 intel_tv_init(dev);
8286
4ef69c7a
CW		 8287 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8288 encoder->base.possible_crtcs = encoder->crtc_mask;
8289 encoder->base.possible_clones =
66a9278e 8290 intel_encoder_clones(encoder);
79e53945 8291 }
47356eb6 8292
40579abe 8293 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9fb526db 8294 ironlake_init_pch_refclk(dev);
79e53945
JB		 8295}
8296
8297static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8298{
8299 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 8300
8301 drm_framebuffer_cleanup(fb);
05394f39 8302 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 8303
8304 kfree(intel_fb);
8305}
8306
8307static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 8308 struct drm_file *file,
79e53945
JB		 8309 unsigned int *handle)
8310{
8311 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 8312 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 8313
05394f39 8314 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 8315}
8316
8317static const struct drm_framebuffer_funcs intel_fb_funcs = {
8318 .destroy = intel_user_framebuffer_destroy,
8319 .create_handle = intel_user_framebuffer_create_handle,
8320};
8321
38651674
DA		 8322int intel_framebuffer_init(struct drm_device *dev,
8323 struct intel_framebuffer *intel_fb,
308e5bcb 8324 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 8325 struct drm_i915_gem_object *obj)
79e53945 8326{
79e53945
JB		 8327 int ret;
8328
05394f39 8329 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 8330 return -EINVAL;
8331
308e5bcb 8332 if (mode_cmd->pitches[0] & 63)
57cd6508
CW		 8333 return -EINVAL;
8334
308e5bcb 8335 switch (mode_cmd->pixel_format) {
04b3924d
VS		 8336 case DRM_FORMAT_RGB332:
8337 case DRM_FORMAT_RGB565:
8338 case DRM_FORMAT_XRGB8888:
b250da79 8339 case DRM_FORMAT_XBGR8888:
04b3924d
VS		 8340 case DRM_FORMAT_ARGB8888:
8341 case DRM_FORMAT_XRGB2101010:
8342 case DRM_FORMAT_ARGB2101010:
308e5bcb 8343 /* RGB formats are common across chipsets */
b5626747 8344 break;
04b3924d
VS		 8345 case DRM_FORMAT_YUYV:
8346 case DRM_FORMAT_UYVY:
8347 case DRM_FORMAT_YVYU:
8348 case DRM_FORMAT_VYUY:
57cd6508
CW		 8349 break;
8350 default:
aca25848
ED		 8351 DRM_DEBUG_KMS("unsupported pixel format %u\n",
8352 mode_cmd->pixel_format);
57cd6508
CW		 8353 return -EINVAL;
8354 }
8355
79e53945
JB		 8356 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8357 if (ret) {
8358 DRM_ERROR("framebuffer init failed %d\n", ret);
8359 return ret;
8360 }
8361
8362 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 8363 intel_fb->obj = obj;
79e53945
JB		 8364 return 0;
8365}
8366
79e53945
JB		 8367static struct drm_framebuffer *
8368intel_user_framebuffer_create(struct drm_device *dev,
8369 struct drm_file *filp,
308e5bcb 8370 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 8371{
05394f39 8372 struct drm_i915_gem_object *obj;
79e53945 8373
308e5bcb
JB		 8374 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8375 mode_cmd->handles[0]));
c8725226 8376 if (&obj->base == NULL)
cce13ff7 8377 return ERR_PTR(-ENOENT);
79e53945 8378
d2dff872 8379 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 8380}
8381
79e53945 8382static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 8383 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 8384 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 8385};
8386
e70236a8
JB		 8387/* Set up chip specific display functions */
8388static void intel_init_display(struct drm_device *dev)
8389{
8390 struct drm_i915_private *dev_priv = dev->dev_private;
8391
8392 /* We always want a DPMS function */
09b4ddf9
PZ		 8393 if (IS_HASWELL(dev)) {
8394 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 8395 dev_priv->display.crtc_enable = haswell_crtc_enable;
8396 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 8397 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 8398 dev_priv->display.update_plane = ironlake_update_plane;
8399 } else if (HAS_PCH_SPLIT(dev)) {
f564048e 8400 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 8401 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8402 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 8403 dev_priv->display.off = ironlake_crtc_off;
17638cd6 8404 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 8405 } else {
f564048e 8406 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 8407 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8408 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 8409 dev_priv->display.off = i9xx_crtc_off;
17638cd6 8410 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8411 }
e70236a8 8412
e70236a8 8413 /* Returns the core display clock speed */
25eb05fc
JB		 8414 if (IS_VALLEYVIEW(dev))
8415 dev_priv->display.get_display_clock_speed =
8416 valleyview_get_display_clock_speed;
8417 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 8418 dev_priv->display.get_display_clock_speed =
8419 i945_get_display_clock_speed;
8420 else if (IS_I915G(dev))
8421 dev_priv->display.get_display_clock_speed =
8422 i915_get_display_clock_speed;
f2b115e6 8423 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 8424 dev_priv->display.get_display_clock_speed =
8425 i9xx_misc_get_display_clock_speed;
8426 else if (IS_I915GM(dev))
8427 dev_priv->display.get_display_clock_speed =
8428 i915gm_get_display_clock_speed;
8429 else if (IS_I865G(dev))
8430 dev_priv->display.get_display_clock_speed =
8431 i865_get_display_clock_speed;
f0f8a9ce 8432 else if (IS_I85X(dev))
e70236a8
JB		 8433 dev_priv->display.get_display_clock_speed =
8434 i855_get_display_clock_speed;
8435 else /* 852, 830 */
8436 dev_priv->display.get_display_clock_speed =
8437 i830_get_display_clock_speed;
8438
7f8a8569 8439 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 8440 if (IS_GEN5(dev)) {
674cf967 8441 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 8442 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 8443 } else if (IS_GEN6(dev)) {
674cf967 8444 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 8445 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 8446 } else if (IS_IVYBRIDGE(dev)) {
8447 /* FIXME: detect B0+ stepping and use auto training */
8448 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 8449 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 8450 dev_priv->display.modeset_global_resources =
8451 ivb_modeset_global_resources;
c82e4d26
ED		 8452 } else if (IS_HASWELL(dev)) {
8453 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 8454 dev_priv->display.write_eld = haswell_write_eld;
7f8a8569
ZW		 8455 } else
8456 dev_priv->display.update_wm = NULL;
6067aaea 8457 } else if (IS_G4X(dev)) {
e0dac65e 8458 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 8459 }
8c9f3aaf
JB		 8460
8461 /* Default just returns -ENODEV to indicate unsupported */
8462 dev_priv->display.queue_flip = intel_default_queue_flip;
8463
8464 switch (INTEL_INFO(dev)->gen) {
8465 case 2:
8466 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8467 break;
8468
8469 case 3:
8470 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8471 break;
8472
8473 case 4:
8474 case 5:
8475 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8476 break;
8477
8478 case 6:
8479 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8480 break;
7c9017e5
JB		 8481 case 7:
8482 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8483 break;
8c9f3aaf 8484 }
e70236a8
JB		 8485}
8486
b690e96c
JB		 8487/*
8488 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8489 * resume, or other times. This quirk makes sure that's the case for
8490 * affected systems.
8491 */
0206e353 8492static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 8493{
8494 struct drm_i915_private *dev_priv = dev->dev_private;
8495
8496 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 8497 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 8498}
8499
435793df
KP		 8500/*
8501 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8502 */
8503static void quirk_ssc_force_disable(struct drm_device *dev)
8504{
8505 struct drm_i915_private *dev_priv = dev->dev_private;
8506 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 8507 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 8508}
8509
4dca20ef 8510/*
5a15ab5b
CE		 8511 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8512 * brightness value
4dca20ef
CE		 8513 */
8514static void quirk_invert_brightness(struct drm_device *dev)
8515{
8516 struct drm_i915_private *dev_priv = dev->dev_private;
8517 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 8518 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 8519}
8520
b690e96c
JB		 8521struct intel_quirk {
8522 int device;
8523 int subsystem_vendor;
8524 int subsystem_device;
8525 void (*hook)(struct drm_device *dev);
8526};
8527
c43b5634 8528static struct intel_quirk intel_quirks[] = {
b690e96c 8529 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 8530 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 8531
b690e96c
JB		 8532 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8533 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8534
b690e96c
JB		 8535 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8536 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8537
ccd0d36e 8538 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 8539 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 8540 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 8541
8542 /* Lenovo U160 cannot use SSC on LVDS */
8543 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 8544
8545 /* Sony Vaio Y cannot use SSC on LVDS */
8546 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 8547
8548 /* Acer Aspire 5734Z must invert backlight brightness */
8549 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
b690e96c
JB		 8550};
8551
8552static void intel_init_quirks(struct drm_device *dev)
8553{
8554 struct pci_dev *d = dev->pdev;
8555 int i;
8556
8557 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8558 struct intel_quirk *q = &intel_quirks[i];
8559
8560 if (d->device == q->device &&
8561 (d->subsystem_vendor == q->subsystem_vendor ||
8562 q->subsystem_vendor == PCI_ANY_ID) &&
8563 (d->subsystem_device == q->subsystem_device ||
8564 q->subsystem_device == PCI_ANY_ID))
8565 q->hook(dev);
8566 }
8567}
8568
9cce37f4
JB		 8569/* Disable the VGA plane that we never use */
8570static void i915_disable_vga(struct drm_device *dev)
8571{
8572 struct drm_i915_private *dev_priv = dev->dev_private;
8573 u8 sr1;
8574 u32 vga_reg;
8575
8576 if (HAS_PCH_SPLIT(dev))
8577 vga_reg = CPU_VGACNTRL;
8578 else
8579 vga_reg = VGACNTRL;
8580
8581 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 8582 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 8583 sr1 = inb(VGA_SR_DATA);
8584 outb(sr1 | 1<<5, VGA_SR_DATA);
8585 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8586 udelay(300);
8587
8588 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8589 POSTING_READ(vga_reg);
8590}
8591
f817586c
DV		 8592void intel_modeset_init_hw(struct drm_device *dev)
8593{
0232e927
ED		 8594 /* We attempt to init the necessary power wells early in the initialization
8595 * time, so the subsystems that expect power to be enabled can work.
8596 */
8597 intel_init_power_wells(dev);
8598
a8f78b58
ED		 8599 intel_prepare_ddi(dev);
8600
f817586c
DV		 8601 intel_init_clock_gating(dev);
8602
79f5b2c7 8603 mutex_lock(&dev->struct_mutex);
8090c6b9 8604 intel_enable_gt_powersave(dev);
79f5b2c7 8605 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 8606}
8607
79e53945
JB		 8608void intel_modeset_init(struct drm_device *dev)
8609{
652c393a 8610 struct drm_i915_private *dev_priv = dev->dev_private;
b840d907 8611 int i, ret;
79e53945
JB		 8612
8613 drm_mode_config_init(dev);
8614
8615 dev->mode_config.min_width = 0;
8616 dev->mode_config.min_height = 0;
8617
019d96cb
DA		 8618 dev->mode_config.preferred_depth = 24;
8619 dev->mode_config.prefer_shadow = 1;
8620
e6ecefaa 8621 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 8622
b690e96c
JB		 8623 intel_init_quirks(dev);
8624
1fa61106
ED		 8625 intel_init_pm(dev);
8626
e70236a8
JB		 8627 intel_init_display(dev);
8628
a6c45cf0
CW		 8629 if (IS_GEN2(dev)) {
8630 dev->mode_config.max_width = 2048;
8631 dev->mode_config.max_height = 2048;
8632 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 8633 dev->mode_config.max_width = 4096;
8634 dev->mode_config.max_height = 4096;
79e53945 8635 } else {
a6c45cf0
CW		 8636 dev->mode_config.max_width = 8192;
8637 dev->mode_config.max_height = 8192;
79e53945 8638 }
dd2757f8 8639 dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
79e53945 8640
28c97730 8641 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 8642 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 8643
a3524f1b 8644 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945 8645 intel_crtc_init(dev, i);
00c2064b
JB		 8646 ret = intel_plane_init(dev, i);
8647 if (ret)
8648 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
79e53945
JB		 8649 }
8650
79f689aa 8651 intel_cpu_pll_init(dev);
ee7b9f93
JB		 8652 intel_pch_pll_init(dev);
8653
9cce37f4
JB		 8654 /* Just disable it once at startup */
8655 i915_disable_vga(dev);
79e53945 8656 intel_setup_outputs(dev);
2c7111db
CW		 8657}
8658
24929352
DV		 8659static void
8660intel_connector_break_all_links(struct intel_connector *connector)
8661{
8662 connector->base.dpms = DRM_MODE_DPMS_OFF;
8663 connector->base.encoder = NULL;
8664 connector->encoder->connectors_active = false;
8665 connector->encoder->base.crtc = NULL;
8666}
8667
7fad798e
DV		 8668static void intel_enable_pipe_a(struct drm_device *dev)
8669{
8670 struct intel_connector *connector;
8671 struct drm_connector *crt = NULL;
8672 struct intel_load_detect_pipe load_detect_temp;
8673
8674 /* We can't just switch on the pipe A, we need to set things up with a
8675 * proper mode and output configuration. As a gross hack, enable pipe A
8676 * by enabling the load detect pipe once. */
8677 list_for_each_entry(connector,
8678 &dev->mode_config.connector_list,
8679 base.head) {
8680 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8681 crt = &connector->base;
8682 break;
8683 }
8684 }
8685
8686 if (!crt)
8687 return;
8688
8689 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8690 intel_release_load_detect_pipe(crt, &load_detect_temp);
8691
8692
8693}
8694
fa555837
DV		 8695static bool
8696intel_check_plane_mapping(struct intel_crtc *crtc)
8697{
8698 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8699 u32 reg, val;
8700
8701 if (dev_priv->num_pipe == 1)
8702 return true;
8703
8704 reg = DSPCNTR(!crtc->plane);
8705 val = I915_READ(reg);
8706
8707 if ((val & DISPLAY_PLANE_ENABLE) &&
8708 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8709 return false;
8710
8711 return true;
8712}
8713
24929352
DV		 8714static void intel_sanitize_crtc(struct intel_crtc *crtc)
8715{
8716 struct drm_device *dev = crtc->base.dev;
8717 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 8718 u32 reg;
24929352 8719
24929352 8720 /* Clear any frame start delays used for debugging left by the BIOS */
702e7a56 8721 reg = PIPECONF(crtc->cpu_transcoder);
24929352
DV		 8722 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8723
8724 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 8725 * disable the crtc (and hence change the state) if it is wrong. Note
8726 * that gen4+ has a fixed plane -> pipe mapping. */
8727 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 8728 struct intel_connector *connector;
8729 bool plane;
8730
24929352
DV		 8731 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8732 crtc->base.base.id);
8733
8734 /* Pipe has the wrong plane attached and the plane is active.
8735 * Temporarily change the plane mapping and disable everything
8736 * ... */
8737 plane = crtc->plane;
8738 crtc->plane = !plane;
8739 dev_priv->display.crtc_disable(&crtc->base);
8740 crtc->plane = plane;
8741
8742 /* ... and break all links. */
8743 list_for_each_entry(connector, &dev->mode_config.connector_list,
8744 base.head) {
8745 if (connector->encoder->base.crtc != &crtc->base)
8746 continue;
8747
8748 intel_connector_break_all_links(connector);
8749 }
8750
8751 WARN_ON(crtc->active);
8752 crtc->base.enabled = false;
8753 }
24929352 8754
7fad798e
DV		 8755 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8756 crtc->pipe == PIPE_A && !crtc->active) {
8757 /* BIOS forgot to enable pipe A, this mostly happens after
8758 * resume. Force-enable the pipe to fix this, the update_dpms
8759 * call below we restore the pipe to the right state, but leave
8760 * the required bits on. */
8761 intel_enable_pipe_a(dev);
8762 }
8763
24929352
DV		 8764 /* Adjust the state of the output pipe according to whether we
8765 * have active connectors/encoders. */
8766 intel_crtc_update_dpms(&crtc->base);
8767
8768 if (crtc->active != crtc->base.enabled) {
8769 struct intel_encoder *encoder;
8770
8771 /* This can happen either due to bugs in the get_hw_state
8772 * functions or because the pipe is force-enabled due to the
8773 * pipe A quirk. */
8774 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8775 crtc->base.base.id,
8776 crtc->base.enabled ? "enabled" : "disabled",
8777 crtc->active ? "enabled" : "disabled");
8778
8779 crtc->base.enabled = crtc->active;
8780
8781 /* Because we only establish the connector -> encoder ->
8782 * crtc links if something is active, this means the
8783 * crtc is now deactivated. Break the links. connector
8784 * -> encoder links are only establish when things are
8785 * actually up, hence no need to break them. */
8786 WARN_ON(crtc->active);
8787
8788 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8789 WARN_ON(encoder->connectors_active);
8790 encoder->base.crtc = NULL;
8791 }
8792 }
8793}
8794
8795static void intel_sanitize_encoder(struct intel_encoder *encoder)
8796{
8797 struct intel_connector *connector;
8798 struct drm_device *dev = encoder->base.dev;
8799
8800 /* We need to check both for a crtc link (meaning that the
8801 * encoder is active and trying to read from a pipe) and the
8802 * pipe itself being active. */
8803 bool has_active_crtc = encoder->base.crtc &&
8804 to_intel_crtc(encoder->base.crtc)->active;
8805
8806 if (encoder->connectors_active && !has_active_crtc) {
8807 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8808 encoder->base.base.id,
8809 drm_get_encoder_name(&encoder->base));
8810
8811 /* Connector is active, but has no active pipe. This is
8812 * fallout from our resume register restoring. Disable
8813 * the encoder manually again. */
8814 if (encoder->base.crtc) {
8815 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8816 encoder->base.base.id,
8817 drm_get_encoder_name(&encoder->base));
8818 encoder->disable(encoder);
8819 }
8820
8821 /* Inconsistent output/port/pipe state happens presumably due to
8822 * a bug in one of the get_hw_state functions. Or someplace else
8823 * in our code, like the register restore mess on resume. Clamp
8824 * things to off as a safer default. */
8825 list_for_each_entry(connector,
8826 &dev->mode_config.connector_list,
8827 base.head) {
8828 if (connector->encoder != encoder)
8829 continue;
8830
8831 intel_connector_break_all_links(connector);
8832 }
8833 }
8834 /* Enabled encoders without active connectors will be fixed in
8835 * the crtc fixup. */
8836}
8837
8838/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8839 * and i915 state tracking structures. */
8840void intel_modeset_setup_hw_state(struct drm_device *dev)
8841{
8842 struct drm_i915_private *dev_priv = dev->dev_private;
8843 enum pipe pipe;
8844 u32 tmp;
8845 struct intel_crtc *crtc;
8846 struct intel_encoder *encoder;
8847 struct intel_connector *connector;
8848
e28d54cb
PZ		 8849 if (IS_HASWELL(dev)) {
8850 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8851
8852 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8853 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8854 case TRANS_DDI_EDP_INPUT_A_ON:
8855 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8856 pipe = PIPE_A;
8857 break;
8858 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8859 pipe = PIPE_B;
8860 break;
8861 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8862 pipe = PIPE_C;
8863 break;
8864 }
8865
8866 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8867 crtc->cpu_transcoder = TRANSCODER_EDP;
8868
8869 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
8870 pipe_name(pipe));
8871 }
8872 }
8873
24929352
DV		 8874 for_each_pipe(pipe) {
8875 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8876
702e7a56 8877 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
24929352
DV		 8878 if (tmp & PIPECONF_ENABLE)
8879 crtc->active = true;
8880 else
8881 crtc->active = false;
8882
8883 crtc->base.enabled = crtc->active;
8884
8885 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
8886 crtc->base.base.id,
8887 crtc->active ? "enabled" : "disabled");
8888 }
8889
6441ab5f
PZ		 8890 if (IS_HASWELL(dev))
8891 intel_ddi_setup_hw_pll_state(dev);
8892
24929352
DV		 8893 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8894 base.head) {
8895 pipe = 0;
8896
8897 if (encoder->get_hw_state(encoder, &pipe)) {
8898 encoder->base.crtc =
8899 dev_priv->pipe_to_crtc_mapping[pipe];
8900 } else {
8901 encoder->base.crtc = NULL;
8902 }
8903
8904 encoder->connectors_active = false;
8905 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
8906 encoder->base.base.id,
8907 drm_get_encoder_name(&encoder->base),
8908 encoder->base.crtc ? "enabled" : "disabled",
8909 pipe);
8910 }
8911
8912 list_for_each_entry(connector, &dev->mode_config.connector_list,
8913 base.head) {
8914 if (connector->get_hw_state(connector)) {
8915 connector->base.dpms = DRM_MODE_DPMS_ON;
8916 connector->encoder->connectors_active = true;
8917 connector->base.encoder = &connector->encoder->base;
8918 } else {
8919 connector->base.dpms = DRM_MODE_DPMS_OFF;
8920 connector->base.encoder = NULL;
8921 }
8922 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
8923 connector->base.base.id,
8924 drm_get_connector_name(&connector->base),
8925 connector->base.encoder ? "enabled" : "disabled");
8926 }
8927
8928 /* HW state is read out, now we need to sanitize this mess. */
8929 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8930 base.head) {
8931 intel_sanitize_encoder(encoder);
8932 }
8933
8934 for_each_pipe(pipe) {
8935 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8936 intel_sanitize_crtc(crtc);
8937 }
9a935856
DV		 8938
8939 intel_modeset_update_staged_output_state(dev);
8af6cf88
DV		 8940
8941 intel_modeset_check_state(dev);
2e938892
DV		 8942
8943 drm_mode_config_reset(dev);
24929352
DV		 8944}
8945
2c7111db
CW		 8946void intel_modeset_gem_init(struct drm_device *dev)
8947{
1833b134 8948 intel_modeset_init_hw(dev);
02e792fb
DV		 8949
8950 intel_setup_overlay(dev);
24929352
DV		 8951
8952 intel_modeset_setup_hw_state(dev);
79e53945
JB		 8953}
8954
8955void intel_modeset_cleanup(struct drm_device *dev)
8956{
652c393a
JB		 8957 struct drm_i915_private *dev_priv = dev->dev_private;
8958 struct drm_crtc *crtc;
8959 struct intel_crtc *intel_crtc;
8960
f87ea761 8961 drm_kms_helper_poll_fini(dev);
652c393a
JB		 8962 mutex_lock(&dev->struct_mutex);
8963
723bfd70
JB		 8964 intel_unregister_dsm_handler();
8965
8966
652c393a
JB		 8967 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8968 /* Skip inactive CRTCs */
8969 if (!crtc->fb)
8970 continue;
8971
8972 intel_crtc = to_intel_crtc(crtc);
3dec0095 8973 intel_increase_pllclock(crtc);
652c393a
JB		 8974 }
8975
973d04f9 8976 intel_disable_fbc(dev);
e70236a8 8977
8090c6b9 8978 intel_disable_gt_powersave(dev);
0cdab21f 8979
930ebb46
DV		 8980 ironlake_teardown_rc6(dev);
8981
57f350b6
JB		 8982 if (IS_VALLEYVIEW(dev))
8983 vlv_init_dpio(dev);
8984
69341a5e
KH		 8985 mutex_unlock(&dev->struct_mutex);
8986
6c0d9350
DV		 8987 /* Disable the irq before mode object teardown, for the irq might
8988 * enqueue unpin/hotplug work. */
8989 drm_irq_uninstall(dev);
8990 cancel_work_sync(&dev_priv->hotplug_work);
c6a828d3 8991 cancel_work_sync(&dev_priv->rps.work);
6c0d9350 8992
1630fe75
CW		 8993 /* flush any delayed tasks or pending work */
8994 flush_scheduled_work();
8995
79e53945
JB		 8996 drm_mode_config_cleanup(dev);
8997}
8998
f1c79df3
ZW		 8999/*
9000 * Return which encoder is currently attached for connector.
9001 */
df0e9248 9002struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9003{
df0e9248
CW		 9004 return &intel_attached_encoder(connector)->base;
9005}
f1c79df3 9006
df0e9248
CW		 9007void intel_connector_attach_encoder(struct intel_connector *connector,
9008 struct intel_encoder *encoder)
9009{
9010 connector->encoder = encoder;
9011 drm_mode_connector_attach_encoder(&connector->base,
9012 &encoder->base);
79e53945 9013}
28d52043
DA		 9014
9015/*
9016 * set vga decode state - true == enable VGA decode
9017 */
9018int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9019{
9020 struct drm_i915_private *dev_priv = dev->dev_private;
9021 u16 gmch_ctrl;
9022
9023 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9024 if (state)
9025 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9026 else
9027 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9028 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9029 return 0;
9030}
c4a1d9e4
CW		 9031
9032#ifdef CONFIG_DEBUG_FS
9033#include <linux/seq_file.h>
9034
9035struct intel_display_error_state {
9036 struct intel_cursor_error_state {
9037 u32 control;
9038 u32 position;
9039 u32 base;
9040 u32 size;
52331309 9041 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 9042
9043 struct intel_pipe_error_state {
9044 u32 conf;
9045 u32 source;
9046
9047 u32 htotal;
9048 u32 hblank;
9049 u32 hsync;
9050 u32 vtotal;
9051 u32 vblank;
9052 u32 vsync;
52331309 9053 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 9054
9055 struct intel_plane_error_state {
9056 u32 control;
9057 u32 stride;
9058 u32 size;
9059 u32 pos;
9060 u32 addr;
9061 u32 surface;
9062 u32 tile_offset;
52331309 9063 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 9064};
9065
9066struct intel_display_error_state *
9067intel_display_capture_error_state(struct drm_device *dev)
9068{
0206e353 9069 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 9070 struct intel_display_error_state *error;
702e7a56 9071 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9072 int i;
9073
9074 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9075 if (error == NULL)
9076 return NULL;
9077
52331309 9078 for_each_pipe(i) {
702e7a56
PZ		 9079 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9080
c4a1d9e4
CW		 9081 error->cursor[i].control = I915_READ(CURCNTR(i));
9082 error->cursor[i].position = I915_READ(CURPOS(i));
9083 error->cursor[i].base = I915_READ(CURBASE(i));
9084
9085 error->plane[i].control = I915_READ(DSPCNTR(i));
9086 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9087 error->plane[i].size = I915_READ(DSPSIZE(i));
0206e353 9088 error->plane[i].pos = I915_READ(DSPPOS(i));
c4a1d9e4
CW		 9089 error->plane[i].addr = I915_READ(DSPADDR(i));
9090 if (INTEL_INFO(dev)->gen >= 4) {
9091 error->plane[i].surface = I915_READ(DSPSURF(i));
9092 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9093 }
9094
702e7a56 9095 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 9096 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 9097 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9098 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9099 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9100 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9101 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9102 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 9103 }
9104
9105 return error;
9106}
9107
9108void
9109intel_display_print_error_state(struct seq_file *m,
9110 struct drm_device *dev,
9111 struct intel_display_error_state *error)
9112{
52331309 9113 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 9114 int i;
9115
52331309
DL		 9116 seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
9117 for_each_pipe(i) {
c4a1d9e4
CW		 9118 seq_printf(m, "Pipe [%d]:\n", i);
9119 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9120 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9121 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9122 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9123 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9124 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9125 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9126 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9127
9128 seq_printf(m, "Plane [%d]:\n", i);
9129 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9130 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9131 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9132 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9133 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9134 if (INTEL_INFO(dev)->gen >= 4) {
9135 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9136 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9137 }
9138
9139 seq_printf(m, "Cursor [%d]:\n", i);
9140 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9141 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9142 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9143 }
9144}
9145#endif
Linux 6.x block layer and io_uring tree(s)