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drm/i915: Make adjusted_mode.clock non-pixel multiplied
[linux-block.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 47
f1f644dc
JB		 48static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
49 struct intel_crtc_config *pipe_config);
50static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
51 struct intel_crtc_config *pipe_config);
52
e7457a9a
DL		 53static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
54 int x, int y, struct drm_framebuffer *old_fb);
55
56
79e53945 57typedef struct {
0206e353 58 int min, max;
79e53945
JB		 59} intel_range_t;
60
61typedef struct {
0206e353
AJ		 62 int dot_limit;
63 int p2_slow, p2_fast;
79e53945
JB		 64} intel_p2_t;
65
d4906093
ML		 66typedef struct intel_limit intel_limit_t;
67struct intel_limit {
0206e353
AJ		 68 intel_range_t dot, vco, n, m, m1, m2, p, p1;
69 intel_p2_t p2;
d4906093 70};
79e53945 71
d2acd215
DV		 72int
73intel_pch_rawclk(struct drm_device *dev)
74{
75 struct drm_i915_private *dev_priv = dev->dev_private;
76
77 WARN_ON(!HAS_PCH_SPLIT(dev));
78
79 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
80}
81
021357ac
CW		 82static inline u32 /* units of 100MHz */
83intel_fdi_link_freq(struct drm_device *dev)
84{
8b99e68c
CW		 85 if (IS_GEN5(dev)) {
86 struct drm_i915_private *dev_priv = dev->dev_private;
87 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
88 } else
89 return 27;
021357ac
CW		 90}
91
5d536e28 92static const intel_limit_t intel_limits_i8xx_dac = {
0206e353
AJ		 93 .dot = { .min = 25000, .max = 350000 },
94 .vco = { .min = 930000, .max = 1400000 },
95 .n = { .min = 3, .max = 16 },
96 .m = { .min = 96, .max = 140 },
97 .m1 = { .min = 18, .max = 26 },
98 .m2 = { .min = 6, .max = 16 },
99 .p = { .min = 4, .max = 128 },
100 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 101 .p2 = { .dot_limit = 165000,
102 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 103};
104
5d536e28
DV		 105static const intel_limit_t intel_limits_i8xx_dvo = {
106 .dot = { .min = 25000, .max = 350000 },
107 .vco = { .min = 930000, .max = 1400000 },
108 .n = { .min = 3, .max = 16 },
109 .m = { .min = 96, .max = 140 },
110 .m1 = { .min = 18, .max = 26 },
111 .m2 = { .min = 6, .max = 16 },
112 .p = { .min = 4, .max = 128 },
113 .p1 = { .min = 2, .max = 33 },
114 .p2 = { .dot_limit = 165000,
115 .p2_slow = 4, .p2_fast = 4 },
116};
117
e4b36699 118static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 119 .dot = { .min = 25000, .max = 350000 },
120 .vco = { .min = 930000, .max = 1400000 },
121 .n = { .min = 3, .max = 16 },
122 .m = { .min = 96, .max = 140 },
123 .m1 = { .min = 18, .max = 26 },
124 .m2 = { .min = 6, .max = 16 },
125 .p = { .min = 4, .max = 128 },
126 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 127 .p2 = { .dot_limit = 165000,
128 .p2_slow = 14, .p2_fast = 7 },
e4b36699 129};
273e27ca 130
e4b36699 131static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 132 .dot = { .min = 20000, .max = 400000 },
133 .vco = { .min = 1400000, .max = 2800000 },
134 .n = { .min = 1, .max = 6 },
135 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 136 .m1 = { .min = 8, .max = 18 },
137 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 138 .p = { .min = 5, .max = 80 },
139 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 140 .p2 = { .dot_limit = 200000,
141 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 142};
143
144static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 145 .dot = { .min = 20000, .max = 400000 },
146 .vco = { .min = 1400000, .max = 2800000 },
147 .n = { .min = 1, .max = 6 },
148 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 149 .m1 = { .min = 8, .max = 18 },
150 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 151 .p = { .min = 7, .max = 98 },
152 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 153 .p2 = { .dot_limit = 112000,
154 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 155};
156
273e27ca 157
e4b36699 158static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 159 .dot = { .min = 25000, .max = 270000 },
160 .vco = { .min = 1750000, .max = 3500000},
161 .n = { .min = 1, .max = 4 },
162 .m = { .min = 104, .max = 138 },
163 .m1 = { .min = 17, .max = 23 },
164 .m2 = { .min = 5, .max = 11 },
165 .p = { .min = 10, .max = 30 },
166 .p1 = { .min = 1, .max = 3},
167 .p2 = { .dot_limit = 270000,
168 .p2_slow = 10,
169 .p2_fast = 10
044c7c41 170 },
e4b36699
KP		 171};
172
173static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 174 .dot = { .min = 22000, .max = 400000 },
175 .vco = { .min = 1750000, .max = 3500000},
176 .n = { .min = 1, .max = 4 },
177 .m = { .min = 104, .max = 138 },
178 .m1 = { .min = 16, .max = 23 },
179 .m2 = { .min = 5, .max = 11 },
180 .p = { .min = 5, .max = 80 },
181 .p1 = { .min = 1, .max = 8},
182 .p2 = { .dot_limit = 165000,
183 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 184};
185
186static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 187 .dot = { .min = 20000, .max = 115000 },
188 .vco = { .min = 1750000, .max = 3500000 },
189 .n = { .min = 1, .max = 3 },
190 .m = { .min = 104, .max = 138 },
191 .m1 = { .min = 17, .max = 23 },
192 .m2 = { .min = 5, .max = 11 },
193 .p = { .min = 28, .max = 112 },
194 .p1 = { .min = 2, .max = 8 },
195 .p2 = { .dot_limit = 0,
196 .p2_slow = 14, .p2_fast = 14
044c7c41 197 },
e4b36699
KP		 198};
199
200static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 201 .dot = { .min = 80000, .max = 224000 },
202 .vco = { .min = 1750000, .max = 3500000 },
203 .n = { .min = 1, .max = 3 },
204 .m = { .min = 104, .max = 138 },
205 .m1 = { .min = 17, .max = 23 },
206 .m2 = { .min = 5, .max = 11 },
207 .p = { .min = 14, .max = 42 },
208 .p1 = { .min = 2, .max = 6 },
209 .p2 = { .dot_limit = 0,
210 .p2_slow = 7, .p2_fast = 7
044c7c41 211 },
e4b36699
KP		 212};
213
f2b115e6 214static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 215 .dot = { .min = 20000, .max = 400000},
216 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 217 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 218 .n = { .min = 3, .max = 6 },
219 .m = { .min = 2, .max = 256 },
273e27ca 220 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 221 .m1 = { .min = 0, .max = 0 },
222 .m2 = { .min = 0, .max = 254 },
223 .p = { .min = 5, .max = 80 },
224 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 225 .p2 = { .dot_limit = 200000,
226 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 227};
228
f2b115e6 229static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 230 .dot = { .min = 20000, .max = 400000 },
231 .vco = { .min = 1700000, .max = 3500000 },
232 .n = { .min = 3, .max = 6 },
233 .m = { .min = 2, .max = 256 },
234 .m1 = { .min = 0, .max = 0 },
235 .m2 = { .min = 0, .max = 254 },
236 .p = { .min = 7, .max = 112 },
237 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 238 .p2 = { .dot_limit = 112000,
239 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 240};
241
273e27ca
EA		 242/* Ironlake / Sandybridge
243 *
244 * We calculate clock using (register_value + 2) for N/M1/M2, so here
245 * the range value for them is (actual_value - 2).
246 */
b91ad0ec 247static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 248 .dot = { .min = 25000, .max = 350000 },
249 .vco = { .min = 1760000, .max = 3510000 },
250 .n = { .min = 1, .max = 5 },
251 .m = { .min = 79, .max = 127 },
252 .m1 = { .min = 12, .max = 22 },
253 .m2 = { .min = 5, .max = 9 },
254 .p = { .min = 5, .max = 80 },
255 .p1 = { .min = 1, .max = 8 },
256 .p2 = { .dot_limit = 225000,
257 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 258};
259
b91ad0ec 260static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 261 .dot = { .min = 25000, .max = 350000 },
262 .vco = { .min = 1760000, .max = 3510000 },
263 .n = { .min = 1, .max = 3 },
264 .m = { .min = 79, .max = 118 },
265 .m1 = { .min = 12, .max = 22 },
266 .m2 = { .min = 5, .max = 9 },
267 .p = { .min = 28, .max = 112 },
268 .p1 = { .min = 2, .max = 8 },
269 .p2 = { .dot_limit = 225000,
270 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 271};
272
273static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 274 .dot = { .min = 25000, .max = 350000 },
275 .vco = { .min = 1760000, .max = 3510000 },
276 .n = { .min = 1, .max = 3 },
277 .m = { .min = 79, .max = 127 },
278 .m1 = { .min = 12, .max = 22 },
279 .m2 = { .min = 5, .max = 9 },
280 .p = { .min = 14, .max = 56 },
281 .p1 = { .min = 2, .max = 8 },
282 .p2 = { .dot_limit = 225000,
283 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 284};
285
273e27ca 286/* LVDS 100mhz refclk limits. */
b91ad0ec 287static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 288 .dot = { .min = 25000, .max = 350000 },
289 .vco = { .min = 1760000, .max = 3510000 },
290 .n = { .min = 1, .max = 2 },
291 .m = { .min = 79, .max = 126 },
292 .m1 = { .min = 12, .max = 22 },
293 .m2 = { .min = 5, .max = 9 },
294 .p = { .min = 28, .max = 112 },
0206e353 295 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 296 .p2 = { .dot_limit = 225000,
297 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 298};
299
300static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 301 .dot = { .min = 25000, .max = 350000 },
302 .vco = { .min = 1760000, .max = 3510000 },
303 .n = { .min = 1, .max = 3 },
304 .m = { .min = 79, .max = 126 },
305 .m1 = { .min = 12, .max = 22 },
306 .m2 = { .min = 5, .max = 9 },
307 .p = { .min = 14, .max = 42 },
0206e353 308 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 309 .p2 = { .dot_limit = 225000,
310 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 311};
312
a0c4da24
JB		 313static const intel_limit_t intel_limits_vlv_dac = {
314 .dot = { .min = 25000, .max = 270000 },
315 .vco = { .min = 4000000, .max = 6000000 },
316 .n = { .min = 1, .max = 7 },
317 .m = { .min = 22, .max = 450 }, /* guess */
318 .m1 = { .min = 2, .max = 3 },
319 .m2 = { .min = 11, .max = 156 },
320 .p = { .min = 10, .max = 30 },
75e53986 321 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 322 .p2 = { .dot_limit = 270000,
323 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 324};
325
326static const intel_limit_t intel_limits_vlv_hdmi = {
75e53986
DV		 327 .dot = { .min = 25000, .max = 270000 },
328 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24
JB		 329 .n = { .min = 1, .max = 7 },
330 .m = { .min = 60, .max = 300 }, /* guess */
331 .m1 = { .min = 2, .max = 3 },
332 .m2 = { .min = 11, .max = 156 },
333 .p = { .min = 10, .max = 30 },
334 .p1 = { .min = 2, .max = 3 },
335 .p2 = { .dot_limit = 270000,
336 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 337};
338
1b894b59
CW		 339static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
340 int refclk)
2c07245f 341{
b91ad0ec 342 struct drm_device *dev = crtc->dev;
2c07245f 343 const intel_limit_t *limit;
b91ad0ec
ZW		 344
345 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 346 if (intel_is_dual_link_lvds(dev)) {
1b894b59 347 if (refclk == 100000)
b91ad0ec
ZW		 348 limit = &intel_limits_ironlake_dual_lvds_100m;
349 else
350 limit = &intel_limits_ironlake_dual_lvds;
351 } else {
1b894b59 352 if (refclk == 100000)
b91ad0ec
ZW		 353 limit = &intel_limits_ironlake_single_lvds_100m;
354 else
355 limit = &intel_limits_ironlake_single_lvds;
356 }
c6bb3538 357 } else
b91ad0ec 358 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 359
360 return limit;
361}
362
044c7c41
ML		 363static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
364{
365 struct drm_device *dev = crtc->dev;
044c7c41
ML		 366 const intel_limit_t *limit;
367
368 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 369 if (intel_is_dual_link_lvds(dev))
e4b36699 370 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 371 else
e4b36699 372 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 373 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
374 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 375 limit = &intel_limits_g4x_hdmi;
044c7c41 376 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 377 limit = &intel_limits_g4x_sdvo;
044c7c41 378 } else /* The option is for other outputs */
e4b36699 379 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 380
381 return limit;
382}
383
1b894b59 384static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 385{
386 struct drm_device *dev = crtc->dev;
387 const intel_limit_t *limit;
388
bad720ff 389 if (HAS_PCH_SPLIT(dev))
1b894b59 390 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 391 else if (IS_G4X(dev)) {
044c7c41 392 limit = intel_g4x_limit(crtc);
f2b115e6 393 } else if (IS_PINEVIEW(dev)) {
2177832f 394 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 395 limit = &intel_limits_pineview_lvds;
2177832f 396 else
f2b115e6 397 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 398 } else if (IS_VALLEYVIEW(dev)) {
399 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
400 limit = &intel_limits_vlv_dac;
a0c4da24 401 else
65ce4bf5 402 limit = &intel_limits_vlv_hdmi;
a6c45cf0
CW		 403 } else if (!IS_GEN2(dev)) {
404 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
405 limit = &intel_limits_i9xx_lvds;
406 else
407 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 408 } else {
409 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 410 limit = &intel_limits_i8xx_lvds;
5d536e28 411 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
e4b36699 412 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 413 else
414 limit = &intel_limits_i8xx_dac;
79e53945
JB		 415 }
416 return limit;
417}
418
f2b115e6
AJ		 419/* m1 is reserved as 0 in Pineview, n is a ring counter */
420static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 421{
2177832f
SL		 422 clock->m = clock->m2 + 2;
423 clock->p = clock->p1 * clock->p2;
424 clock->vco = refclk * clock->m / clock->n;
425 clock->dot = clock->vco / clock->p;
426}
427
7429e9d4
DV		 428static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
429{
430 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
431}
432
ac58c3f0 433static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 434{
7429e9d4 435 clock->m = i9xx_dpll_compute_m(clock);
79e53945
JB		 436 clock->p = clock->p1 * clock->p2;
437 clock->vco = refclk * clock->m / (clock->n + 2);
438 clock->dot = clock->vco / clock->p;
439}
440
79e53945
JB		 441/**
442 * Returns whether any output on the specified pipe is of the specified type
443 */
4ef69c7a 444bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 445{
4ef69c7a 446 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 447 struct intel_encoder *encoder;
448
6c2b7c12
DV		 449 for_each_encoder_on_crtc(dev, crtc, encoder)
450 if (encoder->type == type)
4ef69c7a
CW		 451 return true;
452
453 return false;
79e53945
JB		 454}
455
7c04d1d9 456#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 457/**
458 * Returns whether the given set of divisors are valid for a given refclk with
459 * the given connectors.
460 */
461
1b894b59
CW		 462static bool intel_PLL_is_valid(struct drm_device *dev,
463 const intel_limit_t *limit,
464 const intel_clock_t *clock)
79e53945 465{
79e53945 466 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 467 INTELPllInvalid("p1 out of range\n");
79e53945 468 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 469 INTELPllInvalid("p out of range\n");
79e53945 470 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 471 INTELPllInvalid("m2 out of range\n");
79e53945 472 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 473 INTELPllInvalid("m1 out of range\n");
f2b115e6 474 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 475 INTELPllInvalid("m1 <= m2\n");
79e53945 476 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 477 INTELPllInvalid("m out of range\n");
79e53945 478 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 479 INTELPllInvalid("n out of range\n");
79e53945 480 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 481 INTELPllInvalid("vco out of range\n");
79e53945
JB		 482 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
483 * connector, etc., rather than just a single range.
484 */
485 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 486 INTELPllInvalid("dot out of range\n");
79e53945
JB		 487
488 return true;
489}
490
d4906093 491static bool
ee9300bb 492i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 493 int target, int refclk, intel_clock_t *match_clock,
494 intel_clock_t *best_clock)
79e53945
JB		 495{
496 struct drm_device *dev = crtc->dev;
79e53945 497 intel_clock_t clock;
79e53945
JB		 498 int err = target;
499
a210b028 500 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 501 /*
a210b028
DV		 502 * For LVDS just rely on its current settings for dual-channel.
503 * We haven't figured out how to reliably set up different
504 * single/dual channel state, if we even can.
79e53945 505 */
1974cad0 506 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 507 clock.p2 = limit->p2.p2_fast;
508 else
509 clock.p2 = limit->p2.p2_slow;
510 } else {
511 if (target < limit->p2.dot_limit)
512 clock.p2 = limit->p2.p2_slow;
513 else
514 clock.p2 = limit->p2.p2_fast;
515 }
516
0206e353 517 memset(best_clock, 0, sizeof(*best_clock));
79e53945 518
42158660
ZY		 519 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
520 clock.m1++) {
521 for (clock.m2 = limit->m2.min;
522 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 523 if (clock.m2 >= clock.m1)
42158660
ZY		 524 break;
525 for (clock.n = limit->n.min;
526 clock.n <= limit->n.max; clock.n++) {
527 for (clock.p1 = limit->p1.min;
528 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 529 int this_err;
530
ac58c3f0
DV		 531 i9xx_clock(refclk, &clock);
532 if (!intel_PLL_is_valid(dev, limit,
533 &clock))
534 continue;
535 if (match_clock &&
536 clock.p != match_clock->p)
537 continue;
538
539 this_err = abs(clock.dot - target);
540 if (this_err < err) {
541 *best_clock = clock;
542 err = this_err;
543 }
544 }
545 }
546 }
547 }
548
549 return (err != target);
550}
551
552static bool
ee9300bb
DV		 553pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
554 int target, int refclk, intel_clock_t *match_clock,
555 intel_clock_t *best_clock)
79e53945
JB		 556{
557 struct drm_device *dev = crtc->dev;
79e53945 558 intel_clock_t clock;
79e53945
JB		 559 int err = target;
560
a210b028 561 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 562 /*
a210b028
DV		 563 * For LVDS just rely on its current settings for dual-channel.
564 * We haven't figured out how to reliably set up different
565 * single/dual channel state, if we even can.
79e53945 566 */
1974cad0 567 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 568 clock.p2 = limit->p2.p2_fast;
569 else
570 clock.p2 = limit->p2.p2_slow;
571 } else {
572 if (target < limit->p2.dot_limit)
573 clock.p2 = limit->p2.p2_slow;
574 else
575 clock.p2 = limit->p2.p2_fast;
576 }
577
0206e353 578 memset(best_clock, 0, sizeof(*best_clock));
79e53945 579
42158660
ZY		 580 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
581 clock.m1++) {
582 for (clock.m2 = limit->m2.min;
583 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 584 for (clock.n = limit->n.min;
585 clock.n <= limit->n.max; clock.n++) {
586 for (clock.p1 = limit->p1.min;
587 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 588 int this_err;
589
ac58c3f0 590 pineview_clock(refclk, &clock);
1b894b59
CW		 591 if (!intel_PLL_is_valid(dev, limit,
592 &clock))
79e53945 593 continue;
cec2f356
SP		 594 if (match_clock &&
595 clock.p != match_clock->p)
596 continue;
79e53945
JB		 597
598 this_err = abs(clock.dot - target);
599 if (this_err < err) {
600 *best_clock = clock;
601 err = this_err;
602 }
603 }
604 }
605 }
606 }
607
608 return (err != target);
609}
610
d4906093 611static bool
ee9300bb
DV		 612g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
613 int target, int refclk, intel_clock_t *match_clock,
614 intel_clock_t *best_clock)
d4906093
ML		 615{
616 struct drm_device *dev = crtc->dev;
d4906093
ML		 617 intel_clock_t clock;
618 int max_n;
619 bool found;
6ba770dc
AJ		 620 /* approximately equals target * 0.00585 */
621 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 622 found = false;
623
624 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 625 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 626 clock.p2 = limit->p2.p2_fast;
627 else
628 clock.p2 = limit->p2.p2_slow;
629 } else {
630 if (target < limit->p2.dot_limit)
631 clock.p2 = limit->p2.p2_slow;
632 else
633 clock.p2 = limit->p2.p2_fast;
634 }
635
636 memset(best_clock, 0, sizeof(*best_clock));
637 max_n = limit->n.max;
f77f13e2 638 /* based on hardware requirement, prefer smaller n to precision */
d4906093 639 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 640 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 641 for (clock.m1 = limit->m1.max;
642 clock.m1 >= limit->m1.min; clock.m1--) {
643 for (clock.m2 = limit->m2.max;
644 clock.m2 >= limit->m2.min; clock.m2--) {
645 for (clock.p1 = limit->p1.max;
646 clock.p1 >= limit->p1.min; clock.p1--) {
647 int this_err;
648
ac58c3f0 649 i9xx_clock(refclk, &clock);
1b894b59
CW		 650 if (!intel_PLL_is_valid(dev, limit,
651 &clock))
d4906093 652 continue;
1b894b59
CW		 653
654 this_err = abs(clock.dot - target);
d4906093
ML		 655 if (this_err < err_most) {
656 *best_clock = clock;
657 err_most = this_err;
658 max_n = clock.n;
659 found = true;
660 }
661 }
662 }
663 }
664 }
2c07245f
ZW		 665 return found;
666}
667
a0c4da24 668static bool
ee9300bb
DV		 669vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
670 int target, int refclk, intel_clock_t *match_clock,
671 intel_clock_t *best_clock)
a0c4da24
JB		 672{
673 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
674 u32 m, n, fastclk;
f3f08572 675 u32 updrate, minupdate, p;
a0c4da24
JB		 676 unsigned long bestppm, ppm, absppm;
677 int dotclk, flag;
678
af447bd3 679 flag = 0;
a0c4da24
JB		 680 dotclk = target * 1000;
681 bestppm = 1000000;
682 ppm = absppm = 0;
683 fastclk = dotclk / (2*100);
684 updrate = 0;
685 minupdate = 19200;
a0c4da24
JB		 686 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
687 bestm1 = bestm2 = bestp1 = bestp2 = 0;
688
689 /* based on hardware requirement, prefer smaller n to precision */
690 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
691 updrate = refclk / n;
692 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
693 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
694 if (p2 > 10)
695 p2 = p2 - 1;
696 p = p1 * p2;
697 /* based on hardware requirement, prefer bigger m1,m2 values */
698 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
699 m2 = (((2*(fastclk * p * n / m1 )) +
700 refclk) / (2*refclk));
701 m = m1 * m2;
702 vco = updrate * m;
703 if (vco >= limit->vco.min && vco < limit->vco.max) {
704 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
705 absppm = (ppm > 0) ? ppm : (-ppm);
706 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
707 bestppm = 0;
708 flag = 1;
709 }
710 if (absppm < bestppm - 10) {
711 bestppm = absppm;
712 flag = 1;
713 }
714 if (flag) {
715 bestn = n;
716 bestm1 = m1;
717 bestm2 = m2;
718 bestp1 = p1;
719 bestp2 = p2;
720 flag = 0;
721 }
722 }
723 }
724 }
725 }
726 }
727 best_clock->n = bestn;
728 best_clock->m1 = bestm1;
729 best_clock->m2 = bestm2;
730 best_clock->p1 = bestp1;
731 best_clock->p2 = bestp2;
732
733 return true;
734}
a4fc5ed6 735
a5c961d1
PZ		 736enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
737 enum pipe pipe)
738{
739 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
740 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
741
3b117c8f 742 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 743}
744
a928d536
PZ		 745static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
746{
747 struct drm_i915_private *dev_priv = dev->dev_private;
748 u32 frame, frame_reg = PIPEFRAME(pipe);
749
750 frame = I915_READ(frame_reg);
751
752 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
753 DRM_DEBUG_KMS("vblank wait timed out\n");
754}
755
9d0498a2
JB		 756/**
757 * intel_wait_for_vblank - wait for vblank on a given pipe
758 * @dev: drm device
759 * @pipe: pipe to wait for
760 *
761 * Wait for vblank to occur on a given pipe. Needed for various bits of
762 * mode setting code.
763 */
764void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 765{
9d0498a2 766 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 767 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 768
a928d536
PZ		 769 if (INTEL_INFO(dev)->gen >= 5) {
770 ironlake_wait_for_vblank(dev, pipe);
771 return;
772 }
773
300387c0
CW		 774 /* Clear existing vblank status. Note this will clear any other
775 * sticky status fields as well.
776 *
777 * This races with i915_driver_irq_handler() with the result
778 * that either function could miss a vblank event. Here it is not
779 * fatal, as we will either wait upon the next vblank interrupt or
780 * timeout. Generally speaking intel_wait_for_vblank() is only
781 * called during modeset at which time the GPU should be idle and
782 * should *not* be performing page flips and thus not waiting on
783 * vblanks...
784 * Currently, the result of us stealing a vblank from the irq
785 * handler is that a single frame will be skipped during swapbuffers.
786 */
787 I915_WRITE(pipestat_reg,
788 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
789
9d0498a2 790 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 791 if (wait_for(I915_READ(pipestat_reg) &
792 PIPE_VBLANK_INTERRUPT_STATUS,
793 50))
9d0498a2
JB		 794 DRM_DEBUG_KMS("vblank wait timed out\n");
795}
796
ab7ad7f6
KP		 797/*
798 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 799 * @dev: drm device
800 * @pipe: pipe to wait for
801 *
802 * After disabling a pipe, we can't wait for vblank in the usual way,
803 * spinning on the vblank interrupt status bit, since we won't actually
804 * see an interrupt when the pipe is disabled.
805 *
ab7ad7f6
KP		 806 * On Gen4 and above:
807 * wait for the pipe register state bit to turn off
808 *
809 * Otherwise:
810 * wait for the display line value to settle (it usually
811 * ends up stopping at the start of the next frame).
58e10eb9 812 *
9d0498a2 813 */
58e10eb9 814void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 815{
816 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 817 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
818 pipe);
ab7ad7f6
KP		 819
820 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 821 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 822
823 /* Wait for the Pipe State to go off */
58e10eb9
CW		 824 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
825 100))
284637d9 826 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 827 } else {
837ba00f 828 u32 last_line, line_mask;
58e10eb9 829 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 830 unsigned long timeout = jiffies + msecs_to_jiffies(100);
831
837ba00f
PZ		 832 if (IS_GEN2(dev))
833 line_mask = DSL_LINEMASK_GEN2;
834 else
835 line_mask = DSL_LINEMASK_GEN3;
836
ab7ad7f6
KP		 837 /* Wait for the display line to settle */
838 do {
837ba00f 839 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 840 mdelay(5);
837ba00f 841 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 842 time_after(timeout, jiffies));
843 if (time_after(jiffies, timeout))
284637d9 844 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 845 }
79e53945
JB		 846}
847
b0ea7d37
DL		 848/*
849 * ibx_digital_port_connected - is the specified port connected?
850 * @dev_priv: i915 private structure
851 * @port: the port to test
852 *
853 * Returns true if @port is connected, false otherwise.
854 */
855bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
856 struct intel_digital_port *port)
857{
858 u32 bit;
859
c36346e3
DL		 860 if (HAS_PCH_IBX(dev_priv->dev)) {
861 switch(port->port) {
862 case PORT_B:
863 bit = SDE_PORTB_HOTPLUG;
864 break;
865 case PORT_C:
866 bit = SDE_PORTC_HOTPLUG;
867 break;
868 case PORT_D:
869 bit = SDE_PORTD_HOTPLUG;
870 break;
871 default:
872 return true;
873 }
874 } else {
875 switch(port->port) {
876 case PORT_B:
877 bit = SDE_PORTB_HOTPLUG_CPT;
878 break;
879 case PORT_C:
880 bit = SDE_PORTC_HOTPLUG_CPT;
881 break;
882 case PORT_D:
883 bit = SDE_PORTD_HOTPLUG_CPT;
884 break;
885 default:
886 return true;
887 }
b0ea7d37
DL		 888 }
889
890 return I915_READ(SDEISR) & bit;
891}
892
b24e7179
JB		 893static const char *state_string(bool enabled)
894{
895 return enabled ? "on" : "off";
896}
897
898/* Only for pre-ILK configs */
55607e8a
DV		 899void assert_pll(struct drm_i915_private *dev_priv,
900 enum pipe pipe, bool state)
b24e7179
JB		 901{
902 int reg;
903 u32 val;
904 bool cur_state;
905
906 reg = DPLL(pipe);
907 val = I915_READ(reg);
908 cur_state = !!(val & DPLL_VCO_ENABLE);
909 WARN(cur_state != state,
910 "PLL state assertion failure (expected %s, current %s)\n",
911 state_string(state), state_string(cur_state));
912}
b24e7179 913
23538ef1
JN		 914/* XXX: the dsi pll is shared between MIPI DSI ports */
915static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
916{
917 u32 val;
918 bool cur_state;
919
920 mutex_lock(&dev_priv->dpio_lock);
921 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
922 mutex_unlock(&dev_priv->dpio_lock);
923
924 cur_state = val & DSI_PLL_VCO_EN;
925 WARN(cur_state != state,
926 "DSI PLL state assertion failure (expected %s, current %s)\n",
927 state_string(state), state_string(cur_state));
928}
929#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
930#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
931
55607e8a 932struct intel_shared_dpll *
e2b78267
DV		 933intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
934{
935 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
936
a43f6e0f 937 if (crtc->config.shared_dpll < 0)
e2b78267
DV		 938 return NULL;
939
a43f6e0f 940 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
e2b78267
DV		 941}
942
040484af 943/* For ILK+ */
55607e8a
DV		 944void assert_shared_dpll(struct drm_i915_private *dev_priv,
945 struct intel_shared_dpll *pll,
946 bool state)
040484af 947{
040484af 948 bool cur_state;
5358901f 949 struct intel_dpll_hw_state hw_state;
040484af 950
9d82aa17
ED		 951 if (HAS_PCH_LPT(dev_priv->dev)) {
952 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
953 return;
954 }
955
92b27b08 956 if (WARN (!pll,
46edb027 957 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 958 return;
ee7b9f93 959
5358901f 960 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
92b27b08 961 WARN(cur_state != state,
5358901f
DV		 962 "%s assertion failure (expected %s, current %s)\n",
963 pll->name, state_string(state), state_string(cur_state));
040484af 964}
040484af
JB		 965
966static void assert_fdi_tx(struct drm_i915_private *dev_priv,
967 enum pipe pipe, bool state)
968{
969 int reg;
970 u32 val;
971 bool cur_state;
ad80a810
PZ		 972 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
973 pipe);
040484af 974
affa9354
PZ		 975 if (HAS_DDI(dev_priv->dev)) {
976 /* DDI does not have a specific FDI_TX register */
ad80a810 977 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 978 val = I915_READ(reg);
ad80a810 979 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 980 } else {
981 reg = FDI_TX_CTL(pipe);
982 val = I915_READ(reg);
983 cur_state = !!(val & FDI_TX_ENABLE);
984 }
040484af
JB		 985 WARN(cur_state != state,
986 "FDI TX state assertion failure (expected %s, current %s)\n",
987 state_string(state), state_string(cur_state));
988}
989#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
990#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
991
992static void assert_fdi_rx(struct drm_i915_private *dev_priv,
993 enum pipe pipe, bool state)
994{
995 int reg;
996 u32 val;
997 bool cur_state;
998
d63fa0dc
PZ		 999 reg = FDI_RX_CTL(pipe);
1000 val = I915_READ(reg);
1001 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1002 WARN(cur_state != state,
1003 "FDI RX state assertion failure (expected %s, current %s)\n",
1004 state_string(state), state_string(cur_state));
1005}
1006#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1007#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1008
1009static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1010 enum pipe pipe)
1011{
1012 int reg;
1013 u32 val;
1014
1015 /* ILK FDI PLL is always enabled */
1016 if (dev_priv->info->gen == 5)
1017 return;
1018
bf507ef7 1019 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1020 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1021 return;
1022
040484af
JB		 1023 reg = FDI_TX_CTL(pipe);
1024 val = I915_READ(reg);
1025 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1026}
1027
55607e8a
DV		 1028void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1029 enum pipe pipe, bool state)
040484af
JB		 1030{
1031 int reg;
1032 u32 val;
55607e8a 1033 bool cur_state;
040484af
JB		 1034
1035 reg = FDI_RX_CTL(pipe);
1036 val = I915_READ(reg);
55607e8a
DV		 1037 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1038 WARN(cur_state != state,
1039 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1040 state_string(state), state_string(cur_state));
040484af
JB		 1041}
1042
ea0760cf
JB		 1043static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1044 enum pipe pipe)
1045{
1046 int pp_reg, lvds_reg;
1047 u32 val;
1048 enum pipe panel_pipe = PIPE_A;
0de3b485 1049 bool locked = true;
ea0760cf
JB		 1050
1051 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1052 pp_reg = PCH_PP_CONTROL;
1053 lvds_reg = PCH_LVDS;
1054 } else {
1055 pp_reg = PP_CONTROL;
1056 lvds_reg = LVDS;
1057 }
1058
1059 val = I915_READ(pp_reg);
1060 if (!(val & PANEL_POWER_ON) ||
1061 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1062 locked = false;
1063
1064 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1065 panel_pipe = PIPE_B;
1066
1067 WARN(panel_pipe == pipe && locked,
1068 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1069 pipe_name(pipe));
ea0760cf
JB		 1070}
1071
b840d907
JB		 1072void assert_pipe(struct drm_i915_private *dev_priv,
1073 enum pipe pipe, bool state)
b24e7179
JB		 1074{
1075 int reg;
1076 u32 val;
63d7bbe9 1077 bool cur_state;
702e7a56
PZ		 1078 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1079 pipe);
b24e7179 1080
8e636784
DV		 1081 /* if we need the pipe A quirk it must be always on */
1082 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1083 state = true;
1084
b97186f0
PZ		 1085 if (!intel_display_power_enabled(dev_priv->dev,
1086 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1087 cur_state = false;
1088 } else {
1089 reg = PIPECONF(cpu_transcoder);
1090 val = I915_READ(reg);
1091 cur_state = !!(val & PIPECONF_ENABLE);
1092 }
1093
63d7bbe9
JB		 1094 WARN(cur_state != state,
1095 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1096 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1097}
1098
931872fc
CW		 1099static void assert_plane(struct drm_i915_private *dev_priv,
1100 enum plane plane, bool state)
b24e7179
JB		 1101{
1102 int reg;
1103 u32 val;
931872fc 1104 bool cur_state;
b24e7179
JB		 1105
1106 reg = DSPCNTR(plane);
1107 val = I915_READ(reg);
931872fc
CW		 1108 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1109 WARN(cur_state != state,
1110 "plane %c assertion failure (expected %s, current %s)\n",
1111 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1112}
1113
931872fc
CW		 1114#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1115#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1116
b24e7179
JB		 1117static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1118 enum pipe pipe)
1119{
653e1026 1120 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1121 int reg, i;
1122 u32 val;
1123 int cur_pipe;
1124
653e1026
VS		 1125 /* Primary planes are fixed to pipes on gen4+ */
1126 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1127 reg = DSPCNTR(pipe);
1128 val = I915_READ(reg);
1129 WARN((val & DISPLAY_PLANE_ENABLE),
1130 "plane %c assertion failure, should be disabled but not\n",
1131 plane_name(pipe));
19ec1358 1132 return;
28c05794 1133 }
19ec1358 1134
b24e7179 1135 /* Need to check both planes against the pipe */
08e2a7de 1136 for_each_pipe(i) {
b24e7179
JB		 1137 reg = DSPCNTR(i);
1138 val = I915_READ(reg);
1139 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1140 DISPPLANE_SEL_PIPE_SHIFT;
1141 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1142 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1143 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1144 }
1145}
1146
19332d7a
JB		 1147static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1148 enum pipe pipe)
1149{
20674eef 1150 struct drm_device *dev = dev_priv->dev;
19332d7a
JB		 1151 int reg, i;
1152 u32 val;
1153
20674eef
VS		 1154 if (IS_VALLEYVIEW(dev)) {
1155 for (i = 0; i < dev_priv->num_plane; i++) {
1156 reg = SPCNTR(pipe, i);
1157 val = I915_READ(reg);
1158 WARN((val & SP_ENABLE),
1159 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1160 sprite_name(pipe, i), pipe_name(pipe));
1161 }
1162 } else if (INTEL_INFO(dev)->gen >= 7) {
1163 reg = SPRCTL(pipe);
19332d7a 1164 val = I915_READ(reg);
20674eef 1165 WARN((val & SPRITE_ENABLE),
06da8da2 1166 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1167 plane_name(pipe), pipe_name(pipe));
1168 } else if (INTEL_INFO(dev)->gen >= 5) {
1169 reg = DVSCNTR(pipe);
19332d7a 1170 val = I915_READ(reg);
20674eef 1171 WARN((val & DVS_ENABLE),
06da8da2 1172 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1173 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1174 }
1175}
1176
92f2584a
JB		 1177static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1178{
1179 u32 val;
1180 bool enabled;
1181
9d82aa17
ED		 1182 if (HAS_PCH_LPT(dev_priv->dev)) {
1183 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1184 return;
1185 }
1186
92f2584a
JB		 1187 val = I915_READ(PCH_DREF_CONTROL);
1188 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1189 DREF_SUPERSPREAD_SOURCE_MASK));
1190 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1191}
1192
ab9412ba
DV		 1193static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1194 enum pipe pipe)
92f2584a
JB		 1195{
1196 int reg;
1197 u32 val;
1198 bool enabled;
1199
ab9412ba 1200 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1201 val = I915_READ(reg);
1202 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1203 WARN(enabled,
1204 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1205 pipe_name(pipe));
92f2584a
JB		 1206}
1207
4e634389
KP		 1208static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1209 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1210{
1211 if ((val & DP_PORT_EN) == 0)
1212 return false;
1213
1214 if (HAS_PCH_CPT(dev_priv->dev)) {
1215 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1216 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1217 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1218 return false;
1219 } else {
1220 if ((val & DP_PIPE_MASK) != (pipe << 30))
1221 return false;
1222 }
1223 return true;
1224}
1225
1519b995
KP		 1226static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1227 enum pipe pipe, u32 val)
1228{
dc0fa718 1229 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1230 return false;
1231
1232 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1233 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1234 return false;
1235 } else {
dc0fa718 1236 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1237 return false;
1238 }
1239 return true;
1240}
1241
1242static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1243 enum pipe pipe, u32 val)
1244{
1245 if ((val & LVDS_PORT_EN) == 0)
1246 return false;
1247
1248 if (HAS_PCH_CPT(dev_priv->dev)) {
1249 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1250 return false;
1251 } else {
1252 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1253 return false;
1254 }
1255 return true;
1256}
1257
1258static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1259 enum pipe pipe, u32 val)
1260{
1261 if ((val & ADPA_DAC_ENABLE) == 0)
1262 return false;
1263 if (HAS_PCH_CPT(dev_priv->dev)) {
1264 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1265 return false;
1266 } else {
1267 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1268 return false;
1269 }
1270 return true;
1271}
1272
291906f1 1273static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1274 enum pipe pipe, int reg, u32 port_sel)
291906f1 1275{
47a05eca 1276 u32 val = I915_READ(reg);
4e634389 1277 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1278 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1279 reg, pipe_name(pipe));
de9a35ab 1280
75c5da27
DV		 1281 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1282 && (val & DP_PIPEB_SELECT),
de9a35ab 1283 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1284}
1285
1286static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1287 enum pipe pipe, int reg)
1288{
47a05eca 1289 u32 val = I915_READ(reg);
b70ad586 1290 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1291 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1292 reg, pipe_name(pipe));
de9a35ab 1293
dc0fa718 1294 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1295 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1296 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1297}
1298
1299static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1300 enum pipe pipe)
1301{
1302 int reg;
1303 u32 val;
291906f1 1304
f0575e92
KP		 1305 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1306 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1307 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1308
1309 reg = PCH_ADPA;
1310 val = I915_READ(reg);
b70ad586 1311 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1312 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1313 pipe_name(pipe));
291906f1
JB		 1314
1315 reg = PCH_LVDS;
1316 val = I915_READ(reg);
b70ad586 1317 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1318 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1319 pipe_name(pipe));
291906f1 1320
e2debe91
PZ		 1321 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1322 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1323 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1324}
1325
426115cf 1326static void vlv_enable_pll(struct intel_crtc *crtc)
87442f73 1327{
426115cf
DV		 1328 struct drm_device *dev = crtc->base.dev;
1329 struct drm_i915_private *dev_priv = dev->dev_private;
1330 int reg = DPLL(crtc->pipe);
1331 u32 dpll = crtc->config.dpll_hw_state.dpll;
87442f73 1332
426115cf 1333 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1334
1335 /* No really, not for ILK+ */
1336 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1337
1338 /* PLL is protected by panel, make sure we can write it */
1339 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
426115cf 1340 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1341
426115cf
DV		 1342 I915_WRITE(reg, dpll);
1343 POSTING_READ(reg);
1344 udelay(150);
1345
1346 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1347 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1348
1349 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1350 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1351
1352 /* We do this three times for luck */
426115cf 1353 I915_WRITE(reg, dpll);
87442f73
DV		 1354 POSTING_READ(reg);
1355 udelay(150); /* wait for warmup */
426115cf 1356 I915_WRITE(reg, dpll);
87442f73
DV		 1357 POSTING_READ(reg);
1358 udelay(150); /* wait for warmup */
426115cf 1359 I915_WRITE(reg, dpll);
87442f73
DV		 1360 POSTING_READ(reg);
1361 udelay(150); /* wait for warmup */
1362}
1363
66e3d5c0 1364static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1365{
66e3d5c0
DV		 1366 struct drm_device *dev = crtc->base.dev;
1367 struct drm_i915_private *dev_priv = dev->dev_private;
1368 int reg = DPLL(crtc->pipe);
1369 u32 dpll = crtc->config.dpll_hw_state.dpll;
63d7bbe9 1370
66e3d5c0 1371 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1372
63d7bbe9 1373 /* No really, not for ILK+ */
87442f73 1374 BUG_ON(dev_priv->info->gen >= 5);
63d7bbe9
JB		 1375
1376 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1377 if (IS_MOBILE(dev) && !IS_I830(dev))
1378 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1379
66e3d5c0
DV		 1380 I915_WRITE(reg, dpll);
1381
1382 /* Wait for the clocks to stabilize. */
1383 POSTING_READ(reg);
1384 udelay(150);
1385
1386 if (INTEL_INFO(dev)->gen >= 4) {
1387 I915_WRITE(DPLL_MD(crtc->pipe),
1388 crtc->config.dpll_hw_state.dpll_md);
1389 } else {
1390 /* The pixel multiplier can only be updated once the
1391 * DPLL is enabled and the clocks are stable.
1392 *
1393 * So write it again.
1394 */
1395 I915_WRITE(reg, dpll);
1396 }
63d7bbe9
JB		 1397
1398 /* We do this three times for luck */
66e3d5c0 1399 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1400 POSTING_READ(reg);
1401 udelay(150); /* wait for warmup */
66e3d5c0 1402 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1403 POSTING_READ(reg);
1404 udelay(150); /* wait for warmup */
66e3d5c0 1405 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1406 POSTING_READ(reg);
1407 udelay(150); /* wait for warmup */
1408}
1409
1410/**
50b44a44 1411 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1412 * @dev_priv: i915 private structure
1413 * @pipe: pipe PLL to disable
1414 *
1415 * Disable the PLL for @pipe, making sure the pipe is off first.
1416 *
1417 * Note! This is for pre-ILK only.
1418 */
50b44a44 1419static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
63d7bbe9 1420{
63d7bbe9
JB		 1421 /* Don't disable pipe A or pipe A PLLs if needed */
1422 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1423 return;
1424
1425 /* Make sure the pipe isn't still relying on us */
1426 assert_pipe_disabled(dev_priv, pipe);
1427
50b44a44
DV		 1428 I915_WRITE(DPLL(pipe), 0);
1429 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1430}
1431
89b667f8
JB		 1432void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1433{
1434 u32 port_mask;
1435
1436 if (!port)
1437 port_mask = DPLL_PORTB_READY_MASK;
1438 else
1439 port_mask = DPLL_PORTC_READY_MASK;
1440
1441 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1442 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1443 'B' + port, I915_READ(DPLL(0)));
1444}
1445
92f2584a 1446/**
e72f9fbf 1447 * ironlake_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1448 * @dev_priv: i915 private structure
1449 * @pipe: pipe PLL to enable
1450 *
1451 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1452 * drives the transcoder clock.
1453 */
e2b78267 1454static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1455{
e2b78267
DV		 1456 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1457 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1458
48da64a8 1459 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1460 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1461 if (WARN_ON(pll == NULL))
48da64a8
CW		 1462 return;
1463
1464 if (WARN_ON(pll->refcount == 0))
1465 return;
ee7b9f93 1466
46edb027
DV		 1467 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1468 pll->name, pll->active, pll->on,
e2b78267 1469 crtc->base.base.id);
92f2584a 1470
cdbd2316
DV		 1471 if (pll->active++) {
1472 WARN_ON(!pll->on);
e9d6944e 1473 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1474 return;
1475 }
f4a091c7 1476 WARN_ON(pll->on);
ee7b9f93 1477
46edb027 1478 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1479 pll->enable(dev_priv, pll);
ee7b9f93 1480 pll->on = true;
92f2584a
JB		 1481}
1482
e2b78267 1483static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1484{
e2b78267
DV		 1485 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1486 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1487
92f2584a
JB		 1488 /* PCH only available on ILK+ */
1489 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1490 if (WARN_ON(pll == NULL))
ee7b9f93 1491 return;
92f2584a 1492
48da64a8
CW		 1493 if (WARN_ON(pll->refcount == 0))
1494 return;
7a419866 1495
46edb027
DV		 1496 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1497 pll->name, pll->active, pll->on,
e2b78267 1498 crtc->base.base.id);
7a419866 1499
48da64a8 1500 if (WARN_ON(pll->active == 0)) {
e9d6944e 1501 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1502 return;
1503 }
1504
e9d6944e 1505 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1506 WARN_ON(!pll->on);
cdbd2316 1507 if (--pll->active)
7a419866 1508 return;
ee7b9f93 1509
46edb027 1510 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1511 pll->disable(dev_priv, pll);
ee7b9f93 1512 pll->on = false;
92f2584a
JB		 1513}
1514
b8a4f404
PZ		 1515static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1516 enum pipe pipe)
040484af 1517{
23670b32 1518 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1519 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1520 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1521 uint32_t reg, val, pipeconf_val;
040484af
JB		 1522
1523 /* PCH only available on ILK+ */
1524 BUG_ON(dev_priv->info->gen < 5);
1525
1526 /* Make sure PCH DPLL is enabled */
e72f9fbf 1527 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1528 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1529
1530 /* FDI must be feeding us bits for PCH ports */
1531 assert_fdi_tx_enabled(dev_priv, pipe);
1532 assert_fdi_rx_enabled(dev_priv, pipe);
1533
23670b32
DV		 1534 if (HAS_PCH_CPT(dev)) {
1535 /* Workaround: Set the timing override bit before enabling the
1536 * pch transcoder. */
1537 reg = TRANS_CHICKEN2(pipe);
1538 val = I915_READ(reg);
1539 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1540 I915_WRITE(reg, val);
59c859d6 1541 }
23670b32 1542
ab9412ba 1543 reg = PCH_TRANSCONF(pipe);
040484af 1544 val = I915_READ(reg);
5f7f726d 1545 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1546
1547 if (HAS_PCH_IBX(dev_priv->dev)) {
1548 /*
1549 * make the BPC in transcoder be consistent with
1550 * that in pipeconf reg.
1551 */
dfd07d72
DV		 1552 val &= ~PIPECONF_BPC_MASK;
1553 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1554 }
5f7f726d
PZ		 1555
1556 val &= ~TRANS_INTERLACE_MASK;
1557 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1558 if (HAS_PCH_IBX(dev_priv->dev) &&
1559 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1560 val |= TRANS_LEGACY_INTERLACED_ILK;
1561 else
1562 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1563 else
1564 val |= TRANS_PROGRESSIVE;
1565
040484af
JB		 1566 I915_WRITE(reg, val | TRANS_ENABLE);
1567 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1568 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1569}
1570
8fb033d7 1571static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1572 enum transcoder cpu_transcoder)
040484af 1573{
8fb033d7 1574 u32 val, pipeconf_val;
8fb033d7
PZ		 1575
1576 /* PCH only available on ILK+ */
1577 BUG_ON(dev_priv->info->gen < 5);
1578
8fb033d7 1579 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1580 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1581 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1582
223a6fdf
PZ		 1583 /* Workaround: set timing override bit. */
1584 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1585 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1586 I915_WRITE(_TRANSA_CHICKEN2, val);
1587
25f3ef11 1588 val = TRANS_ENABLE;
937bb610 1589 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1590
9a76b1c6
PZ		 1591 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1592 PIPECONF_INTERLACED_ILK)
a35f2679 1593 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1594 else
1595 val |= TRANS_PROGRESSIVE;
1596
ab9412ba
DV		 1597 I915_WRITE(LPT_TRANSCONF, val);
1598 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 1599 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1600}
1601
b8a4f404
PZ		 1602static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1603 enum pipe pipe)
040484af 1604{
23670b32
DV		 1605 struct drm_device *dev = dev_priv->dev;
1606 uint32_t reg, val;
040484af
JB		 1607
1608 /* FDI relies on the transcoder */
1609 assert_fdi_tx_disabled(dev_priv, pipe);
1610 assert_fdi_rx_disabled(dev_priv, pipe);
1611
291906f1
JB		 1612 /* Ports must be off as well */
1613 assert_pch_ports_disabled(dev_priv, pipe);
1614
ab9412ba 1615 reg = PCH_TRANSCONF(pipe);
040484af
JB		 1616 val = I915_READ(reg);
1617 val &= ~TRANS_ENABLE;
1618 I915_WRITE(reg, val);
1619 /* wait for PCH transcoder off, transcoder state */
1620 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1621 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1622
1623 if (!HAS_PCH_IBX(dev)) {
1624 /* Workaround: Clear the timing override chicken bit again. */
1625 reg = TRANS_CHICKEN2(pipe);
1626 val = I915_READ(reg);
1627 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1628 I915_WRITE(reg, val);
1629 }
040484af
JB		 1630}
1631
ab4d966c 1632static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1633{
8fb033d7
PZ		 1634 u32 val;
1635
ab9412ba 1636 val = I915_READ(LPT_TRANSCONF);
8fb033d7 1637 val &= ~TRANS_ENABLE;
ab9412ba 1638 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 1639 /* wait for PCH transcoder off, transcoder state */
ab9412ba 1640 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 1641 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1642
1643 /* Workaround: clear timing override bit. */
1644 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1645 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1646 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1647}
1648
b24e7179 1649/**
309cfea8 1650 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1651 * @dev_priv: i915 private structure
1652 * @pipe: pipe to enable
040484af 1653 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1654 *
1655 * Enable @pipe, making sure that various hardware specific requirements
1656 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1657 *
1658 * @pipe should be %PIPE_A or %PIPE_B.
1659 *
1660 * Will wait until the pipe is actually running (i.e. first vblank) before
1661 * returning.
1662 */
040484af 1663static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
23538ef1 1664 bool pch_port, bool dsi)
b24e7179 1665{
702e7a56
PZ		 1666 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1667 pipe);
1a240d4d 1668 enum pipe pch_transcoder;
b24e7179
JB		 1669 int reg;
1670 u32 val;
1671
58c6eaa2
DV		 1672 assert_planes_disabled(dev_priv, pipe);
1673 assert_sprites_disabled(dev_priv, pipe);
1674
681e5811 1675 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1676 pch_transcoder = TRANSCODER_A;
1677 else
1678 pch_transcoder = pipe;
1679
b24e7179
JB		 1680 /*
1681 * A pipe without a PLL won't actually be able to drive bits from
1682 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1683 * need the check.
1684 */
1685 if (!HAS_PCH_SPLIT(dev_priv->dev))
23538ef1
JN		 1686 if (dsi)
1687 assert_dsi_pll_enabled(dev_priv);
1688 else
1689 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1690 else {
1691 if (pch_port) {
1692 /* if driving the PCH, we need FDI enabled */
cc391bbb 1693 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1694 assert_fdi_tx_pll_enabled(dev_priv,
1695 (enum pipe) cpu_transcoder);
040484af
JB		 1696 }
1697 /* FIXME: assert CPU port conditions for SNB+ */
1698 }
b24e7179 1699
702e7a56 1700 reg = PIPECONF(cpu_transcoder);
b24e7179 1701 val = I915_READ(reg);
00d70b15
CW		 1702 if (val & PIPECONF_ENABLE)
1703 return;
1704
1705 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1706 intel_wait_for_vblank(dev_priv->dev, pipe);
1707}
1708
1709/**
309cfea8 1710 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1711 * @dev_priv: i915 private structure
1712 * @pipe: pipe to disable
1713 *
1714 * Disable @pipe, making sure that various hardware specific requirements
1715 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1716 *
1717 * @pipe should be %PIPE_A or %PIPE_B.
1718 *
1719 * Will wait until the pipe has shut down before returning.
1720 */
1721static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1722 enum pipe pipe)
1723{
702e7a56
PZ		 1724 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1725 pipe);
b24e7179
JB		 1726 int reg;
1727 u32 val;
1728
1729 /*
1730 * Make sure planes won't keep trying to pump pixels to us,
1731 * or we might hang the display.
1732 */
1733 assert_planes_disabled(dev_priv, pipe);
19332d7a 1734 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1735
1736 /* Don't disable pipe A or pipe A PLLs if needed */
1737 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1738 return;
1739
702e7a56 1740 reg = PIPECONF(cpu_transcoder);
b24e7179 1741 val = I915_READ(reg);
00d70b15
CW		 1742 if ((val & PIPECONF_ENABLE) == 0)
1743 return;
1744
1745 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1746 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1747}
1748
d74362c9
KP		 1749/*
1750 * Plane regs are double buffered, going from enabled->disabled needs a
1751 * trigger in order to latch. The display address reg provides this.
1752 */
6f1d69b0 1753void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1754 enum plane plane)
1755{
14f86147
DL		 1756 if (dev_priv->info->gen >= 4)
1757 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1758 else
1759 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1760}
1761
b24e7179
JB		 1762/**
1763 * intel_enable_plane - enable a display plane on a given pipe
1764 * @dev_priv: i915 private structure
1765 * @plane: plane to enable
1766 * @pipe: pipe being fed
1767 *
1768 * Enable @plane on @pipe, making sure that @pipe is running first.
1769 */
1770static void intel_enable_plane(struct drm_i915_private *dev_priv,
1771 enum plane plane, enum pipe pipe)
1772{
1773 int reg;
1774 u32 val;
1775
1776 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1777 assert_pipe_enabled(dev_priv, pipe);
1778
1779 reg = DSPCNTR(plane);
1780 val = I915_READ(reg);
00d70b15
CW		 1781 if (val & DISPLAY_PLANE_ENABLE)
1782 return;
1783
1784 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1785 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1786 intel_wait_for_vblank(dev_priv->dev, pipe);
1787}
1788
b24e7179
JB		 1789/**
1790 * intel_disable_plane - disable a display plane
1791 * @dev_priv: i915 private structure
1792 * @plane: plane to disable
1793 * @pipe: pipe consuming the data
1794 *
1795 * Disable @plane; should be an independent operation.
1796 */
1797static void intel_disable_plane(struct drm_i915_private *dev_priv,
1798 enum plane plane, enum pipe pipe)
1799{
1800 int reg;
1801 u32 val;
1802
1803 reg = DSPCNTR(plane);
1804 val = I915_READ(reg);
00d70b15
CW		 1805 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1806 return;
1807
1808 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1809 intel_flush_display_plane(dev_priv, plane);
1810 intel_wait_for_vblank(dev_priv->dev, pipe);
1811}
1812
693db184
CW		 1813static bool need_vtd_wa(struct drm_device *dev)
1814{
1815#ifdef CONFIG_INTEL_IOMMU
1816 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1817 return true;
1818#endif
1819 return false;
1820}
1821
127bd2ac 1822int
48b956c5 1823intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1824 struct drm_i915_gem_object *obj,
919926ae 1825 struct intel_ring_buffer *pipelined)
6b95a207 1826{
ce453d81 1827 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1828 u32 alignment;
1829 int ret;
1830
05394f39 1831 switch (obj->tiling_mode) {
6b95a207 1832 case I915_TILING_NONE:
534843da
CW		 1833 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1834 alignment = 128 * 1024;
a6c45cf0 1835 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1836 alignment = 4 * 1024;
1837 else
1838 alignment = 64 * 1024;
6b95a207
KH		 1839 break;
1840 case I915_TILING_X:
1841 /* pin() will align the object as required by fence */
1842 alignment = 0;
1843 break;
1844 case I915_TILING_Y:
8bb6e959
DV		 1845 /* Despite that we check this in framebuffer_init userspace can
1846 * screw us over and change the tiling after the fact. Only
1847 * pinned buffers can't change their tiling. */
1848 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH		 1849 return -EINVAL;
1850 default:
1851 BUG();
1852 }
1853
693db184
CW		 1854 /* Note that the w/a also requires 64 PTE of padding following the
1855 * bo. We currently fill all unused PTE with the shadow page and so
1856 * we should always have valid PTE following the scanout preventing
1857 * the VT-d warning.
1858 */
1859 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1860 alignment = 256 * 1024;
1861
ce453d81 1862 dev_priv->mm.interruptible = false;
2da3b9b9 1863 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1864 if (ret)
ce453d81 1865 goto err_interruptible;
6b95a207
KH		 1866
1867 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1868 * fence, whereas 965+ only requires a fence if using
1869 * framebuffer compression. For simplicity, we always install
1870 * a fence as the cost is not that onerous.
1871 */
06d98131 1872 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1873 if (ret)
1874 goto err_unpin;
1690e1eb 1875
9a5a53b3 1876 i915_gem_object_pin_fence(obj);
6b95a207 1877
ce453d81 1878 dev_priv->mm.interruptible = true;
6b95a207 1879 return 0;
48b956c5
CW		 1880
1881err_unpin:
cc98b413 1882 i915_gem_object_unpin_from_display_plane(obj);
ce453d81
CW		 1883err_interruptible:
1884 dev_priv->mm.interruptible = true;
48b956c5 1885 return ret;
6b95a207
KH		 1886}
1887
1690e1eb
CW		 1888void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1889{
1890 i915_gem_object_unpin_fence(obj);
cc98b413 1891 i915_gem_object_unpin_from_display_plane(obj);
1690e1eb
CW		 1892}
1893
c2c75131
DV		 1894/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1895 * is assumed to be a power-of-two. */
bc752862
CW		 1896unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1897 unsigned int tiling_mode,
1898 unsigned int cpp,
1899 unsigned int pitch)
c2c75131 1900{
bc752862
CW		 1901 if (tiling_mode != I915_TILING_NONE) {
1902 unsigned int tile_rows, tiles;
c2c75131 1903
bc752862
CW		 1904 tile_rows = *y / 8;
1905 *y %= 8;
c2c75131 1906
bc752862
CW		 1907 tiles = *x / (512/cpp);
1908 *x %= 512/cpp;
1909
1910 return tile_rows * pitch * 8 + tiles * 4096;
1911 } else {
1912 unsigned int offset;
1913
1914 offset = *y * pitch + *x * cpp;
1915 *y = 0;
1916 *x = (offset & 4095) / cpp;
1917 return offset & -4096;
1918 }
c2c75131
DV		 1919}
1920
17638cd6
JB		 1921static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1922 int x, int y)
81255565
JB		 1923{
1924 struct drm_device *dev = crtc->dev;
1925 struct drm_i915_private *dev_priv = dev->dev_private;
1926 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1927 struct intel_framebuffer *intel_fb;
05394f39 1928 struct drm_i915_gem_object *obj;
81255565 1929 int plane = intel_crtc->plane;
e506a0c6 1930 unsigned long linear_offset;
81255565 1931 u32 dspcntr;
5eddb70b 1932 u32 reg;
81255565
JB		 1933
1934 switch (plane) {
1935 case 0:
1936 case 1:
1937 break;
1938 default:
84f44ce7 1939 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 1940 return -EINVAL;
1941 }
1942
1943 intel_fb = to_intel_framebuffer(fb);
1944 obj = intel_fb->obj;
81255565 1945
5eddb70b
CW		 1946 reg = DSPCNTR(plane);
1947 dspcntr = I915_READ(reg);
81255565
JB		 1948 /* Mask out pixel format bits in case we change it */
1949 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 1950 switch (fb->pixel_format) {
1951 case DRM_FORMAT_C8:
81255565
JB		 1952 dspcntr |= DISPPLANE_8BPP;
1953 break;
57779d06
VS		 1954 case DRM_FORMAT_XRGB1555:
1955 case DRM_FORMAT_ARGB1555:
1956 dspcntr |= DISPPLANE_BGRX555;
81255565 1957 break;
57779d06
VS		 1958 case DRM_FORMAT_RGB565:
1959 dspcntr |= DISPPLANE_BGRX565;
1960 break;
1961 case DRM_FORMAT_XRGB8888:
1962 case DRM_FORMAT_ARGB8888:
1963 dspcntr |= DISPPLANE_BGRX888;
1964 break;
1965 case DRM_FORMAT_XBGR8888:
1966 case DRM_FORMAT_ABGR8888:
1967 dspcntr |= DISPPLANE_RGBX888;
1968 break;
1969 case DRM_FORMAT_XRGB2101010:
1970 case DRM_FORMAT_ARGB2101010:
1971 dspcntr |= DISPPLANE_BGRX101010;
1972 break;
1973 case DRM_FORMAT_XBGR2101010:
1974 case DRM_FORMAT_ABGR2101010:
1975 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 1976 break;
1977 default:
baba133a 1978 BUG();
81255565 1979 }
57779d06 1980
a6c45cf0 1981 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 1982 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 1983 dspcntr |= DISPPLANE_TILED;
1984 else
1985 dspcntr &= ~DISPPLANE_TILED;
1986 }
1987
de1aa629
VS		 1988 if (IS_G4X(dev))
1989 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1990
5eddb70b 1991 I915_WRITE(reg, dspcntr);
81255565 1992
e506a0c6 1993 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 1994
c2c75131
DV		 1995 if (INTEL_INFO(dev)->gen >= 4) {
1996 intel_crtc->dspaddr_offset =
bc752862
CW		 1997 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
1998 fb->bits_per_pixel / 8,
1999 fb->pitches[0]);
c2c75131
DV		 2000 linear_offset -= intel_crtc->dspaddr_offset;
2001 } else {
e506a0c6 2002 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2003 }
e506a0c6 2004
f343c5f6
BW		 2005 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2006 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2007 fb->pitches[0]);
01f2c773 2008 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2009 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131 2010 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 2011 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2012 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2013 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2014 } else
f343c5f6 2015 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2016 POSTING_READ(reg);
81255565 2017
17638cd6
JB		 2018 return 0;
2019}
2020
2021static int ironlake_update_plane(struct drm_crtc *crtc,
2022 struct drm_framebuffer *fb, int x, int y)
2023{
2024 struct drm_device *dev = crtc->dev;
2025 struct drm_i915_private *dev_priv = dev->dev_private;
2026 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2027 struct intel_framebuffer *intel_fb;
2028 struct drm_i915_gem_object *obj;
2029 int plane = intel_crtc->plane;
e506a0c6 2030 unsigned long linear_offset;
17638cd6
JB		 2031 u32 dspcntr;
2032 u32 reg;
2033
2034 switch (plane) {
2035 case 0:
2036 case 1:
27f8227b 2037 case 2:
17638cd6
JB		 2038 break;
2039 default:
84f44ce7 2040 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 2041 return -EINVAL;
2042 }
2043
2044 intel_fb = to_intel_framebuffer(fb);
2045 obj = intel_fb->obj;
2046
2047 reg = DSPCNTR(plane);
2048 dspcntr = I915_READ(reg);
2049 /* Mask out pixel format bits in case we change it */
2050 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2051 switch (fb->pixel_format) {
2052 case DRM_FORMAT_C8:
17638cd6
JB		 2053 dspcntr |= DISPPLANE_8BPP;
2054 break;
57779d06
VS		 2055 case DRM_FORMAT_RGB565:
2056 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2057 break;
57779d06
VS		 2058 case DRM_FORMAT_XRGB8888:
2059 case DRM_FORMAT_ARGB8888:
2060 dspcntr |= DISPPLANE_BGRX888;
2061 break;
2062 case DRM_FORMAT_XBGR8888:
2063 case DRM_FORMAT_ABGR8888:
2064 dspcntr |= DISPPLANE_RGBX888;
2065 break;
2066 case DRM_FORMAT_XRGB2101010:
2067 case DRM_FORMAT_ARGB2101010:
2068 dspcntr |= DISPPLANE_BGRX101010;
2069 break;
2070 case DRM_FORMAT_XBGR2101010:
2071 case DRM_FORMAT_ABGR2101010:
2072 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2073 break;
2074 default:
baba133a 2075 BUG();
17638cd6
JB		 2076 }
2077
2078 if (obj->tiling_mode != I915_TILING_NONE)
2079 dspcntr |= DISPPLANE_TILED;
2080 else
2081 dspcntr &= ~DISPPLANE_TILED;
2082
1f5d76db
PZ		 2083 if (IS_HASWELL(dev))
2084 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2085 else
2086 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6
JB		 2087
2088 I915_WRITE(reg, dspcntr);
2089
e506a0c6 2090 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2091 intel_crtc->dspaddr_offset =
bc752862
CW		 2092 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2093 fb->bits_per_pixel / 8,
2094 fb->pitches[0]);
c2c75131 2095 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2096
f343c5f6
BW		 2097 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2098 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2099 fb->pitches[0]);
01f2c773 2100 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131 2101 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 2102 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2103 if (IS_HASWELL(dev)) {
2104 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2105 } else {
2106 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2107 I915_WRITE(DSPLINOFF(plane), linear_offset);
2108 }
17638cd6
JB		 2109 POSTING_READ(reg);
2110
2111 return 0;
2112}
2113
2114/* Assume fb object is pinned & idle & fenced and just update base pointers */
2115static int
2116intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2117 int x, int y, enum mode_set_atomic state)
2118{
2119 struct drm_device *dev = crtc->dev;
2120 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2121
6b8e6ed0
CW		 2122 if (dev_priv->display.disable_fbc)
2123 dev_priv->display.disable_fbc(dev);
3dec0095 2124 intel_increase_pllclock(crtc);
81255565 2125
6b8e6ed0 2126 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2127}
2128
96a02917
VS		 2129void intel_display_handle_reset(struct drm_device *dev)
2130{
2131 struct drm_i915_private *dev_priv = dev->dev_private;
2132 struct drm_crtc *crtc;
2133
2134 /*
2135 * Flips in the rings have been nuked by the reset,
2136 * so complete all pending flips so that user space
2137 * will get its events and not get stuck.
2138 *
2139 * Also update the base address of all primary
2140 * planes to the the last fb to make sure we're
2141 * showing the correct fb after a reset.
2142 *
2143 * Need to make two loops over the crtcs so that we
2144 * don't try to grab a crtc mutex before the
2145 * pending_flip_queue really got woken up.
2146 */
2147
2148 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2149 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2150 enum plane plane = intel_crtc->plane;
2151
2152 intel_prepare_page_flip(dev, plane);
2153 intel_finish_page_flip_plane(dev, plane);
2154 }
2155
2156 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2157 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2158
2159 mutex_lock(&crtc->mutex);
2160 if (intel_crtc->active)
2161 dev_priv->display.update_plane(crtc, crtc->fb,
2162 crtc->x, crtc->y);
2163 mutex_unlock(&crtc->mutex);
2164 }
2165}
2166
14667a4b
CW		 2167static int
2168intel_finish_fb(struct drm_framebuffer *old_fb)
2169{
2170 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2171 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2172 bool was_interruptible = dev_priv->mm.interruptible;
2173 int ret;
2174
14667a4b
CW		 2175 /* Big Hammer, we also need to ensure that any pending
2176 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2177 * current scanout is retired before unpinning the old
2178 * framebuffer.
2179 *
2180 * This should only fail upon a hung GPU, in which case we
2181 * can safely continue.
2182 */
2183 dev_priv->mm.interruptible = false;
2184 ret = i915_gem_object_finish_gpu(obj);
2185 dev_priv->mm.interruptible = was_interruptible;
2186
2187 return ret;
2188}
2189
198598d0
VS		 2190static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2191{
2192 struct drm_device *dev = crtc->dev;
2193 struct drm_i915_master_private *master_priv;
2194 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2195
2196 if (!dev->primary->master)
2197 return;
2198
2199 master_priv = dev->primary->master->driver_priv;
2200 if (!master_priv->sarea_priv)
2201 return;
2202
2203 switch (intel_crtc->pipe) {
2204 case 0:
2205 master_priv->sarea_priv->pipeA_x = x;
2206 master_priv->sarea_priv->pipeA_y = y;
2207 break;
2208 case 1:
2209 master_priv->sarea_priv->pipeB_x = x;
2210 master_priv->sarea_priv->pipeB_y = y;
2211 break;
2212 default:
2213 break;
2214 }
2215}
2216
5c3b82e2 2217static int
3c4fdcfb 2218intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2219 struct drm_framebuffer *fb)
79e53945
JB		 2220{
2221 struct drm_device *dev = crtc->dev;
6b8e6ed0 2222 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2223 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2224 struct drm_framebuffer *old_fb;
5c3b82e2 2225 int ret;
79e53945
JB		 2226
2227 /* no fb bound */
94352cf9 2228 if (!fb) {
a5071c2f 2229 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2230 return 0;
2231 }
2232
7eb552ae 2233 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2234 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2235 plane_name(intel_crtc->plane),
2236 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2237 return -EINVAL;
79e53945
JB		 2238 }
2239
5c3b82e2 2240 mutex_lock(&dev->struct_mutex);
265db958 2241 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2242 to_intel_framebuffer(fb)->obj,
919926ae 2243 NULL);
5c3b82e2
CW		 2244 if (ret != 0) {
2245 mutex_unlock(&dev->struct_mutex);
a5071c2f 2246 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2247 return ret;
2248 }
79e53945 2249
4d6a3e63
JB		 2250 /* Update pipe size and adjust fitter if needed */
2251 if (i915_fastboot) {
2252 I915_WRITE(PIPESRC(intel_crtc->pipe),
2253 ((crtc->mode.hdisplay - 1) << 16) |
2254 (crtc->mode.vdisplay - 1));
2255 if (!intel_crtc->config.pch_pfit.size &&
2256 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2257 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2258 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2259 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2260 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2261 }
2262 }
2263
94352cf9 2264 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2265 if (ret) {
94352cf9 2266 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2267 mutex_unlock(&dev->struct_mutex);
a5071c2f 2268 DRM_ERROR("failed to update base address\n");
4e6cfefc 2269 return ret;
79e53945 2270 }
3c4fdcfb 2271
94352cf9
DV		 2272 old_fb = crtc->fb;
2273 crtc->fb = fb;
6c4c86f5
DV		 2274 crtc->x = x;
2275 crtc->y = y;
94352cf9 2276
b7f1de28 2277 if (old_fb) {
d7697eea
DV		 2278 if (intel_crtc->active && old_fb != fb)
2279 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2280 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2281 }
652c393a 2282
6b8e6ed0 2283 intel_update_fbc(dev);
4906557e 2284 intel_edp_psr_update(dev);
5c3b82e2 2285 mutex_unlock(&dev->struct_mutex);
79e53945 2286
198598d0 2287 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2288
2289 return 0;
79e53945
JB		 2290}
2291
5e84e1a4
ZW		 2292static void intel_fdi_normal_train(struct drm_crtc *crtc)
2293{
2294 struct drm_device *dev = crtc->dev;
2295 struct drm_i915_private *dev_priv = dev->dev_private;
2296 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2297 int pipe = intel_crtc->pipe;
2298 u32 reg, temp;
2299
2300 /* enable normal train */
2301 reg = FDI_TX_CTL(pipe);
2302 temp = I915_READ(reg);
61e499bf 2303 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2304 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2305 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2306 } else {
2307 temp &= ~FDI_LINK_TRAIN_NONE;
2308 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2309 }
5e84e1a4
ZW		 2310 I915_WRITE(reg, temp);
2311
2312 reg = FDI_RX_CTL(pipe);
2313 temp = I915_READ(reg);
2314 if (HAS_PCH_CPT(dev)) {
2315 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2316 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2317 } else {
2318 temp &= ~FDI_LINK_TRAIN_NONE;
2319 temp |= FDI_LINK_TRAIN_NONE;
2320 }
2321 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2322
2323 /* wait one idle pattern time */
2324 POSTING_READ(reg);
2325 udelay(1000);
357555c0
JB		 2326
2327 /* IVB wants error correction enabled */
2328 if (IS_IVYBRIDGE(dev))
2329 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2330 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2331}
2332
1e833f40
DV		 2333static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2334{
2335 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2336}
2337
01a415fd
DV		 2338static void ivb_modeset_global_resources(struct drm_device *dev)
2339{
2340 struct drm_i915_private *dev_priv = dev->dev_private;
2341 struct intel_crtc *pipe_B_crtc =
2342 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2343 struct intel_crtc *pipe_C_crtc =
2344 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2345 uint32_t temp;
2346
1e833f40
DV		 2347 /*
2348 * When everything is off disable fdi C so that we could enable fdi B
2349 * with all lanes. Note that we don't care about enabled pipes without
2350 * an enabled pch encoder.
2351 */
2352 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2353 !pipe_has_enabled_pch(pipe_C_crtc)) {
01a415fd
DV		 2354 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2355 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2356
2357 temp = I915_READ(SOUTH_CHICKEN1);
2358 temp &= ~FDI_BC_BIFURCATION_SELECT;
2359 DRM_DEBUG_KMS("disabling fdi C rx\n");
2360 I915_WRITE(SOUTH_CHICKEN1, temp);
2361 }
2362}
2363
8db9d77b
ZW		 2364/* The FDI link training functions for ILK/Ibexpeak. */
2365static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2366{
2367 struct drm_device *dev = crtc->dev;
2368 struct drm_i915_private *dev_priv = dev->dev_private;
2369 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2370 int pipe = intel_crtc->pipe;
0fc932b8 2371 int plane = intel_crtc->plane;
5eddb70b 2372 u32 reg, temp, tries;
8db9d77b 2373
0fc932b8
JB		 2374 /* FDI needs bits from pipe & plane first */
2375 assert_pipe_enabled(dev_priv, pipe);
2376 assert_plane_enabled(dev_priv, plane);
2377
e1a44743
AJ		 2378 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2379 for train result */
5eddb70b
CW		 2380 reg = FDI_RX_IMR(pipe);
2381 temp = I915_READ(reg);
e1a44743
AJ		 2382 temp &= ~FDI_RX_SYMBOL_LOCK;
2383 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2384 I915_WRITE(reg, temp);
2385 I915_READ(reg);
e1a44743
AJ		 2386 udelay(150);
2387
8db9d77b 2388 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2389 reg = FDI_TX_CTL(pipe);
2390 temp = I915_READ(reg);
627eb5a3
DV		 2391 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2392 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2393 temp &= ~FDI_LINK_TRAIN_NONE;
2394 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2395 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2396
5eddb70b
CW		 2397 reg = FDI_RX_CTL(pipe);
2398 temp = I915_READ(reg);
8db9d77b
ZW		 2399 temp &= ~FDI_LINK_TRAIN_NONE;
2400 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2401 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2402
2403 POSTING_READ(reg);
8db9d77b
ZW		 2404 udelay(150);
2405
5b2adf89 2406 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2407 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2408 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2409 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2410
5eddb70b 2411 reg = FDI_RX_IIR(pipe);
e1a44743 2412 for (tries = 0; tries < 5; tries++) {
5eddb70b 2413 temp = I915_READ(reg);
8db9d77b
ZW		 2414 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2415
2416 if ((temp & FDI_RX_BIT_LOCK)) {
2417 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2418 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2419 break;
2420 }
8db9d77b 2421 }
e1a44743 2422 if (tries == 5)
5eddb70b 2423 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2424
2425 /* Train 2 */
5eddb70b
CW		 2426 reg = FDI_TX_CTL(pipe);
2427 temp = I915_READ(reg);
8db9d77b
ZW		 2428 temp &= ~FDI_LINK_TRAIN_NONE;
2429 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2430 I915_WRITE(reg, temp);
8db9d77b 2431
5eddb70b
CW		 2432 reg = FDI_RX_CTL(pipe);
2433 temp = I915_READ(reg);
8db9d77b
ZW		 2434 temp &= ~FDI_LINK_TRAIN_NONE;
2435 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2436 I915_WRITE(reg, temp);
8db9d77b 2437
5eddb70b
CW		 2438 POSTING_READ(reg);
2439 udelay(150);
8db9d77b 2440
5eddb70b 2441 reg = FDI_RX_IIR(pipe);
e1a44743 2442 for (tries = 0; tries < 5; tries++) {
5eddb70b 2443 temp = I915_READ(reg);
8db9d77b
ZW		 2444 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2445
2446 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2447 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2448 DRM_DEBUG_KMS("FDI train 2 done.\n");
2449 break;
2450 }
8db9d77b 2451 }
e1a44743 2452 if (tries == 5)
5eddb70b 2453 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2454
2455 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2456
8db9d77b
ZW		 2457}
2458
0206e353 2459static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2460 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2461 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2462 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2463 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2464};
2465
2466/* The FDI link training functions for SNB/Cougarpoint. */
2467static void gen6_fdi_link_train(struct drm_crtc *crtc)
2468{
2469 struct drm_device *dev = crtc->dev;
2470 struct drm_i915_private *dev_priv = dev->dev_private;
2471 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2472 int pipe = intel_crtc->pipe;
fa37d39e 2473 u32 reg, temp, i, retry;
8db9d77b 2474
e1a44743
AJ		 2475 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2476 for train result */
5eddb70b
CW		 2477 reg = FDI_RX_IMR(pipe);
2478 temp = I915_READ(reg);
e1a44743
AJ		 2479 temp &= ~FDI_RX_SYMBOL_LOCK;
2480 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2481 I915_WRITE(reg, temp);
2482
2483 POSTING_READ(reg);
e1a44743
AJ		 2484 udelay(150);
2485
8db9d77b 2486 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2487 reg = FDI_TX_CTL(pipe);
2488 temp = I915_READ(reg);
627eb5a3
DV		 2489 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2490 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2491 temp &= ~FDI_LINK_TRAIN_NONE;
2492 temp |= FDI_LINK_TRAIN_PATTERN_1;
2493 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2494 /* SNB-B */
2495 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2496 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2497
d74cf324
DV		 2498 I915_WRITE(FDI_RX_MISC(pipe),
2499 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2500
5eddb70b
CW		 2501 reg = FDI_RX_CTL(pipe);
2502 temp = I915_READ(reg);
8db9d77b
ZW		 2503 if (HAS_PCH_CPT(dev)) {
2504 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2505 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2506 } else {
2507 temp &= ~FDI_LINK_TRAIN_NONE;
2508 temp |= FDI_LINK_TRAIN_PATTERN_1;
2509 }
5eddb70b
CW		 2510 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2511
2512 POSTING_READ(reg);
8db9d77b
ZW		 2513 udelay(150);
2514
0206e353 2515 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2516 reg = FDI_TX_CTL(pipe);
2517 temp = I915_READ(reg);
8db9d77b
ZW		 2518 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2519 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2520 I915_WRITE(reg, temp);
2521
2522 POSTING_READ(reg);
8db9d77b
ZW		 2523 udelay(500);
2524
fa37d39e
SP		 2525 for (retry = 0; retry < 5; retry++) {
2526 reg = FDI_RX_IIR(pipe);
2527 temp = I915_READ(reg);
2528 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2529 if (temp & FDI_RX_BIT_LOCK) {
2530 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2531 DRM_DEBUG_KMS("FDI train 1 done.\n");
2532 break;
2533 }
2534 udelay(50);
8db9d77b 2535 }
fa37d39e
SP		 2536 if (retry < 5)
2537 break;
8db9d77b
ZW		 2538 }
2539 if (i == 4)
5eddb70b 2540 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2541
2542 /* Train 2 */
5eddb70b
CW		 2543 reg = FDI_TX_CTL(pipe);
2544 temp = I915_READ(reg);
8db9d77b
ZW		 2545 temp &= ~FDI_LINK_TRAIN_NONE;
2546 temp |= FDI_LINK_TRAIN_PATTERN_2;
2547 if (IS_GEN6(dev)) {
2548 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2549 /* SNB-B */
2550 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2551 }
5eddb70b 2552 I915_WRITE(reg, temp);
8db9d77b 2553
5eddb70b
CW		 2554 reg = FDI_RX_CTL(pipe);
2555 temp = I915_READ(reg);
8db9d77b
ZW		 2556 if (HAS_PCH_CPT(dev)) {
2557 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2558 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2559 } else {
2560 temp &= ~FDI_LINK_TRAIN_NONE;
2561 temp |= FDI_LINK_TRAIN_PATTERN_2;
2562 }
5eddb70b
CW		 2563 I915_WRITE(reg, temp);
2564
2565 POSTING_READ(reg);
8db9d77b
ZW		 2566 udelay(150);
2567
0206e353 2568 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2569 reg = FDI_TX_CTL(pipe);
2570 temp = I915_READ(reg);
8db9d77b
ZW		 2571 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2572 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2573 I915_WRITE(reg, temp);
2574
2575 POSTING_READ(reg);
8db9d77b
ZW		 2576 udelay(500);
2577
fa37d39e
SP		 2578 for (retry = 0; retry < 5; retry++) {
2579 reg = FDI_RX_IIR(pipe);
2580 temp = I915_READ(reg);
2581 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2582 if (temp & FDI_RX_SYMBOL_LOCK) {
2583 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2584 DRM_DEBUG_KMS("FDI train 2 done.\n");
2585 break;
2586 }
2587 udelay(50);
8db9d77b 2588 }
fa37d39e
SP		 2589 if (retry < 5)
2590 break;
8db9d77b
ZW		 2591 }
2592 if (i == 4)
5eddb70b 2593 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2594
2595 DRM_DEBUG_KMS("FDI train done.\n");
2596}
2597
357555c0
JB		 2598/* Manual link training for Ivy Bridge A0 parts */
2599static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2600{
2601 struct drm_device *dev = crtc->dev;
2602 struct drm_i915_private *dev_priv = dev->dev_private;
2603 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2604 int pipe = intel_crtc->pipe;
139ccd3f 2605 u32 reg, temp, i, j;
357555c0
JB		 2606
2607 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2608 for train result */
2609 reg = FDI_RX_IMR(pipe);
2610 temp = I915_READ(reg);
2611 temp &= ~FDI_RX_SYMBOL_LOCK;
2612 temp &= ~FDI_RX_BIT_LOCK;
2613 I915_WRITE(reg, temp);
2614
2615 POSTING_READ(reg);
2616 udelay(150);
2617
01a415fd
DV		 2618 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2619 I915_READ(FDI_RX_IIR(pipe)));
2620
139ccd3f
JB		 2621 /* Try each vswing and preemphasis setting twice before moving on */
2622 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2623 /* disable first in case we need to retry */
2624 reg = FDI_TX_CTL(pipe);
2625 temp = I915_READ(reg);
2626 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2627 temp &= ~FDI_TX_ENABLE;
2628 I915_WRITE(reg, temp);
357555c0 2629
139ccd3f
JB		 2630 reg = FDI_RX_CTL(pipe);
2631 temp = I915_READ(reg);
2632 temp &= ~FDI_LINK_TRAIN_AUTO;
2633 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2634 temp &= ~FDI_RX_ENABLE;
2635 I915_WRITE(reg, temp);
357555c0 2636
139ccd3f 2637 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 2638 reg = FDI_TX_CTL(pipe);
2639 temp = I915_READ(reg);
139ccd3f
JB		 2640 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2641 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2642 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 2643 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 2644 temp |= snb_b_fdi_train_param[j/2];
2645 temp |= FDI_COMPOSITE_SYNC;
2646 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 2647
139ccd3f
JB		 2648 I915_WRITE(FDI_RX_MISC(pipe),
2649 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 2650
139ccd3f 2651 reg = FDI_RX_CTL(pipe);
357555c0 2652 temp = I915_READ(reg);
139ccd3f
JB		 2653 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2654 temp |= FDI_COMPOSITE_SYNC;
2655 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 2656
139ccd3f
JB		 2657 POSTING_READ(reg);
2658 udelay(1); /* should be 0.5us */
357555c0 2659
139ccd3f
JB		 2660 for (i = 0; i < 4; i++) {
2661 reg = FDI_RX_IIR(pipe);
2662 temp = I915_READ(reg);
2663 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 2664
139ccd3f
JB		 2665 if (temp & FDI_RX_BIT_LOCK ||
2666 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2667 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2668 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2669 i);
2670 break;
2671 }
2672 udelay(1); /* should be 0.5us */
2673 }
2674 if (i == 4) {
2675 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2676 continue;
2677 }
357555c0 2678
139ccd3f 2679 /* Train 2 */
357555c0
JB		 2680 reg = FDI_TX_CTL(pipe);
2681 temp = I915_READ(reg);
139ccd3f
JB		 2682 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2683 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2684 I915_WRITE(reg, temp);
2685
2686 reg = FDI_RX_CTL(pipe);
2687 temp = I915_READ(reg);
2688 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2689 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 2690 I915_WRITE(reg, temp);
2691
2692 POSTING_READ(reg);
139ccd3f 2693 udelay(2); /* should be 1.5us */
357555c0 2694
139ccd3f
JB		 2695 for (i = 0; i < 4; i++) {
2696 reg = FDI_RX_IIR(pipe);
2697 temp = I915_READ(reg);
2698 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 2699
139ccd3f
JB		 2700 if (temp & FDI_RX_SYMBOL_LOCK ||
2701 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2702 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2703 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2704 i);
2705 goto train_done;
2706 }
2707 udelay(2); /* should be 1.5us */
357555c0 2708 }
139ccd3f
JB		 2709 if (i == 4)
2710 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 2711 }
357555c0 2712
139ccd3f 2713train_done:
357555c0
JB		 2714 DRM_DEBUG_KMS("FDI train done.\n");
2715}
2716
88cefb6c 2717static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2718{
88cefb6c 2719 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2720 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2721 int pipe = intel_crtc->pipe;
5eddb70b 2722 u32 reg, temp;
79e53945 2723
c64e311e 2724
c98e9dcf 2725 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2726 reg = FDI_RX_CTL(pipe);
2727 temp = I915_READ(reg);
627eb5a3
DV		 2728 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2729 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
dfd07d72 2730 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2731 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2732
2733 POSTING_READ(reg);
c98e9dcf
JB		 2734 udelay(200);
2735
2736 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2737 temp = I915_READ(reg);
2738 I915_WRITE(reg, temp | FDI_PCDCLK);
2739
2740 POSTING_READ(reg);
c98e9dcf
JB		 2741 udelay(200);
2742
20749730
PZ		 2743 /* Enable CPU FDI TX PLL, always on for Ironlake */
2744 reg = FDI_TX_CTL(pipe);
2745 temp = I915_READ(reg);
2746 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2747 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2748
20749730
PZ		 2749 POSTING_READ(reg);
2750 udelay(100);
6be4a607 2751 }
0e23b99d
JB		 2752}
2753
88cefb6c
DV		 2754static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2755{
2756 struct drm_device *dev = intel_crtc->base.dev;
2757 struct drm_i915_private *dev_priv = dev->dev_private;
2758 int pipe = intel_crtc->pipe;
2759 u32 reg, temp;
2760
2761 /* Switch from PCDclk to Rawclk */
2762 reg = FDI_RX_CTL(pipe);
2763 temp = I915_READ(reg);
2764 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2765
2766 /* Disable CPU FDI TX PLL */
2767 reg = FDI_TX_CTL(pipe);
2768 temp = I915_READ(reg);
2769 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2770
2771 POSTING_READ(reg);
2772 udelay(100);
2773
2774 reg = FDI_RX_CTL(pipe);
2775 temp = I915_READ(reg);
2776 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2777
2778 /* Wait for the clocks to turn off. */
2779 POSTING_READ(reg);
2780 udelay(100);
2781}
2782
0fc932b8
JB		 2783static void ironlake_fdi_disable(struct drm_crtc *crtc)
2784{
2785 struct drm_device *dev = crtc->dev;
2786 struct drm_i915_private *dev_priv = dev->dev_private;
2787 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2788 int pipe = intel_crtc->pipe;
2789 u32 reg, temp;
2790
2791 /* disable CPU FDI tx and PCH FDI rx */
2792 reg = FDI_TX_CTL(pipe);
2793 temp = I915_READ(reg);
2794 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2795 POSTING_READ(reg);
2796
2797 reg = FDI_RX_CTL(pipe);
2798 temp = I915_READ(reg);
2799 temp &= ~(0x7 << 16);
dfd07d72 2800 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2801 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2802
2803 POSTING_READ(reg);
2804 udelay(100);
2805
2806 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2807 if (HAS_PCH_IBX(dev)) {
2808 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2809 }
0fc932b8
JB		 2810
2811 /* still set train pattern 1 */
2812 reg = FDI_TX_CTL(pipe);
2813 temp = I915_READ(reg);
2814 temp &= ~FDI_LINK_TRAIN_NONE;
2815 temp |= FDI_LINK_TRAIN_PATTERN_1;
2816 I915_WRITE(reg, temp);
2817
2818 reg = FDI_RX_CTL(pipe);
2819 temp = I915_READ(reg);
2820 if (HAS_PCH_CPT(dev)) {
2821 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2822 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2823 } else {
2824 temp &= ~FDI_LINK_TRAIN_NONE;
2825 temp |= FDI_LINK_TRAIN_PATTERN_1;
2826 }
2827 /* BPC in FDI rx is consistent with that in PIPECONF */
2828 temp &= ~(0x07 << 16);
dfd07d72 2829 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2830 I915_WRITE(reg, temp);
2831
2832 POSTING_READ(reg);
2833 udelay(100);
2834}
2835
5bb61643
CW		 2836static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2837{
2838 struct drm_device *dev = crtc->dev;
2839 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2840 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2841 unsigned long flags;
2842 bool pending;
2843
10d83730
VS		 2844 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2845 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2846 return false;
2847
2848 spin_lock_irqsave(&dev->event_lock, flags);
2849 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2850 spin_unlock_irqrestore(&dev->event_lock, flags);
2851
2852 return pending;
2853}
2854
e6c3a2a6
CW		 2855static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2856{
0f91128d 2857 struct drm_device *dev = crtc->dev;
5bb61643 2858 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2859
2860 if (crtc->fb == NULL)
2861 return;
2862
2c10d571
DV		 2863 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2864
5bb61643
CW		 2865 wait_event(dev_priv->pending_flip_queue,
2866 !intel_crtc_has_pending_flip(crtc));
2867
0f91128d
CW		 2868 mutex_lock(&dev->struct_mutex);
2869 intel_finish_fb(crtc->fb);
2870 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2871}
2872
e615efe4
ED		 2873/* Program iCLKIP clock to the desired frequency */
2874static void lpt_program_iclkip(struct drm_crtc *crtc)
2875{
2876 struct drm_device *dev = crtc->dev;
2877 struct drm_i915_private *dev_priv = dev->dev_private;
2878 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2879 u32 temp;
2880
09153000
DV		 2881 mutex_lock(&dev_priv->dpio_lock);
2882
e615efe4
ED		 2883 /* It is necessary to ungate the pixclk gate prior to programming
2884 * the divisors, and gate it back when it is done.
2885 */
2886 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2887
2888 /* Disable SSCCTL */
2889 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2890 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2891 SBI_SSCCTL_DISABLE,
2892 SBI_ICLK);
e615efe4
ED		 2893
2894 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2895 if (crtc->mode.clock == 20000) {
2896 auxdiv = 1;
2897 divsel = 0x41;
2898 phaseinc = 0x20;
2899 } else {
2900 /* The iCLK virtual clock root frequency is in MHz,
2901 * but the crtc->mode.clock in in KHz. To get the divisors,
2902 * it is necessary to divide one by another, so we
2903 * convert the virtual clock precision to KHz here for higher
2904 * precision.
2905 */
2906 u32 iclk_virtual_root_freq = 172800 * 1000;
2907 u32 iclk_pi_range = 64;
2908 u32 desired_divisor, msb_divisor_value, pi_value;
2909
2910 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2911 msb_divisor_value = desired_divisor / iclk_pi_range;
2912 pi_value = desired_divisor % iclk_pi_range;
2913
2914 auxdiv = 0;
2915 divsel = msb_divisor_value - 2;
2916 phaseinc = pi_value;
2917 }
2918
2919 /* This should not happen with any sane values */
2920 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2921 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2922 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2923 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2924
2925 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2926 crtc->mode.clock,
2927 auxdiv,
2928 divsel,
2929 phasedir,
2930 phaseinc);
2931
2932 /* Program SSCDIVINTPHASE6 */
988d6ee8 2933 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 2934 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2935 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2936 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2937 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2938 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2939 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 2940 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 2941
2942 /* Program SSCAUXDIV */
988d6ee8 2943 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 2944 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2945 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 2946 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 2947
2948 /* Enable modulator and associated divider */
988d6ee8 2949 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 2950 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 2951 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 2952
2953 /* Wait for initialization time */
2954 udelay(24);
2955
2956 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 2957
2958 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 2959}
2960
275f01b2
DV		 2961static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2962 enum pipe pch_transcoder)
2963{
2964 struct drm_device *dev = crtc->base.dev;
2965 struct drm_i915_private *dev_priv = dev->dev_private;
2966 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2967
2968 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2969 I915_READ(HTOTAL(cpu_transcoder)));
2970 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2971 I915_READ(HBLANK(cpu_transcoder)));
2972 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2973 I915_READ(HSYNC(cpu_transcoder)));
2974
2975 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2976 I915_READ(VTOTAL(cpu_transcoder)));
2977 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2978 I915_READ(VBLANK(cpu_transcoder)));
2979 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2980 I915_READ(VSYNC(cpu_transcoder)));
2981 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2982 I915_READ(VSYNCSHIFT(cpu_transcoder)));
2983}
2984
f67a559d
JB		 2985/*
2986 * Enable PCH resources required for PCH ports:
2987 * - PCH PLLs
2988 * - FDI training & RX/TX
2989 * - update transcoder timings
2990 * - DP transcoding bits
2991 * - transcoder
2992 */
2993static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2994{
2995 struct drm_device *dev = crtc->dev;
2996 struct drm_i915_private *dev_priv = dev->dev_private;
2997 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2998 int pipe = intel_crtc->pipe;
ee7b9f93 2999 u32 reg, temp;
2c07245f 3000
ab9412ba 3001 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 3002
cd986abb
DV		 3003 /* Write the TU size bits before fdi link training, so that error
3004 * detection works. */
3005 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3006 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3007
c98e9dcf 3008 /* For PCH output, training FDI link */
674cf967 3009 dev_priv->display.fdi_link_train(crtc);
2c07245f 3010
3ad8a208
DV		 3011 /* We need to program the right clock selection before writing the pixel
3012 * mutliplier into the DPLL. */
303b81e0 3013 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3014 u32 sel;
4b645f14 3015
c98e9dcf 3016 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 3017 temp |= TRANS_DPLL_ENABLE(pipe);
3018 sel = TRANS_DPLLB_SEL(pipe);
a43f6e0f 3019 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 3020 temp |= sel;
3021 else
3022 temp &= ~sel;
c98e9dcf 3023 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3024 }
5eddb70b 3025
3ad8a208
DV		 3026 /* XXX: pch pll's can be enabled any time before we enable the PCH
3027 * transcoder, and we actually should do this to not upset any PCH
3028 * transcoder that already use the clock when we share it.
3029 *
3030 * Note that enable_shared_dpll tries to do the right thing, but
3031 * get_shared_dpll unconditionally resets the pll - we need that to have
3032 * the right LVDS enable sequence. */
3033 ironlake_enable_shared_dpll(intel_crtc);
3034
d9b6cb56
JB		 3035 /* set transcoder timing, panel must allow it */
3036 assert_panel_unlocked(dev_priv, pipe);
275f01b2 3037 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 3038
303b81e0 3039 intel_fdi_normal_train(crtc);
5e84e1a4 3040
c98e9dcf
JB		 3041 /* For PCH DP, enable TRANS_DP_CTL */
3042 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3043 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3044 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3045 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3046 reg = TRANS_DP_CTL(pipe);
3047 temp = I915_READ(reg);
3048 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3049 TRANS_DP_SYNC_MASK |
3050 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3051 temp |= (TRANS_DP_OUTPUT_ENABLE |
3052 TRANS_DP_ENH_FRAMING);
9325c9f0 3053 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3054
3055 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3056 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3057 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3058 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3059
3060 switch (intel_trans_dp_port_sel(crtc)) {
3061 case PCH_DP_B:
5eddb70b 3062 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3063 break;
3064 case PCH_DP_C:
5eddb70b 3065 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3066 break;
3067 case PCH_DP_D:
5eddb70b 3068 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3069 break;
3070 default:
e95d41e1 3071 BUG();
32f9d658 3072 }
2c07245f 3073
5eddb70b 3074 I915_WRITE(reg, temp);
6be4a607 3075 }
b52eb4dc 3076
b8a4f404 3077 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3078}
3079
1507e5bd
PZ		 3080static void lpt_pch_enable(struct drm_crtc *crtc)
3081{
3082 struct drm_device *dev = crtc->dev;
3083 struct drm_i915_private *dev_priv = dev->dev_private;
3084 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3085 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3086
ab9412ba 3087 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3088
8c52b5e8 3089 lpt_program_iclkip(crtc);
1507e5bd 3090
0540e488 3091 /* Set transcoder timing. */
275f01b2 3092 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 3093
937bb610 3094 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3095}
3096
e2b78267 3097static void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3098{
e2b78267 3099 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 3100
3101 if (pll == NULL)
3102 return;
3103
3104 if (pll->refcount == 0) {
46edb027 3105 WARN(1, "bad %s refcount\n", pll->name);
ee7b9f93
JB		 3106 return;
3107 }
3108
f4a091c7
DV		 3109 if (--pll->refcount == 0) {
3110 WARN_ON(pll->on);
3111 WARN_ON(pll->active);
3112 }
3113
a43f6e0f 3114 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 3115}
3116
b89a1d39 3117static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3118{
e2b78267
DV		 3119 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3120 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3121 enum intel_dpll_id i;
ee7b9f93 3122
ee7b9f93 3123 if (pll) {
46edb027
DV		 3124 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3125 crtc->base.base.id, pll->name);
e2b78267 3126 intel_put_shared_dpll(crtc);
ee7b9f93
JB		 3127 }
3128
98b6bd99
DV		 3129 if (HAS_PCH_IBX(dev_priv->dev)) {
3130 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 3131 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 3132 pll = &dev_priv->shared_dplls[i];
98b6bd99 3133
46edb027
DV		 3134 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3135 crtc->base.base.id, pll->name);
98b6bd99
DV		 3136
3137 goto found;
3138 }
3139
e72f9fbf
DV		 3140 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3141 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 3142
3143 /* Only want to check enabled timings first */
3144 if (pll->refcount == 0)
3145 continue;
3146
b89a1d39
DV		 3147 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3148 sizeof(pll->hw_state)) == 0) {
46edb027 3149 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
e2b78267 3150 crtc->base.base.id,
46edb027 3151 pll->name, pll->refcount, pll->active);
ee7b9f93
JB		 3152
3153 goto found;
3154 }
3155 }
3156
3157 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 3158 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3159 pll = &dev_priv->shared_dplls[i];
ee7b9f93 3160 if (pll->refcount == 0) {
46edb027
DV		 3161 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3162 crtc->base.base.id, pll->name);
ee7b9f93
JB		 3163 goto found;
3164 }
3165 }
3166
3167 return NULL;
3168
3169found:
a43f6e0f 3170 crtc->config.shared_dpll = i;
46edb027
DV		 3171 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3172 pipe_name(crtc->pipe));
ee7b9f93 3173
cdbd2316 3174 if (pll->active == 0) {
66e985c0
DV		 3175 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3176 sizeof(pll->hw_state));
3177
46edb027 3178 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
cdbd2316 3179 WARN_ON(pll->on);
e9d6944e 3180 assert_shared_dpll_disabled(dev_priv, pll);
ee7b9f93 3181
15bdd4cf 3182 pll->mode_set(dev_priv, pll);
cdbd2316
DV		 3183 }
3184 pll->refcount++;
e04c7350 3185
ee7b9f93
JB		 3186 return pll;
3187}
3188
a1520318 3189static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 3190{
3191 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3192 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3193 u32 temp;
3194
3195 temp = I915_READ(dslreg);
3196 udelay(500);
3197 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3198 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3199 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3200 }
3201}
3202
b074cec8
JB		 3203static void ironlake_pfit_enable(struct intel_crtc *crtc)
3204{
3205 struct drm_device *dev = crtc->base.dev;
3206 struct drm_i915_private *dev_priv = dev->dev_private;
3207 int pipe = crtc->pipe;
3208
0ef37f3f 3209 if (crtc->config.pch_pfit.size) {
b074cec8
JB		 3210 /* Force use of hard-coded filter coefficients
3211 * as some pre-programmed values are broken,
3212 * e.g. x201.
3213 */
3214 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3215 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3216 PF_PIPE_SEL_IVB(pipe));
3217 else
3218 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3219 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3220 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
d4270e57
JB		 3221 }
3222}
3223
bb53d4ae
VS		 3224static void intel_enable_planes(struct drm_crtc *crtc)
3225{
3226 struct drm_device *dev = crtc->dev;
3227 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3228 struct intel_plane *intel_plane;
3229
3230 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3231 if (intel_plane->pipe == pipe)
3232 intel_plane_restore(&intel_plane->base);
3233}
3234
3235static void intel_disable_planes(struct drm_crtc *crtc)
3236{
3237 struct drm_device *dev = crtc->dev;
3238 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3239 struct intel_plane *intel_plane;
3240
3241 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3242 if (intel_plane->pipe == pipe)
3243 intel_plane_disable(&intel_plane->base);
3244}
3245
f67a559d
JB		 3246static void ironlake_crtc_enable(struct drm_crtc *crtc)
3247{
3248 struct drm_device *dev = crtc->dev;
3249 struct drm_i915_private *dev_priv = dev->dev_private;
3250 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3251 struct intel_encoder *encoder;
f67a559d
JB		 3252 int pipe = intel_crtc->pipe;
3253 int plane = intel_crtc->plane;
f67a559d 3254
08a48469
DV		 3255 WARN_ON(!crtc->enabled);
3256
f67a559d
JB		 3257 if (intel_crtc->active)
3258 return;
3259
3260 intel_crtc->active = true;
8664281b
PZ		 3261
3262 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3263 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3264
f6736a1a 3265 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 3266 if (encoder->pre_enable)
3267 encoder->pre_enable(encoder);
f67a559d 3268
5bfe2ac0 3269 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3270 /* Note: FDI PLL enabling _must_ be done before we enable the
3271 * cpu pipes, hence this is separate from all the other fdi/pch
3272 * enabling. */
88cefb6c 3273 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3274 } else {
3275 assert_fdi_tx_disabled(dev_priv, pipe);
3276 assert_fdi_rx_disabled(dev_priv, pipe);
3277 }
f67a559d 3278
b074cec8 3279 ironlake_pfit_enable(intel_crtc);
f67a559d 3280
9c54c0dd
JB		 3281 /*
3282 * On ILK+ LUT must be loaded before the pipe is running but with
3283 * clocks enabled
3284 */
3285 intel_crtc_load_lut(crtc);
3286
f37fcc2a 3287 intel_update_watermarks(crtc);
5bfe2ac0 3288 intel_enable_pipe(dev_priv, pipe,
23538ef1 3289 intel_crtc->config.has_pch_encoder, false);
f67a559d 3290 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3291 intel_enable_planes(crtc);
5c38d48c 3292 intel_crtc_update_cursor(crtc, true);
f67a559d 3293
5bfe2ac0 3294 if (intel_crtc->config.has_pch_encoder)
f67a559d 3295 ironlake_pch_enable(crtc);
c98e9dcf 3296
d1ebd816 3297 mutex_lock(&dev->struct_mutex);
bed4a673 3298 intel_update_fbc(dev);
d1ebd816
BW		 3299 mutex_unlock(&dev->struct_mutex);
3300
fa5c73b1
DV		 3301 for_each_encoder_on_crtc(dev, crtc, encoder)
3302 encoder->enable(encoder);
61b77ddd
DV		 3303
3304 if (HAS_PCH_CPT(dev))
a1520318 3305 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3306
3307 /*
3308 * There seems to be a race in PCH platform hw (at least on some
3309 * outputs) where an enabled pipe still completes any pageflip right
3310 * away (as if the pipe is off) instead of waiting for vblank. As soon
3311 * as the first vblank happend, everything works as expected. Hence just
3312 * wait for one vblank before returning to avoid strange things
3313 * happening.
3314 */
3315 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3316}
3317
42db64ef
PZ		 3318/* IPS only exists on ULT machines and is tied to pipe A. */
3319static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3320{
f5adf94e 3321 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 3322}
3323
3324static void hsw_enable_ips(struct intel_crtc *crtc)
3325{
3326 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3327
3328 if (!crtc->config.ips_enabled)
3329 return;
3330
3331 /* We can only enable IPS after we enable a plane and wait for a vblank.
3332 * We guarantee that the plane is enabled by calling intel_enable_ips
3333 * only after intel_enable_plane. And intel_enable_plane already waits
3334 * for a vblank, so all we need to do here is to enable the IPS bit. */
3335 assert_plane_enabled(dev_priv, crtc->plane);
3336 I915_WRITE(IPS_CTL, IPS_ENABLE);
3337}
3338
3339static void hsw_disable_ips(struct intel_crtc *crtc)
3340{
3341 struct drm_device *dev = crtc->base.dev;
3342 struct drm_i915_private *dev_priv = dev->dev_private;
3343
3344 if (!crtc->config.ips_enabled)
3345 return;
3346
3347 assert_plane_enabled(dev_priv, crtc->plane);
3348 I915_WRITE(IPS_CTL, 0);
3349
3350 /* We need to wait for a vblank before we can disable the plane. */
3351 intel_wait_for_vblank(dev, crtc->pipe);
3352}
3353
4f771f10
PZ		 3354static void haswell_crtc_enable(struct drm_crtc *crtc)
3355{
3356 struct drm_device *dev = crtc->dev;
3357 struct drm_i915_private *dev_priv = dev->dev_private;
3358 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3359 struct intel_encoder *encoder;
3360 int pipe = intel_crtc->pipe;
3361 int plane = intel_crtc->plane;
4f771f10
PZ		 3362
3363 WARN_ON(!crtc->enabled);
3364
3365 if (intel_crtc->active)
3366 return;
3367
3368 intel_crtc->active = true;
8664281b
PZ		 3369
3370 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3371 if (intel_crtc->config.has_pch_encoder)
3372 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3373
5bfe2ac0 3374 if (intel_crtc->config.has_pch_encoder)
04945641 3375 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3376
3377 for_each_encoder_on_crtc(dev, crtc, encoder)
3378 if (encoder->pre_enable)
3379 encoder->pre_enable(encoder);
3380
1f544388 3381 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3382
b074cec8 3383 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 3384
3385 /*
3386 * On ILK+ LUT must be loaded before the pipe is running but with
3387 * clocks enabled
3388 */
3389 intel_crtc_load_lut(crtc);
3390
1f544388 3391 intel_ddi_set_pipe_settings(crtc);
8228c251 3392 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3393
f37fcc2a 3394 intel_update_watermarks(crtc);
5bfe2ac0 3395 intel_enable_pipe(dev_priv, pipe,
23538ef1 3396 intel_crtc->config.has_pch_encoder, false);
4f771f10 3397 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3398 intel_enable_planes(crtc);
5c38d48c 3399 intel_crtc_update_cursor(crtc, true);
4f771f10 3400
42db64ef
PZ		 3401 hsw_enable_ips(intel_crtc);
3402
5bfe2ac0 3403 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3404 lpt_pch_enable(crtc);
4f771f10
PZ		 3405
3406 mutex_lock(&dev->struct_mutex);
3407 intel_update_fbc(dev);
3408 mutex_unlock(&dev->struct_mutex);
3409
8807e55b 3410 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 3411 encoder->enable(encoder);
8807e55b
JN		 3412 intel_opregion_notify_encoder(encoder, true);
3413 }
4f771f10 3414
4f771f10
PZ		 3415 /*
3416 * There seems to be a race in PCH platform hw (at least on some
3417 * outputs) where an enabled pipe still completes any pageflip right
3418 * away (as if the pipe is off) instead of waiting for vblank. As soon
3419 * as the first vblank happend, everything works as expected. Hence just
3420 * wait for one vblank before returning to avoid strange things
3421 * happening.
3422 */
3423 intel_wait_for_vblank(dev, intel_crtc->pipe);
3424}
3425
3f8dce3a
DV		 3426static void ironlake_pfit_disable(struct intel_crtc *crtc)
3427{
3428 struct drm_device *dev = crtc->base.dev;
3429 struct drm_i915_private *dev_priv = dev->dev_private;
3430 int pipe = crtc->pipe;
3431
3432 /* To avoid upsetting the power well on haswell only disable the pfit if
3433 * it's in use. The hw state code will make sure we get this right. */
3434 if (crtc->config.pch_pfit.size) {
3435 I915_WRITE(PF_CTL(pipe), 0);
3436 I915_WRITE(PF_WIN_POS(pipe), 0);
3437 I915_WRITE(PF_WIN_SZ(pipe), 0);
3438 }
3439}
3440
6be4a607
JB		 3441static void ironlake_crtc_disable(struct drm_crtc *crtc)
3442{
3443 struct drm_device *dev = crtc->dev;
3444 struct drm_i915_private *dev_priv = dev->dev_private;
3445 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3446 struct intel_encoder *encoder;
6be4a607
JB		 3447 int pipe = intel_crtc->pipe;
3448 int plane = intel_crtc->plane;
5eddb70b 3449 u32 reg, temp;
b52eb4dc 3450
ef9c3aee 3451
f7abfe8b
CW		 3452 if (!intel_crtc->active)
3453 return;
3454
ea9d758d
DV		 3455 for_each_encoder_on_crtc(dev, crtc, encoder)
3456 encoder->disable(encoder);
3457
e6c3a2a6 3458 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3459 drm_vblank_off(dev, pipe);
913d8d11 3460
5c3fe8b0 3461 if (dev_priv->fbc.plane == plane)
973d04f9 3462 intel_disable_fbc(dev);
2c07245f 3463
0d5b8c61 3464 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3465 intel_disable_planes(crtc);
0d5b8c61
VS		 3466 intel_disable_plane(dev_priv, plane, pipe);
3467
d925c59a
DV		 3468 if (intel_crtc->config.has_pch_encoder)
3469 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3470
b24e7179 3471 intel_disable_pipe(dev_priv, pipe);
32f9d658 3472
3f8dce3a 3473 ironlake_pfit_disable(intel_crtc);
2c07245f 3474
bf49ec8c
DV		 3475 for_each_encoder_on_crtc(dev, crtc, encoder)
3476 if (encoder->post_disable)
3477 encoder->post_disable(encoder);
2c07245f 3478
d925c59a
DV		 3479 if (intel_crtc->config.has_pch_encoder) {
3480 ironlake_fdi_disable(crtc);
913d8d11 3481
d925c59a
DV		 3482 ironlake_disable_pch_transcoder(dev_priv, pipe);
3483 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
6be4a607 3484
d925c59a
DV		 3485 if (HAS_PCH_CPT(dev)) {
3486 /* disable TRANS_DP_CTL */
3487 reg = TRANS_DP_CTL(pipe);
3488 temp = I915_READ(reg);
3489 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3490 TRANS_DP_PORT_SEL_MASK);
3491 temp |= TRANS_DP_PORT_SEL_NONE;
3492 I915_WRITE(reg, temp);
3493
3494 /* disable DPLL_SEL */
3495 temp = I915_READ(PCH_DPLL_SEL);
11887397 3496 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 3497 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 3498 }
e3421a18 3499
d925c59a 3500 /* disable PCH DPLL */
e72f9fbf 3501 intel_disable_shared_dpll(intel_crtc);
8db9d77b 3502
d925c59a
DV		 3503 ironlake_fdi_pll_disable(intel_crtc);
3504 }
6b383a7f 3505
f7abfe8b 3506 intel_crtc->active = false;
46ba614c 3507 intel_update_watermarks(crtc);
d1ebd816
BW		 3508
3509 mutex_lock(&dev->struct_mutex);
6b383a7f 3510 intel_update_fbc(dev);
d1ebd816 3511 mutex_unlock(&dev->struct_mutex);
6be4a607 3512}
1b3c7a47 3513
4f771f10 3514static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3515{
4f771f10
PZ		 3516 struct drm_device *dev = crtc->dev;
3517 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3518 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3519 struct intel_encoder *encoder;
3520 int pipe = intel_crtc->pipe;
3521 int plane = intel_crtc->plane;
3b117c8f 3522 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3523
4f771f10
PZ		 3524 if (!intel_crtc->active)
3525 return;
3526
8807e55b
JN		 3527 for_each_encoder_on_crtc(dev, crtc, encoder) {
3528 intel_opregion_notify_encoder(encoder, false);
4f771f10 3529 encoder->disable(encoder);
8807e55b 3530 }
4f771f10
PZ		 3531
3532 intel_crtc_wait_for_pending_flips(crtc);
3533 drm_vblank_off(dev, pipe);
4f771f10 3534
891348b2 3535 /* FBC must be disabled before disabling the plane on HSW. */
5c3fe8b0 3536 if (dev_priv->fbc.plane == plane)
4f771f10
PZ		 3537 intel_disable_fbc(dev);
3538
42db64ef
PZ		 3539 hsw_disable_ips(intel_crtc);
3540
0d5b8c61 3541 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3542 intel_disable_planes(crtc);
891348b2
RV		 3543 intel_disable_plane(dev_priv, plane, pipe);
3544
8664281b
PZ		 3545 if (intel_crtc->config.has_pch_encoder)
3546 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ		 3547 intel_disable_pipe(dev_priv, pipe);
3548
ad80a810 3549 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3550
3f8dce3a 3551 ironlake_pfit_disable(intel_crtc);
4f771f10 3552
1f544388 3553 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3554
3555 for_each_encoder_on_crtc(dev, crtc, encoder)
3556 if (encoder->post_disable)
3557 encoder->post_disable(encoder);
3558
88adfff1 3559 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3560 lpt_disable_pch_transcoder(dev_priv);
8664281b 3561 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3562 intel_ddi_fdi_disable(crtc);
83616634 3563 }
4f771f10
PZ		 3564
3565 intel_crtc->active = false;
46ba614c 3566 intel_update_watermarks(crtc);
4f771f10
PZ		 3567
3568 mutex_lock(&dev->struct_mutex);
3569 intel_update_fbc(dev);
3570 mutex_unlock(&dev->struct_mutex);
3571}
3572
ee7b9f93
JB		 3573static void ironlake_crtc_off(struct drm_crtc *crtc)
3574{
3575 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 3576 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 3577}
3578
6441ab5f
PZ		 3579static void haswell_crtc_off(struct drm_crtc *crtc)
3580{
3581 intel_ddi_put_crtc_pll(crtc);
3582}
3583
02e792fb
DV		 3584static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3585{
02e792fb 3586 if (!enable && intel_crtc->overlay) {
23f09ce3 3587 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3588 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3589
23f09ce3 3590 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3591 dev_priv->mm.interruptible = false;
3592 (void) intel_overlay_switch_off(intel_crtc->overlay);
3593 dev_priv->mm.interruptible = true;
23f09ce3 3594 mutex_unlock(&dev->struct_mutex);
02e792fb 3595 }
02e792fb 3596
5dcdbcb0
CW		 3597 /* Let userspace switch the overlay on again. In most cases userspace
3598 * has to recompute where to put it anyway.
3599 */
02e792fb
DV		 3600}
3601
61bc95c1
EE		 3602/**
3603 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3604 * cursor plane briefly if not already running after enabling the display
3605 * plane.
3606 * This workaround avoids occasional blank screens when self refresh is
3607 * enabled.
3608 */
3609static void
3610g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3611{
3612 u32 cntl = I915_READ(CURCNTR(pipe));
3613
3614 if ((cntl & CURSOR_MODE) == 0) {
3615 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3616
3617 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3618 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3619 intel_wait_for_vblank(dev_priv->dev, pipe);
3620 I915_WRITE(CURCNTR(pipe), cntl);
3621 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3622 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3623 }
3624}
3625
2dd24552
JB		 3626static void i9xx_pfit_enable(struct intel_crtc *crtc)
3627{
3628 struct drm_device *dev = crtc->base.dev;
3629 struct drm_i915_private *dev_priv = dev->dev_private;
3630 struct intel_crtc_config *pipe_config = &crtc->config;
3631
328d8e82 3632 if (!crtc->config.gmch_pfit.control)
2dd24552
JB		 3633 return;
3634
2dd24552 3635 /*
c0b03411
DV		 3636 * The panel fitter should only be adjusted whilst the pipe is disabled,
3637 * according to register description and PRM.
2dd24552 3638 */
c0b03411
DV		 3639 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3640 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 3641
b074cec8
JB		 3642 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3643 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 3644
3645 /* Border color in case we don't scale up to the full screen. Black by
3646 * default, change to something else for debugging. */
3647 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 3648}
3649
89b667f8
JB		 3650static void valleyview_crtc_enable(struct drm_crtc *crtc)
3651{
3652 struct drm_device *dev = crtc->dev;
3653 struct drm_i915_private *dev_priv = dev->dev_private;
3654 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3655 struct intel_encoder *encoder;
3656 int pipe = intel_crtc->pipe;
3657 int plane = intel_crtc->plane;
23538ef1 3658 bool is_dsi;
89b667f8
JB		 3659
3660 WARN_ON(!crtc->enabled);
3661
3662 if (intel_crtc->active)
3663 return;
3664
3665 intel_crtc->active = true;
89b667f8 3666
89b667f8
JB		 3667 for_each_encoder_on_crtc(dev, crtc, encoder)
3668 if (encoder->pre_pll_enable)
3669 encoder->pre_pll_enable(encoder);
3670
23538ef1
JN		 3671 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
3672
e9fd1c02
JN		 3673 if (!is_dsi)
3674 vlv_enable_pll(intel_crtc);
89b667f8
JB		 3675
3676 for_each_encoder_on_crtc(dev, crtc, encoder)
3677 if (encoder->pre_enable)
3678 encoder->pre_enable(encoder);
3679
2dd24552
JB		 3680 i9xx_pfit_enable(intel_crtc);
3681
63cbb074
VS		 3682 intel_crtc_load_lut(crtc);
3683
f37fcc2a 3684 intel_update_watermarks(crtc);
23538ef1 3685 intel_enable_pipe(dev_priv, pipe, false, is_dsi);
89b667f8 3686 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3687 intel_enable_planes(crtc);
5c38d48c 3688 intel_crtc_update_cursor(crtc, true);
89b667f8 3689
89b667f8 3690 intel_update_fbc(dev);
5004945f
JN		 3691
3692 for_each_encoder_on_crtc(dev, crtc, encoder)
3693 encoder->enable(encoder);
89b667f8
JB		 3694}
3695
0b8765c6 3696static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3697{
3698 struct drm_device *dev = crtc->dev;
79e53945
JB		 3699 struct drm_i915_private *dev_priv = dev->dev_private;
3700 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3701 struct intel_encoder *encoder;
79e53945 3702 int pipe = intel_crtc->pipe;
80824003 3703 int plane = intel_crtc->plane;
79e53945 3704
08a48469
DV		 3705 WARN_ON(!crtc->enabled);
3706
f7abfe8b
CW		 3707 if (intel_crtc->active)
3708 return;
3709
3710 intel_crtc->active = true;
6b383a7f 3711
9d6d9f19
MK		 3712 for_each_encoder_on_crtc(dev, crtc, encoder)
3713 if (encoder->pre_enable)
3714 encoder->pre_enable(encoder);
3715
f6736a1a
DV		 3716 i9xx_enable_pll(intel_crtc);
3717
2dd24552
JB		 3718 i9xx_pfit_enable(intel_crtc);
3719
63cbb074
VS		 3720 intel_crtc_load_lut(crtc);
3721
f37fcc2a 3722 intel_update_watermarks(crtc);
23538ef1 3723 intel_enable_pipe(dev_priv, pipe, false, false);
b24e7179 3724 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3725 intel_enable_planes(crtc);
22e407d7 3726 /* The fixup needs to happen before cursor is enabled */
61bc95c1
EE		 3727 if (IS_G4X(dev))
3728 g4x_fixup_plane(dev_priv, pipe);
22e407d7 3729 intel_crtc_update_cursor(crtc, true);
79e53945 3730
0b8765c6
JB		 3731 /* Give the overlay scaler a chance to enable if it's on this pipe */
3732 intel_crtc_dpms_overlay(intel_crtc, true);
ef9c3aee 3733
f440eb13 3734 intel_update_fbc(dev);
ef9c3aee 3735
fa5c73b1
DV		 3736 for_each_encoder_on_crtc(dev, crtc, encoder)
3737 encoder->enable(encoder);
0b8765c6 3738}
79e53945 3739
87476d63
DV		 3740static void i9xx_pfit_disable(struct intel_crtc *crtc)
3741{
3742 struct drm_device *dev = crtc->base.dev;
3743 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 3744
328d8e82
DV		 3745 if (!crtc->config.gmch_pfit.control)
3746 return;
87476d63 3747
328d8e82 3748 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 3749
328d8e82
DV		 3750 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3751 I915_READ(PFIT_CONTROL));
3752 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 3753}
3754
0b8765c6
JB		 3755static void i9xx_crtc_disable(struct drm_crtc *crtc)
3756{
3757 struct drm_device *dev = crtc->dev;
3758 struct drm_i915_private *dev_priv = dev->dev_private;
3759 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3760 struct intel_encoder *encoder;
0b8765c6
JB		 3761 int pipe = intel_crtc->pipe;
3762 int plane = intel_crtc->plane;
ef9c3aee 3763
f7abfe8b
CW		 3764 if (!intel_crtc->active)
3765 return;
3766
ea9d758d
DV		 3767 for_each_encoder_on_crtc(dev, crtc, encoder)
3768 encoder->disable(encoder);
3769
0b8765c6 3770 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3771 intel_crtc_wait_for_pending_flips(crtc);
3772 drm_vblank_off(dev, pipe);
0b8765c6 3773
5c3fe8b0 3774 if (dev_priv->fbc.plane == plane)
973d04f9 3775 intel_disable_fbc(dev);
79e53945 3776
0d5b8c61
VS		 3777 intel_crtc_dpms_overlay(intel_crtc, false);
3778 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3779 intel_disable_planes(crtc);
b24e7179 3780 intel_disable_plane(dev_priv, plane, pipe);
0d5b8c61 3781
b24e7179 3782 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3783
87476d63 3784 i9xx_pfit_disable(intel_crtc);
24a1f16d 3785
89b667f8
JB		 3786 for_each_encoder_on_crtc(dev, crtc, encoder)
3787 if (encoder->post_disable)
3788 encoder->post_disable(encoder);
3789
e9fd1c02
JN		 3790 if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3791 i9xx_disable_pll(dev_priv, pipe);
0b8765c6 3792
f7abfe8b 3793 intel_crtc->active = false;
46ba614c 3794 intel_update_watermarks(crtc);
f37fcc2a
VS		 3795
3796 intel_update_fbc(dev);
0b8765c6
JB		 3797}
3798
ee7b9f93
JB		 3799static void i9xx_crtc_off(struct drm_crtc *crtc)
3800{
3801}
3802
976f8a20
DV		 3803static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3804 bool enabled)
2c07245f
ZW		 3805{
3806 struct drm_device *dev = crtc->dev;
3807 struct drm_i915_master_private *master_priv;
3808 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3809 int pipe = intel_crtc->pipe;
79e53945
JB		 3810
3811 if (!dev->primary->master)
3812 return;
3813
3814 master_priv = dev->primary->master->driver_priv;
3815 if (!master_priv->sarea_priv)
3816 return;
3817
79e53945
JB		 3818 switch (pipe) {
3819 case 0:
3820 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3821 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3822 break;
3823 case 1:
3824 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3825 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3826 break;
3827 default:
9db4a9c7 3828 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3829 break;
3830 }
79e53945
JB		 3831}
3832
976f8a20
DV		 3833/**
3834 * Sets the power management mode of the pipe and plane.
3835 */
3836void intel_crtc_update_dpms(struct drm_crtc *crtc)
3837{
3838 struct drm_device *dev = crtc->dev;
3839 struct drm_i915_private *dev_priv = dev->dev_private;
3840 struct intel_encoder *intel_encoder;
3841 bool enable = false;
3842
3843 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3844 enable |= intel_encoder->connectors_active;
3845
3846 if (enable)
3847 dev_priv->display.crtc_enable(crtc);
3848 else
3849 dev_priv->display.crtc_disable(crtc);
3850
3851 intel_crtc_update_sarea(crtc, enable);
3852}
3853
cdd59983
CW		 3854static void intel_crtc_disable(struct drm_crtc *crtc)
3855{
cdd59983 3856 struct drm_device *dev = crtc->dev;
976f8a20 3857 struct drm_connector *connector;
ee7b9f93 3858 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3859 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3860
976f8a20
DV		 3861 /* crtc should still be enabled when we disable it. */
3862 WARN_ON(!crtc->enabled);
3863
3864 dev_priv->display.crtc_disable(crtc);
c77bf565 3865 intel_crtc->eld_vld = false;
976f8a20 3866 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3867 dev_priv->display.off(crtc);
3868
931872fc
CW		 3869 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3870 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3871
3872 if (crtc->fb) {
3873 mutex_lock(&dev->struct_mutex);
1690e1eb 3874 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3875 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3876 crtc->fb = NULL;
3877 }
3878
3879 /* Update computed state. */
3880 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3881 if (!connector->encoder || !connector->encoder->crtc)
3882 continue;
3883
3884 if (connector->encoder->crtc != crtc)
3885 continue;
3886
3887 connector->dpms = DRM_MODE_DPMS_OFF;
3888 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3889 }
3890}
3891
ea5b213a 3892void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3893{
4ef69c7a 3894 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3895
ea5b213a
CW		 3896 drm_encoder_cleanup(encoder);
3897 kfree(intel_encoder);
7e7d76c3
JB		 3898}
3899
9237329d 3900/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
DV		 3901 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3902 * state of the entire output pipe. */
9237329d 3903static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3904{
5ab432ef
DV		 3905 if (mode == DRM_MODE_DPMS_ON) {
3906 encoder->connectors_active = true;
3907
b2cabb0e 3908 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3909 } else {
3910 encoder->connectors_active = false;
3911
b2cabb0e 3912 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3913 }
79e53945
JB		 3914}
3915
0a91ca29
DV		 3916/* Cross check the actual hw state with our own modeset state tracking (and it's
3917 * internal consistency). */
b980514c 3918static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3919{
0a91ca29
DV		 3920 if (connector->get_hw_state(connector)) {
3921 struct intel_encoder *encoder = connector->encoder;
3922 struct drm_crtc *crtc;
3923 bool encoder_enabled;
3924 enum pipe pipe;
3925
3926 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3927 connector->base.base.id,
3928 drm_get_connector_name(&connector->base));
3929
3930 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3931 "wrong connector dpms state\n");
3932 WARN(connector->base.encoder != &encoder->base,
3933 "active connector not linked to encoder\n");
3934 WARN(!encoder->connectors_active,
3935 "encoder->connectors_active not set\n");
3936
3937 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3938 WARN(!encoder_enabled, "encoder not enabled\n");
3939 if (WARN_ON(!encoder->base.crtc))
3940 return;
3941
3942 crtc = encoder->base.crtc;
3943
3944 WARN(!crtc->enabled, "crtc not enabled\n");
3945 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3946 WARN(pipe != to_intel_crtc(crtc)->pipe,
3947 "encoder active on the wrong pipe\n");
3948 }
79e53945
JB		 3949}
3950
5ab432ef
DV		 3951/* Even simpler default implementation, if there's really no special case to
3952 * consider. */
3953void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3954{
5ab432ef 3955 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3956
5ab432ef
DV		 3957 /* All the simple cases only support two dpms states. */
3958 if (mode != DRM_MODE_DPMS_ON)
3959 mode = DRM_MODE_DPMS_OFF;
d4270e57 3960
5ab432ef
DV		 3961 if (mode == connector->dpms)
3962 return;
3963
3964 connector->dpms = mode;
3965
3966 /* Only need to change hw state when actually enabled */
3967 if (encoder->base.crtc)
3968 intel_encoder_dpms(encoder, mode);
3969 else
8af6cf88 3970 WARN_ON(encoder->connectors_active != false);
0a91ca29 3971
b980514c 3972 intel_modeset_check_state(connector->dev);
79e53945
JB		 3973}
3974
f0947c37
DV		 3975/* Simple connector->get_hw_state implementation for encoders that support only
3976 * one connector and no cloning and hence the encoder state determines the state
3977 * of the connector. */
3978bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3979{
24929352 3980 enum pipe pipe = 0;
f0947c37 3981 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3982
f0947c37 3983 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3984}
3985
1857e1da
DV		 3986static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3987 struct intel_crtc_config *pipe_config)
3988{
3989 struct drm_i915_private *dev_priv = dev->dev_private;
3990 struct intel_crtc *pipe_B_crtc =
3991 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3992
3993 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3994 pipe_name(pipe), pipe_config->fdi_lanes);
3995 if (pipe_config->fdi_lanes > 4) {
3996 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3997 pipe_name(pipe), pipe_config->fdi_lanes);
3998 return false;
3999 }
4000
4001 if (IS_HASWELL(dev)) {
4002 if (pipe_config->fdi_lanes > 2) {
4003 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4004 pipe_config->fdi_lanes);
4005 return false;
4006 } else {
4007 return true;
4008 }
4009 }
4010
4011 if (INTEL_INFO(dev)->num_pipes == 2)
4012 return true;
4013
4014 /* Ivybridge 3 pipe is really complicated */
4015 switch (pipe) {
4016 case PIPE_A:
4017 return true;
4018 case PIPE_B:
4019 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4020 pipe_config->fdi_lanes > 2) {
4021 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4022 pipe_name(pipe), pipe_config->fdi_lanes);
4023 return false;
4024 }
4025 return true;
4026 case PIPE_C:
1e833f40 4027 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
1857e1da
DV		 4028 pipe_B_crtc->config.fdi_lanes <= 2) {
4029 if (pipe_config->fdi_lanes > 2) {
4030 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4031 pipe_name(pipe), pipe_config->fdi_lanes);
4032 return false;
4033 }
4034 } else {
4035 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4036 return false;
4037 }
4038 return true;
4039 default:
4040 BUG();
4041 }
4042}
4043
e29c22c0
DV		 4044#define RETRY 1
4045static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4046 struct intel_crtc_config *pipe_config)
877d48d5 4047{
1857e1da 4048 struct drm_device *dev = intel_crtc->base.dev;
877d48d5 4049 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
ff9a6750 4050 int lane, link_bw, fdi_dotclock;
e29c22c0 4051 bool setup_ok, needs_recompute = false;
877d48d5 4052
e29c22c0 4053retry:
877d48d5
DV		 4054 /* FDI is a binary signal running at ~2.7GHz, encoding
4055 * each output octet as 10 bits. The actual frequency
4056 * is stored as a divider into a 100MHz clock, and the
4057 * mode pixel clock is stored in units of 1KHz.
4058 * Hence the bw of each lane in terms of the mode signal
4059 * is:
4060 */
4061 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4062
ff9a6750 4063 fdi_dotclock = adjusted_mode->clock;
877d48d5 4064
2bd89a07 4065 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 4066 pipe_config->pipe_bpp);
4067
4068 pipe_config->fdi_lanes = lane;
4069
2bd89a07 4070 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 4071 link_bw, &pipe_config->fdi_m_n);
1857e1da 4072
e29c22c0
DV		 4073 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4074 intel_crtc->pipe, pipe_config);
4075 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4076 pipe_config->pipe_bpp -= 2*3;
4077 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4078 pipe_config->pipe_bpp);
4079 needs_recompute = true;
4080 pipe_config->bw_constrained = true;
4081
4082 goto retry;
4083 }
4084
4085 if (needs_recompute)
4086 return RETRY;
4087
4088 return setup_ok ? 0 : -EINVAL;
877d48d5
DV		 4089}
4090
42db64ef
PZ		 4091static void hsw_compute_ips_config(struct intel_crtc *crtc,
4092 struct intel_crtc_config *pipe_config)
4093{
3c4ca58c
PZ		 4094 pipe_config->ips_enabled = i915_enable_ips &&
4095 hsw_crtc_supports_ips(crtc) &&
b6dfdc9b 4096 pipe_config->pipe_bpp <= 24;
42db64ef
PZ		 4097}
4098
a43f6e0f 4099static int intel_crtc_compute_config(struct intel_crtc *crtc,
e29c22c0 4100 struct intel_crtc_config *pipe_config)
79e53945 4101{
a43f6e0f 4102 struct drm_device *dev = crtc->base.dev;
b8cecdf5 4103 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 4104
8693a824
DL		 4105 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4106 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 4107 */
4108 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4109 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 4110 return -EINVAL;
44f46b42 4111
bd080ee5 4112 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4113 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4114 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4115 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4116 * for lvds. */
4117 pipe_config->pipe_bpp = 8*3;
4118 }
4119
f5adf94e 4120 if (HAS_IPS(dev))
a43f6e0f
DV		 4121 hsw_compute_ips_config(crtc, pipe_config);
4122
4123 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4124 * clock survives for now. */
4125 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4126 pipe_config->shared_dpll = crtc->config.shared_dpll;
42db64ef 4127
877d48d5 4128 if (pipe_config->has_pch_encoder)
a43f6e0f 4129 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 4130
e29c22c0 4131 return 0;
79e53945
JB		 4132}
4133
25eb05fc
JB		 4134static int valleyview_get_display_clock_speed(struct drm_device *dev)
4135{
4136 return 400000; /* FIXME */
4137}
4138
e70236a8
JB		 4139static int i945_get_display_clock_speed(struct drm_device *dev)
4140{
4141 return 400000;
4142}
79e53945 4143
e70236a8 4144static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4145{
e70236a8
JB		 4146 return 333000;
4147}
79e53945 4148
e70236a8
JB		 4149static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4150{
4151 return 200000;
4152}
79e53945 4153
257a7ffc
DV		 4154static int pnv_get_display_clock_speed(struct drm_device *dev)
4155{
4156 u16 gcfgc = 0;
4157
4158 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4159
4160 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4161 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4162 return 267000;
4163 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4164 return 333000;
4165 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4166 return 444000;
4167 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4168 return 200000;
4169 default:
4170 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4171 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4172 return 133000;
4173 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4174 return 167000;
4175 }
4176}
4177
e70236a8
JB		 4178static int i915gm_get_display_clock_speed(struct drm_device *dev)
4179{
4180 u16 gcfgc = 0;
79e53945 4181
e70236a8
JB		 4182 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4183
4184 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4185 return 133000;
4186 else {
4187 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4188 case GC_DISPLAY_CLOCK_333_MHZ:
4189 return 333000;
4190 default:
4191 case GC_DISPLAY_CLOCK_190_200_MHZ:
4192 return 190000;
79e53945 4193 }
e70236a8
JB		 4194 }
4195}
4196
4197static int i865_get_display_clock_speed(struct drm_device *dev)
4198{
4199 return 266000;
4200}
4201
4202static int i855_get_display_clock_speed(struct drm_device *dev)
4203{
4204 u16 hpllcc = 0;
4205 /* Assume that the hardware is in the high speed state. This
4206 * should be the default.
4207 */
4208 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4209 case GC_CLOCK_133_200:
4210 case GC_CLOCK_100_200:
4211 return 200000;
4212 case GC_CLOCK_166_250:
4213 return 250000;
4214 case GC_CLOCK_100_133:
79e53945 4215 return 133000;
e70236a8 4216 }
79e53945 4217
e70236a8
JB		 4218 /* Shouldn't happen */
4219 return 0;
4220}
79e53945 4221
e70236a8
JB		 4222static int i830_get_display_clock_speed(struct drm_device *dev)
4223{
4224 return 133000;
79e53945
JB		 4225}
4226
2c07245f 4227static void
a65851af 4228intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 4229{
a65851af
VS		 4230 while (*num > DATA_LINK_M_N_MASK ||
4231 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 4232 *num >>= 1;
4233 *den >>= 1;
4234 }
4235}
4236
a65851af
VS		 4237static void compute_m_n(unsigned int m, unsigned int n,
4238 uint32_t *ret_m, uint32_t *ret_n)
4239{
4240 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4241 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4242 intel_reduce_m_n_ratio(ret_m, ret_n);
4243}
4244
e69d0bc1
DV		 4245void
4246intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4247 int pixel_clock, int link_clock,
4248 struct intel_link_m_n *m_n)
2c07245f 4249{
e69d0bc1 4250 m_n->tu = 64;
a65851af
VS		 4251
4252 compute_m_n(bits_per_pixel * pixel_clock,
4253 link_clock * nlanes * 8,
4254 &m_n->gmch_m, &m_n->gmch_n);
4255
4256 compute_m_n(pixel_clock, link_clock,
4257 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4258}
4259
a7615030
CW		 4260static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4261{
72bbe58c
KP		 4262 if (i915_panel_use_ssc >= 0)
4263 return i915_panel_use_ssc != 0;
41aa3448 4264 return dev_priv->vbt.lvds_use_ssc
435793df 4265 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4266}
4267
a0c4da24
JB		 4268static int vlv_get_refclk(struct drm_crtc *crtc)
4269{
4270 struct drm_device *dev = crtc->dev;
4271 struct drm_i915_private *dev_priv = dev->dev_private;
4272 int refclk = 27000; /* for DP & HDMI */
4273
4274 return 100000; /* only one validated so far */
4275
4276 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4277 refclk = 96000;
4278 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4279 if (intel_panel_use_ssc(dev_priv))
4280 refclk = 100000;
4281 else
4282 refclk = 96000;
4283 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4284 refclk = 100000;
4285 }
4286
4287 return refclk;
4288}
4289
c65d77d8
JB		 4290static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4291{
4292 struct drm_device *dev = crtc->dev;
4293 struct drm_i915_private *dev_priv = dev->dev_private;
4294 int refclk;
4295
a0c4da24
JB		 4296 if (IS_VALLEYVIEW(dev)) {
4297 refclk = vlv_get_refclk(crtc);
4298 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8 4299 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
41aa3448 4300 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
c65d77d8
JB		 4301 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4302 refclk / 1000);
4303 } else if (!IS_GEN2(dev)) {
4304 refclk = 96000;
4305 } else {
4306 refclk = 48000;
4307 }
4308
4309 return refclk;
4310}
4311
7429e9d4 4312static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 4313{
7df00d7a 4314 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 4315}
f47709a9 4316
7429e9d4
DV		 4317static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4318{
4319 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 4320}
4321
f47709a9 4322static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4323 intel_clock_t *reduced_clock)
4324{
f47709a9 4325 struct drm_device *dev = crtc->base.dev;
a7516a05 4326 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4327 int pipe = crtc->pipe;
a7516a05
JB		 4328 u32 fp, fp2 = 0;
4329
4330 if (IS_PINEVIEW(dev)) {
7429e9d4 4331 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4332 if (reduced_clock)
7429e9d4 4333 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 4334 } else {
7429e9d4 4335 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4336 if (reduced_clock)
7429e9d4 4337 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 4338 }
4339
4340 I915_WRITE(FP0(pipe), fp);
8bcc2795 4341 crtc->config.dpll_hw_state.fp0 = fp;
a7516a05 4342
f47709a9
DV		 4343 crtc->lowfreq_avail = false;
4344 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4345 reduced_clock && i915_powersave) {
4346 I915_WRITE(FP1(pipe), fp2);
8bcc2795 4347 crtc->config.dpll_hw_state.fp1 = fp2;
f47709a9 4348 crtc->lowfreq_avail = true;
a7516a05
JB		 4349 } else {
4350 I915_WRITE(FP1(pipe), fp);
8bcc2795 4351 crtc->config.dpll_hw_state.fp1 = fp;
a7516a05
JB		 4352 }
4353}
4354
5e69f97f
CML		 4355static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
4356 pipe)
89b667f8
JB		 4357{
4358 u32 reg_val;
4359
4360 /*
4361 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4362 * and set it to a reasonable value instead.
4363 */
5e69f97f 4364 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
89b667f8
JB		 4365 reg_val &= 0xffffff00;
4366 reg_val |= 0x00000030;
5e69f97f 4367 vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
89b667f8 4368
5e69f97f 4369 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
89b667f8
JB		 4370 reg_val &= 0x8cffffff;
4371 reg_val = 0x8c000000;
5e69f97f 4372 vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
89b667f8 4373
5e69f97f 4374 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
89b667f8 4375 reg_val &= 0xffffff00;
5e69f97f 4376 vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
89b667f8 4377
5e69f97f 4378 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
89b667f8
JB		 4379 reg_val &= 0x00ffffff;
4380 reg_val |= 0xb0000000;
5e69f97f 4381 vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
89b667f8
JB		 4382}
4383
b551842d
DV		 4384static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4385 struct intel_link_m_n *m_n)
4386{
4387 struct drm_device *dev = crtc->base.dev;
4388 struct drm_i915_private *dev_priv = dev->dev_private;
4389 int pipe = crtc->pipe;
4390
e3b95f1e
DV		 4391 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4392 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4393 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4394 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 4395}
4396
4397static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4398 struct intel_link_m_n *m_n)
4399{
4400 struct drm_device *dev = crtc->base.dev;
4401 struct drm_i915_private *dev_priv = dev->dev_private;
4402 int pipe = crtc->pipe;
4403 enum transcoder transcoder = crtc->config.cpu_transcoder;
4404
4405 if (INTEL_INFO(dev)->gen >= 5) {
4406 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4407 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4408 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4409 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4410 } else {
e3b95f1e
DV		 4411 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4412 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4413 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4414 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 4415 }
4416}
4417
03afc4a2
DV		 4418static void intel_dp_set_m_n(struct intel_crtc *crtc)
4419{
4420 if (crtc->config.has_pch_encoder)
4421 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4422 else
4423 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4424}
4425
f47709a9 4426static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4427{
f47709a9 4428 struct drm_device *dev = crtc->base.dev;
a0c4da24 4429 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4430 int pipe = crtc->pipe;
89b667f8 4431 u32 dpll, mdiv;
a0c4da24 4432 u32 bestn, bestm1, bestm2, bestp1, bestp2;
198a037f 4433 u32 coreclk, reg_val, dpll_md;
a0c4da24 4434
09153000
DV		 4435 mutex_lock(&dev_priv->dpio_lock);
4436
f47709a9
DV		 4437 bestn = crtc->config.dpll.n;
4438 bestm1 = crtc->config.dpll.m1;
4439 bestm2 = crtc->config.dpll.m2;
4440 bestp1 = crtc->config.dpll.p1;
4441 bestp2 = crtc->config.dpll.p2;
a0c4da24 4442
89b667f8
JB		 4443 /* See eDP HDMI DPIO driver vbios notes doc */
4444
4445 /* PLL B needs special handling */
4446 if (pipe)
5e69f97f 4447 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 4448
4449 /* Set up Tx target for periodic Rcomp update */
5e69f97f 4450 vlv_dpio_write(dev_priv, pipe, DPIO_IREF_BCAST, 0x0100000f);
89b667f8
JB		 4451
4452 /* Disable target IRef on PLL */
5e69f97f 4453 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF_CTL(pipe));
89b667f8 4454 reg_val &= 0x00ffffff;
5e69f97f 4455 vlv_dpio_write(dev_priv, pipe, DPIO_IREF_CTL(pipe), reg_val);
89b667f8
JB		 4456
4457 /* Disable fast lock */
5e69f97f 4458 vlv_dpio_write(dev_priv, pipe, DPIO_FASTCLK_DISABLE, 0x610);
89b667f8
JB		 4459
4460 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4461 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4462 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4463 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4464 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 4465
4466 /*
4467 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4468 * but we don't support that).
4469 * Note: don't use the DAC post divider as it seems unstable.
4470 */
4471 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5e69f97f 4472 vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
a0c4da24 4473
a0c4da24 4474 mdiv |= DPIO_ENABLE_CALIBRATION;
5e69f97f 4475 vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
a0c4da24 4476
89b667f8 4477 /* Set HBR and RBR LPF coefficients */
ff9a6750 4478 if (crtc->config.port_clock == 162000 ||
99750bd4 4479 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
89b667f8 4480 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5e69f97f 4481 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
885b0120 4482 0x009f0003);
89b667f8 4483 else
5e69f97f 4484 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
89b667f8
JB		 4485 0x00d0000f);
4486
4487 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4488 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4489 /* Use SSC source */
4490 if (!pipe)
5e69f97f 4491 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4492 0x0df40000);
4493 else
5e69f97f 4494 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4495 0x0df70000);
4496 } else { /* HDMI or VGA */
4497 /* Use bend source */
4498 if (!pipe)
5e69f97f 4499 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4500 0x0df70000);
4501 else
5e69f97f 4502 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4503 0x0df40000);
4504 }
a0c4da24 4505
5e69f97f 4506 coreclk = vlv_dpio_read(dev_priv, pipe, DPIO_CORE_CLK(pipe));
89b667f8
JB		 4507 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4508 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4509 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4510 coreclk |= 0x01000000;
5e69f97f 4511 vlv_dpio_write(dev_priv, pipe, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4512
5e69f97f 4513 vlv_dpio_write(dev_priv, pipe, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4514
89b667f8
JB		 4515 /* Enable DPIO clock input */
4516 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4517 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4518 if (pipe)
4519 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
a0c4da24
JB		 4520
4521 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4522 crtc->config.dpll_hw_state.dpll = dpll;
4523
ef1b460d
DV		 4524 dpll_md = (crtc->config.pixel_multiplier - 1)
4525 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795
DV		 4526 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4527
89b667f8
JB		 4528 if (crtc->config.has_dp_encoder)
4529 intel_dp_set_m_n(crtc);
09153000
DV		 4530
4531 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4532}
4533
f47709a9
DV		 4534static void i9xx_update_pll(struct intel_crtc *crtc,
4535 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4536 int num_connectors)
4537{
f47709a9 4538 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4539 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 4540 u32 dpll;
4541 bool is_sdvo;
f47709a9 4542 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4543
f47709a9 4544 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4545
f47709a9
DV		 4546 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4547 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4548
4549 dpll = DPLL_VGA_MODE_DIS;
4550
f47709a9 4551 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4552 dpll |= DPLLB_MODE_LVDS;
4553 else
4554 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4555
ef1b460d 4556 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
198a037f
DV		 4557 dpll |= (crtc->config.pixel_multiplier - 1)
4558 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 4559 }
198a037f
DV		 4560
4561 if (is_sdvo)
4a33e48d 4562 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 4563
f47709a9 4564 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4a33e48d 4565 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 4566
4567 /* compute bitmask from p1 value */
4568 if (IS_PINEVIEW(dev))
4569 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4570 else {
4571 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4572 if (IS_G4X(dev) && reduced_clock)
4573 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4574 }
4575 switch (clock->p2) {
4576 case 5:
4577 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4578 break;
4579 case 7:
4580 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4581 break;
4582 case 10:
4583 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4584 break;
4585 case 14:
4586 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4587 break;
4588 }
4589 if (INTEL_INFO(dev)->gen >= 4)
4590 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4591
09ede541 4592 if (crtc->config.sdvo_tv_clock)
eb1cbe48 4593 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4594 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4595 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4596 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4597 else
4598 dpll |= PLL_REF_INPUT_DREFCLK;
4599
4600 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4601 crtc->config.dpll_hw_state.dpll = dpll;
4602
eb1cbe48 4603 if (INTEL_INFO(dev)->gen >= 4) {
ef1b460d
DV		 4604 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4605 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795 4606 crtc->config.dpll_hw_state.dpll_md = dpll_md;
eb1cbe48 4607 }
66e3d5c0
DV		 4608
4609 if (crtc->config.has_dp_encoder)
4610 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4611}
4612
f47709a9 4613static void i8xx_update_pll(struct intel_crtc *crtc,
f47709a9 4614 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4615 int num_connectors)
4616{
f47709a9 4617 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4618 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 4619 u32 dpll;
f47709a9 4620 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4621
f47709a9 4622 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4623
eb1cbe48
DV		 4624 dpll = DPLL_VGA_MODE_DIS;
4625
f47709a9 4626 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4627 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4628 } else {
4629 if (clock->p1 == 2)
4630 dpll |= PLL_P1_DIVIDE_BY_TWO;
4631 else
4632 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4633 if (clock->p2 == 4)
4634 dpll |= PLL_P2_DIVIDE_BY_4;
4635 }
4636
4a33e48d
DV		 4637 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
4638 dpll |= DPLL_DVO_2X_MODE;
4639
f47709a9 4640 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4641 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4642 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4643 else
4644 dpll |= PLL_REF_INPUT_DREFCLK;
4645
4646 dpll |= DPLL_VCO_ENABLE;
8bcc2795 4647 crtc->config.dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 4648}
4649
8a654f3b 4650static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 4651{
4652 struct drm_device *dev = intel_crtc->base.dev;
4653 struct drm_i915_private *dev_priv = dev->dev_private;
4654 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4655 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8a654f3b
DV		 4656 struct drm_display_mode *adjusted_mode =
4657 &intel_crtc->config.adjusted_mode;
4658 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4d8a62ea
DV		 4659 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4660
4661 /* We need to be careful not to changed the adjusted mode, for otherwise
4662 * the hw state checker will get angry at the mismatch. */
4663 crtc_vtotal = adjusted_mode->crtc_vtotal;
4664 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c
PZ		 4665
4666 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4667 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 4668 crtc_vtotal -= 1;
4669 crtc_vblank_end -= 1;
b0e77b9c
PZ		 4670 vsyncshift = adjusted_mode->crtc_hsync_start
4671 - adjusted_mode->crtc_htotal / 2;
4672 } else {
4673 vsyncshift = 0;
4674 }
4675
4676 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4677 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4678
fe2b8f9d 4679 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4680 (adjusted_mode->crtc_hdisplay - 1) |
4681 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4682 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4683 (adjusted_mode->crtc_hblank_start - 1) |
4684 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4685 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4686 (adjusted_mode->crtc_hsync_start - 1) |
4687 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4688
fe2b8f9d 4689 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 4690 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 4691 ((crtc_vtotal - 1) << 16));
fe2b8f9d 4692 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 4693 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 4694 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 4695 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4696 (adjusted_mode->crtc_vsync_start - 1) |
4697 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4698
b5e508d4
PZ		 4699 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4700 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4701 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4702 * bits. */
4703 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4704 (pipe == PIPE_B || pipe == PIPE_C))
4705 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4706
b0e77b9c
PZ		 4707 /* pipesrc controls the size that is scaled from, which should
4708 * always be the user's requested size.
4709 */
4710 I915_WRITE(PIPESRC(pipe),
4711 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4712}
4713
1bd1bd80
DV		 4714static void intel_get_pipe_timings(struct intel_crtc *crtc,
4715 struct intel_crtc_config *pipe_config)
4716{
4717 struct drm_device *dev = crtc->base.dev;
4718 struct drm_i915_private *dev_priv = dev->dev_private;
4719 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4720 uint32_t tmp;
4721
4722 tmp = I915_READ(HTOTAL(cpu_transcoder));
4723 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4724 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4725 tmp = I915_READ(HBLANK(cpu_transcoder));
4726 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4727 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4728 tmp = I915_READ(HSYNC(cpu_transcoder));
4729 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4730 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4731
4732 tmp = I915_READ(VTOTAL(cpu_transcoder));
4733 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4734 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4735 tmp = I915_READ(VBLANK(cpu_transcoder));
4736 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4737 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4738 tmp = I915_READ(VSYNC(cpu_transcoder));
4739 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4740 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4741
4742 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4743 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4744 pipe_config->adjusted_mode.crtc_vtotal += 1;
4745 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4746 }
4747
4748 tmp = I915_READ(PIPESRC(crtc->pipe));
4749 pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4750 pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4751}
4752
babea61d
JB		 4753static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
4754 struct intel_crtc_config *pipe_config)
4755{
4756 struct drm_crtc *crtc = &intel_crtc->base;
4757
4758 crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
4759 crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
4760 crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
4761 crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
4762
4763 crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
4764 crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
4765 crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
4766 crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
4767
4768 crtc->mode.flags = pipe_config->adjusted_mode.flags;
4769
4770 crtc->mode.clock = pipe_config->adjusted_mode.clock;
4771 crtc->mode.flags |= pipe_config->adjusted_mode.flags;
4772}
4773
84b046f3
DV		 4774static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4775{
4776 struct drm_device *dev = intel_crtc->base.dev;
4777 struct drm_i915_private *dev_priv = dev->dev_private;
4778 uint32_t pipeconf;
4779
9f11a9e4 4780 pipeconf = 0;
84b046f3
DV		 4781
4782 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4783 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4784 * core speed.
4785 *
4786 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4787 * pipe == 0 check?
4788 */
4789 if (intel_crtc->config.requested_mode.clock >
4790 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4791 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3
DV		 4792 }
4793
ff9ce46e
DV		 4794 /* only g4x and later have fancy bpc/dither controls */
4795 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e
DV		 4796 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4797 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4798 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 4799 PIPECONF_DITHER_TYPE_SP;
84b046f3 4800
ff9ce46e
DV		 4801 switch (intel_crtc->config.pipe_bpp) {
4802 case 18:
4803 pipeconf |= PIPECONF_6BPC;
4804 break;
4805 case 24:
4806 pipeconf |= PIPECONF_8BPC;
4807 break;
4808 case 30:
4809 pipeconf |= PIPECONF_10BPC;
4810 break;
4811 default:
4812 /* Case prevented by intel_choose_pipe_bpp_dither. */
4813 BUG();
84b046f3
DV		 4814 }
4815 }
4816
4817 if (HAS_PIPE_CXSR(dev)) {
4818 if (intel_crtc->lowfreq_avail) {
4819 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4820 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4821 } else {
4822 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 4823 }
4824 }
4825
84b046f3
DV		 4826 if (!IS_GEN2(dev) &&
4827 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4828 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4829 else
4830 pipeconf |= PIPECONF_PROGRESSIVE;
4831
9f11a9e4
DV		 4832 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4833 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 4834
84b046f3
DV		 4835 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4836 POSTING_READ(PIPECONF(intel_crtc->pipe));
4837}
4838
f564048e 4839static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4840 int x, int y,
94352cf9 4841 struct drm_framebuffer *fb)
79e53945
JB		 4842{
4843 struct drm_device *dev = crtc->dev;
4844 struct drm_i915_private *dev_priv = dev->dev_private;
4845 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5 4846 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
79e53945 4847 int pipe = intel_crtc->pipe;
80824003 4848 int plane = intel_crtc->plane;
c751ce4f 4849 int refclk, num_connectors = 0;
652c393a 4850 intel_clock_t clock, reduced_clock;
84b046f3 4851 u32 dspcntr;
a16af721 4852 bool ok, has_reduced_clock = false;
e9fd1c02 4853 bool is_lvds = false, is_dsi = false;
5eddb70b 4854 struct intel_encoder *encoder;
d4906093 4855 const intel_limit_t *limit;
5c3b82e2 4856 int ret;
79e53945 4857
6c2b7c12 4858 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4859 switch (encoder->type) {
79e53945
JB		 4860 case INTEL_OUTPUT_LVDS:
4861 is_lvds = true;
4862 break;
e9fd1c02
JN		 4863 case INTEL_OUTPUT_DSI:
4864 is_dsi = true;
4865 break;
79e53945 4866 }
43565a06 4867
c751ce4f 4868 num_connectors++;
79e53945
JB		 4869 }
4870
c65d77d8 4871 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4872
65ce4bf5 4873 if (!is_dsi && !intel_crtc->config.clock_set) {
e9fd1c02
JN		 4874 /*
4875 * Returns a set of divisors for the desired target clock with
4876 * the given refclk, or FALSE. The returned values represent
4877 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
4878 * 2) / p1 / p2.
4879 */
4880 limit = intel_limit(crtc, refclk);
4881 ok = dev_priv->display.find_dpll(limit, crtc,
4882 intel_crtc->config.port_clock,
4883 refclk, NULL, &clock);
4884 if (!ok && !intel_crtc->config.clock_set) {
4885 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4886 return -EINVAL;
4887 }
79e53945
JB		 4888 }
4889
cda4b7d3 4890 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4891 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4892
e9fd1c02 4893 if (!is_dsi && is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4894 /*
4895 * Ensure we match the reduced clock's P to the target clock.
4896 * If the clocks don't match, we can't switch the display clock
4897 * by using the FP0/FP1. In such case we will disable the LVDS
4898 * downclock feature.
4899 */
65ce4bf5 4900 limit = intel_limit(crtc, refclk);
ee9300bb
DV		 4901 has_reduced_clock =
4902 dev_priv->display.find_dpll(limit, crtc,
5eddb70b 4903 dev_priv->lvds_downclock,
ee9300bb 4904 refclk, &clock,
5eddb70b 4905 &reduced_clock);
7026d4ac 4906 }
f47709a9
DV		 4907 /* Compat-code for transition, will disappear. */
4908 if (!intel_crtc->config.clock_set) {
4909 intel_crtc->config.dpll.n = clock.n;
4910 intel_crtc->config.dpll.m1 = clock.m1;
4911 intel_crtc->config.dpll.m2 = clock.m2;
4912 intel_crtc->config.dpll.p1 = clock.p1;
4913 intel_crtc->config.dpll.p2 = clock.p2;
4914 }
7026d4ac 4915
e9fd1c02 4916 if (IS_GEN2(dev)) {
8a654f3b 4917 i8xx_update_pll(intel_crtc,
2a8f64ca
VP		 4918 has_reduced_clock ? &reduced_clock : NULL,
4919 num_connectors);
e9fd1c02
JN		 4920 } else if (IS_VALLEYVIEW(dev)) {
4921 if (!is_dsi)
4922 vlv_update_pll(intel_crtc);
4923 } else {
f47709a9 4924 i9xx_update_pll(intel_crtc,
eb1cbe48 4925 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 4926 num_connectors);
e9fd1c02 4927 }
79e53945 4928
79e53945
JB		 4929 /* Set up the display plane register */
4930 dspcntr = DISPPLANE_GAMMA_ENABLE;
4931
da6ecc5d
JB		 4932 if (!IS_VALLEYVIEW(dev)) {
4933 if (pipe == 0)
4934 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4935 else
4936 dspcntr |= DISPPLANE_SEL_PIPE_B;
4937 }
79e53945 4938
8a654f3b 4939 intel_set_pipe_timings(intel_crtc);
5eddb70b
CW		 4940
4941 /* pipesrc and dspsize control the size that is scaled from,
4942 * which should always be the user's requested size.
79e53945 4943 */
929c77fb
EA		 4944 I915_WRITE(DSPSIZE(plane),
4945 ((mode->vdisplay - 1) << 16) |
4946 (mode->hdisplay - 1));
4947 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4948
84b046f3
DV		 4949 i9xx_set_pipeconf(intel_crtc);
4950
f564048e
EA		 4951 I915_WRITE(DSPCNTR(plane), dspcntr);
4952 POSTING_READ(DSPCNTR(plane));
4953
94352cf9 4954 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e 4955
f564048e
EA		 4956 return ret;
4957}
4958
2fa2fe9a
DV		 4959static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4960 struct intel_crtc_config *pipe_config)
4961{
4962 struct drm_device *dev = crtc->base.dev;
4963 struct drm_i915_private *dev_priv = dev->dev_private;
4964 uint32_t tmp;
4965
4966 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 4967 if (!(tmp & PFIT_ENABLE))
4968 return;
2fa2fe9a 4969
06922821 4970 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 4971 if (INTEL_INFO(dev)->gen < 4) {
4972 if (crtc->pipe != PIPE_B)
4973 return;
2fa2fe9a
DV		 4974 } else {
4975 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4976 return;
4977 }
4978
06922821 4979 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 4980 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
4981 if (INTEL_INFO(dev)->gen < 5)
4982 pipe_config->gmch_pfit.lvds_border_bits =
4983 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
4984}
4985
0e8ffe1b
DV		 4986static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4987 struct intel_crtc_config *pipe_config)
4988{
4989 struct drm_device *dev = crtc->base.dev;
4990 struct drm_i915_private *dev_priv = dev->dev_private;
4991 uint32_t tmp;
4992
e143a21c 4993 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 4994 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 4995
0e8ffe1b
DV		 4996 tmp = I915_READ(PIPECONF(crtc->pipe));
4997 if (!(tmp & PIPECONF_ENABLE))
4998 return false;
4999
1bd1bd80
DV		 5000 intel_get_pipe_timings(crtc, pipe_config);
5001
2fa2fe9a
DV		 5002 i9xx_get_pfit_config(crtc, pipe_config);
5003
6c49f241
DV		 5004 if (INTEL_INFO(dev)->gen >= 4) {
5005 tmp = I915_READ(DPLL_MD(crtc->pipe));
5006 pipe_config->pixel_multiplier =
5007 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5008 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 5009 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 5010 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5011 tmp = I915_READ(DPLL(crtc->pipe));
5012 pipe_config->pixel_multiplier =
5013 ((tmp & SDVO_MULTIPLIER_MASK)
5014 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5015 } else {
5016 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5017 * port and will be fixed up in the encoder->get_config
5018 * function. */
5019 pipe_config->pixel_multiplier = 1;
5020 }
8bcc2795
DV		 5021 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5022 if (!IS_VALLEYVIEW(dev)) {
5023 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5024 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 5025 } else {
5026 /* Mask out read-only status bits. */
5027 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5028 DPLL_PORTC_READY_MASK |
5029 DPLL_PORTB_READY_MASK);
8bcc2795 5030 }
6c49f241 5031
0e8ffe1b
DV		 5032 return true;
5033}
5034
dde86e2d 5035static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 5036{
5037 struct drm_i915_private *dev_priv = dev->dev_private;
5038 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 5039 struct intel_encoder *encoder;
74cfd7ac 5040 u32 val, final;
13d83a67 5041 bool has_lvds = false;
199e5d79 5042 bool has_cpu_edp = false;
199e5d79 5043 bool has_panel = false;
99eb6a01
KP		 5044 bool has_ck505 = false;
5045 bool can_ssc = false;
13d83a67
JB		 5046
5047 /* We need to take the global config into account */
199e5d79
KP		 5048 list_for_each_entry(encoder, &mode_config->encoder_list,
5049 base.head) {
5050 switch (encoder->type) {
5051 case INTEL_OUTPUT_LVDS:
5052 has_panel = true;
5053 has_lvds = true;
5054 break;
5055 case INTEL_OUTPUT_EDP:
5056 has_panel = true;
2de6905f 5057 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 5058 has_cpu_edp = true;
5059 break;
13d83a67
JB		 5060 }
5061 }
5062
99eb6a01 5063 if (HAS_PCH_IBX(dev)) {
41aa3448 5064 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 5065 can_ssc = has_ck505;
5066 } else {
5067 has_ck505 = false;
5068 can_ssc = true;
5069 }
5070
2de6905f
ID		 5071 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5072 has_panel, has_lvds, has_ck505);
13d83a67
JB		 5073
5074 /* Ironlake: try to setup display ref clock before DPLL
5075 * enabling. This is only under driver's control after
5076 * PCH B stepping, previous chipset stepping should be
5077 * ignoring this setting.
5078 */
74cfd7ac
CW		 5079 val = I915_READ(PCH_DREF_CONTROL);
5080
5081 /* As we must carefully and slowly disable/enable each source in turn,
5082 * compute the final state we want first and check if we need to
5083 * make any changes at all.
5084 */
5085 final = val;
5086 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5087 if (has_ck505)
5088 final |= DREF_NONSPREAD_CK505_ENABLE;
5089 else
5090 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5091
5092 final &= ~DREF_SSC_SOURCE_MASK;
5093 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5094 final &= ~DREF_SSC1_ENABLE;
5095
5096 if (has_panel) {
5097 final |= DREF_SSC_SOURCE_ENABLE;
5098
5099 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5100 final |= DREF_SSC1_ENABLE;
5101
5102 if (has_cpu_edp) {
5103 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5104 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5105 else
5106 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5107 } else
5108 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5109 } else {
5110 final |= DREF_SSC_SOURCE_DISABLE;
5111 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5112 }
5113
5114 if (final == val)
5115 return;
5116
13d83a67 5117 /* Always enable nonspread source */
74cfd7ac 5118 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5119
99eb6a01 5120 if (has_ck505)
74cfd7ac 5121 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 5122 else
74cfd7ac 5123 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5124
199e5d79 5125 if (has_panel) {
74cfd7ac
CW		 5126 val &= ~DREF_SSC_SOURCE_MASK;
5127 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5128
199e5d79 5129 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5130 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5131 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 5132 val |= DREF_SSC1_ENABLE;
e77166b5 5133 } else
74cfd7ac 5134 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 5135
5136 /* Get SSC going before enabling the outputs */
74cfd7ac 5137 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5138 POSTING_READ(PCH_DREF_CONTROL);
5139 udelay(200);
5140
74cfd7ac 5141 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 5142
5143 /* Enable CPU source on CPU attached eDP */
199e5d79 5144 if (has_cpu_edp) {
99eb6a01 5145 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5146 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 5147 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5148 }
13d83a67 5149 else
74cfd7ac 5150 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 5151 } else
74cfd7ac 5152 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5153
74cfd7ac 5154 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5155 POSTING_READ(PCH_DREF_CONTROL);
5156 udelay(200);
5157 } else {
5158 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5159
74cfd7ac 5160 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 5161
5162 /* Turn off CPU output */
74cfd7ac 5163 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5164
74cfd7ac 5165 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5166 POSTING_READ(PCH_DREF_CONTROL);
5167 udelay(200);
5168
5169 /* Turn off the SSC source */
74cfd7ac
CW		 5170 val &= ~DREF_SSC_SOURCE_MASK;
5171 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 5172
5173 /* Turn off SSC1 */
74cfd7ac 5174 val &= ~DREF_SSC1_ENABLE;
199e5d79 5175
74cfd7ac 5176 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 5177 POSTING_READ(PCH_DREF_CONTROL);
5178 udelay(200);
5179 }
74cfd7ac
CW		 5180
5181 BUG_ON(val != final);
13d83a67
JB		 5182}
5183
f31f2d55 5184static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 5185{
f31f2d55 5186 uint32_t tmp;
dde86e2d 5187
0ff066a9
PZ		 5188 tmp = I915_READ(SOUTH_CHICKEN2);
5189 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5190 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 5191
0ff066a9
PZ		 5192 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5193 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5194 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 5195
0ff066a9
PZ		 5196 tmp = I915_READ(SOUTH_CHICKEN2);
5197 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5198 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 5199
0ff066a9
PZ		 5200 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5201 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5202 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 5203}
5204
5205/* WaMPhyProgramming:hsw */
5206static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5207{
5208 uint32_t tmp;
dde86e2d
PZ		 5209
5210 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5211 tmp &= ~(0xFF << 24);
5212 tmp |= (0x12 << 24);
5213 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5214
dde86e2d
PZ		 5215 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5216 tmp |= (1 << 11);
5217 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5218
5219 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5220 tmp |= (1 << 11);
5221 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5222
dde86e2d
PZ		 5223 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5224 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5225 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5226
5227 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5228 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5229 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5230
0ff066a9
PZ		 5231 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5232 tmp &= ~(7 << 13);
5233 tmp |= (5 << 13);
5234 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 5235
0ff066a9
PZ		 5236 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5237 tmp &= ~(7 << 13);
5238 tmp |= (5 << 13);
5239 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 5240
5241 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5242 tmp &= ~0xFF;
5243 tmp |= 0x1C;
5244 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5245
5246 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5247 tmp &= ~0xFF;
5248 tmp |= 0x1C;
5249 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5250
5251 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5252 tmp &= ~(0xFF << 16);
5253 tmp |= (0x1C << 16);
5254 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5255
5256 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5257 tmp &= ~(0xFF << 16);
5258 tmp |= (0x1C << 16);
5259 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5260
0ff066a9
PZ		 5261 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5262 tmp |= (1 << 27);
5263 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 5264
0ff066a9
PZ		 5265 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5266 tmp |= (1 << 27);
5267 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 5268
0ff066a9
PZ		 5269 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5270 tmp &= ~(0xF << 28);
5271 tmp |= (4 << 28);
5272 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 5273
0ff066a9
PZ		 5274 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5275 tmp &= ~(0xF << 28);
5276 tmp |= (4 << 28);
5277 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 5278}
5279
2fa86a1f
PZ		 5280/* Implements 3 different sequences from BSpec chapter "Display iCLK
5281 * Programming" based on the parameters passed:
5282 * - Sequence to enable CLKOUT_DP
5283 * - Sequence to enable CLKOUT_DP without spread
5284 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5285 */
5286static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5287 bool with_fdi)
f31f2d55
PZ		 5288{
5289 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 5290 uint32_t reg, tmp;
5291
5292 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5293 with_spread = true;
5294 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5295 with_fdi, "LP PCH doesn't have FDI\n"))
5296 with_fdi = false;
f31f2d55
PZ		 5297
5298 mutex_lock(&dev_priv->dpio_lock);
5299
5300 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5301 tmp &= ~SBI_SSCCTL_DISABLE;
5302 tmp |= SBI_SSCCTL_PATHALT;
5303 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5304
5305 udelay(24);
5306
2fa86a1f
PZ		 5307 if (with_spread) {
5308 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5309 tmp &= ~SBI_SSCCTL_PATHALT;
5310 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 5311
2fa86a1f
PZ		 5312 if (with_fdi) {
5313 lpt_reset_fdi_mphy(dev_priv);
5314 lpt_program_fdi_mphy(dev_priv);
5315 }
5316 }
dde86e2d 5317
2fa86a1f
PZ		 5318 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5319 SBI_GEN0 : SBI_DBUFF0;
5320 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5321 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5322 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246
DV		 5323
5324 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5325}
5326
47701c3b
PZ		 5327/* Sequence to disable CLKOUT_DP */
5328static void lpt_disable_clkout_dp(struct drm_device *dev)
5329{
5330 struct drm_i915_private *dev_priv = dev->dev_private;
5331 uint32_t reg, tmp;
5332
5333 mutex_lock(&dev_priv->dpio_lock);
5334
5335 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5336 SBI_GEN0 : SBI_DBUFF0;
5337 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5338 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5339 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5340
5341 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5342 if (!(tmp & SBI_SSCCTL_DISABLE)) {
5343 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5344 tmp |= SBI_SSCCTL_PATHALT;
5345 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5346 udelay(32);
5347 }
5348 tmp |= SBI_SSCCTL_DISABLE;
5349 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5350 }
5351
5352 mutex_unlock(&dev_priv->dpio_lock);
5353}
5354
bf8fa3d3
PZ		 5355static void lpt_init_pch_refclk(struct drm_device *dev)
5356{
5357 struct drm_mode_config *mode_config = &dev->mode_config;
5358 struct intel_encoder *encoder;
5359 bool has_vga = false;
5360
5361 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5362 switch (encoder->type) {
5363 case INTEL_OUTPUT_ANALOG:
5364 has_vga = true;
5365 break;
5366 }
5367 }
5368
47701c3b
PZ		 5369 if (has_vga)
5370 lpt_enable_clkout_dp(dev, true, true);
5371 else
5372 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 5373}
5374
dde86e2d
PZ		 5375/*
5376 * Initialize reference clocks when the driver loads
5377 */
5378void intel_init_pch_refclk(struct drm_device *dev)
5379{
5380 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5381 ironlake_init_pch_refclk(dev);
5382 else if (HAS_PCH_LPT(dev))
5383 lpt_init_pch_refclk(dev);
5384}
5385
d9d444cb
JB		 5386static int ironlake_get_refclk(struct drm_crtc *crtc)
5387{
5388 struct drm_device *dev = crtc->dev;
5389 struct drm_i915_private *dev_priv = dev->dev_private;
5390 struct intel_encoder *encoder;
d9d444cb
JB		 5391 int num_connectors = 0;
5392 bool is_lvds = false;
5393
6c2b7c12 5394 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5395 switch (encoder->type) {
5396 case INTEL_OUTPUT_LVDS:
5397 is_lvds = true;
5398 break;
d9d444cb
JB		 5399 }
5400 num_connectors++;
5401 }
5402
5403 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5404 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
41aa3448
RV		 5405 dev_priv->vbt.lvds_ssc_freq);
5406 return dev_priv->vbt.lvds_ssc_freq * 1000;
d9d444cb
JB		 5407 }
5408
5409 return 120000;
5410}
5411
6ff93609 5412static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 5413{
c8203565 5414 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5415 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5416 int pipe = intel_crtc->pipe;
c8203565
PZ		 5417 uint32_t val;
5418
78114071 5419 val = 0;
c8203565 5420
965e0c48 5421 switch (intel_crtc->config.pipe_bpp) {
c8203565 5422 case 18:
dfd07d72 5423 val |= PIPECONF_6BPC;
c8203565
PZ		 5424 break;
5425 case 24:
dfd07d72 5426 val |= PIPECONF_8BPC;
c8203565
PZ		 5427 break;
5428 case 30:
dfd07d72 5429 val |= PIPECONF_10BPC;
c8203565
PZ		 5430 break;
5431 case 36:
dfd07d72 5432 val |= PIPECONF_12BPC;
c8203565
PZ		 5433 break;
5434 default:
cc769b62
PZ		 5435 /* Case prevented by intel_choose_pipe_bpp_dither. */
5436 BUG();
c8203565
PZ		 5437 }
5438
d8b32247 5439 if (intel_crtc->config.dither)
c8203565
PZ		 5440 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5441
6ff93609 5442 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 5443 val |= PIPECONF_INTERLACED_ILK;
5444 else
5445 val |= PIPECONF_PROGRESSIVE;
5446
50f3b016 5447 if (intel_crtc->config.limited_color_range)
3685a8f3 5448 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 5449
c8203565
PZ		 5450 I915_WRITE(PIPECONF(pipe), val);
5451 POSTING_READ(PIPECONF(pipe));
5452}
5453
86d3efce
VS		 5454/*
5455 * Set up the pipe CSC unit.
5456 *
5457 * Currently only full range RGB to limited range RGB conversion
5458 * is supported, but eventually this should handle various
5459 * RGB<->YCbCr scenarios as well.
5460 */
50f3b016 5461static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5462{
5463 struct drm_device *dev = crtc->dev;
5464 struct drm_i915_private *dev_priv = dev->dev_private;
5465 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5466 int pipe = intel_crtc->pipe;
5467 uint16_t coeff = 0x7800; /* 1.0 */
5468
5469 /*
5470 * TODO: Check what kind of values actually come out of the pipe
5471 * with these coeff/postoff values and adjust to get the best
5472 * accuracy. Perhaps we even need to take the bpc value into
5473 * consideration.
5474 */
5475
50f3b016 5476 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5477 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5478
5479 /*
5480 * GY/GU and RY/RU should be the other way around according
5481 * to BSpec, but reality doesn't agree. Just set them up in
5482 * a way that results in the correct picture.
5483 */
5484 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5485 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5486
5487 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5488 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5489
5490 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5491 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5492
5493 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5494 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5495 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5496
5497 if (INTEL_INFO(dev)->gen > 6) {
5498 uint16_t postoff = 0;
5499
50f3b016 5500 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5501 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5502
5503 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5504 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5505 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5506
5507 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5508 } else {
5509 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5510
50f3b016 5511 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5512 mode |= CSC_BLACK_SCREEN_OFFSET;
5513
5514 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5515 }
5516}
5517
6ff93609 5518static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38
PZ		 5519{
5520 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5521 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5522 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5523 uint32_t val;
5524
3eff4faa 5525 val = 0;
ee2b0b38 5526
d8b32247 5527 if (intel_crtc->config.dither)
ee2b0b38
PZ		 5528 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5529
6ff93609 5530 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 5531 val |= PIPECONF_INTERLACED_ILK;
5532 else
5533 val |= PIPECONF_PROGRESSIVE;
5534
702e7a56
PZ		 5535 I915_WRITE(PIPECONF(cpu_transcoder), val);
5536 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 5537
5538 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5539 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
ee2b0b38
PZ		 5540}
5541
6591c6e4 5542static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6591c6e4
PZ		 5543 intel_clock_t *clock,
5544 bool *has_reduced_clock,
5545 intel_clock_t *reduced_clock)
5546{
5547 struct drm_device *dev = crtc->dev;
5548 struct drm_i915_private *dev_priv = dev->dev_private;
5549 struct intel_encoder *intel_encoder;
5550 int refclk;
d4906093 5551 const intel_limit_t *limit;
a16af721 5552 bool ret, is_lvds = false;
79e53945 5553
6591c6e4
PZ		 5554 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5555 switch (intel_encoder->type) {
79e53945
JB		 5556 case INTEL_OUTPUT_LVDS:
5557 is_lvds = true;
5558 break;
79e53945
JB		 5559 }
5560 }
5561
d9d444cb 5562 refclk = ironlake_get_refclk(crtc);
79e53945 5563
d4906093
ML		 5564 /*
5565 * Returns a set of divisors for the desired target clock with the given
5566 * refclk, or FALSE. The returned values represent the clock equation:
5567 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5568 */
1b894b59 5569 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 5570 ret = dev_priv->display.find_dpll(limit, crtc,
5571 to_intel_crtc(crtc)->config.port_clock,
ee9300bb 5572 refclk, NULL, clock);
6591c6e4
PZ		 5573 if (!ret)
5574 return false;
cda4b7d3 5575
ddc9003c 5576 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5577 /*
5578 * Ensure we match the reduced clock's P to the target clock.
5579 * If the clocks don't match, we can't switch the display clock
5580 * by using the FP0/FP1. In such case we will disable the LVDS
5581 * downclock feature.
5582 */
ee9300bb
DV		 5583 *has_reduced_clock =
5584 dev_priv->display.find_dpll(limit, crtc,
5585 dev_priv->lvds_downclock,
5586 refclk, clock,
5587 reduced_clock);
652c393a 5588 }
61e9653f 5589
6591c6e4
PZ		 5590 return true;
5591}
5592
01a415fd
DV		 5593static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5594{
5595 struct drm_i915_private *dev_priv = dev->dev_private;
5596 uint32_t temp;
5597
5598 temp = I915_READ(SOUTH_CHICKEN1);
5599 if (temp & FDI_BC_BIFURCATION_SELECT)
5600 return;
5601
5602 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5603 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5604
5605 temp |= FDI_BC_BIFURCATION_SELECT;
5606 DRM_DEBUG_KMS("enabling fdi C rx\n");
5607 I915_WRITE(SOUTH_CHICKEN1, temp);
5608 POSTING_READ(SOUTH_CHICKEN1);
5609}
5610
ebfd86fd 5611static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
01a415fd
DV		 5612{
5613 struct drm_device *dev = intel_crtc->base.dev;
5614 struct drm_i915_private *dev_priv = dev->dev_private;
01a415fd
DV		 5615
5616 switch (intel_crtc->pipe) {
5617 case PIPE_A:
ebfd86fd 5618 break;
01a415fd 5619 case PIPE_B:
ebfd86fd 5620 if (intel_crtc->config.fdi_lanes > 2)
01a415fd
DV		 5621 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5622 else
5623 cpt_enable_fdi_bc_bifurcation(dev);
5624
ebfd86fd 5625 break;
01a415fd 5626 case PIPE_C:
01a415fd
DV		 5627 cpt_enable_fdi_bc_bifurcation(dev);
5628
ebfd86fd 5629 break;
01a415fd
DV		 5630 default:
5631 BUG();
5632 }
5633}
5634
d4b1931c
PZ		 5635int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5636{
5637 /*
5638 * Account for spread spectrum to avoid
5639 * oversubscribing the link. Max center spread
5640 * is 2.5%; use 5% for safety's sake.
5641 */
5642 u32 bps = target_clock * bpp * 21 / 20;
5643 return bps / (link_bw * 8) + 1;
5644}
5645
7429e9d4 5646static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 5647{
7429e9d4 5648 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 5649}
5650
de13a2e3 5651static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7429e9d4 5652 u32 *fp,
9a7c7890 5653 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5654{
de13a2e3 5655 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5656 struct drm_device *dev = crtc->dev;
5657 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5658 struct intel_encoder *intel_encoder;
5659 uint32_t dpll;
6cc5f341 5660 int factor, num_connectors = 0;
09ede541 5661 bool is_lvds = false, is_sdvo = false;
79e53945 5662
de13a2e3
PZ		 5663 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5664 switch (intel_encoder->type) {
79e53945
JB		 5665 case INTEL_OUTPUT_LVDS:
5666 is_lvds = true;
5667 break;
5668 case INTEL_OUTPUT_SDVO:
7d57382e 5669 case INTEL_OUTPUT_HDMI:
79e53945 5670 is_sdvo = true;
79e53945 5671 break;
79e53945 5672 }
43565a06 5673
c751ce4f 5674 num_connectors++;
79e53945 5675 }
79e53945 5676
c1858123 5677 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5678 factor = 21;
5679 if (is_lvds) {
5680 if ((intel_panel_use_ssc(dev_priv) &&
41aa3448 5681 dev_priv->vbt.lvds_ssc_freq == 100) ||
f0b44056 5682 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 5683 factor = 25;
09ede541 5684 } else if (intel_crtc->config.sdvo_tv_clock)
8febb297 5685 factor = 20;
c1858123 5686
7429e9d4 5687 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7d0ac5b7 5688 *fp |= FP_CB_TUNE;
2c07245f 5689
9a7c7890
DV		 5690 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5691 *fp2 |= FP_CB_TUNE;
5692
5eddb70b 5693 dpll = 0;
2c07245f 5694
a07d6787
EA		 5695 if (is_lvds)
5696 dpll |= DPLLB_MODE_LVDS;
5697 else
5698 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 5699
ef1b460d
DV		 5700 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5701 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 5702
5703 if (is_sdvo)
4a33e48d 5704 dpll |= DPLL_SDVO_HIGH_SPEED;
9566e9af 5705 if (intel_crtc->config.has_dp_encoder)
4a33e48d 5706 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 5707
a07d6787 5708 /* compute bitmask from p1 value */
7429e9d4 5709 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5710 /* also FPA1 */
7429e9d4 5711 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5712
7429e9d4 5713 switch (intel_crtc->config.dpll.p2) {
a07d6787
EA		 5714 case 5:
5715 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5716 break;
5717 case 7:
5718 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5719 break;
5720 case 10:
5721 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5722 break;
5723 case 14:
5724 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5725 break;
79e53945
JB		 5726 }
5727
b4c09f3b 5728 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5729 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5730 else
5731 dpll |= PLL_REF_INPUT_DREFCLK;
5732
959e16d6 5733 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 5734}
5735
5736static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5737 int x, int y,
5738 struct drm_framebuffer *fb)
5739{
5740 struct drm_device *dev = crtc->dev;
5741 struct drm_i915_private *dev_priv = dev->dev_private;
5742 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5743 int pipe = intel_crtc->pipe;
5744 int plane = intel_crtc->plane;
5745 int num_connectors = 0;
5746 intel_clock_t clock, reduced_clock;
cbbab5bd 5747 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 5748 bool ok, has_reduced_clock = false;
8b47047b 5749 bool is_lvds = false;
de13a2e3 5750 struct intel_encoder *encoder;
e2b78267 5751 struct intel_shared_dpll *pll;
de13a2e3 5752 int ret;
de13a2e3
PZ		 5753
5754 for_each_encoder_on_crtc(dev, crtc, encoder) {
5755 switch (encoder->type) {
5756 case INTEL_OUTPUT_LVDS:
5757 is_lvds = true;
5758 break;
de13a2e3
PZ		 5759 }
5760
5761 num_connectors++;
a07d6787 5762 }
79e53945 5763
5dc5298b
PZ		 5764 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5765 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5766
ff9a6750 5767 ok = ironlake_compute_clocks(crtc, &clock,
de13a2e3 5768 &has_reduced_clock, &reduced_clock);
ee9300bb 5769 if (!ok && !intel_crtc->config.clock_set) {
de13a2e3
PZ		 5770 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5771 return -EINVAL;
79e53945 5772 }
f47709a9
DV		 5773 /* Compat-code for transition, will disappear. */
5774 if (!intel_crtc->config.clock_set) {
5775 intel_crtc->config.dpll.n = clock.n;
5776 intel_crtc->config.dpll.m1 = clock.m1;
5777 intel_crtc->config.dpll.m2 = clock.m2;
5778 intel_crtc->config.dpll.p1 = clock.p1;
5779 intel_crtc->config.dpll.p2 = clock.p2;
5780 }
79e53945 5781
de13a2e3
PZ		 5782 /* Ensure that the cursor is valid for the new mode before changing... */
5783 intel_crtc_update_cursor(crtc, true);
5784
5dc5298b 5785 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 5786 if (intel_crtc->config.has_pch_encoder) {
7429e9d4 5787 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
cbbab5bd 5788 if (has_reduced_clock)
7429e9d4 5789 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 5790
7429e9d4 5791 dpll = ironlake_compute_dpll(intel_crtc,
cbbab5bd
DV		 5792 &fp, &reduced_clock,
5793 has_reduced_clock ? &fp2 : NULL);
5794
959e16d6 5795 intel_crtc->config.dpll_hw_state.dpll = dpll;
66e985c0
DV		 5796 intel_crtc->config.dpll_hw_state.fp0 = fp;
5797 if (has_reduced_clock)
5798 intel_crtc->config.dpll_hw_state.fp1 = fp2;
5799 else
5800 intel_crtc->config.dpll_hw_state.fp1 = fp;
5801
b89a1d39 5802 pll = intel_get_shared_dpll(intel_crtc);
ee7b9f93 5803 if (pll == NULL) {
84f44ce7
VS		 5804 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5805 pipe_name(pipe));
4b645f14
JB		 5806 return -EINVAL;
5807 }
ee7b9f93 5808 } else
e72f9fbf 5809 intel_put_shared_dpll(intel_crtc);
79e53945 5810
03afc4a2
DV		 5811 if (intel_crtc->config.has_dp_encoder)
5812 intel_dp_set_m_n(intel_crtc);
79e53945 5813
bcd644e0
DV		 5814 if (is_lvds && has_reduced_clock && i915_powersave)
5815 intel_crtc->lowfreq_avail = true;
5816 else
5817 intel_crtc->lowfreq_avail = false;
e2b78267
DV		 5818
5819 if (intel_crtc->config.has_pch_encoder) {
5820 pll = intel_crtc_to_shared_dpll(intel_crtc);
5821
652c393a
JB		 5822 }
5823
8a654f3b 5824 intel_set_pipe_timings(intel_crtc);
5eddb70b 5825
ca3a0ff8 5826 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5827 intel_cpu_transcoder_set_m_n(intel_crtc,
5828 &intel_crtc->config.fdi_m_n);
5829 }
2c07245f 5830
ebfd86fd
DV		 5831 if (IS_IVYBRIDGE(dev))
5832 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
79e53945 5833
6ff93609 5834 ironlake_set_pipeconf(crtc);
79e53945 5835
a1f9e77e
PZ		 5836 /* Set up the display plane register */
5837 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5838 POSTING_READ(DSPCNTR(plane));
79e53945 5839
94352cf9 5840 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd 5841
1857e1da 5842 return ret;
79e53945
JB		 5843}
5844
72419203
DV		 5845static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5846 struct intel_crtc_config *pipe_config)
5847{
5848 struct drm_device *dev = crtc->base.dev;
5849 struct drm_i915_private *dev_priv = dev->dev_private;
5850 enum transcoder transcoder = pipe_config->cpu_transcoder;
5851
5852 pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5853 pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5854 pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5855 & ~TU_SIZE_MASK;
5856 pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5857 pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5858 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5859}
5860
2fa2fe9a
DV		 5861static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5862 struct intel_crtc_config *pipe_config)
5863{
5864 struct drm_device *dev = crtc->base.dev;
5865 struct drm_i915_private *dev_priv = dev->dev_private;
5866 uint32_t tmp;
5867
5868 tmp = I915_READ(PF_CTL(crtc->pipe));
5869
5870 if (tmp & PF_ENABLE) {
5871 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5872 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 5873
5874 /* We currently do not free assignements of panel fitters on
5875 * ivb/hsw (since we don't use the higher upscaling modes which
5876 * differentiates them) so just WARN about this case for now. */
5877 if (IS_GEN7(dev)) {
5878 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5879 PF_PIPE_SEL_IVB(crtc->pipe));
5880 }
2fa2fe9a 5881 }
79e53945
JB		 5882}
5883
0e8ffe1b
DV		 5884static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5885 struct intel_crtc_config *pipe_config)
5886{
5887 struct drm_device *dev = crtc->base.dev;
5888 struct drm_i915_private *dev_priv = dev->dev_private;
5889 uint32_t tmp;
5890
e143a21c 5891 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 5892 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 5893
0e8ffe1b
DV		 5894 tmp = I915_READ(PIPECONF(crtc->pipe));
5895 if (!(tmp & PIPECONF_ENABLE))
5896 return false;
5897
ab9412ba 5898 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 5899 struct intel_shared_dpll *pll;
5900
88adfff1
DV		 5901 pipe_config->has_pch_encoder = true;
5902
627eb5a3
DV		 5903 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5904 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5905 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 5906
5907 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 5908
c0d43d62 5909 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 5910 pipe_config->shared_dpll =
5911 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 5912 } else {
5913 tmp = I915_READ(PCH_DPLL_SEL);
5914 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
5915 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
5916 else
5917 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
5918 }
66e985c0
DV		 5919
5920 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
5921
5922 WARN_ON(!pll->get_hw_state(dev_priv, pll,
5923 &pipe_config->dpll_hw_state));
c93f54cf
DV		 5924
5925 tmp = pipe_config->dpll_hw_state.dpll;
5926 pipe_config->pixel_multiplier =
5927 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
5928 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
6c49f241
DV		 5929 } else {
5930 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 5931 }
5932
1bd1bd80
DV		 5933 intel_get_pipe_timings(crtc, pipe_config);
5934
2fa2fe9a
DV		 5935 ironlake_get_pfit_config(crtc, pipe_config);
5936
0e8ffe1b
DV		 5937 return true;
5938}
5939
be256dc7
PZ		 5940static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
5941{
5942 struct drm_device *dev = dev_priv->dev;
5943 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
5944 struct intel_crtc *crtc;
5945 unsigned long irqflags;
bd633a7c 5946 uint32_t val;
be256dc7
PZ		 5947
5948 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
5949 WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
5950 pipe_name(crtc->pipe));
5951
5952 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
5953 WARN(plls->spll_refcount, "SPLL enabled\n");
5954 WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
5955 WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
5956 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
5957 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
5958 "CPU PWM1 enabled\n");
5959 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
5960 "CPU PWM2 enabled\n");
5961 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
5962 "PCH PWM1 enabled\n");
5963 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
5964 "Utility pin enabled\n");
5965 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
5966
5967 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
5968 val = I915_READ(DEIMR);
5969 WARN((val & ~DE_PCH_EVENT_IVB) != val,
5970 "Unexpected DEIMR bits enabled: 0x%x\n", val);
5971 val = I915_READ(SDEIMR);
bd633a7c 5972 WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
be256dc7
PZ		 5973 "Unexpected SDEIMR bits enabled: 0x%x\n", val);
5974 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
5975}
5976
5977/*
5978 * This function implements pieces of two sequences from BSpec:
5979 * - Sequence for display software to disable LCPLL
5980 * - Sequence for display software to allow package C8+
5981 * The steps implemented here are just the steps that actually touch the LCPLL
5982 * register. Callers should take care of disabling all the display engine
5983 * functions, doing the mode unset, fixing interrupts, etc.
5984 */
5985void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
5986 bool switch_to_fclk, bool allow_power_down)
5987{
5988 uint32_t val;
5989
5990 assert_can_disable_lcpll(dev_priv);
5991
5992 val = I915_READ(LCPLL_CTL);
5993
5994 if (switch_to_fclk) {
5995 val |= LCPLL_CD_SOURCE_FCLK;
5996 I915_WRITE(LCPLL_CTL, val);
5997
5998 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
5999 LCPLL_CD_SOURCE_FCLK_DONE, 1))
6000 DRM_ERROR("Switching to FCLK failed\n");
6001
6002 val = I915_READ(LCPLL_CTL);
6003 }
6004
6005 val |= LCPLL_PLL_DISABLE;
6006 I915_WRITE(LCPLL_CTL, val);
6007 POSTING_READ(LCPLL_CTL);
6008
6009 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6010 DRM_ERROR("LCPLL still locked\n");
6011
6012 val = I915_READ(D_COMP);
6013 val |= D_COMP_COMP_DISABLE;
6014 I915_WRITE(D_COMP, val);
6015 POSTING_READ(D_COMP);
6016 ndelay(100);
6017
6018 if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6019 DRM_ERROR("D_COMP RCOMP still in progress\n");
6020
6021 if (allow_power_down) {
6022 val = I915_READ(LCPLL_CTL);
6023 val |= LCPLL_POWER_DOWN_ALLOW;
6024 I915_WRITE(LCPLL_CTL, val);
6025 POSTING_READ(LCPLL_CTL);
6026 }
6027}
6028
6029/*
6030 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6031 * source.
6032 */
6033void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6034{
6035 uint32_t val;
6036
6037 val = I915_READ(LCPLL_CTL);
6038
6039 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6040 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6041 return;
6042
215733fa
PZ		 6043 /* Make sure we're not on PC8 state before disabling PC8, otherwise
6044 * we'll hang the machine! */
6045 dev_priv->uncore.funcs.force_wake_get(dev_priv);
6046
be256dc7
PZ		 6047 if (val & LCPLL_POWER_DOWN_ALLOW) {
6048 val &= ~LCPLL_POWER_DOWN_ALLOW;
6049 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 6050 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 6051 }
6052
6053 val = I915_READ(D_COMP);
6054 val |= D_COMP_COMP_FORCE;
6055 val &= ~D_COMP_COMP_DISABLE;
6056 I915_WRITE(D_COMP, val);
35d8f2eb 6057 POSTING_READ(D_COMP);
be256dc7
PZ		 6058
6059 val = I915_READ(LCPLL_CTL);
6060 val &= ~LCPLL_PLL_DISABLE;
6061 I915_WRITE(LCPLL_CTL, val);
6062
6063 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6064 DRM_ERROR("LCPLL not locked yet\n");
6065
6066 if (val & LCPLL_CD_SOURCE_FCLK) {
6067 val = I915_READ(LCPLL_CTL);
6068 val &= ~LCPLL_CD_SOURCE_FCLK;
6069 I915_WRITE(LCPLL_CTL, val);
6070
6071 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6072 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6073 DRM_ERROR("Switching back to LCPLL failed\n");
6074 }
215733fa
PZ		 6075
6076 dev_priv->uncore.funcs.force_wake_put(dev_priv);
be256dc7
PZ		 6077}
6078
c67a470b
PZ		 6079void hsw_enable_pc8_work(struct work_struct *__work)
6080{
6081 struct drm_i915_private *dev_priv =
6082 container_of(to_delayed_work(__work), struct drm_i915_private,
6083 pc8.enable_work);
6084 struct drm_device *dev = dev_priv->dev;
6085 uint32_t val;
6086
6087 if (dev_priv->pc8.enabled)
6088 return;
6089
6090 DRM_DEBUG_KMS("Enabling package C8+\n");
6091
6092 dev_priv->pc8.enabled = true;
6093
6094 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6095 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6096 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6097 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6098 }
6099
6100 lpt_disable_clkout_dp(dev);
6101 hsw_pc8_disable_interrupts(dev);
6102 hsw_disable_lcpll(dev_priv, true, true);
6103}
6104
6105static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6106{
6107 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6108 WARN(dev_priv->pc8.disable_count < 1,
6109 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6110
6111 dev_priv->pc8.disable_count--;
6112 if (dev_priv->pc8.disable_count != 0)
6113 return;
6114
6115 schedule_delayed_work(&dev_priv->pc8.enable_work,
90058745 6116 msecs_to_jiffies(i915_pc8_timeout));
c67a470b
PZ		 6117}
6118
6119static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6120{
6121 struct drm_device *dev = dev_priv->dev;
6122 uint32_t val;
6123
6124 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6125 WARN(dev_priv->pc8.disable_count < 0,
6126 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6127
6128 dev_priv->pc8.disable_count++;
6129 if (dev_priv->pc8.disable_count != 1)
6130 return;
6131
6132 cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6133 if (!dev_priv->pc8.enabled)
6134 return;
6135
6136 DRM_DEBUG_KMS("Disabling package C8+\n");
6137
6138 hsw_restore_lcpll(dev_priv);
6139 hsw_pc8_restore_interrupts(dev);
6140 lpt_init_pch_refclk(dev);
6141
6142 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6143 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6144 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6145 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6146 }
6147
6148 intel_prepare_ddi(dev);
6149 i915_gem_init_swizzling(dev);
6150 mutex_lock(&dev_priv->rps.hw_lock);
6151 gen6_update_ring_freq(dev);
6152 mutex_unlock(&dev_priv->rps.hw_lock);
6153 dev_priv->pc8.enabled = false;
6154}
6155
6156void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6157{
6158 mutex_lock(&dev_priv->pc8.lock);
6159 __hsw_enable_package_c8(dev_priv);
6160 mutex_unlock(&dev_priv->pc8.lock);
6161}
6162
6163void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6164{
6165 mutex_lock(&dev_priv->pc8.lock);
6166 __hsw_disable_package_c8(dev_priv);
6167 mutex_unlock(&dev_priv->pc8.lock);
6168}
6169
6170static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6171{
6172 struct drm_device *dev = dev_priv->dev;
6173 struct intel_crtc *crtc;
6174 uint32_t val;
6175
6176 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6177 if (crtc->base.enabled)
6178 return false;
6179
6180 /* This case is still possible since we have the i915.disable_power_well
6181 * parameter and also the KVMr or something else might be requesting the
6182 * power well. */
6183 val = I915_READ(HSW_PWR_WELL_DRIVER);
6184 if (val != 0) {
6185 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6186 return false;
6187 }
6188
6189 return true;
6190}
6191
6192/* Since we're called from modeset_global_resources there's no way to
6193 * symmetrically increase and decrease the refcount, so we use
6194 * dev_priv->pc8.requirements_met to track whether we already have the refcount
6195 * or not.
6196 */
6197static void hsw_update_package_c8(struct drm_device *dev)
6198{
6199 struct drm_i915_private *dev_priv = dev->dev_private;
6200 bool allow;
6201
6202 if (!i915_enable_pc8)
6203 return;
6204
6205 mutex_lock(&dev_priv->pc8.lock);
6206
6207 allow = hsw_can_enable_package_c8(dev_priv);
6208
6209 if (allow == dev_priv->pc8.requirements_met)
6210 goto done;
6211
6212 dev_priv->pc8.requirements_met = allow;
6213
6214 if (allow)
6215 __hsw_enable_package_c8(dev_priv);
6216 else
6217 __hsw_disable_package_c8(dev_priv);
6218
6219done:
6220 mutex_unlock(&dev_priv->pc8.lock);
6221}
6222
6223static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6224{
6225 if (!dev_priv->pc8.gpu_idle) {
6226 dev_priv->pc8.gpu_idle = true;
6227 hsw_enable_package_c8(dev_priv);
6228 }
6229}
6230
6231static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6232{
6233 if (dev_priv->pc8.gpu_idle) {
6234 dev_priv->pc8.gpu_idle = false;
6235 hsw_disable_package_c8(dev_priv);
6236 }
be256dc7
PZ		 6237}
6238
d6dd9eb1
DV		 6239static void haswell_modeset_global_resources(struct drm_device *dev)
6240{
d6dd9eb1
DV		 6241 bool enable = false;
6242 struct intel_crtc *crtc;
d6dd9eb1
DV		 6243
6244 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
e7a639c4
DV		 6245 if (!crtc->base.enabled)
6246 continue;
d6dd9eb1 6247
e7a639c4
DV		 6248 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
6249 crtc->config.cpu_transcoder != TRANSCODER_EDP)
d6dd9eb1
DV		 6250 enable = true;
6251 }
6252
d6dd9eb1 6253 intel_set_power_well(dev, enable);
c67a470b
PZ		 6254
6255 hsw_update_package_c8(dev);
d6dd9eb1
DV		 6256}
6257
09b4ddf9 6258static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 6259 int x, int y,
6260 struct drm_framebuffer *fb)
6261{
6262 struct drm_device *dev = crtc->dev;
6263 struct drm_i915_private *dev_priv = dev->dev_private;
6264 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
09b4ddf9 6265 int plane = intel_crtc->plane;
09b4ddf9 6266 int ret;
09b4ddf9 6267
ff9a6750 6268 if (!intel_ddi_pll_mode_set(crtc))
6441ab5f
PZ		 6269 return -EINVAL;
6270
09b4ddf9
PZ		 6271 /* Ensure that the cursor is valid for the new mode before changing... */
6272 intel_crtc_update_cursor(crtc, true);
6273
03afc4a2
DV		 6274 if (intel_crtc->config.has_dp_encoder)
6275 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 6276
6277 intel_crtc->lowfreq_avail = false;
09b4ddf9 6278
8a654f3b 6279 intel_set_pipe_timings(intel_crtc);
09b4ddf9 6280
ca3a0ff8 6281 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 6282 intel_cpu_transcoder_set_m_n(intel_crtc,
6283 &intel_crtc->config.fdi_m_n);
6284 }
09b4ddf9 6285
6ff93609 6286 haswell_set_pipeconf(crtc);
09b4ddf9 6287
50f3b016 6288 intel_set_pipe_csc(crtc);
86d3efce 6289
09b4ddf9 6290 /* Set up the display plane register */
86d3efce 6291 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 6292 POSTING_READ(DSPCNTR(plane));
6293
6294 ret = intel_pipe_set_base(crtc, x, y, fb);
6295
1f803ee5 6296 return ret;
79e53945
JB		 6297}
6298
0e8ffe1b
DV		 6299static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6300 struct intel_crtc_config *pipe_config)
6301{
6302 struct drm_device *dev = crtc->base.dev;
6303 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 6304 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 6305 uint32_t tmp;
6306
e143a21c 6307 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 6308 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6309
eccb140b
DV		 6310 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6311 if (tmp & TRANS_DDI_FUNC_ENABLE) {
6312 enum pipe trans_edp_pipe;
6313 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6314 default:
6315 WARN(1, "unknown pipe linked to edp transcoder\n");
6316 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6317 case TRANS_DDI_EDP_INPUT_A_ON:
6318 trans_edp_pipe = PIPE_A;
6319 break;
6320 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6321 trans_edp_pipe = PIPE_B;
6322 break;
6323 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6324 trans_edp_pipe = PIPE_C;
6325 break;
6326 }
6327
6328 if (trans_edp_pipe == crtc->pipe)
6329 pipe_config->cpu_transcoder = TRANSCODER_EDP;
6330 }
6331
b97186f0 6332 if (!intel_display_power_enabled(dev,
eccb140b 6333 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 6334 return false;
6335
eccb140b 6336 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 6337 if (!(tmp & PIPECONF_ENABLE))
6338 return false;
6339
88adfff1 6340 /*
f196e6be 6341 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV		 6342 * DDI E. So just check whether this pipe is wired to DDI E and whether
6343 * the PCH transcoder is on.
6344 */
eccb140b 6345 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
88adfff1 6346 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
ab9412ba 6347 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
88adfff1
DV		 6348 pipe_config->has_pch_encoder = true;
6349
627eb5a3
DV		 6350 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6351 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6352 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6353
6354 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 6355 }
6356
1bd1bd80
DV		 6357 intel_get_pipe_timings(crtc, pipe_config);
6358
2fa2fe9a
DV		 6359 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6360 if (intel_display_power_enabled(dev, pfit_domain))
6361 ironlake_get_pfit_config(crtc, pipe_config);
88adfff1 6362
42db64ef
PZ		 6363 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6364 (I915_READ(IPS_CTL) & IPS_ENABLE);
6365
6c49f241
DV		 6366 pipe_config->pixel_multiplier = 1;
6367
0e8ffe1b
DV		 6368 return true;
6369}
6370
f564048e 6371static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 6372 int x, int y,
94352cf9 6373 struct drm_framebuffer *fb)
f564048e
EA		 6374{
6375 struct drm_device *dev = crtc->dev;
6376 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19 6377 struct intel_encoder *encoder;
0b701d27 6378 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5 6379 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 6380 int pipe = intel_crtc->pipe;
f564048e
EA		 6381 int ret;
6382
0b701d27 6383 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6384
b8cecdf5
DV		 6385 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6386
79e53945 6387 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6388
9256aa19
DV		 6389 if (ret != 0)
6390 return ret;
6391
6392 for_each_encoder_on_crtc(dev, crtc, encoder) {
6393 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6394 encoder->base.base.id,
6395 drm_get_encoder_name(&encoder->base),
6396 mode->base.id, mode->name);
36f2d1f1 6397 encoder->mode_set(encoder);
9256aa19
DV		 6398 }
6399
6400 return 0;
79e53945
JB		 6401}
6402
3a9627f4
WF		 6403static bool intel_eld_uptodate(struct drm_connector *connector,
6404 int reg_eldv, uint32_t bits_eldv,
6405 int reg_elda, uint32_t bits_elda,
6406 int reg_edid)
6407{
6408 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6409 uint8_t *eld = connector->eld;
6410 uint32_t i;
6411
6412 i = I915_READ(reg_eldv);
6413 i &= bits_eldv;
6414
6415 if (!eld[0])
6416 return !i;
6417
6418 if (!i)
6419 return false;
6420
6421 i = I915_READ(reg_elda);
6422 i &= ~bits_elda;
6423 I915_WRITE(reg_elda, i);
6424
6425 for (i = 0; i < eld[2]; i++)
6426 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6427 return false;
6428
6429 return true;
6430}
6431
e0dac65e
WF		 6432static void g4x_write_eld(struct drm_connector *connector,
6433 struct drm_crtc *crtc)
6434{
6435 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6436 uint8_t *eld = connector->eld;
6437 uint32_t eldv;
6438 uint32_t len;
6439 uint32_t i;
6440
6441 i = I915_READ(G4X_AUD_VID_DID);
6442
6443 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6444 eldv = G4X_ELDV_DEVCL_DEVBLC;
6445 else
6446 eldv = G4X_ELDV_DEVCTG;
6447
3a9627f4
WF		 6448 if (intel_eld_uptodate(connector,
6449 G4X_AUD_CNTL_ST, eldv,
6450 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6451 G4X_HDMIW_HDMIEDID))
6452 return;
6453
e0dac65e
WF		 6454 i = I915_READ(G4X_AUD_CNTL_ST);
6455 i &= ~(eldv | G4X_ELD_ADDR);
6456 len = (i >> 9) & 0x1f; /* ELD buffer size */
6457 I915_WRITE(G4X_AUD_CNTL_ST, i);
6458
6459 if (!eld[0])
6460 return;
6461
6462 len = min_t(uint8_t, eld[2], len);
6463 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6464 for (i = 0; i < len; i++)
6465 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6466
6467 i = I915_READ(G4X_AUD_CNTL_ST);
6468 i |= eldv;
6469 I915_WRITE(G4X_AUD_CNTL_ST, i);
6470}
6471
83358c85
WX		 6472static void haswell_write_eld(struct drm_connector *connector,
6473 struct drm_crtc *crtc)
6474{
6475 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6476 uint8_t *eld = connector->eld;
6477 struct drm_device *dev = crtc->dev;
7b9f35a6 6478 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6479 uint32_t eldv;
6480 uint32_t i;
6481 int len;
6482 int pipe = to_intel_crtc(crtc)->pipe;
6483 int tmp;
6484
6485 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6486 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6487 int aud_config = HSW_AUD_CFG(pipe);
6488 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6489
6490
6491 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6492
6493 /* Audio output enable */
6494 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6495 tmp = I915_READ(aud_cntrl_st2);
6496 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6497 I915_WRITE(aud_cntrl_st2, tmp);
6498
6499 /* Wait for 1 vertical blank */
6500 intel_wait_for_vblank(dev, pipe);
6501
6502 /* Set ELD valid state */
6503 tmp = I915_READ(aud_cntrl_st2);
6504 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6505 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6506 I915_WRITE(aud_cntrl_st2, tmp);
6507 tmp = I915_READ(aud_cntrl_st2);
6508 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6509
6510 /* Enable HDMI mode */
6511 tmp = I915_READ(aud_config);
6512 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6513 /* clear N_programing_enable and N_value_index */
6514 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6515 I915_WRITE(aud_config, tmp);
6516
6517 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6518
6519 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6520 intel_crtc->eld_vld = true;
83358c85
WX		 6521
6522 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6523 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6524 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6525 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6526 } else
6527 I915_WRITE(aud_config, 0);
6528
6529 if (intel_eld_uptodate(connector,
6530 aud_cntrl_st2, eldv,
6531 aud_cntl_st, IBX_ELD_ADDRESS,
6532 hdmiw_hdmiedid))
6533 return;
6534
6535 i = I915_READ(aud_cntrl_st2);
6536 i &= ~eldv;
6537 I915_WRITE(aud_cntrl_st2, i);
6538
6539 if (!eld[0])
6540 return;
6541
6542 i = I915_READ(aud_cntl_st);
6543 i &= ~IBX_ELD_ADDRESS;
6544 I915_WRITE(aud_cntl_st, i);
6545 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6546 DRM_DEBUG_DRIVER("port num:%d\n", i);
6547
6548 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6549 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6550 for (i = 0; i < len; i++)
6551 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6552
6553 i = I915_READ(aud_cntrl_st2);
6554 i |= eldv;
6555 I915_WRITE(aud_cntrl_st2, i);
6556
6557}
6558
e0dac65e
WF		 6559static void ironlake_write_eld(struct drm_connector *connector,
6560 struct drm_crtc *crtc)
6561{
6562 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6563 uint8_t *eld = connector->eld;
6564 uint32_t eldv;
6565 uint32_t i;
6566 int len;
6567 int hdmiw_hdmiedid;
b6daa025 6568 int aud_config;
e0dac65e
WF		 6569 int aud_cntl_st;
6570 int aud_cntrl_st2;
9b138a83 6571 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6572
b3f33cbf 6573 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6574 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6575 aud_config = IBX_AUD_CFG(pipe);
6576 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6577 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6578 } else {
9b138a83
WX		 6579 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6580 aud_config = CPT_AUD_CFG(pipe);
6581 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6582 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6583 }
6584
9b138a83 6585 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6586
6587 i = I915_READ(aud_cntl_st);
9b138a83 6588 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6589 if (!i) {
6590 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6591 /* operate blindly on all ports */
1202b4c6
WF		 6592 eldv = IBX_ELD_VALIDB;
6593 eldv |= IBX_ELD_VALIDB << 4;
6594 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 6595 } else {
2582a850 6596 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 6597 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6598 }
6599
3a9627f4
WF		 6600 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6601 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6602 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6603 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6604 } else
6605 I915_WRITE(aud_config, 0);
e0dac65e 6606
3a9627f4
WF		 6607 if (intel_eld_uptodate(connector,
6608 aud_cntrl_st2, eldv,
6609 aud_cntl_st, IBX_ELD_ADDRESS,
6610 hdmiw_hdmiedid))
6611 return;
6612
e0dac65e
WF		 6613 i = I915_READ(aud_cntrl_st2);
6614 i &= ~eldv;
6615 I915_WRITE(aud_cntrl_st2, i);
6616
6617 if (!eld[0])
6618 return;
6619
e0dac65e 6620 i = I915_READ(aud_cntl_st);
1202b4c6 6621 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6622 I915_WRITE(aud_cntl_st, i);
6623
6624 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6625 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6626 for (i = 0; i < len; i++)
6627 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6628
6629 i = I915_READ(aud_cntrl_st2);
6630 i |= eldv;
6631 I915_WRITE(aud_cntrl_st2, i);
6632}
6633
6634void intel_write_eld(struct drm_encoder *encoder,
6635 struct drm_display_mode *mode)
6636{
6637 struct drm_crtc *crtc = encoder->crtc;
6638 struct drm_connector *connector;
6639 struct drm_device *dev = encoder->dev;
6640 struct drm_i915_private *dev_priv = dev->dev_private;
6641
6642 connector = drm_select_eld(encoder, mode);
6643 if (!connector)
6644 return;
6645
6646 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6647 connector->base.id,
6648 drm_get_connector_name(connector),
6649 connector->encoder->base.id,
6650 drm_get_encoder_name(connector->encoder));
6651
6652 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6653
6654 if (dev_priv->display.write_eld)
6655 dev_priv->display.write_eld(connector, crtc);
6656}
6657
79e53945
JB		 6658/** Loads the palette/gamma unit for the CRTC with the prepared values */
6659void intel_crtc_load_lut(struct drm_crtc *crtc)
6660{
6661 struct drm_device *dev = crtc->dev;
6662 struct drm_i915_private *dev_priv = dev->dev_private;
6663 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
42db64ef
PZ		 6664 enum pipe pipe = intel_crtc->pipe;
6665 int palreg = PALETTE(pipe);
79e53945 6666 int i;
42db64ef 6667 bool reenable_ips = false;
79e53945
JB		 6668
6669 /* The clocks have to be on to load the palette. */
aed3f09d 6670 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6671 return;
6672
23538ef1
JN		 6673 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
6674 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
6675 assert_dsi_pll_enabled(dev_priv);
6676 else
6677 assert_pll_enabled(dev_priv, pipe);
6678 }
14420bd0 6679
f2b115e6 6680 /* use legacy palette for Ironlake */
bad720ff 6681 if (HAS_PCH_SPLIT(dev))
42db64ef
PZ		 6682 palreg = LGC_PALETTE(pipe);
6683
6684 /* Workaround : Do not read or write the pipe palette/gamma data while
6685 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6686 */
6687 if (intel_crtc->config.ips_enabled &&
6688 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6689 GAMMA_MODE_MODE_SPLIT)) {
6690 hsw_disable_ips(intel_crtc);
6691 reenable_ips = true;
6692 }
2c07245f 6693
79e53945
JB		 6694 for (i = 0; i < 256; i++) {
6695 I915_WRITE(palreg + 4 * i,
6696 (intel_crtc->lut_r[i] << 16) |
6697 (intel_crtc->lut_g[i] << 8) |
6698 intel_crtc->lut_b[i]);
6699 }
42db64ef
PZ		 6700
6701 if (reenable_ips)
6702 hsw_enable_ips(intel_crtc);
79e53945
JB		 6703}
6704
560b85bb
CW		 6705static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6706{
6707 struct drm_device *dev = crtc->dev;
6708 struct drm_i915_private *dev_priv = dev->dev_private;
6709 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6710 bool visible = base != 0;
6711 u32 cntl;
6712
6713 if (intel_crtc->cursor_visible == visible)
6714 return;
6715
9db4a9c7 6716 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6717 if (visible) {
6718 /* On these chipsets we can only modify the base whilst
6719 * the cursor is disabled.
6720 */
9db4a9c7 6721 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6722
6723 cntl &= ~(CURSOR_FORMAT_MASK);
6724 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6725 cntl |= CURSOR_ENABLE |
6726 CURSOR_GAMMA_ENABLE |
6727 CURSOR_FORMAT_ARGB;
6728 } else
6729 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6730 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6731
6732 intel_crtc->cursor_visible = visible;
6733}
6734
6735static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6736{
6737 struct drm_device *dev = crtc->dev;
6738 struct drm_i915_private *dev_priv = dev->dev_private;
6739 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6740 int pipe = intel_crtc->pipe;
6741 bool visible = base != 0;
6742
6743 if (intel_crtc->cursor_visible != visible) {
548f245b 6744 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6745 if (base) {
6746 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6747 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6748 cntl |= pipe << 28; /* Connect to correct pipe */
6749 } else {
6750 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6751 cntl |= CURSOR_MODE_DISABLE;
6752 }
9db4a9c7 6753 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6754
6755 intel_crtc->cursor_visible = visible;
6756 }
6757 /* and commit changes on next vblank */
9db4a9c7 6758 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6759}
6760
65a21cd6
JB		 6761static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6762{
6763 struct drm_device *dev = crtc->dev;
6764 struct drm_i915_private *dev_priv = dev->dev_private;
6765 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6766 int pipe = intel_crtc->pipe;
6767 bool visible = base != 0;
6768
6769 if (intel_crtc->cursor_visible != visible) {
6770 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6771 if (base) {
6772 cntl &= ~CURSOR_MODE;
6773 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6774 } else {
6775 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6776 cntl |= CURSOR_MODE_DISABLE;
6777 }
1f5d76db 6778 if (IS_HASWELL(dev)) {
86d3efce 6779 cntl |= CURSOR_PIPE_CSC_ENABLE;
1f5d76db
PZ		 6780 cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
6781 }
65a21cd6
JB		 6782 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6783
6784 intel_crtc->cursor_visible = visible;
6785 }
6786 /* and commit changes on next vblank */
6787 I915_WRITE(CURBASE_IVB(pipe), base);
6788}
6789
cda4b7d3 6790/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6791static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6792 bool on)
cda4b7d3
CW		 6793{
6794 struct drm_device *dev = crtc->dev;
6795 struct drm_i915_private *dev_priv = dev->dev_private;
6796 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6797 int pipe = intel_crtc->pipe;
6798 int x = intel_crtc->cursor_x;
6799 int y = intel_crtc->cursor_y;
560b85bb 6800 u32 base, pos;
cda4b7d3
CW		 6801 bool visible;
6802
6803 pos = 0;
6804
6b383a7f 6805 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6806 base = intel_crtc->cursor_addr;
6807 if (x > (int) crtc->fb->width)
6808 base = 0;
6809
6810 if (y > (int) crtc->fb->height)
6811 base = 0;
6812 } else
6813 base = 0;
6814
6815 if (x < 0) {
6816 if (x + intel_crtc->cursor_width < 0)
6817 base = 0;
6818
6819 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6820 x = -x;
6821 }
6822 pos |= x << CURSOR_X_SHIFT;
6823
6824 if (y < 0) {
6825 if (y + intel_crtc->cursor_height < 0)
6826 base = 0;
6827
6828 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6829 y = -y;
6830 }
6831 pos |= y << CURSOR_Y_SHIFT;
6832
6833 visible = base != 0;
560b85bb 6834 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6835 return;
6836
0cd83aa9 6837 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6838 I915_WRITE(CURPOS_IVB(pipe), pos);
6839 ivb_update_cursor(crtc, base);
6840 } else {
6841 I915_WRITE(CURPOS(pipe), pos);
6842 if (IS_845G(dev) || IS_I865G(dev))
6843 i845_update_cursor(crtc, base);
6844 else
6845 i9xx_update_cursor(crtc, base);
6846 }
cda4b7d3
CW		 6847}
6848
79e53945 6849static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6850 struct drm_file *file,
79e53945
JB		 6851 uint32_t handle,
6852 uint32_t width, uint32_t height)
6853{
6854 struct drm_device *dev = crtc->dev;
6855 struct drm_i915_private *dev_priv = dev->dev_private;
6856 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6857 struct drm_i915_gem_object *obj;
cda4b7d3 6858 uint32_t addr;
3f8bc370 6859 int ret;
79e53945 6860
79e53945
JB		 6861 /* if we want to turn off the cursor ignore width and height */
6862 if (!handle) {
28c97730 6863 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6864 addr = 0;
05394f39 6865 obj = NULL;
5004417d 6866 mutex_lock(&dev->struct_mutex);
3f8bc370 6867 goto finish;
79e53945
JB		 6868 }
6869
6870 /* Currently we only support 64x64 cursors */
6871 if (width != 64 || height != 64) {
6872 DRM_ERROR("we currently only support 64x64 cursors\n");
6873 return -EINVAL;
6874 }
6875
05394f39 6876 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6877 if (&obj->base == NULL)
79e53945
JB		 6878 return -ENOENT;
6879
05394f39 6880 if (obj->base.size < width * height * 4) {
79e53945 6881 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6882 ret = -ENOMEM;
6883 goto fail;
79e53945
JB		 6884 }
6885
71acb5eb 6886 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6887 mutex_lock(&dev->struct_mutex);
b295d1b6 6888 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 6889 unsigned alignment;
6890
d9e86c0e
CW		 6891 if (obj->tiling_mode) {
6892 DRM_ERROR("cursor cannot be tiled\n");
6893 ret = -EINVAL;
6894 goto fail_locked;
6895 }
6896
693db184
CW		 6897 /* Note that the w/a also requires 2 PTE of padding following
6898 * the bo. We currently fill all unused PTE with the shadow
6899 * page and so we should always have valid PTE following the
6900 * cursor preventing the VT-d warning.
6901 */
6902 alignment = 0;
6903 if (need_vtd_wa(dev))
6904 alignment = 64*1024;
6905
6906 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 6907 if (ret) {
6908 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6909 goto fail_locked;
e7b526bb
CW		 6910 }
6911
d9e86c0e
CW		 6912 ret = i915_gem_object_put_fence(obj);
6913 if (ret) {
2da3b9b9 6914 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6915 goto fail_unpin;
6916 }
6917
f343c5f6 6918 addr = i915_gem_obj_ggtt_offset(obj);
71acb5eb 6919 } else {
6eeefaf3 6920 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6921 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6922 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6923 align);
71acb5eb
DA		 6924 if (ret) {
6925 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6926 goto fail_locked;
71acb5eb 6927 }
05394f39 6928 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6929 }
6930
a6c45cf0 6931 if (IS_GEN2(dev))
14b60391
JB		 6932 I915_WRITE(CURSIZE, (height << 12) | width);
6933
3f8bc370 6934 finish:
3f8bc370 6935 if (intel_crtc->cursor_bo) {
b295d1b6 6936 if (dev_priv->info->cursor_needs_physical) {
05394f39 6937 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6938 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6939 } else
cc98b413 6940 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
05394f39 6941 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6942 }
80824003 6943
7f9872e0 6944 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6945
6946 intel_crtc->cursor_addr = addr;
05394f39 6947 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6948 intel_crtc->cursor_width = width;
6949 intel_crtc->cursor_height = height;
6950
40ccc72b 6951 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
3f8bc370 6952
79e53945 6953 return 0;
e7b526bb 6954fail_unpin:
cc98b413 6955 i915_gem_object_unpin_from_display_plane(obj);
7f9872e0 6956fail_locked:
34b8686e 6957 mutex_unlock(&dev->struct_mutex);
bc9025bd 6958fail:
05394f39 6959 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6960 return ret;
79e53945
JB		 6961}
6962
6963static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6964{
79e53945 6965 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6966
cda4b7d3
CW		 6967 intel_crtc->cursor_x = x;
6968 intel_crtc->cursor_y = y;
652c393a 6969
40ccc72b 6970 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
79e53945
JB		 6971
6972 return 0;
6973}
6974
6975/** Sets the color ramps on behalf of RandR */
6976void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6977 u16 blue, int regno)
6978{
6979 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6980
6981 intel_crtc->lut_r[regno] = red >> 8;
6982 intel_crtc->lut_g[regno] = green >> 8;
6983 intel_crtc->lut_b[regno] = blue >> 8;
6984}
6985
b8c00ac5
DA		 6986void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6987 u16 *blue, int regno)
6988{
6989 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6990
6991 *red = intel_crtc->lut_r[regno] << 8;
6992 *green = intel_crtc->lut_g[regno] << 8;
6993 *blue = intel_crtc->lut_b[regno] << 8;
6994}
6995
79e53945 6996static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6997 u16 *blue, uint32_t start, uint32_t size)
79e53945 6998{
7203425a 6999 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 7000 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 7001
7203425a 7002 for (i = start; i < end; i++) {
79e53945
JB		 7003 intel_crtc->lut_r[i] = red[i] >> 8;
7004 intel_crtc->lut_g[i] = green[i] >> 8;
7005 intel_crtc->lut_b[i] = blue[i] >> 8;
7006 }
7007
7008 intel_crtc_load_lut(crtc);
7009}
7010
79e53945
JB		 7011/* VESA 640x480x72Hz mode to set on the pipe */
7012static struct drm_display_mode load_detect_mode = {
7013 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7014 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7015};
7016
d2dff872
CW		 7017static struct drm_framebuffer *
7018intel_framebuffer_create(struct drm_device *dev,
308e5bcb 7019 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 7020 struct drm_i915_gem_object *obj)
7021{
7022 struct intel_framebuffer *intel_fb;
7023 int ret;
7024
7025 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7026 if (!intel_fb) {
7027 drm_gem_object_unreference_unlocked(&obj->base);
7028 return ERR_PTR(-ENOMEM);
7029 }
7030
7031 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7032 if (ret) {
7033 drm_gem_object_unreference_unlocked(&obj->base);
7034 kfree(intel_fb);
7035 return ERR_PTR(ret);
7036 }
7037
7038 return &intel_fb->base;
7039}
7040
7041static u32
7042intel_framebuffer_pitch_for_width(int width, int bpp)
7043{
7044 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7045 return ALIGN(pitch, 64);
7046}
7047
7048static u32
7049intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7050{
7051 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7052 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7053}
7054
7055static struct drm_framebuffer *
7056intel_framebuffer_create_for_mode(struct drm_device *dev,
7057 struct drm_display_mode *mode,
7058 int depth, int bpp)
7059{
7060 struct drm_i915_gem_object *obj;
0fed39bd 7061 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 7062
7063 obj = i915_gem_alloc_object(dev,
7064 intel_framebuffer_size_for_mode(mode, bpp));
7065 if (obj == NULL)
7066 return ERR_PTR(-ENOMEM);
7067
7068 mode_cmd.width = mode->hdisplay;
7069 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 7070 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7071 bpp);
5ca0c34a 7072 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 7073
7074 return intel_framebuffer_create(dev, &mode_cmd, obj);
7075}
7076
7077static struct drm_framebuffer *
7078mode_fits_in_fbdev(struct drm_device *dev,
7079 struct drm_display_mode *mode)
7080{
7081 struct drm_i915_private *dev_priv = dev->dev_private;
7082 struct drm_i915_gem_object *obj;
7083 struct drm_framebuffer *fb;
7084
7085 if (dev_priv->fbdev == NULL)
7086 return NULL;
7087
7088 obj = dev_priv->fbdev->ifb.obj;
7089 if (obj == NULL)
7090 return NULL;
7091
7092 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 7093 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7094 fb->bits_per_pixel))
d2dff872
CW		 7095 return NULL;
7096
01f2c773 7097 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 7098 return NULL;
7099
7100 return fb;
7101}
7102
d2434ab7 7103bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 7104 struct drm_display_mode *mode,
8261b191 7105 struct intel_load_detect_pipe *old)
79e53945
JB		 7106{
7107 struct intel_crtc *intel_crtc;
d2434ab7
DV		 7108 struct intel_encoder *intel_encoder =
7109 intel_attached_encoder(connector);
79e53945 7110 struct drm_crtc *possible_crtc;
4ef69c7a 7111 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 7112 struct drm_crtc *crtc = NULL;
7113 struct drm_device *dev = encoder->dev;
94352cf9 7114 struct drm_framebuffer *fb;
79e53945
JB		 7115 int i = -1;
7116
d2dff872
CW		 7117 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7118 connector->base.id, drm_get_connector_name(connector),
7119 encoder->base.id, drm_get_encoder_name(encoder));
7120
79e53945
JB		 7121 /*
7122 * Algorithm gets a little messy:
7a5e4805 7123 *
79e53945
JB		 7124 * - if the connector already has an assigned crtc, use it (but make
7125 * sure it's on first)
7a5e4805 7126 *
79e53945
JB		 7127 * - try to find the first unused crtc that can drive this connector,
7128 * and use that if we find one
79e53945
JB		 7129 */
7130
7131 /* See if we already have a CRTC for this connector */
7132 if (encoder->crtc) {
7133 crtc = encoder->crtc;
8261b191 7134
7b24056b
DV		 7135 mutex_lock(&crtc->mutex);
7136
24218aac 7137 old->dpms_mode = connector->dpms;
8261b191
CW		 7138 old->load_detect_temp = false;
7139
7140 /* Make sure the crtc and connector are running */
24218aac
DV		 7141 if (connector->dpms != DRM_MODE_DPMS_ON)
7142 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 7143
7173188d 7144 return true;
79e53945
JB		 7145 }
7146
7147 /* Find an unused one (if possible) */
7148 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7149 i++;
7150 if (!(encoder->possible_crtcs & (1 << i)))
7151 continue;
7152 if (!possible_crtc->enabled) {
7153 crtc = possible_crtc;
7154 break;
7155 }
79e53945
JB		 7156 }
7157
7158 /*
7159 * If we didn't find an unused CRTC, don't use any.
7160 */
7161 if (!crtc) {
7173188d
CW		 7162 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7163 return false;
79e53945
JB		 7164 }
7165
7b24056b 7166 mutex_lock(&crtc->mutex);
fc303101
DV		 7167 intel_encoder->new_crtc = to_intel_crtc(crtc);
7168 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 7169
7170 intel_crtc = to_intel_crtc(crtc);
24218aac 7171 old->dpms_mode = connector->dpms;
8261b191 7172 old->load_detect_temp = true;
d2dff872 7173 old->release_fb = NULL;
79e53945 7174
6492711d
CW		 7175 if (!mode)
7176 mode = &load_detect_mode;
79e53945 7177
d2dff872
CW		 7178 /* We need a framebuffer large enough to accommodate all accesses
7179 * that the plane may generate whilst we perform load detection.
7180 * We can not rely on the fbcon either being present (we get called
7181 * during its initialisation to detect all boot displays, or it may
7182 * not even exist) or that it is large enough to satisfy the
7183 * requested mode.
7184 */
94352cf9
DV		 7185 fb = mode_fits_in_fbdev(dev, mode);
7186 if (fb == NULL) {
d2dff872 7187 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 7188 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7189 old->release_fb = fb;
d2dff872
CW		 7190 } else
7191 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 7192 if (IS_ERR(fb)) {
d2dff872 7193 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 7194 mutex_unlock(&crtc->mutex);
0e8b3d3e 7195 return false;
79e53945 7196 }
79e53945 7197
c0c36b94 7198 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 7199 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 7200 if (old->release_fb)
7201 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 7202 mutex_unlock(&crtc->mutex);
0e8b3d3e 7203 return false;
79e53945 7204 }
7173188d 7205
79e53945 7206 /* let the connector get through one full cycle before testing */
9d0498a2 7207 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 7208 return true;
79e53945
JB		 7209}
7210
d2434ab7 7211void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 7212 struct intel_load_detect_pipe *old)
79e53945 7213{
d2434ab7
DV		 7214 struct intel_encoder *intel_encoder =
7215 intel_attached_encoder(connector);
4ef69c7a 7216 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 7217 struct drm_crtc *crtc = encoder->crtc;
79e53945 7218
d2dff872
CW		 7219 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7220 connector->base.id, drm_get_connector_name(connector),
7221 encoder->base.id, drm_get_encoder_name(encoder));
7222
8261b191 7223 if (old->load_detect_temp) {
fc303101
DV		 7224 to_intel_connector(connector)->new_encoder = NULL;
7225 intel_encoder->new_crtc = NULL;
7226 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 7227
36206361
DV		 7228 if (old->release_fb) {
7229 drm_framebuffer_unregister_private(old->release_fb);
7230 drm_framebuffer_unreference(old->release_fb);
7231 }
d2dff872 7232
67c96400 7233 mutex_unlock(&crtc->mutex);
0622a53c 7234 return;
79e53945
JB		 7235 }
7236
c751ce4f 7237 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 7238 if (old->dpms_mode != DRM_MODE_DPMS_ON)
7239 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 7240
7241 mutex_unlock(&crtc->mutex);
79e53945
JB		 7242}
7243
7244/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc
JB		 7245static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7246 struct intel_crtc_config *pipe_config)
79e53945 7247{
f1f644dc 7248 struct drm_device *dev = crtc->base.dev;
79e53945 7249 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 7250 int pipe = pipe_config->cpu_transcoder;
548f245b 7251 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 7252 u32 fp;
7253 intel_clock_t clock;
7254
7255 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 7256 fp = I915_READ(FP0(pipe));
79e53945 7257 else
39adb7a5 7258 fp = I915_READ(FP1(pipe));
79e53945
JB		 7259
7260 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 7261 if (IS_PINEVIEW(dev)) {
7262 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7263 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 7264 } else {
7265 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7266 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7267 }
7268
a6c45cf0 7269 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 7270 if (IS_PINEVIEW(dev))
7271 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7272 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 7273 else
7274 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 7275 DPLL_FPA01_P1_POST_DIV_SHIFT);
7276
7277 switch (dpll & DPLL_MODE_MASK) {
7278 case DPLLB_MODE_DAC_SERIAL:
7279 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7280 5 : 10;
7281 break;
7282 case DPLLB_MODE_LVDS:
7283 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7284 7 : 14;
7285 break;
7286 default:
28c97730 7287 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 7288 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc
JB		 7289 pipe_config->adjusted_mode.clock = 0;
7290 return;
79e53945
JB		 7291 }
7292
ac58c3f0
DV		 7293 if (IS_PINEVIEW(dev))
7294 pineview_clock(96000, &clock);
7295 else
7296 i9xx_clock(96000, &clock);
79e53945
JB		 7297 } else {
7298 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7299
7300 if (is_lvds) {
7301 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7302 DPLL_FPA01_P1_POST_DIV_SHIFT);
7303 clock.p2 = 14;
7304
7305 if ((dpll & PLL_REF_INPUT_MASK) ==
7306 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
7307 /* XXX: might not be 66MHz */
ac58c3f0 7308 i9xx_clock(66000, &clock);
79e53945 7309 } else
ac58c3f0 7310 i9xx_clock(48000, &clock);
79e53945
JB		 7311 } else {
7312 if (dpll & PLL_P1_DIVIDE_BY_TWO)
7313 clock.p1 = 2;
7314 else {
7315 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7316 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7317 }
7318 if (dpll & PLL_P2_DIVIDE_BY_4)
7319 clock.p2 = 4;
7320 else
7321 clock.p2 = 2;
7322
ac58c3f0 7323 i9xx_clock(48000, &clock);
79e53945
JB		 7324 }
7325 }
7326
a2dc53e7 7327 pipe_config->adjusted_mode.clock = clock.dot;
f1f644dc
JB		 7328}
7329
7330static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
7331 struct intel_crtc_config *pipe_config)
7332{
7333 struct drm_device *dev = crtc->base.dev;
7334 struct drm_i915_private *dev_priv = dev->dev_private;
7335 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
1041a02f 7336 int link_freq;
f1f644dc
JB		 7337 u64 clock;
7338 u32 link_m, link_n;
7339
f1f644dc
JB		 7340 /*
7341 * The calculation for the data clock is:
1041a02f 7342 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 7343 * But we want to avoid losing precison if possible, so:
1041a02f 7344 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 7345 *
7346 * and the link clock is simpler:
1041a02f 7347 * link_clock = (m * link_clock) / n
f1f644dc
JB		 7348 */
7349
7350 /*
7351 * We need to get the FDI or DP link clock here to derive
7352 * the M/N dividers.
7353 *
7354 * For FDI, we read it from the BIOS or use a fixed 2.7GHz.
7355 * For DP, it's either 1.62GHz or 2.7GHz.
7356 * We do our calculations in 10*MHz since we don't need much precison.
79e53945 7357 */
f1f644dc
JB		 7358 if (pipe_config->has_pch_encoder)
7359 link_freq = intel_fdi_link_freq(dev) * 10000;
7360 else
7361 link_freq = pipe_config->port_clock;
7362
7363 link_m = I915_READ(PIPE_LINK_M1(cpu_transcoder));
7364 link_n = I915_READ(PIPE_LINK_N1(cpu_transcoder));
7365
7366 if (!link_m || !link_n)
7367 return;
79e53945 7368
1041a02f 7369 clock = ((u64)link_m * (u64)link_freq);
f1f644dc
JB		 7370 do_div(clock, link_n);
7371
3c52f4eb 7372 pipe_config->adjusted_mode.clock = clock;
79e53945
JB		 7373}
7374
7375/** Returns the currently programmed mode of the given pipe. */
7376struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7377 struct drm_crtc *crtc)
7378{
548f245b 7379 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 7380 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 7381 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 7382 struct drm_display_mode *mode;
f1f644dc 7383 struct intel_crtc_config pipe_config;
fe2b8f9d
PZ		 7384 int htot = I915_READ(HTOTAL(cpu_transcoder));
7385 int hsync = I915_READ(HSYNC(cpu_transcoder));
7386 int vtot = I915_READ(VTOTAL(cpu_transcoder));
7387 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 7388
7389 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7390 if (!mode)
7391 return NULL;
7392
f1f644dc
JB		 7393 /*
7394 * Construct a pipe_config sufficient for getting the clock info
7395 * back out of crtc_clock_get.
7396 *
7397 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7398 * to use a real value here instead.
7399 */
e143a21c 7400 pipe_config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
f1f644dc
JB		 7401 pipe_config.pixel_multiplier = 1;
7402 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7403
7404 mode->clock = pipe_config.adjusted_mode.clock;
79e53945
JB		 7405 mode->hdisplay = (htot & 0xffff) + 1;
7406 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7407 mode->hsync_start = (hsync & 0xffff) + 1;
7408 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7409 mode->vdisplay = (vtot & 0xffff) + 1;
7410 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7411 mode->vsync_start = (vsync & 0xffff) + 1;
7412 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7413
7414 drm_mode_set_name(mode);
79e53945
JB		 7415
7416 return mode;
7417}
7418
3dec0095 7419static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 7420{
7421 struct drm_device *dev = crtc->dev;
7422 drm_i915_private_t *dev_priv = dev->dev_private;
7423 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7424 int pipe = intel_crtc->pipe;
dbdc6479
JB		 7425 int dpll_reg = DPLL(pipe);
7426 int dpll;
652c393a 7427
bad720ff 7428 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7429 return;
7430
7431 if (!dev_priv->lvds_downclock_avail)
7432 return;
7433
dbdc6479 7434 dpll = I915_READ(dpll_reg);
652c393a 7435 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 7436 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 7437
8ac5a6d5 7438 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 7439
7440 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7441 I915_WRITE(dpll_reg, dpll);
9d0498a2 7442 intel_wait_for_vblank(dev, pipe);
dbdc6479 7443
652c393a
JB		 7444 dpll = I915_READ(dpll_reg);
7445 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 7446 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 7447 }
652c393a
JB		 7448}
7449
7450static void intel_decrease_pllclock(struct drm_crtc *crtc)
7451{
7452 struct drm_device *dev = crtc->dev;
7453 drm_i915_private_t *dev_priv = dev->dev_private;
7454 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 7455
bad720ff 7456 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7457 return;
7458
7459 if (!dev_priv->lvds_downclock_avail)
7460 return;
7461
7462 /*
7463 * Since this is called by a timer, we should never get here in
7464 * the manual case.
7465 */
7466 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 7467 int pipe = intel_crtc->pipe;
7468 int dpll_reg = DPLL(pipe);
7469 int dpll;
f6e5b160 7470
44d98a61 7471 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7472
8ac5a6d5 7473 assert_panel_unlocked(dev_priv, pipe);
652c393a 7474
dc257cf1 7475 dpll = I915_READ(dpll_reg);
652c393a
JB		 7476 dpll |= DISPLAY_RATE_SELECT_FPA1;
7477 I915_WRITE(dpll_reg, dpll);
9d0498a2 7478 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7479 dpll = I915_READ(dpll_reg);
7480 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7481 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7482 }
7483
7484}
7485
f047e395
CW		 7486void intel_mark_busy(struct drm_device *dev)
7487{
c67a470b
PZ		 7488 struct drm_i915_private *dev_priv = dev->dev_private;
7489
7490 hsw_package_c8_gpu_busy(dev_priv);
7491 i915_update_gfx_val(dev_priv);
f047e395
CW		 7492}
7493
7494void intel_mark_idle(struct drm_device *dev)
652c393a 7495{
c67a470b 7496 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 7497 struct drm_crtc *crtc;
652c393a 7498
c67a470b
PZ		 7499 hsw_package_c8_gpu_idle(dev_priv);
7500
652c393a
JB		 7501 if (!i915_powersave)
7502 return;
7503
652c393a 7504 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 7505 if (!crtc->fb)
7506 continue;
7507
725a5b54 7508 intel_decrease_pllclock(crtc);
652c393a 7509 }
652c393a
JB		 7510}
7511
c65355bb
CW		 7512void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7513 struct intel_ring_buffer *ring)
652c393a 7514{
f047e395
CW		 7515 struct drm_device *dev = obj->base.dev;
7516 struct drm_crtc *crtc;
652c393a 7517
f047e395 7518 if (!i915_powersave)
acb87dfb
CW		 7519 return;
7520
652c393a
JB		 7521 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7522 if (!crtc->fb)
7523 continue;
7524
c65355bb
CW		 7525 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7526 continue;
7527
7528 intel_increase_pllclock(crtc);
7529 if (ring && intel_fbc_enabled(dev))
7530 ring->fbc_dirty = true;
652c393a
JB		 7531 }
7532}
7533
79e53945
JB		 7534static void intel_crtc_destroy(struct drm_crtc *crtc)
7535{
7536 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7537 struct drm_device *dev = crtc->dev;
7538 struct intel_unpin_work *work;
7539 unsigned long flags;
7540
7541 spin_lock_irqsave(&dev->event_lock, flags);
7542 work = intel_crtc->unpin_work;
7543 intel_crtc->unpin_work = NULL;
7544 spin_unlock_irqrestore(&dev->event_lock, flags);
7545
7546 if (work) {
7547 cancel_work_sync(&work->work);
7548 kfree(work);
7549 }
79e53945 7550
40ccc72b
MK		 7551 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7552
79e53945 7553 drm_crtc_cleanup(crtc);
67e77c5a 7554
79e53945
JB		 7555 kfree(intel_crtc);
7556}
7557
6b95a207
KH		 7558static void intel_unpin_work_fn(struct work_struct *__work)
7559{
7560 struct intel_unpin_work *work =
7561 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7562 struct drm_device *dev = work->crtc->dev;
6b95a207 7563
b4a98e57 7564 mutex_lock(&dev->struct_mutex);
1690e1eb 7565 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7566 drm_gem_object_unreference(&work->pending_flip_obj->base);
7567 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7568
b4a98e57
CW		 7569 intel_update_fbc(dev);
7570 mutex_unlock(&dev->struct_mutex);
7571
7572 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7573 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7574
6b95a207
KH		 7575 kfree(work);
7576}
7577
1afe3e9d 7578static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7579 struct drm_crtc *crtc)
6b95a207
KH		 7580{
7581 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7582 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7583 struct intel_unpin_work *work;
6b95a207
KH		 7584 unsigned long flags;
7585
7586 /* Ignore early vblank irqs */
7587 if (intel_crtc == NULL)
7588 return;
7589
7590 spin_lock_irqsave(&dev->event_lock, flags);
7591 work = intel_crtc->unpin_work;
e7d841ca
CW		 7592
7593 /* Ensure we don't miss a work->pending update ... */
7594 smp_rmb();
7595
7596 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7597 spin_unlock_irqrestore(&dev->event_lock, flags);
7598 return;
7599 }
7600
e7d841ca
CW		 7601 /* and that the unpin work is consistent wrt ->pending. */
7602 smp_rmb();
7603
6b95a207 7604 intel_crtc->unpin_work = NULL;
6b95a207 7605
45a066eb
RC		 7606 if (work->event)
7607 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7608
0af7e4df
MK		 7609 drm_vblank_put(dev, intel_crtc->pipe);
7610
6b95a207
KH		 7611 spin_unlock_irqrestore(&dev->event_lock, flags);
7612
2c10d571 7613 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7614
7615 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7616
7617 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7618}
7619
1afe3e9d
JB		 7620void intel_finish_page_flip(struct drm_device *dev, int pipe)
7621{
7622 drm_i915_private_t *dev_priv = dev->dev_private;
7623 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7624
49b14a5c 7625 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7626}
7627
7628void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7629{
7630 drm_i915_private_t *dev_priv = dev->dev_private;
7631 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7632
49b14a5c 7633 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7634}
7635
6b95a207
KH		 7636void intel_prepare_page_flip(struct drm_device *dev, int plane)
7637{
7638 drm_i915_private_t *dev_priv = dev->dev_private;
7639 struct intel_crtc *intel_crtc =
7640 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7641 unsigned long flags;
7642
e7d841ca
CW		 7643 /* NB: An MMIO update of the plane base pointer will also
7644 * generate a page-flip completion irq, i.e. every modeset
7645 * is also accompanied by a spurious intel_prepare_page_flip().
7646 */
6b95a207 7647 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7648 if (intel_crtc->unpin_work)
7649 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7650 spin_unlock_irqrestore(&dev->event_lock, flags);
7651}
7652
e7d841ca
CW		 7653inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7654{
7655 /* Ensure that the work item is consistent when activating it ... */
7656 smp_wmb();
7657 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7658 /* and that it is marked active as soon as the irq could fire. */
7659 smp_wmb();
7660}
7661
8c9f3aaf
JB		 7662static int intel_gen2_queue_flip(struct drm_device *dev,
7663 struct drm_crtc *crtc,
7664 struct drm_framebuffer *fb,
ed8d1975
KP		 7665 struct drm_i915_gem_object *obj,
7666 uint32_t flags)
8c9f3aaf
JB		 7667{
7668 struct drm_i915_private *dev_priv = dev->dev_private;
7669 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7670 u32 flip_mask;
6d90c952 7671 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7672 int ret;
7673
6d90c952 7674 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7675 if (ret)
83d4092b 7676 goto err;
8c9f3aaf 7677
6d90c952 7678 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7679 if (ret)
83d4092b 7680 goto err_unpin;
8c9f3aaf
JB		 7681
7682 /* Can't queue multiple flips, so wait for the previous
7683 * one to finish before executing the next.
7684 */
7685 if (intel_crtc->plane)
7686 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7687 else
7688 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7689 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7690 intel_ring_emit(ring, MI_NOOP);
7691 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7692 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7693 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 7694 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952 7695 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7696
7697 intel_mark_page_flip_active(intel_crtc);
09246732 7698 __intel_ring_advance(ring);
83d4092b
CW		 7699 return 0;
7700
7701err_unpin:
7702 intel_unpin_fb_obj(obj);
7703err:
8c9f3aaf
JB		 7704 return ret;
7705}
7706
7707static int intel_gen3_queue_flip(struct drm_device *dev,
7708 struct drm_crtc *crtc,
7709 struct drm_framebuffer *fb,
ed8d1975
KP		 7710 struct drm_i915_gem_object *obj,
7711 uint32_t flags)
8c9f3aaf
JB		 7712{
7713 struct drm_i915_private *dev_priv = dev->dev_private;
7714 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7715 u32 flip_mask;
6d90c952 7716 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7717 int ret;
7718
6d90c952 7719 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7720 if (ret)
83d4092b 7721 goto err;
8c9f3aaf 7722
6d90c952 7723 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7724 if (ret)
83d4092b 7725 goto err_unpin;
8c9f3aaf
JB		 7726
7727 if (intel_crtc->plane)
7728 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7729 else
7730 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7731 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7732 intel_ring_emit(ring, MI_NOOP);
7733 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7734 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7735 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 7736 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952
DV		 7737 intel_ring_emit(ring, MI_NOOP);
7738
e7d841ca 7739 intel_mark_page_flip_active(intel_crtc);
09246732 7740 __intel_ring_advance(ring);
83d4092b
CW		 7741 return 0;
7742
7743err_unpin:
7744 intel_unpin_fb_obj(obj);
7745err:
8c9f3aaf
JB		 7746 return ret;
7747}
7748
7749static int intel_gen4_queue_flip(struct drm_device *dev,
7750 struct drm_crtc *crtc,
7751 struct drm_framebuffer *fb,
ed8d1975
KP		 7752 struct drm_i915_gem_object *obj,
7753 uint32_t flags)
8c9f3aaf
JB		 7754{
7755 struct drm_i915_private *dev_priv = dev->dev_private;
7756 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7757 uint32_t pf, pipesrc;
6d90c952 7758 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7759 int ret;
7760
6d90c952 7761 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7762 if (ret)
83d4092b 7763 goto err;
8c9f3aaf 7764
6d90c952 7765 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7766 if (ret)
83d4092b 7767 goto err_unpin;
8c9f3aaf
JB		 7768
7769 /* i965+ uses the linear or tiled offsets from the
7770 * Display Registers (which do not change across a page-flip)
7771 * so we need only reprogram the base address.
7772 */
6d90c952
DV		 7773 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7774 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7775 intel_ring_emit(ring, fb->pitches[0]);
c2c75131 7776 intel_ring_emit(ring,
f343c5f6 7777 (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
c2c75131 7778 obj->tiling_mode);
8c9f3aaf
JB		 7779
7780 /* XXX Enabling the panel-fitter across page-flip is so far
7781 * untested on non-native modes, so ignore it for now.
7782 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7783 */
7784 pf = 0;
7785 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7786 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7787
7788 intel_mark_page_flip_active(intel_crtc);
09246732 7789 __intel_ring_advance(ring);
83d4092b
CW		 7790 return 0;
7791
7792err_unpin:
7793 intel_unpin_fb_obj(obj);
7794err:
8c9f3aaf
JB		 7795 return ret;
7796}
7797
7798static int intel_gen6_queue_flip(struct drm_device *dev,
7799 struct drm_crtc *crtc,
7800 struct drm_framebuffer *fb,
ed8d1975
KP		 7801 struct drm_i915_gem_object *obj,
7802 uint32_t flags)
8c9f3aaf
JB		 7803{
7804 struct drm_i915_private *dev_priv = dev->dev_private;
7805 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7806 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7807 uint32_t pf, pipesrc;
7808 int ret;
7809
6d90c952 7810 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7811 if (ret)
83d4092b 7812 goto err;
8c9f3aaf 7813
6d90c952 7814 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7815 if (ret)
83d4092b 7816 goto err_unpin;
8c9f3aaf 7817
6d90c952
DV		 7818 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7819 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7820 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
f343c5f6 7821 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8c9f3aaf 7822
dc257cf1
DV		 7823 /* Contrary to the suggestions in the documentation,
7824 * "Enable Panel Fitter" does not seem to be required when page
7825 * flipping with a non-native mode, and worse causes a normal
7826 * modeset to fail.
7827 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7828 */
7829 pf = 0;
8c9f3aaf 7830 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7831 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7832
7833 intel_mark_page_flip_active(intel_crtc);
09246732 7834 __intel_ring_advance(ring);
83d4092b
CW		 7835 return 0;
7836
7837err_unpin:
7838 intel_unpin_fb_obj(obj);
7839err:
8c9f3aaf
JB		 7840 return ret;
7841}
7842
7c9017e5
JB		 7843static int intel_gen7_queue_flip(struct drm_device *dev,
7844 struct drm_crtc *crtc,
7845 struct drm_framebuffer *fb,
ed8d1975
KP		 7846 struct drm_i915_gem_object *obj,
7847 uint32_t flags)
7c9017e5
JB		 7848{
7849 struct drm_i915_private *dev_priv = dev->dev_private;
7850 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ffe74d75 7851 struct intel_ring_buffer *ring;
cb05d8de 7852 uint32_t plane_bit = 0;
ffe74d75
CW		 7853 int len, ret;
7854
7855 ring = obj->ring;
7856 if (ring == NULL || ring->id != RCS)
7857 ring = &dev_priv->ring[BCS];
7c9017e5
JB		 7858
7859 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7860 if (ret)
83d4092b 7861 goto err;
7c9017e5 7862
cb05d8de
DV		 7863 switch(intel_crtc->plane) {
7864 case PLANE_A:
7865 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7866 break;
7867 case PLANE_B:
7868 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7869 break;
7870 case PLANE_C:
7871 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7872 break;
7873 default:
7874 WARN_ONCE(1, "unknown plane in flip command\n");
7875 ret = -ENODEV;
ab3951eb 7876 goto err_unpin;
cb05d8de
DV		 7877 }
7878
ffe74d75
CW		 7879 len = 4;
7880 if (ring->id == RCS)
7881 len += 6;
7882
7883 ret = intel_ring_begin(ring, len);
7c9017e5 7884 if (ret)
83d4092b 7885 goto err_unpin;
7c9017e5 7886
ffe74d75
CW		 7887 /* Unmask the flip-done completion message. Note that the bspec says that
7888 * we should do this for both the BCS and RCS, and that we must not unmask
7889 * more than one flip event at any time (or ensure that one flip message
7890 * can be sent by waiting for flip-done prior to queueing new flips).
7891 * Experimentation says that BCS works despite DERRMR masking all
7892 * flip-done completion events and that unmasking all planes at once
7893 * for the RCS also doesn't appear to drop events. Setting the DERRMR
7894 * to zero does lead to lockups within MI_DISPLAY_FLIP.
7895 */
7896 if (ring->id == RCS) {
7897 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
7898 intel_ring_emit(ring, DERRMR);
7899 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
7900 DERRMR_PIPEB_PRI_FLIP_DONE |
7901 DERRMR_PIPEC_PRI_FLIP_DONE));
7902 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
7903 intel_ring_emit(ring, DERRMR);
7904 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
7905 }
7906
cb05d8de 7907 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7908 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
f343c5f6 7909 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7c9017e5 7910 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 7911
7912 intel_mark_page_flip_active(intel_crtc);
09246732 7913 __intel_ring_advance(ring);
83d4092b
CW		 7914 return 0;
7915
7916err_unpin:
7917 intel_unpin_fb_obj(obj);
7918err:
7c9017e5
JB		 7919 return ret;
7920}
7921
8c9f3aaf
JB		 7922static int intel_default_queue_flip(struct drm_device *dev,
7923 struct drm_crtc *crtc,
7924 struct drm_framebuffer *fb,
ed8d1975
KP		 7925 struct drm_i915_gem_object *obj,
7926 uint32_t flags)
8c9f3aaf
JB		 7927{
7928 return -ENODEV;
7929}
7930
6b95a207
KH		 7931static int intel_crtc_page_flip(struct drm_crtc *crtc,
7932 struct drm_framebuffer *fb,
ed8d1975
KP		 7933 struct drm_pending_vblank_event *event,
7934 uint32_t page_flip_flags)
6b95a207
KH		 7935{
7936 struct drm_device *dev = crtc->dev;
7937 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 7938 struct drm_framebuffer *old_fb = crtc->fb;
7939 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 7940 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7941 struct intel_unpin_work *work;
8c9f3aaf 7942 unsigned long flags;
52e68630 7943 int ret;
6b95a207 7944
e6a595d2
VS		 7945 /* Can't change pixel format via MI display flips. */
7946 if (fb->pixel_format != crtc->fb->pixel_format)
7947 return -EINVAL;
7948
7949 /*
7950 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7951 * Note that pitch changes could also affect these register.
7952 */
7953 if (INTEL_INFO(dev)->gen > 3 &&
7954 (fb->offsets[0] != crtc->fb->offsets[0] ||
7955 fb->pitches[0] != crtc->fb->pitches[0]))
7956 return -EINVAL;
7957
6b95a207
KH		 7958 work = kzalloc(sizeof *work, GFP_KERNEL);
7959 if (work == NULL)
7960 return -ENOMEM;
7961
6b95a207 7962 work->event = event;
b4a98e57 7963 work->crtc = crtc;
4a35f83b 7964 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 7965 INIT_WORK(&work->work, intel_unpin_work_fn);
7966
7317c75e
JB		 7967 ret = drm_vblank_get(dev, intel_crtc->pipe);
7968 if (ret)
7969 goto free_work;
7970
6b95a207
KH		 7971 /* We borrow the event spin lock for protecting unpin_work */
7972 spin_lock_irqsave(&dev->event_lock, flags);
7973 if (intel_crtc->unpin_work) {
7974 spin_unlock_irqrestore(&dev->event_lock, flags);
7975 kfree(work);
7317c75e 7976 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7977
7978 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7979 return -EBUSY;
7980 }
7981 intel_crtc->unpin_work = work;
7982 spin_unlock_irqrestore(&dev->event_lock, flags);
7983
b4a98e57
CW		 7984 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7985 flush_workqueue(dev_priv->wq);
7986
79158103
CW		 7987 ret = i915_mutex_lock_interruptible(dev);
7988 if (ret)
7989 goto cleanup;
6b95a207 7990
75dfca80 7991 /* Reference the objects for the scheduled work. */
05394f39
CW		 7992 drm_gem_object_reference(&work->old_fb_obj->base);
7993 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7994
7995 crtc->fb = fb;
96b099fd 7996
e1f99ce6 7997 work->pending_flip_obj = obj;
e1f99ce6 7998
4e5359cd
SF		 7999 work->enable_stall_check = true;
8000
b4a98e57 8001 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 8002 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 8003
ed8d1975 8004 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8c9f3aaf
JB		 8005 if (ret)
8006 goto cleanup_pending;
6b95a207 8007
7782de3b 8008 intel_disable_fbc(dev);
c65355bb 8009 intel_mark_fb_busy(obj, NULL);
6b95a207
KH		 8010 mutex_unlock(&dev->struct_mutex);
8011
e5510fac
JB		 8012 trace_i915_flip_request(intel_crtc->plane, obj);
8013
6b95a207 8014 return 0;
96b099fd 8015
8c9f3aaf 8016cleanup_pending:
b4a98e57 8017 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 8018 crtc->fb = old_fb;
05394f39
CW		 8019 drm_gem_object_unreference(&work->old_fb_obj->base);
8020 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 8021 mutex_unlock(&dev->struct_mutex);
8022
79158103 8023cleanup:
96b099fd
CW		 8024 spin_lock_irqsave(&dev->event_lock, flags);
8025 intel_crtc->unpin_work = NULL;
8026 spin_unlock_irqrestore(&dev->event_lock, flags);
8027
7317c75e
JB		 8028 drm_vblank_put(dev, intel_crtc->pipe);
8029free_work:
96b099fd
CW		 8030 kfree(work);
8031
8032 return ret;
6b95a207
KH		 8033}
8034
f6e5b160 8035static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 8036 .mode_set_base_atomic = intel_pipe_set_base_atomic,
8037 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 8038};
8039
50f56119
DV		 8040static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
8041 struct drm_crtc *crtc)
8042{
8043 struct drm_device *dev;
8044 struct drm_crtc *tmp;
8045 int crtc_mask = 1;
47f1c6c9 8046
50f56119 8047 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 8048
50f56119 8049 dev = crtc->dev;
47f1c6c9 8050
50f56119
DV		 8051 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
8052 if (tmp == crtc)
8053 break;
8054 crtc_mask <<= 1;
8055 }
47f1c6c9 8056
50f56119
DV		 8057 if (encoder->possible_crtcs & crtc_mask)
8058 return true;
8059 return false;
47f1c6c9 8060}
79e53945 8061
9a935856
DV		 8062/**
8063 * intel_modeset_update_staged_output_state
8064 *
8065 * Updates the staged output configuration state, e.g. after we've read out the
8066 * current hw state.
8067 */
8068static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 8069{
9a935856
DV		 8070 struct intel_encoder *encoder;
8071 struct intel_connector *connector;
f6e5b160 8072
9a935856
DV		 8073 list_for_each_entry(connector, &dev->mode_config.connector_list,
8074 base.head) {
8075 connector->new_encoder =
8076 to_intel_encoder(connector->base.encoder);
8077 }
f6e5b160 8078
9a935856
DV		 8079 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8080 base.head) {
8081 encoder->new_crtc =
8082 to_intel_crtc(encoder->base.crtc);
8083 }
f6e5b160
CW		 8084}
8085
9a935856
DV		 8086/**
8087 * intel_modeset_commit_output_state
8088 *
8089 * This function copies the stage display pipe configuration to the real one.
8090 */
8091static void intel_modeset_commit_output_state(struct drm_device *dev)
8092{
8093 struct intel_encoder *encoder;
8094 struct intel_connector *connector;
f6e5b160 8095
9a935856
DV		 8096 list_for_each_entry(connector, &dev->mode_config.connector_list,
8097 base.head) {
8098 connector->base.encoder = &connector->new_encoder->base;
8099 }
f6e5b160 8100
9a935856
DV		 8101 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8102 base.head) {
8103 encoder->base.crtc = &encoder->new_crtc->base;
8104 }
8105}
8106
050f7aeb
DV		 8107static void
8108connected_sink_compute_bpp(struct intel_connector * connector,
8109 struct intel_crtc_config *pipe_config)
8110{
8111 int bpp = pipe_config->pipe_bpp;
8112
8113 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8114 connector->base.base.id,
8115 drm_get_connector_name(&connector->base));
8116
8117 /* Don't use an invalid EDID bpc value */
8118 if (connector->base.display_info.bpc &&
8119 connector->base.display_info.bpc * 3 < bpp) {
8120 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8121 bpp, connector->base.display_info.bpc*3);
8122 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8123 }
8124
8125 /* Clamp bpp to 8 on screens without EDID 1.4 */
8126 if (connector->base.display_info.bpc == 0 && bpp > 24) {
8127 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8128 bpp);
8129 pipe_config->pipe_bpp = 24;
8130 }
8131}
8132
4e53c2e0 8133static int
050f7aeb
DV		 8134compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8135 struct drm_framebuffer *fb,
8136 struct intel_crtc_config *pipe_config)
4e53c2e0 8137{
050f7aeb
DV		 8138 struct drm_device *dev = crtc->base.dev;
8139 struct intel_connector *connector;
4e53c2e0
DV		 8140 int bpp;
8141
d42264b1
DV		 8142 switch (fb->pixel_format) {
8143 case DRM_FORMAT_C8:
4e53c2e0
DV		 8144 bpp = 8*3; /* since we go through a colormap */
8145 break;
d42264b1
DV		 8146 case DRM_FORMAT_XRGB1555:
8147 case DRM_FORMAT_ARGB1555:
8148 /* checked in intel_framebuffer_init already */
8149 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8150 return -EINVAL;
8151 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 8152 bpp = 6*3; /* min is 18bpp */
8153 break;
d42264b1
DV		 8154 case DRM_FORMAT_XBGR8888:
8155 case DRM_FORMAT_ABGR8888:
8156 /* checked in intel_framebuffer_init already */
8157 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8158 return -EINVAL;
8159 case DRM_FORMAT_XRGB8888:
8160 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 8161 bpp = 8*3;
8162 break;
d42264b1
DV		 8163 case DRM_FORMAT_XRGB2101010:
8164 case DRM_FORMAT_ARGB2101010:
8165 case DRM_FORMAT_XBGR2101010:
8166 case DRM_FORMAT_ABGR2101010:
8167 /* checked in intel_framebuffer_init already */
8168 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 8169 return -EINVAL;
4e53c2e0
DV		 8170 bpp = 10*3;
8171 break;
baba133a 8172 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 8173 default:
8174 DRM_DEBUG_KMS("unsupported depth\n");
8175 return -EINVAL;
8176 }
8177
4e53c2e0
DV		 8178 pipe_config->pipe_bpp = bpp;
8179
8180 /* Clamp display bpp to EDID value */
8181 list_for_each_entry(connector, &dev->mode_config.connector_list,
050f7aeb 8182 base.head) {
1b829e05
DV		 8183 if (!connector->new_encoder ||
8184 connector->new_encoder->new_crtc != crtc)
4e53c2e0
DV		 8185 continue;
8186
050f7aeb 8187 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV		 8188 }
8189
8190 return bpp;
8191}
8192
c0b03411
DV		 8193static void intel_dump_pipe_config(struct intel_crtc *crtc,
8194 struct intel_crtc_config *pipe_config,
8195 const char *context)
8196{
8197 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8198 context, pipe_name(crtc->pipe));
8199
8200 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8201 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8202 pipe_config->pipe_bpp, pipe_config->dither);
8203 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8204 pipe_config->has_pch_encoder,
8205 pipe_config->fdi_lanes,
8206 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8207 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8208 pipe_config->fdi_m_n.tu);
8209 DRM_DEBUG_KMS("requested mode:\n");
8210 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8211 DRM_DEBUG_KMS("adjusted mode:\n");
8212 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
8213 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8214 pipe_config->gmch_pfit.control,
8215 pipe_config->gmch_pfit.pgm_ratios,
8216 pipe_config->gmch_pfit.lvds_border_bits);
8217 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
8218 pipe_config->pch_pfit.pos,
8219 pipe_config->pch_pfit.size);
42db64ef 8220 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
c0b03411
DV		 8221}
8222
accfc0c5
DV		 8223static bool check_encoder_cloning(struct drm_crtc *crtc)
8224{
8225 int num_encoders = 0;
8226 bool uncloneable_encoders = false;
8227 struct intel_encoder *encoder;
8228
8229 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8230 base.head) {
8231 if (&encoder->new_crtc->base != crtc)
8232 continue;
8233
8234 num_encoders++;
8235 if (!encoder->cloneable)
8236 uncloneable_encoders = true;
8237 }
8238
8239 return !(num_encoders > 1 && uncloneable_encoders);
8240}
8241
b8cecdf5
DV		 8242static struct intel_crtc_config *
8243intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 8244 struct drm_framebuffer *fb,
b8cecdf5 8245 struct drm_display_mode *mode)
ee7b9f93 8246{
7758a113 8247 struct drm_device *dev = crtc->dev;
7758a113 8248 struct intel_encoder *encoder;
b8cecdf5 8249 struct intel_crtc_config *pipe_config;
e29c22c0
DV		 8250 int plane_bpp, ret = -EINVAL;
8251 bool retry = true;
ee7b9f93 8252
accfc0c5
DV		 8253 if (!check_encoder_cloning(crtc)) {
8254 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8255 return ERR_PTR(-EINVAL);
8256 }
8257
b8cecdf5
DV		 8258 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8259 if (!pipe_config)
7758a113
DV		 8260 return ERR_PTR(-ENOMEM);
8261
b8cecdf5
DV		 8262 drm_mode_copy(&pipe_config->adjusted_mode, mode);
8263 drm_mode_copy(&pipe_config->requested_mode, mode);
e143a21c
DV		 8264 pipe_config->cpu_transcoder =
8265 (enum transcoder) to_intel_crtc(crtc)->pipe;
c0d43d62 8266 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
b8cecdf5 8267
2960bc9c
ID		 8268 /*
8269 * Sanitize sync polarity flags based on requested ones. If neither
8270 * positive or negative polarity is requested, treat this as meaning
8271 * negative polarity.
8272 */
8273 if (!(pipe_config->adjusted_mode.flags &
8274 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8275 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8276
8277 if (!(pipe_config->adjusted_mode.flags &
8278 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8279 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8280
050f7aeb
DV		 8281 /* Compute a starting value for pipe_config->pipe_bpp taking the source
8282 * plane pixel format and any sink constraints into account. Returns the
8283 * source plane bpp so that dithering can be selected on mismatches
8284 * after encoders and crtc also have had their say. */
8285 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8286 fb, pipe_config);
4e53c2e0
DV		 8287 if (plane_bpp < 0)
8288 goto fail;
8289
e29c22c0 8290encoder_retry:
ef1b460d 8291 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 8292 pipe_config->port_clock = 0;
ef1b460d 8293 pipe_config->pixel_multiplier = 1;
ff9a6750 8294
135c81b8
DV		 8295 /* Fill in default crtc timings, allow encoders to overwrite them. */
8296 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, 0);
8297
7758a113
DV		 8298 /* Pass our mode to the connectors and the CRTC to give them a chance to
8299 * adjust it according to limitations or connector properties, and also
8300 * a chance to reject the mode entirely.
47f1c6c9 8301 */
7758a113
DV		 8302 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8303 base.head) {
47f1c6c9 8304
7758a113
DV		 8305 if (&encoder->new_crtc->base != crtc)
8306 continue;
7ae89233 8307
efea6e8e
DV		 8308 if (!(encoder->compute_config(encoder, pipe_config))) {
8309 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 8310 goto fail;
8311 }
ee7b9f93 8312 }
47f1c6c9 8313
ff9a6750
DV		 8314 /* Set default port clock if not overwritten by the encoder. Needs to be
8315 * done afterwards in case the encoder adjusts the mode. */
8316 if (!pipe_config->port_clock)
3c52f4eb
VS		 8317 pipe_config->port_clock = pipe_config->adjusted_mode.clock *
8318 pipe_config->pixel_multiplier;
ff9a6750 8319
a43f6e0f 8320 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 8321 if (ret < 0) {
7758a113
DV		 8322 DRM_DEBUG_KMS("CRTC fixup failed\n");
8323 goto fail;
ee7b9f93 8324 }
e29c22c0
DV		 8325
8326 if (ret == RETRY) {
8327 if (WARN(!retry, "loop in pipe configuration computation\n")) {
8328 ret = -EINVAL;
8329 goto fail;
8330 }
8331
8332 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8333 retry = false;
8334 goto encoder_retry;
8335 }
8336
4e53c2e0
DV		 8337 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
8338 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8339 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
8340
b8cecdf5 8341 return pipe_config;
7758a113 8342fail:
b8cecdf5 8343 kfree(pipe_config);
e29c22c0 8344 return ERR_PTR(ret);
ee7b9f93 8345}
47f1c6c9 8346
e2e1ed41
DV		 8347/* Computes which crtcs are affected and sets the relevant bits in the mask. For
8348 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8349static void
8350intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
8351 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 8352{
8353 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 8354 struct drm_device *dev = crtc->dev;
8355 struct intel_encoder *encoder;
8356 struct intel_connector *connector;
8357 struct drm_crtc *tmp_crtc;
79e53945 8358
e2e1ed41 8359 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 8360
e2e1ed41
DV		 8361 /* Check which crtcs have changed outputs connected to them, these need
8362 * to be part of the prepare_pipes mask. We don't (yet) support global
8363 * modeset across multiple crtcs, so modeset_pipes will only have one
8364 * bit set at most. */
8365 list_for_each_entry(connector, &dev->mode_config.connector_list,
8366 base.head) {
8367 if (connector->base.encoder == &connector->new_encoder->base)
8368 continue;
79e53945 8369
e2e1ed41
DV		 8370 if (connector->base.encoder) {
8371 tmp_crtc = connector->base.encoder->crtc;
8372
8373 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8374 }
8375
8376 if (connector->new_encoder)
8377 *prepare_pipes |=
8378 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 8379 }
8380
e2e1ed41
DV		 8381 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8382 base.head) {
8383 if (encoder->base.crtc == &encoder->new_crtc->base)
8384 continue;
8385
8386 if (encoder->base.crtc) {
8387 tmp_crtc = encoder->base.crtc;
8388
8389 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8390 }
8391
8392 if (encoder->new_crtc)
8393 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 8394 }
8395
e2e1ed41
DV		 8396 /* Check for any pipes that will be fully disabled ... */
8397 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8398 base.head) {
8399 bool used = false;
22fd0fab 8400
e2e1ed41
DV		 8401 /* Don't try to disable disabled crtcs. */
8402 if (!intel_crtc->base.enabled)
8403 continue;
7e7d76c3 8404
e2e1ed41
DV		 8405 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8406 base.head) {
8407 if (encoder->new_crtc == intel_crtc)
8408 used = true;
8409 }
8410
8411 if (!used)
8412 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 8413 }
8414
e2e1ed41
DV		 8415
8416 /* set_mode is also used to update properties on life display pipes. */
8417 intel_crtc = to_intel_crtc(crtc);
8418 if (crtc->enabled)
8419 *prepare_pipes |= 1 << intel_crtc->pipe;
8420
b6c5164d
DV		 8421 /*
8422 * For simplicity do a full modeset on any pipe where the output routing
8423 * changed. We could be more clever, but that would require us to be
8424 * more careful with calling the relevant encoder->mode_set functions.
8425 */
e2e1ed41
DV		 8426 if (*prepare_pipes)
8427 *modeset_pipes = *prepare_pipes;
8428
8429 /* ... and mask these out. */
8430 *modeset_pipes &= ~(*disable_pipes);
8431 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 8432
8433 /*
8434 * HACK: We don't (yet) fully support global modesets. intel_set_config
8435 * obies this rule, but the modeset restore mode of
8436 * intel_modeset_setup_hw_state does not.
8437 */
8438 *modeset_pipes &= 1 << intel_crtc->pipe;
8439 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 8440
8441 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8442 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 8443}
79e53945 8444
ea9d758d 8445static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 8446{
ea9d758d 8447 struct drm_encoder *encoder;
f6e5b160 8448 struct drm_device *dev = crtc->dev;
f6e5b160 8449
ea9d758d
DV		 8450 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8451 if (encoder->crtc == crtc)
8452 return true;
8453
8454 return false;
8455}
8456
8457static void
8458intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8459{
8460 struct intel_encoder *intel_encoder;
8461 struct intel_crtc *intel_crtc;
8462 struct drm_connector *connector;
8463
8464 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8465 base.head) {
8466 if (!intel_encoder->base.crtc)
8467 continue;
8468
8469 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8470
8471 if (prepare_pipes & (1 << intel_crtc->pipe))
8472 intel_encoder->connectors_active = false;
8473 }
8474
8475 intel_modeset_commit_output_state(dev);
8476
8477 /* Update computed state. */
8478 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8479 base.head) {
8480 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8481 }
8482
8483 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8484 if (!connector->encoder || !connector->encoder->crtc)
8485 continue;
8486
8487 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8488
8489 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 8490 struct drm_property *dpms_property =
8491 dev->mode_config.dpms_property;
8492
ea9d758d 8493 connector->dpms = DRM_MODE_DPMS_ON;
662595df 8494 drm_object_property_set_value(&connector->base,
68d34720
DV		 8495 dpms_property,
8496 DRM_MODE_DPMS_ON);
ea9d758d
DV		 8497
8498 intel_encoder = to_intel_encoder(connector->encoder);
8499 intel_encoder->connectors_active = true;
8500 }
8501 }
8502
8503}
8504
f1f644dc
JB		 8505static bool intel_fuzzy_clock_check(struct intel_crtc_config *cur,
8506 struct intel_crtc_config *new)
8507{
8508 int clock1, clock2, diff;
8509
8510 clock1 = cur->adjusted_mode.clock;
8511 clock2 = new->adjusted_mode.clock;
8512
8513 if (clock1 == clock2)
8514 return true;
8515
8516 if (!clock1 || !clock2)
8517 return false;
8518
8519 diff = abs(clock1 - clock2);
8520
8521 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8522 return true;
8523
8524 return false;
8525}
8526
25c5b266
DV		 8527#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8528 list_for_each_entry((intel_crtc), \
8529 &(dev)->mode_config.crtc_list, \
8530 base.head) \
0973f18f 8531 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 8532
0e8ffe1b 8533static bool
2fa2fe9a
DV		 8534intel_pipe_config_compare(struct drm_device *dev,
8535 struct intel_crtc_config *current_config,
0e8ffe1b
DV		 8536 struct intel_crtc_config *pipe_config)
8537{
66e985c0
DV		 8538#define PIPE_CONF_CHECK_X(name) \
8539 if (current_config->name != pipe_config->name) { \
8540 DRM_ERROR("mismatch in " #name " " \
8541 "(expected 0x%08x, found 0x%08x)\n", \
8542 current_config->name, \
8543 pipe_config->name); \
8544 return false; \
8545 }
8546
08a24034
DV		 8547#define PIPE_CONF_CHECK_I(name) \
8548 if (current_config->name != pipe_config->name) { \
8549 DRM_ERROR("mismatch in " #name " " \
8550 "(expected %i, found %i)\n", \
8551 current_config->name, \
8552 pipe_config->name); \
8553 return false; \
88adfff1
DV		 8554 }
8555
1bd1bd80
DV		 8556#define PIPE_CONF_CHECK_FLAGS(name, mask) \
8557 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 8558 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 8559 "(expected %i, found %i)\n", \
8560 current_config->name & (mask), \
8561 pipe_config->name & (mask)); \
8562 return false; \
8563 }
8564
bb760063
DV		 8565#define PIPE_CONF_QUIRK(quirk) \
8566 ((current_config->quirks | pipe_config->quirks) & (quirk))
8567
eccb140b
DV		 8568 PIPE_CONF_CHECK_I(cpu_transcoder);
8569
08a24034
DV		 8570 PIPE_CONF_CHECK_I(has_pch_encoder);
8571 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 8572 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8573 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8574 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8575 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8576 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 8577
1bd1bd80
DV		 8578 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8579 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8580 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8581 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8582 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8583 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8584
8585 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8586 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8587 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8588 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8589 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8590 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8591
c93f54cf 8592 PIPE_CONF_CHECK_I(pixel_multiplier);
6c49f241 8593
1bd1bd80
DV		 8594 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8595 DRM_MODE_FLAG_INTERLACE);
8596
bb760063
DV		 8597 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8598 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8599 DRM_MODE_FLAG_PHSYNC);
8600 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8601 DRM_MODE_FLAG_NHSYNC);
8602 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8603 DRM_MODE_FLAG_PVSYNC);
8604 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8605 DRM_MODE_FLAG_NVSYNC);
8606 }
045ac3b5 8607
1bd1bd80
DV		 8608 PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8609 PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8610
2fa2fe9a
DV		 8611 PIPE_CONF_CHECK_I(gmch_pfit.control);
8612 /* pfit ratios are autocomputed by the hw on gen4+ */
8613 if (INTEL_INFO(dev)->gen < 4)
8614 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8615 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8616 PIPE_CONF_CHECK_I(pch_pfit.pos);
8617 PIPE_CONF_CHECK_I(pch_pfit.size);
8618
42db64ef
PZ		 8619 PIPE_CONF_CHECK_I(ips_enabled);
8620
c0d43d62 8621 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 8622 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 8623 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 8624 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8625 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
c0d43d62 8626
66e985c0 8627#undef PIPE_CONF_CHECK_X
08a24034 8628#undef PIPE_CONF_CHECK_I
1bd1bd80 8629#undef PIPE_CONF_CHECK_FLAGS
bb760063 8630#undef PIPE_CONF_QUIRK
88adfff1 8631
f1f644dc
JB		 8632 if (!IS_HASWELL(dev)) {
8633 if (!intel_fuzzy_clock_check(current_config, pipe_config)) {
6f02488e 8634 DRM_ERROR("mismatch in clock (expected %d, found %d)\n",
f1f644dc
JB		 8635 current_config->adjusted_mode.clock,
8636 pipe_config->adjusted_mode.clock);
8637 return false;
8638 }
8639 }
8640
0e8ffe1b
DV		 8641 return true;
8642}
8643
91d1b4bd
DV		 8644static void
8645check_connector_state(struct drm_device *dev)
8af6cf88 8646{
8af6cf88
DV		 8647 struct intel_connector *connector;
8648
8649 list_for_each_entry(connector, &dev->mode_config.connector_list,
8650 base.head) {
8651 /* This also checks the encoder/connector hw state with the
8652 * ->get_hw_state callbacks. */
8653 intel_connector_check_state(connector);
8654
8655 WARN(&connector->new_encoder->base != connector->base.encoder,
8656 "connector's staged encoder doesn't match current encoder\n");
8657 }
91d1b4bd
DV		 8658}
8659
8660static void
8661check_encoder_state(struct drm_device *dev)
8662{
8663 struct intel_encoder *encoder;
8664 struct intel_connector *connector;
8af6cf88
DV		 8665
8666 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8667 base.head) {
8668 bool enabled = false;
8669 bool active = false;
8670 enum pipe pipe, tracked_pipe;
8671
8672 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8673 encoder->base.base.id,
8674 drm_get_encoder_name(&encoder->base));
8675
8676 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8677 "encoder's stage crtc doesn't match current crtc\n");
8678 WARN(encoder->connectors_active && !encoder->base.crtc,
8679 "encoder's active_connectors set, but no crtc\n");
8680
8681 list_for_each_entry(connector, &dev->mode_config.connector_list,
8682 base.head) {
8683 if (connector->base.encoder != &encoder->base)
8684 continue;
8685 enabled = true;
8686 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8687 active = true;
8688 }
8689 WARN(!!encoder->base.crtc != enabled,
8690 "encoder's enabled state mismatch "
8691 "(expected %i, found %i)\n",
8692 !!encoder->base.crtc, enabled);
8693 WARN(active && !encoder->base.crtc,
8694 "active encoder with no crtc\n");
8695
8696 WARN(encoder->connectors_active != active,
8697 "encoder's computed active state doesn't match tracked active state "
8698 "(expected %i, found %i)\n", active, encoder->connectors_active);
8699
8700 active = encoder->get_hw_state(encoder, &pipe);
8701 WARN(active != encoder->connectors_active,
8702 "encoder's hw state doesn't match sw tracking "
8703 "(expected %i, found %i)\n",
8704 encoder->connectors_active, active);
8705
8706 if (!encoder->base.crtc)
8707 continue;
8708
8709 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8710 WARN(active && pipe != tracked_pipe,
8711 "active encoder's pipe doesn't match"
8712 "(expected %i, found %i)\n",
8713 tracked_pipe, pipe);
8714
8715 }
91d1b4bd
DV		 8716}
8717
8718static void
8719check_crtc_state(struct drm_device *dev)
8720{
8721 drm_i915_private_t *dev_priv = dev->dev_private;
8722 struct intel_crtc *crtc;
8723 struct intel_encoder *encoder;
8724 struct intel_crtc_config pipe_config;
8af6cf88
DV		 8725
8726 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8727 base.head) {
8728 bool enabled = false;
8729 bool active = false;
8730
045ac3b5
JB		 8731 memset(&pipe_config, 0, sizeof(pipe_config));
8732
8af6cf88
DV		 8733 DRM_DEBUG_KMS("[CRTC:%d]\n",
8734 crtc->base.base.id);
8735
8736 WARN(crtc->active && !crtc->base.enabled,
8737 "active crtc, but not enabled in sw tracking\n");
8738
8739 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8740 base.head) {
8741 if (encoder->base.crtc != &crtc->base)
8742 continue;
8743 enabled = true;
8744 if (encoder->connectors_active)
8745 active = true;
8746 }
6c49f241 8747
8af6cf88
DV		 8748 WARN(active != crtc->active,
8749 "crtc's computed active state doesn't match tracked active state "
8750 "(expected %i, found %i)\n", active, crtc->active);
8751 WARN(enabled != crtc->base.enabled,
8752 "crtc's computed enabled state doesn't match tracked enabled state "
8753 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8754
0e8ffe1b
DV		 8755 active = dev_priv->display.get_pipe_config(crtc,
8756 &pipe_config);
d62cf62a
DV		 8757
8758 /* hw state is inconsistent with the pipe A quirk */
8759 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
8760 active = crtc->active;
8761
6c49f241
DV		 8762 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8763 base.head) {
3eaba51c 8764 enum pipe pipe;
6c49f241
DV		 8765 if (encoder->base.crtc != &crtc->base)
8766 continue;
3eaba51c
VS		 8767 if (encoder->get_config &&
8768 encoder->get_hw_state(encoder, &pipe))
6c49f241
DV		 8769 encoder->get_config(encoder, &pipe_config);
8770 }
8771
510d5f2f
JB		 8772 if (dev_priv->display.get_clock)
8773 dev_priv->display.get_clock(crtc, &pipe_config);
8774
0e8ffe1b
DV		 8775 WARN(crtc->active != active,
8776 "crtc active state doesn't match with hw state "
8777 "(expected %i, found %i)\n", crtc->active, active);
8778
c0b03411
DV		 8779 if (active &&
8780 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8781 WARN(1, "pipe state doesn't match!\n");
8782 intel_dump_pipe_config(crtc, &pipe_config,
8783 "[hw state]");
8784 intel_dump_pipe_config(crtc, &crtc->config,
8785 "[sw state]");
8786 }
8af6cf88
DV		 8787 }
8788}
8789
91d1b4bd
DV		 8790static void
8791check_shared_dpll_state(struct drm_device *dev)
8792{
8793 drm_i915_private_t *dev_priv = dev->dev_private;
8794 struct intel_crtc *crtc;
8795 struct intel_dpll_hw_state dpll_hw_state;
8796 int i;
5358901f
DV		 8797
8798 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8799 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
8800 int enabled_crtcs = 0, active_crtcs = 0;
8801 bool active;
8802
8803 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
8804
8805 DRM_DEBUG_KMS("%s\n", pll->name);
8806
8807 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
8808
8809 WARN(pll->active > pll->refcount,
8810 "more active pll users than references: %i vs %i\n",
8811 pll->active, pll->refcount);
8812 WARN(pll->active && !pll->on,
8813 "pll in active use but not on in sw tracking\n");
35c95375
DV		 8814 WARN(pll->on && !pll->active,
8815 "pll in on but not on in use in sw tracking\n");
5358901f
DV		 8816 WARN(pll->on != active,
8817 "pll on state mismatch (expected %i, found %i)\n",
8818 pll->on, active);
8819
8820 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8821 base.head) {
8822 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
8823 enabled_crtcs++;
8824 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
8825 active_crtcs++;
8826 }
8827 WARN(pll->active != active_crtcs,
8828 "pll active crtcs mismatch (expected %i, found %i)\n",
8829 pll->active, active_crtcs);
8830 WARN(pll->refcount != enabled_crtcs,
8831 "pll enabled crtcs mismatch (expected %i, found %i)\n",
8832 pll->refcount, enabled_crtcs);
66e985c0
DV		 8833
8834 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
8835 sizeof(dpll_hw_state)),
8836 "pll hw state mismatch\n");
5358901f 8837 }
8af6cf88
DV		 8838}
8839
91d1b4bd
DV		 8840void
8841intel_modeset_check_state(struct drm_device *dev)
8842{
8843 check_connector_state(dev);
8844 check_encoder_state(dev);
8845 check_crtc_state(dev);
8846 check_shared_dpll_state(dev);
8847}
8848
f30da187
DV		 8849static int __intel_set_mode(struct drm_crtc *crtc,
8850 struct drm_display_mode *mode,
8851 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 8852{
8853 struct drm_device *dev = crtc->dev;
dbf2b54e 8854 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 8855 struct drm_display_mode *saved_mode, *saved_hwmode;
8856 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 8857 struct intel_crtc *intel_crtc;
8858 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 8859 int ret = 0;
a6778b3c 8860
3ac18232 8861 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 8862 if (!saved_mode)
8863 return -ENOMEM;
3ac18232 8864 saved_hwmode = saved_mode + 1;
a6778b3c 8865
e2e1ed41 8866 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 8867 &prepare_pipes, &disable_pipes);
8868
3ac18232
TG		 8869 *saved_hwmode = crtc->hwmode;
8870 *saved_mode = crtc->mode;
a6778b3c 8871
25c5b266
DV		 8872 /* Hack: Because we don't (yet) support global modeset on multiple
8873 * crtcs, we don't keep track of the new mode for more than one crtc.
8874 * Hence simply check whether any bit is set in modeset_pipes in all the
8875 * pieces of code that are not yet converted to deal with mutliple crtcs
8876 * changing their mode at the same time. */
25c5b266 8877 if (modeset_pipes) {
4e53c2e0 8878 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 8879 if (IS_ERR(pipe_config)) {
8880 ret = PTR_ERR(pipe_config);
8881 pipe_config = NULL;
8882
3ac18232 8883 goto out;
25c5b266 8884 }
c0b03411
DV		 8885 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8886 "[modeset]");
25c5b266 8887 }
a6778b3c 8888
460da916
DV		 8889 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8890 intel_crtc_disable(&intel_crtc->base);
8891
ea9d758d
DV		 8892 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8893 if (intel_crtc->base.enabled)
8894 dev_priv->display.crtc_disable(&intel_crtc->base);
8895 }
a6778b3c 8896
6c4c86f5
DV		 8897 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8898 * to set it here already despite that we pass it down the callchain.
f6e5b160 8899 */
b8cecdf5 8900 if (modeset_pipes) {
25c5b266 8901 crtc->mode = *mode;
b8cecdf5
DV		 8902 /* mode_set/enable/disable functions rely on a correct pipe
8903 * config. */
8904 to_intel_crtc(crtc)->config = *pipe_config;
8905 }
7758a113 8906
ea9d758d
DV		 8907 /* Only after disabling all output pipelines that will be changed can we
8908 * update the the output configuration. */
8909 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 8910
47fab737
DV		 8911 if (dev_priv->display.modeset_global_resources)
8912 dev_priv->display.modeset_global_resources(dev);
8913
a6778b3c
DV		 8914 /* Set up the DPLL and any encoders state that needs to adjust or depend
8915 * on the DPLL.
f6e5b160 8916 */
25c5b266 8917 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 8918 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 8919 x, y, fb);
8920 if (ret)
8921 goto done;
a6778b3c
DV		 8922 }
8923
8924 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 8925 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8926 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 8927
25c5b266
DV		 8928 if (modeset_pipes) {
8929 /* Store real post-adjustment hardware mode. */
b8cecdf5 8930 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 8931
25c5b266
DV		 8932 /* Calculate and store various constants which
8933 * are later needed by vblank and swap-completion
8934 * timestamping. They are derived from true hwmode.
8935 */
8936 drm_calc_timestamping_constants(crtc);
8937 }
a6778b3c
DV		 8938
8939 /* FIXME: add subpixel order */
8940done:
c0c36b94 8941 if (ret && crtc->enabled) {
3ac18232
TG		 8942 crtc->hwmode = *saved_hwmode;
8943 crtc->mode = *saved_mode;
a6778b3c
DV		 8944 }
8945
3ac18232 8946out:
b8cecdf5 8947 kfree(pipe_config);
3ac18232 8948 kfree(saved_mode);
a6778b3c 8949 return ret;
f6e5b160
CW		 8950}
8951
e7457a9a
DL		 8952static int intel_set_mode(struct drm_crtc *crtc,
8953 struct drm_display_mode *mode,
8954 int x, int y, struct drm_framebuffer *fb)
f30da187
DV		 8955{
8956 int ret;
8957
8958 ret = __intel_set_mode(crtc, mode, x, y, fb);
8959
8960 if (ret == 0)
8961 intel_modeset_check_state(crtc->dev);
8962
8963 return ret;
8964}
8965
c0c36b94
CW		 8966void intel_crtc_restore_mode(struct drm_crtc *crtc)
8967{
8968 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8969}
8970
25c5b266
DV		 8971#undef for_each_intel_crtc_masked
8972
d9e55608
DV		 8973static void intel_set_config_free(struct intel_set_config *config)
8974{
8975 if (!config)
8976 return;
8977
1aa4b628
DV		 8978 kfree(config->save_connector_encoders);
8979 kfree(config->save_encoder_crtcs);
d9e55608
DV		 8980 kfree(config);
8981}
8982
85f9eb71
DV		 8983static int intel_set_config_save_state(struct drm_device *dev,
8984 struct intel_set_config *config)
8985{
85f9eb71
DV		 8986 struct drm_encoder *encoder;
8987 struct drm_connector *connector;
8988 int count;
8989
1aa4b628
DV		 8990 config->save_encoder_crtcs =
8991 kcalloc(dev->mode_config.num_encoder,
8992 sizeof(struct drm_crtc *), GFP_KERNEL);
8993 if (!config->save_encoder_crtcs)
85f9eb71
DV		 8994 return -ENOMEM;
8995
1aa4b628
DV		 8996 config->save_connector_encoders =
8997 kcalloc(dev->mode_config.num_connector,
8998 sizeof(struct drm_encoder *), GFP_KERNEL);
8999 if (!config->save_connector_encoders)
85f9eb71
DV		 9000 return -ENOMEM;
9001
9002 /* Copy data. Note that driver private data is not affected.
9003 * Should anything bad happen only the expected state is
9004 * restored, not the drivers personal bookkeeping.
9005 */
85f9eb71
DV		 9006 count = 0;
9007 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 9008 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 9009 }
9010
9011 count = 0;
9012 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 9013 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 9014 }
9015
9016 return 0;
9017}
9018
9019static void intel_set_config_restore_state(struct drm_device *dev,
9020 struct intel_set_config *config)
9021{
9a935856
DV		 9022 struct intel_encoder *encoder;
9023 struct intel_connector *connector;
85f9eb71
DV		 9024 int count;
9025
85f9eb71 9026 count = 0;
9a935856
DV		 9027 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9028 encoder->new_crtc =
9029 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 9030 }
9031
9032 count = 0;
9a935856
DV		 9033 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
9034 connector->new_encoder =
9035 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 9036 }
9037}
9038
e3de42b6 9039static bool
2e57f47d 9040is_crtc_connector_off(struct drm_mode_set *set)
e3de42b6
ID		 9041{
9042 int i;
9043
2e57f47d
CW		 9044 if (set->num_connectors == 0)
9045 return false;
9046
9047 if (WARN_ON(set->connectors == NULL))
9048 return false;
9049
9050 for (i = 0; i < set->num_connectors; i++)
9051 if (set->connectors[i]->encoder &&
9052 set->connectors[i]->encoder->crtc == set->crtc &&
9053 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
e3de42b6
ID		 9054 return true;
9055
9056 return false;
9057}
9058
5e2b584e
DV		 9059static void
9060intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9061 struct intel_set_config *config)
9062{
9063
9064 /* We should be able to check here if the fb has the same properties
9065 * and then just flip_or_move it */
2e57f47d
CW		 9066 if (is_crtc_connector_off(set)) {
9067 config->mode_changed = true;
e3de42b6 9068 } else if (set->crtc->fb != set->fb) {
5e2b584e
DV		 9069 /* If we have no fb then treat it as a full mode set */
9070 if (set->crtc->fb == NULL) {
319d9827
JB		 9071 struct intel_crtc *intel_crtc =
9072 to_intel_crtc(set->crtc);
9073
9074 if (intel_crtc->active && i915_fastboot) {
9075 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9076 config->fb_changed = true;
9077 } else {
9078 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9079 config->mode_changed = true;
9080 }
5e2b584e
DV		 9081 } else if (set->fb == NULL) {
9082 config->mode_changed = true;
72f4901e
DV		 9083 } else if (set->fb->pixel_format !=
9084 set->crtc->fb->pixel_format) {
5e2b584e 9085 config->mode_changed = true;
e3de42b6 9086 } else {
5e2b584e 9087 config->fb_changed = true;
e3de42b6 9088 }
5e2b584e
DV		 9089 }
9090
835c5873 9091 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 9092 config->fb_changed = true;
9093
9094 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9095 DRM_DEBUG_KMS("modes are different, full mode set\n");
9096 drm_mode_debug_printmodeline(&set->crtc->mode);
9097 drm_mode_debug_printmodeline(set->mode);
9098 config->mode_changed = true;
9099 }
a1d95703
CW		 9100
9101 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9102 set->crtc->base.id, config->mode_changed, config->fb_changed);
5e2b584e
DV		 9103}
9104
2e431051 9105static int
9a935856
DV		 9106intel_modeset_stage_output_state(struct drm_device *dev,
9107 struct drm_mode_set *set,
9108 struct intel_set_config *config)
50f56119 9109{
85f9eb71 9110 struct drm_crtc *new_crtc;
9a935856
DV		 9111 struct intel_connector *connector;
9112 struct intel_encoder *encoder;
f3f08572 9113 int ro;
50f56119 9114
9abdda74 9115 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 9116 * of connectors. For paranoia, double-check this. */
9117 WARN_ON(!set->fb && (set->num_connectors != 0));
9118 WARN_ON(set->fb && (set->num_connectors == 0));
9119
9a935856
DV		 9120 list_for_each_entry(connector, &dev->mode_config.connector_list,
9121 base.head) {
9122 /* Otherwise traverse passed in connector list and get encoders
9123 * for them. */
50f56119 9124 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 9125 if (set->connectors[ro] == &connector->base) {
9126 connector->new_encoder = connector->encoder;
50f56119
DV		 9127 break;
9128 }
9129 }
9130
9a935856
DV		 9131 /* If we disable the crtc, disable all its connectors. Also, if
9132 * the connector is on the changing crtc but not on the new
9133 * connector list, disable it. */
9134 if ((!set->fb || ro == set->num_connectors) &&
9135 connector->base.encoder &&
9136 connector->base.encoder->crtc == set->crtc) {
9137 connector->new_encoder = NULL;
9138
9139 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9140 connector->base.base.id,
9141 drm_get_connector_name(&connector->base));
9142 }
9143
9144
9145 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 9146 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 9147 config->mode_changed = true;
50f56119
DV		 9148 }
9149 }
9a935856 9150 /* connector->new_encoder is now updated for all connectors. */
50f56119 9151
9a935856 9152 /* Update crtc of enabled connectors. */
9a935856
DV		 9153 list_for_each_entry(connector, &dev->mode_config.connector_list,
9154 base.head) {
9155 if (!connector->new_encoder)
50f56119
DV		 9156 continue;
9157
9a935856 9158 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 9159
9160 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 9161 if (set->connectors[ro] == &connector->base)
50f56119
DV		 9162 new_crtc = set->crtc;
9163 }
9164
9165 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 9166 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
9167 new_crtc)) {
5e2b584e 9168 return -EINVAL;
50f56119 9169 }
9a935856
DV		 9170 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9171
9172 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9173 connector->base.base.id,
9174 drm_get_connector_name(&connector->base),
9175 new_crtc->base.id);
9176 }
9177
9178 /* Check for any encoders that needs to be disabled. */
9179 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9180 base.head) {
9181 list_for_each_entry(connector,
9182 &dev->mode_config.connector_list,
9183 base.head) {
9184 if (connector->new_encoder == encoder) {
9185 WARN_ON(!connector->new_encoder->new_crtc);
9186
9187 goto next_encoder;
9188 }
9189 }
9190 encoder->new_crtc = NULL;
9191next_encoder:
9192 /* Only now check for crtc changes so we don't miss encoders
9193 * that will be disabled. */
9194 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 9195 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 9196 config->mode_changed = true;
50f56119
DV		 9197 }
9198 }
9a935856 9199 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 9200
2e431051
DV		 9201 return 0;
9202}
9203
9204static int intel_crtc_set_config(struct drm_mode_set *set)
9205{
9206 struct drm_device *dev;
2e431051
DV		 9207 struct drm_mode_set save_set;
9208 struct intel_set_config *config;
9209 int ret;
2e431051 9210
8d3e375e
DV		 9211 BUG_ON(!set);
9212 BUG_ON(!set->crtc);
9213 BUG_ON(!set->crtc->helper_private);
2e431051 9214
7e53f3a4
DV		 9215 /* Enforce sane interface api - has been abused by the fb helper. */
9216 BUG_ON(!set->mode && set->fb);
9217 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 9218
2e431051
DV		 9219 if (set->fb) {
9220 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9221 set->crtc->base.id, set->fb->base.id,
9222 (int)set->num_connectors, set->x, set->y);
9223 } else {
9224 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 9225 }
9226
9227 dev = set->crtc->dev;
9228
9229 ret = -ENOMEM;
9230 config = kzalloc(sizeof(*config), GFP_KERNEL);
9231 if (!config)
9232 goto out_config;
9233
9234 ret = intel_set_config_save_state(dev, config);
9235 if (ret)
9236 goto out_config;
9237
9238 save_set.crtc = set->crtc;
9239 save_set.mode = &set->crtc->mode;
9240 save_set.x = set->crtc->x;
9241 save_set.y = set->crtc->y;
9242 save_set.fb = set->crtc->fb;
9243
9244 /* Compute whether we need a full modeset, only an fb base update or no
9245 * change at all. In the future we might also check whether only the
9246 * mode changed, e.g. for LVDS where we only change the panel fitter in
9247 * such cases. */
9248 intel_set_config_compute_mode_changes(set, config);
9249
9a935856 9250 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 9251 if (ret)
9252 goto fail;
9253
5e2b584e 9254 if (config->mode_changed) {
c0c36b94
CW		 9255 ret = intel_set_mode(set->crtc, set->mode,
9256 set->x, set->y, set->fb);
5e2b584e 9257 } else if (config->fb_changed) {
4878cae2
VS		 9258 intel_crtc_wait_for_pending_flips(set->crtc);
9259
4f660f49 9260 ret = intel_pipe_set_base(set->crtc,
94352cf9 9261 set->x, set->y, set->fb);
50f56119
DV		 9262 }
9263
2d05eae1 9264 if (ret) {
bf67dfeb
DV		 9265 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9266 set->crtc->base.id, ret);
50f56119 9267fail:
2d05eae1 9268 intel_set_config_restore_state(dev, config);
50f56119 9269
2d05eae1
CW		 9270 /* Try to restore the config */
9271 if (config->mode_changed &&
9272 intel_set_mode(save_set.crtc, save_set.mode,
9273 save_set.x, save_set.y, save_set.fb))
9274 DRM_ERROR("failed to restore config after modeset failure\n");
9275 }
50f56119 9276
d9e55608
DV		 9277out_config:
9278 intel_set_config_free(config);
50f56119
DV		 9279 return ret;
9280}
f6e5b160
CW		 9281
9282static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 9283 .cursor_set = intel_crtc_cursor_set,
9284 .cursor_move = intel_crtc_cursor_move,
9285 .gamma_set = intel_crtc_gamma_set,
50f56119 9286 .set_config = intel_crtc_set_config,
f6e5b160
CW		 9287 .destroy = intel_crtc_destroy,
9288 .page_flip = intel_crtc_page_flip,
9289};
9290
79f689aa
PZ		 9291static void intel_cpu_pll_init(struct drm_device *dev)
9292{
affa9354 9293 if (HAS_DDI(dev))
79f689aa
PZ		 9294 intel_ddi_pll_init(dev);
9295}
9296
5358901f
DV		 9297static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
9298 struct intel_shared_dpll *pll,
9299 struct intel_dpll_hw_state *hw_state)
ee7b9f93 9300{
5358901f 9301 uint32_t val;
ee7b9f93 9302
5358901f 9303 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 9304 hw_state->dpll = val;
9305 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
9306 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 9307
9308 return val & DPLL_VCO_ENABLE;
9309}
9310
15bdd4cf
DV		 9311static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
9312 struct intel_shared_dpll *pll)
9313{
9314 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
9315 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
9316}
9317
e7b903d2
DV		 9318static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
9319 struct intel_shared_dpll *pll)
9320{
e7b903d2
DV		 9321 /* PCH refclock must be enabled first */
9322 assert_pch_refclk_enabled(dev_priv);
9323
15bdd4cf
DV		 9324 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9325
9326 /* Wait for the clocks to stabilize. */
9327 POSTING_READ(PCH_DPLL(pll->id));
9328 udelay(150);
9329
9330 /* The pixel multiplier can only be updated once the
9331 * DPLL is enabled and the clocks are stable.
9332 *
9333 * So write it again.
9334 */
9335 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9336 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 9337 udelay(200);
9338}
9339
9340static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
9341 struct intel_shared_dpll *pll)
9342{
9343 struct drm_device *dev = dev_priv->dev;
9344 struct intel_crtc *crtc;
e7b903d2
DV		 9345
9346 /* Make sure no transcoder isn't still depending on us. */
9347 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9348 if (intel_crtc_to_shared_dpll(crtc) == pll)
9349 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 9350 }
9351
15bdd4cf
DV		 9352 I915_WRITE(PCH_DPLL(pll->id), 0);
9353 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 9354 udelay(200);
9355}
9356
46edb027
DV		 9357static char *ibx_pch_dpll_names[] = {
9358 "PCH DPLL A",
9359 "PCH DPLL B",
9360};
9361
7c74ade1 9362static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 9363{
e7b903d2 9364 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 9365 int i;
9366
7c74ade1 9367 dev_priv->num_shared_dpll = 2;
ee7b9f93 9368
e72f9fbf 9369 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 9370 dev_priv->shared_dplls[i].id = i;
9371 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 9372 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 9373 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
9374 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 9375 dev_priv->shared_dplls[i].get_hw_state =
9376 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 9377 }
9378}
9379
7c74ade1
DV		 9380static void intel_shared_dpll_init(struct drm_device *dev)
9381{
e7b903d2 9382 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1
DV		 9383
9384 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9385 ibx_pch_dpll_init(dev);
9386 else
9387 dev_priv->num_shared_dpll = 0;
9388
9389 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
9390 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9391 dev_priv->num_shared_dpll);
9392}
9393
b358d0a6 9394static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 9395{
22fd0fab 9396 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 9397 struct intel_crtc *intel_crtc;
9398 int i;
9399
9400 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
9401 if (intel_crtc == NULL)
9402 return;
9403
9404 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9405
9406 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 9407 for (i = 0; i < 256; i++) {
9408 intel_crtc->lut_r[i] = i;
9409 intel_crtc->lut_g[i] = i;
9410 intel_crtc->lut_b[i] = i;
9411 }
9412
80824003
JB		 9413 /* Swap pipes & planes for FBC on pre-965 */
9414 intel_crtc->pipe = pipe;
9415 intel_crtc->plane = pipe;
e2e767ab 9416 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 9417 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 9418 intel_crtc->plane = !pipe;
80824003
JB		 9419 }
9420
22fd0fab
JB		 9421 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9422 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9423 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9424 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9425
79e53945 9426 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 9427}
9428
08d7b3d1 9429int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 9430 struct drm_file *file)
08d7b3d1 9431{
08d7b3d1 9432 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 9433 struct drm_mode_object *drmmode_obj;
9434 struct intel_crtc *crtc;
08d7b3d1 9435
1cff8f6b
DV		 9436 if (!drm_core_check_feature(dev, DRIVER_MODESET))
9437 return -ENODEV;
08d7b3d1 9438
c05422d5
DV		 9439 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9440 DRM_MODE_OBJECT_CRTC);
08d7b3d1 9441
c05422d5 9442 if (!drmmode_obj) {
08d7b3d1
CW		 9443 DRM_ERROR("no such CRTC id\n");
9444 return -EINVAL;
9445 }
9446
c05422d5
DV		 9447 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9448 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 9449
c05422d5 9450 return 0;
08d7b3d1
CW		 9451}
9452
66a9278e 9453static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 9454{
66a9278e
DV		 9455 struct drm_device *dev = encoder->base.dev;
9456 struct intel_encoder *source_encoder;
79e53945 9457 int index_mask = 0;
79e53945
JB		 9458 int entry = 0;
9459
66a9278e
DV		 9460 list_for_each_entry(source_encoder,
9461 &dev->mode_config.encoder_list, base.head) {
9462
9463 if (encoder == source_encoder)
79e53945 9464 index_mask |= (1 << entry);
66a9278e
DV		 9465
9466 /* Intel hw has only one MUX where enocoders could be cloned. */
9467 if (encoder->cloneable && source_encoder->cloneable)
9468 index_mask |= (1 << entry);
9469
79e53945
JB		 9470 entry++;
9471 }
4ef69c7a 9472
79e53945
JB		 9473 return index_mask;
9474}
9475
4d302442
CW		 9476static bool has_edp_a(struct drm_device *dev)
9477{
9478 struct drm_i915_private *dev_priv = dev->dev_private;
9479
9480 if (!IS_MOBILE(dev))
9481 return false;
9482
9483 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9484 return false;
9485
9486 if (IS_GEN5(dev) &&
9487 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9488 return false;
9489
9490 return true;
9491}
9492
79e53945
JB		 9493static void intel_setup_outputs(struct drm_device *dev)
9494{
725e30ad 9495 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 9496 struct intel_encoder *encoder;
cb0953d7 9497 bool dpd_is_edp = false;
79e53945 9498
c9093354 9499 intel_lvds_init(dev);
79e53945 9500
c40c0f5b 9501 if (!IS_ULT(dev))
79935fca 9502 intel_crt_init(dev);
cb0953d7 9503
affa9354 9504 if (HAS_DDI(dev)) {
0e72a5b5
ED		 9505 int found;
9506
9507 /* Haswell uses DDI functions to detect digital outputs */
9508 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9509 /* DDI A only supports eDP */
9510 if (found)
9511 intel_ddi_init(dev, PORT_A);
9512
9513 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9514 * register */
9515 found = I915_READ(SFUSE_STRAP);
9516
9517 if (found & SFUSE_STRAP_DDIB_DETECTED)
9518 intel_ddi_init(dev, PORT_B);
9519 if (found & SFUSE_STRAP_DDIC_DETECTED)
9520 intel_ddi_init(dev, PORT_C);
9521 if (found & SFUSE_STRAP_DDID_DETECTED)
9522 intel_ddi_init(dev, PORT_D);
9523 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 9524 int found;
270b3042
DV		 9525 dpd_is_edp = intel_dpd_is_edp(dev);
9526
9527 if (has_edp_a(dev))
9528 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 9529
dc0fa718 9530 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 9531 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 9532 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 9533 if (!found)
e2debe91 9534 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 9535 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 9536 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 9537 }
9538
dc0fa718 9539 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 9540 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 9541
dc0fa718 9542 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 9543 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 9544
5eb08b69 9545 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 9546 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 9547
270b3042 9548 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 9549 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 9550 } else if (IS_VALLEYVIEW(dev)) {
19c03924 9551 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
6f6005a5
JB		 9552 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
9553 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
9554 PORT_C);
9555 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9556 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
9557 PORT_C);
9558 }
19c03924 9559
dc0fa718 9560 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 9561 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9562 PORT_B);
67cfc203
VS		 9563 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9564 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 9565 }
3cfca973
JN		 9566
9567 intel_dsi_init(dev);
103a196f 9568 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 9569 bool found = false;
7d57382e 9570
e2debe91 9571 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9572 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 9573 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 9574 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9575 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 9576 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 9577 }
27185ae1 9578
e7281eab 9579 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9580 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 9581 }
13520b05
KH		 9582
9583 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 9584
e2debe91 9585 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9586 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 9587 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 9588 }
27185ae1 9589
e2debe91 9590 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 9591
b01f2c3a
JB		 9592 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9593 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 9594 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 9595 }
e7281eab 9596 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9597 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 9598 }
27185ae1 9599
b01f2c3a 9600 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 9601 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 9602 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 9603 } else if (IS_GEN2(dev))
79e53945
JB		 9604 intel_dvo_init(dev);
9605
103a196f 9606 if (SUPPORTS_TV(dev))
79e53945
JB		 9607 intel_tv_init(dev);
9608
4ef69c7a
CW		 9609 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9610 encoder->base.possible_crtcs = encoder->crtc_mask;
9611 encoder->base.possible_clones =
66a9278e 9612 intel_encoder_clones(encoder);
79e53945 9613 }
47356eb6 9614
dde86e2d 9615 intel_init_pch_refclk(dev);
270b3042
DV		 9616
9617 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 9618}
9619
ddfe1567
CW		 9620void intel_framebuffer_fini(struct intel_framebuffer *fb)
9621{
9622 drm_framebuffer_cleanup(&fb->base);
9623 drm_gem_object_unreference_unlocked(&fb->obj->base);
9624}
9625
79e53945
JB		 9626static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9627{
9628 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 9629
ddfe1567 9630 intel_framebuffer_fini(intel_fb);
79e53945
JB		 9631 kfree(intel_fb);
9632}
9633
9634static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 9635 struct drm_file *file,
79e53945
JB		 9636 unsigned int *handle)
9637{
9638 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 9639 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 9640
05394f39 9641 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 9642}
9643
9644static const struct drm_framebuffer_funcs intel_fb_funcs = {
9645 .destroy = intel_user_framebuffer_destroy,
9646 .create_handle = intel_user_framebuffer_create_handle,
9647};
9648
38651674
DA		 9649int intel_framebuffer_init(struct drm_device *dev,
9650 struct intel_framebuffer *intel_fb,
308e5bcb 9651 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 9652 struct drm_i915_gem_object *obj)
79e53945 9653{
a35cdaa0 9654 int pitch_limit;
79e53945
JB		 9655 int ret;
9656
c16ed4be
CW		 9657 if (obj->tiling_mode == I915_TILING_Y) {
9658 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 9659 return -EINVAL;
c16ed4be 9660 }
57cd6508 9661
c16ed4be
CW		 9662 if (mode_cmd->pitches[0] & 63) {
9663 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9664 mode_cmd->pitches[0]);
57cd6508 9665 return -EINVAL;
c16ed4be 9666 }
57cd6508 9667
a35cdaa0
CW		 9668 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9669 pitch_limit = 32*1024;
9670 } else if (INTEL_INFO(dev)->gen >= 4) {
9671 if (obj->tiling_mode)
9672 pitch_limit = 16*1024;
9673 else
9674 pitch_limit = 32*1024;
9675 } else if (INTEL_INFO(dev)->gen >= 3) {
9676 if (obj->tiling_mode)
9677 pitch_limit = 8*1024;
9678 else
9679 pitch_limit = 16*1024;
9680 } else
9681 /* XXX DSPC is limited to 4k tiled */
9682 pitch_limit = 8*1024;
9683
9684 if (mode_cmd->pitches[0] > pitch_limit) {
9685 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9686 obj->tiling_mode ? "tiled" : "linear",
9687 mode_cmd->pitches[0], pitch_limit);
5d7bd705 9688 return -EINVAL;
c16ed4be 9689 }
5d7bd705
VS		 9690
9691 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 9692 mode_cmd->pitches[0] != obj->stride) {
9693 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9694 mode_cmd->pitches[0], obj->stride);
5d7bd705 9695 return -EINVAL;
c16ed4be 9696 }
5d7bd705 9697
57779d06 9698 /* Reject formats not supported by any plane early. */
308e5bcb 9699 switch (mode_cmd->pixel_format) {
57779d06 9700 case DRM_FORMAT_C8:
04b3924d
VS		 9701 case DRM_FORMAT_RGB565:
9702 case DRM_FORMAT_XRGB8888:
9703 case DRM_FORMAT_ARGB8888:
57779d06
VS		 9704 break;
9705 case DRM_FORMAT_XRGB1555:
9706 case DRM_FORMAT_ARGB1555:
c16ed4be 9707 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 9708 DRM_DEBUG("unsupported pixel format: %s\n",
9709 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9710 return -EINVAL;
c16ed4be 9711 }
57779d06
VS		 9712 break;
9713 case DRM_FORMAT_XBGR8888:
9714 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 9715 case DRM_FORMAT_XRGB2101010:
9716 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 9717 case DRM_FORMAT_XBGR2101010:
9718 case DRM_FORMAT_ABGR2101010:
c16ed4be 9719 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 9720 DRM_DEBUG("unsupported pixel format: %s\n",
9721 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9722 return -EINVAL;
c16ed4be 9723 }
b5626747 9724 break;
04b3924d
VS		 9725 case DRM_FORMAT_YUYV:
9726 case DRM_FORMAT_UYVY:
9727 case DRM_FORMAT_YVYU:
9728 case DRM_FORMAT_VYUY:
c16ed4be 9729 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 9730 DRM_DEBUG("unsupported pixel format: %s\n",
9731 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9732 return -EINVAL;
c16ed4be 9733 }
57cd6508
CW		 9734 break;
9735 default:
4ee62c76
VS		 9736 DRM_DEBUG("unsupported pixel format: %s\n",
9737 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 9738 return -EINVAL;
9739 }
9740
90f9a336
VS		 9741 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9742 if (mode_cmd->offsets[0] != 0)
9743 return -EINVAL;
9744
c7d73f6a
DV		 9745 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9746 intel_fb->obj = obj;
9747
79e53945
JB		 9748 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9749 if (ret) {
9750 DRM_ERROR("framebuffer init failed %d\n", ret);
9751 return ret;
9752 }
9753
79e53945
JB		 9754 return 0;
9755}
9756
79e53945
JB		 9757static struct drm_framebuffer *
9758intel_user_framebuffer_create(struct drm_device *dev,
9759 struct drm_file *filp,
308e5bcb 9760 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 9761{
05394f39 9762 struct drm_i915_gem_object *obj;
79e53945 9763
308e5bcb
JB		 9764 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9765 mode_cmd->handles[0]));
c8725226 9766 if (&obj->base == NULL)
cce13ff7 9767 return ERR_PTR(-ENOENT);
79e53945 9768
d2dff872 9769 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 9770}
9771
79e53945 9772static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 9773 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 9774 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 9775};
9776
e70236a8
JB		 9777/* Set up chip specific display functions */
9778static void intel_init_display(struct drm_device *dev)
9779{
9780 struct drm_i915_private *dev_priv = dev->dev_private;
9781
ee9300bb
DV		 9782 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9783 dev_priv->display.find_dpll = g4x_find_best_dpll;
9784 else if (IS_VALLEYVIEW(dev))
9785 dev_priv->display.find_dpll = vlv_find_best_dpll;
9786 else if (IS_PINEVIEW(dev))
9787 dev_priv->display.find_dpll = pnv_find_best_dpll;
9788 else
9789 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9790
affa9354 9791 if (HAS_DDI(dev)) {
0e8ffe1b 9792 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 9793 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 9794 dev_priv->display.crtc_enable = haswell_crtc_enable;
9795 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 9796 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 9797 dev_priv->display.update_plane = ironlake_update_plane;
9798 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 9799 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f1f644dc 9800 dev_priv->display.get_clock = ironlake_crtc_clock_get;
f564048e 9801 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 9802 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9803 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 9804 dev_priv->display.off = ironlake_crtc_off;
17638cd6 9805 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 9806 } else if (IS_VALLEYVIEW(dev)) {
9807 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f1f644dc 9808 dev_priv->display.get_clock = i9xx_crtc_clock_get;
89b667f8
JB		 9809 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9810 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9811 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9812 dev_priv->display.off = i9xx_crtc_off;
9813 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9814 } else {
0e8ffe1b 9815 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f1f644dc 9816 dev_priv->display.get_clock = i9xx_crtc_clock_get;
f564048e 9817 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 9818 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9819 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 9820 dev_priv->display.off = i9xx_crtc_off;
17638cd6 9821 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9822 }
e70236a8 9823
e70236a8 9824 /* Returns the core display clock speed */
25eb05fc
JB		 9825 if (IS_VALLEYVIEW(dev))
9826 dev_priv->display.get_display_clock_speed =
9827 valleyview_get_display_clock_speed;
9828 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 9829 dev_priv->display.get_display_clock_speed =
9830 i945_get_display_clock_speed;
9831 else if (IS_I915G(dev))
9832 dev_priv->display.get_display_clock_speed =
9833 i915_get_display_clock_speed;
257a7ffc 9834 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 9835 dev_priv->display.get_display_clock_speed =
9836 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 9837 else if (IS_PINEVIEW(dev))
9838 dev_priv->display.get_display_clock_speed =
9839 pnv_get_display_clock_speed;
e70236a8
JB		 9840 else if (IS_I915GM(dev))
9841 dev_priv->display.get_display_clock_speed =
9842 i915gm_get_display_clock_speed;
9843 else if (IS_I865G(dev))
9844 dev_priv->display.get_display_clock_speed =
9845 i865_get_display_clock_speed;
f0f8a9ce 9846 else if (IS_I85X(dev))
e70236a8
JB		 9847 dev_priv->display.get_display_clock_speed =
9848 i855_get_display_clock_speed;
9849 else /* 852, 830 */
9850 dev_priv->display.get_display_clock_speed =
9851 i830_get_display_clock_speed;
9852
7f8a8569 9853 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 9854 if (IS_GEN5(dev)) {
674cf967 9855 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 9856 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 9857 } else if (IS_GEN6(dev)) {
674cf967 9858 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 9859 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 9860 } else if (IS_IVYBRIDGE(dev)) {
9861 /* FIXME: detect B0+ stepping and use auto training */
9862 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 9863 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 9864 dev_priv->display.modeset_global_resources =
9865 ivb_modeset_global_resources;
c82e4d26
ED		 9866 } else if (IS_HASWELL(dev)) {
9867 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 9868 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 9869 dev_priv->display.modeset_global_resources =
9870 haswell_modeset_global_resources;
a0e63c22 9871 }
6067aaea 9872 } else if (IS_G4X(dev)) {
e0dac65e 9873 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 9874 }
8c9f3aaf
JB		 9875
9876 /* Default just returns -ENODEV to indicate unsupported */
9877 dev_priv->display.queue_flip = intel_default_queue_flip;
9878
9879 switch (INTEL_INFO(dev)->gen) {
9880 case 2:
9881 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9882 break;
9883
9884 case 3:
9885 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9886 break;
9887
9888 case 4:
9889 case 5:
9890 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9891 break;
9892
9893 case 6:
9894 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9895 break;
7c9017e5
JB		 9896 case 7:
9897 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9898 break;
8c9f3aaf 9899 }
e70236a8
JB		 9900}
9901
b690e96c
JB		 9902/*
9903 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9904 * resume, or other times. This quirk makes sure that's the case for
9905 * affected systems.
9906 */
0206e353 9907static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 9908{
9909 struct drm_i915_private *dev_priv = dev->dev_private;
9910
9911 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 9912 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 9913}
9914
435793df
KP		 9915/*
9916 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9917 */
9918static void quirk_ssc_force_disable(struct drm_device *dev)
9919{
9920 struct drm_i915_private *dev_priv = dev->dev_private;
9921 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 9922 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 9923}
9924
4dca20ef 9925/*
5a15ab5b
CE		 9926 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9927 * brightness value
4dca20ef
CE		 9928 */
9929static void quirk_invert_brightness(struct drm_device *dev)
9930{
9931 struct drm_i915_private *dev_priv = dev->dev_private;
9932 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 9933 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 9934}
9935
e85843be
KM		 9936/*
9937 * Some machines (Dell XPS13) suffer broken backlight controls if
9938 * BLM_PCH_PWM_ENABLE is set.
9939 */
9940static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
9941{
9942 struct drm_i915_private *dev_priv = dev->dev_private;
9943 dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
9944 DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
9945}
9946
b690e96c
JB		 9947struct intel_quirk {
9948 int device;
9949 int subsystem_vendor;
9950 int subsystem_device;
9951 void (*hook)(struct drm_device *dev);
9952};
9953
5f85f176
EE		 9954/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9955struct intel_dmi_quirk {
9956 void (*hook)(struct drm_device *dev);
9957 const struct dmi_system_id (*dmi_id_list)[];
9958};
9959
9960static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9961{
9962 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9963 return 1;
9964}
9965
9966static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9967 {
9968 .dmi_id_list = &(const struct dmi_system_id[]) {
9969 {
9970 .callback = intel_dmi_reverse_brightness,
9971 .ident = "NCR Corporation",
9972 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9973 DMI_MATCH(DMI_PRODUCT_NAME, ""),
9974 },
9975 },
9976 { } /* terminating entry */
9977 },
9978 .hook = quirk_invert_brightness,
9979 },
9980};
9981
c43b5634 9982static struct intel_quirk intel_quirks[] = {
b690e96c 9983 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 9984 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 9985
b690e96c
JB		 9986 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9987 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9988
b690e96c
JB		 9989 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9990 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9991
ccd0d36e 9992 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 9993 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 9994 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 9995
9996 /* Lenovo U160 cannot use SSC on LVDS */
9997 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 9998
9999 /* Sony Vaio Y cannot use SSC on LVDS */
10000 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 10001
10002 /* Acer Aspire 5734Z must invert backlight brightness */
10003 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 10004
10005 /* Acer/eMachines G725 */
10006 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 10007
10008 /* Acer/eMachines e725 */
10009 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 10010
10011 /* Acer/Packard Bell NCL20 */
10012 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 10013
10014 /* Acer Aspire 4736Z */
10015 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
e85843be
KM		 10016
10017 /* Dell XPS13 HD Sandy Bridge */
10018 { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
10019 /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
10020 { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
b690e96c
JB		 10021};
10022
10023static void intel_init_quirks(struct drm_device *dev)
10024{
10025 struct pci_dev *d = dev->pdev;
10026 int i;
10027
10028 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
10029 struct intel_quirk *q = &intel_quirks[i];
10030
10031 if (d->device == q->device &&
10032 (d->subsystem_vendor == q->subsystem_vendor ||
10033 q->subsystem_vendor == PCI_ANY_ID) &&
10034 (d->subsystem_device == q->subsystem_device ||
10035 q->subsystem_device == PCI_ANY_ID))
10036 q->hook(dev);
10037 }
5f85f176
EE		 10038 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10039 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10040 intel_dmi_quirks[i].hook(dev);
10041 }
b690e96c
JB		 10042}
10043
9cce37f4
JB		 10044/* Disable the VGA plane that we never use */
10045static void i915_disable_vga(struct drm_device *dev)
10046{
10047 struct drm_i915_private *dev_priv = dev->dev_private;
10048 u8 sr1;
766aa1c4 10049 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 10050
10051 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 10052 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 10053 sr1 = inb(VGA_SR_DATA);
10054 outb(sr1 | 1<<5, VGA_SR_DATA);
81b5c7bc
AW		 10055
10056 /* Disable VGA memory on Intel HD */
10057 if (HAS_PCH_SPLIT(dev)) {
10058 outb(inb(VGA_MSR_READ) & ~VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10059 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10060 VGA_RSRC_NORMAL_IO |
10061 VGA_RSRC_NORMAL_MEM);
10062 }
10063
9cce37f4
JB		 10064 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10065 udelay(300);
10066
10067 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10068 POSTING_READ(vga_reg);
10069}
10070
81b5c7bc
AW		 10071static void i915_enable_vga(struct drm_device *dev)
10072{
10073 /* Enable VGA memory on Intel HD */
10074 if (HAS_PCH_SPLIT(dev)) {
10075 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10076 outb(inb(VGA_MSR_READ) | VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10077 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10078 VGA_RSRC_LEGACY_MEM |
10079 VGA_RSRC_NORMAL_IO |
10080 VGA_RSRC_NORMAL_MEM);
10081 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10082 }
10083}
10084
f817586c
DV		 10085void intel_modeset_init_hw(struct drm_device *dev)
10086{
fa42e23c 10087 intel_init_power_well(dev);
0232e927 10088
a8f78b58
ED		 10089 intel_prepare_ddi(dev);
10090
f817586c
DV		 10091 intel_init_clock_gating(dev);
10092
79f5b2c7 10093 mutex_lock(&dev->struct_mutex);
8090c6b9 10094 intel_enable_gt_powersave(dev);
79f5b2c7 10095 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 10096}
10097
7d708ee4
ID		 10098void intel_modeset_suspend_hw(struct drm_device *dev)
10099{
10100 intel_suspend_hw(dev);
10101}
10102
79e53945
JB		 10103void intel_modeset_init(struct drm_device *dev)
10104{
652c393a 10105 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 10106 int i, j, ret;
79e53945
JB		 10107
10108 drm_mode_config_init(dev);
10109
10110 dev->mode_config.min_width = 0;
10111 dev->mode_config.min_height = 0;
10112
019d96cb
DA		 10113 dev->mode_config.preferred_depth = 24;
10114 dev->mode_config.prefer_shadow = 1;
10115
e6ecefaa 10116 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 10117
b690e96c
JB		 10118 intel_init_quirks(dev);
10119
1fa61106
ED		 10120 intel_init_pm(dev);
10121
e3c74757
BW		 10122 if (INTEL_INFO(dev)->num_pipes == 0)
10123 return;
10124
e70236a8
JB		 10125 intel_init_display(dev);
10126
a6c45cf0
CW		 10127 if (IS_GEN2(dev)) {
10128 dev->mode_config.max_width = 2048;
10129 dev->mode_config.max_height = 2048;
10130 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 10131 dev->mode_config.max_width = 4096;
10132 dev->mode_config.max_height = 4096;
79e53945 10133 } else {
a6c45cf0
CW		 10134 dev->mode_config.max_width = 8192;
10135 dev->mode_config.max_height = 8192;
79e53945 10136 }
5d4545ae 10137 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 10138
28c97730 10139 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 10140 INTEL_INFO(dev)->num_pipes,
10141 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 10142
08e2a7de 10143 for_each_pipe(i) {
79e53945 10144 intel_crtc_init(dev, i);
7f1f3851
JB		 10145 for (j = 0; j < dev_priv->num_plane; j++) {
10146 ret = intel_plane_init(dev, i, j);
10147 if (ret)
06da8da2
VS		 10148 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10149 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 10150 }
79e53945
JB		 10151 }
10152
79f689aa 10153 intel_cpu_pll_init(dev);
e72f9fbf 10154 intel_shared_dpll_init(dev);
ee7b9f93 10155
9cce37f4
JB		 10156 /* Just disable it once at startup */
10157 i915_disable_vga(dev);
79e53945 10158 intel_setup_outputs(dev);
11be49eb
CW		 10159
10160 /* Just in case the BIOS is doing something questionable. */
10161 intel_disable_fbc(dev);
2c7111db
CW		 10162}
10163
24929352
DV		 10164static void
10165intel_connector_break_all_links(struct intel_connector *connector)
10166{
10167 connector->base.dpms = DRM_MODE_DPMS_OFF;
10168 connector->base.encoder = NULL;
10169 connector->encoder->connectors_active = false;
10170 connector->encoder->base.crtc = NULL;
10171}
10172
7fad798e
DV		 10173static void intel_enable_pipe_a(struct drm_device *dev)
10174{
10175 struct intel_connector *connector;
10176 struct drm_connector *crt = NULL;
10177 struct intel_load_detect_pipe load_detect_temp;
10178
10179 /* We can't just switch on the pipe A, we need to set things up with a
10180 * proper mode and output configuration. As a gross hack, enable pipe A
10181 * by enabling the load detect pipe once. */
10182 list_for_each_entry(connector,
10183 &dev->mode_config.connector_list,
10184 base.head) {
10185 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
10186 crt = &connector->base;
10187 break;
10188 }
10189 }
10190
10191 if (!crt)
10192 return;
10193
10194 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
10195 intel_release_load_detect_pipe(crt, &load_detect_temp);
10196
652c393a 10197
7fad798e
DV		 10198}
10199
fa555837
DV		 10200static bool
10201intel_check_plane_mapping(struct intel_crtc *crtc)
10202{
7eb552ae
BW		 10203 struct drm_device *dev = crtc->base.dev;
10204 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 10205 u32 reg, val;
10206
7eb552ae 10207 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 10208 return true;
10209
10210 reg = DSPCNTR(!crtc->plane);
10211 val = I915_READ(reg);
10212
10213 if ((val & DISPLAY_PLANE_ENABLE) &&
10214 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
10215 return false;
10216
10217 return true;
10218}
10219
24929352
DV		 10220static void intel_sanitize_crtc(struct intel_crtc *crtc)
10221{
10222 struct drm_device *dev = crtc->base.dev;
10223 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 10224 u32 reg;
24929352 10225
24929352 10226 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 10227 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 10228 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
10229
10230 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 10231 * disable the crtc (and hence change the state) if it is wrong. Note
10232 * that gen4+ has a fixed plane -> pipe mapping. */
10233 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 10234 struct intel_connector *connector;
10235 bool plane;
10236
24929352
DV		 10237 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10238 crtc->base.base.id);
10239
10240 /* Pipe has the wrong plane attached and the plane is active.
10241 * Temporarily change the plane mapping and disable everything
10242 * ... */
10243 plane = crtc->plane;
10244 crtc->plane = !plane;
10245 dev_priv->display.crtc_disable(&crtc->base);
10246 crtc->plane = plane;
10247
10248 /* ... and break all links. */
10249 list_for_each_entry(connector, &dev->mode_config.connector_list,
10250 base.head) {
10251 if (connector->encoder->base.crtc != &crtc->base)
10252 continue;
10253
10254 intel_connector_break_all_links(connector);
10255 }
10256
10257 WARN_ON(crtc->active);
10258 crtc->base.enabled = false;
10259 }
24929352 10260
7fad798e
DV		 10261 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
10262 crtc->pipe == PIPE_A && !crtc->active) {
10263 /* BIOS forgot to enable pipe A, this mostly happens after
10264 * resume. Force-enable the pipe to fix this, the update_dpms
10265 * call below we restore the pipe to the right state, but leave
10266 * the required bits on. */
10267 intel_enable_pipe_a(dev);
10268 }
10269
24929352
DV		 10270 /* Adjust the state of the output pipe according to whether we
10271 * have active connectors/encoders. */
10272 intel_crtc_update_dpms(&crtc->base);
10273
10274 if (crtc->active != crtc->base.enabled) {
10275 struct intel_encoder *encoder;
10276
10277 /* This can happen either due to bugs in the get_hw_state
10278 * functions or because the pipe is force-enabled due to the
10279 * pipe A quirk. */
10280 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10281 crtc->base.base.id,
10282 crtc->base.enabled ? "enabled" : "disabled",
10283 crtc->active ? "enabled" : "disabled");
10284
10285 crtc->base.enabled = crtc->active;
10286
10287 /* Because we only establish the connector -> encoder ->
10288 * crtc links if something is active, this means the
10289 * crtc is now deactivated. Break the links. connector
10290 * -> encoder links are only establish when things are
10291 * actually up, hence no need to break them. */
10292 WARN_ON(crtc->active);
10293
10294 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
10295 WARN_ON(encoder->connectors_active);
10296 encoder->base.crtc = NULL;
10297 }
10298 }
10299}
10300
10301static void intel_sanitize_encoder(struct intel_encoder *encoder)
10302{
10303 struct intel_connector *connector;
10304 struct drm_device *dev = encoder->base.dev;
10305
10306 /* We need to check both for a crtc link (meaning that the
10307 * encoder is active and trying to read from a pipe) and the
10308 * pipe itself being active. */
10309 bool has_active_crtc = encoder->base.crtc &&
10310 to_intel_crtc(encoder->base.crtc)->active;
10311
10312 if (encoder->connectors_active && !has_active_crtc) {
10313 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10314 encoder->base.base.id,
10315 drm_get_encoder_name(&encoder->base));
10316
10317 /* Connector is active, but has no active pipe. This is
10318 * fallout from our resume register restoring. Disable
10319 * the encoder manually again. */
10320 if (encoder->base.crtc) {
10321 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10322 encoder->base.base.id,
10323 drm_get_encoder_name(&encoder->base));
10324 encoder->disable(encoder);
10325 }
10326
10327 /* Inconsistent output/port/pipe state happens presumably due to
10328 * a bug in one of the get_hw_state functions. Or someplace else
10329 * in our code, like the register restore mess on resume. Clamp
10330 * things to off as a safer default. */
10331 list_for_each_entry(connector,
10332 &dev->mode_config.connector_list,
10333 base.head) {
10334 if (connector->encoder != encoder)
10335 continue;
10336
10337 intel_connector_break_all_links(connector);
10338 }
10339 }
10340 /* Enabled encoders without active connectors will be fixed in
10341 * the crtc fixup. */
10342}
10343
44cec740 10344void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 10345{
10346 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 10347 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 10348
8dc8a27c
PZ		 10349 /* This function can be called both from intel_modeset_setup_hw_state or
10350 * at a very early point in our resume sequence, where the power well
10351 * structures are not yet restored. Since this function is at a very
10352 * paranoid "someone might have enabled VGA while we were not looking"
10353 * level, just check if the power well is enabled instead of trying to
10354 * follow the "don't touch the power well if we don't need it" policy
10355 * the rest of the driver uses. */
10356 if (HAS_POWER_WELL(dev) &&
6aedd1f5 10357 (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
8dc8a27c
PZ		 10358 return;
10359
0fde901f
KM		 10360 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
10361 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 10362 i915_disable_vga(dev);
0fde901f
KM		 10363 }
10364}
10365
30e984df 10366static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 10367{
10368 struct drm_i915_private *dev_priv = dev->dev_private;
10369 enum pipe pipe;
24929352
DV		 10370 struct intel_crtc *crtc;
10371 struct intel_encoder *encoder;
10372 struct intel_connector *connector;
5358901f 10373 int i;
24929352 10374
0e8ffe1b
DV		 10375 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10376 base.head) {
88adfff1 10377 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f 10378
0e8ffe1b
DV		 10379 crtc->active = dev_priv->display.get_pipe_config(crtc,
10380 &crtc->config);
24929352
DV		 10381
10382 crtc->base.enabled = crtc->active;
10383
10384 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10385 crtc->base.base.id,
10386 crtc->active ? "enabled" : "disabled");
10387 }
10388
5358901f 10389 /* FIXME: Smash this into the new shared dpll infrastructure. */
affa9354 10390 if (HAS_DDI(dev))
6441ab5f
PZ		 10391 intel_ddi_setup_hw_pll_state(dev);
10392
5358901f
DV		 10393 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10394 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10395
10396 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
10397 pll->active = 0;
10398 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10399 base.head) {
10400 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10401 pll->active++;
10402 }
10403 pll->refcount = pll->active;
10404
35c95375
DV		 10405 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10406 pll->name, pll->refcount, pll->on);
5358901f
DV		 10407 }
10408
24929352
DV		 10409 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10410 base.head) {
10411 pipe = 0;
10412
10413 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 10414 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10415 encoder->base.crtc = &crtc->base;
510d5f2f 10416 if (encoder->get_config)
045ac3b5 10417 encoder->get_config(encoder, &crtc->config);
24929352
DV		 10418 } else {
10419 encoder->base.crtc = NULL;
10420 }
10421
10422 encoder->connectors_active = false;
10423 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
10424 encoder->base.base.id,
10425 drm_get_encoder_name(&encoder->base),
10426 encoder->base.crtc ? "enabled" : "disabled",
10427 pipe);
10428 }
10429
510d5f2f
JB		 10430 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10431 base.head) {
10432 if (!crtc->active)
10433 continue;
10434 if (dev_priv->display.get_clock)
10435 dev_priv->display.get_clock(crtc,
10436 &crtc->config);
10437 }
10438
24929352
DV		 10439 list_for_each_entry(connector, &dev->mode_config.connector_list,
10440 base.head) {
10441 if (connector->get_hw_state(connector)) {
10442 connector->base.dpms = DRM_MODE_DPMS_ON;
10443 connector->encoder->connectors_active = true;
10444 connector->base.encoder = &connector->encoder->base;
10445 } else {
10446 connector->base.dpms = DRM_MODE_DPMS_OFF;
10447 connector->base.encoder = NULL;
10448 }
10449 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10450 connector->base.base.id,
10451 drm_get_connector_name(&connector->base),
10452 connector->base.encoder ? "enabled" : "disabled");
10453 }
30e984df
DV		 10454}
10455
10456/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10457 * and i915 state tracking structures. */
10458void intel_modeset_setup_hw_state(struct drm_device *dev,
10459 bool force_restore)
10460{
10461 struct drm_i915_private *dev_priv = dev->dev_private;
10462 enum pipe pipe;
10463 struct drm_plane *plane;
10464 struct intel_crtc *crtc;
10465 struct intel_encoder *encoder;
35c95375 10466 int i;
30e984df
DV		 10467
10468 intel_modeset_readout_hw_state(dev);
24929352 10469
babea61d
JB		 10470 /*
10471 * Now that we have the config, copy it to each CRTC struct
10472 * Note that this could go away if we move to using crtc_config
10473 * checking everywhere.
10474 */
10475 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10476 base.head) {
10477 if (crtc->active && i915_fastboot) {
10478 intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10479
10480 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10481 crtc->base.base.id);
10482 drm_mode_debug_printmodeline(&crtc->base.mode);
10483 }
10484 }
10485
24929352
DV		 10486 /* HW state is read out, now we need to sanitize this mess. */
10487 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10488 base.head) {
10489 intel_sanitize_encoder(encoder);
10490 }
10491
10492 for_each_pipe(pipe) {
10493 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10494 intel_sanitize_crtc(crtc);
c0b03411 10495 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
24929352 10496 }
9a935856 10497
35c95375
DV		 10498 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10499 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10500
10501 if (!pll->on || pll->active)
10502 continue;
10503
10504 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
10505
10506 pll->disable(dev_priv, pll);
10507 pll->on = false;
10508 }
10509
45e2b5f6 10510 if (force_restore) {
f30da187
DV		 10511 /*
10512 * We need to use raw interfaces for restoring state to avoid
10513 * checking (bogus) intermediate states.
10514 */
45e2b5f6 10515 for_each_pipe(pipe) {
b5644d05
JB		 10516 struct drm_crtc *crtc =
10517 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 10518
10519 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10520 crtc->fb);
45e2b5f6 10521 }
b5644d05
JB		 10522 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
10523 intel_plane_restore(plane);
0fde901f
KM		 10524
10525 i915_redisable_vga(dev);
45e2b5f6
DV		 10526 } else {
10527 intel_modeset_update_staged_output_state(dev);
10528 }
8af6cf88
DV		 10529
10530 intel_modeset_check_state(dev);
2e938892
DV		 10531
10532 drm_mode_config_reset(dev);
2c7111db
CW		 10533}
10534
10535void intel_modeset_gem_init(struct drm_device *dev)
10536{
1833b134 10537 intel_modeset_init_hw(dev);
02e792fb
DV		 10538
10539 intel_setup_overlay(dev);
24929352 10540
45e2b5f6 10541 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 10542}
10543
10544void intel_modeset_cleanup(struct drm_device *dev)
10545{
652c393a
JB		 10546 struct drm_i915_private *dev_priv = dev->dev_private;
10547 struct drm_crtc *crtc;
652c393a 10548
fd0c0642
DV		 10549 /*
10550 * Interrupts and polling as the first thing to avoid creating havoc.
10551 * Too much stuff here (turning of rps, connectors, ...) would
10552 * experience fancy races otherwise.
10553 */
10554 drm_irq_uninstall(dev);
10555 cancel_work_sync(&dev_priv->hotplug_work);
10556 /*
10557 * Due to the hpd irq storm handling the hotplug work can re-arm the
10558 * poll handlers. Hence disable polling after hpd handling is shut down.
10559 */
f87ea761 10560 drm_kms_helper_poll_fini(dev);
fd0c0642 10561
652c393a
JB		 10562 mutex_lock(&dev->struct_mutex);
10563
723bfd70
JB		 10564 intel_unregister_dsm_handler();
10565
652c393a
JB		 10566 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10567 /* Skip inactive CRTCs */
10568 if (!crtc->fb)
10569 continue;
10570
3dec0095 10571 intel_increase_pllclock(crtc);
652c393a
JB		 10572 }
10573
973d04f9 10574 intel_disable_fbc(dev);
e70236a8 10575
81b5c7bc
AW		 10576 i915_enable_vga(dev);
10577
8090c6b9 10578 intel_disable_gt_powersave(dev);
0cdab21f 10579
930ebb46
DV		 10580 ironlake_teardown_rc6(dev);
10581
69341a5e
KH		 10582 mutex_unlock(&dev->struct_mutex);
10583
1630fe75
CW		 10584 /* flush any delayed tasks or pending work */
10585 flush_scheduled_work();
10586
dc652f90
JN		 10587 /* destroy backlight, if any, before the connectors */
10588 intel_panel_destroy_backlight(dev);
10589
79e53945 10590 drm_mode_config_cleanup(dev);
4d7bb011
DV		 10591
10592 intel_cleanup_overlay(dev);
79e53945
JB		 10593}
10594
f1c79df3
ZW		 10595/*
10596 * Return which encoder is currently attached for connector.
10597 */
df0e9248 10598struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 10599{
df0e9248
CW		 10600 return &intel_attached_encoder(connector)->base;
10601}
f1c79df3 10602
df0e9248
CW		 10603void intel_connector_attach_encoder(struct intel_connector *connector,
10604 struct intel_encoder *encoder)
10605{
10606 connector->encoder = encoder;
10607 drm_mode_connector_attach_encoder(&connector->base,
10608 &encoder->base);
79e53945 10609}
28d52043
DA		 10610
10611/*
10612 * set vga decode state - true == enable VGA decode
10613 */
10614int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10615{
10616 struct drm_i915_private *dev_priv = dev->dev_private;
10617 u16 gmch_ctrl;
10618
10619 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
10620 if (state)
10621 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10622 else
10623 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10624 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10625 return 0;
10626}
c4a1d9e4 10627
c4a1d9e4 10628struct intel_display_error_state {
ff57f1b0
PZ		 10629
10630 u32 power_well_driver;
10631
63b66e5b
CW		 10632 int num_transcoders;
10633
c4a1d9e4
CW		 10634 struct intel_cursor_error_state {
10635 u32 control;
10636 u32 position;
10637 u32 base;
10638 u32 size;
52331309 10639 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 10640
10641 struct intel_pipe_error_state {
c4a1d9e4 10642 u32 source;
52331309 10643 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 10644
10645 struct intel_plane_error_state {
10646 u32 control;
10647 u32 stride;
10648 u32 size;
10649 u32 pos;
10650 u32 addr;
10651 u32 surface;
10652 u32 tile_offset;
52331309 10653 } plane[I915_MAX_PIPES];
63b66e5b
CW		 10654
10655 struct intel_transcoder_error_state {
10656 enum transcoder cpu_transcoder;
10657
10658 u32 conf;
10659
10660 u32 htotal;
10661 u32 hblank;
10662 u32 hsync;
10663 u32 vtotal;
10664 u32 vblank;
10665 u32 vsync;
10666 } transcoder[4];
c4a1d9e4
CW		 10667};
10668
10669struct intel_display_error_state *
10670intel_display_capture_error_state(struct drm_device *dev)
10671{
0206e353 10672 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 10673 struct intel_display_error_state *error;
63b66e5b
CW		 10674 int transcoders[] = {
10675 TRANSCODER_A,
10676 TRANSCODER_B,
10677 TRANSCODER_C,
10678 TRANSCODER_EDP,
10679 };
c4a1d9e4
CW		 10680 int i;
10681
63b66e5b
CW		 10682 if (INTEL_INFO(dev)->num_pipes == 0)
10683 return NULL;
10684
c4a1d9e4
CW		 10685 error = kmalloc(sizeof(*error), GFP_ATOMIC);
10686 if (error == NULL)
10687 return NULL;
10688
ff57f1b0
PZ		 10689 if (HAS_POWER_WELL(dev))
10690 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10691
52331309 10692 for_each_pipe(i) {
a18c4c3d
PZ		 10693 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10694 error->cursor[i].control = I915_READ(CURCNTR(i));
10695 error->cursor[i].position = I915_READ(CURPOS(i));
10696 error->cursor[i].base = I915_READ(CURBASE(i));
10697 } else {
10698 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10699 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10700 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10701 }
c4a1d9e4
CW		 10702
10703 error->plane[i].control = I915_READ(DSPCNTR(i));
10704 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 10705 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 10706 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 10707 error->plane[i].pos = I915_READ(DSPPOS(i));
10708 }
ca291363
PZ		 10709 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10710 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 10711 if (INTEL_INFO(dev)->gen >= 4) {
10712 error->plane[i].surface = I915_READ(DSPSURF(i));
10713 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10714 }
10715
c4a1d9e4 10716 error->pipe[i].source = I915_READ(PIPESRC(i));
63b66e5b
CW		 10717 }
10718
10719 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
10720 if (HAS_DDI(dev_priv->dev))
10721 error->num_transcoders++; /* Account for eDP. */
10722
10723 for (i = 0; i < error->num_transcoders; i++) {
10724 enum transcoder cpu_transcoder = transcoders[i];
10725
10726 error->transcoder[i].cpu_transcoder = cpu_transcoder;
10727
10728 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
10729 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10730 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10731 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10732 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10733 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10734 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 10735 }
10736
12d217c7
PZ		 10737 /* In the code above we read the registers without checking if the power
10738 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10739 * prevent the next I915_WRITE from detecting it and printing an error
10740 * message. */
907b28c5 10741 intel_uncore_clear_errors(dev);
12d217c7 10742
c4a1d9e4
CW		 10743 return error;
10744}
10745
edc3d884
MK		 10746#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10747
c4a1d9e4 10748void
edc3d884 10749intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 10750 struct drm_device *dev,
10751 struct intel_display_error_state *error)
10752{
10753 int i;
10754
63b66e5b
CW		 10755 if (!error)
10756 return;
10757
edc3d884 10758 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
ff57f1b0 10759 if (HAS_POWER_WELL(dev))
edc3d884 10760 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 10761 error->power_well_driver);
52331309 10762 for_each_pipe(i) {
edc3d884 10763 err_printf(m, "Pipe [%d]:\n", i);
edc3d884 10764 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
edc3d884
MK		 10765
10766 err_printf(m, "Plane [%d]:\n", i);
10767 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
10768 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 10769 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 10770 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
10771 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 10772 }
4b71a570 10773 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 10774 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 10775 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 10776 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
10777 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 10778 }
10779
edc3d884
MK		 10780 err_printf(m, "Cursor [%d]:\n", i);
10781 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
10782 err_printf(m, " POS: %08x\n", error->cursor[i].position);
10783 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 10784 }
63b66e5b
CW		 10785
10786 for (i = 0; i < error->num_transcoders; i++) {
10787 err_printf(m, " CPU transcoder: %c\n",
10788 transcoder_name(error->transcoder[i].cpu_transcoder));
10789 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
10790 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
10791 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
10792 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
10793 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
10794 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
10795 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
10796 }
c4a1d9e4 10797}
Linux 6.x block layer and io_uring tree(s)