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b978520d MW |
1 | /* |
2 | * Copyright © 2014-2017 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | ||
25 | #ifndef _INTEL_DEVICE_INFO_H_ | |
26 | #define _INTEL_DEVICE_INFO_H_ | |
27 | ||
4bdafb9d CW |
28 | #include <uapi/drm/i915_drm.h> |
29 | ||
439c8dcc JN |
30 | #include "intel_step.h" |
31 | ||
df0566a6 JN |
32 | #include "display/intel_display.h" |
33 | ||
112ed2d3 CW |
34 | #include "gt/intel_engine_types.h" |
35 | #include "gt/intel_context_types.h" | |
36 | #include "gt/intel_sseu.h" | |
37 | ||
b978520d MW |
38 | struct drm_printer; |
39 | struct drm_i915_private; | |
40 | ||
41 | /* Keep in gen based order, and chronological order within a gen */ | |
42 | enum intel_platform { | |
43 | INTEL_PLATFORM_UNINITIALIZED = 0, | |
44 | /* gen2 */ | |
45 | INTEL_I830, | |
46 | INTEL_I845G, | |
47 | INTEL_I85X, | |
48 | INTEL_I865G, | |
49 | /* gen3 */ | |
50 | INTEL_I915G, | |
51 | INTEL_I915GM, | |
52 | INTEL_I945G, | |
53 | INTEL_I945GM, | |
54 | INTEL_G33, | |
55 | INTEL_PINEVIEW, | |
56 | /* gen4 */ | |
57 | INTEL_I965G, | |
58 | INTEL_I965GM, | |
59 | INTEL_G45, | |
60 | INTEL_GM45, | |
61 | /* gen5 */ | |
62 | INTEL_IRONLAKE, | |
63 | /* gen6 */ | |
64 | INTEL_SANDYBRIDGE, | |
65 | /* gen7 */ | |
66 | INTEL_IVYBRIDGE, | |
67 | INTEL_VALLEYVIEW, | |
68 | INTEL_HASWELL, | |
69 | /* gen8 */ | |
70 | INTEL_BROADWELL, | |
71 | INTEL_CHERRYVIEW, | |
72 | /* gen9 */ | |
73 | INTEL_SKYLAKE, | |
74 | INTEL_BROXTON, | |
75 | INTEL_KABYLAKE, | |
76 | INTEL_GEMINILAKE, | |
77 | INTEL_COFFEELAKE, | |
5f4ae270 | 78 | INTEL_COMETLAKE, |
41231001 RV |
79 | /* gen11 */ |
80 | INTEL_ICELAKE, | |
897f2961 | 81 | INTEL_ELKHARTLAKE, |
24ea098b | 82 | INTEL_JASPERLAKE, |
abd3a0fe DCS |
83 | /* gen12 */ |
84 | INTEL_TIGERLAKE, | |
123f62de | 85 | INTEL_ROCKETLAKE, |
05e26584 | 86 | INTEL_DG1, |
0883d63b | 87 | INTEL_ALDERLAKE_S, |
bdd27cad | 88 | INTEL_ALDERLAKE_P, |
086df54e | 89 | INTEL_XEHPSDV, |
9e22cfc5 | 90 | INTEL_DG2, |
448a54ac | 91 | INTEL_PONTEVECCHIO, |
bcf9b296 | 92 | INTEL_METEORLAKE, |
b978520d MW |
93 | INTEL_MAX_PLATFORMS |
94 | }; | |
95 | ||
805446c8 TU |
96 | /* |
97 | * Subplatform bits share the same namespace per parent platform. In other words | |
98 | * it is fine for the same bit to be used on multiple parent platforms. | |
99 | */ | |
100 | ||
86df4141 | 101 | #define INTEL_SUBPLATFORM_BITS (3) |
56afa701 | 102 | #define INTEL_SUBPLATFORM_MASK (BIT(INTEL_SUBPLATFORM_BITS) - 1) |
805446c8 TU |
103 | |
104 | /* HSW/BDW/SKL/KBL/CFL */ | |
105 | #define INTEL_SUBPLATFORM_ULT (0) | |
106 | #define INTEL_SUBPLATFORM_ULX (1) | |
805446c8 | 107 | |
244dba4c | 108 | /* ICL */ |
805446c8 TU |
109 | #define INTEL_SUBPLATFORM_PORTF (0) |
110 | ||
b9ef8939 JRS |
111 | /* TGL */ |
112 | #define INTEL_SUBPLATFORM_UY (0) | |
113 | ||
9e22cfc5 MR |
114 | /* DG2 */ |
115 | #define INTEL_SUBPLATFORM_G10 0 | |
116 | #define INTEL_SUBPLATFORM_G11 1 | |
86df4141 | 117 | #define INTEL_SUBPLATFORM_G12 2 |
9e22cfc5 | 118 | |
72c3c8d6 MA |
119 | /* ADL */ |
120 | #define INTEL_SUBPLATFORM_RPL 0 | |
52407c22 | 121 | |
7e28d0b2 | 122 | /* ADL-P */ |
72c3c8d6 MA |
123 | /* |
124 | * As #define INTEL_SUBPLATFORM_RPL 0 will apply | |
125 | * here too, SUBPLATFORM_N will have different | |
126 | * bit set | |
127 | */ | |
128 | #define INTEL_SUBPLATFORM_N 1 | |
7e28d0b2 | 129 | |
78353039 RS |
130 | /* MTL */ |
131 | #define INTEL_SUBPLATFORM_M 0 | |
132 | #define INTEL_SUBPLATFORM_P 1 | |
133 | ||
cbecbcca | 134 | enum intel_ppgtt_type { |
4bdafb9d CW |
135 | INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE, |
136 | INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING, | |
137 | INTEL_PPGTT_FULL = I915_GEM_PPGTT_FULL, | |
4bdafb9d CW |
138 | }; |
139 | ||
b978520d MW |
140 | #define DEV_INFO_FOR_EACH_FLAG(func) \ |
141 | func(is_mobile); \ | |
142 | func(is_lp); \ | |
7ef5ef5c | 143 | func(require_force_probe); \ |
dc90fe3f | 144 | func(is_dgfx); \ |
b978520d MW |
145 | /* Keep has_* in alphabetical order */ \ |
146 | func(has_64bit_reloc); \ | |
c83125bb | 147 | func(has_64k_pages); \ |
132aaaf0 | 148 | func(needs_compact_pt); \ |
55277e1f | 149 | func(gpu_reset_clobbers_display); \ |
b409db08 | 150 | func(has_reset_engine); \ |
1eb31338 | 151 | func(has_3d_pipeline); \ |
072ce416 | 152 | func(has_4tile); \ |
5e3094cf | 153 | func(has_flat_ccs); \ |
a7a7a0e6 | 154 | func(has_global_mocs); \ |
c2c70752 | 155 | func(has_gmd_id); \ |
39921e5f | 156 | func(has_gt_uc); \ |
1e3dc1d8 TW |
157 | func(has_heci_pxp); \ |
158 | func(has_heci_gscfi); \ | |
db3b3f3e | 159 | func(has_guc_deprivilege); \ |
9d67edba | 160 | func(has_l3_ccs_read); \ |
b978520d MW |
161 | func(has_l3_dpf); \ |
162 | func(has_llc); \ | |
163 | func(has_logical_ring_contexts); \ | |
3d6c72b7 | 164 | func(has_logical_ring_elsq); \ |
85a040bc | 165 | func(has_media_ratio_mode); \ |
e0d7371b | 166 | func(has_mslice_steering); \ |
5ac342ef | 167 | func(has_one_eu_per_fuse_bit); \ |
e6aa7136 | 168 | func(has_pxp); \ |
fdbec9ff | 169 | func(has_rc6); \ |
b978520d | 170 | func(has_rc6p); \ |
91cbdb83 | 171 | func(has_rps); \ |
b978520d MW |
172 | func(has_runtime_pm); \ |
173 | func(has_snoop); \ | |
900ccf30 | 174 | func(has_coherent_ggtt); \ |
b978520d | 175 | func(unfenced_needs_alignment); \ |
d53db442 JRS |
176 | func(hws_needs_physical); |
177 | ||
178 | #define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \ | |
179 | /* Keep in alphabetical order */ \ | |
b978520d | 180 | func(cursor_needs_physical); \ |
eafaa3e9 | 181 | func(has_cdclk_crawl); \ |
9d8d5a39 | 182 | func(has_ddi); \ |
e91eec91 | 183 | func(has_dp_mst); \ |
18febcb7 | 184 | func(has_dsb); \ |
a321c3c6 | 185 | func(has_fpga_dbg); \ |
b2ae318a | 186 | func(has_gmch); \ |
d53db442 | 187 | func(has_hotplug); \ |
ddff9a60 | 188 | func(has_hti); \ |
d53db442 | 189 | func(has_ipc); \ |
0caf6257 | 190 | func(has_modular_fia); \ |
d53db442 | 191 | func(has_overlay); \ |
9602efab | 192 | func(has_psr); \ |
24d2fc3d | 193 | func(has_psr_hw_tracking); \ |
b978520d | 194 | func(overlay_needs_physical); \ |
d53db442 | 195 | func(supports_tv); |
b978520d | 196 | |
ef7e222c | 197 | struct intel_ip_version { |
a5b7ef27 JRS |
198 | u8 ver; |
199 | u8 rel; | |
c2c70752 | 200 | u8 step; |
a5b7ef27 JRS |
201 | }; |
202 | ||
2c93e7b7 | 203 | struct intel_runtime_info { |
c2c70752 MR |
204 | /* |
205 | * Single "graphics" IP version that represents | |
206 | * render, compute and copy behavior. | |
207 | */ | |
f9e932a8 | 208 | struct { |
ef7e222c | 209 | struct intel_ip_version ip; |
f9e932a8 RS |
210 | } graphics; |
211 | struct { | |
ef7e222c | 212 | struct intel_ip_version ip; |
f9e932a8 RS |
213 | } media; |
214 | struct { | |
ef7e222c | 215 | struct intel_ip_version ip; |
f9e932a8 | 216 | } display; |
43ba44a1 | 217 | |
2c93e7b7 JN |
218 | /* |
219 | * Platform mask is used for optimizing or-ed IS_PLATFORM calls into | |
220 | * single runtime conditionals, and also to provide groundwork for | |
221 | * future per platform, or per SKU build optimizations. | |
222 | * | |
223 | * Array can be extended when necessary if the corresponding | |
224 | * BUILD_BUG_ON is hit. | |
225 | */ | |
226 | u32 platform_mask[2]; | |
227 | ||
228 | u16 device_id; | |
229 | ||
488e29fe JN |
230 | intel_engine_mask_t platform_engine_mask; /* Engines supported by the HW */ |
231 | ||
2c93e7b7 JN |
232 | u32 rawclk_freq; |
233 | ||
234 | struct intel_step_info step; | |
e6f19648 | 235 | |
9d0bad17 JN |
236 | unsigned int page_sizes; /* page sizes supported by the HW */ |
237 | ||
268c67e5 JN |
238 | enum intel_ppgtt_type ppgtt_type; |
239 | unsigned int ppgtt_size; /* log2, e.g. 31/32/48 bits */ | |
240 | ||
f81f30b3 JN |
241 | u32 memory_regions; /* regions supported by the HW */ |
242 | ||
39a445bb JN |
243 | bool has_pooled_eu; |
244 | ||
e6f19648 JN |
245 | /* display */ |
246 | struct { | |
00c6cbfd JN |
247 | u8 pipe_mask; |
248 | u8 cpu_transcoder_mask; | |
249 | ||
e6f19648 JN |
250 | u8 num_sprites[I915_MAX_PIPES]; |
251 | u8 num_scalers[I915_MAX_PIPES]; | |
252 | ||
253 | u8 fbc_mask; | |
7578fc4d JN |
254 | |
255 | bool has_hdcp; | |
e26700fc | 256 | bool has_dmc; |
3a9313d8 | 257 | bool has_dsc; |
e6f19648 | 258 | }; |
2c93e7b7 JN |
259 | }; |
260 | ||
b978520d | 261 | struct intel_device_info { |
b978520d | 262 | enum intel_platform platform; |
b978520d | 263 | |
31a02eb7 MR |
264 | unsigned int dma_mask_size; /* available DMA address bits */ |
265 | ||
938c778f JH |
266 | u8 gt; /* GT number, 0 if undefined */ |
267 | ||
b978520d MW |
268 | #define DEFINE_FLAG(name) u8 name:1 |
269 | DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG); | |
270 | #undef DEFINE_FLAG | |
d53db442 JRS |
271 | |
272 | struct { | |
6678916d VS |
273 | u8 abox_mask; |
274 | ||
04155815 VS |
275 | struct { |
276 | u16 size; /* in blocks */ | |
277 | u8 slice_mask; | |
278 | } dbuf; | |
279 | ||
d53db442 JRS |
280 | #define DEFINE_FLAG(name) u8 name:1 |
281 | DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG); | |
282 | #undef DEFINE_FLAG | |
d53db442 | 283 | |
c92df6aa VS |
284 | /* Global register offset for the display engine */ |
285 | u32 mmio_offset; | |
286 | ||
12d74553 | 287 | /* Register offsets for the various display pipes and transcoders */ |
5ba584ec VS |
288 | u32 pipe_offsets[I915_MAX_TRANSCODERS]; |
289 | u32 trans_offsets[I915_MAX_TRANSCODERS]; | |
290 | u32 cursor_offsets[I915_MAX_PIPES]; | |
b978520d | 291 | |
f7fb92cd VS |
292 | struct { |
293 | u32 degamma_lut_size; | |
294 | u32 gamma_lut_size; | |
295 | u32 degamma_lut_tests; | |
296 | u32 gamma_lut_tests; | |
297 | } color; | |
298 | } display; | |
0258404f | 299 | |
805446c8 | 300 | /* |
2c93e7b7 | 301 | * Initial runtime info. Do not access outside of i915_driver_create(). |
805446c8 | 302 | */ |
2c93e7b7 | 303 | const struct intel_runtime_info __runtime; |
b978520d MW |
304 | }; |
305 | ||
3fed1808 CW |
306 | struct intel_driver_caps { |
307 | unsigned int scheduler; | |
481827b4 | 308 | bool has_logical_contexts:1; |
3fed1808 CW |
309 | }; |
310 | ||
b978520d MW |
311 | const char *intel_platform_name(enum intel_platform platform); |
312 | ||
c2c70752 | 313 | void intel_device_info_runtime_init_early(struct drm_i915_private *dev_priv); |
1400cc7e | 314 | void intel_device_info_runtime_init(struct drm_i915_private *dev_priv); |
72404978 | 315 | |
c7d3c844 JN |
316 | void intel_device_info_print(const struct intel_device_info *info, |
317 | const struct intel_runtime_info *runtime, | |
318 | struct drm_printer *p); | |
b978520d | 319 | |
3fed1808 CW |
320 | void intel_driver_caps_print(const struct intel_driver_caps *caps, |
321 | struct drm_printer *p); | |
322 | ||
b978520d | 323 | #endif |