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b978520d MW |
1 | /* |
2 | * Copyright © 2014-2017 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | ||
25 | #ifndef _INTEL_DEVICE_INFO_H_ | |
26 | #define _INTEL_DEVICE_INFO_H_ | |
27 | ||
4bdafb9d CW |
28 | #include <uapi/drm/i915_drm.h> |
29 | ||
df0566a6 JN |
30 | #include "display/intel_display.h" |
31 | ||
112ed2d3 CW |
32 | #include "gt/intel_engine_types.h" |
33 | #include "gt/intel_context_types.h" | |
34 | #include "gt/intel_sseu.h" | |
35 | ||
b978520d MW |
36 | struct drm_printer; |
37 | struct drm_i915_private; | |
38 | ||
39 | /* Keep in gen based order, and chronological order within a gen */ | |
40 | enum intel_platform { | |
41 | INTEL_PLATFORM_UNINITIALIZED = 0, | |
42 | /* gen2 */ | |
43 | INTEL_I830, | |
44 | INTEL_I845G, | |
45 | INTEL_I85X, | |
46 | INTEL_I865G, | |
47 | /* gen3 */ | |
48 | INTEL_I915G, | |
49 | INTEL_I915GM, | |
50 | INTEL_I945G, | |
51 | INTEL_I945GM, | |
52 | INTEL_G33, | |
53 | INTEL_PINEVIEW, | |
54 | /* gen4 */ | |
55 | INTEL_I965G, | |
56 | INTEL_I965GM, | |
57 | INTEL_G45, | |
58 | INTEL_GM45, | |
59 | /* gen5 */ | |
60 | INTEL_IRONLAKE, | |
61 | /* gen6 */ | |
62 | INTEL_SANDYBRIDGE, | |
63 | /* gen7 */ | |
64 | INTEL_IVYBRIDGE, | |
65 | INTEL_VALLEYVIEW, | |
66 | INTEL_HASWELL, | |
67 | /* gen8 */ | |
68 | INTEL_BROADWELL, | |
69 | INTEL_CHERRYVIEW, | |
70 | /* gen9 */ | |
71 | INTEL_SKYLAKE, | |
72 | INTEL_BROXTON, | |
73 | INTEL_KABYLAKE, | |
74 | INTEL_GEMINILAKE, | |
75 | INTEL_COFFEELAKE, | |
76 | /* gen10 */ | |
77 | INTEL_CANNONLAKE, | |
41231001 RV |
78 | /* gen11 */ |
79 | INTEL_ICELAKE, | |
897f2961 | 80 | INTEL_ELKHARTLAKE, |
abd3a0fe DCS |
81 | /* gen12 */ |
82 | INTEL_TIGERLAKE, | |
123f62de | 83 | INTEL_ROCKETLAKE, |
b978520d MW |
84 | INTEL_MAX_PLATFORMS |
85 | }; | |
86 | ||
805446c8 TU |
87 | /* |
88 | * Subplatform bits share the same namespace per parent platform. In other words | |
89 | * it is fine for the same bit to be used on multiple parent platforms. | |
90 | */ | |
91 | ||
92 | #define INTEL_SUBPLATFORM_BITS (3) | |
93 | ||
94 | /* HSW/BDW/SKL/KBL/CFL */ | |
95 | #define INTEL_SUBPLATFORM_ULT (0) | |
96 | #define INTEL_SUBPLATFORM_ULX (1) | |
805446c8 TU |
97 | |
98 | /* CNL/ICL */ | |
99 | #define INTEL_SUBPLATFORM_PORTF (0) | |
100 | ||
cbecbcca | 101 | enum intel_ppgtt_type { |
4bdafb9d CW |
102 | INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE, |
103 | INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING, | |
104 | INTEL_PPGTT_FULL = I915_GEM_PPGTT_FULL, | |
4bdafb9d CW |
105 | }; |
106 | ||
b978520d MW |
107 | #define DEV_INFO_FOR_EACH_FLAG(func) \ |
108 | func(is_mobile); \ | |
109 | func(is_lp); \ | |
7ef5ef5c | 110 | func(require_force_probe); \ |
dc90fe3f | 111 | func(is_dgfx); \ |
b978520d MW |
112 | /* Keep has_* in alphabetical order */ \ |
113 | func(has_64bit_reloc); \ | |
55277e1f | 114 | func(gpu_reset_clobbers_display); \ |
b978520d | 115 | func(has_reset_engine); \ |
b978520d | 116 | func(has_fpga_dbg); \ |
a7a7a0e6 | 117 | func(has_global_mocs); \ |
702668e6 | 118 | func(has_gt_uc); \ |
b978520d MW |
119 | func(has_l3_dpf); \ |
120 | func(has_llc); \ | |
121 | func(has_logical_ring_contexts); \ | |
05f0addd | 122 | func(has_logical_ring_elsq); \ |
b978520d | 123 | func(has_logical_ring_preemption); \ |
b978520d | 124 | func(has_pooled_eu); \ |
b978520d MW |
125 | func(has_rc6); \ |
126 | func(has_rc6p); \ | |
91cbdb83 | 127 | func(has_rps); \ |
b978520d MW |
128 | func(has_runtime_pm); \ |
129 | func(has_snoop); \ | |
900ccf30 | 130 | func(has_coherent_ggtt); \ |
b978520d | 131 | func(unfenced_needs_alignment); \ |
d53db442 JRS |
132 | func(hws_needs_physical); |
133 | ||
134 | #define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \ | |
135 | /* Keep in alphabetical order */ \ | |
b978520d | 136 | func(cursor_needs_physical); \ |
d53db442 JRS |
137 | func(has_csr); \ |
138 | func(has_ddi); \ | |
139 | func(has_dp_mst); \ | |
18febcb7 | 140 | func(has_dsb); \ |
0f9ed3b2 | 141 | func(has_dsc); \ |
d53db442 | 142 | func(has_fbc); \ |
b2ae318a | 143 | func(has_gmch); \ |
74393109 | 144 | func(has_hdcp); \ |
d53db442 JRS |
145 | func(has_hotplug); \ |
146 | func(has_ipc); \ | |
0caf6257 | 147 | func(has_modular_fia); \ |
d53db442 JRS |
148 | func(has_overlay); \ |
149 | func(has_psr); \ | |
b978520d | 150 | func(overlay_needs_physical); \ |
d53db442 | 151 | func(supports_tv); |
b978520d | 152 | |
b978520d | 153 | struct intel_device_info { |
b978520d MW |
154 | u16 gen_mask; |
155 | ||
156 | u8 gen; | |
157 | u8 gt; /* GT number, 0 if undefined */ | |
8a68d464 | 158 | intel_engine_mask_t engine_mask; /* Engines supported by the HW */ |
b978520d MW |
159 | |
160 | enum intel_platform platform; | |
b978520d | 161 | |
31a02eb7 MR |
162 | unsigned int dma_mask_size; /* available DMA address bits */ |
163 | ||
cbecbcca CW |
164 | enum intel_ppgtt_type ppgtt_type; |
165 | unsigned int ppgtt_size; /* log2, e.g. 31/32/48 bits */ | |
166 | ||
4552f50a | 167 | unsigned int page_sizes; /* page sizes supported by the HW */ |
3aae9d08 AJ |
168 | |
169 | u32 memory_regions; /* regions supported by the HW */ | |
4552f50a | 170 | |
b978520d MW |
171 | u32 display_mmio_offset; |
172 | ||
8d8b0031 | 173 | u8 pipe_mask; |
10cf8e75 | 174 | u8 cpu_transcoder_mask; |
b978520d | 175 | |
b978520d MW |
176 | #define DEFINE_FLAG(name) u8 name:1 |
177 | DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG); | |
178 | #undef DEFINE_FLAG | |
d53db442 JRS |
179 | |
180 | struct { | |
181 | #define DEFINE_FLAG(name) u8 name:1 | |
182 | DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG); | |
183 | #undef DEFINE_FLAG | |
184 | } display; | |
185 | ||
b978520d | 186 | u16 ddb_size; /* in blocks */ |
0f0f9aee | 187 | u8 num_supported_dbuf_slices; /* number of DBuf slices */ |
b978520d MW |
188 | |
189 | /* Register offsets for the various display pipes and transcoders */ | |
190 | int pipe_offsets[I915_MAX_TRANSCODERS]; | |
191 | int trans_offsets[I915_MAX_TRANSCODERS]; | |
b978520d MW |
192 | int cursor_offsets[I915_MAX_PIPES]; |
193 | ||
0258404f | 194 | struct color_luts { |
89a72304 SS |
195 | u32 degamma_lut_size; |
196 | u32 gamma_lut_size; | |
e4c0d531 MR |
197 | u32 degamma_lut_tests; |
198 | u32 gamma_lut_tests; | |
0258404f JN |
199 | } color; |
200 | }; | |
201 | ||
202 | struct intel_runtime_info { | |
805446c8 TU |
203 | /* |
204 | * Platform mask is used for optimizing or-ed IS_PLATFORM calls into | |
205 | * into single runtime conditionals, and also to provide groundwork | |
206 | * for future per platform, or per SKU build optimizations. | |
207 | * | |
208 | * Array can be extended when necessary if the corresponding | |
209 | * BUILD_BUG_ON is hit. | |
210 | */ | |
211 | u32 platform_mask[2]; | |
212 | ||
0258404f JN |
213 | u16 device_id; |
214 | ||
215 | u8 num_sprites[I915_MAX_PIPES]; | |
216 | u8 num_scalers[I915_MAX_PIPES]; | |
217 | ||
8a68d464 | 218 | u8 num_engines; |
0258404f | 219 | |
b978520d MW |
220 | /* Slice/subslice/EU info */ |
221 | struct sseu_dev_info sseu; | |
222 | ||
b04002f4 CW |
223 | u32 rawclk_freq; |
224 | ||
56f1b31f | 225 | u32 cs_timestamp_frequency_hz; |
1883a0a4 | 226 | u32 cs_timestamp_period_ns; |
b978520d | 227 | |
57b19d55 OM |
228 | /* Media engine access to SFC per instance */ |
229 | u8 vdbox_sfc_access; | |
b978520d MW |
230 | }; |
231 | ||
3fed1808 CW |
232 | struct intel_driver_caps { |
233 | unsigned int scheduler; | |
481827b4 | 234 | bool has_logical_contexts:1; |
3fed1808 CW |
235 | }; |
236 | ||
b978520d MW |
237 | const char *intel_platform_name(enum intel_platform platform); |
238 | ||
805446c8 | 239 | void intel_device_info_subplatform_init(struct drm_i915_private *dev_priv); |
1400cc7e | 240 | void intel_device_info_runtime_init(struct drm_i915_private *dev_priv); |
72404978 CW |
241 | |
242 | void intel_device_info_print_static(const struct intel_device_info *info, | |
5fbbe8d4 | 243 | struct drm_printer *p); |
72404978 | 244 | void intel_device_info_print_runtime(const struct intel_runtime_info *info, |
79e9cd5f | 245 | struct drm_printer *p); |
72404978 CW |
246 | void intel_device_info_print_topology(const struct sseu_dev_info *sseu, |
247 | struct drm_printer *p); | |
b978520d | 248 | |
26376a7e OM |
249 | void intel_device_info_init_mmio(struct drm_i915_private *dev_priv); |
250 | ||
3fed1808 CW |
251 | void intel_driver_caps_print(const struct intel_driver_caps *caps, |
252 | struct drm_printer *p); | |
253 | ||
b978520d | 254 | #endif |