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b978520d MW |
1 | /* |
2 | * Copyright © 2014-2017 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | ||
25 | #ifndef _INTEL_DEVICE_INFO_H_ | |
26 | #define _INTEL_DEVICE_INFO_H_ | |
27 | ||
4bdafb9d CW |
28 | #include <uapi/drm/i915_drm.h> |
29 | ||
439c8dcc JN |
30 | #include "intel_step.h" |
31 | ||
df0566a6 JN |
32 | #include "display/intel_display.h" |
33 | ||
112ed2d3 CW |
34 | #include "gt/intel_engine_types.h" |
35 | #include "gt/intel_context_types.h" | |
36 | #include "gt/intel_sseu.h" | |
37 | ||
b978520d MW |
38 | struct drm_printer; |
39 | struct drm_i915_private; | |
40 | ||
41 | /* Keep in gen based order, and chronological order within a gen */ | |
42 | enum intel_platform { | |
43 | INTEL_PLATFORM_UNINITIALIZED = 0, | |
44 | /* gen2 */ | |
45 | INTEL_I830, | |
46 | INTEL_I845G, | |
47 | INTEL_I85X, | |
48 | INTEL_I865G, | |
49 | /* gen3 */ | |
50 | INTEL_I915G, | |
51 | INTEL_I915GM, | |
52 | INTEL_I945G, | |
53 | INTEL_I945GM, | |
54 | INTEL_G33, | |
55 | INTEL_PINEVIEW, | |
56 | /* gen4 */ | |
57 | INTEL_I965G, | |
58 | INTEL_I965GM, | |
59 | INTEL_G45, | |
60 | INTEL_GM45, | |
61 | /* gen5 */ | |
62 | INTEL_IRONLAKE, | |
63 | /* gen6 */ | |
64 | INTEL_SANDYBRIDGE, | |
65 | /* gen7 */ | |
66 | INTEL_IVYBRIDGE, | |
67 | INTEL_VALLEYVIEW, | |
68 | INTEL_HASWELL, | |
69 | /* gen8 */ | |
70 | INTEL_BROADWELL, | |
71 | INTEL_CHERRYVIEW, | |
72 | /* gen9 */ | |
73 | INTEL_SKYLAKE, | |
74 | INTEL_BROXTON, | |
75 | INTEL_KABYLAKE, | |
76 | INTEL_GEMINILAKE, | |
77 | INTEL_COFFEELAKE, | |
5f4ae270 | 78 | INTEL_COMETLAKE, |
41231001 RV |
79 | /* gen11 */ |
80 | INTEL_ICELAKE, | |
897f2961 | 81 | INTEL_ELKHARTLAKE, |
24ea098b | 82 | INTEL_JASPERLAKE, |
abd3a0fe DCS |
83 | /* gen12 */ |
84 | INTEL_TIGERLAKE, | |
123f62de | 85 | INTEL_ROCKETLAKE, |
05e26584 | 86 | INTEL_DG1, |
0883d63b | 87 | INTEL_ALDERLAKE_S, |
bdd27cad | 88 | INTEL_ALDERLAKE_P, |
086df54e | 89 | INTEL_XEHPSDV, |
9e22cfc5 | 90 | INTEL_DG2, |
448a54ac | 91 | INTEL_PONTEVECCHIO, |
bcf9b296 | 92 | INTEL_METEORLAKE, |
b978520d MW |
93 | INTEL_MAX_PLATFORMS |
94 | }; | |
95 | ||
805446c8 TU |
96 | /* |
97 | * Subplatform bits share the same namespace per parent platform. In other words | |
98 | * it is fine for the same bit to be used on multiple parent platforms. | |
99 | */ | |
100 | ||
86df4141 | 101 | #define INTEL_SUBPLATFORM_BITS (3) |
56afa701 | 102 | #define INTEL_SUBPLATFORM_MASK (BIT(INTEL_SUBPLATFORM_BITS) - 1) |
805446c8 TU |
103 | |
104 | /* HSW/BDW/SKL/KBL/CFL */ | |
105 | #define INTEL_SUBPLATFORM_ULT (0) | |
106 | #define INTEL_SUBPLATFORM_ULX (1) | |
805446c8 | 107 | |
244dba4c | 108 | /* ICL */ |
805446c8 TU |
109 | #define INTEL_SUBPLATFORM_PORTF (0) |
110 | ||
b9ef8939 JRS |
111 | /* TGL */ |
112 | #define INTEL_SUBPLATFORM_UY (0) | |
113 | ||
9e22cfc5 MR |
114 | /* DG2 */ |
115 | #define INTEL_SUBPLATFORM_G10 0 | |
116 | #define INTEL_SUBPLATFORM_G11 1 | |
86df4141 | 117 | #define INTEL_SUBPLATFORM_G12 2 |
9e22cfc5 | 118 | |
72c3c8d6 MA |
119 | /* ADL */ |
120 | #define INTEL_SUBPLATFORM_RPL 0 | |
52407c22 | 121 | |
7e28d0b2 | 122 | /* ADL-P */ |
72c3c8d6 MA |
123 | /* |
124 | * As #define INTEL_SUBPLATFORM_RPL 0 will apply | |
125 | * here too, SUBPLATFORM_N will have different | |
126 | * bit set | |
127 | */ | |
128 | #define INTEL_SUBPLATFORM_N 1 | |
7e28d0b2 | 129 | |
78353039 RS |
130 | /* MTL */ |
131 | #define INTEL_SUBPLATFORM_M 0 | |
132 | #define INTEL_SUBPLATFORM_P 1 | |
133 | ||
cbecbcca | 134 | enum intel_ppgtt_type { |
4bdafb9d CW |
135 | INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE, |
136 | INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING, | |
137 | INTEL_PPGTT_FULL = I915_GEM_PPGTT_FULL, | |
4bdafb9d CW |
138 | }; |
139 | ||
b978520d MW |
140 | #define DEV_INFO_FOR_EACH_FLAG(func) \ |
141 | func(is_mobile); \ | |
142 | func(is_lp); \ | |
7ef5ef5c | 143 | func(require_force_probe); \ |
dc90fe3f | 144 | func(is_dgfx); \ |
b978520d MW |
145 | /* Keep has_* in alphabetical order */ \ |
146 | func(has_64bit_reloc); \ | |
c83125bb | 147 | func(has_64k_pages); \ |
132aaaf0 | 148 | func(needs_compact_pt); \ |
55277e1f | 149 | func(gpu_reset_clobbers_display); \ |
b409db08 | 150 | func(has_reset_engine); \ |
1eb31338 | 151 | func(has_3d_pipeline); \ |
072ce416 | 152 | func(has_4tile); \ |
5e3094cf | 153 | func(has_flat_ccs); \ |
a7a7a0e6 | 154 | func(has_global_mocs); \ |
39921e5f | 155 | func(has_gt_uc); \ |
1e3dc1d8 TW |
156 | func(has_heci_pxp); \ |
157 | func(has_heci_gscfi); \ | |
db3b3f3e | 158 | func(has_guc_deprivilege); \ |
9d67edba | 159 | func(has_l3_ccs_read); \ |
b978520d MW |
160 | func(has_l3_dpf); \ |
161 | func(has_llc); \ | |
162 | func(has_logical_ring_contexts); \ | |
3d6c72b7 | 163 | func(has_logical_ring_elsq); \ |
85a040bc | 164 | func(has_media_ratio_mode); \ |
e0d7371b | 165 | func(has_mslice_steering); \ |
5ac342ef | 166 | func(has_one_eu_per_fuse_bit); \ |
b978520d | 167 | func(has_pooled_eu); \ |
e6aa7136 | 168 | func(has_pxp); \ |
fdbec9ff | 169 | func(has_rc6); \ |
b978520d | 170 | func(has_rc6p); \ |
91cbdb83 | 171 | func(has_rps); \ |
b978520d MW |
172 | func(has_runtime_pm); \ |
173 | func(has_snoop); \ | |
900ccf30 | 174 | func(has_coherent_ggtt); \ |
73c7a8a8 | 175 | func(tuning_thread_rr_after_dep); \ |
b978520d | 176 | func(unfenced_needs_alignment); \ |
d53db442 JRS |
177 | func(hws_needs_physical); |
178 | ||
179 | #define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \ | |
180 | /* Keep in alphabetical order */ \ | |
b978520d | 181 | func(cursor_needs_physical); \ |
eafaa3e9 | 182 | func(has_cdclk_crawl); \ |
ec2b1485 | 183 | func(has_dmc); \ |
9d8d5a39 | 184 | func(has_ddi); \ |
e91eec91 | 185 | func(has_dp_mst); \ |
18febcb7 | 186 | func(has_dsb); \ |
0f9ed3b2 | 187 | func(has_dsc); \ |
a321c3c6 | 188 | func(has_fpga_dbg); \ |
b2ae318a | 189 | func(has_gmch); \ |
74393109 | 190 | func(has_hdcp); \ |
d53db442 | 191 | func(has_hotplug); \ |
ddff9a60 | 192 | func(has_hti); \ |
d53db442 | 193 | func(has_ipc); \ |
0caf6257 | 194 | func(has_modular_fia); \ |
d53db442 | 195 | func(has_overlay); \ |
9602efab | 196 | func(has_psr); \ |
24d2fc3d | 197 | func(has_psr_hw_tracking); \ |
b978520d | 198 | func(overlay_needs_physical); \ |
d53db442 | 199 | func(supports_tv); |
b978520d | 200 | |
a5b7ef27 JRS |
201 | struct ip_version { |
202 | u8 ver; | |
203 | u8 rel; | |
204 | }; | |
205 | ||
b978520d | 206 | struct intel_device_info { |
a5b7ef27 JRS |
207 | struct ip_version graphics; |
208 | struct ip_version media; | |
93babb06 | 209 | |
792592e7 | 210 | intel_engine_mask_t platform_engine_mask; /* Engines supported by the HW */ |
b978520d MW |
211 | |
212 | enum intel_platform platform; | |
b978520d | 213 | |
31a02eb7 MR |
214 | unsigned int dma_mask_size; /* available DMA address bits */ |
215 | ||
cbecbcca CW |
216 | enum intel_ppgtt_type ppgtt_type; |
217 | unsigned int ppgtt_size; /* log2, e.g. 31/32/48 bits */ | |
218 | ||
4552f50a | 219 | unsigned int page_sizes; /* page sizes supported by the HW */ |
3aae9d08 AJ |
220 | |
221 | u32 memory_regions; /* regions supported by the HW */ | |
4552f50a | 222 | |
b978520d MW |
223 | u32 display_mmio_offset; |
224 | ||
938c778f JH |
225 | u8 gt; /* GT number, 0 if undefined */ |
226 | ||
b978520d MW |
227 | #define DEFINE_FLAG(name) u8 name:1 |
228 | DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG); | |
229 | #undef DEFINE_FLAG | |
d53db442 JRS |
230 | |
231 | struct { | |
4df9c1ae | 232 | u8 ver; |
a5b7ef27 | 233 | u8 rel; |
01eb15c9 | 234 | |
6678916d VS |
235 | u8 pipe_mask; |
236 | u8 cpu_transcoder_mask; | |
b8ca477e | 237 | u8 fbc_mask; |
6678916d VS |
238 | u8 abox_mask; |
239 | ||
d53db442 JRS |
240 | #define DEFINE_FLAG(name) u8 name:1 |
241 | DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG); | |
242 | #undef DEFINE_FLAG | |
243 | } display; | |
244 | ||
708de86e VS |
245 | struct { |
246 | u16 size; /* in blocks */ | |
578e6ede | 247 | u8 slice_mask; |
708de86e | 248 | } dbuf; |
b978520d MW |
249 | |
250 | /* Register offsets for the various display pipes and transcoders */ | |
251 | int pipe_offsets[I915_MAX_TRANSCODERS]; | |
252 | int trans_offsets[I915_MAX_TRANSCODERS]; | |
b978520d MW |
253 | int cursor_offsets[I915_MAX_PIPES]; |
254 | ||
0258404f | 255 | struct color_luts { |
89a72304 SS |
256 | u32 degamma_lut_size; |
257 | u32 gamma_lut_size; | |
e4c0d531 MR |
258 | u32 degamma_lut_tests; |
259 | u32 gamma_lut_tests; | |
0258404f JN |
260 | } color; |
261 | }; | |
262 | ||
263 | struct intel_runtime_info { | |
805446c8 TU |
264 | /* |
265 | * Platform mask is used for optimizing or-ed IS_PLATFORM calls into | |
266 | * into single runtime conditionals, and also to provide groundwork | |
267 | * for future per platform, or per SKU build optimizations. | |
268 | * | |
269 | * Array can be extended when necessary if the corresponding | |
270 | * BUILD_BUG_ON is hit. | |
271 | */ | |
272 | u32 platform_mask[2]; | |
273 | ||
0258404f JN |
274 | u16 device_id; |
275 | ||
276 | u8 num_sprites[I915_MAX_PIPES]; | |
277 | u8 num_scalers[I915_MAX_PIPES]; | |
278 | ||
b04002f4 | 279 | u32 rawclk_freq; |
439c8dcc | 280 | |
5644dc0a | 281 | struct intel_step_info step; |
b978520d MW |
282 | }; |
283 | ||
3fed1808 CW |
284 | struct intel_driver_caps { |
285 | unsigned int scheduler; | |
481827b4 | 286 | bool has_logical_contexts:1; |
3fed1808 CW |
287 | }; |
288 | ||
b978520d MW |
289 | const char *intel_platform_name(enum intel_platform platform); |
290 | ||
805446c8 | 291 | void intel_device_info_subplatform_init(struct drm_i915_private *dev_priv); |
1400cc7e | 292 | void intel_device_info_runtime_init(struct drm_i915_private *dev_priv); |
72404978 CW |
293 | |
294 | void intel_device_info_print_static(const struct intel_device_info *info, | |
5fbbe8d4 | 295 | struct drm_printer *p); |
72404978 | 296 | void intel_device_info_print_runtime(const struct intel_runtime_info *info, |
79e9cd5f | 297 | struct drm_printer *p); |
b978520d | 298 | |
3fed1808 CW |
299 | void intel_driver_caps_print(const struct intel_driver_caps *caps, |
300 | struct drm_printer *p); | |
301 | ||
b978520d | 302 | #endif |