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b978520d MW |
1 | /* |
2 | * Copyright © 2014-2017 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | ||
25 | #ifndef _INTEL_DEVICE_INFO_H_ | |
26 | #define _INTEL_DEVICE_INFO_H_ | |
27 | ||
4bdafb9d CW |
28 | #include <uapi/drm/i915_drm.h> |
29 | ||
3a891a62 | 30 | #include "intel_engine_types.h" |
b978520d | 31 | #include "intel_display.h" |
09407579 | 32 | #include "intel_sseu.h" |
b978520d MW |
33 | |
34 | struct drm_printer; | |
35 | struct drm_i915_private; | |
36 | ||
37 | /* Keep in gen based order, and chronological order within a gen */ | |
38 | enum intel_platform { | |
39 | INTEL_PLATFORM_UNINITIALIZED = 0, | |
40 | /* gen2 */ | |
41 | INTEL_I830, | |
42 | INTEL_I845G, | |
43 | INTEL_I85X, | |
44 | INTEL_I865G, | |
45 | /* gen3 */ | |
46 | INTEL_I915G, | |
47 | INTEL_I915GM, | |
48 | INTEL_I945G, | |
49 | INTEL_I945GM, | |
50 | INTEL_G33, | |
51 | INTEL_PINEVIEW, | |
52 | /* gen4 */ | |
53 | INTEL_I965G, | |
54 | INTEL_I965GM, | |
55 | INTEL_G45, | |
56 | INTEL_GM45, | |
57 | /* gen5 */ | |
58 | INTEL_IRONLAKE, | |
59 | /* gen6 */ | |
60 | INTEL_SANDYBRIDGE, | |
61 | /* gen7 */ | |
62 | INTEL_IVYBRIDGE, | |
63 | INTEL_VALLEYVIEW, | |
64 | INTEL_HASWELL, | |
65 | /* gen8 */ | |
66 | INTEL_BROADWELL, | |
67 | INTEL_CHERRYVIEW, | |
68 | /* gen9 */ | |
69 | INTEL_SKYLAKE, | |
70 | INTEL_BROXTON, | |
71 | INTEL_KABYLAKE, | |
72 | INTEL_GEMINILAKE, | |
73 | INTEL_COFFEELAKE, | |
74 | /* gen10 */ | |
75 | INTEL_CANNONLAKE, | |
41231001 RV |
76 | /* gen11 */ |
77 | INTEL_ICELAKE, | |
897f2961 | 78 | INTEL_ELKHARTLAKE, |
b978520d MW |
79 | INTEL_MAX_PLATFORMS |
80 | }; | |
81 | ||
805446c8 TU |
82 | /* |
83 | * Subplatform bits share the same namespace per parent platform. In other words | |
84 | * it is fine for the same bit to be used on multiple parent platforms. | |
85 | */ | |
86 | ||
87 | #define INTEL_SUBPLATFORM_BITS (3) | |
88 | ||
89 | /* HSW/BDW/SKL/KBL/CFL */ | |
90 | #define INTEL_SUBPLATFORM_ULT (0) | |
91 | #define INTEL_SUBPLATFORM_ULX (1) | |
92 | #define INTEL_SUBPLATFORM_AML (2) | |
93 | ||
94 | /* CNL/ICL */ | |
95 | #define INTEL_SUBPLATFORM_PORTF (0) | |
96 | ||
cbecbcca | 97 | enum intel_ppgtt_type { |
4bdafb9d CW |
98 | INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE, |
99 | INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING, | |
100 | INTEL_PPGTT_FULL = I915_GEM_PPGTT_FULL, | |
4bdafb9d CW |
101 | }; |
102 | ||
b978520d MW |
103 | #define DEV_INFO_FOR_EACH_FLAG(func) \ |
104 | func(is_mobile); \ | |
105 | func(is_lp); \ | |
106 | func(is_alpha_support); \ | |
107 | /* Keep has_* in alphabetical order */ \ | |
108 | func(has_64bit_reloc); \ | |
55277e1f | 109 | func(gpu_reset_clobbers_display); \ |
b978520d | 110 | func(has_reset_engine); \ |
b978520d | 111 | func(has_fpga_dbg); \ |
b978520d MW |
112 | func(has_guc); \ |
113 | func(has_guc_ct); \ | |
b978520d MW |
114 | func(has_l3_dpf); \ |
115 | func(has_llc); \ | |
116 | func(has_logical_ring_contexts); \ | |
05f0addd | 117 | func(has_logical_ring_elsq); \ |
b978520d | 118 | func(has_logical_ring_preemption); \ |
b978520d | 119 | func(has_pooled_eu); \ |
b978520d MW |
120 | func(has_rc6); \ |
121 | func(has_rc6p); \ | |
91cbdb83 | 122 | func(has_rps); \ |
b978520d MW |
123 | func(has_runtime_pm); \ |
124 | func(has_snoop); \ | |
900ccf30 | 125 | func(has_coherent_ggtt); \ |
b978520d | 126 | func(unfenced_needs_alignment); \ |
d53db442 JRS |
127 | func(hws_needs_physical); |
128 | ||
129 | #define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \ | |
130 | /* Keep in alphabetical order */ \ | |
b978520d | 131 | func(cursor_needs_physical); \ |
d53db442 JRS |
132 | func(has_csr); \ |
133 | func(has_ddi); \ | |
134 | func(has_dp_mst); \ | |
135 | func(has_fbc); \ | |
b2ae318a | 136 | func(has_gmch); \ |
d53db442 JRS |
137 | func(has_hotplug); \ |
138 | func(has_ipc); \ | |
139 | func(has_overlay); \ | |
140 | func(has_psr); \ | |
b978520d | 141 | func(overlay_needs_physical); \ |
d53db442 | 142 | func(supports_tv); |
b978520d | 143 | |
b978520d | 144 | struct intel_device_info { |
b978520d MW |
145 | u16 gen_mask; |
146 | ||
147 | u8 gen; | |
148 | u8 gt; /* GT number, 0 if undefined */ | |
8a68d464 | 149 | intel_engine_mask_t engine_mask; /* Engines supported by the HW */ |
b978520d MW |
150 | |
151 | enum intel_platform platform; | |
b978520d | 152 | |
cbecbcca CW |
153 | enum intel_ppgtt_type ppgtt_type; |
154 | unsigned int ppgtt_size; /* log2, e.g. 31/32/48 bits */ | |
155 | ||
4552f50a TU |
156 | unsigned int page_sizes; /* page sizes supported by the HW */ |
157 | ||
b978520d MW |
158 | u32 display_mmio_offset; |
159 | ||
160 | u8 num_pipes; | |
b978520d | 161 | |
b978520d MW |
162 | #define DEFINE_FLAG(name) u8 name:1 |
163 | DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG); | |
164 | #undef DEFINE_FLAG | |
d53db442 JRS |
165 | |
166 | struct { | |
167 | #define DEFINE_FLAG(name) u8 name:1 | |
168 | DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG); | |
169 | #undef DEFINE_FLAG | |
170 | } display; | |
171 | ||
b978520d MW |
172 | u16 ddb_size; /* in blocks */ |
173 | ||
174 | /* Register offsets for the various display pipes and transcoders */ | |
175 | int pipe_offsets[I915_MAX_TRANSCODERS]; | |
176 | int trans_offsets[I915_MAX_TRANSCODERS]; | |
b978520d MW |
177 | int cursor_offsets[I915_MAX_PIPES]; |
178 | ||
0258404f JN |
179 | struct color_luts { |
180 | u16 degamma_lut_size; | |
181 | u16 gamma_lut_size; | |
e4c0d531 MR |
182 | u32 degamma_lut_tests; |
183 | u32 gamma_lut_tests; | |
0258404f JN |
184 | } color; |
185 | }; | |
186 | ||
187 | struct intel_runtime_info { | |
805446c8 TU |
188 | /* |
189 | * Platform mask is used for optimizing or-ed IS_PLATFORM calls into | |
190 | * into single runtime conditionals, and also to provide groundwork | |
191 | * for future per platform, or per SKU build optimizations. | |
192 | * | |
193 | * Array can be extended when necessary if the corresponding | |
194 | * BUILD_BUG_ON is hit. | |
195 | */ | |
196 | u32 platform_mask[2]; | |
197 | ||
0258404f JN |
198 | u16 device_id; |
199 | ||
200 | u8 num_sprites[I915_MAX_PIPES]; | |
201 | u8 num_scalers[I915_MAX_PIPES]; | |
202 | ||
8a68d464 | 203 | u8 num_engines; |
0258404f | 204 | |
b978520d MW |
205 | /* Slice/subslice/EU info */ |
206 | struct sseu_dev_info sseu; | |
207 | ||
208 | u32 cs_timestamp_frequency_khz; | |
209 | ||
57b19d55 OM |
210 | /* Media engine access to SFC per instance */ |
211 | u8 vdbox_sfc_access; | |
b978520d MW |
212 | }; |
213 | ||
3fed1808 CW |
214 | struct intel_driver_caps { |
215 | unsigned int scheduler; | |
481827b4 | 216 | bool has_logical_contexts:1; |
3fed1808 CW |
217 | }; |
218 | ||
b978520d MW |
219 | static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu) |
220 | { | |
8cc76693 LL |
221 | unsigned int i, total = 0; |
222 | ||
223 | for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++) | |
224 | total += hweight8(sseu->subslice_mask[i]); | |
225 | ||
226 | return total; | |
227 | } | |
228 | ||
229 | static inline int sseu_eu_idx(const struct sseu_dev_info *sseu, | |
230 | int slice, int subslice) | |
231 | { | |
232 | int subslice_stride = DIV_ROUND_UP(sseu->max_eus_per_subslice, | |
233 | BITS_PER_BYTE); | |
234 | int slice_stride = sseu->max_subslices * subslice_stride; | |
235 | ||
236 | return slice * slice_stride + subslice * subslice_stride; | |
237 | } | |
238 | ||
239 | static inline u16 sseu_get_eus(const struct sseu_dev_info *sseu, | |
240 | int slice, int subslice) | |
241 | { | |
242 | int i, offset = sseu_eu_idx(sseu, slice, subslice); | |
243 | u16 eu_mask = 0; | |
244 | ||
245 | for (i = 0; | |
246 | i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) { | |
247 | eu_mask |= ((u16) sseu->eu_mask[offset + i]) << | |
248 | (i * BITS_PER_BYTE); | |
249 | } | |
250 | ||
251 | return eu_mask; | |
252 | } | |
253 | ||
254 | static inline void sseu_set_eus(struct sseu_dev_info *sseu, | |
255 | int slice, int subslice, u16 eu_mask) | |
256 | { | |
257 | int i, offset = sseu_eu_idx(sseu, slice, subslice); | |
258 | ||
259 | for (i = 0; | |
260 | i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) { | |
261 | sseu->eu_mask[offset + i] = | |
262 | (eu_mask >> (BITS_PER_BYTE * i)) & 0xff; | |
263 | } | |
b978520d MW |
264 | } |
265 | ||
266 | const char *intel_platform_name(enum intel_platform platform); | |
267 | ||
805446c8 | 268 | void intel_device_info_subplatform_init(struct drm_i915_private *dev_priv); |
1400cc7e | 269 | void intel_device_info_runtime_init(struct drm_i915_private *dev_priv); |
b978520d MW |
270 | void intel_device_info_dump_flags(const struct intel_device_info *info, |
271 | struct drm_printer *p); | |
0258404f | 272 | void intel_device_info_dump_runtime(const struct intel_runtime_info *info, |
5fbbe8d4 | 273 | struct drm_printer *p); |
79e9cd5f LL |
274 | void intel_device_info_dump_topology(const struct sseu_dev_info *sseu, |
275 | struct drm_printer *p); | |
b978520d | 276 | |
26376a7e OM |
277 | void intel_device_info_init_mmio(struct drm_i915_private *dev_priv); |
278 | ||
3fed1808 CW |
279 | void intel_driver_caps_print(const struct intel_driver_caps *caps, |
280 | struct drm_printer *p); | |
281 | ||
b978520d | 282 | #endif |