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b978520d MW |
1 | /* |
2 | * Copyright © 2014-2017 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | ||
25 | #ifndef _INTEL_DEVICE_INFO_H_ | |
26 | #define _INTEL_DEVICE_INFO_H_ | |
27 | ||
4bdafb9d CW |
28 | #include <uapi/drm/i915_drm.h> |
29 | ||
df0566a6 JN |
30 | #include "display/intel_display.h" |
31 | ||
112ed2d3 CW |
32 | #include "gt/intel_engine_types.h" |
33 | #include "gt/intel_context_types.h" | |
34 | #include "gt/intel_sseu.h" | |
35 | ||
b978520d MW |
36 | struct drm_printer; |
37 | struct drm_i915_private; | |
38 | ||
39 | /* Keep in gen based order, and chronological order within a gen */ | |
40 | enum intel_platform { | |
41 | INTEL_PLATFORM_UNINITIALIZED = 0, | |
42 | /* gen2 */ | |
43 | INTEL_I830, | |
44 | INTEL_I845G, | |
45 | INTEL_I85X, | |
46 | INTEL_I865G, | |
47 | /* gen3 */ | |
48 | INTEL_I915G, | |
49 | INTEL_I915GM, | |
50 | INTEL_I945G, | |
51 | INTEL_I945GM, | |
52 | INTEL_G33, | |
53 | INTEL_PINEVIEW, | |
54 | /* gen4 */ | |
55 | INTEL_I965G, | |
56 | INTEL_I965GM, | |
57 | INTEL_G45, | |
58 | INTEL_GM45, | |
59 | /* gen5 */ | |
60 | INTEL_IRONLAKE, | |
61 | /* gen6 */ | |
62 | INTEL_SANDYBRIDGE, | |
63 | /* gen7 */ | |
64 | INTEL_IVYBRIDGE, | |
65 | INTEL_VALLEYVIEW, | |
66 | INTEL_HASWELL, | |
67 | /* gen8 */ | |
68 | INTEL_BROADWELL, | |
69 | INTEL_CHERRYVIEW, | |
70 | /* gen9 */ | |
71 | INTEL_SKYLAKE, | |
72 | INTEL_BROXTON, | |
73 | INTEL_KABYLAKE, | |
74 | INTEL_GEMINILAKE, | |
75 | INTEL_COFFEELAKE, | |
5f4ae270 | 76 | INTEL_COMETLAKE, |
b978520d MW |
77 | /* gen10 */ |
78 | INTEL_CANNONLAKE, | |
41231001 RV |
79 | /* gen11 */ |
80 | INTEL_ICELAKE, | |
897f2961 | 81 | INTEL_ELKHARTLAKE, |
24ea098b | 82 | INTEL_JASPERLAKE, |
abd3a0fe DCS |
83 | /* gen12 */ |
84 | INTEL_TIGERLAKE, | |
123f62de | 85 | INTEL_ROCKETLAKE, |
05e26584 | 86 | INTEL_DG1, |
0883d63b | 87 | INTEL_ALDERLAKE_S, |
b978520d MW |
88 | INTEL_MAX_PLATFORMS |
89 | }; | |
90 | ||
805446c8 TU |
91 | /* |
92 | * Subplatform bits share the same namespace per parent platform. In other words | |
93 | * it is fine for the same bit to be used on multiple parent platforms. | |
94 | */ | |
95 | ||
96 | #define INTEL_SUBPLATFORM_BITS (3) | |
97 | ||
98 | /* HSW/BDW/SKL/KBL/CFL */ | |
99 | #define INTEL_SUBPLATFORM_ULT (0) | |
100 | #define INTEL_SUBPLATFORM_ULX (1) | |
805446c8 TU |
101 | |
102 | /* CNL/ICL */ | |
103 | #define INTEL_SUBPLATFORM_PORTF (0) | |
104 | ||
cbecbcca | 105 | enum intel_ppgtt_type { |
4bdafb9d CW |
106 | INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE, |
107 | INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING, | |
108 | INTEL_PPGTT_FULL = I915_GEM_PPGTT_FULL, | |
4bdafb9d CW |
109 | }; |
110 | ||
b978520d MW |
111 | #define DEV_INFO_FOR_EACH_FLAG(func) \ |
112 | func(is_mobile); \ | |
113 | func(is_lp); \ | |
7ef5ef5c | 114 | func(require_force_probe); \ |
dc90fe3f | 115 | func(is_dgfx); \ |
b978520d MW |
116 | /* Keep has_* in alphabetical order */ \ |
117 | func(has_64bit_reloc); \ | |
55277e1f | 118 | func(gpu_reset_clobbers_display); \ |
b978520d | 119 | func(has_reset_engine); \ |
a7a7a0e6 | 120 | func(has_global_mocs); \ |
702668e6 | 121 | func(has_gt_uc); \ |
b978520d MW |
122 | func(has_l3_dpf); \ |
123 | func(has_llc); \ | |
124 | func(has_logical_ring_contexts); \ | |
05f0addd | 125 | func(has_logical_ring_elsq); \ |
2ffcfd8d | 126 | func(has_master_unit_irq); \ |
b978520d | 127 | func(has_pooled_eu); \ |
b978520d MW |
128 | func(has_rc6); \ |
129 | func(has_rc6p); \ | |
91cbdb83 | 130 | func(has_rps); \ |
b978520d MW |
131 | func(has_runtime_pm); \ |
132 | func(has_snoop); \ | |
900ccf30 | 133 | func(has_coherent_ggtt); \ |
b978520d | 134 | func(unfenced_needs_alignment); \ |
d53db442 JRS |
135 | func(hws_needs_physical); |
136 | ||
137 | #define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \ | |
138 | /* Keep in alphabetical order */ \ | |
b978520d | 139 | func(cursor_needs_physical); \ |
d53db442 JRS |
140 | func(has_csr); \ |
141 | func(has_ddi); \ | |
142 | func(has_dp_mst); \ | |
18febcb7 | 143 | func(has_dsb); \ |
0f9ed3b2 | 144 | func(has_dsc); \ |
d53db442 | 145 | func(has_fbc); \ |
a321c3c6 | 146 | func(has_fpga_dbg); \ |
b2ae318a | 147 | func(has_gmch); \ |
74393109 | 148 | func(has_hdcp); \ |
d53db442 | 149 | func(has_hotplug); \ |
ddff9a60 | 150 | func(has_hti); \ |
d53db442 | 151 | func(has_ipc); \ |
0caf6257 | 152 | func(has_modular_fia); \ |
d53db442 JRS |
153 | func(has_overlay); \ |
154 | func(has_psr); \ | |
24d2fc3d | 155 | func(has_psr_hw_tracking); \ |
b978520d | 156 | func(overlay_needs_physical); \ |
d53db442 | 157 | func(supports_tv); |
b978520d | 158 | |
b978520d | 159 | struct intel_device_info { |
b978520d MW |
160 | u16 gen_mask; |
161 | ||
162 | u8 gen; | |
163 | u8 gt; /* GT number, 0 if undefined */ | |
792592e7 | 164 | intel_engine_mask_t platform_engine_mask; /* Engines supported by the HW */ |
b978520d MW |
165 | |
166 | enum intel_platform platform; | |
b978520d | 167 | |
31a02eb7 MR |
168 | unsigned int dma_mask_size; /* available DMA address bits */ |
169 | ||
cbecbcca CW |
170 | enum intel_ppgtt_type ppgtt_type; |
171 | unsigned int ppgtt_size; /* log2, e.g. 31/32/48 bits */ | |
172 | ||
4552f50a | 173 | unsigned int page_sizes; /* page sizes supported by the HW */ |
3aae9d08 AJ |
174 | |
175 | u32 memory_regions; /* regions supported by the HW */ | |
4552f50a | 176 | |
b978520d MW |
177 | u32 display_mmio_offset; |
178 | ||
8d8b0031 | 179 | u8 pipe_mask; |
10cf8e75 | 180 | u8 cpu_transcoder_mask; |
b978520d | 181 | |
62afef28 MR |
182 | u8 abox_mask; |
183 | ||
b978520d MW |
184 | #define DEFINE_FLAG(name) u8 name:1 |
185 | DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG); | |
186 | #undef DEFINE_FLAG | |
d53db442 JRS |
187 | |
188 | struct { | |
01eb15c9 MR |
189 | u8 version; |
190 | ||
d53db442 JRS |
191 | #define DEFINE_FLAG(name) u8 name:1 |
192 | DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG); | |
193 | #undef DEFINE_FLAG | |
194 | } display; | |
195 | ||
b978520d | 196 | u16 ddb_size; /* in blocks */ |
0f0f9aee | 197 | u8 num_supported_dbuf_slices; /* number of DBuf slices */ |
b978520d MW |
198 | |
199 | /* Register offsets for the various display pipes and transcoders */ | |
200 | int pipe_offsets[I915_MAX_TRANSCODERS]; | |
201 | int trans_offsets[I915_MAX_TRANSCODERS]; | |
b978520d MW |
202 | int cursor_offsets[I915_MAX_PIPES]; |
203 | ||
0258404f | 204 | struct color_luts { |
89a72304 SS |
205 | u32 degamma_lut_size; |
206 | u32 gamma_lut_size; | |
e4c0d531 MR |
207 | u32 degamma_lut_tests; |
208 | u32 gamma_lut_tests; | |
0258404f JN |
209 | } color; |
210 | }; | |
211 | ||
212 | struct intel_runtime_info { | |
805446c8 TU |
213 | /* |
214 | * Platform mask is used for optimizing or-ed IS_PLATFORM calls into | |
215 | * into single runtime conditionals, and also to provide groundwork | |
216 | * for future per platform, or per SKU build optimizations. | |
217 | * | |
218 | * Array can be extended when necessary if the corresponding | |
219 | * BUILD_BUG_ON is hit. | |
220 | */ | |
221 | u32 platform_mask[2]; | |
222 | ||
0258404f JN |
223 | u16 device_id; |
224 | ||
225 | u8 num_sprites[I915_MAX_PIPES]; | |
226 | u8 num_scalers[I915_MAX_PIPES]; | |
227 | ||
b04002f4 | 228 | u32 rawclk_freq; |
b978520d MW |
229 | }; |
230 | ||
3fed1808 CW |
231 | struct intel_driver_caps { |
232 | unsigned int scheduler; | |
481827b4 | 233 | bool has_logical_contexts:1; |
3fed1808 CW |
234 | }; |
235 | ||
b978520d MW |
236 | const char *intel_platform_name(enum intel_platform platform); |
237 | ||
805446c8 | 238 | void intel_device_info_subplatform_init(struct drm_i915_private *dev_priv); |
1400cc7e | 239 | void intel_device_info_runtime_init(struct drm_i915_private *dev_priv); |
72404978 CW |
240 | |
241 | void intel_device_info_print_static(const struct intel_device_info *info, | |
5fbbe8d4 | 242 | struct drm_printer *p); |
72404978 | 243 | void intel_device_info_print_runtime(const struct intel_runtime_info *info, |
79e9cd5f | 244 | struct drm_printer *p); |
b978520d | 245 | |
3fed1808 CW |
246 | void intel_driver_caps_print(const struct intel_driver_caps *caps, |
247 | struct drm_printer *p); | |
248 | ||
b978520d | 249 | #endif |