[linux-block.git] / drivers / gpu / drm / i915 / intel_device_info.h

/*
 * Copyright © 2014-2017 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 */

#ifndef _INTEL_DEVICE_INFO_H_
#define _INTEL_DEVICE_INFO_H_

#include <uapi/drm/i915_drm.h>

#include "intel_display.h"

struct drm_printer;
struct drm_i915_private;

/* Keep in gen based order, and chronological order within a gen */
enum intel_platform {
	INTEL_PLATFORM_UNINITIALIZED = 0,
	/* gen2 */
	INTEL_I830,
	INTEL_I845G,
	INTEL_I85X,
	INTEL_I865G,
	/* gen3 */
	INTEL_I915G,
	INTEL_I915GM,
	INTEL_I945G,
	INTEL_I945GM,
	INTEL_G33,
	INTEL_PINEVIEW,
	/* gen4 */
	INTEL_I965G,
	INTEL_I965GM,
	INTEL_G45,
	INTEL_GM45,
	/* gen5 */
	INTEL_IRONLAKE,
	/* gen6 */
	INTEL_SANDYBRIDGE,
	/* gen7 */
	INTEL_IVYBRIDGE,
	INTEL_VALLEYVIEW,
	INTEL_HASWELL,
	/* gen8 */
	INTEL_BROADWELL,
	INTEL_CHERRYVIEW,
	/* gen9 */
	INTEL_SKYLAKE,
	INTEL_BROXTON,
	INTEL_KABYLAKE,
	INTEL_GEMINILAKE,
	INTEL_COFFEELAKE,
	/* gen10 */
	INTEL_CANNONLAKE,
	/* gen11 */
	INTEL_ICELAKE,
	INTEL_ELKHARTLAKE,
	INTEL_MAX_PLATFORMS
};

enum intel_ppgtt_type {
	INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
	INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
	INTEL_PPGTT_FULL = I915_GEM_PPGTT_FULL,
};

#define DEV_INFO_FOR_EACH_FLAG(func) \
	func(is_mobile); \
	func(is_lp); \
	func(is_alpha_support); \
	/* Keep has_* in alphabetical order */ \
	func(has_64bit_reloc); \
	func(gpu_reset_clobbers_display); \
	func(has_reset_engine); \
	func(has_fpga_dbg); \
	func(has_guc); \
	func(has_guc_ct); \
	func(has_l3_dpf); \
	func(has_llc); \
	func(has_logical_ring_contexts); \
	func(has_logical_ring_elsq); \
	func(has_logical_ring_preemption); \
	func(has_pooled_eu); \
	func(has_rc6); \
	func(has_rc6p); \
	func(has_runtime_pm); \
	func(has_snoop); \
	func(has_coherent_ggtt); \
	func(unfenced_needs_alignment); \
	func(hws_needs_physical);

#define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \
	/* Keep in alphabetical order */ \
	func(cursor_needs_physical); \
	func(has_csr); \
	func(has_ddi); \
	func(has_dp_mst); \
	func(has_fbc); \
	func(has_gmch); \
	func(has_hotplug); \
	func(has_ipc); \
	func(has_overlay); \
	func(has_psr); \
	func(overlay_needs_physical); \
	func(supports_tv);

#define GEN_MAX_SLICES		(6) /* CNL upper bound */
#define GEN_MAX_SUBSLICES	(8) /* ICL upper bound */

struct sseu_dev_info {
	u8 slice_mask;
	u8 subslice_mask[GEN_MAX_SLICES];
	u16 eu_total;
	u8 eu_per_subslice;
	u8 min_eu_in_pool;
	/* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
	u8 subslice_7eu[3];
	u8 has_slice_pg:1;
	u8 has_subslice_pg:1;
	u8 has_eu_pg:1;

	/* Topology fields */
	u8 max_slices;
	u8 max_subslices;
	u8 max_eus_per_subslice;

	/* We don't have more than 8 eus per subslice at the moment and as we
	 * store eus enabled using bits, no need to multiply by eus per
	 * subslice.
	 */
	u8 eu_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICES];
};

typedef u8 intel_engine_mask_t;

struct intel_device_info {
	u16 gen_mask;

	u8 gen;
	u8 gt; /* GT number, 0 if undefined */
	intel_engine_mask_t engine_mask; /* Engines supported by the HW */

	enum intel_platform platform;
	u32 platform_mask;

	enum intel_ppgtt_type ppgtt_type;
	unsigned int ppgtt_size; /* log2, e.g. 31/32/48 bits */

	unsigned int page_sizes; /* page sizes supported by the HW */

	u32 display_mmio_offset;

	u8 num_pipes;

#define DEFINE_FLAG(name) u8 name:1
	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
#undef DEFINE_FLAG

	struct {
#define DEFINE_FLAG(name) u8 name:1
		DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG);
#undef DEFINE_FLAG
	} display;

	u16 ddb_size; /* in blocks */

	/* Register offsets for the various display pipes and transcoders */
	int pipe_offsets[I915_MAX_TRANSCODERS];
	int trans_offsets[I915_MAX_TRANSCODERS];
	int cursor_offsets[I915_MAX_PIPES];

	struct color_luts {
		u16 degamma_lut_size;
		u16 gamma_lut_size;
		u32 degamma_lut_tests;
		u32 gamma_lut_tests;
	} color;
};

struct intel_runtime_info {
	u16 device_id;

	u8 num_sprites[I915_MAX_PIPES];
	u8 num_scalers[I915_MAX_PIPES];

	u8 num_engines;

	/* Slice/subslice/EU info */
	struct sseu_dev_info sseu;

	u32 cs_timestamp_frequency_khz;

	/* Media engine access to SFC per instance */
	u8 vdbox_sfc_access;
};

struct intel_driver_caps {
	unsigned int scheduler;
	bool has_logical_contexts:1;
};

static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu)
{
	unsigned int i, total = 0;

	for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++)
		total += hweight8(sseu->subslice_mask[i]);

	return total;
}

static inline int sseu_eu_idx(const struct sseu_dev_info *sseu,
			      int slice, int subslice)
{
	int subslice_stride = DIV_ROUND_UP(sseu->max_eus_per_subslice,
					   BITS_PER_BYTE);
	int slice_stride = sseu->max_subslices * subslice_stride;

	return slice * slice_stride + subslice * subslice_stride;
}

static inline u16 sseu_get_eus(const struct sseu_dev_info *sseu,
			       int slice, int subslice)
{
	int i, offset = sseu_eu_idx(sseu, slice, subslice);
	u16 eu_mask = 0;

	for (i = 0;
	     i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) {
		eu_mask |= ((u16) sseu->eu_mask[offset + i]) <<
			(i * BITS_PER_BYTE);
	}

	return eu_mask;
}

static inline void sseu_set_eus(struct sseu_dev_info *sseu,
				int slice, int subslice, u16 eu_mask)
{
	int i, offset = sseu_eu_idx(sseu, slice, subslice);

	for (i = 0;
	     i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) {
		sseu->eu_mask[offset + i] =
			(eu_mask >> (BITS_PER_BYTE * i)) & 0xff;
	}
}

const char *intel_platform_name(enum intel_platform platform);

void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
void intel_device_info_dump_flags(const struct intel_device_info *info,
				  struct drm_printer *p);
void intel_device_info_dump_runtime(const struct intel_runtime_info *info,
				    struct drm_printer *p);
void intel_device_info_dump_topology(const struct sseu_dev_info *sseu,
				     struct drm_printer *p);

void intel_device_info_init_mmio(struct drm_i915_private *dev_priv);

void intel_driver_caps_print(const struct intel_driver_caps *caps,
			     struct drm_printer *p);

#endif
Commit	Line	Data
b978520d MW	1	/*
	2	* Copyright © 2014-2017 Intel Corporation
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
	21	* IN THE SOFTWARE.
	22	*
	23	*/
	24
	25	#ifndef _INTEL_DEVICE_INFO_H_
	26	#define _INTEL_DEVICE_INFO_H_
	27
4bdafb9d CW	28	#include <uapi/drm/i915_drm.h>
4bdafb9d CW	29
b978520d MW	30	#include "intel_display.h"
	31
	32	struct drm_printer;
	33	struct drm_i915_private;
	34
	35	/* Keep in gen based order, and chronological order within a gen */
	36	enum intel_platform {
	37	INTEL_PLATFORM_UNINITIALIZED = 0,
	38	/* gen2 */
	39	INTEL_I830,
	40	INTEL_I845G,
	41	INTEL_I85X,
	42	INTEL_I865G,
	43	/* gen3 */
	44	INTEL_I915G,
	45	INTEL_I915GM,
	46	INTEL_I945G,
	47	INTEL_I945GM,
	48	INTEL_G33,
	49	INTEL_PINEVIEW,
	50	/* gen4 */
	51	INTEL_I965G,
	52	INTEL_I965GM,
	53	INTEL_G45,
	54	INTEL_GM45,
	55	/* gen5 */
	56	INTEL_IRONLAKE,
	57	/* gen6 */
	58	INTEL_SANDYBRIDGE,
	59	/* gen7 */
	60	INTEL_IVYBRIDGE,
	61	INTEL_VALLEYVIEW,
	62	INTEL_HASWELL,
	63	/* gen8 */
	64	INTEL_BROADWELL,
	65	INTEL_CHERRYVIEW,
	66	/* gen9 */
	67	INTEL_SKYLAKE,
	68	INTEL_BROXTON,
	69	INTEL_KABYLAKE,
	70	INTEL_GEMINILAKE,
	71	INTEL_COFFEELAKE,
	72	/* gen10 */
	73	INTEL_CANNONLAKE,
41231001 RV	74	/* gen11 */
41231001 RV	75	INTEL_ICELAKE,
897f2961	76	INTEL_ELKHARTLAKE,
b978520d MW	77	INTEL_MAX_PLATFORMS
	78	};
	79
cbecbcca	80	enum intel_ppgtt_type {
4bdafb9d CW	81	INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
	82	INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
	83	INTEL_PPGTT_FULL = I915_GEM_PPGTT_FULL,
4bdafb9d CW	84	};
4bdafb9d CW	85
b978520d MW	86	#define DEV_INFO_FOR_EACH_FLAG(func) \
	87	func(is_mobile); \
	88	func(is_lp); \
	89	func(is_alpha_support); \
	90	/* Keep has_* in alphabetical order */ \
	91	func(has_64bit_reloc); \
55277e1f	92	func(gpu_reset_clobbers_display); \
b978520d	93	func(has_reset_engine); \
b978520d	94	func(has_fpga_dbg); \
b978520d MW	95	func(has_guc); \
b978520d MW	96	func(has_guc_ct); \
b978520d MW	97	func(has_l3_dpf); \
	98	func(has_llc); \
	99	func(has_logical_ring_contexts); \
05f0addd	100	func(has_logical_ring_elsq); \
b978520d	101	func(has_logical_ring_preemption); \
b978520d	102	func(has_pooled_eu); \
b978520d MW	103	func(has_rc6); \
b978520d MW	104	func(has_rc6p); \
b978520d MW	105	func(has_runtime_pm); \
b978520d MW	106	func(has_snoop); \
900ccf30	107	func(has_coherent_ggtt); \
b978520d	108	func(unfenced_needs_alignment); \
d53db442 JRS	109	func(hws_needs_physical);
	110
	111	#define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \
	112	/* Keep in alphabetical order */ \
b978520d	113	func(cursor_needs_physical); \
d53db442 JRS	114	func(has_csr); \
	115	func(has_ddi); \
	116	func(has_dp_mst); \
	117	func(has_fbc); \
b2ae318a	118	func(has_gmch); \
d53db442 JRS	119	func(has_hotplug); \
	120	func(has_ipc); \
	121	func(has_overlay); \
	122	func(has_psr); \
b978520d	123	func(overlay_needs_physical); \
d53db442	124	func(supports_tv);
b978520d	125
8cc76693	126	#define GEN_MAX_SLICES (6) /* CNL upper bound */
8b5eb5e2	127	#define GEN_MAX_SUBSLICES (8) /* ICL upper bound */
8cc76693	128
b978520d MW	129	struct sseu_dev_info {
b978520d MW	130	u8 slice_mask;
cf303a41	131	u8 subslice_mask[GEN_MAX_SLICES];
8cc76693	132	u16 eu_total;
b978520d MW	133	u8 eu_per_subslice;
	134	u8 min_eu_in_pool;
	135	/* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
	136	u8 subslice_7eu[3];
	137	u8 has_slice_pg:1;
	138	u8 has_subslice_pg:1;
	139	u8 has_eu_pg:1;
8cc76693 LL	140
	141	/* Topology fields */
	142	u8 max_slices;
	143	u8 max_subslices;
	144	u8 max_eus_per_subslice;
	145
	146	/* We don't have more than 8 eus per subslice at the moment and as we
	147	* store eus enabled using bits, no need to multiply by eus per
	148	* subslice.
	149	*/
	150	u8 eu_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICES];
b978520d MW	151	};
b978520d MW	152
8a68d464	153	typedef u8 intel_engine_mask_t;
022d3093	154
b978520d	155	struct intel_device_info {
b978520d MW	156	u16 gen_mask;
	157
	158	u8 gen;
	159	u8 gt; /* GT number, 0 if undefined */
8a68d464	160	intel_engine_mask_t engine_mask; /* Engines supported by the HW */
b978520d MW	161
	162	enum intel_platform platform;
	163	u32 platform_mask;
	164
cbecbcca CW	165	enum intel_ppgtt_type ppgtt_type;
	166	unsigned int ppgtt_size; /* log2, e.g. 31/32/48 bits */
	167
4552f50a TU	168	unsigned int page_sizes; /* page sizes supported by the HW */
4552f50a TU	169
b978520d MW	170	u32 display_mmio_offset;
	171
	172	u8 num_pipes;
b978520d	173
b978520d MW	174	#define DEFINE_FLAG(name) u8 name:1
	175	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
	176	#undef DEFINE_FLAG
d53db442 JRS	177
	178	struct {
	179	#define DEFINE_FLAG(name) u8 name:1
	180	DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG);
	181	#undef DEFINE_FLAG
	182	} display;
	183
b978520d MW	184	u16 ddb_size; /* in blocks */
	185
	186	/* Register offsets for the various display pipes and transcoders */
	187	int pipe_offsets[I915_MAX_TRANSCODERS];
	188	int trans_offsets[I915_MAX_TRANSCODERS];
b978520d MW	189	int cursor_offsets[I915_MAX_PIPES];
b978520d MW	190
0258404f JN	191	struct color_luts {
	192	u16 degamma_lut_size;
	193	u16 gamma_lut_size;
e4c0d531 MR	194	u32 degamma_lut_tests;
e4c0d531 MR	195	u32 gamma_lut_tests;
0258404f JN	196	} color;
	197	};
	198
	199	struct intel_runtime_info {
	200	u16 device_id;
	201
	202	u8 num_sprites[I915_MAX_PIPES];
	203	u8 num_scalers[I915_MAX_PIPES];
	204
8a68d464	205	u8 num_engines;
0258404f	206
b978520d MW	207	/* Slice/subslice/EU info */
	208	struct sseu_dev_info sseu;
	209
	210	u32 cs_timestamp_frequency_khz;
	211
57b19d55 OM	212	/* Media engine access to SFC per instance */
57b19d55 OM	213	u8 vdbox_sfc_access;
b978520d MW	214	};
b978520d MW	215
3fed1808 CW	216	struct intel_driver_caps {
3fed1808 CW	217	unsigned int scheduler;
481827b4	218	bool has_logical_contexts:1;
3fed1808 CW	219	};
3fed1808 CW	220
b978520d MW	221	static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu)
b978520d MW	222	{
8cc76693 LL	223	unsigned int i, total = 0;
	224
	225	for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++)
	226	total += hweight8(sseu->subslice_mask[i]);
	227
	228	return total;
	229	}
	230
	231	static inline int sseu_eu_idx(const struct sseu_dev_info *sseu,
	232	int slice, int subslice)
	233	{
	234	int subslice_stride = DIV_ROUND_UP(sseu->max_eus_per_subslice,
	235	BITS_PER_BYTE);
	236	int slice_stride = sseu->max_subslices * subslice_stride;
	237
	238	return slice * slice_stride + subslice * subslice_stride;
	239	}
	240
	241	static inline u16 sseu_get_eus(const struct sseu_dev_info *sseu,
	242	int slice, int subslice)
	243	{
	244	int i, offset = sseu_eu_idx(sseu, slice, subslice);
	245	u16 eu_mask = 0;
	246
	247	for (i = 0;
	248	i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) {
	249	eu_mask \|= ((u16) sseu->eu_mask[offset + i]) <<
	250	(i * BITS_PER_BYTE);
	251	}
	252
	253	return eu_mask;
	254	}
	255
	256	static inline void sseu_set_eus(struct sseu_dev_info *sseu,
	257	int slice, int subslice, u16 eu_mask)
	258	{
	259	int i, offset = sseu_eu_idx(sseu, slice, subslice);
	260
	261	for (i = 0;
	262	i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) {
	263	sseu->eu_mask[offset + i] =
	264	(eu_mask >> (BITS_PER_BYTE * i)) & 0xff;
	265	}
b978520d MW	266	}
	267
	268	const char *intel_platform_name(enum intel_platform platform);
	269
1400cc7e	270	void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
b978520d MW	271	void intel_device_info_dump_flags(const struct intel_device_info *info,
b978520d MW	272	struct drm_printer *p);
0258404f	273	void intel_device_info_dump_runtime(const struct intel_runtime_info *info,
5fbbe8d4	274	struct drm_printer *p);
79e9cd5f LL	275	void intel_device_info_dump_topology(const struct sseu_dev_info *sseu,
79e9cd5f LL	276	struct drm_printer *p);
b978520d	277
26376a7e OM	278	void intel_device_info_init_mmio(struct drm_i915_private *dev_priv);
26376a7e OM	279
3fed1808 CW	280	void intel_driver_caps_print(const struct intel_driver_caps *caps,
	281	struct drm_printer *p);
	282
b978520d	283	#endif