[linux-block.git] / drivers / gpu / drm / i915 / intel_device_info.h

/*
 * Copyright © 2014-2017 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 */

#ifndef _INTEL_DEVICE_INFO_H_
#define _INTEL_DEVICE_INFO_H_

#include "intel_display.h"

struct drm_printer;
struct drm_i915_private;

/* Keep in gen based order, and chronological order within a gen */
enum intel_platform {
	INTEL_PLATFORM_UNINITIALIZED = 0,
	/* gen2 */
	INTEL_I830,
	INTEL_I845G,
	INTEL_I85X,
	INTEL_I865G,
	/* gen3 */
	INTEL_I915G,
	INTEL_I915GM,
	INTEL_I945G,
	INTEL_I945GM,
	INTEL_G33,
	INTEL_PINEVIEW,
	/* gen4 */
	INTEL_I965G,
	INTEL_I965GM,
	INTEL_G45,
	INTEL_GM45,
	/* gen5 */
	INTEL_IRONLAKE,
	/* gen6 */
	INTEL_SANDYBRIDGE,
	/* gen7 */
	INTEL_IVYBRIDGE,
	INTEL_VALLEYVIEW,
	INTEL_HASWELL,
	/* gen8 */
	INTEL_BROADWELL,
	INTEL_CHERRYVIEW,
	/* gen9 */
	INTEL_SKYLAKE,
	INTEL_BROXTON,
	INTEL_KABYLAKE,
	INTEL_GEMINILAKE,
	INTEL_COFFEELAKE,
	/* gen10 */
	INTEL_CANNONLAKE,
	/* gen11 */
	INTEL_ICELAKE,
	INTEL_MAX_PLATFORMS
};

#define DEV_INFO_FOR_EACH_FLAG(func) \
	func(is_mobile); \
	func(is_lp); \
	func(is_alpha_support); \
	/* Keep has_* in alphabetical order */ \
	func(has_64bit_reloc); \
	func(has_aliasing_ppgtt); \
	func(has_csr); \
	func(has_ddi); \
	func(has_dp_mst); \
	func(has_reset_engine); \
	func(has_fbc); \
	func(has_fpga_dbg); \
	func(has_full_ppgtt); \
	func(has_full_48bit_ppgtt); \
	func(has_gmch_display); \
	func(has_guc); \
	func(has_guc_ct); \
	func(has_hotplug); \
	func(has_l3_dpf); \
	func(has_llc); \
	func(has_logical_ring_contexts); \
	func(has_logical_ring_elsq); \
	func(has_logical_ring_preemption); \
	func(has_overlay); \
	func(has_pooled_eu); \
	func(has_psr); \
	func(has_rc6); \
	func(has_rc6p); \
	func(has_resource_streamer); \
	func(has_runtime_pm); \
	func(has_snoop); \
	func(unfenced_needs_alignment); \
	func(cursor_needs_physical); \
	func(hws_needs_physical); \
	func(overlay_needs_physical); \
	func(supports_tv); \
	func(has_ipc);

#define GEN_MAX_SLICES		(6) /* CNL upper bound */
#define GEN_MAX_SUBSLICES	(8) /* ICL upper bound */

struct sseu_dev_info {
	u8 slice_mask;
	u8 subslice_mask[GEN_MAX_SUBSLICES];
	u16 eu_total;
	u8 eu_per_subslice;
	u8 min_eu_in_pool;
	/* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
	u8 subslice_7eu[3];
	u8 has_slice_pg:1;
	u8 has_subslice_pg:1;
	u8 has_eu_pg:1;

	/* Topology fields */
	u8 max_slices;
	u8 max_subslices;
	u8 max_eus_per_subslice;

	/* We don't have more than 8 eus per subslice at the moment and as we
	 * store eus enabled using bits, no need to multiply by eus per
	 * subslice.
	 */
	u8 eu_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICES];
};

typedef u8 intel_ring_mask_t;

struct intel_device_info {
	u16 device_id;
	u16 gen_mask;

	u8 gen;
	u8 gt; /* GT number, 0 if undefined */
	u8 num_rings;
	intel_ring_mask_t ring_mask; /* Rings supported by the HW */

	enum intel_platform platform;
	u32 platform_mask;

	unsigned int page_sizes; /* page sizes supported by the HW */

	u32 display_mmio_offset;

	u8 num_pipes;
	u8 num_sprites[I915_MAX_PIPES];
	u8 num_scalers[I915_MAX_PIPES];

#define DEFINE_FLAG(name) u8 name:1
	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
#undef DEFINE_FLAG
	u16 ddb_size; /* in blocks */

	/* Register offsets for the various display pipes and transcoders */
	int pipe_offsets[I915_MAX_TRANSCODERS];
	int trans_offsets[I915_MAX_TRANSCODERS];
	int palette_offsets[I915_MAX_PIPES];
	int cursor_offsets[I915_MAX_PIPES];

	/* Slice/subslice/EU info */
	struct sseu_dev_info sseu;

	u32 cs_timestamp_frequency_khz;

	struct color_luts {
		u16 degamma_lut_size;
		u16 gamma_lut_size;
	} color;
};

struct intel_driver_caps {
	unsigned int scheduler;
	bool has_logical_contexts:1;
};

static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu)
{
	unsigned int i, total = 0;

	for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++)
		total += hweight8(sseu->subslice_mask[i]);

	return total;
}

static inline int sseu_eu_idx(const struct sseu_dev_info *sseu,
			      int slice, int subslice)
{
	int subslice_stride = DIV_ROUND_UP(sseu->max_eus_per_subslice,
					   BITS_PER_BYTE);
	int slice_stride = sseu->max_subslices * subslice_stride;

	return slice * slice_stride + subslice * subslice_stride;
}

static inline u16 sseu_get_eus(const struct sseu_dev_info *sseu,
			       int slice, int subslice)
{
	int i, offset = sseu_eu_idx(sseu, slice, subslice);
	u16 eu_mask = 0;

	for (i = 0;
	     i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) {
		eu_mask |= ((u16) sseu->eu_mask[offset + i]) <<
			(i * BITS_PER_BYTE);
	}

	return eu_mask;
}

static inline void sseu_set_eus(struct sseu_dev_info *sseu,
				int slice, int subslice, u16 eu_mask)
{
	int i, offset = sseu_eu_idx(sseu, slice, subslice);

	for (i = 0;
	     i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) {
		sseu->eu_mask[offset + i] =
			(eu_mask >> (BITS_PER_BYTE * i)) & 0xff;
	}
}

const char *intel_platform_name(enum intel_platform platform);

void intel_device_info_runtime_init(struct intel_device_info *info);
void intel_device_info_dump(const struct intel_device_info *info,
			    struct drm_printer *p);
void intel_device_info_dump_flags(const struct intel_device_info *info,
				  struct drm_printer *p);
void intel_device_info_dump_runtime(const struct intel_device_info *info,
				    struct drm_printer *p);
void intel_device_info_dump_topology(const struct sseu_dev_info *sseu,
				     struct drm_printer *p);

void intel_device_info_init_mmio(struct drm_i915_private *dev_priv);

void intel_driver_caps_print(const struct intel_driver_caps *caps,
			     struct drm_printer *p);

#endif
Commit	Line	Data
b978520d MW	1	/*
	2	* Copyright © 2014-2017 Intel Corporation
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
	21	* IN THE SOFTWARE.
	22	*
	23	*/
	24
	25	#ifndef _INTEL_DEVICE_INFO_H_
	26	#define _INTEL_DEVICE_INFO_H_
	27
	28	#include "intel_display.h"
	29
	30	struct drm_printer;
	31	struct drm_i915_private;
	32
	33	/* Keep in gen based order, and chronological order within a gen */
	34	enum intel_platform {
	35	INTEL_PLATFORM_UNINITIALIZED = 0,
	36	/* gen2 */
	37	INTEL_I830,
	38	INTEL_I845G,
	39	INTEL_I85X,
	40	INTEL_I865G,
	41	/* gen3 */
	42	INTEL_I915G,
	43	INTEL_I915GM,
	44	INTEL_I945G,
	45	INTEL_I945GM,
	46	INTEL_G33,
	47	INTEL_PINEVIEW,
	48	/* gen4 */
	49	INTEL_I965G,
	50	INTEL_I965GM,
	51	INTEL_G45,
	52	INTEL_GM45,
	53	/* gen5 */
	54	INTEL_IRONLAKE,
	55	/* gen6 */
	56	INTEL_SANDYBRIDGE,
	57	/* gen7 */
	58	INTEL_IVYBRIDGE,
	59	INTEL_VALLEYVIEW,
	60	INTEL_HASWELL,
	61	/* gen8 */
	62	INTEL_BROADWELL,
	63	INTEL_CHERRYVIEW,
	64	/* gen9 */
65	INTEL_SKYLAKE,
66	INTEL_BROXTON,
67	INTEL_KABYLAKE,
68	INTEL_GEMINILAKE,
69	INTEL_COFFEELAKE,
70	/* gen10 */
71	INTEL_CANNONLAKE,
41231001 RV	72	/* gen11 */
41231001 RV	73	INTEL_ICELAKE,
b978520d MW	74	INTEL_MAX_PLATFORMS
	75	};
	76
	77	#define DEV_INFO_FOR_EACH_FLAG(func) \
	78	func(is_mobile); \
	79	func(is_lp); \
	80	func(is_alpha_support); \
	81	/* Keep has_* in alphabetical order */ \
	82	func(has_64bit_reloc); \
	83	func(has_aliasing_ppgtt); \
	84	func(has_csr); \
	85	func(has_ddi); \
	86	func(has_dp_mst); \
	87	func(has_reset_engine); \
	88	func(has_fbc); \
	89	func(has_fpga_dbg); \
	90	func(has_full_ppgtt); \
	91	func(has_full_48bit_ppgtt); \
	92	func(has_gmch_display); \
	93	func(has_guc); \
	94	func(has_guc_ct); \
	95	func(has_hotplug); \
	96	func(has_l3_dpf); \
	97	func(has_llc); \
	98	func(has_logical_ring_contexts); \
05f0addd	99	func(has_logical_ring_elsq); \
b978520d MW	100	func(has_logical_ring_preemption); \
	101	func(has_overlay); \
	102	func(has_pooled_eu); \
	103	func(has_psr); \
	104	func(has_rc6); \
	105	func(has_rc6p); \
	106	func(has_resource_streamer); \
	107	func(has_runtime_pm); \
	108	func(has_snoop); \
	109	func(unfenced_needs_alignment); \
	110	func(cursor_needs_physical); \
	111	func(hws_needs_physical); \
	112	func(overlay_needs_physical); \
	113	func(supports_tv); \
	114	func(has_ipc);
	115
8cc76693	116	#define GEN_MAX_SLICES (6) /* CNL upper bound */
8b5eb5e2	117	#define GEN_MAX_SUBSLICES (8) /* ICL upper bound */
8cc76693	118
b978520d MW	119	struct sseu_dev_info {
b978520d MW	120	u8 slice_mask;
8cc76693 LL	121	u8 subslice_mask[GEN_MAX_SUBSLICES];
8cc76693 LL	122	u16 eu_total;
b978520d MW	123	u8 eu_per_subslice;
	124	u8 min_eu_in_pool;
	125	/* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
	126	u8 subslice_7eu[3];
	127	u8 has_slice_pg:1;
	128	u8 has_subslice_pg:1;
	129	u8 has_eu_pg:1;
8cc76693 LL	130
	131	/* Topology fields */
	132	u8 max_slices;
	133	u8 max_subslices;
	134	u8 max_eus_per_subslice;
	135
	136	/* We don't have more than 8 eus per subslice at the moment and as we
	137	* store eus enabled using bits, no need to multiply by eus per
	138	* subslice.
	139	*/
	140	u8 eu_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICES];
b978520d MW	141	};
b978520d MW	142
022d3093 TU	143	typedef u8 intel_ring_mask_t;
022d3093 TU	144
b978520d MW	145	struct intel_device_info {
	146	u16 device_id;
	147	u16 gen_mask;
	148
	149	u8 gen;
	150	u8 gt; /* GT number, 0 if undefined */
	151	u8 num_rings;
022d3093	152	intel_ring_mask_t ring_mask; /* Rings supported by the HW */
b978520d MW	153
	154	enum intel_platform platform;
	155	u32 platform_mask;
	156
4552f50a TU	157	unsigned int page_sizes; /* page sizes supported by the HW */
4552f50a TU	158
b978520d MW	159	u32 display_mmio_offset;
	160
	161	u8 num_pipes;
	162	u8 num_sprites[I915_MAX_PIPES];
	163	u8 num_scalers[I915_MAX_PIPES];
	164
b978520d MW	165	#define DEFINE_FLAG(name) u8 name:1
	166	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
	167	#undef DEFINE_FLAG
	168	u16 ddb_size; /* in blocks */
	169
	170	/* Register offsets for the various display pipes and transcoders */
	171	int pipe_offsets[I915_MAX_TRANSCODERS];
	172	int trans_offsets[I915_MAX_TRANSCODERS];
	173	int palette_offsets[I915_MAX_PIPES];
	174	int cursor_offsets[I915_MAX_PIPES];
	175
	176	/* Slice/subslice/EU info */
	177	struct sseu_dev_info sseu;
	178
	179	u32 cs_timestamp_frequency_khz;
	180
	181	struct color_luts {
	182	u16 degamma_lut_size;
	183	u16 gamma_lut_size;
	184	} color;
	185	};
	186
3fed1808 CW	187	struct intel_driver_caps {
3fed1808 CW	188	unsigned int scheduler;
481827b4	189	bool has_logical_contexts:1;
3fed1808 CW	190	};
3fed1808 CW	191
b978520d MW	192	static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu)
b978520d MW	193	{
8cc76693 LL	194	unsigned int i, total = 0;
	195
	196	for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask); i++)
	197	total += hweight8(sseu->subslice_mask[i]);
	198
	199	return total;
	200	}
	201
	202	static inline int sseu_eu_idx(const struct sseu_dev_info *sseu,
	203	int slice, int subslice)
	204	{
	205	int subslice_stride = DIV_ROUND_UP(sseu->max_eus_per_subslice,
	206	BITS_PER_BYTE);
	207	int slice_stride = sseu->max_subslices * subslice_stride;
	208
	209	return slice * slice_stride + subslice * subslice_stride;
	210	}
	211
	212	static inline u16 sseu_get_eus(const struct sseu_dev_info *sseu,
	213	int slice, int subslice)
	214	{
	215	int i, offset = sseu_eu_idx(sseu, slice, subslice);
	216	u16 eu_mask = 0;
	217
	218	for (i = 0;
	219	i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) {
	220	eu_mask \|= ((u16) sseu->eu_mask[offset + i]) <<
	221	(i * BITS_PER_BYTE);
	222	}
	223
	224	return eu_mask;
	225	}
	226
	227	static inline void sseu_set_eus(struct sseu_dev_info *sseu,
	228	int slice, int subslice, u16 eu_mask)
	229	{
	230	int i, offset = sseu_eu_idx(sseu, slice, subslice);
	231
	232	for (i = 0;
	233	i < DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); i++) {
	234	sseu->eu_mask[offset + i] =
	235	(eu_mask >> (BITS_PER_BYTE * i)) & 0xff;
	236	}
b978520d MW	237	}
	238
	239	const char *intel_platform_name(enum intel_platform platform);
	240
6a7e51f3	241	void intel_device_info_runtime_init(struct intel_device_info *info);
b978520d MW	242	void intel_device_info_dump(const struct intel_device_info *info,
	243	struct drm_printer *p);
	244	void intel_device_info_dump_flags(const struct intel_device_info *info,
	245	struct drm_printer *p);
5fbbe8d4 MW	246	void intel_device_info_dump_runtime(const struct intel_device_info *info,
5fbbe8d4 MW	247	struct drm_printer *p);
79e9cd5f LL	248	void intel_device_info_dump_topology(const struct sseu_dev_info *sseu,
79e9cd5f LL	249	struct drm_printer *p);
b978520d	250
26376a7e OM	251	void intel_device_info_init_mmio(struct drm_i915_private *dev_priv);
26376a7e OM	252
3fed1808 CW	253	void intel_driver_caps_print(const struct intel_driver_caps *caps,
	254	struct drm_printer *p);
	255
b978520d	256	#endif