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b978520d MW |
1 | /* |
2 | * Copyright © 2014-2017 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | ||
25 | #ifndef _INTEL_DEVICE_INFO_H_ | |
26 | #define _INTEL_DEVICE_INFO_H_ | |
27 | ||
4bdafb9d CW |
28 | #include <uapi/drm/i915_drm.h> |
29 | ||
439c8dcc JN |
30 | #include "intel_step.h" |
31 | ||
df0566a6 JN |
32 | #include "display/intel_display.h" |
33 | ||
112ed2d3 CW |
34 | #include "gt/intel_engine_types.h" |
35 | #include "gt/intel_context_types.h" | |
36 | #include "gt/intel_sseu.h" | |
37 | ||
b978520d MW |
38 | struct drm_printer; |
39 | struct drm_i915_private; | |
40 | ||
41 | /* Keep in gen based order, and chronological order within a gen */ | |
42 | enum intel_platform { | |
43 | INTEL_PLATFORM_UNINITIALIZED = 0, | |
44 | /* gen2 */ | |
45 | INTEL_I830, | |
46 | INTEL_I845G, | |
47 | INTEL_I85X, | |
48 | INTEL_I865G, | |
49 | /* gen3 */ | |
50 | INTEL_I915G, | |
51 | INTEL_I915GM, | |
52 | INTEL_I945G, | |
53 | INTEL_I945GM, | |
54 | INTEL_G33, | |
55 | INTEL_PINEVIEW, | |
56 | /* gen4 */ | |
57 | INTEL_I965G, | |
58 | INTEL_I965GM, | |
59 | INTEL_G45, | |
60 | INTEL_GM45, | |
61 | /* gen5 */ | |
62 | INTEL_IRONLAKE, | |
63 | /* gen6 */ | |
64 | INTEL_SANDYBRIDGE, | |
65 | /* gen7 */ | |
66 | INTEL_IVYBRIDGE, | |
67 | INTEL_VALLEYVIEW, | |
68 | INTEL_HASWELL, | |
69 | /* gen8 */ | |
70 | INTEL_BROADWELL, | |
71 | INTEL_CHERRYVIEW, | |
72 | /* gen9 */ | |
73 | INTEL_SKYLAKE, | |
74 | INTEL_BROXTON, | |
75 | INTEL_KABYLAKE, | |
76 | INTEL_GEMINILAKE, | |
77 | INTEL_COFFEELAKE, | |
5f4ae270 | 78 | INTEL_COMETLAKE, |
41231001 RV |
79 | /* gen11 */ |
80 | INTEL_ICELAKE, | |
897f2961 | 81 | INTEL_ELKHARTLAKE, |
24ea098b | 82 | INTEL_JASPERLAKE, |
abd3a0fe DCS |
83 | /* gen12 */ |
84 | INTEL_TIGERLAKE, | |
123f62de | 85 | INTEL_ROCKETLAKE, |
05e26584 | 86 | INTEL_DG1, |
0883d63b | 87 | INTEL_ALDERLAKE_S, |
bdd27cad | 88 | INTEL_ALDERLAKE_P, |
086df54e | 89 | INTEL_XEHPSDV, |
9e22cfc5 | 90 | INTEL_DG2, |
b978520d MW |
91 | INTEL_MAX_PLATFORMS |
92 | }; | |
93 | ||
805446c8 TU |
94 | /* |
95 | * Subplatform bits share the same namespace per parent platform. In other words | |
96 | * it is fine for the same bit to be used on multiple parent platforms. | |
97 | */ | |
98 | ||
56afa701 TU |
99 | #define INTEL_SUBPLATFORM_BITS (2) |
100 | #define INTEL_SUBPLATFORM_MASK (BIT(INTEL_SUBPLATFORM_BITS) - 1) | |
805446c8 TU |
101 | |
102 | /* HSW/BDW/SKL/KBL/CFL */ | |
103 | #define INTEL_SUBPLATFORM_ULT (0) | |
104 | #define INTEL_SUBPLATFORM_ULX (1) | |
805446c8 | 105 | |
244dba4c | 106 | /* ICL */ |
805446c8 TU |
107 | #define INTEL_SUBPLATFORM_PORTF (0) |
108 | ||
9e22cfc5 MR |
109 | /* DG2 */ |
110 | #define INTEL_SUBPLATFORM_G10 0 | |
111 | #define INTEL_SUBPLATFORM_G11 1 | |
112 | ||
52407c22 AS |
113 | /* ADL-S */ |
114 | #define INTEL_SUBPLATFORM_RPL_S 0 | |
115 | ||
cbecbcca | 116 | enum intel_ppgtt_type { |
4bdafb9d CW |
117 | INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE, |
118 | INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING, | |
119 | INTEL_PPGTT_FULL = I915_GEM_PPGTT_FULL, | |
4bdafb9d CW |
120 | }; |
121 | ||
b978520d MW |
122 | #define DEV_INFO_FOR_EACH_FLAG(func) \ |
123 | func(is_mobile); \ | |
124 | func(is_lp); \ | |
7ef5ef5c | 125 | func(require_force_probe); \ |
dc90fe3f | 126 | func(is_dgfx); \ |
b978520d MW |
127 | /* Keep has_* in alphabetical order */ \ |
128 | func(has_64bit_reloc); \ | |
c83125bb | 129 | func(has_64k_pages); \ |
55277e1f | 130 | func(gpu_reset_clobbers_display); \ |
b978520d | 131 | func(has_reset_engine); \ |
a7a7a0e6 | 132 | func(has_global_mocs); \ |
702668e6 | 133 | func(has_gt_uc); \ |
db3b3f3e | 134 | func(has_guc_deprivilege); \ |
b978520d MW |
135 | func(has_l3_dpf); \ |
136 | func(has_llc); \ | |
137 | func(has_logical_ring_contexts); \ | |
05f0addd | 138 | func(has_logical_ring_elsq); \ |
3ffe82d7 | 139 | func(has_mslices); \ |
b978520d | 140 | func(has_pooled_eu); \ |
e6aa7136 | 141 | func(has_pxp); \ |
b978520d MW |
142 | func(has_rc6); \ |
143 | func(has_rc6p); \ | |
91cbdb83 | 144 | func(has_rps); \ |
b978520d MW |
145 | func(has_runtime_pm); \ |
146 | func(has_snoop); \ | |
900ccf30 | 147 | func(has_coherent_ggtt); \ |
b978520d | 148 | func(unfenced_needs_alignment); \ |
d53db442 JRS |
149 | func(hws_needs_physical); |
150 | ||
151 | #define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \ | |
152 | /* Keep in alphabetical order */ \ | |
b978520d | 153 | func(cursor_needs_physical); \ |
eafaa3e9 | 154 | func(has_cdclk_crawl); \ |
ec2b1485 | 155 | func(has_dmc); \ |
d53db442 JRS |
156 | func(has_ddi); \ |
157 | func(has_dp_mst); \ | |
18febcb7 | 158 | func(has_dsb); \ |
0f9ed3b2 | 159 | func(has_dsc); \ |
d53db442 | 160 | func(has_fbc); \ |
a321c3c6 | 161 | func(has_fpga_dbg); \ |
b2ae318a | 162 | func(has_gmch); \ |
74393109 | 163 | func(has_hdcp); \ |
d53db442 | 164 | func(has_hotplug); \ |
ddff9a60 | 165 | func(has_hti); \ |
d53db442 | 166 | func(has_ipc); \ |
0caf6257 | 167 | func(has_modular_fia); \ |
d53db442 JRS |
168 | func(has_overlay); \ |
169 | func(has_psr); \ | |
24d2fc3d | 170 | func(has_psr_hw_tracking); \ |
b978520d | 171 | func(overlay_needs_physical); \ |
d53db442 | 172 | func(supports_tv); |
b978520d | 173 | |
a5b7ef27 JRS |
174 | struct ip_version { |
175 | u8 ver; | |
176 | u8 rel; | |
177 | }; | |
178 | ||
b978520d | 179 | struct intel_device_info { |
a5b7ef27 JRS |
180 | struct ip_version graphics; |
181 | struct ip_version media; | |
93babb06 | 182 | |
792592e7 | 183 | intel_engine_mask_t platform_engine_mask; /* Engines supported by the HW */ |
b978520d MW |
184 | |
185 | enum intel_platform platform; | |
b978520d | 186 | |
31a02eb7 MR |
187 | unsigned int dma_mask_size; /* available DMA address bits */ |
188 | ||
cbecbcca CW |
189 | enum intel_ppgtt_type ppgtt_type; |
190 | unsigned int ppgtt_size; /* log2, e.g. 31/32/48 bits */ | |
191 | ||
4552f50a | 192 | unsigned int page_sizes; /* page sizes supported by the HW */ |
3aae9d08 AJ |
193 | |
194 | u32 memory_regions; /* regions supported by the HW */ | |
4552f50a | 195 | |
b978520d MW |
196 | u32 display_mmio_offset; |
197 | ||
938c778f JH |
198 | u8 gt; /* GT number, 0 if undefined */ |
199 | ||
b978520d MW |
200 | #define DEFINE_FLAG(name) u8 name:1 |
201 | DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG); | |
202 | #undef DEFINE_FLAG | |
d53db442 JRS |
203 | |
204 | struct { | |
4df9c1ae | 205 | u8 ver; |
a5b7ef27 | 206 | u8 rel; |
01eb15c9 | 207 | |
6678916d VS |
208 | u8 pipe_mask; |
209 | u8 cpu_transcoder_mask; | |
210 | u8 abox_mask; | |
211 | ||
d53db442 JRS |
212 | #define DEFINE_FLAG(name) u8 name:1 |
213 | DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG); | |
214 | #undef DEFINE_FLAG | |
215 | } display; | |
216 | ||
708de86e VS |
217 | struct { |
218 | u16 size; /* in blocks */ | |
578e6ede | 219 | u8 slice_mask; |
708de86e | 220 | } dbuf; |
b978520d MW |
221 | |
222 | /* Register offsets for the various display pipes and transcoders */ | |
223 | int pipe_offsets[I915_MAX_TRANSCODERS]; | |
224 | int trans_offsets[I915_MAX_TRANSCODERS]; | |
b978520d MW |
225 | int cursor_offsets[I915_MAX_PIPES]; |
226 | ||
0258404f | 227 | struct color_luts { |
89a72304 SS |
228 | u32 degamma_lut_size; |
229 | u32 gamma_lut_size; | |
e4c0d531 MR |
230 | u32 degamma_lut_tests; |
231 | u32 gamma_lut_tests; | |
0258404f JN |
232 | } color; |
233 | }; | |
234 | ||
235 | struct intel_runtime_info { | |
805446c8 TU |
236 | /* |
237 | * Platform mask is used for optimizing or-ed IS_PLATFORM calls into | |
238 | * into single runtime conditionals, and also to provide groundwork | |
239 | * for future per platform, or per SKU build optimizations. | |
240 | * | |
241 | * Array can be extended when necessary if the corresponding | |
242 | * BUILD_BUG_ON is hit. | |
243 | */ | |
244 | u32 platform_mask[2]; | |
245 | ||
0258404f JN |
246 | u16 device_id; |
247 | ||
248 | u8 num_sprites[I915_MAX_PIPES]; | |
249 | u8 num_scalers[I915_MAX_PIPES]; | |
250 | ||
b04002f4 | 251 | u32 rawclk_freq; |
439c8dcc | 252 | |
5644dc0a | 253 | struct intel_step_info step; |
b978520d MW |
254 | }; |
255 | ||
3fed1808 CW |
256 | struct intel_driver_caps { |
257 | unsigned int scheduler; | |
481827b4 | 258 | bool has_logical_contexts:1; |
3fed1808 CW |
259 | }; |
260 | ||
b978520d MW |
261 | const char *intel_platform_name(enum intel_platform platform); |
262 | ||
805446c8 | 263 | void intel_device_info_subplatform_init(struct drm_i915_private *dev_priv); |
1400cc7e | 264 | void intel_device_info_runtime_init(struct drm_i915_private *dev_priv); |
72404978 CW |
265 | |
266 | void intel_device_info_print_static(const struct intel_device_info *info, | |
5fbbe8d4 | 267 | struct drm_printer *p); |
72404978 | 268 | void intel_device_info_print_runtime(const struct intel_runtime_info *info, |
79e9cd5f | 269 | struct drm_printer *p); |
b978520d | 270 | |
3fed1808 CW |
271 | void intel_driver_caps_print(const struct intel_driver_caps *caps, |
272 | struct drm_printer *p); | |
273 | ||
b978520d | 274 | #endif |