[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_device_info.c

/*
 * Copyright © 2016 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 */

#include <linux/string_helpers.h>

#include <drm/drm_print.h>
#include <drm/intel/pciids.h>

#include "gt/intel_gt_regs.h"
#include "i915_drv.h"
#include "i915_reg.h"
#include "i915_utils.h"
#include "intel_device_info.h"

#define PLATFORM_NAME(x) [INTEL_##x] = #x
static const char * const platform_names[] = {
	PLATFORM_NAME(I830),
	PLATFORM_NAME(I845G),
	PLATFORM_NAME(I85X),
	PLATFORM_NAME(I865G),
	PLATFORM_NAME(I915G),
	PLATFORM_NAME(I915GM),
	PLATFORM_NAME(I945G),
	PLATFORM_NAME(I945GM),
	PLATFORM_NAME(G33),
	PLATFORM_NAME(PINEVIEW),
	PLATFORM_NAME(I965G),
	PLATFORM_NAME(I965GM),
	PLATFORM_NAME(G45),
	PLATFORM_NAME(GM45),
	PLATFORM_NAME(IRONLAKE),
	PLATFORM_NAME(SANDYBRIDGE),
	PLATFORM_NAME(IVYBRIDGE),
	PLATFORM_NAME(VALLEYVIEW),
	PLATFORM_NAME(HASWELL),
	PLATFORM_NAME(BROADWELL),
	PLATFORM_NAME(CHERRYVIEW),
	PLATFORM_NAME(SKYLAKE),
	PLATFORM_NAME(BROXTON),
	PLATFORM_NAME(KABYLAKE),
	PLATFORM_NAME(GEMINILAKE),
	PLATFORM_NAME(COFFEELAKE),
	PLATFORM_NAME(COMETLAKE),
	PLATFORM_NAME(ICELAKE),
	PLATFORM_NAME(ELKHARTLAKE),
	PLATFORM_NAME(JASPERLAKE),
	PLATFORM_NAME(TIGERLAKE),
	PLATFORM_NAME(ROCKETLAKE),
	PLATFORM_NAME(DG1),
	PLATFORM_NAME(ALDERLAKE_S),
	PLATFORM_NAME(ALDERLAKE_P),
	PLATFORM_NAME(DG2),
	PLATFORM_NAME(METEORLAKE),
};
#undef PLATFORM_NAME

const char *intel_platform_name(enum intel_platform platform)
{
	BUILD_BUG_ON(ARRAY_SIZE(platform_names) != INTEL_MAX_PLATFORMS);

	if (WARN_ON_ONCE(platform >= ARRAY_SIZE(platform_names) ||
			 platform_names[platform] == NULL))
		return "<unknown>";

	return platform_names[platform];
}

void intel_device_info_print(const struct intel_device_info *info,
			     const struct intel_runtime_info *runtime,
			     struct drm_printer *p)
{
	if (runtime->graphics.ip.rel)
		drm_printf(p, "graphics version: %u.%02u\n",
			   runtime->graphics.ip.ver,
			   runtime->graphics.ip.rel);
	else
		drm_printf(p, "graphics version: %u\n",
			   runtime->graphics.ip.ver);

	if (runtime->media.ip.rel)
		drm_printf(p, "media version: %u.%02u\n",
			   runtime->media.ip.ver,
			   runtime->media.ip.rel);
	else
		drm_printf(p, "media version: %u\n",
			   runtime->media.ip.ver);

	drm_printf(p, "graphics stepping: %s\n", intel_step_name(runtime->step.graphics_step));
	drm_printf(p, "media stepping: %s\n", intel_step_name(runtime->step.media_step));

	drm_printf(p, "gt: %d\n", info->gt);
	drm_printf(p, "memory-regions: 0x%x\n", info->memory_regions);
	drm_printf(p, "page-sizes: 0x%x\n", runtime->page_sizes);
	drm_printf(p, "platform: %s\n", intel_platform_name(info->platform));
	drm_printf(p, "ppgtt-size: %d\n", runtime->ppgtt_size);
	drm_printf(p, "ppgtt-type: %d\n", runtime->ppgtt_type);
	drm_printf(p, "dma_mask_size: %u\n", info->dma_mask_size);

#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, str_yes_no(info->name))
	DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
#undef PRINT_FLAG

	drm_printf(p, "has_pooled_eu: %s\n", str_yes_no(runtime->has_pooled_eu));
}

#define ID(id) (id)

static const u16 subplatform_ult_ids[] = {
	INTEL_HSW_ULT_GT1_IDS(ID),
	INTEL_HSW_ULT_GT2_IDS(ID),
	INTEL_HSW_ULT_GT3_IDS(ID),
	INTEL_BDW_ULT_GT1_IDS(ID),
	INTEL_BDW_ULT_GT2_IDS(ID),
	INTEL_BDW_ULT_GT3_IDS(ID),
	INTEL_BDW_ULT_RSVD_IDS(ID),
	INTEL_SKL_ULT_GT1_IDS(ID),
	INTEL_SKL_ULT_GT2_IDS(ID),
	INTEL_SKL_ULT_GT3_IDS(ID),
	INTEL_KBL_ULT_GT1_IDS(ID),
	INTEL_KBL_ULT_GT2_IDS(ID),
	INTEL_KBL_ULT_GT3_IDS(ID),
	INTEL_CFL_U_GT2_IDS(ID),
	INTEL_CFL_U_GT3_IDS(ID),
	INTEL_WHL_U_GT1_IDS(ID),
	INTEL_WHL_U_GT2_IDS(ID),
	INTEL_WHL_U_GT3_IDS(ID),
	INTEL_CML_U_GT1_IDS(ID),
	INTEL_CML_U_GT2_IDS(ID),
};

static const u16 subplatform_ulx_ids[] = {
	INTEL_HSW_ULX_GT1_IDS(ID),
	INTEL_HSW_ULX_GT2_IDS(ID),
	INTEL_BDW_ULX_GT1_IDS(ID),
	INTEL_BDW_ULX_GT2_IDS(ID),
	INTEL_BDW_ULX_GT3_IDS(ID),
	INTEL_BDW_ULX_RSVD_IDS(ID),
	INTEL_SKL_ULX_GT1_IDS(ID),
	INTEL_SKL_ULX_GT2_IDS(ID),
	INTEL_KBL_ULX_GT1_IDS(ID),
	INTEL_KBL_ULX_GT2_IDS(ID),
	INTEL_AML_KBL_GT2_IDS(ID),
	INTEL_AML_CFL_GT2_IDS(ID),
};

static const u16 subplatform_portf_ids[] = {
	INTEL_ICL_PORT_F_IDS(ID),
};

static const u16 subplatform_uy_ids[] = {
	INTEL_TGL_GT2_IDS(ID),
};

static const u16 subplatform_n_ids[] = {
	INTEL_ADLN_IDS(ID),
};

static const u16 subplatform_rpl_ids[] = {
	INTEL_RPLS_IDS(ID),
	INTEL_RPLU_IDS(ID),
	INTEL_RPLP_IDS(ID),
};

static const u16 subplatform_rplu_ids[] = {
	INTEL_RPLU_IDS(ID),
};

static const u16 subplatform_g10_ids[] = {
	INTEL_DG2_G10_IDS(ID),
	INTEL_ATS_M150_IDS(ID),
};

static const u16 subplatform_g11_ids[] = {
	INTEL_DG2_G11_IDS(ID),
	INTEL_ATS_M75_IDS(ID),
};

static const u16 subplatform_g12_ids[] = {
	INTEL_DG2_G12_IDS(ID),
};

static const u16 subplatform_dg2_d_ids[] = {
	INTEL_DG2_D_IDS(ID),
};

static const u16 subplatform_arl_h_ids[] = {
	INTEL_ARL_H_IDS(ID),
};

static const u16 subplatform_arl_u_ids[] = {
	INTEL_ARL_U_IDS(ID),
};

static const u16 subplatform_arl_s_ids[] = {
	INTEL_ARL_S_IDS(ID),
};

static bool find_devid(u16 id, const u16 *p, unsigned int num)
{
	for (; num; num--, p++) {
		if (*p == id)
			return true;
	}

	return false;
}

static void intel_device_info_subplatform_init(struct drm_i915_private *i915)
{
	const struct intel_device_info *info = INTEL_INFO(i915);
	const struct intel_runtime_info *rinfo = RUNTIME_INFO(i915);
	const unsigned int pi = __platform_mask_index(rinfo, info->platform);
	const unsigned int pb = __platform_mask_bit(rinfo, info->platform);
	u16 devid = INTEL_DEVID(i915);
	u32 mask = 0;

	/* Make sure IS_<platform> checks are working. */
	RUNTIME_INFO(i915)->platform_mask[pi] = BIT(pb);

	/* Find and mark subplatform bits based on the PCI device id. */
	if (find_devid(devid, subplatform_ult_ids,
		       ARRAY_SIZE(subplatform_ult_ids))) {
		mask = BIT(INTEL_SUBPLATFORM_ULT);
	} else if (find_devid(devid, subplatform_ulx_ids,
			      ARRAY_SIZE(subplatform_ulx_ids))) {
		mask = BIT(INTEL_SUBPLATFORM_ULX);
		if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
			/* ULX machines are also considered ULT. */
			mask |= BIT(INTEL_SUBPLATFORM_ULT);
		}
	} else if (find_devid(devid, subplatform_portf_ids,
			      ARRAY_SIZE(subplatform_portf_ids))) {
		mask = BIT(INTEL_SUBPLATFORM_PORTF);
	} else if (find_devid(devid, subplatform_uy_ids,
			   ARRAY_SIZE(subplatform_uy_ids))) {
		mask = BIT(INTEL_SUBPLATFORM_UY);
	} else if (find_devid(devid, subplatform_n_ids,
				ARRAY_SIZE(subplatform_n_ids))) {
		mask = BIT(INTEL_SUBPLATFORM_N);
	} else if (find_devid(devid, subplatform_rpl_ids,
			      ARRAY_SIZE(subplatform_rpl_ids))) {
		mask = BIT(INTEL_SUBPLATFORM_RPL);
		if (find_devid(devid, subplatform_rplu_ids,
			       ARRAY_SIZE(subplatform_rplu_ids)))
			mask |= BIT(INTEL_SUBPLATFORM_RPLU);
	} else if (find_devid(devid, subplatform_g10_ids,
			      ARRAY_SIZE(subplatform_g10_ids))) {
		mask = BIT(INTEL_SUBPLATFORM_G10);
	} else if (find_devid(devid, subplatform_g11_ids,
			      ARRAY_SIZE(subplatform_g11_ids))) {
		mask = BIT(INTEL_SUBPLATFORM_G11);
	} else if (find_devid(devid, subplatform_g12_ids,
			      ARRAY_SIZE(subplatform_g12_ids))) {
		mask = BIT(INTEL_SUBPLATFORM_G12);
	} else if (find_devid(devid, subplatform_arl_h_ids,
			      ARRAY_SIZE(subplatform_arl_h_ids))) {
		mask = BIT(INTEL_SUBPLATFORM_ARL_H);
	} else if (find_devid(devid, subplatform_arl_u_ids,
			      ARRAY_SIZE(subplatform_arl_u_ids))) {
		mask = BIT(INTEL_SUBPLATFORM_ARL_U);
	} else if (find_devid(devid, subplatform_arl_s_ids,
			      ARRAY_SIZE(subplatform_arl_s_ids))) {
		mask = BIT(INTEL_SUBPLATFORM_ARL_S);
	}

	/* DG2_D ids span across multiple DG2 subplatforms */
	if (find_devid(devid, subplatform_dg2_d_ids,
		       ARRAY_SIZE(subplatform_dg2_d_ids)))
		mask |= BIT(INTEL_SUBPLATFORM_D);

	GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_MASK);

	RUNTIME_INFO(i915)->platform_mask[pi] |= mask;
}

static void ip_ver_read(struct drm_i915_private *i915, u32 offset, struct intel_ip_version *ip)
{
	struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
	void __iomem *addr;
	u32 val;
	u8 expected_ver = ip->ver;
	u8 expected_rel = ip->rel;

	addr = pci_iomap_range(pdev, 0, offset, sizeof(u32));
	if (drm_WARN_ON(&i915->drm, !addr))
		return;

	val = ioread32(addr);
	pci_iounmap(pdev, addr);

	ip->ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val);
	ip->rel = REG_FIELD_GET(GMD_ID_RELEASE_MASK, val);
	ip->step = REG_FIELD_GET(GMD_ID_STEP, val);

	/* Sanity check against expected versions from device info */
	if (IP_VER(ip->ver, ip->rel) < IP_VER(expected_ver, expected_rel))
		drm_dbg(&i915->drm,
			"Hardware reports GMD IP version %u.%u (REG[0x%x] = 0x%08x) but minimum expected is %u.%u\n",
			ip->ver, ip->rel, offset, val, expected_ver, expected_rel);
}

/*
 * Setup the graphics version for the current device.  This must be done before
 * any code that performs checks on GRAPHICS_VER or DISPLAY_VER, so this
 * function should be called very early in the driver initialization sequence.
 *
 * Regular MMIO access is not yet setup at the point this function is called so
 * we peek at the appropriate MMIO offset directly.  The GMD_ID register is
 * part of an 'always on' power well by design, so we don't need to worry about
 * forcewake while reading it.
 */
static void intel_ipver_early_init(struct drm_i915_private *i915)
{
	struct intel_runtime_info *runtime = RUNTIME_INFO(i915);

	if (!HAS_GMD_ID(i915)) {
		drm_WARN_ON(&i915->drm, RUNTIME_INFO(i915)->graphics.ip.ver > 12);
		/*
		 * On older platforms, graphics and media share the same ip
		 * version and release.
		 */
		RUNTIME_INFO(i915)->media.ip =
			RUNTIME_INFO(i915)->graphics.ip;
		return;
	}

	ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_GRAPHICS),
		    &runtime->graphics.ip);
	/* Wa_22012778468 */
	if (runtime->graphics.ip.ver == 0x0 &&
	    INTEL_INFO(i915)->platform == INTEL_METEORLAKE) {
		RUNTIME_INFO(i915)->graphics.ip.ver = 12;
		RUNTIME_INFO(i915)->graphics.ip.rel = 70;
	}
	ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_MEDIA),
		    &runtime->media.ip);
}

/**
 * intel_device_info_runtime_init_early - initialize early runtime info
 * @i915: the i915 device
 *
 * Determine early intel_device_info fields at runtime. This function needs
 * to be called before the MMIO has been setup.
 */
void intel_device_info_runtime_init_early(struct drm_i915_private *i915)
{
	intel_ipver_early_init(i915);
	intel_device_info_subplatform_init(i915);
}

/**
 * intel_device_info_runtime_init - initialize runtime info
 * @dev_priv: the i915 device
 *
 * Determine various intel_device_info fields at runtime.
 *
 * Use it when either:
 *   - it's judged too laborious to fill n static structures with the limit
 *     when a simple if statement does the job,
 *   - run-time checks (eg read fuse/strap registers) are needed.
 *
 * This function needs to be called:
 *   - after the MMIO has been setup as we are reading registers,
 *   - after the PCH has been detected,
 *   - before the first usage of the fields it can tweak.
 */
void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
{
	struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv);

	BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES);

	if (GRAPHICS_VER(dev_priv) == 6 && i915_vtd_active(dev_priv)) {
		drm_info(&dev_priv->drm,
			 "Disabling ppGTT for VT-d support\n");
		runtime->ppgtt_type = INTEL_PPGTT_NONE;
	}
}

/*
 * Set up device info and initial runtime info at driver create.
 *
 * Note: i915 is only an allocated blob of memory at this point.
 */
void intel_device_info_driver_create(struct drm_i915_private *i915,
				     u16 device_id,
				     const struct intel_device_info *match_info)
{
	struct intel_runtime_info *runtime;

	/* Setup INTEL_INFO() */
	i915->__info = match_info;

	/* Initialize initial runtime info from static const data and pdev. */
	runtime = RUNTIME_INFO(i915);
	memcpy(runtime, &INTEL_INFO(i915)->__runtime, sizeof(*runtime));

	runtime->device_id = device_id;
}

void intel_driver_caps_print(const struct intel_driver_caps *caps,
			     struct drm_printer *p)
{
	drm_printf(p, "Has logical contexts? %s\n",
		   str_yes_no(caps->has_logical_contexts));
	drm_printf(p, "scheduler: 0x%x\n", caps->scheduler);
}
Commit	Line	Data
94b4f3ba CW	1	/*
	2	* Copyright © 2016 Intel Corporation
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
	21	* IN THE SOFTWARE.
	22	*
	23	*/
	24
01fabda8 LDM	25	#include <linux/string_helpers.h>
01fabda8 LDM	26
a8c9b849	27	#include <drm/drm_print.h>
f719c2a2	28	#include <drm/intel/pciids.h>
a8c9b849	29
c2c70752	30	#include "gt/intel_gt_regs.h"
94b4f3ba	31	#include "i915_drv.h"
801543b2	32	#include "i915_reg.h"
a7f46d5b	33	#include "i915_utils.h"
801543b2	34	#include "intel_device_info.h"
94b4f3ba	35
2e0d26f8 JN	36	#define PLATFORM_NAME(x) [INTEL_##x] = #x
	37	static const char * const platform_names[] = {
	38	PLATFORM_NAME(I830),
	39	PLATFORM_NAME(I845G),
	40	PLATFORM_NAME(I85X),
	41	PLATFORM_NAME(I865G),
	42	PLATFORM_NAME(I915G),
	43	PLATFORM_NAME(I915GM),
	44	PLATFORM_NAME(I945G),
	45	PLATFORM_NAME(I945GM),
	46	PLATFORM_NAME(G33),
	47	PLATFORM_NAME(PINEVIEW),
c0f86832 JN	48	PLATFORM_NAME(I965G),
c0f86832 JN	49	PLATFORM_NAME(I965GM),
f69c11ae JN	50	PLATFORM_NAME(G45),
f69c11ae JN	51	PLATFORM_NAME(GM45),
2e0d26f8 JN	52	PLATFORM_NAME(IRONLAKE),
	53	PLATFORM_NAME(SANDYBRIDGE),
	54	PLATFORM_NAME(IVYBRIDGE),
	55	PLATFORM_NAME(VALLEYVIEW),
	56	PLATFORM_NAME(HASWELL),
	57	PLATFORM_NAME(BROADWELL),
	58	PLATFORM_NAME(CHERRYVIEW),
	59	PLATFORM_NAME(SKYLAKE),
	60	PLATFORM_NAME(BROXTON),
	61	PLATFORM_NAME(KABYLAKE),
	62	PLATFORM_NAME(GEMINILAKE),
71851fa8	63	PLATFORM_NAME(COFFEELAKE),
5f4ae270	64	PLATFORM_NAME(COMETLAKE),
41231001	65	PLATFORM_NAME(ICELAKE),
897f2961	66	PLATFORM_NAME(ELKHARTLAKE),
24ea098b	67	PLATFORM_NAME(JASPERLAKE),
abd3a0fe	68	PLATFORM_NAME(TIGERLAKE),
123f62de	69	PLATFORM_NAME(ROCKETLAKE),
05e26584	70	PLATFORM_NAME(DG1),
0883d63b	71	PLATFORM_NAME(ALDERLAKE_S),
bdd27cad	72	PLATFORM_NAME(ALDERLAKE_P),
9e22cfc5	73	PLATFORM_NAME(DG2),
bcf9b296	74	PLATFORM_NAME(METEORLAKE),
2e0d26f8 JN	75	};
	76	#undef PLATFORM_NAME
	77
	78	const char *intel_platform_name(enum intel_platform platform)
	79	{
9160095c JN	80	BUILD_BUG_ON(ARRAY_SIZE(platform_names) != INTEL_MAX_PLATFORMS);
9160095c JN	81
2e0d26f8 JN	82	if (WARN_ON_ONCE(platform >= ARRAY_SIZE(platform_names) \|\|
	83	platform_names[platform] == NULL))
	84	return "<unknown>";
	85
	86	return platform_names[platform];
	87	}
	88
c7d3c844 JN	89	void intel_device_info_print(const struct intel_device_info *info,
	90	const struct intel_runtime_info *runtime,
	91	struct drm_printer *p)
72404978	92	{
f9e932a8 RS	93	if (runtime->graphics.ip.rel)
	94	drm_printf(p, "graphics version: %u.%02u\n",
	95	runtime->graphics.ip.ver,
	96	runtime->graphics.ip.rel);
ca6374e2	97	else
f9e932a8 RS	98	drm_printf(p, "graphics version: %u\n",
f9e932a8 RS	99	runtime->graphics.ip.ver);
ca6374e2	100
f9e932a8 RS	101	if (runtime->media.ip.rel)
	102	drm_printf(p, "media version: %u.%02u\n",
	103	runtime->media.ip.ver,
	104	runtime->media.ip.rel);
ca6374e2	105	else
f9e932a8 RS	106	drm_printf(p, "media version: %u\n",
f9e932a8 RS	107	runtime->media.ip.ver);
ca6374e2	108
3cd7cb2a VS	109	drm_printf(p, "graphics stepping: %s\n", intel_step_name(runtime->step.graphics_step));
3cd7cb2a VS	110	drm_printf(p, "media stepping: %s\n", intel_step_name(runtime->step.media_step));
3cd7cb2a	111
72404978	112	drm_printf(p, "gt: %d\n", info->gt);
8776711e	113	drm_printf(p, "memory-regions: 0x%x\n", info->memory_regions);
2cfd1b38	114	drm_printf(p, "page-sizes: 0x%x\n", runtime->page_sizes);
72404978	115	drm_printf(p, "platform: %s\n", intel_platform_name(info->platform));
268c67e5 JN	116	drm_printf(p, "ppgtt-size: %d\n", runtime->ppgtt_size);
268c67e5 JN	117	drm_printf(p, "ppgtt-type: %d\n", runtime->ppgtt_type);
31a02eb7	118	drm_printf(p, "dma_mask_size: %u\n", info->dma_mask_size);
72404978	119
01fabda8	120	#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, str_yes_no(info->name))
a8c9b849 MW	121	DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
a8c9b849 MW	122	#undef PRINT_FLAG
d53db442	123
39a445bb	124	drm_printf(p, "has_pooled_eu: %s\n", str_yes_no(runtime->has_pooled_eu));
dab91783 LL	125	}
dab91783 LL	126
3c7bbd4c	127	#define ID(id) (id)
805446c8 TU	128
805446c8 TU	129	static const u16 subplatform_ult_ids[] = {
3c7bbd4c JN	130	INTEL_HSW_ULT_GT1_IDS(ID),
	131	INTEL_HSW_ULT_GT2_IDS(ID),
	132	INTEL_HSW_ULT_GT3_IDS(ID),
	133	INTEL_BDW_ULT_GT1_IDS(ID),
	134	INTEL_BDW_ULT_GT2_IDS(ID),
	135	INTEL_BDW_ULT_GT3_IDS(ID),
	136	INTEL_BDW_ULT_RSVD_IDS(ID),
	137	INTEL_SKL_ULT_GT1_IDS(ID),
	138	INTEL_SKL_ULT_GT2_IDS(ID),
	139	INTEL_SKL_ULT_GT3_IDS(ID),
	140	INTEL_KBL_ULT_GT1_IDS(ID),
	141	INTEL_KBL_ULT_GT2_IDS(ID),
	142	INTEL_KBL_ULT_GT3_IDS(ID),
	143	INTEL_CFL_U_GT2_IDS(ID),
	144	INTEL_CFL_U_GT3_IDS(ID),
	145	INTEL_WHL_U_GT1_IDS(ID),
	146	INTEL_WHL_U_GT2_IDS(ID),
	147	INTEL_WHL_U_GT3_IDS(ID),
	148	INTEL_CML_U_GT1_IDS(ID),
	149	INTEL_CML_U_GT2_IDS(ID),
805446c8 TU	150	};
	151
	152	static const u16 subplatform_ulx_ids[] = {
3c7bbd4c JN	153	INTEL_HSW_ULX_GT1_IDS(ID),
	154	INTEL_HSW_ULX_GT2_IDS(ID),
	155	INTEL_BDW_ULX_GT1_IDS(ID),
	156	INTEL_BDW_ULX_GT2_IDS(ID),
	157	INTEL_BDW_ULX_GT3_IDS(ID),
	158	INTEL_BDW_ULX_RSVD_IDS(ID),
	159	INTEL_SKL_ULX_GT1_IDS(ID),
	160	INTEL_SKL_ULX_GT2_IDS(ID),
	161	INTEL_KBL_ULX_GT1_IDS(ID),
	162	INTEL_KBL_ULX_GT2_IDS(ID),
	163	INTEL_AML_KBL_GT2_IDS(ID),
	164	INTEL_AML_CFL_GT2_IDS(ID),
805446c8 TU	165	};
	166
	167	static const u16 subplatform_portf_ids[] = {
3c7bbd4c	168	INTEL_ICL_PORT_F_IDS(ID),
805446c8 TU	169	};
805446c8 TU	170
b9ef8939	171	static const u16 subplatform_uy_ids[] = {
3c7bbd4c	172	INTEL_TGL_GT2_IDS(ID),
b9ef8939 JRS	173	};
b9ef8939 JRS	174
7e28d0b2	175	static const u16 subplatform_n_ids[] = {
3c7bbd4c	176	INTEL_ADLN_IDS(ID),
7e28d0b2 TU	177	};
7e28d0b2 TU	178
72c3c8d6	179	static const u16 subplatform_rpl_ids[] = {
3c7bbd4c JN	180	INTEL_RPLS_IDS(ID),
	181	INTEL_RPLU_IDS(ID),
	182	INTEL_RPLP_IDS(ID),
52407c22 AS	183	};
52407c22 AS	184
61b795a9	185	static const u16 subplatform_rplu_ids[] = {
3c7bbd4c	186	INTEL_RPLU_IDS(ID),
61b795a9 CKB	187	};
61b795a9 CKB	188
1bc4ae0c	189	static const u16 subplatform_g10_ids[] = {
3c7bbd4c JN	190	INTEL_DG2_G10_IDS(ID),
3c7bbd4c JN	191	INTEL_ATS_M150_IDS(ID),
1bc4ae0c MR	192	};
	193
	194	static const u16 subplatform_g11_ids[] = {
3c7bbd4c JN	195	INTEL_DG2_G11_IDS(ID),
3c7bbd4c JN	196	INTEL_ATS_M75_IDS(ID),
1bc4ae0c MR	197	};
	198
	199	static const u16 subplatform_g12_ids[] = {
3c7bbd4c	200	INTEL_DG2_G12_IDS(ID),
52407c22 AS	201	};
52407c22 AS	202
f9a15b96 RJ	203	static const u16 subplatform_dg2_d_ids[] = {
	204	INTEL_DG2_D_IDS(ID),
	205	};
	206
3c1d5ced DCS	207	static const u16 subplatform_arl_h_ids[] = {
	208	INTEL_ARL_H_IDS(ID),
	209	};
	210
	211	static const u16 subplatform_arl_u_ids[] = {
	212	INTEL_ARL_U_IDS(ID),
	213	};
	214
	215	static const u16 subplatform_arl_s_ids[] = {
	216	INTEL_ARL_S_IDS(ID),
67733d7a JH	217	};
67733d7a JH	218
805446c8 TU	219	static bool find_devid(u16 id, const u16 *p, unsigned int num)
	220	{
	221	for (; num; num--, p++) {
	222	if (*p == id)
	223	return true;
	224	}
	225
	226	return false;
	227	}
	228
c2c70752	229	static void intel_device_info_subplatform_init(struct drm_i915_private *i915)
805446c8 TU	230	{
	231	const struct intel_device_info *info = INTEL_INFO(i915);
	232	const struct intel_runtime_info *rinfo = RUNTIME_INFO(i915);
	233	const unsigned int pi = __platform_mask_index(rinfo, info->platform);
	234	const unsigned int pb = __platform_mask_bit(rinfo, info->platform);
	235	u16 devid = INTEL_DEVID(i915);
640cde65	236	u32 mask = 0;
805446c8 TU	237
	238	/* Make sure IS_<platform> checks are working. */
	239	RUNTIME_INFO(i915)->platform_mask[pi] = BIT(pb);
	240
	241	/* Find and mark subplatform bits based on the PCI device id. */
	242	if (find_devid(devid, subplatform_ult_ids,
	243	ARRAY_SIZE(subplatform_ult_ids))) {
	244	mask = BIT(INTEL_SUBPLATFORM_ULT);
	245	} else if (find_devid(devid, subplatform_ulx_ids,
	246	ARRAY_SIZE(subplatform_ulx_ids))) {
	247	mask = BIT(INTEL_SUBPLATFORM_ULX);
	248	if (IS_HASWELL(i915) \|\| IS_BROADWELL(i915)) {
	249	/* ULX machines are also considered ULT. */
	250	mask \|= BIT(INTEL_SUBPLATFORM_ULT);
	251	}
805446c8 TU	252	} else if (find_devid(devid, subplatform_portf_ids,
	253	ARRAY_SIZE(subplatform_portf_ids))) {
	254	mask = BIT(INTEL_SUBPLATFORM_PORTF);
b9ef8939 JRS	255	} else if (find_devid(devid, subplatform_uy_ids,
	256	ARRAY_SIZE(subplatform_uy_ids))) {
	257	mask = BIT(INTEL_SUBPLATFORM_UY);
7e28d0b2 TU	258	} else if (find_devid(devid, subplatform_n_ids,
	259	ARRAY_SIZE(subplatform_n_ids))) {
	260	mask = BIT(INTEL_SUBPLATFORM_N);
72c3c8d6 MA	261	} else if (find_devid(devid, subplatform_rpl_ids,
	262	ARRAY_SIZE(subplatform_rpl_ids))) {
	263	mask = BIT(INTEL_SUBPLATFORM_RPL);
61b795a9 CKB	264	if (find_devid(devid, subplatform_rplu_ids,
	265	ARRAY_SIZE(subplatform_rplu_ids)))
	266	mask \|= BIT(INTEL_SUBPLATFORM_RPLU);
1bc4ae0c MR	267	} else if (find_devid(devid, subplatform_g10_ids,
	268	ARRAY_SIZE(subplatform_g10_ids))) {
	269	mask = BIT(INTEL_SUBPLATFORM_G10);
	270	} else if (find_devid(devid, subplatform_g11_ids,
	271	ARRAY_SIZE(subplatform_g11_ids))) {
	272	mask = BIT(INTEL_SUBPLATFORM_G11);
	273	} else if (find_devid(devid, subplatform_g12_ids,
	274	ARRAY_SIZE(subplatform_g12_ids))) {
	275	mask = BIT(INTEL_SUBPLATFORM_G12);
3c1d5ced DCS	276	} else if (find_devid(devid, subplatform_arl_h_ids,
	277	ARRAY_SIZE(subplatform_arl_h_ids))) {
	278	mask = BIT(INTEL_SUBPLATFORM_ARL_H);
	279	} else if (find_devid(devid, subplatform_arl_u_ids,
	280	ARRAY_SIZE(subplatform_arl_u_ids))) {
	281	mask = BIT(INTEL_SUBPLATFORM_ARL_U);
	282	} else if (find_devid(devid, subplatform_arl_s_ids,
	283	ARRAY_SIZE(subplatform_arl_s_ids))) {
	284	mask = BIT(INTEL_SUBPLATFORM_ARL_S);
805446c8 TU	285	}
805446c8 TU	286
f9a15b96 RJ	287	/* DG2_D ids span across multiple DG2 subplatforms */
	288	if (find_devid(devid, subplatform_dg2_d_ids,
	289	ARRAY_SIZE(subplatform_dg2_d_ids)))
	290	mask \|= BIT(INTEL_SUBPLATFORM_D);
	291
56afa701	292	GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_MASK);
805446c8 TU	293
	294	RUNTIME_INFO(i915)->platform_mask[pi] \|= mask;
	295	}
	296
ef7e222c	297	static void ip_ver_read(struct drm_i915_private i915, u32 offset, struct intel_ip_version ip)
c2c70752 MR	298	{
	299	struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
	300	void __iomem *addr;
	301	u32 val;
	302	u8 expected_ver = ip->ver;
	303	u8 expected_rel = ip->rel;
	304
	305	addr = pci_iomap_range(pdev, 0, offset, sizeof(u32));
	306	if (drm_WARN_ON(&i915->drm, !addr))
	307	return;
	308
	309	val = ioread32(addr);
	310	pci_iounmap(pdev, addr);
	311
	312	ip->ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val);
	313	ip->rel = REG_FIELD_GET(GMD_ID_RELEASE_MASK, val);
	314	ip->step = REG_FIELD_GET(GMD_ID_STEP, val);
	315
	316	/* Sanity check against expected versions from device info */
	317	if (IP_VER(ip->ver, ip->rel) < IP_VER(expected_ver, expected_rel))
	318	drm_dbg(&i915->drm,
	319	"Hardware reports GMD IP version %u.%u (REG[0x%x] = 0x%08x) but minimum expected is %u.%u\n",
	320	ip->ver, ip->rel, offset, val, expected_ver, expected_rel);
	321	}
	322
	323	/*
	324	* Setup the graphics version for the current device. This must be done before
	325	* any code that performs checks on GRAPHICS_VER or DISPLAY_VER, so this
	326	* function should be called very early in the driver initialization sequence.
	327	*
	328	* Regular MMIO access is not yet setup at the point this function is called so
	329	* we peek at the appropriate MMIO offset directly. The GMD_ID register is
	330	* part of an 'always on' power well by design, so we don't need to worry about
	331	* forcewake while reading it.
	332	*/
	333	static void intel_ipver_early_init(struct drm_i915_private *i915)
	334	{
	335	struct intel_runtime_info *runtime = RUNTIME_INFO(i915);
	336
80c1fb2e RS	337	if (!HAS_GMD_ID(i915)) {
	338	drm_WARN_ON(&i915->drm, RUNTIME_INFO(i915)->graphics.ip.ver > 12);
	339	/*
	340	* On older platforms, graphics and media share the same ip
	341	* version and release.
	342	*/
	343	RUNTIME_INFO(i915)->media.ip =
	344	RUNTIME_INFO(i915)->graphics.ip;
c2c70752	345	return;
80c1fb2e	346	}
c2c70752 MR	347
	348	ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_GRAPHICS),
	349	&runtime->graphics.ip);
41bb543f MR	350	/* Wa_22012778468 */
	351	if (runtime->graphics.ip.ver == 0x0 &&
	352	INTEL_INFO(i915)->platform == INTEL_METEORLAKE) {
	353	RUNTIME_INFO(i915)->graphics.ip.ver = 12;
	354	RUNTIME_INFO(i915)->graphics.ip.rel = 70;
	355	}
c2c70752 MR	356	ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_MEDIA),
	357	&runtime->media.ip);
	358	}
	359
	360	/**
	361	* intel_device_info_runtime_init_early - initialize early runtime info
	362	* @i915: the i915 device
	363	*
	364	* Determine early intel_device_info fields at runtime. This function needs
	365	* to be called before the MMIO has been setup.
	366	*/
	367	void intel_device_info_runtime_init_early(struct drm_i915_private *i915)
	368	{
	369	intel_ipver_early_init(i915);
	370	intel_device_info_subplatform_init(i915);
	371	}
	372
6a7e51f3 MW	373	/**
6a7e51f3 MW	374	* intel_device_info_runtime_init - initialize runtime info
963cc126	375	* @dev_priv: the i915 device
6a7e51f3	376	*
94b4f3ba CW	377	* Determine various intel_device_info fields at runtime.
	378	*
	379	* Use it when either:
	380	* - it's judged too laborious to fill n static structures with the limit
	381	* when a simple if statement does the job,
	382	* - run-time checks (eg read fuse/strap registers) are needed.
	383	*
	384	* This function needs to be called:
	385	* - after the MMIO has been setup as we are reading registers,
	386	* - after the PCH has been detected,
	387	* - before the first usage of the fields it can tweak.
	388	*/
1400cc7e	389	void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
94b4f3ba	390	{
0258404f	391	struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv);
022d3093	392
2d0cdf60	393	BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES);
94b4f3ba	394
a7f46d5b	395	if (GRAPHICS_VER(dev_priv) == 6 && i915_vtd_active(dev_priv)) {
68b32717 WK	396	drm_info(&dev_priv->drm,
68b32717 WK	397	"Disabling ppGTT for VT-d support\n");
268c67e5	398	runtime->ppgtt_type = INTEL_PPGTT_NONE;
4bdafb9d	399	}
94b4f3ba	400	}
3fed1808	401
446a20c9 JN	402	/*
	403	* Set up device info and initial runtime info at driver create.
	404	*
	405	* Note: i915 is only an allocated blob of memory at this point.
	406	*/
	407	void intel_device_info_driver_create(struct drm_i915_private *i915,
	408	u16 device_id,
	409	const struct intel_device_info *match_info)
	410	{
446a20c9 JN	411	struct intel_runtime_info *runtime;
446a20c9 JN	412
0c4f52ba JN	413	/* Setup INTEL_INFO() */
0c4f52ba JN	414	i915->__info = match_info;
446a20c9 JN	415
	416	/* Initialize initial runtime info from static const data and pdev. */
	417	runtime = RUNTIME_INFO(i915);
	418	memcpy(runtime, &INTEL_INFO(i915)->__runtime, sizeof(*runtime));
69d43981	419
446a20c9 JN	420	runtime->device_id = device_id;
	421	}
	422
3fed1808 CW	423	void intel_driver_caps_print(const struct intel_driver_caps *caps,
	424	struct drm_printer *p)
	425	{
481827b4	426	drm_printf(p, "Has logical contexts? %s\n",
01fabda8	427	str_yes_no(caps->has_logical_contexts));
2cfd1b38	428	drm_printf(p, "scheduler: 0x%x\n", caps->scheduler);
3fed1808	429	}