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94b4f3ba CW |
1 | /* |
2 | * Copyright © 2016 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | ||
01fabda8 LDM |
25 | #include <linux/string_helpers.h> |
26 | ||
a8c9b849 | 27 | #include <drm/drm_print.h> |
83d2bdb6 | 28 | #include <drm/i915_pciids.h> |
a8c9b849 | 29 | |
b04002f4 | 30 | #include "display/intel_cdclk.h" |
fdeb6d02 | 31 | #include "display/intel_de.h" |
b978520d | 32 | #include "intel_device_info.h" |
94b4f3ba | 33 | #include "i915_drv.h" |
a7f46d5b | 34 | #include "i915_utils.h" |
94b4f3ba | 35 | |
2e0d26f8 JN |
36 | #define PLATFORM_NAME(x) [INTEL_##x] = #x |
37 | static const char * const platform_names[] = { | |
38 | PLATFORM_NAME(I830), | |
39 | PLATFORM_NAME(I845G), | |
40 | PLATFORM_NAME(I85X), | |
41 | PLATFORM_NAME(I865G), | |
42 | PLATFORM_NAME(I915G), | |
43 | PLATFORM_NAME(I915GM), | |
44 | PLATFORM_NAME(I945G), | |
45 | PLATFORM_NAME(I945GM), | |
46 | PLATFORM_NAME(G33), | |
47 | PLATFORM_NAME(PINEVIEW), | |
c0f86832 JN |
48 | PLATFORM_NAME(I965G), |
49 | PLATFORM_NAME(I965GM), | |
f69c11ae JN |
50 | PLATFORM_NAME(G45), |
51 | PLATFORM_NAME(GM45), | |
2e0d26f8 JN |
52 | PLATFORM_NAME(IRONLAKE), |
53 | PLATFORM_NAME(SANDYBRIDGE), | |
54 | PLATFORM_NAME(IVYBRIDGE), | |
55 | PLATFORM_NAME(VALLEYVIEW), | |
56 | PLATFORM_NAME(HASWELL), | |
57 | PLATFORM_NAME(BROADWELL), | |
58 | PLATFORM_NAME(CHERRYVIEW), | |
59 | PLATFORM_NAME(SKYLAKE), | |
60 | PLATFORM_NAME(BROXTON), | |
61 | PLATFORM_NAME(KABYLAKE), | |
62 | PLATFORM_NAME(GEMINILAKE), | |
71851fa8 | 63 | PLATFORM_NAME(COFFEELAKE), |
5f4ae270 | 64 | PLATFORM_NAME(COMETLAKE), |
41231001 | 65 | PLATFORM_NAME(ICELAKE), |
897f2961 | 66 | PLATFORM_NAME(ELKHARTLAKE), |
24ea098b | 67 | PLATFORM_NAME(JASPERLAKE), |
abd3a0fe | 68 | PLATFORM_NAME(TIGERLAKE), |
123f62de | 69 | PLATFORM_NAME(ROCKETLAKE), |
05e26584 | 70 | PLATFORM_NAME(DG1), |
0883d63b | 71 | PLATFORM_NAME(ALDERLAKE_S), |
bdd27cad | 72 | PLATFORM_NAME(ALDERLAKE_P), |
086df54e | 73 | PLATFORM_NAME(XEHPSDV), |
9e22cfc5 | 74 | PLATFORM_NAME(DG2), |
2e0d26f8 JN |
75 | }; |
76 | #undef PLATFORM_NAME | |
77 | ||
78 | const char *intel_platform_name(enum intel_platform platform) | |
79 | { | |
9160095c JN |
80 | BUILD_BUG_ON(ARRAY_SIZE(platform_names) != INTEL_MAX_PLATFORMS); |
81 | ||
2e0d26f8 JN |
82 | if (WARN_ON_ONCE(platform >= ARRAY_SIZE(platform_names) || |
83 | platform_names[platform] == NULL)) | |
84 | return "<unknown>"; | |
85 | ||
86 | return platform_names[platform]; | |
87 | } | |
88 | ||
72404978 CW |
89 | void intel_device_info_print_static(const struct intel_device_info *info, |
90 | struct drm_printer *p) | |
91 | { | |
a5b7ef27 JRS |
92 | if (info->graphics.rel) |
93 | drm_printf(p, "graphics version: %u.%02u\n", info->graphics.ver, | |
94 | info->graphics.rel); | |
ca6374e2 | 95 | else |
a5b7ef27 | 96 | drm_printf(p, "graphics version: %u\n", info->graphics.ver); |
ca6374e2 | 97 | |
a5b7ef27 JRS |
98 | if (info->media.rel) |
99 | drm_printf(p, "media version: %u.%02u\n", info->media.ver, info->media.rel); | |
ca6374e2 | 100 | else |
a5b7ef27 | 101 | drm_printf(p, "media version: %u\n", info->media.ver); |
ca6374e2 | 102 | |
a5b7ef27 JRS |
103 | if (info->display.rel) |
104 | drm_printf(p, "display version: %u.%02u\n", info->display.ver, info->display.rel); | |
ca6374e2 | 105 | else |
a5b7ef27 | 106 | drm_printf(p, "display version: %u\n", info->display.ver); |
ca6374e2 | 107 | |
72404978 | 108 | drm_printf(p, "gt: %d\n", info->gt); |
72404978 CW |
109 | drm_printf(p, "memory-regions: %x\n", info->memory_regions); |
110 | drm_printf(p, "page-sizes: %x\n", info->page_sizes); | |
111 | drm_printf(p, "platform: %s\n", intel_platform_name(info->platform)); | |
112 | drm_printf(p, "ppgtt-size: %d\n", info->ppgtt_size); | |
113 | drm_printf(p, "ppgtt-type: %d\n", info->ppgtt_type); | |
31a02eb7 | 114 | drm_printf(p, "dma_mask_size: %u\n", info->dma_mask_size); |
72404978 | 115 | |
01fabda8 | 116 | #define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, str_yes_no(info->name)) |
a8c9b849 MW |
117 | DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG); |
118 | #undef PRINT_FLAG | |
d53db442 | 119 | |
01fabda8 | 120 | #define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, str_yes_no(info->display.name)) |
d53db442 JRS |
121 | DEV_INFO_DISPLAY_FOR_EACH_FLAG(PRINT_FLAG); |
122 | #undef PRINT_FLAG | |
a8c9b849 MW |
123 | } |
124 | ||
72404978 CW |
125 | void intel_device_info_print_runtime(const struct intel_runtime_info *info, |
126 | struct drm_printer *p) | |
5fbbe8d4 | 127 | { |
b04002f4 | 128 | drm_printf(p, "rawclk rate: %u kHz\n", info->rawclk_freq); |
dab91783 LL |
129 | } |
130 | ||
805446c8 TU |
131 | #undef INTEL_VGA_DEVICE |
132 | #define INTEL_VGA_DEVICE(id, info) (id) | |
133 | ||
134 | static const u16 subplatform_ult_ids[] = { | |
135 | INTEL_HSW_ULT_GT1_IDS(0), | |
136 | INTEL_HSW_ULT_GT2_IDS(0), | |
137 | INTEL_HSW_ULT_GT3_IDS(0), | |
138 | INTEL_BDW_ULT_GT1_IDS(0), | |
139 | INTEL_BDW_ULT_GT2_IDS(0), | |
140 | INTEL_BDW_ULT_GT3_IDS(0), | |
141 | INTEL_BDW_ULT_RSVD_IDS(0), | |
142 | INTEL_SKL_ULT_GT1_IDS(0), | |
143 | INTEL_SKL_ULT_GT2_IDS(0), | |
144 | INTEL_SKL_ULT_GT3_IDS(0), | |
145 | INTEL_KBL_ULT_GT1_IDS(0), | |
146 | INTEL_KBL_ULT_GT2_IDS(0), | |
147 | INTEL_KBL_ULT_GT3_IDS(0), | |
148 | INTEL_CFL_U_GT2_IDS(0), | |
149 | INTEL_CFL_U_GT3_IDS(0), | |
150 | INTEL_WHL_U_GT1_IDS(0), | |
151 | INTEL_WHL_U_GT2_IDS(0), | |
c3ad8d29 | 152 | INTEL_WHL_U_GT3_IDS(0), |
8717c6b7 LS |
153 | INTEL_CML_U_GT1_IDS(0), |
154 | INTEL_CML_U_GT2_IDS(0), | |
805446c8 TU |
155 | }; |
156 | ||
157 | static const u16 subplatform_ulx_ids[] = { | |
158 | INTEL_HSW_ULX_GT1_IDS(0), | |
159 | INTEL_HSW_ULX_GT2_IDS(0), | |
160 | INTEL_BDW_ULX_GT1_IDS(0), | |
161 | INTEL_BDW_ULX_GT2_IDS(0), | |
162 | INTEL_BDW_ULX_GT3_IDS(0), | |
163 | INTEL_BDW_ULX_RSVD_IDS(0), | |
164 | INTEL_SKL_ULX_GT1_IDS(0), | |
165 | INTEL_SKL_ULX_GT2_IDS(0), | |
166 | INTEL_KBL_ULX_GT1_IDS(0), | |
c3ad8d29 | 167 | INTEL_KBL_ULX_GT2_IDS(0), |
805446c8 | 168 | INTEL_AML_KBL_GT2_IDS(0), |
c3ad8d29 | 169 | INTEL_AML_CFL_GT2_IDS(0), |
805446c8 TU |
170 | }; |
171 | ||
172 | static const u16 subplatform_portf_ids[] = { | |
c3ad8d29 | 173 | INTEL_ICL_PORT_F_IDS(0), |
805446c8 TU |
174 | }; |
175 | ||
b9ef8939 JRS |
176 | static const u16 subplatform_uy_ids[] = { |
177 | INTEL_TGL_12_GT2_IDS(0), | |
178 | }; | |
179 | ||
7e28d0b2 TU |
180 | static const u16 subplatform_n_ids[] = { |
181 | INTEL_ADLN_IDS(0), | |
182 | }; | |
183 | ||
72c3c8d6 | 184 | static const u16 subplatform_rpl_ids[] = { |
52407c22 | 185 | INTEL_RPLS_IDS(0), |
72c3c8d6 | 186 | INTEL_RPLP_IDS(0), |
52407c22 AS |
187 | }; |
188 | ||
805446c8 TU |
189 | static bool find_devid(u16 id, const u16 *p, unsigned int num) |
190 | { | |
191 | for (; num; num--, p++) { | |
192 | if (*p == id) | |
193 | return true; | |
194 | } | |
195 | ||
196 | return false; | |
197 | } | |
198 | ||
199 | void intel_device_info_subplatform_init(struct drm_i915_private *i915) | |
200 | { | |
201 | const struct intel_device_info *info = INTEL_INFO(i915); | |
202 | const struct intel_runtime_info *rinfo = RUNTIME_INFO(i915); | |
203 | const unsigned int pi = __platform_mask_index(rinfo, info->platform); | |
204 | const unsigned int pb = __platform_mask_bit(rinfo, info->platform); | |
205 | u16 devid = INTEL_DEVID(i915); | |
640cde65 | 206 | u32 mask = 0; |
805446c8 TU |
207 | |
208 | /* Make sure IS_<platform> checks are working. */ | |
209 | RUNTIME_INFO(i915)->platform_mask[pi] = BIT(pb); | |
210 | ||
211 | /* Find and mark subplatform bits based on the PCI device id. */ | |
212 | if (find_devid(devid, subplatform_ult_ids, | |
213 | ARRAY_SIZE(subplatform_ult_ids))) { | |
214 | mask = BIT(INTEL_SUBPLATFORM_ULT); | |
215 | } else if (find_devid(devid, subplatform_ulx_ids, | |
216 | ARRAY_SIZE(subplatform_ulx_ids))) { | |
217 | mask = BIT(INTEL_SUBPLATFORM_ULX); | |
218 | if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { | |
219 | /* ULX machines are also considered ULT. */ | |
220 | mask |= BIT(INTEL_SUBPLATFORM_ULT); | |
221 | } | |
805446c8 TU |
222 | } else if (find_devid(devid, subplatform_portf_ids, |
223 | ARRAY_SIZE(subplatform_portf_ids))) { | |
224 | mask = BIT(INTEL_SUBPLATFORM_PORTF); | |
b9ef8939 JRS |
225 | } else if (find_devid(devid, subplatform_uy_ids, |
226 | ARRAY_SIZE(subplatform_uy_ids))) { | |
227 | mask = BIT(INTEL_SUBPLATFORM_UY); | |
7e28d0b2 TU |
228 | } else if (find_devid(devid, subplatform_n_ids, |
229 | ARRAY_SIZE(subplatform_n_ids))) { | |
230 | mask = BIT(INTEL_SUBPLATFORM_N); | |
72c3c8d6 MA |
231 | } else if (find_devid(devid, subplatform_rpl_ids, |
232 | ARRAY_SIZE(subplatform_rpl_ids))) { | |
233 | mask = BIT(INTEL_SUBPLATFORM_RPL); | |
805446c8 TU |
234 | } |
235 | ||
56afa701 | 236 | GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_MASK); |
805446c8 TU |
237 | |
238 | RUNTIME_INFO(i915)->platform_mask[pi] |= mask; | |
239 | } | |
240 | ||
6a7e51f3 MW |
241 | /** |
242 | * intel_device_info_runtime_init - initialize runtime info | |
963cc126 | 243 | * @dev_priv: the i915 device |
6a7e51f3 | 244 | * |
94b4f3ba CW |
245 | * Determine various intel_device_info fields at runtime. |
246 | * | |
247 | * Use it when either: | |
248 | * - it's judged too laborious to fill n static structures with the limit | |
249 | * when a simple if statement does the job, | |
250 | * - run-time checks (eg read fuse/strap registers) are needed. | |
251 | * | |
252 | * This function needs to be called: | |
253 | * - after the MMIO has been setup as we are reading registers, | |
254 | * - after the PCH has been detected, | |
255 | * - before the first usage of the fields it can tweak. | |
256 | */ | |
1400cc7e | 257 | void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) |
94b4f3ba | 258 | { |
1400cc7e | 259 | struct intel_device_info *info = mkwrite_device_info(dev_priv); |
0258404f | 260 | struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv); |
94b4f3ba CW |
261 | enum pipe pipe; |
262 | ||
8ff36e02 | 263 | /* Wa_14011765242: adl-s A0,A1 */ |
46b0d709 | 264 | if (IS_ADLS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A2)) |
ea27113e AS |
265 | for_each_pipe(dev_priv, pipe) |
266 | runtime->num_scalers[pipe] = 0; | |
4c6b3021 | 267 | else if (DISPLAY_VER(dev_priv) >= 11) { |
6e7406db | 268 | for_each_pipe(dev_priv, pipe) |
0258404f | 269 | runtime->num_scalers[pipe] = 2; |
4c6b3021 | 270 | } else if (DISPLAY_VER(dev_priv) >= 9) { |
0258404f JN |
271 | runtime->num_scalers[PIPE_A] = 2; |
272 | runtime->num_scalers[PIPE_B] = 2; | |
273 | runtime->num_scalers[PIPE_C] = 1; | |
0bf0230e ACO |
274 | } |
275 | ||
8a68d464 | 276 | BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES); |
022d3093 | 277 | |
1649a4cc | 278 | if (DISPLAY_VER(dev_priv) >= 13 || HAS_D12_PLANE_MINIMIZATION(dev_priv)) |
99e2d8bc MR |
279 | for_each_pipe(dev_priv, pipe) |
280 | runtime->num_sprites[pipe] = 4; | |
4c6b3021 | 281 | else if (DISPLAY_VER(dev_priv) >= 11) |
6711bd73 | 282 | for_each_pipe(dev_priv, pipe) |
0258404f | 283 | runtime->num_sprites[pipe] = 6; |
4c6b3021 | 284 | else if (DISPLAY_VER(dev_priv) == 10) |
e9c98825 | 285 | for_each_pipe(dev_priv, pipe) |
0258404f | 286 | runtime->num_sprites[pipe] = 3; |
e9c98825 | 287 | else if (IS_BROXTON(dev_priv)) { |
6711bd73 ML |
288 | /* |
289 | * Skylake and Broxton currently don't expose the topmost plane as its | |
290 | * use is exclusive with the legacy cursor and we only want to expose | |
291 | * one of those, not both. Until we can safely expose the topmost plane | |
292 | * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported, | |
293 | * we don't expose the topmost plane at all to prevent ABI breakage | |
294 | * down the line. | |
295 | */ | |
296 | ||
0258404f JN |
297 | runtime->num_sprites[PIPE_A] = 2; |
298 | runtime->num_sprites[PIPE_B] = 2; | |
299 | runtime->num_sprites[PIPE_C] = 1; | |
33edc24d | 300 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
94b4f3ba | 301 | for_each_pipe(dev_priv, pipe) |
0258404f | 302 | runtime->num_sprites[pipe] = 2; |
4c6b3021 | 303 | } else if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) { |
94b4f3ba | 304 | for_each_pipe(dev_priv, pipe) |
0258404f | 305 | runtime->num_sprites[pipe] = 1; |
33edc24d | 306 | } |
94b4f3ba | 307 | |
651e7d48 | 308 | if (HAS_DISPLAY(dev_priv) && IS_GRAPHICS_VER(dev_priv, 7, 8) && |
ef404bc6 | 309 | HAS_PCH_SPLIT(dev_priv)) { |
fdeb6d02 DCS |
310 | u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP); |
311 | u32 sfuse_strap = intel_de_read(dev_priv, SFUSE_STRAP); | |
94b4f3ba CW |
312 | |
313 | /* | |
314 | * SFUSE_STRAP is supposed to have a bit signalling the display | |
315 | * is fused off. Unfortunately it seems that, at least in | |
316 | * certain cases, fused off display means that PCH display | |
317 | * reads don't land anywhere. In that case, we read 0s. | |
318 | * | |
319 | * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK | |
320 | * should be set when taking over after the firmware. | |
321 | */ | |
322 | if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE || | |
323 | sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED || | |
b9eb89b2 | 324 | (HAS_PCH_CPT(dev_priv) && |
94b4f3ba | 325 | !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) { |
68b32717 WK |
326 | drm_info(&dev_priv->drm, |
327 | "Display fused off, disabling\n"); | |
6678916d VS |
328 | info->display.pipe_mask = 0; |
329 | info->display.cpu_transcoder_mask = 0; | |
b8ca477e | 330 | info->display.fbc_mask = 0; |
94b4f3ba | 331 | } else if (fuse_strap & IVB_PIPE_C_DISABLE) { |
68b32717 | 332 | drm_info(&dev_priv->drm, "PipeC fused off\n"); |
6678916d VS |
333 | info->display.pipe_mask &= ~BIT(PIPE_C); |
334 | info->display.cpu_transcoder_mask &= ~BIT(TRANSCODER_C); | |
94b4f3ba | 335 | } |
4fd17728 | 336 | } else if (HAS_DISPLAY(dev_priv) && DISPLAY_VER(dev_priv) >= 9) { |
fdeb6d02 | 337 | u32 dfsm = intel_de_read(dev_priv, SKL_DFSM); |
94b4f3ba | 338 | |
10cf8e75 | 339 | if (dfsm & SKL_DFSM_PIPE_A_DISABLE) { |
6678916d VS |
340 | info->display.pipe_mask &= ~BIT(PIPE_A); |
341 | info->display.cpu_transcoder_mask &= ~BIT(TRANSCODER_A); | |
b8ca477e | 342 | info->display.fbc_mask &= ~BIT(INTEL_FBC_A); |
10cf8e75 VS |
343 | } |
344 | if (dfsm & SKL_DFSM_PIPE_B_DISABLE) { | |
6678916d VS |
345 | info->display.pipe_mask &= ~BIT(PIPE_B); |
346 | info->display.cpu_transcoder_mask &= ~BIT(TRANSCODER_B); | |
10cf8e75 VS |
347 | } |
348 | if (dfsm & SKL_DFSM_PIPE_C_DISABLE) { | |
6678916d VS |
349 | info->display.pipe_mask &= ~BIT(PIPE_C); |
350 | info->display.cpu_transcoder_mask &= ~BIT(TRANSCODER_C); | |
10cf8e75 | 351 | } |
4fd17728 LDM |
352 | |
353 | if (DISPLAY_VER(dev_priv) >= 12 && | |
10cf8e75 | 354 | (dfsm & TGL_DFSM_PIPE_D_DISABLE)) { |
6678916d VS |
355 | info->display.pipe_mask &= ~BIT(PIPE_D); |
356 | info->display.cpu_transcoder_mask &= ~BIT(TRANSCODER_D); | |
10cf8e75 | 357 | } |
74393109 JRS |
358 | |
359 | if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE) | |
360 | info->display.has_hdcp = 0; | |
7a40aac1 JRS |
361 | |
362 | if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE) | |
b8ca477e | 363 | info->display.fbc_mask = 0; |
ee595888 | 364 | |
4fd17728 | 365 | if (DISPLAY_VER(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE)) |
ec2b1485 | 366 | info->display.has_dmc = 0; |
0f9ed3b2 | 367 | |
4fd17728 | 368 | if (DISPLAY_VER(dev_priv) >= 10 && |
a4d082fc | 369 | (dfsm & GLK_DFSM_DISPLAY_DSC_DISABLE)) |
0f9ed3b2 | 370 | info->display.has_dsc = 0; |
94b4f3ba CW |
371 | } |
372 | ||
a7f46d5b | 373 | if (GRAPHICS_VER(dev_priv) == 6 && i915_vtd_active(dev_priv)) { |
68b32717 WK |
374 | drm_info(&dev_priv->drm, |
375 | "Disabling ppGTT for VT-d support\n"); | |
cbecbcca | 376 | info->ppgtt_type = INTEL_PPGTT_NONE; |
4bdafb9d CW |
377 | } |
378 | ||
b04002f4 CW |
379 | runtime->rawclk_freq = intel_read_rawclk(dev_priv); |
380 | drm_dbg(&dev_priv->drm, "rawclk rate: %d kHz\n", runtime->rawclk_freq); | |
381 | ||
5e0e390d JN |
382 | if (!HAS_DISPLAY(dev_priv)) { |
383 | dev_priv->drm.driver_features &= ~(DRIVER_MODESET | | |
384 | DRIVER_ATOMIC); | |
385 | memset(&info->display, 0, sizeof(info->display)); | |
386 | memset(runtime->num_sprites, 0, sizeof(runtime->num_sprites)); | |
387 | memset(runtime->num_scalers, 0, sizeof(runtime->num_scalers)); | |
388 | } | |
94b4f3ba | 389 | } |
3fed1808 CW |
390 | |
391 | void intel_driver_caps_print(const struct intel_driver_caps *caps, | |
392 | struct drm_printer *p) | |
393 | { | |
481827b4 | 394 | drm_printf(p, "Has logical contexts? %s\n", |
01fabda8 | 395 | str_yes_no(caps->has_logical_contexts)); |
3fed1808 CW |
396 | drm_printf(p, "scheduler: %x\n", caps->scheduler); |
397 | } |