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94b4f3ba CW |
1 | /* |
2 | * Copyright © 2016 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | ||
a8c9b849 MW |
25 | #include <drm/drm_print.h> |
26 | ||
b978520d | 27 | #include "intel_device_info.h" |
94b4f3ba CW |
28 | #include "i915_drv.h" |
29 | ||
2e0d26f8 JN |
30 | #define PLATFORM_NAME(x) [INTEL_##x] = #x |
31 | static const char * const platform_names[] = { | |
32 | PLATFORM_NAME(I830), | |
33 | PLATFORM_NAME(I845G), | |
34 | PLATFORM_NAME(I85X), | |
35 | PLATFORM_NAME(I865G), | |
36 | PLATFORM_NAME(I915G), | |
37 | PLATFORM_NAME(I915GM), | |
38 | PLATFORM_NAME(I945G), | |
39 | PLATFORM_NAME(I945GM), | |
40 | PLATFORM_NAME(G33), | |
41 | PLATFORM_NAME(PINEVIEW), | |
c0f86832 JN |
42 | PLATFORM_NAME(I965G), |
43 | PLATFORM_NAME(I965GM), | |
f69c11ae JN |
44 | PLATFORM_NAME(G45), |
45 | PLATFORM_NAME(GM45), | |
2e0d26f8 JN |
46 | PLATFORM_NAME(IRONLAKE), |
47 | PLATFORM_NAME(SANDYBRIDGE), | |
48 | PLATFORM_NAME(IVYBRIDGE), | |
49 | PLATFORM_NAME(VALLEYVIEW), | |
50 | PLATFORM_NAME(HASWELL), | |
51 | PLATFORM_NAME(BROADWELL), | |
52 | PLATFORM_NAME(CHERRYVIEW), | |
53 | PLATFORM_NAME(SKYLAKE), | |
54 | PLATFORM_NAME(BROXTON), | |
55 | PLATFORM_NAME(KABYLAKE), | |
56 | PLATFORM_NAME(GEMINILAKE), | |
71851fa8 | 57 | PLATFORM_NAME(COFFEELAKE), |
413f3c19 | 58 | PLATFORM_NAME(CANNONLAKE), |
41231001 | 59 | PLATFORM_NAME(ICELAKE), |
2e0d26f8 JN |
60 | }; |
61 | #undef PLATFORM_NAME | |
62 | ||
63 | const char *intel_platform_name(enum intel_platform platform) | |
64 | { | |
9160095c JN |
65 | BUILD_BUG_ON(ARRAY_SIZE(platform_names) != INTEL_MAX_PLATFORMS); |
66 | ||
2e0d26f8 JN |
67 | if (WARN_ON_ONCE(platform >= ARRAY_SIZE(platform_names) || |
68 | platform_names[platform] == NULL)) | |
69 | return "<unknown>"; | |
70 | ||
71 | return platform_names[platform]; | |
72 | } | |
73 | ||
a8c9b849 MW |
74 | void intel_device_info_dump_flags(const struct intel_device_info *info, |
75 | struct drm_printer *p) | |
76 | { | |
77 | #define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, yesno(info->name)); | |
78 | DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG); | |
79 | #undef PRINT_FLAG | |
80 | } | |
81 | ||
5fbbe8d4 MW |
82 | static void sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p) |
83 | { | |
8cc76693 LL |
84 | int s; |
85 | ||
5fbbe8d4 MW |
86 | drm_printf(p, "slice mask: %04x\n", sseu->slice_mask); |
87 | drm_printf(p, "slice total: %u\n", hweight8(sseu->slice_mask)); | |
88 | drm_printf(p, "subslice total: %u\n", sseu_subslice_total(sseu)); | |
8cc76693 LL |
89 | for (s = 0; s < ARRAY_SIZE(sseu->subslice_mask); s++) { |
90 | drm_printf(p, "slice%d %u subslices mask=%04x\n", | |
91 | s, hweight8(sseu->subslice_mask[s]), | |
92 | sseu->subslice_mask[s]); | |
93 | } | |
5fbbe8d4 MW |
94 | drm_printf(p, "EU total: %u\n", sseu->eu_total); |
95 | drm_printf(p, "EU per subslice: %u\n", sseu->eu_per_subslice); | |
96 | drm_printf(p, "has slice power gating: %s\n", | |
97 | yesno(sseu->has_slice_pg)); | |
98 | drm_printf(p, "has subslice power gating: %s\n", | |
99 | yesno(sseu->has_subslice_pg)); | |
100 | drm_printf(p, "has EU power gating: %s\n", yesno(sseu->has_eu_pg)); | |
101 | } | |
102 | ||
103 | void intel_device_info_dump_runtime(const struct intel_device_info *info, | |
104 | struct drm_printer *p) | |
105 | { | |
106 | sseu_dump(&info->sseu, p); | |
107 | ||
108 | drm_printf(p, "CS timestamp frequency: %u kHz\n", | |
109 | info->cs_timestamp_frequency_khz); | |
110 | } | |
111 | ||
eb10ed9a MW |
112 | void intel_device_info_dump(const struct intel_device_info *info, |
113 | struct drm_printer *p) | |
94b4f3ba | 114 | { |
eb10ed9a MW |
115 | struct drm_i915_private *dev_priv = |
116 | container_of(info, struct drm_i915_private, info); | |
94b4f3ba | 117 | |
eb10ed9a MW |
118 | drm_printf(p, "pciid=0x%04x rev=0x%02x platform=%s gen=%i\n", |
119 | INTEL_DEVID(dev_priv), | |
120 | INTEL_REVID(dev_priv), | |
121 | intel_platform_name(info->platform), | |
122 | info->gen); | |
a8c9b849 | 123 | |
eb10ed9a | 124 | intel_device_info_dump_flags(info, p); |
94b4f3ba CW |
125 | } |
126 | ||
8cc76693 LL |
127 | static u16 compute_eu_total(const struct sseu_dev_info *sseu) |
128 | { | |
129 | u16 i, total = 0; | |
130 | ||
131 | for (i = 0; i < ARRAY_SIZE(sseu->eu_mask); i++) | |
132 | total += hweight8(sseu->eu_mask[i]); | |
133 | ||
134 | return total; | |
135 | } | |
136 | ||
4e9767bc BW |
137 | static void gen10_sseu_info_init(struct drm_i915_private *dev_priv) |
138 | { | |
139 | struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu; | |
140 | const u32 fuse2 = I915_READ(GEN8_FUSE2); | |
8cc76693 LL |
141 | int s, ss; |
142 | const int eu_mask = 0xff; | |
143 | u32 subslice_mask, eu_en; | |
4e9767bc BW |
144 | |
145 | sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >> | |
146 | GEN10_F2_S_ENA_SHIFT; | |
8cc76693 LL |
147 | sseu->max_slices = 6; |
148 | sseu->max_subslices = 4; | |
149 | sseu->max_eus_per_subslice = 8; | |
4e9767bc | 150 | |
8cc76693 LL |
151 | subslice_mask = (1 << 4) - 1; |
152 | subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >> | |
153 | GEN10_F2_SS_DIS_SHIFT); | |
154 | ||
155 | /* | |
156 | * Slice0 can have up to 3 subslices, but there are only 2 in | |
157 | * slice1/2. | |
158 | */ | |
159 | sseu->subslice_mask[0] = subslice_mask; | |
160 | for (s = 1; s < sseu->max_slices; s++) | |
161 | sseu->subslice_mask[s] = subslice_mask & 0x3; | |
162 | ||
163 | /* Slice0 */ | |
164 | eu_en = ~I915_READ(GEN8_EU_DISABLE0); | |
165 | for (ss = 0; ss < sseu->max_subslices; ss++) | |
166 | sseu_set_eus(sseu, 0, ss, (eu_en >> (8 * ss)) & eu_mask); | |
167 | /* Slice1 */ | |
168 | sseu_set_eus(sseu, 1, 0, (eu_en >> 24) & eu_mask); | |
169 | eu_en = ~I915_READ(GEN8_EU_DISABLE1); | |
170 | sseu_set_eus(sseu, 1, 1, eu_en & eu_mask); | |
171 | /* Slice2 */ | |
172 | sseu_set_eus(sseu, 2, 0, (eu_en >> 8) & eu_mask); | |
173 | sseu_set_eus(sseu, 2, 1, (eu_en >> 16) & eu_mask); | |
174 | /* Slice3 */ | |
175 | sseu_set_eus(sseu, 3, 0, (eu_en >> 24) & eu_mask); | |
176 | eu_en = ~I915_READ(GEN8_EU_DISABLE2); | |
177 | sseu_set_eus(sseu, 3, 1, eu_en & eu_mask); | |
178 | /* Slice4 */ | |
179 | sseu_set_eus(sseu, 4, 0, (eu_en >> 8) & eu_mask); | |
180 | sseu_set_eus(sseu, 4, 1, (eu_en >> 16) & eu_mask); | |
181 | /* Slice5 */ | |
182 | sseu_set_eus(sseu, 5, 0, (eu_en >> 24) & eu_mask); | |
183 | eu_en = ~I915_READ(GEN10_EU_DISABLE3); | |
184 | sseu_set_eus(sseu, 5, 1, eu_en & eu_mask); | |
185 | ||
186 | /* Do a second pass where we mark the subslices disabled if all their | |
187 | * eus are off. | |
188 | */ | |
189 | for (s = 0; s < sseu->max_slices; s++) { | |
190 | for (ss = 0; ss < sseu->max_subslices; ss++) { | |
191 | if (sseu_get_eus(sseu, s, ss) == 0) | |
192 | sseu->subslice_mask[s] &= ~BIT(ss); | |
193 | } | |
194 | } | |
195 | ||
196 | sseu->eu_total = compute_eu_total(sseu); | |
4e9767bc BW |
197 | |
198 | /* | |
199 | * CNL is expected to always have a uniform distribution | |
200 | * of EU across subslices with the exception that any one | |
201 | * EU in any one subslice may be fused off for die | |
202 | * recovery. | |
203 | */ | |
204 | sseu->eu_per_subslice = sseu_subslice_total(sseu) ? | |
205 | DIV_ROUND_UP(sseu->eu_total, | |
206 | sseu_subslice_total(sseu)) : 0; | |
207 | ||
208 | /* No restrictions on Power Gating */ | |
209 | sseu->has_slice_pg = 1; | |
210 | sseu->has_subslice_pg = 1; | |
211 | sseu->has_eu_pg = 1; | |
212 | } | |
213 | ||
94b4f3ba CW |
214 | static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv) |
215 | { | |
43b67998 | 216 | struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu; |
8cc76693 | 217 | u32 fuse; |
94b4f3ba CW |
218 | |
219 | fuse = I915_READ(CHV_FUSE_GT); | |
220 | ||
f08a0c92 | 221 | sseu->slice_mask = BIT(0); |
8cc76693 LL |
222 | sseu->max_slices = 1; |
223 | sseu->max_subslices = 2; | |
224 | sseu->max_eus_per_subslice = 8; | |
94b4f3ba CW |
225 | |
226 | if (!(fuse & CHV_FGT_DISABLE_SS0)) { | |
8cc76693 LL |
227 | u8 disabled_mask = |
228 | ((fuse & CHV_FGT_EU_DIS_SS0_R0_MASK) >> | |
229 | CHV_FGT_EU_DIS_SS0_R0_SHIFT) | | |
230 | (((fuse & CHV_FGT_EU_DIS_SS0_R1_MASK) >> | |
231 | CHV_FGT_EU_DIS_SS0_R1_SHIFT) << 4); | |
232 | ||
233 | sseu->subslice_mask[0] |= BIT(0); | |
234 | sseu_set_eus(sseu, 0, 0, ~disabled_mask); | |
94b4f3ba CW |
235 | } |
236 | ||
237 | if (!(fuse & CHV_FGT_DISABLE_SS1)) { | |
8cc76693 LL |
238 | u8 disabled_mask = |
239 | ((fuse & CHV_FGT_EU_DIS_SS1_R0_MASK) >> | |
240 | CHV_FGT_EU_DIS_SS1_R0_SHIFT) | | |
241 | (((fuse & CHV_FGT_EU_DIS_SS1_R1_MASK) >> | |
242 | CHV_FGT_EU_DIS_SS1_R1_SHIFT) << 4); | |
243 | ||
244 | sseu->subslice_mask[0] |= BIT(1); | |
245 | sseu_set_eus(sseu, 0, 1, ~disabled_mask); | |
94b4f3ba CW |
246 | } |
247 | ||
8cc76693 LL |
248 | sseu->eu_total = compute_eu_total(sseu); |
249 | ||
94b4f3ba CW |
250 | /* |
251 | * CHV expected to always have a uniform distribution of EU | |
252 | * across subslices. | |
253 | */ | |
57ec171e ID |
254 | sseu->eu_per_subslice = sseu_subslice_total(sseu) ? |
255 | sseu->eu_total / sseu_subslice_total(sseu) : | |
94b4f3ba CW |
256 | 0; |
257 | /* | |
258 | * CHV supports subslice power gating on devices with more than | |
259 | * one subslice, and supports EU power gating on devices with | |
260 | * more than one EU pair per subslice. | |
261 | */ | |
43b67998 | 262 | sseu->has_slice_pg = 0; |
57ec171e | 263 | sseu->has_subslice_pg = sseu_subslice_total(sseu) > 1; |
43b67998 | 264 | sseu->has_eu_pg = (sseu->eu_per_subslice > 2); |
94b4f3ba CW |
265 | } |
266 | ||
267 | static void gen9_sseu_info_init(struct drm_i915_private *dev_priv) | |
268 | { | |
269 | struct intel_device_info *info = mkwrite_device_info(dev_priv); | |
43b67998 | 270 | struct sseu_dev_info *sseu = &info->sseu; |
94b4f3ba | 271 | int s, ss; |
8cc76693 LL |
272 | u32 fuse2, eu_disable, subslice_mask; |
273 | const u8 eu_mask = 0xff; | |
94b4f3ba CW |
274 | |
275 | fuse2 = I915_READ(GEN8_FUSE2); | |
f08a0c92 | 276 | sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT; |
94b4f3ba | 277 | |
8cc76693 LL |
278 | /* BXT has a single slice and at most 3 subslices. */ |
279 | sseu->max_slices = IS_GEN9_LP(dev_priv) ? 1 : 3; | |
280 | sseu->max_subslices = IS_GEN9_LP(dev_priv) ? 3 : 4; | |
281 | sseu->max_eus_per_subslice = 8; | |
282 | ||
94b4f3ba CW |
283 | /* |
284 | * The subslice disable field is global, i.e. it applies | |
285 | * to each of the enabled slices. | |
286 | */ | |
8cc76693 LL |
287 | subslice_mask = (1 << sseu->max_subslices) - 1; |
288 | subslice_mask &= ~((fuse2 & GEN9_F2_SS_DIS_MASK) >> | |
289 | GEN9_F2_SS_DIS_SHIFT); | |
94b4f3ba CW |
290 | |
291 | /* | |
292 | * Iterate through enabled slices and subslices to | |
293 | * count the total enabled EU. | |
294 | */ | |
8cc76693 | 295 | for (s = 0; s < sseu->max_slices; s++) { |
f08a0c92 | 296 | if (!(sseu->slice_mask & BIT(s))) |
94b4f3ba CW |
297 | /* skip disabled slice */ |
298 | continue; | |
299 | ||
8cc76693 LL |
300 | sseu->subslice_mask[s] = subslice_mask; |
301 | ||
94b4f3ba | 302 | eu_disable = I915_READ(GEN9_EU_DISABLE(s)); |
8cc76693 | 303 | for (ss = 0; ss < sseu->max_subslices; ss++) { |
94b4f3ba | 304 | int eu_per_ss; |
8cc76693 | 305 | u8 eu_disabled_mask; |
94b4f3ba | 306 | |
8cc76693 | 307 | if (!(sseu->subslice_mask[s] & BIT(ss))) |
94b4f3ba CW |
308 | /* skip disabled subslice */ |
309 | continue; | |
310 | ||
b3e7f866 | 311 | eu_disabled_mask = (eu_disable >> (ss * 8)) & eu_mask; |
8cc76693 LL |
312 | |
313 | sseu_set_eus(sseu, s, ss, ~eu_disabled_mask); | |
314 | ||
315 | eu_per_ss = sseu->max_eus_per_subslice - | |
316 | hweight8(eu_disabled_mask); | |
94b4f3ba CW |
317 | |
318 | /* | |
319 | * Record which subslice(s) has(have) 7 EUs. we | |
320 | * can tune the hash used to spread work among | |
321 | * subslices if they are unbalanced. | |
322 | */ | |
323 | if (eu_per_ss == 7) | |
43b67998 | 324 | sseu->subslice_7eu[s] |= BIT(ss); |
94b4f3ba CW |
325 | } |
326 | } | |
327 | ||
8cc76693 LL |
328 | sseu->eu_total = compute_eu_total(sseu); |
329 | ||
94b4f3ba CW |
330 | /* |
331 | * SKL is expected to always have a uniform distribution | |
332 | * of EU across subslices with the exception that any one | |
333 | * EU in any one subslice may be fused off for die | |
334 | * recovery. BXT is expected to be perfectly uniform in EU | |
335 | * distribution. | |
336 | */ | |
57ec171e | 337 | sseu->eu_per_subslice = sseu_subslice_total(sseu) ? |
43b67998 | 338 | DIV_ROUND_UP(sseu->eu_total, |
57ec171e | 339 | sseu_subslice_total(sseu)) : 0; |
94b4f3ba | 340 | /* |
c7ae7e9a | 341 | * SKL+ supports slice power gating on devices with more than |
94b4f3ba | 342 | * one slice, and supports EU power gating on devices with |
c7ae7e9a | 343 | * more than one EU pair per subslice. BXT+ supports subslice |
94b4f3ba CW |
344 | * power gating on devices with more than one subslice, and |
345 | * supports EU power gating on devices with more than one EU | |
346 | * pair per subslice. | |
347 | */ | |
43b67998 | 348 | sseu->has_slice_pg = |
c7ae7e9a | 349 | !IS_GEN9_LP(dev_priv) && hweight8(sseu->slice_mask) > 1; |
43b67998 | 350 | sseu->has_subslice_pg = |
254e0931 | 351 | IS_GEN9_LP(dev_priv) && sseu_subslice_total(sseu) > 1; |
43b67998 | 352 | sseu->has_eu_pg = sseu->eu_per_subslice > 2; |
94b4f3ba | 353 | |
234516af | 354 | if (IS_GEN9_LP(dev_priv)) { |
8cc76693 LL |
355 | #define IS_SS_DISABLED(ss) (!(sseu->subslice_mask[0] & BIT(ss))) |
356 | info->has_pooled_eu = hweight8(sseu->subslice_mask[0]) == 3; | |
234516af | 357 | |
43b67998 | 358 | sseu->min_eu_in_pool = 0; |
94b4f3ba | 359 | if (info->has_pooled_eu) { |
57ec171e | 360 | if (IS_SS_DISABLED(2) || IS_SS_DISABLED(0)) |
43b67998 | 361 | sseu->min_eu_in_pool = 3; |
57ec171e | 362 | else if (IS_SS_DISABLED(1)) |
43b67998 | 363 | sseu->min_eu_in_pool = 6; |
94b4f3ba | 364 | else |
43b67998 | 365 | sseu->min_eu_in_pool = 9; |
94b4f3ba CW |
366 | } |
367 | #undef IS_SS_DISABLED | |
368 | } | |
369 | } | |
370 | ||
371 | static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv) | |
372 | { | |
43b67998 | 373 | struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu; |
94b4f3ba | 374 | int s, ss; |
8cc76693 | 375 | u32 fuse2, subslice_mask, eu_disable[3]; /* s_max */ |
94b4f3ba CW |
376 | |
377 | fuse2 = I915_READ(GEN8_FUSE2); | |
f08a0c92 | 378 | sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT; |
8cc76693 LL |
379 | sseu->max_slices = 3; |
380 | sseu->max_subslices = 3; | |
381 | sseu->max_eus_per_subslice = 8; | |
382 | ||
57ec171e ID |
383 | /* |
384 | * The subslice disable field is global, i.e. it applies | |
385 | * to each of the enabled slices. | |
386 | */ | |
8cc76693 LL |
387 | subslice_mask = GENMASK(sseu->max_subslices - 1, 0); |
388 | subslice_mask &= ~((fuse2 & GEN8_F2_SS_DIS_MASK) >> | |
389 | GEN8_F2_SS_DIS_SHIFT); | |
94b4f3ba CW |
390 | |
391 | eu_disable[0] = I915_READ(GEN8_EU_DISABLE0) & GEN8_EU_DIS0_S0_MASK; | |
392 | eu_disable[1] = (I915_READ(GEN8_EU_DISABLE0) >> GEN8_EU_DIS0_S1_SHIFT) | | |
393 | ((I915_READ(GEN8_EU_DISABLE1) & GEN8_EU_DIS1_S1_MASK) << | |
394 | (32 - GEN8_EU_DIS0_S1_SHIFT)); | |
395 | eu_disable[2] = (I915_READ(GEN8_EU_DISABLE1) >> GEN8_EU_DIS1_S2_SHIFT) | | |
396 | ((I915_READ(GEN8_EU_DISABLE2) & GEN8_EU_DIS2_S2_MASK) << | |
397 | (32 - GEN8_EU_DIS1_S2_SHIFT)); | |
398 | ||
94b4f3ba CW |
399 | /* |
400 | * Iterate through enabled slices and subslices to | |
401 | * count the total enabled EU. | |
402 | */ | |
8cc76693 | 403 | for (s = 0; s < sseu->max_slices; s++) { |
f08a0c92 | 404 | if (!(sseu->slice_mask & BIT(s))) |
94b4f3ba CW |
405 | /* skip disabled slice */ |
406 | continue; | |
407 | ||
8cc76693 LL |
408 | sseu->subslice_mask[s] = subslice_mask; |
409 | ||
410 | for (ss = 0; ss < sseu->max_subslices; ss++) { | |
411 | u8 eu_disabled_mask; | |
94b4f3ba CW |
412 | u32 n_disabled; |
413 | ||
8cc76693 | 414 | if (!(sseu->subslice_mask[ss] & BIT(ss))) |
94b4f3ba CW |
415 | /* skip disabled subslice */ |
416 | continue; | |
417 | ||
8cc76693 LL |
418 | eu_disabled_mask = |
419 | eu_disable[s] >> (ss * sseu->max_eus_per_subslice); | |
420 | ||
421 | sseu_set_eus(sseu, s, ss, ~eu_disabled_mask); | |
422 | ||
423 | n_disabled = hweight8(eu_disabled_mask); | |
94b4f3ba CW |
424 | |
425 | /* | |
426 | * Record which subslices have 7 EUs. | |
427 | */ | |
8cc76693 | 428 | if (sseu->max_eus_per_subslice - n_disabled == 7) |
43b67998 | 429 | sseu->subslice_7eu[s] |= 1 << ss; |
94b4f3ba CW |
430 | } |
431 | } | |
432 | ||
8cc76693 LL |
433 | sseu->eu_total = compute_eu_total(sseu); |
434 | ||
94b4f3ba CW |
435 | /* |
436 | * BDW is expected to always have a uniform distribution of EU across | |
437 | * subslices with the exception that any one EU in any one subslice may | |
438 | * be fused off for die recovery. | |
439 | */ | |
57ec171e ID |
440 | sseu->eu_per_subslice = sseu_subslice_total(sseu) ? |
441 | DIV_ROUND_UP(sseu->eu_total, | |
442 | sseu_subslice_total(sseu)) : 0; | |
94b4f3ba CW |
443 | |
444 | /* | |
445 | * BDW supports slice power gating on devices with more than | |
446 | * one slice. | |
447 | */ | |
f08a0c92 | 448 | sseu->has_slice_pg = hweight8(sseu->slice_mask) > 1; |
43b67998 ID |
449 | sseu->has_subslice_pg = 0; |
450 | sseu->has_eu_pg = 0; | |
94b4f3ba CW |
451 | } |
452 | ||
b8ec759e LL |
453 | static void haswell_sseu_info_init(struct drm_i915_private *dev_priv) |
454 | { | |
455 | struct intel_device_info *info = mkwrite_device_info(dev_priv); | |
456 | struct sseu_dev_info *sseu = &info->sseu; | |
457 | u32 fuse1; | |
8cc76693 | 458 | int s, ss; |
b8ec759e LL |
459 | |
460 | /* | |
461 | * There isn't a register to tell us how many slices/subslices. We | |
462 | * work off the PCI-ids here. | |
463 | */ | |
464 | switch (info->gt) { | |
465 | default: | |
466 | MISSING_CASE(info->gt); | |
467 | /* fall through */ | |
468 | case 1: | |
469 | sseu->slice_mask = BIT(0); | |
8cc76693 | 470 | sseu->subslice_mask[0] = BIT(0); |
b8ec759e LL |
471 | break; |
472 | case 2: | |
473 | sseu->slice_mask = BIT(0); | |
8cc76693 | 474 | sseu->subslice_mask[0] = BIT(0) | BIT(1); |
b8ec759e LL |
475 | break; |
476 | case 3: | |
477 | sseu->slice_mask = BIT(0) | BIT(1); | |
8cc76693 LL |
478 | sseu->subslice_mask[0] = BIT(0) | BIT(1); |
479 | sseu->subslice_mask[1] = BIT(0) | BIT(1); | |
b8ec759e LL |
480 | break; |
481 | } | |
482 | ||
8cc76693 LL |
483 | sseu->max_slices = hweight8(sseu->slice_mask); |
484 | sseu->max_subslices = hweight8(sseu->subslice_mask[0]); | |
485 | ||
b8ec759e LL |
486 | fuse1 = I915_READ(HSW_PAVP_FUSE1); |
487 | switch ((fuse1 & HSW_F1_EU_DIS_MASK) >> HSW_F1_EU_DIS_SHIFT) { | |
488 | default: | |
489 | MISSING_CASE((fuse1 & HSW_F1_EU_DIS_MASK) >> | |
490 | HSW_F1_EU_DIS_SHIFT); | |
491 | /* fall through */ | |
492 | case HSW_F1_EU_DIS_10EUS: | |
493 | sseu->eu_per_subslice = 10; | |
494 | break; | |
495 | case HSW_F1_EU_DIS_8EUS: | |
496 | sseu->eu_per_subslice = 8; | |
497 | break; | |
498 | case HSW_F1_EU_DIS_6EUS: | |
499 | sseu->eu_per_subslice = 6; | |
500 | break; | |
501 | } | |
8cc76693 LL |
502 | sseu->max_eus_per_subslice = sseu->eu_per_subslice; |
503 | ||
504 | for (s = 0; s < sseu->max_slices; s++) { | |
505 | for (ss = 0; ss < sseu->max_subslices; ss++) { | |
506 | sseu_set_eus(sseu, s, ss, | |
507 | (1UL << sseu->eu_per_subslice) - 1); | |
508 | } | |
509 | } | |
b8ec759e | 510 | |
8cc76693 | 511 | sseu->eu_total = compute_eu_total(sseu); |
b8ec759e LL |
512 | |
513 | /* No powergating for you. */ | |
514 | sseu->has_slice_pg = 0; | |
515 | sseu->has_subslice_pg = 0; | |
516 | sseu->has_eu_pg = 0; | |
517 | } | |
518 | ||
f577a03b | 519 | static u32 read_reference_ts_freq(struct drm_i915_private *dev_priv) |
dab91783 LL |
520 | { |
521 | u32 ts_override = I915_READ(GEN9_TIMESTAMP_OVERRIDE); | |
f577a03b | 522 | u32 base_freq, frac_freq; |
dab91783 LL |
523 | |
524 | base_freq = ((ts_override & GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK) >> | |
525 | GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT) + 1; | |
f577a03b | 526 | base_freq *= 1000; |
dab91783 LL |
527 | |
528 | frac_freq = ((ts_override & | |
529 | GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK) >> | |
530 | GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT); | |
f577a03b | 531 | frac_freq = 1000 / (frac_freq + 1); |
dab91783 LL |
532 | |
533 | return base_freq + frac_freq; | |
534 | } | |
535 | ||
f577a03b | 536 | static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv) |
dab91783 | 537 | { |
f577a03b LL |
538 | u32 f12_5_mhz = 12500; |
539 | u32 f19_2_mhz = 19200; | |
540 | u32 f24_mhz = 24000; | |
dab91783 LL |
541 | |
542 | if (INTEL_GEN(dev_priv) <= 4) { | |
543 | /* PRMs say: | |
544 | * | |
545 | * "The value in this register increments once every 16 | |
546 | * hclks." (through the “Clocking Configuration” | |
547 | * (“CLKCFG”) MCHBAR register) | |
548 | */ | |
f577a03b | 549 | return dev_priv->rawclk_freq / 16; |
dab91783 LL |
550 | } else if (INTEL_GEN(dev_priv) <= 8) { |
551 | /* PRMs say: | |
552 | * | |
553 | * "The PCU TSC counts 10ns increments; this timestamp | |
554 | * reflects bits 38:3 of the TSC (i.e. 80ns granularity, | |
555 | * rolling over every 1.5 hours). | |
556 | */ | |
557 | return f12_5_mhz; | |
558 | } else if (INTEL_GEN(dev_priv) <= 9) { | |
559 | u32 ctc_reg = I915_READ(CTC_MODE); | |
f577a03b | 560 | u32 freq = 0; |
dab91783 LL |
561 | |
562 | if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) { | |
563 | freq = read_reference_ts_freq(dev_priv); | |
564 | } else { | |
565 | freq = IS_GEN9_LP(dev_priv) ? f19_2_mhz : f24_mhz; | |
566 | ||
567 | /* Now figure out how the command stream's timestamp | |
568 | * register increments from this frequency (it might | |
569 | * increment only every few clock cycle). | |
570 | */ | |
571 | freq >>= 3 - ((ctc_reg & CTC_SHIFT_PARAMETER_MASK) >> | |
572 | CTC_SHIFT_PARAMETER_SHIFT); | |
573 | } | |
574 | ||
575 | return freq; | |
576 | } else if (INTEL_GEN(dev_priv) <= 10) { | |
577 | u32 ctc_reg = I915_READ(CTC_MODE); | |
f577a03b | 578 | u32 freq = 0; |
dab91783 LL |
579 | u32 rpm_config_reg = 0; |
580 | ||
581 | /* First figure out the reference frequency. There are 2 ways | |
582 | * we can compute the frequency, either through the | |
583 | * TIMESTAMP_OVERRIDE register or through RPM_CONFIG. CTC_MODE | |
584 | * tells us which one we should use. | |
585 | */ | |
586 | if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) { | |
587 | freq = read_reference_ts_freq(dev_priv); | |
588 | } else { | |
589 | u32 crystal_clock; | |
590 | ||
591 | rpm_config_reg = I915_READ(RPM_CONFIG0); | |
592 | crystal_clock = (rpm_config_reg & | |
593 | GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >> | |
594 | GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT; | |
595 | switch (crystal_clock) { | |
596 | case GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ: | |
597 | freq = f19_2_mhz; | |
598 | break; | |
599 | case GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ: | |
600 | freq = f24_mhz; | |
601 | break; | |
602 | } | |
dab91783 | 603 | |
53ff2641 LL |
604 | /* Now figure out how the command stream's timestamp |
605 | * register increments from this frequency (it might | |
606 | * increment only every few clock cycle). | |
607 | */ | |
608 | freq >>= 3 - ((rpm_config_reg & | |
609 | GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >> | |
610 | GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT); | |
611 | } | |
dab91783 LL |
612 | |
613 | return freq; | |
614 | } | |
615 | ||
fe66e928 | 616 | MISSING_CASE("Unknown gen, unable to read command streamer timestamp frequency\n"); |
dab91783 LL |
617 | return 0; |
618 | } | |
619 | ||
6a7e51f3 MW |
620 | /** |
621 | * intel_device_info_runtime_init - initialize runtime info | |
622 | * @info: intel device info struct | |
623 | * | |
94b4f3ba CW |
624 | * Determine various intel_device_info fields at runtime. |
625 | * | |
626 | * Use it when either: | |
627 | * - it's judged too laborious to fill n static structures with the limit | |
628 | * when a simple if statement does the job, | |
629 | * - run-time checks (eg read fuse/strap registers) are needed. | |
630 | * | |
631 | * This function needs to be called: | |
632 | * - after the MMIO has been setup as we are reading registers, | |
633 | * - after the PCH has been detected, | |
634 | * - before the first usage of the fields it can tweak. | |
635 | */ | |
6a7e51f3 | 636 | void intel_device_info_runtime_init(struct intel_device_info *info) |
94b4f3ba | 637 | { |
6a7e51f3 MW |
638 | struct drm_i915_private *dev_priv = |
639 | container_of(info, struct drm_i915_private, info); | |
94b4f3ba CW |
640 | enum pipe pipe; |
641 | ||
6e7406db MK |
642 | if (INTEL_GEN(dev_priv) >= 10) { |
643 | for_each_pipe(dev_priv, pipe) | |
644 | info->num_scalers[pipe] = 2; | |
645 | } else if (INTEL_GEN(dev_priv) == 9) { | |
0bf0230e ACO |
646 | info->num_scalers[PIPE_A] = 2; |
647 | info->num_scalers[PIPE_B] = 2; | |
648 | info->num_scalers[PIPE_C] = 1; | |
649 | } | |
650 | ||
022d3093 TU |
651 | BUILD_BUG_ON(I915_NUM_ENGINES > |
652 | sizeof(intel_ring_mask_t) * BITS_PER_BYTE); | |
653 | ||
94b4f3ba CW |
654 | /* |
655 | * Skylake and Broxton currently don't expose the topmost plane as its | |
656 | * use is exclusive with the legacy cursor and we only want to expose | |
657 | * one of those, not both. Until we can safely expose the topmost plane | |
658 | * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported, | |
659 | * we don't expose the topmost plane at all to prevent ABI breakage | |
660 | * down the line. | |
661 | */ | |
8366be98 | 662 | if (IS_GEN10(dev_priv) || IS_GEMINILAKE(dev_priv)) |
e9c98825 ACO |
663 | for_each_pipe(dev_priv, pipe) |
664 | info->num_sprites[pipe] = 3; | |
665 | else if (IS_BROXTON(dev_priv)) { | |
94b4f3ba CW |
666 | info->num_sprites[PIPE_A] = 2; |
667 | info->num_sprites[PIPE_B] = 2; | |
668 | info->num_sprites[PIPE_C] = 1; | |
33edc24d | 669 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
94b4f3ba CW |
670 | for_each_pipe(dev_priv, pipe) |
671 | info->num_sprites[pipe] = 2; | |
ab33081a | 672 | } else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) { |
94b4f3ba CW |
673 | for_each_pipe(dev_priv, pipe) |
674 | info->num_sprites[pipe] = 1; | |
33edc24d | 675 | } |
94b4f3ba | 676 | |
4f044a88 | 677 | if (i915_modparams.disable_display) { |
94b4f3ba CW |
678 | DRM_INFO("Display disabled (module parameter)\n"); |
679 | info->num_pipes = 0; | |
680 | } else if (info->num_pipes > 0 && | |
681 | (IS_GEN7(dev_priv) || IS_GEN8(dev_priv)) && | |
682 | HAS_PCH_SPLIT(dev_priv)) { | |
683 | u32 fuse_strap = I915_READ(FUSE_STRAP); | |
684 | u32 sfuse_strap = I915_READ(SFUSE_STRAP); | |
685 | ||
686 | /* | |
687 | * SFUSE_STRAP is supposed to have a bit signalling the display | |
688 | * is fused off. Unfortunately it seems that, at least in | |
689 | * certain cases, fused off display means that PCH display | |
690 | * reads don't land anywhere. In that case, we read 0s. | |
691 | * | |
692 | * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK | |
693 | * should be set when taking over after the firmware. | |
694 | */ | |
695 | if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE || | |
696 | sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED || | |
b9eb89b2 | 697 | (HAS_PCH_CPT(dev_priv) && |
94b4f3ba CW |
698 | !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) { |
699 | DRM_INFO("Display fused off, disabling\n"); | |
700 | info->num_pipes = 0; | |
701 | } else if (fuse_strap & IVB_PIPE_C_DISABLE) { | |
702 | DRM_INFO("PipeC fused off\n"); | |
703 | info->num_pipes -= 1; | |
704 | } | |
705 | } else if (info->num_pipes > 0 && IS_GEN9(dev_priv)) { | |
706 | u32 dfsm = I915_READ(SKL_DFSM); | |
707 | u8 disabled_mask = 0; | |
708 | bool invalid; | |
709 | int num_bits; | |
710 | ||
711 | if (dfsm & SKL_DFSM_PIPE_A_DISABLE) | |
712 | disabled_mask |= BIT(PIPE_A); | |
713 | if (dfsm & SKL_DFSM_PIPE_B_DISABLE) | |
714 | disabled_mask |= BIT(PIPE_B); | |
715 | if (dfsm & SKL_DFSM_PIPE_C_DISABLE) | |
716 | disabled_mask |= BIT(PIPE_C); | |
717 | ||
718 | num_bits = hweight8(disabled_mask); | |
719 | ||
720 | switch (disabled_mask) { | |
721 | case BIT(PIPE_A): | |
722 | case BIT(PIPE_B): | |
723 | case BIT(PIPE_A) | BIT(PIPE_B): | |
724 | case BIT(PIPE_A) | BIT(PIPE_C): | |
725 | invalid = true; | |
726 | break; | |
727 | default: | |
728 | invalid = false; | |
729 | } | |
730 | ||
731 | if (num_bits > info->num_pipes || invalid) | |
732 | DRM_ERROR("invalid pipe fuse configuration: 0x%x\n", | |
733 | disabled_mask); | |
734 | else | |
735 | info->num_pipes -= num_bits; | |
736 | } | |
737 | ||
738 | /* Initialize slice/subslice/EU info */ | |
b8ec759e LL |
739 | if (IS_HASWELL(dev_priv)) |
740 | haswell_sseu_info_init(dev_priv); | |
741 | else if (IS_CHERRYVIEW(dev_priv)) | |
94b4f3ba CW |
742 | cherryview_sseu_info_init(dev_priv); |
743 | else if (IS_BROADWELL(dev_priv)) | |
744 | broadwell_sseu_info_init(dev_priv); | |
4e9767bc | 745 | else if (INTEL_GEN(dev_priv) == 9) |
94b4f3ba | 746 | gen9_sseu_info_init(dev_priv); |
4e9767bc BW |
747 | else if (INTEL_GEN(dev_priv) >= 10) |
748 | gen10_sseu_info_init(dev_priv); | |
94b4f3ba | 749 | |
dab91783 | 750 | /* Initialize command stream timestamp frequency */ |
f577a03b | 751 | info->cs_timestamp_frequency_khz = read_timestamp_frequency(dev_priv); |
94b4f3ba | 752 | } |
3fed1808 CW |
753 | |
754 | void intel_driver_caps_print(const struct intel_driver_caps *caps, | |
755 | struct drm_printer *p) | |
756 | { | |
757 | drm_printf(p, "scheduler: %x\n", caps->scheduler); | |
758 | } |