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94b4f3ba CW |
1 | /* |
2 | * Copyright © 2016 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | ||
25 | #include "i915_drv.h" | |
26 | ||
27 | void intel_device_info_dump(struct drm_i915_private *dev_priv) | |
28 | { | |
29 | const struct intel_device_info *info = &dev_priv->info; | |
30 | ||
31 | #define PRINT_S(name) "%s" | |
32 | #define SEP_EMPTY | |
33 | #define PRINT_FLAG(name) info->name ? #name "," : "" | |
34 | #define SEP_COMMA , | |
35 | DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x rev=0x%02x flags=" | |
36 | DEV_INFO_FOR_EACH_FLAG(PRINT_S, SEP_EMPTY), | |
37 | info->gen, | |
38 | dev_priv->drm.pdev->device, | |
39 | dev_priv->drm.pdev->revision, | |
40 | DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_COMMA)); | |
41 | #undef PRINT_S | |
42 | #undef SEP_EMPTY | |
43 | #undef PRINT_FLAG | |
44 | #undef SEP_COMMA | |
45 | } | |
46 | ||
47 | static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv) | |
48 | { | |
43b67998 | 49 | struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu; |
94b4f3ba CW |
50 | u32 fuse, eu_dis; |
51 | ||
52 | fuse = I915_READ(CHV_FUSE_GT); | |
53 | ||
f08a0c92 | 54 | sseu->slice_mask = BIT(0); |
94b4f3ba CW |
55 | |
56 | if (!(fuse & CHV_FGT_DISABLE_SS0)) { | |
57ec171e | 57 | sseu->subslice_mask |= BIT(0); |
94b4f3ba CW |
58 | eu_dis = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK | |
59 | CHV_FGT_EU_DIS_SS0_R1_MASK); | |
43b67998 | 60 | sseu->eu_total += 8 - hweight32(eu_dis); |
94b4f3ba CW |
61 | } |
62 | ||
63 | if (!(fuse & CHV_FGT_DISABLE_SS1)) { | |
57ec171e | 64 | sseu->subslice_mask |= BIT(1); |
94b4f3ba CW |
65 | eu_dis = fuse & (CHV_FGT_EU_DIS_SS1_R0_MASK | |
66 | CHV_FGT_EU_DIS_SS1_R1_MASK); | |
43b67998 | 67 | sseu->eu_total += 8 - hweight32(eu_dis); |
94b4f3ba CW |
68 | } |
69 | ||
94b4f3ba CW |
70 | /* |
71 | * CHV expected to always have a uniform distribution of EU | |
72 | * across subslices. | |
73 | */ | |
57ec171e ID |
74 | sseu->eu_per_subslice = sseu_subslice_total(sseu) ? |
75 | sseu->eu_total / sseu_subslice_total(sseu) : | |
94b4f3ba CW |
76 | 0; |
77 | /* | |
78 | * CHV supports subslice power gating on devices with more than | |
79 | * one subslice, and supports EU power gating on devices with | |
80 | * more than one EU pair per subslice. | |
81 | */ | |
43b67998 | 82 | sseu->has_slice_pg = 0; |
57ec171e | 83 | sseu->has_subslice_pg = sseu_subslice_total(sseu) > 1; |
43b67998 | 84 | sseu->has_eu_pg = (sseu->eu_per_subslice > 2); |
94b4f3ba CW |
85 | } |
86 | ||
87 | static void gen9_sseu_info_init(struct drm_i915_private *dev_priv) | |
88 | { | |
89 | struct intel_device_info *info = mkwrite_device_info(dev_priv); | |
43b67998 | 90 | struct sseu_dev_info *sseu = &info->sseu; |
94b4f3ba CW |
91 | int s_max = 3, ss_max = 4, eu_max = 8; |
92 | int s, ss; | |
57ec171e | 93 | u32 fuse2, eu_disable; |
94b4f3ba CW |
94 | u8 eu_mask = 0xff; |
95 | ||
96 | fuse2 = I915_READ(GEN8_FUSE2); | |
f08a0c92 | 97 | sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT; |
94b4f3ba | 98 | |
94b4f3ba CW |
99 | /* |
100 | * The subslice disable field is global, i.e. it applies | |
101 | * to each of the enabled slices. | |
102 | */ | |
57ec171e ID |
103 | sseu->subslice_mask = (1 << ss_max) - 1; |
104 | sseu->subslice_mask &= ~((fuse2 & GEN9_F2_SS_DIS_MASK) >> | |
105 | GEN9_F2_SS_DIS_SHIFT); | |
94b4f3ba CW |
106 | |
107 | /* | |
108 | * Iterate through enabled slices and subslices to | |
109 | * count the total enabled EU. | |
110 | */ | |
111 | for (s = 0; s < s_max; s++) { | |
f08a0c92 | 112 | if (!(sseu->slice_mask & BIT(s))) |
94b4f3ba CW |
113 | /* skip disabled slice */ |
114 | continue; | |
115 | ||
116 | eu_disable = I915_READ(GEN9_EU_DISABLE(s)); | |
117 | for (ss = 0; ss < ss_max; ss++) { | |
118 | int eu_per_ss; | |
119 | ||
57ec171e | 120 | if (!(sseu->subslice_mask & BIT(ss))) |
94b4f3ba CW |
121 | /* skip disabled subslice */ |
122 | continue; | |
123 | ||
124 | eu_per_ss = eu_max - hweight8((eu_disable >> (ss*8)) & | |
125 | eu_mask); | |
126 | ||
127 | /* | |
128 | * Record which subslice(s) has(have) 7 EUs. we | |
129 | * can tune the hash used to spread work among | |
130 | * subslices if they are unbalanced. | |
131 | */ | |
132 | if (eu_per_ss == 7) | |
43b67998 | 133 | sseu->subslice_7eu[s] |= BIT(ss); |
94b4f3ba | 134 | |
43b67998 | 135 | sseu->eu_total += eu_per_ss; |
94b4f3ba CW |
136 | } |
137 | } | |
138 | ||
139 | /* | |
140 | * SKL is expected to always have a uniform distribution | |
141 | * of EU across subslices with the exception that any one | |
142 | * EU in any one subslice may be fused off for die | |
143 | * recovery. BXT is expected to be perfectly uniform in EU | |
144 | * distribution. | |
145 | */ | |
57ec171e | 146 | sseu->eu_per_subslice = sseu_subslice_total(sseu) ? |
43b67998 | 147 | DIV_ROUND_UP(sseu->eu_total, |
57ec171e | 148 | sseu_subslice_total(sseu)) : 0; |
94b4f3ba CW |
149 | /* |
150 | * SKL supports slice power gating on devices with more than | |
151 | * one slice, and supports EU power gating on devices with | |
152 | * more than one EU pair per subslice. BXT supports subslice | |
153 | * power gating on devices with more than one subslice, and | |
154 | * supports EU power gating on devices with more than one EU | |
155 | * pair per subslice. | |
156 | */ | |
43b67998 | 157 | sseu->has_slice_pg = |
94b4f3ba | 158 | (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) && |
f08a0c92 | 159 | hweight8(sseu->slice_mask) > 1; |
43b67998 | 160 | sseu->has_subslice_pg = |
57ec171e | 161 | IS_BROXTON(dev_priv) && sseu_subslice_total(sseu) > 1; |
43b67998 | 162 | sseu->has_eu_pg = sseu->eu_per_subslice > 2; |
94b4f3ba CW |
163 | |
164 | if (IS_BROXTON(dev_priv)) { | |
57ec171e | 165 | #define IS_SS_DISABLED(ss) (!(sseu->subslice_mask & BIT(ss))) |
94b4f3ba CW |
166 | /* |
167 | * There is a HW issue in 2x6 fused down parts that requires | |
168 | * Pooled EU to be enabled as a WA. The pool configuration | |
169 | * changes depending upon which subslice is fused down. This | |
170 | * doesn't affect if the device has all 3 subslices enabled. | |
171 | */ | |
172 | /* WaEnablePooledEuFor2x6:bxt */ | |
57ec171e ID |
173 | info->has_pooled_eu = ((hweight8(sseu->subslice_mask) == 3) || |
174 | (hweight8(sseu->subslice_mask) == 2 && | |
94b4f3ba CW |
175 | INTEL_REVID(dev_priv) < BXT_REVID_C0)); |
176 | ||
43b67998 | 177 | sseu->min_eu_in_pool = 0; |
94b4f3ba | 178 | if (info->has_pooled_eu) { |
57ec171e | 179 | if (IS_SS_DISABLED(2) || IS_SS_DISABLED(0)) |
43b67998 | 180 | sseu->min_eu_in_pool = 3; |
57ec171e | 181 | else if (IS_SS_DISABLED(1)) |
43b67998 | 182 | sseu->min_eu_in_pool = 6; |
94b4f3ba | 183 | else |
43b67998 | 184 | sseu->min_eu_in_pool = 9; |
94b4f3ba CW |
185 | } |
186 | #undef IS_SS_DISABLED | |
187 | } | |
188 | } | |
189 | ||
190 | static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv) | |
191 | { | |
43b67998 | 192 | struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu; |
94b4f3ba CW |
193 | const int s_max = 3, ss_max = 3, eu_max = 8; |
194 | int s, ss; | |
57ec171e | 195 | u32 fuse2, eu_disable[s_max]; |
94b4f3ba CW |
196 | |
197 | fuse2 = I915_READ(GEN8_FUSE2); | |
f08a0c92 | 198 | sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT; |
57ec171e ID |
199 | /* |
200 | * The subslice disable field is global, i.e. it applies | |
201 | * to each of the enabled slices. | |
202 | */ | |
203 | sseu->subslice_mask = BIT(ss_max) - 1; | |
204 | sseu->subslice_mask &= ~((fuse2 & GEN8_F2_SS_DIS_MASK) >> | |
205 | GEN8_F2_SS_DIS_SHIFT); | |
94b4f3ba CW |
206 | |
207 | eu_disable[0] = I915_READ(GEN8_EU_DISABLE0) & GEN8_EU_DIS0_S0_MASK; | |
208 | eu_disable[1] = (I915_READ(GEN8_EU_DISABLE0) >> GEN8_EU_DIS0_S1_SHIFT) | | |
209 | ((I915_READ(GEN8_EU_DISABLE1) & GEN8_EU_DIS1_S1_MASK) << | |
210 | (32 - GEN8_EU_DIS0_S1_SHIFT)); | |
211 | eu_disable[2] = (I915_READ(GEN8_EU_DISABLE1) >> GEN8_EU_DIS1_S2_SHIFT) | | |
212 | ((I915_READ(GEN8_EU_DISABLE2) & GEN8_EU_DIS2_S2_MASK) << | |
213 | (32 - GEN8_EU_DIS1_S2_SHIFT)); | |
214 | ||
94b4f3ba CW |
215 | /* |
216 | * Iterate through enabled slices and subslices to | |
217 | * count the total enabled EU. | |
218 | */ | |
219 | for (s = 0; s < s_max; s++) { | |
f08a0c92 | 220 | if (!(sseu->slice_mask & BIT(s))) |
94b4f3ba CW |
221 | /* skip disabled slice */ |
222 | continue; | |
223 | ||
224 | for (ss = 0; ss < ss_max; ss++) { | |
225 | u32 n_disabled; | |
226 | ||
57ec171e | 227 | if (!(sseu->subslice_mask & BIT(ss))) |
94b4f3ba CW |
228 | /* skip disabled subslice */ |
229 | continue; | |
230 | ||
231 | n_disabled = hweight8(eu_disable[s] >> (ss * eu_max)); | |
232 | ||
233 | /* | |
234 | * Record which subslices have 7 EUs. | |
235 | */ | |
236 | if (eu_max - n_disabled == 7) | |
43b67998 | 237 | sseu->subslice_7eu[s] |= 1 << ss; |
94b4f3ba | 238 | |
43b67998 | 239 | sseu->eu_total += eu_max - n_disabled; |
94b4f3ba CW |
240 | } |
241 | } | |
242 | ||
243 | /* | |
244 | * BDW is expected to always have a uniform distribution of EU across | |
245 | * subslices with the exception that any one EU in any one subslice may | |
246 | * be fused off for die recovery. | |
247 | */ | |
57ec171e ID |
248 | sseu->eu_per_subslice = sseu_subslice_total(sseu) ? |
249 | DIV_ROUND_UP(sseu->eu_total, | |
250 | sseu_subslice_total(sseu)) : 0; | |
94b4f3ba CW |
251 | |
252 | /* | |
253 | * BDW supports slice power gating on devices with more than | |
254 | * one slice. | |
255 | */ | |
f08a0c92 | 256 | sseu->has_slice_pg = hweight8(sseu->slice_mask) > 1; |
43b67998 ID |
257 | sseu->has_subslice_pg = 0; |
258 | sseu->has_eu_pg = 0; | |
94b4f3ba CW |
259 | } |
260 | ||
261 | /* | |
262 | * Determine various intel_device_info fields at runtime. | |
263 | * | |
264 | * Use it when either: | |
265 | * - it's judged too laborious to fill n static structures with the limit | |
266 | * when a simple if statement does the job, | |
267 | * - run-time checks (eg read fuse/strap registers) are needed. | |
268 | * | |
269 | * This function needs to be called: | |
270 | * - after the MMIO has been setup as we are reading registers, | |
271 | * - after the PCH has been detected, | |
272 | * - before the first usage of the fields it can tweak. | |
273 | */ | |
274 | void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) | |
275 | { | |
276 | struct intel_device_info *info = mkwrite_device_info(dev_priv); | |
277 | enum pipe pipe; | |
278 | ||
279 | /* | |
280 | * Skylake and Broxton currently don't expose the topmost plane as its | |
281 | * use is exclusive with the legacy cursor and we only want to expose | |
282 | * one of those, not both. Until we can safely expose the topmost plane | |
283 | * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported, | |
284 | * we don't expose the topmost plane at all to prevent ABI breakage | |
285 | * down the line. | |
286 | */ | |
287 | if (IS_BROXTON(dev_priv)) { | |
288 | info->num_sprites[PIPE_A] = 2; | |
289 | info->num_sprites[PIPE_B] = 2; | |
290 | info->num_sprites[PIPE_C] = 1; | |
291 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
292 | for_each_pipe(dev_priv, pipe) | |
293 | info->num_sprites[pipe] = 2; | |
294 | else | |
295 | for_each_pipe(dev_priv, pipe) | |
296 | info->num_sprites[pipe] = 1; | |
297 | ||
298 | if (i915.disable_display) { | |
299 | DRM_INFO("Display disabled (module parameter)\n"); | |
300 | info->num_pipes = 0; | |
301 | } else if (info->num_pipes > 0 && | |
302 | (IS_GEN7(dev_priv) || IS_GEN8(dev_priv)) && | |
303 | HAS_PCH_SPLIT(dev_priv)) { | |
304 | u32 fuse_strap = I915_READ(FUSE_STRAP); | |
305 | u32 sfuse_strap = I915_READ(SFUSE_STRAP); | |
306 | ||
307 | /* | |
308 | * SFUSE_STRAP is supposed to have a bit signalling the display | |
309 | * is fused off. Unfortunately it seems that, at least in | |
310 | * certain cases, fused off display means that PCH display | |
311 | * reads don't land anywhere. In that case, we read 0s. | |
312 | * | |
313 | * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK | |
314 | * should be set when taking over after the firmware. | |
315 | */ | |
316 | if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE || | |
317 | sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED || | |
318 | (dev_priv->pch_type == PCH_CPT && | |
319 | !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) { | |
320 | DRM_INFO("Display fused off, disabling\n"); | |
321 | info->num_pipes = 0; | |
322 | } else if (fuse_strap & IVB_PIPE_C_DISABLE) { | |
323 | DRM_INFO("PipeC fused off\n"); | |
324 | info->num_pipes -= 1; | |
325 | } | |
326 | } else if (info->num_pipes > 0 && IS_GEN9(dev_priv)) { | |
327 | u32 dfsm = I915_READ(SKL_DFSM); | |
328 | u8 disabled_mask = 0; | |
329 | bool invalid; | |
330 | int num_bits; | |
331 | ||
332 | if (dfsm & SKL_DFSM_PIPE_A_DISABLE) | |
333 | disabled_mask |= BIT(PIPE_A); | |
334 | if (dfsm & SKL_DFSM_PIPE_B_DISABLE) | |
335 | disabled_mask |= BIT(PIPE_B); | |
336 | if (dfsm & SKL_DFSM_PIPE_C_DISABLE) | |
337 | disabled_mask |= BIT(PIPE_C); | |
338 | ||
339 | num_bits = hweight8(disabled_mask); | |
340 | ||
341 | switch (disabled_mask) { | |
342 | case BIT(PIPE_A): | |
343 | case BIT(PIPE_B): | |
344 | case BIT(PIPE_A) | BIT(PIPE_B): | |
345 | case BIT(PIPE_A) | BIT(PIPE_C): | |
346 | invalid = true; | |
347 | break; | |
348 | default: | |
349 | invalid = false; | |
350 | } | |
351 | ||
352 | if (num_bits > info->num_pipes || invalid) | |
353 | DRM_ERROR("invalid pipe fuse configuration: 0x%x\n", | |
354 | disabled_mask); | |
355 | else | |
356 | info->num_pipes -= num_bits; | |
357 | } | |
358 | ||
359 | /* Initialize slice/subslice/EU info */ | |
360 | if (IS_CHERRYVIEW(dev_priv)) | |
361 | cherryview_sseu_info_init(dev_priv); | |
362 | else if (IS_BROADWELL(dev_priv)) | |
363 | broadwell_sseu_info_init(dev_priv); | |
364 | else if (INTEL_INFO(dev_priv)->gen >= 9) | |
365 | gen9_sseu_info_init(dev_priv); | |
366 | ||
367 | info->has_snoop = !info->has_llc; | |
368 | ||
369 | /* Snooping is broken on BXT A stepping. */ | |
370 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) | |
371 | info->has_snoop = false; | |
372 | ||
c67ba538 | 373 | DRM_DEBUG_DRIVER("slice mask: %04x\n", info->sseu.slice_mask); |
f08a0c92 | 374 | DRM_DEBUG_DRIVER("slice total: %u\n", hweight8(info->sseu.slice_mask)); |
57ec171e ID |
375 | DRM_DEBUG_DRIVER("subslice total: %u\n", |
376 | sseu_subslice_total(&info->sseu)); | |
c67ba538 | 377 | DRM_DEBUG_DRIVER("subslice mask %04x\n", info->sseu.subslice_mask); |
43b67998 | 378 | DRM_DEBUG_DRIVER("subslice per slice: %u\n", |
57ec171e | 379 | hweight8(info->sseu.subslice_mask)); |
43b67998 ID |
380 | DRM_DEBUG_DRIVER("EU total: %u\n", info->sseu.eu_total); |
381 | DRM_DEBUG_DRIVER("EU per subslice: %u\n", info->sseu.eu_per_subslice); | |
94b4f3ba | 382 | DRM_DEBUG_DRIVER("has slice power gating: %s\n", |
43b67998 | 383 | info->sseu.has_slice_pg ? "y" : "n"); |
94b4f3ba | 384 | DRM_DEBUG_DRIVER("has subslice power gating: %s\n", |
43b67998 | 385 | info->sseu.has_subslice_pg ? "y" : "n"); |
94b4f3ba | 386 | DRM_DEBUG_DRIVER("has EU power gating: %s\n", |
43b67998 | 387 | info->sseu.has_eu_pg ? "y" : "n"); |
94b4f3ba | 388 | } |