[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_device_info.c

/*
 * Copyright © 2016 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 */

#include "i915_drv.h"

#define PLATFORM_NAME(x) [INTEL_##x] = #x
static const char * const platform_names[] = {
	PLATFORM_NAME(I830),
	PLATFORM_NAME(I845G),
	PLATFORM_NAME(I85X),
	PLATFORM_NAME(I865G),
	PLATFORM_NAME(I915G),
	PLATFORM_NAME(I915GM),
	PLATFORM_NAME(I945G),
	PLATFORM_NAME(I945GM),
	PLATFORM_NAME(G33),
	PLATFORM_NAME(PINEVIEW),
	PLATFORM_NAME(BROADWATER),
	PLATFORM_NAME(CRESTLINE),
	PLATFORM_NAME(G4X),
	PLATFORM_NAME(IRONLAKE),
	PLATFORM_NAME(SANDYBRIDGE),
	PLATFORM_NAME(IVYBRIDGE),
	PLATFORM_NAME(VALLEYVIEW),
	PLATFORM_NAME(HASWELL),
	PLATFORM_NAME(BROADWELL),
	PLATFORM_NAME(CHERRYVIEW),
	PLATFORM_NAME(SKYLAKE),
	PLATFORM_NAME(BROXTON),
	PLATFORM_NAME(KABYLAKE),
	PLATFORM_NAME(GEMINILAKE),
};
#undef PLATFORM_NAME

const char *intel_platform_name(enum intel_platform platform)
{
	if (WARN_ON_ONCE(platform >= ARRAY_SIZE(platform_names) ||
			 platform_names[platform] == NULL))
		return "<unknown>";

	return platform_names[platform];
}

void intel_device_info_dump(struct drm_i915_private *dev_priv)
{
	const struct intel_device_info *info = &dev_priv->info;

	DRM_DEBUG_DRIVER("i915 device info: platform=%s gen=%i pciid=0x%04x rev=0x%02x",
			 intel_platform_name(info->platform),
			 info->gen,
			 dev_priv->drm.pdev->device,
			 dev_priv->drm.pdev->revision);
#define PRINT_FLAG(name) \
	DRM_DEBUG_DRIVER("i915 device info: " #name ": %s", yesno(info->name))
	DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
#undef PRINT_FLAG
}

static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
{
	struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
	u32 fuse, eu_dis;

	fuse = I915_READ(CHV_FUSE_GT);

	sseu->slice_mask = BIT(0);

	if (!(fuse & CHV_FGT_DISABLE_SS0)) {
		sseu->subslice_mask |= BIT(0);
		eu_dis = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK |
				 CHV_FGT_EU_DIS_SS0_R1_MASK);
		sseu->eu_total += 8 - hweight32(eu_dis);
	}

	if (!(fuse & CHV_FGT_DISABLE_SS1)) {
		sseu->subslice_mask |= BIT(1);
		eu_dis = fuse & (CHV_FGT_EU_DIS_SS1_R0_MASK |
				 CHV_FGT_EU_DIS_SS1_R1_MASK);
		sseu->eu_total += 8 - hweight32(eu_dis);
	}

	/*
	 * CHV expected to always have a uniform distribution of EU
	 * across subslices.
	*/
	sseu->eu_per_subslice = sseu_subslice_total(sseu) ?
				sseu->eu_total / sseu_subslice_total(sseu) :
				0;
	/*
	 * CHV supports subslice power gating on devices with more than
	 * one subslice, and supports EU power gating on devices with
	 * more than one EU pair per subslice.
	*/
	sseu->has_slice_pg = 0;
	sseu->has_subslice_pg = sseu_subslice_total(sseu) > 1;
	sseu->has_eu_pg = (sseu->eu_per_subslice > 2);
}

static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
{
	struct intel_device_info *info = mkwrite_device_info(dev_priv);
	struct sseu_dev_info *sseu = &info->sseu;
	int s_max = 3, ss_max = 4, eu_max = 8;
	int s, ss;
	u32 fuse2, eu_disable;
	u8 eu_mask = 0xff;

	fuse2 = I915_READ(GEN8_FUSE2);
	sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;

	/*
	 * The subslice disable field is global, i.e. it applies
	 * to each of the enabled slices.
	*/
	sseu->subslice_mask = (1 << ss_max) - 1;
	sseu->subslice_mask &= ~((fuse2 & GEN9_F2_SS_DIS_MASK) >>
				 GEN9_F2_SS_DIS_SHIFT);

	/*
	 * Iterate through enabled slices and subslices to
	 * count the total enabled EU.
	*/
	for (s = 0; s < s_max; s++) {
		if (!(sseu->slice_mask & BIT(s)))
			/* skip disabled slice */
			continue;

		eu_disable = I915_READ(GEN9_EU_DISABLE(s));
		for (ss = 0; ss < ss_max; ss++) {
			int eu_per_ss;

			if (!(sseu->subslice_mask & BIT(ss)))
				/* skip disabled subslice */
				continue;

			eu_per_ss = eu_max - hweight8((eu_disable >> (ss*8)) &
						      eu_mask);

			/*
			 * Record which subslice(s) has(have) 7 EUs. we
			 * can tune the hash used to spread work among
			 * subslices if they are unbalanced.
			 */
			if (eu_per_ss == 7)
				sseu->subslice_7eu[s] |= BIT(ss);

			sseu->eu_total += eu_per_ss;
		}
	}

	/*
	 * SKL is expected to always have a uniform distribution
	 * of EU across subslices with the exception that any one
	 * EU in any one subslice may be fused off for die
	 * recovery. BXT is expected to be perfectly uniform in EU
	 * distribution.
	*/
	sseu->eu_per_subslice = sseu_subslice_total(sseu) ?
				DIV_ROUND_UP(sseu->eu_total,
					     sseu_subslice_total(sseu)) : 0;
	/*
	 * SKL supports slice power gating on devices with more than
	 * one slice, and supports EU power gating on devices with
	 * more than one EU pair per subslice. BXT supports subslice
	 * power gating on devices with more than one subslice, and
	 * supports EU power gating on devices with more than one EU
	 * pair per subslice.
	*/
	sseu->has_slice_pg =
		(IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) &&
		hweight8(sseu->slice_mask) > 1;
	sseu->has_subslice_pg =
		IS_BROXTON(dev_priv) && sseu_subslice_total(sseu) > 1;
	sseu->has_eu_pg = sseu->eu_per_subslice > 2;

	if (IS_BROXTON(dev_priv)) {
#define IS_SS_DISABLED(ss)	(!(sseu->subslice_mask & BIT(ss)))
		/*
		 * There is a HW issue in 2x6 fused down parts that requires
		 * Pooled EU to be enabled as a WA. The pool configuration
		 * changes depending upon which subslice is fused down. This
		 * doesn't affect if the device has all 3 subslices enabled.
		 */
		/* WaEnablePooledEuFor2x6:bxt */
		info->has_pooled_eu = ((hweight8(sseu->subslice_mask) == 3) ||
				       (hweight8(sseu->subslice_mask) == 2 &&
					INTEL_REVID(dev_priv) < BXT_REVID_C0));

		sseu->min_eu_in_pool = 0;
		if (info->has_pooled_eu) {
			if (IS_SS_DISABLED(2) || IS_SS_DISABLED(0))
				sseu->min_eu_in_pool = 3;
			else if (IS_SS_DISABLED(1))
				sseu->min_eu_in_pool = 6;
			else
				sseu->min_eu_in_pool = 9;
		}
#undef IS_SS_DISABLED
	}
}

static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv)
{
	struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
	const int s_max = 3, ss_max = 3, eu_max = 8;
	int s, ss;
	u32 fuse2, eu_disable[3]; /* s_max */

	fuse2 = I915_READ(GEN8_FUSE2);
	sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
	/*
	 * The subslice disable field is global, i.e. it applies
	 * to each of the enabled slices.
	 */
	sseu->subslice_mask = BIT(ss_max) - 1;
	sseu->subslice_mask &= ~((fuse2 & GEN8_F2_SS_DIS_MASK) >>
				 GEN8_F2_SS_DIS_SHIFT);

	eu_disable[0] = I915_READ(GEN8_EU_DISABLE0) & GEN8_EU_DIS0_S0_MASK;
	eu_disable[1] = (I915_READ(GEN8_EU_DISABLE0) >> GEN8_EU_DIS0_S1_SHIFT) |
			((I915_READ(GEN8_EU_DISABLE1) & GEN8_EU_DIS1_S1_MASK) <<
			 (32 - GEN8_EU_DIS0_S1_SHIFT));
	eu_disable[2] = (I915_READ(GEN8_EU_DISABLE1) >> GEN8_EU_DIS1_S2_SHIFT) |
			((I915_READ(GEN8_EU_DISABLE2) & GEN8_EU_DIS2_S2_MASK) <<
			 (32 - GEN8_EU_DIS1_S2_SHIFT));

	/*
	 * Iterate through enabled slices and subslices to
	 * count the total enabled EU.
	 */
	for (s = 0; s < s_max; s++) {
		if (!(sseu->slice_mask & BIT(s)))
			/* skip disabled slice */
			continue;

		for (ss = 0; ss < ss_max; ss++) {
			u32 n_disabled;

			if (!(sseu->subslice_mask & BIT(ss)))
				/* skip disabled subslice */
				continue;

			n_disabled = hweight8(eu_disable[s] >> (ss * eu_max));

			/*
			 * Record which subslices have 7 EUs.
			 */
			if (eu_max - n_disabled == 7)
				sseu->subslice_7eu[s] |= 1 << ss;

			sseu->eu_total += eu_max - n_disabled;
		}
	}

	/*
	 * BDW is expected to always have a uniform distribution of EU across
	 * subslices with the exception that any one EU in any one subslice may
	 * be fused off for die recovery.
	 */
	sseu->eu_per_subslice = sseu_subslice_total(sseu) ?
				DIV_ROUND_UP(sseu->eu_total,
					     sseu_subslice_total(sseu)) : 0;

	/*
	 * BDW supports slice power gating on devices with more than
	 * one slice.
	 */
	sseu->has_slice_pg = hweight8(sseu->slice_mask) > 1;
	sseu->has_subslice_pg = 0;
	sseu->has_eu_pg = 0;
}

/*
 * Determine various intel_device_info fields at runtime.
 *
 * Use it when either:
 *   - it's judged too laborious to fill n static structures with the limit
 *     when a simple if statement does the job,
 *   - run-time checks (eg read fuse/strap registers) are needed.
 *
 * This function needs to be called:
 *   - after the MMIO has been setup as we are reading registers,
 *   - after the PCH has been detected,
 *   - before the first usage of the fields it can tweak.
 */
void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
{
	struct intel_device_info *info = mkwrite_device_info(dev_priv);
	enum pipe pipe;

	/*
	 * Skylake and Broxton currently don't expose the topmost plane as its
	 * use is exclusive with the legacy cursor and we only want to expose
	 * one of those, not both. Until we can safely expose the topmost plane
	 * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported,
	 * we don't expose the topmost plane at all to prevent ABI breakage
	 * down the line.
	 */
	if (IS_GEMINILAKE(dev_priv))
		for_each_pipe(dev_priv, pipe)
			info->num_sprites[pipe] = 3;
	else if (IS_BROXTON(dev_priv)) {
		info->num_sprites[PIPE_A] = 2;
		info->num_sprites[PIPE_B] = 2;
		info->num_sprites[PIPE_C] = 1;
	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
		for_each_pipe(dev_priv, pipe)
			info->num_sprites[pipe] = 2;
	} else if (INTEL_GEN(dev_priv) >= 5) {
		for_each_pipe(dev_priv, pipe)
			info->num_sprites[pipe] = 1;
	}

	if (i915.disable_display) {
		DRM_INFO("Display disabled (module parameter)\n");
		info->num_pipes = 0;
	} else if (info->num_pipes > 0 &&
		   (IS_GEN7(dev_priv) || IS_GEN8(dev_priv)) &&
		   HAS_PCH_SPLIT(dev_priv)) {
		u32 fuse_strap = I915_READ(FUSE_STRAP);
		u32 sfuse_strap = I915_READ(SFUSE_STRAP);

		/*
		 * SFUSE_STRAP is supposed to have a bit signalling the display
		 * is fused off. Unfortunately it seems that, at least in
		 * certain cases, fused off display means that PCH display
		 * reads don't land anywhere. In that case, we read 0s.
		 *
		 * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
		 * should be set when taking over after the firmware.
		 */
		if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
		    sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
		    (dev_priv->pch_type == PCH_CPT &&
		     !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
			DRM_INFO("Display fused off, disabling\n");
			info->num_pipes = 0;
		} else if (fuse_strap & IVB_PIPE_C_DISABLE) {
			DRM_INFO("PipeC fused off\n");
			info->num_pipes -= 1;
		}
	} else if (info->num_pipes > 0 && IS_GEN9(dev_priv)) {
		u32 dfsm = I915_READ(SKL_DFSM);
		u8 disabled_mask = 0;
		bool invalid;
		int num_bits;

		if (dfsm & SKL_DFSM_PIPE_A_DISABLE)
			disabled_mask |= BIT(PIPE_A);
		if (dfsm & SKL_DFSM_PIPE_B_DISABLE)
			disabled_mask |= BIT(PIPE_B);
		if (dfsm & SKL_DFSM_PIPE_C_DISABLE)
			disabled_mask |= BIT(PIPE_C);

		num_bits = hweight8(disabled_mask);

		switch (disabled_mask) {
		case BIT(PIPE_A):
		case BIT(PIPE_B):
		case BIT(PIPE_A) | BIT(PIPE_B):
		case BIT(PIPE_A) | BIT(PIPE_C):
			invalid = true;
			break;
		default:
			invalid = false;
		}

		if (num_bits > info->num_pipes || invalid)
			DRM_ERROR("invalid pipe fuse configuration: 0x%x\n",
				  disabled_mask);
		else
			info->num_pipes -= num_bits;
	}

	/* Initialize slice/subslice/EU info */
	if (IS_CHERRYVIEW(dev_priv))
		cherryview_sseu_info_init(dev_priv);
	else if (IS_BROADWELL(dev_priv))
		broadwell_sseu_info_init(dev_priv);
	else if (INTEL_INFO(dev_priv)->gen >= 9)
		gen9_sseu_info_init(dev_priv);

	info->has_snoop = !info->has_llc;

	/* Snooping is broken on BXT A stepping. */
	if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
		info->has_snoop = false;

	DRM_DEBUG_DRIVER("slice mask: %04x\n", info->sseu.slice_mask);
	DRM_DEBUG_DRIVER("slice total: %u\n", hweight8(info->sseu.slice_mask));
	DRM_DEBUG_DRIVER("subslice total: %u\n",
			 sseu_subslice_total(&info->sseu));
	DRM_DEBUG_DRIVER("subslice mask %04x\n", info->sseu.subslice_mask);
	DRM_DEBUG_DRIVER("subslice per slice: %u\n",
			 hweight8(info->sseu.subslice_mask));
	DRM_DEBUG_DRIVER("EU total: %u\n", info->sseu.eu_total);
	DRM_DEBUG_DRIVER("EU per subslice: %u\n", info->sseu.eu_per_subslice);
	DRM_DEBUG_DRIVER("has slice power gating: %s\n",
			 info->sseu.has_slice_pg ? "y" : "n");
	DRM_DEBUG_DRIVER("has subslice power gating: %s\n",
			 info->sseu.has_subslice_pg ? "y" : "n");
	DRM_DEBUG_DRIVER("has EU power gating: %s\n",
			 info->sseu.has_eu_pg ? "y" : "n");
}
Commit	Line	Data
94b4f3ba CW	1	/*
	2	* Copyright © 2016 Intel Corporation
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
	21	* IN THE SOFTWARE.
	22	*
	23	*/
	24
	25	#include "i915_drv.h"
	26
2e0d26f8 JN	27	#define PLATFORM_NAME(x) [INTEL_##x] = #x
	28	static const char * const platform_names[] = {
	29	PLATFORM_NAME(I830),
	30	PLATFORM_NAME(I845G),
	31	PLATFORM_NAME(I85X),
	32	PLATFORM_NAME(I865G),
	33	PLATFORM_NAME(I915G),
	34	PLATFORM_NAME(I915GM),
	35	PLATFORM_NAME(I945G),
	36	PLATFORM_NAME(I945GM),
	37	PLATFORM_NAME(G33),
	38	PLATFORM_NAME(PINEVIEW),
	39	PLATFORM_NAME(BROADWATER),
	40	PLATFORM_NAME(CRESTLINE),
	41	PLATFORM_NAME(G4X),
	42	PLATFORM_NAME(IRONLAKE),
	43	PLATFORM_NAME(SANDYBRIDGE),
	44	PLATFORM_NAME(IVYBRIDGE),
	45	PLATFORM_NAME(VALLEYVIEW),
	46	PLATFORM_NAME(HASWELL),
	47	PLATFORM_NAME(BROADWELL),
	48	PLATFORM_NAME(CHERRYVIEW),
	49	PLATFORM_NAME(SKYLAKE),
	50	PLATFORM_NAME(BROXTON),
	51	PLATFORM_NAME(KABYLAKE),
	52	PLATFORM_NAME(GEMINILAKE),
	53	};
	54	#undef PLATFORM_NAME
	55
	56	const char *intel_platform_name(enum intel_platform platform)
	57	{
	58	if (WARN_ON_ONCE(platform >= ARRAY_SIZE(platform_names) \|\|
	59	platform_names[platform] == NULL))
	60	return "<unknown>";
	61
	62	return platform_names[platform];
	63	}
	64
94b4f3ba CW	65	void intel_device_info_dump(struct drm_i915_private *dev_priv)
	66	{
	67	const struct intel_device_info *info = &dev_priv->info;
	68
2e0d26f8 JN	69	DRM_DEBUG_DRIVER("i915 device info: platform=%s gen=%i pciid=0x%04x rev=0x%02x",
2e0d26f8 JN	70	intel_platform_name(info->platform),
94b4f3ba CW	71	info->gen,
94b4f3ba CW	72	dev_priv->drm.pdev->device,
604db650 JL	73	dev_priv->drm.pdev->revision);
	74	#define PRINT_FLAG(name) \
	75	DRM_DEBUG_DRIVER("i915 device info: " #name ": %s", yesno(info->name))
	76	DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
94b4f3ba	77	#undef PRINT_FLAG
94b4f3ba CW	78	}
	79
	80	static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
	81	{
43b67998	82	struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
94b4f3ba CW	83	u32 fuse, eu_dis;
	84
	85	fuse = I915_READ(CHV_FUSE_GT);
	86
f08a0c92	87	sseu->slice_mask = BIT(0);
94b4f3ba CW	88
94b4f3ba CW	89	if (!(fuse & CHV_FGT_DISABLE_SS0)) {
57ec171e	90	sseu->subslice_mask \|= BIT(0);
94b4f3ba CW	91	eu_dis = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK \|
94b4f3ba CW	92	CHV_FGT_EU_DIS_SS0_R1_MASK);
43b67998	93	sseu->eu_total += 8 - hweight32(eu_dis);
94b4f3ba CW	94	}
	95
	96	if (!(fuse & CHV_FGT_DISABLE_SS1)) {
57ec171e	97	sseu->subslice_mask \|= BIT(1);
94b4f3ba CW	98	eu_dis = fuse & (CHV_FGT_EU_DIS_SS1_R0_MASK \|
94b4f3ba CW	99	CHV_FGT_EU_DIS_SS1_R1_MASK);
43b67998	100	sseu->eu_total += 8 - hweight32(eu_dis);
94b4f3ba CW	101	}
94b4f3ba CW	102
94b4f3ba CW	103	/*
	104	* CHV expected to always have a uniform distribution of EU
	105	* across subslices.
	106	*/
57ec171e ID	107	sseu->eu_per_subslice = sseu_subslice_total(sseu) ?
57ec171e ID	108	sseu->eu_total / sseu_subslice_total(sseu) :
94b4f3ba CW	109	0;
	110	/*
	111	* CHV supports subslice power gating on devices with more than
	112	* one subslice, and supports EU power gating on devices with
	113	* more than one EU pair per subslice.
	114	*/
43b67998	115	sseu->has_slice_pg = 0;
57ec171e	116	sseu->has_subslice_pg = sseu_subslice_total(sseu) > 1;
43b67998	117	sseu->has_eu_pg = (sseu->eu_per_subslice > 2);
94b4f3ba CW	118	}
	119
	120	static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
	121	{
	122	struct intel_device_info *info = mkwrite_device_info(dev_priv);
43b67998	123	struct sseu_dev_info *sseu = &info->sseu;
94b4f3ba CW	124	int s_max = 3, ss_max = 4, eu_max = 8;
94b4f3ba CW	125	int s, ss;
57ec171e	126	u32 fuse2, eu_disable;
94b4f3ba CW	127	u8 eu_mask = 0xff;
	128
	129	fuse2 = I915_READ(GEN8_FUSE2);
f08a0c92	130	sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
94b4f3ba	131
94b4f3ba CW	132	/*
	133	* The subslice disable field is global, i.e. it applies
	134	* to each of the enabled slices.
	135	*/
57ec171e ID	136	sseu->subslice_mask = (1 << ss_max) - 1;
	137	sseu->subslice_mask &= ~((fuse2 & GEN9_F2_SS_DIS_MASK) >>
	138	GEN9_F2_SS_DIS_SHIFT);
94b4f3ba CW	139
	140	/*
	141	* Iterate through enabled slices and subslices to
	142	* count the total enabled EU.
	143	*/
	144	for (s = 0; s < s_max; s++) {
f08a0c92	145	if (!(sseu->slice_mask & BIT(s)))
94b4f3ba CW	146	/* skip disabled slice */
	147	continue;
	148
	149	eu_disable = I915_READ(GEN9_EU_DISABLE(s));
	150	for (ss = 0; ss < ss_max; ss++) {
	151	int eu_per_ss;
	152
57ec171e	153	if (!(sseu->subslice_mask & BIT(ss)))
94b4f3ba CW	154	/* skip disabled subslice */
	155	continue;
	156
	157	eu_per_ss = eu_max - hweight8((eu_disable >> (ss*8)) &
	158	eu_mask);
	159
	160	/*
	161	* Record which subslice(s) has(have) 7 EUs. we
	162	* can tune the hash used to spread work among
	163	* subslices if they are unbalanced.
	164	*/
	165	if (eu_per_ss == 7)
43b67998	166	sseu->subslice_7eu[s] \|= BIT(ss);
94b4f3ba	167
43b67998	168	sseu->eu_total += eu_per_ss;
94b4f3ba CW	169	}
	170	}
	171
	172	/*
	173	* SKL is expected to always have a uniform distribution
	174	* of EU across subslices with the exception that any one
	175	* EU in any one subslice may be fused off for die
	176	* recovery. BXT is expected to be perfectly uniform in EU
	177	* distribution.
	178	*/
57ec171e	179	sseu->eu_per_subslice = sseu_subslice_total(sseu) ?
43b67998	180	DIV_ROUND_UP(sseu->eu_total,
57ec171e	181	sseu_subslice_total(sseu)) : 0;
94b4f3ba CW	182	/*
	183	* SKL supports slice power gating on devices with more than
	184	* one slice, and supports EU power gating on devices with
	185	* more than one EU pair per subslice. BXT supports subslice
	186	* power gating on devices with more than one subslice, and
	187	* supports EU power gating on devices with more than one EU
	188	* pair per subslice.
	189	*/
43b67998	190	sseu->has_slice_pg =
94b4f3ba	191	(IS_SKYLAKE(dev_priv) \|\| IS_KABYLAKE(dev_priv)) &&
f08a0c92	192	hweight8(sseu->slice_mask) > 1;
43b67998	193	sseu->has_subslice_pg =
57ec171e	194	IS_BROXTON(dev_priv) && sseu_subslice_total(sseu) > 1;
43b67998	195	sseu->has_eu_pg = sseu->eu_per_subslice > 2;
94b4f3ba CW	196
94b4f3ba CW	197	if (IS_BROXTON(dev_priv)) {
57ec171e	198	#define IS_SS_DISABLED(ss) (!(sseu->subslice_mask & BIT(ss)))
94b4f3ba CW	199	/*
	200	* There is a HW issue in 2x6 fused down parts that requires
	201	* Pooled EU to be enabled as a WA. The pool configuration
	202	* changes depending upon which subslice is fused down. This
	203	* doesn't affect if the device has all 3 subslices enabled.
	204	*/
	205	/* WaEnablePooledEuFor2x6:bxt */
57ec171e ID	206	info->has_pooled_eu = ((hweight8(sseu->subslice_mask) == 3) \|\|
57ec171e ID	207	(hweight8(sseu->subslice_mask) == 2 &&
94b4f3ba CW	208	INTEL_REVID(dev_priv) < BXT_REVID_C0));
94b4f3ba CW	209
43b67998	210	sseu->min_eu_in_pool = 0;
94b4f3ba	211	if (info->has_pooled_eu) {
57ec171e	212	if (IS_SS_DISABLED(2) \|\| IS_SS_DISABLED(0))
43b67998	213	sseu->min_eu_in_pool = 3;
57ec171e	214	else if (IS_SS_DISABLED(1))
43b67998	215	sseu->min_eu_in_pool = 6;
94b4f3ba	216	else
43b67998	217	sseu->min_eu_in_pool = 9;
94b4f3ba CW	218	}
	219	#undef IS_SS_DISABLED
	220	}
	221	}
	222
	223	static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv)
	224	{
43b67998	225	struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
94b4f3ba CW	226	const int s_max = 3, ss_max = 3, eu_max = 8;
94b4f3ba CW	227	int s, ss;
ff64aa1e	228	u32 fuse2, eu_disable[3]; /* s_max */
94b4f3ba CW	229
94b4f3ba CW	230	fuse2 = I915_READ(GEN8_FUSE2);
f08a0c92	231	sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
57ec171e ID	232	/*
	233	* The subslice disable field is global, i.e. it applies
	234	* to each of the enabled slices.
	235	*/
	236	sseu->subslice_mask = BIT(ss_max) - 1;
	237	sseu->subslice_mask &= ~((fuse2 & GEN8_F2_SS_DIS_MASK) >>
	238	GEN8_F2_SS_DIS_SHIFT);
94b4f3ba CW	239
	240	eu_disable[0] = I915_READ(GEN8_EU_DISABLE0) & GEN8_EU_DIS0_S0_MASK;
	241	eu_disable[1] = (I915_READ(GEN8_EU_DISABLE0) >> GEN8_EU_DIS0_S1_SHIFT) \|
	242	((I915_READ(GEN8_EU_DISABLE1) & GEN8_EU_DIS1_S1_MASK) <<
	243	(32 - GEN8_EU_DIS0_S1_SHIFT));
	244	eu_disable[2] = (I915_READ(GEN8_EU_DISABLE1) >> GEN8_EU_DIS1_S2_SHIFT) \|
	245	((I915_READ(GEN8_EU_DISABLE2) & GEN8_EU_DIS2_S2_MASK) <<
	246	(32 - GEN8_EU_DIS1_S2_SHIFT));
	247
94b4f3ba CW	248	/*
	249	* Iterate through enabled slices and subslices to
	250	* count the total enabled EU.
	251	*/
	252	for (s = 0; s < s_max; s++) {
f08a0c92	253	if (!(sseu->slice_mask & BIT(s)))
94b4f3ba CW	254	/* skip disabled slice */
	255	continue;
	256
	257	for (ss = 0; ss < ss_max; ss++) {
	258	u32 n_disabled;
	259
57ec171e	260	if (!(sseu->subslice_mask & BIT(ss)))
94b4f3ba CW	261	/* skip disabled subslice */
	262	continue;
	263
	264	n_disabled = hweight8(eu_disable[s] >> (ss * eu_max));
	265
	266	/*
	267	* Record which subslices have 7 EUs.
	268	*/
	269	if (eu_max - n_disabled == 7)
43b67998	270	sseu->subslice_7eu[s] \|= 1 << ss;
94b4f3ba	271
43b67998	272	sseu->eu_total += eu_max - n_disabled;
94b4f3ba CW	273	}
	274	}
	275
	276	/*
	277	* BDW is expected to always have a uniform distribution of EU across
	278	* subslices with the exception that any one EU in any one subslice may
	279	* be fused off for die recovery.
	280	*/
57ec171e ID	281	sseu->eu_per_subslice = sseu_subslice_total(sseu) ?
	282	DIV_ROUND_UP(sseu->eu_total,
	283	sseu_subslice_total(sseu)) : 0;
94b4f3ba CW	284
	285	/*
	286	* BDW supports slice power gating on devices with more than
	287	* one slice.
	288	*/
f08a0c92	289	sseu->has_slice_pg = hweight8(sseu->slice_mask) > 1;
43b67998 ID	290	sseu->has_subslice_pg = 0;
43b67998 ID	291	sseu->has_eu_pg = 0;
94b4f3ba CW	292	}
	293
	294	/*
	295	* Determine various intel_device_info fields at runtime.
	296	*
	297	* Use it when either:
	298	* - it's judged too laborious to fill n static structures with the limit
	299	* when a simple if statement does the job,
	300	* - run-time checks (eg read fuse/strap registers) are needed.
	301	*
	302	* This function needs to be called:
	303	* - after the MMIO has been setup as we are reading registers,
	304	* - after the PCH has been detected,
	305	* - before the first usage of the fields it can tweak.
	306	*/
	307	void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
	308	{
	309	struct intel_device_info *info = mkwrite_device_info(dev_priv);
	310	enum pipe pipe;
	311
	312	/*
	313	* Skylake and Broxton currently don't expose the topmost plane as its
	314	* use is exclusive with the legacy cursor and we only want to expose
	315	* one of those, not both. Until we can safely expose the topmost plane
	316	* as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported,
	317	* we don't expose the topmost plane at all to prevent ABI breakage
	318	* down the line.
	319	*/
e9c98825 ACO	320	if (IS_GEMINILAKE(dev_priv))
	321	for_each_pipe(dev_priv, pipe)
	322	info->num_sprites[pipe] = 3;
	323	else if (IS_BROXTON(dev_priv)) {
94b4f3ba CW	324	info->num_sprites[PIPE_A] = 2;
	325	info->num_sprites[PIPE_B] = 2;
	326	info->num_sprites[PIPE_C] = 1;
33edc24d	327	} else if (IS_VALLEYVIEW(dev_priv) \|\| IS_CHERRYVIEW(dev_priv)) {
94b4f3ba CW	328	for_each_pipe(dev_priv, pipe)
94b4f3ba CW	329	info->num_sprites[pipe] = 2;
33edc24d	330	} else if (INTEL_GEN(dev_priv) >= 5) {
94b4f3ba CW	331	for_each_pipe(dev_priv, pipe)
94b4f3ba CW	332	info->num_sprites[pipe] = 1;
33edc24d	333	}
94b4f3ba CW	334
	335	if (i915.disable_display) {
	336	DRM_INFO("Display disabled (module parameter)\n");
	337	info->num_pipes = 0;
	338	} else if (info->num_pipes > 0 &&
	339	(IS_GEN7(dev_priv) \|\| IS_GEN8(dev_priv)) &&
	340	HAS_PCH_SPLIT(dev_priv)) {
	341	u32 fuse_strap = I915_READ(FUSE_STRAP);
	342	u32 sfuse_strap = I915_READ(SFUSE_STRAP);
	343
	344	/*
	345	* SFUSE_STRAP is supposed to have a bit signalling the display
	346	* is fused off. Unfortunately it seems that, at least in
	347	* certain cases, fused off display means that PCH display
	348	* reads don't land anywhere. In that case, we read 0s.
	349	*
	350	* On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
	351	* should be set when taking over after the firmware.
	352	*/
	353	if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE \|\|
	354	sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED \|\|
	355	(dev_priv->pch_type == PCH_CPT &&
	356	!(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
	357	DRM_INFO("Display fused off, disabling\n");
	358	info->num_pipes = 0;
	359	} else if (fuse_strap & IVB_PIPE_C_DISABLE) {
	360	DRM_INFO("PipeC fused off\n");
	361	info->num_pipes -= 1;
	362	}
	363	} else if (info->num_pipes > 0 && IS_GEN9(dev_priv)) {
	364	u32 dfsm = I915_READ(SKL_DFSM);
	365	u8 disabled_mask = 0;
	366	bool invalid;
	367	int num_bits;
	368
	369	if (dfsm & SKL_DFSM_PIPE_A_DISABLE)
	370	disabled_mask \|= BIT(PIPE_A);
	371	if (dfsm & SKL_DFSM_PIPE_B_DISABLE)
	372	disabled_mask \|= BIT(PIPE_B);
	373	if (dfsm & SKL_DFSM_PIPE_C_DISABLE)
	374	disabled_mask \|= BIT(PIPE_C);
	375
	376	num_bits = hweight8(disabled_mask);
	377
	378	switch (disabled_mask) {
	379	case BIT(PIPE_A):
	380	case BIT(PIPE_B):
	381	case BIT(PIPE_A) \| BIT(PIPE_B):
	382	case BIT(PIPE_A) \| BIT(PIPE_C):
	383	invalid = true;
	384	break;
	385	default:
	386	invalid = false;
	387	}
	388
	389	if (num_bits > info->num_pipes \|\| invalid)
	390	DRM_ERROR("invalid pipe fuse configuration: 0x%x\n",
	391	disabled_mask);
	392	else
	393	info->num_pipes -= num_bits;
	394	}
	395
	396	/* Initialize slice/subslice/EU info */
	397	if (IS_CHERRYVIEW(dev_priv))
398	cherryview_sseu_info_init(dev_priv);
399	else if (IS_BROADWELL(dev_priv))
400	broadwell_sseu_info_init(dev_priv);
401	else if (INTEL_INFO(dev_priv)->gen >= 9)
402	gen9_sseu_info_init(dev_priv);
403
404	info->has_snoop = !info->has_llc;
405
406	/* Snooping is broken on BXT A stepping. */
407	if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
408	info->has_snoop = false;
409
c67ba538	410	DRM_DEBUG_DRIVER("slice mask: %04x\n", info->sseu.slice_mask);
f08a0c92	411	DRM_DEBUG_DRIVER("slice total: %u\n", hweight8(info->sseu.slice_mask));
57ec171e ID	412	DRM_DEBUG_DRIVER("subslice total: %u\n",
57ec171e ID	413	sseu_subslice_total(&info->sseu));
c67ba538	414	DRM_DEBUG_DRIVER("subslice mask %04x\n", info->sseu.subslice_mask);
43b67998	415	DRM_DEBUG_DRIVER("subslice per slice: %u\n",
57ec171e	416	hweight8(info->sseu.subslice_mask));
43b67998 ID	417	DRM_DEBUG_DRIVER("EU total: %u\n", info->sseu.eu_total);
43b67998 ID	418	DRM_DEBUG_DRIVER("EU per subslice: %u\n", info->sseu.eu_per_subslice);
94b4f3ba	419	DRM_DEBUG_DRIVER("has slice power gating: %s\n",
43b67998	420	info->sseu.has_slice_pg ? "y" : "n");
94b4f3ba	421	DRM_DEBUG_DRIVER("has subslice power gating: %s\n",
43b67998	422	info->sseu.has_subslice_pg ? "y" : "n");
94b4f3ba	423	DRM_DEBUG_DRIVER("has EU power gating: %s\n",
43b67998	424	info->sseu.has_eu_pg ? "y" : "n");
94b4f3ba	425	}