[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_device_info.c

/*
 * Copyright © 2016 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 */

#include <drm/drm_print.h>
#include <drm/i915_pciids.h>

#include "display/intel_cdclk.h"
#include "display/intel_de.h"
#include "intel_device_info.h"
#include "i915_drv.h"

#define PLATFORM_NAME(x) [INTEL_##x] = #x
static const char * const platform_names[] = {
	PLATFORM_NAME(I830),
	PLATFORM_NAME(I845G),
	PLATFORM_NAME(I85X),
	PLATFORM_NAME(I865G),
	PLATFORM_NAME(I915G),
	PLATFORM_NAME(I915GM),
	PLATFORM_NAME(I945G),
	PLATFORM_NAME(I945GM),
	PLATFORM_NAME(G33),
	PLATFORM_NAME(PINEVIEW),
	PLATFORM_NAME(I965G),
	PLATFORM_NAME(I965GM),
	PLATFORM_NAME(G45),
	PLATFORM_NAME(GM45),
	PLATFORM_NAME(IRONLAKE),
	PLATFORM_NAME(SANDYBRIDGE),
	PLATFORM_NAME(IVYBRIDGE),
	PLATFORM_NAME(VALLEYVIEW),
	PLATFORM_NAME(HASWELL),
	PLATFORM_NAME(BROADWELL),
	PLATFORM_NAME(CHERRYVIEW),
	PLATFORM_NAME(SKYLAKE),
	PLATFORM_NAME(BROXTON),
	PLATFORM_NAME(KABYLAKE),
	PLATFORM_NAME(GEMINILAKE),
	PLATFORM_NAME(COFFEELAKE),
	PLATFORM_NAME(COMETLAKE),
	PLATFORM_NAME(ICELAKE),
	PLATFORM_NAME(ELKHARTLAKE),
	PLATFORM_NAME(JASPERLAKE),
	PLATFORM_NAME(TIGERLAKE),
	PLATFORM_NAME(ROCKETLAKE),
	PLATFORM_NAME(DG1),
	PLATFORM_NAME(ALDERLAKE_S),
	PLATFORM_NAME(ALDERLAKE_P),
	PLATFORM_NAME(XEHPSDV),
	PLATFORM_NAME(DG2),
};
#undef PLATFORM_NAME

const char *intel_platform_name(enum intel_platform platform)
{
	BUILD_BUG_ON(ARRAY_SIZE(platform_names) != INTEL_MAX_PLATFORMS);

	if (WARN_ON_ONCE(platform >= ARRAY_SIZE(platform_names) ||
			 platform_names[platform] == NULL))
		return "<unknown>";

	return platform_names[platform];
}

static const char *iommu_name(void)
{
	const char *msg = "n/a";

#ifdef CONFIG_INTEL_IOMMU
	msg = enableddisabled(intel_iommu_gfx_mapped);
#endif

	return msg;
}

void intel_device_info_print_static(const struct intel_device_info *info,
				    struct drm_printer *p)
{
	if (info->graphics_rel)
		drm_printf(p, "graphics version: %u.%02u\n", info->graphics_ver, info->graphics_rel);
	else
		drm_printf(p, "graphics version: %u\n", info->graphics_ver);

	if (info->media_rel)
		drm_printf(p, "media version: %u.%02u\n", info->media_ver, info->media_rel);
	else
		drm_printf(p, "media version: %u\n", info->media_ver);

	drm_printf(p, "display version: %u\n", info->display.ver);
	drm_printf(p, "gt: %d\n", info->gt);
	drm_printf(p, "iommu: %s\n", iommu_name());
	drm_printf(p, "memory-regions: %x\n", info->memory_regions);
	drm_printf(p, "page-sizes: %x\n", info->page_sizes);
	drm_printf(p, "platform: %s\n", intel_platform_name(info->platform));
	drm_printf(p, "ppgtt-size: %d\n", info->ppgtt_size);
	drm_printf(p, "ppgtt-type: %d\n", info->ppgtt_type);
	drm_printf(p, "dma_mask_size: %u\n", info->dma_mask_size);

#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, yesno(info->name))
	DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
#undef PRINT_FLAG

#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, yesno(info->display.name));
	DEV_INFO_DISPLAY_FOR_EACH_FLAG(PRINT_FLAG);
#undef PRINT_FLAG
}

void intel_device_info_print_runtime(const struct intel_runtime_info *info,
				     struct drm_printer *p)
{
	drm_printf(p, "rawclk rate: %u kHz\n", info->rawclk_freq);
}

#undef INTEL_VGA_DEVICE
#define INTEL_VGA_DEVICE(id, info) (id)

static const u16 subplatform_ult_ids[] = {
	INTEL_HSW_ULT_GT1_IDS(0),
	INTEL_HSW_ULT_GT2_IDS(0),
	INTEL_HSW_ULT_GT3_IDS(0),
	INTEL_BDW_ULT_GT1_IDS(0),
	INTEL_BDW_ULT_GT2_IDS(0),
	INTEL_BDW_ULT_GT3_IDS(0),
	INTEL_BDW_ULT_RSVD_IDS(0),
	INTEL_SKL_ULT_GT1_IDS(0),
	INTEL_SKL_ULT_GT2_IDS(0),
	INTEL_SKL_ULT_GT3_IDS(0),
	INTEL_KBL_ULT_GT1_IDS(0),
	INTEL_KBL_ULT_GT2_IDS(0),
	INTEL_KBL_ULT_GT3_IDS(0),
	INTEL_CFL_U_GT2_IDS(0),
	INTEL_CFL_U_GT3_IDS(0),
	INTEL_WHL_U_GT1_IDS(0),
	INTEL_WHL_U_GT2_IDS(0),
	INTEL_WHL_U_GT3_IDS(0),
	INTEL_CML_U_GT1_IDS(0),
	INTEL_CML_U_GT2_IDS(0),
};

static const u16 subplatform_ulx_ids[] = {
	INTEL_HSW_ULX_GT1_IDS(0),
	INTEL_HSW_ULX_GT2_IDS(0),
	INTEL_BDW_ULX_GT1_IDS(0),
	INTEL_BDW_ULX_GT2_IDS(0),
	INTEL_BDW_ULX_GT3_IDS(0),
	INTEL_BDW_ULX_RSVD_IDS(0),
	INTEL_SKL_ULX_GT1_IDS(0),
	INTEL_SKL_ULX_GT2_IDS(0),
	INTEL_KBL_ULX_GT1_IDS(0),
	INTEL_KBL_ULX_GT2_IDS(0),
	INTEL_AML_KBL_GT2_IDS(0),
	INTEL_AML_CFL_GT2_IDS(0),
};

static const u16 subplatform_portf_ids[] = {
	INTEL_ICL_PORT_F_IDS(0),
};

static const u16 subplatform_rpls_ids[] = {
	INTEL_RPLS_IDS(0),
};

static bool find_devid(u16 id, const u16 *p, unsigned int num)
{
	for (; num; num--, p++) {
		if (*p == id)
			return true;
	}

	return false;
}

void intel_device_info_subplatform_init(struct drm_i915_private *i915)
{
	const struct intel_device_info *info = INTEL_INFO(i915);
	const struct intel_runtime_info *rinfo = RUNTIME_INFO(i915);
	const unsigned int pi = __platform_mask_index(rinfo, info->platform);
	const unsigned int pb = __platform_mask_bit(rinfo, info->platform);
	u16 devid = INTEL_DEVID(i915);
	u32 mask = 0;

	/* Make sure IS_<platform> checks are working. */
	RUNTIME_INFO(i915)->platform_mask[pi] = BIT(pb);

	/* Find and mark subplatform bits based on the PCI device id. */
	if (find_devid(devid, subplatform_ult_ids,
		       ARRAY_SIZE(subplatform_ult_ids))) {
		mask = BIT(INTEL_SUBPLATFORM_ULT);
	} else if (find_devid(devid, subplatform_ulx_ids,
			      ARRAY_SIZE(subplatform_ulx_ids))) {
		mask = BIT(INTEL_SUBPLATFORM_ULX);
		if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
			/* ULX machines are also considered ULT. */
			mask |= BIT(INTEL_SUBPLATFORM_ULT);
		}
	} else if (find_devid(devid, subplatform_portf_ids,
			      ARRAY_SIZE(subplatform_portf_ids))) {
		mask = BIT(INTEL_SUBPLATFORM_PORTF);
	} else if (find_devid(devid, subplatform_rpls_ids,
			      ARRAY_SIZE(subplatform_rpls_ids))) {
		mask = BIT(INTEL_SUBPLATFORM_RPL_S);
	}

	if (IS_TIGERLAKE(i915)) {
		struct pci_dev *root, *pdev = to_pci_dev(i915->drm.dev);

		root = list_first_entry(&pdev->bus->devices, typeof(*root), bus_list);

		drm_WARN_ON(&i915->drm, mask);
		drm_WARN_ON(&i915->drm, (root->device & TGL_ROOT_DEVICE_MASK) !=
			    TGL_ROOT_DEVICE_ID);

		switch (root->device & TGL_ROOT_DEVICE_SKU_MASK) {
		case TGL_ROOT_DEVICE_SKU_ULX:
			mask = BIT(INTEL_SUBPLATFORM_ULX);
			break;
		case TGL_ROOT_DEVICE_SKU_ULT:
			mask = BIT(INTEL_SUBPLATFORM_ULT);
			break;
		}
	}

	GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_MASK);

	RUNTIME_INFO(i915)->platform_mask[pi] |= mask;
}

/**
 * intel_device_info_runtime_init - initialize runtime info
 * @dev_priv: the i915 device
 *
 * Determine various intel_device_info fields at runtime.
 *
 * Use it when either:
 *   - it's judged too laborious to fill n static structures with the limit
 *     when a simple if statement does the job,
 *   - run-time checks (eg read fuse/strap registers) are needed.
 *
 * This function needs to be called:
 *   - after the MMIO has been setup as we are reading registers,
 *   - after the PCH has been detected,
 *   - before the first usage of the fields it can tweak.
 */
void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
{
	struct intel_device_info *info = mkwrite_device_info(dev_priv);
	struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv);
	enum pipe pipe;

	/* Wa_14011765242: adl-s A0,A1 */
	if (IS_ADLS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A2))
		for_each_pipe(dev_priv, pipe)
			runtime->num_scalers[pipe] = 0;
	else if (DISPLAY_VER(dev_priv) >= 11) {
		for_each_pipe(dev_priv, pipe)
			runtime->num_scalers[pipe] = 2;
	} else if (DISPLAY_VER(dev_priv) >= 9) {
		runtime->num_scalers[PIPE_A] = 2;
		runtime->num_scalers[PIPE_B] = 2;
		runtime->num_scalers[PIPE_C] = 1;
	}

	BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES);

	if (DISPLAY_VER(dev_priv) >= 13 || HAS_D12_PLANE_MINIMIZATION(dev_priv))
		for_each_pipe(dev_priv, pipe)
			runtime->num_sprites[pipe] = 4;
	else if (DISPLAY_VER(dev_priv) >= 11)
		for_each_pipe(dev_priv, pipe)
			runtime->num_sprites[pipe] = 6;
	else if (DISPLAY_VER(dev_priv) == 10)
		for_each_pipe(dev_priv, pipe)
			runtime->num_sprites[pipe] = 3;
	else if (IS_BROXTON(dev_priv)) {
		/*
		 * Skylake and Broxton currently don't expose the topmost plane as its
		 * use is exclusive with the legacy cursor and we only want to expose
		 * one of those, not both. Until we can safely expose the topmost plane
		 * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported,
		 * we don't expose the topmost plane at all to prevent ABI breakage
		 * down the line.
		 */

		runtime->num_sprites[PIPE_A] = 2;
		runtime->num_sprites[PIPE_B] = 2;
		runtime->num_sprites[PIPE_C] = 1;
	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
		for_each_pipe(dev_priv, pipe)
			runtime->num_sprites[pipe] = 2;
	} else if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) {
		for_each_pipe(dev_priv, pipe)
			runtime->num_sprites[pipe] = 1;
	}

	if (HAS_DISPLAY(dev_priv) && IS_GRAPHICS_VER(dev_priv, 7, 8) &&
	    HAS_PCH_SPLIT(dev_priv)) {
		u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP);
		u32 sfuse_strap = intel_de_read(dev_priv, SFUSE_STRAP);

		/*
		 * SFUSE_STRAP is supposed to have a bit signalling the display
		 * is fused off. Unfortunately it seems that, at least in
		 * certain cases, fused off display means that PCH display
		 * reads don't land anywhere. In that case, we read 0s.
		 *
		 * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
		 * should be set when taking over after the firmware.
		 */
		if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
		    sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
		    (HAS_PCH_CPT(dev_priv) &&
		     !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
			drm_info(&dev_priv->drm,
				 "Display fused off, disabling\n");
			info->pipe_mask = 0;
			info->cpu_transcoder_mask = 0;
		} else if (fuse_strap & IVB_PIPE_C_DISABLE) {
			drm_info(&dev_priv->drm, "PipeC fused off\n");
			info->pipe_mask &= ~BIT(PIPE_C);
			info->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
		}
	} else if (HAS_DISPLAY(dev_priv) && DISPLAY_VER(dev_priv) >= 9) {
		u32 dfsm = intel_de_read(dev_priv, SKL_DFSM);

		if (dfsm & SKL_DFSM_PIPE_A_DISABLE) {
			info->pipe_mask &= ~BIT(PIPE_A);
			info->cpu_transcoder_mask &= ~BIT(TRANSCODER_A);
		}
		if (dfsm & SKL_DFSM_PIPE_B_DISABLE) {
			info->pipe_mask &= ~BIT(PIPE_B);
			info->cpu_transcoder_mask &= ~BIT(TRANSCODER_B);
		}
		if (dfsm & SKL_DFSM_PIPE_C_DISABLE) {
			info->pipe_mask &= ~BIT(PIPE_C);
			info->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
		}

		if (DISPLAY_VER(dev_priv) >= 12 &&
		    (dfsm & TGL_DFSM_PIPE_D_DISABLE)) {
			info->pipe_mask &= ~BIT(PIPE_D);
			info->cpu_transcoder_mask &= ~BIT(TRANSCODER_D);
		}

		if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE)
			info->display.has_hdcp = 0;

		if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE)
			info->display.has_fbc = 0;

		if (DISPLAY_VER(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))
			info->display.has_dmc = 0;

		if (DISPLAY_VER(dev_priv) >= 10 &&
		    (dfsm & GLK_DFSM_DISPLAY_DSC_DISABLE))
			info->display.has_dsc = 0;
	}

	if (GRAPHICS_VER(dev_priv) == 6 && intel_vtd_active()) {
		drm_info(&dev_priv->drm,
			 "Disabling ppGTT for VT-d support\n");
		info->ppgtt_type = INTEL_PPGTT_NONE;
	}

	runtime->rawclk_freq = intel_read_rawclk(dev_priv);
	drm_dbg(&dev_priv->drm, "rawclk rate: %d kHz\n", runtime->rawclk_freq);

	if (!HAS_DISPLAY(dev_priv)) {
		dev_priv->drm.driver_features &= ~(DRIVER_MODESET |
						   DRIVER_ATOMIC);
		memset(&info->display, 0, sizeof(info->display));
		memset(runtime->num_sprites, 0, sizeof(runtime->num_sprites));
		memset(runtime->num_scalers, 0, sizeof(runtime->num_scalers));
	}
}

void intel_driver_caps_print(const struct intel_driver_caps *caps,
			     struct drm_printer *p)
{
	drm_printf(p, "Has logical contexts? %s\n",
		   yesno(caps->has_logical_contexts));
	drm_printf(p, "scheduler: %x\n", caps->scheduler);
}
Commit	Line	Data
94b4f3ba CW	1	/*
	2	* Copyright © 2016 Intel Corporation
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
	21	* IN THE SOFTWARE.
	22	*
	23	*/
	24
a8c9b849	25	#include <drm/drm_print.h>
83d2bdb6	26	#include <drm/i915_pciids.h>
a8c9b849	27
b04002f4	28	#include "display/intel_cdclk.h"
fdeb6d02	29	#include "display/intel_de.h"
b978520d	30	#include "intel_device_info.h"
94b4f3ba CW	31	#include "i915_drv.h"
94b4f3ba CW	32
2e0d26f8 JN	33	#define PLATFORM_NAME(x) [INTEL_##x] = #x
	34	static const char * const platform_names[] = {
	35	PLATFORM_NAME(I830),
	36	PLATFORM_NAME(I845G),
	37	PLATFORM_NAME(I85X),
	38	PLATFORM_NAME(I865G),
	39	PLATFORM_NAME(I915G),
	40	PLATFORM_NAME(I915GM),
	41	PLATFORM_NAME(I945G),
	42	PLATFORM_NAME(I945GM),
	43	PLATFORM_NAME(G33),
	44	PLATFORM_NAME(PINEVIEW),
c0f86832 JN	45	PLATFORM_NAME(I965G),
c0f86832 JN	46	PLATFORM_NAME(I965GM),
f69c11ae JN	47	PLATFORM_NAME(G45),
f69c11ae JN	48	PLATFORM_NAME(GM45),
2e0d26f8 JN	49	PLATFORM_NAME(IRONLAKE),
	50	PLATFORM_NAME(SANDYBRIDGE),
	51	PLATFORM_NAME(IVYBRIDGE),
	52	PLATFORM_NAME(VALLEYVIEW),
	53	PLATFORM_NAME(HASWELL),
	54	PLATFORM_NAME(BROADWELL),
	55	PLATFORM_NAME(CHERRYVIEW),
	56	PLATFORM_NAME(SKYLAKE),
	57	PLATFORM_NAME(BROXTON),
	58	PLATFORM_NAME(KABYLAKE),
	59	PLATFORM_NAME(GEMINILAKE),
71851fa8	60	PLATFORM_NAME(COFFEELAKE),
5f4ae270	61	PLATFORM_NAME(COMETLAKE),
41231001	62	PLATFORM_NAME(ICELAKE),
897f2961	63	PLATFORM_NAME(ELKHARTLAKE),
24ea098b	64	PLATFORM_NAME(JASPERLAKE),
abd3a0fe	65	PLATFORM_NAME(TIGERLAKE),
123f62de	66	PLATFORM_NAME(ROCKETLAKE),
05e26584	67	PLATFORM_NAME(DG1),
0883d63b	68	PLATFORM_NAME(ALDERLAKE_S),
bdd27cad	69	PLATFORM_NAME(ALDERLAKE_P),
086df54e	70	PLATFORM_NAME(XEHPSDV),
9e22cfc5	71	PLATFORM_NAME(DG2),
2e0d26f8 JN	72	};
	73	#undef PLATFORM_NAME
	74
	75	const char *intel_platform_name(enum intel_platform platform)
	76	{
9160095c JN	77	BUILD_BUG_ON(ARRAY_SIZE(platform_names) != INTEL_MAX_PLATFORMS);
9160095c JN	78
2e0d26f8 JN	79	if (WARN_ON_ONCE(platform >= ARRAY_SIZE(platform_names) \|\|
	80	platform_names[platform] == NULL))
	81	return "<unknown>";
	82
	83	return platform_names[platform];
	84	}
	85
72404978	86	static const char *iommu_name(void)
a8c9b849	87	{
72404978 CW	88	const char *msg = "n/a";
	89
	90	#ifdef CONFIG_INTEL_IOMMU
	91	msg = enableddisabled(intel_iommu_gfx_mapped);
	92	#endif
	93
	94	return msg;
	95	}
	96
	97	void intel_device_info_print_static(const struct intel_device_info *info,
	98	struct drm_printer *p)
	99	{
ca6374e2 LDM	100	if (info->graphics_rel)
	101	drm_printf(p, "graphics version: %u.%02u\n", info->graphics_ver, info->graphics_rel);
	102	else
	103	drm_printf(p, "graphics version: %u\n", info->graphics_ver);
	104
	105	if (info->media_rel)
	106	drm_printf(p, "media version: %u.%02u\n", info->media_ver, info->media_rel);
	107	else
	108	drm_printf(p, "media version: %u\n", info->media_ver);
	109
0f9b145a	110	drm_printf(p, "display version: %u\n", info->display.ver);
72404978 CW	111	drm_printf(p, "gt: %d\n", info->gt);
	112	drm_printf(p, "iommu: %s\n", iommu_name());
	113	drm_printf(p, "memory-regions: %x\n", info->memory_regions);
	114	drm_printf(p, "page-sizes: %x\n", info->page_sizes);
	115	drm_printf(p, "platform: %s\n", intel_platform_name(info->platform));
	116	drm_printf(p, "ppgtt-size: %d\n", info->ppgtt_size);
	117	drm_printf(p, "ppgtt-type: %d\n", info->ppgtt_type);
31a02eb7	118	drm_printf(p, "dma_mask_size: %u\n", info->dma_mask_size);
72404978	119
c33f83fd	120	#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, yesno(info->name))
a8c9b849 MW	121	DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
a8c9b849 MW	122	#undef PRINT_FLAG
d53db442 JRS	123
	124	#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, yesno(info->display.name));
	125	DEV_INFO_DISPLAY_FOR_EACH_FLAG(PRINT_FLAG);
	126	#undef PRINT_FLAG
a8c9b849 MW	127	}
a8c9b849 MW	128
72404978 CW	129	void intel_device_info_print_runtime(const struct intel_runtime_info *info,
72404978 CW	130	struct drm_printer *p)
5fbbe8d4	131	{
b04002f4	132	drm_printf(p, "rawclk rate: %u kHz\n", info->rawclk_freq);
dab91783 LL	133	}
dab91783 LL	134
805446c8 TU	135	#undef INTEL_VGA_DEVICE
	136	#define INTEL_VGA_DEVICE(id, info) (id)
	137
	138	static const u16 subplatform_ult_ids[] = {
	139	INTEL_HSW_ULT_GT1_IDS(0),
	140	INTEL_HSW_ULT_GT2_IDS(0),
	141	INTEL_HSW_ULT_GT3_IDS(0),
	142	INTEL_BDW_ULT_GT1_IDS(0),
	143	INTEL_BDW_ULT_GT2_IDS(0),
	144	INTEL_BDW_ULT_GT3_IDS(0),
	145	INTEL_BDW_ULT_RSVD_IDS(0),
	146	INTEL_SKL_ULT_GT1_IDS(0),
	147	INTEL_SKL_ULT_GT2_IDS(0),
	148	INTEL_SKL_ULT_GT3_IDS(0),
	149	INTEL_KBL_ULT_GT1_IDS(0),
	150	INTEL_KBL_ULT_GT2_IDS(0),
	151	INTEL_KBL_ULT_GT3_IDS(0),
	152	INTEL_CFL_U_GT2_IDS(0),
	153	INTEL_CFL_U_GT3_IDS(0),
	154	INTEL_WHL_U_GT1_IDS(0),
	155	INTEL_WHL_U_GT2_IDS(0),
c3ad8d29	156	INTEL_WHL_U_GT3_IDS(0),
8717c6b7 LS	157	INTEL_CML_U_GT1_IDS(0),
8717c6b7 LS	158	INTEL_CML_U_GT2_IDS(0),
805446c8 TU	159	};
	160
	161	static const u16 subplatform_ulx_ids[] = {
	162	INTEL_HSW_ULX_GT1_IDS(0),
	163	INTEL_HSW_ULX_GT2_IDS(0),
	164	INTEL_BDW_ULX_GT1_IDS(0),
	165	INTEL_BDW_ULX_GT2_IDS(0),
	166	INTEL_BDW_ULX_GT3_IDS(0),
	167	INTEL_BDW_ULX_RSVD_IDS(0),
	168	INTEL_SKL_ULX_GT1_IDS(0),
	169	INTEL_SKL_ULX_GT2_IDS(0),
	170	INTEL_KBL_ULX_GT1_IDS(0),
c3ad8d29	171	INTEL_KBL_ULX_GT2_IDS(0),
805446c8	172	INTEL_AML_KBL_GT2_IDS(0),
c3ad8d29	173	INTEL_AML_CFL_GT2_IDS(0),
805446c8 TU	174	};
	175
	176	static const u16 subplatform_portf_ids[] = {
c3ad8d29	177	INTEL_ICL_PORT_F_IDS(0),
805446c8 TU	178	};
805446c8 TU	179
52407c22 AS	180	static const u16 subplatform_rpls_ids[] = {
	181	INTEL_RPLS_IDS(0),
	182	};
	183
805446c8 TU	184	static bool find_devid(u16 id, const u16 *p, unsigned int num)
	185	{
	186	for (; num; num--, p++) {
	187	if (*p == id)
	188	return true;
	189	}
	190
	191	return false;
	192	}
	193
	194	void intel_device_info_subplatform_init(struct drm_i915_private *i915)
	195	{
	196	const struct intel_device_info *info = INTEL_INFO(i915);
	197	const struct intel_runtime_info *rinfo = RUNTIME_INFO(i915);
	198	const unsigned int pi = __platform_mask_index(rinfo, info->platform);
	199	const unsigned int pb = __platform_mask_bit(rinfo, info->platform);
	200	u16 devid = INTEL_DEVID(i915);
640cde65	201	u32 mask = 0;
805446c8 TU	202
	203	/* Make sure IS_<platform> checks are working. */
	204	RUNTIME_INFO(i915)->platform_mask[pi] = BIT(pb);
	205
	206	/* Find and mark subplatform bits based on the PCI device id. */
	207	if (find_devid(devid, subplatform_ult_ids,
	208	ARRAY_SIZE(subplatform_ult_ids))) {
	209	mask = BIT(INTEL_SUBPLATFORM_ULT);
	210	} else if (find_devid(devid, subplatform_ulx_ids,
	211	ARRAY_SIZE(subplatform_ulx_ids))) {
	212	mask = BIT(INTEL_SUBPLATFORM_ULX);
	213	if (IS_HASWELL(i915) \|\| IS_BROADWELL(i915)) {
	214	/* ULX machines are also considered ULT. */
	215	mask \|= BIT(INTEL_SUBPLATFORM_ULT);
	216	}
805446c8 TU	217	} else if (find_devid(devid, subplatform_portf_ids,
	218	ARRAY_SIZE(subplatform_portf_ids))) {
	219	mask = BIT(INTEL_SUBPLATFORM_PORTF);
52407c22 AS	220	} else if (find_devid(devid, subplatform_rpls_ids,
	221	ARRAY_SIZE(subplatform_rpls_ids))) {
	222	mask = BIT(INTEL_SUBPLATFORM_RPL_S);
805446c8 TU	223	}
805446c8 TU	224
1d3cc7ab	225	if (IS_TIGERLAKE(i915)) {
8ff5446a	226	struct pci_dev root, pdev = to_pci_dev(i915->drm.dev);
1d3cc7ab JRS	227
	228	root = list_first_entry(&pdev->bus->devices, typeof(*root), bus_list);
	229
	230	drm_WARN_ON(&i915->drm, mask);
	231	drm_WARN_ON(&i915->drm, (root->device & TGL_ROOT_DEVICE_MASK) !=
	232	TGL_ROOT_DEVICE_ID);
	233
	234	switch (root->device & TGL_ROOT_DEVICE_SKU_MASK) {
	235	case TGL_ROOT_DEVICE_SKU_ULX:
	236	mask = BIT(INTEL_SUBPLATFORM_ULX);
	237	break;
	238	case TGL_ROOT_DEVICE_SKU_ULT:
	239	mask = BIT(INTEL_SUBPLATFORM_ULT);
	240	break;
	241	}
	242	}
	243
56afa701	244	GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_MASK);
805446c8 TU	245
	246	RUNTIME_INFO(i915)->platform_mask[pi] \|= mask;
	247	}
	248
6a7e51f3 MW	249	/**
6a7e51f3 MW	250	* intel_device_info_runtime_init - initialize runtime info
963cc126	251	* @dev_priv: the i915 device
6a7e51f3	252	*
94b4f3ba CW	253	* Determine various intel_device_info fields at runtime.
	254	*
	255	* Use it when either:
	256	* - it's judged too laborious to fill n static structures with the limit
	257	* when a simple if statement does the job,
	258	* - run-time checks (eg read fuse/strap registers) are needed.
	259	*
	260	* This function needs to be called:
	261	* - after the MMIO has been setup as we are reading registers,
	262	* - after the PCH has been detected,
	263	* - before the first usage of the fields it can tweak.
	264	*/
1400cc7e	265	void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
94b4f3ba	266	{
1400cc7e	267	struct intel_device_info *info = mkwrite_device_info(dev_priv);
0258404f	268	struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv);
94b4f3ba CW	269	enum pipe pipe;
94b4f3ba CW	270
8ff36e02	271	/* Wa_14011765242: adl-s A0,A1 */
46b0d709	272	if (IS_ADLS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A2))
ea27113e AS	273	for_each_pipe(dev_priv, pipe)
ea27113e AS	274	runtime->num_scalers[pipe] = 0;
4c6b3021	275	else if (DISPLAY_VER(dev_priv) >= 11) {
6e7406db	276	for_each_pipe(dev_priv, pipe)
0258404f	277	runtime->num_scalers[pipe] = 2;
4c6b3021	278	} else if (DISPLAY_VER(dev_priv) >= 9) {
0258404f JN	279	runtime->num_scalers[PIPE_A] = 2;
	280	runtime->num_scalers[PIPE_B] = 2;
	281	runtime->num_scalers[PIPE_C] = 1;
0bf0230e ACO	282	}
0bf0230e ACO	283
8a68d464	284	BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES);
022d3093	285
1649a4cc	286	if (DISPLAY_VER(dev_priv) >= 13 \|\| HAS_D12_PLANE_MINIMIZATION(dev_priv))
99e2d8bc MR	287	for_each_pipe(dev_priv, pipe)
99e2d8bc MR	288	runtime->num_sprites[pipe] = 4;
4c6b3021	289	else if (DISPLAY_VER(dev_priv) >= 11)
6711bd73	290	for_each_pipe(dev_priv, pipe)
0258404f	291	runtime->num_sprites[pipe] = 6;
4c6b3021	292	else if (DISPLAY_VER(dev_priv) == 10)
e9c98825	293	for_each_pipe(dev_priv, pipe)
0258404f	294	runtime->num_sprites[pipe] = 3;
e9c98825	295	else if (IS_BROXTON(dev_priv)) {
6711bd73 ML	296	/*
	297	* Skylake and Broxton currently don't expose the topmost plane as its
	298	* use is exclusive with the legacy cursor and we only want to expose
	299	* one of those, not both. Until we can safely expose the topmost plane
	300	* as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported,
	301	* we don't expose the topmost plane at all to prevent ABI breakage
	302	* down the line.
	303	*/
	304
0258404f JN	305	runtime->num_sprites[PIPE_A] = 2;
	306	runtime->num_sprites[PIPE_B] = 2;
	307	runtime->num_sprites[PIPE_C] = 1;
33edc24d	308	} else if (IS_VALLEYVIEW(dev_priv) \|\| IS_CHERRYVIEW(dev_priv)) {
94b4f3ba	309	for_each_pipe(dev_priv, pipe)
0258404f	310	runtime->num_sprites[pipe] = 2;
4c6b3021	311	} else if (DISPLAY_VER(dev_priv) >= 5 \|\| IS_G4X(dev_priv)) {
94b4f3ba	312	for_each_pipe(dev_priv, pipe)
0258404f	313	runtime->num_sprites[pipe] = 1;
33edc24d	314	}
94b4f3ba	315
651e7d48	316	if (HAS_DISPLAY(dev_priv) && IS_GRAPHICS_VER(dev_priv, 7, 8) &&
ef404bc6	317	HAS_PCH_SPLIT(dev_priv)) {
fdeb6d02 DCS	318	u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP);
fdeb6d02 DCS	319	u32 sfuse_strap = intel_de_read(dev_priv, SFUSE_STRAP);
94b4f3ba CW	320
	321	/*
	322	* SFUSE_STRAP is supposed to have a bit signalling the display
	323	* is fused off. Unfortunately it seems that, at least in
	324	* certain cases, fused off display means that PCH display
	325	* reads don't land anywhere. In that case, we read 0s.
	326	*
	327	* On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
	328	* should be set when taking over after the firmware.
	329	*/
	330	if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE \|\|
	331	sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED \|\|
b9eb89b2	332	(HAS_PCH_CPT(dev_priv) &&
94b4f3ba	333	!(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
68b32717 WK	334	drm_info(&dev_priv->drm,
68b32717 WK	335	"Display fused off, disabling\n");
8d8b0031	336	info->pipe_mask = 0;
10cf8e75	337	info->cpu_transcoder_mask = 0;
94b4f3ba	338	} else if (fuse_strap & IVB_PIPE_C_DISABLE) {
68b32717	339	drm_info(&dev_priv->drm, "PipeC fused off\n");
8d8b0031	340	info->pipe_mask &= ~BIT(PIPE_C);
10cf8e75	341	info->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
94b4f3ba	342	}
4fd17728	343	} else if (HAS_DISPLAY(dev_priv) && DISPLAY_VER(dev_priv) >= 9) {
fdeb6d02	344	u32 dfsm = intel_de_read(dev_priv, SKL_DFSM);
94b4f3ba	345
10cf8e75 VS	346	if (dfsm & SKL_DFSM_PIPE_A_DISABLE) {
	347	info->pipe_mask &= ~BIT(PIPE_A);
	348	info->cpu_transcoder_mask &= ~BIT(TRANSCODER_A);
	349	}
	350	if (dfsm & SKL_DFSM_PIPE_B_DISABLE) {
	351	info->pipe_mask &= ~BIT(PIPE_B);
	352	info->cpu_transcoder_mask &= ~BIT(TRANSCODER_B);
	353	}
	354	if (dfsm & SKL_DFSM_PIPE_C_DISABLE) {
	355	info->pipe_mask &= ~BIT(PIPE_C);
	356	info->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
	357	}
4fd17728 LDM	358
4fd17728 LDM	359	if (DISPLAY_VER(dev_priv) >= 12 &&
10cf8e75 VS	360	(dfsm & TGL_DFSM_PIPE_D_DISABLE)) {
	361	info->pipe_mask &= ~BIT(PIPE_D);
	362	info->cpu_transcoder_mask &= ~BIT(TRANSCODER_D);
	363	}
74393109 JRS	364
	365	if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE)
	366	info->display.has_hdcp = 0;
7a40aac1 JRS	367
	368	if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE)
	369	info->display.has_fbc = 0;
ee595888	370
4fd17728	371	if (DISPLAY_VER(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))
ec2b1485	372	info->display.has_dmc = 0;
0f9ed3b2	373
4fd17728	374	if (DISPLAY_VER(dev_priv) >= 10 &&
a4d082fc	375	(dfsm & GLK_DFSM_DISPLAY_DSC_DISABLE))
0f9ed3b2	376	info->display.has_dsc = 0;
94b4f3ba CW	377	}
94b4f3ba CW	378
651e7d48	379	if (GRAPHICS_VER(dev_priv) == 6 && intel_vtd_active()) {
68b32717 WK	380	drm_info(&dev_priv->drm,
68b32717 WK	381	"Disabling ppGTT for VT-d support\n");
cbecbcca	382	info->ppgtt_type = INTEL_PPGTT_NONE;
4bdafb9d CW	383	}
4bdafb9d CW	384
b04002f4 CW	385	runtime->rawclk_freq = intel_read_rawclk(dev_priv);
	386	drm_dbg(&dev_priv->drm, "rawclk rate: %d kHz\n", runtime->rawclk_freq);
	387
5e0e390d JN	388	if (!HAS_DISPLAY(dev_priv)) {
	389	dev_priv->drm.driver_features &= ~(DRIVER_MODESET \|
	390	DRIVER_ATOMIC);
	391	memset(&info->display, 0, sizeof(info->display));
	392	memset(runtime->num_sprites, 0, sizeof(runtime->num_sprites));
	393	memset(runtime->num_scalers, 0, sizeof(runtime->num_scalers));
	394	}
94b4f3ba	395	}
3fed1808 CW	396
	397	void intel_driver_caps_print(const struct intel_driver_caps *caps,
	398	struct drm_printer *p)
	399	{
481827b4 CW	400	drm_printf(p, "Has logical contexts? %s\n",
481827b4 CW	401	yesno(caps->has_logical_contexts));
3fed1808 CW	402	drm_printf(p, "scheduler: %x\n", caps->scheduler);
3fed1808 CW	403	}