[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_device_info.c

/*
 * Copyright © 2016 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 */

#include <drm/drm_print.h>
#include <drm/i915_pciids.h>

#include "display/intel_cdclk.h"
#include "display/intel_de.h"
#include "intel_device_info.h"
#include "i915_drv.h"

#define PLATFORM_NAME(x) [INTEL_##x] = #x
static const char * const platform_names[] = {
	PLATFORM_NAME(I830),
	PLATFORM_NAME(I845G),
	PLATFORM_NAME(I85X),
	PLATFORM_NAME(I865G),
	PLATFORM_NAME(I915G),
	PLATFORM_NAME(I915GM),
	PLATFORM_NAME(I945G),
	PLATFORM_NAME(I945GM),
	PLATFORM_NAME(G33),
	PLATFORM_NAME(PINEVIEW),
	PLATFORM_NAME(I965G),
	PLATFORM_NAME(I965GM),
	PLATFORM_NAME(G45),
	PLATFORM_NAME(GM45),
	PLATFORM_NAME(IRONLAKE),
	PLATFORM_NAME(SANDYBRIDGE),
	PLATFORM_NAME(IVYBRIDGE),
	PLATFORM_NAME(VALLEYVIEW),
	PLATFORM_NAME(HASWELL),
	PLATFORM_NAME(BROADWELL),
	PLATFORM_NAME(CHERRYVIEW),
	PLATFORM_NAME(SKYLAKE),
	PLATFORM_NAME(BROXTON),
	PLATFORM_NAME(KABYLAKE),
	PLATFORM_NAME(GEMINILAKE),
	PLATFORM_NAME(COFFEELAKE),
	PLATFORM_NAME(COMETLAKE),
	PLATFORM_NAME(CANNONLAKE),
	PLATFORM_NAME(ICELAKE),
	PLATFORM_NAME(ELKHARTLAKE),
	PLATFORM_NAME(JASPERLAKE),
	PLATFORM_NAME(TIGERLAKE),
	PLATFORM_NAME(ROCKETLAKE),
	PLATFORM_NAME(DG1),
	PLATFORM_NAME(ALDERLAKE_S),
	PLATFORM_NAME(ALDERLAKE_P),
};
#undef PLATFORM_NAME

const char *intel_platform_name(enum intel_platform platform)
{
	BUILD_BUG_ON(ARRAY_SIZE(platform_names) != INTEL_MAX_PLATFORMS);

	if (WARN_ON_ONCE(platform >= ARRAY_SIZE(platform_names) ||
			 platform_names[platform] == NULL))
		return "<unknown>";

	return platform_names[platform];
}

static const char *iommu_name(void)
{
	const char *msg = "n/a";

#ifdef CONFIG_INTEL_IOMMU
	msg = enableddisabled(intel_iommu_gfx_mapped);
#endif

	return msg;
}

void intel_device_info_print_static(const struct intel_device_info *info,
				    struct drm_printer *p)
{
	drm_printf(p, "graphics version: %u\n", info->graphics_ver);
	drm_printf(p, "media version: %u\n", info->media_ver);
	drm_printf(p, "display version: %u\n", info->display.ver);
	drm_printf(p, "gt: %d\n", info->gt);
	drm_printf(p, "iommu: %s\n", iommu_name());
	drm_printf(p, "memory-regions: %x\n", info->memory_regions);
	drm_printf(p, "page-sizes: %x\n", info->page_sizes);
	drm_printf(p, "platform: %s\n", intel_platform_name(info->platform));
	drm_printf(p, "ppgtt-size: %d\n", info->ppgtt_size);
	drm_printf(p, "ppgtt-type: %d\n", info->ppgtt_type);
	drm_printf(p, "dma_mask_size: %u\n", info->dma_mask_size);

#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, yesno(info->name))
	DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
#undef PRINT_FLAG

#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, yesno(info->display.name));
	DEV_INFO_DISPLAY_FOR_EACH_FLAG(PRINT_FLAG);
#undef PRINT_FLAG
}

void intel_device_info_print_runtime(const struct intel_runtime_info *info,
				     struct drm_printer *p)
{
	drm_printf(p, "rawclk rate: %u kHz\n", info->rawclk_freq);
}

#undef INTEL_VGA_DEVICE
#define INTEL_VGA_DEVICE(id, info) (id)

static const u16 subplatform_ult_ids[] = {
	INTEL_HSW_ULT_GT1_IDS(0),
	INTEL_HSW_ULT_GT2_IDS(0),
	INTEL_HSW_ULT_GT3_IDS(0),
	INTEL_BDW_ULT_GT1_IDS(0),
	INTEL_BDW_ULT_GT2_IDS(0),
	INTEL_BDW_ULT_GT3_IDS(0),
	INTEL_BDW_ULT_RSVD_IDS(0),
	INTEL_SKL_ULT_GT1_IDS(0),
	INTEL_SKL_ULT_GT2_IDS(0),
	INTEL_SKL_ULT_GT3_IDS(0),
	INTEL_KBL_ULT_GT1_IDS(0),
	INTEL_KBL_ULT_GT2_IDS(0),
	INTEL_KBL_ULT_GT3_IDS(0),
	INTEL_CFL_U_GT2_IDS(0),
	INTEL_CFL_U_GT3_IDS(0),
	INTEL_WHL_U_GT1_IDS(0),
	INTEL_WHL_U_GT2_IDS(0),
	INTEL_WHL_U_GT3_IDS(0),
	INTEL_CML_U_GT1_IDS(0),
	INTEL_CML_U_GT2_IDS(0),
};

static const u16 subplatform_ulx_ids[] = {
	INTEL_HSW_ULX_GT1_IDS(0),
	INTEL_HSW_ULX_GT2_IDS(0),
	INTEL_BDW_ULX_GT1_IDS(0),
	INTEL_BDW_ULX_GT2_IDS(0),
	INTEL_BDW_ULX_GT3_IDS(0),
	INTEL_BDW_ULX_RSVD_IDS(0),
	INTEL_SKL_ULX_GT1_IDS(0),
	INTEL_SKL_ULX_GT2_IDS(0),
	INTEL_KBL_ULX_GT1_IDS(0),
	INTEL_KBL_ULX_GT2_IDS(0),
	INTEL_AML_KBL_GT2_IDS(0),
	INTEL_AML_CFL_GT2_IDS(0),
};

static const u16 subplatform_portf_ids[] = {
	INTEL_CNL_PORT_F_IDS(0),
	INTEL_ICL_PORT_F_IDS(0),
};

static bool find_devid(u16 id, const u16 *p, unsigned int num)
{
	for (; num; num--, p++) {
		if (*p == id)
			return true;
	}

	return false;
}

void intel_device_info_subplatform_init(struct drm_i915_private *i915)
{
	const struct intel_device_info *info = INTEL_INFO(i915);
	const struct intel_runtime_info *rinfo = RUNTIME_INFO(i915);
	const unsigned int pi = __platform_mask_index(rinfo, info->platform);
	const unsigned int pb = __platform_mask_bit(rinfo, info->platform);
	u16 devid = INTEL_DEVID(i915);
	u32 mask = 0;

	/* Make sure IS_<platform> checks are working. */
	RUNTIME_INFO(i915)->platform_mask[pi] = BIT(pb);

	/* Find and mark subplatform bits based on the PCI device id. */
	if (find_devid(devid, subplatform_ult_ids,
		       ARRAY_SIZE(subplatform_ult_ids))) {
		mask = BIT(INTEL_SUBPLATFORM_ULT);
	} else if (find_devid(devid, subplatform_ulx_ids,
			      ARRAY_SIZE(subplatform_ulx_ids))) {
		mask = BIT(INTEL_SUBPLATFORM_ULX);
		if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
			/* ULX machines are also considered ULT. */
			mask |= BIT(INTEL_SUBPLATFORM_ULT);
		}
	} else if (find_devid(devid, subplatform_portf_ids,
			      ARRAY_SIZE(subplatform_portf_ids))) {
		mask = BIT(INTEL_SUBPLATFORM_PORTF);
	}

	if (IS_TIGERLAKE(i915)) {
		struct pci_dev *root, *pdev = to_pci_dev(i915->drm.dev);

		root = list_first_entry(&pdev->bus->devices, typeof(*root), bus_list);

		drm_WARN_ON(&i915->drm, mask);
		drm_WARN_ON(&i915->drm, (root->device & TGL_ROOT_DEVICE_MASK) !=
			    TGL_ROOT_DEVICE_ID);

		switch (root->device & TGL_ROOT_DEVICE_SKU_MASK) {
		case TGL_ROOT_DEVICE_SKU_ULX:
			mask = BIT(INTEL_SUBPLATFORM_ULX);
			break;
		case TGL_ROOT_DEVICE_SKU_ULT:
			mask = BIT(INTEL_SUBPLATFORM_ULT);
			break;
		}
	}

	GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_MASK);

	RUNTIME_INFO(i915)->platform_mask[pi] |= mask;
}

/**
 * intel_device_info_runtime_init - initialize runtime info
 * @dev_priv: the i915 device
 *
 * Determine various intel_device_info fields at runtime.
 *
 * Use it when either:
 *   - it's judged too laborious to fill n static structures with the limit
 *     when a simple if statement does the job,
 *   - run-time checks (eg read fuse/strap registers) are needed.
 *
 * This function needs to be called:
 *   - after the MMIO has been setup as we are reading registers,
 *   - after the PCH has been detected,
 *   - before the first usage of the fields it can tweak.
 */
void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
{
	struct intel_device_info *info = mkwrite_device_info(dev_priv);
	struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv);
	enum pipe pipe;

	/* Wa_14011765242: adl-s A0 */
	if (IS_ADLS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
		for_each_pipe(dev_priv, pipe)
			runtime->num_scalers[pipe] = 0;
	else if (GRAPHICS_VER(dev_priv) >= 10) {
		for_each_pipe(dev_priv, pipe)
			runtime->num_scalers[pipe] = 2;
	} else if (GRAPHICS_VER(dev_priv) == 9) {
		runtime->num_scalers[PIPE_A] = 2;
		runtime->num_scalers[PIPE_B] = 2;
		runtime->num_scalers[PIPE_C] = 1;
	}

	BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES);

	if (DISPLAY_VER(dev_priv) >= 13 || HAS_D12_PLANE_MINIMIZATION(dev_priv))
		for_each_pipe(dev_priv, pipe)
			runtime->num_sprites[pipe] = 4;
	else if (GRAPHICS_VER(dev_priv) >= 11)
		for_each_pipe(dev_priv, pipe)
			runtime->num_sprites[pipe] = 6;
	else if (GRAPHICS_VER(dev_priv) == 10 || IS_GEMINILAKE(dev_priv))
		for_each_pipe(dev_priv, pipe)
			runtime->num_sprites[pipe] = 3;
	else if (IS_BROXTON(dev_priv)) {
		/*
		 * Skylake and Broxton currently don't expose the topmost plane as its
		 * use is exclusive with the legacy cursor and we only want to expose
		 * one of those, not both. Until we can safely expose the topmost plane
		 * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported,
		 * we don't expose the topmost plane at all to prevent ABI breakage
		 * down the line.
		 */

		runtime->num_sprites[PIPE_A] = 2;
		runtime->num_sprites[PIPE_B] = 2;
		runtime->num_sprites[PIPE_C] = 1;
	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
		for_each_pipe(dev_priv, pipe)
			runtime->num_sprites[pipe] = 2;
	} else if (GRAPHICS_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) {
		for_each_pipe(dev_priv, pipe)
			runtime->num_sprites[pipe] = 1;
	}

	if (HAS_DISPLAY(dev_priv) && IS_GRAPHICS_VER(dev_priv, 7, 8) &&
	    HAS_PCH_SPLIT(dev_priv)) {
		u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP);
		u32 sfuse_strap = intel_de_read(dev_priv, SFUSE_STRAP);

		/*
		 * SFUSE_STRAP is supposed to have a bit signalling the display
		 * is fused off. Unfortunately it seems that, at least in
		 * certain cases, fused off display means that PCH display
		 * reads don't land anywhere. In that case, we read 0s.
		 *
		 * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
		 * should be set when taking over after the firmware.
		 */
		if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
		    sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
		    (HAS_PCH_CPT(dev_priv) &&
		     !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
			drm_info(&dev_priv->drm,
				 "Display fused off, disabling\n");
			info->pipe_mask = 0;
			info->cpu_transcoder_mask = 0;
		} else if (fuse_strap & IVB_PIPE_C_DISABLE) {
			drm_info(&dev_priv->drm, "PipeC fused off\n");
			info->pipe_mask &= ~BIT(PIPE_C);
			info->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
		}
	} else if (HAS_DISPLAY(dev_priv) && GRAPHICS_VER(dev_priv) >= 9) {
		u32 dfsm = intel_de_read(dev_priv, SKL_DFSM);

		if (dfsm & SKL_DFSM_PIPE_A_DISABLE) {
			info->pipe_mask &= ~BIT(PIPE_A);
			info->cpu_transcoder_mask &= ~BIT(TRANSCODER_A);
		}
		if (dfsm & SKL_DFSM_PIPE_B_DISABLE) {
			info->pipe_mask &= ~BIT(PIPE_B);
			info->cpu_transcoder_mask &= ~BIT(TRANSCODER_B);
		}
		if (dfsm & SKL_DFSM_PIPE_C_DISABLE) {
			info->pipe_mask &= ~BIT(PIPE_C);
			info->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
		}
		if (GRAPHICS_VER(dev_priv) >= 12 &&
		    (dfsm & TGL_DFSM_PIPE_D_DISABLE)) {
			info->pipe_mask &= ~BIT(PIPE_D);
			info->cpu_transcoder_mask &= ~BIT(TRANSCODER_D);
		}

		if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE)
			info->display.has_hdcp = 0;

		if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE)
			info->display.has_fbc = 0;

		if (GRAPHICS_VER(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))
			info->display.has_dmc = 0;

		if (GRAPHICS_VER(dev_priv) >= 10 &&
		    (dfsm & CNL_DFSM_DISPLAY_DSC_DISABLE))
			info->display.has_dsc = 0;
	}

	if (GRAPHICS_VER(dev_priv) == 6 && intel_vtd_active()) {
		drm_info(&dev_priv->drm,
			 "Disabling ppGTT for VT-d support\n");
		info->ppgtt_type = INTEL_PPGTT_NONE;
	}

	runtime->rawclk_freq = intel_read_rawclk(dev_priv);
	drm_dbg(&dev_priv->drm, "rawclk rate: %d kHz\n", runtime->rawclk_freq);

	if (!HAS_DISPLAY(dev_priv)) {
		dev_priv->drm.driver_features &= ~(DRIVER_MODESET |
						   DRIVER_ATOMIC);
		memset(&info->display, 0, sizeof(info->display));
		memset(runtime->num_sprites, 0, sizeof(runtime->num_sprites));
		memset(runtime->num_scalers, 0, sizeof(runtime->num_scalers));
	}
}

void intel_driver_caps_print(const struct intel_driver_caps *caps,
			     struct drm_printer *p)
{
	drm_printf(p, "Has logical contexts? %s\n",
		   yesno(caps->has_logical_contexts));
	drm_printf(p, "scheduler: %x\n", caps->scheduler);
}
Commit	Line	Data
94b4f3ba CW	1	/*
	2	* Copyright © 2016 Intel Corporation
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
	21	* IN THE SOFTWARE.
	22	*
	23	*/
	24
a8c9b849	25	#include <drm/drm_print.h>
83d2bdb6	26	#include <drm/i915_pciids.h>
a8c9b849	27
b04002f4	28	#include "display/intel_cdclk.h"
fdeb6d02	29	#include "display/intel_de.h"
b978520d	30	#include "intel_device_info.h"
94b4f3ba CW	31	#include "i915_drv.h"
94b4f3ba CW	32
2e0d26f8 JN	33	#define PLATFORM_NAME(x) [INTEL_##x] = #x
	34	static const char * const platform_names[] = {
	35	PLATFORM_NAME(I830),
	36	PLATFORM_NAME(I845G),
	37	PLATFORM_NAME(I85X),
	38	PLATFORM_NAME(I865G),
	39	PLATFORM_NAME(I915G),
	40	PLATFORM_NAME(I915GM),
	41	PLATFORM_NAME(I945G),
	42	PLATFORM_NAME(I945GM),
	43	PLATFORM_NAME(G33),
	44	PLATFORM_NAME(PINEVIEW),
c0f86832 JN	45	PLATFORM_NAME(I965G),
c0f86832 JN	46	PLATFORM_NAME(I965GM),
f69c11ae JN	47	PLATFORM_NAME(G45),
f69c11ae JN	48	PLATFORM_NAME(GM45),
2e0d26f8 JN	49	PLATFORM_NAME(IRONLAKE),
	50	PLATFORM_NAME(SANDYBRIDGE),
	51	PLATFORM_NAME(IVYBRIDGE),
	52	PLATFORM_NAME(VALLEYVIEW),
	53	PLATFORM_NAME(HASWELL),
	54	PLATFORM_NAME(BROADWELL),
	55	PLATFORM_NAME(CHERRYVIEW),
	56	PLATFORM_NAME(SKYLAKE),
	57	PLATFORM_NAME(BROXTON),
	58	PLATFORM_NAME(KABYLAKE),
	59	PLATFORM_NAME(GEMINILAKE),
71851fa8	60	PLATFORM_NAME(COFFEELAKE),
5f4ae270	61	PLATFORM_NAME(COMETLAKE),
413f3c19	62	PLATFORM_NAME(CANNONLAKE),
41231001	63	PLATFORM_NAME(ICELAKE),
897f2961	64	PLATFORM_NAME(ELKHARTLAKE),
24ea098b	65	PLATFORM_NAME(JASPERLAKE),
abd3a0fe	66	PLATFORM_NAME(TIGERLAKE),
123f62de	67	PLATFORM_NAME(ROCKETLAKE),
05e26584	68	PLATFORM_NAME(DG1),
0883d63b	69	PLATFORM_NAME(ALDERLAKE_S),
bdd27cad	70	PLATFORM_NAME(ALDERLAKE_P),
2e0d26f8 JN	71	};
	72	#undef PLATFORM_NAME
	73
	74	const char *intel_platform_name(enum intel_platform platform)
	75	{
9160095c JN	76	BUILD_BUG_ON(ARRAY_SIZE(platform_names) != INTEL_MAX_PLATFORMS);
9160095c JN	77
2e0d26f8 JN	78	if (WARN_ON_ONCE(platform >= ARRAY_SIZE(platform_names) \|\|
	79	platform_names[platform] == NULL))
	80	return "<unknown>";
	81
	82	return platform_names[platform];
	83	}
	84
72404978	85	static const char *iommu_name(void)
a8c9b849	86	{
72404978 CW	87	const char *msg = "n/a";
	88
	89	#ifdef CONFIG_INTEL_IOMMU
	90	msg = enableddisabled(intel_iommu_gfx_mapped);
	91	#endif
	92
	93	return msg;
	94	}
	95
	96	void intel_device_info_print_static(const struct intel_device_info *info,
	97	struct drm_printer *p)
	98	{
0f9b145a LDM	99	drm_printf(p, "graphics version: %u\n", info->graphics_ver);
	100	drm_printf(p, "media version: %u\n", info->media_ver);
	101	drm_printf(p, "display version: %u\n", info->display.ver);
72404978 CW	102	drm_printf(p, "gt: %d\n", info->gt);
	103	drm_printf(p, "iommu: %s\n", iommu_name());
	104	drm_printf(p, "memory-regions: %x\n", info->memory_regions);
	105	drm_printf(p, "page-sizes: %x\n", info->page_sizes);
	106	drm_printf(p, "platform: %s\n", intel_platform_name(info->platform));
	107	drm_printf(p, "ppgtt-size: %d\n", info->ppgtt_size);
	108	drm_printf(p, "ppgtt-type: %d\n", info->ppgtt_type);
31a02eb7	109	drm_printf(p, "dma_mask_size: %u\n", info->dma_mask_size);
72404978	110
c33f83fd	111	#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, yesno(info->name))
a8c9b849 MW	112	DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
a8c9b849 MW	113	#undef PRINT_FLAG
d53db442 JRS	114
	115	#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, yesno(info->display.name));
	116	DEV_INFO_DISPLAY_FOR_EACH_FLAG(PRINT_FLAG);
	117	#undef PRINT_FLAG
a8c9b849 MW	118	}
a8c9b849 MW	119
72404978 CW	120	void intel_device_info_print_runtime(const struct intel_runtime_info *info,
72404978 CW	121	struct drm_printer *p)
5fbbe8d4	122	{
b04002f4	123	drm_printf(p, "rawclk rate: %u kHz\n", info->rawclk_freq);
dab91783 LL	124	}
dab91783 LL	125
805446c8 TU	126	#undef INTEL_VGA_DEVICE
	127	#define INTEL_VGA_DEVICE(id, info) (id)
	128
	129	static const u16 subplatform_ult_ids[] = {
	130	INTEL_HSW_ULT_GT1_IDS(0),
	131	INTEL_HSW_ULT_GT2_IDS(0),
	132	INTEL_HSW_ULT_GT3_IDS(0),
	133	INTEL_BDW_ULT_GT1_IDS(0),
	134	INTEL_BDW_ULT_GT2_IDS(0),
	135	INTEL_BDW_ULT_GT3_IDS(0),
	136	INTEL_BDW_ULT_RSVD_IDS(0),
	137	INTEL_SKL_ULT_GT1_IDS(0),
	138	INTEL_SKL_ULT_GT2_IDS(0),
	139	INTEL_SKL_ULT_GT3_IDS(0),
	140	INTEL_KBL_ULT_GT1_IDS(0),
	141	INTEL_KBL_ULT_GT2_IDS(0),
	142	INTEL_KBL_ULT_GT3_IDS(0),
	143	INTEL_CFL_U_GT2_IDS(0),
	144	INTEL_CFL_U_GT3_IDS(0),
	145	INTEL_WHL_U_GT1_IDS(0),
	146	INTEL_WHL_U_GT2_IDS(0),
c3ad8d29	147	INTEL_WHL_U_GT3_IDS(0),
8717c6b7 LS	148	INTEL_CML_U_GT1_IDS(0),
8717c6b7 LS	149	INTEL_CML_U_GT2_IDS(0),
805446c8 TU	150	};
	151
	152	static const u16 subplatform_ulx_ids[] = {
	153	INTEL_HSW_ULX_GT1_IDS(0),
	154	INTEL_HSW_ULX_GT2_IDS(0),
	155	INTEL_BDW_ULX_GT1_IDS(0),
	156	INTEL_BDW_ULX_GT2_IDS(0),
	157	INTEL_BDW_ULX_GT3_IDS(0),
	158	INTEL_BDW_ULX_RSVD_IDS(0),
	159	INTEL_SKL_ULX_GT1_IDS(0),
	160	INTEL_SKL_ULX_GT2_IDS(0),
	161	INTEL_KBL_ULX_GT1_IDS(0),
c3ad8d29	162	INTEL_KBL_ULX_GT2_IDS(0),
805446c8	163	INTEL_AML_KBL_GT2_IDS(0),
c3ad8d29	164	INTEL_AML_CFL_GT2_IDS(0),
805446c8 TU	165	};
	166
	167	static const u16 subplatform_portf_ids[] = {
	168	INTEL_CNL_PORT_F_IDS(0),
c3ad8d29	169	INTEL_ICL_PORT_F_IDS(0),
805446c8 TU	170	};
	171
	172	static bool find_devid(u16 id, const u16 *p, unsigned int num)
	173	{
	174	for (; num; num--, p++) {
	175	if (*p == id)
	176	return true;
	177	}
	178
	179	return false;
	180	}
	181
	182	void intel_device_info_subplatform_init(struct drm_i915_private *i915)
	183	{
	184	const struct intel_device_info *info = INTEL_INFO(i915);
	185	const struct intel_runtime_info *rinfo = RUNTIME_INFO(i915);
	186	const unsigned int pi = __platform_mask_index(rinfo, info->platform);
	187	const unsigned int pb = __platform_mask_bit(rinfo, info->platform);
	188	u16 devid = INTEL_DEVID(i915);
640cde65	189	u32 mask = 0;
805446c8 TU	190
	191	/* Make sure IS_<platform> checks are working. */
	192	RUNTIME_INFO(i915)->platform_mask[pi] = BIT(pb);
	193
	194	/* Find and mark subplatform bits based on the PCI device id. */
	195	if (find_devid(devid, subplatform_ult_ids,
	196	ARRAY_SIZE(subplatform_ult_ids))) {
	197	mask = BIT(INTEL_SUBPLATFORM_ULT);
	198	} else if (find_devid(devid, subplatform_ulx_ids,
	199	ARRAY_SIZE(subplatform_ulx_ids))) {
	200	mask = BIT(INTEL_SUBPLATFORM_ULX);
	201	if (IS_HASWELL(i915) \|\| IS_BROADWELL(i915)) {
	202	/* ULX machines are also considered ULT. */
	203	mask \|= BIT(INTEL_SUBPLATFORM_ULT);
	204	}
805446c8 TU	205	} else if (find_devid(devid, subplatform_portf_ids,
	206	ARRAY_SIZE(subplatform_portf_ids))) {
	207	mask = BIT(INTEL_SUBPLATFORM_PORTF);
	208	}
	209
1d3cc7ab	210	if (IS_TIGERLAKE(i915)) {
8ff5446a	211	struct pci_dev root, pdev = to_pci_dev(i915->drm.dev);
1d3cc7ab JRS	212
	213	root = list_first_entry(&pdev->bus->devices, typeof(*root), bus_list);
	214
	215	drm_WARN_ON(&i915->drm, mask);
	216	drm_WARN_ON(&i915->drm, (root->device & TGL_ROOT_DEVICE_MASK) !=
	217	TGL_ROOT_DEVICE_ID);
	218
	219	switch (root->device & TGL_ROOT_DEVICE_SKU_MASK) {
	220	case TGL_ROOT_DEVICE_SKU_ULX:
	221	mask = BIT(INTEL_SUBPLATFORM_ULX);
	222	break;
	223	case TGL_ROOT_DEVICE_SKU_ULT:
	224	mask = BIT(INTEL_SUBPLATFORM_ULT);
	225	break;
	226	}
	227	}
	228
56afa701	229	GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_MASK);
805446c8 TU	230
	231	RUNTIME_INFO(i915)->platform_mask[pi] \|= mask;
	232	}
	233
6a7e51f3 MW	234	/**
6a7e51f3 MW	235	* intel_device_info_runtime_init - initialize runtime info
963cc126	236	* @dev_priv: the i915 device
6a7e51f3	237	*
94b4f3ba CW	238	* Determine various intel_device_info fields at runtime.
	239	*
	240	* Use it when either:
	241	* - it's judged too laborious to fill n static structures with the limit
	242	* when a simple if statement does the job,
	243	* - run-time checks (eg read fuse/strap registers) are needed.
	244	*
	245	* This function needs to be called:
	246	* - after the MMIO has been setup as we are reading registers,
	247	* - after the PCH has been detected,
	248	* - before the first usage of the fields it can tweak.
	249	*/
1400cc7e	250	void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
94b4f3ba	251	{
1400cc7e	252	struct intel_device_info *info = mkwrite_device_info(dev_priv);
0258404f	253	struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv);
94b4f3ba CW	254	enum pipe pipe;
94b4f3ba CW	255
ea27113e	256	/* Wa_14011765242: adl-s A0 */
cd0fcf5a	257	if (IS_ADLS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0))
ea27113e AS	258	for_each_pipe(dev_priv, pipe)
ea27113e AS	259	runtime->num_scalers[pipe] = 0;
651e7d48	260	else if (GRAPHICS_VER(dev_priv) >= 10) {
6e7406db	261	for_each_pipe(dev_priv, pipe)
0258404f	262	runtime->num_scalers[pipe] = 2;
651e7d48	263	} else if (GRAPHICS_VER(dev_priv) == 9) {
0258404f JN	264	runtime->num_scalers[PIPE_A] = 2;
	265	runtime->num_scalers[PIPE_B] = 2;
	266	runtime->num_scalers[PIPE_C] = 1;
0bf0230e ACO	267	}
0bf0230e ACO	268
8a68d464	269	BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES);
022d3093	270
1649a4cc	271	if (DISPLAY_VER(dev_priv) >= 13 \|\| HAS_D12_PLANE_MINIMIZATION(dev_priv))
99e2d8bc MR	272	for_each_pipe(dev_priv, pipe)
99e2d8bc MR	273	runtime->num_sprites[pipe] = 4;
651e7d48	274	else if (GRAPHICS_VER(dev_priv) >= 11)
6711bd73	275	for_each_pipe(dev_priv, pipe)
0258404f	276	runtime->num_sprites[pipe] = 6;
651e7d48	277	else if (GRAPHICS_VER(dev_priv) == 10 \|\| IS_GEMINILAKE(dev_priv))
e9c98825	278	for_each_pipe(dev_priv, pipe)
0258404f	279	runtime->num_sprites[pipe] = 3;
e9c98825	280	else if (IS_BROXTON(dev_priv)) {
6711bd73 ML	281	/*
	282	* Skylake and Broxton currently don't expose the topmost plane as its
	283	* use is exclusive with the legacy cursor and we only want to expose
	284	* one of those, not both. Until we can safely expose the topmost plane
	285	* as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported,
	286	* we don't expose the topmost plane at all to prevent ABI breakage
	287	* down the line.
	288	*/
	289
0258404f JN	290	runtime->num_sprites[PIPE_A] = 2;
	291	runtime->num_sprites[PIPE_B] = 2;
	292	runtime->num_sprites[PIPE_C] = 1;
33edc24d	293	} else if (IS_VALLEYVIEW(dev_priv) \|\| IS_CHERRYVIEW(dev_priv)) {
94b4f3ba	294	for_each_pipe(dev_priv, pipe)
0258404f	295	runtime->num_sprites[pipe] = 2;
651e7d48	296	} else if (GRAPHICS_VER(dev_priv) >= 5 \|\| IS_G4X(dev_priv)) {
94b4f3ba	297	for_each_pipe(dev_priv, pipe)
0258404f	298	runtime->num_sprites[pipe] = 1;
33edc24d	299	}
94b4f3ba	300
651e7d48	301	if (HAS_DISPLAY(dev_priv) && IS_GRAPHICS_VER(dev_priv, 7, 8) &&
ef404bc6	302	HAS_PCH_SPLIT(dev_priv)) {
fdeb6d02 DCS	303	u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP);
fdeb6d02 DCS	304	u32 sfuse_strap = intel_de_read(dev_priv, SFUSE_STRAP);
94b4f3ba CW	305
	306	/*
	307	* SFUSE_STRAP is supposed to have a bit signalling the display
	308	* is fused off. Unfortunately it seems that, at least in
	309	* certain cases, fused off display means that PCH display
	310	* reads don't land anywhere. In that case, we read 0s.
	311	*
	312	* On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
	313	* should be set when taking over after the firmware.
	314	*/
	315	if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE \|\|
	316	sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED \|\|
b9eb89b2	317	(HAS_PCH_CPT(dev_priv) &&
94b4f3ba	318	!(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
68b32717 WK	319	drm_info(&dev_priv->drm,
68b32717 WK	320	"Display fused off, disabling\n");
8d8b0031	321	info->pipe_mask = 0;
10cf8e75	322	info->cpu_transcoder_mask = 0;
94b4f3ba	323	} else if (fuse_strap & IVB_PIPE_C_DISABLE) {
68b32717	324	drm_info(&dev_priv->drm, "PipeC fused off\n");
8d8b0031	325	info->pipe_mask &= ~BIT(PIPE_C);
10cf8e75	326	info->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
94b4f3ba	327	}
651e7d48	328	} else if (HAS_DISPLAY(dev_priv) && GRAPHICS_VER(dev_priv) >= 9) {
fdeb6d02	329	u32 dfsm = intel_de_read(dev_priv, SKL_DFSM);
94b4f3ba	330
10cf8e75 VS	331	if (dfsm & SKL_DFSM_PIPE_A_DISABLE) {
	332	info->pipe_mask &= ~BIT(PIPE_A);
	333	info->cpu_transcoder_mask &= ~BIT(TRANSCODER_A);
	334	}
	335	if (dfsm & SKL_DFSM_PIPE_B_DISABLE) {
	336	info->pipe_mask &= ~BIT(PIPE_B);
	337	info->cpu_transcoder_mask &= ~BIT(TRANSCODER_B);
	338	}
	339	if (dfsm & SKL_DFSM_PIPE_C_DISABLE) {
	340	info->pipe_mask &= ~BIT(PIPE_C);
	341	info->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
	342	}
651e7d48	343	if (GRAPHICS_VER(dev_priv) >= 12 &&
10cf8e75 VS	344	(dfsm & TGL_DFSM_PIPE_D_DISABLE)) {
	345	info->pipe_mask &= ~BIT(PIPE_D);
	346	info->cpu_transcoder_mask &= ~BIT(TRANSCODER_D);
	347	}
74393109 JRS	348
	349	if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE)
	350	info->display.has_hdcp = 0;
7a40aac1 JRS	351
	352	if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE)
	353	info->display.has_fbc = 0;
ee595888	354
651e7d48	355	if (GRAPHICS_VER(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))
ec2b1485	356	info->display.has_dmc = 0;
0f9ed3b2	357
651e7d48	358	if (GRAPHICS_VER(dev_priv) >= 10 &&
0f9ed3b2 JRS	359	(dfsm & CNL_DFSM_DISPLAY_DSC_DISABLE))
0f9ed3b2 JRS	360	info->display.has_dsc = 0;
94b4f3ba CW	361	}
94b4f3ba CW	362
651e7d48	363	if (GRAPHICS_VER(dev_priv) == 6 && intel_vtd_active()) {
68b32717 WK	364	drm_info(&dev_priv->drm,
68b32717 WK	365	"Disabling ppGTT for VT-d support\n");
cbecbcca	366	info->ppgtt_type = INTEL_PPGTT_NONE;
4bdafb9d CW	367	}
4bdafb9d CW	368
b04002f4 CW	369	runtime->rawclk_freq = intel_read_rawclk(dev_priv);
	370	drm_dbg(&dev_priv->drm, "rawclk rate: %d kHz\n", runtime->rawclk_freq);
	371
5e0e390d JN	372	if (!HAS_DISPLAY(dev_priv)) {
	373	dev_priv->drm.driver_features &= ~(DRIVER_MODESET \|
	374	DRIVER_ATOMIC);
	375	memset(&info->display, 0, sizeof(info->display));
	376	memset(runtime->num_sprites, 0, sizeof(runtime->num_sprites));
	377	memset(runtime->num_scalers, 0, sizeof(runtime->num_scalers));
	378	}
94b4f3ba	379	}
3fed1808 CW	380
	381	void intel_driver_caps_print(const struct intel_driver_caps *caps,
	382	struct drm_printer *p)
	383	{
481827b4 CW	384	drm_printf(p, "Has logical contexts? %s\n",
481827b4 CW	385	yesno(caps->has_logical_contexts));
3fed1808 CW	386	drm_printf(p, "scheduler: %x\n", caps->scheduler);
3fed1808 CW	387	}