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94b4f3ba CW |
1 | /* |
2 | * Copyright © 2016 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | ||
01fabda8 LDM |
25 | #include <linux/string_helpers.h> |
26 | ||
a8c9b849 | 27 | #include <drm/drm_print.h> |
83d2bdb6 | 28 | #include <drm/i915_pciids.h> |
a8c9b849 | 29 | |
b04002f4 | 30 | #include "display/intel_cdclk.h" |
fdeb6d02 | 31 | #include "display/intel_de.h" |
b978520d | 32 | #include "intel_device_info.h" |
94b4f3ba | 33 | #include "i915_drv.h" |
a7f46d5b | 34 | #include "i915_utils.h" |
94b4f3ba | 35 | |
2e0d26f8 JN |
36 | #define PLATFORM_NAME(x) [INTEL_##x] = #x |
37 | static const char * const platform_names[] = { | |
38 | PLATFORM_NAME(I830), | |
39 | PLATFORM_NAME(I845G), | |
40 | PLATFORM_NAME(I85X), | |
41 | PLATFORM_NAME(I865G), | |
42 | PLATFORM_NAME(I915G), | |
43 | PLATFORM_NAME(I915GM), | |
44 | PLATFORM_NAME(I945G), | |
45 | PLATFORM_NAME(I945GM), | |
46 | PLATFORM_NAME(G33), | |
47 | PLATFORM_NAME(PINEVIEW), | |
c0f86832 JN |
48 | PLATFORM_NAME(I965G), |
49 | PLATFORM_NAME(I965GM), | |
f69c11ae JN |
50 | PLATFORM_NAME(G45), |
51 | PLATFORM_NAME(GM45), | |
2e0d26f8 JN |
52 | PLATFORM_NAME(IRONLAKE), |
53 | PLATFORM_NAME(SANDYBRIDGE), | |
54 | PLATFORM_NAME(IVYBRIDGE), | |
55 | PLATFORM_NAME(VALLEYVIEW), | |
56 | PLATFORM_NAME(HASWELL), | |
57 | PLATFORM_NAME(BROADWELL), | |
58 | PLATFORM_NAME(CHERRYVIEW), | |
59 | PLATFORM_NAME(SKYLAKE), | |
60 | PLATFORM_NAME(BROXTON), | |
61 | PLATFORM_NAME(KABYLAKE), | |
62 | PLATFORM_NAME(GEMINILAKE), | |
71851fa8 | 63 | PLATFORM_NAME(COFFEELAKE), |
5f4ae270 | 64 | PLATFORM_NAME(COMETLAKE), |
41231001 | 65 | PLATFORM_NAME(ICELAKE), |
897f2961 | 66 | PLATFORM_NAME(ELKHARTLAKE), |
24ea098b | 67 | PLATFORM_NAME(JASPERLAKE), |
abd3a0fe | 68 | PLATFORM_NAME(TIGERLAKE), |
123f62de | 69 | PLATFORM_NAME(ROCKETLAKE), |
05e26584 | 70 | PLATFORM_NAME(DG1), |
0883d63b | 71 | PLATFORM_NAME(ALDERLAKE_S), |
bdd27cad | 72 | PLATFORM_NAME(ALDERLAKE_P), |
086df54e | 73 | PLATFORM_NAME(XEHPSDV), |
9e22cfc5 | 74 | PLATFORM_NAME(DG2), |
448a54ac | 75 | PLATFORM_NAME(PONTEVECCHIO), |
bcf9b296 | 76 | PLATFORM_NAME(METEORLAKE), |
2e0d26f8 JN |
77 | }; |
78 | #undef PLATFORM_NAME | |
79 | ||
80 | const char *intel_platform_name(enum intel_platform platform) | |
81 | { | |
9160095c JN |
82 | BUILD_BUG_ON(ARRAY_SIZE(platform_names) != INTEL_MAX_PLATFORMS); |
83 | ||
2e0d26f8 JN |
84 | if (WARN_ON_ONCE(platform >= ARRAY_SIZE(platform_names) || |
85 | platform_names[platform] == NULL)) | |
86 | return "<unknown>"; | |
87 | ||
88 | return platform_names[platform]; | |
89 | } | |
90 | ||
72404978 CW |
91 | void intel_device_info_print_static(const struct intel_device_info *info, |
92 | struct drm_printer *p) | |
93 | { | |
a5b7ef27 JRS |
94 | if (info->graphics.rel) |
95 | drm_printf(p, "graphics version: %u.%02u\n", info->graphics.ver, | |
96 | info->graphics.rel); | |
ca6374e2 | 97 | else |
a5b7ef27 | 98 | drm_printf(p, "graphics version: %u\n", info->graphics.ver); |
ca6374e2 | 99 | |
a5b7ef27 JRS |
100 | if (info->media.rel) |
101 | drm_printf(p, "media version: %u.%02u\n", info->media.ver, info->media.rel); | |
ca6374e2 | 102 | else |
a5b7ef27 | 103 | drm_printf(p, "media version: %u\n", info->media.ver); |
ca6374e2 | 104 | |
a5b7ef27 JRS |
105 | if (info->display.rel) |
106 | drm_printf(p, "display version: %u.%02u\n", info->display.ver, info->display.rel); | |
ca6374e2 | 107 | else |
a5b7ef27 | 108 | drm_printf(p, "display version: %u\n", info->display.ver); |
ca6374e2 | 109 | |
72404978 | 110 | drm_printf(p, "gt: %d\n", info->gt); |
72404978 CW |
111 | drm_printf(p, "memory-regions: %x\n", info->memory_regions); |
112 | drm_printf(p, "page-sizes: %x\n", info->page_sizes); | |
113 | drm_printf(p, "platform: %s\n", intel_platform_name(info->platform)); | |
114 | drm_printf(p, "ppgtt-size: %d\n", info->ppgtt_size); | |
115 | drm_printf(p, "ppgtt-type: %d\n", info->ppgtt_type); | |
31a02eb7 | 116 | drm_printf(p, "dma_mask_size: %u\n", info->dma_mask_size); |
72404978 | 117 | |
01fabda8 | 118 | #define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, str_yes_no(info->name)) |
a8c9b849 MW |
119 | DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG); |
120 | #undef PRINT_FLAG | |
d53db442 | 121 | |
01fabda8 | 122 | #define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, str_yes_no(info->display.name)) |
d53db442 JRS |
123 | DEV_INFO_DISPLAY_FOR_EACH_FLAG(PRINT_FLAG); |
124 | #undef PRINT_FLAG | |
a8c9b849 MW |
125 | } |
126 | ||
72404978 CW |
127 | void intel_device_info_print_runtime(const struct intel_runtime_info *info, |
128 | struct drm_printer *p) | |
5fbbe8d4 | 129 | { |
b04002f4 | 130 | drm_printf(p, "rawclk rate: %u kHz\n", info->rawclk_freq); |
dab91783 LL |
131 | } |
132 | ||
805446c8 TU |
133 | #undef INTEL_VGA_DEVICE |
134 | #define INTEL_VGA_DEVICE(id, info) (id) | |
135 | ||
136 | static const u16 subplatform_ult_ids[] = { | |
137 | INTEL_HSW_ULT_GT1_IDS(0), | |
138 | INTEL_HSW_ULT_GT2_IDS(0), | |
139 | INTEL_HSW_ULT_GT3_IDS(0), | |
140 | INTEL_BDW_ULT_GT1_IDS(0), | |
141 | INTEL_BDW_ULT_GT2_IDS(0), | |
142 | INTEL_BDW_ULT_GT3_IDS(0), | |
143 | INTEL_BDW_ULT_RSVD_IDS(0), | |
144 | INTEL_SKL_ULT_GT1_IDS(0), | |
145 | INTEL_SKL_ULT_GT2_IDS(0), | |
146 | INTEL_SKL_ULT_GT3_IDS(0), | |
147 | INTEL_KBL_ULT_GT1_IDS(0), | |
148 | INTEL_KBL_ULT_GT2_IDS(0), | |
149 | INTEL_KBL_ULT_GT3_IDS(0), | |
150 | INTEL_CFL_U_GT2_IDS(0), | |
151 | INTEL_CFL_U_GT3_IDS(0), | |
152 | INTEL_WHL_U_GT1_IDS(0), | |
153 | INTEL_WHL_U_GT2_IDS(0), | |
c3ad8d29 | 154 | INTEL_WHL_U_GT3_IDS(0), |
8717c6b7 LS |
155 | INTEL_CML_U_GT1_IDS(0), |
156 | INTEL_CML_U_GT2_IDS(0), | |
805446c8 TU |
157 | }; |
158 | ||
159 | static const u16 subplatform_ulx_ids[] = { | |
160 | INTEL_HSW_ULX_GT1_IDS(0), | |
161 | INTEL_HSW_ULX_GT2_IDS(0), | |
162 | INTEL_BDW_ULX_GT1_IDS(0), | |
163 | INTEL_BDW_ULX_GT2_IDS(0), | |
164 | INTEL_BDW_ULX_GT3_IDS(0), | |
165 | INTEL_BDW_ULX_RSVD_IDS(0), | |
166 | INTEL_SKL_ULX_GT1_IDS(0), | |
167 | INTEL_SKL_ULX_GT2_IDS(0), | |
168 | INTEL_KBL_ULX_GT1_IDS(0), | |
c3ad8d29 | 169 | INTEL_KBL_ULX_GT2_IDS(0), |
805446c8 | 170 | INTEL_AML_KBL_GT2_IDS(0), |
c3ad8d29 | 171 | INTEL_AML_CFL_GT2_IDS(0), |
805446c8 TU |
172 | }; |
173 | ||
174 | static const u16 subplatform_portf_ids[] = { | |
c3ad8d29 | 175 | INTEL_ICL_PORT_F_IDS(0), |
805446c8 TU |
176 | }; |
177 | ||
b9ef8939 JRS |
178 | static const u16 subplatform_uy_ids[] = { |
179 | INTEL_TGL_12_GT2_IDS(0), | |
180 | }; | |
181 | ||
7e28d0b2 TU |
182 | static const u16 subplatform_n_ids[] = { |
183 | INTEL_ADLN_IDS(0), | |
184 | }; | |
185 | ||
72c3c8d6 | 186 | static const u16 subplatform_rpl_ids[] = { |
52407c22 | 187 | INTEL_RPLS_IDS(0), |
72c3c8d6 | 188 | INTEL_RPLP_IDS(0), |
52407c22 AS |
189 | }; |
190 | ||
1bc4ae0c MR |
191 | static const u16 subplatform_g10_ids[] = { |
192 | INTEL_DG2_G10_IDS(0), | |
8618b848 | 193 | INTEL_ATS_M150_IDS(0), |
1bc4ae0c MR |
194 | }; |
195 | ||
196 | static const u16 subplatform_g11_ids[] = { | |
197 | INTEL_DG2_G11_IDS(0), | |
8618b848 | 198 | INTEL_ATS_M75_IDS(0), |
1bc4ae0c MR |
199 | }; |
200 | ||
201 | static const u16 subplatform_g12_ids[] = { | |
202 | INTEL_DG2_G12_IDS(0), | |
52407c22 AS |
203 | }; |
204 | ||
78353039 RS |
205 | static const u16 subplatform_m_ids[] = { |
206 | INTEL_MTL_M_IDS(0), | |
207 | }; | |
208 | ||
209 | static const u16 subplatform_p_ids[] = { | |
210 | INTEL_MTL_P_IDS(0), | |
211 | }; | |
212 | ||
805446c8 TU |
213 | static bool find_devid(u16 id, const u16 *p, unsigned int num) |
214 | { | |
215 | for (; num; num--, p++) { | |
216 | if (*p == id) | |
217 | return true; | |
218 | } | |
219 | ||
220 | return false; | |
221 | } | |
222 | ||
223 | void intel_device_info_subplatform_init(struct drm_i915_private *i915) | |
224 | { | |
225 | const struct intel_device_info *info = INTEL_INFO(i915); | |
226 | const struct intel_runtime_info *rinfo = RUNTIME_INFO(i915); | |
227 | const unsigned int pi = __platform_mask_index(rinfo, info->platform); | |
228 | const unsigned int pb = __platform_mask_bit(rinfo, info->platform); | |
229 | u16 devid = INTEL_DEVID(i915); | |
640cde65 | 230 | u32 mask = 0; |
805446c8 TU |
231 | |
232 | /* Make sure IS_<platform> checks are working. */ | |
233 | RUNTIME_INFO(i915)->platform_mask[pi] = BIT(pb); | |
234 | ||
235 | /* Find and mark subplatform bits based on the PCI device id. */ | |
236 | if (find_devid(devid, subplatform_ult_ids, | |
237 | ARRAY_SIZE(subplatform_ult_ids))) { | |
238 | mask = BIT(INTEL_SUBPLATFORM_ULT); | |
239 | } else if (find_devid(devid, subplatform_ulx_ids, | |
240 | ARRAY_SIZE(subplatform_ulx_ids))) { | |
241 | mask = BIT(INTEL_SUBPLATFORM_ULX); | |
242 | if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { | |
243 | /* ULX machines are also considered ULT. */ | |
244 | mask |= BIT(INTEL_SUBPLATFORM_ULT); | |
245 | } | |
805446c8 TU |
246 | } else if (find_devid(devid, subplatform_portf_ids, |
247 | ARRAY_SIZE(subplatform_portf_ids))) { | |
248 | mask = BIT(INTEL_SUBPLATFORM_PORTF); | |
b9ef8939 JRS |
249 | } else if (find_devid(devid, subplatform_uy_ids, |
250 | ARRAY_SIZE(subplatform_uy_ids))) { | |
251 | mask = BIT(INTEL_SUBPLATFORM_UY); | |
7e28d0b2 TU |
252 | } else if (find_devid(devid, subplatform_n_ids, |
253 | ARRAY_SIZE(subplatform_n_ids))) { | |
254 | mask = BIT(INTEL_SUBPLATFORM_N); | |
72c3c8d6 MA |
255 | } else if (find_devid(devid, subplatform_rpl_ids, |
256 | ARRAY_SIZE(subplatform_rpl_ids))) { | |
257 | mask = BIT(INTEL_SUBPLATFORM_RPL); | |
1bc4ae0c MR |
258 | } else if (find_devid(devid, subplatform_g10_ids, |
259 | ARRAY_SIZE(subplatform_g10_ids))) { | |
260 | mask = BIT(INTEL_SUBPLATFORM_G10); | |
261 | } else if (find_devid(devid, subplatform_g11_ids, | |
262 | ARRAY_SIZE(subplatform_g11_ids))) { | |
263 | mask = BIT(INTEL_SUBPLATFORM_G11); | |
264 | } else if (find_devid(devid, subplatform_g12_ids, | |
265 | ARRAY_SIZE(subplatform_g12_ids))) { | |
266 | mask = BIT(INTEL_SUBPLATFORM_G12); | |
78353039 RS |
267 | } else if (find_devid(devid, subplatform_m_ids, |
268 | ARRAY_SIZE(subplatform_m_ids))) { | |
269 | mask = BIT(INTEL_SUBPLATFORM_M); | |
270 | } else if (find_devid(devid, subplatform_p_ids, | |
271 | ARRAY_SIZE(subplatform_p_ids))) { | |
272 | mask = BIT(INTEL_SUBPLATFORM_P); | |
805446c8 TU |
273 | } |
274 | ||
56afa701 | 275 | GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_MASK); |
805446c8 TU |
276 | |
277 | RUNTIME_INFO(i915)->platform_mask[pi] |= mask; | |
278 | } | |
279 | ||
6a7e51f3 MW |
280 | /** |
281 | * intel_device_info_runtime_init - initialize runtime info | |
963cc126 | 282 | * @dev_priv: the i915 device |
6a7e51f3 | 283 | * |
94b4f3ba CW |
284 | * Determine various intel_device_info fields at runtime. |
285 | * | |
286 | * Use it when either: | |
287 | * - it's judged too laborious to fill n static structures with the limit | |
288 | * when a simple if statement does the job, | |
289 | * - run-time checks (eg read fuse/strap registers) are needed. | |
290 | * | |
291 | * This function needs to be called: | |
292 | * - after the MMIO has been setup as we are reading registers, | |
293 | * - after the PCH has been detected, | |
294 | * - before the first usage of the fields it can tweak. | |
295 | */ | |
1400cc7e | 296 | void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) |
94b4f3ba | 297 | { |
1400cc7e | 298 | struct intel_device_info *info = mkwrite_device_info(dev_priv); |
0258404f | 299 | struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv); |
94b4f3ba CW |
300 | enum pipe pipe; |
301 | ||
8ff36e02 | 302 | /* Wa_14011765242: adl-s A0,A1 */ |
46b0d709 | 303 | if (IS_ADLS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A2)) |
ea27113e AS |
304 | for_each_pipe(dev_priv, pipe) |
305 | runtime->num_scalers[pipe] = 0; | |
4c6b3021 | 306 | else if (DISPLAY_VER(dev_priv) >= 11) { |
6e7406db | 307 | for_each_pipe(dev_priv, pipe) |
0258404f | 308 | runtime->num_scalers[pipe] = 2; |
4c6b3021 | 309 | } else if (DISPLAY_VER(dev_priv) >= 9) { |
0258404f JN |
310 | runtime->num_scalers[PIPE_A] = 2; |
311 | runtime->num_scalers[PIPE_B] = 2; | |
312 | runtime->num_scalers[PIPE_C] = 1; | |
0bf0230e ACO |
313 | } |
314 | ||
8a68d464 | 315 | BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES); |
022d3093 | 316 | |
1649a4cc | 317 | if (DISPLAY_VER(dev_priv) >= 13 || HAS_D12_PLANE_MINIMIZATION(dev_priv)) |
99e2d8bc MR |
318 | for_each_pipe(dev_priv, pipe) |
319 | runtime->num_sprites[pipe] = 4; | |
4c6b3021 | 320 | else if (DISPLAY_VER(dev_priv) >= 11) |
6711bd73 | 321 | for_each_pipe(dev_priv, pipe) |
0258404f | 322 | runtime->num_sprites[pipe] = 6; |
4c6b3021 | 323 | else if (DISPLAY_VER(dev_priv) == 10) |
e9c98825 | 324 | for_each_pipe(dev_priv, pipe) |
0258404f | 325 | runtime->num_sprites[pipe] = 3; |
e9c98825 | 326 | else if (IS_BROXTON(dev_priv)) { |
6711bd73 ML |
327 | /* |
328 | * Skylake and Broxton currently don't expose the topmost plane as its | |
329 | * use is exclusive with the legacy cursor and we only want to expose | |
330 | * one of those, not both. Until we can safely expose the topmost plane | |
331 | * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported, | |
332 | * we don't expose the topmost plane at all to prevent ABI breakage | |
333 | * down the line. | |
334 | */ | |
335 | ||
0258404f JN |
336 | runtime->num_sprites[PIPE_A] = 2; |
337 | runtime->num_sprites[PIPE_B] = 2; | |
338 | runtime->num_sprites[PIPE_C] = 1; | |
33edc24d | 339 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
94b4f3ba | 340 | for_each_pipe(dev_priv, pipe) |
0258404f | 341 | runtime->num_sprites[pipe] = 2; |
4c6b3021 | 342 | } else if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) { |
94b4f3ba | 343 | for_each_pipe(dev_priv, pipe) |
0258404f | 344 | runtime->num_sprites[pipe] = 1; |
33edc24d | 345 | } |
94b4f3ba | 346 | |
651e7d48 | 347 | if (HAS_DISPLAY(dev_priv) && IS_GRAPHICS_VER(dev_priv, 7, 8) && |
ef404bc6 | 348 | HAS_PCH_SPLIT(dev_priv)) { |
fdeb6d02 DCS |
349 | u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP); |
350 | u32 sfuse_strap = intel_de_read(dev_priv, SFUSE_STRAP); | |
94b4f3ba CW |
351 | |
352 | /* | |
353 | * SFUSE_STRAP is supposed to have a bit signalling the display | |
354 | * is fused off. Unfortunately it seems that, at least in | |
355 | * certain cases, fused off display means that PCH display | |
356 | * reads don't land anywhere. In that case, we read 0s. | |
357 | * | |
358 | * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK | |
359 | * should be set when taking over after the firmware. | |
360 | */ | |
361 | if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE || | |
362 | sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED || | |
b9eb89b2 | 363 | (HAS_PCH_CPT(dev_priv) && |
94b4f3ba | 364 | !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) { |
68b32717 WK |
365 | drm_info(&dev_priv->drm, |
366 | "Display fused off, disabling\n"); | |
6678916d VS |
367 | info->display.pipe_mask = 0; |
368 | info->display.cpu_transcoder_mask = 0; | |
b8ca477e | 369 | info->display.fbc_mask = 0; |
94b4f3ba | 370 | } else if (fuse_strap & IVB_PIPE_C_DISABLE) { |
68b32717 | 371 | drm_info(&dev_priv->drm, "PipeC fused off\n"); |
6678916d VS |
372 | info->display.pipe_mask &= ~BIT(PIPE_C); |
373 | info->display.cpu_transcoder_mask &= ~BIT(TRANSCODER_C); | |
94b4f3ba | 374 | } |
4fd17728 | 375 | } else if (HAS_DISPLAY(dev_priv) && DISPLAY_VER(dev_priv) >= 9) { |
fdeb6d02 | 376 | u32 dfsm = intel_de_read(dev_priv, SKL_DFSM); |
94b4f3ba | 377 | |
10cf8e75 | 378 | if (dfsm & SKL_DFSM_PIPE_A_DISABLE) { |
6678916d VS |
379 | info->display.pipe_mask &= ~BIT(PIPE_A); |
380 | info->display.cpu_transcoder_mask &= ~BIT(TRANSCODER_A); | |
b8ca477e | 381 | info->display.fbc_mask &= ~BIT(INTEL_FBC_A); |
10cf8e75 VS |
382 | } |
383 | if (dfsm & SKL_DFSM_PIPE_B_DISABLE) { | |
6678916d VS |
384 | info->display.pipe_mask &= ~BIT(PIPE_B); |
385 | info->display.cpu_transcoder_mask &= ~BIT(TRANSCODER_B); | |
10cf8e75 VS |
386 | } |
387 | if (dfsm & SKL_DFSM_PIPE_C_DISABLE) { | |
6678916d VS |
388 | info->display.pipe_mask &= ~BIT(PIPE_C); |
389 | info->display.cpu_transcoder_mask &= ~BIT(TRANSCODER_C); | |
10cf8e75 | 390 | } |
4fd17728 LDM |
391 | |
392 | if (DISPLAY_VER(dev_priv) >= 12 && | |
10cf8e75 | 393 | (dfsm & TGL_DFSM_PIPE_D_DISABLE)) { |
6678916d VS |
394 | info->display.pipe_mask &= ~BIT(PIPE_D); |
395 | info->display.cpu_transcoder_mask &= ~BIT(TRANSCODER_D); | |
10cf8e75 | 396 | } |
74393109 JRS |
397 | |
398 | if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE) | |
399 | info->display.has_hdcp = 0; | |
7a40aac1 JRS |
400 | |
401 | if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE) | |
b8ca477e | 402 | info->display.fbc_mask = 0; |
ee595888 | 403 | |
4fd17728 | 404 | if (DISPLAY_VER(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE)) |
ec2b1485 | 405 | info->display.has_dmc = 0; |
0f9ed3b2 | 406 | |
4fd17728 | 407 | if (DISPLAY_VER(dev_priv) >= 10 && |
a4d082fc | 408 | (dfsm & GLK_DFSM_DISPLAY_DSC_DISABLE)) |
0f9ed3b2 | 409 | info->display.has_dsc = 0; |
94b4f3ba CW |
410 | } |
411 | ||
a7f46d5b | 412 | if (GRAPHICS_VER(dev_priv) == 6 && i915_vtd_active(dev_priv)) { |
68b32717 WK |
413 | drm_info(&dev_priv->drm, |
414 | "Disabling ppGTT for VT-d support\n"); | |
cbecbcca | 415 | info->ppgtt_type = INTEL_PPGTT_NONE; |
4bdafb9d CW |
416 | } |
417 | ||
b04002f4 CW |
418 | runtime->rawclk_freq = intel_read_rawclk(dev_priv); |
419 | drm_dbg(&dev_priv->drm, "rawclk rate: %d kHz\n", runtime->rawclk_freq); | |
420 | ||
5e0e390d JN |
421 | if (!HAS_DISPLAY(dev_priv)) { |
422 | dev_priv->drm.driver_features &= ~(DRIVER_MODESET | | |
423 | DRIVER_ATOMIC); | |
424 | memset(&info->display, 0, sizeof(info->display)); | |
425 | memset(runtime->num_sprites, 0, sizeof(runtime->num_sprites)); | |
426 | memset(runtime->num_scalers, 0, sizeof(runtime->num_scalers)); | |
427 | } | |
94b4f3ba | 428 | } |
3fed1808 CW |
429 | |
430 | void intel_driver_caps_print(const struct intel_driver_caps *caps, | |
431 | struct drm_printer *p) | |
432 | { | |
481827b4 | 433 | drm_printf(p, "Has logical contexts? %s\n", |
01fabda8 | 434 | str_yes_no(caps->has_logical_contexts)); |
3fed1808 CW |
435 | drm_printf(p, "scheduler: %x\n", caps->scheduler); |
436 | } |