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drm/i915/skl: Buffer translation improvements
[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_ddi.c
CommitLineData
45244b87
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28#include "i915_drv.h"
29#include "intel_drv.h"
30
10122051
JN		 31struct ddi_buf_trans {
32 u32 trans1; /* balance leg enable, de-emph level */
33 u32 trans2; /* vref sel, vswing */
f8896f5d 34 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
10122051
JN		 35};
36
45244b87
ED		 37/* HDMI/DVI modes ignore everything but the last 2 items. So we share
38 * them for both DP and FDI transports, allowing those ports to
39 * automatically adapt to HDMI connections as well
40 */
10122051 41static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
f8896f5d
DW		 42 { 0x00FFFFFF, 0x0006000E, 0x0 },
43 { 0x00D75FFF, 0x0005000A, 0x0 },
44 { 0x00C30FFF, 0x00040006, 0x0 },
45 { 0x80AAAFFF, 0x000B0000, 0x0 },
46 { 0x00FFFFFF, 0x0005000A, 0x0 },
47 { 0x00D75FFF, 0x000C0004, 0x0 },
48 { 0x80C30FFF, 0x000B0000, 0x0 },
49 { 0x00FFFFFF, 0x00040006, 0x0 },
50 { 0x80D75FFF, 0x000B0000, 0x0 },
45244b87
ED		 51};
52
10122051 53static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
f8896f5d
DW		 54 { 0x00FFFFFF, 0x0007000E, 0x0 },
55 { 0x00D75FFF, 0x000F000A, 0x0 },
56 { 0x00C30FFF, 0x00060006, 0x0 },
57 { 0x00AAAFFF, 0x001E0000, 0x0 },
58 { 0x00FFFFFF, 0x000F000A, 0x0 },
59 { 0x00D75FFF, 0x00160004, 0x0 },
60 { 0x00C30FFF, 0x001E0000, 0x0 },
61 { 0x00FFFFFF, 0x00060006, 0x0 },
62 { 0x00D75FFF, 0x001E0000, 0x0 },
6acab15a
PZ		 63};
64
10122051
JN		 65static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
66 /* Idx NT mV d T mV d db */
f8896f5d
DW		 67 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */
68 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */
69 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */
70 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */
71 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */
72 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */
73 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */
74 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */
75 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */
76 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */
77 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */
78 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */
45244b87
ED		 79};
80
10122051 81static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
f8896f5d
DW		 82 { 0x00FFFFFF, 0x00000012, 0x0 },
83 { 0x00EBAFFF, 0x00020011, 0x0 },
84 { 0x00C71FFF, 0x0006000F, 0x0 },
85 { 0x00AAAFFF, 0x000E000A, 0x0 },
86 { 0x00FFFFFF, 0x00020011, 0x0 },
87 { 0x00DB6FFF, 0x0005000F, 0x0 },
88 { 0x00BEEFFF, 0x000A000C, 0x0 },
89 { 0x00FFFFFF, 0x0005000F, 0x0 },
90 { 0x00DB6FFF, 0x000A000C, 0x0 },
300644c7
PZ		 91};
92
10122051 93static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
f8896f5d
DW		 94 { 0x00FFFFFF, 0x0007000E, 0x0 },
95 { 0x00D75FFF, 0x000E000A, 0x0 },
96 { 0x00BEFFFF, 0x00140006, 0x0 },
97 { 0x80B2CFFF, 0x001B0002, 0x0 },
98 { 0x00FFFFFF, 0x000E000A, 0x0 },
99 { 0x00DB6FFF, 0x00160005, 0x0 },
100 { 0x80C71FFF, 0x001A0002, 0x0 },
101 { 0x00F7DFFF, 0x00180004, 0x0 },
102 { 0x80D75FFF, 0x001B0002, 0x0 },
e58623cb
AR		 103};
104
10122051 105static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
f8896f5d
DW		 106 { 0x00FFFFFF, 0x0001000E, 0x0 },
107 { 0x00D75FFF, 0x0004000A, 0x0 },
108 { 0x00C30FFF, 0x00070006, 0x0 },
109 { 0x00AAAFFF, 0x000C0000, 0x0 },
110 { 0x00FFFFFF, 0x0004000A, 0x0 },
111 { 0x00D75FFF, 0x00090004, 0x0 },
112 { 0x00C30FFF, 0x000C0000, 0x0 },
113 { 0x00FFFFFF, 0x00070006, 0x0 },
114 { 0x00D75FFF, 0x000C0000, 0x0 },
e58623cb
AR		 115};
116
10122051
JN		 117static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
118 /* Idx NT mV d T mV df db */
f8896f5d
DW		 119 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */
120 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */
121 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */
122 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */
123 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */
124 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */
125 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */
126 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */
127 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */
128 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */
a26aa8ba
DL		 129};
130
f8896f5d 131/* Skylake H, S, and Skylake Y with 0.95V VccIO */
7f88e3af 132static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
f8896f5d
DW		 133 { 0x00002016, 0x000000A0, 0x0 },
134 { 0x00005012, 0x0000009B, 0x0 },
135 { 0x00007011, 0x00000088, 0x0 },
136 { 0x00009010, 0x000000C7, 0x0 },
137 { 0x00002016, 0x0000009B, 0x0 },
138 { 0x00005012, 0x00000088, 0x0 },
139 { 0x00007011, 0x000000C7, 0x0 },
140 { 0x00002016, 0x000000DF, 0x0 },
141 { 0x00005012, 0x000000C7, 0x0 },
7f88e3af
DL		 142};
143
f8896f5d
DW		 144/* Skylake U */
145static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
146 { 0x00002016, 0x000000A2, 0x0 },
147 { 0x00005012, 0x00000088, 0x0 },
148 { 0x00007011, 0x00000087, 0x0 },
149 { 0x80009010, 0x000000C7, 0x1 }, /* Uses I_boost */
150 { 0x00002016, 0x0000009D, 0x0 },
151 { 0x00005012, 0x000000C7, 0x0 },
152 { 0x00007011, 0x000000C7, 0x0 },
153 { 0x00002016, 0x00000088, 0x0 },
154 { 0x00005012, 0x000000C7, 0x0 },
155};
156
157/* Skylake Y with 0.85V VccIO */
158static const struct ddi_buf_trans skl_y_085v_ddi_translations_dp[] = {
159 { 0x00000018, 0x000000A2, 0x0 },
160 { 0x00005012, 0x00000088, 0x0 },
161 { 0x00007011, 0x00000087, 0x0 },
162 { 0x80009010, 0x000000C7, 0x1 }, /* Uses I_boost */
163 { 0x00000018, 0x0000009D, 0x0 },
164 { 0x00005012, 0x000000C7, 0x0 },
165 { 0x00007011, 0x000000C7, 0x0 },
166 { 0x00000018, 0x00000088, 0x0 },
167 { 0x00005012, 0x000000C7, 0x0 },
168};
169
170/*
171 * Skylake H and S, and Skylake Y with 0.95V VccIO
172 * eDP 1.4 low vswing translation parameters
173 */
7ad14a29 174static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
f8896f5d
DW		 175 { 0x00000018, 0x000000A8, 0x0 },
176 { 0x00004013, 0x000000A9, 0x0 },
177 { 0x00007011, 0x000000A2, 0x0 },
178 { 0x00009010, 0x0000009C, 0x0 },
179 { 0x00000018, 0x000000A9, 0x0 },
180 { 0x00006013, 0x000000A2, 0x0 },
181 { 0x00007011, 0x000000A6, 0x0 },
182 { 0x00000018, 0x000000AB, 0x0 },
183 { 0x00007013, 0x0000009F, 0x0 },
184 { 0x00000018, 0x000000DF, 0x0 },
185};
186
187/*
188 * Skylake U
189 * eDP 1.4 low vswing translation parameters
190 */
191static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
192 { 0x00000018, 0x000000A8, 0x0 },
193 { 0x00004013, 0x000000A9, 0x0 },
194 { 0x00007011, 0x000000A2, 0x0 },
195 { 0x00009010, 0x0000009C, 0x0 },
196 { 0x00000018, 0x000000A9, 0x0 },
197 { 0x00006013, 0x000000A2, 0x0 },
198 { 0x00007011, 0x000000A6, 0x0 },
199 { 0x00002016, 0x000000AB, 0x0 },
200 { 0x00005013, 0x0000009F, 0x0 },
201 { 0x00000018, 0x000000DF, 0x0 },
7ad14a29
SJ		 202};
203
f8896f5d
DW		 204/*
205 * Skylake Y with 0.95V VccIO
206 * eDP 1.4 low vswing translation parameters
207 */
208static const struct ddi_buf_trans skl_y_085v_ddi_translations_edp[] = {
209 { 0x00000018, 0x000000A8, 0x0 },
210 { 0x00004013, 0x000000AB, 0x0 },
211 { 0x00007011, 0x000000A4, 0x0 },
212 { 0x00009010, 0x000000DF, 0x0 },
213 { 0x00000018, 0x000000AA, 0x0 },
214 { 0x00006013, 0x000000A4, 0x0 },
215 { 0x00007011, 0x0000009D, 0x0 },
216 { 0x00000018, 0x000000A0, 0x0 },
217 { 0x00006012, 0x000000DF, 0x0 },
218 { 0x00000018, 0x0000008A, 0x0 },
219};
7ad14a29 220
f8896f5d 221/* Skylake H, S and U, and Skylake Y with 0.95V VccIO */
7f88e3af 222static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
f8896f5d
DW		 223 { 0x00000018, 0x000000AC, 0x0 },
224 { 0x00005012, 0x0000009D, 0x0 },
225 { 0x00007011, 0x00000088, 0x0 },
226 { 0x00000018, 0x000000A1, 0x0 },
227 { 0x00000018, 0x00000098, 0x0 },
228 { 0x00004013, 0x00000088, 0x0 },
229 { 0x00006012, 0x00000087, 0x0 },
230 { 0x00000018, 0x000000DF, 0x0 },
231 { 0x00003015, 0x00000087, 0x0 }, /* Default */
232 { 0x00003015, 0x000000C7, 0x0 },
233 { 0x00000018, 0x000000C7, 0x0 },
234};
235
236/* Skylake Y with 0.85V VccIO */
237static const struct ddi_buf_trans skl_y_085v_ddi_translations_hdmi[] = {
238 { 0x00000018, 0x000000A1, 0x0 },
239 { 0x00005012, 0x000000DF, 0x0 },
240 { 0x00007011, 0x00000084, 0x0 },
241 { 0x00000018, 0x000000A4, 0x0 },
242 { 0x00000018, 0x0000009D, 0x0 },
243 { 0x00004013, 0x00000080, 0x0 },
244 { 0x00006013, 0x000000C7, 0x0 },
245 { 0x00000018, 0x0000008A, 0x0 },
246 { 0x00003015, 0x000000C7, 0x0 }, /* Default */
247 { 0x80003015, 0x000000C7, 0x7 }, /* Uses I_boost */
248 { 0x00000018, 0x000000C7, 0x0 },
7f88e3af
DL		 249};
250
96fb9f9b
VK		 251struct bxt_ddi_buf_trans {
252 u32 margin; /* swing value */
253 u32 scale; /* scale value */
254 u32 enable; /* scale enable */
255 u32 deemphasis;
256 bool default_index; /* true if the entry represents default value */
257};
258
259/* BSpec does not define separate vswing/pre-emphasis values for eDP.
260 * Using DP values for eDP as well.
261 */
262static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
263 /* Idx NT mV diff db */
fe4c63c8
ID		 264 { 52, 0x9A, 0, 128, true }, /* 0: 400 0 */
265 { 78, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
266 { 104, 0x9A, 0, 64, false }, /* 2: 400 6 */
267 { 154, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
268 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
269 { 116, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
270 { 154, 0x9A, 0, 64, false }, /* 6: 600 6 */
271 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
272 { 154, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
f8896f5d 273 { 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */
96fb9f9b
VK		 274};
275
276/* BSpec has 2 recommended values - entries 0 and 8.
277 * Using the entry with higher vswing.
278 */
279static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
280 /* Idx NT mV diff db */
fe4c63c8
ID		 281 { 52, 0x9A, 0, 128, false }, /* 0: 400 0 */
282 { 52, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
283 { 52, 0x9A, 0, 64, false }, /* 2: 400 6 */
284 { 42, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
285 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
286 { 77, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
287 { 77, 0x9A, 0, 64, false }, /* 6: 600 6 */
288 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
289 { 102, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
96fb9f9b
VK		 290 { 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */
291};
292
f8896f5d
DW		 293static void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
294 enum port port, int type);
295
a1e6ad66
ID		 296static void ddi_get_encoder_port(struct intel_encoder *intel_encoder,
297 struct intel_digital_port **dig_port,
298 enum port *port)
fc914639 299{
0bdee30e 300 struct drm_encoder *encoder = &intel_encoder->base;
fc914639
PZ		 301 int type = intel_encoder->type;
302
0e32b39c 303 if (type == INTEL_OUTPUT_DP_MST) {
a1e6ad66
ID		 304 *dig_port = enc_to_mst(encoder)->primary;
305 *port = (*dig_port)->port;
0e32b39c 306 } else if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP ||
00c09d70 307 type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) {
a1e6ad66
ID		 308 *dig_port = enc_to_dig_port(encoder);
309 *port = (*dig_port)->port;
fc914639 310 } else if (type == INTEL_OUTPUT_ANALOG) {
a1e6ad66
ID		 311 *dig_port = NULL;
312 *port = PORT_E;
fc914639
PZ		 313 } else {
314 DRM_ERROR("Invalid DDI encoder type %d\n", type);
315 BUG();
316 }
317}
318
a1e6ad66
ID		 319enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
320{
321 struct intel_digital_port *dig_port;
322 enum port port;
323
324 ddi_get_encoder_port(intel_encoder, &dig_port, &port);
325
326 return port;
327}
328
ce3b7e9b
DL		 329static bool
330intel_dig_port_supports_hdmi(const struct intel_digital_port *intel_dig_port)
331{
332 return intel_dig_port->hdmi.hdmi_reg;
333}
334
f8896f5d
DW		 335static const struct ddi_buf_trans *skl_get_buf_trans_dp(struct drm_device *dev,
336 int *n_entries)
337{
338 struct drm_i915_private *dev_priv = dev->dev_private;
339 const struct ddi_buf_trans *ddi_translations;
340 static int is_095v = -1;
341
342 if (is_095v == -1) {
343 u32 spr1 = I915_READ(UAIMI_SPR1);
344
345 is_095v = spr1 & SKL_VCCIO_MASK;
346 }
347
348 if (IS_SKL_ULX(dev) && !is_095v) {
349 ddi_translations = skl_y_085v_ddi_translations_dp;
350 *n_entries = ARRAY_SIZE(skl_y_085v_ddi_translations_dp);
351 } else if (IS_SKL_ULT(dev)) {
352 ddi_translations = skl_u_ddi_translations_dp;
353 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
354 } else {
355 ddi_translations = skl_ddi_translations_dp;
356 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
357 }
358
359 return ddi_translations;
360}
361
362static const struct ddi_buf_trans *skl_get_buf_trans_edp(struct drm_device *dev,
363 int *n_entries)
364{
365 struct drm_i915_private *dev_priv = dev->dev_private;
366 const struct ddi_buf_trans *ddi_translations;
367 static int is_095v = -1;
368
369 if (is_095v == -1) {
370 u32 spr1 = I915_READ(UAIMI_SPR1);
371
372 is_095v = spr1 & SKL_VCCIO_MASK;
373 }
374
375 if (IS_SKL_ULX(dev) && !is_095v) {
376 if (dev_priv->edp_low_vswing) {
377 ddi_translations = skl_y_085v_ddi_translations_edp;
378 *n_entries =
379 ARRAY_SIZE(skl_y_085v_ddi_translations_edp);
380 } else {
381 ddi_translations = skl_y_085v_ddi_translations_dp;
382 *n_entries =
383 ARRAY_SIZE(skl_y_085v_ddi_translations_dp);
384 }
385 } else if (IS_SKL_ULT(dev)) {
386 if (dev_priv->edp_low_vswing) {
387 ddi_translations = skl_u_ddi_translations_edp;
388 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
389 } else {
390 ddi_translations = skl_u_ddi_translations_dp;
391 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
392 }
393 } else {
394 if (dev_priv->edp_low_vswing) {
395 ddi_translations = skl_ddi_translations_edp;
396 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
397 } else {
398 ddi_translations = skl_ddi_translations_dp;
399 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
400 }
401 }
402
403 return ddi_translations;
404}
405
406static const struct ddi_buf_trans *
407skl_get_buf_trans_hdmi(struct drm_device *dev,
408 int *n_entries)
409{
410 struct drm_i915_private *dev_priv = dev->dev_private;
411 const struct ddi_buf_trans *ddi_translations;
412 static int is_095v = -1;
413
414 if (is_095v == -1) {
415 u32 spr1 = I915_READ(UAIMI_SPR1);
416
417 is_095v = spr1 & SKL_VCCIO_MASK;
418 }
419
420 if (IS_SKL_ULX(dev) && !is_095v) {
421 ddi_translations = skl_y_085v_ddi_translations_hdmi;
422 *n_entries = ARRAY_SIZE(skl_y_085v_ddi_translations_hdmi);
423 } else {
424 ddi_translations = skl_ddi_translations_hdmi;
425 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
426 }
427
428 return ddi_translations;
429}
430
e58623cb
AR		 431/*
432 * Starting with Haswell, DDI port buffers must be programmed with correct
433 * values in advance. The buffer values are different for FDI and DP modes,
45244b87
ED		 434 * but the HDMI/DVI fields are shared among those. So we program the DDI
435 * in either FDI or DP modes only, as HDMI connections will work with both
436 * of those
437 */
faa0cdbe
ID		 438static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port,
439 bool supports_hdmi)
45244b87
ED		 440{
441 struct drm_i915_private *dev_priv = dev->dev_private;
442 u32 reg;
7ff44670 443 int i, n_hdmi_entries, n_dp_entries, n_edp_entries, hdmi_default_entry,
7ad14a29 444 size;
6acab15a 445 int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
10122051
JN		 446 const struct ddi_buf_trans *ddi_translations_fdi;
447 const struct ddi_buf_trans *ddi_translations_dp;
448 const struct ddi_buf_trans *ddi_translations_edp;
449 const struct ddi_buf_trans *ddi_translations_hdmi;
450 const struct ddi_buf_trans *ddi_translations;
e58623cb 451
96fb9f9b 452 if (IS_BROXTON(dev)) {
faa0cdbe 453 if (!supports_hdmi)
96fb9f9b
VK		 454 return;
455
456 /* Vswing programming for HDMI */
457 bxt_ddi_vswing_sequence(dev, hdmi_level, port,
458 INTEL_OUTPUT_HDMI);
459 return;
460 } else if (IS_SKYLAKE(dev)) {
f8896f5d
DW		 461 ddi_translations_dp =
462 skl_get_buf_trans_dp(dev, &n_dp_entries);
463 ddi_translations_edp =
464 skl_get_buf_trans_edp(dev, &n_edp_entries);
465 ddi_translations_hdmi =
466 skl_get_buf_trans_hdmi(dev, &n_hdmi_entries);
467 hdmi_default_entry = 8;
7f88e3af 468 } else if (IS_BROADWELL(dev)) {
e58623cb
AR		 469 ddi_translations_fdi = bdw_ddi_translations_fdi;
470 ddi_translations_dp = bdw_ddi_translations_dp;
300644c7 471 ddi_translations_edp = bdw_ddi_translations_edp;
a26aa8ba 472 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
7ad14a29
SJ		 473 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
474 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
10122051 475 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
7ff44670 476 hdmi_default_entry = 7;
e58623cb
AR		 477 } else if (IS_HASWELL(dev)) {
478 ddi_translations_fdi = hsw_ddi_translations_fdi;
479 ddi_translations_dp = hsw_ddi_translations_dp;
300644c7 480 ddi_translations_edp = hsw_ddi_translations_dp;
a26aa8ba 481 ddi_translations_hdmi = hsw_ddi_translations_hdmi;
7ad14a29 482 n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
10122051 483 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
7ff44670 484 hdmi_default_entry = 6;
e58623cb
AR		 485 } else {
486 WARN(1, "ddi translation table missing\n");
300644c7 487 ddi_translations_edp = bdw_ddi_translations_dp;
e58623cb
AR		 488 ddi_translations_fdi = bdw_ddi_translations_fdi;
489 ddi_translations_dp = bdw_ddi_translations_dp;
a26aa8ba 490 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
7ad14a29
SJ		 491 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
492 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
10122051 493 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
7ff44670 494 hdmi_default_entry = 7;
e58623cb
AR		 495 }
496
300644c7
PZ		 497 switch (port) {
498 case PORT_A:
499 ddi_translations = ddi_translations_edp;
7ad14a29 500 size = n_edp_entries;
300644c7
PZ		 501 break;
502 case PORT_B:
503 case PORT_C:
300644c7 504 ddi_translations = ddi_translations_dp;
7ad14a29 505 size = n_dp_entries;
300644c7 506 break;
77d8d009 507 case PORT_D:
7ad14a29 508 if (intel_dp_is_edp(dev, PORT_D)) {
77d8d009 509 ddi_translations = ddi_translations_edp;
7ad14a29
SJ		 510 size = n_edp_entries;
511 } else {
77d8d009 512 ddi_translations = ddi_translations_dp;
7ad14a29
SJ		 513 size = n_dp_entries;
514 }
77d8d009 515 break;
300644c7 516 case PORT_E:
7f88e3af
DL		 517 if (ddi_translations_fdi)
518 ddi_translations = ddi_translations_fdi;
519 else
520 ddi_translations = ddi_translations_dp;
7ad14a29 521 size = n_dp_entries;
300644c7
PZ		 522 break;
523 default:
524 BUG();
525 }
45244b87 526
7ad14a29 527 for (i = 0, reg = DDI_BUF_TRANS(port); i < size; i++) {
10122051
JN		 528 I915_WRITE(reg, ddi_translations[i].trans1);
529 reg += 4;
530 I915_WRITE(reg, ddi_translations[i].trans2);
45244b87
ED		 531 reg += 4;
532 }
ce4dd49e 533
faa0cdbe 534 if (!supports_hdmi)
ce3b7e9b
DL		 535 return;
536
ce4dd49e
DL		 537 /* Choose a good default if VBT is badly populated */
538 if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
539 hdmi_level >= n_hdmi_entries)
7ff44670 540 hdmi_level = hdmi_default_entry;
ce4dd49e 541
6acab15a 542 /* Entry 9 is for HDMI: */
10122051
JN		 543 I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans1);
544 reg += 4;
545 I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans2);
546 reg += 4;
45244b87
ED		 547}
548
549/* Program DDI buffers translations for DP. By default, program ports A-D in DP
550 * mode and port E for FDI.
551 */
552void intel_prepare_ddi(struct drm_device *dev)
553{
faa0cdbe 554 struct intel_encoder *intel_encoder;
b403745c 555 bool visited[I915_MAX_PORTS] = { 0, };
45244b87 556
0d536cb4
PZ		 557 if (!HAS_DDI(dev))
558 return;
45244b87 559
faa0cdbe
ID		 560 for_each_intel_encoder(dev, intel_encoder) {
561 struct intel_digital_port *intel_dig_port;
562 enum port port;
563 bool supports_hdmi;
564
565 ddi_get_encoder_port(intel_encoder, &intel_dig_port, &port);
566
567 if (visited[port])
b403745c
DL		 568 continue;
569
faa0cdbe
ID		 570 supports_hdmi = intel_dig_port &&
571 intel_dig_port_supports_hdmi(intel_dig_port);
572
573 intel_prepare_ddi_buffers(dev, port, supports_hdmi);
574 visited[port] = true;
b403745c 575 }
45244b87 576}
c82e4d26 577
248138b5
PZ		 578static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
579 enum port port)
580{
581 uint32_t reg = DDI_BUF_CTL(port);
582 int i;
583
3449ca85 584 for (i = 0; i < 16; i++) {
248138b5
PZ		 585 udelay(1);
586 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
587 return;
588 }
589 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
590}
c82e4d26
ED		 591
592/* Starting with Haswell, different DDI ports can work in FDI mode for
593 * connection to the PCH-located connectors. For this, it is necessary to train
594 * both the DDI port and PCH receiver for the desired DDI buffer settings.
595 *
596 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
597 * please note that when FDI mode is active on DDI E, it shares 2 lines with
598 * DDI A (which is used for eDP)
599 */
600
601void hsw_fdi_link_train(struct drm_crtc *crtc)
602{
603 struct drm_device *dev = crtc->dev;
604 struct drm_i915_private *dev_priv = dev->dev_private;
605 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
04945641 606 u32 temp, i, rx_ctl_val;
c82e4d26 607
04945641
PZ		 608 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
609 * mode set "sequence for CRT port" document:
610 * - TP1 to TP2 time with the default value
611 * - FDI delay to 90h
8693a824
DL		 612 *
613 * WaFDIAutoLinkSetTimingOverrride:hsw
04945641
PZ		 614 */
615 I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
616 FDI_RX_PWRDN_LANE0_VAL(2) |
617 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
618
619 /* Enable the PCH Receiver FDI PLL */
3e68320e 620 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
33d29b14 621 FDI_RX_PLL_ENABLE |
6e3c9717 622 FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
04945641
PZ		 623 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
624 POSTING_READ(_FDI_RXA_CTL);
625 udelay(220);
626
627 /* Switch from Rawclk to PCDclk */
628 rx_ctl_val |= FDI_PCDCLK;
629 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
630
631 /* Configure Port Clock Select */
6e3c9717
ACO		 632 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel);
633 WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL);
04945641
PZ		 634
635 /* Start the training iterating through available voltages and emphasis,
636 * testing each value twice. */
10122051 637 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
c82e4d26
ED		 638 /* Configure DP_TP_CTL with auto-training */
639 I915_WRITE(DP_TP_CTL(PORT_E),
640 DP_TP_CTL_FDI_AUTOTRAIN |
641 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
642 DP_TP_CTL_LINK_TRAIN_PAT1 |
643 DP_TP_CTL_ENABLE);
644
876a8cdf
DL		 645 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
646 * DDI E does not support port reversal, the functionality is
647 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
648 * port reversal bit */
c82e4d26 649 I915_WRITE(DDI_BUF_CTL(PORT_E),
04945641 650 DDI_BUF_CTL_ENABLE |
6e3c9717 651 ((intel_crtc->config->fdi_lanes - 1) << 1) |
c5fe6a06 652 DDI_BUF_TRANS_SELECT(i / 2));
04945641 653 POSTING_READ(DDI_BUF_CTL(PORT_E));
c82e4d26
ED		 654
655 udelay(600);
656
04945641
PZ		 657 /* Program PCH FDI Receiver TU */
658 I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
659
660 /* Enable PCH FDI Receiver with auto-training */
661 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
662 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
663 POSTING_READ(_FDI_RXA_CTL);
664
665 /* Wait for FDI receiver lane calibration */
666 udelay(30);
667
668 /* Unset FDI_RX_MISC pwrdn lanes */
669 temp = I915_READ(_FDI_RXA_MISC);
670 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
671 I915_WRITE(_FDI_RXA_MISC, temp);
672 POSTING_READ(_FDI_RXA_MISC);
673
674 /* Wait for FDI auto training time */
675 udelay(5);
c82e4d26
ED		 676
677 temp = I915_READ(DP_TP_STATUS(PORT_E));
678 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
04945641 679 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
c82e4d26
ED		 680
681 /* Enable normal pixel sending for FDI */
682 I915_WRITE(DP_TP_CTL(PORT_E),
04945641
PZ		 683 DP_TP_CTL_FDI_AUTOTRAIN |
684 DP_TP_CTL_LINK_TRAIN_NORMAL |
685 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
686 DP_TP_CTL_ENABLE);
c82e4d26 687
04945641 688 return;
c82e4d26 689 }
04945641 690
248138b5
PZ		 691 temp = I915_READ(DDI_BUF_CTL(PORT_E));
692 temp &= ~DDI_BUF_CTL_ENABLE;
693 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
694 POSTING_READ(DDI_BUF_CTL(PORT_E));
695
04945641 696 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
248138b5
PZ		 697 temp = I915_READ(DP_TP_CTL(PORT_E));
698 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
699 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
700 I915_WRITE(DP_TP_CTL(PORT_E), temp);
701 POSTING_READ(DP_TP_CTL(PORT_E));
702
703 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
04945641
PZ		 704
705 rx_ctl_val &= ~FDI_RX_ENABLE;
706 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
248138b5 707 POSTING_READ(_FDI_RXA_CTL);
04945641
PZ		 708
709 /* Reset FDI_RX_MISC pwrdn lanes */
710 temp = I915_READ(_FDI_RXA_MISC);
711 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
712 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
713 I915_WRITE(_FDI_RXA_MISC, temp);
248138b5 714 POSTING_READ(_FDI_RXA_MISC);
c82e4d26
ED		 715 }
716
04945641 717 DRM_ERROR("FDI link training failed!\n");
c82e4d26 718}
0e72a5b5 719
44905a27
DA		 720void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
721{
722 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
723 struct intel_digital_port *intel_dig_port =
724 enc_to_dig_port(&encoder->base);
725
726 intel_dp->DP = intel_dig_port->saved_port_bits |
c5fe6a06 727 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
44905a27
DA		 728 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
729
730}
731
8d9ddbcb
PZ		 732static struct intel_encoder *
733intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
734{
735 struct drm_device *dev = crtc->dev;
736 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
737 struct intel_encoder *intel_encoder, *ret = NULL;
738 int num_encoders = 0;
739
740 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
741 ret = intel_encoder;
742 num_encoders++;
743 }
744
745 if (num_encoders != 1)
84f44ce7
VS		 746 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
747 pipe_name(intel_crtc->pipe));
8d9ddbcb
PZ		 748
749 BUG_ON(ret == NULL);
750 return ret;
751}
752
bcddf610 753struct intel_encoder *
3165c074 754intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
d0737e1d 755{
3165c074
ACO		 756 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
757 struct intel_encoder *ret = NULL;
758 struct drm_atomic_state *state;
da3ced29
ACO		 759 struct drm_connector *connector;
760 struct drm_connector_state *connector_state;
d0737e1d 761 int num_encoders = 0;
3165c074 762 int i;
d0737e1d 763
3165c074
ACO		 764 state = crtc_state->base.state;
765
da3ced29
ACO		 766 for_each_connector_in_state(state, connector, connector_state, i) {
767 if (connector_state->crtc != crtc_state->base.crtc)
3165c074
ACO		 768 continue;
769
da3ced29 770 ret = to_intel_encoder(connector_state->best_encoder);
3165c074 771 num_encoders++;
d0737e1d
ACO		 772 }
773
774 WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
775 pipe_name(crtc->pipe));
776
777 BUG_ON(ret == NULL);
778 return ret;
779}
780
1c0b85c5 781#define LC_FREQ 2700
27893390 782#define LC_FREQ_2K U64_C(LC_FREQ * 2000)
1c0b85c5
DL		 783
784#define P_MIN 2
785#define P_MAX 64
786#define P_INC 2
787
788/* Constraints for PLL good behavior */
789#define REF_MIN 48
790#define REF_MAX 400
791#define VCO_MIN 2400
792#define VCO_MAX 4800
793
27893390
DL		 794#define abs_diff(a, b) ({ \
795 typeof(a) __a = (a); \
796 typeof(b) __b = (b); \
797 (void) (&__a == &__b); \
798 __a > __b ? (__a - __b) : (__b - __a); })
1c0b85c5 799
63582983 800struct hsw_wrpll_rnp {
1c0b85c5
DL		 801 unsigned p, n2, r2;
802};
803
63582983 804static unsigned hsw_wrpll_get_budget_for_freq(int clock)
6441ab5f 805{
1c0b85c5
DL		 806 unsigned budget;
807
808 switch (clock) {
809 case 25175000:
810 case 25200000:
811 case 27000000:
812 case 27027000:
813 case 37762500:
814 case 37800000:
815 case 40500000:
816 case 40541000:
817 case 54000000:
818 case 54054000:
819 case 59341000:
820 case 59400000:
821 case 72000000:
822 case 74176000:
823 case 74250000:
824 case 81000000:
825 case 81081000:
826 case 89012000:
827 case 89100000:
828 case 108000000:
829 case 108108000:
830 case 111264000:
831 case 111375000:
832 case 148352000:
833 case 148500000:
834 case 162000000:
835 case 162162000:
836 case 222525000:
837 case 222750000:
838 case 296703000:
839 case 297000000:
840 budget = 0;
841 break;
842 case 233500000:
843 case 245250000:
844 case 247750000:
845 case 253250000:
846 case 298000000:
847 budget = 1500;
848 break;
849 case 169128000:
850 case 169500000:
851 case 179500000:
852 case 202000000:
853 budget = 2000;
854 break;
855 case 256250000:
856 case 262500000:
857 case 270000000:
858 case 272500000:
859 case 273750000:
860 case 280750000:
861 case 281250000:
862 case 286000000:
863 case 291750000:
864 budget = 4000;
865 break;
866 case 267250000:
867 case 268500000:
868 budget = 5000;
869 break;
870 default:
871 budget = 1000;
872 break;
873 }
6441ab5f 874
1c0b85c5
DL		 875 return budget;
876}
877
63582983
DL		 878static void hsw_wrpll_update_rnp(uint64_t freq2k, unsigned budget,
879 unsigned r2, unsigned n2, unsigned p,
880 struct hsw_wrpll_rnp *best)
1c0b85c5
DL		 881{
882 uint64_t a, b, c, d, diff, diff_best;
6441ab5f 883
1c0b85c5
DL		 884 /* No best (r,n,p) yet */
885 if (best->p == 0) {
886 best->p = p;
887 best->n2 = n2;
888 best->r2 = r2;
889 return;
890 }
6441ab5f 891
1c0b85c5
DL		 892 /*
893 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
894 * freq2k.
895 *
896 * delta = 1e6 *
897 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
898 * freq2k;
899 *
900 * and we would like delta <= budget.
901 *
902 * If the discrepancy is above the PPM-based budget, always prefer to
903 * improve upon the previous solution. However, if you're within the
904 * budget, try to maximize Ref * VCO, that is N / (P * R^2).
905 */
906 a = freq2k * budget * p * r2;
907 b = freq2k * budget * best->p * best->r2;
27893390
DL		 908 diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2);
909 diff_best = abs_diff(freq2k * best->p * best->r2,
910 LC_FREQ_2K * best->n2);
1c0b85c5
DL		 911 c = 1000000 * diff;
912 d = 1000000 * diff_best;
913
914 if (a < c && b < d) {
915 /* If both are above the budget, pick the closer */
916 if (best->p * best->r2 * diff < p * r2 * diff_best) {
917 best->p = p;
918 best->n2 = n2;
919 best->r2 = r2;
920 }
921 } else if (a >= c && b < d) {
922 /* If A is below the threshold but B is above it? Update. */
923 best->p = p;
924 best->n2 = n2;
925 best->r2 = r2;
926 } else if (a >= c && b >= d) {
927 /* Both are below the limit, so pick the higher n2/(r2*r2) */
928 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
929 best->p = p;
930 best->n2 = n2;
931 best->r2 = r2;
932 }
933 }
934 /* Otherwise a < c && b >= d, do nothing */
935}
936
63582983 937static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv, int reg)
11578553
JB		 938{
939 int refclk = LC_FREQ;
940 int n, p, r;
941 u32 wrpll;
942
943 wrpll = I915_READ(reg);
114fe488
DV		 944 switch (wrpll & WRPLL_PLL_REF_MASK) {
945 case WRPLL_PLL_SSC:
946 case WRPLL_PLL_NON_SSC:
11578553
JB		 947 /*
948 * We could calculate spread here, but our checking
949 * code only cares about 5% accuracy, and spread is a max of
950 * 0.5% downspread.
951 */
952 refclk = 135;
953 break;
114fe488 954 case WRPLL_PLL_LCPLL:
11578553
JB		 955 refclk = LC_FREQ;
956 break;
957 default:
958 WARN(1, "bad wrpll refclk\n");
959 return 0;
960 }
961
962 r = wrpll & WRPLL_DIVIDER_REF_MASK;
963 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
964 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
965
20f0ec16
JB		 966 /* Convert to KHz, p & r have a fixed point portion */
967 return (refclk * n * 100) / (p * r);
11578553
JB		 968}
969
540e732c
S		 970static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
971 uint32_t dpll)
972{
973 uint32_t cfgcr1_reg, cfgcr2_reg;
974 uint32_t cfgcr1_val, cfgcr2_val;
975 uint32_t p0, p1, p2, dco_freq;
976
977 cfgcr1_reg = GET_CFG_CR1_REG(dpll);
978 cfgcr2_reg = GET_CFG_CR2_REG(dpll);
979
980 cfgcr1_val = I915_READ(cfgcr1_reg);
981 cfgcr2_val = I915_READ(cfgcr2_reg);
982
983 p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
984 p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
985
986 if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1))
987 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
988 else
989 p1 = 1;
990
991
992 switch (p0) {
993 case DPLL_CFGCR2_PDIV_1:
994 p0 = 1;
995 break;
996 case DPLL_CFGCR2_PDIV_2:
997 p0 = 2;
998 break;
999 case DPLL_CFGCR2_PDIV_3:
1000 p0 = 3;
1001 break;
1002 case DPLL_CFGCR2_PDIV_7:
1003 p0 = 7;
1004 break;
1005 }
1006
1007 switch (p2) {
1008 case DPLL_CFGCR2_KDIV_5:
1009 p2 = 5;
1010 break;
1011 case DPLL_CFGCR2_KDIV_2:
1012 p2 = 2;
1013 break;
1014 case DPLL_CFGCR2_KDIV_3:
1015 p2 = 3;
1016 break;
1017 case DPLL_CFGCR2_KDIV_1:
1018 p2 = 1;
1019 break;
1020 }
1021
1022 dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
1023
1024 dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
1025 1000) / 0x8000;
1026
1027 return dco_freq / (p0 * p1 * p2 * 5);
1028}
1029
1030
1031static void skl_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 1032 struct intel_crtc_state *pipe_config)
540e732c
S		 1033{
1034 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
540e732c
S		 1035 int link_clock = 0;
1036 uint32_t dpll_ctl1, dpll;
1037
134ffa44 1038 dpll = pipe_config->ddi_pll_sel;
540e732c
S		 1039
1040 dpll_ctl1 = I915_READ(DPLL_CTRL1);
1041
1042 if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
1043 link_clock = skl_calc_wrpll_link(dev_priv, dpll);
1044 } else {
71cd8423
DL		 1045 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll);
1046 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll);
540e732c
S		 1047
1048 switch (link_clock) {
71cd8423 1049 case DPLL_CTRL1_LINK_RATE_810:
540e732c
S		 1050 link_clock = 81000;
1051 break;
71cd8423 1052 case DPLL_CTRL1_LINK_RATE_1080:
a8f3ef61
SJ		 1053 link_clock = 108000;
1054 break;
71cd8423 1055 case DPLL_CTRL1_LINK_RATE_1350:
540e732c
S		 1056 link_clock = 135000;
1057 break;
71cd8423 1058 case DPLL_CTRL1_LINK_RATE_1620:
a8f3ef61
SJ		 1059 link_clock = 162000;
1060 break;
71cd8423 1061 case DPLL_CTRL1_LINK_RATE_2160:
a8f3ef61
SJ		 1062 link_clock = 216000;
1063 break;
71cd8423 1064 case DPLL_CTRL1_LINK_RATE_2700:
540e732c
S		 1065 link_clock = 270000;
1066 break;
1067 default:
1068 WARN(1, "Unsupported link rate\n");
1069 break;
1070 }
1071 link_clock *= 2;
1072 }
1073
1074 pipe_config->port_clock = link_clock;
1075
1076 if (pipe_config->has_dp_encoder)
2d112de7 1077 pipe_config->base.adjusted_mode.crtc_clock =
540e732c
S		 1078 intel_dotclock_calculate(pipe_config->port_clock,
1079 &pipe_config->dp_m_n);
1080 else
2d112de7 1081 pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
540e732c
S		 1082}
1083
3d51278a 1084static void hsw_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 1085 struct intel_crtc_state *pipe_config)
11578553
JB		 1086{
1087 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
11578553
JB		 1088 int link_clock = 0;
1089 u32 val, pll;
1090
26804afd 1091 val = pipe_config->ddi_pll_sel;
11578553
JB		 1092 switch (val & PORT_CLK_SEL_MASK) {
1093 case PORT_CLK_SEL_LCPLL_810:
1094 link_clock = 81000;
1095 break;
1096 case PORT_CLK_SEL_LCPLL_1350:
1097 link_clock = 135000;
1098 break;
1099 case PORT_CLK_SEL_LCPLL_2700:
1100 link_clock = 270000;
1101 break;
1102 case PORT_CLK_SEL_WRPLL1:
63582983 1103 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1);
11578553
JB		 1104 break;
1105 case PORT_CLK_SEL_WRPLL2:
63582983 1106 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2);
11578553
JB		 1107 break;
1108 case PORT_CLK_SEL_SPLL:
1109 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
1110 if (pll == SPLL_PLL_FREQ_810MHz)
1111 link_clock = 81000;
1112 else if (pll == SPLL_PLL_FREQ_1350MHz)
1113 link_clock = 135000;
1114 else if (pll == SPLL_PLL_FREQ_2700MHz)
1115 link_clock = 270000;
1116 else {
1117 WARN(1, "bad spll freq\n");
1118 return;
1119 }
1120 break;
1121 default:
1122 WARN(1, "bad port clock sel\n");
1123 return;
1124 }
1125
1126 pipe_config->port_clock = link_clock * 2;
1127
1128 if (pipe_config->has_pch_encoder)
2d112de7 1129 pipe_config->base.adjusted_mode.crtc_clock =
11578553
JB		 1130 intel_dotclock_calculate(pipe_config->port_clock,
1131 &pipe_config->fdi_m_n);
1132 else if (pipe_config->has_dp_encoder)
2d112de7 1133 pipe_config->base.adjusted_mode.crtc_clock =
11578553
JB		 1134 intel_dotclock_calculate(pipe_config->port_clock,
1135 &pipe_config->dp_m_n);
1136 else
2d112de7 1137 pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
11578553
JB		 1138}
1139
977bb38d
S		 1140static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
1141 enum intel_dpll_id dpll)
1142{
1143 /* FIXME formula not available in bspec */
1144 return 0;
1145}
1146
1147static void bxt_ddi_clock_get(struct intel_encoder *encoder,
1148 struct intel_crtc_state *pipe_config)
1149{
1150 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1151 enum port port = intel_ddi_get_encoder_port(encoder);
1152 uint32_t dpll = port;
1153
1154 pipe_config->port_clock =
1155 bxt_calc_pll_link(dev_priv, dpll);
1156
1157 if (pipe_config->has_dp_encoder)
1158 pipe_config->base.adjusted_mode.crtc_clock =
1159 intel_dotclock_calculate(pipe_config->port_clock,
1160 &pipe_config->dp_m_n);
1161 else
1162 pipe_config->base.adjusted_mode.crtc_clock =
1163 pipe_config->port_clock;
1164}
1165
3d51278a 1166void intel_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 1167 struct intel_crtc_state *pipe_config)
3d51278a 1168{
22606a18
DL		 1169 struct drm_device *dev = encoder->base.dev;
1170
1171 if (INTEL_INFO(dev)->gen <= 8)
1172 hsw_ddi_clock_get(encoder, pipe_config);
977bb38d 1173 else if (IS_SKYLAKE(dev))
22606a18 1174 skl_ddi_clock_get(encoder, pipe_config);
977bb38d
S		 1175 else if (IS_BROXTON(dev))
1176 bxt_ddi_clock_get(encoder, pipe_config);
3d51278a
DV		 1177}
1178
1c0b85c5 1179static void
d664c0ce
DL		 1180hsw_ddi_calculate_wrpll(int clock /* in Hz */,
1181 unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
1c0b85c5
DL		 1182{
1183 uint64_t freq2k;
1184 unsigned p, n2, r2;
63582983 1185 struct hsw_wrpll_rnp best = { 0, 0, 0 };
1c0b85c5
DL		 1186 unsigned budget;
1187
1188 freq2k = clock / 100;
1189
63582983 1190 budget = hsw_wrpll_get_budget_for_freq(clock);
1c0b85c5
DL		 1191
1192 /* Special case handling for 540 pixel clock: bypass WR PLL entirely
1193 * and directly pass the LC PLL to it. */
1194 if (freq2k == 5400000) {
1195 *n2_out = 2;
1196 *p_out = 1;
1197 *r2_out = 2;
1198 return;
1199 }
1200
1201 /*
1202 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
1203 * the WR PLL.
1204 *
1205 * We want R so that REF_MIN <= Ref <= REF_MAX.
1206 * Injecting R2 = 2 * R gives:
1207 * REF_MAX * r2 > LC_FREQ * 2 and
1208 * REF_MIN * r2 < LC_FREQ * 2
1209 *
1210 * Which means the desired boundaries for r2 are:
1211 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
1212 *
1213 */
1214 for (r2 = LC_FREQ * 2 / REF_MAX + 1;
1215 r2 <= LC_FREQ * 2 / REF_MIN;
1216 r2++) {
1217
1218 /*
1219 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
1220 *
1221 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
1222 * Injecting R2 = 2 * R and N2 = 2 * N, we get:
1223 * VCO_MAX * r2 > n2 * LC_FREQ and
1224 * VCO_MIN * r2 < n2 * LC_FREQ)
1225 *
1226 * Which means the desired boundaries for n2 are:
1227 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
1228 */
1229 for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
1230 n2 <= VCO_MAX * r2 / LC_FREQ;
1231 n2++) {
1232
1233 for (p = P_MIN; p <= P_MAX; p += P_INC)
63582983
DL		 1234 hsw_wrpll_update_rnp(freq2k, budget,
1235 r2, n2, p, &best);
1c0b85c5
DL		 1236 }
1237 }
6441ab5f 1238
1c0b85c5
DL		 1239 *n2_out = best.n2;
1240 *p_out = best.p;
1241 *r2_out = best.r2;
6441ab5f
PZ		 1242}
1243
0220ab6e 1244static bool
d664c0ce 1245hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
190f68c5 1246 struct intel_crtc_state *crtc_state,
d664c0ce
DL		 1247 struct intel_encoder *intel_encoder,
1248 int clock)
6441ab5f 1249{
d664c0ce 1250 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
e0b01be4 1251 struct intel_shared_dpll *pll;
716c2e55 1252 uint32_t val;
1c0b85c5 1253 unsigned p, n2, r2;
6441ab5f 1254
d664c0ce 1255 hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
0694001b 1256
114fe488 1257 val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
0694001b
PZ		 1258 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
1259 WRPLL_DIVIDER_POST(p);
1260
dd3cd74a
ACO		 1261 memset(&crtc_state->dpll_hw_state, 0,
1262 sizeof(crtc_state->dpll_hw_state));
1263
190f68c5 1264 crtc_state->dpll_hw_state.wrpll = val;
6441ab5f 1265
190f68c5 1266 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
716c2e55
DV		 1267 if (pll == NULL) {
1268 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1269 pipe_name(intel_crtc->pipe));
1270 return false;
0694001b 1271 }
d452c5b6 1272
190f68c5 1273 crtc_state->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);
6441ab5f
PZ		 1274 }
1275
6441ab5f
PZ		 1276 return true;
1277}
1278
dc253813
DL		 1279struct skl_wrpll_context {
1280 uint64_t min_deviation; /* current minimal deviation */
1281 uint64_t central_freq; /* chosen central freq */
1282 uint64_t dco_freq; /* chosen dco freq */
1283 unsigned int p; /* chosen divider */
1284};
1285
1286static void skl_wrpll_context_init(struct skl_wrpll_context *ctx)
1287{
1288 memset(ctx, 0, sizeof(*ctx));
1289
1290 ctx->min_deviation = U64_MAX;
1291}
1292
1293/* DCO freq must be within +1%/-6% of the DCO central freq */
1294#define SKL_DCO_MAX_PDEVIATION 100
1295#define SKL_DCO_MAX_NDEVIATION 600
1296
1297static void skl_wrpll_try_divider(struct skl_wrpll_context *ctx,
1298 uint64_t central_freq,
1299 uint64_t dco_freq,
1300 unsigned int divider)
1301{
1302 uint64_t deviation;
1303
1304 deviation = div64_u64(10000 * abs_diff(dco_freq, central_freq),
1305 central_freq);
1306
1307 /* positive deviation */
1308 if (dco_freq >= central_freq) {
1309 if (deviation < SKL_DCO_MAX_PDEVIATION &&
1310 deviation < ctx->min_deviation) {
1311 ctx->min_deviation = deviation;
1312 ctx->central_freq = central_freq;
1313 ctx->dco_freq = dco_freq;
1314 ctx->p = divider;
1315 }
1316 /* negative deviation */
1317 } else if (deviation < SKL_DCO_MAX_NDEVIATION &&
1318 deviation < ctx->min_deviation) {
1319 ctx->min_deviation = deviation;
1320 ctx->central_freq = central_freq;
1321 ctx->dco_freq = dco_freq;
1322 ctx->p = divider;
1323 }
dc253813
DL		 1324}
1325
1326static void skl_wrpll_get_multipliers(unsigned int p,
1327 unsigned int *p0 /* out */,
1328 unsigned int *p1 /* out */,
1329 unsigned int *p2 /* out */)
1330{
1331 /* even dividers */
1332 if (p % 2 == 0) {
1333 unsigned int half = p / 2;
1334
1335 if (half == 1 || half == 2 || half == 3 || half == 5) {
1336 *p0 = 2;
1337 *p1 = 1;
1338 *p2 = half;
1339 } else if (half % 2 == 0) {
1340 *p0 = 2;
1341 *p1 = half / 2;
1342 *p2 = 2;
1343 } else if (half % 3 == 0) {
1344 *p0 = 3;
1345 *p1 = half / 3;
1346 *p2 = 2;
1347 } else if (half % 7 == 0) {
1348 *p0 = 7;
1349 *p1 = half / 7;
1350 *p2 = 2;
1351 }
1352 } else if (p == 3 || p == 9) { /* 3, 5, 7, 9, 15, 21, 35 */
1353 *p0 = 3;
1354 *p1 = 1;
1355 *p2 = p / 3;
1356 } else if (p == 5 || p == 7) {
1357 *p0 = p;
1358 *p1 = 1;
1359 *p2 = 1;
1360 } else if (p == 15) {
1361 *p0 = 3;
1362 *p1 = 1;
1363 *p2 = 5;
1364 } else if (p == 21) {
1365 *p0 = 7;
1366 *p1 = 1;
1367 *p2 = 3;
1368 } else if (p == 35) {
1369 *p0 = 7;
1370 *p1 = 1;
1371 *p2 = 5;
1372 }
1373}
1374
82d35437
S		 1375struct skl_wrpll_params {
1376 uint32_t dco_fraction;
1377 uint32_t dco_integer;
1378 uint32_t qdiv_ratio;
1379 uint32_t qdiv_mode;
1380 uint32_t kdiv;
1381 uint32_t pdiv;
1382 uint32_t central_freq;
1383};
1384
76516fbc
DL		 1385static void skl_wrpll_params_populate(struct skl_wrpll_params *params,
1386 uint64_t afe_clock,
1387 uint64_t central_freq,
1388 uint32_t p0, uint32_t p1, uint32_t p2)
1389{
1390 uint64_t dco_freq;
1391
76516fbc
DL		 1392 switch (central_freq) {
1393 case 9600000000ULL:
1394 params->central_freq = 0;
1395 break;
1396 case 9000000000ULL:
1397 params->central_freq = 1;
1398 break;
1399 case 8400000000ULL:
1400 params->central_freq = 3;
1401 }
1402
1403 switch (p0) {
1404 case 1:
1405 params->pdiv = 0;
1406 break;
1407 case 2:
1408 params->pdiv = 1;
1409 break;
1410 case 3:
1411 params->pdiv = 2;
1412 break;
1413 case 7:
1414 params->pdiv = 4;
1415 break;
1416 default:
1417 WARN(1, "Incorrect PDiv\n");
1418 }
1419
1420 switch (p2) {
1421 case 5:
1422 params->kdiv = 0;
1423 break;
1424 case 2:
1425 params->kdiv = 1;
1426 break;
1427 case 3:
1428 params->kdiv = 2;
1429 break;
1430 case 1:
1431 params->kdiv = 3;
1432 break;
1433 default:
1434 WARN(1, "Incorrect KDiv\n");
1435 }
1436
1437 params->qdiv_ratio = p1;
1438 params->qdiv_mode = (params->qdiv_ratio == 1) ? 0 : 1;
1439
1440 dco_freq = p0 * p1 * p2 * afe_clock;
1441
1442 /*
1443 * Intermediate values are in Hz.
1444 * Divide by MHz to match bsepc
1445 */
30a7862d 1446 params->dco_integer = div_u64(dco_freq, 24 * MHz(1));
76516fbc 1447 params->dco_fraction =
30a7862d
DL		 1448 div_u64((div_u64(dco_freq, 24) -
1449 params->dco_integer * MHz(1)) * 0x8000, MHz(1));
76516fbc
DL		 1450}
1451
318bd821 1452static bool
82d35437
S		 1453skl_ddi_calculate_wrpll(int clock /* in Hz */,
1454 struct skl_wrpll_params *wrpll_params)
1455{
1456 uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
21318cce
DL		 1457 uint64_t dco_central_freq[3] = {8400000000ULL,
1458 9000000000ULL,
1459 9600000000ULL};
dc253813
DL		 1460 static const int even_dividers[] = { 4, 6, 8, 10, 12, 14, 16, 18, 20,
1461 24, 28, 30, 32, 36, 40, 42, 44,
1462 48, 52, 54, 56, 60, 64, 66, 68,
1463 70, 72, 76, 78, 80, 84, 88, 90,
1464 92, 96, 98 };
1465 static const int odd_dividers[] = { 3, 5, 7, 9, 15, 21, 35 };
1466 static const struct {
1467 const int *list;
1468 int n_dividers;
1469 } dividers[] = {
1470 { even_dividers, ARRAY_SIZE(even_dividers) },
1471 { odd_dividers, ARRAY_SIZE(odd_dividers) },
1472 };
1473 struct skl_wrpll_context ctx;
1474 unsigned int dco, d, i;
1475 unsigned int p0, p1, p2;
1476
1477 skl_wrpll_context_init(&ctx);
1478
1479 for (d = 0; d < ARRAY_SIZE(dividers); d++) {
1480 for (dco = 0; dco < ARRAY_SIZE(dco_central_freq); dco++) {
1481 for (i = 0; i < dividers[d].n_dividers; i++) {
1482 unsigned int p = dividers[d].list[i];
1483 uint64_t dco_freq = p * afe_clock;
1484
1485 skl_wrpll_try_divider(&ctx,
1486 dco_central_freq[dco],
1487 dco_freq,
1488 p);
e7ad9878
DL		 1489 /*
1490 * Skip the remaining dividers if we're sure to
1491 * have found the definitive divider, we can't
1492 * improve a 0 deviation.
1493 */
1494 if (ctx.min_deviation == 0)
1495 goto skip_remaining_dividers;
82d35437
S		 1496 }
1497 }
267db663 1498
e7ad9878 1499skip_remaining_dividers:
267db663
DL		 1500 /*
1501 * If a solution is found with an even divider, prefer
1502 * this one.
1503 */
1504 if (d == 0 && ctx.p)
1505 break;
82d35437
S		 1506 }
1507
dc253813
DL		 1508 if (!ctx.p) {
1509 DRM_DEBUG_DRIVER("No valid divider found for %dHz\n", clock);
318bd821 1510 return false;
dc253813 1511 }
82d35437 1512
dc253813
DL		 1513 /*
1514 * gcc incorrectly analyses that these can be used without being
1515 * initialized. To be fair, it's hard to guess.
1516 */
1517 p0 = p1 = p2 = 0;
1518 skl_wrpll_get_multipliers(ctx.p, &p0, &p1, &p2);
1519 skl_wrpll_params_populate(wrpll_params, afe_clock, ctx.central_freq,
1520 p0, p1, p2);
318bd821
DL		 1521
1522 return true;
82d35437
S		 1523}
1524
82d35437
S		 1525static bool
1526skl_ddi_pll_select(struct intel_crtc *intel_crtc,
190f68c5 1527 struct intel_crtc_state *crtc_state,
82d35437
S		 1528 struct intel_encoder *intel_encoder,
1529 int clock)
1530{
1531 struct intel_shared_dpll *pll;
1532 uint32_t ctrl1, cfgcr1, cfgcr2;
1533
1534 /*
1535 * See comment in intel_dpll_hw_state to understand why we always use 0
1536 * as the DPLL id in this function.
1537 */
1538
1539 ctrl1 = DPLL_CTRL1_OVERRIDE(0);
1540
1541 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1542 struct skl_wrpll_params wrpll_params = { 0, };
1543
1544 ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
1545
318bd821
DL		 1546 if (!skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params))
1547 return false;
82d35437
S		 1548
1549 cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE |
1550 DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) |
1551 wrpll_params.dco_integer;
1552
1553 cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) |
1554 DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) |
1555 DPLL_CFGCR2_KDIV(wrpll_params.kdiv) |
1556 DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
1557 wrpll_params.central_freq;
1558 } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
1559 struct drm_encoder *encoder = &intel_encoder->base;
1560 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1561
1562 switch (intel_dp->link_bw) {
1563 case DP_LINK_BW_1_62:
71cd8423 1564 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0);
82d35437
S		 1565 break;
1566 case DP_LINK_BW_2_7:
71cd8423 1567 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0);
82d35437
S		 1568 break;
1569 case DP_LINK_BW_5_4:
71cd8423 1570 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0);
82d35437
S		 1571 break;
1572 }
1573
1574 cfgcr1 = cfgcr2 = 0;
1575 } else /* eDP */
1576 return true;
1577
dd3cd74a
ACO		 1578 memset(&crtc_state->dpll_hw_state, 0,
1579 sizeof(crtc_state->dpll_hw_state));
1580
190f68c5
ACO		 1581 crtc_state->dpll_hw_state.ctrl1 = ctrl1;
1582 crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
1583 crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
82d35437 1584
190f68c5 1585 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
82d35437
S		 1586 if (pll == NULL) {
1587 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1588 pipe_name(intel_crtc->pipe));
1589 return false;
1590 }
1591
1592 /* shared DPLL id 0 is DPLL 1 */
190f68c5 1593 crtc_state->ddi_pll_sel = pll->id + 1;
82d35437
S		 1594
1595 return true;
1596}
0220ab6e 1597
d683f3bc
S		 1598/* bxt clock parameters */
1599struct bxt_clk_div {
64987fc5 1600 int clock;
d683f3bc
S		 1601 uint32_t p1;
1602 uint32_t p2;
1603 uint32_t m2_int;
1604 uint32_t m2_frac;
1605 bool m2_frac_en;
1606 uint32_t n;
d683f3bc
S		 1607};
1608
1609/* pre-calculated values for DP linkrates */
64987fc5
SJ		 1610static const struct bxt_clk_div bxt_dp_clk_val[] = {
1611 {162000, 4, 2, 32, 1677722, 1, 1},
1612 {270000, 4, 1, 27, 0, 0, 1},
1613 {540000, 2, 1, 27, 0, 0, 1},
1614 {216000, 3, 2, 32, 1677722, 1, 1},
1615 {243000, 4, 1, 24, 1258291, 1, 1},
1616 {324000, 4, 1, 32, 1677722, 1, 1},
1617 {432000, 3, 1, 32, 1677722, 1, 1}
d683f3bc
S		 1618};
1619
1620static bool
1621bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
1622 struct intel_crtc_state *crtc_state,
1623 struct intel_encoder *intel_encoder,
1624 int clock)
1625{
1626 struct intel_shared_dpll *pll;
1627 struct bxt_clk_div clk_div = {0};
b6dc71f3
VK		 1628 int vco = 0;
1629 uint32_t prop_coef, int_coef, gain_ctl, targ_cnt;
e0681e38 1630 uint32_t dcoampovr_en_h, dco_amp, lanestagger;
d683f3bc
S		 1631
1632 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1633 intel_clock_t best_clock;
1634
1635 /* Calculate HDMI div */
1636 /*
1637 * FIXME: tie the following calculation into
1638 * i9xx_crtc_compute_clock
1639 */
1640 if (!bxt_find_best_dpll(crtc_state, clock, &best_clock)) {
1641 DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n",
1642 clock, pipe_name(intel_crtc->pipe));
1643 return false;
1644 }
1645
1646 clk_div.p1 = best_clock.p1;
1647 clk_div.p2 = best_clock.p2;
1648 WARN_ON(best_clock.m1 != 2);
1649 clk_div.n = best_clock.n;
1650 clk_div.m2_int = best_clock.m2 >> 22;
1651 clk_div.m2_frac = best_clock.m2 & ((1 << 22) - 1);
1652 clk_div.m2_frac_en = clk_div.m2_frac != 0;
1653
b6dc71f3 1654 vco = best_clock.vco;
d683f3bc
S		 1655 } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
1656 intel_encoder->type == INTEL_OUTPUT_EDP) {
64987fc5 1657 int i;
d683f3bc 1658
64987fc5
SJ		 1659 clk_div = bxt_dp_clk_val[0];
1660 for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
1661 if (bxt_dp_clk_val[i].clock == clock) {
1662 clk_div = bxt_dp_clk_val[i];
1663 break;
1664 }
d683f3bc 1665 }
b6dc71f3
VK		 1666 vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2;
1667 }
1668
1669 dco_amp = 15;
1670 dcoampovr_en_h = 0;
1671 if (vco >= 6200000 && vco <= 6480000) {
1672 prop_coef = 4;
1673 int_coef = 9;
1674 gain_ctl = 3;
1675 targ_cnt = 8;
1676 } else if ((vco > 5400000 && vco < 6200000) ||
1677 (vco >= 4800000 && vco < 5400000)) {
1678 prop_coef = 5;
1679 int_coef = 11;
1680 gain_ctl = 3;
1681 targ_cnt = 9;
1682 if (vco >= 4800000 && vco < 5400000)
1683 dcoampovr_en_h = 1;
1684 } else if (vco == 5400000) {
1685 prop_coef = 3;
1686 int_coef = 8;
1687 gain_ctl = 1;
1688 targ_cnt = 9;
1689 } else {
1690 DRM_ERROR("Invalid VCO\n");
1691 return false;
d683f3bc
S		 1692 }
1693
dd3cd74a
ACO		 1694 memset(&crtc_state->dpll_hw_state, 0,
1695 sizeof(crtc_state->dpll_hw_state));
1696
e0681e38
VK		 1697 if (clock > 270000)
1698 lanestagger = 0x18;
1699 else if (clock > 135000)
1700 lanestagger = 0x0d;
1701 else if (clock > 67000)
1702 lanestagger = 0x07;
1703 else if (clock > 33000)
1704 lanestagger = 0x04;
1705 else
1706 lanestagger = 0x02;
1707
d683f3bc
S		 1708 crtc_state->dpll_hw_state.ebb0 =
1709 PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2);
1710 crtc_state->dpll_hw_state.pll0 = clk_div.m2_int;
1711 crtc_state->dpll_hw_state.pll1 = PORT_PLL_N(clk_div.n);
1712 crtc_state->dpll_hw_state.pll2 = clk_div.m2_frac;
1713
1714 if (clk_div.m2_frac_en)
1715 crtc_state->dpll_hw_state.pll3 =
1716 PORT_PLL_M2_FRAC_ENABLE;
1717
1718 crtc_state->dpll_hw_state.pll6 =
b6dc71f3 1719 prop_coef | PORT_PLL_INT_COEFF(int_coef);
d683f3bc 1720 crtc_state->dpll_hw_state.pll6 |=
b6dc71f3
VK		 1721 PORT_PLL_GAIN_CTL(gain_ctl);
1722
1723 crtc_state->dpll_hw_state.pll8 = targ_cnt;
d683f3bc 1724
b6dc71f3
VK		 1725 if (dcoampovr_en_h)
1726 crtc_state->dpll_hw_state.pll10 = PORT_PLL_DCO_AMP_OVR_EN_H;
1727
1728 crtc_state->dpll_hw_state.pll10 |= PORT_PLL_DCO_AMP(dco_amp);
d683f3bc
S		 1729
1730 crtc_state->dpll_hw_state.pcsdw12 =
e0681e38 1731 LANESTAGGER_STRAP_OVRD | lanestagger;
d683f3bc
S		 1732
1733 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
1734 if (pll == NULL) {
1735 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1736 pipe_name(intel_crtc->pipe));
1737 return false;
1738 }
1739
1740 /* shared DPLL id 0 is DPLL A */
1741 crtc_state->ddi_pll_sel = pll->id;
1742
1743 return true;
1744}
1745
0220ab6e
DL		 1746/*
1747 * Tries to find a *shared* PLL for the CRTC and store it in
1748 * intel_crtc->ddi_pll_sel.
1749 *
1750 * For private DPLLs, compute_config() should do the selection for us. This
1751 * function should be folded into compute_config() eventually.
1752 */
190f68c5
ACO		 1753bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
1754 struct intel_crtc_state *crtc_state)
0220ab6e 1755{
82d35437 1756 struct drm_device *dev = intel_crtc->base.dev;
d0737e1d 1757 struct intel_encoder *intel_encoder =
3165c074 1758 intel_ddi_get_crtc_new_encoder(crtc_state);
190f68c5 1759 int clock = crtc_state->port_clock;
0220ab6e 1760
82d35437 1761 if (IS_SKYLAKE(dev))
190f68c5
ACO		 1762 return skl_ddi_pll_select(intel_crtc, crtc_state,
1763 intel_encoder, clock);
d683f3bc
S		 1764 else if (IS_BROXTON(dev))
1765 return bxt_ddi_pll_select(intel_crtc, crtc_state,
1766 intel_encoder, clock);
82d35437 1767 else
190f68c5
ACO		 1768 return hsw_ddi_pll_select(intel_crtc, crtc_state,
1769 intel_encoder, clock);
0220ab6e
DL		 1770}
1771
dae84799
PZ		 1772void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
1773{
1774 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1775 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1776 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
6e3c9717 1777 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
dae84799
PZ		 1778 int type = intel_encoder->type;
1779 uint32_t temp;
1780
0e32b39c 1781 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
c9809791 1782 temp = TRANS_MSA_SYNC_CLK;
6e3c9717 1783 switch (intel_crtc->config->pipe_bpp) {
dae84799 1784 case 18:
c9809791 1785 temp |= TRANS_MSA_6_BPC;
dae84799
PZ		 1786 break;
1787 case 24:
c9809791 1788 temp |= TRANS_MSA_8_BPC;
dae84799
PZ		 1789 break;
1790 case 30:
c9809791 1791 temp |= TRANS_MSA_10_BPC;
dae84799
PZ		 1792 break;
1793 case 36:
c9809791 1794 temp |= TRANS_MSA_12_BPC;
dae84799
PZ		 1795 break;
1796 default:
4e53c2e0 1797 BUG();
dae84799 1798 }
c9809791 1799 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
dae84799
PZ		 1800 }
1801}
1802
0e32b39c
DA		 1803void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state)
1804{
1805 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1806 struct drm_device *dev = crtc->dev;
1807 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1808 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
0e32b39c
DA		 1809 uint32_t temp;
1810 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1811 if (state == true)
1812 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1813 else
1814 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1815 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1816}
1817
8228c251 1818void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
8d9ddbcb
PZ		 1819{
1820 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1821 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
7739c33b 1822 struct drm_encoder *encoder = &intel_encoder->base;
c7670b10
PZ		 1823 struct drm_device *dev = crtc->dev;
1824 struct drm_i915_private *dev_priv = dev->dev_private;
8d9ddbcb 1825 enum pipe pipe = intel_crtc->pipe;
6e3c9717 1826 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
174edf1f 1827 enum port port = intel_ddi_get_encoder_port(intel_encoder);
7739c33b 1828 int type = intel_encoder->type;
8d9ddbcb
PZ		 1829 uint32_t temp;
1830
ad80a810
PZ		 1831 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1832 temp = TRANS_DDI_FUNC_ENABLE;
174edf1f 1833 temp |= TRANS_DDI_SELECT_PORT(port);
dfcef252 1834
6e3c9717 1835 switch (intel_crtc->config->pipe_bpp) {
dfcef252 1836 case 18:
ad80a810 1837 temp |= TRANS_DDI_BPC_6;
dfcef252
PZ		 1838 break;
1839 case 24:
ad80a810 1840 temp |= TRANS_DDI_BPC_8;
dfcef252
PZ		 1841 break;
1842 case 30:
ad80a810 1843 temp |= TRANS_DDI_BPC_10;
dfcef252
PZ		 1844 break;
1845 case 36:
ad80a810 1846 temp |= TRANS_DDI_BPC_12;
dfcef252
PZ		 1847 break;
1848 default:
4e53c2e0 1849 BUG();
dfcef252 1850 }
72662e10 1851
6e3c9717 1852 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
ad80a810 1853 temp |= TRANS_DDI_PVSYNC;
6e3c9717 1854 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
ad80a810 1855 temp |= TRANS_DDI_PHSYNC;
f63eb7c4 1856
e6f0bfc4
PZ		 1857 if (cpu_transcoder == TRANSCODER_EDP) {
1858 switch (pipe) {
1859 case PIPE_A:
c7670b10
PZ		 1860 /* On Haswell, can only use the always-on power well for
1861 * eDP when not using the panel fitter, and when not
1862 * using motion blur mitigation (which we don't
1863 * support). */
fabf6e51 1864 if (IS_HASWELL(dev) &&
6e3c9717
ACO		 1865 (intel_crtc->config->pch_pfit.enabled ||
1866 intel_crtc->config->pch_pfit.force_thru))
d6dd9eb1
DV		 1867 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1868 else
1869 temp |= TRANS_DDI_EDP_INPUT_A_ON;
e6f0bfc4
PZ		 1870 break;
1871 case PIPE_B:
1872 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1873 break;
1874 case PIPE_C:
1875 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1876 break;
1877 default:
1878 BUG();
1879 break;
1880 }
1881 }
1882
7739c33b 1883 if (type == INTEL_OUTPUT_HDMI) {
6e3c9717 1884 if (intel_crtc->config->has_hdmi_sink)
ad80a810 1885 temp |= TRANS_DDI_MODE_SELECT_HDMI;
8d9ddbcb 1886 else
ad80a810 1887 temp |= TRANS_DDI_MODE_SELECT_DVI;
8d9ddbcb 1888
7739c33b 1889 } else if (type == INTEL_OUTPUT_ANALOG) {
ad80a810 1890 temp |= TRANS_DDI_MODE_SELECT_FDI;
6e3c9717 1891 temp |= (intel_crtc->config->fdi_lanes - 1) << 1;
7739c33b
PZ		 1892
1893 } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
1894 type == INTEL_OUTPUT_EDP) {
1895 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1896
0e32b39c
DA		 1897 if (intel_dp->is_mst) {
1898 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1899 } else
1900 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1901
1902 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
1903 } else if (type == INTEL_OUTPUT_DP_MST) {
1904 struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp;
1905
1906 if (intel_dp->is_mst) {
1907 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1908 } else
1909 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
7739c33b 1910
17aa6be9 1911 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
8d9ddbcb 1912 } else {
84f44ce7
VS		 1913 WARN(1, "Invalid encoder type %d for pipe %c\n",
1914 intel_encoder->type, pipe_name(pipe));
8d9ddbcb
PZ		 1915 }
1916
ad80a810 1917 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
8d9ddbcb 1918}
72662e10 1919
ad80a810
PZ		 1920void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1921 enum transcoder cpu_transcoder)
8d9ddbcb 1922{
ad80a810 1923 uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
8d9ddbcb
PZ		 1924 uint32_t val = I915_READ(reg);
1925
0e32b39c 1926 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
ad80a810 1927 val |= TRANS_DDI_PORT_NONE;
8d9ddbcb 1928 I915_WRITE(reg, val);
72662e10
ED		 1929}
1930
bcbc889b
PZ		 1931bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1932{
1933 struct drm_device *dev = intel_connector->base.dev;
1934 struct drm_i915_private *dev_priv = dev->dev_private;
1935 struct intel_encoder *intel_encoder = intel_connector->encoder;
1936 int type = intel_connector->base.connector_type;
1937 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1938 enum pipe pipe = 0;
1939 enum transcoder cpu_transcoder;
882244a3 1940 enum intel_display_power_domain power_domain;
bcbc889b
PZ		 1941 uint32_t tmp;
1942
882244a3 1943 power_domain = intel_display_port_power_domain(intel_encoder);
f458ebbc 1944 if (!intel_display_power_is_enabled(dev_priv, power_domain))
882244a3
PZ		 1945 return false;
1946
bcbc889b
PZ		 1947 if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
1948 return false;
1949
1950 if (port == PORT_A)
1951 cpu_transcoder = TRANSCODER_EDP;
1952 else
1a240d4d 1953 cpu_transcoder = (enum transcoder) pipe;
bcbc889b
PZ		 1954
1955 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1956
1957 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1958 case TRANS_DDI_MODE_SELECT_HDMI:
1959 case TRANS_DDI_MODE_SELECT_DVI:
1960 return (type == DRM_MODE_CONNECTOR_HDMIA);
1961
1962 case TRANS_DDI_MODE_SELECT_DP_SST:
1963 if (type == DRM_MODE_CONNECTOR_eDP)
1964 return true;
bcbc889b 1965 return (type == DRM_MODE_CONNECTOR_DisplayPort);
0e32b39c
DA		 1966 case TRANS_DDI_MODE_SELECT_DP_MST:
1967 /* if the transcoder is in MST state then
1968 * connector isn't connected */
1969 return false;
bcbc889b
PZ		 1970
1971 case TRANS_DDI_MODE_SELECT_FDI:
1972 return (type == DRM_MODE_CONNECTOR_VGA);
1973
1974 default:
1975 return false;
1976 }
1977}
1978
85234cdc
DV		 1979bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1980 enum pipe *pipe)
1981{
1982 struct drm_device *dev = encoder->base.dev;
1983 struct drm_i915_private *dev_priv = dev->dev_private;
fe43d3f5 1984 enum port port = intel_ddi_get_encoder_port(encoder);
6d129bea 1985 enum intel_display_power_domain power_domain;
85234cdc
DV		 1986 u32 tmp;
1987 int i;
1988
6d129bea 1989 power_domain = intel_display_port_power_domain(encoder);
f458ebbc 1990 if (!intel_display_power_is_enabled(dev_priv, power_domain))
6d129bea
ID		 1991 return false;
1992
fe43d3f5 1993 tmp = I915_READ(DDI_BUF_CTL(port));
85234cdc
DV		 1994
1995 if (!(tmp & DDI_BUF_CTL_ENABLE))
1996 return false;
1997
ad80a810
PZ		 1998 if (port == PORT_A) {
1999 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
85234cdc 2000
ad80a810
PZ		 2001 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
2002 case TRANS_DDI_EDP_INPUT_A_ON:
2003 case TRANS_DDI_EDP_INPUT_A_ONOFF:
2004 *pipe = PIPE_A;
2005 break;
2006 case TRANS_DDI_EDP_INPUT_B_ONOFF:
2007 *pipe = PIPE_B;
2008 break;
2009 case TRANS_DDI_EDP_INPUT_C_ONOFF:
2010 *pipe = PIPE_C;
2011 break;
2012 }
2013
2014 return true;
2015 } else {
2016 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
2017 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
2018
2019 if ((tmp & TRANS_DDI_PORT_MASK)
2020 == TRANS_DDI_SELECT_PORT(port)) {
0e32b39c
DA		 2021 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST)
2022 return false;
2023
ad80a810
PZ		 2024 *pipe = i;
2025 return true;
2026 }
85234cdc
DV		 2027 }
2028 }
2029
84f44ce7 2030 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
85234cdc 2031
22f9fe50 2032 return false;
85234cdc
DV		 2033}
2034
fc914639
PZ		 2035void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
2036{
2037 struct drm_crtc *crtc = &intel_crtc->base;
2038 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
2039 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
2040 enum port port = intel_ddi_get_encoder_port(intel_encoder);
6e3c9717 2041 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
fc914639 2042
bb523fc0
PZ		 2043 if (cpu_transcoder != TRANSCODER_EDP)
2044 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2045 TRANS_CLK_SEL_PORT(port));
fc914639
PZ		 2046}
2047
2048void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
2049{
2050 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
6e3c9717 2051 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
fc914639 2052
bb523fc0
PZ		 2053 if (cpu_transcoder != TRANSCODER_EDP)
2054 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
2055 TRANS_CLK_SEL_DISABLED);
fc914639
PZ		 2056}
2057
f8896f5d
DW		 2058static void skl_ddi_set_iboost(struct drm_device *dev, u32 level,
2059 enum port port, int type)
2060{
2061 struct drm_i915_private *dev_priv = dev->dev_private;
2062 const struct ddi_buf_trans *ddi_translations;
2063 uint8_t iboost;
2064 int n_entries;
2065 u32 reg;
2066
2067 if (type == INTEL_OUTPUT_DISPLAYPORT) {
2068 ddi_translations = skl_get_buf_trans_dp(dev, &n_entries);
2069 iboost = ddi_translations[port].i_boost;
2070 } else if (type == INTEL_OUTPUT_EDP) {
2071 ddi_translations = skl_get_buf_trans_edp(dev, &n_entries);
2072 iboost = ddi_translations[port].i_boost;
2073 } else if (type == INTEL_OUTPUT_HDMI) {
2074 ddi_translations = skl_get_buf_trans_hdmi(dev, &n_entries);
2075 iboost = ddi_translations[port].i_boost;
2076 } else {
2077 return;
2078 }
2079
2080 /* Make sure that the requested I_boost is valid */
2081 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
2082 DRM_ERROR("Invalid I_boost value %u\n", iboost);
2083 return;
2084 }
2085
2086 reg = I915_READ(DISPIO_CR_TX_BMU_CR0);
2087 reg &= ~BALANCE_LEG_MASK(port);
2088 reg &= ~(1 << (BALANCE_LEG_DISABLE_SHIFT + port));
2089
2090 if (iboost)
2091 reg |= iboost << BALANCE_LEG_SHIFT(port);
2092 else
2093 reg |= 1 << (BALANCE_LEG_DISABLE_SHIFT + port);
2094
2095 I915_WRITE(DISPIO_CR_TX_BMU_CR0, reg);
2096}
2097
2098static void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
2099 enum port port, int type)
96fb9f9b
VK		 2100{
2101 struct drm_i915_private *dev_priv = dev->dev_private;
2102 const struct bxt_ddi_buf_trans *ddi_translations;
2103 u32 n_entries, i;
2104 uint32_t val;
2105
2106 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
2107 n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
2108 ddi_translations = bxt_ddi_translations_dp;
2109 } else if (type == INTEL_OUTPUT_HDMI) {
2110 n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
2111 ddi_translations = bxt_ddi_translations_hdmi;
2112 } else {
2113 DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n",
2114 type);
2115 return;
2116 }
2117
2118 /* Check if default value has to be used */
2119 if (level >= n_entries ||
2120 (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) {
2121 for (i = 0; i < n_entries; i++) {
2122 if (ddi_translations[i].default_index) {
2123 level = i;
2124 break;
2125 }
2126 }
2127 }
2128
2129 /*
2130 * While we write to the group register to program all lanes at once we
2131 * can read only lane registers and we pick lanes 0/1 for that.
2132 */
2133 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
2134 val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
2135 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
2136
2137 val = I915_READ(BXT_PORT_TX_DW2_LN0(port));
2138 val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE);
2139 val |= ddi_translations[level].margin << MARGIN_000_SHIFT |
2140 ddi_translations[level].scale << UNIQ_TRANS_SCALE_SHIFT;
2141 I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val);
2142
2143 val = I915_READ(BXT_PORT_TX_DW3_LN0(port));
2144 val &= ~UNIQE_TRANGE_EN_METHOD;
2145 if (ddi_translations[level].enable)
2146 val |= UNIQE_TRANGE_EN_METHOD;
2147 I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val);
2148
2149 val = I915_READ(BXT_PORT_TX_DW4_LN0(port));
2150 val &= ~DE_EMPHASIS;
2151 val |= ddi_translations[level].deemphasis << DEEMPH_SHIFT;
2152 I915_WRITE(BXT_PORT_TX_DW4_GRP(port), val);
2153
2154 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
2155 val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT;
2156 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
2157}
2158
f8896f5d
DW		 2159static uint32_t translate_signal_level(int signal_levels)
2160{
2161 uint32_t level;
2162
2163 switch (signal_levels) {
2164 default:
2165 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2166 signal_levels);
2167 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2168 level = 0;
2169 break;
2170 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2171 level = 1;
2172 break;
2173 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
2174 level = 2;
2175 break;
2176 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
2177 level = 3;
2178 break;
2179
2180 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2181 level = 4;
2182 break;
2183 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2184 level = 5;
2185 break;
2186 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
2187 level = 6;
2188 break;
2189
2190 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2191 level = 7;
2192 break;
2193 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2194 level = 8;
2195 break;
2196
2197 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2198 level = 9;
2199 break;
2200 }
2201
2202 return level;
2203}
2204
2205uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
2206{
2207 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2208 struct drm_device *dev = dport->base.base.dev;
2209 struct intel_encoder *encoder = &dport->base;
2210 uint8_t train_set = intel_dp->train_set[0];
2211 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2212 DP_TRAIN_PRE_EMPHASIS_MASK);
2213 enum port port = dport->port;
2214 uint32_t level;
2215
2216 level = translate_signal_level(signal_levels);
2217
2218 if (IS_SKYLAKE(dev))
2219 skl_ddi_set_iboost(dev, level, port, encoder->type);
2220 else if (IS_BROXTON(dev))
2221 bxt_ddi_vswing_sequence(dev, level, port, encoder->type);
2222
2223 return DDI_BUF_TRANS_SELECT(level);
2224}
2225
00c09d70 2226static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
6441ab5f 2227{
c19b0669 2228 struct drm_encoder *encoder = &intel_encoder->base;
efa80add
S		 2229 struct drm_device *dev = encoder->dev;
2230 struct drm_i915_private *dev_priv = dev->dev_private;
30cf6db8 2231 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
6441ab5f 2232 enum port port = intel_ddi_get_encoder_port(intel_encoder);
82a4d9c0 2233 int type = intel_encoder->type;
96fb9f9b 2234 int hdmi_level;
6441ab5f 2235
82a4d9c0
PZ		 2236 if (type == INTEL_OUTPUT_EDP) {
2237 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4be73780 2238 intel_edp_panel_on(intel_dp);
82a4d9c0 2239 }
6441ab5f 2240
efa80add 2241 if (IS_SKYLAKE(dev)) {
6e3c9717 2242 uint32_t dpll = crtc->config->ddi_pll_sel;
efa80add
S		 2243 uint32_t val;
2244
5416d871
DL		 2245 /*
2246 * DPLL0 is used for eDP and is the only "private" DPLL (as
2247 * opposed to shared) on SKL
2248 */
2249 if (type == INTEL_OUTPUT_EDP) {
2250 WARN_ON(dpll != SKL_DPLL0);
2251
2252 val = I915_READ(DPLL_CTRL1);
2253
2254 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) |
2255 DPLL_CTRL1_SSC(dpll) |
71cd8423 2256 DPLL_CTRL1_LINK_RATE_MASK(dpll));
6e3c9717 2257 val |= crtc->config->dpll_hw_state.ctrl1 << (dpll * 6);
5416d871
DL		 2258
2259 I915_WRITE(DPLL_CTRL1, val);
2260 POSTING_READ(DPLL_CTRL1);
2261 }
2262
2263 /* DDI -> PLL mapping */
efa80add
S		 2264 val = I915_READ(DPLL_CTRL2);
2265
2266 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
2267 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
2268 val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) |
2269 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
2270
2271 I915_WRITE(DPLL_CTRL2, val);
5416d871 2272
1ab23380 2273 } else if (INTEL_INFO(dev)->gen < 9) {
6e3c9717
ACO		 2274 WARN_ON(crtc->config->ddi_pll_sel == PORT_CLK_SEL_NONE);
2275 I915_WRITE(PORT_CLK_SEL(port), crtc->config->ddi_pll_sel);
efa80add 2276 }
c19b0669 2277
82a4d9c0 2278 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
c19b0669 2279 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
30cf6db8 2280
44905a27 2281 intel_ddi_init_dp_buf_reg(intel_encoder);
c19b0669
PZ		 2282
2283 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2284 intel_dp_start_link_train(intel_dp);
2285 intel_dp_complete_link_train(intel_dp);
23f08d83 2286 if (port != PORT_A || INTEL_INFO(dev)->gen >= 9)
3ab9c637 2287 intel_dp_stop_link_train(intel_dp);
30cf6db8
DV		 2288 } else if (type == INTEL_OUTPUT_HDMI) {
2289 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2290
96fb9f9b
VK		 2291 if (IS_BROXTON(dev)) {
2292 hdmi_level = dev_priv->vbt.
2293 ddi_port_info[port].hdmi_level_shift;
2294 bxt_ddi_vswing_sequence(dev, hdmi_level, port,
2295 INTEL_OUTPUT_HDMI);
2296 }
30cf6db8 2297 intel_hdmi->set_infoframes(encoder,
6e3c9717
ACO		 2298 crtc->config->has_hdmi_sink,
2299 &crtc->config->base.adjusted_mode);
c19b0669 2300 }
6441ab5f
PZ		 2301}
2302
00c09d70 2303static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
6441ab5f
PZ		 2304{
2305 struct drm_encoder *encoder = &intel_encoder->base;
efa80add
S		 2306 struct drm_device *dev = encoder->dev;
2307 struct drm_i915_private *dev_priv = dev->dev_private;
6441ab5f 2308 enum port port = intel_ddi_get_encoder_port(intel_encoder);
82a4d9c0 2309 int type = intel_encoder->type;
2886e93f 2310 uint32_t val;
a836bdf9 2311 bool wait = false;
2886e93f
PZ		 2312
2313 val = I915_READ(DDI_BUF_CTL(port));
2314 if (val & DDI_BUF_CTL_ENABLE) {
2315 val &= ~DDI_BUF_CTL_ENABLE;
2316 I915_WRITE(DDI_BUF_CTL(port), val);
a836bdf9 2317 wait = true;
2886e93f 2318 }
6441ab5f 2319
a836bdf9
PZ		 2320 val = I915_READ(DP_TP_CTL(port));
2321 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2322 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2323 I915_WRITE(DP_TP_CTL(port), val);
2324
2325 if (wait)
2326 intel_wait_ddi_buf_idle(dev_priv, port);
2327
76bb80ed 2328 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
82a4d9c0 2329 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
76bb80ed 2330 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
24f3e092 2331 intel_edp_panel_vdd_on(intel_dp);
4be73780 2332 intel_edp_panel_off(intel_dp);
82a4d9c0
PZ		 2333 }
2334
efa80add
S		 2335 if (IS_SKYLAKE(dev))
2336 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
2337 DPLL_CTRL2_DDI_CLK_OFF(port)));
1ab23380 2338 else if (INTEL_INFO(dev)->gen < 9)
efa80add 2339 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
6441ab5f
PZ		 2340}
2341
00c09d70 2342static void intel_enable_ddi(struct intel_encoder *intel_encoder)
72662e10 2343{
6547fef8 2344 struct drm_encoder *encoder = &intel_encoder->base;
7b9f35a6
WX		 2345 struct drm_crtc *crtc = encoder->crtc;
2346 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6547fef8 2347 struct drm_device *dev = encoder->dev;
72662e10 2348 struct drm_i915_private *dev_priv = dev->dev_private;
6547fef8
PZ		 2349 enum port port = intel_ddi_get_encoder_port(intel_encoder);
2350 int type = intel_encoder->type;
72662e10 2351
6547fef8 2352 if (type == INTEL_OUTPUT_HDMI) {
876a8cdf
DL		 2353 struct intel_digital_port *intel_dig_port =
2354 enc_to_dig_port(encoder);
2355
6547fef8
PZ		 2356 /* In HDMI/DVI mode, the port width, and swing/emphasis values
2357 * are ignored so nothing special needs to be done besides
2358 * enabling the port.
2359 */
876a8cdf 2360 I915_WRITE(DDI_BUF_CTL(port),
bcf53de4
SM		 2361 intel_dig_port->saved_port_bits |
2362 DDI_BUF_CTL_ENABLE);
d6c50ff8
PZ		 2363 } else if (type == INTEL_OUTPUT_EDP) {
2364 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2365
23f08d83 2366 if (port == PORT_A && INTEL_INFO(dev)->gen < 9)
3ab9c637
ID		 2367 intel_dp_stop_link_train(intel_dp);
2368
4be73780 2369 intel_edp_backlight_on(intel_dp);
0bc12bcb 2370 intel_psr_enable(intel_dp);
c395578e 2371 intel_edp_drrs_enable(intel_dp);
6547fef8 2372 }
7b9f35a6 2373
6e3c9717 2374 if (intel_crtc->config->has_audio) {
d45a0bf5 2375 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
69bfe1a9 2376 intel_audio_codec_enable(intel_encoder);
7b9f35a6 2377 }
5ab432ef
DV		 2378}
2379
00c09d70 2380static void intel_disable_ddi(struct intel_encoder *intel_encoder)
5ab432ef 2381{
d6c50ff8 2382 struct drm_encoder *encoder = &intel_encoder->base;
7b9f35a6
WX		 2383 struct drm_crtc *crtc = encoder->crtc;
2384 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
d6c50ff8 2385 int type = intel_encoder->type;
7b9f35a6
WX		 2386 struct drm_device *dev = encoder->dev;
2387 struct drm_i915_private *dev_priv = dev->dev_private;
d6c50ff8 2388
6e3c9717 2389 if (intel_crtc->config->has_audio) {
69bfe1a9 2390 intel_audio_codec_disable(intel_encoder);
d45a0bf5
PZ		 2391 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
2392 }
2831d842 2393
d6c50ff8
PZ		 2394 if (type == INTEL_OUTPUT_EDP) {
2395 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2396
c395578e 2397 intel_edp_drrs_disable(intel_dp);
0bc12bcb 2398 intel_psr_disable(intel_dp);
4be73780 2399 intel_edp_backlight_off(intel_dp);
d6c50ff8 2400 }
72662e10 2401}
79f689aa 2402
e0b01be4
DV		 2403static void hsw_ddi_pll_enable(struct drm_i915_private *dev_priv,
2404 struct intel_shared_dpll *pll)
2405{
3e369b76 2406 I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll);
e0b01be4
DV		 2407 POSTING_READ(WRPLL_CTL(pll->id));
2408 udelay(20);
2409}
2410
12030431
DV		 2411static void hsw_ddi_pll_disable(struct drm_i915_private *dev_priv,
2412 struct intel_shared_dpll *pll)
2413{
2414 uint32_t val;
2415
2416 val = I915_READ(WRPLL_CTL(pll->id));
12030431
DV		 2417 I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE);
2418 POSTING_READ(WRPLL_CTL(pll->id));
2419}
2420
d452c5b6
DV		 2421static bool hsw_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2422 struct intel_shared_dpll *pll,
2423 struct intel_dpll_hw_state *hw_state)
2424{
2425 uint32_t val;
2426
f458ebbc 2427 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
d452c5b6
DV		 2428 return false;
2429
2430 val = I915_READ(WRPLL_CTL(pll->id));
2431 hw_state->wrpll = val;
2432
2433 return val & WRPLL_PLL_ENABLE;
2434}
2435
ca1381b5 2436static const char * const hsw_ddi_pll_names[] = {
9cd86933
DV		 2437 "WRPLL 1",
2438 "WRPLL 2",
2439};
2440
143b307c 2441static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv)
79f689aa 2442{
9cd86933
DV		 2443 int i;
2444
716c2e55 2445 dev_priv->num_shared_dpll = 2;
9cd86933 2446
716c2e55 2447 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9cd86933
DV		 2448 dev_priv->shared_dplls[i].id = i;
2449 dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
12030431 2450 dev_priv->shared_dplls[i].disable = hsw_ddi_pll_disable;
e0b01be4 2451 dev_priv->shared_dplls[i].enable = hsw_ddi_pll_enable;
d452c5b6
DV		 2452 dev_priv->shared_dplls[i].get_hw_state =
2453 hsw_ddi_pll_get_hw_state;
9cd86933 2454 }
143b307c
DL		 2455}
2456
d1a2dc78
S		 2457static const char * const skl_ddi_pll_names[] = {
2458 "DPLL 1",
2459 "DPLL 2",
2460 "DPLL 3",
2461};
2462
2463struct skl_dpll_regs {
2464 u32 ctl, cfgcr1, cfgcr2;
2465};
2466
2467/* this array is indexed by the *shared* pll id */
2468static const struct skl_dpll_regs skl_dpll_regs[3] = {
2469 {
2470 /* DPLL 1 */
2471 .ctl = LCPLL2_CTL,
2472 .cfgcr1 = DPLL1_CFGCR1,
2473 .cfgcr2 = DPLL1_CFGCR2,
2474 },
2475 {
2476 /* DPLL 2 */
2477 .ctl = WRPLL_CTL1,
2478 .cfgcr1 = DPLL2_CFGCR1,
2479 .cfgcr2 = DPLL2_CFGCR2,
2480 },
2481 {
2482 /* DPLL 3 */
2483 .ctl = WRPLL_CTL2,
2484 .cfgcr1 = DPLL3_CFGCR1,
2485 .cfgcr2 = DPLL3_CFGCR2,
2486 },
2487};
2488
2489static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv,
2490 struct intel_shared_dpll *pll)
2491{
2492 uint32_t val;
2493 unsigned int dpll;
2494 const struct skl_dpll_regs *regs = skl_dpll_regs;
2495
2496 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
2497 dpll = pll->id + 1;
2498
2499 val = I915_READ(DPLL_CTRL1);
2500
2501 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | DPLL_CTRL1_SSC(dpll) |
71cd8423 2502 DPLL_CTRL1_LINK_RATE_MASK(dpll));
d1a2dc78
S		 2503 val |= pll->config.hw_state.ctrl1 << (dpll * 6);
2504
2505 I915_WRITE(DPLL_CTRL1, val);
2506 POSTING_READ(DPLL_CTRL1);
2507
2508 I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1);
2509 I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2);
2510 POSTING_READ(regs[pll->id].cfgcr1);
2511 POSTING_READ(regs[pll->id].cfgcr2);
2512
2513 /* the enable bit is always bit 31 */
2514 I915_WRITE(regs[pll->id].ctl,
2515 I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE);
2516
2517 if (wait_for(I915_READ(DPLL_STATUS) & DPLL_LOCK(dpll), 5))
2518 DRM_ERROR("DPLL %d not locked\n", dpll);
2519}
2520
2521static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv,
2522 struct intel_shared_dpll *pll)
2523{
2524 const struct skl_dpll_regs *regs = skl_dpll_regs;
2525
2526 /* the enable bit is always bit 31 */
2527 I915_WRITE(regs[pll->id].ctl,
2528 I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE);
2529 POSTING_READ(regs[pll->id].ctl);
2530}
2531
2532static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2533 struct intel_shared_dpll *pll,
2534 struct intel_dpll_hw_state *hw_state)
2535{
2536 uint32_t val;
2537 unsigned int dpll;
2538 const struct skl_dpll_regs *regs = skl_dpll_regs;
2539
2540 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
2541 return false;
2542
2543 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
2544 dpll = pll->id + 1;
2545
2546 val = I915_READ(regs[pll->id].ctl);
2547 if (!(val & LCPLL_PLL_ENABLE))
2548 return false;
2549
2550 val = I915_READ(DPLL_CTRL1);
2551 hw_state->ctrl1 = (val >> (dpll * 6)) & 0x3f;
2552
2553 /* avoid reading back stale values if HDMI mode is not enabled */
2554 if (val & DPLL_CTRL1_HDMI_MODE(dpll)) {
2555 hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1);
2556 hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2);
2557 }
2558
2559 return true;
2560}
2561
2562static void skl_shared_dplls_init(struct drm_i915_private *dev_priv)
2563{
2564 int i;
2565
2566 dev_priv->num_shared_dpll = 3;
2567
2568 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2569 dev_priv->shared_dplls[i].id = i;
2570 dev_priv->shared_dplls[i].name = skl_ddi_pll_names[i];
2571 dev_priv->shared_dplls[i].disable = skl_ddi_pll_disable;
2572 dev_priv->shared_dplls[i].enable = skl_ddi_pll_enable;
2573 dev_priv->shared_dplls[i].get_hw_state =
2574 skl_ddi_pll_get_hw_state;
2575 }
2576}
2577
5c6706e5
VK		 2578static void broxton_phy_init(struct drm_i915_private *dev_priv,
2579 enum dpio_phy phy)
2580{
2581 enum port port;
2582 uint32_t val;
2583
2584 val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
2585 val |= GT_DISPLAY_POWER_ON(phy);
2586 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
2587
2588 /* Considering 10ms timeout until BSpec is updated */
2589 if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10))
2590 DRM_ERROR("timeout during PHY%d power on\n", phy);
2591
2592 for (port = (phy == DPIO_PHY0 ? PORT_B : PORT_A);
2593 port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) {
2594 int lane;
2595
2596 for (lane = 0; lane < 4; lane++) {
2597 val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
2598 /*
2599 * Note that on CHV this flag is called UPAR, but has
2600 * the same function.
2601 */
2602 val &= ~LATENCY_OPTIM;
2603 if (lane != 1)
2604 val |= LATENCY_OPTIM;
2605
2606 I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val);
2607 }
2608 }
2609
2610 /* Program PLL Rcomp code offset */
2611 val = I915_READ(BXT_PORT_CL1CM_DW9(phy));
2612 val &= ~IREF0RC_OFFSET_MASK;
2613 val |= 0xE4 << IREF0RC_OFFSET_SHIFT;
2614 I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val);
2615
2616 val = I915_READ(BXT_PORT_CL1CM_DW10(phy));
2617 val &= ~IREF1RC_OFFSET_MASK;
2618 val |= 0xE4 << IREF1RC_OFFSET_SHIFT;
2619 I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val);
2620
2621 /* Program power gating */
2622 val = I915_READ(BXT_PORT_CL1CM_DW28(phy));
2623 val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN |
2624 SUS_CLK_CONFIG;
2625 I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
2626
2627 if (phy == DPIO_PHY0) {
2628 val = I915_READ(BXT_PORT_CL2CM_DW6_BC);
2629 val |= DW6_OLDO_DYN_PWR_DOWN_EN;
2630 I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val);
2631 }
2632
2633 val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
2634 val &= ~OCL2_LDOFUSE_PWR_DIS;
2635 /*
2636 * On PHY1 disable power on the second channel, since no port is
2637 * connected there. On PHY0 both channels have a port, so leave it
2638 * enabled.
2639 * TODO: port C is only connected on BXT-P, so on BXT0/1 we should
2640 * power down the second channel on PHY0 as well.
2641 */
2642 if (phy == DPIO_PHY1)
2643 val |= OCL2_LDOFUSE_PWR_DIS;
2644 I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
2645
2646 if (phy == DPIO_PHY0) {
2647 uint32_t grc_code;
2648 /*
2649 * PHY0 isn't connected to an RCOMP resistor so copy over
2650 * the corresponding calibrated value from PHY1, and disable
2651 * the automatic calibration on PHY0.
2652 */
2653 if (wait_for(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE,
2654 10))
2655 DRM_ERROR("timeout waiting for PHY1 GRC\n");
2656
2657 val = I915_READ(BXT_PORT_REF_DW6(DPIO_PHY1));
2658 val = (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
2659 grc_code = val << GRC_CODE_FAST_SHIFT |
2660 val << GRC_CODE_SLOW_SHIFT |
2661 val;
2662 I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code);
2663
2664 val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0));
2665 val |= GRC_DIS | GRC_RDY_OVRD;
2666 I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val);
2667 }
2668
2669 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
2670 val |= COMMON_RESET_DIS;
2671 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
2672}
2673
2674void broxton_ddi_phy_init(struct drm_device *dev)
2675{
2676 /* Enable PHY1 first since it provides Rcomp for PHY0 */
2677 broxton_phy_init(dev->dev_private, DPIO_PHY1);
2678 broxton_phy_init(dev->dev_private, DPIO_PHY0);
2679}
2680
2681static void broxton_phy_uninit(struct drm_i915_private *dev_priv,
2682 enum dpio_phy phy)
2683{
2684 uint32_t val;
2685
2686 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
2687 val &= ~COMMON_RESET_DIS;
2688 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
2689}
2690
2691void broxton_ddi_phy_uninit(struct drm_device *dev)
2692{
2693 struct drm_i915_private *dev_priv = dev->dev_private;
2694
2695 broxton_phy_uninit(dev_priv, DPIO_PHY1);
2696 broxton_phy_uninit(dev_priv, DPIO_PHY0);
2697
2698 /* FIXME: do this in broxton_phy_uninit per phy */
2699 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, 0);
2700}
2701
dfb82408
S		 2702static const char * const bxt_ddi_pll_names[] = {
2703 "PORT PLL A",
2704 "PORT PLL B",
2705 "PORT PLL C",
2706};
2707
2708static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
2709 struct intel_shared_dpll *pll)
2710{
2711 uint32_t temp;
2712 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2713
2714 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2715 temp &= ~PORT_PLL_REF_SEL;
2716 /* Non-SSC reference */
2717 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2718
2719 /* Disable 10 bit clock */
2720 temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
2721 temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
2722 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2723
2724 /* Write P1 & P2 */
2725 temp = I915_READ(BXT_PORT_PLL_EBB_0(port));
2726 temp &= ~(PORT_PLL_P1_MASK | PORT_PLL_P2_MASK);
2727 temp |= pll->config.hw_state.ebb0;
2728 I915_WRITE(BXT_PORT_PLL_EBB_0(port), temp);
2729
2730 /* Write M2 integer */
2731 temp = I915_READ(BXT_PORT_PLL(port, 0));
2732 temp &= ~PORT_PLL_M2_MASK;
2733 temp |= pll->config.hw_state.pll0;
2734 I915_WRITE(BXT_PORT_PLL(port, 0), temp);
2735
2736 /* Write N */
2737 temp = I915_READ(BXT_PORT_PLL(port, 1));
2738 temp &= ~PORT_PLL_N_MASK;
2739 temp |= pll->config.hw_state.pll1;
2740 I915_WRITE(BXT_PORT_PLL(port, 1), temp);
2741
2742 /* Write M2 fraction */
2743 temp = I915_READ(BXT_PORT_PLL(port, 2));
2744 temp &= ~PORT_PLL_M2_FRAC_MASK;
2745 temp |= pll->config.hw_state.pll2;
2746 I915_WRITE(BXT_PORT_PLL(port, 2), temp);
2747
2748 /* Write M2 fraction enable */
2749 temp = I915_READ(BXT_PORT_PLL(port, 3));
2750 temp &= ~PORT_PLL_M2_FRAC_ENABLE;
2751 temp |= pll->config.hw_state.pll3;
2752 I915_WRITE(BXT_PORT_PLL(port, 3), temp);
2753
2754 /* Write coeff */
2755 temp = I915_READ(BXT_PORT_PLL(port, 6));
2756 temp &= ~PORT_PLL_PROP_COEFF_MASK;
2757 temp &= ~PORT_PLL_INT_COEFF_MASK;
2758 temp &= ~PORT_PLL_GAIN_CTL_MASK;
2759 temp |= pll->config.hw_state.pll6;
2760 I915_WRITE(BXT_PORT_PLL(port, 6), temp);
2761
2762 /* Write calibration val */
2763 temp = I915_READ(BXT_PORT_PLL(port, 8));
2764 temp &= ~PORT_PLL_TARGET_CNT_MASK;
2765 temp |= pll->config.hw_state.pll8;
2766 I915_WRITE(BXT_PORT_PLL(port, 8), temp);
2767
b6dc71f3
VK		 2768 temp = I915_READ(BXT_PORT_PLL(port, 9));
2769 temp &= ~PORT_PLL_LOCK_THRESHOLD_MASK;
2770 temp |= (5 << 1);
2771 I915_WRITE(BXT_PORT_PLL(port, 9), temp);
2772
2773 temp = I915_READ(BXT_PORT_PLL(port, 10));
2774 temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H;
2775 temp &= ~PORT_PLL_DCO_AMP_MASK;
2776 temp |= pll->config.hw_state.pll10;
2777 I915_WRITE(BXT_PORT_PLL(port, 10), temp);
dfb82408
S		 2778
2779 /* Recalibrate with new settings */
2780 temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
2781 temp |= PORT_PLL_RECALIBRATE;
2782 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2783 /* Enable 10 bit clock */
2784 temp |= PORT_PLL_10BIT_CLK_ENABLE;
2785 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2786
2787 /* Enable PLL */
2788 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2789 temp |= PORT_PLL_ENABLE;
2790 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2791 POSTING_READ(BXT_PORT_PLL_ENABLE(port));
2792
2793 if (wait_for_atomic_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) &
2794 PORT_PLL_LOCK), 200))
2795 DRM_ERROR("PLL %d not locked\n", port);
2796
2797 /*
2798 * While we write to the group register to program all lanes at once we
2799 * can read only lane registers and we pick lanes 0/1 for that.
2800 */
2801 temp = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
2802 temp &= ~LANE_STAGGER_MASK;
2803 temp &= ~LANESTAGGER_STRAP_OVRD;
2804 temp |= pll->config.hw_state.pcsdw12;
2805 I915_WRITE(BXT_PORT_PCS_DW12_GRP(port), temp);
2806}
2807
2808static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv,
2809 struct intel_shared_dpll *pll)
2810{
2811 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2812 uint32_t temp;
2813
2814 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2815 temp &= ~PORT_PLL_ENABLE;
2816 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2817 POSTING_READ(BXT_PORT_PLL_ENABLE(port));
2818}
2819
2820static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2821 struct intel_shared_dpll *pll,
2822 struct intel_dpll_hw_state *hw_state)
2823{
2824 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2825 uint32_t val;
2826
2827 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
2828 return false;
2829
2830 val = I915_READ(BXT_PORT_PLL_ENABLE(port));
2831 if (!(val & PORT_PLL_ENABLE))
2832 return false;
2833
2834 hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(port));
2835 hw_state->pll0 = I915_READ(BXT_PORT_PLL(port, 0));
2836 hw_state->pll1 = I915_READ(BXT_PORT_PLL(port, 1));
2837 hw_state->pll2 = I915_READ(BXT_PORT_PLL(port, 2));
2838 hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3));
2839 hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6));
2840 hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8));
b6dc71f3 2841 hw_state->pll10 = I915_READ(BXT_PORT_PLL(port, 10));
dfb82408
S		 2842 /*
2843 * While we write to the group register to program all lanes at once we
2844 * can read only lane registers. We configure all lanes the same way, so
2845 * here just read out lanes 0/1 and output a note if lanes 2/3 differ.
2846 */
2847 hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
2848 if (I915_READ(BXT_PORT_PCS_DW12_LN23(port) != hw_state->pcsdw12))
2849 DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n",
2850 hw_state->pcsdw12,
2851 I915_READ(BXT_PORT_PCS_DW12_LN23(port)));
2852
2853 return true;
2854}
2855
2856static void bxt_shared_dplls_init(struct drm_i915_private *dev_priv)
2857{
2858 int i;
2859
2860 dev_priv->num_shared_dpll = 3;
2861
2862 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2863 dev_priv->shared_dplls[i].id = i;
2864 dev_priv->shared_dplls[i].name = bxt_ddi_pll_names[i];
2865 dev_priv->shared_dplls[i].disable = bxt_ddi_pll_disable;
2866 dev_priv->shared_dplls[i].enable = bxt_ddi_pll_enable;
2867 dev_priv->shared_dplls[i].get_hw_state =
2868 bxt_ddi_pll_get_hw_state;
2869 }
2870}
2871
143b307c
DL		 2872void intel_ddi_pll_init(struct drm_device *dev)
2873{
2874 struct drm_i915_private *dev_priv = dev->dev_private;
2875 uint32_t val = I915_READ(LCPLL_CTL);
2876
d1a2dc78
S		 2877 if (IS_SKYLAKE(dev))
2878 skl_shared_dplls_init(dev_priv);
dfb82408
S		 2879 else if (IS_BROXTON(dev))
2880 bxt_shared_dplls_init(dev_priv);
d1a2dc78
S		 2881 else
2882 hsw_shared_dplls_init(dev_priv);
79f689aa 2883
121643c2 2884 if (IS_SKYLAKE(dev)) {
d9062ae5
DL		 2885 int cdclk_freq;
2886
2887 cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5d96d8af 2888 dev_priv->skl_boot_cdclk = cdclk_freq;
121643c2
S		 2889 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
2890 DRM_ERROR("LCPLL1 is disabled\n");
5d96d8af
DL		 2891 else
2892 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
f8437dd1
VK		 2893 } else if (IS_BROXTON(dev)) {
2894 broxton_init_cdclk(dev);
5c6706e5 2895 broxton_ddi_phy_init(dev);
121643c2
S		 2896 } else {
2897 /*
2898 * The LCPLL register should be turned on by the BIOS. For now
2899 * let's just check its state and print errors in case
2900 * something is wrong. Don't even try to turn it on.
2901 */
2902
2903 if (val & LCPLL_CD_SOURCE_FCLK)
2904 DRM_ERROR("CDCLK source is not LCPLL\n");
79f689aa 2905
121643c2
S		 2906 if (val & LCPLL_PLL_DISABLE)
2907 DRM_ERROR("LCPLL is disabled\n");
2908 }
79f689aa 2909}
c19b0669
PZ		 2910
2911void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
2912{
174edf1f
PZ		 2913 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2914 struct intel_dp *intel_dp = &intel_dig_port->dp;
c19b0669 2915 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
174edf1f 2916 enum port port = intel_dig_port->port;
c19b0669 2917 uint32_t val;
f3e227df 2918 bool wait = false;
c19b0669
PZ		 2919
2920 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
2921 val = I915_READ(DDI_BUF_CTL(port));
2922 if (val & DDI_BUF_CTL_ENABLE) {
2923 val &= ~DDI_BUF_CTL_ENABLE;
2924 I915_WRITE(DDI_BUF_CTL(port), val);
2925 wait = true;
2926 }
2927
2928 val = I915_READ(DP_TP_CTL(port));
2929 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2930 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2931 I915_WRITE(DP_TP_CTL(port), val);
2932 POSTING_READ(DP_TP_CTL(port));
2933
2934 if (wait)
2935 intel_wait_ddi_buf_idle(dev_priv, port);
2936 }
2937
0e32b39c 2938 val = DP_TP_CTL_ENABLE |
c19b0669 2939 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
0e32b39c
DA		 2940 if (intel_dp->is_mst)
2941 val |= DP_TP_CTL_MODE_MST;
2942 else {
2943 val |= DP_TP_CTL_MODE_SST;
2944 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2945 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
2946 }
c19b0669
PZ		 2947 I915_WRITE(DP_TP_CTL(port), val);
2948 POSTING_READ(DP_TP_CTL(port));
2949
2950 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
2951 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
2952 POSTING_READ(DDI_BUF_CTL(port));
2953
2954 udelay(600);
2955}
00c09d70 2956
1ad960f2
PZ		 2957void intel_ddi_fdi_disable(struct drm_crtc *crtc)
2958{
2959 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
2960 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
2961 uint32_t val;
2962
2963 intel_ddi_post_disable(intel_encoder);
2964
2965 val = I915_READ(_FDI_RXA_CTL);
2966 val &= ~FDI_RX_ENABLE;
2967 I915_WRITE(_FDI_RXA_CTL, val);
2968
2969 val = I915_READ(_FDI_RXA_MISC);
2970 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
2971 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
2972 I915_WRITE(_FDI_RXA_MISC, val);
2973
2974 val = I915_READ(_FDI_RXA_CTL);
2975 val &= ~FDI_PCDCLK;
2976 I915_WRITE(_FDI_RXA_CTL, val);
2977
2978 val = I915_READ(_FDI_RXA_CTL);
2979 val &= ~FDI_RX_PLL_ENABLE;
2980 I915_WRITE(_FDI_RXA_CTL, val);
2981}
2982
6801c18c 2983void intel_ddi_get_config(struct intel_encoder *encoder,
5cec258b 2984 struct intel_crtc_state *pipe_config)
045ac3b5
JB		 2985{
2986 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
2987 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
0cb09a97 2988 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
bbd440fb 2989 struct intel_hdmi *intel_hdmi;
045ac3b5
JB		 2990 u32 temp, flags = 0;
2991
2992 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
2993 if (temp & TRANS_DDI_PHSYNC)
2994 flags |= DRM_MODE_FLAG_PHSYNC;
2995 else
2996 flags |= DRM_MODE_FLAG_NHSYNC;
2997 if (temp & TRANS_DDI_PVSYNC)
2998 flags |= DRM_MODE_FLAG_PVSYNC;
2999 else
3000 flags |= DRM_MODE_FLAG_NVSYNC;
3001
2d112de7 3002 pipe_config->base.adjusted_mode.flags |= flags;
42571aef
VS		 3003
3004 switch (temp & TRANS_DDI_BPC_MASK) {
3005 case TRANS_DDI_BPC_6:
3006 pipe_config->pipe_bpp = 18;
3007 break;
3008 case TRANS_DDI_BPC_8:
3009 pipe_config->pipe_bpp = 24;
3010 break;
3011 case TRANS_DDI_BPC_10:
3012 pipe_config->pipe_bpp = 30;
3013 break;
3014 case TRANS_DDI_BPC_12:
3015 pipe_config->pipe_bpp = 36;
3016 break;
3017 default:
3018 break;
3019 }
eb14cb74
VS		 3020
3021 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
3022 case TRANS_DDI_MODE_SELECT_HDMI:
6897b4b5 3023 pipe_config->has_hdmi_sink = true;
bbd440fb
DV		 3024 intel_hdmi = enc_to_intel_hdmi(&encoder->base);
3025
3026 if (intel_hdmi->infoframe_enabled(&encoder->base))
3027 pipe_config->has_infoframe = true;
cbc572a9 3028 break;
eb14cb74
VS		 3029 case TRANS_DDI_MODE_SELECT_DVI:
3030 case TRANS_DDI_MODE_SELECT_FDI:
3031 break;
3032 case TRANS_DDI_MODE_SELECT_DP_SST:
3033 case TRANS_DDI_MODE_SELECT_DP_MST:
3034 pipe_config->has_dp_encoder = true;
3035 intel_dp_get_m_n(intel_crtc, pipe_config);
3036 break;
3037 default:
3038 break;
3039 }
10214420 3040
f458ebbc 3041 if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
a60551b1 3042 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
82910ac6 3043 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
a60551b1
PZ		 3044 pipe_config->has_audio = true;
3045 }
9ed109a7 3046
10214420
DV		 3047 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp &&
3048 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
3049 /*
3050 * This is a big fat ugly hack.
3051 *
3052 * Some machines in UEFI boot mode provide us a VBT that has 18
3053 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3054 * unknown we fail to light up. Yet the same BIOS boots up with
3055 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3056 * max, not what it tells us to use.
3057 *
3058 * Note: This will still be broken if the eDP panel is not lit
3059 * up by the BIOS, and thus we can't get the mode at module
3060 * load.
3061 */
3062 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3063 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
3064 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
3065 }
11578553 3066
22606a18 3067 intel_ddi_clock_get(encoder, pipe_config);
045ac3b5
JB		 3068}
3069
00c09d70
PZ		 3070static void intel_ddi_destroy(struct drm_encoder *encoder)
3071{
3072 /* HDMI has nothing special to destroy, so we can go with this. */
3073 intel_dp_encoder_destroy(encoder);
3074}
3075
5bfe2ac0 3076static bool intel_ddi_compute_config(struct intel_encoder *encoder,
5cec258b 3077 struct intel_crtc_state *pipe_config)
00c09d70 3078{
5bfe2ac0 3079 int type = encoder->type;
eccb140b 3080 int port = intel_ddi_get_encoder_port(encoder);
00c09d70 3081
5bfe2ac0 3082 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
00c09d70 3083
eccb140b
DV		 3084 if (port == PORT_A)
3085 pipe_config->cpu_transcoder = TRANSCODER_EDP;
3086
00c09d70 3087 if (type == INTEL_OUTPUT_HDMI)
5bfe2ac0 3088 return intel_hdmi_compute_config(encoder, pipe_config);
00c09d70 3089 else
5bfe2ac0 3090 return intel_dp_compute_config(encoder, pipe_config);
00c09d70
PZ		 3091}
3092
3093static const struct drm_encoder_funcs intel_ddi_funcs = {
3094 .destroy = intel_ddi_destroy,
3095};
3096
4a28ae58
PZ		 3097static struct intel_connector *
3098intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
3099{
3100 struct intel_connector *connector;
3101 enum port port = intel_dig_port->port;
3102
9bdbd0b9 3103 connector = intel_connector_alloc();
4a28ae58
PZ		 3104 if (!connector)
3105 return NULL;
3106
3107 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
3108 if (!intel_dp_init_connector(intel_dig_port, connector)) {
3109 kfree(connector);
3110 return NULL;
3111 }
3112
3113 return connector;
3114}
3115
3116static struct intel_connector *
3117intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
3118{
3119 struct intel_connector *connector;
3120 enum port port = intel_dig_port->port;
3121
9bdbd0b9 3122 connector = intel_connector_alloc();
4a28ae58
PZ		 3123 if (!connector)
3124 return NULL;
3125
3126 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
3127 intel_hdmi_init_connector(intel_dig_port, connector);
3128
3129 return connector;
3130}
3131
00c09d70
PZ		 3132void intel_ddi_init(struct drm_device *dev, enum port port)
3133{
876a8cdf 3134 struct drm_i915_private *dev_priv = dev->dev_private;
00c09d70
PZ		 3135 struct intel_digital_port *intel_dig_port;
3136 struct intel_encoder *intel_encoder;
3137 struct drm_encoder *encoder;
311a2094
PZ		 3138 bool init_hdmi, init_dp;
3139
3140 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
3141 dev_priv->vbt.ddi_port_info[port].supports_hdmi);
3142 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
3143 if (!init_dp && !init_hdmi) {
f68d697e 3144 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, assuming it is\n",
311a2094
PZ		 3145 port_name(port));
3146 init_hdmi = true;
3147 init_dp = true;
3148 }
00c09d70 3149
b14c5679 3150 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
00c09d70
PZ		 3151 if (!intel_dig_port)
3152 return;
3153
00c09d70
PZ		 3154 intel_encoder = &intel_dig_port->base;
3155 encoder = &intel_encoder->base;
3156
3157 drm_encoder_init(dev, encoder, &intel_ddi_funcs,
3158 DRM_MODE_ENCODER_TMDS);
00c09d70 3159
5bfe2ac0 3160 intel_encoder->compute_config = intel_ddi_compute_config;
00c09d70
PZ		 3161 intel_encoder->enable = intel_enable_ddi;
3162 intel_encoder->pre_enable = intel_ddi_pre_enable;
3163 intel_encoder->disable = intel_disable_ddi;
3164 intel_encoder->post_disable = intel_ddi_post_disable;
3165 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
045ac3b5 3166 intel_encoder->get_config = intel_ddi_get_config;
00c09d70
PZ		 3167
3168 intel_dig_port->port = port;
bcf53de4
SM		 3169 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
3170 (DDI_BUF_PORT_REVERSAL |
3171 DDI_A_4_LANES);
00c09d70
PZ		 3172
3173 intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
f68d697e 3174 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
bc079e8b 3175 intel_encoder->cloneable = 0;
00c09d70 3176
f68d697e
CW		 3177 if (init_dp) {
3178 if (!intel_ddi_init_dp_connector(intel_dig_port))
3179 goto err;
13cf5504 3180
f68d697e 3181 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5fcece80 3182 dev_priv->hotplug.irq_port[port] = intel_dig_port;
f68d697e 3183 }
21a8e6a4 3184
311a2094
PZ		 3185 /* In theory we don't need the encoder->type check, but leave it just in
3186 * case we have some really bad VBTs... */
f68d697e
CW		 3187 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
3188 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
3189 goto err;
21a8e6a4 3190 }
f68d697e
CW		 3191
3192 return;
3193
3194err:
3195 drm_encoder_cleanup(encoder);
3196 kfree(intel_dig_port);
00c09d70 3197}
Linux 6.x block layer and io_uring tree(s)