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45244b87 ED |
1 | /* |
2 | * Copyright © 2012 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eugeni Dodonov <eugeni.dodonov@intel.com> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "i915_drv.h" | |
29 | #include "intel_drv.h" | |
30 | ||
31 | /* HDMI/DVI modes ignore everything but the last 2 items. So we share | |
32 | * them for both DP and FDI transports, allowing those ports to | |
33 | * automatically adapt to HDMI connections as well | |
34 | */ | |
35 | static const u32 hsw_ddi_translations_dp[] = { | |
36 | 0x00FFFFFF, 0x0006000E, /* DP parameters */ | |
37 | 0x00D75FFF, 0x0005000A, | |
38 | 0x00C30FFF, 0x00040006, | |
39 | 0x80AAAFFF, 0x000B0000, | |
40 | 0x00FFFFFF, 0x0005000A, | |
41 | 0x00D75FFF, 0x000C0004, | |
42 | 0x80C30FFF, 0x000B0000, | |
43 | 0x00FFFFFF, 0x00040006, | |
44 | 0x80D75FFF, 0x000B0000, | |
45244b87 ED |
45 | }; |
46 | ||
47 | static const u32 hsw_ddi_translations_fdi[] = { | |
48 | 0x00FFFFFF, 0x0007000E, /* FDI parameters */ | |
49 | 0x00D75FFF, 0x000F000A, | |
50 | 0x00C30FFF, 0x00060006, | |
51 | 0x00AAAFFF, 0x001E0000, | |
52 | 0x00FFFFFF, 0x000F000A, | |
53 | 0x00D75FFF, 0x00160004, | |
54 | 0x00C30FFF, 0x001E0000, | |
55 | 0x00FFFFFF, 0x00060006, | |
56 | 0x00D75FFF, 0x001E0000, | |
6acab15a PZ |
57 | }; |
58 | ||
59 | static const u32 hsw_ddi_translations_hdmi[] = { | |
60 | /* Idx NT mV diff T mV diff db */ | |
61 | 0x00FFFFFF, 0x0006000E, /* 0: 400 400 0 */ | |
62 | 0x00E79FFF, 0x000E000C, /* 1: 400 500 2 */ | |
63 | 0x00D75FFF, 0x0005000A, /* 2: 400 600 3.5 */ | |
64 | 0x00FFFFFF, 0x0005000A, /* 3: 600 600 0 */ | |
65 | 0x00E79FFF, 0x001D0007, /* 4: 600 750 2 */ | |
66 | 0x00D75FFF, 0x000C0004, /* 5: 600 900 3.5 */ | |
67 | 0x00FFFFFF, 0x00040006, /* 6: 800 800 0 */ | |
68 | 0x80E79FFF, 0x00030002, /* 7: 800 1000 2 */ | |
69 | 0x00FFFFFF, 0x00140005, /* 8: 850 850 0 */ | |
70 | 0x00FFFFFF, 0x000C0004, /* 9: 900 900 0 */ | |
71 | 0x00FFFFFF, 0x001C0003, /* 10: 950 950 0 */ | |
72 | 0x80FFFFFF, 0x00030002, /* 11: 1000 1000 0 */ | |
45244b87 ED |
73 | }; |
74 | ||
300644c7 PZ |
75 | static const u32 bdw_ddi_translations_edp[] = { |
76 | 0x00FFFFFF, 0x00000012, /* DP parameters */ | |
77 | 0x00EBAFFF, 0x00020011, | |
78 | 0x00C71FFF, 0x0006000F, | |
79 | 0x00FFFFFF, 0x00020011, | |
80 | 0x00DB6FFF, 0x0005000F, | |
81 | 0x00BEEFFF, 0x000A000C, | |
82 | 0x00FFFFFF, 0x0005000F, | |
83 | 0x00DB6FFF, 0x000A000C, | |
84 | 0x00FFFFFF, 0x000A000C, | |
85 | 0x00FFFFFF, 0x00140006 /* HDMI parameters 800mV 0dB*/ | |
86 | }; | |
87 | ||
e58623cb AR |
88 | static const u32 bdw_ddi_translations_dp[] = { |
89 | 0x00FFFFFF, 0x0007000E, /* DP parameters */ | |
90 | 0x00D75FFF, 0x000E000A, | |
91 | 0x00BEFFFF, 0x00140006, | |
92 | 0x00FFFFFF, 0x000E000A, | |
93 | 0x00D75FFF, 0x00180004, | |
94 | 0x80CB2FFF, 0x001B0002, | |
95 | 0x00F7DFFF, 0x00180004, | |
96 | 0x80D75FFF, 0x001B0002, | |
97 | 0x80FFFFFF, 0x001B0002, | |
98 | 0x00FFFFFF, 0x00140006 /* HDMI parameters 800mV 0dB*/ | |
99 | }; | |
100 | ||
101 | static const u32 bdw_ddi_translations_fdi[] = { | |
102 | 0x00FFFFFF, 0x0001000E, /* FDI parameters */ | |
103 | 0x00D75FFF, 0x0004000A, | |
104 | 0x00C30FFF, 0x00070006, | |
105 | 0x00AAAFFF, 0x000C0000, | |
106 | 0x00FFFFFF, 0x0004000A, | |
107 | 0x00D75FFF, 0x00090004, | |
108 | 0x00C30FFF, 0x000C0000, | |
109 | 0x00FFFFFF, 0x00070006, | |
110 | 0x00D75FFF, 0x000C0000, | |
111 | 0x00FFFFFF, 0x00140006 /* HDMI parameters 800mV 0dB*/ | |
112 | }; | |
113 | ||
20f4dbe4 | 114 | enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder) |
fc914639 | 115 | { |
0bdee30e | 116 | struct drm_encoder *encoder = &intel_encoder->base; |
fc914639 PZ |
117 | int type = intel_encoder->type; |
118 | ||
174edf1f | 119 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || |
00c09d70 | 120 | type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) { |
174edf1f PZ |
121 | struct intel_digital_port *intel_dig_port = |
122 | enc_to_dig_port(encoder); | |
123 | return intel_dig_port->port; | |
0bdee30e | 124 | |
fc914639 PZ |
125 | } else if (type == INTEL_OUTPUT_ANALOG) { |
126 | return PORT_E; | |
0bdee30e | 127 | |
fc914639 PZ |
128 | } else { |
129 | DRM_ERROR("Invalid DDI encoder type %d\n", type); | |
130 | BUG(); | |
131 | } | |
132 | } | |
133 | ||
e58623cb AR |
134 | /* |
135 | * Starting with Haswell, DDI port buffers must be programmed with correct | |
136 | * values in advance. The buffer values are different for FDI and DP modes, | |
45244b87 ED |
137 | * but the HDMI/DVI fields are shared among those. So we program the DDI |
138 | * in either FDI or DP modes only, as HDMI connections will work with both | |
139 | * of those | |
140 | */ | |
ad8d270c | 141 | static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port) |
45244b87 ED |
142 | { |
143 | struct drm_i915_private *dev_priv = dev->dev_private; | |
144 | u32 reg; | |
145 | int i; | |
6acab15a | 146 | int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift; |
e58623cb AR |
147 | const u32 *ddi_translations_fdi; |
148 | const u32 *ddi_translations_dp; | |
300644c7 | 149 | const u32 *ddi_translations_edp; |
e58623cb AR |
150 | const u32 *ddi_translations; |
151 | ||
152 | if (IS_BROADWELL(dev)) { | |
153 | ddi_translations_fdi = bdw_ddi_translations_fdi; | |
154 | ddi_translations_dp = bdw_ddi_translations_dp; | |
300644c7 | 155 | ddi_translations_edp = bdw_ddi_translations_edp; |
e58623cb AR |
156 | } else if (IS_HASWELL(dev)) { |
157 | ddi_translations_fdi = hsw_ddi_translations_fdi; | |
158 | ddi_translations_dp = hsw_ddi_translations_dp; | |
300644c7 | 159 | ddi_translations_edp = hsw_ddi_translations_dp; |
e58623cb AR |
160 | } else { |
161 | WARN(1, "ddi translation table missing\n"); | |
300644c7 | 162 | ddi_translations_edp = bdw_ddi_translations_dp; |
e58623cb AR |
163 | ddi_translations_fdi = bdw_ddi_translations_fdi; |
164 | ddi_translations_dp = bdw_ddi_translations_dp; | |
165 | } | |
166 | ||
300644c7 PZ |
167 | switch (port) { |
168 | case PORT_A: | |
169 | ddi_translations = ddi_translations_edp; | |
170 | break; | |
171 | case PORT_B: | |
172 | case PORT_C: | |
300644c7 PZ |
173 | ddi_translations = ddi_translations_dp; |
174 | break; | |
77d8d009 PZ |
175 | case PORT_D: |
176 | if (intel_dpd_is_edp(dev)) | |
177 | ddi_translations = ddi_translations_edp; | |
178 | else | |
179 | ddi_translations = ddi_translations_dp; | |
180 | break; | |
300644c7 PZ |
181 | case PORT_E: |
182 | ddi_translations = ddi_translations_fdi; | |
183 | break; | |
184 | default: | |
185 | BUG(); | |
186 | } | |
45244b87 | 187 | |
f72d19f0 PZ |
188 | for (i = 0, reg = DDI_BUF_TRANS(port); |
189 | i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) { | |
45244b87 ED |
190 | I915_WRITE(reg, ddi_translations[i]); |
191 | reg += 4; | |
192 | } | |
6acab15a PZ |
193 | /* Entry 9 is for HDMI: */ |
194 | for (i = 0; i < 2; i++) { | |
195 | I915_WRITE(reg, hsw_ddi_translations_hdmi[hdmi_level * 2 + i]); | |
196 | reg += 4; | |
197 | } | |
45244b87 ED |
198 | } |
199 | ||
200 | /* Program DDI buffers translations for DP. By default, program ports A-D in DP | |
201 | * mode and port E for FDI. | |
202 | */ | |
203 | void intel_prepare_ddi(struct drm_device *dev) | |
204 | { | |
205 | int port; | |
206 | ||
0d536cb4 PZ |
207 | if (!HAS_DDI(dev)) |
208 | return; | |
45244b87 | 209 | |
ad8d270c PZ |
210 | for (port = PORT_A; port <= PORT_E; port++) |
211 | intel_prepare_ddi_buffers(dev, port); | |
45244b87 | 212 | } |
c82e4d26 ED |
213 | |
214 | static const long hsw_ddi_buf_ctl_values[] = { | |
215 | DDI_BUF_EMP_400MV_0DB_HSW, | |
216 | DDI_BUF_EMP_400MV_3_5DB_HSW, | |
217 | DDI_BUF_EMP_400MV_6DB_HSW, | |
218 | DDI_BUF_EMP_400MV_9_5DB_HSW, | |
219 | DDI_BUF_EMP_600MV_0DB_HSW, | |
220 | DDI_BUF_EMP_600MV_3_5DB_HSW, | |
221 | DDI_BUF_EMP_600MV_6DB_HSW, | |
222 | DDI_BUF_EMP_800MV_0DB_HSW, | |
223 | DDI_BUF_EMP_800MV_3_5DB_HSW | |
224 | }; | |
225 | ||
248138b5 PZ |
226 | static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, |
227 | enum port port) | |
228 | { | |
229 | uint32_t reg = DDI_BUF_CTL(port); | |
230 | int i; | |
231 | ||
232 | for (i = 0; i < 8; i++) { | |
233 | udelay(1); | |
234 | if (I915_READ(reg) & DDI_BUF_IS_IDLE) | |
235 | return; | |
236 | } | |
237 | DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port)); | |
238 | } | |
c82e4d26 ED |
239 | |
240 | /* Starting with Haswell, different DDI ports can work in FDI mode for | |
241 | * connection to the PCH-located connectors. For this, it is necessary to train | |
242 | * both the DDI port and PCH receiver for the desired DDI buffer settings. | |
243 | * | |
244 | * The recommended port to work in FDI mode is DDI E, which we use here. Also, | |
245 | * please note that when FDI mode is active on DDI E, it shares 2 lines with | |
246 | * DDI A (which is used for eDP) | |
247 | */ | |
248 | ||
249 | void hsw_fdi_link_train(struct drm_crtc *crtc) | |
250 | { | |
251 | struct drm_device *dev = crtc->dev; | |
252 | struct drm_i915_private *dev_priv = dev->dev_private; | |
253 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
04945641 | 254 | u32 temp, i, rx_ctl_val; |
c82e4d26 | 255 | |
04945641 PZ |
256 | /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the |
257 | * mode set "sequence for CRT port" document: | |
258 | * - TP1 to TP2 time with the default value | |
259 | * - FDI delay to 90h | |
8693a824 DL |
260 | * |
261 | * WaFDIAutoLinkSetTimingOverrride:hsw | |
04945641 PZ |
262 | */ |
263 | I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) | | |
264 | FDI_RX_PWRDN_LANE0_VAL(2) | | |
265 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
266 | ||
267 | /* Enable the PCH Receiver FDI PLL */ | |
3e68320e | 268 | rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE | |
33d29b14 | 269 | FDI_RX_PLL_ENABLE | |
627eb5a3 | 270 | FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); |
04945641 PZ |
271 | I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); |
272 | POSTING_READ(_FDI_RXA_CTL); | |
273 | udelay(220); | |
274 | ||
275 | /* Switch from Rawclk to PCDclk */ | |
276 | rx_ctl_val |= FDI_PCDCLK; | |
277 | I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); | |
278 | ||
279 | /* Configure Port Clock Select */ | |
280 | I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->ddi_pll_sel); | |
281 | ||
282 | /* Start the training iterating through available voltages and emphasis, | |
283 | * testing each value twice. */ | |
284 | for (i = 0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values) * 2; i++) { | |
c82e4d26 ED |
285 | /* Configure DP_TP_CTL with auto-training */ |
286 | I915_WRITE(DP_TP_CTL(PORT_E), | |
287 | DP_TP_CTL_FDI_AUTOTRAIN | | |
288 | DP_TP_CTL_ENHANCED_FRAME_ENABLE | | |
289 | DP_TP_CTL_LINK_TRAIN_PAT1 | | |
290 | DP_TP_CTL_ENABLE); | |
291 | ||
876a8cdf DL |
292 | /* Configure and enable DDI_BUF_CTL for DDI E with next voltage. |
293 | * DDI E does not support port reversal, the functionality is | |
294 | * achieved on the PCH side in FDI_RX_CTL, so no need to set the | |
295 | * port reversal bit */ | |
c82e4d26 | 296 | I915_WRITE(DDI_BUF_CTL(PORT_E), |
04945641 | 297 | DDI_BUF_CTL_ENABLE | |
33d29b14 | 298 | ((intel_crtc->config.fdi_lanes - 1) << 1) | |
04945641 PZ |
299 | hsw_ddi_buf_ctl_values[i / 2]); |
300 | POSTING_READ(DDI_BUF_CTL(PORT_E)); | |
c82e4d26 ED |
301 | |
302 | udelay(600); | |
303 | ||
04945641 PZ |
304 | /* Program PCH FDI Receiver TU */ |
305 | I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64)); | |
306 | ||
307 | /* Enable PCH FDI Receiver with auto-training */ | |
308 | rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO; | |
309 | I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); | |
310 | POSTING_READ(_FDI_RXA_CTL); | |
311 | ||
312 | /* Wait for FDI receiver lane calibration */ | |
313 | udelay(30); | |
314 | ||
315 | /* Unset FDI_RX_MISC pwrdn lanes */ | |
316 | temp = I915_READ(_FDI_RXA_MISC); | |
317 | temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); | |
318 | I915_WRITE(_FDI_RXA_MISC, temp); | |
319 | POSTING_READ(_FDI_RXA_MISC); | |
320 | ||
321 | /* Wait for FDI auto training time */ | |
322 | udelay(5); | |
c82e4d26 ED |
323 | |
324 | temp = I915_READ(DP_TP_STATUS(PORT_E)); | |
325 | if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) { | |
04945641 | 326 | DRM_DEBUG_KMS("FDI link training done on step %d\n", i); |
c82e4d26 ED |
327 | |
328 | /* Enable normal pixel sending for FDI */ | |
329 | I915_WRITE(DP_TP_CTL(PORT_E), | |
04945641 PZ |
330 | DP_TP_CTL_FDI_AUTOTRAIN | |
331 | DP_TP_CTL_LINK_TRAIN_NORMAL | | |
332 | DP_TP_CTL_ENHANCED_FRAME_ENABLE | | |
333 | DP_TP_CTL_ENABLE); | |
c82e4d26 | 334 | |
04945641 | 335 | return; |
c82e4d26 | 336 | } |
04945641 | 337 | |
248138b5 PZ |
338 | temp = I915_READ(DDI_BUF_CTL(PORT_E)); |
339 | temp &= ~DDI_BUF_CTL_ENABLE; | |
340 | I915_WRITE(DDI_BUF_CTL(PORT_E), temp); | |
341 | POSTING_READ(DDI_BUF_CTL(PORT_E)); | |
342 | ||
04945641 | 343 | /* Disable DP_TP_CTL and FDI_RX_CTL and retry */ |
248138b5 PZ |
344 | temp = I915_READ(DP_TP_CTL(PORT_E)); |
345 | temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); | |
346 | temp |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
347 | I915_WRITE(DP_TP_CTL(PORT_E), temp); | |
348 | POSTING_READ(DP_TP_CTL(PORT_E)); | |
349 | ||
350 | intel_wait_ddi_buf_idle(dev_priv, PORT_E); | |
04945641 PZ |
351 | |
352 | rx_ctl_val &= ~FDI_RX_ENABLE; | |
353 | I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); | |
248138b5 | 354 | POSTING_READ(_FDI_RXA_CTL); |
04945641 PZ |
355 | |
356 | /* Reset FDI_RX_MISC pwrdn lanes */ | |
357 | temp = I915_READ(_FDI_RXA_MISC); | |
358 | temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); | |
359 | temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); | |
360 | I915_WRITE(_FDI_RXA_MISC, temp); | |
248138b5 | 361 | POSTING_READ(_FDI_RXA_MISC); |
c82e4d26 ED |
362 | } |
363 | ||
04945641 | 364 | DRM_ERROR("FDI link training failed!\n"); |
c82e4d26 | 365 | } |
0e72a5b5 | 366 | |
c7d8be30 | 367 | static void intel_ddi_mode_set(struct intel_encoder *encoder) |
72662e10 | 368 | { |
c7d8be30 DV |
369 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
370 | int port = intel_ddi_get_encoder_port(encoder); | |
371 | int pipe = crtc->pipe; | |
372 | int type = encoder->type; | |
373 | struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode; | |
72662e10 | 374 | |
bf98a726 | 375 | DRM_DEBUG_KMS("Preparing DDI mode on port %c, pipe %c\n", |
247d89f6 | 376 | port_name(port), pipe_name(pipe)); |
72662e10 | 377 | |
c7d8be30 | 378 | crtc->eld_vld = false; |
247d89f6 | 379 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { |
c7d8be30 | 380 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
876a8cdf | 381 | struct intel_digital_port *intel_dig_port = |
c7d8be30 | 382 | enc_to_dig_port(&encoder->base); |
4f07854d | 383 | |
bcf53de4 | 384 | intel_dp->DP = intel_dig_port->saved_port_bits | |
876a8cdf | 385 | DDI_BUF_CTL_ENABLE | DDI_BUF_EMP_400MV_0DB_HSW; |
17aa6be9 | 386 | intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count); |
247d89f6 | 387 | |
8fed6193 TI |
388 | if (intel_dp->has_audio) { |
389 | DRM_DEBUG_DRIVER("DP audio on pipe %c on DDI\n", | |
c7d8be30 | 390 | pipe_name(crtc->pipe)); |
8fed6193 TI |
391 | |
392 | /* write eld */ | |
393 | DRM_DEBUG_DRIVER("DP audio: write eld information\n"); | |
c7d8be30 | 394 | intel_write_eld(&encoder->base, adjusted_mode); |
8fed6193 | 395 | } |
247d89f6 | 396 | } else if (type == INTEL_OUTPUT_HDMI) { |
c7d8be30 | 397 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
247d89f6 PZ |
398 | |
399 | if (intel_hdmi->has_audio) { | |
400 | /* Proper support for digital audio needs a new logic | |
401 | * and a new set of registers, so we leave it for future | |
402 | * patch bombing. | |
403 | */ | |
404 | DRM_DEBUG_DRIVER("HDMI audio on pipe %c on DDI\n", | |
c7d8be30 | 405 | pipe_name(crtc->pipe)); |
247d89f6 PZ |
406 | |
407 | /* write eld */ | |
408 | DRM_DEBUG_DRIVER("HDMI audio: write eld information\n"); | |
c7d8be30 | 409 | intel_write_eld(&encoder->base, adjusted_mode); |
247d89f6 | 410 | } |
72662e10 | 411 | |
c7d8be30 | 412 | intel_hdmi->set_infoframes(&encoder->base, adjusted_mode); |
247d89f6 | 413 | } |
8d9ddbcb PZ |
414 | } |
415 | ||
416 | static struct intel_encoder * | |
417 | intel_ddi_get_crtc_encoder(struct drm_crtc *crtc) | |
418 | { | |
419 | struct drm_device *dev = crtc->dev; | |
420 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
421 | struct intel_encoder *intel_encoder, *ret = NULL; | |
422 | int num_encoders = 0; | |
423 | ||
424 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { | |
425 | ret = intel_encoder; | |
426 | num_encoders++; | |
427 | } | |
428 | ||
429 | if (num_encoders != 1) | |
84f44ce7 VS |
430 | WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders, |
431 | pipe_name(intel_crtc->pipe)); | |
8d9ddbcb PZ |
432 | |
433 | BUG_ON(ret == NULL); | |
434 | return ret; | |
435 | } | |
436 | ||
6441ab5f PZ |
437 | void intel_ddi_put_crtc_pll(struct drm_crtc *crtc) |
438 | { | |
439 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
440 | struct intel_ddi_plls *plls = &dev_priv->ddi_plls; | |
441 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
442 | uint32_t val; | |
443 | ||
444 | switch (intel_crtc->ddi_pll_sel) { | |
445 | case PORT_CLK_SEL_SPLL: | |
446 | plls->spll_refcount--; | |
447 | if (plls->spll_refcount == 0) { | |
448 | DRM_DEBUG_KMS("Disabling SPLL\n"); | |
449 | val = I915_READ(SPLL_CTL); | |
450 | WARN_ON(!(val & SPLL_PLL_ENABLE)); | |
451 | I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE); | |
452 | POSTING_READ(SPLL_CTL); | |
453 | } | |
454 | break; | |
455 | case PORT_CLK_SEL_WRPLL1: | |
456 | plls->wrpll1_refcount--; | |
457 | if (plls->wrpll1_refcount == 0) { | |
458 | DRM_DEBUG_KMS("Disabling WRPLL 1\n"); | |
459 | val = I915_READ(WRPLL_CTL1); | |
460 | WARN_ON(!(val & WRPLL_PLL_ENABLE)); | |
461 | I915_WRITE(WRPLL_CTL1, val & ~WRPLL_PLL_ENABLE); | |
462 | POSTING_READ(WRPLL_CTL1); | |
463 | } | |
464 | break; | |
465 | case PORT_CLK_SEL_WRPLL2: | |
466 | plls->wrpll2_refcount--; | |
467 | if (plls->wrpll2_refcount == 0) { | |
468 | DRM_DEBUG_KMS("Disabling WRPLL 2\n"); | |
469 | val = I915_READ(WRPLL_CTL2); | |
470 | WARN_ON(!(val & WRPLL_PLL_ENABLE)); | |
471 | I915_WRITE(WRPLL_CTL2, val & ~WRPLL_PLL_ENABLE); | |
472 | POSTING_READ(WRPLL_CTL2); | |
473 | } | |
474 | break; | |
475 | } | |
476 | ||
477 | WARN(plls->spll_refcount < 0, "Invalid SPLL refcount\n"); | |
478 | WARN(plls->wrpll1_refcount < 0, "Invalid WRPLL1 refcount\n"); | |
479 | WARN(plls->wrpll2_refcount < 0, "Invalid WRPLL2 refcount\n"); | |
480 | ||
481 | intel_crtc->ddi_pll_sel = PORT_CLK_SEL_NONE; | |
482 | } | |
483 | ||
1c0b85c5 DL |
484 | #define LC_FREQ 2700 |
485 | #define LC_FREQ_2K (LC_FREQ * 2000) | |
486 | ||
487 | #define P_MIN 2 | |
488 | #define P_MAX 64 | |
489 | #define P_INC 2 | |
490 | ||
491 | /* Constraints for PLL good behavior */ | |
492 | #define REF_MIN 48 | |
493 | #define REF_MAX 400 | |
494 | #define VCO_MIN 2400 | |
495 | #define VCO_MAX 4800 | |
496 | ||
497 | #define ABS_DIFF(a, b) ((a > b) ? (a - b) : (b - a)) | |
498 | ||
499 | struct wrpll_rnp { | |
500 | unsigned p, n2, r2; | |
501 | }; | |
502 | ||
503 | static unsigned wrpll_get_budget_for_freq(int clock) | |
6441ab5f | 504 | { |
1c0b85c5 DL |
505 | unsigned budget; |
506 | ||
507 | switch (clock) { | |
508 | case 25175000: | |
509 | case 25200000: | |
510 | case 27000000: | |
511 | case 27027000: | |
512 | case 37762500: | |
513 | case 37800000: | |
514 | case 40500000: | |
515 | case 40541000: | |
516 | case 54000000: | |
517 | case 54054000: | |
518 | case 59341000: | |
519 | case 59400000: | |
520 | case 72000000: | |
521 | case 74176000: | |
522 | case 74250000: | |
523 | case 81000000: | |
524 | case 81081000: | |
525 | case 89012000: | |
526 | case 89100000: | |
527 | case 108000000: | |
528 | case 108108000: | |
529 | case 111264000: | |
530 | case 111375000: | |
531 | case 148352000: | |
532 | case 148500000: | |
533 | case 162000000: | |
534 | case 162162000: | |
535 | case 222525000: | |
536 | case 222750000: | |
537 | case 296703000: | |
538 | case 297000000: | |
539 | budget = 0; | |
540 | break; | |
541 | case 233500000: | |
542 | case 245250000: | |
543 | case 247750000: | |
544 | case 253250000: | |
545 | case 298000000: | |
546 | budget = 1500; | |
547 | break; | |
548 | case 169128000: | |
549 | case 169500000: | |
550 | case 179500000: | |
551 | case 202000000: | |
552 | budget = 2000; | |
553 | break; | |
554 | case 256250000: | |
555 | case 262500000: | |
556 | case 270000000: | |
557 | case 272500000: | |
558 | case 273750000: | |
559 | case 280750000: | |
560 | case 281250000: | |
561 | case 286000000: | |
562 | case 291750000: | |
563 | budget = 4000; | |
564 | break; | |
565 | case 267250000: | |
566 | case 268500000: | |
567 | budget = 5000; | |
568 | break; | |
569 | default: | |
570 | budget = 1000; | |
571 | break; | |
572 | } | |
6441ab5f | 573 | |
1c0b85c5 DL |
574 | return budget; |
575 | } | |
576 | ||
577 | static void wrpll_update_rnp(uint64_t freq2k, unsigned budget, | |
578 | unsigned r2, unsigned n2, unsigned p, | |
579 | struct wrpll_rnp *best) | |
580 | { | |
581 | uint64_t a, b, c, d, diff, diff_best; | |
6441ab5f | 582 | |
1c0b85c5 DL |
583 | /* No best (r,n,p) yet */ |
584 | if (best->p == 0) { | |
585 | best->p = p; | |
586 | best->n2 = n2; | |
587 | best->r2 = r2; | |
588 | return; | |
589 | } | |
6441ab5f | 590 | |
1c0b85c5 DL |
591 | /* |
592 | * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to | |
593 | * freq2k. | |
594 | * | |
595 | * delta = 1e6 * | |
596 | * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) / | |
597 | * freq2k; | |
598 | * | |
599 | * and we would like delta <= budget. | |
600 | * | |
601 | * If the discrepancy is above the PPM-based budget, always prefer to | |
602 | * improve upon the previous solution. However, if you're within the | |
603 | * budget, try to maximize Ref * VCO, that is N / (P * R^2). | |
604 | */ | |
605 | a = freq2k * budget * p * r2; | |
606 | b = freq2k * budget * best->p * best->r2; | |
607 | diff = ABS_DIFF((freq2k * p * r2), (LC_FREQ_2K * n2)); | |
608 | diff_best = ABS_DIFF((freq2k * best->p * best->r2), | |
609 | (LC_FREQ_2K * best->n2)); | |
610 | c = 1000000 * diff; | |
611 | d = 1000000 * diff_best; | |
612 | ||
613 | if (a < c && b < d) { | |
614 | /* If both are above the budget, pick the closer */ | |
615 | if (best->p * best->r2 * diff < p * r2 * diff_best) { | |
616 | best->p = p; | |
617 | best->n2 = n2; | |
618 | best->r2 = r2; | |
619 | } | |
620 | } else if (a >= c && b < d) { | |
621 | /* If A is below the threshold but B is above it? Update. */ | |
622 | best->p = p; | |
623 | best->n2 = n2; | |
624 | best->r2 = r2; | |
625 | } else if (a >= c && b >= d) { | |
626 | /* Both are below the limit, so pick the higher n2/(r2*r2) */ | |
627 | if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) { | |
628 | best->p = p; | |
629 | best->n2 = n2; | |
630 | best->r2 = r2; | |
631 | } | |
632 | } | |
633 | /* Otherwise a < c && b >= d, do nothing */ | |
634 | } | |
635 | ||
636 | static void | |
637 | intel_ddi_calculate_wrpll(int clock /* in Hz */, | |
638 | unsigned *r2_out, unsigned *n2_out, unsigned *p_out) | |
639 | { | |
640 | uint64_t freq2k; | |
641 | unsigned p, n2, r2; | |
642 | struct wrpll_rnp best = { 0, 0, 0 }; | |
643 | unsigned budget; | |
644 | ||
645 | freq2k = clock / 100; | |
646 | ||
647 | budget = wrpll_get_budget_for_freq(clock); | |
648 | ||
649 | /* Special case handling for 540 pixel clock: bypass WR PLL entirely | |
650 | * and directly pass the LC PLL to it. */ | |
651 | if (freq2k == 5400000) { | |
652 | *n2_out = 2; | |
653 | *p_out = 1; | |
654 | *r2_out = 2; | |
655 | return; | |
656 | } | |
657 | ||
658 | /* | |
659 | * Ref = LC_FREQ / R, where Ref is the actual reference input seen by | |
660 | * the WR PLL. | |
661 | * | |
662 | * We want R so that REF_MIN <= Ref <= REF_MAX. | |
663 | * Injecting R2 = 2 * R gives: | |
664 | * REF_MAX * r2 > LC_FREQ * 2 and | |
665 | * REF_MIN * r2 < LC_FREQ * 2 | |
666 | * | |
667 | * Which means the desired boundaries for r2 are: | |
668 | * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN | |
669 | * | |
670 | */ | |
671 | for (r2 = LC_FREQ * 2 / REF_MAX + 1; | |
672 | r2 <= LC_FREQ * 2 / REF_MIN; | |
673 | r2++) { | |
674 | ||
675 | /* | |
676 | * VCO = N * Ref, that is: VCO = N * LC_FREQ / R | |
677 | * | |
678 | * Once again we want VCO_MIN <= VCO <= VCO_MAX. | |
679 | * Injecting R2 = 2 * R and N2 = 2 * N, we get: | |
680 | * VCO_MAX * r2 > n2 * LC_FREQ and | |
681 | * VCO_MIN * r2 < n2 * LC_FREQ) | |
682 | * | |
683 | * Which means the desired boundaries for n2 are: | |
684 | * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ | |
685 | */ | |
686 | for (n2 = VCO_MIN * r2 / LC_FREQ + 1; | |
687 | n2 <= VCO_MAX * r2 / LC_FREQ; | |
688 | n2++) { | |
689 | ||
690 | for (p = P_MIN; p <= P_MAX; p += P_INC) | |
691 | wrpll_update_rnp(freq2k, budget, | |
692 | r2, n2, p, &best); | |
693 | } | |
694 | } | |
6441ab5f | 695 | |
1c0b85c5 DL |
696 | *n2_out = best.n2; |
697 | *p_out = best.p; | |
698 | *r2_out = best.r2; | |
6441ab5f | 699 | |
1c0b85c5 DL |
700 | DRM_DEBUG_KMS("WRPLL: %dHz refresh rate with p=%d, n2=%d r2=%d\n", |
701 | clock, *p_out, *n2_out, *r2_out); | |
6441ab5f PZ |
702 | } |
703 | ||
ff9a6750 | 704 | bool intel_ddi_pll_mode_set(struct drm_crtc *crtc) |
6441ab5f PZ |
705 | { |
706 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
707 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
068759bd | 708 | struct drm_encoder *encoder = &intel_encoder->base; |
6441ab5f PZ |
709 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
710 | struct intel_ddi_plls *plls = &dev_priv->ddi_plls; | |
711 | int type = intel_encoder->type; | |
712 | enum pipe pipe = intel_crtc->pipe; | |
713 | uint32_t reg, val; | |
ff9a6750 | 714 | int clock = intel_crtc->config.port_clock; |
6441ab5f PZ |
715 | |
716 | /* TODO: reuse PLLs when possible (compare values) */ | |
717 | ||
718 | intel_ddi_put_crtc_pll(crtc); | |
719 | ||
068759bd PZ |
720 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { |
721 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
722 | ||
723 | switch (intel_dp->link_bw) { | |
724 | case DP_LINK_BW_1_62: | |
725 | intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810; | |
726 | break; | |
727 | case DP_LINK_BW_2_7: | |
728 | intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350; | |
729 | break; | |
730 | case DP_LINK_BW_5_4: | |
731 | intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700; | |
732 | break; | |
733 | default: | |
734 | DRM_ERROR("Link bandwidth %d unsupported\n", | |
735 | intel_dp->link_bw); | |
736 | return false; | |
737 | } | |
738 | ||
739 | /* We don't need to turn any PLL on because we'll use LCPLL. */ | |
740 | return true; | |
741 | ||
742 | } else if (type == INTEL_OUTPUT_HDMI) { | |
1c0b85c5 | 743 | unsigned p, n2, r2; |
6441ab5f PZ |
744 | |
745 | if (plls->wrpll1_refcount == 0) { | |
746 | DRM_DEBUG_KMS("Using WRPLL 1 on pipe %c\n", | |
747 | pipe_name(pipe)); | |
748 | plls->wrpll1_refcount++; | |
749 | reg = WRPLL_CTL1; | |
750 | intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL1; | |
751 | } else if (plls->wrpll2_refcount == 0) { | |
752 | DRM_DEBUG_KMS("Using WRPLL 2 on pipe %c\n", | |
753 | pipe_name(pipe)); | |
754 | plls->wrpll2_refcount++; | |
755 | reg = WRPLL_CTL2; | |
756 | intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL2; | |
757 | } else { | |
758 | DRM_ERROR("No WRPLLs available!\n"); | |
759 | return false; | |
760 | } | |
761 | ||
762 | WARN(I915_READ(reg) & WRPLL_PLL_ENABLE, | |
763 | "WRPLL already enabled\n"); | |
764 | ||
1c0b85c5 | 765 | intel_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p); |
6441ab5f PZ |
766 | |
767 | val = WRPLL_PLL_ENABLE | WRPLL_PLL_SELECT_LCPLL_2700 | | |
768 | WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) | | |
769 | WRPLL_DIVIDER_POST(p); | |
770 | ||
771 | } else if (type == INTEL_OUTPUT_ANALOG) { | |
772 | if (plls->spll_refcount == 0) { | |
773 | DRM_DEBUG_KMS("Using SPLL on pipe %c\n", | |
774 | pipe_name(pipe)); | |
775 | plls->spll_refcount++; | |
776 | reg = SPLL_CTL; | |
777 | intel_crtc->ddi_pll_sel = PORT_CLK_SEL_SPLL; | |
00037c2e DL |
778 | } else { |
779 | DRM_ERROR("SPLL already in use\n"); | |
780 | return false; | |
6441ab5f PZ |
781 | } |
782 | ||
783 | WARN(I915_READ(reg) & SPLL_PLL_ENABLE, | |
784 | "SPLL already enabled\n"); | |
785 | ||
39bc66c9 | 786 | val = SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC; |
6441ab5f PZ |
787 | |
788 | } else { | |
789 | WARN(1, "Invalid DDI encoder type %d\n", type); | |
790 | return false; | |
791 | } | |
792 | ||
793 | I915_WRITE(reg, val); | |
794 | udelay(20); | |
795 | ||
796 | return true; | |
797 | } | |
798 | ||
dae84799 PZ |
799 | void intel_ddi_set_pipe_settings(struct drm_crtc *crtc) |
800 | { | |
801 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
802 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
803 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
3b117c8f | 804 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
dae84799 PZ |
805 | int type = intel_encoder->type; |
806 | uint32_t temp; | |
807 | ||
808 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { | |
809 | ||
c9809791 | 810 | temp = TRANS_MSA_SYNC_CLK; |
965e0c48 | 811 | switch (intel_crtc->config.pipe_bpp) { |
dae84799 | 812 | case 18: |
c9809791 | 813 | temp |= TRANS_MSA_6_BPC; |
dae84799 PZ |
814 | break; |
815 | case 24: | |
c9809791 | 816 | temp |= TRANS_MSA_8_BPC; |
dae84799 PZ |
817 | break; |
818 | case 30: | |
c9809791 | 819 | temp |= TRANS_MSA_10_BPC; |
dae84799 PZ |
820 | break; |
821 | case 36: | |
c9809791 | 822 | temp |= TRANS_MSA_12_BPC; |
dae84799 PZ |
823 | break; |
824 | default: | |
4e53c2e0 | 825 | BUG(); |
dae84799 | 826 | } |
c9809791 | 827 | I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp); |
dae84799 PZ |
828 | } |
829 | } | |
830 | ||
8228c251 | 831 | void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc) |
8d9ddbcb PZ |
832 | { |
833 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
834 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
7739c33b | 835 | struct drm_encoder *encoder = &intel_encoder->base; |
c7670b10 PZ |
836 | struct drm_device *dev = crtc->dev; |
837 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8d9ddbcb | 838 | enum pipe pipe = intel_crtc->pipe; |
3b117c8f | 839 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
174edf1f | 840 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
7739c33b | 841 | int type = intel_encoder->type; |
8d9ddbcb PZ |
842 | uint32_t temp; |
843 | ||
ad80a810 PZ |
844 | /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ |
845 | temp = TRANS_DDI_FUNC_ENABLE; | |
174edf1f | 846 | temp |= TRANS_DDI_SELECT_PORT(port); |
dfcef252 | 847 | |
965e0c48 | 848 | switch (intel_crtc->config.pipe_bpp) { |
dfcef252 | 849 | case 18: |
ad80a810 | 850 | temp |= TRANS_DDI_BPC_6; |
dfcef252 PZ |
851 | break; |
852 | case 24: | |
ad80a810 | 853 | temp |= TRANS_DDI_BPC_8; |
dfcef252 PZ |
854 | break; |
855 | case 30: | |
ad80a810 | 856 | temp |= TRANS_DDI_BPC_10; |
dfcef252 PZ |
857 | break; |
858 | case 36: | |
ad80a810 | 859 | temp |= TRANS_DDI_BPC_12; |
dfcef252 PZ |
860 | break; |
861 | default: | |
4e53c2e0 | 862 | BUG(); |
dfcef252 | 863 | } |
72662e10 | 864 | |
a666283e | 865 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) |
ad80a810 | 866 | temp |= TRANS_DDI_PVSYNC; |
a666283e | 867 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) |
ad80a810 | 868 | temp |= TRANS_DDI_PHSYNC; |
f63eb7c4 | 869 | |
e6f0bfc4 PZ |
870 | if (cpu_transcoder == TRANSCODER_EDP) { |
871 | switch (pipe) { | |
872 | case PIPE_A: | |
c7670b10 PZ |
873 | /* On Haswell, can only use the always-on power well for |
874 | * eDP when not using the panel fitter, and when not | |
875 | * using motion blur mitigation (which we don't | |
876 | * support). */ | |
877 | if (IS_HASWELL(dev) && intel_crtc->config.pch_pfit.enabled) | |
d6dd9eb1 DV |
878 | temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; |
879 | else | |
880 | temp |= TRANS_DDI_EDP_INPUT_A_ON; | |
e6f0bfc4 PZ |
881 | break; |
882 | case PIPE_B: | |
883 | temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; | |
884 | break; | |
885 | case PIPE_C: | |
886 | temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; | |
887 | break; | |
888 | default: | |
889 | BUG(); | |
890 | break; | |
891 | } | |
892 | } | |
893 | ||
7739c33b PZ |
894 | if (type == INTEL_OUTPUT_HDMI) { |
895 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
8d9ddbcb PZ |
896 | |
897 | if (intel_hdmi->has_hdmi_sink) | |
ad80a810 | 898 | temp |= TRANS_DDI_MODE_SELECT_HDMI; |
8d9ddbcb | 899 | else |
ad80a810 | 900 | temp |= TRANS_DDI_MODE_SELECT_DVI; |
8d9ddbcb | 901 | |
7739c33b | 902 | } else if (type == INTEL_OUTPUT_ANALOG) { |
ad80a810 | 903 | temp |= TRANS_DDI_MODE_SELECT_FDI; |
33d29b14 | 904 | temp |= (intel_crtc->config.fdi_lanes - 1) << 1; |
7739c33b PZ |
905 | |
906 | } else if (type == INTEL_OUTPUT_DISPLAYPORT || | |
907 | type == INTEL_OUTPUT_EDP) { | |
908 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
909 | ||
ad80a810 | 910 | temp |= TRANS_DDI_MODE_SELECT_DP_SST; |
7739c33b | 911 | |
17aa6be9 | 912 | temp |= DDI_PORT_WIDTH(intel_dp->lane_count); |
8d9ddbcb | 913 | } else { |
84f44ce7 VS |
914 | WARN(1, "Invalid encoder type %d for pipe %c\n", |
915 | intel_encoder->type, pipe_name(pipe)); | |
8d9ddbcb PZ |
916 | } |
917 | ||
ad80a810 | 918 | I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); |
8d9ddbcb | 919 | } |
72662e10 | 920 | |
ad80a810 PZ |
921 | void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, |
922 | enum transcoder cpu_transcoder) | |
8d9ddbcb | 923 | { |
ad80a810 | 924 | uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
8d9ddbcb PZ |
925 | uint32_t val = I915_READ(reg); |
926 | ||
ad80a810 PZ |
927 | val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK); |
928 | val |= TRANS_DDI_PORT_NONE; | |
8d9ddbcb | 929 | I915_WRITE(reg, val); |
72662e10 ED |
930 | } |
931 | ||
bcbc889b PZ |
932 | bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) |
933 | { | |
934 | struct drm_device *dev = intel_connector->base.dev; | |
935 | struct drm_i915_private *dev_priv = dev->dev_private; | |
936 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
937 | int type = intel_connector->base.connector_type; | |
938 | enum port port = intel_ddi_get_encoder_port(intel_encoder); | |
939 | enum pipe pipe = 0; | |
940 | enum transcoder cpu_transcoder; | |
941 | uint32_t tmp; | |
942 | ||
943 | if (!intel_encoder->get_hw_state(intel_encoder, &pipe)) | |
944 | return false; | |
945 | ||
946 | if (port == PORT_A) | |
947 | cpu_transcoder = TRANSCODER_EDP; | |
948 | else | |
1a240d4d | 949 | cpu_transcoder = (enum transcoder) pipe; |
bcbc889b PZ |
950 | |
951 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); | |
952 | ||
953 | switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { | |
954 | case TRANS_DDI_MODE_SELECT_HDMI: | |
955 | case TRANS_DDI_MODE_SELECT_DVI: | |
956 | return (type == DRM_MODE_CONNECTOR_HDMIA); | |
957 | ||
958 | case TRANS_DDI_MODE_SELECT_DP_SST: | |
959 | if (type == DRM_MODE_CONNECTOR_eDP) | |
960 | return true; | |
961 | case TRANS_DDI_MODE_SELECT_DP_MST: | |
962 | return (type == DRM_MODE_CONNECTOR_DisplayPort); | |
963 | ||
964 | case TRANS_DDI_MODE_SELECT_FDI: | |
965 | return (type == DRM_MODE_CONNECTOR_VGA); | |
966 | ||
967 | default: | |
968 | return false; | |
969 | } | |
970 | } | |
971 | ||
85234cdc DV |
972 | bool intel_ddi_get_hw_state(struct intel_encoder *encoder, |
973 | enum pipe *pipe) | |
974 | { | |
975 | struct drm_device *dev = encoder->base.dev; | |
976 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fe43d3f5 | 977 | enum port port = intel_ddi_get_encoder_port(encoder); |
85234cdc DV |
978 | u32 tmp; |
979 | int i; | |
980 | ||
fe43d3f5 | 981 | tmp = I915_READ(DDI_BUF_CTL(port)); |
85234cdc DV |
982 | |
983 | if (!(tmp & DDI_BUF_CTL_ENABLE)) | |
984 | return false; | |
985 | ||
ad80a810 PZ |
986 | if (port == PORT_A) { |
987 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); | |
85234cdc | 988 | |
ad80a810 PZ |
989 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { |
990 | case TRANS_DDI_EDP_INPUT_A_ON: | |
991 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
992 | *pipe = PIPE_A; | |
993 | break; | |
994 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
995 | *pipe = PIPE_B; | |
996 | break; | |
997 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
998 | *pipe = PIPE_C; | |
999 | break; | |
1000 | } | |
1001 | ||
1002 | return true; | |
1003 | } else { | |
1004 | for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) { | |
1005 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(i)); | |
1006 | ||
1007 | if ((tmp & TRANS_DDI_PORT_MASK) | |
1008 | == TRANS_DDI_SELECT_PORT(port)) { | |
1009 | *pipe = i; | |
1010 | return true; | |
1011 | } | |
85234cdc DV |
1012 | } |
1013 | } | |
1014 | ||
84f44ce7 | 1015 | DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port)); |
85234cdc | 1016 | |
22f9fe50 | 1017 | return false; |
85234cdc DV |
1018 | } |
1019 | ||
6441ab5f PZ |
1020 | static uint32_t intel_ddi_get_crtc_pll(struct drm_i915_private *dev_priv, |
1021 | enum pipe pipe) | |
1022 | { | |
1023 | uint32_t temp, ret; | |
a42f704b | 1024 | enum port port = I915_MAX_PORTS; |
ad80a810 PZ |
1025 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1026 | pipe); | |
6441ab5f PZ |
1027 | int i; |
1028 | ||
ad80a810 PZ |
1029 | if (cpu_transcoder == TRANSCODER_EDP) { |
1030 | port = PORT_A; | |
1031 | } else { | |
1032 | temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); | |
1033 | temp &= TRANS_DDI_PORT_MASK; | |
1034 | ||
1035 | for (i = PORT_B; i <= PORT_E; i++) | |
1036 | if (temp == TRANS_DDI_SELECT_PORT(i)) | |
1037 | port = i; | |
1038 | } | |
6441ab5f | 1039 | |
a42f704b DL |
1040 | if (port == I915_MAX_PORTS) { |
1041 | WARN(1, "Pipe %c enabled on an unknown port\n", | |
1042 | pipe_name(pipe)); | |
1043 | ret = PORT_CLK_SEL_NONE; | |
1044 | } else { | |
1045 | ret = I915_READ(PORT_CLK_SEL(port)); | |
1046 | DRM_DEBUG_KMS("Pipe %c connected to port %c using clock " | |
1047 | "0x%08x\n", pipe_name(pipe), port_name(port), | |
1048 | ret); | |
1049 | } | |
6441ab5f PZ |
1050 | |
1051 | return ret; | |
1052 | } | |
1053 | ||
1054 | void intel_ddi_setup_hw_pll_state(struct drm_device *dev) | |
1055 | { | |
1056 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1057 | enum pipe pipe; | |
1058 | struct intel_crtc *intel_crtc; | |
1059 | ||
1060 | for_each_pipe(pipe) { | |
1061 | intel_crtc = | |
1062 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
1063 | ||
1064 | if (!intel_crtc->active) | |
1065 | continue; | |
1066 | ||
1067 | intel_crtc->ddi_pll_sel = intel_ddi_get_crtc_pll(dev_priv, | |
1068 | pipe); | |
1069 | ||
1070 | switch (intel_crtc->ddi_pll_sel) { | |
1071 | case PORT_CLK_SEL_SPLL: | |
1072 | dev_priv->ddi_plls.spll_refcount++; | |
1073 | break; | |
1074 | case PORT_CLK_SEL_WRPLL1: | |
1075 | dev_priv->ddi_plls.wrpll1_refcount++; | |
1076 | break; | |
1077 | case PORT_CLK_SEL_WRPLL2: | |
1078 | dev_priv->ddi_plls.wrpll2_refcount++; | |
1079 | break; | |
1080 | } | |
1081 | } | |
1082 | } | |
1083 | ||
fc914639 PZ |
1084 | void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc) |
1085 | { | |
1086 | struct drm_crtc *crtc = &intel_crtc->base; | |
1087 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
1088 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
1089 | enum port port = intel_ddi_get_encoder_port(intel_encoder); | |
3b117c8f | 1090 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
fc914639 | 1091 | |
bb523fc0 PZ |
1092 | if (cpu_transcoder != TRANSCODER_EDP) |
1093 | I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), | |
1094 | TRANS_CLK_SEL_PORT(port)); | |
fc914639 PZ |
1095 | } |
1096 | ||
1097 | void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc) | |
1098 | { | |
1099 | struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; | |
3b117c8f | 1100 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
fc914639 | 1101 | |
bb523fc0 PZ |
1102 | if (cpu_transcoder != TRANSCODER_EDP) |
1103 | I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), | |
1104 | TRANS_CLK_SEL_DISABLED); | |
fc914639 PZ |
1105 | } |
1106 | ||
00c09d70 | 1107 | static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder) |
6441ab5f | 1108 | { |
c19b0669 PZ |
1109 | struct drm_encoder *encoder = &intel_encoder->base; |
1110 | struct drm_crtc *crtc = encoder->crtc; | |
1111 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; | |
6441ab5f PZ |
1112 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
1113 | enum port port = intel_ddi_get_encoder_port(intel_encoder); | |
82a4d9c0 | 1114 | int type = intel_encoder->type; |
6441ab5f | 1115 | |
82a4d9c0 PZ |
1116 | if (type == INTEL_OUTPUT_EDP) { |
1117 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
1118 | ironlake_edp_panel_vdd_on(intel_dp); | |
1119 | ironlake_edp_panel_on(intel_dp); | |
1120 | ironlake_edp_panel_vdd_off(intel_dp, true); | |
1121 | } | |
6441ab5f | 1122 | |
82a4d9c0 | 1123 | WARN_ON(intel_crtc->ddi_pll_sel == PORT_CLK_SEL_NONE); |
6441ab5f | 1124 | I915_WRITE(PORT_CLK_SEL(port), intel_crtc->ddi_pll_sel); |
c19b0669 | 1125 | |
82a4d9c0 | 1126 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { |
c19b0669 PZ |
1127 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
1128 | ||
1129 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); | |
1130 | intel_dp_start_link_train(intel_dp); | |
1131 | intel_dp_complete_link_train(intel_dp); | |
3ab9c637 ID |
1132 | if (port != PORT_A) |
1133 | intel_dp_stop_link_train(intel_dp); | |
c19b0669 | 1134 | } |
6441ab5f PZ |
1135 | } |
1136 | ||
00c09d70 | 1137 | static void intel_ddi_post_disable(struct intel_encoder *intel_encoder) |
6441ab5f PZ |
1138 | { |
1139 | struct drm_encoder *encoder = &intel_encoder->base; | |
1140 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; | |
1141 | enum port port = intel_ddi_get_encoder_port(intel_encoder); | |
82a4d9c0 | 1142 | int type = intel_encoder->type; |
2886e93f | 1143 | uint32_t val; |
a836bdf9 | 1144 | bool wait = false; |
2886e93f PZ |
1145 | |
1146 | val = I915_READ(DDI_BUF_CTL(port)); | |
1147 | if (val & DDI_BUF_CTL_ENABLE) { | |
1148 | val &= ~DDI_BUF_CTL_ENABLE; | |
1149 | I915_WRITE(DDI_BUF_CTL(port), val); | |
a836bdf9 | 1150 | wait = true; |
2886e93f | 1151 | } |
6441ab5f | 1152 | |
a836bdf9 PZ |
1153 | val = I915_READ(DP_TP_CTL(port)); |
1154 | val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); | |
1155 | val |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
1156 | I915_WRITE(DP_TP_CTL(port), val); | |
1157 | ||
1158 | if (wait) | |
1159 | intel_wait_ddi_buf_idle(dev_priv, port); | |
1160 | ||
82a4d9c0 PZ |
1161 | if (type == INTEL_OUTPUT_EDP) { |
1162 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
1163 | ironlake_edp_panel_vdd_on(intel_dp); | |
1164 | ironlake_edp_panel_off(intel_dp); | |
1165 | } | |
1166 | ||
6441ab5f PZ |
1167 | I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); |
1168 | } | |
1169 | ||
00c09d70 | 1170 | static void intel_enable_ddi(struct intel_encoder *intel_encoder) |
72662e10 | 1171 | { |
6547fef8 | 1172 | struct drm_encoder *encoder = &intel_encoder->base; |
7b9f35a6 WX |
1173 | struct drm_crtc *crtc = encoder->crtc; |
1174 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1175 | int pipe = intel_crtc->pipe; | |
6547fef8 | 1176 | struct drm_device *dev = encoder->dev; |
72662e10 | 1177 | struct drm_i915_private *dev_priv = dev->dev_private; |
6547fef8 PZ |
1178 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
1179 | int type = intel_encoder->type; | |
7b9f35a6 | 1180 | uint32_t tmp; |
72662e10 | 1181 | |
6547fef8 | 1182 | if (type == INTEL_OUTPUT_HDMI) { |
876a8cdf DL |
1183 | struct intel_digital_port *intel_dig_port = |
1184 | enc_to_dig_port(encoder); | |
1185 | ||
6547fef8 PZ |
1186 | /* In HDMI/DVI mode, the port width, and swing/emphasis values |
1187 | * are ignored so nothing special needs to be done besides | |
1188 | * enabling the port. | |
1189 | */ | |
876a8cdf | 1190 | I915_WRITE(DDI_BUF_CTL(port), |
bcf53de4 SM |
1191 | intel_dig_port->saved_port_bits | |
1192 | DDI_BUF_CTL_ENABLE); | |
d6c50ff8 PZ |
1193 | } else if (type == INTEL_OUTPUT_EDP) { |
1194 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
1195 | ||
3ab9c637 ID |
1196 | if (port == PORT_A) |
1197 | intel_dp_stop_link_train(intel_dp); | |
1198 | ||
d6c50ff8 | 1199 | ironlake_edp_backlight_on(intel_dp); |
4906557e | 1200 | intel_edp_psr_enable(intel_dp); |
6547fef8 | 1201 | } |
7b9f35a6 | 1202 | |
c77bf565 | 1203 | if (intel_crtc->eld_vld && type != INTEL_OUTPUT_EDP) { |
7b9f35a6 WX |
1204 | tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); |
1205 | tmp |= ((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << (pipe * 4)); | |
1206 | I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); | |
1207 | } | |
5ab432ef DV |
1208 | } |
1209 | ||
00c09d70 | 1210 | static void intel_disable_ddi(struct intel_encoder *intel_encoder) |
5ab432ef | 1211 | { |
d6c50ff8 | 1212 | struct drm_encoder *encoder = &intel_encoder->base; |
7b9f35a6 WX |
1213 | struct drm_crtc *crtc = encoder->crtc; |
1214 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1215 | int pipe = intel_crtc->pipe; | |
d6c50ff8 | 1216 | int type = intel_encoder->type; |
7b9f35a6 WX |
1217 | struct drm_device *dev = encoder->dev; |
1218 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1219 | uint32_t tmp; | |
d6c50ff8 | 1220 | |
c77bf565 PZ |
1221 | if (intel_crtc->eld_vld && type != INTEL_OUTPUT_EDP) { |
1222 | tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); | |
1223 | tmp &= ~((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << | |
1224 | (pipe * 4)); | |
1225 | I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); | |
1226 | } | |
2831d842 | 1227 | |
d6c50ff8 PZ |
1228 | if (type == INTEL_OUTPUT_EDP) { |
1229 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
1230 | ||
4906557e | 1231 | intel_edp_psr_disable(intel_dp); |
d6c50ff8 PZ |
1232 | ironlake_edp_backlight_off(intel_dp); |
1233 | } | |
72662e10 | 1234 | } |
79f689aa | 1235 | |
b8fc2f6a | 1236 | int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv) |
79f689aa | 1237 | { |
e39bf98a | 1238 | struct drm_device *dev = dev_priv->dev; |
a4006641 | 1239 | uint32_t lcpll = I915_READ(LCPLL_CTL); |
e39bf98a | 1240 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; |
a4006641 | 1241 | |
e39bf98a | 1242 | if (lcpll & LCPLL_CD_SOURCE_FCLK) { |
a4006641 | 1243 | return 800000; |
e39bf98a | 1244 | } else if (I915_READ(HSW_FUSE_STRAP) & HSW_CDCLK_LIMIT) { |
b2b877ff | 1245 | return 450000; |
e39bf98a | 1246 | } else if (freq == LCPLL_CLK_FREQ_450) { |
b2b877ff | 1247 | return 450000; |
e39bf98a PZ |
1248 | } else if (IS_HASWELL(dev)) { |
1249 | if (IS_ULT(dev)) | |
1250 | return 337500; | |
1251 | else | |
1252 | return 540000; | |
1253 | } else { | |
1254 | if (freq == LCPLL_CLK_FREQ_54O_BDW) | |
1255 | return 540000; | |
1256 | else if (freq == LCPLL_CLK_FREQ_337_5_BDW) | |
1257 | return 337500; | |
1258 | else | |
1259 | return 675000; | |
1260 | } | |
79f689aa PZ |
1261 | } |
1262 | ||
1263 | void intel_ddi_pll_init(struct drm_device *dev) | |
1264 | { | |
1265 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1266 | uint32_t val = I915_READ(LCPLL_CTL); | |
1267 | ||
1268 | /* The LCPLL register should be turned on by the BIOS. For now let's | |
1269 | * just check its state and print errors in case something is wrong. | |
1270 | * Don't even try to turn it on. | |
1271 | */ | |
1272 | ||
b2b877ff | 1273 | DRM_DEBUG_KMS("CDCLK running at %dKHz\n", |
79f689aa PZ |
1274 | intel_ddi_get_cdclk_freq(dev_priv)); |
1275 | ||
1276 | if (val & LCPLL_CD_SOURCE_FCLK) | |
1277 | DRM_ERROR("CDCLK source is not LCPLL\n"); | |
1278 | ||
1279 | if (val & LCPLL_PLL_DISABLE) | |
1280 | DRM_ERROR("LCPLL is disabled\n"); | |
1281 | } | |
c19b0669 PZ |
1282 | |
1283 | void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder) | |
1284 | { | |
174edf1f PZ |
1285 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
1286 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
c19b0669 | 1287 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
174edf1f | 1288 | enum port port = intel_dig_port->port; |
c19b0669 | 1289 | uint32_t val; |
f3e227df | 1290 | bool wait = false; |
c19b0669 PZ |
1291 | |
1292 | if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) { | |
1293 | val = I915_READ(DDI_BUF_CTL(port)); | |
1294 | if (val & DDI_BUF_CTL_ENABLE) { | |
1295 | val &= ~DDI_BUF_CTL_ENABLE; | |
1296 | I915_WRITE(DDI_BUF_CTL(port), val); | |
1297 | wait = true; | |
1298 | } | |
1299 | ||
1300 | val = I915_READ(DP_TP_CTL(port)); | |
1301 | val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); | |
1302 | val |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
1303 | I915_WRITE(DP_TP_CTL(port), val); | |
1304 | POSTING_READ(DP_TP_CTL(port)); | |
1305 | ||
1306 | if (wait) | |
1307 | intel_wait_ddi_buf_idle(dev_priv, port); | |
1308 | } | |
1309 | ||
1310 | val = DP_TP_CTL_ENABLE | DP_TP_CTL_MODE_SST | | |
1311 | DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE; | |
6aba5b6c | 1312 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
c19b0669 PZ |
1313 | val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; |
1314 | I915_WRITE(DP_TP_CTL(port), val); | |
1315 | POSTING_READ(DP_TP_CTL(port)); | |
1316 | ||
1317 | intel_dp->DP |= DDI_BUF_CTL_ENABLE; | |
1318 | I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP); | |
1319 | POSTING_READ(DDI_BUF_CTL(port)); | |
1320 | ||
1321 | udelay(600); | |
1322 | } | |
00c09d70 | 1323 | |
1ad960f2 PZ |
1324 | void intel_ddi_fdi_disable(struct drm_crtc *crtc) |
1325 | { | |
1326 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
1327 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
1328 | uint32_t val; | |
1329 | ||
1330 | intel_ddi_post_disable(intel_encoder); | |
1331 | ||
1332 | val = I915_READ(_FDI_RXA_CTL); | |
1333 | val &= ~FDI_RX_ENABLE; | |
1334 | I915_WRITE(_FDI_RXA_CTL, val); | |
1335 | ||
1336 | val = I915_READ(_FDI_RXA_MISC); | |
1337 | val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); | |
1338 | val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); | |
1339 | I915_WRITE(_FDI_RXA_MISC, val); | |
1340 | ||
1341 | val = I915_READ(_FDI_RXA_CTL); | |
1342 | val &= ~FDI_PCDCLK; | |
1343 | I915_WRITE(_FDI_RXA_CTL, val); | |
1344 | ||
1345 | val = I915_READ(_FDI_RXA_CTL); | |
1346 | val &= ~FDI_RX_PLL_ENABLE; | |
1347 | I915_WRITE(_FDI_RXA_CTL, val); | |
1348 | } | |
1349 | ||
00c09d70 PZ |
1350 | static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder) |
1351 | { | |
1352 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
1353 | int type = intel_encoder->type; | |
1354 | ||
1355 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) | |
1356 | intel_dp_check_link_status(intel_dp); | |
1357 | } | |
1358 | ||
6801c18c VS |
1359 | void intel_ddi_get_config(struct intel_encoder *encoder, |
1360 | struct intel_crtc_config *pipe_config) | |
045ac3b5 JB |
1361 | { |
1362 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
1363 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); | |
1364 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; | |
1365 | u32 temp, flags = 0; | |
1366 | ||
1367 | temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); | |
1368 | if (temp & TRANS_DDI_PHSYNC) | |
1369 | flags |= DRM_MODE_FLAG_PHSYNC; | |
1370 | else | |
1371 | flags |= DRM_MODE_FLAG_NHSYNC; | |
1372 | if (temp & TRANS_DDI_PVSYNC) | |
1373 | flags |= DRM_MODE_FLAG_PVSYNC; | |
1374 | else | |
1375 | flags |= DRM_MODE_FLAG_NVSYNC; | |
1376 | ||
1377 | pipe_config->adjusted_mode.flags |= flags; | |
42571aef VS |
1378 | |
1379 | switch (temp & TRANS_DDI_BPC_MASK) { | |
1380 | case TRANS_DDI_BPC_6: | |
1381 | pipe_config->pipe_bpp = 18; | |
1382 | break; | |
1383 | case TRANS_DDI_BPC_8: | |
1384 | pipe_config->pipe_bpp = 24; | |
1385 | break; | |
1386 | case TRANS_DDI_BPC_10: | |
1387 | pipe_config->pipe_bpp = 30; | |
1388 | break; | |
1389 | case TRANS_DDI_BPC_12: | |
1390 | pipe_config->pipe_bpp = 36; | |
1391 | break; | |
1392 | default: | |
1393 | break; | |
1394 | } | |
eb14cb74 VS |
1395 | |
1396 | switch (temp & TRANS_DDI_MODE_SELECT_MASK) { | |
1397 | case TRANS_DDI_MODE_SELECT_HDMI: | |
1398 | case TRANS_DDI_MODE_SELECT_DVI: | |
1399 | case TRANS_DDI_MODE_SELECT_FDI: | |
1400 | break; | |
1401 | case TRANS_DDI_MODE_SELECT_DP_SST: | |
1402 | case TRANS_DDI_MODE_SELECT_DP_MST: | |
1403 | pipe_config->has_dp_encoder = true; | |
1404 | intel_dp_get_m_n(intel_crtc, pipe_config); | |
1405 | break; | |
1406 | default: | |
1407 | break; | |
1408 | } | |
10214420 DV |
1409 | |
1410 | if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp && | |
1411 | pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) { | |
1412 | /* | |
1413 | * This is a big fat ugly hack. | |
1414 | * | |
1415 | * Some machines in UEFI boot mode provide us a VBT that has 18 | |
1416 | * bpp and 1.62 GHz link bandwidth for eDP, which for reasons | |
1417 | * unknown we fail to light up. Yet the same BIOS boots up with | |
1418 | * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as | |
1419 | * max, not what it tells us to use. | |
1420 | * | |
1421 | * Note: This will still be broken if the eDP panel is not lit | |
1422 | * up by the BIOS, and thus we can't get the mode at module | |
1423 | * load. | |
1424 | */ | |
1425 | DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", | |
1426 | pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp); | |
1427 | dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp; | |
1428 | } | |
045ac3b5 JB |
1429 | } |
1430 | ||
00c09d70 PZ |
1431 | static void intel_ddi_destroy(struct drm_encoder *encoder) |
1432 | { | |
1433 | /* HDMI has nothing special to destroy, so we can go with this. */ | |
1434 | intel_dp_encoder_destroy(encoder); | |
1435 | } | |
1436 | ||
5bfe2ac0 DV |
1437 | static bool intel_ddi_compute_config(struct intel_encoder *encoder, |
1438 | struct intel_crtc_config *pipe_config) | |
00c09d70 | 1439 | { |
5bfe2ac0 | 1440 | int type = encoder->type; |
eccb140b | 1441 | int port = intel_ddi_get_encoder_port(encoder); |
00c09d70 | 1442 | |
5bfe2ac0 | 1443 | WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n"); |
00c09d70 | 1444 | |
eccb140b DV |
1445 | if (port == PORT_A) |
1446 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
1447 | ||
00c09d70 | 1448 | if (type == INTEL_OUTPUT_HDMI) |
5bfe2ac0 | 1449 | return intel_hdmi_compute_config(encoder, pipe_config); |
00c09d70 | 1450 | else |
5bfe2ac0 | 1451 | return intel_dp_compute_config(encoder, pipe_config); |
00c09d70 PZ |
1452 | } |
1453 | ||
1454 | static const struct drm_encoder_funcs intel_ddi_funcs = { | |
1455 | .destroy = intel_ddi_destroy, | |
1456 | }; | |
1457 | ||
4a28ae58 PZ |
1458 | static struct intel_connector * |
1459 | intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port) | |
1460 | { | |
1461 | struct intel_connector *connector; | |
1462 | enum port port = intel_dig_port->port; | |
1463 | ||
1464 | connector = kzalloc(sizeof(*connector), GFP_KERNEL); | |
1465 | if (!connector) | |
1466 | return NULL; | |
1467 | ||
1468 | intel_dig_port->dp.output_reg = DDI_BUF_CTL(port); | |
1469 | if (!intel_dp_init_connector(intel_dig_port, connector)) { | |
1470 | kfree(connector); | |
1471 | return NULL; | |
1472 | } | |
1473 | ||
1474 | return connector; | |
1475 | } | |
1476 | ||
1477 | static struct intel_connector * | |
1478 | intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port) | |
1479 | { | |
1480 | struct intel_connector *connector; | |
1481 | enum port port = intel_dig_port->port; | |
1482 | ||
1483 | connector = kzalloc(sizeof(*connector), GFP_KERNEL); | |
1484 | if (!connector) | |
1485 | return NULL; | |
1486 | ||
1487 | intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); | |
1488 | intel_hdmi_init_connector(intel_dig_port, connector); | |
1489 | ||
1490 | return connector; | |
1491 | } | |
1492 | ||
00c09d70 PZ |
1493 | void intel_ddi_init(struct drm_device *dev, enum port port) |
1494 | { | |
876a8cdf | 1495 | struct drm_i915_private *dev_priv = dev->dev_private; |
00c09d70 PZ |
1496 | struct intel_digital_port *intel_dig_port; |
1497 | struct intel_encoder *intel_encoder; | |
1498 | struct drm_encoder *encoder; | |
1499 | struct intel_connector *hdmi_connector = NULL; | |
1500 | struct intel_connector *dp_connector = NULL; | |
311a2094 PZ |
1501 | bool init_hdmi, init_dp; |
1502 | ||
1503 | init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi || | |
1504 | dev_priv->vbt.ddi_port_info[port].supports_hdmi); | |
1505 | init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp; | |
1506 | if (!init_dp && !init_hdmi) { | |
1507 | DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible\n", | |
1508 | port_name(port)); | |
1509 | init_hdmi = true; | |
1510 | init_dp = true; | |
1511 | } | |
00c09d70 | 1512 | |
b14c5679 | 1513 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
00c09d70 PZ |
1514 | if (!intel_dig_port) |
1515 | return; | |
1516 | ||
00c09d70 PZ |
1517 | intel_encoder = &intel_dig_port->base; |
1518 | encoder = &intel_encoder->base; | |
1519 | ||
1520 | drm_encoder_init(dev, encoder, &intel_ddi_funcs, | |
1521 | DRM_MODE_ENCODER_TMDS); | |
00c09d70 | 1522 | |
5bfe2ac0 | 1523 | intel_encoder->compute_config = intel_ddi_compute_config; |
c7d8be30 | 1524 | intel_encoder->mode_set = intel_ddi_mode_set; |
00c09d70 PZ |
1525 | intel_encoder->enable = intel_enable_ddi; |
1526 | intel_encoder->pre_enable = intel_ddi_pre_enable; | |
1527 | intel_encoder->disable = intel_disable_ddi; | |
1528 | intel_encoder->post_disable = intel_ddi_post_disable; | |
1529 | intel_encoder->get_hw_state = intel_ddi_get_hw_state; | |
045ac3b5 | 1530 | intel_encoder->get_config = intel_ddi_get_config; |
00c09d70 PZ |
1531 | |
1532 | intel_dig_port->port = port; | |
bcf53de4 SM |
1533 | intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) & |
1534 | (DDI_BUF_PORT_REVERSAL | | |
1535 | DDI_A_4_LANES); | |
00c09d70 PZ |
1536 | |
1537 | intel_encoder->type = INTEL_OUTPUT_UNKNOWN; | |
1538 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); | |
1539 | intel_encoder->cloneable = false; | |
1540 | intel_encoder->hot_plug = intel_ddi_hot_plug; | |
1541 | ||
4a28ae58 PZ |
1542 | if (init_dp) |
1543 | dp_connector = intel_ddi_init_dp_connector(intel_dig_port); | |
21a8e6a4 | 1544 | |
311a2094 PZ |
1545 | /* In theory we don't need the encoder->type check, but leave it just in |
1546 | * case we have some really bad VBTs... */ | |
4a28ae58 PZ |
1547 | if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) |
1548 | hdmi_connector = intel_ddi_init_hdmi_connector(intel_dig_port); | |
21a8e6a4 | 1549 | |
4a28ae58 PZ |
1550 | if (!dp_connector && !hdmi_connector) { |
1551 | drm_encoder_cleanup(encoder); | |
1552 | kfree(intel_dig_port); | |
21a8e6a4 | 1553 | } |
00c09d70 | 1554 | } |