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45244b87 ED |
1 | /* |
2 | * Copyright © 2012 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eugeni Dodonov <eugeni.dodonov@intel.com> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "i915_drv.h" | |
29 | #include "intel_drv.h" | |
30 | ||
31 | /* HDMI/DVI modes ignore everything but the last 2 items. So we share | |
32 | * them for both DP and FDI transports, allowing those ports to | |
33 | * automatically adapt to HDMI connections as well | |
34 | */ | |
35 | static const u32 hsw_ddi_translations_dp[] = { | |
36 | 0x00FFFFFF, 0x0006000E, /* DP parameters */ | |
37 | 0x00D75FFF, 0x0005000A, | |
38 | 0x00C30FFF, 0x00040006, | |
39 | 0x80AAAFFF, 0x000B0000, | |
40 | 0x00FFFFFF, 0x0005000A, | |
41 | 0x00D75FFF, 0x000C0004, | |
42 | 0x80C30FFF, 0x000B0000, | |
43 | 0x00FFFFFF, 0x00040006, | |
44 | 0x80D75FFF, 0x000B0000, | |
45 | 0x00FFFFFF, 0x00040006 /* HDMI parameters */ | |
46 | }; | |
47 | ||
48 | static const u32 hsw_ddi_translations_fdi[] = { | |
49 | 0x00FFFFFF, 0x0007000E, /* FDI parameters */ | |
50 | 0x00D75FFF, 0x000F000A, | |
51 | 0x00C30FFF, 0x00060006, | |
52 | 0x00AAAFFF, 0x001E0000, | |
53 | 0x00FFFFFF, 0x000F000A, | |
54 | 0x00D75FFF, 0x00160004, | |
55 | 0x00C30FFF, 0x001E0000, | |
56 | 0x00FFFFFF, 0x00060006, | |
57 | 0x00D75FFF, 0x001E0000, | |
58 | 0x00FFFFFF, 0x00040006 /* HDMI parameters */ | |
59 | }; | |
60 | ||
fc914639 PZ |
61 | static enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder) |
62 | { | |
0bdee30e | 63 | struct drm_encoder *encoder = &intel_encoder->base; |
fc914639 PZ |
64 | int type = intel_encoder->type; |
65 | ||
174edf1f PZ |
66 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || |
67 | type == INTEL_OUTPUT_HDMI) { | |
68 | struct intel_digital_port *intel_dig_port = | |
69 | enc_to_dig_port(encoder); | |
70 | return intel_dig_port->port; | |
0bdee30e | 71 | |
fc914639 PZ |
72 | } else if (type == INTEL_OUTPUT_ANALOG) { |
73 | return PORT_E; | |
0bdee30e | 74 | |
fc914639 PZ |
75 | } else { |
76 | DRM_ERROR("Invalid DDI encoder type %d\n", type); | |
77 | BUG(); | |
78 | } | |
79 | } | |
80 | ||
45244b87 ED |
81 | /* On Haswell, DDI port buffers must be programmed with correct values |
82 | * in advance. The buffer values are different for FDI and DP modes, | |
83 | * but the HDMI/DVI fields are shared among those. So we program the DDI | |
84 | * in either FDI or DP modes only, as HDMI connections will work with both | |
85 | * of those | |
86 | */ | |
87 | void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port, bool use_fdi_mode) | |
88 | { | |
89 | struct drm_i915_private *dev_priv = dev->dev_private; | |
90 | u32 reg; | |
91 | int i; | |
92 | const u32 *ddi_translations = ((use_fdi_mode) ? | |
93 | hsw_ddi_translations_fdi : | |
94 | hsw_ddi_translations_dp); | |
95 | ||
96 | DRM_DEBUG_DRIVER("Initializing DDI buffers for port %c in %s mode\n", | |
97 | port_name(port), | |
98 | use_fdi_mode ? "FDI" : "DP"); | |
99 | ||
100 | WARN((use_fdi_mode && (port != PORT_E)), | |
101 | "Programming port %c in FDI mode, this probably will not work.\n", | |
102 | port_name(port)); | |
103 | ||
104 | for (i=0, reg=DDI_BUF_TRANS(port); i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) { | |
105 | I915_WRITE(reg, ddi_translations[i]); | |
106 | reg += 4; | |
107 | } | |
108 | } | |
109 | ||
110 | /* Program DDI buffers translations for DP. By default, program ports A-D in DP | |
111 | * mode and port E for FDI. | |
112 | */ | |
113 | void intel_prepare_ddi(struct drm_device *dev) | |
114 | { | |
115 | int port; | |
116 | ||
117 | if (IS_HASWELL(dev)) { | |
118 | for (port = PORT_A; port < PORT_E; port++) | |
119 | intel_prepare_ddi_buffers(dev, port, false); | |
120 | ||
121 | /* DDI E is the suggested one to work in FDI mode, so program is as such by | |
122 | * default. It will have to be re-programmed in case a digital DP output | |
123 | * will be detected on it | |
124 | */ | |
125 | intel_prepare_ddi_buffers(dev, PORT_E, true); | |
126 | } | |
127 | } | |
c82e4d26 ED |
128 | |
129 | static const long hsw_ddi_buf_ctl_values[] = { | |
130 | DDI_BUF_EMP_400MV_0DB_HSW, | |
131 | DDI_BUF_EMP_400MV_3_5DB_HSW, | |
132 | DDI_BUF_EMP_400MV_6DB_HSW, | |
133 | DDI_BUF_EMP_400MV_9_5DB_HSW, | |
134 | DDI_BUF_EMP_600MV_0DB_HSW, | |
135 | DDI_BUF_EMP_600MV_3_5DB_HSW, | |
136 | DDI_BUF_EMP_600MV_6DB_HSW, | |
137 | DDI_BUF_EMP_800MV_0DB_HSW, | |
138 | DDI_BUF_EMP_800MV_3_5DB_HSW | |
139 | }; | |
140 | ||
141 | ||
142 | /* Starting with Haswell, different DDI ports can work in FDI mode for | |
143 | * connection to the PCH-located connectors. For this, it is necessary to train | |
144 | * both the DDI port and PCH receiver for the desired DDI buffer settings. | |
145 | * | |
146 | * The recommended port to work in FDI mode is DDI E, which we use here. Also, | |
147 | * please note that when FDI mode is active on DDI E, it shares 2 lines with | |
148 | * DDI A (which is used for eDP) | |
149 | */ | |
150 | ||
151 | void hsw_fdi_link_train(struct drm_crtc *crtc) | |
152 | { | |
153 | struct drm_device *dev = crtc->dev; | |
154 | struct drm_i915_private *dev_priv = dev->dev_private; | |
155 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
156 | int pipe = intel_crtc->pipe; | |
157 | u32 reg, temp, i; | |
158 | ||
c82e4d26 ED |
159 | /* Start the training iterating through available voltages and emphasis */ |
160 | for (i=0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values); i++) { | |
161 | /* Configure DP_TP_CTL with auto-training */ | |
162 | I915_WRITE(DP_TP_CTL(PORT_E), | |
163 | DP_TP_CTL_FDI_AUTOTRAIN | | |
164 | DP_TP_CTL_ENHANCED_FRAME_ENABLE | | |
165 | DP_TP_CTL_LINK_TRAIN_PAT1 | | |
166 | DP_TP_CTL_ENABLE); | |
167 | ||
168 | /* Configure and enable DDI_BUF_CTL for DDI E with next voltage */ | |
169 | temp = I915_READ(DDI_BUF_CTL(PORT_E)); | |
170 | temp = (temp & ~DDI_BUF_EMP_MASK); | |
171 | I915_WRITE(DDI_BUF_CTL(PORT_E), | |
172 | temp | | |
173 | DDI_BUF_CTL_ENABLE | | |
174 | DDI_PORT_WIDTH_X2 | | |
175 | hsw_ddi_buf_ctl_values[i]); | |
176 | ||
177 | udelay(600); | |
178 | ||
4acf5186 ED |
179 | /* We need to program FDI_RX_MISC with the default TP1 to TP2 |
180 | * values before enabling the receiver, and configure the delay | |
181 | * for the FDI timing generator to 90h. Luckily, all the other | |
182 | * bits are supposed to be zeroed, so we can write those values | |
183 | * directly. | |
184 | */ | |
185 | I915_WRITE(FDI_RX_MISC(pipe), FDI_RX_TP1_TO_TP2_48 | | |
186 | FDI_RX_FDI_DELAY_90); | |
187 | ||
c82e4d26 ED |
188 | /* Enable CPU FDI Receiver with auto-training */ |
189 | reg = FDI_RX_CTL(pipe); | |
190 | I915_WRITE(reg, | |
191 | I915_READ(reg) | | |
192 | FDI_LINK_TRAIN_AUTO | | |
193 | FDI_RX_ENABLE | | |
194 | FDI_LINK_TRAIN_PATTERN_1_CPT | | |
195 | FDI_RX_ENHANCE_FRAME_ENABLE | | |
196 | FDI_PORT_WIDTH_2X_LPT | | |
197 | FDI_RX_PLL_ENABLE); | |
198 | POSTING_READ(reg); | |
199 | udelay(100); | |
200 | ||
201 | temp = I915_READ(DP_TP_STATUS(PORT_E)); | |
202 | if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) { | |
203 | DRM_DEBUG_DRIVER("BUF_CTL training done on %d step\n", i); | |
204 | ||
205 | /* Enable normal pixel sending for FDI */ | |
206 | I915_WRITE(DP_TP_CTL(PORT_E), | |
207 | DP_TP_CTL_FDI_AUTOTRAIN | | |
208 | DP_TP_CTL_LINK_TRAIN_NORMAL | | |
209 | DP_TP_CTL_ENHANCED_FRAME_ENABLE | | |
210 | DP_TP_CTL_ENABLE); | |
211 | ||
c82e4d26 ED |
212 | break; |
213 | } else { | |
214 | DRM_ERROR("Error training BUF_CTL %d\n", i); | |
215 | ||
216 | /* Disable DP_TP_CTL and FDI_RX_CTL) and retry */ | |
217 | I915_WRITE(DP_TP_CTL(PORT_E), | |
218 | I915_READ(DP_TP_CTL(PORT_E)) & | |
219 | ~DP_TP_CTL_ENABLE); | |
220 | I915_WRITE(FDI_RX_CTL(pipe), | |
221 | I915_READ(FDI_RX_CTL(pipe)) & | |
222 | ~FDI_RX_PLL_ENABLE); | |
223 | continue; | |
224 | } | |
225 | } | |
226 | ||
227 | DRM_DEBUG_KMS("FDI train done.\n"); | |
228 | } | |
0e72a5b5 ED |
229 | |
230 | /* For DDI connections, it is possible to support different outputs over the | |
231 | * same DDI port, such as HDMI or DP or even VGA via FDI. So we don't know by | |
232 | * the time the output is detected what exactly is on the other end of it. This | |
233 | * function aims at providing support for this detection and proper output | |
234 | * configuration. | |
235 | */ | |
236 | void intel_ddi_init(struct drm_device *dev, enum port port) | |
237 | { | |
238 | /* For now, we don't do any proper output detection and assume that we | |
239 | * handle HDMI only */ | |
240 | ||
241 | switch(port){ | |
242 | case PORT_A: | |
0e72a5b5 | 243 | DRM_DEBUG_DRIVER("Found digital output on DDI port A\n"); |
5de8bbf5 | 244 | intel_dp_init(dev, DDI_BUF_CTL_A, PORT_A); |
0e72a5b5 ED |
245 | break; |
246 | /* Assume that the ports B, C and D are working in HDMI mode for now */ | |
247 | case PORT_B: | |
248 | case PORT_C: | |
249 | case PORT_D: | |
08d644ad | 250 | intel_hdmi_init(dev, DDI_BUF_CTL(port), port); |
0e72a5b5 ED |
251 | break; |
252 | default: | |
253 | DRM_DEBUG_DRIVER("No handlers defined for port %d, skipping DDI initialization\n", | |
254 | port); | |
255 | break; | |
256 | } | |
257 | } | |
12a13a33 ED |
258 | |
259 | /* WRPLL clock dividers */ | |
260 | struct wrpll_tmds_clock { | |
261 | u32 clock; | |
262 | u16 p; /* Post divider */ | |
263 | u16 n2; /* Feedback divider */ | |
264 | u16 r2; /* Reference divider */ | |
265 | }; | |
266 | ||
126e9be8 PZ |
267 | /* Table of matching values for WRPLL clocks programming for each frequency. |
268 | * The code assumes this table is sorted. */ | |
12a13a33 ED |
269 | static const struct wrpll_tmds_clock wrpll_tmds_clock_table[] = { |
270 | {19750, 38, 25, 18}, | |
271 | {20000, 48, 32, 18}, | |
272 | {21000, 36, 21, 15}, | |
273 | {21912, 42, 29, 17}, | |
274 | {22000, 36, 22, 15}, | |
275 | {23000, 36, 23, 15}, | |
276 | {23500, 40, 40, 23}, | |
277 | {23750, 26, 16, 14}, | |
12a13a33 ED |
278 | {24000, 36, 24, 15}, |
279 | {25000, 36, 25, 15}, | |
280 | {25175, 26, 40, 33}, | |
281 | {25200, 30, 21, 15}, | |
282 | {26000, 36, 26, 15}, | |
283 | {27000, 30, 21, 14}, | |
284 | {27027, 18, 100, 111}, | |
285 | {27500, 30, 29, 19}, | |
286 | {28000, 34, 30, 17}, | |
287 | {28320, 26, 30, 22}, | |
288 | {28322, 32, 42, 25}, | |
289 | {28750, 24, 23, 18}, | |
290 | {29000, 30, 29, 18}, | |
291 | {29750, 32, 30, 17}, | |
292 | {30000, 30, 25, 15}, | |
293 | {30750, 30, 41, 24}, | |
294 | {31000, 30, 31, 18}, | |
295 | {31500, 30, 28, 16}, | |
296 | {32000, 30, 32, 18}, | |
297 | {32500, 28, 32, 19}, | |
298 | {33000, 24, 22, 15}, | |
299 | {34000, 28, 30, 17}, | |
300 | {35000, 26, 32, 19}, | |
301 | {35500, 24, 30, 19}, | |
302 | {36000, 26, 26, 15}, | |
303 | {36750, 26, 46, 26}, | |
304 | {37000, 24, 23, 14}, | |
305 | {37762, 22, 40, 26}, | |
306 | {37800, 20, 21, 15}, | |
307 | {38000, 24, 27, 16}, | |
308 | {38250, 24, 34, 20}, | |
309 | {39000, 24, 26, 15}, | |
310 | {40000, 24, 32, 18}, | |
311 | {40500, 20, 21, 14}, | |
312 | {40541, 22, 147, 89}, | |
313 | {40750, 18, 19, 14}, | |
314 | {41000, 16, 17, 14}, | |
315 | {41500, 22, 44, 26}, | |
316 | {41540, 22, 44, 26}, | |
317 | {42000, 18, 21, 15}, | |
318 | {42500, 22, 45, 26}, | |
319 | {43000, 20, 43, 27}, | |
320 | {43163, 20, 24, 15}, | |
321 | {44000, 18, 22, 15}, | |
322 | {44900, 20, 108, 65}, | |
323 | {45000, 20, 25, 15}, | |
324 | {45250, 20, 52, 31}, | |
325 | {46000, 18, 23, 15}, | |
326 | {46750, 20, 45, 26}, | |
327 | {47000, 20, 40, 23}, | |
328 | {48000, 18, 24, 15}, | |
329 | {49000, 18, 49, 30}, | |
330 | {49500, 16, 22, 15}, | |
331 | {50000, 18, 25, 15}, | |
332 | {50500, 18, 32, 19}, | |
333 | {51000, 18, 34, 20}, | |
334 | {52000, 18, 26, 15}, | |
335 | {52406, 14, 34, 25}, | |
336 | {53000, 16, 22, 14}, | |
337 | {54000, 16, 24, 15}, | |
338 | {54054, 16, 173, 108}, | |
339 | {54500, 14, 24, 17}, | |
340 | {55000, 12, 22, 18}, | |
341 | {56000, 14, 45, 31}, | |
342 | {56250, 16, 25, 15}, | |
343 | {56750, 14, 25, 17}, | |
344 | {57000, 16, 27, 16}, | |
345 | {58000, 16, 43, 25}, | |
346 | {58250, 16, 38, 22}, | |
347 | {58750, 16, 40, 23}, | |
348 | {59000, 14, 26, 17}, | |
349 | {59341, 14, 40, 26}, | |
350 | {59400, 16, 44, 25}, | |
351 | {60000, 16, 32, 18}, | |
352 | {60500, 12, 39, 29}, | |
353 | {61000, 14, 49, 31}, | |
354 | {62000, 14, 37, 23}, | |
355 | {62250, 14, 42, 26}, | |
356 | {63000, 12, 21, 15}, | |
357 | {63500, 14, 28, 17}, | |
358 | {64000, 12, 27, 19}, | |
359 | {65000, 14, 32, 19}, | |
360 | {65250, 12, 29, 20}, | |
361 | {65500, 12, 32, 22}, | |
362 | {66000, 12, 22, 15}, | |
363 | {66667, 14, 38, 22}, | |
364 | {66750, 10, 21, 17}, | |
365 | {67000, 14, 33, 19}, | |
366 | {67750, 14, 58, 33}, | |
367 | {68000, 14, 30, 17}, | |
368 | {68179, 14, 46, 26}, | |
369 | {68250, 14, 46, 26}, | |
370 | {69000, 12, 23, 15}, | |
371 | {70000, 12, 28, 18}, | |
372 | {71000, 12, 30, 19}, | |
373 | {72000, 12, 24, 15}, | |
374 | {73000, 10, 23, 17}, | |
375 | {74000, 12, 23, 14}, | |
376 | {74176, 8, 100, 91}, | |
377 | {74250, 10, 22, 16}, | |
378 | {74481, 12, 43, 26}, | |
379 | {74500, 10, 29, 21}, | |
380 | {75000, 12, 25, 15}, | |
381 | {75250, 10, 39, 28}, | |
382 | {76000, 12, 27, 16}, | |
383 | {77000, 12, 53, 31}, | |
384 | {78000, 12, 26, 15}, | |
385 | {78750, 12, 28, 16}, | |
386 | {79000, 10, 38, 26}, | |
387 | {79500, 10, 28, 19}, | |
388 | {80000, 12, 32, 18}, | |
389 | {81000, 10, 21, 14}, | |
390 | {81081, 6, 100, 111}, | |
391 | {81624, 8, 29, 24}, | |
392 | {82000, 8, 17, 14}, | |
393 | {83000, 10, 40, 26}, | |
394 | {83950, 10, 28, 18}, | |
395 | {84000, 10, 28, 18}, | |
396 | {84750, 6, 16, 17}, | |
397 | {85000, 6, 17, 18}, | |
398 | {85250, 10, 30, 19}, | |
399 | {85750, 10, 27, 17}, | |
400 | {86000, 10, 43, 27}, | |
401 | {87000, 10, 29, 18}, | |
402 | {88000, 10, 44, 27}, | |
403 | {88500, 10, 41, 25}, | |
404 | {89000, 10, 28, 17}, | |
405 | {89012, 6, 90, 91}, | |
406 | {89100, 10, 33, 20}, | |
407 | {90000, 10, 25, 15}, | |
408 | {91000, 10, 32, 19}, | |
409 | {92000, 10, 46, 27}, | |
410 | {93000, 10, 31, 18}, | |
411 | {94000, 10, 40, 23}, | |
412 | {94500, 10, 28, 16}, | |
413 | {95000, 10, 44, 25}, | |
414 | {95654, 10, 39, 22}, | |
415 | {95750, 10, 39, 22}, | |
416 | {96000, 10, 32, 18}, | |
417 | {97000, 8, 23, 16}, | |
418 | {97750, 8, 42, 29}, | |
419 | {98000, 8, 45, 31}, | |
420 | {99000, 8, 22, 15}, | |
421 | {99750, 8, 34, 23}, | |
422 | {100000, 6, 20, 18}, | |
423 | {100500, 6, 19, 17}, | |
424 | {101000, 6, 37, 33}, | |
425 | {101250, 8, 21, 14}, | |
426 | {102000, 6, 17, 15}, | |
427 | {102250, 6, 25, 22}, | |
428 | {103000, 8, 29, 19}, | |
429 | {104000, 8, 37, 24}, | |
430 | {105000, 8, 28, 18}, | |
431 | {106000, 8, 22, 14}, | |
432 | {107000, 8, 46, 29}, | |
433 | {107214, 8, 27, 17}, | |
434 | {108000, 8, 24, 15}, | |
435 | {108108, 8, 173, 108}, | |
436 | {109000, 6, 23, 19}, | |
12a13a33 ED |
437 | {110000, 6, 22, 18}, |
438 | {110013, 6, 22, 18}, | |
439 | {110250, 8, 49, 30}, | |
440 | {110500, 8, 36, 22}, | |
441 | {111000, 8, 23, 14}, | |
442 | {111264, 8, 150, 91}, | |
443 | {111375, 8, 33, 20}, | |
444 | {112000, 8, 63, 38}, | |
445 | {112500, 8, 25, 15}, | |
446 | {113100, 8, 57, 34}, | |
447 | {113309, 8, 42, 25}, | |
448 | {114000, 8, 27, 16}, | |
449 | {115000, 6, 23, 18}, | |
450 | {116000, 8, 43, 25}, | |
451 | {117000, 8, 26, 15}, | |
452 | {117500, 8, 40, 23}, | |
453 | {118000, 6, 38, 29}, | |
454 | {119000, 8, 30, 17}, | |
455 | {119500, 8, 46, 26}, | |
456 | {119651, 8, 39, 22}, | |
457 | {120000, 8, 32, 18}, | |
458 | {121000, 6, 39, 29}, | |
459 | {121250, 6, 31, 23}, | |
460 | {121750, 6, 23, 17}, | |
461 | {122000, 6, 42, 31}, | |
462 | {122614, 6, 30, 22}, | |
463 | {123000, 6, 41, 30}, | |
464 | {123379, 6, 37, 27}, | |
465 | {124000, 6, 51, 37}, | |
466 | {125000, 6, 25, 18}, | |
467 | {125250, 4, 13, 14}, | |
468 | {125750, 4, 27, 29}, | |
469 | {126000, 6, 21, 15}, | |
470 | {127000, 6, 24, 17}, | |
471 | {127250, 6, 41, 29}, | |
472 | {128000, 6, 27, 19}, | |
473 | {129000, 6, 43, 30}, | |
474 | {129859, 4, 25, 26}, | |
475 | {130000, 6, 26, 18}, | |
476 | {130250, 6, 42, 29}, | |
477 | {131000, 6, 32, 22}, | |
478 | {131500, 6, 38, 26}, | |
479 | {131850, 6, 41, 28}, | |
480 | {132000, 6, 22, 15}, | |
481 | {132750, 6, 28, 19}, | |
482 | {133000, 6, 34, 23}, | |
483 | {133330, 6, 37, 25}, | |
484 | {134000, 6, 61, 41}, | |
485 | {135000, 6, 21, 14}, | |
486 | {135250, 6, 167, 111}, | |
487 | {136000, 6, 62, 41}, | |
488 | {137000, 6, 35, 23}, | |
489 | {138000, 6, 23, 15}, | |
490 | {138500, 6, 40, 26}, | |
491 | {138750, 6, 37, 24}, | |
492 | {139000, 6, 34, 22}, | |
493 | {139050, 6, 34, 22}, | |
494 | {139054, 6, 34, 22}, | |
495 | {140000, 6, 28, 18}, | |
496 | {141000, 6, 36, 23}, | |
497 | {141500, 6, 22, 14}, | |
498 | {142000, 6, 30, 19}, | |
499 | {143000, 6, 27, 17}, | |
500 | {143472, 4, 17, 16}, | |
501 | {144000, 6, 24, 15}, | |
502 | {145000, 6, 29, 18}, | |
503 | {146000, 6, 47, 29}, | |
504 | {146250, 6, 26, 16}, | |
505 | {147000, 6, 49, 30}, | |
506 | {147891, 6, 23, 14}, | |
507 | {148000, 6, 23, 14}, | |
508 | {148250, 6, 28, 17}, | |
509 | {148352, 4, 100, 91}, | |
510 | {148500, 6, 33, 20}, | |
511 | {149000, 6, 48, 29}, | |
512 | {150000, 6, 25, 15}, | |
513 | {151000, 4, 19, 17}, | |
514 | {152000, 6, 27, 16}, | |
515 | {152280, 6, 44, 26}, | |
516 | {153000, 6, 34, 20}, | |
517 | {154000, 6, 53, 31}, | |
518 | {155000, 6, 31, 18}, | |
519 | {155250, 6, 50, 29}, | |
520 | {155750, 6, 45, 26}, | |
521 | {156000, 6, 26, 15}, | |
522 | {157000, 6, 61, 35}, | |
523 | {157500, 6, 28, 16}, | |
524 | {158000, 6, 65, 37}, | |
525 | {158250, 6, 44, 25}, | |
526 | {159000, 6, 53, 30}, | |
527 | {159500, 6, 39, 22}, | |
528 | {160000, 6, 32, 18}, | |
529 | {161000, 4, 31, 26}, | |
530 | {162000, 4, 18, 15}, | |
531 | {162162, 4, 131, 109}, | |
532 | {162500, 4, 53, 44}, | |
533 | {163000, 4, 29, 24}, | |
534 | {164000, 4, 17, 14}, | |
535 | {165000, 4, 22, 18}, | |
536 | {166000, 4, 32, 26}, | |
537 | {167000, 4, 26, 21}, | |
538 | {168000, 4, 46, 37}, | |
539 | {169000, 4, 104, 83}, | |
540 | {169128, 4, 64, 51}, | |
541 | {169500, 4, 39, 31}, | |
542 | {170000, 4, 34, 27}, | |
543 | {171000, 4, 19, 15}, | |
544 | {172000, 4, 51, 40}, | |
545 | {172750, 4, 32, 25}, | |
546 | {172800, 4, 32, 25}, | |
547 | {173000, 4, 41, 32}, | |
548 | {174000, 4, 49, 38}, | |
549 | {174787, 4, 22, 17}, | |
550 | {175000, 4, 35, 27}, | |
551 | {176000, 4, 30, 23}, | |
552 | {177000, 4, 38, 29}, | |
553 | {178000, 4, 29, 22}, | |
554 | {178500, 4, 37, 28}, | |
555 | {179000, 4, 53, 40}, | |
556 | {179500, 4, 73, 55}, | |
557 | {180000, 4, 20, 15}, | |
558 | {181000, 4, 55, 41}, | |
559 | {182000, 4, 31, 23}, | |
560 | {183000, 4, 42, 31}, | |
561 | {184000, 4, 30, 22}, | |
562 | {184750, 4, 26, 19}, | |
563 | {185000, 4, 37, 27}, | |
564 | {186000, 4, 51, 37}, | |
565 | {187000, 4, 36, 26}, | |
566 | {188000, 4, 32, 23}, | |
567 | {189000, 4, 21, 15}, | |
568 | {190000, 4, 38, 27}, | |
569 | {190960, 4, 41, 29}, | |
570 | {191000, 4, 41, 29}, | |
571 | {192000, 4, 27, 19}, | |
572 | {192250, 4, 37, 26}, | |
573 | {193000, 4, 20, 14}, | |
574 | {193250, 4, 53, 37}, | |
575 | {194000, 4, 23, 16}, | |
576 | {194208, 4, 23, 16}, | |
577 | {195000, 4, 26, 18}, | |
578 | {196000, 4, 45, 31}, | |
579 | {197000, 4, 35, 24}, | |
580 | {197750, 4, 41, 28}, | |
581 | {198000, 4, 22, 15}, | |
582 | {198500, 4, 25, 17}, | |
583 | {199000, 4, 28, 19}, | |
584 | {200000, 4, 37, 25}, | |
585 | {201000, 4, 61, 41}, | |
586 | {202000, 4, 112, 75}, | |
587 | {202500, 4, 21, 14}, | |
588 | {203000, 4, 146, 97}, | |
589 | {204000, 4, 62, 41}, | |
590 | {204750, 4, 44, 29}, | |
591 | {205000, 4, 38, 25}, | |
592 | {206000, 4, 29, 19}, | |
593 | {207000, 4, 23, 15}, | |
594 | {207500, 4, 40, 26}, | |
595 | {208000, 4, 37, 24}, | |
596 | {208900, 4, 48, 31}, | |
597 | {209000, 4, 48, 31}, | |
598 | {209250, 4, 31, 20}, | |
599 | {210000, 4, 28, 18}, | |
600 | {211000, 4, 25, 16}, | |
601 | {212000, 4, 22, 14}, | |
602 | {213000, 4, 30, 19}, | |
603 | {213750, 4, 38, 24}, | |
604 | {214000, 4, 46, 29}, | |
605 | {214750, 4, 35, 22}, | |
606 | {215000, 4, 43, 27}, | |
607 | {216000, 4, 24, 15}, | |
608 | {217000, 4, 37, 23}, | |
609 | {218000, 4, 42, 26}, | |
610 | {218250, 4, 42, 26}, | |
611 | {218750, 4, 34, 21}, | |
612 | {219000, 4, 47, 29}, | |
12a13a33 ED |
613 | {220000, 4, 44, 27}, |
614 | {220640, 4, 49, 30}, | |
615 | {220750, 4, 36, 22}, | |
616 | {221000, 4, 36, 22}, | |
617 | {222000, 4, 23, 14}, | |
618 | {222525, 4, 28, 17}, | |
619 | {222750, 4, 33, 20}, | |
620 | {227000, 4, 37, 22}, | |
621 | {230250, 4, 29, 17}, | |
622 | {233500, 4, 38, 22}, | |
623 | {235000, 4, 40, 23}, | |
624 | {238000, 4, 30, 17}, | |
625 | {241500, 2, 17, 19}, | |
626 | {245250, 2, 20, 22}, | |
627 | {247750, 2, 22, 24}, | |
628 | {253250, 2, 15, 16}, | |
629 | {256250, 2, 18, 19}, | |
630 | {262500, 2, 31, 32}, | |
631 | {267250, 2, 66, 67}, | |
632 | {268500, 2, 94, 95}, | |
633 | {270000, 2, 14, 14}, | |
634 | {272500, 2, 77, 76}, | |
635 | {273750, 2, 57, 56}, | |
636 | {280750, 2, 24, 23}, | |
637 | {281250, 2, 23, 22}, | |
638 | {286000, 2, 17, 16}, | |
639 | {291750, 2, 26, 24}, | |
640 | {296703, 2, 56, 51}, | |
641 | {297000, 2, 22, 20}, | |
642 | {298000, 2, 21, 19}, | |
643 | }; | |
72662e10 ED |
644 | |
645 | void intel_ddi_mode_set(struct drm_encoder *encoder, | |
646 | struct drm_display_mode *mode, | |
647 | struct drm_display_mode *adjusted_mode) | |
648 | { | |
72662e10 ED |
649 | struct drm_crtc *crtc = encoder->crtc; |
650 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
247d89f6 PZ |
651 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
652 | int port = intel_ddi_get_encoder_port(intel_encoder); | |
72662e10 | 653 | int pipe = intel_crtc->pipe; |
247d89f6 | 654 | int type = intel_encoder->type; |
72662e10 | 655 | |
247d89f6 PZ |
656 | DRM_DEBUG_KMS("Preparing DDI mode for Haswell on port %c, pipe %c\n", |
657 | port_name(port), pipe_name(pipe)); | |
72662e10 | 658 | |
247d89f6 PZ |
659 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { |
660 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
4f07854d | 661 | |
247d89f6 PZ |
662 | intel_dp->DP = DDI_BUF_CTL_ENABLE | DDI_BUF_EMP_400MV_0DB_HSW; |
663 | switch (intel_dp->lane_count) { | |
664 | case 1: | |
665 | intel_dp->DP |= DDI_PORT_WIDTH_X1; | |
666 | break; | |
667 | case 2: | |
668 | intel_dp->DP |= DDI_PORT_WIDTH_X2; | |
669 | break; | |
670 | case 4: | |
671 | intel_dp->DP |= DDI_PORT_WIDTH_X4; | |
672 | break; | |
673 | default: | |
674 | intel_dp->DP |= DDI_PORT_WIDTH_X4; | |
675 | WARN(1, "Unexpected DP lane count %d\n", | |
676 | intel_dp->lane_count); | |
677 | break; | |
678 | } | |
679 | ||
680 | intel_dp_init_link_config(intel_dp); | |
681 | ||
682 | } else if (type == INTEL_OUTPUT_HDMI) { | |
683 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
684 | ||
685 | if (intel_hdmi->has_audio) { | |
686 | /* Proper support for digital audio needs a new logic | |
687 | * and a new set of registers, so we leave it for future | |
688 | * patch bombing. | |
689 | */ | |
690 | DRM_DEBUG_DRIVER("HDMI audio on pipe %c on DDI\n", | |
691 | pipe_name(intel_crtc->pipe)); | |
692 | ||
693 | /* write eld */ | |
694 | DRM_DEBUG_DRIVER("HDMI audio: write eld information\n"); | |
695 | intel_write_eld(encoder, adjusted_mode); | |
696 | } | |
72662e10 | 697 | |
247d89f6 PZ |
698 | intel_hdmi->set_infoframes(encoder, adjusted_mode); |
699 | } | |
8d9ddbcb PZ |
700 | } |
701 | ||
702 | static struct intel_encoder * | |
703 | intel_ddi_get_crtc_encoder(struct drm_crtc *crtc) | |
704 | { | |
705 | struct drm_device *dev = crtc->dev; | |
706 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
707 | struct intel_encoder *intel_encoder, *ret = NULL; | |
708 | int num_encoders = 0; | |
709 | ||
710 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { | |
711 | ret = intel_encoder; | |
712 | num_encoders++; | |
713 | } | |
714 | ||
715 | if (num_encoders != 1) | |
716 | WARN(1, "%d encoders on crtc for pipe %d\n", num_encoders, | |
717 | intel_crtc->pipe); | |
718 | ||
719 | BUG_ON(ret == NULL); | |
720 | return ret; | |
721 | } | |
722 | ||
6441ab5f PZ |
723 | void intel_ddi_put_crtc_pll(struct drm_crtc *crtc) |
724 | { | |
725 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
726 | struct intel_ddi_plls *plls = &dev_priv->ddi_plls; | |
727 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
728 | uint32_t val; | |
729 | ||
730 | switch (intel_crtc->ddi_pll_sel) { | |
731 | case PORT_CLK_SEL_SPLL: | |
732 | plls->spll_refcount--; | |
733 | if (plls->spll_refcount == 0) { | |
734 | DRM_DEBUG_KMS("Disabling SPLL\n"); | |
735 | val = I915_READ(SPLL_CTL); | |
736 | WARN_ON(!(val & SPLL_PLL_ENABLE)); | |
737 | I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE); | |
738 | POSTING_READ(SPLL_CTL); | |
739 | } | |
740 | break; | |
741 | case PORT_CLK_SEL_WRPLL1: | |
742 | plls->wrpll1_refcount--; | |
743 | if (plls->wrpll1_refcount == 0) { | |
744 | DRM_DEBUG_KMS("Disabling WRPLL 1\n"); | |
745 | val = I915_READ(WRPLL_CTL1); | |
746 | WARN_ON(!(val & WRPLL_PLL_ENABLE)); | |
747 | I915_WRITE(WRPLL_CTL1, val & ~WRPLL_PLL_ENABLE); | |
748 | POSTING_READ(WRPLL_CTL1); | |
749 | } | |
750 | break; | |
751 | case PORT_CLK_SEL_WRPLL2: | |
752 | plls->wrpll2_refcount--; | |
753 | if (plls->wrpll2_refcount == 0) { | |
754 | DRM_DEBUG_KMS("Disabling WRPLL 2\n"); | |
755 | val = I915_READ(WRPLL_CTL2); | |
756 | WARN_ON(!(val & WRPLL_PLL_ENABLE)); | |
757 | I915_WRITE(WRPLL_CTL2, val & ~WRPLL_PLL_ENABLE); | |
758 | POSTING_READ(WRPLL_CTL2); | |
759 | } | |
760 | break; | |
761 | } | |
762 | ||
763 | WARN(plls->spll_refcount < 0, "Invalid SPLL refcount\n"); | |
764 | WARN(plls->wrpll1_refcount < 0, "Invalid WRPLL1 refcount\n"); | |
765 | WARN(plls->wrpll2_refcount < 0, "Invalid WRPLL2 refcount\n"); | |
766 | ||
767 | intel_crtc->ddi_pll_sel = PORT_CLK_SEL_NONE; | |
768 | } | |
769 | ||
770 | static void intel_ddi_calculate_wrpll(int clock, int *p, int *n2, int *r2) | |
771 | { | |
772 | u32 i; | |
773 | ||
774 | for (i = 0; i < ARRAY_SIZE(wrpll_tmds_clock_table); i++) | |
775 | if (clock <= wrpll_tmds_clock_table[i].clock) | |
776 | break; | |
777 | ||
778 | if (i == ARRAY_SIZE(wrpll_tmds_clock_table)) | |
779 | i--; | |
780 | ||
781 | *p = wrpll_tmds_clock_table[i].p; | |
782 | *n2 = wrpll_tmds_clock_table[i].n2; | |
783 | *r2 = wrpll_tmds_clock_table[i].r2; | |
784 | ||
785 | if (wrpll_tmds_clock_table[i].clock != clock) | |
786 | DRM_INFO("WRPLL: using settings for %dKHz on %dKHz mode\n", | |
787 | wrpll_tmds_clock_table[i].clock, clock); | |
788 | ||
789 | DRM_DEBUG_KMS("WRPLL: %dKHz refresh rate with p=%d, n2=%d r2=%d\n", | |
790 | clock, *p, *n2, *r2); | |
791 | } | |
792 | ||
793 | bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock) | |
794 | { | |
795 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
796 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
068759bd | 797 | struct drm_encoder *encoder = &intel_encoder->base; |
6441ab5f PZ |
798 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
799 | struct intel_ddi_plls *plls = &dev_priv->ddi_plls; | |
800 | int type = intel_encoder->type; | |
801 | enum pipe pipe = intel_crtc->pipe; | |
802 | uint32_t reg, val; | |
803 | ||
804 | /* TODO: reuse PLLs when possible (compare values) */ | |
805 | ||
806 | intel_ddi_put_crtc_pll(crtc); | |
807 | ||
068759bd PZ |
808 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { |
809 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
810 | ||
811 | switch (intel_dp->link_bw) { | |
812 | case DP_LINK_BW_1_62: | |
813 | intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810; | |
814 | break; | |
815 | case DP_LINK_BW_2_7: | |
816 | intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350; | |
817 | break; | |
818 | case DP_LINK_BW_5_4: | |
819 | intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700; | |
820 | break; | |
821 | default: | |
822 | DRM_ERROR("Link bandwidth %d unsupported\n", | |
823 | intel_dp->link_bw); | |
824 | return false; | |
825 | } | |
826 | ||
827 | /* We don't need to turn any PLL on because we'll use LCPLL. */ | |
828 | return true; | |
829 | ||
830 | } else if (type == INTEL_OUTPUT_HDMI) { | |
6441ab5f PZ |
831 | int p, n2, r2; |
832 | ||
833 | if (plls->wrpll1_refcount == 0) { | |
834 | DRM_DEBUG_KMS("Using WRPLL 1 on pipe %c\n", | |
835 | pipe_name(pipe)); | |
836 | plls->wrpll1_refcount++; | |
837 | reg = WRPLL_CTL1; | |
838 | intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL1; | |
839 | } else if (plls->wrpll2_refcount == 0) { | |
840 | DRM_DEBUG_KMS("Using WRPLL 2 on pipe %c\n", | |
841 | pipe_name(pipe)); | |
842 | plls->wrpll2_refcount++; | |
843 | reg = WRPLL_CTL2; | |
844 | intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL2; | |
845 | } else { | |
846 | DRM_ERROR("No WRPLLs available!\n"); | |
847 | return false; | |
848 | } | |
849 | ||
850 | WARN(I915_READ(reg) & WRPLL_PLL_ENABLE, | |
851 | "WRPLL already enabled\n"); | |
852 | ||
853 | intel_ddi_calculate_wrpll(clock, &p, &n2, &r2); | |
854 | ||
855 | val = WRPLL_PLL_ENABLE | WRPLL_PLL_SELECT_LCPLL_2700 | | |
856 | WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) | | |
857 | WRPLL_DIVIDER_POST(p); | |
858 | ||
859 | } else if (type == INTEL_OUTPUT_ANALOG) { | |
860 | if (plls->spll_refcount == 0) { | |
861 | DRM_DEBUG_KMS("Using SPLL on pipe %c\n", | |
862 | pipe_name(pipe)); | |
863 | plls->spll_refcount++; | |
864 | reg = SPLL_CTL; | |
865 | intel_crtc->ddi_pll_sel = PORT_CLK_SEL_SPLL; | |
866 | } | |
867 | ||
868 | WARN(I915_READ(reg) & SPLL_PLL_ENABLE, | |
869 | "SPLL already enabled\n"); | |
870 | ||
39bc66c9 | 871 | val = SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC; |
6441ab5f PZ |
872 | |
873 | } else { | |
874 | WARN(1, "Invalid DDI encoder type %d\n", type); | |
875 | return false; | |
876 | } | |
877 | ||
878 | I915_WRITE(reg, val); | |
879 | udelay(20); | |
880 | ||
881 | return true; | |
882 | } | |
883 | ||
dae84799 PZ |
884 | void intel_ddi_set_pipe_settings(struct drm_crtc *crtc) |
885 | { | |
886 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
887 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
888 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
c9809791 | 889 | enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder; |
dae84799 PZ |
890 | int type = intel_encoder->type; |
891 | uint32_t temp; | |
892 | ||
893 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { | |
894 | ||
c9809791 | 895 | temp = TRANS_MSA_SYNC_CLK; |
dae84799 PZ |
896 | switch (intel_crtc->bpp) { |
897 | case 18: | |
c9809791 | 898 | temp |= TRANS_MSA_6_BPC; |
dae84799 PZ |
899 | break; |
900 | case 24: | |
c9809791 | 901 | temp |= TRANS_MSA_8_BPC; |
dae84799 PZ |
902 | break; |
903 | case 30: | |
c9809791 | 904 | temp |= TRANS_MSA_10_BPC; |
dae84799 PZ |
905 | break; |
906 | case 36: | |
c9809791 | 907 | temp |= TRANS_MSA_12_BPC; |
dae84799 PZ |
908 | break; |
909 | default: | |
c9809791 PZ |
910 | temp |= TRANS_MSA_8_BPC; |
911 | WARN(1, "%d bpp unsupported by DDI function\n", | |
dae84799 PZ |
912 | intel_crtc->bpp); |
913 | } | |
c9809791 | 914 | I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp); |
dae84799 PZ |
915 | } |
916 | } | |
917 | ||
8d9ddbcb PZ |
918 | void intel_ddi_enable_pipe_func(struct drm_crtc *crtc) |
919 | { | |
920 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
921 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
7739c33b | 922 | struct drm_encoder *encoder = &intel_encoder->base; |
8d9ddbcb PZ |
923 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
924 | enum pipe pipe = intel_crtc->pipe; | |
ad80a810 | 925 | enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder; |
174edf1f | 926 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
7739c33b | 927 | int type = intel_encoder->type; |
8d9ddbcb PZ |
928 | uint32_t temp; |
929 | ||
ad80a810 PZ |
930 | /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ |
931 | temp = TRANS_DDI_FUNC_ENABLE; | |
174edf1f | 932 | temp |= TRANS_DDI_SELECT_PORT(port); |
dfcef252 PZ |
933 | |
934 | switch (intel_crtc->bpp) { | |
935 | case 18: | |
ad80a810 | 936 | temp |= TRANS_DDI_BPC_6; |
dfcef252 PZ |
937 | break; |
938 | case 24: | |
ad80a810 | 939 | temp |= TRANS_DDI_BPC_8; |
dfcef252 PZ |
940 | break; |
941 | case 30: | |
ad80a810 | 942 | temp |= TRANS_DDI_BPC_10; |
dfcef252 PZ |
943 | break; |
944 | case 36: | |
ad80a810 | 945 | temp |= TRANS_DDI_BPC_12; |
dfcef252 PZ |
946 | break; |
947 | default: | |
ad80a810 | 948 | WARN(1, "%d bpp unsupported by transcoder DDI function\n", |
dfcef252 PZ |
949 | intel_crtc->bpp); |
950 | } | |
72662e10 | 951 | |
8d9ddbcb | 952 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
ad80a810 | 953 | temp |= TRANS_DDI_PVSYNC; |
8d9ddbcb | 954 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) |
ad80a810 | 955 | temp |= TRANS_DDI_PHSYNC; |
f63eb7c4 | 956 | |
e6f0bfc4 PZ |
957 | if (cpu_transcoder == TRANSCODER_EDP) { |
958 | switch (pipe) { | |
959 | case PIPE_A: | |
960 | temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; | |
961 | break; | |
962 | case PIPE_B: | |
963 | temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; | |
964 | break; | |
965 | case PIPE_C: | |
966 | temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; | |
967 | break; | |
968 | default: | |
969 | BUG(); | |
970 | break; | |
971 | } | |
972 | } | |
973 | ||
7739c33b PZ |
974 | if (type == INTEL_OUTPUT_HDMI) { |
975 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
8d9ddbcb PZ |
976 | |
977 | if (intel_hdmi->has_hdmi_sink) | |
ad80a810 | 978 | temp |= TRANS_DDI_MODE_SELECT_HDMI; |
8d9ddbcb | 979 | else |
ad80a810 | 980 | temp |= TRANS_DDI_MODE_SELECT_DVI; |
8d9ddbcb | 981 | |
7739c33b | 982 | } else if (type == INTEL_OUTPUT_ANALOG) { |
ad80a810 | 983 | temp |= TRANS_DDI_MODE_SELECT_FDI; |
7739c33b PZ |
984 | |
985 | } else if (type == INTEL_OUTPUT_DISPLAYPORT || | |
986 | type == INTEL_OUTPUT_EDP) { | |
987 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
988 | ||
ad80a810 | 989 | temp |= TRANS_DDI_MODE_SELECT_DP_SST; |
7739c33b PZ |
990 | |
991 | switch (intel_dp->lane_count) { | |
992 | case 1: | |
ad80a810 | 993 | temp |= TRANS_DDI_PORT_WIDTH_X1; |
7739c33b PZ |
994 | break; |
995 | case 2: | |
ad80a810 | 996 | temp |= TRANS_DDI_PORT_WIDTH_X2; |
7739c33b PZ |
997 | break; |
998 | case 4: | |
ad80a810 | 999 | temp |= TRANS_DDI_PORT_WIDTH_X4; |
7739c33b PZ |
1000 | break; |
1001 | default: | |
ad80a810 | 1002 | temp |= TRANS_DDI_PORT_WIDTH_X4; |
7739c33b PZ |
1003 | WARN(1, "Unsupported lane count %d\n", |
1004 | intel_dp->lane_count); | |
1005 | } | |
1006 | ||
8d9ddbcb PZ |
1007 | } else { |
1008 | WARN(1, "Invalid encoder type %d for pipe %d\n", | |
1009 | intel_encoder->type, pipe); | |
1010 | } | |
1011 | ||
ad80a810 | 1012 | I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); |
8d9ddbcb | 1013 | } |
72662e10 | 1014 | |
ad80a810 PZ |
1015 | void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, |
1016 | enum transcoder cpu_transcoder) | |
8d9ddbcb | 1017 | { |
ad80a810 | 1018 | uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
8d9ddbcb PZ |
1019 | uint32_t val = I915_READ(reg); |
1020 | ||
ad80a810 PZ |
1021 | val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK); |
1022 | val |= TRANS_DDI_PORT_NONE; | |
8d9ddbcb | 1023 | I915_WRITE(reg, val); |
72662e10 ED |
1024 | } |
1025 | ||
bcbc889b PZ |
1026 | bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) |
1027 | { | |
1028 | struct drm_device *dev = intel_connector->base.dev; | |
1029 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1030 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
1031 | int type = intel_connector->base.connector_type; | |
1032 | enum port port = intel_ddi_get_encoder_port(intel_encoder); | |
1033 | enum pipe pipe = 0; | |
1034 | enum transcoder cpu_transcoder; | |
1035 | uint32_t tmp; | |
1036 | ||
1037 | if (!intel_encoder->get_hw_state(intel_encoder, &pipe)) | |
1038 | return false; | |
1039 | ||
1040 | if (port == PORT_A) | |
1041 | cpu_transcoder = TRANSCODER_EDP; | |
1042 | else | |
1043 | cpu_transcoder = pipe; | |
1044 | ||
1045 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); | |
1046 | ||
1047 | switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { | |
1048 | case TRANS_DDI_MODE_SELECT_HDMI: | |
1049 | case TRANS_DDI_MODE_SELECT_DVI: | |
1050 | return (type == DRM_MODE_CONNECTOR_HDMIA); | |
1051 | ||
1052 | case TRANS_DDI_MODE_SELECT_DP_SST: | |
1053 | if (type == DRM_MODE_CONNECTOR_eDP) | |
1054 | return true; | |
1055 | case TRANS_DDI_MODE_SELECT_DP_MST: | |
1056 | return (type == DRM_MODE_CONNECTOR_DisplayPort); | |
1057 | ||
1058 | case TRANS_DDI_MODE_SELECT_FDI: | |
1059 | return (type == DRM_MODE_CONNECTOR_VGA); | |
1060 | ||
1061 | default: | |
1062 | return false; | |
1063 | } | |
1064 | } | |
1065 | ||
85234cdc DV |
1066 | bool intel_ddi_get_hw_state(struct intel_encoder *encoder, |
1067 | enum pipe *pipe) | |
1068 | { | |
1069 | struct drm_device *dev = encoder->base.dev; | |
1070 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fe43d3f5 | 1071 | enum port port = intel_ddi_get_encoder_port(encoder); |
85234cdc DV |
1072 | u32 tmp; |
1073 | int i; | |
1074 | ||
fe43d3f5 | 1075 | tmp = I915_READ(DDI_BUF_CTL(port)); |
85234cdc DV |
1076 | |
1077 | if (!(tmp & DDI_BUF_CTL_ENABLE)) | |
1078 | return false; | |
1079 | ||
ad80a810 PZ |
1080 | if (port == PORT_A) { |
1081 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); | |
85234cdc | 1082 | |
ad80a810 PZ |
1083 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { |
1084 | case TRANS_DDI_EDP_INPUT_A_ON: | |
1085 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
1086 | *pipe = PIPE_A; | |
1087 | break; | |
1088 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
1089 | *pipe = PIPE_B; | |
1090 | break; | |
1091 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
1092 | *pipe = PIPE_C; | |
1093 | break; | |
1094 | } | |
1095 | ||
1096 | return true; | |
1097 | } else { | |
1098 | for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) { | |
1099 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(i)); | |
1100 | ||
1101 | if ((tmp & TRANS_DDI_PORT_MASK) | |
1102 | == TRANS_DDI_SELECT_PORT(port)) { | |
1103 | *pipe = i; | |
1104 | return true; | |
1105 | } | |
85234cdc DV |
1106 | } |
1107 | } | |
1108 | ||
fe43d3f5 | 1109 | DRM_DEBUG_KMS("No pipe for ddi port %i found\n", port); |
85234cdc DV |
1110 | |
1111 | return true; | |
1112 | } | |
1113 | ||
6441ab5f PZ |
1114 | static uint32_t intel_ddi_get_crtc_pll(struct drm_i915_private *dev_priv, |
1115 | enum pipe pipe) | |
1116 | { | |
1117 | uint32_t temp, ret; | |
1118 | enum port port; | |
ad80a810 PZ |
1119 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1120 | pipe); | |
6441ab5f PZ |
1121 | int i; |
1122 | ||
ad80a810 PZ |
1123 | if (cpu_transcoder == TRANSCODER_EDP) { |
1124 | port = PORT_A; | |
1125 | } else { | |
1126 | temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); | |
1127 | temp &= TRANS_DDI_PORT_MASK; | |
1128 | ||
1129 | for (i = PORT_B; i <= PORT_E; i++) | |
1130 | if (temp == TRANS_DDI_SELECT_PORT(i)) | |
1131 | port = i; | |
1132 | } | |
6441ab5f PZ |
1133 | |
1134 | ret = I915_READ(PORT_CLK_SEL(port)); | |
1135 | ||
1136 | DRM_DEBUG_KMS("Pipe %c connected to port %c using clock 0x%08x\n", | |
1137 | pipe_name(pipe), port_name(port), ret); | |
1138 | ||
1139 | return ret; | |
1140 | } | |
1141 | ||
1142 | void intel_ddi_setup_hw_pll_state(struct drm_device *dev) | |
1143 | { | |
1144 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1145 | enum pipe pipe; | |
1146 | struct intel_crtc *intel_crtc; | |
1147 | ||
1148 | for_each_pipe(pipe) { | |
1149 | intel_crtc = | |
1150 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
1151 | ||
1152 | if (!intel_crtc->active) | |
1153 | continue; | |
1154 | ||
1155 | intel_crtc->ddi_pll_sel = intel_ddi_get_crtc_pll(dev_priv, | |
1156 | pipe); | |
1157 | ||
1158 | switch (intel_crtc->ddi_pll_sel) { | |
1159 | case PORT_CLK_SEL_SPLL: | |
1160 | dev_priv->ddi_plls.spll_refcount++; | |
1161 | break; | |
1162 | case PORT_CLK_SEL_WRPLL1: | |
1163 | dev_priv->ddi_plls.wrpll1_refcount++; | |
1164 | break; | |
1165 | case PORT_CLK_SEL_WRPLL2: | |
1166 | dev_priv->ddi_plls.wrpll2_refcount++; | |
1167 | break; | |
1168 | } | |
1169 | } | |
1170 | } | |
1171 | ||
fc914639 PZ |
1172 | void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc) |
1173 | { | |
1174 | struct drm_crtc *crtc = &intel_crtc->base; | |
1175 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
1176 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
1177 | enum port port = intel_ddi_get_encoder_port(intel_encoder); | |
bb523fc0 | 1178 | enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder; |
fc914639 | 1179 | |
bb523fc0 PZ |
1180 | if (cpu_transcoder != TRANSCODER_EDP) |
1181 | I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), | |
1182 | TRANS_CLK_SEL_PORT(port)); | |
fc914639 PZ |
1183 | } |
1184 | ||
1185 | void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc) | |
1186 | { | |
1187 | struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; | |
bb523fc0 | 1188 | enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder; |
fc914639 | 1189 | |
bb523fc0 PZ |
1190 | if (cpu_transcoder != TRANSCODER_EDP) |
1191 | I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), | |
1192 | TRANS_CLK_SEL_DISABLED); | |
fc914639 PZ |
1193 | } |
1194 | ||
6441ab5f PZ |
1195 | void intel_ddi_pre_enable(struct intel_encoder *intel_encoder) |
1196 | { | |
c19b0669 PZ |
1197 | struct drm_encoder *encoder = &intel_encoder->base; |
1198 | struct drm_crtc *crtc = encoder->crtc; | |
1199 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; | |
6441ab5f PZ |
1200 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
1201 | enum port port = intel_ddi_get_encoder_port(intel_encoder); | |
82a4d9c0 | 1202 | int type = intel_encoder->type; |
6441ab5f | 1203 | |
82a4d9c0 PZ |
1204 | if (type == INTEL_OUTPUT_EDP) { |
1205 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
1206 | ironlake_edp_panel_vdd_on(intel_dp); | |
1207 | ironlake_edp_panel_on(intel_dp); | |
1208 | ironlake_edp_panel_vdd_off(intel_dp, true); | |
1209 | } | |
6441ab5f | 1210 | |
82a4d9c0 | 1211 | WARN_ON(intel_crtc->ddi_pll_sel == PORT_CLK_SEL_NONE); |
6441ab5f | 1212 | I915_WRITE(PORT_CLK_SEL(port), intel_crtc->ddi_pll_sel); |
c19b0669 | 1213 | |
82a4d9c0 | 1214 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { |
c19b0669 PZ |
1215 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
1216 | ||
1217 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); | |
1218 | intel_dp_start_link_train(intel_dp); | |
1219 | intel_dp_complete_link_train(intel_dp); | |
1220 | } | |
6441ab5f PZ |
1221 | } |
1222 | ||
2886e93f PZ |
1223 | static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, |
1224 | enum port port) | |
1225 | { | |
1226 | uint32_t reg = DDI_BUF_CTL(port); | |
1227 | int i; | |
1228 | ||
1229 | for (i = 0; i < 8; i++) { | |
1230 | udelay(1); | |
1231 | if (I915_READ(reg) & DDI_BUF_IS_IDLE) | |
1232 | return; | |
1233 | } | |
1234 | DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port)); | |
1235 | } | |
1236 | ||
6441ab5f PZ |
1237 | void intel_ddi_post_disable(struct intel_encoder *intel_encoder) |
1238 | { | |
1239 | struct drm_encoder *encoder = &intel_encoder->base; | |
1240 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; | |
1241 | enum port port = intel_ddi_get_encoder_port(intel_encoder); | |
82a4d9c0 | 1242 | int type = intel_encoder->type; |
2886e93f | 1243 | uint32_t val; |
a836bdf9 | 1244 | bool wait = false; |
2886e93f PZ |
1245 | |
1246 | val = I915_READ(DDI_BUF_CTL(port)); | |
1247 | if (val & DDI_BUF_CTL_ENABLE) { | |
1248 | val &= ~DDI_BUF_CTL_ENABLE; | |
1249 | I915_WRITE(DDI_BUF_CTL(port), val); | |
a836bdf9 | 1250 | wait = true; |
2886e93f | 1251 | } |
6441ab5f | 1252 | |
a836bdf9 PZ |
1253 | val = I915_READ(DP_TP_CTL(port)); |
1254 | val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); | |
1255 | val |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
1256 | I915_WRITE(DP_TP_CTL(port), val); | |
1257 | ||
1258 | if (wait) | |
1259 | intel_wait_ddi_buf_idle(dev_priv, port); | |
1260 | ||
82a4d9c0 PZ |
1261 | if (type == INTEL_OUTPUT_EDP) { |
1262 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
1263 | ironlake_edp_panel_vdd_on(intel_dp); | |
1264 | ironlake_edp_panel_off(intel_dp); | |
1265 | } | |
1266 | ||
6441ab5f PZ |
1267 | I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); |
1268 | } | |
1269 | ||
6547fef8 | 1270 | void intel_enable_ddi(struct intel_encoder *intel_encoder) |
72662e10 | 1271 | { |
6547fef8 PZ |
1272 | struct drm_encoder *encoder = &intel_encoder->base; |
1273 | struct drm_device *dev = encoder->dev; | |
72662e10 | 1274 | struct drm_i915_private *dev_priv = dev->dev_private; |
6547fef8 PZ |
1275 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
1276 | int type = intel_encoder->type; | |
72662e10 | 1277 | |
6547fef8 PZ |
1278 | if (type == INTEL_OUTPUT_HDMI) { |
1279 | /* In HDMI/DVI mode, the port width, and swing/emphasis values | |
1280 | * are ignored so nothing special needs to be done besides | |
1281 | * enabling the port. | |
1282 | */ | |
1283 | I915_WRITE(DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE); | |
d6c50ff8 PZ |
1284 | } else if (type == INTEL_OUTPUT_EDP) { |
1285 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
1286 | ||
1287 | ironlake_edp_backlight_on(intel_dp); | |
6547fef8 | 1288 | } |
5ab432ef DV |
1289 | } |
1290 | ||
d6c50ff8 | 1291 | void intel_disable_ddi(struct intel_encoder *intel_encoder) |
5ab432ef | 1292 | { |
d6c50ff8 PZ |
1293 | struct drm_encoder *encoder = &intel_encoder->base; |
1294 | int type = intel_encoder->type; | |
1295 | ||
1296 | if (type == INTEL_OUTPUT_EDP) { | |
1297 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
1298 | ||
1299 | ironlake_edp_backlight_off(intel_dp); | |
1300 | } | |
72662e10 | 1301 | } |
79f689aa | 1302 | |
b8fc2f6a | 1303 | int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv) |
79f689aa PZ |
1304 | { |
1305 | if (I915_READ(HSW_FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
1306 | return 450; | |
1307 | else if ((I915_READ(LCPLL_CTL) & LCPLL_CLK_FREQ_MASK) == | |
1308 | LCPLL_CLK_FREQ_450) | |
1309 | return 450; | |
1310 | else | |
1311 | return 540; | |
1312 | } | |
1313 | ||
1314 | void intel_ddi_pll_init(struct drm_device *dev) | |
1315 | { | |
1316 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1317 | uint32_t val = I915_READ(LCPLL_CTL); | |
1318 | ||
1319 | /* The LCPLL register should be turned on by the BIOS. For now let's | |
1320 | * just check its state and print errors in case something is wrong. | |
1321 | * Don't even try to turn it on. | |
1322 | */ | |
1323 | ||
1324 | DRM_DEBUG_KMS("CDCLK running at %dMHz\n", | |
1325 | intel_ddi_get_cdclk_freq(dev_priv)); | |
1326 | ||
1327 | if (val & LCPLL_CD_SOURCE_FCLK) | |
1328 | DRM_ERROR("CDCLK source is not LCPLL\n"); | |
1329 | ||
1330 | if (val & LCPLL_PLL_DISABLE) | |
1331 | DRM_ERROR("LCPLL is disabled\n"); | |
1332 | } | |
c19b0669 PZ |
1333 | |
1334 | void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder) | |
1335 | { | |
174edf1f PZ |
1336 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
1337 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
c19b0669 | 1338 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
174edf1f | 1339 | enum port port = intel_dig_port->port; |
c19b0669 PZ |
1340 | bool wait; |
1341 | uint32_t val; | |
1342 | ||
1343 | if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) { | |
1344 | val = I915_READ(DDI_BUF_CTL(port)); | |
1345 | if (val & DDI_BUF_CTL_ENABLE) { | |
1346 | val &= ~DDI_BUF_CTL_ENABLE; | |
1347 | I915_WRITE(DDI_BUF_CTL(port), val); | |
1348 | wait = true; | |
1349 | } | |
1350 | ||
1351 | val = I915_READ(DP_TP_CTL(port)); | |
1352 | val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); | |
1353 | val |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
1354 | I915_WRITE(DP_TP_CTL(port), val); | |
1355 | POSTING_READ(DP_TP_CTL(port)); | |
1356 | ||
1357 | if (wait) | |
1358 | intel_wait_ddi_buf_idle(dev_priv, port); | |
1359 | } | |
1360 | ||
1361 | val = DP_TP_CTL_ENABLE | DP_TP_CTL_MODE_SST | | |
1362 | DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE; | |
1363 | if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN) | |
1364 | val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; | |
1365 | I915_WRITE(DP_TP_CTL(port), val); | |
1366 | POSTING_READ(DP_TP_CTL(port)); | |
1367 | ||
1368 | intel_dp->DP |= DDI_BUF_CTL_ENABLE; | |
1369 | I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP); | |
1370 | POSTING_READ(DDI_BUF_CTL(port)); | |
1371 | ||
1372 | udelay(600); | |
1373 | } |