Commit | Line | Data |
---|---|---|
45244b87 ED |
1 | /* |
2 | * Copyright © 2012 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eugeni Dodonov <eugeni.dodonov@intel.com> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "i915_drv.h" | |
29 | #include "intel_drv.h" | |
30 | ||
31 | /* HDMI/DVI modes ignore everything but the last 2 items. So we share | |
32 | * them for both DP and FDI transports, allowing those ports to | |
33 | * automatically adapt to HDMI connections as well | |
34 | */ | |
35 | static const u32 hsw_ddi_translations_dp[] = { | |
36 | 0x00FFFFFF, 0x0006000E, /* DP parameters */ | |
37 | 0x00D75FFF, 0x0005000A, | |
38 | 0x00C30FFF, 0x00040006, | |
39 | 0x80AAAFFF, 0x000B0000, | |
40 | 0x00FFFFFF, 0x0005000A, | |
41 | 0x00D75FFF, 0x000C0004, | |
42 | 0x80C30FFF, 0x000B0000, | |
43 | 0x00FFFFFF, 0x00040006, | |
44 | 0x80D75FFF, 0x000B0000, | |
45244b87 ED |
45 | }; |
46 | ||
47 | static const u32 hsw_ddi_translations_fdi[] = { | |
48 | 0x00FFFFFF, 0x0007000E, /* FDI parameters */ | |
49 | 0x00D75FFF, 0x000F000A, | |
50 | 0x00C30FFF, 0x00060006, | |
51 | 0x00AAAFFF, 0x001E0000, | |
52 | 0x00FFFFFF, 0x000F000A, | |
53 | 0x00D75FFF, 0x00160004, | |
54 | 0x00C30FFF, 0x001E0000, | |
55 | 0x00FFFFFF, 0x00060006, | |
56 | 0x00D75FFF, 0x001E0000, | |
6acab15a PZ |
57 | }; |
58 | ||
59 | static const u32 hsw_ddi_translations_hdmi[] = { | |
60 | /* Idx NT mV diff T mV diff db */ | |
61 | 0x00FFFFFF, 0x0006000E, /* 0: 400 400 0 */ | |
62 | 0x00E79FFF, 0x000E000C, /* 1: 400 500 2 */ | |
63 | 0x00D75FFF, 0x0005000A, /* 2: 400 600 3.5 */ | |
64 | 0x00FFFFFF, 0x0005000A, /* 3: 600 600 0 */ | |
65 | 0x00E79FFF, 0x001D0007, /* 4: 600 750 2 */ | |
66 | 0x00D75FFF, 0x000C0004, /* 5: 600 900 3.5 */ | |
67 | 0x00FFFFFF, 0x00040006, /* 6: 800 800 0 */ | |
68 | 0x80E79FFF, 0x00030002, /* 7: 800 1000 2 */ | |
69 | 0x00FFFFFF, 0x00140005, /* 8: 850 850 0 */ | |
70 | 0x00FFFFFF, 0x000C0004, /* 9: 900 900 0 */ | |
71 | 0x00FFFFFF, 0x001C0003, /* 10: 950 950 0 */ | |
72 | 0x80FFFFFF, 0x00030002, /* 11: 1000 1000 0 */ | |
45244b87 ED |
73 | }; |
74 | ||
300644c7 | 75 | static const u32 bdw_ddi_translations_edp[] = { |
e1b22732 | 76 | 0x00FFFFFF, 0x00000012, /* eDP parameters */ |
300644c7 PZ |
77 | 0x00EBAFFF, 0x00020011, |
78 | 0x00C71FFF, 0x0006000F, | |
9576c27f | 79 | 0x00AAAFFF, 0x000E000A, |
300644c7 PZ |
80 | 0x00FFFFFF, 0x00020011, |
81 | 0x00DB6FFF, 0x0005000F, | |
82 | 0x00BEEFFF, 0x000A000C, | |
83 | 0x00FFFFFF, 0x0005000F, | |
84 | 0x00DB6FFF, 0x000A000C, | |
300644c7 PZ |
85 | 0x00FFFFFF, 0x00140006 /* HDMI parameters 800mV 0dB*/ |
86 | }; | |
87 | ||
e58623cb AR |
88 | static const u32 bdw_ddi_translations_dp[] = { |
89 | 0x00FFFFFF, 0x0007000E, /* DP parameters */ | |
90 | 0x00D75FFF, 0x000E000A, | |
91 | 0x00BEFFFF, 0x00140006, | |
9576c27f | 92 | 0x80B2CFFF, 0x001B0002, |
e58623cb AR |
93 | 0x00FFFFFF, 0x000E000A, |
94 | 0x00D75FFF, 0x00180004, | |
95 | 0x80CB2FFF, 0x001B0002, | |
96 | 0x00F7DFFF, 0x00180004, | |
97 | 0x80D75FFF, 0x001B0002, | |
e58623cb AR |
98 | 0x00FFFFFF, 0x00140006 /* HDMI parameters 800mV 0dB*/ |
99 | }; | |
100 | ||
101 | static const u32 bdw_ddi_translations_fdi[] = { | |
102 | 0x00FFFFFF, 0x0001000E, /* FDI parameters */ | |
103 | 0x00D75FFF, 0x0004000A, | |
104 | 0x00C30FFF, 0x00070006, | |
105 | 0x00AAAFFF, 0x000C0000, | |
106 | 0x00FFFFFF, 0x0004000A, | |
107 | 0x00D75FFF, 0x00090004, | |
108 | 0x00C30FFF, 0x000C0000, | |
109 | 0x00FFFFFF, 0x00070006, | |
110 | 0x00D75FFF, 0x000C0000, | |
111 | 0x00FFFFFF, 0x00140006 /* HDMI parameters 800mV 0dB*/ | |
112 | }; | |
113 | ||
20f4dbe4 | 114 | enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder) |
fc914639 | 115 | { |
0bdee30e | 116 | struct drm_encoder *encoder = &intel_encoder->base; |
fc914639 PZ |
117 | int type = intel_encoder->type; |
118 | ||
174edf1f | 119 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || |
00c09d70 | 120 | type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) { |
174edf1f PZ |
121 | struct intel_digital_port *intel_dig_port = |
122 | enc_to_dig_port(encoder); | |
123 | return intel_dig_port->port; | |
0bdee30e | 124 | |
fc914639 PZ |
125 | } else if (type == INTEL_OUTPUT_ANALOG) { |
126 | return PORT_E; | |
0bdee30e | 127 | |
fc914639 PZ |
128 | } else { |
129 | DRM_ERROR("Invalid DDI encoder type %d\n", type); | |
130 | BUG(); | |
131 | } | |
132 | } | |
133 | ||
e58623cb AR |
134 | /* |
135 | * Starting with Haswell, DDI port buffers must be programmed with correct | |
136 | * values in advance. The buffer values are different for FDI and DP modes, | |
45244b87 ED |
137 | * but the HDMI/DVI fields are shared among those. So we program the DDI |
138 | * in either FDI or DP modes only, as HDMI connections will work with both | |
139 | * of those | |
140 | */ | |
ad8d270c | 141 | static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port) |
45244b87 ED |
142 | { |
143 | struct drm_i915_private *dev_priv = dev->dev_private; | |
144 | u32 reg; | |
145 | int i; | |
6acab15a | 146 | int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift; |
e58623cb AR |
147 | const u32 *ddi_translations_fdi; |
148 | const u32 *ddi_translations_dp; | |
300644c7 | 149 | const u32 *ddi_translations_edp; |
e58623cb AR |
150 | const u32 *ddi_translations; |
151 | ||
152 | if (IS_BROADWELL(dev)) { | |
153 | ddi_translations_fdi = bdw_ddi_translations_fdi; | |
154 | ddi_translations_dp = bdw_ddi_translations_dp; | |
300644c7 | 155 | ddi_translations_edp = bdw_ddi_translations_edp; |
e58623cb AR |
156 | } else if (IS_HASWELL(dev)) { |
157 | ddi_translations_fdi = hsw_ddi_translations_fdi; | |
158 | ddi_translations_dp = hsw_ddi_translations_dp; | |
300644c7 | 159 | ddi_translations_edp = hsw_ddi_translations_dp; |
e58623cb AR |
160 | } else { |
161 | WARN(1, "ddi translation table missing\n"); | |
300644c7 | 162 | ddi_translations_edp = bdw_ddi_translations_dp; |
e58623cb AR |
163 | ddi_translations_fdi = bdw_ddi_translations_fdi; |
164 | ddi_translations_dp = bdw_ddi_translations_dp; | |
165 | } | |
166 | ||
300644c7 PZ |
167 | switch (port) { |
168 | case PORT_A: | |
169 | ddi_translations = ddi_translations_edp; | |
170 | break; | |
171 | case PORT_B: | |
172 | case PORT_C: | |
300644c7 PZ |
173 | ddi_translations = ddi_translations_dp; |
174 | break; | |
77d8d009 | 175 | case PORT_D: |
5d8a7752 | 176 | if (intel_dp_is_edp(dev, PORT_D)) |
77d8d009 PZ |
177 | ddi_translations = ddi_translations_edp; |
178 | else | |
179 | ddi_translations = ddi_translations_dp; | |
180 | break; | |
300644c7 PZ |
181 | case PORT_E: |
182 | ddi_translations = ddi_translations_fdi; | |
183 | break; | |
184 | default: | |
185 | BUG(); | |
186 | } | |
45244b87 | 187 | |
f72d19f0 PZ |
188 | for (i = 0, reg = DDI_BUF_TRANS(port); |
189 | i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) { | |
45244b87 ED |
190 | I915_WRITE(reg, ddi_translations[i]); |
191 | reg += 4; | |
192 | } | |
6acab15a PZ |
193 | /* Entry 9 is for HDMI: */ |
194 | for (i = 0; i < 2; i++) { | |
195 | I915_WRITE(reg, hsw_ddi_translations_hdmi[hdmi_level * 2 + i]); | |
196 | reg += 4; | |
197 | } | |
45244b87 ED |
198 | } |
199 | ||
200 | /* Program DDI buffers translations for DP. By default, program ports A-D in DP | |
201 | * mode and port E for FDI. | |
202 | */ | |
203 | void intel_prepare_ddi(struct drm_device *dev) | |
204 | { | |
205 | int port; | |
206 | ||
0d536cb4 PZ |
207 | if (!HAS_DDI(dev)) |
208 | return; | |
45244b87 | 209 | |
ad8d270c PZ |
210 | for (port = PORT_A; port <= PORT_E; port++) |
211 | intel_prepare_ddi_buffers(dev, port); | |
45244b87 | 212 | } |
c82e4d26 ED |
213 | |
214 | static const long hsw_ddi_buf_ctl_values[] = { | |
215 | DDI_BUF_EMP_400MV_0DB_HSW, | |
216 | DDI_BUF_EMP_400MV_3_5DB_HSW, | |
217 | DDI_BUF_EMP_400MV_6DB_HSW, | |
218 | DDI_BUF_EMP_400MV_9_5DB_HSW, | |
219 | DDI_BUF_EMP_600MV_0DB_HSW, | |
220 | DDI_BUF_EMP_600MV_3_5DB_HSW, | |
221 | DDI_BUF_EMP_600MV_6DB_HSW, | |
222 | DDI_BUF_EMP_800MV_0DB_HSW, | |
223 | DDI_BUF_EMP_800MV_3_5DB_HSW | |
224 | }; | |
225 | ||
248138b5 PZ |
226 | static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, |
227 | enum port port) | |
228 | { | |
229 | uint32_t reg = DDI_BUF_CTL(port); | |
230 | int i; | |
231 | ||
232 | for (i = 0; i < 8; i++) { | |
233 | udelay(1); | |
234 | if (I915_READ(reg) & DDI_BUF_IS_IDLE) | |
235 | return; | |
236 | } | |
237 | DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port)); | |
238 | } | |
c82e4d26 ED |
239 | |
240 | /* Starting with Haswell, different DDI ports can work in FDI mode for | |
241 | * connection to the PCH-located connectors. For this, it is necessary to train | |
242 | * both the DDI port and PCH receiver for the desired DDI buffer settings. | |
243 | * | |
244 | * The recommended port to work in FDI mode is DDI E, which we use here. Also, | |
245 | * please note that when FDI mode is active on DDI E, it shares 2 lines with | |
246 | * DDI A (which is used for eDP) | |
247 | */ | |
248 | ||
249 | void hsw_fdi_link_train(struct drm_crtc *crtc) | |
250 | { | |
251 | struct drm_device *dev = crtc->dev; | |
252 | struct drm_i915_private *dev_priv = dev->dev_private; | |
253 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
04945641 | 254 | u32 temp, i, rx_ctl_val; |
c82e4d26 | 255 | |
04945641 PZ |
256 | /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the |
257 | * mode set "sequence for CRT port" document: | |
258 | * - TP1 to TP2 time with the default value | |
259 | * - FDI delay to 90h | |
8693a824 DL |
260 | * |
261 | * WaFDIAutoLinkSetTimingOverrride:hsw | |
04945641 PZ |
262 | */ |
263 | I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) | | |
264 | FDI_RX_PWRDN_LANE0_VAL(2) | | |
265 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
266 | ||
267 | /* Enable the PCH Receiver FDI PLL */ | |
3e68320e | 268 | rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE | |
33d29b14 | 269 | FDI_RX_PLL_ENABLE | |
627eb5a3 | 270 | FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); |
04945641 PZ |
271 | I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); |
272 | POSTING_READ(_FDI_RXA_CTL); | |
273 | udelay(220); | |
274 | ||
275 | /* Switch from Rawclk to PCDclk */ | |
276 | rx_ctl_val |= FDI_PCDCLK; | |
277 | I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); | |
278 | ||
279 | /* Configure Port Clock Select */ | |
280 | I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->ddi_pll_sel); | |
281 | ||
282 | /* Start the training iterating through available voltages and emphasis, | |
283 | * testing each value twice. */ | |
284 | for (i = 0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values) * 2; i++) { | |
c82e4d26 ED |
285 | /* Configure DP_TP_CTL with auto-training */ |
286 | I915_WRITE(DP_TP_CTL(PORT_E), | |
287 | DP_TP_CTL_FDI_AUTOTRAIN | | |
288 | DP_TP_CTL_ENHANCED_FRAME_ENABLE | | |
289 | DP_TP_CTL_LINK_TRAIN_PAT1 | | |
290 | DP_TP_CTL_ENABLE); | |
291 | ||
876a8cdf DL |
292 | /* Configure and enable DDI_BUF_CTL for DDI E with next voltage. |
293 | * DDI E does not support port reversal, the functionality is | |
294 | * achieved on the PCH side in FDI_RX_CTL, so no need to set the | |
295 | * port reversal bit */ | |
c82e4d26 | 296 | I915_WRITE(DDI_BUF_CTL(PORT_E), |
04945641 | 297 | DDI_BUF_CTL_ENABLE | |
33d29b14 | 298 | ((intel_crtc->config.fdi_lanes - 1) << 1) | |
04945641 PZ |
299 | hsw_ddi_buf_ctl_values[i / 2]); |
300 | POSTING_READ(DDI_BUF_CTL(PORT_E)); | |
c82e4d26 ED |
301 | |
302 | udelay(600); | |
303 | ||
04945641 PZ |
304 | /* Program PCH FDI Receiver TU */ |
305 | I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64)); | |
306 | ||
307 | /* Enable PCH FDI Receiver with auto-training */ | |
308 | rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO; | |
309 | I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); | |
310 | POSTING_READ(_FDI_RXA_CTL); | |
311 | ||
312 | /* Wait for FDI receiver lane calibration */ | |
313 | udelay(30); | |
314 | ||
315 | /* Unset FDI_RX_MISC pwrdn lanes */ | |
316 | temp = I915_READ(_FDI_RXA_MISC); | |
317 | temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); | |
318 | I915_WRITE(_FDI_RXA_MISC, temp); | |
319 | POSTING_READ(_FDI_RXA_MISC); | |
320 | ||
321 | /* Wait for FDI auto training time */ | |
322 | udelay(5); | |
c82e4d26 ED |
323 | |
324 | temp = I915_READ(DP_TP_STATUS(PORT_E)); | |
325 | if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) { | |
04945641 | 326 | DRM_DEBUG_KMS("FDI link training done on step %d\n", i); |
c82e4d26 ED |
327 | |
328 | /* Enable normal pixel sending for FDI */ | |
329 | I915_WRITE(DP_TP_CTL(PORT_E), | |
04945641 PZ |
330 | DP_TP_CTL_FDI_AUTOTRAIN | |
331 | DP_TP_CTL_LINK_TRAIN_NORMAL | | |
332 | DP_TP_CTL_ENHANCED_FRAME_ENABLE | | |
333 | DP_TP_CTL_ENABLE); | |
c82e4d26 | 334 | |
04945641 | 335 | return; |
c82e4d26 | 336 | } |
04945641 | 337 | |
248138b5 PZ |
338 | temp = I915_READ(DDI_BUF_CTL(PORT_E)); |
339 | temp &= ~DDI_BUF_CTL_ENABLE; | |
340 | I915_WRITE(DDI_BUF_CTL(PORT_E), temp); | |
341 | POSTING_READ(DDI_BUF_CTL(PORT_E)); | |
342 | ||
04945641 | 343 | /* Disable DP_TP_CTL and FDI_RX_CTL and retry */ |
248138b5 PZ |
344 | temp = I915_READ(DP_TP_CTL(PORT_E)); |
345 | temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); | |
346 | temp |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
347 | I915_WRITE(DP_TP_CTL(PORT_E), temp); | |
348 | POSTING_READ(DP_TP_CTL(PORT_E)); | |
349 | ||
350 | intel_wait_ddi_buf_idle(dev_priv, PORT_E); | |
04945641 PZ |
351 | |
352 | rx_ctl_val &= ~FDI_RX_ENABLE; | |
353 | I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); | |
248138b5 | 354 | POSTING_READ(_FDI_RXA_CTL); |
04945641 PZ |
355 | |
356 | /* Reset FDI_RX_MISC pwrdn lanes */ | |
357 | temp = I915_READ(_FDI_RXA_MISC); | |
358 | temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); | |
359 | temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); | |
360 | I915_WRITE(_FDI_RXA_MISC, temp); | |
248138b5 | 361 | POSTING_READ(_FDI_RXA_MISC); |
c82e4d26 ED |
362 | } |
363 | ||
04945641 | 364 | DRM_ERROR("FDI link training failed!\n"); |
c82e4d26 | 365 | } |
0e72a5b5 | 366 | |
8d9ddbcb PZ |
367 | static struct intel_encoder * |
368 | intel_ddi_get_crtc_encoder(struct drm_crtc *crtc) | |
369 | { | |
370 | struct drm_device *dev = crtc->dev; | |
371 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
372 | struct intel_encoder *intel_encoder, *ret = NULL; | |
373 | int num_encoders = 0; | |
374 | ||
375 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { | |
376 | ret = intel_encoder; | |
377 | num_encoders++; | |
378 | } | |
379 | ||
380 | if (num_encoders != 1) | |
84f44ce7 VS |
381 | WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders, |
382 | pipe_name(intel_crtc->pipe)); | |
8d9ddbcb PZ |
383 | |
384 | BUG_ON(ret == NULL); | |
385 | return ret; | |
386 | } | |
387 | ||
6441ab5f PZ |
388 | void intel_ddi_put_crtc_pll(struct drm_crtc *crtc) |
389 | { | |
390 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
391 | struct intel_ddi_plls *plls = &dev_priv->ddi_plls; | |
392 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
393 | uint32_t val; | |
394 | ||
395 | switch (intel_crtc->ddi_pll_sel) { | |
396 | case PORT_CLK_SEL_SPLL: | |
397 | plls->spll_refcount--; | |
398 | if (plls->spll_refcount == 0) { | |
399 | DRM_DEBUG_KMS("Disabling SPLL\n"); | |
400 | val = I915_READ(SPLL_CTL); | |
401 | WARN_ON(!(val & SPLL_PLL_ENABLE)); | |
402 | I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE); | |
403 | POSTING_READ(SPLL_CTL); | |
404 | } | |
405 | break; | |
406 | case PORT_CLK_SEL_WRPLL1: | |
407 | plls->wrpll1_refcount--; | |
408 | if (plls->wrpll1_refcount == 0) { | |
409 | DRM_DEBUG_KMS("Disabling WRPLL 1\n"); | |
410 | val = I915_READ(WRPLL_CTL1); | |
411 | WARN_ON(!(val & WRPLL_PLL_ENABLE)); | |
412 | I915_WRITE(WRPLL_CTL1, val & ~WRPLL_PLL_ENABLE); | |
413 | POSTING_READ(WRPLL_CTL1); | |
414 | } | |
415 | break; | |
416 | case PORT_CLK_SEL_WRPLL2: | |
417 | plls->wrpll2_refcount--; | |
418 | if (plls->wrpll2_refcount == 0) { | |
419 | DRM_DEBUG_KMS("Disabling WRPLL 2\n"); | |
420 | val = I915_READ(WRPLL_CTL2); | |
421 | WARN_ON(!(val & WRPLL_PLL_ENABLE)); | |
422 | I915_WRITE(WRPLL_CTL2, val & ~WRPLL_PLL_ENABLE); | |
423 | POSTING_READ(WRPLL_CTL2); | |
424 | } | |
425 | break; | |
426 | } | |
427 | ||
428 | WARN(plls->spll_refcount < 0, "Invalid SPLL refcount\n"); | |
429 | WARN(plls->wrpll1_refcount < 0, "Invalid WRPLL1 refcount\n"); | |
430 | WARN(plls->wrpll2_refcount < 0, "Invalid WRPLL2 refcount\n"); | |
431 | ||
432 | intel_crtc->ddi_pll_sel = PORT_CLK_SEL_NONE; | |
433 | } | |
434 | ||
1c0b85c5 DL |
435 | #define LC_FREQ 2700 |
436 | #define LC_FREQ_2K (LC_FREQ * 2000) | |
437 | ||
438 | #define P_MIN 2 | |
439 | #define P_MAX 64 | |
440 | #define P_INC 2 | |
441 | ||
442 | /* Constraints for PLL good behavior */ | |
443 | #define REF_MIN 48 | |
444 | #define REF_MAX 400 | |
445 | #define VCO_MIN 2400 | |
446 | #define VCO_MAX 4800 | |
447 | ||
448 | #define ABS_DIFF(a, b) ((a > b) ? (a - b) : (b - a)) | |
449 | ||
450 | struct wrpll_rnp { | |
451 | unsigned p, n2, r2; | |
452 | }; | |
453 | ||
454 | static unsigned wrpll_get_budget_for_freq(int clock) | |
6441ab5f | 455 | { |
1c0b85c5 DL |
456 | unsigned budget; |
457 | ||
458 | switch (clock) { | |
459 | case 25175000: | |
460 | case 25200000: | |
461 | case 27000000: | |
462 | case 27027000: | |
463 | case 37762500: | |
464 | case 37800000: | |
465 | case 40500000: | |
466 | case 40541000: | |
467 | case 54000000: | |
468 | case 54054000: | |
469 | case 59341000: | |
470 | case 59400000: | |
471 | case 72000000: | |
472 | case 74176000: | |
473 | case 74250000: | |
474 | case 81000000: | |
475 | case 81081000: | |
476 | case 89012000: | |
477 | case 89100000: | |
478 | case 108000000: | |
479 | case 108108000: | |
480 | case 111264000: | |
481 | case 111375000: | |
482 | case 148352000: | |
483 | case 148500000: | |
484 | case 162000000: | |
485 | case 162162000: | |
486 | case 222525000: | |
487 | case 222750000: | |
488 | case 296703000: | |
489 | case 297000000: | |
490 | budget = 0; | |
491 | break; | |
492 | case 233500000: | |
493 | case 245250000: | |
494 | case 247750000: | |
495 | case 253250000: | |
496 | case 298000000: | |
497 | budget = 1500; | |
498 | break; | |
499 | case 169128000: | |
500 | case 169500000: | |
501 | case 179500000: | |
502 | case 202000000: | |
503 | budget = 2000; | |
504 | break; | |
505 | case 256250000: | |
506 | case 262500000: | |
507 | case 270000000: | |
508 | case 272500000: | |
509 | case 273750000: | |
510 | case 280750000: | |
511 | case 281250000: | |
512 | case 286000000: | |
513 | case 291750000: | |
514 | budget = 4000; | |
515 | break; | |
516 | case 267250000: | |
517 | case 268500000: | |
518 | budget = 5000; | |
519 | break; | |
520 | default: | |
521 | budget = 1000; | |
522 | break; | |
523 | } | |
6441ab5f | 524 | |
1c0b85c5 DL |
525 | return budget; |
526 | } | |
527 | ||
528 | static void wrpll_update_rnp(uint64_t freq2k, unsigned budget, | |
529 | unsigned r2, unsigned n2, unsigned p, | |
530 | struct wrpll_rnp *best) | |
531 | { | |
532 | uint64_t a, b, c, d, diff, diff_best; | |
6441ab5f | 533 | |
1c0b85c5 DL |
534 | /* No best (r,n,p) yet */ |
535 | if (best->p == 0) { | |
536 | best->p = p; | |
537 | best->n2 = n2; | |
538 | best->r2 = r2; | |
539 | return; | |
540 | } | |
6441ab5f | 541 | |
1c0b85c5 DL |
542 | /* |
543 | * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to | |
544 | * freq2k. | |
545 | * | |
546 | * delta = 1e6 * | |
547 | * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) / | |
548 | * freq2k; | |
549 | * | |
550 | * and we would like delta <= budget. | |
551 | * | |
552 | * If the discrepancy is above the PPM-based budget, always prefer to | |
553 | * improve upon the previous solution. However, if you're within the | |
554 | * budget, try to maximize Ref * VCO, that is N / (P * R^2). | |
555 | */ | |
556 | a = freq2k * budget * p * r2; | |
557 | b = freq2k * budget * best->p * best->r2; | |
558 | diff = ABS_DIFF((freq2k * p * r2), (LC_FREQ_2K * n2)); | |
559 | diff_best = ABS_DIFF((freq2k * best->p * best->r2), | |
560 | (LC_FREQ_2K * best->n2)); | |
561 | c = 1000000 * diff; | |
562 | d = 1000000 * diff_best; | |
563 | ||
564 | if (a < c && b < d) { | |
565 | /* If both are above the budget, pick the closer */ | |
566 | if (best->p * best->r2 * diff < p * r2 * diff_best) { | |
567 | best->p = p; | |
568 | best->n2 = n2; | |
569 | best->r2 = r2; | |
570 | } | |
571 | } else if (a >= c && b < d) { | |
572 | /* If A is below the threshold but B is above it? Update. */ | |
573 | best->p = p; | |
574 | best->n2 = n2; | |
575 | best->r2 = r2; | |
576 | } else if (a >= c && b >= d) { | |
577 | /* Both are below the limit, so pick the higher n2/(r2*r2) */ | |
578 | if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) { | |
579 | best->p = p; | |
580 | best->n2 = n2; | |
581 | best->r2 = r2; | |
582 | } | |
583 | } | |
584 | /* Otherwise a < c && b >= d, do nothing */ | |
585 | } | |
586 | ||
11578553 JB |
587 | static int intel_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv, |
588 | int reg) | |
589 | { | |
590 | int refclk = LC_FREQ; | |
591 | int n, p, r; | |
592 | u32 wrpll; | |
593 | ||
594 | wrpll = I915_READ(reg); | |
595 | switch (wrpll & SPLL_PLL_REF_MASK) { | |
596 | case SPLL_PLL_SSC: | |
597 | case SPLL_PLL_NON_SSC: | |
598 | /* | |
599 | * We could calculate spread here, but our checking | |
600 | * code only cares about 5% accuracy, and spread is a max of | |
601 | * 0.5% downspread. | |
602 | */ | |
603 | refclk = 135; | |
604 | break; | |
605 | case SPLL_PLL_LCPLL: | |
606 | refclk = LC_FREQ; | |
607 | break; | |
608 | default: | |
609 | WARN(1, "bad wrpll refclk\n"); | |
610 | return 0; | |
611 | } | |
612 | ||
613 | r = wrpll & WRPLL_DIVIDER_REF_MASK; | |
614 | p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT; | |
615 | n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT; | |
616 | ||
20f0ec16 JB |
617 | /* Convert to KHz, p & r have a fixed point portion */ |
618 | return (refclk * n * 100) / (p * r); | |
11578553 JB |
619 | } |
620 | ||
621 | static void intel_ddi_clock_get(struct intel_encoder *encoder, | |
622 | struct intel_crtc_config *pipe_config) | |
623 | { | |
624 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
625 | enum port port = intel_ddi_get_encoder_port(encoder); | |
626 | int link_clock = 0; | |
627 | u32 val, pll; | |
628 | ||
629 | val = I915_READ(PORT_CLK_SEL(port)); | |
630 | switch (val & PORT_CLK_SEL_MASK) { | |
631 | case PORT_CLK_SEL_LCPLL_810: | |
632 | link_clock = 81000; | |
633 | break; | |
634 | case PORT_CLK_SEL_LCPLL_1350: | |
635 | link_clock = 135000; | |
636 | break; | |
637 | case PORT_CLK_SEL_LCPLL_2700: | |
638 | link_clock = 270000; | |
639 | break; | |
640 | case PORT_CLK_SEL_WRPLL1: | |
641 | link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1); | |
642 | break; | |
643 | case PORT_CLK_SEL_WRPLL2: | |
644 | link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2); | |
645 | break; | |
646 | case PORT_CLK_SEL_SPLL: | |
647 | pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK; | |
648 | if (pll == SPLL_PLL_FREQ_810MHz) | |
649 | link_clock = 81000; | |
650 | else if (pll == SPLL_PLL_FREQ_1350MHz) | |
651 | link_clock = 135000; | |
652 | else if (pll == SPLL_PLL_FREQ_2700MHz) | |
653 | link_clock = 270000; | |
654 | else { | |
655 | WARN(1, "bad spll freq\n"); | |
656 | return; | |
657 | } | |
658 | break; | |
659 | default: | |
660 | WARN(1, "bad port clock sel\n"); | |
661 | return; | |
662 | } | |
663 | ||
664 | pipe_config->port_clock = link_clock * 2; | |
665 | ||
666 | if (pipe_config->has_pch_encoder) | |
667 | pipe_config->adjusted_mode.crtc_clock = | |
668 | intel_dotclock_calculate(pipe_config->port_clock, | |
669 | &pipe_config->fdi_m_n); | |
670 | else if (pipe_config->has_dp_encoder) | |
671 | pipe_config->adjusted_mode.crtc_clock = | |
672 | intel_dotclock_calculate(pipe_config->port_clock, | |
673 | &pipe_config->dp_m_n); | |
674 | else | |
675 | pipe_config->adjusted_mode.crtc_clock = pipe_config->port_clock; | |
676 | } | |
677 | ||
1c0b85c5 DL |
678 | static void |
679 | intel_ddi_calculate_wrpll(int clock /* in Hz */, | |
680 | unsigned *r2_out, unsigned *n2_out, unsigned *p_out) | |
681 | { | |
682 | uint64_t freq2k; | |
683 | unsigned p, n2, r2; | |
684 | struct wrpll_rnp best = { 0, 0, 0 }; | |
685 | unsigned budget; | |
686 | ||
687 | freq2k = clock / 100; | |
688 | ||
689 | budget = wrpll_get_budget_for_freq(clock); | |
690 | ||
691 | /* Special case handling for 540 pixel clock: bypass WR PLL entirely | |
692 | * and directly pass the LC PLL to it. */ | |
693 | if (freq2k == 5400000) { | |
694 | *n2_out = 2; | |
695 | *p_out = 1; | |
696 | *r2_out = 2; | |
697 | return; | |
698 | } | |
699 | ||
700 | /* | |
701 | * Ref = LC_FREQ / R, where Ref is the actual reference input seen by | |
702 | * the WR PLL. | |
703 | * | |
704 | * We want R so that REF_MIN <= Ref <= REF_MAX. | |
705 | * Injecting R2 = 2 * R gives: | |
706 | * REF_MAX * r2 > LC_FREQ * 2 and | |
707 | * REF_MIN * r2 < LC_FREQ * 2 | |
708 | * | |
709 | * Which means the desired boundaries for r2 are: | |
710 | * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN | |
711 | * | |
712 | */ | |
713 | for (r2 = LC_FREQ * 2 / REF_MAX + 1; | |
714 | r2 <= LC_FREQ * 2 / REF_MIN; | |
715 | r2++) { | |
716 | ||
717 | /* | |
718 | * VCO = N * Ref, that is: VCO = N * LC_FREQ / R | |
719 | * | |
720 | * Once again we want VCO_MIN <= VCO <= VCO_MAX. | |
721 | * Injecting R2 = 2 * R and N2 = 2 * N, we get: | |
722 | * VCO_MAX * r2 > n2 * LC_FREQ and | |
723 | * VCO_MIN * r2 < n2 * LC_FREQ) | |
724 | * | |
725 | * Which means the desired boundaries for n2 are: | |
726 | * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ | |
727 | */ | |
728 | for (n2 = VCO_MIN * r2 / LC_FREQ + 1; | |
729 | n2 <= VCO_MAX * r2 / LC_FREQ; | |
730 | n2++) { | |
731 | ||
732 | for (p = P_MIN; p <= P_MAX; p += P_INC) | |
733 | wrpll_update_rnp(freq2k, budget, | |
734 | r2, n2, p, &best); | |
735 | } | |
736 | } | |
6441ab5f | 737 | |
1c0b85c5 DL |
738 | *n2_out = best.n2; |
739 | *p_out = best.p; | |
740 | *r2_out = best.r2; | |
6441ab5f PZ |
741 | } |
742 | ||
566b734a PZ |
743 | /* |
744 | * Tries to find a PLL for the CRTC. If it finds, it increases the refcount and | |
745 | * stores it in intel_crtc->ddi_pll_sel, so other mode sets won't be able to | |
746 | * steal the selected PLL. You need to call intel_ddi_pll_enable to actually | |
747 | * enable the PLL. | |
748 | */ | |
749 | bool intel_ddi_pll_select(struct intel_crtc *intel_crtc) | |
6441ab5f | 750 | { |
566b734a | 751 | struct drm_crtc *crtc = &intel_crtc->base; |
6441ab5f | 752 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); |
068759bd | 753 | struct drm_encoder *encoder = &intel_encoder->base; |
6441ab5f PZ |
754 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
755 | struct intel_ddi_plls *plls = &dev_priv->ddi_plls; | |
756 | int type = intel_encoder->type; | |
757 | enum pipe pipe = intel_crtc->pipe; | |
ff9a6750 | 758 | int clock = intel_crtc->config.port_clock; |
6441ab5f | 759 | |
6441ab5f PZ |
760 | intel_ddi_put_crtc_pll(crtc); |
761 | ||
068759bd PZ |
762 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { |
763 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
764 | ||
765 | switch (intel_dp->link_bw) { | |
766 | case DP_LINK_BW_1_62: | |
767 | intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810; | |
768 | break; | |
769 | case DP_LINK_BW_2_7: | |
770 | intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350; | |
771 | break; | |
772 | case DP_LINK_BW_5_4: | |
773 | intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700; | |
774 | break; | |
775 | default: | |
776 | DRM_ERROR("Link bandwidth %d unsupported\n", | |
777 | intel_dp->link_bw); | |
778 | return false; | |
779 | } | |
780 | ||
068759bd | 781 | } else if (type == INTEL_OUTPUT_HDMI) { |
566b734a | 782 | uint32_t reg, val; |
1c0b85c5 | 783 | unsigned p, n2, r2; |
6441ab5f | 784 | |
0694001b PZ |
785 | intel_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p); |
786 | ||
787 | val = WRPLL_PLL_ENABLE | WRPLL_PLL_SELECT_LCPLL_2700 | | |
788 | WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) | | |
789 | WRPLL_DIVIDER_POST(p); | |
790 | ||
791 | if (val == I915_READ(WRPLL_CTL1)) { | |
792 | DRM_DEBUG_KMS("Reusing WRPLL 1 on pipe %c\n", | |
793 | pipe_name(pipe)); | |
794 | reg = WRPLL_CTL1; | |
795 | } else if (val == I915_READ(WRPLL_CTL2)) { | |
796 | DRM_DEBUG_KMS("Reusing WRPLL 2 on pipe %c\n", | |
797 | pipe_name(pipe)); | |
798 | reg = WRPLL_CTL2; | |
799 | } else if (plls->wrpll1_refcount == 0) { | |
6441ab5f PZ |
800 | DRM_DEBUG_KMS("Using WRPLL 1 on pipe %c\n", |
801 | pipe_name(pipe)); | |
6441ab5f | 802 | reg = WRPLL_CTL1; |
6441ab5f PZ |
803 | } else if (plls->wrpll2_refcount == 0) { |
804 | DRM_DEBUG_KMS("Using WRPLL 2 on pipe %c\n", | |
805 | pipe_name(pipe)); | |
6441ab5f | 806 | reg = WRPLL_CTL2; |
6441ab5f PZ |
807 | } else { |
808 | DRM_ERROR("No WRPLLs available!\n"); | |
809 | return false; | |
810 | } | |
811 | ||
566b734a PZ |
812 | DRM_DEBUG_KMS("WRPLL: %dKHz refresh rate with p=%d, n2=%d r2=%d\n", |
813 | clock, p, n2, r2); | |
814 | ||
0694001b PZ |
815 | if (reg == WRPLL_CTL1) { |
816 | plls->wrpll1_refcount++; | |
817 | intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL1; | |
818 | } else { | |
819 | plls->wrpll2_refcount++; | |
820 | intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL2; | |
821 | } | |
6441ab5f PZ |
822 | |
823 | } else if (type == INTEL_OUTPUT_ANALOG) { | |
824 | if (plls->spll_refcount == 0) { | |
825 | DRM_DEBUG_KMS("Using SPLL on pipe %c\n", | |
826 | pipe_name(pipe)); | |
827 | plls->spll_refcount++; | |
6441ab5f | 828 | intel_crtc->ddi_pll_sel = PORT_CLK_SEL_SPLL; |
00037c2e DL |
829 | } else { |
830 | DRM_ERROR("SPLL already in use\n"); | |
831 | return false; | |
6441ab5f PZ |
832 | } |
833 | ||
6441ab5f PZ |
834 | } else { |
835 | WARN(1, "Invalid DDI encoder type %d\n", type); | |
836 | return false; | |
837 | } | |
838 | ||
6441ab5f PZ |
839 | return true; |
840 | } | |
841 | ||
566b734a PZ |
842 | /* |
843 | * To be called after intel_ddi_pll_select(). That one selects the PLL to be | |
844 | * used, this one actually enables the PLL. | |
845 | */ | |
846 | void intel_ddi_pll_enable(struct intel_crtc *crtc) | |
847 | { | |
848 | struct drm_device *dev = crtc->base.dev; | |
849 | struct drm_i915_private *dev_priv = dev->dev_private; | |
850 | struct intel_ddi_plls *plls = &dev_priv->ddi_plls; | |
851 | int clock = crtc->config.port_clock; | |
852 | uint32_t reg, cur_val, new_val; | |
853 | int refcount; | |
854 | const char *pll_name; | |
855 | uint32_t enable_bit = (1 << 31); | |
856 | unsigned int p, n2, r2; | |
857 | ||
858 | BUILD_BUG_ON(enable_bit != SPLL_PLL_ENABLE); | |
859 | BUILD_BUG_ON(enable_bit != WRPLL_PLL_ENABLE); | |
860 | ||
861 | switch (crtc->ddi_pll_sel) { | |
862 | case PORT_CLK_SEL_LCPLL_2700: | |
863 | case PORT_CLK_SEL_LCPLL_1350: | |
864 | case PORT_CLK_SEL_LCPLL_810: | |
865 | /* | |
866 | * LCPLL should always be enabled at this point of the mode set | |
867 | * sequence, so nothing to do. | |
868 | */ | |
869 | return; | |
870 | ||
871 | case PORT_CLK_SEL_SPLL: | |
872 | pll_name = "SPLL"; | |
873 | reg = SPLL_CTL; | |
874 | refcount = plls->spll_refcount; | |
875 | new_val = SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | | |
876 | SPLL_PLL_SSC; | |
877 | break; | |
878 | ||
879 | case PORT_CLK_SEL_WRPLL1: | |
880 | case PORT_CLK_SEL_WRPLL2: | |
881 | if (crtc->ddi_pll_sel == PORT_CLK_SEL_WRPLL1) { | |
882 | pll_name = "WRPLL1"; | |
883 | reg = WRPLL_CTL1; | |
884 | refcount = plls->wrpll1_refcount; | |
885 | } else { | |
886 | pll_name = "WRPLL2"; | |
887 | reg = WRPLL_CTL2; | |
888 | refcount = plls->wrpll2_refcount; | |
889 | } | |
890 | ||
891 | intel_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p); | |
892 | ||
893 | new_val = WRPLL_PLL_ENABLE | WRPLL_PLL_SELECT_LCPLL_2700 | | |
894 | WRPLL_DIVIDER_REFERENCE(r2) | | |
895 | WRPLL_DIVIDER_FEEDBACK(n2) | WRPLL_DIVIDER_POST(p); | |
896 | ||
897 | break; | |
898 | ||
899 | case PORT_CLK_SEL_NONE: | |
900 | WARN(1, "Bad selected pll: PORT_CLK_SEL_NONE\n"); | |
901 | return; | |
902 | default: | |
903 | WARN(1, "Bad selected pll: 0x%08x\n", crtc->ddi_pll_sel); | |
904 | return; | |
905 | } | |
906 | ||
907 | cur_val = I915_READ(reg); | |
908 | ||
909 | WARN(refcount < 1, "Bad %s refcount: %d\n", pll_name, refcount); | |
910 | if (refcount == 1) { | |
911 | WARN(cur_val & enable_bit, "%s already enabled\n", pll_name); | |
912 | I915_WRITE(reg, new_val); | |
913 | POSTING_READ(reg); | |
914 | udelay(20); | |
915 | } else { | |
916 | WARN((cur_val & enable_bit) == 0, "%s disabled\n", pll_name); | |
917 | } | |
918 | } | |
919 | ||
dae84799 PZ |
920 | void intel_ddi_set_pipe_settings(struct drm_crtc *crtc) |
921 | { | |
922 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
923 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
924 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
3b117c8f | 925 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
dae84799 PZ |
926 | int type = intel_encoder->type; |
927 | uint32_t temp; | |
928 | ||
929 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { | |
930 | ||
c9809791 | 931 | temp = TRANS_MSA_SYNC_CLK; |
965e0c48 | 932 | switch (intel_crtc->config.pipe_bpp) { |
dae84799 | 933 | case 18: |
c9809791 | 934 | temp |= TRANS_MSA_6_BPC; |
dae84799 PZ |
935 | break; |
936 | case 24: | |
c9809791 | 937 | temp |= TRANS_MSA_8_BPC; |
dae84799 PZ |
938 | break; |
939 | case 30: | |
c9809791 | 940 | temp |= TRANS_MSA_10_BPC; |
dae84799 PZ |
941 | break; |
942 | case 36: | |
c9809791 | 943 | temp |= TRANS_MSA_12_BPC; |
dae84799 PZ |
944 | break; |
945 | default: | |
4e53c2e0 | 946 | BUG(); |
dae84799 | 947 | } |
c9809791 | 948 | I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp); |
dae84799 PZ |
949 | } |
950 | } | |
951 | ||
8228c251 | 952 | void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc) |
8d9ddbcb PZ |
953 | { |
954 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
955 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
7739c33b | 956 | struct drm_encoder *encoder = &intel_encoder->base; |
c7670b10 PZ |
957 | struct drm_device *dev = crtc->dev; |
958 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8d9ddbcb | 959 | enum pipe pipe = intel_crtc->pipe; |
3b117c8f | 960 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
174edf1f | 961 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
7739c33b | 962 | int type = intel_encoder->type; |
8d9ddbcb PZ |
963 | uint32_t temp; |
964 | ||
ad80a810 PZ |
965 | /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ |
966 | temp = TRANS_DDI_FUNC_ENABLE; | |
174edf1f | 967 | temp |= TRANS_DDI_SELECT_PORT(port); |
dfcef252 | 968 | |
965e0c48 | 969 | switch (intel_crtc->config.pipe_bpp) { |
dfcef252 | 970 | case 18: |
ad80a810 | 971 | temp |= TRANS_DDI_BPC_6; |
dfcef252 PZ |
972 | break; |
973 | case 24: | |
ad80a810 | 974 | temp |= TRANS_DDI_BPC_8; |
dfcef252 PZ |
975 | break; |
976 | case 30: | |
ad80a810 | 977 | temp |= TRANS_DDI_BPC_10; |
dfcef252 PZ |
978 | break; |
979 | case 36: | |
ad80a810 | 980 | temp |= TRANS_DDI_BPC_12; |
dfcef252 PZ |
981 | break; |
982 | default: | |
4e53c2e0 | 983 | BUG(); |
dfcef252 | 984 | } |
72662e10 | 985 | |
a666283e | 986 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) |
ad80a810 | 987 | temp |= TRANS_DDI_PVSYNC; |
a666283e | 988 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) |
ad80a810 | 989 | temp |= TRANS_DDI_PHSYNC; |
f63eb7c4 | 990 | |
e6f0bfc4 PZ |
991 | if (cpu_transcoder == TRANSCODER_EDP) { |
992 | switch (pipe) { | |
993 | case PIPE_A: | |
c7670b10 PZ |
994 | /* On Haswell, can only use the always-on power well for |
995 | * eDP when not using the panel fitter, and when not | |
996 | * using motion blur mitigation (which we don't | |
997 | * support). */ | |
998 | if (IS_HASWELL(dev) && intel_crtc->config.pch_pfit.enabled) | |
d6dd9eb1 DV |
999 | temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; |
1000 | else | |
1001 | temp |= TRANS_DDI_EDP_INPUT_A_ON; | |
e6f0bfc4 PZ |
1002 | break; |
1003 | case PIPE_B: | |
1004 | temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; | |
1005 | break; | |
1006 | case PIPE_C: | |
1007 | temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; | |
1008 | break; | |
1009 | default: | |
1010 | BUG(); | |
1011 | break; | |
1012 | } | |
1013 | } | |
1014 | ||
7739c33b | 1015 | if (type == INTEL_OUTPUT_HDMI) { |
6897b4b5 | 1016 | if (intel_crtc->config.has_hdmi_sink) |
ad80a810 | 1017 | temp |= TRANS_DDI_MODE_SELECT_HDMI; |
8d9ddbcb | 1018 | else |
ad80a810 | 1019 | temp |= TRANS_DDI_MODE_SELECT_DVI; |
8d9ddbcb | 1020 | |
7739c33b | 1021 | } else if (type == INTEL_OUTPUT_ANALOG) { |
ad80a810 | 1022 | temp |= TRANS_DDI_MODE_SELECT_FDI; |
33d29b14 | 1023 | temp |= (intel_crtc->config.fdi_lanes - 1) << 1; |
7739c33b PZ |
1024 | |
1025 | } else if (type == INTEL_OUTPUT_DISPLAYPORT || | |
1026 | type == INTEL_OUTPUT_EDP) { | |
1027 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
1028 | ||
ad80a810 | 1029 | temp |= TRANS_DDI_MODE_SELECT_DP_SST; |
7739c33b | 1030 | |
17aa6be9 | 1031 | temp |= DDI_PORT_WIDTH(intel_dp->lane_count); |
8d9ddbcb | 1032 | } else { |
84f44ce7 VS |
1033 | WARN(1, "Invalid encoder type %d for pipe %c\n", |
1034 | intel_encoder->type, pipe_name(pipe)); | |
8d9ddbcb PZ |
1035 | } |
1036 | ||
ad80a810 | 1037 | I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); |
8d9ddbcb | 1038 | } |
72662e10 | 1039 | |
ad80a810 PZ |
1040 | void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, |
1041 | enum transcoder cpu_transcoder) | |
8d9ddbcb | 1042 | { |
ad80a810 | 1043 | uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
8d9ddbcb PZ |
1044 | uint32_t val = I915_READ(reg); |
1045 | ||
ad80a810 PZ |
1046 | val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK); |
1047 | val |= TRANS_DDI_PORT_NONE; | |
8d9ddbcb | 1048 | I915_WRITE(reg, val); |
72662e10 ED |
1049 | } |
1050 | ||
bcbc889b PZ |
1051 | bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) |
1052 | { | |
1053 | struct drm_device *dev = intel_connector->base.dev; | |
1054 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1055 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
1056 | int type = intel_connector->base.connector_type; | |
1057 | enum port port = intel_ddi_get_encoder_port(intel_encoder); | |
1058 | enum pipe pipe = 0; | |
1059 | enum transcoder cpu_transcoder; | |
882244a3 | 1060 | enum intel_display_power_domain power_domain; |
bcbc889b PZ |
1061 | uint32_t tmp; |
1062 | ||
882244a3 PZ |
1063 | power_domain = intel_display_port_power_domain(intel_encoder); |
1064 | if (!intel_display_power_enabled(dev_priv, power_domain)) | |
1065 | return false; | |
1066 | ||
bcbc889b PZ |
1067 | if (!intel_encoder->get_hw_state(intel_encoder, &pipe)) |
1068 | return false; | |
1069 | ||
1070 | if (port == PORT_A) | |
1071 | cpu_transcoder = TRANSCODER_EDP; | |
1072 | else | |
1a240d4d | 1073 | cpu_transcoder = (enum transcoder) pipe; |
bcbc889b PZ |
1074 | |
1075 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); | |
1076 | ||
1077 | switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { | |
1078 | case TRANS_DDI_MODE_SELECT_HDMI: | |
1079 | case TRANS_DDI_MODE_SELECT_DVI: | |
1080 | return (type == DRM_MODE_CONNECTOR_HDMIA); | |
1081 | ||
1082 | case TRANS_DDI_MODE_SELECT_DP_SST: | |
1083 | if (type == DRM_MODE_CONNECTOR_eDP) | |
1084 | return true; | |
1085 | case TRANS_DDI_MODE_SELECT_DP_MST: | |
1086 | return (type == DRM_MODE_CONNECTOR_DisplayPort); | |
1087 | ||
1088 | case TRANS_DDI_MODE_SELECT_FDI: | |
1089 | return (type == DRM_MODE_CONNECTOR_VGA); | |
1090 | ||
1091 | default: | |
1092 | return false; | |
1093 | } | |
1094 | } | |
1095 | ||
85234cdc DV |
1096 | bool intel_ddi_get_hw_state(struct intel_encoder *encoder, |
1097 | enum pipe *pipe) | |
1098 | { | |
1099 | struct drm_device *dev = encoder->base.dev; | |
1100 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fe43d3f5 | 1101 | enum port port = intel_ddi_get_encoder_port(encoder); |
6d129bea | 1102 | enum intel_display_power_domain power_domain; |
85234cdc DV |
1103 | u32 tmp; |
1104 | int i; | |
1105 | ||
6d129bea ID |
1106 | power_domain = intel_display_port_power_domain(encoder); |
1107 | if (!intel_display_power_enabled(dev_priv, power_domain)) | |
1108 | return false; | |
1109 | ||
fe43d3f5 | 1110 | tmp = I915_READ(DDI_BUF_CTL(port)); |
85234cdc DV |
1111 | |
1112 | if (!(tmp & DDI_BUF_CTL_ENABLE)) | |
1113 | return false; | |
1114 | ||
ad80a810 PZ |
1115 | if (port == PORT_A) { |
1116 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); | |
85234cdc | 1117 | |
ad80a810 PZ |
1118 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { |
1119 | case TRANS_DDI_EDP_INPUT_A_ON: | |
1120 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
1121 | *pipe = PIPE_A; | |
1122 | break; | |
1123 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
1124 | *pipe = PIPE_B; | |
1125 | break; | |
1126 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
1127 | *pipe = PIPE_C; | |
1128 | break; | |
1129 | } | |
1130 | ||
1131 | return true; | |
1132 | } else { | |
1133 | for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) { | |
1134 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(i)); | |
1135 | ||
1136 | if ((tmp & TRANS_DDI_PORT_MASK) | |
1137 | == TRANS_DDI_SELECT_PORT(port)) { | |
1138 | *pipe = i; | |
1139 | return true; | |
1140 | } | |
85234cdc DV |
1141 | } |
1142 | } | |
1143 | ||
84f44ce7 | 1144 | DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port)); |
85234cdc | 1145 | |
22f9fe50 | 1146 | return false; |
85234cdc DV |
1147 | } |
1148 | ||
6441ab5f PZ |
1149 | static uint32_t intel_ddi_get_crtc_pll(struct drm_i915_private *dev_priv, |
1150 | enum pipe pipe) | |
1151 | { | |
1152 | uint32_t temp, ret; | |
a42f704b | 1153 | enum port port = I915_MAX_PORTS; |
ad80a810 PZ |
1154 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1155 | pipe); | |
6441ab5f PZ |
1156 | int i; |
1157 | ||
ad80a810 PZ |
1158 | if (cpu_transcoder == TRANSCODER_EDP) { |
1159 | port = PORT_A; | |
1160 | } else { | |
1161 | temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); | |
1162 | temp &= TRANS_DDI_PORT_MASK; | |
1163 | ||
1164 | for (i = PORT_B; i <= PORT_E; i++) | |
1165 | if (temp == TRANS_DDI_SELECT_PORT(i)) | |
1166 | port = i; | |
1167 | } | |
6441ab5f | 1168 | |
a42f704b DL |
1169 | if (port == I915_MAX_PORTS) { |
1170 | WARN(1, "Pipe %c enabled on an unknown port\n", | |
1171 | pipe_name(pipe)); | |
1172 | ret = PORT_CLK_SEL_NONE; | |
1173 | } else { | |
1174 | ret = I915_READ(PORT_CLK_SEL(port)); | |
1175 | DRM_DEBUG_KMS("Pipe %c connected to port %c using clock " | |
1176 | "0x%08x\n", pipe_name(pipe), port_name(port), | |
1177 | ret); | |
1178 | } | |
6441ab5f PZ |
1179 | |
1180 | return ret; | |
1181 | } | |
1182 | ||
1183 | void intel_ddi_setup_hw_pll_state(struct drm_device *dev) | |
1184 | { | |
1185 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1186 | enum pipe pipe; | |
1187 | struct intel_crtc *intel_crtc; | |
1188 | ||
0882dae9 PZ |
1189 | dev_priv->ddi_plls.spll_refcount = 0; |
1190 | dev_priv->ddi_plls.wrpll1_refcount = 0; | |
1191 | dev_priv->ddi_plls.wrpll2_refcount = 0; | |
1192 | ||
6441ab5f PZ |
1193 | for_each_pipe(pipe) { |
1194 | intel_crtc = | |
1195 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
1196 | ||
0882dae9 PZ |
1197 | if (!intel_crtc->active) { |
1198 | intel_crtc->ddi_pll_sel = PORT_CLK_SEL_NONE; | |
6441ab5f | 1199 | continue; |
0882dae9 | 1200 | } |
6441ab5f PZ |
1201 | |
1202 | intel_crtc->ddi_pll_sel = intel_ddi_get_crtc_pll(dev_priv, | |
1203 | pipe); | |
1204 | ||
1205 | switch (intel_crtc->ddi_pll_sel) { | |
1206 | case PORT_CLK_SEL_SPLL: | |
1207 | dev_priv->ddi_plls.spll_refcount++; | |
1208 | break; | |
1209 | case PORT_CLK_SEL_WRPLL1: | |
1210 | dev_priv->ddi_plls.wrpll1_refcount++; | |
1211 | break; | |
1212 | case PORT_CLK_SEL_WRPLL2: | |
1213 | dev_priv->ddi_plls.wrpll2_refcount++; | |
1214 | break; | |
1215 | } | |
1216 | } | |
1217 | } | |
1218 | ||
fc914639 PZ |
1219 | void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc) |
1220 | { | |
1221 | struct drm_crtc *crtc = &intel_crtc->base; | |
1222 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
1223 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
1224 | enum port port = intel_ddi_get_encoder_port(intel_encoder); | |
3b117c8f | 1225 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
fc914639 | 1226 | |
bb523fc0 PZ |
1227 | if (cpu_transcoder != TRANSCODER_EDP) |
1228 | I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), | |
1229 | TRANS_CLK_SEL_PORT(port)); | |
fc914639 PZ |
1230 | } |
1231 | ||
1232 | void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc) | |
1233 | { | |
1234 | struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; | |
3b117c8f | 1235 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
fc914639 | 1236 | |
bb523fc0 PZ |
1237 | if (cpu_transcoder != TRANSCODER_EDP) |
1238 | I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), | |
1239 | TRANS_CLK_SEL_DISABLED); | |
fc914639 PZ |
1240 | } |
1241 | ||
00c09d70 | 1242 | static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder) |
6441ab5f | 1243 | { |
c19b0669 | 1244 | struct drm_encoder *encoder = &intel_encoder->base; |
c19b0669 | 1245 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
30cf6db8 | 1246 | struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); |
6441ab5f | 1247 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
82a4d9c0 | 1248 | int type = intel_encoder->type; |
6441ab5f | 1249 | |
30cf6db8 DV |
1250 | if (crtc->config.has_audio) { |
1251 | DRM_DEBUG_DRIVER("Audio on pipe %c on DDI\n", | |
1252 | pipe_name(crtc->pipe)); | |
1253 | ||
1254 | /* write eld */ | |
1255 | DRM_DEBUG_DRIVER("DDI audio: write eld information\n"); | |
1256 | intel_write_eld(encoder, &crtc->config.adjusted_mode); | |
1257 | } | |
1258 | ||
82a4d9c0 PZ |
1259 | if (type == INTEL_OUTPUT_EDP) { |
1260 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
4be73780 | 1261 | intel_edp_panel_on(intel_dp); |
82a4d9c0 | 1262 | } |
6441ab5f | 1263 | |
30cf6db8 DV |
1264 | WARN_ON(crtc->ddi_pll_sel == PORT_CLK_SEL_NONE); |
1265 | I915_WRITE(PORT_CLK_SEL(port), crtc->ddi_pll_sel); | |
c19b0669 | 1266 | |
82a4d9c0 | 1267 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { |
c19b0669 | 1268 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
30cf6db8 DV |
1269 | struct intel_digital_port *intel_dig_port = |
1270 | enc_to_dig_port(encoder); | |
1271 | ||
1272 | intel_dp->DP = intel_dig_port->saved_port_bits | | |
1273 | DDI_BUF_CTL_ENABLE | DDI_BUF_EMP_400MV_0DB_HSW; | |
1274 | intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count); | |
c19b0669 PZ |
1275 | |
1276 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); | |
1277 | intel_dp_start_link_train(intel_dp); | |
1278 | intel_dp_complete_link_train(intel_dp); | |
3ab9c637 ID |
1279 | if (port != PORT_A) |
1280 | intel_dp_stop_link_train(intel_dp); | |
30cf6db8 DV |
1281 | } else if (type == INTEL_OUTPUT_HDMI) { |
1282 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
1283 | ||
1284 | intel_hdmi->set_infoframes(encoder, | |
1285 | crtc->config.has_hdmi_sink, | |
1286 | &crtc->config.adjusted_mode); | |
c19b0669 | 1287 | } |
6441ab5f PZ |
1288 | } |
1289 | ||
00c09d70 | 1290 | static void intel_ddi_post_disable(struct intel_encoder *intel_encoder) |
6441ab5f PZ |
1291 | { |
1292 | struct drm_encoder *encoder = &intel_encoder->base; | |
1293 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; | |
1294 | enum port port = intel_ddi_get_encoder_port(intel_encoder); | |
82a4d9c0 | 1295 | int type = intel_encoder->type; |
2886e93f | 1296 | uint32_t val; |
a836bdf9 | 1297 | bool wait = false; |
2886e93f PZ |
1298 | |
1299 | val = I915_READ(DDI_BUF_CTL(port)); | |
1300 | if (val & DDI_BUF_CTL_ENABLE) { | |
1301 | val &= ~DDI_BUF_CTL_ENABLE; | |
1302 | I915_WRITE(DDI_BUF_CTL(port), val); | |
a836bdf9 | 1303 | wait = true; |
2886e93f | 1304 | } |
6441ab5f | 1305 | |
a836bdf9 PZ |
1306 | val = I915_READ(DP_TP_CTL(port)); |
1307 | val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); | |
1308 | val |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
1309 | I915_WRITE(DP_TP_CTL(port), val); | |
1310 | ||
1311 | if (wait) | |
1312 | intel_wait_ddi_buf_idle(dev_priv, port); | |
1313 | ||
76bb80ed | 1314 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { |
82a4d9c0 | 1315 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
76bb80ed | 1316 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); |
24f3e092 | 1317 | intel_edp_panel_vdd_on(intel_dp); |
4be73780 | 1318 | intel_edp_panel_off(intel_dp); |
82a4d9c0 PZ |
1319 | } |
1320 | ||
6441ab5f PZ |
1321 | I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); |
1322 | } | |
1323 | ||
00c09d70 | 1324 | static void intel_enable_ddi(struct intel_encoder *intel_encoder) |
72662e10 | 1325 | { |
6547fef8 | 1326 | struct drm_encoder *encoder = &intel_encoder->base; |
7b9f35a6 WX |
1327 | struct drm_crtc *crtc = encoder->crtc; |
1328 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1329 | int pipe = intel_crtc->pipe; | |
6547fef8 | 1330 | struct drm_device *dev = encoder->dev; |
72662e10 | 1331 | struct drm_i915_private *dev_priv = dev->dev_private; |
6547fef8 PZ |
1332 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
1333 | int type = intel_encoder->type; | |
7b9f35a6 | 1334 | uint32_t tmp; |
72662e10 | 1335 | |
6547fef8 | 1336 | if (type == INTEL_OUTPUT_HDMI) { |
876a8cdf DL |
1337 | struct intel_digital_port *intel_dig_port = |
1338 | enc_to_dig_port(encoder); | |
1339 | ||
6547fef8 PZ |
1340 | /* In HDMI/DVI mode, the port width, and swing/emphasis values |
1341 | * are ignored so nothing special needs to be done besides | |
1342 | * enabling the port. | |
1343 | */ | |
876a8cdf | 1344 | I915_WRITE(DDI_BUF_CTL(port), |
bcf53de4 SM |
1345 | intel_dig_port->saved_port_bits | |
1346 | DDI_BUF_CTL_ENABLE); | |
d6c50ff8 PZ |
1347 | } else if (type == INTEL_OUTPUT_EDP) { |
1348 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
1349 | ||
3ab9c637 ID |
1350 | if (port == PORT_A) |
1351 | intel_dp_stop_link_train(intel_dp); | |
1352 | ||
4be73780 | 1353 | intel_edp_backlight_on(intel_dp); |
4906557e | 1354 | intel_edp_psr_enable(intel_dp); |
6547fef8 | 1355 | } |
7b9f35a6 | 1356 | |
9ed109a7 | 1357 | if (intel_crtc->config.has_audio) { |
d45a0bf5 | 1358 | intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO); |
7b9f35a6 WX |
1359 | tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); |
1360 | tmp |= ((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << (pipe * 4)); | |
1361 | I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); | |
1362 | } | |
5ab432ef DV |
1363 | } |
1364 | ||
00c09d70 | 1365 | static void intel_disable_ddi(struct intel_encoder *intel_encoder) |
5ab432ef | 1366 | { |
d6c50ff8 | 1367 | struct drm_encoder *encoder = &intel_encoder->base; |
7b9f35a6 WX |
1368 | struct drm_crtc *crtc = encoder->crtc; |
1369 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1370 | int pipe = intel_crtc->pipe; | |
d6c50ff8 | 1371 | int type = intel_encoder->type; |
7b9f35a6 WX |
1372 | struct drm_device *dev = encoder->dev; |
1373 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1374 | uint32_t tmp; | |
d6c50ff8 | 1375 | |
d45a0bf5 PZ |
1376 | /* We can't touch HSW_AUD_PIN_ELD_CP_VLD uncionditionally because this |
1377 | * register is part of the power well on Haswell. */ | |
1378 | if (intel_crtc->config.has_audio) { | |
1379 | tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); | |
1380 | tmp &= ~((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << | |
1381 | (pipe * 4)); | |
1382 | I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); | |
1383 | intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO); | |
1384 | } | |
2831d842 | 1385 | |
d6c50ff8 PZ |
1386 | if (type == INTEL_OUTPUT_EDP) { |
1387 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
1388 | ||
4906557e | 1389 | intel_edp_psr_disable(intel_dp); |
4be73780 | 1390 | intel_edp_backlight_off(intel_dp); |
d6c50ff8 | 1391 | } |
72662e10 | 1392 | } |
79f689aa | 1393 | |
b8fc2f6a | 1394 | int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv) |
79f689aa | 1395 | { |
e39bf98a | 1396 | struct drm_device *dev = dev_priv->dev; |
a4006641 | 1397 | uint32_t lcpll = I915_READ(LCPLL_CTL); |
e39bf98a | 1398 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; |
a4006641 | 1399 | |
e39bf98a | 1400 | if (lcpll & LCPLL_CD_SOURCE_FCLK) { |
a4006641 | 1401 | return 800000; |
e3589908 | 1402 | } else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) { |
b2b877ff | 1403 | return 450000; |
e39bf98a | 1404 | } else if (freq == LCPLL_CLK_FREQ_450) { |
b2b877ff | 1405 | return 450000; |
e39bf98a PZ |
1406 | } else if (IS_HASWELL(dev)) { |
1407 | if (IS_ULT(dev)) | |
1408 | return 337500; | |
1409 | else | |
1410 | return 540000; | |
1411 | } else { | |
1412 | if (freq == LCPLL_CLK_FREQ_54O_BDW) | |
1413 | return 540000; | |
1414 | else if (freq == LCPLL_CLK_FREQ_337_5_BDW) | |
1415 | return 337500; | |
1416 | else | |
1417 | return 675000; | |
1418 | } | |
79f689aa PZ |
1419 | } |
1420 | ||
1421 | void intel_ddi_pll_init(struct drm_device *dev) | |
1422 | { | |
1423 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1424 | uint32_t val = I915_READ(LCPLL_CTL); | |
1425 | ||
1426 | /* The LCPLL register should be turned on by the BIOS. For now let's | |
1427 | * just check its state and print errors in case something is wrong. | |
1428 | * Don't even try to turn it on. | |
1429 | */ | |
1430 | ||
b2b877ff | 1431 | DRM_DEBUG_KMS("CDCLK running at %dKHz\n", |
79f689aa PZ |
1432 | intel_ddi_get_cdclk_freq(dev_priv)); |
1433 | ||
1434 | if (val & LCPLL_CD_SOURCE_FCLK) | |
1435 | DRM_ERROR("CDCLK source is not LCPLL\n"); | |
1436 | ||
1437 | if (val & LCPLL_PLL_DISABLE) | |
1438 | DRM_ERROR("LCPLL is disabled\n"); | |
1439 | } | |
c19b0669 PZ |
1440 | |
1441 | void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder) | |
1442 | { | |
174edf1f PZ |
1443 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
1444 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
c19b0669 | 1445 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
174edf1f | 1446 | enum port port = intel_dig_port->port; |
c19b0669 | 1447 | uint32_t val; |
f3e227df | 1448 | bool wait = false; |
c19b0669 PZ |
1449 | |
1450 | if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) { | |
1451 | val = I915_READ(DDI_BUF_CTL(port)); | |
1452 | if (val & DDI_BUF_CTL_ENABLE) { | |
1453 | val &= ~DDI_BUF_CTL_ENABLE; | |
1454 | I915_WRITE(DDI_BUF_CTL(port), val); | |
1455 | wait = true; | |
1456 | } | |
1457 | ||
1458 | val = I915_READ(DP_TP_CTL(port)); | |
1459 | val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); | |
1460 | val |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
1461 | I915_WRITE(DP_TP_CTL(port), val); | |
1462 | POSTING_READ(DP_TP_CTL(port)); | |
1463 | ||
1464 | if (wait) | |
1465 | intel_wait_ddi_buf_idle(dev_priv, port); | |
1466 | } | |
1467 | ||
1468 | val = DP_TP_CTL_ENABLE | DP_TP_CTL_MODE_SST | | |
1469 | DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE; | |
6aba5b6c | 1470 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
c19b0669 PZ |
1471 | val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; |
1472 | I915_WRITE(DP_TP_CTL(port), val); | |
1473 | POSTING_READ(DP_TP_CTL(port)); | |
1474 | ||
1475 | intel_dp->DP |= DDI_BUF_CTL_ENABLE; | |
1476 | I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP); | |
1477 | POSTING_READ(DDI_BUF_CTL(port)); | |
1478 | ||
1479 | udelay(600); | |
1480 | } | |
00c09d70 | 1481 | |
1ad960f2 PZ |
1482 | void intel_ddi_fdi_disable(struct drm_crtc *crtc) |
1483 | { | |
1484 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
1485 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
1486 | uint32_t val; | |
1487 | ||
1488 | intel_ddi_post_disable(intel_encoder); | |
1489 | ||
1490 | val = I915_READ(_FDI_RXA_CTL); | |
1491 | val &= ~FDI_RX_ENABLE; | |
1492 | I915_WRITE(_FDI_RXA_CTL, val); | |
1493 | ||
1494 | val = I915_READ(_FDI_RXA_MISC); | |
1495 | val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); | |
1496 | val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); | |
1497 | I915_WRITE(_FDI_RXA_MISC, val); | |
1498 | ||
1499 | val = I915_READ(_FDI_RXA_CTL); | |
1500 | val &= ~FDI_PCDCLK; | |
1501 | I915_WRITE(_FDI_RXA_CTL, val); | |
1502 | ||
1503 | val = I915_READ(_FDI_RXA_CTL); | |
1504 | val &= ~FDI_RX_PLL_ENABLE; | |
1505 | I915_WRITE(_FDI_RXA_CTL, val); | |
1506 | } | |
1507 | ||
00c09d70 PZ |
1508 | static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder) |
1509 | { | |
1510 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
1511 | int type = intel_encoder->type; | |
1512 | ||
1513 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) | |
1514 | intel_dp_check_link_status(intel_dp); | |
1515 | } | |
1516 | ||
6801c18c VS |
1517 | void intel_ddi_get_config(struct intel_encoder *encoder, |
1518 | struct intel_crtc_config *pipe_config) | |
045ac3b5 JB |
1519 | { |
1520 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
1521 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); | |
1522 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; | |
1523 | u32 temp, flags = 0; | |
1524 | ||
1525 | temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); | |
1526 | if (temp & TRANS_DDI_PHSYNC) | |
1527 | flags |= DRM_MODE_FLAG_PHSYNC; | |
1528 | else | |
1529 | flags |= DRM_MODE_FLAG_NHSYNC; | |
1530 | if (temp & TRANS_DDI_PVSYNC) | |
1531 | flags |= DRM_MODE_FLAG_PVSYNC; | |
1532 | else | |
1533 | flags |= DRM_MODE_FLAG_NVSYNC; | |
1534 | ||
1535 | pipe_config->adjusted_mode.flags |= flags; | |
42571aef VS |
1536 | |
1537 | switch (temp & TRANS_DDI_BPC_MASK) { | |
1538 | case TRANS_DDI_BPC_6: | |
1539 | pipe_config->pipe_bpp = 18; | |
1540 | break; | |
1541 | case TRANS_DDI_BPC_8: | |
1542 | pipe_config->pipe_bpp = 24; | |
1543 | break; | |
1544 | case TRANS_DDI_BPC_10: | |
1545 | pipe_config->pipe_bpp = 30; | |
1546 | break; | |
1547 | case TRANS_DDI_BPC_12: | |
1548 | pipe_config->pipe_bpp = 36; | |
1549 | break; | |
1550 | default: | |
1551 | break; | |
1552 | } | |
eb14cb74 VS |
1553 | |
1554 | switch (temp & TRANS_DDI_MODE_SELECT_MASK) { | |
1555 | case TRANS_DDI_MODE_SELECT_HDMI: | |
6897b4b5 | 1556 | pipe_config->has_hdmi_sink = true; |
eb14cb74 VS |
1557 | case TRANS_DDI_MODE_SELECT_DVI: |
1558 | case TRANS_DDI_MODE_SELECT_FDI: | |
1559 | break; | |
1560 | case TRANS_DDI_MODE_SELECT_DP_SST: | |
1561 | case TRANS_DDI_MODE_SELECT_DP_MST: | |
1562 | pipe_config->has_dp_encoder = true; | |
1563 | intel_dp_get_m_n(intel_crtc, pipe_config); | |
1564 | break; | |
1565 | default: | |
1566 | break; | |
1567 | } | |
10214420 | 1568 | |
a60551b1 PZ |
1569 | if (intel_display_power_enabled(dev_priv, POWER_DOMAIN_AUDIO)) { |
1570 | temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); | |
1571 | if (temp & (AUDIO_OUTPUT_ENABLE_A << (intel_crtc->pipe * 4))) | |
1572 | pipe_config->has_audio = true; | |
1573 | } | |
9ed109a7 | 1574 | |
10214420 DV |
1575 | if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp && |
1576 | pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) { | |
1577 | /* | |
1578 | * This is a big fat ugly hack. | |
1579 | * | |
1580 | * Some machines in UEFI boot mode provide us a VBT that has 18 | |
1581 | * bpp and 1.62 GHz link bandwidth for eDP, which for reasons | |
1582 | * unknown we fail to light up. Yet the same BIOS boots up with | |
1583 | * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as | |
1584 | * max, not what it tells us to use. | |
1585 | * | |
1586 | * Note: This will still be broken if the eDP panel is not lit | |
1587 | * up by the BIOS, and thus we can't get the mode at module | |
1588 | * load. | |
1589 | */ | |
1590 | DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", | |
1591 | pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp); | |
1592 | dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp; | |
1593 | } | |
11578553 JB |
1594 | |
1595 | intel_ddi_clock_get(encoder, pipe_config); | |
045ac3b5 JB |
1596 | } |
1597 | ||
00c09d70 PZ |
1598 | static void intel_ddi_destroy(struct drm_encoder *encoder) |
1599 | { | |
1600 | /* HDMI has nothing special to destroy, so we can go with this. */ | |
1601 | intel_dp_encoder_destroy(encoder); | |
1602 | } | |
1603 | ||
5bfe2ac0 DV |
1604 | static bool intel_ddi_compute_config(struct intel_encoder *encoder, |
1605 | struct intel_crtc_config *pipe_config) | |
00c09d70 | 1606 | { |
5bfe2ac0 | 1607 | int type = encoder->type; |
eccb140b | 1608 | int port = intel_ddi_get_encoder_port(encoder); |
00c09d70 | 1609 | |
5bfe2ac0 | 1610 | WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n"); |
00c09d70 | 1611 | |
eccb140b DV |
1612 | if (port == PORT_A) |
1613 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
1614 | ||
00c09d70 | 1615 | if (type == INTEL_OUTPUT_HDMI) |
5bfe2ac0 | 1616 | return intel_hdmi_compute_config(encoder, pipe_config); |
00c09d70 | 1617 | else |
5bfe2ac0 | 1618 | return intel_dp_compute_config(encoder, pipe_config); |
00c09d70 PZ |
1619 | } |
1620 | ||
1621 | static const struct drm_encoder_funcs intel_ddi_funcs = { | |
1622 | .destroy = intel_ddi_destroy, | |
1623 | }; | |
1624 | ||
4a28ae58 PZ |
1625 | static struct intel_connector * |
1626 | intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port) | |
1627 | { | |
1628 | struct intel_connector *connector; | |
1629 | enum port port = intel_dig_port->port; | |
1630 | ||
1631 | connector = kzalloc(sizeof(*connector), GFP_KERNEL); | |
1632 | if (!connector) | |
1633 | return NULL; | |
1634 | ||
1635 | intel_dig_port->dp.output_reg = DDI_BUF_CTL(port); | |
1636 | if (!intel_dp_init_connector(intel_dig_port, connector)) { | |
1637 | kfree(connector); | |
1638 | return NULL; | |
1639 | } | |
1640 | ||
1641 | return connector; | |
1642 | } | |
1643 | ||
1644 | static struct intel_connector * | |
1645 | intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port) | |
1646 | { | |
1647 | struct intel_connector *connector; | |
1648 | enum port port = intel_dig_port->port; | |
1649 | ||
1650 | connector = kzalloc(sizeof(*connector), GFP_KERNEL); | |
1651 | if (!connector) | |
1652 | return NULL; | |
1653 | ||
1654 | intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); | |
1655 | intel_hdmi_init_connector(intel_dig_port, connector); | |
1656 | ||
1657 | return connector; | |
1658 | } | |
1659 | ||
00c09d70 PZ |
1660 | void intel_ddi_init(struct drm_device *dev, enum port port) |
1661 | { | |
876a8cdf | 1662 | struct drm_i915_private *dev_priv = dev->dev_private; |
00c09d70 PZ |
1663 | struct intel_digital_port *intel_dig_port; |
1664 | struct intel_encoder *intel_encoder; | |
1665 | struct drm_encoder *encoder; | |
1666 | struct intel_connector *hdmi_connector = NULL; | |
1667 | struct intel_connector *dp_connector = NULL; | |
311a2094 PZ |
1668 | bool init_hdmi, init_dp; |
1669 | ||
1670 | init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi || | |
1671 | dev_priv->vbt.ddi_port_info[port].supports_hdmi); | |
1672 | init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp; | |
1673 | if (!init_dp && !init_hdmi) { | |
1674 | DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible\n", | |
1675 | port_name(port)); | |
1676 | init_hdmi = true; | |
1677 | init_dp = true; | |
1678 | } | |
00c09d70 | 1679 | |
b14c5679 | 1680 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
00c09d70 PZ |
1681 | if (!intel_dig_port) |
1682 | return; | |
1683 | ||
00c09d70 PZ |
1684 | intel_encoder = &intel_dig_port->base; |
1685 | encoder = &intel_encoder->base; | |
1686 | ||
1687 | drm_encoder_init(dev, encoder, &intel_ddi_funcs, | |
1688 | DRM_MODE_ENCODER_TMDS); | |
00c09d70 | 1689 | |
5bfe2ac0 | 1690 | intel_encoder->compute_config = intel_ddi_compute_config; |
00c09d70 PZ |
1691 | intel_encoder->enable = intel_enable_ddi; |
1692 | intel_encoder->pre_enable = intel_ddi_pre_enable; | |
1693 | intel_encoder->disable = intel_disable_ddi; | |
1694 | intel_encoder->post_disable = intel_ddi_post_disable; | |
1695 | intel_encoder->get_hw_state = intel_ddi_get_hw_state; | |
045ac3b5 | 1696 | intel_encoder->get_config = intel_ddi_get_config; |
00c09d70 PZ |
1697 | |
1698 | intel_dig_port->port = port; | |
bcf53de4 SM |
1699 | intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) & |
1700 | (DDI_BUF_PORT_REVERSAL | | |
1701 | DDI_A_4_LANES); | |
00c09d70 PZ |
1702 | |
1703 | intel_encoder->type = INTEL_OUTPUT_UNKNOWN; | |
1704 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); | |
bc079e8b | 1705 | intel_encoder->cloneable = 0; |
00c09d70 PZ |
1706 | intel_encoder->hot_plug = intel_ddi_hot_plug; |
1707 | ||
4a28ae58 PZ |
1708 | if (init_dp) |
1709 | dp_connector = intel_ddi_init_dp_connector(intel_dig_port); | |
21a8e6a4 | 1710 | |
311a2094 PZ |
1711 | /* In theory we don't need the encoder->type check, but leave it just in |
1712 | * case we have some really bad VBTs... */ | |
4a28ae58 PZ |
1713 | if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) |
1714 | hdmi_connector = intel_ddi_init_hdmi_connector(intel_dig_port); | |
21a8e6a4 | 1715 | |
4a28ae58 PZ |
1716 | if (!dp_connector && !hdmi_connector) { |
1717 | drm_encoder_cleanup(encoder); | |
1718 | kfree(intel_dig_port); | |
21a8e6a4 | 1719 | } |
00c09d70 | 1720 | } |