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45244b87 ED |
1 | /* |
2 | * Copyright © 2012 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eugeni Dodonov <eugeni.dodonov@intel.com> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "i915_drv.h" | |
29 | #include "intel_drv.h" | |
30 | ||
10122051 JN |
31 | struct ddi_buf_trans { |
32 | u32 trans1; /* balance leg enable, de-emph level */ | |
33 | u32 trans2; /* vref sel, vswing */ | |
f8896f5d | 34 | u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */ |
10122051 JN |
35 | }; |
36 | ||
45244b87 ED |
37 | /* HDMI/DVI modes ignore everything but the last 2 items. So we share |
38 | * them for both DP and FDI transports, allowing those ports to | |
39 | * automatically adapt to HDMI connections as well | |
40 | */ | |
10122051 | 41 | static const struct ddi_buf_trans hsw_ddi_translations_dp[] = { |
f8896f5d DW |
42 | { 0x00FFFFFF, 0x0006000E, 0x0 }, |
43 | { 0x00D75FFF, 0x0005000A, 0x0 }, | |
44 | { 0x00C30FFF, 0x00040006, 0x0 }, | |
45 | { 0x80AAAFFF, 0x000B0000, 0x0 }, | |
46 | { 0x00FFFFFF, 0x0005000A, 0x0 }, | |
47 | { 0x00D75FFF, 0x000C0004, 0x0 }, | |
48 | { 0x80C30FFF, 0x000B0000, 0x0 }, | |
49 | { 0x00FFFFFF, 0x00040006, 0x0 }, | |
50 | { 0x80D75FFF, 0x000B0000, 0x0 }, | |
45244b87 ED |
51 | }; |
52 | ||
10122051 | 53 | static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = { |
f8896f5d DW |
54 | { 0x00FFFFFF, 0x0007000E, 0x0 }, |
55 | { 0x00D75FFF, 0x000F000A, 0x0 }, | |
56 | { 0x00C30FFF, 0x00060006, 0x0 }, | |
57 | { 0x00AAAFFF, 0x001E0000, 0x0 }, | |
58 | { 0x00FFFFFF, 0x000F000A, 0x0 }, | |
59 | { 0x00D75FFF, 0x00160004, 0x0 }, | |
60 | { 0x00C30FFF, 0x001E0000, 0x0 }, | |
61 | { 0x00FFFFFF, 0x00060006, 0x0 }, | |
62 | { 0x00D75FFF, 0x001E0000, 0x0 }, | |
6acab15a PZ |
63 | }; |
64 | ||
10122051 JN |
65 | static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = { |
66 | /* Idx NT mV d T mV d db */ | |
f8896f5d DW |
67 | { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */ |
68 | { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */ | |
69 | { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */ | |
70 | { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */ | |
71 | { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */ | |
72 | { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */ | |
73 | { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */ | |
74 | { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */ | |
75 | { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */ | |
76 | { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */ | |
77 | { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */ | |
78 | { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */ | |
45244b87 ED |
79 | }; |
80 | ||
10122051 | 81 | static const struct ddi_buf_trans bdw_ddi_translations_edp[] = { |
f8896f5d DW |
82 | { 0x00FFFFFF, 0x00000012, 0x0 }, |
83 | { 0x00EBAFFF, 0x00020011, 0x0 }, | |
84 | { 0x00C71FFF, 0x0006000F, 0x0 }, | |
85 | { 0x00AAAFFF, 0x000E000A, 0x0 }, | |
86 | { 0x00FFFFFF, 0x00020011, 0x0 }, | |
87 | { 0x00DB6FFF, 0x0005000F, 0x0 }, | |
88 | { 0x00BEEFFF, 0x000A000C, 0x0 }, | |
89 | { 0x00FFFFFF, 0x0005000F, 0x0 }, | |
90 | { 0x00DB6FFF, 0x000A000C, 0x0 }, | |
300644c7 PZ |
91 | }; |
92 | ||
10122051 | 93 | static const struct ddi_buf_trans bdw_ddi_translations_dp[] = { |
f8896f5d DW |
94 | { 0x00FFFFFF, 0x0007000E, 0x0 }, |
95 | { 0x00D75FFF, 0x000E000A, 0x0 }, | |
96 | { 0x00BEFFFF, 0x00140006, 0x0 }, | |
97 | { 0x80B2CFFF, 0x001B0002, 0x0 }, | |
98 | { 0x00FFFFFF, 0x000E000A, 0x0 }, | |
99 | { 0x00DB6FFF, 0x00160005, 0x0 }, | |
100 | { 0x80C71FFF, 0x001A0002, 0x0 }, | |
101 | { 0x00F7DFFF, 0x00180004, 0x0 }, | |
102 | { 0x80D75FFF, 0x001B0002, 0x0 }, | |
e58623cb AR |
103 | }; |
104 | ||
10122051 | 105 | static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = { |
f8896f5d DW |
106 | { 0x00FFFFFF, 0x0001000E, 0x0 }, |
107 | { 0x00D75FFF, 0x0004000A, 0x0 }, | |
108 | { 0x00C30FFF, 0x00070006, 0x0 }, | |
109 | { 0x00AAAFFF, 0x000C0000, 0x0 }, | |
110 | { 0x00FFFFFF, 0x0004000A, 0x0 }, | |
111 | { 0x00D75FFF, 0x00090004, 0x0 }, | |
112 | { 0x00C30FFF, 0x000C0000, 0x0 }, | |
113 | { 0x00FFFFFF, 0x00070006, 0x0 }, | |
114 | { 0x00D75FFF, 0x000C0000, 0x0 }, | |
e58623cb AR |
115 | }; |
116 | ||
10122051 JN |
117 | static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = { |
118 | /* Idx NT mV d T mV df db */ | |
f8896f5d DW |
119 | { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */ |
120 | { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */ | |
121 | { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */ | |
122 | { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */ | |
123 | { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */ | |
124 | { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */ | |
125 | { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */ | |
126 | { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */ | |
127 | { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */ | |
128 | { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */ | |
a26aa8ba DL |
129 | }; |
130 | ||
5f8b2531 | 131 | /* Skylake H and S */ |
7f88e3af | 132 | static const struct ddi_buf_trans skl_ddi_translations_dp[] = { |
f8896f5d DW |
133 | { 0x00002016, 0x000000A0, 0x0 }, |
134 | { 0x00005012, 0x0000009B, 0x0 }, | |
135 | { 0x00007011, 0x00000088, 0x0 }, | |
d7097cff | 136 | { 0x80009010, 0x000000C0, 0x1 }, |
f8896f5d DW |
137 | { 0x00002016, 0x0000009B, 0x0 }, |
138 | { 0x00005012, 0x00000088, 0x0 }, | |
d7097cff | 139 | { 0x80007011, 0x000000C0, 0x1 }, |
f8896f5d | 140 | { 0x00002016, 0x000000DF, 0x0 }, |
d7097cff | 141 | { 0x80005012, 0x000000C0, 0x1 }, |
7f88e3af DL |
142 | }; |
143 | ||
f8896f5d DW |
144 | /* Skylake U */ |
145 | static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = { | |
5f8b2531 | 146 | { 0x0000201B, 0x000000A2, 0x0 }, |
f8896f5d | 147 | { 0x00005012, 0x00000088, 0x0 }, |
5ac90567 | 148 | { 0x80007011, 0x000000CD, 0x1 }, |
d7097cff | 149 | { 0x80009010, 0x000000C0, 0x1 }, |
5f8b2531 | 150 | { 0x0000201B, 0x0000009D, 0x0 }, |
d7097cff RV |
151 | { 0x80005012, 0x000000C0, 0x1 }, |
152 | { 0x80007011, 0x000000C0, 0x1 }, | |
f8896f5d | 153 | { 0x00002016, 0x00000088, 0x0 }, |
d7097cff | 154 | { 0x80005012, 0x000000C0, 0x1 }, |
f8896f5d DW |
155 | }; |
156 | ||
5f8b2531 RV |
157 | /* Skylake Y */ |
158 | static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = { | |
f8896f5d DW |
159 | { 0x00000018, 0x000000A2, 0x0 }, |
160 | { 0x00005012, 0x00000088, 0x0 }, | |
5ac90567 | 161 | { 0x80007011, 0x000000CD, 0x3 }, |
d7097cff | 162 | { 0x80009010, 0x000000C0, 0x3 }, |
f8896f5d | 163 | { 0x00000018, 0x0000009D, 0x0 }, |
d7097cff RV |
164 | { 0x80005012, 0x000000C0, 0x3 }, |
165 | { 0x80007011, 0x000000C0, 0x3 }, | |
f8896f5d | 166 | { 0x00000018, 0x00000088, 0x0 }, |
d7097cff | 167 | { 0x80005012, 0x000000C0, 0x3 }, |
f8896f5d DW |
168 | }; |
169 | ||
0fdd4918 RV |
170 | /* Kabylake H and S */ |
171 | static const struct ddi_buf_trans kbl_ddi_translations_dp[] = { | |
172 | { 0x00002016, 0x000000A0, 0x0 }, | |
173 | { 0x00005012, 0x0000009B, 0x0 }, | |
174 | { 0x00007011, 0x00000088, 0x0 }, | |
175 | { 0x80009010, 0x000000C0, 0x1 }, | |
176 | { 0x00002016, 0x0000009B, 0x0 }, | |
177 | { 0x00005012, 0x00000088, 0x0 }, | |
178 | { 0x80007011, 0x000000C0, 0x1 }, | |
179 | { 0x00002016, 0x00000097, 0x0 }, | |
180 | { 0x80005012, 0x000000C0, 0x1 }, | |
181 | }; | |
182 | ||
183 | /* Kabylake U */ | |
184 | static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = { | |
185 | { 0x0000201B, 0x000000A1, 0x0 }, | |
186 | { 0x00005012, 0x00000088, 0x0 }, | |
187 | { 0x80007011, 0x000000CD, 0x3 }, | |
188 | { 0x80009010, 0x000000C0, 0x3 }, | |
189 | { 0x0000201B, 0x0000009D, 0x0 }, | |
190 | { 0x80005012, 0x000000C0, 0x3 }, | |
191 | { 0x80007011, 0x000000C0, 0x3 }, | |
192 | { 0x00002016, 0x0000004F, 0x0 }, | |
193 | { 0x80005012, 0x000000C0, 0x3 }, | |
194 | }; | |
195 | ||
196 | /* Kabylake Y */ | |
197 | static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = { | |
198 | { 0x00001017, 0x000000A1, 0x0 }, | |
199 | { 0x00005012, 0x00000088, 0x0 }, | |
200 | { 0x80007011, 0x000000CD, 0x3 }, | |
201 | { 0x8000800F, 0x000000C0, 0x3 }, | |
202 | { 0x00001017, 0x0000009D, 0x0 }, | |
203 | { 0x80005012, 0x000000C0, 0x3 }, | |
204 | { 0x80007011, 0x000000C0, 0x3 }, | |
205 | { 0x00001017, 0x0000004C, 0x0 }, | |
206 | { 0x80005012, 0x000000C0, 0x3 }, | |
207 | }; | |
208 | ||
f8896f5d | 209 | /* |
0fdd4918 | 210 | * Skylake/Kabylake H and S |
f8896f5d DW |
211 | * eDP 1.4 low vswing translation parameters |
212 | */ | |
7ad14a29 | 213 | static const struct ddi_buf_trans skl_ddi_translations_edp[] = { |
f8896f5d DW |
214 | { 0x00000018, 0x000000A8, 0x0 }, |
215 | { 0x00004013, 0x000000A9, 0x0 }, | |
216 | { 0x00007011, 0x000000A2, 0x0 }, | |
217 | { 0x00009010, 0x0000009C, 0x0 }, | |
218 | { 0x00000018, 0x000000A9, 0x0 }, | |
219 | { 0x00006013, 0x000000A2, 0x0 }, | |
220 | { 0x00007011, 0x000000A6, 0x0 }, | |
221 | { 0x00000018, 0x000000AB, 0x0 }, | |
222 | { 0x00007013, 0x0000009F, 0x0 }, | |
223 | { 0x00000018, 0x000000DF, 0x0 }, | |
224 | }; | |
225 | ||
226 | /* | |
0fdd4918 | 227 | * Skylake/Kabylake U |
f8896f5d DW |
228 | * eDP 1.4 low vswing translation parameters |
229 | */ | |
230 | static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = { | |
231 | { 0x00000018, 0x000000A8, 0x0 }, | |
232 | { 0x00004013, 0x000000A9, 0x0 }, | |
233 | { 0x00007011, 0x000000A2, 0x0 }, | |
234 | { 0x00009010, 0x0000009C, 0x0 }, | |
235 | { 0x00000018, 0x000000A9, 0x0 }, | |
236 | { 0x00006013, 0x000000A2, 0x0 }, | |
237 | { 0x00007011, 0x000000A6, 0x0 }, | |
238 | { 0x00002016, 0x000000AB, 0x0 }, | |
239 | { 0x00005013, 0x0000009F, 0x0 }, | |
240 | { 0x00000018, 0x000000DF, 0x0 }, | |
7ad14a29 SJ |
241 | }; |
242 | ||
f8896f5d | 243 | /* |
0fdd4918 | 244 | * Skylake/Kabylake Y |
f8896f5d DW |
245 | * eDP 1.4 low vswing translation parameters |
246 | */ | |
5f8b2531 | 247 | static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = { |
f8896f5d DW |
248 | { 0x00000018, 0x000000A8, 0x0 }, |
249 | { 0x00004013, 0x000000AB, 0x0 }, | |
250 | { 0x00007011, 0x000000A4, 0x0 }, | |
251 | { 0x00009010, 0x000000DF, 0x0 }, | |
252 | { 0x00000018, 0x000000AA, 0x0 }, | |
253 | { 0x00006013, 0x000000A4, 0x0 }, | |
254 | { 0x00007011, 0x0000009D, 0x0 }, | |
255 | { 0x00000018, 0x000000A0, 0x0 }, | |
256 | { 0x00006012, 0x000000DF, 0x0 }, | |
257 | { 0x00000018, 0x0000008A, 0x0 }, | |
258 | }; | |
7ad14a29 | 259 | |
0fdd4918 | 260 | /* Skylake/Kabylake U, H and S */ |
7f88e3af | 261 | static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = { |
f8896f5d DW |
262 | { 0x00000018, 0x000000AC, 0x0 }, |
263 | { 0x00005012, 0x0000009D, 0x0 }, | |
264 | { 0x00007011, 0x00000088, 0x0 }, | |
265 | { 0x00000018, 0x000000A1, 0x0 }, | |
266 | { 0x00000018, 0x00000098, 0x0 }, | |
267 | { 0x00004013, 0x00000088, 0x0 }, | |
2e78416e | 268 | { 0x80006012, 0x000000CD, 0x1 }, |
f8896f5d | 269 | { 0x00000018, 0x000000DF, 0x0 }, |
2e78416e RV |
270 | { 0x80003015, 0x000000CD, 0x1 }, /* Default */ |
271 | { 0x80003015, 0x000000C0, 0x1 }, | |
272 | { 0x80000018, 0x000000C0, 0x1 }, | |
f8896f5d DW |
273 | }; |
274 | ||
0fdd4918 | 275 | /* Skylake/Kabylake Y */ |
5f8b2531 | 276 | static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = { |
f8896f5d DW |
277 | { 0x00000018, 0x000000A1, 0x0 }, |
278 | { 0x00005012, 0x000000DF, 0x0 }, | |
2e78416e | 279 | { 0x80007011, 0x000000CB, 0x3 }, |
f8896f5d DW |
280 | { 0x00000018, 0x000000A4, 0x0 }, |
281 | { 0x00000018, 0x0000009D, 0x0 }, | |
282 | { 0x00004013, 0x00000080, 0x0 }, | |
2e78416e | 283 | { 0x80006013, 0x000000C0, 0x3 }, |
f8896f5d | 284 | { 0x00000018, 0x0000008A, 0x0 }, |
2e78416e RV |
285 | { 0x80003015, 0x000000C0, 0x3 }, /* Default */ |
286 | { 0x80003015, 0x000000C0, 0x3 }, | |
287 | { 0x80000018, 0x000000C0, 0x3 }, | |
7f88e3af DL |
288 | }; |
289 | ||
96fb9f9b VK |
290 | struct bxt_ddi_buf_trans { |
291 | u32 margin; /* swing value */ | |
292 | u32 scale; /* scale value */ | |
293 | u32 enable; /* scale enable */ | |
294 | u32 deemphasis; | |
295 | bool default_index; /* true if the entry represents default value */ | |
296 | }; | |
297 | ||
96fb9f9b VK |
298 | static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = { |
299 | /* Idx NT mV diff db */ | |
fe4c63c8 ID |
300 | { 52, 0x9A, 0, 128, true }, /* 0: 400 0 */ |
301 | { 78, 0x9A, 0, 85, false }, /* 1: 400 3.5 */ | |
302 | { 104, 0x9A, 0, 64, false }, /* 2: 400 6 */ | |
303 | { 154, 0x9A, 0, 43, false }, /* 3: 400 9.5 */ | |
304 | { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */ | |
305 | { 116, 0x9A, 0, 85, false }, /* 5: 600 3.5 */ | |
306 | { 154, 0x9A, 0, 64, false }, /* 6: 600 6 */ | |
307 | { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */ | |
308 | { 154, 0x9A, 0, 85, false }, /* 8: 800 3.5 */ | |
f8896f5d | 309 | { 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */ |
96fb9f9b VK |
310 | }; |
311 | ||
d9d7000d SJ |
312 | static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = { |
313 | /* Idx NT mV diff db */ | |
314 | { 26, 0, 0, 128, false }, /* 0: 200 0 */ | |
315 | { 38, 0, 0, 112, false }, /* 1: 200 1.5 */ | |
316 | { 48, 0, 0, 96, false }, /* 2: 200 4 */ | |
317 | { 54, 0, 0, 69, false }, /* 3: 200 6 */ | |
318 | { 32, 0, 0, 128, false }, /* 4: 250 0 */ | |
319 | { 48, 0, 0, 104, false }, /* 5: 250 1.5 */ | |
320 | { 54, 0, 0, 85, false }, /* 6: 250 4 */ | |
321 | { 43, 0, 0, 128, false }, /* 7: 300 0 */ | |
322 | { 54, 0, 0, 101, false }, /* 8: 300 1.5 */ | |
323 | { 48, 0, 0, 128, false }, /* 9: 300 0 */ | |
324 | }; | |
325 | ||
96fb9f9b VK |
326 | /* BSpec has 2 recommended values - entries 0 and 8. |
327 | * Using the entry with higher vswing. | |
328 | */ | |
329 | static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = { | |
330 | /* Idx NT mV diff db */ | |
fe4c63c8 ID |
331 | { 52, 0x9A, 0, 128, false }, /* 0: 400 0 */ |
332 | { 52, 0x9A, 0, 85, false }, /* 1: 400 3.5 */ | |
333 | { 52, 0x9A, 0, 64, false }, /* 2: 400 6 */ | |
334 | { 42, 0x9A, 0, 43, false }, /* 3: 400 9.5 */ | |
335 | { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */ | |
336 | { 77, 0x9A, 0, 85, false }, /* 5: 600 3.5 */ | |
337 | { 77, 0x9A, 0, 64, false }, /* 6: 600 6 */ | |
338 | { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */ | |
339 | { 102, 0x9A, 0, 85, false }, /* 8: 800 3.5 */ | |
96fb9f9b VK |
340 | { 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */ |
341 | }; | |
342 | ||
5a5d24dc | 343 | enum port intel_ddi_get_encoder_port(struct intel_encoder *encoder) |
fc914639 | 344 | { |
5a5d24dc | 345 | switch (encoder->type) { |
8cd21b7f | 346 | case INTEL_OUTPUT_DP_MST: |
5a5d24dc | 347 | return enc_to_mst(&encoder->base)->primary->port; |
cca0502b | 348 | case INTEL_OUTPUT_DP: |
8cd21b7f JN |
349 | case INTEL_OUTPUT_EDP: |
350 | case INTEL_OUTPUT_HDMI: | |
351 | case INTEL_OUTPUT_UNKNOWN: | |
5a5d24dc | 352 | return enc_to_dig_port(&encoder->base)->port; |
8cd21b7f | 353 | case INTEL_OUTPUT_ANALOG: |
5a5d24dc VS |
354 | return PORT_E; |
355 | default: | |
356 | MISSING_CASE(encoder->type); | |
357 | return PORT_A; | |
fc914639 PZ |
358 | } |
359 | } | |
360 | ||
a930acd9 VS |
361 | static const struct ddi_buf_trans * |
362 | bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) | |
363 | { | |
364 | if (dev_priv->vbt.edp.low_vswing) { | |
365 | *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp); | |
366 | return bdw_ddi_translations_edp; | |
367 | } else { | |
368 | *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp); | |
369 | return bdw_ddi_translations_dp; | |
370 | } | |
371 | } | |
372 | ||
acee2998 | 373 | static const struct ddi_buf_trans * |
78ab0bae | 374 | skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) |
f8896f5d | 375 | { |
0fdd4918 | 376 | if (IS_SKL_ULX(dev_priv)) { |
5f8b2531 | 377 | *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp); |
acee2998 | 378 | return skl_y_ddi_translations_dp; |
0fdd4918 | 379 | } else if (IS_SKL_ULT(dev_priv)) { |
f8896f5d | 380 | *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp); |
acee2998 | 381 | return skl_u_ddi_translations_dp; |
f8896f5d | 382 | } else { |
f8896f5d | 383 | *n_entries = ARRAY_SIZE(skl_ddi_translations_dp); |
acee2998 | 384 | return skl_ddi_translations_dp; |
f8896f5d | 385 | } |
f8896f5d DW |
386 | } |
387 | ||
0fdd4918 RV |
388 | static const struct ddi_buf_trans * |
389 | kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) | |
390 | { | |
391 | if (IS_KBL_ULX(dev_priv)) { | |
392 | *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp); | |
393 | return kbl_y_ddi_translations_dp; | |
394 | } else if (IS_KBL_ULT(dev_priv)) { | |
395 | *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp); | |
396 | return kbl_u_ddi_translations_dp; | |
397 | } else { | |
398 | *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp); | |
399 | return kbl_ddi_translations_dp; | |
400 | } | |
401 | } | |
402 | ||
acee2998 | 403 | static const struct ddi_buf_trans * |
78ab0bae | 404 | skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) |
f8896f5d | 405 | { |
06411f08 | 406 | if (dev_priv->vbt.edp.low_vswing) { |
78ab0bae | 407 | if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) { |
5f8b2531 | 408 | *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp); |
acee2998 | 409 | return skl_y_ddi_translations_edp; |
78ab0bae | 410 | } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv)) { |
f8896f5d | 411 | *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp); |
acee2998 | 412 | return skl_u_ddi_translations_edp; |
f8896f5d | 413 | } else { |
f8896f5d | 414 | *n_entries = ARRAY_SIZE(skl_ddi_translations_edp); |
acee2998 | 415 | return skl_ddi_translations_edp; |
f8896f5d DW |
416 | } |
417 | } | |
cd1101cb | 418 | |
0fdd4918 RV |
419 | if (IS_KABYLAKE(dev_priv)) |
420 | return kbl_get_buf_trans_dp(dev_priv, n_entries); | |
421 | else | |
422 | return skl_get_buf_trans_dp(dev_priv, n_entries); | |
f8896f5d DW |
423 | } |
424 | ||
425 | static const struct ddi_buf_trans * | |
78ab0bae | 426 | skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) |
f8896f5d | 427 | { |
78ab0bae | 428 | if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) { |
5f8b2531 | 429 | *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi); |
acee2998 | 430 | return skl_y_ddi_translations_hdmi; |
f8896f5d | 431 | } else { |
f8896f5d | 432 | *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi); |
acee2998 | 433 | return skl_ddi_translations_hdmi; |
f8896f5d | 434 | } |
f8896f5d DW |
435 | } |
436 | ||
8d8bb85e VS |
437 | static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port) |
438 | { | |
439 | int n_hdmi_entries; | |
440 | int hdmi_level; | |
441 | int hdmi_default_entry; | |
442 | ||
443 | hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift; | |
444 | ||
445 | if (IS_BROXTON(dev_priv)) | |
446 | return hdmi_level; | |
447 | ||
448 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { | |
449 | skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries); | |
450 | hdmi_default_entry = 8; | |
451 | } else if (IS_BROADWELL(dev_priv)) { | |
452 | n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); | |
453 | hdmi_default_entry = 7; | |
454 | } else if (IS_HASWELL(dev_priv)) { | |
455 | n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi); | |
456 | hdmi_default_entry = 6; | |
457 | } else { | |
458 | WARN(1, "ddi translation table missing\n"); | |
459 | n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); | |
460 | hdmi_default_entry = 7; | |
461 | } | |
462 | ||
463 | /* Choose a good default if VBT is badly populated */ | |
464 | if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN || | |
465 | hdmi_level >= n_hdmi_entries) | |
466 | hdmi_level = hdmi_default_entry; | |
467 | ||
468 | return hdmi_level; | |
469 | } | |
470 | ||
e58623cb AR |
471 | /* |
472 | * Starting with Haswell, DDI port buffers must be programmed with correct | |
32bdc400 VS |
473 | * values in advance. This function programs the correct values for |
474 | * DP/eDP/FDI use cases. | |
45244b87 | 475 | */ |
32bdc400 | 476 | void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder) |
45244b87 | 477 | { |
6a7e4f99 | 478 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
75067dde | 479 | u32 iboost_bit = 0; |
32bdc400 VS |
480 | int i, n_dp_entries, n_edp_entries, size; |
481 | enum port port = intel_ddi_get_encoder_port(encoder); | |
10122051 JN |
482 | const struct ddi_buf_trans *ddi_translations_fdi; |
483 | const struct ddi_buf_trans *ddi_translations_dp; | |
484 | const struct ddi_buf_trans *ddi_translations_edp; | |
10122051 | 485 | const struct ddi_buf_trans *ddi_translations; |
e58623cb | 486 | |
9f332437 | 487 | if (IS_BROXTON(dev_priv)) |
96fb9f9b | 488 | return; |
6a7e4f99 | 489 | |
0fdd4918 RV |
490 | if (IS_KABYLAKE(dev_priv)) { |
491 | ddi_translations_fdi = NULL; | |
492 | ddi_translations_dp = | |
493 | kbl_get_buf_trans_dp(dev_priv, &n_dp_entries); | |
494 | ddi_translations_edp = | |
495 | skl_get_buf_trans_edp(dev_priv, &n_edp_entries); | |
496 | } else if (IS_SKYLAKE(dev_priv)) { | |
c30400fc | 497 | ddi_translations_fdi = NULL; |
f8896f5d | 498 | ddi_translations_dp = |
78ab0bae | 499 | skl_get_buf_trans_dp(dev_priv, &n_dp_entries); |
f8896f5d | 500 | ddi_translations_edp = |
78ab0bae | 501 | skl_get_buf_trans_edp(dev_priv, &n_edp_entries); |
78ab0bae | 502 | } else if (IS_BROADWELL(dev_priv)) { |
e58623cb AR |
503 | ddi_translations_fdi = bdw_ddi_translations_fdi; |
504 | ddi_translations_dp = bdw_ddi_translations_dp; | |
a930acd9 | 505 | ddi_translations_edp = bdw_get_buf_trans_edp(dev_priv, &n_edp_entries); |
7ad14a29 | 506 | n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp); |
78ab0bae | 507 | } else if (IS_HASWELL(dev_priv)) { |
e58623cb AR |
508 | ddi_translations_fdi = hsw_ddi_translations_fdi; |
509 | ddi_translations_dp = hsw_ddi_translations_dp; | |
300644c7 | 510 | ddi_translations_edp = hsw_ddi_translations_dp; |
7ad14a29 | 511 | n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp); |
e58623cb AR |
512 | } else { |
513 | WARN(1, "ddi translation table missing\n"); | |
300644c7 | 514 | ddi_translations_edp = bdw_ddi_translations_dp; |
e58623cb AR |
515 | ddi_translations_fdi = bdw_ddi_translations_fdi; |
516 | ddi_translations_dp = bdw_ddi_translations_dp; | |
7ad14a29 SJ |
517 | n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp); |
518 | n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp); | |
e58623cb AR |
519 | } |
520 | ||
0a91877c RV |
521 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { |
522 | /* If we're boosting the current, set bit 31 of trans1 */ | |
523 | if (dev_priv->vbt.ddi_port_info[port].dp_boost_level) | |
524 | iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; | |
525 | ||
526 | if (WARN_ON(encoder->type == INTEL_OUTPUT_EDP && | |
527 | port != PORT_A && port != PORT_E && | |
528 | n_edp_entries > 9)) | |
529 | n_edp_entries = 9; | |
530 | } | |
531 | ||
6a7e4f99 VS |
532 | switch (encoder->type) { |
533 | case INTEL_OUTPUT_EDP: | |
300644c7 | 534 | ddi_translations = ddi_translations_edp; |
7ad14a29 | 535 | size = n_edp_entries; |
300644c7 | 536 | break; |
cca0502b | 537 | case INTEL_OUTPUT_DP: |
300644c7 | 538 | ddi_translations = ddi_translations_dp; |
7ad14a29 | 539 | size = n_dp_entries; |
300644c7 | 540 | break; |
6a7e4f99 VS |
541 | case INTEL_OUTPUT_ANALOG: |
542 | ddi_translations = ddi_translations_fdi; | |
7ad14a29 | 543 | size = n_dp_entries; |
300644c7 PZ |
544 | break; |
545 | default: | |
546 | BUG(); | |
547 | } | |
45244b87 | 548 | |
9712e688 VS |
549 | for (i = 0; i < size; i++) { |
550 | I915_WRITE(DDI_BUF_TRANS_LO(port, i), | |
551 | ddi_translations[i].trans1 | iboost_bit); | |
552 | I915_WRITE(DDI_BUF_TRANS_HI(port, i), | |
553 | ddi_translations[i].trans2); | |
45244b87 | 554 | } |
32bdc400 VS |
555 | } |
556 | ||
557 | /* | |
558 | * Starting with Haswell, DDI port buffers must be programmed with correct | |
559 | * values in advance. This function programs the correct values for | |
560 | * HDMI/DVI use cases. | |
561 | */ | |
562 | static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder) | |
563 | { | |
564 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
565 | u32 iboost_bit = 0; | |
566 | int n_hdmi_entries, hdmi_level; | |
567 | enum port port = intel_ddi_get_encoder_port(encoder); | |
568 | const struct ddi_buf_trans *ddi_translations_hdmi; | |
ce4dd49e | 569 | |
32bdc400 | 570 | if (IS_BROXTON(dev_priv)) |
ce3b7e9b DL |
571 | return; |
572 | ||
32bdc400 VS |
573 | hdmi_level = intel_ddi_hdmi_level(dev_priv, port); |
574 | ||
575 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { | |
576 | ddi_translations_hdmi = skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries); | |
1edaaa2f | 577 | |
32bdc400 | 578 | /* If we're boosting the current, set bit 31 of trans1 */ |
1edaaa2f | 579 | if (dev_priv->vbt.ddi_port_info[port].hdmi_boost_level) |
32bdc400 VS |
580 | iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; |
581 | } else if (IS_BROADWELL(dev_priv)) { | |
582 | ddi_translations_hdmi = bdw_ddi_translations_hdmi; | |
583 | n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); | |
584 | } else if (IS_HASWELL(dev_priv)) { | |
585 | ddi_translations_hdmi = hsw_ddi_translations_hdmi; | |
586 | n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi); | |
587 | } else { | |
588 | WARN(1, "ddi translation table missing\n"); | |
589 | ddi_translations_hdmi = bdw_ddi_translations_hdmi; | |
590 | n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); | |
591 | } | |
592 | ||
6acab15a | 593 | /* Entry 9 is for HDMI: */ |
ed9c77d2 | 594 | I915_WRITE(DDI_BUF_TRANS_LO(port, 9), |
9712e688 | 595 | ddi_translations_hdmi[hdmi_level].trans1 | iboost_bit); |
ed9c77d2 | 596 | I915_WRITE(DDI_BUF_TRANS_HI(port, 9), |
9712e688 | 597 | ddi_translations_hdmi[hdmi_level].trans2); |
45244b87 ED |
598 | } |
599 | ||
248138b5 PZ |
600 | static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, |
601 | enum port port) | |
602 | { | |
f0f59a00 | 603 | i915_reg_t reg = DDI_BUF_CTL(port); |
248138b5 PZ |
604 | int i; |
605 | ||
3449ca85 | 606 | for (i = 0; i < 16; i++) { |
248138b5 PZ |
607 | udelay(1); |
608 | if (I915_READ(reg) & DDI_BUF_IS_IDLE) | |
609 | return; | |
610 | } | |
611 | DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port)); | |
612 | } | |
c82e4d26 | 613 | |
c856052a ACO |
614 | static uint32_t hsw_pll_to_ddi_pll_sel(struct intel_shared_dpll *pll) |
615 | { | |
616 | switch (pll->id) { | |
617 | case DPLL_ID_WRPLL1: | |
618 | return PORT_CLK_SEL_WRPLL1; | |
619 | case DPLL_ID_WRPLL2: | |
620 | return PORT_CLK_SEL_WRPLL2; | |
621 | case DPLL_ID_SPLL: | |
622 | return PORT_CLK_SEL_SPLL; | |
623 | case DPLL_ID_LCPLL_810: | |
624 | return PORT_CLK_SEL_LCPLL_810; | |
625 | case DPLL_ID_LCPLL_1350: | |
626 | return PORT_CLK_SEL_LCPLL_1350; | |
627 | case DPLL_ID_LCPLL_2700: | |
628 | return PORT_CLK_SEL_LCPLL_2700; | |
629 | default: | |
630 | MISSING_CASE(pll->id); | |
631 | return PORT_CLK_SEL_NONE; | |
632 | } | |
633 | } | |
634 | ||
c82e4d26 ED |
635 | /* Starting with Haswell, different DDI ports can work in FDI mode for |
636 | * connection to the PCH-located connectors. For this, it is necessary to train | |
637 | * both the DDI port and PCH receiver for the desired DDI buffer settings. | |
638 | * | |
639 | * The recommended port to work in FDI mode is DDI E, which we use here. Also, | |
640 | * please note that when FDI mode is active on DDI E, it shares 2 lines with | |
641 | * DDI A (which is used for eDP) | |
642 | */ | |
643 | ||
644 | void hsw_fdi_link_train(struct drm_crtc *crtc) | |
645 | { | |
646 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 647 | struct drm_i915_private *dev_priv = to_i915(dev); |
c82e4d26 | 648 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6a7e4f99 | 649 | struct intel_encoder *encoder; |
c856052a | 650 | u32 temp, i, rx_ctl_val, ddi_pll_sel; |
c82e4d26 | 651 | |
6a7e4f99 VS |
652 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
653 | WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG); | |
32bdc400 | 654 | intel_prepare_dp_ddi_buffers(encoder); |
6a7e4f99 VS |
655 | } |
656 | ||
04945641 PZ |
657 | /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the |
658 | * mode set "sequence for CRT port" document: | |
659 | * - TP1 to TP2 time with the default value | |
660 | * - FDI delay to 90h | |
8693a824 DL |
661 | * |
662 | * WaFDIAutoLinkSetTimingOverrride:hsw | |
04945641 | 663 | */ |
eede3b53 | 664 | I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) | |
04945641 PZ |
665 | FDI_RX_PWRDN_LANE0_VAL(2) | |
666 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
667 | ||
668 | /* Enable the PCH Receiver FDI PLL */ | |
3e68320e | 669 | rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE | |
33d29b14 | 670 | FDI_RX_PLL_ENABLE | |
6e3c9717 | 671 | FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
eede3b53 VS |
672 | I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); |
673 | POSTING_READ(FDI_RX_CTL(PIPE_A)); | |
04945641 PZ |
674 | udelay(220); |
675 | ||
676 | /* Switch from Rawclk to PCDclk */ | |
677 | rx_ctl_val |= FDI_PCDCLK; | |
eede3b53 | 678 | I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); |
04945641 PZ |
679 | |
680 | /* Configure Port Clock Select */ | |
c856052a ACO |
681 | ddi_pll_sel = hsw_pll_to_ddi_pll_sel(intel_crtc->config->shared_dpll); |
682 | I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel); | |
683 | WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL); | |
04945641 PZ |
684 | |
685 | /* Start the training iterating through available voltages and emphasis, | |
686 | * testing each value twice. */ | |
10122051 | 687 | for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) { |
c82e4d26 ED |
688 | /* Configure DP_TP_CTL with auto-training */ |
689 | I915_WRITE(DP_TP_CTL(PORT_E), | |
690 | DP_TP_CTL_FDI_AUTOTRAIN | | |
691 | DP_TP_CTL_ENHANCED_FRAME_ENABLE | | |
692 | DP_TP_CTL_LINK_TRAIN_PAT1 | | |
693 | DP_TP_CTL_ENABLE); | |
694 | ||
876a8cdf DL |
695 | /* Configure and enable DDI_BUF_CTL for DDI E with next voltage. |
696 | * DDI E does not support port reversal, the functionality is | |
697 | * achieved on the PCH side in FDI_RX_CTL, so no need to set the | |
698 | * port reversal bit */ | |
c82e4d26 | 699 | I915_WRITE(DDI_BUF_CTL(PORT_E), |
04945641 | 700 | DDI_BUF_CTL_ENABLE | |
6e3c9717 | 701 | ((intel_crtc->config->fdi_lanes - 1) << 1) | |
c5fe6a06 | 702 | DDI_BUF_TRANS_SELECT(i / 2)); |
04945641 | 703 | POSTING_READ(DDI_BUF_CTL(PORT_E)); |
c82e4d26 ED |
704 | |
705 | udelay(600); | |
706 | ||
04945641 | 707 | /* Program PCH FDI Receiver TU */ |
eede3b53 | 708 | I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64)); |
04945641 PZ |
709 | |
710 | /* Enable PCH FDI Receiver with auto-training */ | |
711 | rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO; | |
eede3b53 VS |
712 | I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); |
713 | POSTING_READ(FDI_RX_CTL(PIPE_A)); | |
04945641 PZ |
714 | |
715 | /* Wait for FDI receiver lane calibration */ | |
716 | udelay(30); | |
717 | ||
718 | /* Unset FDI_RX_MISC pwrdn lanes */ | |
eede3b53 | 719 | temp = I915_READ(FDI_RX_MISC(PIPE_A)); |
04945641 | 720 | temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); |
eede3b53 VS |
721 | I915_WRITE(FDI_RX_MISC(PIPE_A), temp); |
722 | POSTING_READ(FDI_RX_MISC(PIPE_A)); | |
04945641 PZ |
723 | |
724 | /* Wait for FDI auto training time */ | |
725 | udelay(5); | |
c82e4d26 ED |
726 | |
727 | temp = I915_READ(DP_TP_STATUS(PORT_E)); | |
728 | if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) { | |
04945641 | 729 | DRM_DEBUG_KMS("FDI link training done on step %d\n", i); |
a308ccb3 VS |
730 | break; |
731 | } | |
c82e4d26 | 732 | |
a308ccb3 VS |
733 | /* |
734 | * Leave things enabled even if we failed to train FDI. | |
735 | * Results in less fireworks from the state checker. | |
736 | */ | |
737 | if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) { | |
738 | DRM_ERROR("FDI link training failed!\n"); | |
739 | break; | |
c82e4d26 | 740 | } |
04945641 | 741 | |
5b421c57 VS |
742 | rx_ctl_val &= ~FDI_RX_ENABLE; |
743 | I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); | |
744 | POSTING_READ(FDI_RX_CTL(PIPE_A)); | |
745 | ||
248138b5 PZ |
746 | temp = I915_READ(DDI_BUF_CTL(PORT_E)); |
747 | temp &= ~DDI_BUF_CTL_ENABLE; | |
748 | I915_WRITE(DDI_BUF_CTL(PORT_E), temp); | |
749 | POSTING_READ(DDI_BUF_CTL(PORT_E)); | |
750 | ||
04945641 | 751 | /* Disable DP_TP_CTL and FDI_RX_CTL and retry */ |
248138b5 PZ |
752 | temp = I915_READ(DP_TP_CTL(PORT_E)); |
753 | temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); | |
754 | temp |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
755 | I915_WRITE(DP_TP_CTL(PORT_E), temp); | |
756 | POSTING_READ(DP_TP_CTL(PORT_E)); | |
757 | ||
758 | intel_wait_ddi_buf_idle(dev_priv, PORT_E); | |
04945641 | 759 | |
04945641 | 760 | /* Reset FDI_RX_MISC pwrdn lanes */ |
eede3b53 | 761 | temp = I915_READ(FDI_RX_MISC(PIPE_A)); |
04945641 PZ |
762 | temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); |
763 | temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); | |
eede3b53 VS |
764 | I915_WRITE(FDI_RX_MISC(PIPE_A), temp); |
765 | POSTING_READ(FDI_RX_MISC(PIPE_A)); | |
c82e4d26 ED |
766 | } |
767 | ||
a308ccb3 VS |
768 | /* Enable normal pixel sending for FDI */ |
769 | I915_WRITE(DP_TP_CTL(PORT_E), | |
770 | DP_TP_CTL_FDI_AUTOTRAIN | | |
771 | DP_TP_CTL_LINK_TRAIN_NORMAL | | |
772 | DP_TP_CTL_ENHANCED_FRAME_ENABLE | | |
773 | DP_TP_CTL_ENABLE); | |
c82e4d26 | 774 | } |
0e72a5b5 | 775 | |
44905a27 DA |
776 | void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder) |
777 | { | |
778 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
779 | struct intel_digital_port *intel_dig_port = | |
780 | enc_to_dig_port(&encoder->base); | |
781 | ||
782 | intel_dp->DP = intel_dig_port->saved_port_bits | | |
c5fe6a06 | 783 | DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0); |
901c2daf | 784 | intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count); |
44905a27 DA |
785 | } |
786 | ||
8d9ddbcb PZ |
787 | static struct intel_encoder * |
788 | intel_ddi_get_crtc_encoder(struct drm_crtc *crtc) | |
789 | { | |
790 | struct drm_device *dev = crtc->dev; | |
791 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
792 | struct intel_encoder *intel_encoder, *ret = NULL; | |
793 | int num_encoders = 0; | |
794 | ||
795 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { | |
796 | ret = intel_encoder; | |
797 | num_encoders++; | |
798 | } | |
799 | ||
800 | if (num_encoders != 1) | |
84f44ce7 VS |
801 | WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders, |
802 | pipe_name(intel_crtc->pipe)); | |
8d9ddbcb PZ |
803 | |
804 | BUG_ON(ret == NULL); | |
805 | return ret; | |
806 | } | |
807 | ||
bcddf610 | 808 | struct intel_encoder * |
3165c074 | 809 | intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state) |
d0737e1d | 810 | { |
3165c074 ACO |
811 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
812 | struct intel_encoder *ret = NULL; | |
813 | struct drm_atomic_state *state; | |
da3ced29 ACO |
814 | struct drm_connector *connector; |
815 | struct drm_connector_state *connector_state; | |
d0737e1d | 816 | int num_encoders = 0; |
3165c074 | 817 | int i; |
d0737e1d | 818 | |
3165c074 ACO |
819 | state = crtc_state->base.state; |
820 | ||
da3ced29 ACO |
821 | for_each_connector_in_state(state, connector, connector_state, i) { |
822 | if (connector_state->crtc != crtc_state->base.crtc) | |
3165c074 ACO |
823 | continue; |
824 | ||
da3ced29 | 825 | ret = to_intel_encoder(connector_state->best_encoder); |
3165c074 | 826 | num_encoders++; |
d0737e1d ACO |
827 | } |
828 | ||
829 | WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders, | |
830 | pipe_name(crtc->pipe)); | |
831 | ||
832 | BUG_ON(ret == NULL); | |
833 | return ret; | |
834 | } | |
835 | ||
1c0b85c5 | 836 | #define LC_FREQ 2700 |
1c0b85c5 | 837 | |
f0f59a00 VS |
838 | static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv, |
839 | i915_reg_t reg) | |
11578553 JB |
840 | { |
841 | int refclk = LC_FREQ; | |
842 | int n, p, r; | |
843 | u32 wrpll; | |
844 | ||
845 | wrpll = I915_READ(reg); | |
114fe488 DV |
846 | switch (wrpll & WRPLL_PLL_REF_MASK) { |
847 | case WRPLL_PLL_SSC: | |
848 | case WRPLL_PLL_NON_SSC: | |
11578553 JB |
849 | /* |
850 | * We could calculate spread here, but our checking | |
851 | * code only cares about 5% accuracy, and spread is a max of | |
852 | * 0.5% downspread. | |
853 | */ | |
854 | refclk = 135; | |
855 | break; | |
114fe488 | 856 | case WRPLL_PLL_LCPLL: |
11578553 JB |
857 | refclk = LC_FREQ; |
858 | break; | |
859 | default: | |
860 | WARN(1, "bad wrpll refclk\n"); | |
861 | return 0; | |
862 | } | |
863 | ||
864 | r = wrpll & WRPLL_DIVIDER_REF_MASK; | |
865 | p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT; | |
866 | n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT; | |
867 | ||
20f0ec16 JB |
868 | /* Convert to KHz, p & r have a fixed point portion */ |
869 | return (refclk * n * 100) / (p * r); | |
11578553 JB |
870 | } |
871 | ||
540e732c S |
872 | static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv, |
873 | uint32_t dpll) | |
874 | { | |
f0f59a00 | 875 | i915_reg_t cfgcr1_reg, cfgcr2_reg; |
540e732c S |
876 | uint32_t cfgcr1_val, cfgcr2_val; |
877 | uint32_t p0, p1, p2, dco_freq; | |
878 | ||
923c1241 VS |
879 | cfgcr1_reg = DPLL_CFGCR1(dpll); |
880 | cfgcr2_reg = DPLL_CFGCR2(dpll); | |
540e732c S |
881 | |
882 | cfgcr1_val = I915_READ(cfgcr1_reg); | |
883 | cfgcr2_val = I915_READ(cfgcr2_reg); | |
884 | ||
885 | p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK; | |
886 | p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK; | |
887 | ||
888 | if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1)) | |
889 | p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8; | |
890 | else | |
891 | p1 = 1; | |
892 | ||
893 | ||
894 | switch (p0) { | |
895 | case DPLL_CFGCR2_PDIV_1: | |
896 | p0 = 1; | |
897 | break; | |
898 | case DPLL_CFGCR2_PDIV_2: | |
899 | p0 = 2; | |
900 | break; | |
901 | case DPLL_CFGCR2_PDIV_3: | |
902 | p0 = 3; | |
903 | break; | |
904 | case DPLL_CFGCR2_PDIV_7: | |
905 | p0 = 7; | |
906 | break; | |
907 | } | |
908 | ||
909 | switch (p2) { | |
910 | case DPLL_CFGCR2_KDIV_5: | |
911 | p2 = 5; | |
912 | break; | |
913 | case DPLL_CFGCR2_KDIV_2: | |
914 | p2 = 2; | |
915 | break; | |
916 | case DPLL_CFGCR2_KDIV_3: | |
917 | p2 = 3; | |
918 | break; | |
919 | case DPLL_CFGCR2_KDIV_1: | |
920 | p2 = 1; | |
921 | break; | |
922 | } | |
923 | ||
924 | dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000; | |
925 | ||
926 | dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 * | |
927 | 1000) / 0x8000; | |
928 | ||
929 | return dco_freq / (p0 * p1 * p2 * 5); | |
930 | } | |
931 | ||
398a017e VS |
932 | static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) |
933 | { | |
934 | int dotclock; | |
935 | ||
936 | if (pipe_config->has_pch_encoder) | |
937 | dotclock = intel_dotclock_calculate(pipe_config->port_clock, | |
938 | &pipe_config->fdi_m_n); | |
37a5650b | 939 | else if (intel_crtc_has_dp_encoder(pipe_config)) |
398a017e VS |
940 | dotclock = intel_dotclock_calculate(pipe_config->port_clock, |
941 | &pipe_config->dp_m_n); | |
942 | else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36) | |
943 | dotclock = pipe_config->port_clock * 2 / 3; | |
944 | else | |
945 | dotclock = pipe_config->port_clock; | |
946 | ||
947 | if (pipe_config->pixel_multiplier) | |
948 | dotclock /= pipe_config->pixel_multiplier; | |
949 | ||
950 | pipe_config->base.adjusted_mode.crtc_clock = dotclock; | |
951 | } | |
540e732c S |
952 | |
953 | static void skl_ddi_clock_get(struct intel_encoder *encoder, | |
5cec258b | 954 | struct intel_crtc_state *pipe_config) |
540e732c | 955 | { |
fac5e23e | 956 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
540e732c S |
957 | int link_clock = 0; |
958 | uint32_t dpll_ctl1, dpll; | |
959 | ||
c856052a | 960 | dpll = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll); |
540e732c S |
961 | |
962 | dpll_ctl1 = I915_READ(DPLL_CTRL1); | |
963 | ||
964 | if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) { | |
965 | link_clock = skl_calc_wrpll_link(dev_priv, dpll); | |
966 | } else { | |
71cd8423 DL |
967 | link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll); |
968 | link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll); | |
540e732c S |
969 | |
970 | switch (link_clock) { | |
71cd8423 | 971 | case DPLL_CTRL1_LINK_RATE_810: |
540e732c S |
972 | link_clock = 81000; |
973 | break; | |
71cd8423 | 974 | case DPLL_CTRL1_LINK_RATE_1080: |
a8f3ef61 SJ |
975 | link_clock = 108000; |
976 | break; | |
71cd8423 | 977 | case DPLL_CTRL1_LINK_RATE_1350: |
540e732c S |
978 | link_clock = 135000; |
979 | break; | |
71cd8423 | 980 | case DPLL_CTRL1_LINK_RATE_1620: |
a8f3ef61 SJ |
981 | link_clock = 162000; |
982 | break; | |
71cd8423 | 983 | case DPLL_CTRL1_LINK_RATE_2160: |
a8f3ef61 SJ |
984 | link_clock = 216000; |
985 | break; | |
71cd8423 | 986 | case DPLL_CTRL1_LINK_RATE_2700: |
540e732c S |
987 | link_clock = 270000; |
988 | break; | |
989 | default: | |
990 | WARN(1, "Unsupported link rate\n"); | |
991 | break; | |
992 | } | |
993 | link_clock *= 2; | |
994 | } | |
995 | ||
996 | pipe_config->port_clock = link_clock; | |
997 | ||
398a017e | 998 | ddi_dotclock_get(pipe_config); |
540e732c S |
999 | } |
1000 | ||
3d51278a | 1001 | static void hsw_ddi_clock_get(struct intel_encoder *encoder, |
5cec258b | 1002 | struct intel_crtc_state *pipe_config) |
11578553 | 1003 | { |
fac5e23e | 1004 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
11578553 JB |
1005 | int link_clock = 0; |
1006 | u32 val, pll; | |
1007 | ||
c856052a | 1008 | val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll); |
11578553 JB |
1009 | switch (val & PORT_CLK_SEL_MASK) { |
1010 | case PORT_CLK_SEL_LCPLL_810: | |
1011 | link_clock = 81000; | |
1012 | break; | |
1013 | case PORT_CLK_SEL_LCPLL_1350: | |
1014 | link_clock = 135000; | |
1015 | break; | |
1016 | case PORT_CLK_SEL_LCPLL_2700: | |
1017 | link_clock = 270000; | |
1018 | break; | |
1019 | case PORT_CLK_SEL_WRPLL1: | |
01403de3 | 1020 | link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0)); |
11578553 JB |
1021 | break; |
1022 | case PORT_CLK_SEL_WRPLL2: | |
01403de3 | 1023 | link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1)); |
11578553 JB |
1024 | break; |
1025 | case PORT_CLK_SEL_SPLL: | |
1026 | pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK; | |
1027 | if (pll == SPLL_PLL_FREQ_810MHz) | |
1028 | link_clock = 81000; | |
1029 | else if (pll == SPLL_PLL_FREQ_1350MHz) | |
1030 | link_clock = 135000; | |
1031 | else if (pll == SPLL_PLL_FREQ_2700MHz) | |
1032 | link_clock = 270000; | |
1033 | else { | |
1034 | WARN(1, "bad spll freq\n"); | |
1035 | return; | |
1036 | } | |
1037 | break; | |
1038 | default: | |
1039 | WARN(1, "bad port clock sel\n"); | |
1040 | return; | |
1041 | } | |
1042 | ||
1043 | pipe_config->port_clock = link_clock * 2; | |
1044 | ||
398a017e | 1045 | ddi_dotclock_get(pipe_config); |
11578553 JB |
1046 | } |
1047 | ||
977bb38d S |
1048 | static int bxt_calc_pll_link(struct drm_i915_private *dev_priv, |
1049 | enum intel_dpll_id dpll) | |
1050 | { | |
aa610dcb ID |
1051 | struct intel_shared_dpll *pll; |
1052 | struct intel_dpll_hw_state *state; | |
9e2c8475 | 1053 | struct dpll clock; |
aa610dcb ID |
1054 | |
1055 | /* For DDI ports we always use a shared PLL. */ | |
1056 | if (WARN_ON(dpll == DPLL_ID_PRIVATE)) | |
1057 | return 0; | |
1058 | ||
1059 | pll = &dev_priv->shared_dplls[dpll]; | |
1060 | state = &pll->config.hw_state; | |
1061 | ||
1062 | clock.m1 = 2; | |
1063 | clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22; | |
1064 | if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE) | |
1065 | clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK; | |
1066 | clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT; | |
1067 | clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT; | |
1068 | clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT; | |
1069 | ||
1070 | return chv_calc_dpll_params(100000, &clock); | |
977bb38d S |
1071 | } |
1072 | ||
1073 | static void bxt_ddi_clock_get(struct intel_encoder *encoder, | |
1074 | struct intel_crtc_state *pipe_config) | |
1075 | { | |
fac5e23e | 1076 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
977bb38d S |
1077 | enum port port = intel_ddi_get_encoder_port(encoder); |
1078 | uint32_t dpll = port; | |
1079 | ||
398a017e | 1080 | pipe_config->port_clock = bxt_calc_pll_link(dev_priv, dpll); |
977bb38d | 1081 | |
398a017e | 1082 | ddi_dotclock_get(pipe_config); |
977bb38d S |
1083 | } |
1084 | ||
3d51278a | 1085 | void intel_ddi_clock_get(struct intel_encoder *encoder, |
5cec258b | 1086 | struct intel_crtc_state *pipe_config) |
3d51278a | 1087 | { |
0853723b | 1088 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
22606a18 | 1089 | |
0853723b | 1090 | if (INTEL_GEN(dev_priv) <= 8) |
22606a18 | 1091 | hsw_ddi_clock_get(encoder, pipe_config); |
0853723b | 1092 | else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) |
22606a18 | 1093 | skl_ddi_clock_get(encoder, pipe_config); |
0853723b | 1094 | else if (IS_BROXTON(dev_priv)) |
977bb38d | 1095 | bxt_ddi_clock_get(encoder, pipe_config); |
3d51278a DV |
1096 | } |
1097 | ||
0220ab6e | 1098 | static bool |
d664c0ce | 1099 | hsw_ddi_pll_select(struct intel_crtc *intel_crtc, |
190f68c5 | 1100 | struct intel_crtc_state *crtc_state, |
96f3f1f9 | 1101 | struct intel_encoder *intel_encoder) |
6441ab5f | 1102 | { |
daedf20a | 1103 | struct intel_shared_dpll *pll; |
6441ab5f | 1104 | |
9d16da65 ACO |
1105 | pll = intel_get_shared_dpll(intel_crtc, crtc_state, |
1106 | intel_encoder); | |
1107 | if (!pll) | |
1108 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", | |
1109 | pipe_name(intel_crtc->pipe)); | |
1110 | ||
1111 | return pll; | |
6441ab5f PZ |
1112 | } |
1113 | ||
82d35437 S |
1114 | static bool |
1115 | skl_ddi_pll_select(struct intel_crtc *intel_crtc, | |
190f68c5 | 1116 | struct intel_crtc_state *crtc_state, |
96f3f1f9 | 1117 | struct intel_encoder *intel_encoder) |
82d35437 S |
1118 | { |
1119 | struct intel_shared_dpll *pll; | |
82d35437 | 1120 | |
daedf20a | 1121 | pll = intel_get_shared_dpll(intel_crtc, crtc_state, intel_encoder); |
82d35437 S |
1122 | if (pll == NULL) { |
1123 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", | |
1124 | pipe_name(intel_crtc->pipe)); | |
1125 | return false; | |
1126 | } | |
1127 | ||
82d35437 S |
1128 | return true; |
1129 | } | |
0220ab6e | 1130 | |
d683f3bc S |
1131 | static bool |
1132 | bxt_ddi_pll_select(struct intel_crtc *intel_crtc, | |
1133 | struct intel_crtc_state *crtc_state, | |
96f3f1f9 | 1134 | struct intel_encoder *intel_encoder) |
d683f3bc | 1135 | { |
34177c24 | 1136 | return !!intel_get_shared_dpll(intel_crtc, crtc_state, intel_encoder); |
d683f3bc S |
1137 | } |
1138 | ||
0220ab6e DL |
1139 | /* |
1140 | * Tries to find a *shared* PLL for the CRTC and store it in | |
1141 | * intel_crtc->ddi_pll_sel. | |
1142 | * | |
1143 | * For private DPLLs, compute_config() should do the selection for us. This | |
1144 | * function should be folded into compute_config() eventually. | |
1145 | */ | |
190f68c5 ACO |
1146 | bool intel_ddi_pll_select(struct intel_crtc *intel_crtc, |
1147 | struct intel_crtc_state *crtc_state) | |
0220ab6e | 1148 | { |
0853723b | 1149 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); |
d0737e1d | 1150 | struct intel_encoder *intel_encoder = |
3165c074 | 1151 | intel_ddi_get_crtc_new_encoder(crtc_state); |
0220ab6e | 1152 | |
0853723b | 1153 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) |
190f68c5 | 1154 | return skl_ddi_pll_select(intel_crtc, crtc_state, |
96f3f1f9 | 1155 | intel_encoder); |
0853723b | 1156 | else if (IS_BROXTON(dev_priv)) |
d683f3bc | 1157 | return bxt_ddi_pll_select(intel_crtc, crtc_state, |
96f3f1f9 | 1158 | intel_encoder); |
82d35437 | 1159 | else |
190f68c5 | 1160 | return hsw_ddi_pll_select(intel_crtc, crtc_state, |
96f3f1f9 | 1161 | intel_encoder); |
0220ab6e DL |
1162 | } |
1163 | ||
dae84799 PZ |
1164 | void intel_ddi_set_pipe_settings(struct drm_crtc *crtc) |
1165 | { | |
fac5e23e | 1166 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
dae84799 PZ |
1167 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
1168 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
6e3c9717 | 1169 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
dae84799 PZ |
1170 | int type = intel_encoder->type; |
1171 | uint32_t temp; | |
1172 | ||
cca0502b | 1173 | if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) { |
4d1de975 JN |
1174 | WARN_ON(transcoder_is_dsi(cpu_transcoder)); |
1175 | ||
c9809791 | 1176 | temp = TRANS_MSA_SYNC_CLK; |
6e3c9717 | 1177 | switch (intel_crtc->config->pipe_bpp) { |
dae84799 | 1178 | case 18: |
c9809791 | 1179 | temp |= TRANS_MSA_6_BPC; |
dae84799 PZ |
1180 | break; |
1181 | case 24: | |
c9809791 | 1182 | temp |= TRANS_MSA_8_BPC; |
dae84799 PZ |
1183 | break; |
1184 | case 30: | |
c9809791 | 1185 | temp |= TRANS_MSA_10_BPC; |
dae84799 PZ |
1186 | break; |
1187 | case 36: | |
c9809791 | 1188 | temp |= TRANS_MSA_12_BPC; |
dae84799 PZ |
1189 | break; |
1190 | default: | |
4e53c2e0 | 1191 | BUG(); |
dae84799 | 1192 | } |
c9809791 | 1193 | I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp); |
dae84799 PZ |
1194 | } |
1195 | } | |
1196 | ||
0e32b39c DA |
1197 | void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state) |
1198 | { | |
1199 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1200 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 1201 | struct drm_i915_private *dev_priv = to_i915(dev); |
6e3c9717 | 1202 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
0e32b39c DA |
1203 | uint32_t temp; |
1204 | temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); | |
1205 | if (state == true) | |
1206 | temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC; | |
1207 | else | |
1208 | temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC; | |
1209 | I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); | |
1210 | } | |
1211 | ||
8228c251 | 1212 | void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc) |
8d9ddbcb PZ |
1213 | { |
1214 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1215 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
c7670b10 | 1216 | struct drm_device *dev = crtc->dev; |
fac5e23e | 1217 | struct drm_i915_private *dev_priv = to_i915(dev); |
8d9ddbcb | 1218 | enum pipe pipe = intel_crtc->pipe; |
6e3c9717 | 1219 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
174edf1f | 1220 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
7739c33b | 1221 | int type = intel_encoder->type; |
8d9ddbcb PZ |
1222 | uint32_t temp; |
1223 | ||
ad80a810 PZ |
1224 | /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ |
1225 | temp = TRANS_DDI_FUNC_ENABLE; | |
174edf1f | 1226 | temp |= TRANS_DDI_SELECT_PORT(port); |
dfcef252 | 1227 | |
6e3c9717 | 1228 | switch (intel_crtc->config->pipe_bpp) { |
dfcef252 | 1229 | case 18: |
ad80a810 | 1230 | temp |= TRANS_DDI_BPC_6; |
dfcef252 PZ |
1231 | break; |
1232 | case 24: | |
ad80a810 | 1233 | temp |= TRANS_DDI_BPC_8; |
dfcef252 PZ |
1234 | break; |
1235 | case 30: | |
ad80a810 | 1236 | temp |= TRANS_DDI_BPC_10; |
dfcef252 PZ |
1237 | break; |
1238 | case 36: | |
ad80a810 | 1239 | temp |= TRANS_DDI_BPC_12; |
dfcef252 PZ |
1240 | break; |
1241 | default: | |
4e53c2e0 | 1242 | BUG(); |
dfcef252 | 1243 | } |
72662e10 | 1244 | |
6e3c9717 | 1245 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) |
ad80a810 | 1246 | temp |= TRANS_DDI_PVSYNC; |
6e3c9717 | 1247 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) |
ad80a810 | 1248 | temp |= TRANS_DDI_PHSYNC; |
f63eb7c4 | 1249 | |
e6f0bfc4 PZ |
1250 | if (cpu_transcoder == TRANSCODER_EDP) { |
1251 | switch (pipe) { | |
1252 | case PIPE_A: | |
c7670b10 PZ |
1253 | /* On Haswell, can only use the always-on power well for |
1254 | * eDP when not using the panel fitter, and when not | |
1255 | * using motion blur mitigation (which we don't | |
1256 | * support). */ | |
772c2a51 | 1257 | if (IS_HASWELL(dev_priv) && |
6e3c9717 ACO |
1258 | (intel_crtc->config->pch_pfit.enabled || |
1259 | intel_crtc->config->pch_pfit.force_thru)) | |
d6dd9eb1 DV |
1260 | temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; |
1261 | else | |
1262 | temp |= TRANS_DDI_EDP_INPUT_A_ON; | |
e6f0bfc4 PZ |
1263 | break; |
1264 | case PIPE_B: | |
1265 | temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; | |
1266 | break; | |
1267 | case PIPE_C: | |
1268 | temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; | |
1269 | break; | |
1270 | default: | |
1271 | BUG(); | |
1272 | break; | |
1273 | } | |
1274 | } | |
1275 | ||
7739c33b | 1276 | if (type == INTEL_OUTPUT_HDMI) { |
6e3c9717 | 1277 | if (intel_crtc->config->has_hdmi_sink) |
ad80a810 | 1278 | temp |= TRANS_DDI_MODE_SELECT_HDMI; |
8d9ddbcb | 1279 | else |
ad80a810 | 1280 | temp |= TRANS_DDI_MODE_SELECT_DVI; |
7739c33b | 1281 | } else if (type == INTEL_OUTPUT_ANALOG) { |
ad80a810 | 1282 | temp |= TRANS_DDI_MODE_SELECT_FDI; |
6e3c9717 | 1283 | temp |= (intel_crtc->config->fdi_lanes - 1) << 1; |
cca0502b | 1284 | } else if (type == INTEL_OUTPUT_DP || |
7739c33b | 1285 | type == INTEL_OUTPUT_EDP) { |
64ee2fd2 | 1286 | temp |= TRANS_DDI_MODE_SELECT_DP_SST; |
90a6b7b0 | 1287 | temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count); |
0e32b39c | 1288 | } else if (type == INTEL_OUTPUT_DP_MST) { |
64ee2fd2 | 1289 | temp |= TRANS_DDI_MODE_SELECT_DP_MST; |
90a6b7b0 | 1290 | temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count); |
8d9ddbcb | 1291 | } else { |
84f44ce7 VS |
1292 | WARN(1, "Invalid encoder type %d for pipe %c\n", |
1293 | intel_encoder->type, pipe_name(pipe)); | |
8d9ddbcb PZ |
1294 | } |
1295 | ||
ad80a810 | 1296 | I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); |
8d9ddbcb | 1297 | } |
72662e10 | 1298 | |
ad80a810 PZ |
1299 | void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, |
1300 | enum transcoder cpu_transcoder) | |
8d9ddbcb | 1301 | { |
f0f59a00 | 1302 | i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
8d9ddbcb PZ |
1303 | uint32_t val = I915_READ(reg); |
1304 | ||
0e32b39c | 1305 | val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC); |
ad80a810 | 1306 | val |= TRANS_DDI_PORT_NONE; |
8d9ddbcb | 1307 | I915_WRITE(reg, val); |
72662e10 ED |
1308 | } |
1309 | ||
bcbc889b PZ |
1310 | bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) |
1311 | { | |
1312 | struct drm_device *dev = intel_connector->base.dev; | |
fac5e23e | 1313 | struct drm_i915_private *dev_priv = to_i915(dev); |
bcbc889b PZ |
1314 | struct intel_encoder *intel_encoder = intel_connector->encoder; |
1315 | int type = intel_connector->base.connector_type; | |
1316 | enum port port = intel_ddi_get_encoder_port(intel_encoder); | |
1317 | enum pipe pipe = 0; | |
1318 | enum transcoder cpu_transcoder; | |
882244a3 | 1319 | enum intel_display_power_domain power_domain; |
bcbc889b | 1320 | uint32_t tmp; |
e27daab4 | 1321 | bool ret; |
bcbc889b | 1322 | |
882244a3 | 1323 | power_domain = intel_display_port_power_domain(intel_encoder); |
e27daab4 | 1324 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) |
882244a3 PZ |
1325 | return false; |
1326 | ||
e27daab4 ID |
1327 | if (!intel_encoder->get_hw_state(intel_encoder, &pipe)) { |
1328 | ret = false; | |
1329 | goto out; | |
1330 | } | |
bcbc889b PZ |
1331 | |
1332 | if (port == PORT_A) | |
1333 | cpu_transcoder = TRANSCODER_EDP; | |
1334 | else | |
1a240d4d | 1335 | cpu_transcoder = (enum transcoder) pipe; |
bcbc889b PZ |
1336 | |
1337 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); | |
1338 | ||
1339 | switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { | |
1340 | case TRANS_DDI_MODE_SELECT_HDMI: | |
1341 | case TRANS_DDI_MODE_SELECT_DVI: | |
e27daab4 ID |
1342 | ret = type == DRM_MODE_CONNECTOR_HDMIA; |
1343 | break; | |
bcbc889b PZ |
1344 | |
1345 | case TRANS_DDI_MODE_SELECT_DP_SST: | |
e27daab4 ID |
1346 | ret = type == DRM_MODE_CONNECTOR_eDP || |
1347 | type == DRM_MODE_CONNECTOR_DisplayPort; | |
1348 | break; | |
1349 | ||
0e32b39c DA |
1350 | case TRANS_DDI_MODE_SELECT_DP_MST: |
1351 | /* if the transcoder is in MST state then | |
1352 | * connector isn't connected */ | |
e27daab4 ID |
1353 | ret = false; |
1354 | break; | |
bcbc889b PZ |
1355 | |
1356 | case TRANS_DDI_MODE_SELECT_FDI: | |
e27daab4 ID |
1357 | ret = type == DRM_MODE_CONNECTOR_VGA; |
1358 | break; | |
bcbc889b PZ |
1359 | |
1360 | default: | |
e27daab4 ID |
1361 | ret = false; |
1362 | break; | |
bcbc889b | 1363 | } |
e27daab4 ID |
1364 | |
1365 | out: | |
1366 | intel_display_power_put(dev_priv, power_domain); | |
1367 | ||
1368 | return ret; | |
bcbc889b PZ |
1369 | } |
1370 | ||
85234cdc DV |
1371 | bool intel_ddi_get_hw_state(struct intel_encoder *encoder, |
1372 | enum pipe *pipe) | |
1373 | { | |
1374 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 1375 | struct drm_i915_private *dev_priv = to_i915(dev); |
fe43d3f5 | 1376 | enum port port = intel_ddi_get_encoder_port(encoder); |
6d129bea | 1377 | enum intel_display_power_domain power_domain; |
85234cdc DV |
1378 | u32 tmp; |
1379 | int i; | |
e27daab4 | 1380 | bool ret; |
85234cdc | 1381 | |
6d129bea | 1382 | power_domain = intel_display_port_power_domain(encoder); |
e27daab4 | 1383 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) |
6d129bea ID |
1384 | return false; |
1385 | ||
e27daab4 ID |
1386 | ret = false; |
1387 | ||
fe43d3f5 | 1388 | tmp = I915_READ(DDI_BUF_CTL(port)); |
85234cdc DV |
1389 | |
1390 | if (!(tmp & DDI_BUF_CTL_ENABLE)) | |
e27daab4 | 1391 | goto out; |
85234cdc | 1392 | |
ad80a810 PZ |
1393 | if (port == PORT_A) { |
1394 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); | |
85234cdc | 1395 | |
ad80a810 PZ |
1396 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { |
1397 | case TRANS_DDI_EDP_INPUT_A_ON: | |
1398 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
1399 | *pipe = PIPE_A; | |
1400 | break; | |
1401 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
1402 | *pipe = PIPE_B; | |
1403 | break; | |
1404 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
1405 | *pipe = PIPE_C; | |
1406 | break; | |
1407 | } | |
1408 | ||
e27daab4 | 1409 | ret = true; |
ad80a810 | 1410 | |
e27daab4 ID |
1411 | goto out; |
1412 | } | |
0e32b39c | 1413 | |
e27daab4 ID |
1414 | for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) { |
1415 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(i)); | |
1416 | ||
1417 | if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(port)) { | |
1418 | if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == | |
1419 | TRANS_DDI_MODE_SELECT_DP_MST) | |
1420 | goto out; | |
1421 | ||
1422 | *pipe = i; | |
1423 | ret = true; | |
1424 | ||
1425 | goto out; | |
85234cdc DV |
1426 | } |
1427 | } | |
1428 | ||
84f44ce7 | 1429 | DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port)); |
85234cdc | 1430 | |
e27daab4 | 1431 | out: |
e93da0a0 ID |
1432 | if (ret && IS_BROXTON(dev_priv)) { |
1433 | tmp = I915_READ(BXT_PHY_CTL(port)); | |
1434 | if ((tmp & (BXT_PHY_LANE_POWERDOWN_ACK | | |
1435 | BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED) | |
1436 | DRM_ERROR("Port %c enabled but PHY powered down? " | |
1437 | "(PHY_CTL %08x)\n", port_name(port), tmp); | |
1438 | } | |
1439 | ||
e27daab4 ID |
1440 | intel_display_power_put(dev_priv, power_domain); |
1441 | ||
1442 | return ret; | |
85234cdc DV |
1443 | } |
1444 | ||
fc914639 PZ |
1445 | void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc) |
1446 | { | |
1447 | struct drm_crtc *crtc = &intel_crtc->base; | |
7d4aefd0 | 1448 | struct drm_device *dev = crtc->dev; |
fac5e23e | 1449 | struct drm_i915_private *dev_priv = to_i915(dev); |
fc914639 PZ |
1450 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); |
1451 | enum port port = intel_ddi_get_encoder_port(intel_encoder); | |
6e3c9717 | 1452 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
fc914639 | 1453 | |
bb523fc0 PZ |
1454 | if (cpu_transcoder != TRANSCODER_EDP) |
1455 | I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), | |
1456 | TRANS_CLK_SEL_PORT(port)); | |
fc914639 PZ |
1457 | } |
1458 | ||
1459 | void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc) | |
1460 | { | |
fac5e23e | 1461 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); |
6e3c9717 | 1462 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
fc914639 | 1463 | |
bb523fc0 PZ |
1464 | if (cpu_transcoder != TRANSCODER_EDP) |
1465 | I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), | |
1466 | TRANS_CLK_SEL_DISABLED); | |
fc914639 PZ |
1467 | } |
1468 | ||
a7d8dbc0 VS |
1469 | static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv, |
1470 | enum port port, uint8_t iboost) | |
f8896f5d | 1471 | { |
a7d8dbc0 VS |
1472 | u32 tmp; |
1473 | ||
1474 | tmp = I915_READ(DISPIO_CR_TX_BMU_CR0); | |
1475 | tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port)); | |
1476 | if (iboost) | |
1477 | tmp |= iboost << BALANCE_LEG_SHIFT(port); | |
1478 | else | |
1479 | tmp |= BALANCE_LEG_DISABLE(port); | |
1480 | I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp); | |
1481 | } | |
1482 | ||
1483 | static void skl_ddi_set_iboost(struct intel_encoder *encoder, u32 level) | |
1484 | { | |
1485 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base); | |
1486 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); | |
1487 | enum port port = intel_dig_port->port; | |
1488 | int type = encoder->type; | |
f8896f5d DW |
1489 | const struct ddi_buf_trans *ddi_translations; |
1490 | uint8_t iboost; | |
75067dde | 1491 | uint8_t dp_iboost, hdmi_iboost; |
f8896f5d | 1492 | int n_entries; |
f8896f5d | 1493 | |
75067dde AK |
1494 | /* VBT may override standard boost values */ |
1495 | dp_iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level; | |
1496 | hdmi_iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level; | |
1497 | ||
cca0502b | 1498 | if (type == INTEL_OUTPUT_DP) { |
75067dde AK |
1499 | if (dp_iboost) { |
1500 | iboost = dp_iboost; | |
1501 | } else { | |
0fdd4918 RV |
1502 | if (IS_KABYLAKE(dev_priv)) |
1503 | ddi_translations = kbl_get_buf_trans_dp(dev_priv, | |
1504 | &n_entries); | |
1505 | else | |
1506 | ddi_translations = skl_get_buf_trans_dp(dev_priv, | |
1507 | &n_entries); | |
e4d4c05b | 1508 | iboost = ddi_translations[level].i_boost; |
75067dde | 1509 | } |
f8896f5d | 1510 | } else if (type == INTEL_OUTPUT_EDP) { |
75067dde AK |
1511 | if (dp_iboost) { |
1512 | iboost = dp_iboost; | |
1513 | } else { | |
78ab0bae | 1514 | ddi_translations = skl_get_buf_trans_edp(dev_priv, &n_entries); |
10afa0b6 VS |
1515 | |
1516 | if (WARN_ON(port != PORT_A && | |
1517 | port != PORT_E && n_entries > 9)) | |
1518 | n_entries = 9; | |
1519 | ||
e4d4c05b | 1520 | iboost = ddi_translations[level].i_boost; |
75067dde | 1521 | } |
f8896f5d | 1522 | } else if (type == INTEL_OUTPUT_HDMI) { |
75067dde AK |
1523 | if (hdmi_iboost) { |
1524 | iboost = hdmi_iboost; | |
1525 | } else { | |
78ab0bae | 1526 | ddi_translations = skl_get_buf_trans_hdmi(dev_priv, &n_entries); |
e4d4c05b | 1527 | iboost = ddi_translations[level].i_boost; |
75067dde | 1528 | } |
f8896f5d DW |
1529 | } else { |
1530 | return; | |
1531 | } | |
1532 | ||
1533 | /* Make sure that the requested I_boost is valid */ | |
1534 | if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { | |
1535 | DRM_ERROR("Invalid I_boost value %u\n", iboost); | |
1536 | return; | |
1537 | } | |
1538 | ||
a7d8dbc0 | 1539 | _skl_ddi_set_iboost(dev_priv, port, iboost); |
f8896f5d | 1540 | |
a7d8dbc0 VS |
1541 | if (port == PORT_A && intel_dig_port->max_lanes == 4) |
1542 | _skl_ddi_set_iboost(dev_priv, PORT_E, iboost); | |
f8896f5d DW |
1543 | } |
1544 | ||
78ab0bae VS |
1545 | static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv, |
1546 | u32 level, enum port port, int type) | |
96fb9f9b | 1547 | { |
96fb9f9b VK |
1548 | const struct bxt_ddi_buf_trans *ddi_translations; |
1549 | u32 n_entries, i; | |
1550 | uint32_t val; | |
1551 | ||
06411f08 | 1552 | if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) { |
d9d7000d SJ |
1553 | n_entries = ARRAY_SIZE(bxt_ddi_translations_edp); |
1554 | ddi_translations = bxt_ddi_translations_edp; | |
cca0502b | 1555 | } else if (type == INTEL_OUTPUT_DP |
d9d7000d | 1556 | || type == INTEL_OUTPUT_EDP) { |
96fb9f9b VK |
1557 | n_entries = ARRAY_SIZE(bxt_ddi_translations_dp); |
1558 | ddi_translations = bxt_ddi_translations_dp; | |
1559 | } else if (type == INTEL_OUTPUT_HDMI) { | |
1560 | n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi); | |
1561 | ddi_translations = bxt_ddi_translations_hdmi; | |
1562 | } else { | |
1563 | DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n", | |
1564 | type); | |
1565 | return; | |
1566 | } | |
1567 | ||
1568 | /* Check if default value has to be used */ | |
1569 | if (level >= n_entries || | |
1570 | (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) { | |
1571 | for (i = 0; i < n_entries; i++) { | |
1572 | if (ddi_translations[i].default_index) { | |
1573 | level = i; | |
1574 | break; | |
1575 | } | |
1576 | } | |
1577 | } | |
1578 | ||
1579 | /* | |
1580 | * While we write to the group register to program all lanes at once we | |
1581 | * can read only lane registers and we pick lanes 0/1 for that. | |
1582 | */ | |
1583 | val = I915_READ(BXT_PORT_PCS_DW10_LN01(port)); | |
1584 | val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT); | |
1585 | I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val); | |
1586 | ||
1587 | val = I915_READ(BXT_PORT_TX_DW2_LN0(port)); | |
1588 | val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE); | |
1589 | val |= ddi_translations[level].margin << MARGIN_000_SHIFT | | |
1590 | ddi_translations[level].scale << UNIQ_TRANS_SCALE_SHIFT; | |
1591 | I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val); | |
1592 | ||
1593 | val = I915_READ(BXT_PORT_TX_DW3_LN0(port)); | |
9c58a049 | 1594 | val &= ~SCALE_DCOMP_METHOD; |
96fb9f9b | 1595 | if (ddi_translations[level].enable) |
9c58a049 SJ |
1596 | val |= SCALE_DCOMP_METHOD; |
1597 | ||
1598 | if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD)) | |
1599 | DRM_ERROR("Disabled scaling while ouniqetrangenmethod was set"); | |
1600 | ||
96fb9f9b VK |
1601 | I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val); |
1602 | ||
1603 | val = I915_READ(BXT_PORT_TX_DW4_LN0(port)); | |
1604 | val &= ~DE_EMPHASIS; | |
1605 | val |= ddi_translations[level].deemphasis << DEEMPH_SHIFT; | |
1606 | I915_WRITE(BXT_PORT_TX_DW4_GRP(port), val); | |
1607 | ||
1608 | val = I915_READ(BXT_PORT_PCS_DW10_LN01(port)); | |
1609 | val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT; | |
1610 | I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val); | |
1611 | } | |
1612 | ||
f8896f5d DW |
1613 | static uint32_t translate_signal_level(int signal_levels) |
1614 | { | |
1615 | uint32_t level; | |
1616 | ||
1617 | switch (signal_levels) { | |
1618 | default: | |
1619 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level: 0x%x\n", | |
1620 | signal_levels); | |
1621 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: | |
1622 | level = 0; | |
1623 | break; | |
1624 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: | |
1625 | level = 1; | |
1626 | break; | |
1627 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: | |
1628 | level = 2; | |
1629 | break; | |
1630 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3: | |
1631 | level = 3; | |
1632 | break; | |
1633 | ||
1634 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: | |
1635 | level = 4; | |
1636 | break; | |
1637 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: | |
1638 | level = 5; | |
1639 | break; | |
1640 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2: | |
1641 | level = 6; | |
1642 | break; | |
1643 | ||
1644 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: | |
1645 | level = 7; | |
1646 | break; | |
1647 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: | |
1648 | level = 8; | |
1649 | break; | |
1650 | ||
1651 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0: | |
1652 | level = 9; | |
1653 | break; | |
1654 | } | |
1655 | ||
1656 | return level; | |
1657 | } | |
1658 | ||
1659 | uint32_t ddi_signal_levels(struct intel_dp *intel_dp) | |
1660 | { | |
1661 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); | |
78ab0bae | 1662 | struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev); |
f8896f5d DW |
1663 | struct intel_encoder *encoder = &dport->base; |
1664 | uint8_t train_set = intel_dp->train_set[0]; | |
1665 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | | |
1666 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
1667 | enum port port = dport->port; | |
1668 | uint32_t level; | |
1669 | ||
1670 | level = translate_signal_level(signal_levels); | |
1671 | ||
78ab0bae | 1672 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) |
a7d8dbc0 | 1673 | skl_ddi_set_iboost(encoder, level); |
78ab0bae VS |
1674 | else if (IS_BROXTON(dev_priv)) |
1675 | bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type); | |
f8896f5d DW |
1676 | |
1677 | return DDI_BUF_TRANS_SELECT(level); | |
1678 | } | |
1679 | ||
e404ba8d | 1680 | void intel_ddi_clk_select(struct intel_encoder *encoder, |
c856052a | 1681 | struct intel_shared_dpll *pll) |
6441ab5f | 1682 | { |
e404ba8d VS |
1683 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
1684 | enum port port = intel_ddi_get_encoder_port(encoder); | |
6441ab5f | 1685 | |
c856052a ACO |
1686 | if (WARN_ON(!pll)) |
1687 | return; | |
1688 | ||
e404ba8d | 1689 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { |
efa80add S |
1690 | uint32_t val; |
1691 | ||
5416d871 | 1692 | /* DDI -> PLL mapping */ |
efa80add S |
1693 | val = I915_READ(DPLL_CTRL2); |
1694 | ||
1695 | val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) | | |
1696 | DPLL_CTRL2_DDI_CLK_SEL_MASK(port)); | |
c856052a | 1697 | val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->id, port) | |
efa80add S |
1698 | DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); |
1699 | ||
1700 | I915_WRITE(DPLL_CTRL2, val); | |
5416d871 | 1701 | |
e404ba8d | 1702 | } else if (INTEL_INFO(dev_priv)->gen < 9) { |
c856052a | 1703 | I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll)); |
efa80add | 1704 | } |
e404ba8d VS |
1705 | } |
1706 | ||
ba88d153 MN |
1707 | static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder, |
1708 | int link_rate, uint32_t lane_count, | |
1709 | struct intel_shared_dpll *pll, | |
1710 | bool link_mst) | |
e404ba8d | 1711 | { |
ba88d153 MN |
1712 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
1713 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
1714 | enum port port = intel_ddi_get_encoder_port(encoder); | |
b2ccb822 | 1715 | |
ba88d153 MN |
1716 | intel_dp_set_link_params(intel_dp, link_rate, lane_count, |
1717 | link_mst); | |
1718 | if (encoder->type == INTEL_OUTPUT_EDP) | |
e404ba8d | 1719 | intel_edp_panel_on(intel_dp); |
32bdc400 | 1720 | |
ba88d153 MN |
1721 | intel_ddi_clk_select(encoder, pll); |
1722 | intel_prepare_dp_ddi_buffers(encoder); | |
1723 | intel_ddi_init_dp_buf_reg(encoder); | |
1724 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); | |
1725 | intel_dp_start_link_train(intel_dp); | |
1726 | if (port != PORT_A || INTEL_GEN(dev_priv) >= 9) | |
1727 | intel_dp_stop_link_train(intel_dp); | |
1728 | } | |
901c2daf | 1729 | |
ba88d153 MN |
1730 | static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder, |
1731 | bool has_hdmi_sink, | |
1732 | struct drm_display_mode *adjusted_mode, | |
1733 | struct intel_shared_dpll *pll) | |
1734 | { | |
1735 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
1736 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
1737 | struct drm_encoder *drm_encoder = &encoder->base; | |
1738 | enum port port = intel_ddi_get_encoder_port(encoder); | |
1739 | int level = intel_ddi_hdmi_level(dev_priv, port); | |
c19b0669 | 1740 | |
ba88d153 MN |
1741 | intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); |
1742 | intel_ddi_clk_select(encoder, pll); | |
1743 | intel_prepare_hdmi_ddi_buffers(encoder); | |
1744 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) | |
1745 | skl_ddi_set_iboost(encoder, level); | |
1746 | else if (IS_BROXTON(dev_priv)) | |
1747 | bxt_ddi_vswing_sequence(dev_priv, level, port, | |
1748 | INTEL_OUTPUT_HDMI); | |
8d8bb85e | 1749 | |
ba88d153 MN |
1750 | intel_hdmi->set_infoframes(drm_encoder, |
1751 | has_hdmi_sink, | |
1752 | adjusted_mode); | |
1753 | } | |
32bdc400 | 1754 | |
ba88d153 MN |
1755 | static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder, |
1756 | struct intel_crtc_state *pipe_config, | |
1757 | struct drm_connector_state *conn_state) | |
1758 | { | |
1759 | struct drm_encoder *encoder = &intel_encoder->base; | |
1760 | struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); | |
1761 | int type = intel_encoder->type; | |
30cf6db8 | 1762 | |
ba88d153 MN |
1763 | if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) { |
1764 | intel_ddi_pre_enable_dp(intel_encoder, | |
1765 | crtc->config->port_clock, | |
1766 | crtc->config->lane_count, | |
1767 | crtc->config->shared_dpll, | |
1768 | intel_crtc_has_type(crtc->config, | |
1769 | INTEL_OUTPUT_DP_MST)); | |
1770 | } | |
1771 | if (type == INTEL_OUTPUT_HDMI) { | |
1772 | intel_ddi_pre_enable_hdmi(intel_encoder, | |
1773 | crtc->config->has_hdmi_sink, | |
1774 | &crtc->config->base.adjusted_mode, | |
1775 | crtc->config->shared_dpll); | |
c19b0669 | 1776 | } |
6441ab5f PZ |
1777 | } |
1778 | ||
fd6bbda9 ML |
1779 | static void intel_ddi_post_disable(struct intel_encoder *intel_encoder, |
1780 | struct intel_crtc_state *old_crtc_state, | |
1781 | struct drm_connector_state *old_conn_state) | |
6441ab5f PZ |
1782 | { |
1783 | struct drm_encoder *encoder = &intel_encoder->base; | |
efa80add | 1784 | struct drm_device *dev = encoder->dev; |
fac5e23e | 1785 | struct drm_i915_private *dev_priv = to_i915(dev); |
6441ab5f | 1786 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
82a4d9c0 | 1787 | int type = intel_encoder->type; |
2886e93f | 1788 | uint32_t val; |
a836bdf9 | 1789 | bool wait = false; |
2886e93f | 1790 | |
fd6bbda9 ML |
1791 | /* old_crtc_state and old_conn_state are NULL when called from DP_MST */ |
1792 | ||
2886e93f PZ |
1793 | val = I915_READ(DDI_BUF_CTL(port)); |
1794 | if (val & DDI_BUF_CTL_ENABLE) { | |
1795 | val &= ~DDI_BUF_CTL_ENABLE; | |
1796 | I915_WRITE(DDI_BUF_CTL(port), val); | |
a836bdf9 | 1797 | wait = true; |
2886e93f | 1798 | } |
6441ab5f | 1799 | |
a836bdf9 PZ |
1800 | val = I915_READ(DP_TP_CTL(port)); |
1801 | val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); | |
1802 | val |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
1803 | I915_WRITE(DP_TP_CTL(port), val); | |
1804 | ||
1805 | if (wait) | |
1806 | intel_wait_ddi_buf_idle(dev_priv, port); | |
1807 | ||
cca0502b | 1808 | if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) { |
82a4d9c0 | 1809 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
76bb80ed | 1810 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); |
24f3e092 | 1811 | intel_edp_panel_vdd_on(intel_dp); |
4be73780 | 1812 | intel_edp_panel_off(intel_dp); |
82a4d9c0 PZ |
1813 | } |
1814 | ||
0853723b | 1815 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) |
efa80add S |
1816 | I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) | |
1817 | DPLL_CTRL2_DDI_CLK_OFF(port))); | |
1ab23380 | 1818 | else if (INTEL_INFO(dev)->gen < 9) |
efa80add | 1819 | I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); |
b2ccb822 VS |
1820 | |
1821 | if (type == INTEL_OUTPUT_HDMI) { | |
1822 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
1823 | ||
1824 | intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); | |
1825 | } | |
6441ab5f PZ |
1826 | } |
1827 | ||
b7076546 ML |
1828 | void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder, |
1829 | struct intel_crtc_state *old_crtc_state, | |
1830 | struct drm_connector_state *old_conn_state) | |
1831 | { | |
1832 | struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); | |
1833 | uint32_t val; | |
1834 | ||
1835 | /* | |
1836 | * Bspec lists this as both step 13 (before DDI_BUF_CTL disable) | |
1837 | * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN, | |
1838 | * step 13 is the correct place for it. Step 18 is where it was | |
1839 | * originally before the BUN. | |
1840 | */ | |
1841 | val = I915_READ(FDI_RX_CTL(PIPE_A)); | |
1842 | val &= ~FDI_RX_ENABLE; | |
1843 | I915_WRITE(FDI_RX_CTL(PIPE_A), val); | |
1844 | ||
1845 | intel_ddi_post_disable(intel_encoder, old_crtc_state, old_conn_state); | |
1846 | ||
1847 | val = I915_READ(FDI_RX_MISC(PIPE_A)); | |
1848 | val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); | |
1849 | val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); | |
1850 | I915_WRITE(FDI_RX_MISC(PIPE_A), val); | |
1851 | ||
1852 | val = I915_READ(FDI_RX_CTL(PIPE_A)); | |
1853 | val &= ~FDI_PCDCLK; | |
1854 | I915_WRITE(FDI_RX_CTL(PIPE_A), val); | |
1855 | ||
1856 | val = I915_READ(FDI_RX_CTL(PIPE_A)); | |
1857 | val &= ~FDI_RX_PLL_ENABLE; | |
1858 | I915_WRITE(FDI_RX_CTL(PIPE_A), val); | |
1859 | } | |
1860 | ||
fd6bbda9 ML |
1861 | static void intel_enable_ddi(struct intel_encoder *intel_encoder, |
1862 | struct intel_crtc_state *pipe_config, | |
1863 | struct drm_connector_state *conn_state) | |
72662e10 | 1864 | { |
6547fef8 | 1865 | struct drm_encoder *encoder = &intel_encoder->base; |
7b9f35a6 WX |
1866 | struct drm_crtc *crtc = encoder->crtc; |
1867 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6547fef8 | 1868 | struct drm_device *dev = encoder->dev; |
fac5e23e | 1869 | struct drm_i915_private *dev_priv = to_i915(dev); |
6547fef8 PZ |
1870 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
1871 | int type = intel_encoder->type; | |
72662e10 | 1872 | |
6547fef8 | 1873 | if (type == INTEL_OUTPUT_HDMI) { |
876a8cdf DL |
1874 | struct intel_digital_port *intel_dig_port = |
1875 | enc_to_dig_port(encoder); | |
1876 | ||
6547fef8 PZ |
1877 | /* In HDMI/DVI mode, the port width, and swing/emphasis values |
1878 | * are ignored so nothing special needs to be done besides | |
1879 | * enabling the port. | |
1880 | */ | |
876a8cdf | 1881 | I915_WRITE(DDI_BUF_CTL(port), |
bcf53de4 SM |
1882 | intel_dig_port->saved_port_bits | |
1883 | DDI_BUF_CTL_ENABLE); | |
d6c50ff8 PZ |
1884 | } else if (type == INTEL_OUTPUT_EDP) { |
1885 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
1886 | ||
23f08d83 | 1887 | if (port == PORT_A && INTEL_INFO(dev)->gen < 9) |
3ab9c637 ID |
1888 | intel_dp_stop_link_train(intel_dp); |
1889 | ||
4be73780 | 1890 | intel_edp_backlight_on(intel_dp); |
0bc12bcb | 1891 | intel_psr_enable(intel_dp); |
85cb48a1 | 1892 | intel_edp_drrs_enable(intel_dp, pipe_config); |
6547fef8 | 1893 | } |
7b9f35a6 | 1894 | |
6e3c9717 | 1895 | if (intel_crtc->config->has_audio) { |
d45a0bf5 | 1896 | intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO); |
69bfe1a9 | 1897 | intel_audio_codec_enable(intel_encoder); |
7b9f35a6 | 1898 | } |
5ab432ef DV |
1899 | } |
1900 | ||
fd6bbda9 ML |
1901 | static void intel_disable_ddi(struct intel_encoder *intel_encoder, |
1902 | struct intel_crtc_state *old_crtc_state, | |
1903 | struct drm_connector_state *old_conn_state) | |
5ab432ef | 1904 | { |
d6c50ff8 | 1905 | struct drm_encoder *encoder = &intel_encoder->base; |
7b9f35a6 WX |
1906 | struct drm_crtc *crtc = encoder->crtc; |
1907 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
d6c50ff8 | 1908 | int type = intel_encoder->type; |
7b9f35a6 | 1909 | struct drm_device *dev = encoder->dev; |
fac5e23e | 1910 | struct drm_i915_private *dev_priv = to_i915(dev); |
d6c50ff8 | 1911 | |
6e3c9717 | 1912 | if (intel_crtc->config->has_audio) { |
69bfe1a9 | 1913 | intel_audio_codec_disable(intel_encoder); |
d45a0bf5 PZ |
1914 | intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO); |
1915 | } | |
2831d842 | 1916 | |
d6c50ff8 PZ |
1917 | if (type == INTEL_OUTPUT_EDP) { |
1918 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
1919 | ||
85cb48a1 | 1920 | intel_edp_drrs_disable(intel_dp, old_crtc_state); |
0bc12bcb | 1921 | intel_psr_disable(intel_dp); |
4be73780 | 1922 | intel_edp_backlight_off(intel_dp); |
d6c50ff8 | 1923 | } |
72662e10 | 1924 | } |
79f689aa | 1925 | |
fd6bbda9 ML |
1926 | static void bxt_ddi_pre_pll_enable(struct intel_encoder *encoder, |
1927 | struct intel_crtc_state *pipe_config, | |
1928 | struct drm_connector_state *conn_state) | |
95a7a2ae | 1929 | { |
95a7a2ae | 1930 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
47a6bc61 | 1931 | uint8_t mask = intel_crtc->config->lane_lat_optim_mask; |
95a7a2ae | 1932 | |
47a6bc61 | 1933 | bxt_ddi_phy_set_lane_optim_mask(encoder, mask); |
95a7a2ae ID |
1934 | } |
1935 | ||
ad64217b | 1936 | void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp) |
c19b0669 | 1937 | { |
ad64217b ACO |
1938 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1939 | struct drm_i915_private *dev_priv = | |
1940 | to_i915(intel_dig_port->base.base.dev); | |
174edf1f | 1941 | enum port port = intel_dig_port->port; |
c19b0669 | 1942 | uint32_t val; |
f3e227df | 1943 | bool wait = false; |
c19b0669 PZ |
1944 | |
1945 | if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) { | |
1946 | val = I915_READ(DDI_BUF_CTL(port)); | |
1947 | if (val & DDI_BUF_CTL_ENABLE) { | |
1948 | val &= ~DDI_BUF_CTL_ENABLE; | |
1949 | I915_WRITE(DDI_BUF_CTL(port), val); | |
1950 | wait = true; | |
1951 | } | |
1952 | ||
1953 | val = I915_READ(DP_TP_CTL(port)); | |
1954 | val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); | |
1955 | val |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
1956 | I915_WRITE(DP_TP_CTL(port), val); | |
1957 | POSTING_READ(DP_TP_CTL(port)); | |
1958 | ||
1959 | if (wait) | |
1960 | intel_wait_ddi_buf_idle(dev_priv, port); | |
1961 | } | |
1962 | ||
0e32b39c | 1963 | val = DP_TP_CTL_ENABLE | |
c19b0669 | 1964 | DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE; |
64ee2fd2 | 1965 | if (intel_dp->link_mst) |
0e32b39c DA |
1966 | val |= DP_TP_CTL_MODE_MST; |
1967 | else { | |
1968 | val |= DP_TP_CTL_MODE_SST; | |
1969 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) | |
1970 | val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; | |
1971 | } | |
c19b0669 PZ |
1972 | I915_WRITE(DP_TP_CTL(port), val); |
1973 | POSTING_READ(DP_TP_CTL(port)); | |
1974 | ||
1975 | intel_dp->DP |= DDI_BUF_CTL_ENABLE; | |
1976 | I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP); | |
1977 | POSTING_READ(DDI_BUF_CTL(port)); | |
1978 | ||
1979 | udelay(600); | |
1980 | } | |
00c09d70 | 1981 | |
6801c18c | 1982 | void intel_ddi_get_config(struct intel_encoder *encoder, |
5cec258b | 1983 | struct intel_crtc_state *pipe_config) |
045ac3b5 | 1984 | { |
fac5e23e | 1985 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
045ac3b5 | 1986 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
0cb09a97 | 1987 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; |
bbd440fb | 1988 | struct intel_hdmi *intel_hdmi; |
045ac3b5 JB |
1989 | u32 temp, flags = 0; |
1990 | ||
4d1de975 JN |
1991 | /* XXX: DSI transcoder paranoia */ |
1992 | if (WARN_ON(transcoder_is_dsi(cpu_transcoder))) | |
1993 | return; | |
1994 | ||
045ac3b5 JB |
1995 | temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
1996 | if (temp & TRANS_DDI_PHSYNC) | |
1997 | flags |= DRM_MODE_FLAG_PHSYNC; | |
1998 | else | |
1999 | flags |= DRM_MODE_FLAG_NHSYNC; | |
2000 | if (temp & TRANS_DDI_PVSYNC) | |
2001 | flags |= DRM_MODE_FLAG_PVSYNC; | |
2002 | else | |
2003 | flags |= DRM_MODE_FLAG_NVSYNC; | |
2004 | ||
2d112de7 | 2005 | pipe_config->base.adjusted_mode.flags |= flags; |
42571aef VS |
2006 | |
2007 | switch (temp & TRANS_DDI_BPC_MASK) { | |
2008 | case TRANS_DDI_BPC_6: | |
2009 | pipe_config->pipe_bpp = 18; | |
2010 | break; | |
2011 | case TRANS_DDI_BPC_8: | |
2012 | pipe_config->pipe_bpp = 24; | |
2013 | break; | |
2014 | case TRANS_DDI_BPC_10: | |
2015 | pipe_config->pipe_bpp = 30; | |
2016 | break; | |
2017 | case TRANS_DDI_BPC_12: | |
2018 | pipe_config->pipe_bpp = 36; | |
2019 | break; | |
2020 | default: | |
2021 | break; | |
2022 | } | |
eb14cb74 VS |
2023 | |
2024 | switch (temp & TRANS_DDI_MODE_SELECT_MASK) { | |
2025 | case TRANS_DDI_MODE_SELECT_HDMI: | |
6897b4b5 | 2026 | pipe_config->has_hdmi_sink = true; |
bbd440fb DV |
2027 | intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
2028 | ||
cda0aaaf | 2029 | if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config)) |
bbd440fb | 2030 | pipe_config->has_infoframe = true; |
d4d6279a | 2031 | /* fall through */ |
eb14cb74 | 2032 | case TRANS_DDI_MODE_SELECT_DVI: |
d4d6279a ACO |
2033 | pipe_config->lane_count = 4; |
2034 | break; | |
eb14cb74 VS |
2035 | case TRANS_DDI_MODE_SELECT_FDI: |
2036 | break; | |
2037 | case TRANS_DDI_MODE_SELECT_DP_SST: | |
2038 | case TRANS_DDI_MODE_SELECT_DP_MST: | |
90a6b7b0 VS |
2039 | pipe_config->lane_count = |
2040 | ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; | |
eb14cb74 VS |
2041 | intel_dp_get_m_n(intel_crtc, pipe_config); |
2042 | break; | |
2043 | default: | |
2044 | break; | |
2045 | } | |
10214420 | 2046 | |
be754b10 DP |
2047 | if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) { |
2048 | temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); | |
2049 | if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe)) | |
2050 | pipe_config->has_audio = true; | |
2051 | } | |
9ed109a7 | 2052 | |
6aa23e65 JN |
2053 | if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp && |
2054 | pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { | |
10214420 DV |
2055 | /* |
2056 | * This is a big fat ugly hack. | |
2057 | * | |
2058 | * Some machines in UEFI boot mode provide us a VBT that has 18 | |
2059 | * bpp and 1.62 GHz link bandwidth for eDP, which for reasons | |
2060 | * unknown we fail to light up. Yet the same BIOS boots up with | |
2061 | * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as | |
2062 | * max, not what it tells us to use. | |
2063 | * | |
2064 | * Note: This will still be broken if the eDP panel is not lit | |
2065 | * up by the BIOS, and thus we can't get the mode at module | |
2066 | * load. | |
2067 | */ | |
2068 | DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", | |
6aa23e65 JN |
2069 | pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); |
2070 | dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; | |
10214420 | 2071 | } |
11578553 | 2072 | |
22606a18 | 2073 | intel_ddi_clock_get(encoder, pipe_config); |
95a7a2ae ID |
2074 | |
2075 | if (IS_BROXTON(dev_priv)) | |
2076 | pipe_config->lane_lat_optim_mask = | |
2077 | bxt_ddi_phy_get_lane_lat_optim_mask(encoder); | |
045ac3b5 JB |
2078 | } |
2079 | ||
5bfe2ac0 | 2080 | static bool intel_ddi_compute_config(struct intel_encoder *encoder, |
0a478c27 ML |
2081 | struct intel_crtc_state *pipe_config, |
2082 | struct drm_connector_state *conn_state) | |
00c09d70 | 2083 | { |
fac5e23e | 2084 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
5bfe2ac0 | 2085 | int type = encoder->type; |
eccb140b | 2086 | int port = intel_ddi_get_encoder_port(encoder); |
95a7a2ae | 2087 | int ret; |
00c09d70 | 2088 | |
5bfe2ac0 | 2089 | WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n"); |
00c09d70 | 2090 | |
eccb140b DV |
2091 | if (port == PORT_A) |
2092 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
2093 | ||
00c09d70 | 2094 | if (type == INTEL_OUTPUT_HDMI) |
0a478c27 | 2095 | ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state); |
00c09d70 | 2096 | else |
0a478c27 | 2097 | ret = intel_dp_compute_config(encoder, pipe_config, conn_state); |
95a7a2ae ID |
2098 | |
2099 | if (IS_BROXTON(dev_priv) && ret) | |
2100 | pipe_config->lane_lat_optim_mask = | |
2101 | bxt_ddi_phy_calc_lane_lat_optim_mask(encoder, | |
b284eeda | 2102 | pipe_config->lane_count); |
95a7a2ae ID |
2103 | |
2104 | return ret; | |
2105 | ||
00c09d70 PZ |
2106 | } |
2107 | ||
2108 | static const struct drm_encoder_funcs intel_ddi_funcs = { | |
bf93ba67 ID |
2109 | .reset = intel_dp_encoder_reset, |
2110 | .destroy = intel_dp_encoder_destroy, | |
00c09d70 PZ |
2111 | }; |
2112 | ||
4a28ae58 PZ |
2113 | static struct intel_connector * |
2114 | intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port) | |
2115 | { | |
2116 | struct intel_connector *connector; | |
2117 | enum port port = intel_dig_port->port; | |
2118 | ||
9bdbd0b9 | 2119 | connector = intel_connector_alloc(); |
4a28ae58 PZ |
2120 | if (!connector) |
2121 | return NULL; | |
2122 | ||
2123 | intel_dig_port->dp.output_reg = DDI_BUF_CTL(port); | |
2124 | if (!intel_dp_init_connector(intel_dig_port, connector)) { | |
2125 | kfree(connector); | |
2126 | return NULL; | |
2127 | } | |
2128 | ||
2129 | return connector; | |
2130 | } | |
2131 | ||
2132 | static struct intel_connector * | |
2133 | intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port) | |
2134 | { | |
2135 | struct intel_connector *connector; | |
2136 | enum port port = intel_dig_port->port; | |
2137 | ||
9bdbd0b9 | 2138 | connector = intel_connector_alloc(); |
4a28ae58 PZ |
2139 | if (!connector) |
2140 | return NULL; | |
2141 | ||
2142 | intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); | |
2143 | intel_hdmi_init_connector(intel_dig_port, connector); | |
2144 | ||
2145 | return connector; | |
2146 | } | |
2147 | ||
f169660e JB |
2148 | struct intel_shared_dpll * |
2149 | intel_ddi_get_link_dpll(struct intel_dp *intel_dp, int clock) | |
2150 | { | |
2151 | struct intel_connector *connector = intel_dp->attached_connector; | |
2152 | struct intel_encoder *encoder = connector->encoder; | |
2153 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
2154 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
2155 | struct intel_shared_dpll *pll = NULL; | |
2156 | struct intel_shared_dpll_config tmp_pll_config; | |
2157 | enum intel_dpll_id dpll_id; | |
2158 | ||
2159 | if (IS_BROXTON(dev_priv)) { | |
2160 | dpll_id = (enum intel_dpll_id)dig_port->port; | |
2161 | /* | |
2162 | * Select the required PLL. This works for platforms where | |
2163 | * there is no shared DPLL. | |
2164 | */ | |
2165 | pll = &dev_priv->shared_dplls[dpll_id]; | |
2166 | if (WARN_ON(pll->active_mask)) { | |
2167 | ||
2168 | DRM_ERROR("Shared DPLL in use. active_mask:%x\n", | |
2169 | pll->active_mask); | |
2170 | return NULL; | |
2171 | } | |
2172 | tmp_pll_config = pll->config; | |
2173 | if (!bxt_ddi_dp_set_dpll_hw_state(clock, | |
2174 | &pll->config.hw_state)) { | |
2175 | DRM_ERROR("Could not setup DPLL\n"); | |
2176 | pll->config = tmp_pll_config; | |
2177 | return NULL; | |
2178 | } | |
2686ebfd | 2179 | } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { |
f169660e JB |
2180 | pll = skl_find_link_pll(dev_priv, clock); |
2181 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { | |
2182 | pll = hsw_ddi_dp_get_dpll(encoder, clock); | |
2183 | } | |
2184 | return pll; | |
2185 | } | |
2186 | ||
00c09d70 PZ |
2187 | void intel_ddi_init(struct drm_device *dev, enum port port) |
2188 | { | |
fac5e23e | 2189 | struct drm_i915_private *dev_priv = to_i915(dev); |
00c09d70 PZ |
2190 | struct intel_digital_port *intel_dig_port; |
2191 | struct intel_encoder *intel_encoder; | |
2192 | struct drm_encoder *encoder; | |
ff662124 | 2193 | bool init_hdmi, init_dp, init_lspcon = false; |
10e7bec3 VS |
2194 | int max_lanes; |
2195 | ||
2196 | if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) { | |
2197 | switch (port) { | |
2198 | case PORT_A: | |
2199 | max_lanes = 4; | |
2200 | break; | |
2201 | case PORT_E: | |
2202 | max_lanes = 0; | |
2203 | break; | |
2204 | default: | |
2205 | max_lanes = 4; | |
2206 | break; | |
2207 | } | |
2208 | } else { | |
2209 | switch (port) { | |
2210 | case PORT_A: | |
2211 | max_lanes = 2; | |
2212 | break; | |
2213 | case PORT_E: | |
2214 | max_lanes = 2; | |
2215 | break; | |
2216 | default: | |
2217 | max_lanes = 4; | |
2218 | break; | |
2219 | } | |
2220 | } | |
311a2094 PZ |
2221 | |
2222 | init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi || | |
2223 | dev_priv->vbt.ddi_port_info[port].supports_hdmi); | |
2224 | init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp; | |
ff662124 SS |
2225 | |
2226 | if (intel_bios_is_lspcon_present(dev_priv, port)) { | |
2227 | /* | |
2228 | * Lspcon device needs to be driven with DP connector | |
2229 | * with special detection sequence. So make sure DP | |
2230 | * is initialized before lspcon. | |
2231 | */ | |
2232 | init_dp = true; | |
2233 | init_lspcon = true; | |
2234 | init_hdmi = false; | |
2235 | DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port)); | |
2236 | } | |
2237 | ||
311a2094 | 2238 | if (!init_dp && !init_hdmi) { |
500ea70d | 2239 | DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", |
311a2094 | 2240 | port_name(port)); |
500ea70d | 2241 | return; |
311a2094 | 2242 | } |
00c09d70 | 2243 | |
b14c5679 | 2244 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
00c09d70 PZ |
2245 | if (!intel_dig_port) |
2246 | return; | |
2247 | ||
00c09d70 PZ |
2248 | intel_encoder = &intel_dig_port->base; |
2249 | encoder = &intel_encoder->base; | |
2250 | ||
2251 | drm_encoder_init(dev, encoder, &intel_ddi_funcs, | |
580d8ed5 | 2252 | DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port)); |
00c09d70 | 2253 | |
5bfe2ac0 | 2254 | intel_encoder->compute_config = intel_ddi_compute_config; |
00c09d70 | 2255 | intel_encoder->enable = intel_enable_ddi; |
95a7a2ae ID |
2256 | if (IS_BROXTON(dev_priv)) |
2257 | intel_encoder->pre_pll_enable = bxt_ddi_pre_pll_enable; | |
00c09d70 PZ |
2258 | intel_encoder->pre_enable = intel_ddi_pre_enable; |
2259 | intel_encoder->disable = intel_disable_ddi; | |
2260 | intel_encoder->post_disable = intel_ddi_post_disable; | |
2261 | intel_encoder->get_hw_state = intel_ddi_get_hw_state; | |
045ac3b5 | 2262 | intel_encoder->get_config = intel_ddi_get_config; |
bf93ba67 | 2263 | intel_encoder->suspend = intel_dp_encoder_suspend; |
00c09d70 PZ |
2264 | |
2265 | intel_dig_port->port = port; | |
bcf53de4 SM |
2266 | intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) & |
2267 | (DDI_BUF_PORT_REVERSAL | | |
2268 | DDI_A_4_LANES); | |
00c09d70 | 2269 | |
6c566dc9 MR |
2270 | /* |
2271 | * Bspec says that DDI_A_4_LANES is the only supported configuration | |
2272 | * for Broxton. Yet some BIOS fail to set this bit on port A if eDP | |
2273 | * wasn't lit up at boot. Force this bit on in our internal | |
2274 | * configuration so that we use the proper lane count for our | |
2275 | * calculations. | |
2276 | */ | |
e2d214ae | 2277 | if (IS_BROXTON(dev_priv) && port == PORT_A) { |
6c566dc9 MR |
2278 | if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) { |
2279 | DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n"); | |
2280 | intel_dig_port->saved_port_bits |= DDI_A_4_LANES; | |
ed8d60f4 | 2281 | max_lanes = 4; |
6c566dc9 MR |
2282 | } |
2283 | } | |
2284 | ||
ed8d60f4 MR |
2285 | intel_dig_port->max_lanes = max_lanes; |
2286 | ||
00c09d70 | 2287 | intel_encoder->type = INTEL_OUTPUT_UNKNOWN; |
03cdc1d4 | 2288 | intel_encoder->port = port; |
f68d697e | 2289 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
bc079e8b | 2290 | intel_encoder->cloneable = 0; |
00c09d70 | 2291 | |
f68d697e CW |
2292 | if (init_dp) { |
2293 | if (!intel_ddi_init_dp_connector(intel_dig_port)) | |
2294 | goto err; | |
13cf5504 | 2295 | |
f68d697e | 2296 | intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; |
cf1d5883 SJ |
2297 | /* |
2298 | * On BXT A0/A1, sw needs to activate DDIA HPD logic and | |
2299 | * interrupts to check the external panel connection. | |
2300 | */ | |
e2d214ae | 2301 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1) && port == PORT_B) |
cf1d5883 SJ |
2302 | dev_priv->hotplug.irq_port[PORT_A] = intel_dig_port; |
2303 | else | |
2304 | dev_priv->hotplug.irq_port[port] = intel_dig_port; | |
f68d697e | 2305 | } |
21a8e6a4 | 2306 | |
311a2094 PZ |
2307 | /* In theory we don't need the encoder->type check, but leave it just in |
2308 | * case we have some really bad VBTs... */ | |
f68d697e CW |
2309 | if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { |
2310 | if (!intel_ddi_init_hdmi_connector(intel_dig_port)) | |
2311 | goto err; | |
21a8e6a4 | 2312 | } |
f68d697e | 2313 | |
ff662124 SS |
2314 | if (init_lspcon) { |
2315 | if (lspcon_init(intel_dig_port)) | |
2316 | /* TODO: handle hdmi info frame part */ | |
2317 | DRM_DEBUG_KMS("LSPCON init success on port %c\n", | |
2318 | port_name(port)); | |
2319 | else | |
2320 | /* | |
2321 | * LSPCON init faied, but DP init was success, so | |
2322 | * lets try to drive as DP++ port. | |
2323 | */ | |
2324 | DRM_ERROR("LSPCON init failed on port %c\n", | |
2325 | port_name(port)); | |
2326 | } | |
2327 | ||
f68d697e CW |
2328 | return; |
2329 | ||
2330 | err: | |
2331 | drm_encoder_cleanup(encoder); | |
2332 | kfree(intel_dig_port); | |
00c09d70 | 2333 | } |