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eb805623 DV |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | #include <linux/firmware.h> | |
25 | #include "i915_drv.h" | |
26 | #include "i915_reg.h" | |
27 | ||
aa9145c4 AM |
28 | /** |
29 | * DOC: csr support for dmc | |
30 | * | |
31 | * Display Context Save and Restore (CSR) firmware support added from gen9 | |
32 | * onwards to drive newly added DMC (Display microcontroller) in display | |
33 | * engine to save and restore the state of display engine when it enter into | |
34 | * low-power state and comes back to normal. | |
aa9145c4 AM |
35 | */ |
36 | ||
aebfd1d3 | 37 | #define I915_CSR_GLK "i915/glk_dmc_ver1_04.bin" |
b607990c | 38 | MODULE_FIRMWARE(I915_CSR_GLK); |
aebfd1d3 | 39 | #define GLK_CSR_VERSION_REQUIRED CSR_VERSION(1, 4) |
dbb28b5c | 40 | |
fe9a9da6 AS |
41 | #define I915_CSR_CNL "i915/cnl_dmc_ver1_07.bin" |
42 | MODULE_FIRMWARE(I915_CSR_CNL); | |
43 | #define CNL_CSR_VERSION_REQUIRED CSR_VERSION(1, 7) | |
cebfcead | 44 | |
4f0aa1fa | 45 | #define I915_CSR_KBL "i915/kbl_dmc_ver1_04.bin" |
4922d491 | 46 | MODULE_FIRMWARE(I915_CSR_KBL); |
4f0aa1fa | 47 | #define KBL_CSR_VERSION_REQUIRED CSR_VERSION(1, 4) |
4922d491 | 48 | |
39ccc985 | 49 | #define I915_CSR_SKL "i915/skl_dmc_ver1_27.bin" |
4922d491 | 50 | MODULE_FIRMWARE(I915_CSR_SKL); |
39ccc985 | 51 | #define SKL_CSR_VERSION_REQUIRED CSR_VERSION(1, 27) |
4922d491 | 52 | |
536ab3ca | 53 | #define I915_CSR_BXT "i915/bxt_dmc_ver1_07.bin" |
4922d491 RV |
54 | MODULE_FIRMWARE(I915_CSR_BXT); |
55 | #define BXT_CSR_VERSION_REQUIRED CSR_VERSION(1, 7) | |
eb805623 | 56 | |
9c5308ea | 57 | |
eb805623 DV |
58 | #define CSR_MAX_FW_SIZE 0x2FFF |
59 | #define CSR_DEFAULT_FW_OFFSET 0xFFFFFFFF | |
eb805623 DV |
60 | |
61 | struct intel_css_header { | |
62 | /* 0x09 for DMC */ | |
63 | uint32_t module_type; | |
64 | ||
65 | /* Includes the DMC specific header in dwords */ | |
66 | uint32_t header_len; | |
67 | ||
68 | /* always value would be 0x10000 */ | |
69 | uint32_t header_ver; | |
70 | ||
71 | /* Not used */ | |
72 | uint32_t module_id; | |
73 | ||
74 | /* Not used */ | |
75 | uint32_t module_vendor; | |
76 | ||
77 | /* in YYYYMMDD format */ | |
78 | uint32_t date; | |
79 | ||
80 | /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */ | |
81 | uint32_t size; | |
82 | ||
83 | /* Not used */ | |
84 | uint32_t key_size; | |
85 | ||
86 | /* Not used */ | |
87 | uint32_t modulus_size; | |
88 | ||
89 | /* Not used */ | |
90 | uint32_t exponent_size; | |
91 | ||
92 | /* Not used */ | |
93 | uint32_t reserved1[12]; | |
94 | ||
95 | /* Major Minor */ | |
96 | uint32_t version; | |
97 | ||
98 | /* Not used */ | |
99 | uint32_t reserved2[8]; | |
100 | ||
101 | /* Not used */ | |
102 | uint32_t kernel_header_info; | |
103 | } __packed; | |
104 | ||
105 | struct intel_fw_info { | |
106 | uint16_t reserved1; | |
107 | ||
108 | /* Stepping (A, B, C, ..., *). * is a wildcard */ | |
109 | char stepping; | |
110 | ||
111 | /* Sub-stepping (0, 1, ..., *). * is a wildcard */ | |
112 | char substepping; | |
113 | ||
114 | uint32_t offset; | |
115 | uint32_t reserved2; | |
116 | } __packed; | |
117 | ||
118 | struct intel_package_header { | |
119 | /* DMC container header length in dwords */ | |
120 | unsigned char header_len; | |
121 | ||
122 | /* always value would be 0x01 */ | |
123 | unsigned char header_ver; | |
124 | ||
125 | unsigned char reserved[10]; | |
126 | ||
127 | /* Number of valid entries in the FWInfo array below */ | |
128 | uint32_t num_entries; | |
129 | ||
130 | struct intel_fw_info fw_info[20]; | |
131 | } __packed; | |
132 | ||
133 | struct intel_dmc_header { | |
134 | /* always value would be 0x40403E3E */ | |
135 | uint32_t signature; | |
136 | ||
137 | /* DMC binary header length */ | |
138 | unsigned char header_len; | |
139 | ||
140 | /* 0x01 */ | |
141 | unsigned char header_ver; | |
142 | ||
143 | /* Reserved */ | |
144 | uint16_t dmcc_ver; | |
145 | ||
146 | /* Major, Minor */ | |
147 | uint32_t project; | |
148 | ||
149 | /* Firmware program size (excluding header) in dwords */ | |
150 | uint32_t fw_size; | |
151 | ||
152 | /* Major Minor version */ | |
153 | uint32_t fw_version; | |
154 | ||
155 | /* Number of valid MMIO cycles present. */ | |
156 | uint32_t mmio_count; | |
157 | ||
158 | /* MMIO address */ | |
159 | uint32_t mmioaddr[8]; | |
160 | ||
161 | /* MMIO data */ | |
162 | uint32_t mmiodata[8]; | |
163 | ||
164 | /* FW filename */ | |
165 | unsigned char dfile[32]; | |
166 | ||
167 | uint32_t reserved1[2]; | |
168 | } __packed; | |
169 | ||
170 | struct stepping_info { | |
171 | char stepping; | |
172 | char substepping; | |
173 | }; | |
174 | ||
175 | static const struct stepping_info skl_stepping_info[] = { | |
84cb00ec JN |
176 | {'A', '0'}, {'B', '0'}, {'C', '0'}, |
177 | {'D', '0'}, {'E', '0'}, {'F', '0'}, | |
a41c8882 MM |
178 | {'G', '0'}, {'H', '0'}, {'I', '0'}, |
179 | {'J', '0'}, {'K', '0'} | |
eb805623 DV |
180 | }; |
181 | ||
b9cd5bfd | 182 | static const struct stepping_info bxt_stepping_info[] = { |
cff765fb AM |
183 | {'A', '0'}, {'A', '1'}, {'A', '2'}, |
184 | {'B', '0'}, {'B', '1'}, {'B', '2'} | |
185 | }; | |
186 | ||
1bb4308e CW |
187 | static const struct stepping_info no_stepping_info = { '*', '*' }; |
188 | ||
189 | static const struct stepping_info * | |
190 | intel_get_stepping_info(struct drm_i915_private *dev_priv) | |
eb805623 | 191 | { |
b1a14c6e JN |
192 | const struct stepping_info *si; |
193 | unsigned int size; | |
194 | ||
1c00164d | 195 | if (IS_SKYLAKE(dev_priv)) { |
b1a14c6e JN |
196 | size = ARRAY_SIZE(skl_stepping_info); |
197 | si = skl_stepping_info; | |
1bb4308e | 198 | } else if (IS_BROXTON(dev_priv)) { |
b1a14c6e JN |
199 | size = ARRAY_SIZE(bxt_stepping_info); |
200 | si = bxt_stepping_info; | |
201 | } else { | |
1bb4308e | 202 | size = 0; |
2f59f1b3 | 203 | si = NULL; |
b1a14c6e | 204 | } |
eb805623 | 205 | |
1bb4308e CW |
206 | if (INTEL_REVID(dev_priv) < size) |
207 | return si + INTEL_REVID(dev_priv); | |
b1a14c6e | 208 | |
1bb4308e | 209 | return &no_stepping_info; |
eb805623 DV |
210 | } |
211 | ||
2abc525b ID |
212 | static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv) |
213 | { | |
214 | uint32_t val, mask; | |
215 | ||
216 | mask = DC_STATE_DEBUG_MASK_MEMORY_UP; | |
217 | ||
b7208a3f | 218 | if (IS_GEN9_LP(dev_priv)) |
2abc525b ID |
219 | mask |= DC_STATE_DEBUG_MASK_CORES; |
220 | ||
221 | /* The below bit doesn't need to be cleared ever afterwards */ | |
222 | val = I915_READ(DC_STATE_DEBUG); | |
223 | if ((val & mask) != mask) { | |
224 | val |= mask; | |
225 | I915_WRITE(DC_STATE_DEBUG, val); | |
226 | POSTING_READ(DC_STATE_DEBUG); | |
227 | } | |
228 | } | |
229 | ||
aa9145c4 AM |
230 | /** |
231 | * intel_csr_load_program() - write the firmware from memory to register. | |
f4448375 | 232 | * @dev_priv: i915 drm device. |
aa9145c4 AM |
233 | * |
234 | * CSR firmware is read from a .bin file and kept in internal memory one time. | |
235 | * Everytime display comes back from low power state this function is called to | |
236 | * copy the firmware from internal memory to registers. | |
237 | */ | |
2abc525b | 238 | void intel_csr_load_program(struct drm_i915_private *dev_priv) |
eb805623 | 239 | { |
a7f749f9 | 240 | u32 *payload = dev_priv->csr.dmc_payload; |
eb805623 DV |
241 | uint32_t i, fw_size; |
242 | ||
1a7399aa | 243 | if (!HAS_CSR(dev_priv)) { |
eb805623 | 244 | DRM_ERROR("No CSR support available for this platform\n"); |
2abc525b | 245 | return; |
eb805623 DV |
246 | } |
247 | ||
fc131bf2 PJ |
248 | if (!dev_priv->csr.dmc_payload) { |
249 | DRM_ERROR("Tried to program CSR with empty payload\n"); | |
2abc525b | 250 | return; |
fc131bf2 | 251 | } |
4b7ab5fc | 252 | |
eb805623 | 253 | fw_size = dev_priv->csr.dmc_fw_size; |
dff457d7 DW |
254 | assert_rpm_wakelock_held(dev_priv); |
255 | ||
256 | preempt_disable(); | |
257 | ||
eb805623 | 258 | for (i = 0; i < fw_size; i++) |
dff457d7 DW |
259 | I915_WRITE_FW(CSR_PROGRAM(i), payload[i]); |
260 | ||
261 | preempt_enable(); | |
eb805623 DV |
262 | |
263 | for (i = 0; i < dev_priv->csr.mmio_count; i++) { | |
264 | I915_WRITE(dev_priv->csr.mmioaddr[i], | |
f98f70d9 | 265 | dev_priv->csr.mmiodata[i]); |
eb805623 | 266 | } |
832dba88 PJ |
267 | |
268 | dev_priv->csr.dc_state = 0; | |
1e657ad7 | 269 | |
2abc525b | 270 | gen9_set_dc_state_debugmask(dev_priv); |
eb805623 DV |
271 | } |
272 | ||
6a6582bf DV |
273 | static uint32_t *parse_csr_fw(struct drm_i915_private *dev_priv, |
274 | const struct firmware *fw) | |
eb805623 | 275 | { |
eb805623 DV |
276 | struct intel_css_header *css_header; |
277 | struct intel_package_header *package_header; | |
278 | struct intel_dmc_header *dmc_header; | |
279 | struct intel_csr *csr = &dev_priv->csr; | |
1bb4308e | 280 | const struct stepping_info *si = intel_get_stepping_info(dev_priv); |
eb805623 DV |
281 | uint32_t dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount = 0, nbytes; |
282 | uint32_t i; | |
a7f749f9 | 283 | uint32_t *dmc_payload; |
4aa7fb9c | 284 | uint32_t required_version; |
eb805623 | 285 | |
9c5308ea | 286 | if (!fw) |
6a6582bf | 287 | return NULL; |
eb805623 | 288 | |
eb805623 DV |
289 | /* Extract CSS Header information*/ |
290 | css_header = (struct intel_css_header *)fw->data; | |
291 | if (sizeof(struct intel_css_header) != | |
f98f70d9 | 292 | (css_header->header_len * 4)) { |
f1e86cec MW |
293 | DRM_ERROR("DMC firmware has wrong CSS header length " |
294 | "(%u bytes)\n", | |
f98f70d9 | 295 | (css_header->header_len * 4)); |
6a6582bf | 296 | return NULL; |
eb805623 | 297 | } |
b6e7d894 DL |
298 | |
299 | csr->version = css_header->version; | |
300 | ||
cebfcead AS |
301 | if (IS_CANNONLAKE(dev_priv)) { |
302 | required_version = CNL_CSR_VERSION_REQUIRED; | |
303 | } else if (IS_GEMINILAKE(dev_priv)) { | |
dbb28b5c | 304 | required_version = GLK_CSR_VERSION_REQUIRED; |
84cd843e | 305 | } else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) { |
4aa7fb9c | 306 | required_version = KBL_CSR_VERSION_REQUIRED; |
4922d491 | 307 | } else if (IS_SKYLAKE(dev_priv)) { |
4aa7fb9c | 308 | required_version = SKL_CSR_VERSION_REQUIRED; |
e7968531 | 309 | } else if (IS_BROXTON(dev_priv)) { |
4aa7fb9c | 310 | required_version = BXT_CSR_VERSION_REQUIRED; |
e7968531 ID |
311 | } else { |
312 | MISSING_CASE(INTEL_REVID(dev_priv)); | |
4aa7fb9c | 313 | required_version = 0; |
e7968531 ID |
314 | } |
315 | ||
4aa7fb9c PJ |
316 | if (csr->version != required_version) { |
317 | DRM_INFO("Refusing to load DMC firmware v%u.%u," | |
f1e86cec | 318 | " please use v%u.%u\n", |
9c5308ea MK |
319 | CSR_VERSION_MAJOR(csr->version), |
320 | CSR_VERSION_MINOR(csr->version), | |
4aa7fb9c PJ |
321 | CSR_VERSION_MAJOR(required_version), |
322 | CSR_VERSION_MINOR(required_version)); | |
6a6582bf | 323 | return NULL; |
9c5308ea MK |
324 | } |
325 | ||
eb805623 DV |
326 | readcount += sizeof(struct intel_css_header); |
327 | ||
328 | /* Extract Package Header information*/ | |
329 | package_header = (struct intel_package_header *) | |
f98f70d9 | 330 | &fw->data[readcount]; |
eb805623 | 331 | if (sizeof(struct intel_package_header) != |
f98f70d9 | 332 | (package_header->header_len * 4)) { |
f1e86cec MW |
333 | DRM_ERROR("DMC firmware has wrong package header length " |
334 | "(%u bytes)\n", | |
f98f70d9 | 335 | (package_header->header_len * 4)); |
6a6582bf | 336 | return NULL; |
eb805623 DV |
337 | } |
338 | readcount += sizeof(struct intel_package_header); | |
339 | ||
340 | /* Search for dmc_offset to find firware binary. */ | |
341 | for (i = 0; i < package_header->num_entries; i++) { | |
342 | if (package_header->fw_info[i].substepping == '*' && | |
1bb4308e | 343 | si->stepping == package_header->fw_info[i].stepping) { |
eb805623 DV |
344 | dmc_offset = package_header->fw_info[i].offset; |
345 | break; | |
1bb4308e CW |
346 | } else if (si->stepping == package_header->fw_info[i].stepping && |
347 | si->substepping == package_header->fw_info[i].substepping) { | |
eb805623 DV |
348 | dmc_offset = package_header->fw_info[i].offset; |
349 | break; | |
350 | } else if (package_header->fw_info[i].stepping == '*' && | |
f98f70d9 | 351 | package_header->fw_info[i].substepping == '*') |
eb805623 DV |
352 | dmc_offset = package_header->fw_info[i].offset; |
353 | } | |
354 | if (dmc_offset == CSR_DEFAULT_FW_OFFSET) { | |
f1e86cec | 355 | DRM_ERROR("DMC firmware not supported for %c stepping\n", |
1bb4308e | 356 | si->stepping); |
6a6582bf | 357 | return NULL; |
eb805623 DV |
358 | } |
359 | readcount += dmc_offset; | |
360 | ||
361 | /* Extract dmc_header information. */ | |
362 | dmc_header = (struct intel_dmc_header *)&fw->data[readcount]; | |
363 | if (sizeof(struct intel_dmc_header) != (dmc_header->header_len)) { | |
f1e86cec MW |
364 | DRM_ERROR("DMC firmware has wrong dmc header length " |
365 | "(%u bytes)\n", | |
f98f70d9 | 366 | (dmc_header->header_len)); |
6a6582bf | 367 | return NULL; |
eb805623 DV |
368 | } |
369 | readcount += sizeof(struct intel_dmc_header); | |
370 | ||
371 | /* Cache the dmc header info. */ | |
372 | if (dmc_header->mmio_count > ARRAY_SIZE(csr->mmioaddr)) { | |
f1e86cec | 373 | DRM_ERROR("DMC firmware has wrong mmio count %u\n", |
f98f70d9 | 374 | dmc_header->mmio_count); |
6a6582bf | 375 | return NULL; |
eb805623 DV |
376 | } |
377 | csr->mmio_count = dmc_header->mmio_count; | |
378 | for (i = 0; i < dmc_header->mmio_count; i++) { | |
982b0b2d | 379 | if (dmc_header->mmioaddr[i] < CSR_MMIO_START_RANGE || |
f98f70d9 | 380 | dmc_header->mmioaddr[i] > CSR_MMIO_END_RANGE) { |
f1e86cec | 381 | DRM_ERROR("DMC firmware has wrong mmio address 0x%x\n", |
f98f70d9 | 382 | dmc_header->mmioaddr[i]); |
6a6582bf | 383 | return NULL; |
eb805623 | 384 | } |
f0f59a00 | 385 | csr->mmioaddr[i] = _MMIO(dmc_header->mmioaddr[i]); |
eb805623 DV |
386 | csr->mmiodata[i] = dmc_header->mmiodata[i]; |
387 | } | |
388 | ||
389 | /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */ | |
390 | nbytes = dmc_header->fw_size * 4; | |
391 | if (nbytes > CSR_MAX_FW_SIZE) { | |
f1e86cec | 392 | DRM_ERROR("DMC firmware too big (%u bytes)\n", nbytes); |
6a6582bf | 393 | return NULL; |
eb805623 DV |
394 | } |
395 | csr->dmc_fw_size = dmc_header->fw_size; | |
396 | ||
6a6582bf DV |
397 | dmc_payload = kmalloc(nbytes, GFP_KERNEL); |
398 | if (!dmc_payload) { | |
eb805623 | 399 | DRM_ERROR("Memory allocation failed for dmc payload\n"); |
6a6582bf | 400 | return NULL; |
eb805623 DV |
401 | } |
402 | ||
1bb4308e | 403 | return memcpy(dmc_payload, &fw->data[readcount], nbytes); |
6a6582bf DV |
404 | } |
405 | ||
8144ac59 | 406 | static void csr_load_work_fn(struct work_struct *work) |
6a6582bf | 407 | { |
8144ac59 DV |
408 | struct drm_i915_private *dev_priv; |
409 | struct intel_csr *csr; | |
3aaa8aba | 410 | const struct firmware *fw = NULL; |
8144ac59 DV |
411 | |
412 | dev_priv = container_of(work, typeof(*dev_priv), csr.work); | |
413 | csr = &dev_priv->csr; | |
6a6582bf | 414 | |
ec78828e | 415 | request_firmware(&fw, dev_priv->csr.fw_path, &dev_priv->drm.pdev->dev); |
2abc525b ID |
416 | if (fw) |
417 | dev_priv->csr.dmc_payload = parse_csr_fw(dev_priv, fw); | |
6a6582bf | 418 | |
6a6582bf | 419 | if (dev_priv->csr.dmc_payload) { |
2abc525b ID |
420 | intel_csr_load_program(dev_priv); |
421 | ||
01a6908c | 422 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); |
9c5308ea | 423 | |
b2251c08 | 424 | DRM_INFO("Finished loading DMC firmware %s (v%u.%u)\n", |
9c5308ea MK |
425 | dev_priv->csr.fw_path, |
426 | CSR_VERSION_MAJOR(csr->version), | |
427 | CSR_VERSION_MINOR(csr->version)); | |
428 | } else { | |
91c8a326 | 429 | dev_notice(dev_priv->drm.dev, |
f1e86cec MW |
430 | "Failed to load DMC firmware %s." |
431 | " Disabling runtime power management.\n", | |
432 | csr->fw_path); | |
433 | dev_notice(dev_priv->drm.dev, "DMC firmware homepage: %s", | |
434 | INTEL_UC_FIRMWARE_URL); | |
9c5308ea MK |
435 | } |
436 | ||
eb805623 DV |
437 | release_firmware(fw); |
438 | } | |
439 | ||
aa9145c4 AM |
440 | /** |
441 | * intel_csr_ucode_init() - initialize the firmware loading. | |
f4448375 | 442 | * @dev_priv: i915 drm device. |
aa9145c4 AM |
443 | * |
444 | * This function is called at the time of loading the display driver to read | |
445 | * firmware from a .bin file and copied into a internal memory. | |
446 | */ | |
f4448375 | 447 | void intel_csr_ucode_init(struct drm_i915_private *dev_priv) |
eb805623 | 448 | { |
eb805623 | 449 | struct intel_csr *csr = &dev_priv->csr; |
8144ac59 DV |
450 | |
451 | INIT_WORK(&dev_priv->csr.work, csr_load_work_fn); | |
eb805623 | 452 | |
f4448375 | 453 | if (!HAS_CSR(dev_priv)) |
eb805623 DV |
454 | return; |
455 | ||
cebfcead AS |
456 | if (IS_CANNONLAKE(dev_priv)) |
457 | csr->fw_path = I915_CSR_CNL; | |
458 | else if (IS_GEMINILAKE(dev_priv)) | |
dbb28b5c | 459 | csr->fw_path = I915_CSR_GLK; |
84cd843e | 460 | else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) |
4922d491 RV |
461 | csr->fw_path = I915_CSR_KBL; |
462 | else if (IS_SKYLAKE(dev_priv)) | |
eb805623 | 463 | csr->fw_path = I915_CSR_SKL; |
18c237c0 AM |
464 | else if (IS_BROXTON(dev_priv)) |
465 | csr->fw_path = I915_CSR_BXT; | |
eb805623 DV |
466 | else { |
467 | DRM_ERROR("Unexpected: no known CSR firmware for platform\n"); | |
468 | return; | |
469 | } | |
470 | ||
abd41dc9 DL |
471 | DRM_DEBUG_KMS("Loading %s\n", csr->fw_path); |
472 | ||
dc174300 SS |
473 | /* |
474 | * Obtain a runtime pm reference, until CSR is loaded, | |
475 | * to avoid entering runtime-suspend. | |
476 | */ | |
01a6908c | 477 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); |
dc174300 | 478 | |
8144ac59 | 479 | schedule_work(&dev_priv->csr.work); |
eb805623 DV |
480 | } |
481 | ||
f74ed08d ID |
482 | /** |
483 | * intel_csr_ucode_suspend() - prepare CSR firmware before system suspend | |
484 | * @dev_priv: i915 drm device | |
485 | * | |
486 | * Prepare the DMC firmware before entering system suspend. This includes | |
487 | * flushing pending work items and releasing any resources acquired during | |
488 | * init. | |
489 | */ | |
490 | void intel_csr_ucode_suspend(struct drm_i915_private *dev_priv) | |
491 | { | |
492 | if (!HAS_CSR(dev_priv)) | |
493 | return; | |
494 | ||
495 | flush_work(&dev_priv->csr.work); | |
496 | ||
497 | /* Drop the reference held in case DMC isn't loaded. */ | |
498 | if (!dev_priv->csr.dmc_payload) | |
499 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); | |
500 | } | |
501 | ||
502 | /** | |
503 | * intel_csr_ucode_resume() - init CSR firmware during system resume | |
504 | * @dev_priv: i915 drm device | |
505 | * | |
506 | * Reinitialize the DMC firmware during system resume, reacquiring any | |
507 | * resources released in intel_csr_ucode_suspend(). | |
508 | */ | |
509 | void intel_csr_ucode_resume(struct drm_i915_private *dev_priv) | |
510 | { | |
511 | if (!HAS_CSR(dev_priv)) | |
512 | return; | |
513 | ||
514 | /* | |
515 | * Reacquire the reference to keep RPM disabled in case DMC isn't | |
516 | * loaded. | |
517 | */ | |
518 | if (!dev_priv->csr.dmc_payload) | |
519 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); | |
520 | } | |
521 | ||
aa9145c4 AM |
522 | /** |
523 | * intel_csr_ucode_fini() - unload the CSR firmware. | |
f4448375 | 524 | * @dev_priv: i915 drm device. |
aa9145c4 | 525 | * |
f74ed08d | 526 | * Firmmware unloading includes freeing the internal memory and reset the |
aa9145c4 AM |
527 | * firmware loading status. |
528 | */ | |
f4448375 | 529 | void intel_csr_ucode_fini(struct drm_i915_private *dev_priv) |
eb805623 | 530 | { |
f4448375 | 531 | if (!HAS_CSR(dev_priv)) |
eb805623 DV |
532 | return; |
533 | ||
f74ed08d | 534 | intel_csr_ucode_suspend(dev_priv); |
15e72c1f | 535 | |
eb805623 DV |
536 | kfree(dev_priv->csr.dmc_payload); |
537 | } |